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166 Commits

Author SHA1 Message Date
Xuepeng Guo d6aab7a11b x86: Support Intel AVX512 BF16 
Add assembler and disassembler support Intel AVX512 BF16:

https://software.intel.com/en-us/download/intel-architecture-instruction-set-extensions-programming-reference

gas/

2019-04-05  Xuepeng Guo  <xuepeng.guo@intel.com>

	* config/tc-i386.c (cpu_arch): Add .avx512_bf16.
	(cpu_noarch): Add noavx512_bf16.
	* doc/c-i386.texi: Document avx512_bf16.
	* testsuite/gas/i386/avx512_bf16.d: New file.
	* testsuite/gas/i386/avx512_bf16.s: Likewise.
	* testsuite/gas/i386/avx512_bf16_vl-inval.l: Likewise.
	* testsuite/gas/i386/avx512_bf16_vl-inval.s: Likewise.
	* testsuite/gas/i386/avx512_bf16_vl.d: Likewise.
	* testsuite/gas/i386/avx512_bf16_vl.s: Likewise.
	* testsuite/gas/i386/x86-64-avx512_bf16.d: Likewise.
	* testsuite/gas/i386/x86-64-avx512_bf16.s: Likewise.
	* testsuite/gas/i386/x86-64-avx512_bf16_vl-inval.l: Likesie.
	* testsuite/gas/i386/x86-64-avx512_bf16_vl-inval.s: Likewise.
	* testsuite/gas/i386/x86-64-avx512_bf16_vl.d: Likewise.
	* testsuite/gas/i386/x86-64-avx512_bf16_vl.s: Likewise.
	* testsuite/gas/i386/i386.exp: Add BF16 related tests.

opcodes/

2019-04-05  Xuepeng Guo  <xuepeng.guo@intel.com>

	* i386-dis-evex.h (evex_table): Updated to support BF16
	instructions.
	* i386-dis.c (enum): Add EVEX_W_0F3852_P_1, EVEX_W_0F3872_P_1
	and EVEX_W_0F3872_P_3.
	* i386-gen.c (cpu_flag_init): Add CPU_AVX512_BF16_FLAGS.
	(cpu_flags): Add bitfield for CpuAVX512_BF16.
	* i386-opc.h (enum): Add CpuAVX512_BF16.
	(i386_cpu_flags): Add bitfield for cpuavx512_bf16.
	* i386-opc.tbl: Add AVX512 BF16 instructions.
	* i386-init.h: Regenerated.
	* i386-tbl.h: Likewise.
 2019-04-05 11:03:13 -07:00
Alan Modra 827041555a Update year range in copyright notice of binutils files 2019-01-01 22:06:53 +10:30
Jan Beulich 673fe0f0a7 x86: fold Size{16,32,64} template attributes 
Only one of them can be set at a time, which means they can be expressed
by a single 2-bit field instead of three 1-bit ones.
 2018-10-10 08:41:52 +02:00
H.J. Lu 6865c0435a x86: Support VEX/EVEX WIG encoding 
Add VEXWIG, defined as 3, to indicate that the VEX.W/EVEX.W bit is
ignored by such VEX/EVEX instructions, aka WIG instructions.  Set
VexW=3 on VEX/EVEX WIG instructions.  Update assembler to check
VEXWIG when setting the VEX.W bit.

gas/

	PR gas/23642
	* config/tc-i386.c (build_vex_prefix): Check VEXWIG when setting
	the VEX.W bit.
	(build_evex_prefix): Check VEXWIG when setting the EVEX.W bit.

opcodes/

	PR gas/23642
	* i386-opc.h (VEXWIG): New.
	* i386-opc.tbl: Set VexW=3 on VEX/EVEX WIG instructions.
	* i386-tbl.h: Regenerated.
 2018-09-14 12:20:10 -07:00
Jan Beulich dbbc8b7e62 x86: use D attribute also for SIMD templates 
Various moves come in load and store forms, and just like on the GPR
and FPU sides there would better be only one pattern. In some cases this
is not feasible because the opcodes are too different, but quite a few
cases follow a similar standard scheme. Introduce Opcode_SIMD_FloatD and
Opcode_SIMD_IntD, generalize handling in operand_size_match() (reverse
operand handling there simply needs to match "straight" operand one),
and fix a long standing, but so far only latent bug with when to zap
found_reverse_match.

Also once again drop IgnoreSize where pointlessly applied to templates
touched anyway as well as *word when redundant with Reg*.
 2018-09-13 11:07:07 +02:00
H.J. Lu d871f3f483 x86: Add CpuCMOV and CpuFXSR 
There are separate CPUID feature bits for fxsave/fxrstor and cmovCC
instructions.  This patch adds CpuCMOV and CpuFXSR to replace Cpu686
on corresponding instructions.

gas/

	* config/tc-i386.c (cpu_arch): Add .cmov and .fxsr.
	(cpu_noarch): Add nocmov and nofxsr.
	* doc/c-i386.texi: Document cmov and fxsr.

opcodes/

	* i386-gen.c (cpu_flag_init): Add CpuCMOV and CpuFXSR to
	CPU_I686_FLAGS.  Add CPU_CMOV_FLAGS, CPU_FXSR_FLAGS,
	CPU_ANY_CMOV_FLAGS and CPU_ANY_FXSR_FLAGS.
	(cpu_flags): Add CpuCMOV and CpuFXSR.
	* i386-opc.tbl: Replace Cpu686 with CpuFXSR on fxsave, fxsave64,
	fxrstor and fxrstor64.  Replace Cpu686 with CpuCMOV on cmovCC.
	* i386-init.h: Regenerated.
	* i386-tbl.h: Likewise.
 2018-08-11 14:37:32 -07:00
Jan Beulich e968fc9b63 x86: fold RegEip/RegRip and RegEiz/RegRiz 
This allows to simplify the code in a number of places.
 2018-08-06 08:34:36 +02:00
Jan Beulich c48dadc9a8 x86: drop "mem" operand type attribute 
No template specifies this bit, so there's no point recording it in the
templates. Use a flags[] bit instead.
 2018-08-03 09:30:02 +02:00
Jan Beulich ae2387feae x86: fold various AVX512 templates with so far differing Masking attributes 
There's no insn allowing ZEROING_MASKING alone. Re-purpose its value for
handling the not uncommon case of insns allowing either form of masking
with register operands, but only merging masking with a memory operand.
 2018-07-31 10:57:09 +02:00
Jan Beulich e951d5ca3d x86: drop CpuVREX 
It is fully redundant with CpuAVX512F.
 2018-07-31 10:52:37 +02:00
H.J. Lu 4a1b91eabb x86: Expand Broadcast to 3 bits 
Expand Broadcast to 3 bits so that the number of bytes to broadcast
can be computed as 1 << (Broadcast - 1).  Use it to simplify x86
assembler.

gas/

	* config/tc-i386.c (Broadcast_Operation): Add bytes.
	(build_evex_prefix): Use i.broadcast->bytes.
	(match_broadcast_size): New function.
	(check_VecOperands): Use the broadcast field to compute the
	number of bytes to broadcast directly.  Set i.broadcast->bytes.
	Use match_broadcast_size.

opcodes/

	* i386-gen.c (adjust_broadcast_modifier): New function.
	(process_i386_opcode_modifier): Add an argument for operands.
	Adjust the Broadcast value based on operands.
	(output_i386_opcode): Pass operand_types to
	process_i386_opcode_modifier.
	(process_i386_opcodes): Pass NULL as operands to
	process_i386_opcode_modifier.
	* i386-opc.h (BYTE_BROADCAST): New.
	(WORD_BROADCAST): Likewise.
	(DWORD_BROADCAST): Likewise.
	(QWORD_BROADCAST): Likewise.
	(i386_opcode_modifier): Expand broadcast to 3 bits.
	* i386-tbl.h: Regenerated.
 2018-07-25 15:28:24 -07:00
Jan Beulich 7091c61201 x86: fold various AVX512VL templates into their AVX512F counterparts 2018-07-19 08:29:35 +02:00
H.J. Lu 11a322db5c x86: Split vcvtps2{,u}qq and vcvttps2{,u}qq 
After

commit 1b54b8d7e4
Author: Jan Beulich <jbeulich@novell.com>
Date:   Mon Dec 18 09:36:14 2017 +0100

    x86: fold RegXMM/RegYMM/RegZMM into RegSIMD

    ... qualified by their respective sizes, allowing to drop FirstXmm0 at
    the same time.

folded RegXMM, RegYMM and RegZMM into RegSIMD, it's no longer impossible
to distinguish if Xmmword can represent a memory reference when operand
specification contains SIMD register. For example, template operands
specification like these

RegXMM|...|Xmmword|...

and

RegXMM|...

The Xmmword bitfield is always set by RegXMM which is represented by
"RegSIMD|Xmmword".  This patch splits each of vcvtps2qq, vcvtps2uqq,
vcvttps2qq and vcvttps2uqq into 2 templates: one template only has
RegXMM source operand and the other only has mempry source operand.

gas/

	PR gas/23418
	* testsuite/gas/i386/xmmword.s: Add tests for vcvtps2qq,
	vcvtps2uqq, vcvttps2qq and vcvttps2uqq.
	* testsuite/gas/i386/xmmword.l: Updated.

opcodes/

	PR gas/23418
	* i386-opc.h (Byte): Update comments.
	(Word): Likewise.
	(Dword): Likewise.
	(Fword): Likewise.
	(Qword): Likewise.
	(Tbyte): Likewise.
	(Xmmword): Likewise.
	(Ymmword): Likewise.
	(Zmmword): Likewise.
	* i386-opc.tbl: Split vcvtps2qq, vcvtps2uqq, vcvttps2qq and
	vcvttps2uqq.
	* i386-tbl.h: Regenerated.
 2018-07-18 05:33:50 -07:00
Jan Beulich f0a85b0706 x86: replace off-by-one OTMax 
With its name it should equal to the largest prior enumerator, which is
not very helpful as that will change every once in a while. Rename it to
OTNum instead to make name and value match, and correct use sites to no
longer use one too large a value.
 2018-07-11 10:24:44 +02:00
H.J. Lu c0a30a9f0a Enable Intel MOVDIRI, MOVDIR64B instructions 
gas/

	* config/tc-i386.c (cpu_arch): Add .movdir, .movdir64b.
	(cpu_noarch): Likewise.
	(process_suffix): Add check for register size.
	* doc/c-i386.texi: Document movdiri, movdir64b.
	* testsuite/gas/i386/i386.exp: Run MOVDIR{I,64B} tests.
	* testsuite/gas/i386/movdir-intel.d: New file.
	* testsuite/gas/i386/movdir.d: Likewise.
	* testsuite/gas/i386/movdir.s: Likewise.
	* testsuite/gas/i386/movdir64b-reg.s: Likewise.
	* testsuite/gas/i386/movdir64b-reg.l: Likewise.
	* testsuite/gas/i386/x86-64-movdir-intel.d: Likewise.
	* testsuite/gas/i386/x86-64-movdir.d: Likewise.
	* testsuite/gas/i386/x86-64-movdir.s: Likewise.
	* testsuite/gas/i386/x86-64-movdir64b-reg.s: Likewise.
	* testsuite/gas/i386/x86-64-movdir64b-reg.l: Likewise.

opcodes/

	* i386-dis.c (Gva): New.
	(enum): Add PREFIX_0F38F8, PREFIX_0F38F9,
	MOD_0F38F8_PREFIX_2, MOD_0F38F9_PREFIX_0.
	(prefix_table): New instructions (see prefix above).
	(mod_table): New instructions (see prefix above).
	(OP_G): Handle va_mode.
	* i386-gen.c (cpu_flag_init): Add CPU_MOVDIRI_FLAGS,
	CPU_MOVDIR64B_FLAGS.
	(cpu_flags): Add CpuMOVDIRI and CpuMOVDIR64B.
	* i386-opc.h (enum): Add CpuMOVDIRI, CpuMOVDIR64B.
	(i386_cpu_flags): Add cpumovdiri and cpumovdir64b.
	* i386-opc.tbl: Add movidir{i,64b}.
	* i386-init.h: Regenerated.
	* i386-tbl.h: Likewise.
 2018-05-07 16:57:48 -07:00
H.J. Lu 75c0a43899 x86: Replace AddrPrefixOp0 with AddrPrefixOpReg 
This patch replaces AddrPrefixOp0 with AddrPrefixOpReg to indicate that
the size of register operand is controlled by the address size prefix.
This will be used by Intel MOVDIRI and MOVDIR64B instructions later.

gas/

	* config/tc-i386.c (process_suffix): Check addrprefixopreg
	instead of addrprefixop0.

opcodes/

	* i386-gen.c (opcode_modifiers): Replace AddrPrefixOp0 with
	AddrPrefixOpReg.
	* i386-opc.h (AddrPrefixOp0): Renamed to ...
	(AddrPrefixOpReg): This.
	(i386_opcode_modifier): Rename addrprefixop0 to addrprefixopreg.
	* i386-opc.tbl: Replace AddrPrefixOp0 with AddrPrefixOpReg.
 2018-05-07 09:57:06 -07:00
Igor Tsimbalist aa17843739 Revert "Enable Intel MOVDIRI, MOVDIR64B instructions." 
This reverts commit a914a7c958.
 2018-04-27 14:34:13 +02:00
Igor Tsimbalist a914a7c958 Enable Intel MOVDIRI, MOVDIR64B instructions. 
gas/
	* config/tc-i386.c (cpu_arch): Add .movdir, .movdir64b.
	(cpu_noarch): Likewise.
	(process_suffix): Add check for register size.
	* doc/c-i386.texi: Document movdiri, movdir64b.
	* testsuite/gas/i386/i386.exp: Run MOVDIR{I,64B} tests.
	* testsuite/gas/i386/movdir-intel.d: New test.
	* testsuite/gas/i386/movdir.d: Likewise.
	* testsuite/gas/i386/movdir.s: Likewise.
	* testsuite/gas/i386/movdir64b-reg.s: Likewise.
	* testsuite/gas/i386/movdir64b-reg.l: Likewise.
	* testsuite/gas/i386/x86-64-movdir-intel.d: Likewise.
	* testsuite/gas/i386/x86-64-movdir.d: Likewise.
	* testsuite/gas/i386/x86-64-movdir.s: Likewise.
	* testsuite/gas/i386/x86-64-movdir64b-reg.s: Likewise.
	* testsuite/gas/i386/x86-64-movdir64b-reg.l: Likewise.

opcodes/
	* i386-dis.c (enum): Add PREFIX_0F38F8, PREFIX_0F38F9.
	(prefix_table): New instructions (see prefix above).
	Add Gva macro and handling in OP_G.
	* i386-gen.c (cpu_flag_init): Add CPU_MOVDIRI_FLAGS,
	CPU_MOVDIR64B_FLAGS.
	(cpu_flags): Likewise.
	(opcode_modifiers): Add AddrPrefixOpReg.
	(i386_opcode_modifier): Likewise.
	* i386-opc.h (enum): Add CpuMOVDIRI, CpuMOVDIR64B.
	(i386_cpu_flags): Likewise.
	* i386-opc.tbl: Add movidir{i,64b}.
	* i386-init.h: Regenerate.
	* i386-tbl.h: Likewise.
 2018-04-26 23:34:04 +02:00
Jan Beulich 6e041cf4b0 x86: drop CpuRegMMX, CpuReg[XYZ]MM, and CpuRegMask 
It's not clear to me why they had been introduced - the respective
comments in opcodes/i386-gen.c are certainly wrong: ymm<N> registers
are very well supported (and necessary) with just AVX512F.
 2018-04-26 08:48:01 +02:00
Jan Beulich 2f1bada2dc x86: drop VexImmExt 
It's only used in assertions, and hence not really needed for correct
code generation.
 2018-04-26 08:30:06 +02:00
Igor Tsimbalist c48935d75f Enable Intel CLDEMOTE instruction. 
gas/
	* config/tc-i386.c (cpu_arch): Add .cldemote.
	* doc/c-i386.texi: Document cldemote/.cldemote.
	* testsuite/gas/i386/cldemote-intel.d: New.
	* testsuite/gas/i386/cldemote.d: Likewise.
	* testsuite/gas/i386/cldemote.s: Likewise.
	* testsuite/gas/i386/i386.exp: Run new tests.
	* testsuite/gas/i386/x86-64-cldemote-intel.d: New.
	* testsuite/gas/i386/x86-64-cldemote.d: Likewise.
	* testsuite/gas/i386/x86-64-cldemote.s: Likewise.
	* testsuite/gas/i386/ilp32/x86-64-nops.d: Remove 0x0f1c
	NOP encoding that maps to cldemote.
	* testsuite/gas/i386/nops.d: Likewise.
	* testsuite/gas/i386/nops.s: Likewise.
	* testsuite/gas/i386/x86-64-nops.d: Likewise.
	* testsuite/gas/i386/x86-64-nops.s: Likewise.

opcode/
	* i386-dis.c: Add REG_0F1C_MOD_0, MOD_0F1C_PREFIX_0,
	PREFIX_0F1C.
	* i386-gen.c (cpu_flag_init): Add CPU_CLDEMOTE_FLAGS,
	(cpu_flags): Add CpuCLDEMOTE.
	* i386-init.h: Regenerate.
	* i386-opc.h (enum): Add CpuCLDEMOTE,
	(i386_cpu_flags): Add cpucldemote.
	* i386-opc.tbl: Add cldemote.
	* i386-tbl.h: Regenerate.
 2018-04-17 11:56:34 +02:00
Igor Tsimbalist de89d0a34d Enable Intel WAITPKG instructions. 
Intel has disclosed a set of new instructions for Tremont processor.
The spec is
https://software.intel.com/en-us/intel-architecture-instruction-set-extensions-programming-reference
This patch enables Intel WAITPKG instructions.

gas/
	* config/tc-i386.c (cpu_arch): Add WAITPKG.
	(cpu_noarch): Likewise.
	* doc/c-i386.texi: Document WAITPKG.
	* i386/i386.exp: Run WAITPKG tests.
	* testsuite/gas/i386/waitpkg-intel.d: New test.
	* testsuite/gas/i386/waitpkg.d: Likewise.
	* testsuite/gas/i386/waitpkg.s: Likewise.
	* testsuite/gas/i386/x86-64-waitpkg-intel.d: Likewise.
	* testsuite/gas/i386/x86-64-waitpkg.d: Likewise.
	* testsuite/gas/i386/x86-64-waitpkg.s: Likewise.

opcodes/
	* i386-dis.c (enum): Add PREFIX_MOD_0_0FAE_REG_6,
	PREFIX_MOD_1_0FAE_REG_6.
	(va_mode): New.
	(OP_E_register): Use va_mode.
	* i386-dis-evex.h (prefix_table):
	New instructions (see prefixes above).
	* i386-gen.c (cpu_flag_init): Add WAITPKG.
	(cpu_flags): Likewise.
	* i386-opc.h (enum): Likewise.
	(i386_cpu_flags): Likewise.
	* i386-opc.tbl: Add umonitor, umwait, tpause.
	* i386-init.h: Regenerate.
	* i386-tbl.h: Likewise.
 2018-04-11 21:37:12 +02:00
Jan Beulich c39e5b2671 x86: drop VecESize 
It again can be inferred from other information.

The vpopcntd templates all need to have Dword added to their memory
operands; the lack thereof was actually a bug preventing certain Intel
syntax code to assemble, so test cases get extended.
 2018-03-28 14:25:07 +02:00
Jan Beulich 8e6e0792d1 x86: convert broadcast insn attribute to boolean 
The (only) valid broadcast type for an insn can be inferred from other
information.
 2018-03-28 14:24:05 +02:00
H.J. Lu bd5dea8822 x86: Remove support for old (<= 2.8.1) versions of gcc 
Old (<= 2.8.1) versions of gcc generate broken fsubp, fsubrp, fdivp and
fdivrp instructions.  Assembler translates them to correct ones with a
warning:

[hjl@gnu-cfl-1 gas]$ cat x.s
	fsubp %st(3),%st
[hjl@gnu-cfl-1 gas]$ gcc -c x.s
x.s: Assembler messages:
x.s:1: Warning: translating to `fsubp %st,%st(3)'
[hjl@gnu-cfl-1 gas]$

This patch removes support for old (<= 2.8.1) versions of gcc:

[hjl@gnu-cfl-1 gas]$ ./as-new -o x.o x.s
x.s: Assembler messages:
x.s:1: Error: operand type mismatch for `fsubp'
[hjl@gnu-cfl-1 gas]$

gas/

	* NEWS: Mention -mold-gcc removal.
	* config/tc-i386.c (i386_error): Remove old_gcc_only.
	(old_gcc): Removed.
	(match_template): Remove old gcc support.
	(OPTION_MOLD_GCC): Removed.
	(OPTION_MRELAX_RELOCATIONS): Updated.
	(md_longopts): Remove OPTION_MOLD_GCC.
	(md_parse_option): Likewise.
	(md_show_usage): Remove -mold-gcc.
	* testsuite/gas/i386/general.s: Convert fsub/fdiv tests for old
	(<= 2.8.1) versions of gcc.
	* testsuite/gas/i386/intel.s: Likewise.
	* testsuite/gas/i386/general.l: Updated.
	* testsuite/gas/i386/intel-intel.d: Likewise.
	* testsuite/gas/i386/intel.d: Likewise.
	* testsuite/gas/i386/intel.e: Likewise.
	* testsuite/gas/i386/i386.exp: Don't pass -mold-gcc to general.

include/

	* opcode/i386 (OLDGCC_COMPAT): Removed.

opcodes/

	* i386-gen.c (opcode_modifiers): Remove OldGcc.
	* i386-opc.h (OldGcc): Removed.
	(i386_opcode_modifier): Remove oldgcc.
	* i386-opc.tbl: Remove fsubp, fsubrp, fdivp and fdivrp
	instructions for old (<= 2.8.1) versions of gcc.
	* i386-tbl.h: Regenerated.
 2018-03-08 06:31:52 -08:00
Jan Beulich e771e7c9fb x86: fold several AVX512VL templates 
The differences between some of the register and memory forms of the
same insn often don't really require the templates to be separate. For
example, Disp8MemShift is simply irrelevant to register forms. Fold
these as far as possible, and also fold register-only forms. Further
folding is possible, but needs other prereq work done first.

A note regarding EVEXDYN: This is intended to be used only when no other
properties of the template would make is_evex_encoding() return true. In
all "normal" cases I think it is preferable to omit this indicator, to
keep the table half way readable.
 2018-03-08 08:58:55 +01:00
Jan Beulich 38e314eb06 x86: drop FloatD 
It can be expressed by D, when making the consumer look at operand size
to tell apart both uses.
 2018-03-08 08:34:09 +01:00
H.J. Lu b6f8c7c452 x86: Add -O[2|s] assembler command-line options 
On x86, some instructions have alternate shorter encodings:

1. When the upper 32 bits of destination registers of

andq $imm31, %r64
testq $imm31, %r64
xorq %r64, %r64
subq %r64, %r64

known to be zero, we can encode them without the REX_W bit:

andl $imm31, %r32
testl $imm31, %r32
xorl %r32, %r32
subl %r32, %r32

This optimization is enabled with -O, -O2 and -Os.
2. Since 0xb0 mov with 32-bit destination registers zero-extends 32-bit
immediate to 64-bit destination register, we can use it to encode 64-bit
mov with 32-bit immediates.  This optimization is enabled with -O, -O2
and -Os.
3. Since the upper bits of destination registers of VEX128 and EVEX128
instructions are extended to zero, if all bits of destination registers
of AVX256 or AVX512 instructions are zero, we can use VEX128 or EVEX128
encoding to encode AVX256 or AVX512 instructions.  When 2 source
registers are identical, AVX256 and AVX512 andn and xor instructions:

VOP %reg, %reg, %dest_reg

can be encoded with

VOP128 %reg, %reg, %dest_reg

This optimization is enabled with -O2 and -Os.
4. 16-bit, 32-bit and 64-bit register tests with immediate may be
encoded as 8-bit register test with immediate.  This optimization is
enabled with -Os.

This patch does:

1. Add {nooptimize} pseudo prefix to disable instruction size
optimization.
2. Add optimize to i386_opcode_modifier to tell assembler that encoding
of an instruction may be optimized.

gas/

	PR gas/22871
	* NEWS: Mention -O[2|s].
	* config/tc-i386.c (_i386_insn): Add no_optimize.
	(optimize): New.
	(optimize_for_space): Likewise.
	(fits_in_imm7): New function.
	(fits_in_imm31): Likewise.
	(optimize_encoding): Likewise.
	(md_assemble): Call optimize_encoding to optimize encoding.
	(parse_insn): Handle {nooptimize}.
	(md_shortopts): Append "O::".
	(md_parse_option): Handle -On.
	* doc/c-i386.texi: Document -O0, -O, -O1, -O2 and -Os as well
	as {nooptimize}.
	* testsuite/gas/cfi/cfi-x86_64.d: Pass -O0 to assembler.
	* testsuite/gas/i386/ilp32/cfi/cfi-x86_64.d: Likewise.
	* testsuite/gas/i386/i386.exp: Run optimize-1, optimize-2,
	optimize-3, x86-64-optimize-1, x86-64-optimize-2,
	x86-64-optimize-3 and x86-64-optimize-4.
	* testsuite/gas/i386/optimize-1.d: New file.
	* testsuite/gas/i386/optimize-1.s: Likewise.
	* testsuite/gas/i386/optimize-2.d: Likewise.
	* testsuite/gas/i386/optimize-2.s: Likewise.
	* testsuite/gas/i386/optimize-3.d: Likewise.
	* testsuite/gas/i386/optimize-3.s: Likewise.
	* testsuite/gas/i386/x86-64-optimize-1.s: Likewise.
	* testsuite/gas/i386/x86-64-optimize-1.d: Likewise.
	* testsuite/gas/i386/x86-64-optimize-2.d: Likewise.
	* testsuite/gas/i386/x86-64-optimize-2.s: Likewise.
	* testsuite/gas/i386/x86-64-optimize-3.d: Likewise.
	* testsuite/gas/i386/x86-64-optimize-3.s: Likewise.
	* testsuite/gas/i386/x86-64-optimize-4.d: Likewise.
	* testsuite/gas/i386/x86-64-optimize-4.s: Likewise.

opcodes/

	PR gas/22871
	* i386-gen.c (opcode_modifiers): Add Optimize.
	* i386-opc.h (Optimize): New enum.
	(i386_opcode_modifier): Add optimize.
	* i386-opc.tbl: Add "Optimize" to "mov $imm, reg",
	"sub reg, reg/mem", "test $imm, acc", "test $imm, reg/mem",
	"and $imm, acc", "and $imm, reg/mem", "xor reg, reg/mem",
	"movq $imm, reg" and AVX256 and AVX512 versions of vandnps,
	vandnpd, vpandn, vpandnd, vpandnq, vxorps, vxorpd, vpxor,
	vpxord and vpxorq.
	* i386-tbl.h: Regenerated.
 2018-02-27 07:36:43 -08:00
Igor Tsimbalist be3a8dca2d Enable Intel PCONFIG instruction. 
Intel has disclosed a set of new instructions for Icelake processor.
The spec is
https://software.intel.com/sites/default/files/managed/c5/15/architecture-instruction-set-extensions-programming-reference.pdf

This patch enables Intel PCONFIG instruction.

gas/
	* config/tc-i386.c (cpu_arch): Add .pconfig.
	* doc/c-i386.texi: Document .pconfig.
	* testsuite/gas/i386/i386.exp: Add PCONFIG tests.
	* testsuite/gas/i386/pconfig-intel.d: New test.
	* testsuite/gas/i386/pconfig.d: Likewise.
	* testsuite/gas/i386/pconfig.s: Likewise.
	* testsuite/gas/i386/x86-64-pconfig-intel.d: Likewise.
	* testsuite/gas/i386/x86-64-pconfig.d: Likewise.
	* testsuite/gas/i386/x86-64-pconfig.s: Likewise.
opcodes/
	* i386-dis.c (enum): Add pconfig.
	* i386-gen.c (cpu_flag_init): Add CPU_PCONFIG_FLAGS.
	(cpu_flags): Add CpuPCONFIG.
	* i386-opc.h (enum): Add CpuPCONFIG.
	(i386_cpu_flags): Add cpupconfig.
	* i386-opc.tbl: Add PCONFIG instruction.
	* i386-init.h: Regenerate.
	* i386-tbl.h: Likewise.
 2018-01-23 20:09:35 +03:00
Igor Tsimbalist 3233d7d074 Enable Intel WBNOINVD instruction. 
Intel has disclosed a set of new instructions for Icelake processor.
The spec is
https://software.intel.com/sites/default/files/managed/c5/15/architecture-instruction-set-extensions-programming-reference.pdf

This patch enables Intel WBNOINVD instruction.

gas/
	* config/tc-i386.c (cpu_arch): Add .wbnoinvd.
	* doc/c-i386.texi: Document .wbnoinvd.
	* testsuite/gas/i386/i386.exp: Add WBNOINVD tests.
	* testsuite/gas/i386/wbnoinvd-intel.d: New test.
	* testsuite/gas/i386/wbnoinvd.d: Likewise.
	* testsuite/gas/i386/wbnoinvd.s: Likewise.
	* testsuite/gas/i386/x86-64-wbnoinvd-intel.d: Likewise.
	* testsuite/gas/i386/x86-64-wbnoinvd.d: Likewise.
	* testsuite/gas/i386/x86-64-wbnoinvd.s: Likewise.
opcodes/
	* i386-dis.c (enum): Add PREFIX_0F09.
	* i386-gen.c (cpu_flag_init): Add CPU_WBNOINVD_FLAGS.
	(cpu_flags): Add CpuWBNOINVD.
	* i386-opc.h (enum): Add CpuWBNOINVD.
	(i386_cpu_flags): Add cpuwbnoinvd.
	* i386-opc.tbl: Add WBNOINVD instruction.
	* i386-init.h: Regenerate.
	* i386-tbl.h: Likewise.
 2018-01-23 20:05:33 +03:00
Igor Tsimbalist d777820bf5 Replace CET bit with IBT and SHSTK bits. 
The latest specification for Intel CET technology defined two
new bits instead of previously used CET bit. These are IBT and
SHSTK bits. The patch replaces CET bit with IBT and SHSTK bits.

gas/
	* config/tc-i386.c (cpu_arch): Delete .cet. Add .ibt, .shstk.
	(cpu_noarch): Add noibt, noshstk.
	(parse_insn): Change cpucet to cpuibt.
	* doc/c-i386.texi: Delete .cet. Add .ibt, .shstk.
	* testsuite/gas/i386/cet-ibt-inval.l: New test.
	* testsuite/gas/i386/cet-ibt-inval.s: Likewise.
	* testsuite/gas/i386/cet-shstk-inval.l: Likewise.
	* testsuite/gas/i386/cet-shstk-inval.s: Likewise.
	* testsuite/gas/i386/x86-64-cet-ibt-inval.l: Likewise.
	* testsuite/gas/i386/x86-64-cet-ibt-inval.s: Likewise.
	* testsuite/gas/i386/x86-64-cet-shstk-inval.l: Likewise.
	* testsuite/gas/i386/x86-64-cet-shstk-inval.s: Likewise.

opcodes/
	* i386-gen.c (cpu_flag_init): Delete CPU_CET_FLAGS,
	CpuCET. Add CPU_IBT_FLAGS, CPU_SHSTK_FLAGS, CPY_ANY_IBT_FLAGS,
	CPU_ANY_SHSTK_FLAGS, CpuIBT, CpuSHSTK.
	(cpu_flags): Add CpuIBT, CpuSHSTK.
	* i386-opc.h (enum): Add CpuIBT, CpuSHSTK.
	(i386_cpu_flags): Add cpuibt, cpushstk.
	* i386-opc.tbl: Change CpuCET to CpuSHSTK and CpuIBT.
	* i386-init.h: Regenerate.
	* i386-tbl.h: Likewise.
 2018-01-17 19:48:28 +03:00
Alan Modra 219d1afa89 Update year range in copyright notice of binutils files 2018-01-03 17:49:56 +10:30
Jan Beulich 10c17abdd0 x86: fold certain AVX and AVX2 templates 
Just like for instructions in GPRs, there's no need to have separate
templates for otherwise identical insns acting on XMM or YMM registers
(or memory of the same size).
 2017-12-18 09:37:15 +01:00
Jan Beulich 1b54b8d7e4 x86: fold RegXMM/RegYMM/RegZMM into RegSIMD 
... qualified by their respective sizes, allowing to drop FirstXmm0 at
the same time.
 2017-12-18 09:36:14 +01:00
Jan Beulich ca0d63fe07 x86: drop FloatReg and FloatAcc 
Express them as Reg|Tbyte and Acc|Tbyte respectively.
 2017-12-18 09:35:01 +01:00
Jan Beulich dc821c5f9a x86: replace Reg8, Reg16, Reg32, and Reg64 
Use a combination of a single new Reg bit and Byte, Word, Dword, or
Qword instead.

Besides shrinking the number of operand type bits this has the benefit
of making register handling more similar to accumulator handling (a
generic flag is being accompanied by a "size qualifier"). It requires,
however, to split a few insn templates, as it is no longer correct to
have combinations like Reg32|Reg64|Byte. This slight growth in size will
hopefully be outweighed by this change paving the road for folding a
presumably much larger number of templates later on.
 2017-12-18 09:34:00 +01:00
Jan Beulich b5014f7af2 x86: drop Vec_Disp8 
This is fully redundant with Disp8MemShift being non-zero, and hence can
be folded with normal Disp8 handling.
 2017-11-30 11:47:38 +01:00
Igor Tsimbalist ee6872beb1 Enable Intel AVX512_BITALG instructions. 
Intel has disclosed a set of new instructions. The spec is
https://software.intel.com/sites/default/files/managed/c5/15/architecture-instruction-set-extensions-programming-reference.pdf

gas/

	* config/tc-i386.c (cpu_arch): Add .avx512_bitalg.
	(cpu_noarch): noavx512_bitalg.
	* doc/c-i386.texi: Document .avx512_bitalg, noavx512_bitalg.
	* testsuite/gas/i386/i386.exp: Add AVX512_BITALG tests.
	* testsuite/gas/i386/avx512f_bitalg-intel.d: New test.
	* testsuite/gas/i386/avx512f_bitalg.d: Likewise.
	* testsuite/gas/i386/avx512f_bitalg.s: Likewise.
	* testsuite/gas/i386/avx512vl_bitalg-intel.d: Likewise.
	* testsuite/gas/i386/avx512vl_bitalg.d: Likewise.
	* testsuite/gas/i386/avx512vl_bitalg.s: Likewise.
	* testsuite/gas/i386/x86-64-avx512f_bitalg-intel.d: Likewise.
	* testsuite/gas/i386/x86-64-avx512f_bitalg.d: Likewise.
	* testsuite/gas/i386/x86-64-avx512f_bitalg.s: Likewise.
	* testsuite/gas/i386/x86-64-avx512vl_bitalg-intel.d: Likewise.
	* testsuite/gas/i386/x86-64-avx512vl_bitalg.d: Likewise.
	* testsuite/gas/i386/x86-64-avx512vl_bitalg.s: Likewise.

opcodes/

	* i386-dis.c (enum): Add PREFIX_EVEX_0F3854, PREFIX_EVEX_0F388F.
	(enum): Add EVEX_W_0F3854_P_2.
	* i386-dis-evex.h (evex_table): Updated.
	* i386-gen.c (cpu_flag_init): Add CPU_AVX512_BITALG,
	CPU_ANY_AVX512_BITALG_FLAGS. Update CPU_ANY_AVX512F_FLAGS.
	(cpu_flags): Add CpuAVX512_BITALG.
	* i386-opc.h (enum): Add CpuAVX512_BITALG.
	(i386_cpu_flags): Add cpuavx512_bitalg..
	* i386-opc.tbl: Add Intel AVX512_BITALG instructions.
	* i386-init.h: Regenerate.
	* i386-tbl.h: Likewise.
 2017-10-23 15:58:18 +03:00
Igor Tsimbalist 8cfcb7659c Enable Intel AVX512_VNNI instructions. 
Intel has disclosed a set of new instructions. The spec is
https://software.intel.com/sites/default/files/managed/c5/15/architecture-instruction-set-extensions-programming-reference.pdf

gas/

	* config/tc-i386.c (cpu_arch): Add .avx512_vnni.
	(cpu_noarch): Add noavx512_vnni.
	* doc/c-i386.texi: Document .avx512_vnni.
	* testsuite/gas/i386/i386.exp: Add AVX512_VNNI tests.
	* testsuite/gas/i386/avx512vnni-intel.d: New test.
	* testsuite/gas/i386/avx512vnni.d: Likewise.
	* testsuite/gas/i386/avx512vnni.s: Likewise.
	* testsuite/gas/i386/avx512vnni_vl-intel.d: Likewise.
	* testsuite/gas/i386/avx512vnni_vl.d: Likewise.
	* testsuite/gas/i386/avx512vnni_vl.s: Likewise.
	* testsuite/gas/i386/x86-64-avx512vnni-intel.d: Likewise.
	* testsuite/gas/i386/x86-64-avx512vnni.d: Likewise.
	* testsuite/gas/i386/x86-64-avx512vnni.s: Likewise.
	* testsuite/gas/i386/x86-64-avx512vnni_vl-intel.d: Likewise.
	* testsuite/gas/i386/x86-64-avx512vnni_vl.d: Likewise.
	* testsuite/gas/i386/x86-64-avx512vnni_vl.s: Likewise.

opcodes/

	* i386-dis.c (enum): Add PREFIX_EVEX_0F3850, PREFIX_EVEX_0F3851.
	* i386-dis-evex.h (evex_table): Updated.
	* i386-gen.c (cpu_flag_init): Add CPU_AVX512_VNNI,
	CPU_ANY_AVX512_VNNI_FLAGS. Update CPU_ANY_AVX512F_FLAGS.
	(cpu_flags): Add CpuAVX512_VNNI.
	* i386-opc.h (enum): Add CpuAVX512_VNNI.
	(i386_cpu_flags): Add cpuavx512_vnni.
	* i386-opc.tbl Add Intel AVX512_VNNI instructions.
	* i386-init.h: Regenerate.
	* i386-tbl.h: Likewise.
 2017-10-23 15:58:18 +03:00
Igor Tsimbalist ff1982d53a Enable Intel VPCLMULQDQ instruction. 
Intel has disclosed a set of new instructions. The spec is
https://software.intel.com/sites/default/files/managed/c5/15/architecture-instruction-set-extensions-programming-reference.pdf

gas/

	* config/tc-i386.c (cpu_arch): Add VPCLMULQDQ.
	* doc/c-i386.texi: Document VPCLMULQDQ.
	* testsuite/gas/i386/i386.exp: Run VPCLMULQDQ tests.
	* testsuite/gas/i386/avx512f_vpclmulqdq-intel.d: New test.
	* testsuite/gas/i386/avx512f_vpclmulqdq-wig.s: Ditto.
	* testsuite/gas/i386/avx512f_vpclmulqdq-wig1-intel.d: Ditto.
	* testsuite/gas/i386/avx512f_vpclmulqdq-wig1.d: Ditto.
	* testsuite/gas/i386/avx512f_vpclmulqdq.d: Ditto.
	* testsuite/gas/i386/avx512f_vpclmulqdq.s: Ditto.
	* testsuite/gas/i386/avx512vl_vpclmulqdq-intel.d: Ditto.
	* testsuite/gas/i386/avx512vl_vpclmulqdq-wig.s: Ditto.
	* testsuite/gas/i386/avx512vl_vpclmulqdq-wig1-intel.d: Ditto.
	* testsuite/gas/i386/avx512vl_vpclmulqdq-wig1.d: Ditto.
	* testsuite/gas/i386/avx512vl_vpclmulqdq.d: Ditto.
	* testsuite/gas/i386/avx512vl_vpclmulqdq.s: Ditto.
	* testsuite/gas/i386/vpclmulqdq-intel.d: Ditto.
	* testsuite/gas/i386/vpclmulqdq.d: Ditto.
	* testsuite/gas/i386/vpclmulqdq.s: Ditto.
	* testsuite/gas/i386/x86-64-avx512f_vpclmulqdq-intel.d: Ditto.
	* testsuite/gas/i386/x86-64-avx512f_vpclmulqdq-wig.s: Ditto.
	* testsuite/gas/i386/x86-64-avx512f_vpclmulqdq-wig1-intel.d: Ditto.
	* testsuite/gas/i386/x86-64-avx512f_vpclmulqdq-wig1.d: Ditto.
	* testsuite/gas/i386/x86-64-avx512f_vpclmulqdq.d: Ditto.
	* testsuite/gas/i386/x86-64-avx512f_vpclmulqdq.s: Ditto.
	* testsuite/gas/i386/x86-64-avx512vl_vpclmulqdq-intel.d: Ditto.
	* testsuite/gas/i386/x86-64-avx512vl_vpclmulqdq-wig.s: Ditto.
	* testsuite/gas/i386/x86-64-avx512vl_vpclmulqdq-wig1-intel.d: Ditto.
	* testsuite/gas/i386/x86-64-avx512vl_vpclmulqdq-wig1.d: Ditto.
	* testsuite/gas/i386/x86-64-avx512vl_vpclmulqdq.d: Ditto.
	* testsuite/gas/i386/x86-64-avx512vl_vpclmulqdq.s: Ditto.
	* testsuite/gas/i386/x86-64-vpclmulqdq-intel.d: Ditto.
	* testsuite/gas/i386/x86-64-vpclmulqdq.d: Ditto.
	* testsuite/gas/i386/x86-64-vpclmulqdq.s: Ditto.

opcodes/

	* i386-dis.c (enum): Add PREFIX_EVEX_0F3A44.
	(enum): Remove VEX_LEN_0F3A44_P_2.
	(vex_len_table): Ditto.
	(enum): Remove VEX_W_0F3A44_P_2.
	(vew_w_table): Ditto.
	(prefix_table): Adjust instructions (see prefixes above).
	* i386-dis-evex.h (evex_table):
	Add new instructions (see prefixes above).
	* i386-gen.c (cpu_flag_init): Add VPCLMULQDQ.
	(bitfield_cpu_flags): Ditto.
	* i386-opc.h (enum): Ditto.
	(i386_cpu_flags): Ditto.
	(CpuUnused): Comment out to avoid zero-width field problem.
	* i386-opc.tbl (vpclmulqdq): New instruction.
	* i386-init.h: Regenerate.
	* i386-tbl.h: Ditto.
 2017-10-23 15:58:18 +03:00
Igor Tsimbalist 8dcf1fadf2 Enable Intel VAES instructions. 
Intel has disclosed a set of new instructions. The spec is
https://software.intel.com/sites/default/files/managed/c5/15/architecture-instruction-set-extensions-programming-reference.pdf

gas/

	* config/tc-i386.c (cpu_arch): Add VAES.
	* doc/c-i386.texi: Document VAES.
	* testsuite/gas/i386/i386.exp: Run VAES tests.
	* testsuite/gas/i386/avx512f_vaes-intel.d: New test.
	* testsuite/gas/i386/avx512f_vaes-wig.s: Ditto.
	* testsuite/gas/i386/avx512f_vaes-wig1-intel.d: Ditto.
	* testsuite/gas/i386/avx512f_vaes-wig1.d: Ditto.
	* testsuite/gas/i386/avx512f_vaes.d: Ditto.
	* testsuite/gas/i386/avx512f_vaes.s: Ditto.
	* testsuite/gas/i386/avx512vl_vaes-intel.d: Ditto.
	* testsuite/gas/i386/avx512vl_vaes-wig.s: Ditto.
	* testsuite/gas/i386/avx512vl_vaes-wig1-intel.d: Ditto.
	* testsuite/gas/i386/avx512vl_vaes-wig1.d: Ditto.
	* testsuite/gas/i386/avx512vl_vaes.d: Ditto.
	* testsuite/gas/i386/avx512vl_vaes.s: Ditto.
	* testsuite/gas/i386/vaes-intel.d: Ditto.
	* testsuite/gas/i386/vaes.d: Ditto.
	* testsuite/gas/i386/vaes.s: Ditto.
	* testsuite/gas/i386/x86-64-avx512f_vaes-intel.d: Ditto.
	* testsuite/gas/i386/x86-64-avx512f_vaes-wig.s: Ditto.
	* testsuite/gas/i386/x86-64-avx512f_vaes-wig1-intel.d: Ditto.
	* testsuite/gas/i386/x86-64-avx512f_vaes-wig1.d: Ditto.
	* testsuite/gas/i386/x86-64-avx512f_vaes.d: Ditto.
	* testsuite/gas/i386/x86-64-avx512f_vaes.s: Ditto.
	* testsuite/gas/i386/x86-64-avx512vl_vaes-intel.d: Ditto.
	* testsuite/gas/i386/x86-64-avx512vl_vaes-wig.s: Ditto.
	* testsuite/gas/i386/x86-64-avx512vl_vaes-wig1-intel.d: Ditto.
	* testsuite/gas/i386/x86-64-avx512vl_vaes-wig1.d: Ditto.
	* testsuite/gas/i386/x86-64-avx512vl_vaes.d: Ditto.
	* testsuite/gas/i386/x86-64-avx512vl_vaes.s: Ditto.
	* testsuite/gas/i386/x86-64-vaes-intel.d: Ditto.
	* testsuite/gas/i386/x86-64-vaes.d: Ditto.
	* testsuite/gas/i386/x86-64-vaes.s: Ditto.

opcodes/

	* i386-dis.c (enum): Add PREFIX_EVEX_0F38DC, PREFIX_EVEX_0F38DD,
	PREFIX_EVEX_0F38DE, PREFIX_EVEX_0F38DF.
	(enum): Remove VEX_LEN_0F38DC_P_2, VEX_LEN_0F38DD_P_2,
	VEX_LEN_0F38DE_P_2, VEX_LEN_0F38DF_P_2.
	(vex_len_table): Ditto.
	(enum): Remove VEX_W_0F38DC_P_2, VEX_W_0F38DD_P_2,
	VEX_W_0F38DE_P_2, VEX_W_0F38DF_P_2.
	(vew_w_table): Ditto.
	(prefix_table): Adjust instructions (see prefixes above).
	* i386-dis-evex.h (evex_table):
	Add new instructions (see prefixes above).
	* i386-gen.c (cpu_flag_init): Add VAES.
	(bitfield_cpu_flags): Ditto.
	* i386-opc.h (enum): Ditto.
	(i386_cpu_flags): Ditto.
	* i386-opc.tbl (vaes{enc,dec}{last,}): New instructions.
	* i386-init.h: Regenerate.
	* i386-tbl.h: Ditto.
 2017-10-23 15:58:18 +03:00
Igor Tsimbalist 48521003d5 Enable Intel GFNI instructions. 
Intel has disclosed a set of new instructions. The spec is
https://software.intel.com/sites/default/files/managed/c5/15/architecture-instruction-set-extensions-programming-reference.pdf

gas/

	* config/tc-i386.c (cpu_arch): Add .gfni.
	* doc/c-i386.texi: Document .gfni.
	* testsuite/gas/i386/i386.exp: Add GFNI tests.
	* testsuite/gas/i386/avx.s: New GFNI test.
	* testsuite/gas/i386/x86-64-avx.s: Likewise.
	* testsuite/gas/i386/avx.d: Adjust.
	* testsuite/gas/i386/avx-intel.d: Likewise
	* testsuite/gas/i386/ilp32/x86-64-avx-intel.d: Likewise.
	* testsuite/gas/i386/ilp32/x86-64-avx.d: Likewise.
	* testsuite/gas/i386/avx512f_gfni-intel.d: New test.
	* testsuite/gas/i386/avx512f_gfni.d: Likewise.
	* testsuite/gas/i386/avx512f_gfni.s: Likewise.
	* testsuite/gas/i386/avx512vl_gfni-intel.d: Likewise.
	* testsuite/gas/i386/avx512vl_gfni.d: Likewise.
	* testsuite/gas/i386/avx512vl_gfni.s: Likewise.
	* testsuite/gas/i386/gfni-intel.d: Likewise.
	* testsuite/gas/i386/gfni.d: Likewise.
	* testsuite/gas/i386/gfni.s: Likewise.
	* testsuite/gas/i386/x86-64-avx512f_gfni-intel.d: Likewise.
	* testsuite/gas/i386/x86-64-avx512f_gfni.d: Likewise.
	* testsuite/gas/i386/x86-64-avx512f_gfni.s: Likewise.
	* testsuite/gas/i386/x86-64-avx512vl_gfni-intel.d: Likewise.
	* testsuite/gas/i386/x86-64-avx512vl_gfni.d: Likewise.
	* testsuite/gas/i386/x86-64-avx512vl_gfni.s: Likewise.
	* testsuite/gas/i386/x86-64-avx_gfni-intel.d: Likewise.
	* testsuite/gas/i386/x86-64-avx_gfni.d: Likewise.
	* testsuite/gas/i386/x86-64-avx_gfni.s: Likewise.
	* testsuite/gas/i386/x86-64-gfni-intel.d: Likewise.
	* testsuite/gas/i386/x86-64-gfni.d: Likewise.
	* testsuite/gas/i386/x86-64-gfni.s: Likewise.

opcodes/

	* i386-dis.c (enum): Add PREFIX_0F38CF, PREFIX_0F3ACE, PREFIX_0F3ACF,
	PREFIX_VEX_0F38CF, PREFIX_VEX_0F3ACE, PREFIX_VEX_0F3ACF,
	PREFIX_EVEX_0F38CF, PREFIX_EVEX_0F3ACE, PREFIX_EVEX_0F3ACF.
	(enum): Add VEX_W_0F38CF_P_2, VEX_W_0F3ACE_P_2, VEX_W_0F3ACF_P_2,
	EVEX_W_0F3ACE_P_2, EVEX_W_0F3ACF_P_2.
	(prefix_table): Updated (see prefixes above).
	(three_byte_table): Likewise.
	(vex_w_table): Likewise.
	* i386-dis-evex.h: Likewise.
	* i386-gen.c (cpu_flag_init): Add CPU_GFNI_FLAGS, CpuGFNI.
	(cpu_flags): Add CpuGFNI.
	* i386-opc.h (enum): Add CpuGFNI.
	(i386_cpu_flags): Add cpugfni.
	* i386-opc.tbl: Add Intel GFNI instructions.
	* i386-init.h: Regenerate.
	* i386-tbl.h: Likewise.
 2017-10-23 15:58:13 +03:00
Igor Tsimbalist 53467f5707 Enable Intel AVX512_VBMI2 instructions. 
Intel has disclosed a set of new instructions. The spec is
https://software.intel.com/sites/default/files/managed/c5/15/architecture-instruction-set-extensions-programming-reference.pdf

gas/

	* config/tc-i386.c (cpu_arch): Add .avx512_vbmi2.
	(cpu_noarch): noavx512_vbmi2.
	* doc/c-i386.texi: Document .avx512_vbmi2, noavx512_vbmi2.
	* testsuite/gas/i386/i386.exp: Add AVX512_VBMI2 tests.
	* testsuite/gas/i386/avx512vbmi2-intel.d: New test.
	* testsuite/gas/i386/avx512vbmi2.d: Likewise.
	* testsuite/gas/i386/avx512vbmi2.s: Likewise.
	* testsuite/gas/i386/avx512vbmi2_vl-intel.d: Likewise.
	* testsuite/gas/i386/avx512vbmi2_vl.d: Likewise.
	* testsuite/gas/i386/avx512vbmi2_vl.s: Likewise.
	* testsuite/gas/i386/x86-64-avx512vbmi2-intel.d: Likewise.
	* testsuite/gas/i386/x86-64-avx512vbmi2.d: Likewise.
	* testsuite/gas/i386/x86-64-avx512vbmi2.s: Likewise.
	* testsuite/gas/i386/x86-64-avx512vbmi2_vl-intel.d: Likewise.
	* testsuite/gas/i386/x86-64-avx512vbmi2_vl.d: Likewise.
	* testsuite/gas/i386/x86-64-avx512vbmi2_vl.s: Likewise.

opcodes/

	* i386-dis.c (enum): Add b_scalar_mode, w_scalar_mode.
	Define EXbScalar and EXwScalar for OP_EX.
	(enum): Add PREFIX_EVEX_0F3862, PREFIX_EVEX_0F3863,
	PREFIX_EVEX_0F3870, PREFIX_EVEX_0F3871, PREFIX_EVEX_0F3872,
	PREFIX_EVEX_0F3873, PREFIX_EVEX_0F3A70, PREFIX_EVEX_0F3A71,
	PREFIX_EVEX_0F3A72, PREFIX_EVEX_0F3A73.
	(enum): Add EVEX_W_0F3862_P_2, EVEX_W_0F3863_P_2,
	EVEX_W_0F3870_P_2, EVEX_W_0F3871_P_2, EVEX_W_0F3872_P_2,
	EVEX_W_0F3873_P_2, EVEX_W_0F3A70_P_2, EVEX_W_0F3A71_P_2,
	EVEX_W_0F3A72_P_2, EVEX_W_0F3A73_P_2.
	(intel_operand_size): Handle b_scalar_mode and w_scalar_mode.
	(OP_E_memory): Likewise.
	* i386-dis-evex.h: Updated.
	* i386-gen.c (cpu_flag_init): Add CPU_AVX512_VBMI2,
	CPU_ANY_AVX512_VBMI2_FLAGS. Update CPU_ANY_AVX512F_FLAGS.
	(cpu_flags): Add CpuAVX512_VBMI2.
	* i386-opc.h (enum): Add CpuAVX512_VBMI2.
	(i386_cpu_flags): Add cpuavx512_vbmi2.
	* i386-opc.tbl: Add Intel AVX512_VBMI2 instructions.
	* i386-init.h: Regenerate.
	* i386-tbl.h: Likewise.
 2017-10-23 15:58:07 +03:00
H.J. Lu 04ef582ace x86: Add NOTRACK prefix support 
For register indirect branches, NOTRACK prefix (0x3e), which is also
the DS segment register prefix, can be used to ignore the CET indirect
branch track.

gas/

	* config/tc-i386.c (REX_PREFIX): Changed to 7.
	(NOTRACK_PREFIX): New.
	(MAX_PREFIXES): Changed to 8.
	(_i386_insn): Add notrack_prefix.
	(PREFIX_GROUP): Add PREFIX_DS.
	(add_prefix): Return PREFIX_DS for DS_PREFIX_OPCODE.
	(md_assemble): Check if NOTRACK prefix is supported.
	(parse_insn): Set notrack_prefix and issue an error for
	other prefixes after NOTRACK prefix.
	* testsuite/gas/i386/i386.exp: Run tests for NOTRACK prefix.
	* testsuite/gas/i386/notrack-intel.d: New file.
	* testsuite/gas/i386/notrack.d: Likewise.
	* testsuite/gas/i386/notrack.s: Likewise.
	* testsuite/gas/i386/notrackbad.l: Likewise.
	* testsuite/gas/i386/notrackbad.s: Likewise.
	* testsuite/gas/i386/x86-64-notrack-intel.d: Likewise.
	* testsuite/gas/i386/x86-64-notrack.d: Likewise.
	* testsuite/gas/i386/x86-64-notrack.s: Likewise.
	* testsuite/gas/i386/x86-64-notrackbad.l: Likewise.
	* testsuite/gas/i386/x86-64-notrackbad.s: Likewise.

include/

	* include/opcode/i386.h (NOTRACK_PREFIX_OPCODE): New.

opcodes/

	* i386-dis.c (NOTRACK_Fixup): New.
	(NOTRACK): Likewise.
	(NOTRACK_PREFIX): Likewise.
	(last_active_prefix): Likewise.
	(reg_table): Use NOTRACK on indirect call and jmp.
	(ckprefix): Set last_active_prefix.
	(prefix_name): Return "notrack" for NOTRACK_PREFIX.
	* i386-gen.c (opcode_modifiers): Add NoTrackPrefixOk.
	* i386-opc.h (NoTrackPrefixOk): New.
	(i386_opcode_modifier): Add notrackprefixok.
	* i386-opc.tbl: Add NoTrackPrefixOk to indirect call and jmp.
	Add notrack.
	* i386-tbl.h: Regenerated.
 2017-05-22 11:02:58 -07:00
H.J. Lu 86fa6981e7 X86: Add pseudo prefixes to control encoding 
Many x86 instructions have more than one encodings.  Assembler picks
the default one, usually the shortest one.  Although the ".s", ".d8"
and ".d32" suffixes can be used to swap register operands or specify
displacement size, they aren't very flexible.  This patch adds pseudo
prefixes, {xxx}, to control instruction encoding.  The available
pseudo prefixes are {disp8}, {disp32}, {load}, {store}, {vex2}, {vex3}
and {evex}.  Pseudo prefixes are preferred over the ".s", ".d8" and
".d32" suffixes, which are deprecated.

gas/

	* config/tc-i386.c (_i386_insn): Add dir_encoding and
	vec_encoding.  Remove swap_operand and need_vrex.
	(extra_symbol_chars): Add '}'.
	(md_begin): Mark '}' with LEX_BEGIN_NAME.  Allow '}' in
	mnemonic.
	(build_vex_prefix): Don't use 2-byte VEX encoding with
	{vex3}.  Check dir_encoding and load.
	(parse_insn): Check pseudo prefixes.  Set dir_encoding.
	(VEX_check_operands): Likewise.
	(match_template): Check dir_encoding and load.
	(parse_real_register): Set vec_encoding instead of need_vrex.
	(parse_register): Likewise.
	* doc/c-i386.texi: Document {disp8}, {disp32}, {load}, {store},
	{vex2}, {vex3} and {evex}.  Remove ".s", ".d8" and ".d32"
	* testsuite/gas/i386/i386.exp: Run pseudos and x86-64-pseudos.
	* testsuite/gas/i386/pseudos.d: New file.
	* testsuite/gas/i386/pseudos.s: Likewise.
	* testsuite/gas/i386/x86-64-pseudos.d: Likewise.
	* testsuite/gas/i386/x86-64-pseudos.s: Likewise.

opcodes/

	* i386-gen.c (opcode_modifiers): Replace S with Load.
	* i386-opc.h (S): Removed.
	(Load): New.
	(i386_opcode_modifier): Replace s with load.
	* i386-opc.tbl: Add {disp8}, {disp32}, {swap}, {vex2}, {vex3}
	and {evex}.  Replace S with Load.
	* i386-tbl.h: Regenerated.
 2017-03-09 09:59:00 -08:00
H.J. Lu 603555e563 Add support for Intel CET instructions 
Support Intel Control-flow Enforcement Technology (CET) instructions:

https://software.intel.com/sites/default/files/managed/4d/2a/control-flow-enforcement-technology-preview.pdf

gas/

	* config/tc-i386.c (cpu_arch): Add .cet.
	* doc/c-i386.texi: Document cet.
	* testsuite/gas/i386/cet-intel.d: New file.
	* testsuite/gas/i386/cet.d: Likewise.
	* testsuite/gas/i386/cet.s: Likewise.
	* testsuite/gas/i386/x86-64-cet-intel.d: Likewise.
	* testsuite/gas/i386/x86-64-cet.d: Likewise.
	* testsuite/gas/i386/x86-64-cet.s: Likewise.
	* testsuite/gas/i386/i386.exp: Run Intel CET tests.

opcodes/

	* i386-dis.c (REG_0F1E_MOD_3): New enum.
	(MOD_0F1E_PREFIX_1): Likewise.
	(MOD_0F38F5_PREFIX_2): Likewise.
	(MOD_0F38F6_PREFIX_0): Likewise.
	(RM_0F1E_MOD_3_REG_7): Likewise.
	(PREFIX_MOD_0_0F01_REG_5): Likewise.
	(PREFIX_MOD_3_0F01_REG_5_RM_1): Likewise.
	(PREFIX_MOD_3_0F01_REG_5_RM_2): Likewise.
	(PREFIX_0F1E): Likewise.
	(PREFIX_MOD_0_0FAE_REG_5): Likewise.
	(PREFIX_0F38F5): Likewise.
	(dis386_twobyte): Use PREFIX_0F1E.
	(reg_table): Add REG_0F1E_MOD_3.
	(prefix_table): Add PREFIX_MOD_0_0F01_REG_5,
	PREFIX_MOD_3_0F01_REG_5_RM_1, PREFIX_MOD_3_0F01_REG_5_RM_2,
	PREFIX_0F1E, PREFIX_MOD_0_0FAE_REG_5 and PREFIX_0F38F5.  Update
	PREFIX_0FAE_REG_6 and PREFIX_0F38F6.
	(three_byte_table): Use PREFIX_0F38F5.
	(mod_table): Use PREFIX_MOD_0_0F01_REG_5, PREFIX_MOD_0_0FAE_REG_5.
	Add MOD_0F1E_PREFIX_1, MOD_0F38F5_PREFIX_2, MOD_0F38F6_PREFIX_0.
	(rm_table): Add MOD_0F38F5_PREFIX_2, MOD_0F38F6_PREFIX_0,
	RM_0F1E_MOD_3_REG_7.  Use PREFIX_MOD_3_0F01_REG_5_RM_1 and
	PREFIX_MOD_3_0F01_REG_5_RM_2.
	* i386-gen.c (cpu_flag_init): Add CPU_CET_FLAGS.
	(cpu_flags): Add CpuCET.
	* i386-opc.h (CpuCET): New enum.
	(CpuUnused): Commented out.
	(i386_cpu_flags): Add cpucet.
	* i386-opc.tbl: Add Intel CET instructions.
	* i386-init.h: Regenerated.
	* i386-tbl.h: Likewise.
 2017-03-06 15:26:37 -08:00
Igor Tsimbalist 620214f742 Enable Intel AVX512_VPOPCNTDQ instructions 
gas/

2017-01-12  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>

	* config/tc-i386.c (cpu_arch): Add .avx512_vpopcntdq.
	(cpu_noarch): Add noavx512_vpopcntdq.
	* doc/c-i386.texi: Document avx512_vpopcntdq, noavx512_vpopcntdq.
	* testsuite/gas/i386/i386.exp: Run AVX512_VPOPCNTDQ tests.
	* testsuite/gas/i386/avx512_vpopcntdqd-intel.d: New file.
	* testsuite/gas/i386/avx512_vpopcntdqd.d: Ditto.
	* testsuite/gas/i386/avx512_vpopcntdqd.s: Ditto.
	* testsuite/gas/i386/x86-64-avx512_vpopcntdqd-intel.d: Ditto.
	* testsuite/gas/i386/x86-64-avx512_vpopcntdqd.d: Ditto.
	* testsuite/gas/i386/x86-64-avx512_vpopcntdqd.s: Ditto.

opcodes/

2017-01-12  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>

	* i386-dis.c (enum): Add PREFIX_EVEX_0F3855, EVEX_W_0F3855_P_2.
	* i386-dis-evex.h (evex_table): Updated.
	* i386-gen.c (cpu_flag_init): Add CPU_AVX512_VPOPCNTDQ_FLAGS,
	CPU_ANY_AVX512_VPOPCNTDQ_FLAGS. Update CPU_ANY_AVX512F_FLAGS.
	(cpu_flags): Add CpuAVX512_VPOPCNTDQ.
	* i386-opc.h (enum): (AVX512_VPOPCNTDQ): New.
	(i386_cpu_flags): Add cpuavx512_vpopcntdq.
	* i386-opc.tbl: Add Intel AVX512_VPOPCNTDQ instructions.
	* i386-init.h: Regenerate.
	* i386-tbl.h: Ditto.
 2017-01-12 08:44:24 -08:00
Alan Modra 2571583aed Update year range in copyright notice of all files. 2017-01-02 14:08:56 +10:30
Igor Tsimbalist 47acf0bd9f Enable Intel AVX512_4VNNIW instructions 
gas/

	* config/tc-i386.c: (cpu_arch) Add .avx512_4vnniw.
	(cpu_noarch): Add noavx512_4vnniw.
	* doc/c-i386.texi: Document avx512_4vnniw, noavx512_4vnniw.
	* testsuite/gas/i386/i386.exp: Run AVX512_4VNNIW tests.
	* testsuite/gas/i386/avx512_4vnniwd_vl-intel.d: New test.
	* testsuite/gas/i386/avx512_4vnniwd_vl.d: Ditto.
	* testsuite/gas/i386/avx512_4vnniwd_vl.s: Ditto.
	* testsuite/gas/i386/avx512_4vnniwd-intel.d: Ditto.
	* testsuite/gas/i386/avx512_4vnniwd.d: Ditto.
	* testsuite/gas/i386/avx512_4vnniwd.s: Ditto.
	* testsuite/gas/i386/x86-64-avx512_4vnniwd_vl-intel.d: Ditto.
	* testsuite/gas/i386/x86-64-avx512_4vnniwd_vl.d: Ditto.
	* testsuite/gas/i386/x86-64-avx512_4vnniwd_vl.s: Ditto.
	* testsuite/gas/i386/x86-64-avx512_4vnniwd-intel.d: Ditto.
	* testsuite/gas/i386/x86-64-avx512_4vnniwd.d: Ditto.
	* testsuite/gas/i386/x86-64-avx512_4vnniwd.s: Ditto.

opcodes/

	* i386-dis.c (enum): Add PREFIX_EVEX_0F3852, PREFIX_EVEX_0F3853.
	* i386-dis-evex.h (evex_table): Updated.
	* i386-gen.c (cpu_flag_init): Add CPU_AVX512_4VNNIW_FLAGS,
	CPU_ANY_AVX512_4VNNIW_FLAGS. Update CPU_ANY_AVX512F_FLAGS.
	(cpu_flags): Add CpuAVX512_4VNNIW.
	* i386-opc.h (enum): (AVX512_4VNNIW): New.
	(i386_cpu_flags): Add cpuavx512_4vnniw.
	* i386-opc.tbl: Add Intel AVX512_4VNNIW instructions.
	* i386-init.h: Regenerate.
	* i386-tbl.h: Ditto.
 2016-11-02 12:31:25 -07:00
Igor Tsimbalist 920d2ddccb Enable Intel AVX512_4FMAPS instructions 
gas/

	* config/tc-i386.c (cpu_arch): Add .avx512_4fmaps.
	(cpu_noarch): Add noavx512_4fmaps.
	(process_operands): Handle implicit quad group.
	* doc/c-i386.texi: Document avx512_4fmaps, noavx512_4fmaps.
	* testsuite/gas/i386/i386.exp: Add AVX512_4FMAPS tests.
	* testsuite/gas/i386/avx512_4fmaps_vl-intel.d: New test.
	* testsuite/gas/i386/avx512_4fmaps_vl.d: Ditto.
	* testsuite/gas/i386/avx512_4fmaps_vl.s: Ditto.
	* testsuite/gas/i386/avx512_4fmaps-intel.d: Ditto.
	* testsuite/gas/i386/avx512_4fmaps.d: Ditto.
	* testsuite/gas/i386/avx512_4fmaps.s: Ditto.
	* testsuite/gas/i386/avx512_4fmaps-warn.l: Ditto.
	* testsuite/gas/i386/avx512_4fmaps-warn.s: Ditto.
	* testsuite/gas/i386/avx512_4fmaps_vl-warn.l: Ditto.
	* testsuite/gas/i386/avx512_4fmaps_vl-warn.s: Ditto.
	* testsuite/gas/i386/x86-64-avx512_4fmaps_vl-intel.d: Ditto.
	* testsuite/gas/i386/x86-64-avx512_4fmaps_vl.d: Ditto.
	* testsuite/gas/i386/x86-64-avx512_4fmaps_vl.s: Ditto.
	* testsuite/gas/i386/x86-64-avx512_4fmaps-intel.d: Ditto.
	* testsuite/gas/i386/x86-64-avx512_4fmaps.d: Ditto.
	* testsuite/gas/i386/x86-64-avx512_4fmaps.s: Ditto.
	* testsuite/gas/i386/x86-64-avx512_4fmaps-warn.l: Ditto.
	* testsuite/gas/i386/x86-64-avx512_4fmaps-warn.s: Ditto.
	* testsuite/gas/i386/x86-64-avx512_4fmaps_vl-warn.l: Ditto.
	* testsuite/gas/i386/x86-64-avx512_4fmaps_vl-warn.s: Ditto.

opcodes/

	* i386-dis.c. (enum): Add PREFIX_EVEX_0F389A,
	PREFIX_EVEX_0F389B, PREFIX_EVEX_0F38AA, PREFIX_EVEX_0F38AB.
	* i386-dis-evex.h (evex_table): Updated.
	* i386-gen.c (cpu_flag_init): Add CPU_AVX512_4FMAPS_FLAGS,
	CPU_ANY_AVX512_4FMAPS_FLAGS. Update CPU_ANY_AVX512F_FLAGS.
	(cpu_flags): Add CpuAVX512_4FMAPS.
	(opcode_modifiers): Add ImplicitQuadGroup modifier.
	* i386-opc.h (AVX512_4FMAP): New.
	(i386_cpu_flags): Add cpuavx512_4fmaps.
	(ImplicitQuadGroup): New.
	(i386_opcode_modifier): Add implicitquadgroup.
	* i386-opc.tbl: Add Intel AVX512_4FMAPS instructions.
	* i386-init.h: Regenerate.
	* i386-tbl.h: Ditto.
 2016-11-02 12:25:34 -07:00