Add support for the CRC Application Specific Extension for Release 6 of
the MIPS Architecture.
[1] "MIPS Architecture for Programmers Volume II-A: The MIPS32
Instruction Set Manual", Imagination Technologies Ltd., Document
Number: MD00086, Revision 6.06, December 15, 2016, Section 3.2
"Alphabetical List of Instructions", pp. 143-148
[2] "MIPS Architecture for Programmers Volume II-A: The MIPS64
Instruction Set Manual", Imagination Technologies Ltd., Document
Number: MD00087, Revision 6.06, December 15, 2016, Section 3.2
"Alphabetical List of Instructions", pp. 165-170
ChangeLog:
bfd/
2018-06-13 Scott Egerton <scott.egerton@imgtec.com>
Faraz Shahbazker <Faraz.Shahbazker@mips.com>
* elfxx-mips.c (print_mips_ases): Add CRC.
binutils/
2018-06-13 Scott Egerton <scott.egerton@imgtec.com>
Faraz Shahbazker <Faraz.Shahbazker@mips.com>
* readelf.c (print_mips_ases): Add CRC.
gas/
2018-06-13 Scott Egerton <scott.egerton@imgtec.com>
Faraz Shahbazker <Faraz.Shahbazker@mips.com>
Maciej W. Rozycki <macro@mips.com>
* config/tc-mips.c (options): Add OPTION_CRC and OPTION_NO_CRC.
(md_longopts): Likewise.
(md_show_usage): Add help for -mcrc and -mno-crc.
(mips_ases): Define availability for CRC and CRC64.
(mips_convert_ase_flags): Map ASE_CRC to AFL_ASE_CRC.
* doc/as.texinfo: Document -mcrc, -mno-crc.
* doc/c-mips.texi: Document -mcrc, -mno-crc, .set crc and
.set no-crc.
* testsuite/gas/mips/ase-errors-1.l: Add error checks for CRC
ASE.
* testsuite/gas/mips/ase-errors-2.l: Likewise.
* testsuite/gas/mips/ase-errors-1.s: Likewise.
* testsuite/gas/mips/ase-errors-2.s: Likewise.
* testsuite/gas/mips/crc.d: New test.
* testsuite/gas/mips/crc64.d: New test.
* testsuite/gas/mips/crc-err.d: New test.
* testsuite/gas/mips/crc64-err.d: New test.
* testsuite/gas/mips/crc-err.l: New test stderr output.
* testsuite/gas/mips/crc64-err.l: New test stderr output.
* testsuite/gas/mips/crc.s: New test source.
* testsuite/gas/mips/crc64.s: New test source.
* testsuite/gas/mips/crc-err.s: New test source.
* testsuite/gas/mips/crc64-err.s: New test source.
* testsuite/gas/mips/mips.exp: Run the new tests.
include/
2018-06-13 Scott Egerton <scott.egerton@imgtec.com>
Faraz Shahbazker <Faraz.Shahbazker@mips.com>
* elf/mips.h (AFL_ASE_CRC): New macro.
(AFL_ASE_MASK): Update to include AFL_ASE_CRC.
* opcode/mips.h (ASE_CRC): New macro.
* opcode/mips.h (ASE_CRC64): Likewise.
opcodes/
2018-06-13 Scott Egerton <scott.egerton@imgtec.com>
Faraz Shahbazker <Faraz.Shahbazker@mips.com>
* mips-dis.c (mips_arch_choices): Add CRC and CRC64 ASEs.
* mips-opc.c (CRC, CRC64): New macros.
(mips_builtin_opcodes): Define crc32b, crc32h, crc32w,
crc32cb, crc32ch and crc32cw for CRC. Define crc32d and
crc32cd for CRC64.
Match commit 4ffff32f75 ("Match mips_optimize to the -O option
supplied") and adjust `--help' output for `-O0', `-O', `-O1' and `-O2'
options.
gas/
* config/tc-mips.c (md_show_usage): Correct help text for `-O0'
and `-O'. Mention `-O1'. Add `-O2' and its description.
This patch adds support to gas for -mcpu=cortex-a76 in the usual way.
make check-gas passes without problems.
2018-06-08 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
* config/tc-arm.c (arm_cpus): Add Cortex-A76 entry.
* doc/c-arm.texi (-mcpu): Document cortex-a76.
This patch adds support to gas for -mcpu=cortex-a76 in the usual way.
make check-gas passes without problems.
2018-06-08 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
* config/tc-aarch64.c (aarch64_cpus): Add Cortex-A76 entry.
* doc/c-aarch64.texi (-mcpu): Document cortex-a76.
Detect illegal FMOV instructions that changes the size from 32 bits to 64
bits and vice versa. Add tests for these and other undefined FMOV
instructions.
PR 20319
gas * testsuite/gas/aarch64/illegal-3.s: Test if unallocated FMOV encodings
are detected as undefined.
* testsuite/gas/aarch64/illegal-3.d: Likewise.
* testsuite/gas/aarch64/illegal.s: Test if FMOV instructions that are
changing the size from 32 bits to 64 bits and vice versa trigger an
error.
* testsuite/gas/aarch64/illegal.l: Likewise.
opcodes * aarch64-tbl.h: Introduce QL_INT2FP_FMOV and QL_FP2INT_FMOV.
(aarch64_opcode_table) : Use QL_INT2FP_FMOV and QL_FP2INT_FMOV.
This patch fixes an uninitialized memory issue that can under certain
circumstances turn an error into a warning because non_fatal was not initialised
in all cases.
Verified using valgrind.
gas/config/tc-aarch64.c
PR binutils/21446
* tc-aarch64.c (record_operand_error, record_operand_error_with_data):
Initialize non_fatal.
It is currently not possible to correctly match .xt.prop information
for sections with identical VMA. Allow creation of separate property
sections in the BFD. Add assembler option --separate-prop-tables to
allow creation of separate property sections.
2018-06-04 Volodymyr Arbatov <arbatov@cadence.com>
bfd/
* elf32-xtensa.c (elf32xtensa_separate_props): New global
variable.
(xtensa_add_names): New function.
(xtensa_property_section_name): Add new parameter
separate_sections, use it to choose property section name.
(xtensa_get_separate_property_section): New function.
(xtensa_get_property_section): Invoke
xtensa_get_separate_property_section to get individual property
section if it exists, common property section otherwise.
(xtensa_make_property_section): Pass elf32xtensa_separate_props
to xtensa_property_section_name.
gas/
* config/tc-xtensa.c (elf32xtensa_separate_props): New
declaration.
(option_separate_props, option_no_separate_props): New
enumeration constants.
(md_longopts): Add separate-prop-tables option.
(md_parse_option): Add cases for option_separate_props and
option_no_separate_props.
(md_show_usage): Add help for [no-]separate-prop-tables options.
Bump version number to 2.30.52 since _bfd_link_hide_symbol has been added
to bfd_target.
bfd/
* version.m4: Bump version to 2.30.52
* configure: Regenerated.
binutils/
* configure: Regenerated.
gas/
* configure: Regenerated.
gprof/
* configure: Regenerated.
ld/
* configure: Regenerated.
opcodes/
* configure: Regenerated.
Fix locviews on ia64. If we do not drop the view after copying line
info to slots in the bundle, we may attempt to compute the view more
than once and get very confused.
for gas/ChangeLog
* dwarf2dbg.c (dwarf2_consume_line_info): Drop view.
All REX bits can be specified via individual prefixes. Redundancy should
only be reported on a per-bit basis.
Note that I originally had further checks added to the test case,
checking the effect also on PDEP. I had to strip those, because my patch
to correctly handle those
(https://sourceware.org/ml/binutils/2017-02/msg00280.html) was rejected.
I continue to think that there should not be any new prefix introduced
to handle the VEX case - whether the encoding of an insn requires VEX et
al should not be of immediate interest to the programmer.
... as is already done elsewhere: There's no need for the use of
operand_type_equal() here - the bit identifying control registers isn't
used for any other purposes.
The control register is never expressed by REX.B; this bit only affects
the involved GPR. Also only one of the operands can have its "control"
flag set, so only check the correct operand.
This patch regenerates a number of files that either were edited by
hand or not regenerated when s12z support was added to binutils.
bfd/
* Makefile.in: Regenerate.
* po/SRC-POTFILES.in: Regenerate.
gas/
* po/POTFILES.in: Regenerate.
ld/
* po/BLD-POTFILES.in: Regenerate.
opcodes/
* Makefile.in: Regenerate.
* po/POTFILES.in: Regenerate.
bfd * Makefile.am: Add s12z files.
* Makefile.in: Regenerate.
* archures.c: Add bfd_s12z_arch.
* bfd-in.h: Add exports of bfd_putb24 and bfd_putl24.
* bfd-in2.h: Regenerate.
* config.bfd: Add s12z target.
* configure.ac: Add s12z target.
* configure: Regenerate.
* cpu-s12z.c: New file.
* elf32-s12z.c: New file.
* libbfd.c (bfd_putb24): New function.
(bfd_putl24): New function.
* libbfd.h: Regenerate.
* reloc.c: Add s12z relocations.
(bfd_get_reloc_size): Handle size 5 relocs.
* targets.c: Add s12z_elf32_vec.
opcodes * Makefile.am: Add support for s12z architecture.
* configure.ac: Likewise.
* disassemble.c: Likewise.
* disassemble.h: Likewise.
* Makefile.in: Regenerate.
* configure: Regenerate.
* s12z-dis.c: New file.
* s12z.h: New file.
include * elf/s12z.h: New header.
ld * Makefile.am: Add support for s12z architecture.
* configure.tgt: Likewise.
* Makefile.in: Regenerate.
* emulparams/m9s12zelf.sh: New file.
* scripttempl/elfm9s12z.sc: New file.
* testsuite/ld-discard/static.d: Expect to fail for the s12z
target.
* testsuite/ld-elf/endsym.d: Likewise.
* testsuite/ld-elf/merge.d: Likewise.
* testsuite/ld-elf/pr14926.d: Skip for the s12z target.
* testsuite/ld-elf/sec64k.exp: Likewise.
* testsuite/ld-s12z: New directory.
* testsuite/ld-s12z/opr-linking.d: New file.
* testsuite/ld-s12z/opr-linking.s: New file.
* testsuite/ld-s12z/relative-linking.d: New file.
* testsuite/ld-s12z/relative-linking.s: New file.
* testsuite/ld-s12z/z12s.exp: New file.
gas * Makefile.am: Add support for s12z target.
* Makefile.in: Regenerate.
* NEWS: Mention the new support.
* config/tc-s12z.c: New file.
* config/tc-s12z.h: New file.
* configure.tgt: Add s12z support.
* doc/Makefile.am: Likewise.
* doc/Makefile.in: Regenerate.
* doc/all.texi: Add s12z documentation.
* doc/as.textinfo: Likewise.
* doc/c-s12z.texi: New file.
* testsuite/gas/s12z: New directory.
* testsuite/gas/s12z/abs.d: New file.
* testsuite/gas/s12z/abs.s: New file.
* testsuite/gas/s12z/adc-imm.d: New file.
* testsuite/gas/s12z/adc-imm.s: New file.
* testsuite/gas/s12z/adc-opr.d: New file.
* testsuite/gas/s12z/adc-opr.s: New file.
* testsuite/gas/s12z/add-imm.d: New file.
* testsuite/gas/s12z/add-imm.s: New file.
* testsuite/gas/s12z/add-opr.d: New file.
* testsuite/gas/s12z/add-opr.s: New file.
* testsuite/gas/s12z/and-imm.d: New file.
* testsuite/gas/s12z/and-imm.s: New file.
* testsuite/gas/s12z/and-opr.d: New file.
* testsuite/gas/s12z/and-opr.s: New file.
* testsuite/gas/s12z/and-or-cc.d: New file.
* testsuite/gas/s12z/and-or-cc.s: New file.
* testsuite/gas/s12z/bfext-special.d: New file.
* testsuite/gas/s12z/bfext-special.s: New file.
* testsuite/gas/s12z/bfext.d: New file.
* testsuite/gas/s12z/bfext.s: New file.
* testsuite/gas/s12z/bit-manip.d: New file.
* testsuite/gas/s12z/bit-manip.s: New file.
* testsuite/gas/s12z/bit.d: New file.
* testsuite/gas/s12z/bit.s: New file.
* testsuite/gas/s12z/bra-expression-defined.d: New file.
* testsuite/gas/s12z/bra-expression-defined.s: New file.
* testsuite/gas/s12z/bra-expression-undef.d: New file.
* testsuite/gas/s12z/bra-expression-undef.s: New file.
* testsuite/gas/s12z/bra.d: New file.
* testsuite/gas/s12z/bra.s: New file.
* testsuite/gas/s12z/brclr-symbols.d: New file.
* testsuite/gas/s12z/brclr-symbols.s: New file.
* testsuite/gas/s12z/brset-clr-opr-imm-rel.d: New file.
* testsuite/gas/s12z/brset-clr-opr-imm-rel.s: New file.
* testsuite/gas/s12z/brset-clr-opr-reg-rel.d: New file.
* testsuite/gas/s12z/brset-clr-opr-reg-rel.s: New file.
* testsuite/gas/s12z/brset-clr-reg-imm-rel.d: New file.
* testsuite/gas/s12z/brset-clr-reg-imm-rel.s: New file.
* testsuite/gas/s12z/brset-clr-reg-reg-rel.d: New file.
* testsuite/gas/s12z/brset-clr-reg-reg-rel.s: New file.
* testsuite/gas/s12z/clb.d: New file.
* testsuite/gas/s12z/clb.s: New file.
* testsuite/gas/s12z/clr-opr.d: New file.
* testsuite/gas/s12z/clr-opr.s: New file.
* testsuite/gas/s12z/clr.d: New file.
* testsuite/gas/s12z/clr.s: New file.
* testsuite/gas/s12z/cmp-imm.d: New file.
* testsuite/gas/s12z/cmp-imm.s: New file.
* testsuite/gas/s12z/cmp-opr-inc.d: New file.
* testsuite/gas/s12z/cmp-opr-inc.s: New file.
* testsuite/gas/s12z/cmp-opr-rdirect.d: New file.
* testsuite/gas/s12z/cmp-opr-rdirect.s: New file.
* testsuite/gas/s12z/cmp-opr-reg.d: New file.
* testsuite/gas/s12z/cmp-opr-reg.s: New file.
* testsuite/gas/s12z/cmp-opr-rindirect.d: New file.
* testsuite/gas/s12z/cmp-opr-rindirect.s: New file.
* testsuite/gas/s12z/cmp-opr-sxe4.d: New file.
* testsuite/gas/s12z/cmp-opr-sxe4.s: New file.
* testsuite/gas/s12z/cmp-opr-xys.d: New file.
* testsuite/gas/s12z/cmp-opr-xys.s: New file.
* testsuite/gas/s12z/cmp-s-imm.d: New file.
* testsuite/gas/s12z/cmp-s-imm.s: New file.
* testsuite/gas/s12z/cmp-s-opr.d: New file.
* testsuite/gas/s12z/cmp-s-opr.s: New file.
* testsuite/gas/s12z/cmp-xy.d: New file.
* testsuite/gas/s12z/cmp-xy.s: New file.
* testsuite/gas/s12z/com-opr.d: New file.
* testsuite/gas/s12z/com-opr.s: New file.
* testsuite/gas/s12z/complex-shifts.d: New file.
* testsuite/gas/s12z/complex-shifts.s: New file.
* testsuite/gas/s12z/db-tb-cc-opr.d: New file.
* testsuite/gas/s12z/db-tb-cc-opr.s: New file.
* testsuite/gas/s12z/db-tb-cc-reg.d: New file.
* testsuite/gas/s12z/db-tb-cc-reg.s: New file.
* testsuite/gas/s12z/dbCC.d: New file.
* testsuite/gas/s12z/dbCC.s: New file.
* testsuite/gas/s12z/dec-opr.d: New file.
* testsuite/gas/s12z/dec-opr.s: New file.
* testsuite/gas/s12z/dec.d: New file.
* testsuite/gas/s12z/dec.s: New file.
* testsuite/gas/s12z/div.d: New file.
* testsuite/gas/s12z/div.s: New file.
* testsuite/gas/s12z/eor.d: New file.
* testsuite/gas/s12z/eor.s: New file.
* testsuite/gas/s12z/exg.d: New file.
* testsuite/gas/s12z/exg.s: New file.
* testsuite/gas/s12z/ext24-ld-xy.d: New file.
* testsuite/gas/s12z/ext24-ld-xy.s: New file.
* testsuite/gas/s12z/inc-opr.d: New file.
* testsuite/gas/s12z/inc-opr.s: New file.
* testsuite/gas/s12z/inc.d: New file.
* testsuite/gas/s12z/inc.s: New file.
* testsuite/gas/s12z/inh.d: New file.
* testsuite/gas/s12z/inh.s: New file.
* testsuite/gas/s12z/jmp.d: New file.
* testsuite/gas/s12z/jmp.s: New file.
* testsuite/gas/s12z/jsr.d: New file.
* testsuite/gas/s12z/jsr.s: New file.
* testsuite/gas/s12z/ld-imm-page2.d: New file.
* testsuite/gas/s12z/ld-imm-page2.s: New file.
* testsuite/gas/s12z/ld-imm.d: New file.
* testsuite/gas/s12z/ld-imm.s: New file.
* testsuite/gas/s12z/ld-immu18.d: New file.
* testsuite/gas/s12z/ld-immu18.s: New file.
* testsuite/gas/s12z/ld-large-direct.d: New file.
* testsuite/gas/s12z/ld-large-direct.s: New file.
* testsuite/gas/s12z/ld-opr.d: New file.
* testsuite/gas/s12z/ld-opr.s: New file.
* testsuite/gas/s12z/ld-s-opr.d: New file.
* testsuite/gas/s12z/ld-s-opr.s: New file.
* testsuite/gas/s12z/ld-small-direct.d: New file.
* testsuite/gas/s12z/ld-small-direct.s: New file.
* testsuite/gas/s12z/lea-immu18.d: New file.
* testsuite/gas/s12z/lea-immu18.s: New file.
* testsuite/gas/s12z/lea.d: New file.
* testsuite/gas/s12z/lea.s: New file.
* testsuite/gas/s12z/mac.d: New file.
* testsuite/gas/s12z/mac.s: New file.
* testsuite/gas/s12z/min-max.d: New file.
* testsuite/gas/s12z/min-max.s: New file.
* testsuite/gas/s12z/mod.d: New file.
* testsuite/gas/s12z/mod.s: New file.
* testsuite/gas/s12z/mov.d: New file.
* testsuite/gas/s12z/mov.s: New file.
* testsuite/gas/s12z/mul-imm.d: New file.
* testsuite/gas/s12z/mul-imm.s: New file.
* testsuite/gas/s12z/mul-opr-opr.d: New file.
* testsuite/gas/s12z/mul-opr-opr.s: New file.
* testsuite/gas/s12z/mul-opr.d: New file.
* testsuite/gas/s12z/mul-opr.s: New file.
* testsuite/gas/s12z/mul-reg.d: New file.
* testsuite/gas/s12z/mul-reg.s: New file.
* testsuite/gas/s12z/mul.d: New file.
* testsuite/gas/s12z/mul.s: New file.
* testsuite/gas/s12z/neg-opr.d: New file.
* testsuite/gas/s12z/neg-opr.s: New file.
* testsuite/gas/s12z/not-so-simple-shifts.d: New file.
* testsuite/gas/s12z/not-so-simple-shifts.s: New file.
* testsuite/gas/s12z/opr-18u.d: New file.
* testsuite/gas/s12z/opr-18u.s: New file.
* testsuite/gas/s12z/opr-expr.d: New file.
* testsuite/gas/s12z/opr-expr.s: New file.
* testsuite/gas/s12z/opr-ext-18.d: New file.
* testsuite/gas/s12z/opr-ext-18.s: New file.
* testsuite/gas/s12z/opr-idx-24-reg.d: New file.
* testsuite/gas/s12z/opr-idx-24-reg.s: New file.
* testsuite/gas/s12z/opr-idx3-reg.d: New file.
* testsuite/gas/s12z/opr-idx3-reg.s: New file.
* testsuite/gas/s12z/opr-idx3-xysp-24.d: New file.
* testsuite/gas/s12z/opr-idx3-xysp-24.s: New file.
* testsuite/gas/s12z/opr-indirect-expr.d: New file.
* testsuite/gas/s12z/opr-indirect-expr.s: New file.
* testsuite/gas/s12z/opr-symbol.d: New file.
* testsuite/gas/s12z/opr-symbol.s: New file.
* testsuite/gas/s12z/or-imm.d: New file.
* testsuite/gas/s12z/or-imm.s: New file.
* testsuite/gas/s12z/or-opr.d: New file.
* testsuite/gas/s12z/or-opr.s: New file.
* testsuite/gas/s12z/p2-mul.d: New file.
* testsuite/gas/s12z/p2-mul.s: New file.
* testsuite/gas/s12z/page2-inh.d: New file.
* testsuite/gas/s12z/page2-inh.s: New file.
* testsuite/gas/s12z/psh-pul.d: New file.
* testsuite/gas/s12z/psh-pul.s: New file.
* testsuite/gas/s12z/qmul.d: New file.
* testsuite/gas/s12z/qmul.s: New file.
* testsuite/gas/s12z/rotate.d: New file.
* testsuite/gas/s12z/rotate.s: New file.
* testsuite/gas/s12z/s12z.exp: New file.
* testsuite/gas/s12z/sat.d: New file.
* testsuite/gas/s12z/sat.s: New file.
* testsuite/gas/s12z/sbc-imm.d: New file.
* testsuite/gas/s12z/sbc-imm.s: New file.
* testsuite/gas/s12z/sbc-opr.d: New file.
* testsuite/gas/s12z/sbc-opr.s: New file.
* testsuite/gas/s12z/shift.d: New file.
* testsuite/gas/s12z/shift.s: New file.
* testsuite/gas/s12z/simple-shift.d: New file.
* testsuite/gas/s12z/simple-shift.s: New file.
* testsuite/gas/s12z/single-ops.d: New file.
* testsuite/gas/s12z/single-ops.s: New file.
* testsuite/gas/s12z/specd6.d: New file.
* testsuite/gas/s12z/specd6.s: New file.
* testsuite/gas/s12z/st-large-direct.d: New file.
* testsuite/gas/s12z/st-large-direct.s: New file.
* testsuite/gas/s12z/st-opr.d: New file.
* testsuite/gas/s12z/st-opr.s: New file.
* testsuite/gas/s12z/st-s-opr.d: New file.
* testsuite/gas/s12z/st-s-opr.s: New file.
* testsuite/gas/s12z/st-small-direct.d: New file.
* testsuite/gas/s12z/st-small-direct.s: New file.
* testsuite/gas/s12z/st-xy.d: New file.
* testsuite/gas/s12z/st-xy.s: New file.
* testsuite/gas/s12z/sub-imm.d: New file.
* testsuite/gas/s12z/sub-imm.s: New file.
* testsuite/gas/s12z/sub-opr.d: New file.
* testsuite/gas/s12z/sub-opr.s: New file.
* testsuite/gas/s12z/tfr.d: New file.
* testsuite/gas/s12z/tfr.s: New file.
* testsuite/gas/s12z/trap.d: New file.
* testsuite/gas/s12z/trap.s: New file.
binutils* readelf.c: Add support for s12z architecture.
* testsuite/lib/binutils-common.exp (is_elf_format): Excluse s12z
targets.
Remove `-Wshadow' compilation errors:
cc1: warnings being treated as errors
.../gas/config/tc-nds32.c: In function 'md_assemble':
.../gas/config/tc-nds32.c:5212: error: declaration of 'expr' shadows a global declaration
.../gas/expr.h:180: error: shadowed declaration is here
make[4]: *** [tc-nds32.o] Error 1
which for versions of GCC before 4.8 prevent support for NDS32 targets
from being built. See also GCC PR c/53066.
gas/
* tc-nds32.c (md_assemble): Rename `expr' local variable to
`insn_expr'.
This patch adds constraints for read and write only system registers with the
msr and mrs instructions. The code will treat having both flags set and none
set as the same. These flags add constraints that must be matched up. e.g. a
system register with a READ only flag set, can only be used with mrs. If The
constraint fails a warning is emitted.
Examples of the warnings generated:
test.s: Assembler messages:
test.s:5: Warning: specified register cannot be written to at operand 1 -- `msr dbgdtrrx_el0,x3'
test.s:7: Warning: specified register cannot be read from at operand 2 -- `mrs x3,dbgdtrtx_el0'
test.s:8: Warning: specified register cannot be written to at operand 1 -- `msr midr_el1,x3'
and disassembly notes:
0000000000000000 <main>:
0: d5130503 msr dbgdtrtx_el0, x3
4: d5130503 msr dbgdtrtx_el0, x3
8: d5330503 mrs x3, dbgdtrrx_el0
c: d5330503 mrs x3, dbgdtrrx_el0
10: d5180003 msr midr_el1, x3 ; note: writing to a read-only register.
Note that because dbgdtrrx_el0 and dbgdtrtx_el0 have the same encoding, during
disassembly the constraints are use to disambiguate between the two. An exact
constraint match is always prefered over partial ones if available.
As always the warnings can be suppressed with -w and also be made errors using
warnings as errors.
binutils/
PR binutils/21446
* doc/binutils.texi (-M): Document AArch64 options.
gas/
PR binutils/21446
* testsuite/gas/aarch64/illegal-sysreg-2.s: Fix pmbidr_el1 test.
* testsuite/gas/aarch64/illegal-sysreg-2.l: Likewise.
* testsuite/gas/aarch64/illegal-sysreg-2.d: Likewise.
* testsuite/gas/aarch64/sysreg-diagnostic.s: New.
* testsuite/gas/aarch64/sysreg-diagnostic.l: New.
* testsuite/gas/aarch64/sysreg-diagnostic.d: New.
include/
PR binutils/21446
* opcode/aarch64.h (F_SYS_READ, F_SYS_WRITE): New.
opcodes/
PR binutils/21446
* aarch64-asm.c (opintl.h): Include.
(aarch64_ins_sysreg): Enforce read/write constraints.
* aarch64-dis.c (aarch64_ext_sysreg): Likewise.
* aarch64-opc.h (F_DEPRECATED, F_ARCHEXT, F_HASXT): Moved here.
(F_REG_READ, F_REG_WRITE): New.
* aarch64-opc.c (aarch64_print_operand): Generate notes for
AARCH64_OPND_SYSREG.
(F_DEPRECATED, F_ARCHEXT, F_HASXT): Move to aarch64-opc.h.
(aarch64_sys_regs): Add constraints to currentel, midr_el1, ctr_el0,
mpidr_el1, revidr_el1, aidr_el1, dczid_el0, id_dfr0_el1, id_pfr0_el1,
id_pfr1_el1, id_afr0_el1, id_mmfr0_el1, id_mmfr1_el1, id_mmfr2_el1,
id_mmfr3_el1, id_mmfr4_el1, id_isar0_el1, id_isar1_el1, id_isar2_el1,
id_isar3_el1, id_isar4_el1, id_isar5_el1, mvfr0_el1, mvfr1_el1,
mvfr2_el1, ccsidr_el1, id_aa64pfr0_el1, id_aa64pfr1_el1,
id_aa64dfr0_el1, id_aa64dfr1_el1, id_aa64isar0_el1, id_aa64isar1_el1,
id_aa64mmfr0_el1, id_aa64mmfr1_el1, id_aa64mmfr2_el1, id_aa64afr0_el1,
id_aa64afr0_el1, id_aa64afr1_el1, id_aa64zfr0_el1, clidr_el1,
csselr_el1, vsesr_el2, erridr_el1, erxfr_el1, rvbar_el1, rvbar_el2,
rvbar_el3, isr_el1, tpidrro_el0, cntfrq_el0, cntpct_el0, cntvct_el0,
mdccsr_el0, dbgdtrrx_el0, dbgdtrtx_el0, osdtrrx_el1, osdtrtx_el1,
mdrar_el1, oslar_el1, oslsr_el1, dbgauthstatus_el1, pmbidr_el1,
pmsidr_el1, pmswinc_el0, pmceid0_el0, pmceid1_el0.
* aarch64-tbl.h (aarch64_opcode_table): Add constraints to
msr (F_SYS_WRITE), mrs (F_SYS_READ).
This patch adds a new platform option "notes" that can be used to indicate if
disassembly notes should be placed in the disassembly as comments.
These notes can contain information about a failing constraint such as reading
from a write-only register. The disassembly will not be blocked because of this
but -M notes will emit a comment saying that the operation is not allowed.
For assembly this patch adds a new non-fatal status for errors. This is
essentially a warning. The reason for not creating an actual warning type is
that this causes the interaction between the ordering of warnings and errors to
be problematic. Currently the error buffer is almost always filled because of
the way operands are matched during assembly. An earlier template may have put
an error there that would only be displayed if no other template matches or
generates a higher priority error. But by definition a warning is lower
priority than a warning, so the error (which is incorrect if another template
matched) will supersede the warning. By treating warnings as errors and only
later relaxing the severity this relationship keeps working and the existing
reporting infrastructure can be re-used.
binutils/
PR binutils/21446
* doc/binutils.texi (-M): Document AArch64 options.
* NEWS: Document notes and warnings.
gas/
PR binutils/21446
* config/tc-aarch64.c (print_operands): Indicate no notes.
(output_operand_error_record): Support non-fatal errors.
(output_operand_error_report, warn_unpredictable_ldst, md_assemble):
Likewise.
include/
PR binutils/21446
* opcode/aarch64.h (aarch64_operand_error): Add non_fatal.
(aarch64_print_operand): Support notes.
opcodes/
PR binutils/21446
* aarch64-dis.c (no_notes: New.
(parse_aarch64_dis_option): Support notes.
(aarch64_decode_insn, print_operands): Likewise.
(print_aarch64_disassembler_options): Document notes.
* aarch64-opc.c (aarch64_print_operand): Support notes.
This patch if the first patch in a series to add the ability to add constraints
to system registers that an instruction must adhere to in order for the register
to be usable with that instruction.
These constraints can also be used to disambiguate between registers with the
same encoding during disassembly.
This patch adds a new flags entry in the sysreg structures and ensures it is
filled in and read out during assembly/disassembly. It also adds the ability for
the assemble and disassemble functions to be able to gracefully fail and re-use
the existing error reporting infrastructure.
The return type of these functions are changed to a boolean to denote success or
failure and the error structure is passed around to them. This requires
aarch64-gen changes so a lot of the changes here are just mechanical.
gas/
PR binutils/21446
* config/tc-aarch64.c (parse_sys_reg): Return register flags.
(parse_operands): Fill in register flags.
gdb/
PR binutils/21446
* aarch64-tdep.c (aarch64_analyze_prologue,
aarch64_software_single_step, aarch64_displaced_step_copy_insn):
Indicate not interested in errors.
include/
PR binutils/21446
* opcode/aarch64.h (aarch64_opnd_info): Change sysreg to struct.
(aarch64_decode_insn): Accept error struct.
opcodes/
PR binutils/21446
* aarch64-asm.h (aarch64_insert_operand, aarch64_##x): Return boolean
and take error struct.
* aarch64-asm.c (aarch64_ext_regno, aarch64_ins_reglane,
aarch64_ins_reglist, aarch64_ins_ldst_reglist,
aarch64_ins_ldst_reglist_r, aarch64_ins_ldst_elemlist,
aarch64_ins_advsimd_imm_shift, aarch64_ins_imm, aarch64_ins_imm_half,
aarch64_ins_advsimd_imm_modified, aarch64_ins_fpimm,
aarch64_ins_imm_rotate1, aarch64_ins_imm_rotate2, aarch64_ins_fbits,
aarch64_ins_aimm, aarch64_ins_limm_1, aarch64_ins_limm,
aarch64_ins_inv_limm, aarch64_ins_ft, aarch64_ins_addr_simple,
aarch64_ins_addr_regoff, aarch64_ins_addr_offset, aarch64_ins_addr_simm,
aarch64_ins_addr_simm10, aarch64_ins_addr_uimm12,
aarch64_ins_simd_addr_post, aarch64_ins_cond, aarch64_ins_sysreg,
aarch64_ins_pstatefield, aarch64_ins_sysins_op, aarch64_ins_barrier,
aarch64_ins_prfop, aarch64_ins_hint, aarch64_ins_reg_extended,
aarch64_ins_reg_shifted, aarch64_ins_sve_addr_ri_s4xvl,
aarch64_ins_sve_addr_ri_s6xvl, aarch64_ins_sve_addr_ri_s9xvl,
aarch64_ins_sve_addr_ri_s4, aarch64_ins_sve_addr_ri_u6,
aarch64_ins_sve_addr_rr_lsl, aarch64_ins_sve_addr_rz_xtw,
aarch64_ins_sve_addr_zi_u5, aarch64_ext_sve_addr_zz,
aarch64_ins_sve_addr_zz_lsl, aarch64_ins_sve_addr_zz_sxtw,
aarch64_ins_sve_addr_zz_uxtw, aarch64_ins_sve_aimm,
aarch64_ins_sve_asimm, aarch64_ins_sve_index, aarch64_ins_sve_limm_mov,
aarch64_ins_sve_quad_index, aarch64_ins_sve_reglist,
aarch64_ins_sve_scale, aarch64_ins_sve_shlimm, aarch64_ins_sve_shrimm,
aarch64_ins_sve_float_half_one, aarch64_ins_sve_float_half_two,
aarch64_ins_sve_float_zero_one, aarch64_opcode_encode): Likewise.
* aarch64-dis.h (aarch64_extract_operand, aarch64_##x): Likewise.
* aarch64-dis.c (aarch64_ext_regno, aarch64_ext_reglane,
aarch64_ext_reglist, aarch64_ext_ldst_reglist,
aarch64_ext_ldst_reglist_r, aarch64_ext_ldst_elemlist,
aarch64_ext_advsimd_imm_shift, aarch64_ext_imm, aarch64_ext_imm_half,
aarch64_ext_advsimd_imm_modified, aarch64_ext_fpimm,
aarch64_ext_imm_rotate1, aarch64_ext_imm_rotate2, aarch64_ext_fbits,
aarch64_ext_aimm, aarch64_ext_limm_1, aarch64_ext_limm, decode_limm,
aarch64_ext_inv_limm, aarch64_ext_ft, aarch64_ext_addr_simple,
aarch64_ext_addr_regoff, aarch64_ext_addr_offset, aarch64_ext_addr_simm,
aarch64_ext_addr_simm10, aarch64_ext_addr_uimm12,
aarch64_ext_simd_addr_post, aarch64_ext_cond, aarch64_ext_sysreg,
aarch64_ext_pstatefield, aarch64_ext_sysins_op, aarch64_ext_barrier,
aarch64_ext_prfop, aarch64_ext_hint, aarch64_ext_reg_extended,
aarch64_ext_reg_shifted, aarch64_ext_sve_addr_ri_s4xvl,
aarch64_ext_sve_addr_ri_s6xvl, aarch64_ext_sve_addr_ri_s9xvl,
aarch64_ext_sve_addr_ri_s4, aarch64_ext_sve_addr_ri_u6,
aarch64_ext_sve_addr_rr_lsl, aarch64_ext_sve_addr_rz_xtw,
aarch64_ext_sve_addr_zi_u5, aarch64_ext_sve_addr_zz,
aarch64_ext_sve_addr_zz_lsl, aarch64_ext_sve_addr_zz_sxtw,
aarch64_ext_sve_addr_zz_uxtw, aarch64_ext_sve_aimm,
aarch64_ext_sve_asimm, aarch64_ext_sve_index, aarch64_ext_sve_limm_mov,
aarch64_ext_sve_quad_index, aarch64_ext_sve_reglist,
aarch64_ext_sve_scale, aarch64_ext_sve_shlimm, aarch64_ext_sve_shrimm,
aarch64_ext_sve_float_half_one, aarch64_ext_sve_float_half_two,
aarch64_ext_sve_float_zero_one, aarch64_opcode_decode): Likewise.
(determine_disassembling_preference, aarch64_decode_insn,
print_insn_aarch64_word, print_insn_data): Take errors struct.
(print_insn_aarch64): Use errors.
* aarch64-asm-2.c: Regenerate.
* aarch64-dis-2.c: Regenerate.
* aarch64-gen.c (print_operand_inserter): Use errors and change type to
boolean in aarch64_insert_operan.
(print_operand_extractor): Likewise.
* aarch64-opc.c (aarch64_print_operand): Use sysreg struct.
gas * write.c (maybe_generate_build_notes): Generate notes on a
per-code-section basis. Skip linkonce sections.
ld * testsuite/ld-elf/notes.exp: New file: Run new test.
* testsuite/ld-elf/note1_1.s: New file: Source file for test.
* testsuite/ld-elf/note1_2.s: New file: Source file for test.
* testsuite/ld-elf/note1.r: New file: Expected readelf output.
Rather than just silencing the gcc-8 warnings, I decided to rewrite
the buffer handling in the two functions where gcc was warning.
The rest of the file could do with the same treatment.
* config/tc-score.c (s3_do_macro_bcmp): Don't use fixed size
buffers.
(s3_do_macro_bcmpz): Likewise.
This patch makes it possible to use an integer immediate with the fmov instructions
allowing you to simply write fmov d0, #2 instead of needing fmov d0, #2.0.
The parse double function already know to deal with this so we just need to list the
restriction put in place in parser.
The is considered a QoL improvement for hand assembly writers and allows more
code portability between assembler.
gas/
* config/tc-aarch64.c (parse_aarch64_imm_float): Remove restrictions.
* testsuite/gas/aarch64/diagnostic.s: Move fmov int test to..
* testsuite/gas/aarch64/fpmov.s: Here.
* testsuite/gas/aarch64/fpmov.d: Update results with fmov.
* testsuite/gas/aarch64/diagnostic.l: Remove fmov values.
* testsuite/gas/aarch64/sve-invalid.s: Update test files.
* testsuite/gas/aarch64/sve-invalid.l: Likewise
This patch fixes the case where you want to use an integer value the
floating point immediate to a VFP vmov instruction such as
vmovmi.f32 s27, #11.
If the immediate is not a float we convert it and copy it's representation
into the imm field and then carry on validating as if we originally entered
a floating point immediate.
The is considered a QoL improvement for hand assembly writers and allows more
code portability between assembler.
gas/
* gas/config/tc-arm.c (do_neon_mov): Allow integer literal for float
immediate.
* testsuite/gas/arm/vfp-mov-enc.s: New.
* testsuite/gas/arm/vfp-mov-enc.d: New.
Not all literals need to be moved in the presence of
--text-section-literals or --auto-litpools, but only those created by
.literal pseudo op or generated as a result of relaxation. Attempts to
move other literals may result in abnormal termination of the assembler
due to the following assertion failure:
Internal error in xg_find_litpool at gas/config/tc-xtensa.c:11209.
The same assertion may also be triggered by attempting to assign literal
pools to literals in .init and .fini sections; don't try to do that.
gas/
2018-05-09 Max Filippov <jcmvbkbc@gmail.com>
* config/tc-xtensa.c (xtensa_is_init_fini): New function.
(xtensa_move_literals): Only attempt to assign literal pool to
literals with tc_frag_data.is_literal mark and not in .init or
.fini sections.
Join nested 'if' conditions to simplify function structure.
(xtensa_switch_to_non_abs_literal_fragment): Use
xtensa_is_init_fini to test for .init/.fini sections.
* testsuite/gas/xtensa/all.exp (auto-litpools-3)
(auto-litpools-4, text-section-literals-1): New tests.
* testsuite/gas/xtensa/auto-litpools-3.d: New test results.
* testsuite/gas/xtensa/auto-litpools-3.s: New test source.
* testsuite/gas/xtensa/auto-litpools-4.d: New test results.
* testsuite/gas/xtensa/auto-litpools-4.s: New test source.
* testsuite/gas/xtensa/text-section-literals-1.d: New test results.
* testsuite/gas/xtensa/text-section-literals-1.s: New test source.
My original implementation for LDI32 pseudo does not conform to
the TI ABI. I wrongly documented my TI PRU ELF object files inspection,
which got propagated into my binutils implementation.
Issue was exposed when running the GCC ABI testsuite against TI toolchain.
According to TI ABI, LDI32 must use first LDI instruction to load
the MSB 16bits, and second LDI instruction for the LSB 16bits.
This patch will break binary compatibility with previously released
binutils versions for PRU. Still, I think it is better to fix
binutils to conform to the chip vendor ABI.
bfd * elf32-pru.c (pru_elf32_do_ldi32_relocate): Make LDI32 relocation
conformant to TI ABI.
(pru_elf32_relax_section): Likewise.
(pru_elf_relax_delete_bytes): Fix offsets for new LDI32 code.
* elf32-pru.c (pru_elf32_do_ldi32_relocate): Ignore addend.
(pru_elf32_pmem_relocate): Trap - should not get here.
(pru_elf32_relocate_section): Add support for REL relocations.
(elf_info_to_howto_rel): Enable REL.
(elf_backend_may_use_rel_p): Likewise.
(elf_backend_may_use_rela_p): Likewise.
(elf_backend_default_use_rela_p): Likewise.
gas * config/tc-pru.c (md_apply_fix): Make LDI32 relocation conformant
to TI ABI.
(pru_assemble_arg_i): Likewise.
(output_insn_ldi32): Likewise.
* testsuite/gas/pru/ldi.d: Update test for the now fixed LDI32.
* gas/config/tc-pru.c (pru_assemble_arg_b): Check imm8 operand range.
* gas/testsuite/gas/pru/illegal2.l: New test.
* gas/testsuite/gas/pru/illegal2.s: New test.
* gas/testsuite/gas/pru/pru.exp: Register new illegal2 test.
ld * scripttempl/pru.sc: Add LD sections to allow linking TI
toolchain object files.
* scripttempl/pru.sc: Switch to init_array.
* testsuite/ld-pru/ldi32.d: Update LDI32 test to conform to TI ABI.
* testsuite/ld-pru/norelax_ldi32-data.d: Likewise.
* testsuite/ld-pru/norelax_ldi32-dis.d: Likewise.
* testsuite/ld-pru/relax_ldi32-data.d: Likewise.
* testsuite/ld-pru/relax_ldi32-dis.d: Likewise.
This patch replaces AddrPrefixOp0 with AddrPrefixOpReg to indicate that
the size of register operand is controlled by the address size prefix.
This will be used by Intel MOVDIRI and MOVDIR64B instructions later.
gas/
* config/tc-i386.c (process_suffix): Check addrprefixopreg
instead of addrprefixop0.
opcodes/
* i386-gen.c (opcode_modifiers): Replace AddrPrefixOp0 with
AddrPrefixOpReg.
* i386-opc.h (AddrPrefixOp0): Renamed to ...
(AddrPrefixOpReg): This.
(i386_opcode_modifier): Rename addrprefixop0 to addrprefixopreg.
* i386-opc.tbl: Replace AddrPrefixOp0 with AddrPrefixOpReg.
This patch is aimed at silencing gcc8 -Wstringop-truncation warnings.
Unfortunately adding __attribute__ ((__nonstring)) doesn't work in a
number of the places patched here, (see
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=85643) so if you have
recent glibc headers installed you'll need to configure binutils with
--disable-werror to compile using gcc8 or gcc9.
include/
* ansidecl.h: Import from gcc.
* coff/internal.h (struct internal_scnhdr): Add ATTRIBUTE_NONSTRING
to s_name.
(struct internal_syment): Add ATTRIBUTE_NONSTRING to _n_name.
bfd/
* elf-linux-core.h (struct elf_external_linux_prpsinfo32_ugid32),
(struct elf_external_linux_prpsinfo32_ugid16),
(struct elf_external_linux_prpsinfo64_ugid32),
(struct elf_external_linux_prpsinfo64_ugid16): Add ATTRIBUTE_NONSTRING
to pr_fname and pr_psargs fields. Remove GCC diagnostic pragmas.
Move comment to..
* elf.c (elfcore_write_prpsinfo): ..here. Indent nested preprocessor
directives.
* elf32-arm.c (elf32_arm_nabi_write_core_note): Add ATTRIBUTE_NONSTRING
to data.
* elf32-ppc.c (ppc_elf_write_core_note): Likewise.
* elf32-s390.c (elf_s390_write_core_note): Likewise.
* elf64-s390.c (elf_s390_write_core_note): Likewise.
* elfxx-aarch64.c (_bfd_aarch64_elf_write_core_note): Likewise.
* elf64-x86-64.c (elf_x86_64_write_core_note): Add GCC diagnostic
pragmas.
* peXXigen.c (_bfd_XXi_swap_scnhdr_out): Use strnlen to avoid
false positive gcc-8 warning.
gas/
* config/obj-evax.c (shorten_identifier): Use memcpy in place
of strncpy.
* config/obj-macho.c (obj_mach_o_make_or_get_sect): Ensure
segname and sectname fields are NUL terminated.
Implement a more complex way of selecting targets to include or exclude
with `run_dump_test' cases, by extending the syntax for the `target',
`not-target', `skip' and `not-skip' options (with the binutils and GAS
test suites) and the `target', `alltargets' and `notarget' options (with
the LD test suite) to also accept a name of a TCL procedure instead of a
target triplet glob matching expression. The result, 1 or 0, of the
procedure determines whether the test is to be run or not. This mimics
and expands `dg-require-effective-target' from the GCC test suite.
Names of TCL procedures are supplied in square brackets `[]' as with TCL
procedure calls, observing that target triplet glob matching expressions
do not normally start and end with matching square brackets both at a
time. Arguments for procedures are allowed if required.
Having a way to specify a complex condition for a `run_dump_test' case
to run has the advantage of keeping it local within the test case itself
where tool options related to the check might be also present, removing
the need to wrap `run_dump_test' calls into an `if' block whose only
reason is to do a feature check, and ultimately lets one have the test
reported as UNSUPPORTED automagically if required (not currently
supported by the `run_dump_test' options used for LD).
binutils/
* testsuite/lib/binutils-common.exp (match_target): New procedure.
* testsuite/lib/utils-lib.exp (run_dump_test): Use it in place
of `istarget' for matching with `target', `not-target', `skip'
and `not-skip' options.
gas/
* testsuite/lib/gas-defs.exp (run_dump_test): Use `match_target'
in place of `istarget' for matching with `target', `not-target',
`skip' and `not-skip' options.
ld/
* testsuite/lib/ld-lib.exp (run_dump_test): Use `match_target'
in place of `istarget' for matching with `target', `alltargets'
and `notarget' options.
gas * as.c (flag_generate_build_notes): New variable.
(show_usage): Add entry for --generate-missing-build-notes.
(parse_args): Parse --generate-missing-build-notes.
* as.h: Export flag_generate_build_notes.
* symbols.c (save_symbol_name): Ensure that the name parameter is
not NULL.
* write.c (create_obj_attrs_section): Reformat.
(create_note_reloc): New function - creates a relocation for a
field in a GNU Build attribute note.
(maybe_generate_build_notes): New function - created GNU Build
attribute notes if none are present in the output file.
(write_object_file): Call maybe_generate_build_notes.
* configure.ac (--enable-generate-build-notes): New option.
* NEWS: Announce the new feature.
* doc/as.textinfo: Document the new option.
* config.in: Regenerate.
* configure: Regenerate.
binutils* readelf.c (is_32bit_abs_reloc): Support R_PARISC_DIR32 as a
32-bit absolute reloc for the HPPA target.
* testsuite/binutils-all/note-5.d: New test.
* testsuite/binutils-all/note-5.s: Source file for new test.
* testsuite/binutils-all/objcopy.exp: Run new test.
There's little point carrying up to three templates per insn flavor
when the sole difference is operand size and the dependency on AVX512VL
being enabled. Instead the need for AVX512VL can be derived from an
operand allowing for ZMMword as well as one or both or XMMword and
YMMword (irrespective of whether this is a register or memory operand).
Without further abstraction to deal with the different Disp8MemShift
values between the templates, only a limited set (mostly ones only
allowing for non-memory operands) can be folded, which is being done
here.
Also drop IgnoreSize wherever possible from anything that's being
touched anyway.
When zeroing an element of a register it doesn't matter whether the zero
results from the actual operation (xor, sub, or nand) or from the
zeroing-masking taking effect due to a clear mask register bit.
Pseudo prefixes are supposed to be a hint only - when the specific
encoding can't be used to encode an insn, silently override it. But
this overriding must only happen after the respective check, to
avoid forcing EVEX encoding because of something that isn't a valid
register name in the given context.
All of AVX, LWP, MPX, and PKU require XSAVE, and hence it as well as
XRSTOR should be enabled when enabling these ISA extensions. Leverage
these implications to shorten some of the cpu_flag_init[] entries.
It's not clear to me why they had been introduced - the respective
comments in opcodes/i386-gen.c are certainly wrong: ymm<N> registers
are very well supported (and necessary) with just AVX512F.
Scott Egerton
Maciej W. Rozycki
kyrtka01
Egeyar Bagcioglu
Tamar Christina
Sameera Deshpande
Alan Modra
Max Filippov
H.J. Lu
Alexandre Oliva
Jan Beulich
Amit Pawar
Jim Wilson
Peter Bergner
John Darrington
Nick Clifton
Dimitar Dimitrov
Igor Tsimbalist