Commit Graph

214 Commits

Author SHA1 Message Date
Yao Qi
6394c60699 Don't use print_insn_XXX in GDB
This is a follow-up to

  [PATCH 0/6] Unify the disassembler selection in gdb and objdump
  https://sourceware.org/ml/binutils/2017-05/msg00192.html

that is, opcodes is able to select the right disassembler, so gdb
doesn't have to select them.  Instead, gdb can just use
default_print_insn.  As a result, these print_insn_XXX are not used
out of opcodes, so this patch also moves their declarations from
include/dis-asm.h to opcodes/disassemble.h.  With this change,
GDB doesn't use any print_insn_XXX directly any more.

gdb:

2017-06-14  Yao Qi  <yao.qi@linaro.org>

	* aarch64-tdep.c (aarch64_gdb_print_insn): Call
	default_print_insn instead of print_insn_aarch64.
	* arm-tdep.c (gdb_print_insn_arm): Call
	default_print_insn instead of print_insn_big_arm
	and print_insn_little_arm.
	* i386-tdep.c (i386_print_insn): Call default_print_insn
	instead of print_insn_i386.
	* ia64-tdep.c (ia64_print_insn): Call
	default_print_insn instead of print_insn_ia64.
	* mips-tdep.c (gdb_print_insn_mips): Call
	default_print_insn instead of print_insn_big_mips
	and print_insn_little_mips.
	* spu-tdep.c (gdb_print_insn_spu): Call default_print_insn
	instead of print_insn_spu.

include:

2017-06-14  Yao Qi  <yao.qi@linaro.org>

	* dis-asm.h (print_insn_aarch64): Move it to opcodes/disassemble.h.
	(print_insn_big_arm, print_insn_big_mips): Likewise.
	(print_insn_i386, print_insn_ia64): Likewise.
	(print_insn_little_arm, print_insn_little_mips): Likewise.
	(print_insn_spu): Likewise.

opcodes:

2017-06-14  Yao Qi  <yao.qi@linaro.org>

	* aarch64-dis.c: Include disassemble.h instead of dis-asm.h.
	* arm-dis.c: Likewise.
	* ia64-dis.c: Likewise.
	* mips-dis.c: Likewise.
	* spu-dis.c: Likewise.
	* disassemble.h (print_insn_aarch64): New declaration, moved from
	include/dis-asm.h.
	(print_insn_big_arm, print_insn_big_mips): Likewise.
	(print_insn_i386, print_insn_ia64): Likewise.
	(print_insn_little_arm, print_insn_little_mips): Likewise.
2017-06-14 16:29:01 +01:00
Andre Vieira
05c966f3c9 [opcodes][arm] Remove bogus entry added by accident in former patch
2017-07-14  Andre Vieira  <andre.simoesdiasvieira@arm.com>

	* arm-dis.c (print_insn_arm): Remove bogus entry for bx.
2017-06-14 10:52:40 +01:00
Bernd Edlinger
fe50e98c9a Fix value in comment of disassembled ARM type A opcodes.
* arm-dis.c (print_insn_thumb32): Fix value_in_comment.
2017-05-02 10:28:09 +01:00
Pedro Alves
f995bbe8e6 -Wwrite-strings: Constify struct disassemble_info's disassembler_options field
The memory disassemble_info::disassembler_options points to is always
owned by the client.  I.e., that field is an non-owning, observing
pointer.  Thus const makes sense.

Are the include/ and opcodes/ bits OK?

Tested on x86_64 Fedora 23, built with --enable-targets=all.

include/ChangeLog:
2017-04-05  Pedro Alves  <palves@redhat.com>

	* dis-asm.h (disassemble_info) <disassembler_options>: Now a
	"const char *".
	(next_disassembler_option): Constify.

opcodes/ChangeLog:
2017-04-05  Pedro Alves  <palves@redhat.com>

	* arc-dis.c (parse_option, parse_disassembler_options): Constify.
	* arm-dis.c (parse_arm_disassembler_options): Constify.
	* ppc-dis.c (powerpc_init_dialect): Constify local.
	* vax-dis.c (parse_disassembler_options): Constify.

gdb/ChangeLog:
2017-04-05  Pedro Alves  <palves@redhat.com>

	* arm-tdep.c (show_disassembly_style_sfunc): Constify local.
	* disasm.c (set_disassembler_options): Constify local.
	* i386-tdep.c (i386_print_insn): Remove cast and FIXME comment.
2017-04-05 19:21:33 +01:00
Peter Bergner
65b48a8140 GDB: Add support for the new set/show disassembler-options commands.
This commit adds support to GDB so that it can modify the disassembler-options
value that is passed to the disassembler, similar to objdump's -M option.
Currently, the only supported targets are ARM, PowerPC and S/390, but
adding support for a new target(s) is not difficult.

include/
	* dis-asm.h (disasm_options_t): New typedef.
	(parse_arm_disassembler_option): Remove prototype.
	(set_arm_regname_option): Likewise.
	(get_arm_regnames): Likewise.
	(get_arm_regname_num_options): Likewise.
	(disassemble_init_s390): New prototype.
	(disassembler_options_powerpc): Likewise.
	(disassembler_options_arm): Likewise.
	(disassembler_options_s390): Likewise.
	(remove_whitespace_and_extra_commas): Likewise.
	(disassembler_options_cmp): Likewise.
	(next_disassembler_option): New inline function.
	(FOR_EACH_DISASSEMBLER_OPTION): New macro.

opcodes/
	* disassemble.c Include "safe-ctype.h".
	(disassemble_init_for_target): Handle s390 init.
	(remove_whitespace_and_extra_commas): New function.
	(disassembler_options_cmp): Likewise.
	* arm-dis.c: Include "libiberty.h".
	(NUM_ELEM): Delete.
	(regnames): Use long disassembler style names.
	Add force-thumb and no-force-thumb options.
	(NUM_ARM_REGNAMES): Rename from this...
	(NUM_ARM_OPTIONS): ...to this.  Use ARRAY_SIZE.
	(get_arm_regname_num_options): Delete.
	(set_arm_regname_option): Likewise.
	(get_arm_regnames): Likewise.
	(parse_disassembler_options): Likewise.
	(parse_arm_disassembler_option): Rename from this...
	(parse_arm_disassembler_options): ...to this.  Make static.
	Use new FOR_EACH_DISASSEMBLER_OPTION macro to scan over options.
	(print_insn): Use parse_arm_disassembler_options.
	(disassembler_options_arm): New function.
	(print_arm_disassembler_options): Handle updated regnames.
	* ppc-dis.c: Include "libiberty.h".
	(ppc_opts): Add "32" and "64" entries.
	(ppc_parse_cpu): Use ARRAY_SIZE and disassembler_options_cmp.
	(powerpc_init_dialect): Add break to switch statement.
	Use new FOR_EACH_DISASSEMBLER_OPTION macro.
	(disassembler_options_powerpc): New function.
	(print_ppc_disassembler_options): Use ARRAY_SIZE.
	Remove printing of "32" and "64".
	* s390-dis.c: Include "libiberty.h".
	(init_flag): Remove unneeded variable.
	(struct s390_options_t): New structure type.
	(options): New structure.
	(init_disasm): Rename from this...
	(disassemble_init_s390): ...to this.  Add initializations for
	current_arch_mask and option_use_insn_len_bits_p.  Remove init_flag.
	(print_insn_s390): Delete call to init_disasm.
	(disassembler_options_s390): New function.
	(print_s390_disassembler_options): Print using information from
	struct 'options'.
	* po/opcodes.pot: Regenerate.

binutils/
	* objdump.c (main): Use remove_whitespace_and_extra_commas.

gdb/
	* NEWS: Mention new set/show disassembler-options commands.
	* doc/gdb.texinfo: Document new set/show disassembler-options commands.
	* disasm.c: Include "arch-utils.h", "gdbcmd.h" and "safe-ctype.h".
	(prospective_options): New static variable.
	(gdb_disassembler::gdb_disassembler): Initialize
	m_di.disassembler_options.
	(gdb_buffered_insn_length_init_dis): Initilize di->disassembler_options.
	(get_disassembler_options): New function.
	(set_disassembler_options): Likewise.
	(set_disassembler_options_sfunc): Likewise.
	(show_disassembler_options_sfunc): Likewise.
	(disassembler_options_completer): Likewise.
	(_initialize_disasm): Likewise.
	* disasm.h (get_disassembler_options): New prototype.
	(set_disassembler_options): Likewise.
	* gdbarch.sh (gdbarch_disassembler_options): New variable.
	(gdbarch_verify_disassembler_options): Likewise.
	* gdbarch.c: Regenerate.
	* gdbarch.h: Likewise.
	* arm-tdep.c (num_disassembly_options): Delete.
	(set_disassembly_style): Likewise.
	(arm_disassembler_options): New static variable.
	(set_disassembly_style_sfunc): Convert short style name into long
	option name.  Call set_disassembler_options.
	(show_disassembly_style_sfunc): New function.
	(arm_gdbarch_init): Call set_gdbarch_disassembler_options and
	set_gdbarch_verify_disassembler_options.
	(_initialize_arm_tdep): Delete regnames variable and update callers.
	(arm_disassembler_options): Initialize.
	(disasm_options): New variable.
	(num_disassembly_options): Rename from this...
	(num_disassembly_styles): ...to this.  Compute by scanning through
	disasm_options.
	(valid_disassembly_styles): Initialize using disasm_options.
	Remove calls to parse_arm_disassembler_option, get_arm_regnames and
	set_arm_regname_option.
	Pass show_disassembly_style_sfunc to the "disassembler" setshow command.
	* rs6000-tdep.c (powerpc_disassembler_options): New static variable.
	(rs6000_gdbarch_init): Call set_gdbarch_disassembler_options and
	set_gdbarch_verify_disassembler_options.
	* s390-tdep.c (s390_disassembler_options): New static variable.
	(s390_gdbarch_init):all set_gdbarch_disassembler_options and
	set_gdbarch_verify_disassembler_options.

gdb/testsuite/
	* gdb.arch/powerpc-power.exp: Delete test.
	* gdb.arch/powerpc-power.s: Likewise.
	* gdb.disasm/disassembler-options.exp: New test.
	* gdb.arch/powerpc-altivec.exp: Likewise.
	* gdb.arch/powerpc-altivec.s: Likewise.
	* gdb.arch/powerpc-altivec2.exp: Likewise.
	* gdb.arch/powerpc-altivec2.s: Likewise.
	* gdb.arch/powerpc-altivec3.exp: Likewise.
	* gdb.arch/powerpc-altivec3.s: Likewise.
	* gdb.arch/powerpc-power7.exp: Likewise.
	* gdb.arch/powerpc-power7.s: Likewise.
	* gdb.arch/powerpc-power8.exp: Likewise.
	* gdb.arch/powerpc-power8.s: Likewise.
	* gdb.arch/powerpc-power9.exp: Likewise.
	* gdb.arch/powerpc-power9.s: Likewise.
	* gdb.arch/powerpc-vsx.exp: Likewise.
	* gdb.arch/powerpc-vsx.s: Likewise.
	* gdb.arch/powerpc-vsx2.exp: Likewise.
	* gdb.arch/powerpc-vsx2.s: Likewise.
	* gdb.arch/powerpc-vsx3.exp: Likewise.
	* gdb.arch/powerpc-vsx3.s: Likewise.
	* gdb.arch/arm-disassembler-options.exp: Likewise.
	* gdb.arch/powerpc-disassembler-options.exp: Likewise.
	* gdb.arch/s390-disassembler-options.exp: Likewise.
2017-02-28 12:32:07 -06:00
Szabolcs Nagy
c13a63b046 [ARM] Fix the decoding of indexed element VCMLA instruction
Bit 24 of the indexed element vcmla decode mask was incorrectly
left unset.  This could cause incorrect disassembly of some
currently undefined instructions as vcmla.

Rotatation immediates were not printed correctly in the disassembly
(could print 170 and 280 instead of 180 and 270).

opcodes/
	* arm-dis.c (coprocessor_opcodes): Fix vcmla mask and disassembly.

gas/
	* testsuite/gas/arm/armv8_3-a-simd.s: Add vcmla tests.
	* testsuite/gas/arm/armv8_3-a-simd.d: Update.
2017-01-18 17:08:34 +00:00
Alan Modra
2571583aed Update year range in copyright notice of all files. 2017-01-02 14:08:56 +10:30
Nick Clifton
db7b55faa1 Fix compile time warning building arm-dis.c 2016-12-16 10:59:36 +00:00
Szabolcs Nagy
c28eeff2ea [ARM] Add ARMv8.3 VCMLA and VCADD instructions
Add support for VCMLA and VCADD advanced SIMD complex number instructions.

The command line option is -march=armv8.3-a+fp16+simd for enabling all
instructions.

In arm-dis.c the formatting syntax was abused a bit to select between
0 vs 90 or 180 vs 270 or 90 vs 270 based on a bit value instead of
duplicating entries in the opcode table.

gas/
	* config/tc-arm.c (do_vcmla, do_vcadd): Define.
	(neon_scalar_for_vcmla): Define.
	(enum operand_parse_code): Add OP_IROT1 and OP_IROT2.
	(NEON_ENC_TAB): Add DDSI and QQSI variants.
	(insns): Add vcmla and vcadd.
	* testsuite/gas/arm/armv8_3-a-simd.d: New.
	* testsuite/gas/arm/armv8_3-a-simd.s: New.
	* testsuite/gas/arm/armv8_3-a-simd-bad.d: New.
	* testsuite/gas/arm/armv8_3-a-simd-bad.l: New.
	* testsuite/gas/arm/armv8_3-a-simd-bad.s: New.

opcodes/
	* arm-dis.c (coprocessor_opcodes): Add vcmla and vcadd.
	(print_insn_coprocessor): Add 'V' format for neon D or Q regs.
2016-12-05 14:24:17 +00:00
Szabolcs Nagy
49e8a72582 [ARM] Add ARMv8.3 VJCVT instruction
Add support for VJCVT javascript conversion instruction.

gas/
	* config/tc-arm.c (arm_ext_v8_3, do_vjcvt): Define.
	(insns): Add vjcvt.
	* testsuite/gas/aarch64/armv8_3-a-fp.s: New.
	* testsuite/gas/aarch64/armv8_3-a-fp.d: New.
	* testsuite/gas/aarch64/armv8_3-a-fp-bad.s: New.
	* testsuite/gas/aarch64/armv8_3-a-fp-bad.d: New.
	* testsuite/gas/aarch64/armv8_3-a-fp-bad.l: New.

opcodes/
	* arm-dis.c (coprocessor_opcodes): Add vjcvt.
2016-12-05 14:13:27 +00:00
Alan Modra
1a0670f374 -Wimplicit-fallthrough warning fixes
Comment changes.

bfd/
	* coff-h8300.c: Spell fall through comments consistently.
	* coffgen.c: Likewise.
	* elf32-hppa.c: Likewise.
	* elf32-ppc.c: Likewise.
	* elf32-score.c: Likewise.
	* elf32-score7.c: Likewise.
	* elf64-ppc.c: Likewise.
	* elfxx-aarch64.c: Likewise.
	* elfxx-mips.c: Likewise.
	* cpu-ns32k.c: Add missing fall through comments.
	* elf-m10300.c: Likewise.
	* elf32-arm.c: Likewise.
	* elf32-avr.c: Likewise.
	* elf32-bfin.c: Likewise.
	* elf32-frv.c: Likewise.
	* elf32-i386.c: Likewise.
	* elf32-microblaze.c: Likewise.
	* elf32-nds32.c: Likewise.
	* elf32-ppc.c: Likewise.
	* elf32-rl78.c: Likewise.
	* elf32-rx.c: Likewise.
	* elf32-s390.c: Likewise.
	* elf32-sh.c: Likewise.
	* elf32-tic6x.c: Likewise.
	* elf64-ia64-vms.c: Likewise.
	* elf64-ppc.c: Likewise.
	* elf64-s390.c: Likewise.
	* elf64-x86-64.c: Likewise.
	* elflink.c: Likewise.
	* elfnn-aarch64.c: Likewise.
	* elfnn-ia64.c: Likewise.
	* ieee.c: Likewise.
	* oasys.c: Likewise.
	* pdp11.c: Likewise.
	* srec.c: Likewise.
	* versados.c: Likewise.
opcodes/
	* aarch64-opc.c: Spell fall through comments consistently.
	* i386-dis.c: Likewise.
	* aarch64-dis.c: Add missing fall through comments.
	* aarch64-opc.c: Likewise.
	* arc-dis.c: Likewise.
	* arm-dis.c: Likewise.
	* i386-dis.c: Likewise.
	* m68k-dis.c: Likewise.
	* mep-asm.c: Likewise.
	* ns32k-dis.c: Likewise.
	* sh-dis.c: Likewise.
	* tic4x-dis.c: Likewise.
	* tic6x-dis.c: Likewise.
	* vax-dis.c: Likewise.
binutils/
	* dlltool.c: Spell fall through comments consistently.
	* objcopy.c: Likewise.
	* readelf.c: Likewise.
	* dwarf.c: Add missing fall through comments.
	* elfcomm.c: Likewise.
	* sysinfo.y: Likewise.
	* readelf.c: Likewise.  Also remove extraneous comments.
gas/
	* app.c: Add missing fall through comments.
	* dw2gencfi.c: Likewise.
	* expr.c: Likewise.
	* config/tc-alpha.c: Likewise.
	* config/tc-arc.c: Likewise.
	* config/tc-arm.c: Likewise.
	* config/tc-cr16.c: Likewise.
	* config/tc-crx.c: Likewise.
	* config/tc-dlx.c: Likewise.
	* config/tc-h8300.c: Likewise.
	* config/tc-hppa.c: Likewise.
	* config/tc-i370.c: Likewise.
	* config/tc-i386.c: Likewise.
	* config/tc-i960.c: Likewise.
	* config/tc-ia64.c: Likewise.
	* config/tc-m68hc11.c: Likewise.
	* config/tc-m68k.c: Likewise.
	* config/tc-mep.c: Likewise.
	* config/tc-metag.c: Likewise.
	* config/tc-microblaze.c: Likewise.
	* config/tc-mips.c: Likewise.
	* config/tc-ns32k.c: Likewise.
	* config/tc-rx.c: Likewise.
	* config/tc-score.c: Likewise.
	* config/tc-score7.c: Likewise.
	* config/tc-sh.c: Likewise.
	* config/tc-tic4x.c: Likewise.
	* config/tc-vax.c: Likewise.
	* config/tc-xstormy16.c: Likewise.
	* config/tc-z80.c: Likewise.
	* config/tc-z8k.c: Likewise.
	* config/obj-elf.c: Likewise.
	* config/tc-i386.c: Likewise.
	* depend.c: Spell fall through comments consistently.
	* config/tc-arm.c: Likewise.
	* config/tc-d10v.c: Likewise.
	* config/tc-i960.c: Likewise.
	* config/tc-ia64.c: Likewise.
	* config/tc-m68k.c: Likewise.
	* config/tc-mcore.c: Likewise.
	* config/tc-mep.c: Likewise.
	* config/tc-ns32k.c: Likewise.
	* config/tc-visium.c: Likewise.
	* config/tc-xstormy16.c: Likewise.
	* config/tc-z8k.c: Likewise.
gprof/
	* gprof.c: Add missing fall through comments.
ld/
	* lexsup.c: Spell fall through comments consistently and add
	missing fall through comments.
2016-10-06 10:13:15 +10:30
Thomas Preud'homme
1a336194b7 Add missing ARMv8-M special registers
2016-08-26  Thomas Preud'homme  <thomas.preudhomme@arm.com>

gas/
	* config/tc-arm.c (v7m_psrs): Add MSPLIM, PSPLIM, MSPLIM_NS,
	PSPLIM_NS, PRIMASK_NS, BASEPRI_NS, FAULTMASK_NS, CONTROL_NS, SP_NS and
	their lowecase counterpart special registers.  Write register
	identifier in hex.
	* testsuite/gas/arm/archv8m-cmse-msr.s: Reorganize tests per
	operation, special register and then case.  Use different register for
	each operation.  Add tests for new special registers.
	* testsuite/gas/arm/archv8m-cmse-msr-base.d: Adapt expected result
	accordingly.
	* testsuite/gas/arm/archv8m-cmse-msr-main.d: Likewise.
	* testsuite/gas/arm/archv8m-main-dsp-4.d: Likewise.

opcodes/
	* arm-dis.c (psr_name): Use hex as case labels.  Add detection for
	MSPLIM, PSPLIM, MSPLIM_NS, PSPLIM_NS, PRIMASK_NS, BASEPRI_NS,
	FAULTMASK_NS, CONTROL_NS and SP_NS special registers.
2016-08-26 11:53:30 +01:00
Yao Qi
838441e4a2 Fix typo in comment
This patch fixes the typo "uf" in the comment.  I'll push it in as the
change is obvious.

2016-06-30  Yao Qi  <yao.qi@linaro.org>

	* arm-dis.c (print_insn): Fix typo in comment.
2016-06-30 16:03:07 +01:00
Matthew Wahab
4d1464f294 [ARM] Add command line option for RAS extension.
This patch adds the architecture extension "+ras" to enable RAS
support. It is enabled by default for -march=armv8.2-a and available but
disabled by default for armv8-a and armv8.1-a.

gas/
	* config/tc-arm.c (arm_ext_v8_2): Rename to arm_ext_ras.
	(arm_ext_ras): Renamed from arm_ext_v8_2.
	(insns): Update for arm_ext_v8_2 renaming.
	(arm_extensions): Add "ras".
	* doc/c-arm.texi (ARM Options): Add an entry for "ras".
	* testsuite/gas/arm/armv8-a+ras.d: New.
	* testsuite/gas/arm/armv8_2-a.d: Add explicit command line
	options.

include/
	* opcode/arm.h (ARM_EXT2_RAS): New.  Also align preceding
	entries.
	(ARM_AEXT_V8_2A): Add ARM_EXT2_RAS.

opcodes/
	* arm-dis.c (arm_opcodes): Replace ARM_EXT_V8_2A with
	ARM_EXT_RAS in relevant entries.
2016-06-07 09:56:42 +01:00
Thomas Preud'homme
39d911fc3c Use getters/setters to access ARM branch type
2016-05-10  Thomas Preud'homme  <thomas.preudhomme@arm.com>

bfd/
	* elf32-arm.c (elf32_arm_size_stubs): Use new macros
	ARM_GET_SYM_BRANCH_TYPE and ARM_SET_SYM_BRANCH_TYPE to respectively get
	and set branch type of a symbol.
	(bfd_elf32_arm_process_before_allocation): Likewise.
	(elf32_arm_relocate_section): Likewise and fix identation along the
	way.
	(allocate_dynrelocs_for_symbol): Likewise.
	(elf32_arm_finish_dynamic_symbol): Likewise.
	(elf32_arm_swap_symbol_in): Likewise.
	(elf32_arm_swap_symbol_out): Likewise.

gas/
	* config/tc-arm.c (arm_adjust_symtab): Use ARM_SET_SYM_BRANCH_TYPE to
	set branch type of a symbol.

gdb/
	* arm-tdep.c (arm_elf_make_msymbol_special): Use
	ARM_GET_SYM_BRANCH_TYPE to get branch type of a symbol.

include/
	* arm.h (enum arm_st_branch_type): Add new ST_BRANCH_ENUM_SIZE
	enumerator.
	(NUM_ENUM_ARM_ST_BRANCH_TYPE_BITS): New macro.
	(ENUM_ARM_ST_BRANCH_TYPE_BITMASK): Likewise.
	(ARM_SYM_BRANCH_TYPE): Replace by ...
	(ARM_GET_SYM_BRANCH_TYPE): This and ...
	(ARM_SET_SYM_BRANCH_TYPE): This in two versions depending on whether
	BFD_ASSERT is defined or not.

ld/
	* emultempl/armelf.em (gld${EMULATION_NAME}_finish): Use
	ARM_GET_SYM_BRANCH_TYPE to get branch type of a symbol.

opcodes/
	* arm-dis.c (get_sym_code_type): Use ARM_GET_SYM_BRANCH_TYPE to get
	branch type of a symbol.
	(print_insn): Likewise.
2016-05-10 16:17:04 +01:00
Thomas Preud'homme
16a1fa25be Add support for ARMv8-M security extensions instructions
2016-05-10  Thomas Preud'homme  <thomas.preudhomme@arm.com>

gas/
	* config/tc-arm.c (arm_ext_m): Add feature bit ARM_EXT2_V8M_MAIN.
	(arm_ext_v8m_main): New feature set for bit ARM_EXT2_V8M_MAIN.
	(arm_ext_v8m_m_only): New feature set for instructions in ARMv8-M not
	shared with a non M profile architecture.
	(do_rn): New function.
	(known_t32_only_insn): Check opcode against arm_ext_v8m_m_only rather
	than arm_ext_v8m.
	(v7m_psrs): Add ARMv8-M security extensions new special registers.
	(insns): Add ARMv8-M Security Extensions instructions.
	(aeabi_set_public_attributes): Use arm_ext_v8m_m_only instead of
	arm_ext_v8m_m to decide the profile and the Thumb ISA.
	* testsuite/gas/arm/archv8m-cmse.s: New file.
	* testsuite/gas/arm/archv8m-cmse-main.s: Likewise..
	* testsuite/gas/arm/archv8m-cmse-msr.s: Likewise.
	* testsuite/gas/arm/any-cmse.d: Likewise.
	* testsuite/gas/arm/any-cmse-main.d: Likewise.
	* testsuite/gas/arm/archv8m-cmse-base.d: Likewise.
	* testsuite/gas/arm/archv8m-cmse-msr-base.d: Likewise.
	* testsuite/gas/arm/archv8m-cmse-main-1.d: Likewise.
	* testsuite/gas/arm/archv8m-cmse-main-2.d: Likewise.
	* testsuite/gas/arm/archv8m-cmse-msr-main.d: Likewise.

include/
	* opcode/arm.h (ARM_EXT2_V8M_MAIN): new feature bit.
	(ARM_AEXT2_V8M_MAIN): New architecture extension feature set.
	(ARM_ARCH_V8M_MAIN): Use ARM_AEXT2_V8M_MAIN instead of ARM_AEXT2_V8M
	for the high core bits.

opcodes/
	* arm-dis.c (coprocessor_opcodes): Add entries for VFP ARMv8-M
	Mainline Security Extensions instructions.
	(thumb_opcodes): Add entries for narrow ARMv8-M Security
	Extensions instructions.
	(thumb32_opcodes): Add entries for wide ARMv8-M Security Extensions
	instructions.
	(psr_name): Add new MSP_NS and PSP_NS ARMv8-M Security Extensions
	special registers.
2016-05-10 15:03:38 +01:00
Jiong Wang
589a7d8830 [ARM] Add ARMv8.2 FP16 vmul/vmla/vmls (by scalar)
gas/
  * config/tc-arm.c (do_neon_mac_maybe_scalar): Allow F16.
  * testsuite/gas/arm/armv8-2-fp16-simd.s: New tests.
  * testsuite/gas/arm/armv8-2-fp16-simd.d: New expected results.
  * testsuite/gas/arm/armv8-2-fp16-simd-thum.d: Likewise for Thumb.
  * testsuite/gas/arm/armv8-2-fp16-simd-warning.l: New warning results.
  * testsuite/gas/arm/simd_by_scalar_low_regbank.s: New test source.
  * testsuite/gas/arm/simd_by_scalar_low_regbank.d: New testcase.
  * testsuite/gas/arm/simd_by_scalar_low_regbank_thumb.d: Likewise for Thumb.
  * testsuite/gas/arm/simd_by_scalar_low_regbank.l: New warning results.

opcodes/
  * arm-dis.c: Support FP16 vmul, vmla, vmls (by scalar).
2016-04-05 15:54:00 +01:00
Jiong Wang
cc93330137 [ARM] Support ARMv8.2 FP16 simd instructions
gas/
	* config/tc-arm.c (N_S_32): New.
	(N_F_16_32): Likewise.
	(N_SUF_32): Support N_F16.
	(N_IF_32): Likewise.
	(neon_dyadic_misc): Likewise.
	(do_neon_cmp): Likewise.
	(do_neon_cmp_inv): Likewise.
	(do_neon_mul): Likewise.
	(do_neon_fcmp_absolute): Likewise.
	(do_neon_step): Likewise.
	(do_neon_abs_neg): Likewise.
	(CVT_FLAVOR_VAR): Likewise.
	(do_neon_cvt_1): Likewise.
	(do_neon_recip_est): Likewise.
	(do_vmaxnm): Likewise.
	(do_vrint_1): Likewise.
	(neon_check_type): Check architecture support for FP16 extension.
	(insns): Update comments.
	* testsuite/gas/arm/armv8-2-fp16-simd.s: New test source.
	* testsuite/gas/arm/armv8-2-fp16-simd.d: New testcase for arm mode.
	* testsuite/gas/arm/armv8-2-fp16-simd-thumb.d: Likewise for thumb mode.
	* testsuite/gas/arm/armv8-2-fp16-simd-warning.d: New rejection test for
	arm mode.
	* testsuite/gas/arm/armv8-2-fp16-simd-warning-thumb.d: Likewise for
	thumb mode.
	* testsuite/gas/arm/armv8-2-fp16-simd-warning.l: New expected rejection
	error file.

opcode/
	* arm-dis.c (neon_opcodes): Support new FP16 instructions.
2016-03-16 16:11:59 +00:00
Renlin Li
b0c1177766 [OPCODES][ARM][1/3]Add armv8.2 fp16 instruction dissembler support.
opcodes/

2016-02-24  Renlin Li  <renlin.li@arm.com>

	* arm-dis.c (coprocessor_opcodes): Add fp16 instruction entries.
	(print_insn_coprocessor): Support fp16 instruction.

gas/

2016-02-24  Renlin Li  <renlin.li@arm.com>

	* testsuite/gas/arm/copro.d: Adjust output.
	* testsuite/gas/arm/copro.s: Adjust co-processor num.
2016-02-24 14:08:39 +00:00
Renlin Li
3e309328e8 [OPCODES][ARM]Fix mask for a few coprocessor opcodes.
opcodes/

2016-02-24  Renlin Li  <renlin.li@arm.com>

	* arm-dis.c (coprocessor_opcodes): Fix mask for vsel, vmaxnm, vminnm,
	vrint(mpna).

gas/

2016-02-24  Renlin Li  <renlin.li@arm.com>

	* testsuite/gas/arm/mask_1.d: New.
	* testsuite/gas/arm/mask_1.s: New.
2016-02-24 14:02:51 +00:00
Renlin Li
8afc7bea40 [OPCODE][ARM]Correct disassembler for cdp/cdp2, mcr/mcr2, mrc/mrc2, ldc/ldc2, stc/stc2
opcodes/

2016-02-24  Renlin Li  <renlin.li@arm.com>

	* arm-dis.c (print_insn_coprocessor): Check co-processor number for
	cpd/cpd2, mcr/mcr2, mrc/mrc2, ldc/ldc2, stc/stc2.

gas/

2016-02-24  Renlin Li  <renlin.li@arm.com>

	* testsuite/gas/arm/copro.s: Use coprocessor other than 10, 11.
	* testsuite/gas/arm/copro.d: Update.
2016-02-24 14:02:51 +00:00
Renlin Li
5bc5ae8810 [PATCH[ARM]Check mapping symbol while backward searching for IT block.
opcodes/

	* arm-dis.c (mapping_symbol_for_insn): New function.
	(find_ifthen_state): Call mapping_symbol_for_insn().

gas/

	* testsuite/gas/arm/thumb2_it_search.d: New.
	* testsuite/gas/arm/thumb2_it_search.s: New.
2016-01-25 15:14:29 +00:00
Matthew Wahab
105bde5771 [ARM] Support ARMv8.2 RAS extension.
The ARMv8.2 architecture includes the RAS extension which adds an
instruction, ESB, and a number of coprocessor registers. This patch adds
the instruction to binutils, making it available when -march=armv8.2-a
is selected. It also adds tests for the instruction and for the
coprocessor registers.

gas/
2016-01-12  Matthew Wahab  <matthew.wahab@arm.com>

	* config/tc-arm.c (arm_ext_v8_2): New.
	(insns): Add "esb".
	* testsuite/gas/arm/armv8_2-a.d: New.
	* testsuite/gas/arm/armv8_2-a.s: New.

opcodes/
2016-01-12  Matthew Wahab  <matthew.wahab@arm.com>

	* arm-dis.c (arm_opcodes): Add "esb".
	(thumb_opcodes): Likewise.

Change-Id: I67f3d70789db78d1c66a56c4994675f99ac15e34
2016-01-12 16:41:07 +00:00
Alan Modra
6f2750feaf Copyright update for binutils 2016-01-01 23:00:01 +10:30
Thomas Preud'homme
ff8646eef8 Add assembler support for ARMv8-M Baseline
2015-12-24  Thomas Preud'homme  <thomas.preudhomme@arm.com>

bfd/
    (tag_cpu_arch_combine): Adjust comment in v4t_plus_v6_m with regards
    to merging with ARMv8-M Baseline.

binutils/
    * readelf.c (arm_attr_tag_CPU_arch): Add ARMv8-M Baseline Tag_CPU_arch
    value.

gas/
    * config/tc-arm.c (arm_ext_v6t2_v8m): New feature for instructions
    shared between ARMv6T2 and ARMv8-M.
    (move_or_literal_pool): Check mov.w/mvn and movw availability against
    arm_ext_v6t2 and arm_ext_v6t2_v8m respectively instead of checking
    arm_arch_t2.
    (do_t_branch): Error out for wide conditional branch instructions if
    targetting ARMv8-M Baseline.
    (non_v6t2_wide_only_insn): Add the logic for new wide-only instructions
    in ARMv8-M Baseline.
    (wide_insn_ok): New function.
    (md_assemble): Use wide_insn_ok instead of non_v6t2_wide_only_insn and
    adapt error message for unsupported wide instruction to ARMv8-M
    Baseline.
    (insns): Reorganize instructions shared by ARMv8-M Baseline and
    ARMv6t2 architecture.
    (arm_cpus): Set feature bit ARM_EXT2_V6T2_V8M for marvell-pj4 and
    marvell-whitney cores.
    (arm_archs): Define armv8-m.base architecture.
    (cpu_arch_ver): Define ARM_ARCH_V8M_BASE architecture version.
    (aeabi_set_public_attributes): Add logic to set Tag_CPU_arch to 17 for
    ARMv8-M Mainline.  Set Tag_DIV_use for ARMv8-M Baseline as well.

gas/testsuite/
    * gas/arm/archv8m-base.d: New file.
    * gas/arm/attr-march-armv8m.base.d: Likewise.
    * gas/arm/armv8m.base-idiv.d: Likewise.
    * gas/arm/any-armv8m.d: Adapt to deal with ARMv8-M Baseline.

include/elf/
    * arm.h (TAG_CPU_ARCH_V8M_BASE): Declare.

include/opcode/
    * arm.h (ARM_EXT2_V6T2_V8M): New extension bit.
    (ARM_AEXT2_V8A): New architecture extension bitfield.
    (ARM_AEXT2_V8_1A): Use ARM_AEXT2_V8A instead of ARM_EXT2_ATOMICS.
    (ARM_AEXT_V8M_BASE): New architecture extension bitfield.
    (ARM_AEXT2_V8M): Add extension bit ARM_EXT2_V6T2_V8M.
    (ARM_ARCH_V6T2): Use ARM_EXT2_V6T2_V8M for the second extension
    bitfield.
    (ARM_ARCH_V6KT2): Likewise.
    (ARM_ARCH_V6ZT2): Likewise.
    (ARM_ARCH_V6KZT2): Likewise.
    (ARM_ARCH_V7): Likewise.
    (ARM_ARCH_V7A): Likewise.
    (ARM_ARCH_V7VE): Likewise.
    (ARM_ARCH_V7R): Likewise.
    (ARM_ARCH_V7M): Likewise.
    (ARM_ARCH_V7EM): Likewise.
    (ARM_ARCH_V8A): Likewise.
    (ARM_ARCH_V8M_BASE): New architecture bitfield.
    (ARM_ARCH_THUMB2): Include instructions shared by ARMv6t2 and ARMv8-M.
    (ARM_ARCH_V7A_SEC): Use ARM_EXT2_V6T2_V8M for the second extension
    bitfield and reindent.
    (ARM_ARCH_V7A_MP_SEC): Likewise.
    (ARM_ARCH_V7R_IDIV): Likewise.
    (ARM_ARCH_V8A_FP): Use ARM_AEXT2_V8A instead of ARM_EXT2_ATOMICS.
    (ARM_ARCH_V8A_SIMD): Likewise.
    (ARM_ARCH_V8A_CRYPTOV1): Likewise.

opcodes/
    * arm-dis.c (arm_opcodes): Guard movw, movt cbz, cbnz, clrex, ldrex,
    ldrexb, ldrexh, strex, strexb, strexh shared by ARMv6T2 and ARMv8-M by
    ARM_EXT2_V6T2_V8M instead of ARM_EXT_V6T2.
2015-12-24 17:27:21 +08:00
Thomas Preud'homme
4ed7ed8db2 Add assembler support for ARMv8-M Mainline
2015-12-24  Thomas Preud'homme  <thomas.preudhomme@arm.com>

bfd/
    (tag_cpu_arch_combine): Adjust v4t_plus_v6_m and comb array to account
    for new TAG_CPU_ARCH_V4T_PLUS_V6_M value.  Deal with NULL values in
    comb array.

binutils/
    * readelf.c (arm_attr_tag_CPU_arch): Add ARMv8-M Mainline Tag_CPU_arch
    value.
    (arm_attr_tag_THUMB_ISA_use): Add ARMv8-M Mainline Tag_THUMB_ISA_use
    value.

gas/
    * config/tc-arm.c (arm_ext_m): Include ARMv8-M.
    (arm_ext_v8m): New feature for ARMv8-M.
    (arm_ext_atomics): New feature for ARMv8 atomics.
    (do_tt): New encoding function for TT* instructions.
    (insns): Add new entries for ARMv8-M specific instructions and
    reorganize the ones shared by ARMv8-M Mainline and ARMv8-A.
    (arm_archs): Define armv8-m.main architecture.
    (cpu_arch_ver): Define ARM_ARCH_V8M_MAIN architecture version and
    clarify the ordering rule.
    (aeabi_set_public_attributes): Use TAG_CPU_ARCH_* macro to refer to
    Tag_CPU_arch values for ARMv7e-M detection.  Add logic to keep setting
    Tag_CPU_arch to ARMv8-A for -march=all.  Also set Tag_CPU_arch_profile
    to 'A' if extension bit for atomic instructions is set, unless it is
    ARMv8-M.  Set Tag_THUMB_ISA_use to 3 for ARMv8-M.  Set Tag_DIV_use to 0
    for ARMv8-M Mainline.

gas/testsuite/
    * gas/arm/archv8m.s: New file.
    * gas/arm/archv8m-main.d: Likewise.
    * gas/arm/attr-march-armv8m.main.d: Likewise.
    * gas/arm/any-armv8m.s: Likewise.
    * gas/arm/any-armv8m.d: Likewise.

include/elf/
    * arm.h (TAG_CPU_ARCH_V8M_MAIN): Declare.
    (MAX_TAG_CPU_ARCH): Define to TAG_CPU_ARCH_V8M_MAIN.
    (TAG_CPU_ARCH_V4T_PLUS_V6_M): Define to unused value 15.

include/opcode/
    * arm.h (ARM_EXT2_ATOMICS): New extension bit.
    (ARM_EXT2_V8M): Likewise.
    (ARM_EXT_V8): Adjust comment with regards to atomics and remove
    mention of legacy use for that bit.
    (ARM_AEXT2_V8_1A): New architecture extension bitfield.
    (ARM_AEXT2_V8_2A): Likewise.
    (ARM_AEXT_V8M_MAIN): Likewise.
    (ARM_AEXT2_V8M): Likewise.
    (ARM_ARCH_V8A): Use ARM_EXT2_ATOMICS for features in second bitfield.
    (ARM_ARCH_V8_1A): Likewise with ARM_AEXT2_V8_1A.
    (ARM_ARCH_V8_2A): Likewise with ARM_AEXT2_V8_2A.
    (ARM_ARCH_V8M_MAIN): New architecture feature bitfield.
    (ARM_ARCH_V8A_FP): Use ARM_EXT2_ATOMICS for features in second bitfield
    and reindent.
    (ARM_ARCH_V8A_SIMD): Likewise.
    (ARM_ARCH_V8A_CRYPTOV1): Likewise.
    (ARM_ARCH_V8_1A_FP): Use ARM_AEXT2_V8_1A to set second bitfield of
    feature bits.
    (ARM_ARCH_V8_1A_SIMD): Likewise.
    (ARM_ARCH_V8_1A_CRYPTOV1): Likewise.

opcodes/
    * arm-dis.c (arm_opcodes): Guard lda, ldab, ldaex, ldaexb, ldaexh, stl,
    stlb, stlh, stlex, stlexb and stlexh by ARM_EXT2_ATOMICS instead of
    ARM_EXT_V8.
    (thumb32_opcodes): Add entries for wide ARMv8-M instructions.
2015-12-24 17:26:54 +08:00
Andre Vieira
3395762edd Fix ldah being disassembled as ldaexh
2015-12-02  Andre Vieira  <andre.simoesdiasvieira@arm.com>

opcodes/
    * arm-dis.c (arm_opcodes): <ldaexh>: Fix typo...
    <ldah>: ... to this.

gas/testsuite/
    * gas/arm/armv8-a.d: <ldaexh>: Rename mismatched mnemonics ...
    <ldah>: ... to this.
2015-12-02 09:26:58 +08:00
Tristan Gingold
e49d43ff73 opcodes: handle mach-o for thumb/arm disambiguation.
opcodes/
	* arm-dis.c (print_insn): Also set is_thumb for Mach-O.
2015-11-23 15:50:29 +01:00
Andre Vieira
4ab90a7a90 Fixes for unpredictable nops and 26-bit versions of teq,tst,cmn,cmp.
opcodes * arm-dis.c (print_insn_arm): Disassembling for all targets V6
	and higher with ARM instruction set will now mark the 26-bit
	versions of teq,tst,cmn and cmp as UNPREDICTABLE.
	(arm_opcodes): Fix for unpredictable nop being recognized as a teq.

test    * gas/arm/nops.d: New.
	* gas/arm/nops.s: New.
	* gas/arm/inst.d: Changed expectation file for 26-bit  teq,
	tst, cmn and cmp.
2015-08-13 11:39:08 +01:00
H.J. Lu
43e65147c0 Remove trailing spaces in opcodes 2015-08-12 04:45:07 -07:00
Alessandro Marzocchi
6f1c214259 Updates the ARM disassembler's output of floating point constants to include the actual floating point value.
opcodes	* arm-dis.c (print_insn_coprocessor): Added support for quarter
	float bitfield format.
	(coprocessor_opcodes): Changed VFP vmov reg,immediate to use new
	quarter float bitfield format.

tests	* gas/arm/vfpv3-const-conv.d: Update expected result due to change
	of comment for vmov reg,immediate with VFP coprocessor.
2015-07-16 16:43:16 +01:00
Szabolcs Nagy
24b4cf66a6 Fixes a compile time warnng about left shifting a negative value.
* arm-dis.c (print_insn_coprocessor): Avoid negative shift.
2015-06-16 13:35:33 +01:00
Matthew Wahab
d6b4b13ed2 [ARM] Support for ARMv8.1 Adv.SIMD extension 2015-06-02 12:37:33 +01:00
Matthew Wahab
ddfded2f7b [ARM] Add support for ARMv8.1 PAN extension 2015-06-02 12:30:38 +01:00
Matthew Wahab
1af1dd51db [ARM] Rework CPU feature selection in the disassembler
include/opcode/
	* arm.h (ARM_FEATURE_ALL): New.

opcodes/
	* arm-dis.c (select_arm_features): Rework to avoid used of
	redefined macros.
2015-06-02 12:24:24 +01:00
Renlin Li
f0fba320ab [ARM] Disassembles SSAT and SSAT16 instructions incorrectly for Thumb-2
2015-04-15  Renlin Li  <renlin.li@arm.com>
opcodes/:
    * arm-dis.c (thumb32_opcodes): Define 'D' format control code,
    use it for ssat and ssat16.
    (print_insn_thumb32): Add handle case for 'D' control code.

gas/testsuite/:
    * gas/arm/arch7em.d: Adjust required ssat and ssat16 immediate field.
    * gas/arm/thumb32.d: Likewise.
2015-04-15 17:44:03 +01:00
Terry Guo
823d25713d Extend arm_feature_set struct to provide more bits
gas/ChangeLog:
2015-03-24  Terry Guo  <terry.guo@arm.com>

	* config/tc-arm.c (no_cpu_selected): Use new macro to compare
	features.
	(parse_psr): Likewise.
	(do_t_mrs): Likewise.
	(do_t_msr): Likewise.
	(static const arm_feature_set arm_ext_*): Defined with new
	macros.
	(static const arm_feature_set arm_cext_*): Likewise.
	(static const arm_feature_set fpu_fpa_ext_*): Likewise.
	(static const arm_feature_set fpu_vfp_ext_*): Likewise.
	(deprecated_coproc_regs): Likewise.
	(UL_BARRIER): Likewise.
	(barrier_opt_names): Likewise.
	(arm_cpus): Likewise.
	(arm_extensions): Likewise.

include/opcode/ChangeLog:
2015-03-24  Terry Guo  <terry.guo@arm.com>

	* arm.h (arm_feature_set): Extended to provide more available
	* bits.
	(ARM_ANY): Updated to follow above new definition.
	(ARM_CPU_HAS_FEATURE): Likewise.
	(ARM_CPU_IS_ANY): Likewise.
	(ARM_MERGE_FEATURE_SETS): Likewise.
	(ARM_CLEAR_FEATURE): Likewise.
	(ARM_FEATURE): Likewise.
	(ARM_FEATURE_COPY): New macro.
	(ARM_FEATURE_EQUAL): Likewise.
	(ARM_FEATURE_ZERO): Likewise.
	(ARM_FEATURE_CORE_EQUAL): Likewise.
	(ARM_FEATURE_LOW): Likewise.
	(ARM_FEATURE_CORE_LOW): Likewise.
	(ARM_FEATURE_CORE_COPROC): Likewise.

opcodes/ChangeLog:
2015-03-24  Terry Guo  <terry.guo@arm.com>

	* arm-dis.c (opcode32): Updated to use new arm feature struct.
	(opcode16): Likewise.
	(coprocessor_opcodes): Replace bit with feature struct.
	(neon_opcodes): Likewise.
	(arm_opcodes): Likewise.
	(thumb_opcodes): Likewise.
	(thumb32_opcodes): Likewise.
	(print_insn_coprocessor): Likewise.
	(print_insn_arm): Likewise.
	(select_arm_features): Follow new feature struct.
2015-03-24 14:08:08 +08:00
Jiong Wang
d8282f0eb1 [ARM] Skip private symbol when doing objdump
2015-03-03  Jiong Wang  <jiong.wang@arm.com>

  opcode/
    * arm-dis.c (arm_symbol_is_valid): Skip ARM private symbols.

  binutils/testsuite/
    * binutils-all/arm/rvct_symbol.s: New testcase.
    * binutils-all/arm/objdump.exp: Run it.
2015-03-03 15:00:59 +00:00
Alan Modra
b90efa5b79 ChangeLog rotatation and copyright year update 2015-01-02 00:53:45 +10:30
Maciej W. Rozycki
84919466a8 ARM/opcodes: Fix negative hexadecimal offset disassembly
2014-08-21  Nathan Sidwell  <nathan@codesourcery.com>
            Maciej W. Rozycki  <macro@codesourcery.com>

	opcodes/
	* arm-dis.c (print_arm_address): Negate the GPR-relative offset
	returned if the U bit is set.

2014-08-21  Paul Brook  <paul@codesourcery.com>

	gas/testsuite/
	* gas/arm/arch7a-mp.d: Adjust according to `print_arm_address'
	offset fix.
	* gas/arm/arch7r-mp.d: Likewise.
2014-08-22 16:42:12 +01:00
Alan Modra
4b95cf5c0c Update copyright years 2014-03-05 22:16:15 +10:30
Ramana Radhakrishnan
8518117318 Fix neon vshll disassembly.
opcodes/
2013-10-15  Ramana Radhakrishnan  <ramana.radhakrishnan@arm.com>

	* arm-dis.c (neon_opcodes): Adjust print string for vshll.

gas/testsuite/
2013-10-15  Ramana Radhakrishnan  <ramana.radhakrishnan@arm.com>

	* gas/arm/neon-cov.d: Adjust output.
2013-10-15 13:30:40 +00:00
Nick Clifton
74db7efbe3 PR gas/15914
* config/tc-arm.c (T16_32_TAB): Add _udf.
	(do_t_udf): New function.
	(insns): Add "udf".

	* gas/arm/udf-bad.s: New file.
	* gas/arm/udf-bad.d: New file.
	* gas/arm/udf-bad.l: New file.
	* gas/arm/udf.s: New file.
	* gas/arm/udf.d: New file.
	* gas/arm/udf.l: New file.

	* arm-dis.c (arm_opcodes): Add udf.
	(thumb_opcodes): Use "udf" mnemonic rather than UNDEFINED_INSTRUCTION.
	(thumb32_opcodes): Add udf.w.
	(print_insn_thumb32): Handle %H as the thumb32_opcodes comment says.
2013-09-04 07:59:33 +00:00
Kyrylo Tkachov
dd5181d57f Add support for AArch32 CRC instruction in ARMv8.
gas/ChangeLog
2013-03-11  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>

	* config/tc-arm.c (crc_ext_armv8): New feature set.
	(UNPRED_REG): New macro.
	(do_crc32_1): New function.
	(do_crc32b, do_crc32h, do_crc32w, do_crc32cb,
	do_crc32ch, do_crc32cw): Likewise.
	(TUEc): New macro.
	(insns): Add entries for crc32 mnemonics.
	(arm_extensions): Add entry for crc.

include/opcode/ChangeLog
2013-03-11  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>

	* arm.h (CRC_EXT_ARMV8): New constant.
	(ARCH_CRC_ARMV8): New macro.

opcodes/ChangeLog
2013-03-11  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>

	* arm-dis.c (arm_opcodes): Add entries for CRC instructions.
	(thumb32_opcodes): Likewise.
	(print_insn_thumb32): Handle 'S' control char.

gas/testsuite/ChangeLog
2013-03-11  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>

	* gas/arm/crc32-bad.d: New file.
	* gas/arm/crc32-bad.l: Likewise.
	* gas/arm/crc32-bad.s: Likewise.
	* gas/arm/crc32.d: Likewise.
	* gas/arm/crc32.s: Likewise.
2013-03-11 11:09:33 +00:00
Richard Earnshaw
6fe6ded97b 2013-02-11 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
* arm-dis.c: Update strht pattern.

	* gas/arm/archv6t2.s: Add strht and ldrht tests.
	* gas/arm/archv6t2.d: Add disassembly patterns for the above.
2013-02-11 10:15:52 +00:00
Richard Earnshaw
f8ece37fb1 2012-10-11 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
* arm-dis.c: Use preferred form of vrint instruction variants
	for disassembly.

2012-10-11  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>

	* gas/arm/armv8-a+fp.d: Use preferred form of vrint instruction
	variants for disassembly.
	* gas/arm/armv8-a+fp.s: Likewise.
	* gas/arm/armv8-a+simd.d: Likewise.
	* gas/arm/armv8-a+simd.s: Likewise.
2012-10-11 15:33:08 +00:00
Richard Earnshaw
4b8c8c02e9 2012-09-18 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
opcodes:
	* arm-dis.c: Changed ldra and strl-form mnemonics
	to lda and stl-form.
gas:
	* config/tc-arm.c: Changed ldra and strl-form mnemonics
	to lda and stl-form for armv8.
gas/testsuite:
	* gas/arm/armv8-a-bad.l: Updated for changed mnemonics.
	* gas/arm/armv8-a-bad.s: Likewise.
	* gas/arm/armv8-a.d: Likewise.
	* gas/arm/armv8-a.s: Likewise.
	* gas/arm/inst.s: Added test for ldrt encoding compatibly with ldralt.
	* gas/arm/inst.d: Updated.
2012-09-18 14:52:43 +00:00
Matthew Gretton-Dann
3c9017d250 * gas/config/tc-arm.c (ARM_ENC_TAB): Add sha1h and sha2op entries.
(do_sha1h): New function.
	(do_sha1su1): Likewise.
	(do_sha256su0): Likewise.
	(insns): Add 2 operand SHA instructions.
	* gas/testsuite/gas/arm/armv8-a+crypto.s: Update testcase.
	* gas/testsuite/gas/arm/armv8-a+crypto.d: Likewise.
	* opcodes/arm-dis.c (neon_opcodes): Add 2 operand sha instructions.
2012-08-24 08:14:40 +00:00
Matthew Gretton-Dann
48adcd8ed5 * gas/config/tc-arm.c (NEON_ENC_TAB): Add sha3op entry.
(do_crypto_3op_1): New function.
	(do_sha1c): Likewise.
	(do_sha1p): Likewise.
	(do_sha1m): Likewise.
	(do_sha1su0): Likewise.
	(do_sha256h): Likewise.
	(do_sha256h2): Likewise.
	(do_sha256su1): Likewise.
	(insns): Add SHA 3 operand instructions.
	* gas/testsuite/gas/arm/armv8-a+crypto.d: Update testcase.
	* gas/testsuite/gas/arm/armv8-a+crypto.s: Likewise.
	* opcodes/arm-dis.c (neon_opcodes): Add SHA 3-operand instructions.
2012-08-24 08:14:04 +00:00
Matthew Gretton-Dann
4f51b4bdbb * gas/config/tc-arm.c (neon_type_mask): Add P64 type.
(type_chk_of_el_type): Handle P64 type.
	(el_type_of_type_chk): Likewise.
	(do_neon_vmull): Handle VMULL.P64.
	* gas/testsuite/gas/arm/armv8-a+crypto.d: Update testcase.
	* gas/testsuite/gas/arm/armv8-a+crypto.s: Likewise.
	* opcodes/arm-dis.c (neon_opcodes): Handle VMULL.P64.
2012-08-24 08:13:24 +00:00