This commit eliminates make_cleanup_obstack_free, replacing it with a
new auto_obstack type that inherits obstack to add cdtors.
These changes in the parsers may not be obvious:
- obstack_init (&name_obstack);
- make_cleanup_obstack_free (&name_obstack);
+ name_obstack.clear ();
Here, the 'name_obstack' variable is a global. The change means that
the obstack's contents from a previous parse will stay around until
the next parsing starts. I.e., memory won't be reclaimed until then.
I don't think that's a problem, these objects don't really grow much
at all.
The other option I tried was to add a separate type that is like
auto_obstack but manages an external obstack, just for those cases. I
like the current approach better as that other approach adds more
boilerplate and yet another type to learn.
gdb/ChangeLog:
2017-06-27 Pedro Alves <palves@redhat.com>
* c-exp.y (name_obstack): Now an auto_obstack.
(yylex): Use auto_obstack::clear.
(c_parse): Use auto_obstack::clear instead of reinitializing and
freeing the obstack.
* c-lang.c (evaluate_subexp_c): Use auto_obstack.
* d-exp.y (name_obstack): Now an auto_obstack.
(yylex): Use auto_obstack::clear.
(d_parse): Use auto_obstack::clear instead of reinitializing and
freeing the obstack.
* dwarf2loc.c (fetch_const_value_from_synthetic_pointer): Use
auto_obstack.
* dwarf2read.c (create_addrmap_from_index)
(dwarf2_build_psymtabs_hard)
(update_enumeration_type_from_children): Likewise.
* gdb_obstack.h (auto_obstack): New type.
* go-exp.y (name_obstack): Now an auto_obstack.
(build_packaged_name): Use auto_obstack::clear.
(go_parse): Use auto_obstack::clear instead of reinitializing and
freeing the obstack.
* linux-tdep.c (linux_make_mappings_corefile_notes): Use
auto_obstack.
* printcmd.c (printf_wide_c_string, ui_printf): Use auto_obstack.
* rust-exp.y (work_obstack): Now an auto_obstack.
(rust_parse, rust_lex_tests): Use auto_obstack::clear instead of
reinitializing and freeing the obstack.
* utils.c (do_obstack_free, make_cleanup_obstack_free): Delete.
(host_char_to_target): Use auto_obstack.
* utils.h (make_cleanup_obstack_free): Delete declaration.
* valprint.c (generic_emit_char, generic_printstr): Use
auto_obstack.
Fix incorrect adjustment of diff relocs when relaxing, and thus the
resulting source line to address mismatch.
Fix two issues when adjusting diff relocs to account for
deleted bytes.
1. Don't adjust the difference if the end address is the shrinked
insn's address i.e. use < instead of <=. The relaxation code deletes
count bytes from or after shrinked_insn_address, so the difference
between start_address and end_address should remain unchanged in this
case.
2. Adjust the reloc addend if the difference is to be adjusted and
symval + reloc addend is past the shrinked insn address. This is
because for a typical sym1 - sym2 diff reloc, sym1 is .text +
irel->r_addend, and the addend should be reduced to account for the
shrinked insn.
For example, assume the reloc value is .text + 0x8 with .text = 0, the
diff value in the object file = 0x4, and shrinked_insn_address = 0x4
with count = 0x2. Then the existing code writes 0x2 into the object
file to account for the deleted bytes, as shrinked_insn_address lies
between 0x8 and 0x8 - 0x4 = 0x4, but leaves the addend as is. The next
time the reloc is looked at, the code sees if a shrinked_insn_address
lies between 0x8 and 0x8 - 0x2 = 0x6, instead of 0x6 and 0x4. If there
happens to be one, then the diff value in the object file ends up
getting reduced again.
bfd/
2017-06-27 Senthil Kumar Selvaraj <senthil_kumar.selvaraj@atmel.com>
PR ld/13402
* elf32-avr.c (elf32_avr_adjust_diff_reloc_value): Adjust
reloc addend if necessary. Adjust diff only if
shrinked_insn_address < end_address.
ld/
2017-06-27 Senthil Kumar Selvaraj <senthil_kumar.selvaraj@atmel.com>
PR ld/13402
* testsuite/ld-avr/pr13402.d: New test.
* testsuite/ld-avr/pr13402.s: New test.
Starting a process on macOS/Darwin currently leads to this error:
/Users/simark/src/binutils-gdb/gdb/darwin-nat.c:383: internal-error: void darwin_check_new_threads(struct inferior *): Assertion `tp' failed.
with the corresponding partial backtrace (sorry, taken with lldb,
because well, gdb is broken :)):
frame #9: 0x000000010004605a gdb`darwin_check_new_threads(inf=0x0000000100edf670) at darwin-nat.c:383
frame #10: 0x0000000100045848 gdb`darwin_init_thread_list(inf=0x0000000100edf670) at darwin-nat.c:1710
frame #11: 0x00000001000452f8 gdb`darwin_ptrace_him(pid=8375) at darwin-nat.c:1792
frame #12: 0x0000000100041d95 gdb`fork_inferior(...) at fork-inferior.c:440
frame #13: 0x0000000100043f82 gdb`darwin_create_inferior(...) at darwin-nat.c:1841
frame #14: 0x000000010034ac32 gdb`run_command_1(args=0x0000000000000000, from_tty=1, tbreak_at_main=1) at infcmd.c:611
The issue was introduced by commit
"Share fork_inferior et al with gdbserver"
because it changed the place where the dummy thread (pid, 0, 0) is added,
relative to the call to the init_trace_fun callback. In this callback, darwin
checks for new threads in the program (there should be exactly one) in order to
update this dummy thread with the right tid. Previously, things happened in
this order:
- fork_inferior calls fork()
- fork_inferior adds dummy thread
- fork_inferior calls init_trace_fun callback, which updates the dummy
thread info
Following the commit mentioned above, the new thread is added in the
darwin-nat code, after having called fork_inferior (in
darwin_create_inferior). So gdb tries to do things in this order:
- fork_inferior calls fork()
- fork_inferior calls init_trace_fun callback, which tries to update
the dummy thread info
- darwin_create_inferior adds the dummy thread
The error happens while trying to update the dummy thread that has not
been added yet.
I don't think this dummy thread is necessary for darwin. Previously, it
was fork_inferior that was adding this thread, for all targets, so
darwin had to deal with it. Now that it's done by targets themselves,
we can just skip that on darwin. darwin_check_new_threads called
indirectly by init_trace_fun/darwin_ptrace_him will simply notice the
new thread and add it with the right information.
My level of testing was: try to start a process and try to attach to a
process, and it seems to work somewhat like it did before. I tried to
run the testsuite, but it leaves a huge amount of zombie processes that
launchd doesn't seem to reap, leading to exhaustion of system resources
(number of processes).
gdb/ChangeLog:
* darwin-nat.c (darwin_check_new_threads): Don't handle dummy
thread.
(darwin_init_thread_list): Don't update dummy thread.
(darwin_create_inferior, darwin_attach): Don't add a dummy thread.
Complement commit 351cdf24d2 ("[MIPS] Implement O32 FPXX, FP64 and
FP64A ABI extensions") and add optional MIPS ABI Flags handling to
`good_combination' in the `mips-elf-flags.exp' test script. This lets
callers of this procedure request to examine MIPS ABI Flags in addition
to the `e_flags' member of the ELF file header so as to verify that
flags are merged correctly by LD. The presence of further arguments
triggers this verification, in which case `readelf' is called with the
`-A' option additionally specified and the ISA member, the ISA Extension
member and the ASEs member will be examined as per the arguments.
Unlike with `readelf -h' output consider a failure to retrieve the
member requested a test case failure rather than an unresolved result.
This is because unlike with the `e_flags' member of the ELF file header
which is always there in any valid ELF file the MIPS ABI Flags structure
is optional in LD output and the absence of this structure when expected
is surely a bug in LD.
ld/
* testsuite/ld-mips-elf/mips-elf-flags.exp (good_combination):
Add an `args' final argument and examination code for `readelf
-A' output. Update procedure description accordingly.
For ELF file header flag verification done in `good_combination' in the
`mips-elf-flags.exp' test script the version of `readelf' built along
with the rest of binutils has to be used rather than any such executable
already present on the build system, so that flags recognized by the
tool match those supported by LD being tested. Use `remote_exec' as
elsewhere in the LD test framework and also with GAS and LD used here,
getting and arranging for extra reporting of `readelf' calls included in
test logs on this occasion as well.
ld/
* testsuite/ld-mips-elf/mips-elf-flags.exp (good_combination):
Use `remote_exec' to call `readelf'. Log the command issued.
For the purpose of link-time object compatibility handling verification
code in the `good_combination' procedure from the `mips-elf-flags.exp'
test script only examines the `e_flags' member of the ELF file header
and ignores data from any ELF program or section headers present. Use
`readelf -h' rather than `readelf --headers' then to obtain data for
examination, avoiding unnecessary processing to extract this extraneous
information.
ld/
* testsuite/ld-mips-elf/mips-elf-flags.exp (good_combination):
Use `readelf -h' rather than `readelf --headers'.
The symbol address in .eh_frame may be adjusted in
_bfd_elf_discard_section_eh_frame, and the content of .eh_frame will be
adjusted in _bfd_elf_write_section_eh_frame. Therefore, we cannot insert
a relocation whose addend symbol is in .eh_frame. Othrewise, the value
may be adjusted twice.
bfd/ChangeLog
2017-06-26 Kuan-Lin Chen <rufus@andestech.com>
* elfnn-riscv.c (perform_relocation): Support the new
R_RISCV_32_PCREL relocation.
(riscv_elf_relocate_section): Likewise.
* elfxx-riscv.c (howto_table): Likewise.
(riscv_reloc_map): Likewise.
* bfd-in2.h (BFD_RELOC_RISCV_32_PCREL): New relocation.
* libbfd.h: Regenerate.
gas/ChangeLog
2017-06-26 Kuan-Lin Chen <rufus@andestech.com>
* config/tc-riscv.c (md_apply_fix) [BFD_RELOC_32]: Convert to a
R_RISCV_32_PCREL relocation.
include/ChangeLog
2017-06-26 Kuan-Lin Chen <rufus@andestech.com>
* elf/riscv.h (R_RISCV_32_PCREL): New.
Make BFD agree with GAS and mark the LSI MiniRISC CW4010 processor core
(for an odd reason referred to as LSI R4010 across our code base) as a
MIPS II processor in BFD as well, fixing a bug that has been there since
forever and addressing linker warnings like:
$ as -m4010 empty.s -o 4010.o
$ ld -r 4010.o -o 4010-r.o
ld: 4010.o: warning: Inconsistent ISA between e_flags and .MIPS.abiflags
$
due to the ISA level being recorded as MIPS III in ELF file header's
`e_flags' vs MIPS II in the MIPS ABI Flags section:
$ readelf -Ah 4010.o
ELF Header:
Magic: 7f 45 4c 46 01 02 01 00 00 00 00 00 00 00 00 00
Class: ELF32
Data: 2's complement, big endian
Version: 1 (current)
OS/ABI: UNIX - System V
ABI Version: 0
Type: REL (Relocatable file)
Machine: MIPS R3000
Version: 0x1
Entry point address: 0x0
Start of program headers: 0 (bytes into file)
Start of section headers: 348 (bytes into file)
Flags: 0x20821000, 4010, o32, mips3
Size of this header: 52 (bytes)
Size of program headers: 0 (bytes)
Number of program headers: 0
Size of section headers: 40 (bytes)
Number of section headers: 11
Section header string table index: 10
Attribute Section: gnu
File Attributes
Tag_GNU_MIPS_ABI_FP: Hard float (double precision)
MIPS ABI Flags Version: 0
ISA: MIPS2
GPR size: 32
CPR1 size: 32
CPR2 size: 0
FP ABI: Hard float (double precision)
ISA Extension: LSI R4010
ASEs:
None
FLAGS 1: 00000000
FLAGS 2: 00000000
$
Available documentation[1][2] clearly indicates the LSI CW4010 processor
is only backwards compatible with the MIPS R4000 processor as far as the
latter's 32-bit instructions are concerned and consequently can only be
considered a MIPS II ISA implementation (with vendor extensions).
This fixes an LD testsuite failure:
FAIL: MIPS incompatible objects: "-march=r4010 -32" "-march=r4650 -32"
triggered for the `mips-sgi-irix5' and `mips-sgi-irix6' targets.
References:
[1] Paul Cobb, Bob Caulk, Joe Cesana, "The MiniRISC CW4010: A
Superscalar MIPS Processor ASIC Core", LSI Logic, July 1995,
presented at Hot Chips VII, Stanford University, Stanford,
California, August 1995
[2] "MiniRISC MR4010 Superscalar Microprocessor Reference Device", LSI
Logic, November 1996, Doc. No. DB09-000028-00, Order No. C15017
bfd/
* cpu-mips.c (arch_info_struct): Mark the 4010 32-bit.
* elfxx-mips.c (mips_set_isa_flags) <bfd_mach_mips4010>: Set
E_MIPS_ARCH_2 rather than E_MIPS_ARCH_3 in `e_flags'.
(mips_mach_extensions): Mark `bfd_mach_mips4010' as extending
`bfd_mach_mips6000' rather than `bfd_mach_mips4000'.
ld/
* testsuite/ld-mips-elf/lsi-4010-isa.d: New test.
* ld/testsuite/ld-mips-elf/mips-elf.exp: Run the new test.
Don't check the section size in bfd_get_full_section_contents since
the size of a decompressed section may be larger than the file size.
Instead, check file size in _bfd_generic_get_section_contents.
PR binutils/21665
* compress.c (bfd_get_full_section_contents): Don't check the
file size here.
* libbfd.c (_bfd_generic_get_section_contents): Check for and
reject a section whoes size + offset is greater than the size
of the entire file.
(_bfd_generic_get_section_contents_in_window): Likewise.
Correct .startof.SECNAME/.sizeof.SECNAME tests for MIPS/IRIX targets,
complementing commit dc74becf49 ("ld: Add tests for -Ur") and commit
da614360f5 ("ld: Add tests for .startof.SECNAME/.sizeof.SECNAME") with
subsequent updates, and in reference to commit cbd0eecf26 ("Always
define referenced __start_SECNAME/__stop_SECNAME") and commit
7dba9362c1 ("Rewrite __start and __stop symbol handling").
These targets set the STT_OBJECT type for non-function symbol
references, according to `elf_frob_symbol' code in gas/config/obj-elf.c:
/* The Irix 5 and 6 assemblers set the type of any common symbol and
any undefined non-function symbol to STT_OBJECT. We try to be
compatible, since newer Irix 5 and 6 linkers care. However, we
only set undefined symbols to be STT_OBJECT if we are on Irix,
because that is the only time gcc will generate the necessary
.global directives to mark functions. */
if (S_IS_COMMON (symp))
symbol_get_bfdsym (symp)->flags |= BSF_OBJECT;
if (strstr (TARGET_OS, "irix") != NULL
&& ! S_IS_DEFINED (symp)
&& (symbol_get_bfdsym (symp)->flags & BSF_FUNCTION) == 0)
symbol_get_bfdsym (symp)->flags |= BSF_OBJECT;
and consequently entries in the symbol table listing from `readelf'
produced with these tests do not match the NOTYPE pattern expected,
causing test suite failures:
FAIL: ld-elf/sizeofa
FAIL: ld-elf/sizeofc
FAIL: ld-elf/startofa
FAIL: ld-elf/startofc
specifically with the `mips-sgi-irix5' and `mips-sgi-irix6' targets.
Given that it does not matter for the feature covered by these tests
whether the type of the symbols produced is STT_NOTYPE or STT_OBJECT
adjust the problematic cases to accept either type, removing the
failures observed.
ld/
* testsuite/ld-elf/sizeofa.d: Also accept the OBJECT type for
the symbols examined.
* testsuite/ld-elf/sizeofc.d: Likewise.
* testsuite/ld-elf/startofa.d: Likewise.
* testsuite/ld-elf/startofc.d: Likewise.
clang shows this warning:
/home/emaisin/src/binutils-gdb/gdb/record-full.c:2344:1: error: unused function 'netorder16' [-Werror,-Wunused-function]
netorder16 (uint16_t input)
^
Remove this function, which, AFAIK, has never been used. Note that GCC
doesn't warn about this, because the function is marked as inline.
According to gcc's man page, it should ideed not warn:
-Wunused-function
Warn whenever a static function is declared but not defined or a non-inline static function is unused. This warning is enabled by -Wall.
So it's probably not a GCC bug that it doesn't find this unused function, but a
different definition of "unused".
gdb/ChangeLog:
* record-full.c (netorder16): Remove.
clang has a too aggressive (or broken, depends on how you want to see
it) -Wunused-function warning, which is triggered by the functions
defined by DEF_VEC_* but not used in the current source file. Normally,
it won't warn about unused static inline functions defined in header
files, because it's expected that a source file won't use all functions
defined in a header file it includes. However, if the DEF_VEC_* macro
is used in a source file, it considers those functions as defined in the
source file, which leads it to think that we should remove those
functions. It is therefore missing a check to see whether those
functions are resulting from macro expansion. A bug already exists for
that:
https://bugs.llvm.org//show_bug.cgi?id=22712
It's quite easy to silence this warning in a localized way, that is in
the DEF_VEC_* macros.
gdb/ChangeLog:
* common/diagnostics.h: Define macros for GCC.
(DIAGNOSTIC_IGNORE_UNUSED_FUNCTION): New macro.
* common/vec.h: Include diagnostics.h.
(DIAGNOSTIC_IGNORE_UNUSED_VEC_FUNCTION): New macro.
(DEF_VEC_I, DEF_VEC_P, DEF_VEC_O): Ignore -Wunused-function
warning.
Some older versions of flex (such as the one shipped with macOS) generate
code that use the register keyword, which clang warns about. This patch
makes the compiler ignore those warnings for the portion of the code
generated by flex.
gdb/ChangeLog:
* common/diagnostics.h (DIAGNOSTIC_IGNORE_DEPRECATED_REGISTER):
New macro.
* ada-lex.l: Ignore deprecated register warnings.
PR binutils/21665
bfd * opncls.c (get_build_id): Check that the section is beig enough
to contain the whole note.
* compress.c (bfd_get_full_section_contents): Check for and reject
a section whoes size is greater than the size of the entire file.
* elf32-v850.c (v850_elf_copy_notes): Allow for the ouput to not
contain a notes section.
binutils* objdump.c (disassemble_section): Skip any section that is bigger
than the entire file.
The .symver directive on common symbol creates a new common symbol,
which shouldn't be allowed, similar to alias on common symbol:
$ cat y.S
.comm bar,8,8
.set bar1,bar
$ as -o y.o y.S
y.S: Assembler messages:
y.S:2: Error: `bar1' can't be equated to common symbol 'bar'
$
PR gas/21661
* config/obj-elf.c (obj_elf_symver): Don't allow .symver with
common symbol.
(elf_frob_symbol): Likewise.
* testsuite/gas/elf/elf.exp: Run pr21661.
* testsuite/gas/elf/pr21661.d: New file.
* testsuite/gas/elf/pr21661.s: Likewise.
The recent pgste patch caused several testcases to fail with a
segfault. Fixed with this patch by adding NULL pointer checks.
regression-tested on s390x.
bfd/ChangeLog:
2017-06-26 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
* elf64-s390.c (elf_s390_additional_program_headers): Add NULL
pointer checks.
(elf_s390_modify_segment_map): Likewise.
(bfd_elf_s390_set_options): Lisewise.
ARC cpus do not accept any jump or instructions with long immediate
into the delay slots.
gas/
2017-06-07 Claudiu Zissulescu <claziss@synopsys.com>
* /config/tc-arc.c (is_br_jmp_insn_p): Update macro with known
instructions to be accounted as jumps.
(assemble_insn): Check for limms into the delay slots. Emit an
error if so.
* testsuite/gas/arc/asm-errors-3.d: New file.
* testsuite/gas/arc/asm-errors-3.err: Likewise.
* testsuite/gas/arc/asm-errors-3.s: Likewise.
All sections on a --just-syms bfd are discarded from the output, so
attaching linker created sections to such a bfd results in errors.
In other cases, like the .note.GNU-stack check, it's wrong to have a
--just-syms object potentially affect the output.
bfd/
* elflink.c (_bfd_elf_link_create_dynstrtab): Don't make dynobj
a --just-syms bfd.
(_bfd_elf_size_group_sections): Skip --just-syms bfds.
(bfd_elf_size_dynamic_sections): Ignore .note.GNU-stack and
.preinit_array on --just-syms bfds.
(_bfd_elf_gc_mark_extra_sections): Skip --just-syms bfds.
(elf_gc_sweep, bfd_elf_parse_eh_frame_entries): Likewise.
(bfd_elf_gc_sections, bfd_elf_discard_info): Likewise.
ld/
* emultempl/elf32.em (gld${EMULATION_NAME}_after_open): Skip
--just-syms bfds when looking for a place to attach .note.gnu.build-id
and .eh_frame_hdr sections. Delete dead code.
clang shows this warning:
/home/emaisin/src/binutils-gdb/gdb/main.c:227:56: error: adding 'int' to a string does not append to the string [-Werror,-Wstring-plus-int]
char *tmp_sys_gdbinit = xstrdup (SYSTEM_GDBINIT + datadir_len);
~~~~~~~~~~~~~~~^~~~~~~~~~~~~
/home/emaisin/src/binutils-gdb/gdb/main.c:227:56: note: use array indexing to silence this warning
char *tmp_sys_gdbinit = xstrdup (SYSTEM_GDBINIT + datadir_len);
^
& [ ]
It's quite easy to get rid of it by using &foo[len] instead of foo + len.
I think this warning is relevant to keep enabled, because it can be an
easy mistake to do.
This warning is already discussed here in GCC bugzilla:
https://gcc.gnu.org/ml/gcc-patches/2017-06/msg00729.html
and a patch series for it was submitted very recently.
gdb/ChangeLog:
* main.c (get_init_files): Replace "SYSTEM_GDBINIT +
datadir_len" with "&SYSTEM_GDBINIT[datadir_len]".
clang shows this warning.
/home/emaisin/src/binutils-gdb/gdb/dtrace-probe.c:424:52: error: while loop has empty body [-Werror,-Wempty-body]
while (*p++ != '\0' && p - strtab < strtab_size);
^
/home/emaisin/src/binutils-gdb/gdb/dtrace-probe.c:424:52: note: put the semicolon on a separate line to silence this warning
Putting the semicolon on its own line is not a big sacrifice to get rid of this
warning. I think it's also useful to keep this, because it can catch errors
like this:
while (something);
{
...
}
although gcc would warn about it in a different way (misleading indentation).
This warning is already discussed here in the GCC bugzilla:
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=62184
gdb/ChangeLog:
* dtrace-probe.c (dtrace_process_dof_probe): Put semi-colon on
its own line.
This get around this warning given by clang...
/home/emaisin/src/binutils-gdb/gdb/nat/x86-dregs.c:209:7: error: variable 'i' is incremented both in the loop header and in the loop body [-Werror,-Wfor-loop-analysis]
i++;
^
/home/emaisin/src/binutils-gdb/gdb/nat/x86-dregs.c:199:32: note: incremented here
ALL_DEBUG_ADDRESS_REGISTERS (i)
^
... I decided in the end to simply print the debug registers one per
line. I don't think it particularly helps readability to have them two
per line anyway.
gdb/ChangeLog:
* nat/x86-dregs.c (x86_show_dr): Print registers one per line.
The out-of-bounds access is reproducible on 'ia64-strip' command
(see sample from https://bugs.gentoo.org/show_bug.cgi?id=622500)
The output file contains less section than original one.
This tricks 'hint' access to go out-of-bounds:
* elf.c (find_link): Bounds check "hint".
=== Context ===
This patch is part of a patch series to add support for ARMv8-R
architecture. Its purpose is to add support for ARM Cortex-R52
processor.
=== Patch description ===
This patch adds support for Cortex-R52 as an ARMv8-R processor with CRC
extensions.
2017-06-26 Thomas Preud'homme <thomas.preudhomme@arm.com>
gas/
* NEWS: Mention support of ARM Cortex-R52 processor.
* config/tc-arm.c (arm_cpus): Add entry for ARM Cortex-R52 processor.
* doc/c-arm.texi: Mention support for -mcpu=cortex-r52.
=== Context ===
This patch is part of a patch series to add support for ARMv8-R
architecture. Its purpose is to add support for ARMv8-R in the linker.
=== Patch description ===
This patch is composed of 3 changes:
1) The main change is the addition of the logic for merging a file whose
Tag_CPU_arch build attribute is 15 (ARMv8-R). Namely, all pre-ARMv8 are
merged into ARMv8-R as well as ARMv8-R itself. ARMv8-A (14) merges into
ARMv8-A. ARMv8-M Baseline (16) and Mainline (17) are not allowed to
merge merge with ARMv8-R. Note that merging only occurs if the two
profiles are identical or one is S (Application or Realtime) and the
other is R.
2) using_thumb_only, using_thumb2_bl, using_thumb2 and arch_has_arm_nop
are updated according to capabilities of ARMv8-R and their BFD_ASSERT
updated to reflect that the logic is valid for ARMv8-R.
3) 2 build attribute merging tests are added to test the first change.
2017-06-24 Thomas Preud'homme <thomas.preudhomme@arm.com>
bfd/
* elf32-arm.c (using_thumb_only): Update list of architectures in
BFD_ASSERT for which the logic is valid.
(using_thumb2_bl): Likewise.
(using_thumb2): Likewise and return true for ARMv8-R.
(arch_has_arm_nop): Likewise.
(tag_cpu_arch_combine): New v8r table for ARMv8-R Tag_CPU_arch
merging logic. Update commentis for value 15 of v8m_baseline,
v8m_mainline and v4t_plus_v6_m arrays. Use v8r array to decide
merging of value 15 of Tag_CPU_arch.
ld/
* testsuite/ld-arm/arm-elf.exp (EABI attribute merging 11): New test.
(EABI attribute merging 12): Likewise.
* testsuite/ld-arm/attr-merge-11a.s: New file.
* testsuite/ld-arm/attr-merge-11b.s: New file.
* testsuite/ld-arm/attr-merge-11.attr: New file.
* testsuite/ld-arm/attr-merge-12a.s: New file.
* testsuite/ld-arm/attr-merge-12b.s: New file.
* testsuite/ld-arm/attr-merge-12.attr: New file.
=== Context ===
This patch is part of a patch series to add support for ARMv8-R
architecture. Its purpose is to add support for ARMv8-R in GAS:
instructions, build attributes and readelf.
=== Patch description ===
Although some differences exist for system registers, from GAS point of
view ARMv8-R supports the same instructions as ARMv8-A Aarch32 state
and a subset of its extensions. This patch therefore introduce a new
feature bit to distinguish the availability of the pan, ras and rdma
extensions between ARMv8-A and ARMv8-R and allow crypto, fp and simd
extensions to be used by ARMv8-R.
Most of the changes are then in the testsuite to (i) rename source files
and error output to be shared between ARMv8-A and ARMv8-R, (ii) rename
files with expected output for ARMv8-A build attributes and (iii) add
new files with expected output for ARMv8-R build attributes.
2017-06-24 Thomas Preud'homme <thomas.preudhomme@arm.com>
binutils/
* readelf.c (arm_attr_tag_CPU_arch): Fill value for ARMv8-R.
gas/
* NEWS: Mention support for ARMv8-R architecture.
* config/tc-arm.c (arm_archs): Add entry for ARMv8-R.
(arm_extensions): Restrict pan, ras and rdma extension to
ARMv8-A and make crypto, fp and simd extensions available to
ARMv8-R.
(cpu_arch_ver): Add entry for ARMv8-R.
(aeabi_set_public_attributes): Update gas_assert for Tag_DIV_use
logic.
* testsuite/gas/arm/armv8-a+fp.s: Rename into ...
* testsuite/gas/arm/armv8-ar+fp.s: This. Remove .arch directive.
* testsuite/gas/arm/armv8-a+fp.d: Specify source to assemble and
architecture to assemble for.
* testsuite/gas/arm/armv8-r+fp.d: New.
* testsuite/gas/arm/armv8-a+simd.s: Rename into ...
* testsuite/gas/arm/armv8-ar+simd.s: This. Remove .arch directive.
* testsuite/gas/arm/armv8-a+simd.d: Specify source to assemble and
architecture to assemble for.
* testsuite/gas/arm/armv8-r+simd.d: New.
* testsuite/gas/arm/armv8-a-bad.s: Rename into ...
* testsuite/gas/arm/armv8-ar-bad.s: This. Remove .arch directive.
* testsuite/gas/arm/armv8-a-bad.l: Rename into ...
* testsuite/gas/arm/armv8-ar-bad.l: This. Decrement line number by 1.
* testsuite/gas/arm/armv8-a-bad.d: Specify source to assemble,
architecture to assemble for and adjust error output file.
* testsuite/gas/arm/armv8-r-bad.d: New.
* testsuite/gas/arm/armv8-a-barrier.s: Rename into ...
* testsuite/gas/arm/armv8-ar-barrier.s: This.
* testsuite/gas/arm/armv8-a-barrier-arm.d: Adjust source.
* testsuite/gas/arm/armv8-a-barrier-thumb.d: Likewise.
* testsuite/gas/arm/armv8-r-barrier-arm.d: New.
* testsuite/gas/arm/armv8-r-barrier-thumb.d: New.
* testsuite/gas/arm/armv8-a-it-bad.s: Rename into ...
* testsuite/gas/arm/armv8-ar-it-bad.s: This. Remove .arch directive.
* testsuite/gas/arm/armv8-a-it-bad.l: Rename into ...
* testsuite/gas/arm/armv8-ar-it-bad.l: This. Decrement line number
by 1.
* testsuite/gas/arm/armv8-a-it-bad.d: Specify source to assemble,
architecture to assemble for and adjust error output file.
* testsuite/gas/arm/armv8-r-it-bad.d: New.
* testsuite/gas/arm/armv8-a.s: Rename into ...
* testsuite/gas/arm/armv8-ar.s: This. Remove .arch directive.
* testsuite/gas/arm/armv8-a.d: Specify source to assemble and
architecture to assemble for.
* testsuite/gas/arm/armv8-r.d: New.
* testsuite/gas/arm/attr-march-armv8-r+crypto.d: New.
* testsuite/gas/arm/attr-march-armv8-r+fp.d: New.
* testsuite/gas/arm/attr-march-armv8-r+simd.d: New.
* testsuite/gas/arm/attr-march-armv8-r.d: New.
* testsuite/gas/arm/crc32.s: Rename into ...
* testsuite/gas/arm/crc32-armv8-ar.s: This.
* testsuite/gas/arm/crc32.d: Rename into ...
* testsuite/gas/arm/crc32-armv8-a.d: This. Specify source to assemble.
* testsuite/gas/arm/crc32-armv8-r.d: New.
* testsuite/gas/arm/crc32-bad.s: Rename into ...
* testsuite/gas/arm/crc32-armv8-ar-bad.s: This.
* testsuite/gas/arm/crc32-bad.d: Rename into ...
* testsuite/gas/arm/crc32-armv8-a-bad.d: This. Specify source to
assemble.
* testsuite/gas/arm/crc32-armv8-r-bad.d: New.
* testsuite/gas/arm/mask_1.s: Rename into ...
* testsuite/gas/arm/mask_1-armv8-ar.s: This.
* testsuite/gas/arm/mask_1.d: Rename into ...
* testsuite/gas/arm/mask_1-armv8-a.d: This. Specify source to
assemble.
* testsuite/gas/arm/mask_1-armv8-r.d: new.
include/
* elf/arm.h (TAG_CPU_ARCH_V8R): New macro.
* opcode/arm.h (ARM_EXT2_V8A): New macro.
(ARM_AEXT2_V8A): Rename into ...
(ARM_AEXT2_V8AR): This.
(ARM_AEXT2_V8A): New macro.
(ARM_AEXT_V8R): New macro.
(ARM_AEXT2_V8R): New macro.
(ARM_ARCH_V8R): New macro.
=== Context ===
This patch is part of a patch series to add support for ARMv8-R
architecture. Its purpose is to remove special casing for ARMv6S-M
autodetection.
=== Motivation ===
Currently, SWI and SVC mnemonics are enabled for ARMv4T and successor
architectures with extra checks in the handler function (do_t_swi) to
give an error message when ARMv6-M is targeted and some more special
casing in aeabi_set_public_attributes. This was made to exclude these
mnemonics for ARMv6-M unless the OS extension is in use.
However this logic is superfluous: there is already code to check
whether an instruction is available based on the feature bit it is part
of and whether the targeted architecture has that feature bit. This
patch aims at removing that unneeded complexity.
=== Patch description ===
The OS extension is already limited to the ARMv6-M architecture so all
this patch does is redefined availability of the ARM_EXT_OS feature bit
to not be present for ARM_ARCH_V6M. ARM_ARCH_V6SM does not need any
change either because it already includes ARM_EXT_OS.
The patch also make sure that the error message that was given by
do_t_swi when SWI/SVC is unavailable is still the same by detecting the
situation in md_assemble.
2017-06-24 Thomas Preud'homme <thomas.preudhomme@arm.com>
gas/
* config/tc-arm.c (arm_ext_v6m): Delete.
(arm_ext_v7m): Delete.
(arm_ext_m): Remove ARM_EXT_OS from the set of feature defined M
profile.
(arm_arch_v6m_only): Delete.
(do_t_swi): Remove special case for ARMv6S-M.
(md_assemble): Display error message previously in do_t_swi when
SVC is not available.
(insns): Guard swi and svc by arm_ext_os for Thumb mode.
(aeabi_set_public_attributes): Remove special case for ARMv6S-M.
include/
* opcode/arm.h (ARM_AEXT_V4TxM): Add ARM_EXT_OS bit to the set.
(ARM_AEXT_V4T): Likewise.
(ARM_AEXT_V5TxM): Likewise.
(ARM_AEXT_V5T): Likewise.
(ARM_AEXT_V6M): Mask off ARM_EXT_OS bit.
2017-06-23 Andrew Waterman <andrew@sifive.com>
* riscv-opc.c (riscv_opcodes): Mark I-type SLT instruction as an
alias; do not mark SLTI instruction as an alias.
BFD_RELOC_AARCH64_ADR_GOTPAGE should be BFD_RELOC_AARCH64_ADR_GOT_PAGE.
bfd/
* reloc.c (BFD_RELOC_AARCH64_ADR_GOTPAGE): Rename to
BFD_RELOC_AARCH64_ADR_GOT_PAGE
* bfd-in2.h: Regenerated.
elfcpp/
* elfcpp.h (DT_PPC64_OPT): Define.
* powerpc.h (PPC64_OPT_TLS, PPC64_OPT_MULTI_TOC,
PPC64_OPT_LOCALENTRY): Define.
gold/
* options.h (General_options): Add plt_localentry.
* powerpc.cc (Target_powerpc::st_other): New function.
(Target_powerpc::plt_localentry0_, plt_localentry0_init_,
has_localentry0_): New vars.
(Target_powerpc::plt_localentry0, set_has_localentry0,
is_elfv2_localentry0): New functions.
(Target_powerpc::Branch_info::mark_pltcall): Don't set tocsave or
return true for localentry:0 calls.
(Stub_table::Plt_stub_ent::localentry0_): New var.
(Stub_table::add_plt_call_entry): Set localentry0_ and has_localentry0_.
Don't set r2save_ for localentry:0 calls.
(Output_data_glink::do_write): Save r2 in __glink_PLTresolve for elfv2.
(Target_powerpc::scan_relocs): Default plt_localentry0_.
(Target_powerpc::do_finalize_sections): Set DT_PPC64_OPT.
(Target_powerpc::Relocate::relocate): Don't require nop following
calls for localentry:0 plt calls, and don't change nop.
This adds support to gold for the tocsave relocs already supported by
ld.bfd. R_PPC64_TOCSAVE relocs are part of a scheme to move r2 saves
to the prologue of a function rather than in each plt call stub. We
don't want a compiler to always emit the r2 save, as this would be
wasted if the calls turned out to be local. See the tocsave*.s in
ld/testsuite/ld-powerpc/.
* powerpc.cc (Target_powerpc::tocsave_loc_): New var.
(Target_powerpc::mark_pltcall, add_tocsave, tocsave_loc): New functions.
(Target_powerpc::Branch_info::tocsave_): New var.
(Target_powerpc::Branch_info::mark_pltcall): New function.
(Target_powerpc::Branch_info::make_stub): Pass tocsave_ to
add_plt_call_entry.
(Stub_table::Plt_stub_ent): Make public. Add r2save_.
(Stub_table::add_plt_call_entry): Add bool tocsave_ param. Set
r2save_.
(Stub_table::find_plt_call_entry): Return Plt_stub_ent*. Adjust
use throughout.
(Stub_table::do_write): Conditionally output r2 save in plt stubs.
(Target_powerpc::Scan::local): Handle R_PPC64_TOCSAVE.
(Target_powerpc::Scan::global): Likewise.
(Target_powerpc::Relocate::relocate): Skip r2 save in plt call stub
with tocsave reloc. Replace header tocsave nop with r2 save.
* symtab.h (struct Symbol_location_hash): Make public.
