Nowadays, memory error in rx disassembly is not handled, so if I
start a fresh GDB, and disassemble,
(gdb) set architecture rx
The target architecture is assumed to be rx
(gdb) disassemble 0x0,+4
Dump of assembler code from 0x0 to 0x4:
0x00000000: brk
0x00000001: brk
0x00000002: brk
0x00000003: brk
the output is wrong. This patch adds code to call dis->memory_error_func
on memory error, and longjmp to print_insn_rx. With this patch applied,
(gdb) set architecture rx
The target architecture is assumed to be rx
(gdb) disassemble 0,+4
Dump of assembler code from 0x0 to 0x4:
0x00000000: Cannot access memory at address 0x0
opcodes:
2016-12-12 Yao Qi <yao.qi@linaro.org>
* rx-dis.c: Include <setjmp.h>
(struct private): New.
(rx_get_byte): Check return value of read_memory_func, and
call memory_error_func and OPCODES_SIGLONGJMP on error.
(print_insn_rx): Call OPCODES_SIGSETJMP.
Nowadays, memory error in rl78 disassembly is not handled, so if I
start a fresh GDB, and disassemble,
(gdb) set architecture rl78
The target architecture is assumed to be rl78
(gdb) disassemble 0x0,+4
Dump of assembler code from 0x0 to 0x4:
0x00000000: nop
0x00000001: nop
0x00000002: nop
0x00000003: nop
the output is wrong. This patch adds code to call dis->memory_error_func
on memory error, and longjmp to print_insn_rl78_common. With this
patch applied,
(gdb) set architecture rl78
The target architecture is assumed to be rl78
(gdb) disassemble 0,+4
Dump of assembler code from 0x0 to 0x4:
0x00000000: Cannot access memory at address 0x0
opcodes:
2016-12-12 Yao Qi <yao.qi@linaro.org>
* rl78-dis.c: Include <setjmp.h>.
(struct private): New.
(rl78_get_byte): Check return value of read_memory_func, and
call memory_error_func and OPCODES_SIGLONGJMP on error.
(print_insn_rl78_common): Call OPCODES_SIGJMP.
This code has never been used throughout the repository history, and
likely not before either, as due to the assymetry of MIPS16 instruction
set encoding there are no 32-bit shift operations having their immediate
shift count placed in the position of the usual `rx' instruction field.
gas/
* config/tc-mips.c (mips16_macro_build) <'>'>: Remove case.
include/
* opcode/mips.h: Remove references to `>' operand code.
opcodes/
* mips16-opc.c (decode_mips16_operand) <'>'>: Remove cases.
Make the `e' operand code used with raw EXTEND instructions use the
hexadecimal rather than decimal format, for consistency with what is
actually produced by code in `print_insn_mips16' dedicated to EXTEND
disassembly. Due to that special handling the operand code is only
interpreted for assembly however, which accepts either format either
way, so there is no functional change here.
opcodes/
* mips16-opc.c (decode_mips16_operand) <'e'>: Use HINT rather
than UINT.
gas/
* testsuite/gas/mips/mips16-extend.d: New test.
* testsuite/gas/mips/mips16-extend.s: New test source.
* testsuite/gas/mips/mips.exp: Run the new test.
Use a tab rather than a space to separate `extend' and its uninterpreted
argument output, like with regular instructions. Separate hexadecimal
halves of undecoded extended instructions output with a space instead of
presenting them concatenated.
opcodes/
* mips-dis.c (print_insn_mips16): Use a tab rather than a space
to separate `extend' and its uninterpreted argument output.
Separate hexadecimal halves of undecoded extended instructions
output.
binutils/
* testsuite/binutils-all/mips/mips16-extend-noinsn.d: New test.
* testsuite/binutils-all/mips/mips16-extend-noinsn.s: New test
source.
* testsuite/binutils-all/mips/mips.exp: Run the new test.
Complement commit dd8b7c222e ("MIPS: mips16e jalrc/jrc opcodes"),
<https://sourceware.org/ml/binutils/2005-07/msg00349.html>, and stop the
disassembler making a delay-slot adjustment for PC-relative operations
following either MIPS16e compact jumps, or undefined RR/J(AL)R(C)
encodings that have the `l' (link) and `ra' (source register is `ra')
bits set both at a time. Adjust code description for accuracy. Add a
suitable test case.
opcodes/
* mips-dis.c (print_mips16_insn_arg): Avoid delay-slot
adjustment for PC-relative operations following MIPS16e compact
jumps or undefined RR/J(AL)R(C) encodings.
binutils/
* testsuite/binutils-all/mips/mips16-pcrel.d: New test.
* testsuite/binutils-all/mips/mips16-pcrel.s: New test source.
* testsuite/binutils-all/mips/mips.exp: Run the new test.
Fix a commit c2c4ff8d52 ("[AArch64] Add ARMv8.3 FCMLA and FCADD
instructions") build regression:
cc1: warnings being treated as errors
.../opcodes/aarch64-dis.c: In function 'aarch64_ext_sve_addr_rr_lsl':
.../opcodes/aarch64-dis.c:1324: error: declaration of 'index' shadows a global declaration
/usr/include/string.h:303: error: shadowed declaration is here
make[4]: *** [aarch64-asm.lo] Error 1
in a way following commit 91d6fa6a03 ("Add -Wshadow to the gcc command
line options used when compiling the binutils.").
opcodes/
* aarch64-asm.c (aarch64_ins_reglane): Rename `index' local
variable to `reglane_index'.
I got a report of a gdb crash for vle and further investigation showed an
attempt to disassemble an invalid memory range. I tracked the crash down
to the code in get_powerpc_dialect, where we fail to make sure we have a
valid section pointer before dereferencing it.
There is no such problem for rs6000-based disassembling.
opcodes/ChangeLog:
2016-12-08 Luis Machado <lgustavo@codesourcery.com>
* ppc-dis.c (get_powerpc_dialect): Check NULL info->section.
Add support for VCMLA and VCADD advanced SIMD complex number instructions.
The command line option is -march=armv8.3-a+fp16+simd for enabling all
instructions.
In arm-dis.c the formatting syntax was abused a bit to select between
0 vs 90 or 180 vs 270 or 90 vs 270 based on a bit value instead of
duplicating entries in the opcode table.
gas/
* config/tc-arm.c (do_vcmla, do_vcadd): Define.
(neon_scalar_for_vcmla): Define.
(enum operand_parse_code): Add OP_IROT1 and OP_IROT2.
(NEON_ENC_TAB): Add DDSI and QQSI variants.
(insns): Add vcmla and vcadd.
* testsuite/gas/arm/armv8_3-a-simd.d: New.
* testsuite/gas/arm/armv8_3-a-simd.s: New.
* testsuite/gas/arm/armv8_3-a-simd-bad.d: New.
* testsuite/gas/arm/armv8_3-a-simd-bad.l: New.
* testsuite/gas/arm/armv8_3-a-simd-bad.s: New.
opcodes/
* arm-dis.c (coprocessor_opcodes): Add vcmla and vcadd.
(print_insn_coprocessor): Add 'V' format for neon D or Q regs.
This patch fixes:
- fpus and fpud are swaped.
- quarkse_em doesn't include FPX extensions.
- auto guessed opcode mechanism may ignore the option passed via -M<feature> option.
opcodes/
2016-11-29 Claudiu Zissulescu <claziss@synopsys.com>
* arc-dis.c (is_compatible_p): Remove function.
(skip_this_opcode): Don't add any decoding class to decode list.
Remove warning.
(find_format_from_table): Go through all opcodes, and warn if we
use a guessed mnemonic.
binutils/
2016-11-29 Claudiu Zissulescu <claziss@synopsys.com>
* testsuite/binutils-all/arc/objdump.exp (Warning test): Update
test.
While decoding 32-bit XOP instructions, 64 bit registers names are printed.
This patch fixes this by ignoring REX_B bit in 32-bit mode.
opcodes/
PR binutils/20637
* i386-dis.c (get_valid_dis386): Ignore REX_B for 32-bit XOP
instructions.
gas/
PR binutils/20637
* testsuite/gas/i386/xop32reg.d: New file.
* testsuite/gas/i386/xop32reg.s: New file.
* testsuite/gas/i386/i386.exp: Run new test.
When the assembler finds an instruction which is part of a higher
opcode architecture it bumps the current opcode architecture. For
example:
$ echo "mwait" | as -bump
{standard input}: Assembler messages:
{standard input}:1: Warning: architecture bumped from "v6" to "v9m" on "mwait"
However, when two instructions pertaining to the same opcode
architecture but associated to different SPARC hardware capabilities
are found in the input stream, and no GAS architecture is specified in
the command line, the assembler bangs:
$ echo "mwait; wr %g0,%g1,%mcdper" | as -bump
{standard input}: Assembler messages:
{standard input}:1: Warning: architecture bumped from "v6" to "v9m" on "mwait"
{standard input}:1: Error: Hardware capability "sparc5" not enabled for "wr".
... and it should'nt, as WRMCDPER pertains to the same architecture
level than MWAIT.
This patch fixes this by extending the definition of sparc opcode
architectures to contain a set of hardware capabilities and making the
assembler to take these capabilities into account when updating the
set of allowed hwcaps when an architecture bump is triggered by some
instruction.
This way, hwcaps associated to architecture levels are maintained in
opcodes, while the assembler keeps the flexibiity of defining GAS
architectures including additional hwcaps (like -Asparcfmaf or the
v8plus* variants).
A test covering this failure case is included.
gas/ChangeLog:
2016-11-22 Jose E. Marchesi <jose.marchesi@oracle.com>
* config/tc-sparc.c: Move HWS_* and HWS2_* definitions to
opcodes/sparc-opc.c.
(sparc_arch): Clarify the new role of the hwcap_allowed and
hwcap2_allowed fields.
(sparc_arch_table): Remove HWS_* and HWS2_* instances from
hwcap_allowed and hwcap2_allowed respectively.
(md_parse_option): Include the opcode arch hwcaps when processing
-A.
(sparc_ip): Use the current opcode arch hwcaps to update
hwcap_allowed, as well of the hwcaps of the instruction triggering
the bump.
* testsuite/gas/sparc/hwcaps-bump.s: New file.
* testsuite/gas/sparc/hwcaps-bump.l: Likewise.
* testsuite/gas/sparc/sparc.exp (gas_64_check): Run tests in
hwcaps-bump.
include/ChangeLog:
2016-11-22 Jose E. Marchesi <jose.marchesi@oracle.com>
* opcode/sparc.h (sparc_opcode_arch): New fields hwcaps and
hwcaps2.
opcodes/ChangeLog:
2016-11-22 Jose E. Marchesi <jose.marchesi@oracle.com>
* sparc-opc.c (HWS_V8): Definition moved from
gas/config/tc-sparc.c.
(HWS_V9): Likewise.
(HWS_VA): Likewise.
(HWS_VB): Likewise.
(HWS_VC): Likewise.
(HWS_VD): Likewise.
(HWS_VE): Likewise.
(HWS_VV): Likewise.
(HWS_VM): Likewise.
(HWS2_VM): Likewise.
(sparc_opcode_archs): Initialize hwcaps and hwcaps2 fields of
existing entries.
Add support for FCMLA and FCADD complex arithmetic SIMD instructions.
FCMLA has an indexed element variant where the index range has to be
treated specially because a complex number takes two elements and the
indexed vector size depends on the other operands.
These complex number SIMD instructions are part of ARMv8.3
https://community.arm.com/groups/processors/blog/2016/10/27/armv8-a-architecture-2016-additions
include/
2016-11-18 Szabolcs Nagy <szabolcs.nagy@arm.com>
* opcode/aarch64.h (enum aarch64_opnd): Add AARCH64_OPND_IMM_ROT1,
AARCH64_OPND_IMM_ROT2, AARCH64_OPND_IMM_ROT3.
(enum aarch64_op): Add OP_FCMLA_ELEM.
opcodes/
2016-11-18 Szabolcs Nagy <szabolcs.nagy@arm.com>
* aarch64-tbl.h (QL_V3SAMEHSD_ROT, QL_ELEMENT_ROT): Define.
(aarch64_feature_simd_v8_3, SIMD_V8_3): Define.
(aarch64_opcode_table): Add fcmla and fcadd.
(AARCH64_OPERANDS): Add IMM_ROT{1,2,3}.
* aarch64-asm.h (aarch64_ins_imm_rotate): Declare.
* aarch64-asm.c (aarch64_ins_imm_rotate): Define.
* aarch64-dis.h (aarch64_ext_imm_rotate): Declare.
* aarch64-dis.c (aarch64_ext_imm_rotate): Define.
* aarch64-opc.h (enum aarch64_field_kind): Add FLD_rotate{1,2,3}.
* aarch64-opc.c (fields): Add FLD_rotate{1,2,3}.
(operand_general_constraint_met_p): Rotate and index range check.
(aarch64_print_operand): Handle rotate operand.
* aarch64-asm-2.c: Regenerate.
* aarch64-dis-2.c: Likewise.
* aarch64-opc-2.c: Likewise.
gas/
2016-11-18 Szabolcs Nagy <szabolcs.nagy@arm.com>
* config/tc-aarch64.c (parse_operands): Handle AARCH64_OPND_IMM_ROT*.
* testsuite/gas/aarch64/advsimd-armv8_3.d: New.
* testsuite/gas/aarch64/advsimd-armv8_3.s: New.
* testsuite/gas/aarch64/illegal-fcmla.s: New.
* testsuite/gas/aarch64/illegal-fcmla.l: New.
* testsuite/gas/aarch64/illegal-fcmla.d: New.
Add support for system registers introduced in ARMv8.3
for pointer authentication.
opcodes/
2016-11-11 Szabolcs Nagy <szabolcs.nagy@arm.com>
* aarch64-opc.c (aarch64_sys_regs): Add apiakeylo_el1, apiakeyhi_el1,
apibkeylo_el1, apibkeyhi_el1, apdakeylo_el1, apdakeyhi_el1,
apdbkeylo_el1, apdbkeyhi_el1, apgakeylo_el1 and apgakeyhi_el1.
(aarch64_sys_reg_supported_p): Add feature test for new registers.
gas/
2016-11-11 Szabolcs Nagy <szabolcs.nagy@arm.com>
* testsuite/gas/aarch64/sysreg-3.s: New.
* testsuite/gas/aarch64/sysreg-3.d: New.
* testsuite/gas/aarch64/illegal-sysreg-3.l: New.
* testsuite/gas/aarch64/illegal-sysreg-3.d: New.
This patch adds support for a subset of the ARMv8.3 pointer authentication
instructions: XPACLRI, PACIA1716, PACIB1716, AUTIA1716, AUTIA1716, PACIAZ,
PACIASP, PACIBZ, PACISP, AUTIAZ, AUTIASP, AUTIBZ, AUTIBSP.
These are aliases to HINT #0x7, HINT #0x8, HINT #0xa, HINT #0xc, HINT #0xe,
HINT #0x18, HINT #0x19, ..., HINT #0x1f respectively.
For more details about pointer authentication in ARMv8.3 see
https://community.arm.com/groups/processors/blog/2016/10/27/armv8-a-architecture-2016-additions
opcodes/
2016-11-11 Szabolcs Nagy <szabolcs.nagy@arm.com>
* aarch64-tbl.h (aarch64_feature_v8_3, ARMV8_3, V8_3_INSN): New.
(arch64_opcode_table): Add xpaclri, pacia1716, pacib1716, autia1716,
autib1716, paciaz, paciasp, pacibz, pacibsp, autiaz, autiasp, autibz,
autibsp.
* aarch64-asm-2.c: Regenerate.
* aarch64-dis-2.c: Regenerate.
gas/
2016-11-11 Szabolcs Nagy <szabolcs.nagy@arm.com>
* testsuite/gas/aarch64/system-3.s: New.
* testsuite/gas/aarch64/system-3.d: New.
* testsuite/gas/aarch64/system.d: Update expected output.
Some ARMv8.3 pointer authentication instructions are encoded as HINT aliases,
so to allow more instruction aliases in the generator, max_num_aliases is
increased from 16 to 32.
opcodes/
2016-11-11 Szabolcs Nagy <szabolcs.nagy@arm.com>
* aarch64-gen.c (find_alias_opcode): Increase max_num_aliases to 32.
AVX512F vmovq doesn't support masking. We can't swap register operand
in AVX512F vmovq with Reg64 since Reg64 != RegXMM. This patch merges
AVX512F vmovq.
* i386-opc.tbl: Merge AVX512F vmovq.
Remove the THREE_BYTE_0F7A entry which is leftover from SSE5.
PR binutils/20701
* i386-dis.c (THREE_BYTE_0F7A): Removed.
(dis386_twobyte): Don't use THREE_BYTE_0F7A.
(three_byte_table): Remove THREE_BYTE_0F7A.
Since Bad_Opcode and FGRPd9_2 were the same in i386-dis.c, all
Bad_Opcode entries in float_reg were displaced as FGRPd9_2. This
patch adds an entry for Bad_Opcode in fgrps to avoid treating it
as FGRPd9_2.
gas/
PR binutils/20775
* testsuite/gas/i386/i386.exp: Run fpu-bad.
* testsuite/gas/i386/fpu-bad.d: New file.
* testsuite/gas/i386/fpu-bad.s: Likewise.
opcodes/
PR binutils/20775
* i386-dis.c (FGRPd9_2): Replace 0 with 1.
(FGRPd9_4): Replace 1 with 2.
(FGRPd9_5): Replace 2 with 3.
(FGRPd9_6): Replace 3 with 4.
(FGRPd9_7): Replace 4 with 5.
(FGRPda_5): Replace 5 with 6.
(FGRPdb_4): Replace 6 with 7.
(FGRPde_3): Replace 7 with 8.
(FGRPdf_4): Replace 8 with 9.
(fgrps): Add an entry for Bad_Opcode.
When we match against an address type operand within an instruction it
is important that we match exactly the right address type operand early
on, during the opcode selection phase. If we wait until the operand
insertion phase to check that we have the correct address operand, then
it is too late to select an alternative opcode. This becomes important
only when we have multiple opcodes with the same mnemonic, and operand
lists that differ only in the type of the address operands.
This commit fixes this issue, and adds some example instructions that
require this issue to be fixed (the instructions are identical except
for the address type operand).
gas/ChangeLog:
* config/tc-arc.c (find_opcode_match): Use insert function to
validate matching address type operands.
* testsuite/gas/arc/nps400-10.d: New file.
* testsuite/gas/arc/nps400-10.s: New file.
opcodes/ChangeLog:
* arc-opc.c (arc_flag_operands): Add F_DI14.
(arc_flag_classes): Add C_DI14.
* arc-nps400-tbl.h: Add new exc instructions.
The current handling for arc instructions longer than 32-bits is all
handled as a special case in both the assembler and disassembler.
The problem with this approach is that it leads to code duplication,
selecting a long instruction is exactly the same process as selecting a
short instruction, except over more bits, in both cases we select based
on bit comparison, and initial operand insertion and extraction.
This commit unifies both the long and short instruction worlds,
converting the core opcodes library from being largely 32-bit focused,
to being largely 64-bit focused.
The changes are, on the whole, not too much. There's obviously a lot of
type changes but otherwise the bulk of the code just works. Most of the
actual functional changes are to code that previously handled the longer
48 or 64 bit instructions. The insert/extract handlers for these have
now been brought into line with the short instruction insert/extract
handlers.
All of the special case handling code that was previously added has now
been removed again. Overall, this commit reduces the amount of code in
the arc assembler and disassembler.
gas/ChangeLog:
* config/tc-arc.c (struct arc_insn): Change type of insn field.
(md_number_to_chars_midend): Support 6- and 8-byte values.
(emit_insn0): Update debug output.
(find_opcode_match): Likewise.
(build_fake_opcode_hash_entry): Delete.
(find_special_case_long_opcode): Delete.
(find_special_case): Remove long format special case handling.
(insert_operand): Change instruction type and update debug print
format.
(assemble_insn): Change instruction type, update debug print
formats, and remove unneeded assert.
include/ChangeLog:
* opcode/arc.h (struct arc_opcode): Change type of opcode and mask
fields.
(struct arc_long_opcode): Delete.
(struct arc_operand): Change types for insert and extract
handlers.
opcodes/ChangeLog:
* arc-dis.c (struct arc_operand_iterator): Remove all fields
relating to long instruction processing, add new limm field.
(OPCODE): Rename to...
(OPCODE_32BIT_INSN): ...this.
(OPCODE_AC): Delete.
(skip_this_opcode): Handle different instruction lengths, update
macro name.
(special_flag_p): Update parameter type.
(find_format_from_table): Update for more instruction lengths.
(find_format_long_instructions): Delete.
(find_format): Update for more instruction lengths.
(arc_insn_length): Likewise.
(extract_operand_value): Update for more instruction lengths.
(operand_iterator_next): Remove code relating to long
instructions.
(arc_opcode_to_insn_type): New function.
(print_insn_arc):Update for more instructions lengths.
* arc-ext.c (extInstruction_t): Change argument type.
* arc-ext.h (extInstruction_t): Change argument type.
* arc-fxi.h: Change type unsigned to unsigned long long
extensively throughout.
* arc-nps400-tbl.h: Add long instructions taken from
arc_long_opcodes table in arc-opc.c.
* arc-opc.c: Update parameter types on insert/extract handlers.
(arc_long_opcodes): Delete.
(arc_num_long_opcodes): Delete.
(arc_opcode_len): Update for more instruction lengths.
highbyte and lowbyte actually refer to the low byte and the high
byte respectively, but are used consistently in this swapped
order. This commit swaps them round so that highbyte refers to the
high byte and lowbyte refers to the low byte.
There should be no functional change after this commit.
opcodes/ChangeLog:
* arc-dis.c (print_insn_arc): Swap highbyte and lowbyte.
In preparation for moving to a world where arc instructions can be 2, 4,
6, or 8 bytes in length, replace the ARC_SHORT macro (which is either
true of false) with an arc_opcode_len function that returns a length in
bytes.
There should be no functional change after this commit.
gas/ChangeLog:
* config/tc-arc.c (assemble_insn): Replace use of ARC_SHORT with
arc_opcode_len.
include/ChangeLog:
* opcode/arc.h (arc_opcode_len): Declare.
(ARC_SHORT): Delete.
opcodes/ChangeLog:
* arc-dis.c (find_format_from_table): Replace use of ARC_SHORT
with arc_opcode_len.
(find_format_long_instructions): Likewise.
* arc-opc.c (arc_opcode_len): New function.
A few masks were incorrect, there were opcode bits that lives outside of
the instruction mask, the effected instructions are decode1, zncv, and
efabgt.
Previously these instructions would assemble and disassemble correctly,
and a correctly encoded binary should behave no differently. The only
difference would be seen in a few incorrectly encoded binaries,
previously these would have decoded to the above instructions, while now
they will not.
opcodes/ChangeLog:
* arc-nps400-tbl.h: Fix some instruction masks.
The REG_82 entry in x86 disassembler is for opcode 0x83, not opcode
0x82.
* i386-dis.c (REG_82): Renamed to ...
(REG_83): This.
(dis386): Updated.
(reg_table): Likewise.
In 32-bit, the REX_B bit in the 3-byte VEX prefix is ignored and the
the highest bit in VEX.vvvv is either 1 or ignored. In 64-bit, we
need to check invalid mask registers.
gas/
PR binutis/20705
* testsuite/gas/i386/i386.exp: Run x86-64-opcode-bad.
* testsuite/gas/i386/x86-64-opcode-bad.d: New file.
* testsuite/gas/i386/x86-64-opcode-bad.s: Likewise.
opcodes/
PR binutis/20705
* i386-dis.c (get_valid_dis386): Ignore the REX_B bit and
the highest bit in VEX.vvvv for the 3-byte VEX prefix in
32-bit mode. Don't check vex.register_specifier in 32-bit
mode.
(OP_E_register): Check invalid mask registers.
(OP_G): Likewise.
(OP_VEX): Likewise.
