The following relocation types were added to GCC/binutils:
ARC_JLI_SECTOFF is a relocation type in Metaware that is now used by
GCC as well to adjust the index of function calls to functions with
attribute jli_call_always.
bfd/
2017-07-19 Claudiu Zissulescu <claziss@synopsys.com>
John Eric Martin <John.Martin@emmicro-us.com>
* bfd-in2.h: Regenerate.
* libbfd.h: Regenerate.
* elf32-arc.c (JLI): Define.
* reloc.c: Add JLI relocations.
gas/
2017-07-19 Claudiu Zissulescu <claziss@synopsys.com>
* testsuite/gas/arc/jli-1.d: New file.
* testsuite/gas/arc/jli-1.s: Likewise.
* testsuite/gas/arc/taux.d: Update for jli_base.
include/
2017-07-19 Claudiu Zissulescu <claziss@synopsys.com>
John Eric Martin <John.Martin@emmicro-us.com>
* elf/arc-reloc.def: Add JLI relocs howto.
* opcode/arc-func.h (replace_jli): New function.
ld/
2017-07-19 Claudiu Zissulescu <claziss@synopsys.com>
John Eric Martin <John.Martin@emmicro-us.com>
* emulparams/arcelf.sh (JLI_START_TABLE): Define.
* scripttempl/elfarc.sc: Handle jlitab section.
* scripttempl/elfarcv2.sc: Likewise.
* testsuite/ld-arc/arc.exp: Add JLI test.
* testsuite/ld-arc/jli-script.ld: New file.
* testsuite/ld-arc/jli-simple.dd: Likewise.
* testsuite/ld-arc/jli-simple.rd: Likewise.
* testsuite/ld-arc/jli-simple.s: Likewise.
* testsuite/ld/testsuite/ld-arc/jli-overflow.s: Likewise.
* testsuite/ld/testsuite/ld-arc/jli-overflow.d: Likewise.
* testsuite/ld/testsuite/ld-arc/jli-overflow.err: Likewise.
opcode/
2017-07-19 Claudiu Zissulescu <claziss@synopsys.com>
John Eric Martin <John.Martin@emmicro-us.com>
* arc-opc.c (UIMM10_6_S_JLIOFF): Define.
(UIMM3_23): Adjust accordingly.
* arc-regs.h: Add/correct jli_base register.
* arc-tbl.h (jli_s): Likewise.
PR gas/21683
include * opcode/avr.h (AVR_INSN): Add one for __gcc_isr.
gas * doc/c-avr.texi (AVR Options) <-mgcc-isr>: Document it.
(AVR Pseudo Instructions): New node.
* config/tc-avr.h (md_pre_output_hook): Define to avr_pre_output_hook.
(md_undefined_symbol): Define to avr_undefined_symbol.
(avr_pre_output_hook, avr_undefined_symbol): New protos.
* config/tc-avr.c (struc-symbol.h): Include it.
(ISR_CHUNK_Done, ISR_CHUNK_Prologue, ISR_CHUNK_Epilogue): New enums.
(avr_isr, avr_gccisr_opcode)
(avr_no_sreg_hash, avr_no_sreg): New static variables.
(avr_opt_s) <have_gccisr>: Add field.
(avr_opt): Add initializer for have_gccisr.
(enum options) <OPTION_HAVE_GCCISR>: Add enum.
(md_longopts) <"mgcc-isr">: Add entry.
(md_show_usage): Document -mgcc-isr.
(md_parse_option) [OPTION_HAVE_GCCISR]: Handle it.
(md_undefined_symbol): Remove.
(avr_undefined_symbol, avr_pre_output_hook): New fuctions.
(md_begin) <avr_no_sreg_hash, avr_gccisr_opcode>: Initialize them.
(avr_operand) <pregno>: Add argument and set *pregno if function
is called for a register constraint.
[N]: Handle constraint.
(avr_operands) <avr_operand>: Pass 5th parameter to calls.
[avr_opt.have_gccisr]: Call avr_update_gccisr. Call
avr_gccisr_operands instead of avr_operands.
(avr_update_gccisr, avr_emit_insn, avr_patch_gccisr_frag)
(avr_gccisr_operands, avr_check_gccisr_done): New static functions.
* testsuite/gas/avr/gccisr-01.d: New test.
* testsuite/gas/avr/gccisr-01.s: New test.
* testsuite/gas/avr/gccisr-02.d: New test.
* testsuite/gas/avr/gccisr-02.s: New test.
* testsuite/gas/avr/gccisr-03.d: New test.
* testsuite/gas/avr/gccisr-03.s: New test.
Correct a commit 7d64c587c1 ("Add support for the MIPS eXtended
Physical Address (XPA) ASE.") bug, causing XPA base and Virtualization
ASE instructions to be wrongly always enabled with the selection of the
MIPS32r2 or higher ISA.
For example this source assembles successfully as shown below:
$ cat xpa.s
mfhc0 $2, $1
$ as -32 -mips32 -o xpa.o xpa.s
xpa.s: Assembler messages:
xpa.s:1: Error: opcode not supported on this processor: mips32 (mips32) `mfhc0 $2,$1'
$ as -32 -mips32r2 -o xpa.o xpa.s
$ objdump -d xpa.o
xpa.o: file format elf32-tradbigmips
Disassembly of section .text:
00000000 <.text>:
0: 40420800 mfhc0 v0,c0_random
...
$
To address this issue remove the I33 (INSN_ISA32R2) marking from all XPA
instructions in the opcode table. Additionally, for XPA Virtualization
ASE instructions implement an XPAVZ (ASE_XPA_VIRT) combination ASE flag
and use it in place of IVIRT|XPA (ASE_VIRT|ASE_XPA).
Now the same source is correctly rejected unless the `-mxpa' option is
also used:
$ as -32 -mips32r2 -o xpa.o xpa.s
xpa.s: Assembler messages:
xpa.s:1: Error: opcode not supported on this processor: mips32r2 (mips32r2) `mfhc0 $2,$1'
$ as -32 -mips32r2 -mxpa -o xpa.o xpa.s
$
Add test cases for XPA base and XPA Virtualization ASE instructions.
Parts of this change by Andrew Bennett.
include/
* opcode/mips.h (ASE_XPA_VIRT): New macro.
opcodes/
* mips-dis.c (mips_calculate_combination_ases): Handle the
ASE_XPA_VIRT flag.
(parse_mips_ase_option): New function.
(parse_mips_dis_option): Factor out ASE option handling to the
new function. Call `mips_calculate_combination_ases'.
* mips-opc.c (XPAVZ): New macro.
(mips_builtin_opcodes): Correct ISA and ASE flags for "mfhc0",
"mfhgc0", "mthc0" and "mthgc0".
gas/
* config/tc-mips.c (mips_set_ase): Handle the ASE_XPA_VIRT flag.
* testsuite/gas/mips/xpa.d: Remove `xpa' from `-M' in `objdump'
flags. Add `-mvirt' to `as' flags.
* testsuite/gas/mips/xpa-err.d: New test.
* testsuite/gas/mips/xpa-virt-err.d: New test.
* testsuite/gas/mips/xpa-err.l: New stderr output.
* testsuite/gas/mips/xpa-virt-err.l: New stderr output.
* testsuite/gas/mips/xpa-err.s: New test source.
* testsuite/gas/mips/xpa-virt-err.s: New test source.
* testsuite/gas/mips/mips.exp: Run the new tests.
binutils/
* testsuite/binutils-all/mips/mips-xpa-virt-1.d: New test.
* testsuite/binutils-all/mips/mips-xpa-virt-2.d: New test.
* testsuite/binutils-all/mips/mips-xpa-virt-3.d: New test.
* testsuite/binutils-all/mips/mips-xpa-virt-4.d: New test.
* testsuite/binutils-all/mips/mips-xpa-virt.s: New test source.
* testsuite/binutils-all/mips/mips.exp: Run the new tests.
This patch add assembler and disassembler support for new Dot Product
Extension.
The support can be enabled through the new "+dotprod" extension.
include/
* opcode/arm.h (FPU_NEON_EXT_DOTPROD): New macro.
(FPU_ARCH_DOTPROD_NEON_VFP_ARMV8): New macro.
gas/
* config/tc-arm.c (fpu_neon_ext_dotprod): New variable.
(neon_scalar_for_mul): Improve comments.
(do_neon_dotproduct): New function to encode Dot Product instructions.
(do_neon_dotproduct_s): Wrapper function for signed Dot Product
instructions.
(do_neon_dotproduct_u): Wrapper function for unsigned Dot Product
instructions.
(insns): New entries for vsdot and vudot.
(arm_extensions): New entry for "dotprod".
* doc/c-arm.texi: Document new "dotprod" extension.
* testsuite/gas/arm/dotprod.s: New test source.
* testsuite/gas/arm/dotprod-illegal.s: New test source.
* testsuite/gas/arm/dotprod.d: New test.
* testsuite/gas/arm/dotprod-thumb2.d: New test.
* testsuite/gas/arm/dotprod-illegal.d: New test.
* testsuite/gas/arm/dotprod-legacy-arch.d: New test.
* testsuite/gas/arm/dotprod-illegal.l: New error file.
* testsuite/gas/arm/dotprod-legacy-arch.l: New error file.
opcodes/
* arm-dis.c (coprocessor_opcodes): New entries for vsdot and vudot.
Add support for the Imagination interAptiv MR2 MIPS32r3 processor with
the MIPS16e2 ASE as per documentation, including in particular:
1. Support for implementation-specific interAptiv MR2 COPYW and UCOPYW
MIPS16e2 instructions[1], for assembly and disassembly,
2. Support for implementation-specific interAptiv MR2 SAVE and RESTORE
regular MIPS instructions[2], for assembly and disassembly,
3. ELF binary file annotation for the interAptiv MR2 MIPS architecture
extension.
4. Support for interAptiv MR2 architecture selection for assembly, in
the form of the `-march=interaptiv-mr2' command-line option and its
corresponding `arch=interaptiv-mr2' setting for the `.set' and
`.module' pseudo-ops.
5. Support for interAptiv MR2 architecture selection for disassembly,
in the form of the `mips:interaptiv-mr2' target architecture, for
use e.g. with the `-m' command-line option for `objdump'.
Parts of this change by Matthew Fortune and Andrew Bennett.
References:
[1] "MIPS32 interAptiv Multiprocessing System Software User's Manual",
Imagination Technologies Ltd., Document Number: MD00904, Revision
02.01, June 15, 2016, Section 24.3 "MIPS16e2 Implementation Specific
Instructions", pp. 878-883
[2] same, Chapter 25 "Implementation-specific Instructions", pp. 911-917
include/
* elf/mips.h (E_MIPS_MACH_IAMR2): New macro.
(AFL_EXT_INTERAPTIV_MR2): Likewise.
* opcode/mips.h: Document new operand codes defined.
(INSN_INTERAPTIV_MR2): New macro.
(INSN_CHIP_MASK): Adjust accordingly.
(CPU_INTERAPTIV_MR2): New macro.
(cpu_is_member) <CPU_INTERAPTIV_MR2>: New case.
(MIPS16_ALL_ARGS): Rename to...
(MIPS_SVRS_ALL_ARGS): ... this.
(MIPS16_ALL_STATICS): Rename to...
(MIPS_SVRS_ALL_STATICS): ... this.
bfd/
* archures.c (bfd_mach_mips_interaptiv_mr2): New macro.
* cpu-mips.c (I_interaptiv_mr2): New enum value.
(arch_info_struct): Add "mips:interaptiv-mr2" entry.
* elfxx-mips.c (_bfd_elf_mips_mach) <E_MIPS_MACH_IAMR2>: New
case.
(mips_set_isa_flags) <bfd_mach_mips_interaptiv_mr2>: Likewise.
(bfd_mips_isa_ext) <bfd_mach_mips_interaptiv_mr2>: Likewise.
(print_mips_isa_ext) <AFL_EXT_INTERAPTIV_MR2>: Likewise.
(mips_mach_extensions): Add `bfd_mach_mipsisa32r3' and
`bfd_mach_mips_interaptiv_mr2' entries.
* bfd-in2.h: Regenerate.
opcodes/
* mips-formats.h (INT_BIAS): New macro.
(INT_ADJ): Redefine in INT_BIAS terms.
* mips-dis.c (mips_arch_choices): Add "interaptiv-mr2" entry.
(mips_print_save_restore): New function.
(print_insn_arg) <OP_SAVE_RESTORE_LIST>: Update comment.
(validate_insn_args) <OP_SAVE_RESTORE_LIST>: Remove `abort'
call.
(print_insn_args): Handle OP_SAVE_RESTORE_LIST.
(print_mips16_insn_arg): Call `mips_print_save_restore' for
OP_SAVE_RESTORE_LIST handling, factored out from here.
* mips-opc.c (decode_mips_operand) <'-'> <'m'>: New case.
(RD_31, RD_SP, WR_SP, MOD_SP, IAMR2): New macros.
(mips_builtin_opcodes): Add "restore" and "save" entries.
* mips16-opc.c (decode_mips16_operand) <'n', 'o'>: New cases.
(IAMR2): New macro.
(mips16_opcodes): Add "copyw" and "ucopyw" entries.
binutils/
* readelf.c (get_machine_flags) <E_MIPS_MACH_IAMR2>: New case.
(print_mips_isa_ext) <AFL_EXT_INTERAPTIV_MR2>: Likewise.
* NEWS: Mention Imagination interAptiv MR2 processor support.
gas/
* config/tc-mips.c (validate_mips_insn): Handle
OP_SAVE_RESTORE_LIST specially.
(mips_encode_save_restore, mips16_encode_save_restore): New
functions.
(match_save_restore_list_operand): Factor out SAVE/RESTORE
operand insertion into the instruction word or halfword to these
new functions.
(mips_cpu_info_table): Add "interaptiv-mr2" entry.
* doc/c-mips.texi (MIPS Options): Add `interaptiv-mr2' to the
`-march=' argument list.
=== Context ===
This patch is part of a patch series to add support for ARMv8-R
architecture. Its purpose is to add support for ARMv8-R in GAS:
instructions, build attributes and readelf.
=== Patch description ===
Although some differences exist for system registers, from GAS point of
view ARMv8-R supports the same instructions as ARMv8-A Aarch32 state
and a subset of its extensions. This patch therefore introduce a new
feature bit to distinguish the availability of the pan, ras and rdma
extensions between ARMv8-A and ARMv8-R and allow crypto, fp and simd
extensions to be used by ARMv8-R.
Most of the changes are then in the testsuite to (i) rename source files
and error output to be shared between ARMv8-A and ARMv8-R, (ii) rename
files with expected output for ARMv8-A build attributes and (iii) add
new files with expected output for ARMv8-R build attributes.
2017-06-24 Thomas Preud'homme <thomas.preudhomme@arm.com>
binutils/
* readelf.c (arm_attr_tag_CPU_arch): Fill value for ARMv8-R.
gas/
* NEWS: Mention support for ARMv8-R architecture.
* config/tc-arm.c (arm_archs): Add entry for ARMv8-R.
(arm_extensions): Restrict pan, ras and rdma extension to
ARMv8-A and make crypto, fp and simd extensions available to
ARMv8-R.
(cpu_arch_ver): Add entry for ARMv8-R.
(aeabi_set_public_attributes): Update gas_assert for Tag_DIV_use
logic.
* testsuite/gas/arm/armv8-a+fp.s: Rename into ...
* testsuite/gas/arm/armv8-ar+fp.s: This. Remove .arch directive.
* testsuite/gas/arm/armv8-a+fp.d: Specify source to assemble and
architecture to assemble for.
* testsuite/gas/arm/armv8-r+fp.d: New.
* testsuite/gas/arm/armv8-a+simd.s: Rename into ...
* testsuite/gas/arm/armv8-ar+simd.s: This. Remove .arch directive.
* testsuite/gas/arm/armv8-a+simd.d: Specify source to assemble and
architecture to assemble for.
* testsuite/gas/arm/armv8-r+simd.d: New.
* testsuite/gas/arm/armv8-a-bad.s: Rename into ...
* testsuite/gas/arm/armv8-ar-bad.s: This. Remove .arch directive.
* testsuite/gas/arm/armv8-a-bad.l: Rename into ...
* testsuite/gas/arm/armv8-ar-bad.l: This. Decrement line number by 1.
* testsuite/gas/arm/armv8-a-bad.d: Specify source to assemble,
architecture to assemble for and adjust error output file.
* testsuite/gas/arm/armv8-r-bad.d: New.
* testsuite/gas/arm/armv8-a-barrier.s: Rename into ...
* testsuite/gas/arm/armv8-ar-barrier.s: This.
* testsuite/gas/arm/armv8-a-barrier-arm.d: Adjust source.
* testsuite/gas/arm/armv8-a-barrier-thumb.d: Likewise.
* testsuite/gas/arm/armv8-r-barrier-arm.d: New.
* testsuite/gas/arm/armv8-r-barrier-thumb.d: New.
* testsuite/gas/arm/armv8-a-it-bad.s: Rename into ...
* testsuite/gas/arm/armv8-ar-it-bad.s: This. Remove .arch directive.
* testsuite/gas/arm/armv8-a-it-bad.l: Rename into ...
* testsuite/gas/arm/armv8-ar-it-bad.l: This. Decrement line number
by 1.
* testsuite/gas/arm/armv8-a-it-bad.d: Specify source to assemble,
architecture to assemble for and adjust error output file.
* testsuite/gas/arm/armv8-r-it-bad.d: New.
* testsuite/gas/arm/armv8-a.s: Rename into ...
* testsuite/gas/arm/armv8-ar.s: This. Remove .arch directive.
* testsuite/gas/arm/armv8-a.d: Specify source to assemble and
architecture to assemble for.
* testsuite/gas/arm/armv8-r.d: New.
* testsuite/gas/arm/attr-march-armv8-r+crypto.d: New.
* testsuite/gas/arm/attr-march-armv8-r+fp.d: New.
* testsuite/gas/arm/attr-march-armv8-r+simd.d: New.
* testsuite/gas/arm/attr-march-armv8-r.d: New.
* testsuite/gas/arm/crc32.s: Rename into ...
* testsuite/gas/arm/crc32-armv8-ar.s: This.
* testsuite/gas/arm/crc32.d: Rename into ...
* testsuite/gas/arm/crc32-armv8-a.d: This. Specify source to assemble.
* testsuite/gas/arm/crc32-armv8-r.d: New.
* testsuite/gas/arm/crc32-bad.s: Rename into ...
* testsuite/gas/arm/crc32-armv8-ar-bad.s: This.
* testsuite/gas/arm/crc32-bad.d: Rename into ...
* testsuite/gas/arm/crc32-armv8-a-bad.d: This. Specify source to
assemble.
* testsuite/gas/arm/crc32-armv8-r-bad.d: New.
* testsuite/gas/arm/mask_1.s: Rename into ...
* testsuite/gas/arm/mask_1-armv8-ar.s: This.
* testsuite/gas/arm/mask_1.d: Rename into ...
* testsuite/gas/arm/mask_1-armv8-a.d: This. Specify source to
assemble.
* testsuite/gas/arm/mask_1-armv8-r.d: new.
include/
* elf/arm.h (TAG_CPU_ARCH_V8R): New macro.
* opcode/arm.h (ARM_EXT2_V8A): New macro.
(ARM_AEXT2_V8A): Rename into ...
(ARM_AEXT2_V8AR): This.
(ARM_AEXT2_V8A): New macro.
(ARM_AEXT_V8R): New macro.
(ARM_AEXT2_V8R): New macro.
(ARM_ARCH_V8R): New macro.
=== Context ===
This patch is part of a patch series to add support for ARMv8-R
architecture. Its purpose is to remove special casing for ARMv6S-M
autodetection.
=== Motivation ===
Currently, SWI and SVC mnemonics are enabled for ARMv4T and successor
architectures with extra checks in the handler function (do_t_swi) to
give an error message when ARMv6-M is targeted and some more special
casing in aeabi_set_public_attributes. This was made to exclude these
mnemonics for ARMv6-M unless the OS extension is in use.
However this logic is superfluous: there is already code to check
whether an instruction is available based on the feature bit it is part
of and whether the targeted architecture has that feature bit. This
patch aims at removing that unneeded complexity.
=== Patch description ===
The OS extension is already limited to the ARMv6-M architecture so all
this patch does is redefined availability of the ARM_EXT_OS feature bit
to not be present for ARM_ARCH_V6M. ARM_ARCH_V6SM does not need any
change either because it already includes ARM_EXT_OS.
The patch also make sure that the error message that was given by
do_t_swi when SWI/SVC is unavailable is still the same by detecting the
situation in md_assemble.
2017-06-24 Thomas Preud'homme <thomas.preudhomme@arm.com>
gas/
* config/tc-arm.c (arm_ext_v6m): Delete.
(arm_ext_v7m): Delete.
(arm_ext_m): Remove ARM_EXT_OS from the set of feature defined M
profile.
(arm_arch_v6m_only): Delete.
(do_t_swi): Remove special case for ARMv6S-M.
(md_assemble): Display error message previously in do_t_swi when
SVC is not available.
(insns): Guard swi and svc by arm_ext_os for Thumb mode.
(aeabi_set_public_attributes): Remove special case for ARMv6S-M.
include/
* opcode/arm.h (ARM_AEXT_V4TxM): Add ARM_EXT_OS bit to the set.
(ARM_AEXT_V4T): Likewise.
(ARM_AEXT_V5TxM): Likewise.
(ARM_AEXT_V5T): Likewise.
(ARM_AEXT_V6M): Mask off ARM_EXT_OS bit.
=== Context ===
This patch is part of a patch series to add support for ARMv8-R
architecture. Its purpose is to rework the Tag_CPU_arch build attribute
value selection to (i) match architecture or CPU if specified by user
without any need for hack and (ii) match an architecture with all the
features used if in autodetection mode or return an error.
=== Motivation ===
Currently, Tag_CPU_arch build attribute value selection assumes that an
architecture is always a superset of architectures released earlier. As
such, the logic is to browse architectures in chronological order of
release and selecting the Tag_CPU_arch value of the last one to
contribute a feature used[1]/requested[2] not contributed by earlier
architectures.
[1] in case of autodetection mode
[2] otherwise, ie. in case of -mcpu/-march or associated directives
This logic fails the two objectives mentionned in the Context section.
First, due to the assumption it does an architecture can be selected
while not having all the features used/requested which fails the second
objective. Second, not doing an exact match when an architecture or CPU
is selected by the user means the wrong value is chosen when a later
architecture provides a subset of the feature bits of an earlier
architecture. This is the case for the implementation of ARMv8-R (see
later patch).
An added benefit of this patch is that it is possible to easily generate
more consistent build attribute by setting the feature bits from the
architecture matched in aeabi_set_public_attributes in autodetection
mode. This is better done as a separate patch because lots of testcase'
expected results must then be updated accordingly.
=== Patch description ===
The patch changes the main logic for Tag_CPU_arch and
Tag_CPU_arch_profile
values selection to:
- look for an exact match in case an architecture or CPU was specified
on the command line or in a directive
- select the first released architecture that provides a superset of the
feature used in the autodetection case
- select the most featureful architecture in case of -march=all
The array cpu_arch_ver is updated to include all architectures in order
to make the first point work.
Note that when looking for an exact match, the architecture with
selected extension is tried first and then only the architecture. This
is because some architectures are exactly equivalent to an earlier
architecture with its extensions selected. ARMv6S-M (= ARMv6-M + OS
extension) and ARMv6KZ (ARMv6K + security extension) are two such
examples.
Other adjustments are also necessary in aeabi_set_public_attributes to
make this change work.
1) The logic to set Tag_ARM_ISA_use and Tag_THUMB_ISA_use must check the
absence of feature bit used/requested to decide whether to give the
default value for empty files (see EABI attribute defaults test). It was
previously checking that arch == 0 which would only happen if no feature
bit could be matched by any architecture, ie there is no feature bit to
match.
2) A fallback to a superset match must exist when no_cpu_selected ()
returns true. This is because aeabi_set_public_attributes is called
again after relaxation and at this point selected_cpu is set from the
previous execution of that function. There is therefore no way to check
whether the user specified an architecture or CPU.
3) Tag_CPU_arch lines are removed from expected output when the
detected architecture should be pre-ARMv4, since 0 is the Tag_CPU_arch
value for pre-ARMv4 architectures and default value for an absent entry
is 0.
2017-06-21 Thomas Preud'homme <thomas.preudhomme@arm.com>
gas/
* config/tc-arm.c (fpu_any): Defined from FPU_ANY.
(cpu_arch_ver): Add all architectures and sort by release date.
(have_ext_for_needed_feat_p): New.
(get_aeabi_cpu_arch_from_fset): New.
(aeabi_set_public_attributes): Call above function to determine
Tag_CPU_arch and Tag_CPU_arch_profile values. Adapt Tag_ARM_ISA_use
and Tag_THUMB_ISA_use selection logic to check absence of feature bit
accordingly.
* testsuite/gas/arm/attr-march-armv1.d: Fix expected Tag_CPU_arch build
attribute value.
* testsuite/gas/arm/attr-march-armv2.d: Likewise.
* testsuite/gas/arm/attr-march-armv2a.d: Likewise.
* testsuite/gas/arm/attr-march-armv2s.d: Likewise.
* testsuite/gas/arm/attr-march-armv3.d: Likewise.
* testsuite/gas/arm/attr-march-armv3m.d: Likewise.
* testsuite/gas/arm/pr12198-2.d: Likewise.
include/
* opcode/arm.h (FPU_ANY): New macro.
So far we only had an instruction flag which made an arbitrary number
of operands optional. This limits error checking capabilities for
instructions marked that way. With this patch the optparm flag only
allows a single optional parameter and another one is added (optparm2)
allowing 2 optional arguments. Hopefully we won't need more than that
in the future. So far there will be only a single use of optparm2.
gas/ChangeLog:
2017-05-30 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
* config/tc-s390.c (md_gather_operands): Support new optparm2
instruction flag.
include/ChangeLog:
2017-05-30 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
* opcode/s390.h: Add new instruction flags optparm2.
opcodes/ChangeLog:
2017-05-30 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
* s390-dis.c (s390_print_insn_with_opcode): Support new optparm2
instruction flag.
* s390-mkopc.c (main): Recognize the new instruction flag when
parsing instruction list.
The per operand optional flag hasn't been used for quite some time.
Cleanup some remains.
include/ChangeLog:
2017-05-30 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
* opcode/s390.h: Remove S390_OPERAND_OPTIONAL.
gas/ChangeLog:
2017-05-30 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
* config/tc-s390.c (md_gather_operands): Remove code dealing with
S390_OPERAND_OPTIONAL.
It is required to parse instructions like ldb.x.a.di.
include/
2017-05-23 Claudiu Zissulescu <claziss@synopsys.com>
* opcode/arc.h (MAX_INSN_FLGS): Update to 4.
Add MIPS16e2 ASE support as per the architecture specification[1],
including in particular:
1. A new ELF ASE flag to mark MIPS16e2 binaries.
2. MIPS16e2 instruction assembly support, including a relaxation update
to use LUI rather than an LI/SLL instruction pair for loading the
high part of 32-bit addresses.
3. MIPS16e2 instruction disassembly support, including updated rules for
extended forms of instructions that are now subdecoded and therefore
do not alias to the original MIPS16 ISA revision instructions even
for encodings that are not valid in the MIPS16e2 instruction set.
Add `-mmips16e2' and `-mno-mips16e2' GAS command-line options and their
corresponding `mips16e2' and `no-mips16e2' settings for the `.set' and
`.module' pseudo-ops. Control the availability of the MT ASE subset of
the MIPS16e2 instruction set with a combination of these controls and
the preexisting MT ASE controls.
Parts of this change by Matthew Fortune and Andrew Bennett.
References:
[1] "MIPS32 Architecture for Programmers: MIPS16e2 Application-Specific
Extension Technical Reference Manual", Imagination Technologies
Ltd., Document Number: MD01172, Revision 01.00, April 26, 2016
include/
* elf/mips.h (AFL_ASE_MIPS16E2): New macro.
(AFL_ASE_MASK): Adjust accordingly.
* opcode/mips.h: Document new operand codes defined.
(mips_operand_type): Add OP_REG28 enum value.
(INSN2_SHORT_ONLY): Update description.
(ASE_MIPS16E2, ASE_MIPS16E2_MT): New macros.
bfd/
* elfxx-mips.c (print_mips_ases): Handle MIPS16e2 ASE.
opcodes/
* mips-dis.c (mips_arch_choices): Add ASE_MIPS16E2 and
ASE_MIPS16E2_MT flags to the unnamed MIPS16 entry.
(mips_convert_abiflags_ases): Handle the AFL_ASE_MIPS16E2 flag.
(print_insn_arg) <OP_REG28>: Add handler.
(validate_insn_args) <OP_REG28>: Handle.
(print_mips16_insn_arg): Handle MIPS16 instructions that require
32-bit encoding and 9-bit immediates.
(print_insn_mips16): Handle MIPS16 instructions that require
32-bit encoding and MFC0/MTC0 operand decoding.
* mips16-opc.c (decode_mips16_operand) <'>', '9', 'G', 'N', 'O'>
<'Q', 'T', 'b', 'c', 'd', 'r', 'u'>: Add handlers.
(RD_C0, WR_C0, E2, E2MT): New macros.
(mips16_opcodes): Add entries for MIPS16e2 instructions:
GP-relative "addiu" and its "addu" spelling, "andi", "cache",
"di", "ehb", "ei", "ext", "ins", GP-relative "lb", "lbu", "lh",
"lhu", and "lw" instructions, "ll", "lui", "lwl", "lwr", "mfc0",
"movn", "movtn", "movtz", "movz", "mtc0", "ori", "pause",
"pref", "rdhwr", "sc", GP-relative "sb", "sh" and "sw"
instructions, "swl", "swr", "sync" and its "sync_acquire",
"sync_mb", "sync_release", "sync_rmb" and "sync_wmb" aliases,
"xori", "dmt", "dvpe", "emt" and "evpe". Add split
regular/extended entries for original MIPS16 ISA revision
instructions whose extended forms are subdecoded in the MIPS16e2
ISA revision: "li", "sll" and "srl".
binutils/
* readelf.c (print_mips_ases): Handle MIPS16e2 ASE.
* NEWS: Mention MIPS16e2 ASE support.
gas/
* config/tc-mips.c (RELAX_MIPS16_ENCODE): Add `e2' flag.
(RELAX_MIPS16_E2): New macro.
(RELAX_MIPS16_PIC, RELAX_MIPS16_SYM32, RELAX_MIPS16_NOMACRO)
(RELAX_MIPS16_USER_SMALL, RELAX_MIPS16_USER_EXT)
(RELAX_MIPS16_DSLOT, RELAX_MIPS16_JAL_DSLOT)
(RELAX_MIPS16_EXTENDED, RELAX_MIPS16_MARK_EXTENDED)
(RELAX_MIPS16_CLEAR_EXTENDED, RELAX_MIPS16_ALWAYS_EXTENDED)
(RELAX_MIPS16_MARK_ALWAYS_EXTENDED)
(RELAX_MIPS16_CLEAR_ALWAYS_EXTENDED, RELAX_MIPS16_MACRO)
(RELAX_MIPS16_MARK_MACRO, RELAX_MIPS16_CLEAR_MACRO): Shift bits.
(mips16_immed_extend): New prototype.
(options): Add OPTION_MIPS16E2 and OPTION_NO_MIPS16E2 enum
values.
(md_longopts): Add "mmips16e2" and "mno-mips16e2" options.
(mips_ases): Add "mips16e2" entry.
(mips_set_ase): Handle MIPS16e2 ASE.
(insn_insert_operand): Explicitly handle immediates with MIPS16
instructions that require 32-bit encoding.
(is_opcode_valid_16): Pass enabled ASE bitmask on to
`opcode_is_member'.
(validate_mips_insn): Explicitly handle immediates with MIPS16
instructions that require 32-bit encoding.
(operand_reg_mask) <OP_REG28>: Add handler.
(match_reg28_operand): New function.
(match_operand) <OP_REG28>: Add handler.
(append_insn): Pass ASE_MIPS16E2 setting to RELAX_MIPS16_ENCODE.
(match_mips16_insn): Handle MIPS16 instructions that require
32-bit encoding and `V' and `u' operand codes.
(mips16_ip): Allow any characters except from `.' in opcodes.
(mips16_immed_extend): Handle 9-bit immediates. Do not shuffle
immediates whose width is not one of these listed.
(md_estimate_size_before_relax): Handle MIPS16e2 relaxation.
(mips_relax_frag): Likewise.
(md_convert_frag): Likewise.
(mips_convert_ase_flags): Handle MIPS16e2 ASE.
* doc/as.texinfo (Target MIPS options): Add `-mmips16e2' and
`-mno-mips16e2' options.
(-mmips16e2, -mno-mips16e2): New options.
* doc/c-mips.texi (MIPS Options): Add `-mmips16e2' and
`-mno-mips16e2' options.
(MIPS ASE Instruction Generation Overrides): Add `.set mips16e2'
and `.set nomips16e2'.
PPC_OPCODE_* renumbered to fill the gaps left by previous patches,
and reordered chronologically just because. I kept PPC_OPCODE_TMR
because presumably it might be used in future APUinfo for e6500.
include/
* opcode/ppc.h (PPC_OPCODE_*): Renumber and order chronologically.
(PPC_OPCODE_SPE): Comment on this and other bits used for APUinfo.
opcodes/
* ppc-dis.c (ppc_opts): Formatting. Set PPC_OPCODE_TMR for e6500.
* ppc-opc.c (powerpc_opcodes <mftmr, mttmr>): Remove now
unnecessary E6500.
This bit is also useless as it can be replaced with PPC_OPCODE_POWER9.
Defining the VSX2 and VSX3 selection based on cpu bits also lets the
assembler/disassembler distinguish between the power7 VSX opcodes and
the power8 ones. Note that this change means -mvsx now reverts back
to just adding the power7 VSX insns.
include/
* opcode/ppc.h (PPC_OPCODE_VSX3): Delete.
opcodes/
* ppc-dis.c (ppc_opts): Remove PPC_OPCODE_VSX3.
* ppc-opc.c (PPCVSX2): Define as PPC_OPCODE_POWER8.
(PPCVSX3): Define as PPC_OPCODE_POWER9.
This bit is worse than useless. Using it prevents the assembler and
disassembler distinguishing between opcodes added for power8 and those
added for power9.
include/
* opcode/ppc.h (PPC_OPCODE_ALTIVEC2): Delete.
opcodes/
* ppc-dis.c (ppc_opts): Remove PPC_OPCODE_ALTIVEC2.
* ppc-opc.c (PPCVEC2): Define as PPC_OPCODE_POWER8|PPC_OPCODE_E6500.
(PPCVEC3): Define as PPC_OPCODE_POWER9.
This adds -Mraw for PowerPC objdump, a disassembler option to display
the underlying machine instruction rather than aliases. For example,
"rlwinm" always rather than "rotlwi" when the instruction is
performing a simple rotate.
binutils/
* doc/binutils.texi (objdump): Document PowerPC -M options.
gas/
* config/tc-ppc.c (md_parse_option): Reject -mraw.
include/
* opcode/ppc.h (PPC_OPCODE_RAW): Define.
(PPC_OPCODE_*): Make them all unsigned long long constants.
opcodes/
* ppc-dis.c (ppc_opts): Set PPC_OPCODE_PPC for "any" flags. Add
"raw" option.
(lookup_powerpc): Don't special case -1 dialect. Handle
PPC_OPCODE_RAW.
(print_insn_powerpc): Mask out PPC_OPCODE_ANY on first
lookup_powerpc call, pass it on second.
This patch removes the vx2 facility flag. It will not be used by GCC
and was a misnomer anyway.
Committed to mainline and 2.28 branch.
include/ChangeLog:
2017-03-21 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
* opcode/s390.h (S390_INSTR_FLAG_VX2): Remove.
(S390_INSTR_FLAG_FACILITY_MASK): Adjust value.
gas/ChangeLog:
2017-03-21 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
* config/tc-s390.c (s390_parse_cpu): Remove S390_INSTR_FLAG_VX2
from cpu_table. Remove vx2, and novx2 from cpu_flags.
opcodes/ChangeLog:
2017-03-21 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
* s390-mkopc.c (main): Remove vx2 check.
* s390-opc.txt: Remove vx2 instruction flags.
Instructions for loading or storing 16/32B data from one address type to
another.
gas/ChangeLog
* testsuite/gas/arc/nps400-11.s: New file.
* testsuite/gas/arc/nps400-11.d: New file.
include/ChangeLog
* opcode/arc.h (insn_class_t): Add DMA class.
opcodes/ChangeLog
* arc-nps400-tbl.h: Add cp32/cp16 instructions format.
* arc-opc.c: Add F_NPS_NA, NPS_DMA_IMM_ENTRY, NPS_DMA_IMM_OFFSET.
(insert_nps_imm_offset): New function.
(extract_nps_imm_offset): New function.
(insert_nps_imm_entry): New function.
(extract_nps_imm_entry): New function.
This patch supports some additions to the SVE architecture prior to
its public release.
include/
* opcode/aarch64.h (AARCH64_OPND_SVE_ADDR_RI_S4x16)
(AARCH64_OPND_SVE_IMM_ROT1, AARCH64_OPND_SVE_IMM_ROT2)
(AARCH64_OPND_SVE_Zm3_INDEX, AARCH64_OPND_SVE_Zm3_22_INDEX)
(AARCH64_OPND_SVE_Zm4_INDEX): New aarch64_opnds.
opcodes/
* aarch64-tbl.h (OP_SVE_HMH, OP_SVE_VMU_HSD, OP_SVE_VMVU_HSD)
(OP_SVE_VMVV_HSD, OP_SVE_VMVVU_HSD, OP_SVE_VM_HSD, OP_SVE_VUVV_HSD)
(OP_SVE_VUV_HSD, OP_SVE_VU_HSD, OP_SVE_VVVU_H, OP_SVE_VVVU_S)
(OP_SVE_VVVU_HSD, OP_SVE_VVV_D, OP_SVE_VVV_D_H, OP_SVE_VVV_H)
(OP_SVE_VVV_HSD, OP_SVE_VVV_S, OP_SVE_VVV_S_B, OP_SVE_VVV_SD_BH)
(OP_SVE_VV_BHSDQ, OP_SVE_VV_HSD, OP_SVE_VZVV_HSD, OP_SVE_VZV_HSD)
(OP_SVE_V_HSD): New macros.
(OP_SVE_VMU_SD, OP_SVE_VMVU_SD, OP_SVE_VM_SD, OP_SVE_VUVV_SD)
(OP_SVE_VU_SD, OP_SVE_VVVU_SD, OP_SVE_VVV_SD, OP_SVE_VZVV_SD)
(OP_SVE_VZV_SD, OP_SVE_V_SD): Delete.
(aarch64_opcode_table): Add new SVE instructions.
(aarch64_opcode_table): Use imm_rotate{1,2} instead of imm_rotate
for rotation operands. Add new SVE operands.
* aarch64-asm.h (ins_sve_addr_ri_s4): New inserter.
(ins_sve_quad_index): Likewise.
(ins_imm_rotate): Split into...
(ins_imm_rotate1, ins_imm_rotate2): ...these two inserters.
* aarch64-asm.c (aarch64_ins_imm_rotate): Split into...
(aarch64_ins_imm_rotate1, aarch64_ins_imm_rotate2): ...these two
functions.
(aarch64_ins_sve_addr_ri_s4): New function.
(aarch64_ins_sve_quad_index): Likewise.
(do_misc_encoding): Handle "MOV Zn.Q, Qm".
* aarch64-asm-2.c: Regenerate.
* aarch64-dis.h (ext_sve_addr_ri_s4): New extractor.
(ext_sve_quad_index): Likewise.
(ext_imm_rotate): Split into...
(ext_imm_rotate1, ext_imm_rotate2): ...these two extractors.
* aarch64-dis.c (aarch64_ext_imm_rotate): Split into...
(aarch64_ext_imm_rotate1, aarch64_ext_imm_rotate2): ...these two
functions.
(aarch64_ext_sve_addr_ri_s4): New function.
(aarch64_ext_sve_quad_index): Likewise.
(aarch64_ext_sve_index): Allow quad indices.
(do_misc_decoding): Likewise.
* aarch64-dis-2.c: Regenerate.
* aarch64-opc.h (FLD_SVE_i3h, FLD_SVE_rot1, FLD_SVE_rot2): New
aarch64_field_kinds.
(OPD_F_OD_MASK): Widen by one bit.
(OPD_F_NO_ZR): Bump accordingly.
(get_operand_field_width): New function.
* aarch64-opc.c (fields): Add new SVE fields.
(operand_general_constraint_met_p): Handle new SVE operands.
(aarch64_print_operand): Likewise.
* aarch64-opc-2.c: Regenerate.
gas/
* doc/c-aarch64.texi: Document that sve implies fp16, simd and compnum.
* config/tc-aarch64.c (parse_vector_type_for_operand): Allow .q
to be used with SVE registers.
(parse_operands): Handle new SVE operands.
(aarch64_features): Make "sve" require F16 rather than FP. Also
require COMPNUM.
* testsuite/gas/aarch64/sve.s: Add tests for new instructions.
Include compnum tests.
* testsuite/gas/aarch64/sve.d: Update accordingly.
* testsuite/gas/aarch64/sve-invalid.s: Add tests for new instructions.
* testsuite/gas/aarch64/sve-invalid.l: Update accordingly. Also
update expected output for new FMOV and MOV alternatives.
This patch adds a named "compnum" feature for the ARMv8.3-A FCADD
and FCMLA extensions.
include/
* opcode/aarch64.h (AARCH64_FEATURE_COMPNUM): New macro.
(AARCH64_ARCH_V8_3): Include AARCH64_FEATURE_COMPNUM.
opcodes/
* aarch64-tbl.h (aarch64_feature_simd_v8_3): Replace with...
(aarch64_feature_compnum): ...this.
(SIMD_V8_3): Replace with...
(COMPNUM): ...this.
(CNUM_INSN): New macro.
(aarch64_opcode_table): Use it for the complex number instructions.
gas/
* doc/c-aarch64.texi: Add a "compnum" entry.
* config/tc-aarch64.c (aarch64_features): Likewise,
* testsuite/gas/aarch64/advsimd-compnum.s: New test.
* testsuite/gas/aarch64/advsimd-compnum.d: Likewise.
This adds support of new instructions to the S/390 specific parts.
The important feature of the new instruction set is the support of
single and extended precision floating point vector operations.
Note: arch12 is NOT the official name of the new CPU. It just
continues the series of archXX options supported as alternate names.
The archXX terminology refers to the edition number of the Principle
of Operations manual. The official CPU name will be added later while
keeping support of the arch12 for backwards compatibility.
No testsuite regressions.
Committed to mainline.
Bye,
-Andreas-
opcodes/ChangeLog:
2017-02-23 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
* s390-mkopc.c (main): Accept arch12 as cpu string and vx2 as
facility.
* s390-opc.c: Add new operand description macros, new instruction
types, instruction masks, and new .insn instruction types.
* s390-opc.txt: Add new arch12 instructions.
include/ChangeLog:
2017-02-23 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
* opcode/s390.h (enum s390_opcode_cpu_val): New value
S390_OPCODE_ARCH12.
(S390_INSTR_FLAG_VX2): New macro definition.
gas/ChangeLog:
2017-02-23 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
* config/tc-s390.c (s390_parse_cpu): New entry for arch12.
* doc/as.texinfo: Document arch12 as cpu type.
* doc/c-s390.texi: Likewise.
* testsuite/gas/s390/s390.exp: Run arch12 specific tests.
* testsuite/gas/s390/zarch-arch12.d: New test.
* testsuite/gas/s390/zarch-arch12.s: New test.
* testsuite/gas/s390/zarch-z13.d: Rename some mnemonics in the
output patterns.
With this change an architecture level bump due to assembly ASIs will show
up as a warning/error depending on options passed to gas.
Tested with sparc64-linux-gnu, and it does not introduce any regressions.
gas/ChangeLog:
Add support for associating SPARC ASIs with an architecture level.
* config/tc-sparc.c (parse_sparc_asi): New encode SPARC ASIs.
opcodes/ChangeLog:
Add support for associating SPARC ASIs with an architecture level.
* include/opcode/sparc.h (sparc_asi): New sparc_asi struct.
* opcodes/sparc-opc.c (asi_table): Updated asi_table and encoding/
decoding of SPARC ASIs.
This stops powerpc gas blithely accepting such nonsense as
"addi %f4,%cr3,%r31".
PR 21118
gas/
* NEWS: Mention powerpc register checks.
* config/tc-ppc.c (struct pd_reg): Make value a short. Add flags.
(pre_defined_registers): Delete fpscr and pmr entries. Set
register type in flags.
(cr_names): Set type in flags.
(reg_name_search): Return pointer to struct pd_reg rather than value.
(register_name): Adjust to suit. Set X_md from flags.
(ppc_parse_name): Likewise.
(ppc_optimize_expr): New function.
(md_assemble): Verify expresion reg flags match operand.
* config/tc-ppc.h (md_optimize_expr): Define.
(ppc_optimize_expr): Declare.
include/
* opcode/ppc.h (PPC_OPERAND_*): Reassign values, regs first.
(PPC_OPERAND_SPR, PPC_OPERAND_GQR): Define.
opcodes/
* ppc-opc.c (powerpc_operands): Flag SPR, SPRG and TBR entries
with PPC_OPERAND_SPR. Flag PSQ and PSQM with PPC_OPERAND_GQR.
The weaker release consistency support of ARMv8.3-A is allowed as an optional
extension for ARMv8.2-A, so separate command line option and feature flag is
added: -march=armv8.2-a+rcpc turns LDAPR, LDAPRB, LDAPRH instructions on.
opcodes/
* aarch64-tbl.h (RCPC, RCPC_INSN): Define.
(aarch64_opcode_table): Use RCPC_INSN.
include/
* opcode/aarch64.h (AARCH64_FEATURE_RCPC): Define.
(AARCH64_ARCH_V8_3): Update.
gas/
* config/tc-aarch64.c (aarch64_features): Add rcpc.
* doc/c-aarch64.texi (AArch64 Extensions): Document rcpc.
* testsuite/gas/aarch64/ldst-exclusive-armv8_3.d: Rename to ...
* testsuite/gas/aarch64/ldst-rcpc.d: This.
* testsuite/gas/aarch64/ldst-exclusive-armv8_3.s: Rename to ...
* testsuite/gas/aarch64/ldst-rcpc.s: This.
* testsuite/gas/aarch64/ldst-rcpc-armv8_2.d: New test.
gas * config/tc-riscv.c (riscv_set_arch): Whitelist the "q" ISA
extension.
(riscv_after_parse_args): Set FLOAT_ABI_QUAD when the Q ISA is
enabled and no other ABI is specified.
include * opcode/riscv-opc.h: Add support for the "q" ISA extension.
opcodes * riscv-opc.c (riscv-opcodes): Add support for the "q" ISA
extension.
* riscv-opcodes/all-opcodes: Likewise.
Add ASMACRO instruction support as per the MIPS16e ASE architecture
specifications [1][2], completing MIPS16e instruction set support.
[1] "MIPS32 Architecture for Programmers, Volume IV-a: The MIPS16e
Application-Specific Extension to the MIPS32 Architecture", MIPS
Technologies, Inc., Document Number: MD00076, Revision 2.63, July
16, 2013, Section 4.1 "MIPS16e Instruction Descriptions", p. 65
[2] "MIPS64 Architecture for Programmers, Volume IV-a: The MIPS16e
Application-Specific Extension to the MIPS64 Architecture", MIPS
Technologies, Inc., Document Number: MD00077, Revision 2.60, June
25, 2008, Section 1.1 "MIPS16e Instruction Descriptions", p. 66
include/
* opcode/mips.h: Document `0', `1', `2', `3', `4' and `s'
operand codes.
opcodes/
* mips16-opc.c (decode_mips16_operand): Add `0', `1', `2', `3',
`4' and `s' operand codes.
(mips16_opcodes): Add "asmacro" entry.
binutils/
* testsuite/binutils-all/mips/mips16-extend-insn.d: Update for
ASMACRO support.
gas/
* testsuite/gas/mips/mips16-asmacro.d: New test.
* testsuite/gas/mips/mips16-32@mips16-asmacro.d: New test.
* testsuite/gas/mips/mips16-64@mips16-asmacro.d: New test.
* testsuite/gas/mips/mips16-asmacro.s: New test source.
* testsuite/gas/mips/mips.exp: Run the new tests.
Replace `0' and `4' operand codes with `.' and `F' respectively to free
up the `0'-`4' consecutive range. No functional change.
gas/
* config/tc-mips.c (mips16_macro_build): Replace `0' and `4'
operand codes with `.' and `F' respectively.
(mips16_macro): Likewise.
include/
* opcode/mips.h: Replace `0' and `4' operand codes with `.' and
`F' respectively.
opcodes/
* mips16-opc.c (decode_mips16_operand): Replace `0' and `4'
operand codes with `.' and `F' respectively.
(mips16_opcodes): Likewise.
Identify non-extensible instructions in the MIPS16 opcode table and
disallow their use with the `.e' instruction size suffix in assembly and
do not interpret any EXTEND prefix present as a part of the instruction
in disassembly.
According to all versions of the MIPS16 ASE specifications the following
instructions encodings are not extensible [1][2][3][4][5][6]: I8/MOV32R,
I8/MOVR32, all RRR minor opcodes, all RR minor opcodes except from DSRA
and DSRL, and EXTEND itself, and as from revision 2.50 of the MIPS16e
ASE specifications it has been further clarified what was previously
implied, that non-extesiable instructions when preceded with an EXTEND
prefix must cause a Reserved Instruction exception [3][5].
Therefore in the presence of an EXTEND prefix none of these instructions
are supposed to be handled as extended instructions and supporting these
forms in disassembly causes confusion, and in the case of the RRR major
opcode it also clashes with the ASMACRO encoding.
References:
[1] "Product Description, MIPS16 Application-Specific Extension",
Version 1.3, MIPS Technologies, Inc., 970130, Table 3. "MIPS16
Instruction Set Summary", p. 5
[2] same, Table 5 "RR Minor Opcodes (RR-type instructions)", p.10
[3] "MIPS32 Architecture for Programmers, Volume IV-a: The MIPS16e
Application-Specific Extension to the MIPS32 Architecture", MIPS
Technologies, Inc., Document Number: MD00076, Revision 2.63, July
16, 2013, Section 3.9 "MIPS16e Instruction Summaries", pp. 37-39
[4] same, Section 3.15 "Instruction Bit Encoding", pp. 46-49
[5] "MIPS64 Architecture for Programmers, Volume IV-a: The MIPS16e
Application-Specific Extension to the MIPS64 Architecture", MIPS
Technologies, Inc., Document Number: MD00077, Revision 2.60, June
25, 2008, Section 1.9 "MIPS16e Instruction Summaries", pp. 38-41
[6] same, Section 1.15 "Instruction Bit Encoding", pp. 48-51
include/
* opcode/mips.h (INSN2_SHORT_ONLY): New macro.
gas/
* config/tc-mips.c (is_size_valid_16): Disallow a `.e' suffix
instruction size override for INSN2_SHORT_ONLY opcode table
entries.
* testsuite/gas/mips/mips16-extend-swap.d: Adjust output.
* testsuite/gas/mips/mips16-macro-e.l: Adjust error messages.
* testsuite/gas/mips/mips16-32@mips16-macro-e.l: Adjust error
messages.
* testsuite/gas/mips/mips16e-32@mips16-macro-e.l: Adjust error
messages.
* testsuite/gas/mips/mips16-insn-e.d: New test.
* testsuite/gas/mips/mips16-insn-t.d: New test.
* testsuite/gas/mips/mips16-32@mips16-insn-e.d: New test.
* testsuite/gas/mips/mips16-64@mips16-insn-e.d: New test.
* testsuite/gas/mips/mips16e-32@mips16-insn-e.d: New test.
* testsuite/gas/mips/mips16-32@mips16-insn-t.d: New test.
* testsuite/gas/mips/mips16-64@mips16-insn-t.d: New test.
* testsuite/gas/mips/mips16e-32@mips16-insn-t.d: New test.
* testsuite/gas/mips/mips16-insn-e.l: New stderr output.
* testsuite/gas/mips/mips16-insn-t.l: New stderr output.
* testsuite/gas/mips/mips16-32@mips16-insn-e.l: New stderr
output.
* testsuite/gas/mips/mips16-64@mips16-insn-e.l: New stderr
output.
* testsuite/gas/mips/mips16e-32@mips16-insn-e.l: New stderr
output.
* testsuite/gas/mips/mips16-32@mips16-insn-t.l: New stderr
output.
* testsuite/gas/mips/mips16-64@mips16-insn-t.l: New stderr
output.
* testsuite/gas/mips/mips16e-32@mips16-insn-t.l: New stderr
output.
* testsuite/gas/mips/mips16-insn-e.s: New test source.
* testsuite/gas/mips/mips16-insn-t.s: New test source.
* testsuite/gas/mips/mips.exp: Run the new tests.
opcodes/
* mips-dis.c (print_insn_mips16): Disallow EXTEND prefix
matching for INSN2_SHORT_ONLY opcode table entries.
* mips16-opc.c (SH): New macro.
(mips16_opcodes): Set SH in `pinfo2' for non-extensible
instruction entries: "nop", "addu", "and", "break", "cmp",
"daddu", "ddiv", "ddivu", "div", "divu", "dmult", "dmultu",
"drem", "dremu", "dsllv", "dsll", "dsrav", "dsra", "dsrlv",
"dsrl", "dsubu", "exit", "entry", "jalr", "jal", "jr", "j",
"jalrc", "jrc", "mfhi", "mflo", "move", "mult", "multu", "neg",
"not", "or", "rem", "remu", "sllv", "sll", "slt", "sltu",
"srav", "sra", "srlv", "srl", "subu", "xor", "sdbbp", "seb",
"seh", "sew", "zeb", "zeh", "zew" and "extend".
binutils/
* testsuite/binutils-all/mips/mips16-extend-insn.d: New test.
* testsuite/binutils-all/mips/mips16-extend-insn.s: New test
source.
* testsuite/binutils-all/mips/mips.exp: Run the new tests.
gas/
* doc/c-lm32.texi: Fix chars with high bit set.
* testsuite/gas/bfin/vector2.s: Likewise.
gold/
* arm.cc: Fix comment chars with high bit set.
include/
* coff/pe.h: Fix comment chars with high bit set.
* opcode/xgate.h: Likewise.
ld/
* testsuite/ld-scripts/sysroot-prefix.exp: Fix chars with high bit set.
Switch to 32-bit MIPS16 opcode table entry interpretation, similar to
how the microMIPS opcode table is handled, for both the `match' and
`mask' fields, removing special casing for JAL and JALX instructions and
their `a' and `i' operand codes throughout, while retaining automatic
processing of extendable opcodes in assembly and disassembly.
In assembly disallow size enforcement suffixes as appropriate: `.t' for
both 32-bit instructions and macros and `.e' for macros only, making
macro handling consistent with the microMIPS instruction set.
In disassembly fully decode EXTEND prefixes prepended to unsupported
instruction encodings (according to the ISA selection) rather than
dumping them as hexadecimal data along with the following instruction,
removing all special casing for the EXTEND prefix and making its
handling rely on its opcode table entry, except where it is considered a
part of an extendable instruction.
include/
* opcode/mips.h (mips_opcode_32bit_p): New inline function.
gas/
* config/tc-mips.c (micromips_insn_length): Use
`mips_opcode_32bit_p'.
(is_size_valid): Adjust description.
(is_size_valid_16): New function.
(validate_mips_insn): Use `mips_opcode_32bit_p' in MIPS16
operand decoding.
(validate_mips16_insn): Remove `a' and `i' operand code special
casing, use `mips_opcode_32bit_p' to determine instruction
width.
(append_insn): Adjust forced MIPS16 instruction size
determination.
(match_mips16_insn): Likewise. Don't shift the instruction's
opcode with the `a' and `i' operand codes. Use
`mips_opcode_32bit_p' in operand decoding.
(match_mips16_insns): Check for forced instruction size's
validity.
(mips16_ip): Don't force instruction size in the `noautoextend'
mode.
* testsuite/gas/mips/mips16-jal-e.d: New test.
* testsuite/gas/mips/mips16-jal-t.d: New test.
* testsuite/gas/mips/mips16-macro-e.d: New test.
* testsuite/gas/mips/mips16-macro-t.d: New test.
* testsuite/gas/mips/mips16-jal-t.l: New stderr output.
* testsuite/gas/mips/mips16-macro-e.l: New stderr output.
* testsuite/gas/mips/mips16-macro-t.l: New stderr output.
* testsuite/gas/mips/mips16-jal-e.s: New test source.
* testsuite/gas/mips/mips16-jal-t.s: New test source.
* testsuite/gas/mips/mips16-macro-e.s: New test source.
* testsuite/gas/mips/mips16-macro-t.s: New test source.
* testsuite/gas/mips/mips.exp: Run the new tests.
opcodes/
* mips-dis.c (print_mips16_insn_arg): Always handle `extend' and
`insn' together, with `extend' as the high-order 16 bits.
(match_kind): New enum.
(print_insn_mips16): Rework for 32-bit instruction matching.
Do not dump EXTEND prefixes here.
* mips16-opc.c (mips16_opcodes): Move "extend" entry to the end.
Recode `match' and `mask' fields as 32-bit in absolute "jal" and
"jalx" entries.
binutils/
* testsuite/binutils-all/mips/mips16-extend-noinsn.d: Adjust
test for separate EXTEND prefix disassembly.
Kuan-Lin Chen
Alexander Fedotov
Claudiu Zissulescu
John Eric Martin
Yuri Chornovian
Georg-Johann Lay
Maciej W. Rozycki
Tamar Christina
Jiong Wang
Thomas Preud'homme
Andreas Krebbel
H.J. Lu
Jose E. Marchesi
John David Anglin
Alan Modra
Andrew Waterman
Pip Cet
Rinat Zelig
Richard Sandiford
Sheldon Lobo
Dimitar Dimitrov
Szabolcs Nagy
Kito Cheng