dae39accc2
gas/
...
2008-04-18 H.J. Lu <hongjiu.lu@intel.com>
* config/tc-i386.c (build_modrm_byte): Swap REG and NDS for
FMA.
gas/testsuite/
2008-04-18 H.J. Lu <hongjiu.lu@intel.com>
* gas/i386/arch-10.d: Updated.
* gas/i386/avx.d: Likewise.
* gas/i386/avx-intel.d: Likewise.
* gas/i386/x86-64-arch-2.d: Likewise.
* gas/i386/x86-64-avx.d: Likewise.
* gas/i386/x86-64-avx-intel.d: Likewise.
opcodes/
2008-04-18 H.J. Lu <hongjiu.lu@intel.com>
* i386-dis.c (OP_VEX_FMA): New.
(OP_EX_VexImmW): Likewise.
(VexFMA): Likewise.
(Vex128FMA): Likewise.
(EXVexImmW): Likewise.
(get_vex_imm8): Likewise.
(OP_EX_VexReg): Likewise.
(vex_i4_done): Renamed to ...
(vex_w_done): This.
(prefix_table): Replace EXVexW with EXVexImmW on vpermil2ps
and vpermil2pd. Replace Vex/Vex128 with VexFMA/Vex128FMA on
FMA instructions.
(print_insn): Updated.
(OP_EX_VexW): Rewrite to swap register in VEX with EX.
(OP_REG_VexI4): Check invalid high registers.
2008-04-18 13:10:32 +00:00
ce886ab1f8
<opcode changes>
...
2008-04-16 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com>
Michael Meissner <michael.meissner@amd.com>
* i386-opc.tbl: Fix protX to allow memory in the middle operand.
* i386-tbl.h: Regenerate from i386-opc.tbl.
<gas/testsuite changes>
2008-04-16 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com>
Michael Meissner <michael.meissner@amd.com>
* gas/i386/x86-64-sse5.s: Add protX tests to allow memory in the middle
operand.
* gas/i386/x86-64-sse5.d: Likewise.
2008-04-16 15:31:33 +00:00
dc2f32e79b
Sorry, missed this ChangeLog updat in previous commit.
2008-04-16 08:52:15 +00:00
739f7f82be
bfd/
...
* reloc.c (BFD_RELOC_SPARC_GOTDATA_HIX22,
BFD_RELOC_SPARC_GOTDATA_LOX10, BFD_RELOC_SPARC_GOTDATA_OP_HIX22,
BFD_RELOC_SPARC_GOTDATA_OP_LOX10, BFD_RELOC_SPARC_GOTDATA_OP): New.
* libbfd.h: Regnerate.
* bfd-in2.h: Regenerate.
* elfxx-sparc.c (_bfd_sparc_elf_howto_table): Add entries for
GOTDATA relocations.
(sparc_reloc_map): Likewise.
(_bfd_sparc_elf_check_relocs): Handle R_SPARC_GOTDATA_* like
R_SPARC_GOT*.
(_bfd_sparc_elf_gc_sweep_hook): Likewise.
(_bfd_sparc_elf_relocate_section): Transform R_SPARC_GOTDATA_HIX22,
R_SPARC_GOTDATA_LOX10, R_SPARC_GOTDATA_OP_HIX22, and
R_SPARC_GOTDATA_OP_LOX10 into the equivalent R_SPARC_GOT* reloc.
Simply ignore R_SPARC_GOTDATA_OP relocations.
gas/
* config/tc-sparc.c (sparc_ip): Add support for gotdata mnemonics
and relocation generation.
(tc_gen_reloc): Likewise.
gas/testsuite/
* gas/sparc/gotops32.d: New.
* gas/sparc/gotops32.s: Likewise.
* gas/sparc/gotops64.d: Likewise.
* gas/sparc/gotops64.s: Likewise.
* gas/sparc/sparc.exp: Run new gotdata tests.
ld/testsuite/
* ld-sparc/gotop32.dd: New.
* ld-sparc/gotop32.rd: Likewise.
* ld-sparc/gotop32.s: Likewise.
* ld-sparc/gotop32.sd: Likewise.
* ld-sparc/gotop32.td: Likewise.
* ld-sparc/gotop64.dd: Likewise.
* ld-sparc/gotop64.rd: Likewise.
* ld-sparc/gotop64.s: Likewise.
* ld-sparc/gotop64.sd: Likewise.
* ld-sparc/gotop64.td: Likewise.
* ld-sparc/sparc.exp: Run new gotdata tests.
2008-04-16 08:51:18 +00:00
52b5ca5b35
2008-04-15 Andrew Stubbs <andrew.stubbs@st.com>
...
gas/
* config/tc-sh.c (md_apply_fix): Make sure BFD_RELOC_SH_PCRELIMM8BY4
relocations are properly aligned, and not negative.
gas/testsuite/
* gas/sh/arch/arch.exp: Align PC-relative instructions in the gererated
assembly files.
* gas/sh/arch/sh-dsp.s: Regenerate.
* gas/sh/arch/sh.s: Regenerate.
* gas/sh/arch/sh2.s: Regenerate.
* gas/sh/arch/sh2a-nofpu-or-sh3-nommu.s: Regenerate.
* gas/sh/arch/sh2a-nofpu-or-sh4-nommu-nofpu.s: Regenerate.
* gas/sh/arch/sh2a-nofpu.s: Regenerate.
* gas/sh/arch/sh2a-or-sh3e.s: Regenerate.: Regenerate.
* gas/sh/arch/sh2a-or-sh4.s: Regenerate.
* gas/sh/arch/sh2a.s: Regenerate.
* gas/sh/arch/sh2e.s: Regenerate.
* gas/sh/arch/sh3-dsp.s: Regenerate.
* gas/sh/arch/sh3-nommu.s: Regenerate.
* gas/sh/arch/sh3.s: Regenerate.
* gas/sh/arch/sh3e.s: Regenerate.
* gas/sh/arch/sh4-nofpu.s: Regenerate.
* gas/sh/arch/sh4-nommu-nofpu.s: Regenerate.
* gas/sh/arch/sh4.s: Regenerate.
* gas/sh/arch/sh4a-nofpu.s: Regenerate.
* gas/sh/arch/sh4a.s: Regenerate.
* gas/sh/arch/sh4al-dsp.s: Regenerate.
* gas/sh/err-mova.s: New test.
ld/testsuite/
* ld-sh/arch/sh-dsp.s: Regenerate.
* ld-sh/arch/sh.s: Regenerate.
* ld-sh/arch/sh2.s: Regenerate.
* ld-sh/arch/sh2a-nofpu-or-sh3-nommu.s: Regenerate.
* ld-sh/arch/sh2a-nofpu-or-sh4-nommu-nofpu.s: Regenerate.
* ld-sh/arch/sh2a-nofpu.s: Regenerate.
* ld-sh/arch/sh2a-or-sh3e.s: Regenerate.: Regenerate.
* ld-sh/arch/sh2a-or-sh4.s: Regenerate.
* ld-sh/arch/sh2a.s: Regenerate.
* ld-sh/arch/sh2e.s: Regenerate.
* ld-sh/arch/sh3-dsp.s: Regenerate.
* ld-sh/arch/sh3-nommu.s: Regenerate.
* ld-sh/arch/sh3.s: Regenerate.
* ld-sh/arch/sh3e.s: Regenerate.
* ld-sh/arch/sh4-nofpu.s: Regenerate.
* ld-sh/arch/sh4-nommu-nofpu.s: Regenerate.
* ld-sh/arch/sh4.s: Regenerate.
* ld-sh/arch/sh4a-nofpu.s: Regenerate.
* ld-sh/arch/sh4a.s: Regenerate.
* ld-sh/arch/sh4al-dsp.s: Regenerate.
2008-04-15 15:53:26 +00:00
19a6653ce8
ppc e500mc support
2008-04-14 11:01:38 +00:00
24f4d50fc1
2008-04-11 H.J. Lu <hongjiu.lu@intel.com>
...
* gas/lns/lns-big-delta.d: Updated.
* gas/lns/lns-common-1.d: Likewise.
* gas/lns/lns-common-1-alt.d: Likewise.
* gas/lns/lns-duplicate.d: Likewise.
2008-04-11 17:51:15 +00:00
daf50ae75d
gas/
...
2008-04-10 H.J. Lu <hongjiu.lu@intel.com>
* NEWS: Mention -msse-check=[none|error|warning].
* config/tc-i386.c (sse_check): New.
(OPTION_MSSE_CHECK): Likewise.
(md_assemble): Check SSE instructions if needed.
(md_longopts): Add -msse-check.
(md_parse_option): Handle OPTION_MSSE_CHECK.
(md_show_usage): Show -msse-check=[none|error|warning].
* doc/c-i386.texi: Document -msse-check=[none|error|warning].
gas/testsuite/
2008-04-10 H.J. Lu <hongjiu.lu@intel.com>
* gas/i386/i386.exp: Run sse-check, sse-check-warn,
sse-check-error, x86-64-sse-check, x86-64-sse-check-warn and
x86-64-sse-check-error.
* gas/i386/sse-check.d: New.
* gas/i386/sse-check.s: Likewise.
* gas/i386/sse-check-error.l: Likewise.
* gas/i386/sse-check-error.s: Likewise.
* gas/i386/sse-check-warn.d: Likewise.
* gas/i386/sse-check-warn.e: Likewise.
* gas/i386/x86-64-sse-check.d: Likewise.
* gas/i386/x86-64-sse-check-error.l: Likewise.
* gas/i386/x86-64-sse-check-error.s: Likewise.
* gas/i386/x86-64-sse-check-warn.d: Likewise.
2008-04-10 17:53:40 +00:00
83f10cb26a
* listing.c: Add -ag listing flag to show general information in
...
listings such as gas version, passed options, and time stamp.
(listing_general_info): New function.
(print_options): New function.
(print_single_option): New function.
(print_timestamp): New function.
(MAX_DATELEN): Define.
(listing_print): Add call to listing_general_info.
* listing.h (LISTING_GENERAL): Define.
(listing_print): Add new parameter.
* as.c (show_usage): Print new switch.
(parse_args): Parse new switch.
(main): Pass command line on to listing_print.
* NEWS: Mention this new feature.
* doc/as.texinfo: Document the new sub-option.
* gas/all/gas.exp: Check the performance of the -ag command line
switch.
2008-04-10 12:45:18 +00:00
45a5551e74
2008-04-10 Andreas Krebbel <krebbel1@de.ibm.com>
...
* s390-mkopc.c (s390_cond_ext_format): Add back the mnemonic
extensions for conditional jumps (o, p, m, nz, z, nm, np, no).
(s390_crb_extensions): New extensions table.
(insertExpandedMnemonic): Handle '$' tag.
* s390-opc.txt: Remove conditional jump variants which can now
be expanded automatically.
Replace '*' tag with '$' in the compare and branch instructions.
2008-04-10 Andreas Krebbel <krebbel1@de.ibm.com>
* gas/s390/zarch-z10.d: Map the compare and branch variants
with odd condition code mask to version with an even mask.
2008-04-10 08:59:46 +00:00
f04cc279d0
Add the missing ymm test in the last checkin.
2008-04-07 14:38:25 +00:00
40f1253383
gas/
...
2008-04-07 H.J. Lu <hongjiu.lu@intel.com>
* config/tc-i386.c (parse_real_register): Return AVX register
only if AVX is enabled.
gas/testsuite/
2008-04-07 H.J. Lu <hongjiu.lu@intel.com>
* gas/i386/att-regs.s: Add AVX register test.
* gas/i386/intel-regs.s: Likewise.
* gas/i386/att-regs.d: Updated.
* gas/i386/intel-regs.d: Likewise.
2008-04-07 13:07:16 +00:00
783d3e7187
PR gas/6043
...
* config/tc-sh64.c (shmedia_md_pcrel_from_section): Use
md_pcrel_from_section for BFD_RELOC_64 and BFD_RELOC_64_PCREL.
* gas/sh/sh64/eh-1.d: New.
* gas/sh/sh64/eh-1.d: Likewise.
2008-04-07 02:55:08 +00:00
594ab6a333
gas/
...
2008-04-04 H.J. Lu <hongjiu.lu@intel.com>
* NEWS: Mention XSAVE. Change CLMUL to PCLMUL.
* config/tc-i386.c (cpu_arch): Add .pclmul.
(md_show_usage): Replace clmul with pclmul.
* doc/c-i386.texi: Likewise.
gas/testsuite/
2008-04-04 H.J. Lu <hongjiu.lu@intel.com>
* gas/i386/arch-10-1.l: Replace CLMUL with PCLMUL.
* gas/i386/arch-10-2.l: Likewise.
* gas/i386/arch-10-3.l: Likewise.
* gas/i386/arch-10-4.l: Likewise.
* gas/i386/arch-10.s: Likewise.
* gas/i386/clmul-intel.d: Likewise.
* gas/i386/clmul.d: Likewise.
* gas/i386/clmul.s: Likewise.
* gas/i386/x86-64-arch-2.s: Likewise.
* gas/i386/x86-64-clmul-intel.d: Likewise.
* gas/i386/x86-64-clmul.d: Likewise.
* gas/i386/x86-64-clmul.s: Likewise.
* gas/i386/arch-10.d: Replace clmul with pclmul.
* gas/i386/x86-64-arch-2.d: Likewise.
opcodes/
2008-04-04 H.J. Lu <hongjiu.lu@intel.com>
* i386-gen.c (cpu_flag_init): Replace CPU_CLMUL_FLAGS/CpuCLMUL
with CPU_PCLMUL_FLAGS/CpuPCLMUL.
(cpu_flags): Replace CpuCLMUL with CpuPCLMUL.
* i386-opc.tbl: Likewise.
* i386-opc.h (CpuCLMUL): Renamed to ...
(CpuPCLMUL): This.
(CpuFMA): Updated.
(i386_cpu_flags): Replace cpuclmul with cpupclmul.
* i386-init.h: Regenerated.
2008-04-04 16:34:23 +00:00
c0f3af977b
binutils/
...
2008-04-03 H.J. Lu <hongjiu.lu@intel.com>
* dwarf.c (dwarf_regnames_i386): Add AVX registers.
(dwarf_regnames_x86_64): Likewise.
gas/
2008-04-03 H.J. Lu <hongjiu.lu@intel.com>
* NEWS: Mention AES, CLMUL, AVX/FMA and -msse2avx.
* doc/c-i386.texi: Add avx, aes, clmul and fma to -march=.
Document -msse2avx, .avx, .aes, .clmul and .fma.
* config/tc-i386.c (YMMWORD_MNEM_SUFFIX): New.
(vex_prefix): Likewise.
(sse2avx): Likewise.
(CPU_FLAGS_ARCH_MATCH): Likewise.
(CPU_FLAGS_64BIT_MATCH): Likewise.
(CPU_FLAGS_32BIT_MATCH): Likewise.
(CPU_FLAGS_PERFECT_MATCH): Likewise.
(regymm): Likewise.
(vex_imm4): Likewise.
(fits_in_imm4): Likewise.
(build_vex_prefix): Likewise.
(VEX_check_operands): Likewise.
(bad_implicit_operand): Likewise.
(OPTION_MSSE2AVX): Likewise.
(T_YMMWORD): Likewise.
(_i386_insn): Add vex.
(cpu_arch): Add .avx, .aes, .clmul and .fma.
(cpu_flags_match): Changed to take a pointer to const template.
Enable encoding SSE instructions with VEX prefix for -msse2avx.
(match_mem_size): Also check ymmword.
(operand_type_match): Clear ymmword.
(md_begin): Allow '_' in mnemonic.
(type_names): Add OPERAND_TYPE_VEX_IMM4.
(process_immext): Update assert.
(md_assemble): Don't call process_immext if sse2avx and immext
are true. Call build_vex_prefix if vex is true.
(parse_insn): Updated for cpu_flags_match.
(swap_operands): Handle 5 operands.
(match_template): Handle 5 operands. Updated for cpu_flags_match.
Check regymm. Call VEX_check_operands. Handle YMMWORD_MNEM_SUFFIX.
(process_suffix): Handle YMMWORD_MNEM_SUFFIX.
(check_byte_reg): Check regymm.
(process_operands): Duplicate the destination register for
-msse2avx if needed.
(build_modrm_byte): Updated for instructions with VEX encoding.
(output_insn): Output VEX prefix if needed.
(md_longopts): Add msse2avx.
(md_parse_option): Handle OPTION_MSSE2AVX.
(md_show_usage): Add avx, aes, clmul, fma and -msse2avx.
(intel_e09): Support YMMWORD.
(intel_e11): Likewise.
(intel_get_token): Likewise.
gas/testsuite/
2008-04-03 H.J. Lu <hongjiu.lu@intel.com>
* gas/i386/i386.exp: Run aes, aes-intel, x86-64-aes,
x86-64-aes-intel, avx, avx-intel, inval-avx, x86-64-avx,
x86-64-avx-intel and x86-64-inval-avx.
* gas/cfi/cfi-i386.s: Add tests for AVX register maps.
* gas/cfi/cfi-x86_64.s: Likewise.
* gas/i386/aes.d: New.
* gas/i386/aes.s: Likewise.
* gas/i386/aes-intel.d: Likewise.
* gas/i386/avx.d: Likewise.
* gas/i386/avx.s: Likewise.
* gas/i386/avx-intel.d: Likewise.
* gas/i386/clmul.d: Likewise.
* gas/i386/clmul-intel.d: Likewise.
* gas/i386/clmul.s: Likewise.
* gas/i386/i386.exp: Likewise.
* gas/i386/inval-avx.l: Likewise.
* gas/i386/inval-avx.s: Likewise.
* gas/i386/sse2avx.d: Likewise.
* gas/i386/sse2avx.s: Likewise.
* gas/i386/x86-64-aes.d: Likewise.
* gas/i386/x86-64-aes.s: Likewise.
* gas/i386/x86-64-aes-intel.d: Likewise.
* gas/i386/x86-64-avx.d: Likewise.
* gas/i386/x86-64-avx.s: Likewise.
* gas/i386/x86-64-avx-intel.d: Likewise.
* gas/i386/x86-64-clmul.d: Likewise.
* gas/i386/x86-64-clmul-intel.d: Likewise.
* gas/i386/x86-64-clmul.s: Likewise.
* gas/i386/x86-64-inval-avx.l: Likewise.
* gas/i386/x86-64-inval-avx.s: Likewise.
* gas/i386/x86-64-sse2avx.d: Likewise.
* gas/i386/x86-64-sse2avx.s: Likewise.
* gas/i386/arch-10.s: Add tests for AVX, AES, CLMUL and FMA.
* gas/i386/x86-64-arch-2.s: Likewise.
* gas/i386/rexw.s: Add AVX tests.
* gas/i386/x86-64-opcode-inval.s: Remove lds/les test.
* gas/cfi/cfi-i386.d: Updated.
* gas/cfi/cfi-x86_64.d: Likewise.
* gas/i386/arch-10.d: Likewise.
* gas/i386/arch-10-1.l: Likewise.
* gas/i386/arch-10-2.l: Likewise.
* gas/i386/arch-10-3.l: Likewise.
* gas/i386/arch-10-4.l: Likewise.
* gas/i386/rexw.d: Likewise.
* gas/i386/x86-64-arch-2.d: Likewise.
* gas/i386/x86-64-opcode-inval.d: Likewise.
* gas/i386/x86-64-opcode-inval-intel.d: Likewise.
include/opcode/
2008-04-03 H.J. Lu <hongjiu.lu@intel.com>
* i386.h (MAX_OPERANDS): Set to 5.
(MAX_MNEM_SIZE): Changed to 20.
opcodes/
2008-04-03 H.J. Lu <hongjiu.lu@intel.com>
* i386-dis.c (OP_E_register): New.
(OP_E_memory): Likewise.
(OP_VEX): Likewise.
(OP_EX_Vex): Likewise.
(OP_EX_VexW): Likewise.
(OP_XMM_Vex): Likewise.
(OP_XMM_VexW): Likewise.
(OP_REG_VexI4): Likewise.
(PCLMUL_Fixup): Likewise.
(VEXI4_Fixup): Likewise.
(VZERO_Fixup): Likewise.
(VCMP_Fixup): Likewise.
(VPERMIL2_Fixup): Likewise.
(rex_original): Likewise.
(rex_ignored): Likewise.
(Mxmm): Likewise.
(XMM): Likewise.
(EXxmm): Likewise.
(EXxmmq): Likewise.
(EXymmq): Likewise.
(Vex): Likewise.
(Vex128): Likewise.
(Vex256): Likewise.
(VexI4): Likewise.
(EXdVex): Likewise.
(EXqVex): Likewise.
(EXVexW): Likewise.
(EXdVexW): Likewise.
(EXqVexW): Likewise.
(XMVex): Likewise.
(XMVexW): Likewise.
(XMVexI4): Likewise.
(PCLMUL): Likewise.
(VZERO): Likewise.
(VCMP): Likewise.
(VPERMIL2): Likewise.
(xmm_mode): Likewise.
(xmmq_mode): Likewise.
(ymmq_mode): Likewise.
(vex_mode): Likewise.
(vex128_mode): Likewise.
(vex256_mode): Likewise.
(USE_VEX_C4_TABLE): Likewise.
(USE_VEX_C5_TABLE): Likewise.
(USE_VEX_LEN_TABLE): Likewise.
(VEX_C4_TABLE): Likewise.
(VEX_C5_TABLE): Likewise.
(VEX_LEN_TABLE): Likewise.
(REG_VEX_XX): Likewise.
(MOD_VEX_XXX): Likewise.
(PREFIX_0F38DB..PREFIX_0F38DF): Likewise.
(PREFIX_0F3A44): Likewise.
(PREFIX_0F3ADF): Likewise.
(PREFIX_VEX_XXX): Likewise.
(VEX_OF): Likewise.
(VEX_OF38): Likewise.
(VEX_OF3A): Likewise.
(VEX_LEN_XXX): Likewise.
(vex): Likewise.
(need_vex): Likewise.
(need_vex_reg): Likewise.
(vex_i4_done): Likewise.
(vex_table): Likewise.
(vex_len_table): Likewise.
(OP_REG_VexI4): Likewise.
(vex_cmp_op): Likewise.
(pclmul_op): Likewise.
(vpermil2_op): Likewise.
(m_mode): Updated.
(es_reg): Likewise.
(PREFIX_0F38F0): Likewise.
(PREFIX_0F3A60): Likewise.
(reg_table): Add REG_VEX_71...REG_VEX_73 and REG_VEX_AE.
(prefix_table): Add PREFIX_0F38DB..PREFIX_0F38DF, PREFIX_0F3ADF
and PREFIX_VEX_XXX entries.
(x86_64_table): Use VEX_C4_TABLE and VEX_C5_TABLE.
(three_byte_table): Use PREFIX_0F38DB..PREFIX_0F38DF and
PREFIX_0F3ADF.
(mod_table): Use VEX_C4_TABLE, VEX_C5_TABLE and VEX_LEN_TABLE.
Add MOD_VEX_XXX entries.
(ckprefix): Initialize rex_original and rex_ignored. Store the
REX byte in rex_original.
(get_valid_dis386): Handle the implicit prefix in VEX prefix
bytes and USE_VEX_LEN_TABLE/USE_VEX_C4_TABLE/USE_VEX_C5_TABLE.
(print_insn): Set need_vex/need_vex_reg/vex_i4_done to 0 before
calling get_valid_dis386. Use rex_original and rex_ignored when
printing out REX.
(putop): Handle "XY".
(intel_operand_size): Handle VEX, xmm_mode, xmmq_mode and
ymmq_mode.
(OP_E_extended): Updated to use OP_E_register and
OP_E_memory.
(OP_XMM): Handle VEX.
(OP_EX): Likewise.
(XMM_Fixup): Likewise.
(CMP_Fixup): Use ARRAY_SIZE.
* i386-gen.c (cpu_flag_init): Add CpuAES, CPU_CLMUL_FLAGS,
CPU_FMA_FLAGS and CPU_AVX_FLAGS.
(operand_type_init): Add OPERAND_TYPE_REGYMM and
OPERAND_TYPE_VEX_IMM4.
(cpu_flags): Add CpuAVX, CpuAES, CpuCLMUL and CpuFMA.
(opcode_modifiers): Add Implicit1stXmm0, Vex, Vex256, VexNDD,
VexNDS, VexW0, VexW1, Vex0F, Vex0F38, Vex0F3A, Vex3Sources,
VexImmExt and SSE2AVX.
(operand_types): Add RegYMM, Ymmword and Vex_Imm4.
* i386-opc.h (CpuAVX): New.
(CpuAES): Likewise.
(CpuCLMUL): Likewise.
(CpuFMA): Likewise.
(Vex): Likewise.
(Vex256): Likewise.
(VexNDS): Likewise.
(VexNDD): Likewise.
(VexW0): Likewise.
(VexW1): Likewise.
(Vex0F): Likewise.
(Vex0F38): Likewise.
(Vex0F3A): Likewise.
(Vex3Sources): Likewise.
(VexImmExt): Likewise.
(SSE2AVX): Likewise.
(RegYMM): Likewise.
(Ymmword): Likewise.
(Vex_Imm4): Likewise.
(Implicit1stXmm0): Likewise.
(CpuXsave): Updated.
(CpuLM): Likewise.
(ByteOkIntel): Likewise.
(OldGcc): Likewise.
(Control): Likewise.
(Unspecified): Likewise.
(OTMax): Likewise.
(i386_cpu_flags): Add cpuavx, cpuaes, cpuclmul and cpufma.
(i386_opcode_modifier): Add implicit1stxmm0, vex, vex256,
vexnds, vexndd, vexw0, vexw1, vex0f, vex0f38, vex0f3a,
vex3sources, veximmext and sse2avx.
(i386_operand_type): Add regymm, ymmword and vex_imm4.
* i386-opc.tbl: Add AES, CLMUL, AVX and FMA new instructions.
* i386-reg.tbl: Add AVX registers, ymm0..ymm15.
* i386-init.h: Regenerated.
* i386-tbl.h: Likewise.
2008-04-03 14:03:21 +00:00
086134ec0e
gas/testsuite/:
...
From Robin Getz <rgetz@blackfin.uclinux.org>
* gas/bfin/arithmetic.d: Update to reflect spaces/capitalization in
recent changes in opcodes/bfin-dis.c.
gas/bfin/arithmetic.s: Likewise.
gas/bfin/bit.d: Likewise.
gas/bfin/bit2.d: Likewise.
gas/bfin/control_code.d: Likewise.
gas/bfin/control_code2.d: Likewise.
gas/bfin/event.d: Likewise.
gas/bfin/event2.d: Likewise.
gas/bfin/flow.d: Likewise.
gas/bfin/flow2.d: Likewise.
gas/bfin/load.d: Likewise.
gas/bfin/logical.d: Likewise.
gas/bfin/logical2.d: Likewise.
gas/bfin/move.d: Likewise.
gas/bfin/move2.d: Likewise.
gas/bfin/parallel.d: Likewise.
gas/bfin/parallel2.d: Likewise.
gas/bfin/parallel3.d: Likewise.
gas/bfin/parallel4.d: Likewise.
gas/bfin/shift.d: Likewise.
gas/bfin/shift2.d: Likewise.
gas/bfin/stack.d: Likewise.
gas/bfin/stack2.d: Likewise.
gas/bfin/store.d: Likewise.
gas/bfin/vector.d: Likewise.
gas/bfin/vector2.d: Likewise.
gas/bfin/video.d: Likewise.
gas/bfin/video2.d: Likewise.
opcodes/:
* bfin-dis.c: (c_uimm4s4d, c_imm5d, c_imm7d, c_imm16d, c_uimm16s4d,
c_imm32, c_huimm32e): Define.
(constant_formats): Add flags for printing decimal, leading spaces, and
exact symbols.
(comment, parallel): Add global flags in all disassembly.
(fmtconst): Take advantage of new flags, and print default in hex.
(fmtconst_val): Likewise.
(decode_macfunc): Be consistant with spaces, tabs, comments,
capitalization in disassembly, fix minor coding style issues.
(reg_names, amod0, amod1, amod0amod2, aligndir, get_allreg): Likewise.
(decode_ProgCtrl_0, decode_PushPopMultiple_0, decode_CCflag_0,
decode_CC2dreg_0, decode_CC2stat_0, decode_BRCC_0, decode_UJUMP_0,
decode_REGMV_0, decode_ALU2op_0, decode_PTR2op_0, decode_LOGI2op_0,
decode_COMP3op_0, decode_COMPI2opD_0, decode_COMPI2opP_0,
decode_LDSTpmod_0, decode_dagMODim_0, decode_dagMODik_0,
decode_dspLDST_0, decode_LDST_0, decode_LDSTiiFP_0, decode_LDSTii_0,
decode_LoopSetup_0, decode_LDIMMhalf_0, decode_CALLa_0,
decode_LDSTidxI_0, decode_linkage_0, decode_dsp32alu_0,
decode_dsp32shift_0, decode_dsp32shiftimm_0, decode_pseudodbg_assert_0,
_print_insn_bfin, print_insn_bfin): Likewise.
2008-03-26 16:48:32 +00:00
e2c038d34c
gas/:
...
* config/tc-bfin.c (bfin_start_line_hook): Localize the labels
generated for LOOP_BEGIN and LOOP_END instructions.
(bfin_gen_loop): Likewise.
gas/testsuite/:
* gas/bfin/flow.d: Adjust since the generated labels for LOOP_BEGIN
and LOOP_END instruction are local now.
* gas/bfin/flow2.d: Likewise.
2008-03-26 16:33:33 +00:00
ee171c8f94
gas/
...
* config/bfin-parse.y (check_macfunc_option): Allow (IU)
option for multiply and multiply-accumulate to data register
instruction.
(check_macfuncs): Don't check if accumulator matches the data register
here.
(assign_macfunc): Check if accumulator matches the
data register in each rule that moves to the data
register.
gas/testsuite/
* gas/bfin/arithmetic.s, gas/bfin/arithmetic.d: Add check
for IU option.
* gas/bfin/expected_errors.l, gas/bfin/expected_errors.s:
Add check for mismatch of accumulator and data register.
opcodes/
* bfin-dis.c (decode_dsp32mac_0): Decode (IU) option for
multiply and multiply-accumulate to data register instruction.
2008-03-26 16:21:10 +00:00
c1db045b89
gas/:
...
* config/bfin-parse.y (check_macfunc_option): New.
(check_macfuncs): Check option by calling check_macfunc_option.
Fix comparison always true warnings. Both scalar instructions
of vector instruction must share the same mode option. Only allow
option mode at the end of the second instruction of the vector.
(asm_1): Check option by calling check_macfunc_option.
gas/testsuite/:
* gas/bfin/expected_errors.l, gas/bfin/expected_errors.s: Add
tests for bad options of "multiply and multipy-accumulate to
accumulator" instructions. Add new vector instruction option
mode tests.
* gas/bfin/vector2.s: Add new vector instruction option mode test.
* gas/bfin/vector2.d: Adjust accordingly.
* gas/bfin/expected_errors.s, gas/bfin/expected_errors.l: Add test
for mismatched half registers in vector multipy-accumulate
instructions.
2008-03-26 15:58:27 +00:00
99bfa74a53
gas/
...
From Jie Zhang <jie.zhang@analog.com>
* config/bfin-parse.y (asm_1): Check AREGS in comparison
instructions. And call yyerror () when comparing PREG with
DREG.
gas/testsuite/:
* gas/bfin/expected_comparison_errors.l: New test.
* gas/bfin/expected_comparison_errors.s: New test.
* gas/bfin/bfin.exp: Add expected_comparison_errors.
2008-03-26 15:18:42 +00:00
b21c9cb440
opcodes:
...
From Robin Getz <robin.getz@analog.com>
* bfin-dis.c (bu32): Typedef.
(enum const_forms_t): Add c_uimm32 and c_huimm32.
(constant_formats[]): Add uimm32 and huimm16.
(fmtconst_val): New.
(uimm32): Define.
(huimm32): Define.
(imm16_val): Define.
(luimm16_val): Define.
(struct saved_state): Define.
(GREG, DPREG, DREG, PREG, SPREG, FPREG, IREG, MREG, BREG, LREG,
A0XREG, A0WREG, A1XREG, A1WREG,CCREG, LC0REG, LT0REG, LB0REG,
LC1REG, LT1REG, LB1REG, RETSREG, PCREG): Define.
(get_allreg): New.
(decode_LDIMMhalf_0): Print out the whole register value.
gas/testsuite:
From Jie Zhang <jie.zhang@analog.com>
* gas/bfin/load.d: Update.
2008-03-26 14:50:52 +00:00
5746fb46c8
2008-03-19 Andreas Krebbel <krebbel1@de.ibm.com>
...
* opcodes/s390-mkopc.c (s390_opcode_cpu_val): S390_OPCODE_Z10 added.
(s390_cond_extensions): Reduced extensions to the compare related.
(main): z10 cpu type option added.
(expandConditionalJump): Renamed to ...
(insertExpandedMnemonic): ... this.
* opcodes/s390-opc.c: Re-group the operand format makros.
(INSTR_RIE_RRPU, INSTR_RIE_RRP0, INSTR_RIE_RUPI,
INSTR_RIE_R0PI, INSTR_RIE_RUPU, INSTR_RIE_R0PU, INSTR_RIE_R0IU,
INSTR_RIE_R0I0, INSTR_RIE_R0UU, INSTR_RIE_R0U0,
INSTR_RIE_RRUUU, INSTR_RIS_RURDI, INSTR_RIS_R0RDI, INSTR_RIS_RURDU,
INSTR_RIS_R0RDU, INSTR_RRF_U0RR, INSTR_RRF_00RR, INSTR_RRS_RRRDU,
INSTR_RRS_RRRD0, INSTR_RXY_URRD, INSTR_SIY_IRD, INSTR_SIL_RDI,
INSTR_SIL_RDU): New instruction formats added.
(MASK_RIE_RRPU, MASK_RIE_RRP0, MASK_RIE_RUPI, MASK_RIE_R0PI,
MASK_RIE_RUPU, MASK_RIE_R0PU, MASK_RIE_R0IU, MASK_RIE_R0I0,
MASK_RIE_R0UU, MASK_RIE_R0U0, MASK_RIE_RRUUU, MASK_RIS_RURDI,
MASK_RIS_R0RDI, MASK_RIS_RURDU, MASK_RIS_R0RDU, MASK_RRF_U0RR,
MASK_RRF_00RR, MASK_RRS_RRRDU, MASK_RRS_RRRD0, MASK_RXY_URRD,
MASK_SIY_IRD, MASK_SIL_RDI, MASK_SIL_RDU): New instruction format
masks added.
(s390_opformats): New formats added "ris", "rrs", "sil".
* opcodes/s390-opc.txt: Add the conditional jumps with the
extensions removed from automatic expansion in s390-mkopc.c manually.
(asi - trtre): Add new System z10 EC instructions.
* include/opcode/s390.h (s390_opcode_cpu_val): S390_OPCODE_Z10 added.
2008-03-19 Andreas Krebbel <krebbel1@de.ibm.com>
* config/tc-s390.c (md_parse_option): z10 option added.
2008-03-19 Andreas Krebbel <krebbel1@de.ibm.com>
* gas/s390/zarch-z10.d: New file.
* gas/s390/zarch-z10.s: New file.
* gas/s390/s390.exp: Run the z10 testcases.
2008-03-19 10:29:18 +00:00
188e2ff3a5
* gas/macros/test1.s: Rename symbols to avoid conflicts with
...
possible register names.
* gas/macros/test1.d: Update expected disassembly.
2008-03-18 16:56:00 +00:00
08e8dfaf50
gas/testsuite/
...
* gas/mips/elf-rel26.d: Add -32.
* gas/mips/mips16-intermix.d: Likewise.
ld/testsuite/
* ld-mips-elf/mips-elf.exp (o32_as_flags, o32_ld_flags): New variables.
(mips16_call_global_test, mips16_intermix_test): Use them.
2008-03-17 18:45:35 +00:00
5808f4a685
PR gas/5895
...
* read.c (s_mexit): Warn if attempting to exit a macro when not
inside a macro definition.
* gas/macros/exit.s: New test case.
* gas/macros/macros.exp: Run the new test, expect it to produce an
error result.
2008-03-13 10:51:33 +00:00
b1cc4aeb65
2008-03-09 Paul Brook <paul@codesourcery.com>
...
bfd/
* elf32-arm.c (elf32_arm_merge_eabi_attributes): Handle new
Tag_VFP_arch values.
binutils/
* readelf.c (arm_attr_tag_VFP_arch): Add "VFPv3-D16".
gas/
* config/tc-arm.c (fpu_vfp_ext_d32): New vairable.
(parse_vfp_reg_list, encode_arm_vfp_reg): Use it.
(arm_option_cpu_value): Add vfpv3-d16, vfpv2 and vfpv3.
(aeabi_set_public_attributes): Handle Tag_VFP_arch=VFPV3-D16.
* doc/c-arm.texi: Document new ARM FPU variants.
gas/testsuite/
* gas/arm/vfpv3-d16-bad.d: New test.
* gas/arm/vfpv3-d16-bad.l: New test.
include/opcode/
* arm.h (FPU_VFP_EXT_D32, FPU_VFP_V3D16, FPU_ARCH_VFP_V3D16): Define.
2008-03-09 13:23:29 +00:00
98c3d90597
2008-03-06 Florian Krohm <fkrohm@us.ibm.com>
...
* s390-opc.c (INSTR_RSL_R0RD): Fix operands.
* s390-opc.txt (cmpsc): Duplicate entry removed.
(dxr, sqdr, sqer, cxfbr, cdfbr, cefbr, lzer, lzdr, lzxr,
cegbr, cdgbr, cxgbr, cegr, cdgr, cxgr, cxfr, cdfr, cefr, fixr, fidr,
fier, cu42, cu41): Fix operand format.
2008-03-06 Andreas Krebbel <krebbel1@de.ibm.com>
* gas/s390/esa-g5.d (cdfbr, cdfr, cefbr, cefr, cxfbr, cxfr,
dxr, fidr, fier, fixr, lzdr, lzer, lzxr, sqdr, sqer, tp): Fix
operand format.
* gas/s390/esa-g5.s: Likewise.
* gas/s390/zarch-z900.d (cdgbr, cdgr, cegbr, cegr, cxgbr,
cxgr): Likewise.
* gas/s390/zarch-z900.s: Likewise.
* gas/s390/zarch-z9-109.d (cu41, cu42): Remove mask operand.
* gas/s390/zarch-z9-109.s: Likewise.
2008-03-06 12:01:13 +00:00
7e8064706d
2008-03-04 Paul Brook <paul@codesourcery.com>
...
gas/
* config/tc-arm.c (arm_ext_barrier, arm_ext_msr): New.
(arm_ext_v7m): Rename...
(arm_ext_m): ... to this. Include v6-M.
(do_t_add_sub): Allow narrow low-reg non flag setting adds.
(do_t_mrs, do_t_msr, aeabi_set_public_attributes): Use arm_ext_m.
(md_assemble): Allow wide msr instructions.
(insns): Add classifications for v6-m instructions.
(arm_cpu_option_table): Add cortex-m1.
(arm_arch_option_table): Add armv6-m.
(cpu_arch): Add ARM_ARCH_V6M. Fix numbering of other v6 variants.
gas/testsuite/
* gas/arm/archv6m.d: New test.
* gas/arm/archv6m.s: New test.
* gas/arm/t16-bad.s: Test low register non flag setting add.
* gas/arm/t16-bad.l: Update expected output.
include/opcode/
* arm.h (ARM_EXT_V6M, ARM_EXT_BARRIER, ARM_EXT_THUMB_MSR): Define.
(ARM_AEXT_V6T2, ARM_AEXT_V7_ARM, ARM_AEXT_V7M): Use new flags.
(ARM_AEXT_V6M, ARM_ARCH_V6M): Define.
2008-03-05 01:31:26 +00:00
d0548f348f
gas/
...
2008-03-03 Denys Vlasenko <vda.linux@googlemail.com>
H.J. Lu <hongjiu.lu@intel.com>
PR gas/5543
* read.c (pseudo_set): Don't allow global register symbol.
* symbols.c (S_SET_EXTERNAL): Don't allow register symbol
global.
2008-03-03 H.J. Lu <hongjiu.lu@intel.com>
PR gas/5543
* write.c (write_object_file): Don't allow symbols which were
equated to register. Stop if there is an error.
gas/testsuite/
2008-03-03 H.J. Lu <hongjiu.lu@intel.com>
PR gas/5543
* gas/i386/i386.exp: Run inval-equ-1 and inval-equ-2.
* gas/i386/inval-equ-1.l: New.
* gas/i386/inval-equ-1.s: Likewise.
* gas/i386/inval-equ-2.l: Likewise.
* gas/i386/inval-equ-2.s: Likewise.
2008-03-03 15:28:58 +00:00
28dbc07952
gas/testsuite/
...
2008-03-01 H.J. Lu <hongjiu.lu@intel.com>
* gas/i386/x86-64-branch.s: Add tests for 16-bit near indirect
branches.
* gas/i386/x86-64-inval.s: Remove tests for 16-bit near indirect
branches.
* gas/i386/x86-64-branch.d: Updated.
* gas/i386/x86-64-inval.l: Likewise.
opcodes/
2008-03-01 H.J. Lu <hongjiu.lu@intel.com>
* i386-opc.tbl: Allow 16-bit near indirect branches for x86-64.
* i386-tbl.h: Regenerated.
2008-03-01 23:30:51 +00:00
af7329f0ff
PR 3134
...
* h8300.h (h8_opcodes): Add an encoding for a mov.l instruction
with a 32-bit displacement but without the top bit of the 4th byte
set.
* gas/h8300/pr3134.s: New test.
* gas/h8300/pr3134.d: Expected disassembly
* gas/h8300/h8300.exp: Run the new test.
* gas/h8300/h8300-coff.exp: Fix test for COFF based ports to
accept h8300-rtemscoff not just h8300-rtems.
2008-02-27 12:33:43 +00:00
58abc3ebf6
2008-02-26 H.J. Lu <hongjiu.lu@intel.com>
...
* gas/i386/jump.d: Updated for COFF.
2008-02-26 16:18:16 +00:00
849830bdfb
gas/testsuite/
...
2008-02-23 H.J. Lu <hongjiu.lu@intel.com>
* gas/i386/jump.s: Add tests for far branches.
* gas/i386/jump16.s: Likewise.
* gas/i386/jump.d: Updated.
* gas/i386/jump16.d: Likewise.
* gas/i386/x86-64-inval.l: Likewise.
* gas/i386/x86-64-inval.s: Add tests for 16-bit near indirect
branches.
opcodes/
2008-02-23 H.J. Lu <hongjiu.lu@intel.com>
* i386-opc.tbl: Disallow 16-bit near indirect branches for
x86-64.
* i386-tbl.h: Regenerated.
2008-02-23 17:29:17 +00:00
a696b49ec5
* gas/m68hc11/bug-1825.d: Update to match changes in the
...
information generated with source-in-disassembly listings.
* gas/m68hc11/indexed12.d: Likewise.
* gas/m68hc11/insns-dwarf2.d: Likewise.
* gas/m68hc11/lbranch-dwarf2.d: Likewise.
2008-02-22 15:33:31 +00:00
785d276e24
Correct year.
2008-02-20 23:32:33 +00:00
845b51d665
2008-02-20 Paul Brook <paul@codesourcery.com>
...
ld/
* emultempl/armelf.em (OPTION_FIX_V4BX_INTERWORKING): Define.
(PARSE_AND_LIST_LONGOPTS): Add fix-v4bx-interworking.
(PARSE_AND_LIST_OPTIONS): Ditto.
(PARSE_AND_LIST_ARGS_CASES): Handle OPTION_FIX_V4BX_INTERWORKING.
* emulparams/armelf.sh (OTHER_TEXT_SECTIONS): Add .v4_bx.
* emulparams/armelf_linux.sh (OTHER_TEXT_SECTIONS): Ditto.
* emulparams/armnto.sh (OTHER_TEXT_SECTIONS): Ditto.
* ld.texinfo: Document --fix-v4bx-interworking.
ld/testsuite/
* ld-arm/armv4-bx.d: New test.
* ld-arm/armv4-bx.s: New test.
* ld-arm/arm.ld: Add .v4bx.
* ld-arm/arm-elf.exp: Add armv4-bx.
gas/testsuite/
* gas/arm/thumb.d: Exclude EABI targets.
* gas/arm/arch4t.d: Exclude EABI targts.
* gas/arm/v4bx.d: New test.
* gas/arm/v4bx.s: New test.
* gas/arm/thumb-eabi.d: New test.
* gas/arm/arch4t-eabi.d: New test.
gas/
* config/tc-arm.c (fix_v4bx): New variable.
(do_bx): Generate V4BX relocations.
(md_assemble): Allow bx on v4 codes when fix_v4bx.
(md_apply_fix): Handle BFD_RELOC_ARM_V4BX.
(tc_gen_reloc): Ditto.
(OPTION_FIX_V4BX): Define.
(md_longopts): Add fix-v4bx.
(md_parse_option): Handle OPTION_FIX_V4BX.
(md_show_usage): Document --fix-v4bx.
* doc/c-arm.texi: Document --fix-v4bx.
bfd/
* reloc.c: Add BFD_RELOC_ARM_V4BX.
* elf32-arm.c (elf32_arm_reloc_map): Add BFD_RELOC_ARM_V4BX.
(ARM_BX_GLUE_SECTION_NAME, ARM_BX_GLUE_SECTION_NAME): Define.
(elf32_arm_link_hash_table): Add bx_glue_size and bx_glue_offset.
Update comment for fix_v4bx.
(elf32_arm_link_hash_table_create): Zero bx_glue_size and
bx_glue_offset.
(ARM_BX_VENEER_SIZE, armbx1_tst_insn, armbx2_moveq_insn,
armbx3_bx_insn): New.
(bfd_elf32_arm_allocate_interworking_sections): Allocate BX veneer
section.
(bfd_elf32_arm_add_glue_sections_to_bfd): Ditto.
(bfd_elf32_arm_process_before_allocation): Record BX veneers.
(record_arm_bx_glue, elf32_arm_bx_glue): New functions.
(elf32_arm_final_link_relocate): Handle BX veneers.
(elf32_arm_output_arch_local_syms): Output mapping symbol for .v4_bx.
* bfd-in2.h: Regenerate.
* libbfd.h: Regenerate.
2008-02-20 15:17:56 +00:00
b646068837
2008-02-18 H.J. Lu <hongjiu.lu@intel.com>
...
* cfi/cfi.exp (gas_x86_64_check): New.
(gas_x86_32_check): Likewise.
Run 32bit and 64bit tests for x86 targets if they are supportd.
2008-02-18 21:05:07 +00:00
192dc9c6fd
gas/
...
2008-02-18 Jan Beulich <jbeulich@novell.com>
* config/tc-i386.c (match_template): Disallow 'l' suffix when
currently selected CPU has no 32-bit support.
(parse_real_register): Do not return registers not available on
currently selected CPU.
gas/testsuite/
2008-02-18 Jan Beulich <jbeulich@novell.com>
* gas/i386/att-regs.s, gas/i386/att-regs.d,
gas/i386/intel-regs.s, gas/i386/intel-regs.d: New.
* gas/i386/i386.exp: Run new tests.
2008-02-18 08:44:38 +00:00
93ac268764
PR gas/5712
...
* config/tc-arm.c (s_arm_unwind_save): Advance the input line
pointer past the comma after parsing a floating point register
name.
* gas/arm/fp-save.s: New test.
* gas/arm/fp-save.d: Expected disassembly.
2008-02-14 16:35:51 +00:00
9579d38232
* gas/mips/branch-misc-2pic-64.d (#name): Have a unique name
...
different from the branch-misc-2-64.d test.
2008-02-13 17:22:43 +00:00
b7240065b3
gas/
...
2008-02-13 Jan Beulich <jbeulich@novell.com>
* config/tc-i386.c (parse_real_register): Don't return 'FLAT'
if not in Intel mode.
(i386_intel_operand): Ignore segment overrides in immediate and
offset operands.
(intel_e11): Range-check i.mem_operands before use as array
index. Filter out FLAT for uses other than as segment override.
(intel_get_token): Remove broken promotion of "FLAT:" to mean
"offset FLAT:".
gas/testsuite/
2008-02-13 Jan Beulich <jbeulich@novell.com>
* gas/i386/intelok.s: Replace invalid offset expression with
valid ones.
* gas/i386/x86_64.s: Likewise.
opcodes/
2008-02-13 Jan Beulich <jbeulich@novell.com>
* i386-opc.h (RegFlat): New.
* i386-reg.tbl (flat): Add.
* i386-tbl.h: Re-generate.
2008-02-13 13:41:26 +00:00
34b772a651
gas/
...
2008-02-13 Jan Beulich <jbeulich@novell.com>
* config/tc-i386.c (intel_e09): Also special-case 'bound'.
gas/testsuite/
2008-02-13 Jan Beulich <jbeulich@novell.com>
* gas/i386/intelbad.s, gas/i386/intelok.s: Add 'bound' tests.
* gas/i386/intelbad.l, gas/i386/intelok.l, gas/i386/intelok.e,
gas/i386/opcode-intel.d: Adjust.
opcodes/
2008-02-13 Jan Beulich <jbeulich@novell.com>
* i386-dis.c (a_mode): New.
(cond_jump_mode): Adjust.
(Ma): Change to a_mode.
(intel_operand_size): Handle a_mode.
* i386-opc.tbl: Allow Dword and Qword for bound.
* i386-tbl.h: Re-generate.
2008-02-13 13:29:31 +00:00
a60de03c61
gas/
...
2008-02-13 Jan Beulich <jbeulich@novell.com>
* config/tc-i386.c (allow_pseudo_reg): New.
(parse_real_register): Check for NULL just once. Allow all
register table entries when allow_pseudo_reg is non-zero.
Don't allow any registers without type when allow_pseudo_reg
is zero.
(tc_x86_regname_to_dw2regnum): Replace with ...
(tc_x86_parse_to_dw2regnum): ... this.
(tc_x86_frame_initial_instructions): Adjust for above change.
* config/tc-i386.h (tc_regname_to_dw2regnum): Remove.
(tc_parse_to_dw2regnum): New.
(tc_x86_regname_to_dw2regnum): Replace with ...
(tc_x86_parse_to_dw2regnum): ... this.
* dw2gencfi.c (tc_parse_to_dw2regnum): New, broken out of ...
(cfi_parse_reg): ... this. Use tc_parse_to_dw2regnum. Adjust
error handling.
gas/testsuite/
2008-02-13 Jan Beulich <jbeulich@novell.com>
* gas/cfi/cfi-i386.s: Add code testing use of all registers.
Fix a few comments.
* gas/cfi/cfi-x86_64.s: Likewise.
* gas/cfi/cfi-i386.d, gas/cfi/cfi-x86_64.d: Adjust.
opcodes/
2008-02-13 Jan Beulich <jbeulich@novell.com>
* i386-gen.c (process_i386_registers): Process new fields.
* i386-opc.h (reg_entry): Shrink reg_flags and reg_num to
unsigned char. Add dw2_regnum and Dw2Inval.
* i386-reg.tbl: Provide initializers for dw2_regnum. Add pseudo
register names.
* i386-tbl.h: Re-generate.
2008-02-13 10:14:40 +00:00
e8efc4d9fd
2002-02-12 H.J. Lu <hongjiu.lu@intel.com>
...
* gas/i386/i386.exp: Run x86-64-arch-2 instead of
x86-64-arch-10.
* gas/i386/x86-64-arch-10.d: Removed.
* gas/i386/x86-64-arch-2.d: New.
* gas/i386/x86-64-arch-2.s: Likewise.
2008-02-12 18:56:12 +00:00
a3ac9d5899
2008-02-12 H.J. Lu <hongjiu.lu@intel.com>
...
* gas/i386/x86-64-xsave.d: Remove prefix.
2008-02-12 15:35:29 +00:00
f03fe4c110
gas/
...
2008-02-11 H.J. Lu <hongjiu.lu@intel.com>
* config/tc-i386.c (cpu_arch): Add .xsave.
(md_show_usage): Add .xsave.
* doc/c-i386.texi: Add xsave to -march=.
gas/testsuite/
2008-02-11 H.J. Lu <hongjiu.lu@intel.com>
* gas/i386/arch-10.s: Add xgetbv.
* gas/i386/arch-10.d: Updated.
* gas/i386/arch-10-1.l: Likewise.
* gas/i386/arch-10-2.l: Likewise.
* gas/i386/arch-10-3.l: Likewise.
* gas/i386/arch-10-4.l: Likewise.
* gas/i386/x86-64-arch-10.d: Likewise.
opcodes/
2008-02-11 H.J. Lu <hongjiu.lu@intel.com>
* i386-gen.c (cpu_flag_init): Add CPU_XSAVE_FLAGS.
* i386-init.h: Updated.
2008-02-12 05:35:36 +00:00
475a2301db
gas/testsuite/
...
2002-02-11 H.J. Lu <hongjiu.lu@intel.com>
* gas/i386/i386.exp: Run xsave, xsave-intel, x86-64-xsave
and x86-64-xsave-intel.
* gas/i386/x86-64-xsave-intel.d: New file.
* gas/i386/x86-64-xsave.d: Likewise.
* gas/i386/x86-64-xsave.s: Likewise.
* gas/i386/xsave-intel.d: Likewise.
* gas/i386/xsave.d: Likewise.
* gas/i386/xsave.s: Likewise.
opcodes/
2008-02-11 H.J. Lu <hongjiu.lu@intel.com>
* i386-gen.c (cpu_flags): Add CpuXsave.
* i386-opc.h (CpuXsave): New.
(Cpu64): Updated.
(i386_cpu_flags): Add cpuxsave.
* i386-dis.c (MOD_0FAE_REG_4): New.
(RM_0F01_REG_2): Likewise.
(MOD_0FAE_REG_5): Updated.
(RM_0F01_REG_3): Likewise.
(reg_table): Use MOD_0FAE_REG_4.
(mod_table): Use RM_0F01_REG_2. Add MOD_0FAE_REG_4. Updated
for xrstor.
(rm_table): Add RM_0F01_REG_2.
* i386-opc.tbl: Add xsave, xrstor, xgetbv and xsetbv.
* i386-init.h: Regenerated.
* i386-tbl.h: Likewise.
2008-02-12 00:04:45 +00:00
0797561a54
* gas/mips/mips.exp: Invoke the tests smartmips, mips32-dsp,
...
mips32-dspr2, mips64-dsp and mips32-mt with run_dump_test instead
of run_dump_test_arches.
* gas/mips/smartmips.d: Pass -mips32.
* gas/mips/mips64-dsp.d: Pass -mips64r2.
* gas/mips/mips32-dsp.d: Pass -mips32r2.
* gas/mips/mips32-dspr2.d: Likewise.
* gas/mips/mips32-mt.d: Likewise.
2008-02-06 05:29:03 +00:00
61d4e56d1b
* gas/mips/mips.exp: Call mips_arch_create for Octeon. Invoke
...
Octeon tests.
* gas/mips/octeon.s, gas/mips/octeon.d: New test.
2008-02-04 19:19:43 +00:00
f8a52b5923
2008-01-31 Marc Gauthier <marc@tensilica.com>
...
bfd/
* config.bfd (xtensa*-*-*): Recognize processor variants.
gas/
* configure.tgt (xtensa*-*-*): Recognize processor variants.
gas/testsuite/
* gas/all/gas.exp: Recognize Xtensa processor variants.
* gas/elf/elf.exp: Likewise.
* gas/lns/lns.exp: Likewise.
ld/
* configure.tgt (xtensa*-*-*): Recognize processor variants.
ld/testsuite/
* ld-elf/merge.d: Recognize Xtensa processor variants.
* ld-xtensa/coalesce.exp: Likewise.
* ld-xtensa/lcall.exp: Likewise.
2008-02-01 17:58:48 +00:00
H.J. Lu
Dwarakanath Rajagopal
David S. Miller
Andrew Stubbs
Alan Modra
Nick Clifton
Andreas Krebbel
Kaz Kojima
Bernd Schmidt
Richard Sandiford
Paul Brook
Jan Beulich
Adam Nemet
Bob Wilson