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5933 Commits

Author SHA1 Message Date
Jan Beulich
989993d80a gas/testsuite/ 
2011-09-28  Jan Beulich  <jbeulich@suse.com>

	* gas/ppc/476.s: Fix lswi first operand.
	* gas/ppc/476.d: Adjust expected output.
	* gas/ppc/a2.s: Fix lswi first operand.
	* gas/ppc/a2.d: Adjust expected output.
	* gas/ppc/power6.s: Fix lfdpx first operand.
	* gas/ppc/power6.d: Adjust expected output.

opcodes/
2011-09-28  Jan Beulich  <jbeulich@suse.com>

	* ppc-opc.c (insert_nbi, insert_rbx, FRAp, FRBp, FRSp, FRTp, NBI, RAX,
	RBX): New.
	(insert_bo, insert_boe): Reject bcctr with bit 2 in bo unset.
	(powerpc_opcodes): Use RAX for second and RBXC for third operand of
	lswx. Use NBI for third operand of lswi. Use FRTp for first operand of
	lfdp and lfdpx. Use FRSp for first operand of stfdp and stfdpx, and
	mark them as invalid on POWER7. Use FRTp, FRAp, and FRBp repsectively
	on DFP quad instructions.
 2011-10-06 09:22:58 +00:00
Nick Clifton
d4cb0ea0ca * readelf.c (get_machine_dlags): Add support for RX's PID mode. 
* ld-scripts/phdrs.exp: Expect to fail for the RX.

	* elf32-rx.c: Add support for PID mode.
	(rx_elf_relocate_section): Add checks for unsafe PID relocations.
	Include addend in R_RX_SYM relocations.

	* config/rx-defs.h (rx_pid_register): New.
	(rx_gp_register): New.
	* config/rx-parse.y (rx_lex): Add support for %gpreg and %pidreg.
	(displacement): Add PID support.
	* config/tc-rx.c (rx_pid_mode): New.
	(rx_num_int_regs): New.
	(rx_pid_register): New.
	(rx_gp_register): New.
	(options): Add -mpid and -mint-register= options.
	(md_longopts): Likewise.
	(md_parse_option): Likewise.
	(md_show_usage): Likewise.
	(rx_pid_symbol): New.
	(rx_pidreg_symbol): New.
	(rx_gpreg_symbol): New.
	(md_begin): Support PID.
	(rx_validate_fix_sub): Support PID.
	(tc_gen_reloc): Support PID.
	* doc/c-rx.texi: Document PID support.

	* rx.h (E_FLAG_RX_PID): New.
 2011-10-05 14:13:31 +00:00
Kai Tietz
9af6978cc0 Another typo ... :( 2011-09-28 12:04:24 +00:00
Kai Tietz
8d7f3066f1 * gas/pe/section-exclude.d: Correct testcase. 2011-09-28 12:01:12 +00:00
Kai Tietz
c348982892 2011-09-27 Kai Tietz <ktietz@redhat.com> 
* config/obj-coff.c (obj_coff_section): Add 'e' as specifier
       for marking section SEC_EXCLUDE.

2011-09-27  Kai Tietz  <ktietz@redhat.com>

       * gas/pe/pe.exp: Add new testcase.
       * gas/pe/section-exclude.d: New file.
       * gas/pe/section-exclude.s: New file.
 2011-09-27 18:57:22 +00:00
David S. Miller
92a7795b59 opcodes/ 
* sparc-opc.c (sparc_opcodes): Fix random instruction to write
	to a float instead of an integer register.

gas/testsuite/

	* gas/sparc/hpcvis3.s: Update to use float reg for random insn.
	* gas/sparc/hpcvis3.d: Likewise.
 2011-09-27 04:30:32 +00:00
David S. Miller
e91d10767a Add sparc integer multiply-add instructions. 
opcodes/

	* sparc-opc.c (sparc_opcodes): Add integer multiply-add
	instructions.

gas/testsuite/

	* gas/sparc/ima.d: New test.
	* gas/sparc/ima.s: New test source.
	* gas/sparc/sparc.exp: Run new test.
 2011-09-26 09:19:24 +00:00
Tristan Gingold
a7142d9403 binutils/ 
2011-09-22  Tristan Gingold  <gingold@adacore.com>

	* NEWS: Add marker for 2.22.

gas/
2011-09-22  Tristan Gingold  <gingold@adacore.com>

	* NEWS: Add marker for 2.22.

ld/
2011-09-22  Tristan Gingold  <gingold@adacore.com>

	* NEWS: Add marker for 2.22.
 2011-09-22 08:11:16 +00:00
David S. Miller
4bafe00ecf Add new sparc options to control instruction availability. 
gas/

	* config/tc-sparc.c (hwcap_allowed): New.
	(struct sparc_arch): New field 'hwcap_allowed' containing a bitmask
	of F_FOO flags which are enabled by the particular arch setting.
	Add new options that provide explicit access to new instructions.
	(md_parse_option): Only bump max_architecture if the requested one
	is larger, or this is the first explicit request.
	(get_hwcap_name): New function.
	(sparc_ip): Validate that hwcaps used by an instruction have actually
	been enabled.
	* doc/c-sparc.texi: Document new sparc options.
 2011-09-22 00:03:30 +00:00
David S. Miller
527563502c Fix sparc testcases when building with 64-bit default. 
gas/testsuite/

	* gas/sparc/imm-plus-rreg.d: Fix address regex for 64-bit.
	* gas/sparc/save-args.d: Likewise.
	* gas/sparc/ticc-imm-reg.d: Likewise, add -32 to options.
	* gas/sparc/v8-movwr-imm.d: Likewise.
 2011-09-21 22:29:55 +00:00
David S. Miller
9e8c70f96b Annotate sparc objects with cpu hardware capabilities used. 
bfd/

	* elfxx-sparc.c (_bfd_sparc_elf_merge_private_bfd_data): New.
	* elfxx-sparc.h: Declare it.
	* elf32-sparc.c (elf32_sparc_merge_private_bfd_data): Call it.
	* elf64-sparc.c (elf64_sparc_merge_private_bfd_data): Likewise.

binutils/

	* readelf.c (display_sparc_hwcaps): New.
	(display_sparc_gnu_attribute): New.
	(process_sparc_specific): New.
	(process_arch_specific): When EM_SPARC, EM_SPARC32PLUS,
	or EM_SPARCV9 invoke process_sparc_specific.

gas/

	* config/tc-sparc.c (hwcap_seen): New bitmask, defined when
	not TE_SOLARIS.
	(sparc_ip): When not TE_SOLARIS, accumulate hwcap bits from
	sparc_opcode->flags of instruction into hwcap_seen.
	(sparc_md_end): Create Tag_GNU_Sparc_HWCAPS attribute if
	hwcap_seen is non-zero and not TE_SOLARIS.

gas/testsuite/

	* gas/sparc/hpcvis3.s: Update for fixed fchksum16 mnemonic.
	* gas/sparc/hpcvis3.d: Likewise.

include/elf/

	* sparc.h (Tag_GNU_Sparc_HWCAPS): New object attribute.
	(ELF_SPARC_HWCAP_*): New HWCAPS bitmask values.

include/opcode/

	* sparc.h (struct sparc_opcode): Expand 'flags' to unsigned int.
	(F_MUL32, F_DIV32, F_FSMULD, F_V8PLUS, F_POPC, F_VIS, F_VIS2,
	F_ASI_BLK_INIT, F_FMAF, F_VIS3, F_HPC, F_RANDOM, F_TRANS,
	F_FJFMAU, F_IMA, F_ASI_CACHE_SPARING): New flag bits.

opcodes/

	* sparc-opc.c (sparc_opcodes): Annotate table with HWCAP flag
	bits.  Fix "fchksm16" mnemonic.
 2011-09-21 20:49:16 +00:00
Tristan Gingold
a06413e3ef 2011-09-19 Tristan Gingold <gingold@adacore.com> 
* config/tc-alpha.c (insert_operand): Call as_bad_value_out_of_range
	instead of as_warn_out_of_range.
 2011-09-19 08:24:23 +00:00
Andreas Schwab
b2ea18299b Add PR markers 2011-09-10 08:13:45 +00:00
David S. Miller
8dbb9eb3c6 opcodes/ 
* sparc-opc.c (sparc_opcodes): Add entry for 'save simm13,regrs1,regrd'
	This has been reported as being accepted by the Sun assmebler.

gas/testsuite/

	* gas/sparc/save-args.[sd]: New test.
	* gas/sparc/sparc.exp: Run new test.
 2011-09-08 19:03:17 +00:00
David S. Miller
9bf29d72d4 opcodes/ 
The changes below bring 'mov' and 'ticc' instructions into line
	with the V8 SPARC Architecture Manual.
	* sparc-opc.c (sparc_opcodes): Add entry for 'ticc imm + regrs1'.
	* sparc-opc.c (sparc_opcodes): Add alias entries for
	'mov regrs2,%asrX'; 'mov regrs2,%y'; 'mov regrs2,%prs';
	'mov regrs2,%wim' and 'mov regrs2,%tbr'.
	* sparc-opc.c (sparc_opcodes): Move/Change entries for
	'mov imm,%asrX'; 'mov imm,%y'; 'mov imm,%prs'; 'mov imm,%wim'
	and 'mov imm,%tbr'.
	* sparc-opc.c (sparc_opcodes): Add wr alias entries to match above
	mov aliases.

gas/testsuite/

	* gas/sparc/ticc-imm-reg.[sd]: New test.
	* gas/sparc/v8-movwr-imm.[sd]: New test.
	* gas/sparc/sparc.exp: Run new tests.
 2011-09-08 19:01:11 +00:00
David S. Miller
f124dd4f3f gas/ 
* config/tc-sparc.c (sparc_ip): Handle 'i' + r<0..31>
	in addition to 'i' + [goli]<0..7>.

gas/testsuite/

	* gas/sparc/imm-plus-rreg.[sd]: New test.
	* gas/sparc/sparc.exp: Run new test.
 2011-09-08 16:56:10 +00:00
David S. Miller
cdf492019f opcodes/ 
* sparc-opc.c (pdistn): Destination is integer not float register.

gas/testsuite/

	* gas/sparc/hpcvis3.s: Correct pdistn test.
	* gas/sparc/hpcvis3.d: Likewise.
 2011-09-08 16:40:47 +00:00
Nick Clifton
32425e36f3 * cgen.c (gas_cgen_pcrel_r_type): New function. 
(gas_cgen_tc_gen_reloc): Check for GAS_CGEN_PCREL_R_TYPE.
	* cgen.h (gas_cgen_pcrel_r_type): Declare.
 2011-09-08 16:07:11 +00:00
Richard Sandiford
48b0740182 gas/ 
PR gas/13167
	* dwarf2dbg.c (dwarf2_flush_pending_lines): Use symbol_temp_new_now.

gas/testsuite/
	PR gas/13167
	* gas/ia64/pr13167.d, gas/ia64/pr13167.s: New test.
	* gas/ia64/ia64.exp: Run it.
 2011-09-08 12:18:28 +00:00
Andreas Schwab
96e67898bc * gas/testsuite/gas/m68k/all.exp: Run "mode5" test also with -mcpu=5200. 
* gas/testsuite/gas/m68k/mode5.s: Add moveml testcases.
* gas/testsuite/gas/m68k/mode5.d: Update.

* opcodes/m68k-opc.c: Use "y" in moveml pattern for mcfisa_a.
 2011-09-07 20:56:09 +00:00
Richard Sandiford
5045d76649 gas/ 
PR gas/13024
	* dwarf2dbg.c (pending_lines, pending_lines_tail): New variables.
	(dwarf2_gen_line_info_1): Delete.
	(dwarf2_push_line, dwarf2_flush_pending_lines): New functions.
	(dwarf2_gen_line_info, dwarf2_emit_label): Use them.
	(dwarf2_consume_line_info): Call dwarf2_flush_pending_lines.
	(dwarf2_directive_loc): Push previous .locs instead of generating
	them immediately.

gas/testsuite/
	* gas/mips/loc-swap-2.s, gas/mips/loc-swap-2.d,
	gas/mips/micromips@loc-swap-2.d,
	gas/mips/mips16@loc-swap-2.d: New test.
	* gas/mips/mips.exp: Run it.
 2011-09-05 19:19:01 +00:00
Nick Clifton
7cf8042268 Updated Spanish translations. 2011-08-26 15:15:52 +00:00
Tristan Gingold
0ac5db1998 2011-08-26 Tristan Gingold <gingold@adacore.com> 
* config/tc-alpha.c (s_alpha_linkage): Simplify.  Add comments.
 2011-08-26 13:37:28 +00:00
Tristan Gingold
0189c2eba7 2011-08-26 Tristan Gingold <gingold@adacore.com> 
* config/tc-alpha.c (add_to_link_pool): Improve comment.
	(s_alpha_fp_save): Fix indentation.
 2011-08-26 13:16:36 +00:00
H.J. Lu
be748880a3 Update AVX tests. 
2011-08-19  Sergey A. Guriev  <sergeya.a.guriev@intel.com>

	* gas/i386/avx-gather-intel.d: Added missing vpgather tests.
	* gas/i386/avx-gather.d: Likewise.
	* gas/i386/x86-64-avx-gather-intel.d: Likewise.
	* gas/i386/x86-64-avx-gather.d: Likewise.

	* gas/i386/avx-intel.d: Added missing vpinsrd and removed
	duplicated vpinsrb instructions.
	* gas/i386/avx.d: Likewise.
	* gas/i386/avx.s: Likewise.
	* gas/i386/ilp32/x86-64-avx-intel.d: Likewise.
	* gas/i386/ilp32/x86-64-avx.d: Likewise.
	* gas/i386/x86-64-avx-intel.d: Likewise.
	* gas/i386/x86-64-avx.d: Likewise.
	* gas/i386/x86-64-avx.s: Likewise.
 2011-08-19 19:27:53 +00:00
Nick Clifton
6753e72f10 * doc/as.texinfo: Include c-xstormy16.texi. 2011-08-19 14:48:40 +00:00
Alan Modra
7230378dfd * write.c (resolve_reloc_expr_symbols): Convert local symbols 
on relocs to section+offset.
	(get_frag_for_reloc): New function.
	(write_relocs): Merge sort fixup relocs with those from .reloc
	directives.
 2011-08-18 14:10:35 +00:00
Maciej W. Rozycki
87333bb72b * config/tc-mips.c (can_swap_branch_p): Update the comment on 
MIPS16 fixups.
 2011-08-10 22:55:57 +00:00
Maciej W. Rozycki
85bb418f5e * gas/mips/micromips@mips5.d: Rename to... 
* gas/mips/micromips@mips5-fp.d: ... this.
	* gas/mips/mips5.d: Rename to...
	* gas/mips/mips5-fp.d: ... this.
	* gas/mips/mips5.l: Rename to...
	* gas/mips/mips5-fp.l: ... this.
	* gas/mips/mips5.s: Rename to...
	* gas/mips/mips5-fp.s: ... this.
	* gas/mips/mips.exp: Update accordingly.
 2011-08-10 22:52:03 +00:00
Maciej W. Rozycki
8d367dd5c0 * gas/mips/mips.exp: Define new "fpisa3", "fpisa4" and "fpisa5" 
architecture properties adding them to "mips3", "mips4", "mips5"
	and "mips32r2" architectures.  Use the new properties for the
	"24k-triple-stores-1", "24k-triple-stores-3", "mips4-fp",
	"mips5" and "alnv_ps-swap" tests.
 2011-08-10 22:28:41 +00:00
Maciej W. Rozycki
b5503c7b66 * config/tc-mips.c (mips_cpu_info_table): Add "m14k" and 
"m14kc".
	* doc/c-mips.texi (MIPS architecture options): Add "m14k" and
	"m14kc" to the list of -march options.
 2011-08-09 15:25:32 +00:00
Maciej W. Rozycki
dec0624dcd gas/ 
* config/tc-mips.c (mips_set_options): Add ase_mcu.
	(mips_opts): Initialise ase_mcu to -1.
	(ISA_SUPPORTS_MCU_ASE): New macro.
	(MIPS_CPU_ASE_MCU): Likewise.
	(is_opcode_valid): Handle MCU.
	(macro_build, macro): Likewise.
	(validate_mips_insn, validate_micromips_insn): Likewise.
	(mips_ip): Likewise.
	(options): Add OPTION_MCU and OPTION_NO_MCU.
	(md_longopts): Add mmcu and mno-mcu.
	(md_parse_option): Handle OPTION_MCU and OPTION_NO_MCU.
	(mips_after_parse_args): Handle MCU.
	(s_mipsset): Likewise.
	(md_show_usage): Handle MCU options.

	* doc/as.texinfo: Document -mmcu and -mno-mcu options.
	* doc/c-mips.texi: Likewise, and document ".set mcu" and
	".set nomcu" directives.

	gas/testsuite/
	* gas/mips/micromips@mcu.d: New test.
	* gas/mips/mcu.d: Likewise.
	* gas/mips/mcu.s: New test source.
	* gas/mips/mips.exp: Run the new tests.

	include/opcode/
	* mips.h (OP_MASK_3BITPOS, OP_SH_3BITPOS): New macros.
	(OP_MASK_OFFSET12, OP_SH_OFFSET12): Redefine.
	(INSN_ASE_MASK): Add the MCU bit.
	(INSN_MCU): New macro.
	(M_ACLR_AB, M_ACLR_OB, M_ASET_AB, M_ASET_OB): New enum values.
	(MICROMIPSOP_MASK_3BITPOS, MICROMIPSOP_SH_3BITPOS): New macros.

	opcodes/
	* mips-dis.c (mips_arch_choices): Enable MCU for "mips32r2"
	and "mips64r2".
	(print_insn_args, print_insn_micromips): Handle MCU.
	* micromips-opc.c (MC): New macro.
	(micromips_opcodes): Add "aclr", "aset" and "iret".
	* mips-opc.c (MC): New macro.
	(mips_builtin_opcodes): Add "aclr", "aset" and "iret".
 2011-08-09 15:20:03 +00:00
Maciej W. Rozycki
2b0c8b40ed include/opcode/ 
* mips.h (INSN_WRITE_GPR_S, INSN2_WRITE_GPR_MB): New macros.
	(INSN2_READ_GPR_MC, INSN2_READ_GPR_ME): Likewise.
	(INSN2_WRITE_GPR_MF, INSN2_READ_GPR_MG): Likewise.
	(INSN2_READ_GPR_MJ, INSN2_WRITE_GPR_MJ): Likewise.
	(INSN2_READ_GPR_MP, INSN2_WRITE_GPR_MP): Likewise.
	(INSN2_READ_GPR_MQ, INSN2_WRITE_GPR_MHI): Likewise.
	(INSN2_READ_GPR_MMN): Likewise.
	(INSN2_READ_FPR_D): Change the bit used.
	(INSN2_MOD_GPR_MD, INSN2_MOD_GPR_MF): Likewise.
	(INSN2_MOD_SP, INSN2_READ_GPR_31, INSN2_READ_GP): Likewise.
	(INSN2_READ_PC, INSN2_UNCOND_BRANCH): Likewise.
	(INSN2_COND_BRANCH): Likewise.
	(INSN2_WRITE_GPR_S, INSN2_MOD_GPR_MB): Remove macros.
	(INSN2_MOD_GPR_MC, INSN2_MOD_GPR_ME, INSN2_MOD_GPR_MG): Likewise.
	(INSN2_MOD_GPR_MJ, INSN2_MOD_GPR_MP, INSN2_MOD_GPR_MQ): Likewise.
	(INSN2_MOD_GPR_MHI, INSN2_MOD_GPR_MM): Likewise.
	(INSN2_MOD_GPR_MN): Likewise.

	gas/
	* config/tc-mips.c (gpr_mod_mask): Remove INSN2_MOD_GPR_MB,
	INSN2_MOD_GPR_MC, INSN2_MOD_GPR_ME, INSN2_MOD_GPR_MG,
	INSN2_MOD_GPR_MHI, INSN2_MOD_GPR_MJ, INSN2_MOD_GPR_MM,
	INSN2_MOD_GPR_MN, INSN2_MOD_GPR_MP and INSN2_MOD_GPR_MQ opcode
	register use checks.
	(gpr_read_mask): Add INSN2_READ_GPR_MC, INSN2_READ_GPR_ME
	INSN2_READ_GPR_MG, INSN2_READ_GPR_MJ, INSN2_READ_GPR_MMN,
	INSN2_READ_GPR_MP and INSN2_READ_GPR_MQ opcode register use
	checks.
	(gpr_write_mask): Replace INSN2_WRITE_GPR_S opcode register
	use flag with INSN_WRITE_GPR_S.  Add INSN2_WRITE_GPR_MB,
	INSN2_WRITE_GPR_MHI, INSN2_WRITE_GPR_MJ and INSN2_WRITE_GPR_MP
	opcode register use checks.
	(can_swap_branch_p): Enable microMIPS branch swapping.
	(append_insn): Likewise.

	gas/testsuite/
	* gas/mips/micromips.d: Update according to changes to enable
	microMIPS branch swapping.
	* gas/mips/micromips-trap.d: Likewise.
	* gas/mips/micromips@jal-svr4pic.d: Likewise.
	* gas/mips/micromips@loc-swap.d: Likewise.
	* gas/mips/micromips@loc-swap-dis.d: Likewise.

	opcodes/
	* micromips-opc.c (MOD_mb, MOD_mc, MOD_md): Remove macros.
	(MOD_me, MOD_mf, MOD_mg, MOD_mhi, MOD_mj, MOD_ml): Likewise.
	(MOD_mm, MOD_mn, MOD_mp, MOD_mq, MOD_sp): Likewise.
	(WR_mb, RD_mc, RD_md, WR_md, RD_me, RD_mf, WR_mf): New macros.
	(RD_mg, WR_mhi, RD_mj, WR_mj, RD_ml, RD_mmn): Likewise.
	(RD_mp, WR_mp, RD_mq, RD_sp, WR_sp): Likewise.
	(WR_s): Update macro.
	(micromips_opcodes): Update register use flags of: "addiu",
	"addiupc", "addiur1sp", "addiur2", "addius5", "addiusp", "addu",
	"and", "andi", "beq", "beqz", "bne", "bnez", "di", "ei", "j",
	"jalr", "jalrs", "jr", "jraddiusp", "jrc", "lbu", "lhu", "li",
	"lui", "lw", "lwm", "mfhi", "mflo", "move", "movep", "not",
	"nor", "or", "ori", "sb", "sh", "sll", "srl", "subu", "sw",
	"swm" and "xor" instructions.
 2011-08-09 14:25:29 +00:00
Maciej W. Rozycki
40209cad0b * config/tc-mips.c (RELAX_MICROMIPS_ENCODE): Remove forced 16-bit 
branch size information.
	(RELAX_MICROMIPS_U16BIT): Remove macro.
	(RELAX_MICROMIPS_UNCOND): Adjust accordingly.
	(RELAX_MICROMIPS_COMPACT, RELAX_MICROMIPS_LINK): Likewise.
	(RELAX_MICROMIPS_RELAX32): Likewise.
	(RELAX_MICROMIPS_TOOFAR16): Likewise.
	(RELAX_MICROMIPS_MARK_TOOFAR16): Likewise.
	(RELAX_MICROMIPS_CLEAR_TOOFAR16): Likewise.
	(RELAX_MICROMIPS_TOOFAR32): Likewise.
	(RELAX_MICROMIPS_MARK_TOOFAR32): Likewise.
	(RELAX_MICROMIPS_CLEAR_TOOFAR32): Likewise.
	(append_insn): Always check forced_insn_length for microMIPS
	relaxation.  Adjust code for the removal of
	RELAX_MICROMIPS_U16BIT.
	(mips_ip) <'D', 'E'>: If forced_insn_length, then emit the
	relocation straight away.
	(relaxed_micromips_16bit_branch_length): Adjust code for the
	removal of RELAX_MICROMIPS_U16BIT.
 2011-08-09 13:39:39 +00:00
Tristan Gingold
74a6005fea 2011-08-08 Tristan Gingold <gingold@adacore.com> 
* config/obj-macho.c (obj_mach_o_section): New function.
	(struct known_section): New type.
	(known_sections): Declare.
	(obj_mach_o_known_section): New function.
	(obj_mach_o_common_parse): Ditto.
	(obj_mach_o_comm): Ditto.
	(obj_mach_o_subsections_via_symbols): Ditto.
	(mach_o_pseudo_table): Add new pseudos.
 2011-08-08 12:20:01 +00:00
Richard Henderson
af385746fb * dw2gencfi.c (all_fde_data): Export. 
* dw2gencfi.h (all_fde_data): Declare.
        * config/tc-alpha.c (alpha_elf_md_end): Don't convert legacy unwind
        info to cfi unwind info if the user already has supplied some.
 2011-08-07 16:32:20 +00:00
Richard Sandiford
14fe068bd8 gas/ 
* config/tc-mips.c (emit_nop): Delete.
	(get_delay_slot_nop): New function.
	(nops_for_insn_or_target): Use it.
	(append_insn): Likewise.  When avoiding hazards, call add_fixed_insn
	and insert_into_history directly.
 2011-08-06 10:25:01 +00:00
Richard Sandiford
11625dd84f gas/ 
* config/tc-mips.c (delayed_branch_p, compact_branch_p)
	(uncond_branch_p, branch_likely_p): New functions.
	(insns_between, nops_for_insn_or_target, append_insn)
	(macro_start): Use them.
	(get_append_method): Likewise.  Remove redundant test.
 2011-08-06 10:02:03 +00:00
David S. Miller
ea783ef3a0 include/opcode/ 
* sparc.h: Document new format codes '4', '5', and '('.
	(OPF_LOW4, RS3): New macros.
opcodes/
	* sparc-dis.c (v9a_ast_reg_names): Add "cps".
	(X_RS3): New macro.
	(print_insn_sparc): Handle '4', '5', and '(' format codes.
	Accept %asr numbers below 28.
	* sparc-opc.c (sparc_opcodes): Add entries for HPC and VIS3
	instructions.
gas/
	* config/tc-sparc.c (v9a_asr_table): Add "cps".
	(sparc_ip): Handle '4', '5' and '(' format codes.
gas/testsuite
	* gas/sparc/hpcvis3.d: New test.
	* gas/sparc/hpcvis3.s: New test source.
	* gas/sparc/sparc.exp: Run new test.
 2011-08-05 16:52:50 +00:00
H.J. Lu
13077567ee Update gas/i386/x86-64-branch.d to support win64. 
2011-08-05  H.J. Lu  <hongjiu.lu@intel.com>

	* gas/i386/x86-64-branch.d: Pass -dw to objdump and support
	win64.
 2011-08-05 14:11:43 +00:00
H.J. Lu
2ae0848317 Call bfd_cache_close_all on error 
2011-08-04  H.J. Lu  <hongjiu.lu@intel.com>

	PR gas/13056
	* output-file.c (output_file_close): Call bfd_cache_close_all
	on error.

	* write.c (write_object_file): Revert the last change.
 2011-08-04 20:53:58 +00:00
H.J. Lu
cfba7fd516 Add a testcase for group error. 
2011-08-04  H.J. Lu  <hongjiu.lu@intel.com>

	* gas/elf/bad-group.d: New.
	* gas/elf/bad-group.err: Likewise.
	* gas/elf/bad-group.s: Likewise.

	* gas/elf/elf.exp: Run bad-group.
 2011-08-04 20:20:11 +00:00
Alan Modra
5e9f6467f7 * write.c (write_object_file): Call set_symtab even if we had 
errors.
 2011-08-04 10:24:00 +00:00
Tristan Gingold
249a777b4c 2011-08-04 Tristan Gingold <gingold@adacore.com> 
* config/obj-elf.c (obj_elf_section): Do not free name.
 2011-08-04 07:44:44 +00:00
Nick Clifton
877807f8c4 * config/tc-arm.c (do_t_strexbh): New. 
(insns): Update accordingly.

	* gas/arm/strex-bad-t.d: New testcase.
	* gas/arm/strex-bad-t.s: Likewise.
	* gas/arm/strex-bad-t.l: Likewise.
	* gas/arm/strex-t.s: Likewise.
	* gas/arm/strex-t.d: Likewise.
 2011-08-03 11:35:56 +00:00
H.J. Lu
d7921315ba Check R_X86_64_32 overflow and allow R_X86_64_64 for x32. 
bfd/

2011-08-01  H.J. Lu  <hongjiu.lu@intel.com>

	PR ld/13048
	* archures.c (bfd_mach_i386_intel_syntax): New.
	(bfd_mach_i386_i8086): Updated.
	(bfd_mach_i386_i386): Likewise.
	(bfd_mach_x86_64): Likewise.
	(bfd_mach_x64_32): Likewise.
	(bfd_mach_i386_i386_intel_syntax): Likewise.
	(bfd_mach_x86_64_intel_syntax): Likewise.
	(bfd_mach_x64_32_intel_syntax): Likewise.
	(bfd_mach_l1om): Likewise.
	(bfd_mach_l1om_intel_syntax): Likewise.
	(bfd_mach_k1om): Likewise.
	(bfd_mach_k1om_intel_syntax): Likewise.

	* bfd-in2.h: Regenerated.

	* cpu-i386.c (bfd_i386_compatible): Check mach instead of
	bits_per_address.
	(bfd_x64_32_arch_intel_syntax): Set bits_per_address to 64.
	(bfd_x64_32_arch): Likewise.

	* elf64-x86-64.c: Include "libiberty.h".
	(x86_64_elf_howto_table): Append x32 R_X86_64_32.
	(elf_x86_64_rtype_to_howto): Support x32 R_X86_64_32.
	(elf_x86_64_reloc_type_lookup): Likewise.
	(elf_x86_64_reloc_name_lookup): Likewise.
	(elf_x86_64_relocate_section): Likewise.
	(elf_x86_64_check_relocs): Allow R_X86_64_64 relocations for x32.

gas/

2011-08-01  H.J. Lu  <hongjiu.lu@intel.com>

	PR ld/13048
	* config/tc-i386.c (handle_quad): Removed.
	(md_pseudo_table): Remove "quad".
	(tc_gen_reloc): Don't check BFD_RELOC_64 for disallow_64bit_reloc.
	(x86_dwarf2_addr_size): New.

	* config/tc-i386.h (x86_dwarf2_addr_size): New.
	(DWARF2_ADDR_SIZE): Likewise.

gas/testsuite/

2011-08-01  H.J. Lu  <hongjiu.lu@intel.com>

	PR ld/13048
	* gas/i386/ilp32/ilp32.exp: Don't run inval.

	* gas/i386/ilp32/inval.l: Removed.
	* gas/i386/ilp32/inval.s: Likewise.

	* gas/i386/ilp32/quad.d: Expect R_X86_64_64 instead of
	R_X86_64_32.

	* gas/i386/ilp32/x86-64-pcrel.s: Add tests for movabs.
	* gas/i386/ilp32/x86-64-pcrel.d: Updated.

ld/testsuite/

2011-08-01  H.J. Lu  <hongjiu.lu@intel.com>

	PR ld/13048
	* ld-x86-64/ilp32-6.d: New.
	* ld-x86-64/ilp32-6.s: Likewise.
	* ld-x86-64/ilp32-7.d: Likewise.
	* ld-x86-64/ilp32-7.s: Likewise.
	* ld-x86-64/ilp32-8.d: Likewise.
	* ld-x86-64/ilp32-8.s: Likewise.
	* ld-x86-64/ilp32-9.d: Likewise.
	* ld-x86-64/ilp32-9.s: Likewise.

	* ld-x86-64/x86-64.exp: Run ilp32-6, ilp32-7, ilp32-8 and ilp32-9.

opcodes/

2011-08-01  H.J. Lu  <hongjiu.lu@intel.com>

	PR ld/13048
	* i386-dis.c (print_insn): Optimize info->mach check.
 2011-08-01 23:04:23 +00:00
H.J. Lu
00f51a41a8 Add Disp32S to 64bit call. 
gas/testsuite/

2011-08-01  H.J. Lu  <hongjiu.lu@intel.com>

	PR gas/13046
	* gas/i386/x86-64-branch.s: Add tests for direct branch.
	* gas/i386/x86-64-branch.d: Updated.
	* gas/i386/ilp32/x86-64-branch.d: Likewise.

opcodes/

2011-08-01  H.J. Lu  <hongjiu.lu@intel.com>

	PR gas/13046
	* i386-opc.tbl: Add Disp32S to 64bit call.
	* i386-tbl.h: Regenerated.
 2011-08-01 19:25:48 +00:00
Nick Clifton
a8040cf231 PR ld/12974 
* config/tc-arm.c (literal_pool): Add locs field.
	(add_to_lit_pool): Initialise the locs entry for the new literal.
	(s_ltorg): Generate a DWARF2 line number entry for each emitted
	literal pool entry.
 2011-08-01 11:27:14 +00:00
Tristan Gingold
1596988d53 2011-08-01 Tristan Gingold <gingold@adacore.com> 
* write.c (write_relocs): Fix -Wshadow in DEBUG3 and DEBUG4.
 2011-08-01 09:05:40 +00:00
Tristan Gingold
8d8385cfb8 2011-08-01 Tristan Gingold <gingold@adacore.com> 
* frags.c (frag_grow): Simplify the code.
 2011-08-01 08:05:49 +00:00