It again can be inferred from other information.
The vpopcntd templates all need to have Dword added to their memory
operands; the lack thereof was actually a bug preventing certain Intel
syntax code to assemble, so test cases get extended.
In the course of folding their patterns (possible now that the pointless
and partly even bogus VecESize are no longer in the way) I've noticed
that vcvt*2usi, other than their vcvt*2si counterparts, don't allow for
any suffixes. As that is supposedly intentional, make the disassembler
consistently omit suffixes for all to-scalar-int conversion insns.
A few of them were missed in commit 7ac2002247 ("x86: derive DispN
from BaseIndex") and also couldn't be removed by subsequent commits
touching certain templates anyway.
The wrong placement of the Load attribute in the templates prevented
this from working. The disassembler also didn't handle this consistently
with other similar dual-encoding insns.
While many templates allowing multiple suitably matching XMM/YMM/ZMM
operand sizes can be folded, a few need to be split in order to not
wrongly accept "xmmword ptr" operands when only XMM registers are
permitted (and memory operands are more narrow). Add a test case
validating this.
"clr reg" is an alias of "xor reg, reg". We can encode "clr reg64" as
"xor reg32, reg32".
gas/
* config/tc-i386.c (optimize_encoding): Also encode "clr reg64"
as "xor reg32, reg32".
* testsuite/gas/i386/x86-64-optimize-1.s: Add "clr reg64" tests.
* testsuite/gas/i386/x86-64-optimize-1.d: Updated.
opcodes/
* i386-opc.tbl: Add Optimize to clr.
* i386-tbl.h: Regenerated.
The differences between some of the register and memory forms of the
same insn often don't really require the templates to be separate. For
example, Disp8MemShift is simply irrelevant to register forms. Fold
these as far as possible, and also fold register-only forms. Further
folding is possible, but needs other prereq work done first.
A note regarding EVEXDYN: This is intended to be used only when no other
properties of the template would make is_evex_encoding() return true. In
all "normal" cases I think it is preferable to omit this indicator, to
keep the table half way readable.
Their memory forms were bogusly using VexLWP instead of VexNDD. Adjust
VexNDD handling to cope with these, allowing their register and memory
forms to be folded.
The differences between some of the register and memory forms of the
same insn often don't really require the templates to be separate. For
example, Disp8MemShift is simply irrelevant to register forms. Fold them
as far as possible. Further folding is possible, but needs other prereq
work done first.
They aren't really useful (anymore?): The conflicting operand size check
isn't applicable to any insn validly using respective memory operand
sizes (and if they're used wrongly, another error would result), and the
logic in process_suffix() can be easily changed to work without them.
While re-structuring conditionals in process_suffix() also drop the
CMPXCHG8B special case in favor of a NoRex64 attribute in the opcode
table.
Neither touches any XMM register, so the check is pointless. It is imo
even questionable whether in SSE2AVX mode the two should be converted to
their AVX counterparts.
fsub/fsubr/fsubp/fsubrp as well as fdiv/fdivr/fdivp/fdivrp disassembly
should match (a) the Intel SDM and (b) respective input fed to gas (both
of course with the exception of when we intentionally convert bogus
insns, accompanied by a warning).
This requires a change to ModR/M handling: Recording of displacement
types must not discard operand size information. Change the respective
code to alter only .disp<N>.
xcoff (32-bit) objdump accepted but ignored -M options unless
-mpowerpc was also given. This patch fixes that, leaving the default
as -Mpwr for xcoff. I've also enabled more tests for xcoff targets.
binutils/
* configure.ac: Add objdump_private_desc_xcoff for rs6000.
* configure: Regenerate.
gas/
* testsuite/gas/ppc/aix.exp: Run for rs6000 too.
* testsuite/gas/ppc/ppc.exp: Run more tests for non-ELF targets.
* testsuite/gas/ppc/machine.d: Don't run for PE targets.
opcodes/
* disassemble.c (disassembler): Use bfd_arch_powerpc entry for
bfd_arch_rs6000.
* disassemble.h (print_insn_rs6000): Delete.
* ppc-dis.c (powerpc_init_dialect): Handle rs6000.
(disassemble_init_powerpc): Call powerpc_init_dialect for rs6000.
(print_insn_rs6000): Delete.
Among the macros to manipulate an arm_feature_set structure is the
ARM_FEATURE_COPY which copy the value of a feature set into another.
This can be achieved with a simple assignement which most of the
existing code does. This patch removes the last 2 uses of that macro and
remove the macro altogether.
2018-02-27 Thomas Preud'homme <thomas.preudhomme@arm.com>
include/
* opcode/arm.h (ARM_FEATURE_COPY): Remove macro definition.
2018-02-27 Thomas Preud'homme <thomas.preudhomme@arm.com>
opcodes/
* arm-dis.c (print_insn_coprocessor): Replace uses of ARM_FEATURE_COPY
macro by assignements.
On x86, some instructions have alternate shorter encodings:
1. When the upper 32 bits of destination registers of
andq $imm31, %r64
testq $imm31, %r64
xorq %r64, %r64
subq %r64, %r64
known to be zero, we can encode them without the REX_W bit:
andl $imm31, %r32
testl $imm31, %r32
xorl %r32, %r32
subl %r32, %r32
This optimization is enabled with -O, -O2 and -Os.
2. Since 0xb0 mov with 32-bit destination registers zero-extends 32-bit
immediate to 64-bit destination register, we can use it to encode 64-bit
mov with 32-bit immediates. This optimization is enabled with -O, -O2
and -Os.
3. Since the upper bits of destination registers of VEX128 and EVEX128
instructions are extended to zero, if all bits of destination registers
of AVX256 or AVX512 instructions are zero, we can use VEX128 or EVEX128
encoding to encode AVX256 or AVX512 instructions. When 2 source
registers are identical, AVX256 and AVX512 andn and xor instructions:
VOP %reg, %reg, %dest_reg
can be encoded with
VOP128 %reg, %reg, %dest_reg
This optimization is enabled with -O2 and -Os.
4. 16-bit, 32-bit and 64-bit register tests with immediate may be
encoded as 8-bit register test with immediate. This optimization is
enabled with -Os.
This patch does:
1. Add {nooptimize} pseudo prefix to disable instruction size
optimization.
2. Add optimize to i386_opcode_modifier to tell assembler that encoding
of an instruction may be optimized.
gas/
PR gas/22871
* NEWS: Mention -O[2|s].
* config/tc-i386.c (_i386_insn): Add no_optimize.
(optimize): New.
(optimize_for_space): Likewise.
(fits_in_imm7): New function.
(fits_in_imm31): Likewise.
(optimize_encoding): Likewise.
(md_assemble): Call optimize_encoding to optimize encoding.
(parse_insn): Handle {nooptimize}.
(md_shortopts): Append "O::".
(md_parse_option): Handle -On.
* doc/c-i386.texi: Document -O0, -O, -O1, -O2 and -Os as well
as {nooptimize}.
* testsuite/gas/cfi/cfi-x86_64.d: Pass -O0 to assembler.
* testsuite/gas/i386/ilp32/cfi/cfi-x86_64.d: Likewise.
* testsuite/gas/i386/i386.exp: Run optimize-1, optimize-2,
optimize-3, x86-64-optimize-1, x86-64-optimize-2,
x86-64-optimize-3 and x86-64-optimize-4.
* testsuite/gas/i386/optimize-1.d: New file.
* testsuite/gas/i386/optimize-1.s: Likewise.
* testsuite/gas/i386/optimize-2.d: Likewise.
* testsuite/gas/i386/optimize-2.s: Likewise.
* testsuite/gas/i386/optimize-3.d: Likewise.
* testsuite/gas/i386/optimize-3.s: Likewise.
* testsuite/gas/i386/x86-64-optimize-1.s: Likewise.
* testsuite/gas/i386/x86-64-optimize-1.d: Likewise.
* testsuite/gas/i386/x86-64-optimize-2.d: Likewise.
* testsuite/gas/i386/x86-64-optimize-2.s: Likewise.
* testsuite/gas/i386/x86-64-optimize-3.d: Likewise.
* testsuite/gas/i386/x86-64-optimize-3.s: Likewise.
* testsuite/gas/i386/x86-64-optimize-4.d: Likewise.
* testsuite/gas/i386/x86-64-optimize-4.s: Likewise.
opcodes/
PR gas/22871
* i386-gen.c (opcode_modifiers): Add Optimize.
* i386-opc.h (Optimize): New enum.
(i386_opcode_modifier): Add optimize.
* i386-opc.tbl: Add "Optimize" to "mov $imm, reg",
"sub reg, reg/mem", "test $imm, acc", "test $imm, reg/mem",
"and $imm, acc", "and $imm, reg/mem", "xor reg, reg/mem",
"movq $imm, reg" and AVX256 and AVX512 versions of vandnps,
vandnpd, vpandn, vpandnd, vpandnq, vxorps, vxorpd, vpxor,
vpxord and vpxorq.
* i386-tbl.h: Regenerated.
gcc8 complains wrongly about the buffer not being large enough, at
least at -Og optimization.
* crx-dis.c (getregliststring): Allocate a large enough buffer
to silence false positive gcc8 warning.
Add {rex} pseudo prefix to generate a REX byte for integer and legacy
vector instructions if possible. Note that this differs from the rex
prefix which generates REX prefix unconditionally.
gas/
* config/tc-i386.c (_i386_insn): Add rex_encoding.
(md_assemble): When i.rex_encoding is true, generate a REX byte
if possible.
(parse_insn): Set i.rex_encoding for {rex}.
* doc/c-i386.texi: Document {rex}.
* testsuite/gas/i386/x86-64-pseudos.s: Add {rex} tests.
* testsuite/gas/i386/x86-64-pseudos.d: Updated.
opcodes/
* i386-opc.tbl: Add {rex},
* i386-tbl.h: Regenerated.
The `M' and `m' MIPS16 operand codes are functionally the same, denoting
a 7-bit register list that is encoded the same way for both SAVE and
RESTORE. Use `m' for both instructions then, making `M' available for a
different use.
opcodes/
* mips16-opc.c (decode_mips16_operand) <'M'>: Remove case.
(mips16_opcodes): Replace `M' with `m' for "restore".
include/
* opcode/mips.h: Remove `M' operand code.
Bit 7 of BXNS is a fixed bit which distinguish it from BLXNS. Yet it is
not set in the disassembler entry mask. This commit fixes that.
2018-02-19 Thomas Preud'homme <thomas.preudhomme@arm.com>
opcodes/
* arm-dis.c (thumb_opcodes): Fix BXNS mask.
Remove `-Wshadow' compilation errors:
cc1: warnings being treated as errors
.../bfd/wasm-module.c: In function 'wasm_scan_name_function_section':
.../bfd/wasm-module.c:312: error: declaration of 'index' shadows a global declaration
/usr/include/string.h:303: error: shadowed declaration is here
.../bfd/wasm-module.c: In function 'wasm_register_section':
.../bfd/wasm-module.c:494: error: declaration of 'index' shadows a global declaration
/usr/include/string.h:303: error: shadowed declaration is here
.../bfd/wasm-module.c: In function 'wasm_compute_custom_section_file_position':
.../bfd/wasm-module.c:523: error: declaration of 'index' shadows a global declaration
/usr/include/string.h:303: error: shadowed declaration is here
and:
cc1: warnings being treated as errors
.../opcodes/wasm32-dis.c: In function 'print_insn_wasm32':
.../opcodes/wasm32-dis.c:272: error: declaration of 'index' shadows a global declaration
/usr/include/string.h:303: error: shadowed declaration is here
make[4]: *** [wasm32-dis.lo] Error 1
which for versions of GCC before 4.8 prevent support for the WebAssembly
target from being built. See also GCC PR c/53066.
bfd/
* wasm-module.c (wasm_scan_name_function_section): Rename
`index' local variable to `idx'.
opcodes/
* wasm32-dis.c (print_insn_wasm32): Rename `index' local
variable to `function_index'.
The instruction encoding for the MIPS r6 sigrie instruction seems to be
incorrect. It's currently 0x4170xxxx (which overlaps with ei, di, evp,
and dvp), but should be 0x0417xxxx. See ISA reference[1][2].
References:
[1] "MIPS Architecture for Programmers Volume II-A: The MIPS32
Instruction Set Manual", Imagination Technologies, Inc., Document
Number: MD00086, Revision 6.06, December 15, 2016, Table A.4 "MIPS32
REGIMM Encoding of rt Field", p. 452
[2] "MIPS Architecture For Programmers Volume II-A: The MIPS64
Instruction Set Reference Manual", Imagination Technologies, Inc.,
Document Number: MD00087, Revision 6.06, December 15, 2016, Table
A.4 "MIPS64 REGIMM Encoding of rt Field", p. 581
opcodes/
* mips-opc.c (mips_builtin_opcodes): Correct "sigrie" encoding.
gas/
* testsuite/gas/mips/r6.d: Update for "sigrie" encoding fix.
* testsuite/gas/mips/r6-n32.d: Likewise.
* testsuite/gas/mips/r6-n64.d: Likewise.
gas/
* testsuite/gas/riscv/c-zero-imm.s: Test addi that compresses to c.nop.
* testsuite/gas/riscv/c-zero-imm.d: Likewise.
opcodes/
* riscv-opc.c (match_c_nop): New.
(riscv_opcodes) <addi>: Handle an addi that compresses to c.nop.
Jan Beulich
Nick Clifton
Jim Wilson
H.J. Lu
Alan Modra
Thomas Preud'homme
Maciej W. Rozycki
Henry Wong
Igor Tsimbalist