* m68k.h (mcf_mask): Define.
opcodes/
* m68k-opc.c (m68k_opcodes): Fix the masks of the Coldfire fmovemd
and fmovem entries. Put register list entries before immediate
mask entries. Use "l" rather than "L" in the fmovem entries.
* m68k-dis.c (match_insn_m68k): Remove the PRIV argument and work it
out from INFO.
(m68k_scan_mask): New function, split out from...
(print_insn_m68k): ...here. If no architecture has been set,
first try printing an m680x0 instruction, then try a Coldfire one.
gas/testsuite/
* gas/m68k/mcf-fpu.s: Add fmovemd and fmovem instructions.
* gas/m68k/mcf-fpu.d: Adjust accordingly.
2006-04-30 Thiemo Seufer <ths@mips.com>
David Ung <davidu@mips.com>
* config/tc-mips.c (validate_mips_insn): Handling of udi cases.
(mips_immed): New table that records various handling of udi
instruction patterns.
(mips_ip): Adds udi handling.
[ include/opcode/ChangeLog ]
2006-04-30 Thiemo Seufer <ths@mips.com>
David Ung <davidu@mips.com>
* mips.h: Defines udi bits and masks. Add description of
characters which may appear in the args field of udi
instructions.
[ opcodes/ChangeLog ]
2006-04-30 Thiemo Seufer <ths@mips.com>
David Ung <davidu@mips.com>
* mips-opc.c (mips_builtin_opcodes): Add udi instructions
"udi0" to "udi15".
* mips-dis.c (print_insn_args): Adds udi argument handling.
2006-04-06 H.J. Lu <hongjiu.lu@intel.com>
* elfxx-ia64.c (elfNN_ia64_relax_section): Skip unneeded passes
with the skip_relax_pass_0 and skip_relax_pass_1 bits in the
section structure.
include/
2006-04-06 H.J. Lu <hongjiu.lu@intel.com>
* bfdlink.h (bfd_link_info): Replace need_relax_finalize with
relax_pass.
ld/
2006-04-06 H.J. Lu <hongjiu.lu@intel.com>
* emultempl/ia64elf.em: Set link_info.relax_pass to 2. Remove
link_info.need_relax_finalize.
* ldlang.c (relax_sections): New.
(lang_process): Use. Call relax_sections link_info.relax_pass
times.
* ldmain.c (main): Set link_info.relax_pass to 1. Remove
link_info.need_relax_finalize.
bfd/ChangeLog:
* reloc.c: Add BFD_RELOC_X86_64_GOT64, BFD_RELOC_X86_64_GOTPCREL64,
BFD_RELOC_X86_64_GOTPC64, BFD_RELOC_X86_64_GOTPLT64,
BFD_RELOC_X86_64_PLTOFF64.
* bfd-in2.h: Regenerated.
* libbfd.h: Regenerated.
* elf64-x86-64.c (x86_64_elf_howto_table): Correct comment.
Add howtos for above relocs.
(x86_64_reloc_map): Add mappings for new relocs.
(elf64_x86_64_check_relocs): R_X86_64_GOT64, R_X86_64_GOTPCREL64,
R_X86_64_GOTPLT64 need a got entry. R_X86_64_GOTPLT64 also a PLT
entry. R_X86_64_GOTPC64 needs a .got section. R_X86_64_PLTOFF64
needs a PLT entry.
(elf64_x86_64_gc_sweep_hook): Reflect changes from
elf64_x86_64_check_relocs for the new relocs.
(elf64_x86_64_relocate_section): Handle new relocs.
gas/ChangeLog:
* config/tc-i386.c (type_names): Correct placement of 'static'.
(reloc): Map some more relocs to their 64 bit counterpart when
size is 8.
(output_insn): Work around breakage if DEBUG386 is defined.
(output_disp): A BFD_RELOC_64 with GOT_symbol as operand also
needs to be mapped to BFD_RELOC_X86_64_GOTPC64 or
BFD_RELOC_X86_64_GOTPC32. Also x86-64 handles pcrel addressing
different from i386.
(output_imm): Ditto.
(lex_got): Recognize @PLTOFF and @GOTPLT. Make @GOT accept also
Imm64.
(md_convert_frag): Jumps can now be larger than 2GB away, error
out in that case.
(tc_gen_reloc): New relocs are passed through. BFD_RELOC_64
and BFD_RELOC_64_PCREL are mapped to BFD_RELOC_X86_64_GOTPC64.
gas/testsuite/ChangeLog:
* gas/i386/reloc64.s: Accept 64-bit forms.
* gas/i386/reloc64.d: Adjust.
* gas/i386/reloc64.l: Adjust.
include/ChangeLog:
* elf/x86-64.h: Add the new relocations with their official
numbers.
Daniel Jacobowitz <dan@codesourcery.com>
Phil Edwards <phil@codesourcery.com>
Zack Weinberg <zack@codesourcery.com>
Mark Mitchell <mark@codesourcery.com>
Nathan Sidwell <nathan@codesourcery.com>
bfd/
* bfd-in2.h: Regenerate.
* config.bfd (mips*-*-vxworks*, mips*el-*-vxworks*): New stanzas.
* configure.in (bfd_elf32_bigmips_vxworks_vec): New stanza.
(bfd_elf32_littlemips_vxworks_vec): Likewise.
(bfd_elf32_bigmips_vec): Add elf-vxworks.lo.
(bfd_elf32_littlemips_vec): Likewise.
(bfd_elf32_nbigmips_vec): Likewise.
(bfd_elf32_nlittlemips_vec): Likewise.
(bfd_elf32_ntradbigmips_vec): Likewise.
(bfd_elf32_ntradlittlemips_vec): Likewise.
(bfd_elf32_tradbigmips_vec): Likewise.
(bfd_elf32_tradlittlemips_vec): Likewise.
(bfd_elf64_bigmips_vec): Likewise.
(bfd_elf64_littlemips_vec): Likewise.
(bfd_elf64_tradbigmips_vec): Likewise.
(bfd_elf64_tradlittlemips_vec): Likewise.
* elf32-mips.c: Include elf-vxworks.h.
(mips_info_to_howto_rel): Use elf_backend_mips_rtype_to_howto
instead of calling mips_elf32_rtype_to_howto directly.
(mips_vxworks_copy_howto_rela): New reloc howto.
(mips_vxworks_jump_slot_howto_rela): Likewise.
(mips_vxworks_bfd_reloc_type_lookup): New function.
(mips_vxworks_rtype_to_howto): Likewise.
(mips_vxworks_final_write_processing): Likewise.
(TARGET_LITTLE_SYM, TARGET_LITTLE_NAME): Override for VxWorks.
(TARGET_BIG_SYM, TARGET_BIG_NAME, elf_bed, ELF_MAXPAGESIZE): Likewise.
(elf_backend_want_got_plt): Likewise.
(elf_backend_want_plt_sym): Likewise.
(elf_backend_got_symbol_offset): Likewise.
(elf_backend_want_dynbss): Likewise.
(elf_backend_may_use_rel_p): Likewise.
(elf_backend_may_use_rela_p): Likewise.
(elf_backend_default_use_rela_p): Likewise.
(elf_backend_got_header_size: Likewise.
(elf_backend_plt_readonly): Likewise.
(bfd_elf32_bfd_reloc_type_lookup): Likewise.
(elf_backend_mips_rtype_to_howto): Likewise.
(elf_backend_adjust_dynamic_symbol): Likewise.
(elf_backend_finish_dynamic_symbol): Likewise.
(bfd_elf32_bfd_link_hash_table_create): Likewise.
(elf_backend_add_symbol_hook): Likewise.
(elf_backend_link_output_symbol_hook): Likewise.
(elf_backend_emit_relocs): Likewise.
(elf_backend_final_write_processing: Likewise.
(elf_backend_additional_program_headers): Likewise.
(elf_backend_modify_segment_map): Likewise.
(elf_backend_symbol_processing): Likewise.
* elfxx-mips.c: Include elf-vxworks.h.
(mips_elf_link_hash_entry): Add is_relocation_target and
is_branch_target fields.
(mips_elf_link_hash_table): Add is_vxworks, srelbss, sdynbss, srelplt,
srelplt2, sgotplt, splt, plt_header_size and plt_entry_size fields.
(MIPS_ELF_RELA_SIZE, MIPS_ELF_REL_DYN_NAME): New macros.
(MIPS_RESERVED_GOTNO): Take a mips_elf_link_hash_table argument.
Return 3 for VxWorks.
(ELF_MIPS_GP_OFFSET): Change the argument from a bfd to a
mips_elf_link_hash_table. Return 0 for VxWorks.
(MIPS_ELF_GOT_MAX_SIZE): Change the argument from a bfd to a
mips_elf_link_hash_table. Update the call to ELF_MIPS_GP_OFFSET.
(mips_vxworks_exec_plt0_entry): New variable.
(mips_vxworks_exec_plt_entry): Likewise.
(mips_vxworks_shared_plt0_entry): Likewise.
(mips_vxworks_shared_plt_entry): Likewise.
(mips_elf_link_hash_newfunc): Initialize the new hash_entry fields.
(mips_elf_rel_dyn_section): Change the bfd argument to a
mips_elf_link_hash_table. Use MIPS_ELF_REL_DYN_NAME to get
the name of the section.
(mips_elf_initialize_tls_slots): Update the call to
mips_elf_rel_dyn_section.
(mips_elf_gotplt_index): New function.
(mips_elf_local_got_index): Add an input_section argument.
Update the call to mips_elf_create_local_got_entry.
(mips_elf_got_page): Likewise.
(mips_elf_got16_entry): Likewise.
(mips_elf_create_local_got_entry): Add bfd_link_info and input_section
arguments. Create dynamic relocations for each entry on VxWorks.
(mips_elf_merge_gots): Update the use of MIPS_ELF_GOT_MAX_SIZE.
(mips_elf_multi_got): Update the uses of MIPS_ELF_GOT_MAX_SIZE
and MIPS_RESERVED_GOTNO.
(mips_elf_create_got_section): Update the uses of
MIPS_ELF_GOT_MAX_SIZE. Create .got.plt on VxWorks.
(is_gott_symbol): New function.
(mips_elf_calculate_relocation): Use a dynobj local variable.
Update the calls to mips_elf_local_got_index, mips_elf_got16_entry and
mips_elf_got_page_entry. Set G to the .got.plt entry when calculating
VxWorks R_MIPS_CALL* relocations. Calculate and use G for all GOT
relocations on VxWorks. Add dynamic relocations for references
to the VxWorks __GOTT_BASE__ and __GOTT_INDEX__ symbols. Don't
create dynamic relocations for R_MIPS_32, R_MIPS_REL32 or R_MIPS_64
in VxWorks executables.
(mips_elf_allocate_dynamic_relocations): Add a bfd_link_info argument.
Use MIPS_ELF_RELA_SIZE to calculate the size of a VxWorks entry.
Don't allocate a null entry on VxWorks.
(mips_elf_create_dynamic_relocation): Update the call to
mips_elf_rel_dyn_section. Use absolute rather than relative
relocations for VxWorks, and make them RELA rather than REL.
(_bfd_mips_elf_create_dynamic_sections): Don't make .dynamic
read-only on VxWorks. Update the call to mips_elf_rel_dyn_section.
Create the .plt, .rela.plt, .dynbss and .rela.bss sections on
VxWorks. Likewise create the _PROCEDURE_LINKAGE_TABLE symbol.
Call elf_vxworks_create_dynamic_sections for VxWorks and
initialize the plt_header_size and plt_entry_size fields.
(_bfd_mips_elf_check_relocs): Don't allow GOT relocations to be
used in VxWorks executables. Don't allocate dynamic relocations
for R_MIPS_32, R_MIPS_REL32 or R_MIPS_64 in VxWorks executables.
Set is_relocation_target for each symbol referenced by a relocation.
Allocate .rela.dyn entries for relocations against the special
VxWorks __GOTT_BASE__ and __GOTT_INDEX__ symbols. Create GOT
entries for all VxWorks R_MIPS_GOT16 relocations. Don't allocate
a global GOT entry for symbols mentioned in VxWorks R_MIPS_CALL*,
R_MIPS_32, R_MIPS_REL32 or R_MIPS_64 relocations. Update the calls
to mips_elf_rel_dyn_section and mips_elf_allocate_dynamic_relocations.
Set is_branch_target for symbols mentioned in R_MIPS_PC16 or R_MIPS_26
relocations. Don't set no_fn_stub on VxWorks.
(_bfd_mips_elf_adjust_dynamic_symbol): Update the call to
mips_elf_allocate_dynamic_relocations.
(_bfd_mips_vxworks_adjust_dynamic_symbol): New function.
(_bfd_mips_elf_always_size_sections): Do not allocate GOT page
entries for VxWorks, and do not create multiple GOTs.
(_bfd_mips_elf_size_dynamic_sections): Use MIPS_ELF_REL_DYN_NAME.
Handle .got specially for VxWorks. Update the uses of
MIPS_RESERVED_GOTNO and mips_elf_allocate_dynamic_relocations.
Check for sgotplt and splt. Allocate the .rel(a).dyn contents last,
once its final size is known. Set DF_TEXTREL for VxWorks. Add
DT_RELA, DT_RELASZ, DT_RELAENT, DT_PLTREL, DT_PLTRELSZ and DT_JMPREL
tags on VxWorks. Do not add the MIPS-specific tags for VxWorks.
(_bfd_mips_vxworks_finish_dynamic_symbol): New function.
(mips_vxworks_finish_exec_plt): Likewise.
(mips_vxworks_finish_shared_plt): Likewise.
(_bfd_mips_elf_finish_dynamic_sections): Remove an unncessary call
to mips_elf_rel_dyn_section. Use a VxWorks-specific value of
DT_PLTGOT. Handle DT_RELA, DT_RELASZ, DT_RELAENT, DT_PLTREL,
DT_PLTRELSZ and DT_JMPREL. Update the uses of MIPS_RESERVED_GOTNO
and mips_elf_rel_dyn_section. Use a different GOT header for
VxWorks. Don't sort .rela.dyn on VxWorks. Finish the PLT on VxWorks.
(_bfd_mips_elf_link_hash_table_create): Initialize the new
mips_elf_link_hash_table fields.
(_bfd_mips_vxworks_link_hash_table_create): New function.
(_bfd_mips_elf_final_link): Set the GP value to _GLOBAL_OFFSET_TABLE_
on VxWorks. Update the call to ELF_MIPS_GP_OFFSET.
* elfxx-mips.h (_bfd_mips_vxworks_adjust_dynamic_symbol): Declare.
(_bfd_mips_vxworks_finish_dynamic_symbol): Likewise.
(_bfd_mips_vxworks_link_hash_table_create): Likewise.
* libbfd.h: Regenerate.
* Makefile.am (elfxx-mips.lo): Depend on elf-vxworks.h.
(elf32-mips.lo): Likewise.
* Makefile.in: Regenerate.
* reloc.c (BFD_RELOC_MIPS_COPY, BFD_RELOC_MIPS_JUMP_SLOT): Declare.
* targets.c (bfd_elf32_bigmips_vxworks_vec): Declare.
(bfd_elf32_littlemips_vxworks_vec): Likewise.
(_bfd_target_vector): Add entries for them.
gas/
* config/tc-mips.c (mips_target_format): Handle vxworks targets.
(md_begin): Complain about -G being used for PIC. Don't change
the text, data and bss alignments on VxWorks.
(reloc_needs_lo_p): Don't return true for R_MIPS_GOT16 when
generating VxWorks PIC.
(load_address): Extend SVR4_PIC handling to VXWORKS_PIC.
(macro): Likewise, but do not treat la $25 specially for
VxWorks PIC, and do not handle jal.
(OPTION_MVXWORKS_PIC): New macro.
(md_longopts): Add -mvxworks-pic.
(md_parse_option): Don't complain about using PIC and -G together here.
Handle OPTION_MVXWORKS_PIC.
(md_estimate_size_before_relax): Always use the first relaxation
sequence on VxWorks.
* config/tc-mips.h (VXWORKS_PIC): New.
gas/testsuite/
* gas/mips/vxworks1.s, gas/mips/vxworks1.d,
* gas/mips/vxworks1-xgot.d: New tests.
* gas/mips/mips.exp: Run them. Do not run other tests on VxWorks.
include/elf/
* mips.h (R_MIPS_COPY, R_MIPS_JUMP_SLOT): New relocs.
ld/
* configure.tgt (mips*el-*-vxworks*, mips*-*-vxworks*): Use
separate VxWorks emulations.
* emulparams/elf32ebmipvxworks.sh: New file.
* emulparams/elf32elmipvxworks.sh: New file.
* Makefile.am (ALL_EMULATIONS): Add eelf32ebmipvxworks.o and
eelf32elmipvxworks.o.
(eelf32ebmipvxworks.c, eelf32elmipvxworks.c): New rules.
* Makefile.in: Regenerate.
ld/testsuite/
* ld-mips/vxworks1.dd, ld-mips/vxworks1.ld, ld-mips/vxworks1-lib.dd,
* ld-mips/vxworks1-lib.nd, ld-mips/vxworks1-lib.rd,
* ld-mips/vxworks1-lib.s, ld-mips/vxworks1.rd, ld-mips/vxworks1.s,
* ld-mips/vxworks1-static.d, ld-mips/vxworks2.s, ld-mips/vxworks2.sd,
* ld-mips/vxworks2-static.sd: New tests.
* ld-mips/mips-elf.exp: Run them.
2006-02-27 H.J. Lu <hongjiu.lu@intel.com>
* gas/config/tc-i386.c (output_insn): Support Intel Merom New
Instructions.
* gas/config/tc-i386.h (CpuMNI): New.
(CpuUnknownFlags): Add CpuMNI.
gas/testsuite/
2006-02-27 H.J. Lu <hongjiu.lu@intel.com>
* gas/i386/i386.exp: Add merom and x86-64-merom.
* gas/i386/merom.d: New file.
* gas/i386/merom.s: Likewise.
* gas/i386/x86-64-merom.d: Likewise.
* gas/i386/x86-64-merom.s: Likewise.
include/opcode/
2006-02-27 H.J. Lu <hongjiu.lu@intel.com>
* i386.h (i386_optab): Support Intel Merom New Instructions.
opcodes/
2006-02-27 H.J. Lu <hongjiu.lu@intel.com>
* i386-dis.c (IS_3BYTE_OPCODE): New for 3-byte opcodes used by
Intel Merom New Instructions.
(THREE_BYTE_0): Likewise.
(THREE_BYTE_1): Likewise.
(three_byte_table): Likewise.
(dis386_twobyte): Use THREE_BYTE_0 for entry 0x38. Use
THREE_BYTE_1 for entry 0x3a.
(twobyte_has_modrm): Updated.
(twobyte_uses_SSE_prefix): Likewise.
(print_insn): Handle 3-byte opcodes used by Intel Merom New
Instructions.
* xtensa-config.h (XCHAL_HAVE_WIDE_BRANCHES): New.
gas:
* config/tc-xtensa.c (op_placement_info_struct): Delete single,
single_size, widest, and widest_size fields. Add narrowest_slot.
(xg_emit_insn_to_buf): Remove fmt parameter and compute it here.
Use xg_get_single_slot to find the slot.
(finish_vinsn): Use emit_single_op instead of bundle_single_op.
(bundle_single_op): Rename this to....
(bundle_tinsn): ...this function, which builds a vliw_insn but does
not call finish_vinsn.
(emit_single_op): Use bundle_tinsn instead of bundle_single_op.
(relax_frag_immed): Get num_slots from cur_vinsn.
(convert_frag_narrow): Update call to xg_emit_insn_to_buf.
(convert_frag_immed): Likewise. Also, get num_slots from cur_vinsn.
(init_op_placement_info_table): Set narrowest_slot field. Remove
code for deleted fields.
(xg_get_single_size): Return narrowest_size field, not single_size.
(xg_get_single_format): Return narrowest field, not single.
(xg_get_single_slot): New.
(tinsn_to_insnbuf): Rewrite to use tinsn_to_slotbuf.
* config/xtensa-relax.c (widen_spec_list): Add wide branch relaxations.
(transition_applies): Check wide branch option availability.
instructions. Define MIPS16_ALL_ARGS and MIPS16_ALL_STATICS for
save/restore encoding of the args field.
* mips16-opc.c: Add MIPS16e save/restore opcodes.
* mips-dis.c (print_mips16_insn_arg): Handle printing of 'm'/'M'
codes for save/restore.
* config/tc-mips.c (mips16_ip): Add handling of 'm' and 'M' codes
for the MIPS16e save/restore instructions.
* gas/mips/mips.exp: Run new save/restore tests.
* gas/testsuite/gas/mips/mips16e-save.s: New test for generating
different styles of save/restore instructions.
* gas/testsuite/gas/mips/mips16e-save.d: New.
* readelf.c (get_mips_symbol_other): New function.
(get_symbol_other): New function.
(process_symbol_table): Call get_symbol_other() to get a description of the
st_other field if it contains more information than just the visibility.
* elfxx-mips.c (mips_elf_calculate_relocation): Ignore an undefined symbol if
it is optional.
(_bfd_mips_elf_merge_symbol_attribute): Make sure that the optional flag is
merged as well as the visibility.
* elfxx-mips.h (_bfd_mips_elf_merge_symbol_attribute): Prototype.
(elf_backend_merge_symbol_attribute): Define.
* mips.h (STO_OPTIONAL): Define.
(ELF_MIPS_IS_OPTIONAL): Define.
Contribute the following changes:
2003-09-29 Dave Brolley <brolley@redhat.com>
* dis-asm.h (disassemble_info): insn_sets now (void *) to allow for
more exotic underlying types to be used.
Contribute the following changes:
2005-02-16 Dave Brolley <brolley@redhat.com>
* cgen-bitset.h: Rename CGEN_ISA_MASK to CGEN_BITSET. Rename
cgen_isa_mask_* to cgen_bitset_*.
* cgen.h: Likewise.
2005-10-24 Jan Beulich <jbeulich@novell.com>
* ia64.h (enum ia64_opnd): Move memory operand out of set of
indirect operands.
bfd/
2005-10-24 Jan Beulich <jbeulich@novell.com>
* cpu-ia64-opc.c (elf64_ia64_operands): Move memory operand out of
set of indirect operands.
gas/
2005-10-24 Jan Beulich <jbeulich@novell.com>
* config/tc-ia64.c (enum reg_symbol): Delete IND_MEM.
(dot_rot): Change type of num_* variables. Check for positive count.
(ia64_optimize_expr): Re-structure.
(md_operand): Check for general register.
gas/testsuite/
2005-10-24 Jan Beulich <jbeulich@novell.com>
* gas/ia64/index.[sl]: New.
* gas/ia64/rotX.[sl]: New.
* gas/ia64/ia64.exp: Run new tests.
opcodes/
2005-10-24 Jan Beulich <jbeulich@novell.com>
* ia64-asmtab.c: Regenerate.
(pa_ip): Promote from PA 1.0 to 1.1 immediately when 1.1 match is
found. Simplify handling of "ma" and "mb" completers.
* hppa.h (FLAG_STRICT): Revise comment.
(pa_opcode): Revise ordering rules. Add/move strict pa10 variants
before corresponding pa11 opcodes. Add strict pa10 register-immediate
entries for "fdc".
* argv.c (safe-ctype.h): Include it.
(ISBLANK): Remove.
(stdio.h): Include.
(buildargv): Use ISSPACE instead of ISBLANK.
(expandargv): New function.
* Makefile.in: Regenerated.
OP_SH_MTACC_T, OP_MASK_MTACC_T, OP_SH_MTACC_D, OP_MASK_MTACC_D): New
define.
Document !, $, *, &, g, +t, +T operand formats for MT instructions.
(INSN_ASE_MASK): Update to include INSN_MT.
(INSN_MT): New define for MT ASE.
2005-07-27 Jan Beulich <jbeulich@novell.com>
* i386.h (i386_optab): Add comment to movd. Use LongMem for all
movd-s. Add NoRex64 to movq-s dealing only with mmx or xmm registers.
Add movq-s as 64-bit variants of movd-s.
implicit space-register addressing. Set space-register bits on opcodes
using implicit space-register addressing. Add various missing pa20
long-immediate opcodes. Remove various opcodes using implicit 3-bit
space-register addressing. Use "fE" instead of "fe" in various
fstw opcodes.
* readelf.c (read_and_display_attr_value): Handle a DW_AT_encoding
value of DW_ATE_decimal_float instead of DW_ATE_GNU_decimal_float.
include/elf/
* dwarf2.h (enum dwarf_type): Remove DW_AT_GNU_decimal_float.
Replace with DW_ATE_decimal_float (now in DWARF 3).
2005-07-14 Jim Blandy <jimb@redhat.com>
* configure.in: Add cases for Renesas m32c.
* configure: Regenerated.
bfd/ChangeLog:
2005-07-14 Jim Blandy <jimb@redhat.com>
Add support for m32c-*-elf (Renesas m32c and m16c).
* Makefile.am (ALL_MACHINES): Add cpu-m32c.lo.
(ALL_MACHINES_CFILES): Add cpu-m32c.c.
(BFD32_BACKENDS): Add elf32-m32c.lo.
(BFD32_BACKENDS_CFILES): Add elf32-m32c.c.
(cpu-m32c.lo, elf32-m32c.lo): New rules, generated by 'make dep-am'.
* Makefile.in: Regenerated.
* archures.c (bfd_arch_m32c, bfd_mach_m16c, bfd_mach_m32c): New
arch and mach codes.
(bfd_m32c_arch): New arch info object.
(bfd_archures_list): List bfd_m32c_arch.
* bfd-in2.h: Regenerated.
* config.bfd: Add case for the m32c.
* configure.in: Add case for the m32c.
* configure: Regenerated.
* cpu-m32c.c, elf32-m32c.c: New files.
* libbfd.h: Regenerated.
* targets.c (bfd_elf32_m32c_vec): Declare.
(_bfd_target_vector): List bfd_elf32_m32c_vec.
binutils/ChangeLog:
2005-07-14 Jim Blandy <jimb@redhat.com>
* readelf.c: #include "elf/m32c.h"
(guess_is_rela, dump_relocations, get_machine_name): Add cases for
EM_M32C.
* Makefile.am (readelf.o): Update dependencies.
* Makefile.in: Regenerated.
cpu/ChangeLog:
2005-07-14 Jim Blandy <jimb@redhat.com>
* m32c.cpu, m32c.opc: Machine description for the Renesas M32C.
gas/ChangeLog:
2005-07-14 Jim Blandy <jimb@redhat.com>
Add support for the Renesas M32C.
* Makefile.am (CPU_TYPES): List m32c.
(TARGET_CPU_CFILES): List config/tc-m32c.c.
(TARGET_CPU_HFILES): List config/tc-m32c.h.
* configure.in: Add case for m32c.
* configure.tgt: Add cases for m32c and m32c-*-elf.
* configure: Regenerated.
* config/tc-m32c.c, config/tc-m32c.h: New files.
* doc/Makefile.am (CPU_DOCS): Add c-m32c.texi.
* doc/Makefile.in: Regenerated.
* doc/all.texi: Set M32C.
* doc/as.texinfo: Add text for the M32C-specific options and line
comment characters, and refer to c-m32c.texi.
* doc/c-m32c.texi: New file.
include/ChangeLog:
2005-07-14 Jim Blandy <jimb@redhat.com>
* dis-asm.h (print_insn_m32c): New declaration.
include/elf/ChangeLog:
2005-07-14 Jim Blandy <jimb@redhat.com>
Add support for Renesas M32C and M16C.
* common.h (EM_M32C): New machine number.
* m32c.h: New file.
ld/ChangeLog:
2005-07-14 Jim Blandy <jimb@redhat.com>
Add support for the Renesas M32C and M16C.
* Makefile.am (ALL_EMULATIONS): Add eelf32m32c.o.
(eelf32m32c.c): New target.
* Makefile.in: Regenerated.
* configure.tgt: Add case for m32c-*-elf.
* emulparams/elf32m32c.sh: New file.
opcodes/ChangeLog:
2005-07-14 Jim Blandy <jimb@redhat.com>
Add support for the Renesas M32C and M16C.
* m32c-asm.c, m32c-desc.c, m32c-dis.c, m32c-ibld.c, m32c-opc.c: New.
* m32c-desc.h, m32c-opc.h: New.
* Makefile.am (HFILES): List m32c-desc.h and m32c-opc.h.
(CFILES): List m32c-asm.c, m32c-desc.c, m32c-dis.c, m32c-ibld.c,
m32c-opc.c.
(ALL_MACHINES): List m32c-asm.lo, m32c-desc.lo, m32c-dis.lo,
m32c-ibld.lo, m32c-opc.lo.
(CLEANFILES): List stamp-m32c.
(M32C_DEPS): List stamp-m32c, if CGEN_MAINT.
(CGEN_CPUS): Add m32c.
(m32c-asm.c, m32c-desc.c, m32c-dis.c, m32c-ibld.c, m32c-opc.c)
(m32c-desc.h, m32c-opc.h): Depend on M32C_DEPS.
(m32c_opc_h): New variable.
(stamp-m32c, m32c-asm.lo, m32c-desc.lo, m32c-dis.lo, m32c-ibld.lo)
(m32c-opc.lo): New rules.
* Makefile.in: Regenerated.
* configure.in: Add case for bfd_m32c_arch.
* configure: Regenerated.
* disassemble.c (ARCH_m32c): New.
[ARCH_m32c]: #include "m32c-desc.h".
(disassembler) [ARCH_m32c]: Add case for bfd_arch_m32c.
(disassemble_init_for_target) [ARCH_m32c]: Same.
* cgen-ops.h, cgen-types.h: New files.
* Makefile.am (HFILES): List them.
* Makefile.in: Regenerated.
2005-07-05 Jan Beulich <jbeulich@novell.com>
* config/tc-i386.h (CpuSVME): New.
(CpuUnknownFlags): Include CpuSVME.
* config/tc-i386.c (cpu_arch): Add .pacifica and .svme. Add opteron
as alias of sledgehammer.
(md_assemble): Include invlpga in the check for insns with two source
operands.
(process_operands): Include SVME insns in the check for ignored
segment overrides. Adjust diagnostic.
(i386_index_check): Special-case SVME insns with memory operands.
gas/testsuite/
2005-07-05 Jan Beulich <jbeulich@novell.com>
* gas/i386/svme.d: New.
* gas/i386/svme.s: New.
* gas/i386/svme64.d: New.
* gas/i386/i386.exp: Run new tests.
include/opcode/
2005-07-05 Jan Beulich <jbeulich@novell.com>
* i386.h (i386_optab): Add new insns.
opcodes/
2005-07-05 Jan Beulich <jbeulich@novell.com>
* i386-dis.c (SVME_Fixup): New.
(grps): Use it for the lidt entry.
(PNI_Fixup): Call OP_M rather than OP_E.
(INVLPG_Fixup): Likewise.
2005-06-20 H.J. Lu <hongjiu.lu@intel.com>
PR 1013
* config/tc-i386.c (md_assemble): Don't call optimize_disp on
movabs.
(optimize_disp): Optimize only if possible. Don't use 64bit
displacement on non-constants and do same on constants if
possible.
gas/testsuite/
2005-06-20 H.J. Lu <hongjiu.lu@intel.com>
PR 1013
* i386/x86_64.s: Add absolute 64bit addressing tests for mov.
* i386/x86_64.s: Updated.
include/opcode/
2005-06-20 H.J. Lu <hongjiu.lu@intel.com>
PR 1013
* i386.h (i386_optab): Update comments for 64bit addressing on
mov. Allow 64bit addressing for mov and movq.
* readelf.c (CHECK_ENTSIZE_VALUES, CHECK_ENTSIZE): Define.
(process_section_headers): Use it.
(process_relocs): Don't crash if symsec is not SHT_SYMTAB
or SHT_DYNSYM.
(process_version_sections): Use sizeof (Elf_External_Versym)
instead of sh_entsize.
2005-06-17 Jan Beulich <jbeulich@novell.com>
* bfd-in2.h (elf_x86_64_reloc_type): Add BFD_RELOC_X86_64_GOTOFF64
and BFD_RELOC_X86_64_GOTPC32.
* libbfd.h (bfd_reloc_code_real_names): Likewise.
* elf64-x86-64.c (x86_64_elf_howto_table): Add entries for
R_X86_64_PC64, R_X86_64_GOTOFF64, and R_X86_64_GOTPC32.
(x86_64_reloc_map): Add entries for R_X86_64_PC64, R_X86_64_GOTOFF64,
and R_X86_64_GOTPC32.
(elf64_x86_64_info_to_howto): Adjust bounding relocation type.
(elf64_x86_64_check_relocs): Also handle R_X86_64_PC64,
R_X86_64_GOTOFF64, and R_X86_64_GOTPC32.
(elf64_x86_64_relocate_section): Likewise.
(elf64_x86_64_gc_sweep_hook): Also handle R_X86_64_PC64.
gas/
2005-06-17 Jan Beulich <jbeulich@novell.com>
* config/tc-i386.c (reloc): Also handle BFD_RELOC_64_PCREL.
(tc_i386_fix_adjustable): Include BFD_RELOC_X86_64_GOTOFF64,
BFD_RELOC_X86_64_DTPOFF64, and BFD_RELOC_X86_64_TPOFF64.
(output_disp): Do GOTPC conversion also for BFD_RELOC_X86_64_32S
and BFD_RELOC_32_PCREL. Use BFD_RELOC_X86_64_GOTPC32 instead of
aborting.
(output_imm): Do GOTPC conversion also for BFD_RELOC_X86_64_32S.
Use BFD_RELOC_X86_64_GOTPC32 instead of aborting.
(tc_gen_reloc): Do GOTPC conversion also for BFD_RELOC_32_PCREL.
Use BFD_RELOC_X86_64_GOTPC32 instead of aborting. Also handle
BFD_RELOC_X86_64_GOTOFF64, BFD_RELOC_X86_64_GOTPC32,
BFD_RELOC_X86_64_DTPOFF64, and BFD_RELOC_X86_64_TPOFF64. Also
convert 8-byte pc-relative relocations.
(lex_got): Use BFD_RELOC_X86_64_GOTOFF64 for 64-bit @gotoff.
(i386_validate_fix): Likewise.
(x86_cons): Also handle quad values in 64-bit mode.
(i386_displacement): Also handle BFD_RELOC_X86_64_GOTOFF64.
(md_apply_fix): Include BFD_RELOC_X86_64_DTPOFF64 and
BFD_RELOC_X86_64_TPOFF64 in the TLS check. Also convert BFD_RELOC_64
to pc-relative variant. Also check for BFD_RELOC_64_PCREL.
gas/testsuite/
2005-06-17 Jan Beulich <jbeulich@novell.com>
* gas/i386/x86-64-pcrel.s: Add insn requiring 64-bit pc-relative
relocation. Add insns for all widths of non-pc-relative relocations.
* gas/i386/x86-64-pcrel.d: Adjust.
include/elf/
2005-06-17 Jan Beulich <jbeulich@novell.com>
* x86-64.h (elf_x86_64_reloc_type): Adjust comment for
R_X86_64_GOTPCREL. Add R_X86_64_PC64, R_X86_64_GOTOFF64, and
R_X86_64_GOTPC32.
* arm-opc.h: Delete; fold contents into ...
* arm-dis.c: ... here. Move includes of internal COFF headers
next to includes of internal ELF headers.
(streq, WORD_ADDRESS, BDISP, BDISP23): Delete, unused.
(struct arm_opcode): Rename struct opcode32. Make 'assembler' const.
(struct thumb_opcode): Rename struct opcode16. Make 'assembler' const.
(arm_conditional, arm_fp_const, arm_shift, arm_regname, regnames)
(iwmmxt_wwnames, iwmmxt_wwssnames):
Make const.
(regnames): Remove iWMMXt coprocessor register sets.
(iwmmxt_regnames, iwmmxt_cregnames): New statics.
(get_arm_regnames): Adjust fourth argument to match above changes.
(set_iwmmxt_regnames): Delete.
(print_insn_arm): Constify 'c'. Use ISO syntax for function
pointer calls. Expand sole use of BDISP. Use iwmmxt_regnames
and iwmmxt_cregnames, not set_iwmmxt_regnames.
(print_insn_thumb16, print_insn_thumb32): Constify 'c'. Use
ISO syntax for function pointer calls.
include:
* dis-asm.h (get_arm_regnames): Update prototype.
(pa_opcodes): Update load and store entries to allow both PA 1.X and
PA 2.0 mneumonics when equivalent. Entries with cache control
completers now require PA 1.1. Adjust whitespace.
* readelf.c (read_and_display_attr_value): Handle a DW_AT_encoding
value of DW_ATE_GNU_decimal_float.
include/elf/ChangeLog
* dwarf2.h (enum dwarf_type): Assign DW_ATE_GNU_decimal_float from
the user-defined encoding space pending inclusion in the standard.
* arm.h: Import complete list of official relocation names
and numbers from AAELF. Define FAKE_RELOCs for old names.
Remove a few old names no longer used anywhere.
bfd:
* elf32-arm.c: Wherever possible, use official reloc names
from AAELF.
(elf32_arm_howto_table, elf32_arm_tls_gd32_howto)
(elf32_arm_tls_ldo32_howto, elf32_arm_tls_ldm32_howto)
(elf32_arm_tls_le32_howto, elf32_arm_tls_ie32_howto)
(elf32_arm_vtinherit_howto, elf32_arm_vtentry_howto)
(elf32_arm_pc11_howto, elf32_arm_thm_pc9_howto, elf32_arm_got_prel)
(elf32_arm_r_howto): Replace with elf32_arm_howto_table_1,
elf32_arm_howto_table_2, and elf32_arm_howto_table_3.
Add many new relocations from AAELF.
(elf32_arm_howto_from_type): Update to match.
(elf32_arm_reloc_map): Add entries for R_ARM_THM_JUMP24,
R_ARM_THM_JUMP11, R_ARM_THM_JUMP19, R_ARM_THM_JUMP8,
R_ARM_THM_JUMP6, R_ARM_GNU_VTINHERIT, and R_ARM_GNU_VTENTRY.
(elf32_arm_reloc_type_lookup): Use elf32_arm_howto_from_type.
(elf32_arm_final_link_relocate): Add support for
R_ARM_THM_JUMP24, R_ARM_THM_JUMP19, R_ARM_THM_JUMP6. Remove
case entries redundant with default.
* reloc.c: Reorganize ARM relocations. Add Thumb
assembler-internal relocations BFD_RELOC_ARM_T32_OFFSET_U8,
BFD_RELOC_ARM_T32_OFFSET_IMM, BFD_RELOC_ARM_T32_IMMEDIATE.
Add visible relocations BFD_RELOC_THUMB_PCREL_BRANCH7,
BFD_RELOC_THUMB_BRANCH20, BFD_RELOC_THUMB_BRANCH25.
Delete unused relocations BFD_RELOC_ARM_GOT12, BFD_RELOC_ARM_COPY.
* bfd-in2.h, libbfd.h: Regenerate.
opcodes:
* arm-dis.c (thumb_opcodes): Add disassembly for V6T2 16-bit
instructions. Adjust disassembly of some opcodes to match
unified syntax.
(thumb32_opcodes): New table.
(print_insn_thumb): Rename print_insn_thumb16; don't handle
two-halfword branches here.
(print_insn_thumb32): New function.
(print_insn): Choose among print_insn_arm, print_insn_thumb16,
and print_insn_thumb32. Be consistent about order of
halfwords when printing 32-bit instructions.
gas:
* hash.c (hash_lookup): Add len parameter. All callers changed.
(hash_find_n): New interface.
* hash.h: Prototype hash_find_n.
* sb.c: Include as.h.
(scrub_from_sb, sb_to_scrub, scrub_position): New statics.
(sb_scrub_and_add_sb): New interface.
* sb.h: Prototype sb_scrub_and_add_sb.
* input-scrub.c (input_scrub_include_sb): Use sb_scrub_and_add_sb.
* config/tc-arm.h (TC_FORCE_RELOCATION_LOCAL): Remove
reference to BFD_RELOC_ARM_GOT12 which is never generated.
* config/tc-arm.c: Rewrite, adding Thumb-2 support.
gas/testsuite:
* gas/arm/arm.exp: Convert all existing "gas_test" tests to
"run_dump_test" tests. Run more tests unconditionally. Run new tests.
* gas/arm/arch4t.s, gas/arm/arch6zk.s, gas/arm/arm3.s, gas/arm/arm6.s
* gas/arm/arm7dm.s, gas/arm/bignum1.s, gas/arm/float.s
* gas/arm/immed.s, gas/arm/iwmmxt.s, gas/arm/offset.s, gas/arm/thumb.s:
Adjust to work as a dump test.
* gas/arm/arch4t.d, gas/arm/arch6zk.d, gas/arm/arm3.d, gas/arm/arm6.d
* gas/arm/arm7dm.d, gas/arm/bignum1.d, gas/arm/float.d
* gas/arm/immed.d, gas/arm/iwmmxt.d, gas/arm/offset.d, gas/arm/thumb.d:
New files.
* gas/arm/armv1-bad.l, gas/arm/armv1-bad.s: Remove tests for
diagnostics that don't happen in the first pass anymore.
* gas/arm/iwmmxt-bad.l, gas/arm/r15-bad.l, gas/arm/req.l
* gas/arm/vfp-bad.l:
Update expected diagnostics.
* gas/arm/pic.d: Update expected reloc name.
* gas/arm/thumbv6.d: CPY no longer appears in disassembly.
* gas/arm/r15-bad.s: Avoid two-argument mul.
* gas/arm/req.s: Adjust comments.
* gas/arm/maverick.d, gas/arm/maverick.s: Avoid inappropriate
use of PC.
* gas/arm/macro-1.d, gas/arm/macro1.s
* gas/arm/t16-bad.l, gas/arm/t16-bad.s
* gas/arm/tcompat.d, gas/arm/tcompat.s
* gas/arm/tcompat2.d, gas/arm/tcompat2.s
* gas/arm/thumb32.d, gas/arm/thumb32.s
New test pair.
ld/testsuite:
* ld-arm/mixed-app.d: Adjust expected disassembly a little.
2005-05-09 Jan Beulich <jbeulich@novell.com>
* config/tc-i386.c (parse_insn): Disallow use of prefix separator
and comma in Intel mode.
include/opcode/
2005-05-09 Jan Beulich <jbeulich@novell.com>
* i386.h (i386_optab): Add ht and hnt.
* config/tc-i386.c (md_begin): Allow hyphens in mnemonics.
include/opcode/ChangeLog:
* i386.h: Insert hyphens into selected VIA PadLock extensions.
Add xcrypt-ctr. Provide aliases without hyphens.
opcodes/ChangeLog:
* i386-dis.c: Insert hyphens into selected VIA PadLock extensions.
Add xcrypt-ctr.
* i386.h (i386_optab): Mark VIA PadLock instructions as ImmExt and
adjust them accordingly.
gas/ChangeLog:
* config/tc-i386.c (output_insn): Handle VIA PadLock instructions
similar to other instructions now that they're marked as ImmExt.
2005-03-29 H.J. Lu <hongjiu.lu@intel.com>
* gas/i386/i386.exp: Run segment and inval-seg for i386. Run
x86-64-segment and x86-64-inval-seg for x86-64.
* gas/i386/intel.d: Expect movw for moving between memory and
segment register.
* gas/i386/naked.d: Likewise.
* gas/i386/opcode.d: Likewise.
* gas/i386/x86-64-opcode.d: Likewise.
* gas/i386/opcode.s: Use movw for moving between memory and
segment register.
* gas/i386/x86-64-opcode.s: Likewise.
* : Likewise.
* gas/i386/inval-seg.l: New.
* gas/i386/inval-seg.s: New.
* gas/i386/segment.l: New.
* gas/i386/segment.s: New.
* gas/i386/x86-64-inval-seg.l: New.
* gas/i386/x86-64-inval-seg.s: New.
* gas/i386/x86-64-segment.l: New.
* gas/i386/x86-64-segment.s: New.
include/opcode/
2005-03-29 H.J. Lu <hongjiu.lu@intel.com>
* i386.h (i386_optab): Don't allow the `l' suffix for moving
moving between memory and segment register. Allow movq for
moving between general-purpose register and segment register.
opcodes/
2005-03-29 H.J. Lu <hongjiu.lu@intel.com>
* i386-dis.c (SEG_Fixup): New.
(Sv): New.
(dis386): Use "Sv" for 0x8c and 0x8e.
Richard Sandiford
Nick Clifton
Thiemo Seufer
H.J. Lu
Julian Brown
Andreas Jaeger
DJ Delorie
Nathan Sidwell
Bernd Schmidt
Dave Anglin
Paul Brook
Ben Elliston
Steve Ellcey
Arnold Metselaar
Alexandre Oliva
Andreas Schwab
Bob Wilson
Hans-Peter Nilsson
Alan Modra
Dave Brolley
Jan Beulich
Catherine Moore
Mark Mitchell
Richard Earnshaw
Chao-ying Fu
Daniel Jacobowitz
Martin Schwidefsky
Jim Blandy
Jim Wilson
Geoffrey Keating
Jakub Jelinek
Zack Weinberg
Aldy Hernandez
Richard Henderson
Mark Kettenis
Ian Lance Taylor