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binutils-gdb/gas/testsuite/gas/riscv
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Jim Wilson 25982ee022 Add missing RISC-V fsrmi and fsflagsi instructions. 
PR 22599
	gas/
	* testsuite/gas/riscv/fsxxi.d, testsuite/gas/riscv/fsxxi.s: New.
	opcodes/
	* riscv-opc.c (riscv_opcodes) <fsrmi, fsflagsi>: New.
 		2017-12-13 14:59:42 -08:00
..
align-1.l Fix riscv malloc error on small alignment after norvc. 2017-11-29 10:36:46 -08:00
align-1.s Fix riscv malloc error on small alignment after norvc. 2017-11-29 10:36:46 -08:00
c-addi4spn-fail.d RISC-V: Fix disassembly of c.addi4spn, c.addi16sp, c.lui when imm=0 2017-10-24 09:47:36 -07:00
c-addi4spn-fail.l RISC-V: Fix disassembly of c.addi4spn, c.addi16sp, c.lui when imm=0 2017-10-24 09:47:36 -07:00
c-addi4spn-fail.s RISC-V: Fix disassembly of c.addi4spn, c.addi16sp, c.lui when imm=0 2017-10-24 09:47:36 -07:00
c-addi16sp-fail.d RISC-V: Fix disassembly of c.addi4spn, c.addi16sp, c.lui when imm=0 2017-10-24 09:47:36 -07:00
c-addi16sp-fail.l RISC-V: Fix disassembly of c.addi4spn, c.addi16sp, c.lui when imm=0 2017-10-24 09:47:36 -07:00
c-addi16sp-fail.s RISC-V: Fix disassembly of c.addi4spn, c.addi16sp, c.lui when imm=0 2017-10-24 09:47:36 -07:00
c-ld.d Compress loads/stores with implicit 0 offset. 2017-11-27 19:20:53 -08:00
c-ld.s Compress loads/stores with implicit 0 offset. 2017-11-27 19:20:53 -08:00
c-lui-fail.d RISC-V: Only relax to C.LUI when imm != 0 and rd != 0/2 2017-10-24 08:02:46 -07:00
c-lui-fail.l RISC-V: Only relax to C.LUI when imm != 0 and rd != 0/2 2017-10-24 08:02:46 -07:00
c-lui-fail.s RISC-V: Only relax to C.LUI when imm != 0 and rd != 0/2 2017-10-24 08:02:46 -07:00
c-lw.d Compress loads/stores with implicit 0 offset. 2017-11-27 19:20:53 -08:00
c-lw.s Compress loads/stores with implicit 0 offset. 2017-11-27 19:20:53 -08:00
eh-relocs.d RISC-V: Fix riscv g++ testsuite EH failures. 2017-11-07 09:13:52 -08:00
eh-relocs.s RISC-V: Fix riscv g++ testsuite EH failures. 2017-11-07 09:13:52 -08:00
fmv.x.d Add support for the new names of the RISC-V fmv.x.s and fmv.s.x instructions, vis: fmv.x.w and fmv.w.x. 2017-09-27 16:21:36 +01:00
fmv.x.s Add support for the new names of the RISC-V fmv.x.s and fmv.s.x instructions, vis: fmv.x.w and fmv.w.x. 2017-09-27 16:21:36 +01:00
fsxxi.d Add missing RISC-V fsrmi and fsflagsi instructions. 2017-12-13 14:59:42 -08:00
fsxxi.s Add missing RISC-V fsrmi and fsflagsi instructions. 2017-12-13 14:59:42 -08:00
riscv.exp Fix riscv malloc error on small alignment after norvc. 2017-11-29 10:36:46 -08:00
satp.d RISC-V: Add satp as an alias for sptbr 2017-11-07 09:00:37 -08:00
satp.s RISC-V: Add satp as an alias for sptbr 2017-11-07 09:00:37 -08:00
t_insns.d Add support for RISC-V architecture. 2016-11-01 16:45:57 +00:00
t_insns.s Add support for RISC-V architecture. 2016-11-01 16:45:57 +00:00