2007-11-11 01:04:49 +01:00
|
|
|
/*
|
2008-04-11 06:55:07 +02:00
|
|
|
* Luminary Micro Stellaris peripherals
|
2007-11-11 01:04:49 +01:00
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|
|
*
|
|
|
|
* Copyright (c) 2006 CodeSourcery.
|
|
|
|
* Written by Paul Brook
|
|
|
|
*
|
2011-06-26 04:21:35 +02:00
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|
|
* This code is licensed under the GPL.
|
2007-11-11 01:04:49 +01:00
|
|
|
*/
|
|
|
|
|
2015-12-07 17:23:45 +01:00
|
|
|
#include "qemu/osdep.h"
|
include/qemu/osdep.h: Don't include qapi/error.h
Commit 57cb38b included qapi/error.h into qemu/osdep.h to get the
Error typedef. Since then, we've moved to include qemu/osdep.h
everywhere. Its file comment explains: "To avoid getting into
possible circular include dependencies, this file should not include
any other QEMU headers, with the exceptions of config-host.h,
compiler.h, os-posix.h and os-win32.h, all of which are doing a
similar job to this file and are under similar constraints."
qapi/error.h doesn't do a similar job, and it doesn't adhere to
similar constraints: it includes qapi-types.h. That's in excess of
100KiB of crap most .c files don't actually need.
Add the typedef to qemu/typedefs.h, and include that instead of
qapi/error.h. Include qapi/error.h in .c files that need it and don't
get it now. Include qapi-types.h in qom/object.h for uint16List.
Update scripts/clean-includes accordingly. Update it further to match
reality: replace config.h by config-target.h, add sysemu/os-posix.h,
sysemu/os-win32.h. Update the list of includes in the qemu/osdep.h
comment quoted above similarly.
This reduces the number of objects depending on qapi/error.h from "all
of them" to less than a third. Unfortunately, the number depending on
qapi-types.h shrinks only a little. More work is needed for that one.
Signed-off-by: Markus Armbruster <armbru@redhat.com>
[Fix compilation without the spice devel packages. - Paolo]
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2016-03-14 09:01:28 +01:00
|
|
|
#include "qapi/error.h"
|
2013-02-04 15:40:22 +01:00
|
|
|
#include "hw/sysbus.h"
|
2021-11-17 17:33:57 +01:00
|
|
|
#include "hw/sd/sd.h"
|
2016-01-21 15:15:03 +01:00
|
|
|
#include "hw/ssi/ssi.h"
|
2019-05-23 15:47:43 +02:00
|
|
|
#include "hw/arm/boot.h"
|
2012-12-17 18:20:00 +01:00
|
|
|
#include "qemu/timer.h"
|
2013-02-05 17:06:20 +01:00
|
|
|
#include "hw/i2c/i2c.h"
|
2012-10-24 08:43:34 +02:00
|
|
|
#include "net/net.h"
|
2013-02-04 15:40:22 +01:00
|
|
|
#include "hw/boards.h"
|
2015-12-15 13:16:16 +01:00
|
|
|
#include "qemu/log.h"
|
2012-12-17 18:19:49 +01:00
|
|
|
#include "exec/address-spaces.h"
|
2015-11-03 14:49:41 +01:00
|
|
|
#include "sysemu/sysemu.h"
|
2018-06-15 15:57:13 +02:00
|
|
|
#include "hw/arm/armv7m.h"
|
2016-06-06 17:59:31 +02:00
|
|
|
#include "hw/char/pl011.h"
|
2019-04-12 18:54:11 +02:00
|
|
|
#include "hw/input/gamepad.h"
|
2019-08-12 07:23:42 +02:00
|
|
|
#include "hw/irq.h"
|
2019-03-05 00:16:22 +01:00
|
|
|
#include "hw/watchdog/cmsdk-apb-watchdog.h"
|
2019-08-12 07:23:45 +02:00
|
|
|
#include "migration/vmstate.h"
|
2017-02-07 19:30:00 +01:00
|
|
|
#include "hw/misc/unimp.h"
|
2021-08-12 11:33:54 +02:00
|
|
|
#include "hw/timer/stellaris-gptm.h"
|
2021-01-28 12:41:37 +01:00
|
|
|
#include "hw/qdev-clock.h"
|
2020-09-03 22:43:22 +02:00
|
|
|
#include "qom/object.h"
|
2007-11-11 01:04:49 +01:00
|
|
|
|
2007-11-18 15:36:08 +01:00
|
|
|
#define GPIO_A 0
|
|
|
|
#define GPIO_B 1
|
|
|
|
#define GPIO_C 2
|
|
|
|
#define GPIO_D 3
|
|
|
|
#define GPIO_E 4
|
|
|
|
#define GPIO_F 5
|
|
|
|
#define GPIO_G 6
|
|
|
|
|
|
|
|
#define BP_OLED_I2C 0x01
|
|
|
|
#define BP_OLED_SSI 0x02
|
|
|
|
#define BP_GAMEPAD 0x04
|
|
|
|
|
2015-02-05 14:37:21 +01:00
|
|
|
#define NUM_IRQ_LINES 64
|
|
|
|
|
2007-11-11 01:04:49 +01:00
|
|
|
typedef const struct {
|
|
|
|
const char *name;
|
|
|
|
uint32_t did0;
|
|
|
|
uint32_t did1;
|
|
|
|
uint32_t dc0;
|
|
|
|
uint32_t dc1;
|
|
|
|
uint32_t dc2;
|
|
|
|
uint32_t dc3;
|
|
|
|
uint32_t dc4;
|
2007-11-18 15:36:08 +01:00
|
|
|
uint32_t peripherals;
|
2007-11-11 01:04:49 +01:00
|
|
|
} stellaris_board_info;
|
|
|
|
|
|
|
|
/* System controller. */
|
|
|
|
|
2021-01-28 12:41:36 +01:00
|
|
|
#define TYPE_STELLARIS_SYS "stellaris-sys"
|
|
|
|
OBJECT_DECLARE_SIMPLE_TYPE(ssys_state, STELLARIS_SYS)
|
|
|
|
|
|
|
|
struct ssys_state {
|
|
|
|
SysBusDevice parent_obj;
|
|
|
|
|
2011-10-17 17:28:29 +02:00
|
|
|
MemoryRegion iomem;
|
2007-11-11 01:04:49 +01:00
|
|
|
uint32_t pborctl;
|
|
|
|
uint32_t ldopctl;
|
|
|
|
uint32_t int_status;
|
|
|
|
uint32_t int_mask;
|
|
|
|
uint32_t resc;
|
|
|
|
uint32_t rcc;
|
2011-08-03 23:15:23 +02:00
|
|
|
uint32_t rcc2;
|
2007-11-11 01:04:49 +01:00
|
|
|
uint32_t rcgc[3];
|
|
|
|
uint32_t scgc[3];
|
|
|
|
uint32_t dcgc[3];
|
|
|
|
uint32_t clkvclr;
|
|
|
|
uint32_t ldoarst;
|
2021-01-28 12:41:36 +01:00
|
|
|
qemu_irq irq;
|
2021-01-28 12:41:37 +01:00
|
|
|
Clock *sysclk;
|
2021-01-28 12:41:36 +01:00
|
|
|
/* Properties (all read-only registers) */
|
2007-11-24 04:13:04 +01:00
|
|
|
uint32_t user0;
|
|
|
|
uint32_t user1;
|
2021-01-28 12:41:36 +01:00
|
|
|
uint32_t did0;
|
|
|
|
uint32_t did1;
|
|
|
|
uint32_t dc0;
|
|
|
|
uint32_t dc1;
|
|
|
|
uint32_t dc2;
|
|
|
|
uint32_t dc3;
|
|
|
|
uint32_t dc4;
|
|
|
|
};
|
2007-11-11 01:04:49 +01:00
|
|
|
|
|
|
|
static void ssys_update(ssys_state *s)
|
|
|
|
{
|
|
|
|
qemu_set_irq(s->irq, (s->int_status & s->int_mask) != 0);
|
|
|
|
}
|
|
|
|
|
|
|
|
static uint32_t pllcfg_sandstorm[16] = {
|
|
|
|
0x31c0, /* 1 Mhz */
|
|
|
|
0x1ae0, /* 1.8432 Mhz */
|
|
|
|
0x18c0, /* 2 Mhz */
|
|
|
|
0xd573, /* 2.4576 Mhz */
|
|
|
|
0x37a6, /* 3.57954 Mhz */
|
|
|
|
0x1ae2, /* 3.6864 Mhz */
|
|
|
|
0x0c40, /* 4 Mhz */
|
|
|
|
0x98bc, /* 4.906 Mhz */
|
|
|
|
0x935b, /* 4.9152 Mhz */
|
|
|
|
0x09c0, /* 5 Mhz */
|
|
|
|
0x4dee, /* 5.12 Mhz */
|
|
|
|
0x0c41, /* 6 Mhz */
|
|
|
|
0x75db, /* 6.144 Mhz */
|
|
|
|
0x1ae6, /* 7.3728 Mhz */
|
|
|
|
0x0600, /* 8 Mhz */
|
|
|
|
0x585b /* 8.192 Mhz */
|
|
|
|
};
|
|
|
|
|
|
|
|
static uint32_t pllcfg_fury[16] = {
|
|
|
|
0x3200, /* 1 Mhz */
|
|
|
|
0x1b20, /* 1.8432 Mhz */
|
|
|
|
0x1900, /* 2 Mhz */
|
|
|
|
0xf42b, /* 2.4576 Mhz */
|
|
|
|
0x37e3, /* 3.57954 Mhz */
|
|
|
|
0x1b21, /* 3.6864 Mhz */
|
|
|
|
0x0c80, /* 4 Mhz */
|
|
|
|
0x98ee, /* 4.906 Mhz */
|
|
|
|
0xd5b4, /* 4.9152 Mhz */
|
|
|
|
0x0a00, /* 5 Mhz */
|
|
|
|
0x4e27, /* 5.12 Mhz */
|
|
|
|
0x1902, /* 6 Mhz */
|
|
|
|
0xec1c, /* 6.144 Mhz */
|
|
|
|
0x1b23, /* 7.3728 Mhz */
|
|
|
|
0x0640, /* 8 Mhz */
|
|
|
|
0xb11c /* 8.192 Mhz */
|
|
|
|
};
|
|
|
|
|
2011-08-03 23:15:23 +02:00
|
|
|
#define DID0_VER_MASK 0x70000000
|
|
|
|
#define DID0_VER_0 0x00000000
|
|
|
|
#define DID0_VER_1 0x10000000
|
|
|
|
|
|
|
|
#define DID0_CLASS_MASK 0x00FF0000
|
|
|
|
#define DID0_CLASS_SANDSTORM 0x00000000
|
|
|
|
#define DID0_CLASS_FURY 0x00010000
|
|
|
|
|
|
|
|
static int ssys_board_class(const ssys_state *s)
|
|
|
|
{
|
2021-01-28 12:41:36 +01:00
|
|
|
uint32_t did0 = s->did0;
|
2011-08-03 23:15:23 +02:00
|
|
|
switch (did0 & DID0_VER_MASK) {
|
|
|
|
case DID0_VER_0:
|
|
|
|
return DID0_CLASS_SANDSTORM;
|
|
|
|
case DID0_VER_1:
|
|
|
|
switch (did0 & DID0_CLASS_MASK) {
|
|
|
|
case DID0_CLASS_SANDSTORM:
|
|
|
|
case DID0_CLASS_FURY:
|
|
|
|
return did0 & DID0_CLASS_MASK;
|
|
|
|
}
|
|
|
|
/* for unknown classes, fall through */
|
|
|
|
default:
|
2017-04-20 18:32:29 +02:00
|
|
|
/* This can only happen if the hardwired constant did0 value
|
|
|
|
* in this board's stellaris_board_info struct is wrong.
|
|
|
|
*/
|
|
|
|
g_assert_not_reached();
|
2011-08-03 23:15:23 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2012-10-23 12:30:10 +02:00
|
|
|
static uint64_t ssys_read(void *opaque, hwaddr offset,
|
2011-10-17 17:28:29 +02:00
|
|
|
unsigned size)
|
2007-11-11 01:04:49 +01:00
|
|
|
{
|
|
|
|
ssys_state *s = (ssys_state *)opaque;
|
|
|
|
|
|
|
|
switch (offset) {
|
|
|
|
case 0x000: /* DID0 */
|
2021-01-28 12:41:36 +01:00
|
|
|
return s->did0;
|
2007-11-11 01:04:49 +01:00
|
|
|
case 0x004: /* DID1 */
|
2021-01-28 12:41:36 +01:00
|
|
|
return s->did1;
|
2007-11-11 01:04:49 +01:00
|
|
|
case 0x008: /* DC0 */
|
2021-01-28 12:41:36 +01:00
|
|
|
return s->dc0;
|
2007-11-11 01:04:49 +01:00
|
|
|
case 0x010: /* DC1 */
|
2021-01-28 12:41:36 +01:00
|
|
|
return s->dc1;
|
2007-11-11 01:04:49 +01:00
|
|
|
case 0x014: /* DC2 */
|
2021-01-28 12:41:36 +01:00
|
|
|
return s->dc2;
|
2007-11-11 01:04:49 +01:00
|
|
|
case 0x018: /* DC3 */
|
2021-01-28 12:41:36 +01:00
|
|
|
return s->dc3;
|
2007-11-11 01:04:49 +01:00
|
|
|
case 0x01c: /* DC4 */
|
2021-01-28 12:41:36 +01:00
|
|
|
return s->dc4;
|
2007-11-11 01:04:49 +01:00
|
|
|
case 0x030: /* PBORCTL */
|
|
|
|
return s->pborctl;
|
|
|
|
case 0x034: /* LDOPCTL */
|
|
|
|
return s->ldopctl;
|
|
|
|
case 0x040: /* SRCR0 */
|
|
|
|
return 0;
|
|
|
|
case 0x044: /* SRCR1 */
|
|
|
|
return 0;
|
|
|
|
case 0x048: /* SRCR2 */
|
|
|
|
return 0;
|
|
|
|
case 0x050: /* RIS */
|
|
|
|
return s->int_status;
|
|
|
|
case 0x054: /* IMC */
|
|
|
|
return s->int_mask;
|
|
|
|
case 0x058: /* MISC */
|
|
|
|
return s->int_status & s->int_mask;
|
|
|
|
case 0x05c: /* RESC */
|
|
|
|
return s->resc;
|
|
|
|
case 0x060: /* RCC */
|
|
|
|
return s->rcc;
|
|
|
|
case 0x064: /* PLLCFG */
|
|
|
|
{
|
|
|
|
int xtal;
|
|
|
|
xtal = (s->rcc >> 6) & 0xf;
|
2011-08-03 23:15:23 +02:00
|
|
|
switch (ssys_board_class(s)) {
|
|
|
|
case DID0_CLASS_FURY:
|
2007-11-11 01:04:49 +01:00
|
|
|
return pllcfg_fury[xtal];
|
2011-08-03 23:15:23 +02:00
|
|
|
case DID0_CLASS_SANDSTORM:
|
2007-11-11 01:04:49 +01:00
|
|
|
return pllcfg_sandstorm[xtal];
|
2011-08-03 23:15:23 +02:00
|
|
|
default:
|
2017-04-20 18:32:29 +02:00
|
|
|
g_assert_not_reached();
|
2007-11-11 01:04:49 +01:00
|
|
|
}
|
|
|
|
}
|
2011-08-03 23:15:23 +02:00
|
|
|
case 0x070: /* RCC2 */
|
|
|
|
return s->rcc2;
|
2007-11-11 01:04:49 +01:00
|
|
|
case 0x100: /* RCGC0 */
|
|
|
|
return s->rcgc[0];
|
|
|
|
case 0x104: /* RCGC1 */
|
|
|
|
return s->rcgc[1];
|
|
|
|
case 0x108: /* RCGC2 */
|
|
|
|
return s->rcgc[2];
|
|
|
|
case 0x110: /* SCGC0 */
|
|
|
|
return s->scgc[0];
|
|
|
|
case 0x114: /* SCGC1 */
|
|
|
|
return s->scgc[1];
|
|
|
|
case 0x118: /* SCGC2 */
|
|
|
|
return s->scgc[2];
|
|
|
|
case 0x120: /* DCGC0 */
|
|
|
|
return s->dcgc[0];
|
|
|
|
case 0x124: /* DCGC1 */
|
|
|
|
return s->dcgc[1];
|
|
|
|
case 0x128: /* DCGC2 */
|
|
|
|
return s->dcgc[2];
|
|
|
|
case 0x150: /* CLKVCLR */
|
|
|
|
return s->clkvclr;
|
|
|
|
case 0x160: /* LDOARST */
|
|
|
|
return s->ldoarst;
|
2007-11-24 04:13:04 +01:00
|
|
|
case 0x1e0: /* USER0 */
|
|
|
|
return s->user0;
|
|
|
|
case 0x1e4: /* USER1 */
|
|
|
|
return s->user1;
|
2007-11-11 01:04:49 +01:00
|
|
|
default:
|
2017-04-20 18:32:29 +02:00
|
|
|
qemu_log_mask(LOG_GUEST_ERROR,
|
|
|
|
"SSYS: read at bad offset 0x%x\n", (int)offset);
|
2007-11-11 01:04:49 +01:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2011-08-03 23:15:23 +02:00
|
|
|
static bool ssys_use_rcc2(ssys_state *s)
|
|
|
|
{
|
|
|
|
return (s->rcc2 >> 31) & 0x1;
|
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
2021-01-28 12:41:37 +01:00
|
|
|
* Calculate the system clock period. We only want to propagate
|
|
|
|
* this change to the rest of the system if we're not being called
|
|
|
|
* from migration post-load.
|
2011-08-03 23:15:23 +02:00
|
|
|
*/
|
2021-01-28 12:41:37 +01:00
|
|
|
static void ssys_calculate_system_clock(ssys_state *s, bool propagate_clock)
|
2008-07-02 18:48:32 +02:00
|
|
|
{
|
2021-08-12 11:33:56 +02:00
|
|
|
int period_ns;
|
2021-01-28 12:41:37 +01:00
|
|
|
/*
|
|
|
|
* SYSDIV field specifies divisor: 0 == /1, 1 == /2, etc. Input
|
|
|
|
* clock is 200MHz, which is a period of 5 ns. Dividing the clock
|
|
|
|
* frequency by X is the same as multiplying the period by X.
|
|
|
|
*/
|
2011-08-03 23:15:23 +02:00
|
|
|
if (ssys_use_rcc2(s)) {
|
2021-08-12 11:33:56 +02:00
|
|
|
period_ns = 5 * (((s->rcc2 >> 23) & 0x3f) + 1);
|
2011-08-03 23:15:23 +02:00
|
|
|
} else {
|
2021-08-12 11:33:56 +02:00
|
|
|
period_ns = 5 * (((s->rcc >> 23) & 0xf) + 1);
|
2011-08-03 23:15:23 +02:00
|
|
|
}
|
2021-08-12 11:33:56 +02:00
|
|
|
clock_set_ns(s->sysclk, period_ns);
|
2021-01-28 12:41:37 +01:00
|
|
|
if (propagate_clock) {
|
|
|
|
clock_propagate(s->sysclk);
|
|
|
|
}
|
2008-07-02 18:48:32 +02:00
|
|
|
}
|
|
|
|
|
2012-10-23 12:30:10 +02:00
|
|
|
static void ssys_write(void *opaque, hwaddr offset,
|
2011-10-17 17:28:29 +02:00
|
|
|
uint64_t value, unsigned size)
|
2007-11-11 01:04:49 +01:00
|
|
|
{
|
|
|
|
ssys_state *s = (ssys_state *)opaque;
|
|
|
|
|
|
|
|
switch (offset) {
|
|
|
|
case 0x030: /* PBORCTL */
|
|
|
|
s->pborctl = value & 0xffff;
|
|
|
|
break;
|
|
|
|
case 0x034: /* LDOPCTL */
|
|
|
|
s->ldopctl = value & 0x1f;
|
|
|
|
break;
|
|
|
|
case 0x040: /* SRCR0 */
|
|
|
|
case 0x044: /* SRCR1 */
|
|
|
|
case 0x048: /* SRCR2 */
|
2018-06-26 18:50:41 +02:00
|
|
|
qemu_log_mask(LOG_UNIMP, "Peripheral reset not implemented\n");
|
2007-11-11 01:04:49 +01:00
|
|
|
break;
|
|
|
|
case 0x054: /* IMC */
|
|
|
|
s->int_mask = value & 0x7f;
|
|
|
|
break;
|
|
|
|
case 0x058: /* MISC */
|
|
|
|
s->int_status &= ~value;
|
|
|
|
break;
|
|
|
|
case 0x05c: /* RESC */
|
|
|
|
s->resc = value & 0x3f;
|
|
|
|
break;
|
|
|
|
case 0x060: /* RCC */
|
|
|
|
if ((s->rcc & (1 << 13)) != 0 && (value & (1 << 13)) == 0) {
|
|
|
|
/* PLL enable. */
|
|
|
|
s->int_status |= (1 << 6);
|
|
|
|
}
|
|
|
|
s->rcc = value;
|
2021-01-28 12:41:37 +01:00
|
|
|
ssys_calculate_system_clock(s, true);
|
2007-11-11 01:04:49 +01:00
|
|
|
break;
|
2011-08-03 23:15:23 +02:00
|
|
|
case 0x070: /* RCC2 */
|
|
|
|
if (ssys_board_class(s) == DID0_CLASS_SANDSTORM) {
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
|
|
|
if ((s->rcc2 & (1 << 13)) != 0 && (value & (1 << 13)) == 0) {
|
|
|
|
/* PLL enable. */
|
|
|
|
s->int_status |= (1 << 6);
|
|
|
|
}
|
|
|
|
s->rcc2 = value;
|
2021-01-28 12:41:37 +01:00
|
|
|
ssys_calculate_system_clock(s, true);
|
2011-08-03 23:15:23 +02:00
|
|
|
break;
|
2007-11-11 01:04:49 +01:00
|
|
|
case 0x100: /* RCGC0 */
|
|
|
|
s->rcgc[0] = value;
|
|
|
|
break;
|
|
|
|
case 0x104: /* RCGC1 */
|
|
|
|
s->rcgc[1] = value;
|
|
|
|
break;
|
|
|
|
case 0x108: /* RCGC2 */
|
|
|
|
s->rcgc[2] = value;
|
|
|
|
break;
|
|
|
|
case 0x110: /* SCGC0 */
|
|
|
|
s->scgc[0] = value;
|
|
|
|
break;
|
|
|
|
case 0x114: /* SCGC1 */
|
|
|
|
s->scgc[1] = value;
|
|
|
|
break;
|
|
|
|
case 0x118: /* SCGC2 */
|
|
|
|
s->scgc[2] = value;
|
|
|
|
break;
|
|
|
|
case 0x120: /* DCGC0 */
|
|
|
|
s->dcgc[0] = value;
|
|
|
|
break;
|
|
|
|
case 0x124: /* DCGC1 */
|
|
|
|
s->dcgc[1] = value;
|
|
|
|
break;
|
|
|
|
case 0x128: /* DCGC2 */
|
|
|
|
s->dcgc[2] = value;
|
|
|
|
break;
|
|
|
|
case 0x150: /* CLKVCLR */
|
|
|
|
s->clkvclr = value;
|
|
|
|
break;
|
|
|
|
case 0x160: /* LDOARST */
|
|
|
|
s->ldoarst = value;
|
|
|
|
break;
|
|
|
|
default:
|
2017-04-20 18:32:29 +02:00
|
|
|
qemu_log_mask(LOG_GUEST_ERROR,
|
|
|
|
"SSYS: write at bad offset 0x%x\n", (int)offset);
|
2007-11-11 01:04:49 +01:00
|
|
|
}
|
|
|
|
ssys_update(s);
|
|
|
|
}
|
|
|
|
|
2011-10-17 17:28:29 +02:00
|
|
|
static const MemoryRegionOps ssys_ops = {
|
|
|
|
.read = ssys_read,
|
|
|
|
.write = ssys_write,
|
|
|
|
.endianness = DEVICE_NATIVE_ENDIAN,
|
2007-11-11 01:04:49 +01:00
|
|
|
};
|
|
|
|
|
2021-01-28 12:41:36 +01:00
|
|
|
static void stellaris_sys_reset_enter(Object *obj, ResetType type)
|
2007-11-11 01:04:49 +01:00
|
|
|
{
|
2021-01-28 12:41:36 +01:00
|
|
|
ssys_state *s = STELLARIS_SYS(obj);
|
2007-11-11 01:04:49 +01:00
|
|
|
|
|
|
|
s->pborctl = 0x7ffd;
|
|
|
|
s->rcc = 0x078e3ac0;
|
2011-08-03 23:15:23 +02:00
|
|
|
|
|
|
|
if (ssys_board_class(s) == DID0_CLASS_SANDSTORM) {
|
|
|
|
s->rcc2 = 0;
|
|
|
|
} else {
|
|
|
|
s->rcc2 = 0x07802810;
|
|
|
|
}
|
2007-11-11 01:04:49 +01:00
|
|
|
s->rcgc[0] = 1;
|
|
|
|
s->scgc[0] = 1;
|
|
|
|
s->dcgc[0] = 1;
|
2021-01-28 12:41:36 +01:00
|
|
|
}
|
|
|
|
|
|
|
|
static void stellaris_sys_reset_hold(Object *obj)
|
|
|
|
{
|
|
|
|
ssys_state *s = STELLARIS_SYS(obj);
|
|
|
|
|
2021-01-28 12:41:37 +01:00
|
|
|
/* OK to propagate clocks from the hold phase */
|
|
|
|
ssys_calculate_system_clock(s, true);
|
2007-11-11 01:04:49 +01:00
|
|
|
}
|
|
|
|
|
2021-01-28 12:41:36 +01:00
|
|
|
static void stellaris_sys_reset_exit(Object *obj)
|
|
|
|
{
|
|
|
|
}
|
|
|
|
|
2010-12-02 03:03:11 +01:00
|
|
|
static int stellaris_sys_post_load(void *opaque, int version_id)
|
2008-07-02 18:48:32 +02:00
|
|
|
{
|
2010-12-02 03:03:11 +01:00
|
|
|
ssys_state *s = opaque;
|
2008-07-02 18:48:32 +02:00
|
|
|
|
2021-01-28 12:41:37 +01:00
|
|
|
ssys_calculate_system_clock(s, false);
|
2008-07-02 18:48:32 +02:00
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2010-12-02 03:03:11 +01:00
|
|
|
static const VMStateDescription vmstate_stellaris_sys = {
|
|
|
|
.name = "stellaris_sys",
|
2011-08-03 23:15:23 +02:00
|
|
|
.version_id = 2,
|
2010-12-02 03:03:11 +01:00
|
|
|
.minimum_version_id = 1,
|
|
|
|
.post_load = stellaris_sys_post_load,
|
2014-05-13 17:09:35 +02:00
|
|
|
.fields = (VMStateField[]) {
|
2010-12-02 03:03:11 +01:00
|
|
|
VMSTATE_UINT32(pborctl, ssys_state),
|
|
|
|
VMSTATE_UINT32(ldopctl, ssys_state),
|
|
|
|
VMSTATE_UINT32(int_mask, ssys_state),
|
|
|
|
VMSTATE_UINT32(int_status, ssys_state),
|
|
|
|
VMSTATE_UINT32(resc, ssys_state),
|
|
|
|
VMSTATE_UINT32(rcc, ssys_state),
|
2011-08-03 23:15:23 +02:00
|
|
|
VMSTATE_UINT32_V(rcc2, ssys_state, 2),
|
2010-12-02 03:03:11 +01:00
|
|
|
VMSTATE_UINT32_ARRAY(rcgc, ssys_state, 3),
|
|
|
|
VMSTATE_UINT32_ARRAY(scgc, ssys_state, 3),
|
|
|
|
VMSTATE_UINT32_ARRAY(dcgc, ssys_state, 3),
|
|
|
|
VMSTATE_UINT32(clkvclr, ssys_state),
|
|
|
|
VMSTATE_UINT32(ldoarst, ssys_state),
|
2021-01-28 12:41:37 +01:00
|
|
|
/* No field for sysclk -- handled in post-load instead */
|
2010-12-02 03:03:11 +01:00
|
|
|
VMSTATE_END_OF_LIST()
|
|
|
|
}
|
|
|
|
};
|
|
|
|
|
2021-01-28 12:41:36 +01:00
|
|
|
static Property stellaris_sys_properties[] = {
|
|
|
|
DEFINE_PROP_UINT32("user0", ssys_state, user0, 0),
|
|
|
|
DEFINE_PROP_UINT32("user1", ssys_state, user1, 0),
|
|
|
|
DEFINE_PROP_UINT32("did0", ssys_state, did0, 0),
|
|
|
|
DEFINE_PROP_UINT32("did1", ssys_state, did1, 0),
|
|
|
|
DEFINE_PROP_UINT32("dc0", ssys_state, dc0, 0),
|
|
|
|
DEFINE_PROP_UINT32("dc1", ssys_state, dc1, 0),
|
|
|
|
DEFINE_PROP_UINT32("dc2", ssys_state, dc2, 0),
|
|
|
|
DEFINE_PROP_UINT32("dc3", ssys_state, dc3, 0),
|
|
|
|
DEFINE_PROP_UINT32("dc4", ssys_state, dc4, 0),
|
|
|
|
DEFINE_PROP_END_OF_LIST()
|
|
|
|
};
|
|
|
|
|
|
|
|
static void stellaris_sys_instance_init(Object *obj)
|
|
|
|
{
|
|
|
|
ssys_state *s = STELLARIS_SYS(obj);
|
|
|
|
SysBusDevice *sbd = SYS_BUS_DEVICE(s);
|
|
|
|
|
|
|
|
memory_region_init_io(&s->iomem, obj, &ssys_ops, s, "ssys", 0x00001000);
|
|
|
|
sysbus_init_mmio(sbd, &s->iomem);
|
|
|
|
sysbus_init_irq(sbd, &s->irq);
|
2021-01-28 12:41:37 +01:00
|
|
|
s->sysclk = qdev_init_clock_out(DEVICE(s), "SYSCLK");
|
2021-01-28 12:41:36 +01:00
|
|
|
}
|
|
|
|
|
2007-11-11 01:04:49 +01:00
|
|
|
/* I2C controller. */
|
|
|
|
|
2013-07-24 09:08:23 +02:00
|
|
|
#define TYPE_STELLARIS_I2C "stellaris-i2c"
|
2020-09-16 20:25:19 +02:00
|
|
|
OBJECT_DECLARE_SIMPLE_TYPE(stellaris_i2c_state, STELLARIS_I2C)
|
2013-07-24 09:08:23 +02:00
|
|
|
|
2020-09-03 22:43:22 +02:00
|
|
|
struct stellaris_i2c_state {
|
2013-07-24 09:08:23 +02:00
|
|
|
SysBusDevice parent_obj;
|
|
|
|
|
2013-08-03 00:18:51 +02:00
|
|
|
I2CBus *bus;
|
2007-11-11 01:04:49 +01:00
|
|
|
qemu_irq irq;
|
2011-10-17 17:28:30 +02:00
|
|
|
MemoryRegion iomem;
|
2007-11-11 01:04:49 +01:00
|
|
|
uint32_t msa;
|
|
|
|
uint32_t mcs;
|
|
|
|
uint32_t mdr;
|
|
|
|
uint32_t mtpr;
|
|
|
|
uint32_t mimr;
|
|
|
|
uint32_t mris;
|
|
|
|
uint32_t mcr;
|
2020-09-03 22:43:22 +02:00
|
|
|
};
|
2007-11-11 01:04:49 +01:00
|
|
|
|
|
|
|
#define STELLARIS_I2C_MCS_BUSY 0x01
|
|
|
|
#define STELLARIS_I2C_MCS_ERROR 0x02
|
|
|
|
#define STELLARIS_I2C_MCS_ADRACK 0x04
|
|
|
|
#define STELLARIS_I2C_MCS_DATACK 0x08
|
|
|
|
#define STELLARIS_I2C_MCS_ARBLST 0x10
|
|
|
|
#define STELLARIS_I2C_MCS_IDLE 0x20
|
|
|
|
#define STELLARIS_I2C_MCS_BUSBSY 0x40
|
|
|
|
|
2012-10-23 12:30:10 +02:00
|
|
|
static uint64_t stellaris_i2c_read(void *opaque, hwaddr offset,
|
2011-10-17 17:28:30 +02:00
|
|
|
unsigned size)
|
2007-11-11 01:04:49 +01:00
|
|
|
{
|
|
|
|
stellaris_i2c_state *s = (stellaris_i2c_state *)opaque;
|
|
|
|
|
|
|
|
switch (offset) {
|
|
|
|
case 0x00: /* MSA */
|
|
|
|
return s->msa;
|
|
|
|
case 0x04: /* MCS */
|
|
|
|
/* We don't emulate timing, so the controller is never busy. */
|
|
|
|
return s->mcs | STELLARIS_I2C_MCS_IDLE;
|
|
|
|
case 0x08: /* MDR */
|
|
|
|
return s->mdr;
|
|
|
|
case 0x0c: /* MTPR */
|
|
|
|
return s->mtpr;
|
|
|
|
case 0x10: /* MIMR */
|
|
|
|
return s->mimr;
|
|
|
|
case 0x14: /* MRIS */
|
|
|
|
return s->mris;
|
|
|
|
case 0x18: /* MMIS */
|
|
|
|
return s->mris & s->mimr;
|
|
|
|
case 0x20: /* MCR */
|
|
|
|
return s->mcr;
|
|
|
|
default:
|
2017-04-20 18:32:29 +02:00
|
|
|
qemu_log_mask(LOG_GUEST_ERROR,
|
|
|
|
"stellaris_i2c: read at bad offset 0x%x\n", (int)offset);
|
2007-11-11 01:04:49 +01:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
static void stellaris_i2c_update(stellaris_i2c_state *s)
|
|
|
|
{
|
|
|
|
int level;
|
|
|
|
|
|
|
|
level = (s->mris & s->mimr) != 0;
|
|
|
|
qemu_set_irq(s->irq, level);
|
|
|
|
}
|
|
|
|
|
2012-10-23 12:30:10 +02:00
|
|
|
static void stellaris_i2c_write(void *opaque, hwaddr offset,
|
2011-10-17 17:28:30 +02:00
|
|
|
uint64_t value, unsigned size)
|
2007-11-11 01:04:49 +01:00
|
|
|
{
|
|
|
|
stellaris_i2c_state *s = (stellaris_i2c_state *)opaque;
|
|
|
|
|
|
|
|
switch (offset) {
|
|
|
|
case 0x00: /* MSA */
|
|
|
|
s->msa = value & 0xff;
|
|
|
|
break;
|
|
|
|
case 0x04: /* MCS */
|
|
|
|
if ((s->mcr & 0x10) == 0) {
|
|
|
|
/* Disabled. Do nothing. */
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
/* Grab the bus if this is starting a transfer. */
|
|
|
|
if ((value & 2) && (s->mcs & STELLARIS_I2C_MCS_BUSBSY) == 0) {
|
|
|
|
if (i2c_start_transfer(s->bus, s->msa >> 1, s->msa & 1)) {
|
|
|
|
s->mcs |= STELLARIS_I2C_MCS_ARBLST;
|
|
|
|
} else {
|
|
|
|
s->mcs &= ~STELLARIS_I2C_MCS_ARBLST;
|
|
|
|
s->mcs |= STELLARIS_I2C_MCS_BUSBSY;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
/* If we don't have the bus then indicate an error. */
|
|
|
|
if (!i2c_bus_busy(s->bus)
|
|
|
|
|| (s->mcs & STELLARIS_I2C_MCS_BUSBSY) == 0) {
|
|
|
|
s->mcs |= STELLARIS_I2C_MCS_ERROR;
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
s->mcs &= ~STELLARIS_I2C_MCS_ERROR;
|
|
|
|
if (value & 1) {
|
|
|
|
/* Transfer a byte. */
|
|
|
|
/* TODO: Handle errors. */
|
|
|
|
if (s->msa & 1) {
|
|
|
|
/* Recv */
|
2018-11-20 18:10:58 +01:00
|
|
|
s->mdr = i2c_recv(s->bus);
|
2007-11-11 01:04:49 +01:00
|
|
|
} else {
|
|
|
|
/* Send */
|
|
|
|
i2c_send(s->bus, s->mdr);
|
|
|
|
}
|
|
|
|
/* Raise an interrupt. */
|
|
|
|
s->mris |= 1;
|
|
|
|
}
|
|
|
|
if (value & 4) {
|
|
|
|
/* Finish transfer. */
|
|
|
|
i2c_end_transfer(s->bus);
|
|
|
|
s->mcs &= ~STELLARIS_I2C_MCS_BUSBSY;
|
|
|
|
}
|
|
|
|
break;
|
|
|
|
case 0x08: /* MDR */
|
|
|
|
s->mdr = value & 0xff;
|
|
|
|
break;
|
|
|
|
case 0x0c: /* MTPR */
|
|
|
|
s->mtpr = value & 0xff;
|
|
|
|
break;
|
|
|
|
case 0x10: /* MIMR */
|
|
|
|
s->mimr = 1;
|
|
|
|
break;
|
|
|
|
case 0x1c: /* MICR */
|
|
|
|
s->mris &= ~value;
|
|
|
|
break;
|
|
|
|
case 0x20: /* MCR */
|
2017-04-20 18:32:29 +02:00
|
|
|
if (value & 1) {
|
2018-06-08 14:15:33 +02:00
|
|
|
qemu_log_mask(LOG_UNIMP,
|
|
|
|
"stellaris_i2c: Loopback not implemented\n");
|
2017-04-20 18:32:29 +02:00
|
|
|
}
|
|
|
|
if (value & 0x20) {
|
|
|
|
qemu_log_mask(LOG_UNIMP,
|
2018-06-08 14:15:33 +02:00
|
|
|
"stellaris_i2c: Slave mode not implemented\n");
|
2017-04-20 18:32:29 +02:00
|
|
|
}
|
2007-11-11 01:04:49 +01:00
|
|
|
s->mcr = value & 0x31;
|
|
|
|
break;
|
|
|
|
default:
|
2017-04-20 18:32:29 +02:00
|
|
|
qemu_log_mask(LOG_GUEST_ERROR,
|
|
|
|
"stellaris_i2c: write at bad offset 0x%x\n", (int)offset);
|
2007-11-11 01:04:49 +01:00
|
|
|
}
|
|
|
|
stellaris_i2c_update(s);
|
|
|
|
}
|
|
|
|
|
|
|
|
static void stellaris_i2c_reset(stellaris_i2c_state *s)
|
|
|
|
{
|
|
|
|
if (s->mcs & STELLARIS_I2C_MCS_BUSBSY)
|
|
|
|
i2c_end_transfer(s->bus);
|
|
|
|
|
|
|
|
s->msa = 0;
|
|
|
|
s->mcs = 0;
|
|
|
|
s->mdr = 0;
|
|
|
|
s->mtpr = 1;
|
|
|
|
s->mimr = 0;
|
|
|
|
s->mris = 0;
|
|
|
|
s->mcr = 0;
|
|
|
|
stellaris_i2c_update(s);
|
|
|
|
}
|
|
|
|
|
2011-10-17 17:28:30 +02:00
|
|
|
static const MemoryRegionOps stellaris_i2c_ops = {
|
|
|
|
.read = stellaris_i2c_read,
|
|
|
|
.write = stellaris_i2c_write,
|
|
|
|
.endianness = DEVICE_NATIVE_ENDIAN,
|
2007-11-11 01:04:49 +01:00
|
|
|
};
|
|
|
|
|
2010-12-02 02:48:43 +01:00
|
|
|
static const VMStateDescription vmstate_stellaris_i2c = {
|
|
|
|
.name = "stellaris_i2c",
|
|
|
|
.version_id = 1,
|
|
|
|
.minimum_version_id = 1,
|
2014-05-13 17:09:35 +02:00
|
|
|
.fields = (VMStateField[]) {
|
2010-12-02 02:48:43 +01:00
|
|
|
VMSTATE_UINT32(msa, stellaris_i2c_state),
|
|
|
|
VMSTATE_UINT32(mcs, stellaris_i2c_state),
|
|
|
|
VMSTATE_UINT32(mdr, stellaris_i2c_state),
|
|
|
|
VMSTATE_UINT32(mtpr, stellaris_i2c_state),
|
|
|
|
VMSTATE_UINT32(mimr, stellaris_i2c_state),
|
|
|
|
VMSTATE_UINT32(mris, stellaris_i2c_state),
|
|
|
|
VMSTATE_UINT32(mcr, stellaris_i2c_state),
|
|
|
|
VMSTATE_END_OF_LIST()
|
|
|
|
}
|
|
|
|
};
|
2008-07-02 18:48:32 +02:00
|
|
|
|
2016-03-07 08:05:48 +01:00
|
|
|
static void stellaris_i2c_init(Object *obj)
|
2007-11-11 01:04:49 +01:00
|
|
|
{
|
2016-03-07 08:05:48 +01:00
|
|
|
DeviceState *dev = DEVICE(obj);
|
|
|
|
stellaris_i2c_state *s = STELLARIS_I2C(obj);
|
|
|
|
SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
|
2013-08-03 00:18:51 +02:00
|
|
|
I2CBus *bus;
|
2007-11-11 01:04:49 +01:00
|
|
|
|
2013-07-24 09:08:23 +02:00
|
|
|
sysbus_init_irq(sbd, &s->irq);
|
|
|
|
bus = i2c_init_bus(dev, "i2c");
|
2007-11-11 01:04:49 +01:00
|
|
|
s->bus = bus;
|
|
|
|
|
2016-03-07 08:05:48 +01:00
|
|
|
memory_region_init_io(&s->iomem, obj, &stellaris_i2c_ops, s,
|
2011-10-17 17:28:30 +02:00
|
|
|
"i2c", 0x1000);
|
2013-07-24 09:08:23 +02:00
|
|
|
sysbus_init_mmio(sbd, &s->iomem);
|
2007-11-11 01:04:49 +01:00
|
|
|
/* ??? For now we only implement the master interface. */
|
|
|
|
stellaris_i2c_reset(s);
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Analogue to Digital Converter. This is only partially implemented,
|
|
|
|
enough for applications that use a combined ADC and timer tick. */
|
|
|
|
|
|
|
|
#define STELLARIS_ADC_EM_CONTROLLER 0
|
|
|
|
#define STELLARIS_ADC_EM_COMP 1
|
|
|
|
#define STELLARIS_ADC_EM_EXTERNAL 4
|
|
|
|
#define STELLARIS_ADC_EM_TIMER 5
|
|
|
|
#define STELLARIS_ADC_EM_PWM0 6
|
|
|
|
#define STELLARIS_ADC_EM_PWM1 7
|
|
|
|
#define STELLARIS_ADC_EM_PWM2 8
|
|
|
|
|
|
|
|
#define STELLARIS_ADC_FIFO_EMPTY 0x0100
|
|
|
|
#define STELLARIS_ADC_FIFO_FULL 0x1000
|
|
|
|
|
2013-07-24 09:13:06 +02:00
|
|
|
#define TYPE_STELLARIS_ADC "stellaris-adc"
|
2020-09-03 22:43:22 +02:00
|
|
|
typedef struct StellarisADCState stellaris_adc_state;
|
2020-08-31 23:07:33 +02:00
|
|
|
DECLARE_INSTANCE_CHECKER(stellaris_adc_state, STELLARIS_ADC,
|
|
|
|
TYPE_STELLARIS_ADC)
|
2013-07-24 09:13:06 +02:00
|
|
|
|
2020-09-03 22:43:22 +02:00
|
|
|
struct StellarisADCState {
|
2013-07-24 09:13:06 +02:00
|
|
|
SysBusDevice parent_obj;
|
|
|
|
|
2011-10-17 17:28:31 +02:00
|
|
|
MemoryRegion iomem;
|
2007-11-11 01:04:49 +01:00
|
|
|
uint32_t actss;
|
|
|
|
uint32_t ris;
|
|
|
|
uint32_t im;
|
|
|
|
uint32_t emux;
|
|
|
|
uint32_t ostat;
|
|
|
|
uint32_t ustat;
|
|
|
|
uint32_t sspri;
|
|
|
|
uint32_t sac;
|
|
|
|
struct {
|
|
|
|
uint32_t state;
|
|
|
|
uint32_t data[16];
|
|
|
|
} fifo[4];
|
|
|
|
uint32_t ssmux[4];
|
|
|
|
uint32_t ssctl[4];
|
2008-07-02 18:48:32 +02:00
|
|
|
uint32_t noise;
|
2009-06-02 16:30:27 +02:00
|
|
|
qemu_irq irq[4];
|
2020-09-03 22:43:22 +02:00
|
|
|
};
|
2007-11-11 01:04:49 +01:00
|
|
|
|
|
|
|
static uint32_t stellaris_adc_fifo_read(stellaris_adc_state *s, int n)
|
|
|
|
{
|
|
|
|
int tail;
|
|
|
|
|
|
|
|
tail = s->fifo[n].state & 0xf;
|
|
|
|
if (s->fifo[n].state & STELLARIS_ADC_FIFO_EMPTY) {
|
|
|
|
s->ustat |= 1 << n;
|
|
|
|
} else {
|
|
|
|
s->fifo[n].state = (s->fifo[n].state & ~0xf) | ((tail + 1) & 0xf);
|
|
|
|
s->fifo[n].state &= ~STELLARIS_ADC_FIFO_FULL;
|
|
|
|
if (tail + 1 == ((s->fifo[n].state >> 4) & 0xf))
|
|
|
|
s->fifo[n].state |= STELLARIS_ADC_FIFO_EMPTY;
|
|
|
|
}
|
|
|
|
return s->fifo[n].data[tail];
|
|
|
|
}
|
|
|
|
|
|
|
|
static void stellaris_adc_fifo_write(stellaris_adc_state *s, int n,
|
|
|
|
uint32_t value)
|
|
|
|
{
|
|
|
|
int head;
|
|
|
|
|
2009-06-02 16:30:27 +02:00
|
|
|
/* TODO: Real hardware has limited size FIFOs. We have a full 16 entry
|
|
|
|
FIFO fir each sequencer. */
|
2007-11-11 01:04:49 +01:00
|
|
|
head = (s->fifo[n].state >> 4) & 0xf;
|
|
|
|
if (s->fifo[n].state & STELLARIS_ADC_FIFO_FULL) {
|
|
|
|
s->ostat |= 1 << n;
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
s->fifo[n].data[head] = value;
|
|
|
|
head = (head + 1) & 0xf;
|
|
|
|
s->fifo[n].state &= ~STELLARIS_ADC_FIFO_EMPTY;
|
|
|
|
s->fifo[n].state = (s->fifo[n].state & ~0xf0) | (head << 4);
|
|
|
|
if ((s->fifo[n].state & 0xf) == head)
|
|
|
|
s->fifo[n].state |= STELLARIS_ADC_FIFO_FULL;
|
|
|
|
}
|
|
|
|
|
|
|
|
static void stellaris_adc_update(stellaris_adc_state *s)
|
|
|
|
{
|
|
|
|
int level;
|
2009-06-02 16:30:27 +02:00
|
|
|
int n;
|
2007-11-11 01:04:49 +01:00
|
|
|
|
2009-06-02 16:30:27 +02:00
|
|
|
for (n = 0; n < 4; n++) {
|
|
|
|
level = (s->ris & s->im & (1 << n)) != 0;
|
|
|
|
qemu_set_irq(s->irq[n], level);
|
|
|
|
}
|
2007-11-11 01:04:49 +01:00
|
|
|
}
|
|
|
|
|
|
|
|
static void stellaris_adc_trigger(void *opaque, int irq, int level)
|
|
|
|
{
|
|
|
|
stellaris_adc_state *s = (stellaris_adc_state *)opaque;
|
2009-06-02 16:30:27 +02:00
|
|
|
int n;
|
2007-11-11 01:04:49 +01:00
|
|
|
|
2009-06-02 16:30:27 +02:00
|
|
|
for (n = 0; n < 4; n++) {
|
|
|
|
if ((s->actss & (1 << n)) == 0) {
|
|
|
|
continue;
|
|
|
|
}
|
2007-11-11 01:04:49 +01:00
|
|
|
|
2009-06-02 16:30:27 +02:00
|
|
|
if (((s->emux >> (n * 4)) & 0xff) != 5) {
|
|
|
|
continue;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Some applications use the ADC as a random number source, so introduce
|
|
|
|
some variation into the signal. */
|
|
|
|
s->noise = s->noise * 314159 + 1;
|
|
|
|
/* ??? actual inputs not implemented. Return an arbitrary value. */
|
|
|
|
stellaris_adc_fifo_write(s, n, 0x200 + ((s->noise >> 16) & 7));
|
|
|
|
s->ris |= (1 << n);
|
|
|
|
stellaris_adc_update(s);
|
|
|
|
}
|
2007-11-11 01:04:49 +01:00
|
|
|
}
|
|
|
|
|
|
|
|
static void stellaris_adc_reset(stellaris_adc_state *s)
|
|
|
|
{
|
|
|
|
int n;
|
|
|
|
|
|
|
|
for (n = 0; n < 4; n++) {
|
|
|
|
s->ssmux[n] = 0;
|
|
|
|
s->ssctl[n] = 0;
|
|
|
|
s->fifo[n].state = STELLARIS_ADC_FIFO_EMPTY;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2012-10-23 12:30:10 +02:00
|
|
|
static uint64_t stellaris_adc_read(void *opaque, hwaddr offset,
|
2011-10-17 17:28:31 +02:00
|
|
|
unsigned size)
|
2007-11-11 01:04:49 +01:00
|
|
|
{
|
|
|
|
stellaris_adc_state *s = (stellaris_adc_state *)opaque;
|
|
|
|
|
|
|
|
/* TODO: Implement this. */
|
|
|
|
if (offset >= 0x40 && offset < 0xc0) {
|
|
|
|
int n;
|
|
|
|
n = (offset - 0x40) >> 5;
|
|
|
|
switch (offset & 0x1f) {
|
|
|
|
case 0x00: /* SSMUX */
|
|
|
|
return s->ssmux[n];
|
|
|
|
case 0x04: /* SSCTL */
|
|
|
|
return s->ssctl[n];
|
|
|
|
case 0x08: /* SSFIFO */
|
|
|
|
return stellaris_adc_fifo_read(s, n);
|
|
|
|
case 0x0c: /* SSFSTAT */
|
|
|
|
return s->fifo[n].state;
|
|
|
|
default:
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
switch (offset) {
|
|
|
|
case 0x00: /* ACTSS */
|
|
|
|
return s->actss;
|
|
|
|
case 0x04: /* RIS */
|
|
|
|
return s->ris;
|
|
|
|
case 0x08: /* IM */
|
|
|
|
return s->im;
|
|
|
|
case 0x0c: /* ISC */
|
|
|
|
return s->ris & s->im;
|
|
|
|
case 0x10: /* OSTAT */
|
|
|
|
return s->ostat;
|
|
|
|
case 0x14: /* EMUX */
|
|
|
|
return s->emux;
|
|
|
|
case 0x18: /* USTAT */
|
|
|
|
return s->ustat;
|
|
|
|
case 0x20: /* SSPRI */
|
|
|
|
return s->sspri;
|
|
|
|
case 0x30: /* SAC */
|
|
|
|
return s->sac;
|
|
|
|
default:
|
2017-04-20 18:32:29 +02:00
|
|
|
qemu_log_mask(LOG_GUEST_ERROR,
|
|
|
|
"stellaris_adc: read at bad offset 0x%x\n", (int)offset);
|
2007-11-11 01:04:49 +01:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2012-10-23 12:30:10 +02:00
|
|
|
static void stellaris_adc_write(void *opaque, hwaddr offset,
|
2011-10-17 17:28:31 +02:00
|
|
|
uint64_t value, unsigned size)
|
2007-11-11 01:04:49 +01:00
|
|
|
{
|
|
|
|
stellaris_adc_state *s = (stellaris_adc_state *)opaque;
|
|
|
|
|
|
|
|
/* TODO: Implement this. */
|
|
|
|
if (offset >= 0x40 && offset < 0xc0) {
|
|
|
|
int n;
|
|
|
|
n = (offset - 0x40) >> 5;
|
|
|
|
switch (offset & 0x1f) {
|
|
|
|
case 0x00: /* SSMUX */
|
|
|
|
s->ssmux[n] = value & 0x33333333;
|
|
|
|
return;
|
|
|
|
case 0x04: /* SSCTL */
|
|
|
|
if (value != 6) {
|
2017-04-20 18:32:29 +02:00
|
|
|
qemu_log_mask(LOG_UNIMP,
|
|
|
|
"ADC: Unimplemented sequence %" PRIx64 "\n",
|
|
|
|
value);
|
2007-11-11 01:04:49 +01:00
|
|
|
}
|
|
|
|
s->ssctl[n] = value;
|
|
|
|
return;
|
|
|
|
default:
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
switch (offset) {
|
|
|
|
case 0x00: /* ACTSS */
|
|
|
|
s->actss = value & 0xf;
|
|
|
|
break;
|
|
|
|
case 0x08: /* IM */
|
|
|
|
s->im = value;
|
|
|
|
break;
|
|
|
|
case 0x0c: /* ISC */
|
|
|
|
s->ris &= ~value;
|
|
|
|
break;
|
|
|
|
case 0x10: /* OSTAT */
|
|
|
|
s->ostat &= ~value;
|
|
|
|
break;
|
|
|
|
case 0x14: /* EMUX */
|
|
|
|
s->emux = value;
|
|
|
|
break;
|
|
|
|
case 0x18: /* USTAT */
|
|
|
|
s->ustat &= ~value;
|
|
|
|
break;
|
|
|
|
case 0x20: /* SSPRI */
|
|
|
|
s->sspri = value;
|
|
|
|
break;
|
|
|
|
case 0x28: /* PSSI */
|
2018-06-08 14:15:33 +02:00
|
|
|
qemu_log_mask(LOG_UNIMP, "ADC: sample initiate unimplemented\n");
|
2007-11-11 01:04:49 +01:00
|
|
|
break;
|
|
|
|
case 0x30: /* SAC */
|
|
|
|
s->sac = value;
|
|
|
|
break;
|
|
|
|
default:
|
2017-04-20 18:32:29 +02:00
|
|
|
qemu_log_mask(LOG_GUEST_ERROR,
|
|
|
|
"stellaris_adc: write at bad offset 0x%x\n", (int)offset);
|
2007-11-11 01:04:49 +01:00
|
|
|
}
|
|
|
|
stellaris_adc_update(s);
|
|
|
|
}
|
|
|
|
|
2011-10-17 17:28:31 +02:00
|
|
|
static const MemoryRegionOps stellaris_adc_ops = {
|
|
|
|
.read = stellaris_adc_read,
|
|
|
|
.write = stellaris_adc_write,
|
|
|
|
.endianness = DEVICE_NATIVE_ENDIAN,
|
2007-11-11 01:04:49 +01:00
|
|
|
};
|
|
|
|
|
2010-12-03 01:27:58 +01:00
|
|
|
static const VMStateDescription vmstate_stellaris_adc = {
|
|
|
|
.name = "stellaris_adc",
|
|
|
|
.version_id = 1,
|
|
|
|
.minimum_version_id = 1,
|
2014-05-13 17:09:35 +02:00
|
|
|
.fields = (VMStateField[]) {
|
2010-12-03 01:27:58 +01:00
|
|
|
VMSTATE_UINT32(actss, stellaris_adc_state),
|
|
|
|
VMSTATE_UINT32(ris, stellaris_adc_state),
|
|
|
|
VMSTATE_UINT32(im, stellaris_adc_state),
|
|
|
|
VMSTATE_UINT32(emux, stellaris_adc_state),
|
|
|
|
VMSTATE_UINT32(ostat, stellaris_adc_state),
|
|
|
|
VMSTATE_UINT32(ustat, stellaris_adc_state),
|
|
|
|
VMSTATE_UINT32(sspri, stellaris_adc_state),
|
|
|
|
VMSTATE_UINT32(sac, stellaris_adc_state),
|
|
|
|
VMSTATE_UINT32(fifo[0].state, stellaris_adc_state),
|
|
|
|
VMSTATE_UINT32_ARRAY(fifo[0].data, stellaris_adc_state, 16),
|
|
|
|
VMSTATE_UINT32(ssmux[0], stellaris_adc_state),
|
|
|
|
VMSTATE_UINT32(ssctl[0], stellaris_adc_state),
|
|
|
|
VMSTATE_UINT32(fifo[1].state, stellaris_adc_state),
|
|
|
|
VMSTATE_UINT32_ARRAY(fifo[1].data, stellaris_adc_state, 16),
|
|
|
|
VMSTATE_UINT32(ssmux[1], stellaris_adc_state),
|
|
|
|
VMSTATE_UINT32(ssctl[1], stellaris_adc_state),
|
|
|
|
VMSTATE_UINT32(fifo[2].state, stellaris_adc_state),
|
|
|
|
VMSTATE_UINT32_ARRAY(fifo[2].data, stellaris_adc_state, 16),
|
|
|
|
VMSTATE_UINT32(ssmux[2], stellaris_adc_state),
|
|
|
|
VMSTATE_UINT32(ssctl[2], stellaris_adc_state),
|
|
|
|
VMSTATE_UINT32(fifo[3].state, stellaris_adc_state),
|
|
|
|
VMSTATE_UINT32_ARRAY(fifo[3].data, stellaris_adc_state, 16),
|
|
|
|
VMSTATE_UINT32(ssmux[3], stellaris_adc_state),
|
|
|
|
VMSTATE_UINT32(ssctl[3], stellaris_adc_state),
|
|
|
|
VMSTATE_UINT32(noise, stellaris_adc_state),
|
|
|
|
VMSTATE_END_OF_LIST()
|
2008-07-02 18:48:32 +02:00
|
|
|
}
|
2010-12-03 01:27:58 +01:00
|
|
|
};
|
2008-07-02 18:48:32 +02:00
|
|
|
|
2016-03-07 08:05:48 +01:00
|
|
|
static void stellaris_adc_init(Object *obj)
|
2007-11-11 01:04:49 +01:00
|
|
|
{
|
2016-03-07 08:05:48 +01:00
|
|
|
DeviceState *dev = DEVICE(obj);
|
|
|
|
stellaris_adc_state *s = STELLARIS_ADC(obj);
|
|
|
|
SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
|
2009-06-02 16:30:27 +02:00
|
|
|
int n;
|
2007-11-11 01:04:49 +01:00
|
|
|
|
2009-06-02 16:30:27 +02:00
|
|
|
for (n = 0; n < 4; n++) {
|
2013-07-24 09:13:06 +02:00
|
|
|
sysbus_init_irq(sbd, &s->irq[n]);
|
2009-06-02 16:30:27 +02:00
|
|
|
}
|
2007-11-11 01:04:49 +01:00
|
|
|
|
2016-03-07 08:05:48 +01:00
|
|
|
memory_region_init_io(&s->iomem, obj, &stellaris_adc_ops, s,
|
2011-10-17 17:28:31 +02:00
|
|
|
"adc", 0x1000);
|
2013-07-24 09:13:06 +02:00
|
|
|
sysbus_init_mmio(sbd, &s->iomem);
|
2007-11-11 01:04:49 +01:00
|
|
|
stellaris_adc_reset(s);
|
2013-07-24 09:13:06 +02:00
|
|
|
qdev_init_gpio_in(dev, stellaris_adc_trigger, 1);
|
2007-11-11 01:04:49 +01:00
|
|
|
}
|
|
|
|
|
|
|
|
/* Board init. */
|
|
|
|
static stellaris_board_info stellaris_boards[] = {
|
|
|
|
{ "LM3S811EVB",
|
|
|
|
0,
|
|
|
|
0x0032000e,
|
|
|
|
0x001f001f, /* dc0 */
|
|
|
|
0x001132bf,
|
|
|
|
0x01071013,
|
|
|
|
0x3f0f01ff,
|
|
|
|
0x0000001f,
|
2007-11-18 15:36:08 +01:00
|
|
|
BP_OLED_I2C
|
2007-11-11 01:04:49 +01:00
|
|
|
},
|
|
|
|
{ "LM3S6965EVB",
|
|
|
|
0x10010002,
|
|
|
|
0x1073402e,
|
|
|
|
0x00ff007f, /* dc0 */
|
|
|
|
0x001133ff,
|
|
|
|
0x030f5317,
|
|
|
|
0x0f0f87ff,
|
|
|
|
0x5000007f,
|
2007-11-18 15:36:08 +01:00
|
|
|
BP_OLED_SSI | BP_GAMEPAD
|
2007-11-11 01:04:49 +01:00
|
|
|
}
|
|
|
|
};
|
|
|
|
|
2017-09-13 18:04:57 +02:00
|
|
|
static void stellaris_init(MachineState *ms, stellaris_board_info *board)
|
2007-11-11 01:04:49 +01:00
|
|
|
{
|
|
|
|
static const int uart_irq[] = {5, 6, 33, 34};
|
|
|
|
static const int timer_irq[] = {19, 21, 23, 35};
|
|
|
|
static const uint32_t gpio_addr[7] =
|
|
|
|
{ 0x40004000, 0x40005000, 0x40006000, 0x40007000,
|
|
|
|
0x40024000, 0x40025000, 0x40026000};
|
|
|
|
static const int gpio_irq[7] = {0, 1, 2, 3, 4, 30, 31};
|
|
|
|
|
2017-02-07 19:30:00 +01:00
|
|
|
/* Memory map of SoC devices, from
|
|
|
|
* Stellaris LM3S6965 Microcontroller Data Sheet (rev I)
|
|
|
|
* http://www.ti.com/lit/ds/symlink/lm3s6965.pdf
|
|
|
|
*
|
2019-03-05 00:16:22 +01:00
|
|
|
* 40000000 wdtimer
|
2017-02-07 19:30:00 +01:00
|
|
|
* 40002000 i2c (unimplemented)
|
|
|
|
* 40004000 GPIO
|
|
|
|
* 40005000 GPIO
|
|
|
|
* 40006000 GPIO
|
|
|
|
* 40007000 GPIO
|
|
|
|
* 40008000 SSI
|
|
|
|
* 4000c000 UART
|
|
|
|
* 4000d000 UART
|
|
|
|
* 4000e000 UART
|
|
|
|
* 40020000 i2c
|
|
|
|
* 40021000 i2c (unimplemented)
|
|
|
|
* 40024000 GPIO
|
|
|
|
* 40025000 GPIO
|
|
|
|
* 40026000 GPIO
|
|
|
|
* 40028000 PWM (unimplemented)
|
|
|
|
* 4002c000 QEI (unimplemented)
|
|
|
|
* 4002d000 QEI (unimplemented)
|
|
|
|
* 40030000 gptimer
|
|
|
|
* 40031000 gptimer
|
|
|
|
* 40032000 gptimer
|
|
|
|
* 40033000 gptimer
|
|
|
|
* 40038000 ADC
|
|
|
|
* 4003c000 analogue comparator (unimplemented)
|
|
|
|
* 40048000 ethernet
|
|
|
|
* 400fc000 hibernation module (unimplemented)
|
|
|
|
* 400fd000 flash memory control (unimplemented)
|
|
|
|
* 400fe000 system control
|
|
|
|
*/
|
|
|
|
|
2015-11-03 14:49:41 +01:00
|
|
|
DeviceState *gpio_dev[7], *nvic;
|
2009-06-03 16:16:49 +02:00
|
|
|
qemu_irq gpio_in[7][8];
|
|
|
|
qemu_irq gpio_out[7][8];
|
2007-11-11 01:04:49 +01:00
|
|
|
qemu_irq adc;
|
|
|
|
int sram_size;
|
|
|
|
int flash_size;
|
2013-08-03 00:18:51 +02:00
|
|
|
I2CBus *i2c;
|
2009-06-03 16:16:49 +02:00
|
|
|
DeviceState *dev;
|
2021-01-28 12:41:37 +01:00
|
|
|
DeviceState *ssys_dev;
|
2007-11-11 01:04:49 +01:00
|
|
|
int i;
|
2009-06-03 16:16:49 +02:00
|
|
|
int j;
|
2021-08-12 11:33:48 +02:00
|
|
|
const uint8_t *macaddr;
|
2007-11-11 01:04:49 +01:00
|
|
|
|
2015-02-05 14:37:21 +01:00
|
|
|
MemoryRegion *sram = g_new(MemoryRegion, 1);
|
|
|
|
MemoryRegion *flash = g_new(MemoryRegion, 1);
|
|
|
|
MemoryRegion *system_memory = get_system_memory();
|
|
|
|
|
|
|
|
flash_size = (((board->dc0 & 0xffff) + 1) << 1) * 1024;
|
|
|
|
sram_size = ((board->dc0 >> 18) + 1) * 1024;
|
|
|
|
|
|
|
|
/* Flash programming is done via the SCU, so pretend it is ROM. */
|
2020-02-24 19:50:18 +01:00
|
|
|
memory_region_init_rom(flash, NULL, "stellaris.flash", flash_size,
|
Fix bad error handling after memory_region_init_ram()
Symptom:
$ qemu-system-x86_64 -m 10000000
Unexpected error in ram_block_add() at /work/armbru/qemu/exec.c:1456:
upstream-qemu: cannot set up guest memory 'pc.ram': Cannot allocate memory
Aborted (core dumped)
Root cause: commit ef701d7 screwed up handling of out-of-memory
conditions. Before the commit, we report the error and exit(1), in
one place, ram_block_add(). The commit lifts the error handling up
the call chain some, to three places. Fine. Except it uses
&error_abort in these places, changing the behavior from exit(1) to
abort(), and thus undoing the work of commit 3922825 "exec: Don't
abort when we can't allocate guest memory".
The three places are:
* memory_region_init_ram()
Commit 4994653 (right after commit ef701d7) lifted the error
handling further, through memory_region_init_ram(), multiplying the
incorrect use of &error_abort. Later on, imitation of existing
(bad) code may have created more.
* memory_region_init_ram_ptr()
The &error_abort is still there.
* memory_region_init_rom_device()
Doesn't need fixing, because commit 33e0eb5 (soon after commit
ef701d7) lifted the error handling further, and in the process
changed it from &error_abort to passing it up the call chain.
Correct, because the callers are realize() methods.
Fix the error handling after memory_region_init_ram() with a
Coccinelle semantic patch:
@r@
expression mr, owner, name, size, err;
position p;
@@
memory_region_init_ram(mr, owner, name, size,
(
- &error_abort
+ &error_fatal
|
err@p
)
);
@script:python@
p << r.p;
@@
print "%s:%s:%s" % (p[0].file, p[0].line, p[0].column)
When the last argument is &error_abort, it gets replaced by
&error_fatal. This is the fix.
If the last argument is anything else, its position is reported. This
lets us check the fix is complete. Four positions get reported:
* ram_backend_memory_alloc()
Error is passed up the call chain, ultimately through
user_creatable_complete(). As far as I can tell, it's callers all
handle the error sanely.
* fsl_imx25_realize(), fsl_imx31_realize(), dp8393x_realize()
DeviceClass.realize() methods, errors handled sanely further up the
call chain.
We're good. Test case again behaves:
$ qemu-system-x86_64 -m 10000000
qemu-system-x86_64: cannot set up guest memory 'pc.ram': Cannot allocate memory
[Exit 1 ]
The next commits will repair the rest of commit ef701d7's damage.
Signed-off-by: Markus Armbruster <armbru@redhat.com>
Message-Id: <1441983105-26376-3-git-send-email-armbru@redhat.com>
Reviewed-by: Peter Crosthwaite <crosthwaite.peter@gmail.com>
2015-09-11 16:51:43 +02:00
|
|
|
&error_fatal);
|
2015-02-05 14:37:21 +01:00
|
|
|
memory_region_add_subregion(system_memory, 0, flash);
|
|
|
|
|
2017-07-07 16:42:53 +02:00
|
|
|
memory_region_init_ram(sram, NULL, "stellaris.sram", sram_size,
|
Fix bad error handling after memory_region_init_ram()
Symptom:
$ qemu-system-x86_64 -m 10000000
Unexpected error in ram_block_add() at /work/armbru/qemu/exec.c:1456:
upstream-qemu: cannot set up guest memory 'pc.ram': Cannot allocate memory
Aborted (core dumped)
Root cause: commit ef701d7 screwed up handling of out-of-memory
conditions. Before the commit, we report the error and exit(1), in
one place, ram_block_add(). The commit lifts the error handling up
the call chain some, to three places. Fine. Except it uses
&error_abort in these places, changing the behavior from exit(1) to
abort(), and thus undoing the work of commit 3922825 "exec: Don't
abort when we can't allocate guest memory".
The three places are:
* memory_region_init_ram()
Commit 4994653 (right after commit ef701d7) lifted the error
handling further, through memory_region_init_ram(), multiplying the
incorrect use of &error_abort. Later on, imitation of existing
(bad) code may have created more.
* memory_region_init_ram_ptr()
The &error_abort is still there.
* memory_region_init_rom_device()
Doesn't need fixing, because commit 33e0eb5 (soon after commit
ef701d7) lifted the error handling further, and in the process
changed it from &error_abort to passing it up the call chain.
Correct, because the callers are realize() methods.
Fix the error handling after memory_region_init_ram() with a
Coccinelle semantic patch:
@r@
expression mr, owner, name, size, err;
position p;
@@
memory_region_init_ram(mr, owner, name, size,
(
- &error_abort
+ &error_fatal
|
err@p
)
);
@script:python@
p << r.p;
@@
print "%s:%s:%s" % (p[0].file, p[0].line, p[0].column)
When the last argument is &error_abort, it gets replaced by
&error_fatal. This is the fix.
If the last argument is anything else, its position is reported. This
lets us check the fix is complete. Four positions get reported:
* ram_backend_memory_alloc()
Error is passed up the call chain, ultimately through
user_creatable_complete(). As far as I can tell, it's callers all
handle the error sanely.
* fsl_imx25_realize(), fsl_imx31_realize(), dp8393x_realize()
DeviceClass.realize() methods, errors handled sanely further up the
call chain.
We're good. Test case again behaves:
$ qemu-system-x86_64 -m 10000000
qemu-system-x86_64: cannot set up guest memory 'pc.ram': Cannot allocate memory
[Exit 1 ]
The next commits will repair the rest of commit ef701d7's damage.
Signed-off-by: Markus Armbruster <armbru@redhat.com>
Message-Id: <1441983105-26376-3-git-send-email-armbru@redhat.com>
Reviewed-by: Peter Crosthwaite <crosthwaite.peter@gmail.com>
2015-09-11 16:51:43 +02:00
|
|
|
&error_fatal);
|
2015-02-05 14:37:21 +01:00
|
|
|
memory_region_add_subregion(system_memory, 0x20000000, sram);
|
|
|
|
|
2021-08-12 11:33:47 +02:00
|
|
|
/*
|
|
|
|
* Create the system-registers object early, because we will
|
|
|
|
* need its sysclk output.
|
|
|
|
*/
|
|
|
|
ssys_dev = qdev_new(TYPE_STELLARIS_SYS);
|
|
|
|
/* Most devices come preprogrammed with a MAC address in the user data. */
|
|
|
|
macaddr = nd_table[0].macaddr.a;
|
|
|
|
qdev_prop_set_uint32(ssys_dev, "user0",
|
|
|
|
macaddr[0] | (macaddr[1] << 8) | (macaddr[2] << 16));
|
|
|
|
qdev_prop_set_uint32(ssys_dev, "user1",
|
|
|
|
macaddr[3] | (macaddr[4] << 8) | (macaddr[5] << 16));
|
|
|
|
qdev_prop_set_uint32(ssys_dev, "did0", board->did0);
|
|
|
|
qdev_prop_set_uint32(ssys_dev, "did1", board->did1);
|
|
|
|
qdev_prop_set_uint32(ssys_dev, "dc0", board->dc0);
|
|
|
|
qdev_prop_set_uint32(ssys_dev, "dc1", board->dc1);
|
|
|
|
qdev_prop_set_uint32(ssys_dev, "dc2", board->dc2);
|
|
|
|
qdev_prop_set_uint32(ssys_dev, "dc3", board->dc3);
|
|
|
|
qdev_prop_set_uint32(ssys_dev, "dc4", board->dc4);
|
|
|
|
sysbus_realize_and_unref(SYS_BUS_DEVICE(ssys_dev), &error_fatal);
|
|
|
|
|
qdev: Convert uses of qdev_create() with Coccinelle
This is the transformation explained in the commit before previous.
Takes care of just one pattern that needs conversion. More to come in
this series.
Coccinelle script:
@ depends on !(file in "hw/arm/highbank.c")@
expression bus, type_name, dev, expr;
@@
- dev = qdev_create(bus, type_name);
+ dev = qdev_new(type_name);
... when != dev = expr
- qdev_init_nofail(dev);
+ qdev_realize_and_unref(dev, bus, &error_fatal);
@@
expression bus, type_name, dev, expr;
identifier DOWN;
@@
- dev = DOWN(qdev_create(bus, type_name));
+ dev = DOWN(qdev_new(type_name));
... when != dev = expr
- qdev_init_nofail(DEVICE(dev));
+ qdev_realize_and_unref(DEVICE(dev), bus, &error_fatal);
@@
expression bus, type_name, expr;
identifier dev;
@@
- DeviceState *dev = qdev_create(bus, type_name);
+ DeviceState *dev = qdev_new(type_name);
... when != dev = expr
- qdev_init_nofail(dev);
+ qdev_realize_and_unref(dev, bus, &error_fatal);
@@
expression bus, type_name, dev, expr, errp;
symbol true;
@@
- dev = qdev_create(bus, type_name);
+ dev = qdev_new(type_name);
... when != dev = expr
- object_property_set_bool(OBJECT(dev), true, "realized", errp);
+ qdev_realize_and_unref(dev, bus, errp);
@@
expression bus, type_name, expr, errp;
identifier dev;
symbol true;
@@
- DeviceState *dev = qdev_create(bus, type_name);
+ DeviceState *dev = qdev_new(type_name);
... when != dev = expr
- object_property_set_bool(OBJECT(dev), true, "realized", errp);
+ qdev_realize_and_unref(dev, bus, errp);
The first rule exempts hw/arm/highbank.c, because it matches along two
control flow paths there, with different @type_name. Covered by the
next commit's manual conversions.
Missing #include "qapi/error.h" added manually.
Signed-off-by: Markus Armbruster <armbru@redhat.com>
Reviewed-by: Paolo Bonzini <pbonzini@redhat.com>
Message-Id: <20200610053247.1583243-10-armbru@redhat.com>
[Conflicts in hw/misc/empty_slot.c and hw/sparc/leon3.c resolved]
2020-06-10 07:31:58 +02:00
|
|
|
nvic = qdev_new(TYPE_ARMV7M);
|
2018-06-15 15:57:13 +02:00
|
|
|
qdev_prop_set_uint32(nvic, "num-irq", NUM_IRQ_LINES);
|
|
|
|
qdev_prop_set_string(nvic, "cpu-type", ms->cpu_type);
|
2018-08-16 15:05:28 +02:00
|
|
|
qdev_prop_set_bit(nvic, "enable-bitband", true);
|
2021-08-12 11:33:48 +02:00
|
|
|
qdev_connect_clock_in(nvic, "cpuclk",
|
|
|
|
qdev_get_clock_out(ssys_dev, "SYSCLK"));
|
|
|
|
/* This SoC does not connect the systick reference clock */
|
qom: Put name parameter before value / visitor parameter
The object_property_set_FOO() setters take property name and value in
an unusual order:
void object_property_set_FOO(Object *obj, FOO_TYPE value,
const char *name, Error **errp)
Having to pass value before name feels grating. Swap them.
Same for object_property_set(), object_property_get(), and
object_property_parse().
Convert callers with this Coccinelle script:
@@
identifier fun = {
object_property_get, object_property_parse, object_property_set_str,
object_property_set_link, object_property_set_bool,
object_property_set_int, object_property_set_uint, object_property_set,
object_property_set_qobject
};
expression obj, v, name, errp;
@@
- fun(obj, v, name, errp)
+ fun(obj, name, v, errp)
Chokes on hw/arm/musicpal.c's lcd_refresh() with the unhelpful error
message "no position information". Convert that one manually.
Fails to convert hw/arm/armsse.c, because Coccinelle gets confused by
ARMSSE being used both as typedef and function-like macro there.
Convert manually.
Fails to convert hw/rx/rx-gdbsim.c, because Coccinelle gets confused
by RXCPU being used both as typedef and function-like macro there.
Convert manually. The other files using RXCPU that way don't need
conversion.
Signed-off-by: Markus Armbruster <armbru@redhat.com>
Reviewed-by: Eric Blake <eblake@redhat.com>
Reviewed-by: Vladimir Sementsov-Ogievskiy <vsementsov@virtuozzo.com>
Message-Id: <20200707160613.848843-27-armbru@redhat.com>
[Straightforwad conflict with commit 2336172d9b "audio: set default
value for pcspk.iobase property" resolved]
2020-07-07 18:05:54 +02:00
|
|
|
object_property_set_link(OBJECT(nvic), "memory",
|
|
|
|
OBJECT(get_system_memory()), &error_abort);
|
2018-06-15 15:57:13 +02:00
|
|
|
/* This will exit with an error if the user passed us a bad cpu_type */
|
sysbus: Convert to sysbus_realize() etc. with Coccinelle
Convert from qdev_realize(), qdev_realize_and_unref() with null @bus
argument to sysbus_realize(), sysbus_realize_and_unref().
Coccinelle script:
@@
expression dev, errp;
@@
- qdev_realize(DEVICE(dev), NULL, errp);
+ sysbus_realize(SYS_BUS_DEVICE(dev), errp);
@@
expression sysbus_dev, dev, errp;
@@
+ sysbus_dev = SYS_BUS_DEVICE(dev);
- qdev_realize_and_unref(dev, NULL, errp);
+ sysbus_realize_and_unref(sysbus_dev, errp);
- sysbus_dev = SYS_BUS_DEVICE(dev);
@@
expression sysbus_dev, dev, errp;
expression expr;
@@
sysbus_dev = SYS_BUS_DEVICE(dev);
... when != dev = expr;
- qdev_realize_and_unref(dev, NULL, errp);
+ sysbus_realize_and_unref(sysbus_dev, errp);
@@
expression dev, errp;
@@
- qdev_realize_and_unref(DEVICE(dev), NULL, errp);
+ sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), errp);
@@
expression dev, errp;
@@
- qdev_realize_and_unref(dev, NULL, errp);
+ sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), errp);
Whitespace changes minimized manually.
Signed-off-by: Markus Armbruster <armbru@redhat.com>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Reviewed-by: Paolo Bonzini <pbonzini@redhat.com>
Message-Id: <20200610053247.1583243-46-armbru@redhat.com>
[Conflicts in hw/misc/empty_slot.c and hw/sparc/leon3.c resolved]
2020-06-10 07:32:34 +02:00
|
|
|
sysbus_realize_and_unref(SYS_BUS_DEVICE(nvic), &error_fatal);
|
2007-11-11 01:04:49 +01:00
|
|
|
|
2021-08-12 11:33:47 +02:00
|
|
|
/* Now we can wire up the IRQ and MMIO of the system registers */
|
|
|
|
sysbus_mmio_map(SYS_BUS_DEVICE(ssys_dev), 0, 0x400fe000);
|
|
|
|
sysbus_connect_irq(SYS_BUS_DEVICE(ssys_dev), 0, qdev_get_gpio_in(nvic, 28));
|
|
|
|
|
2007-11-11 01:04:49 +01:00
|
|
|
if (board->dc1 & (1 << 16)) {
|
2013-07-24 09:13:06 +02:00
|
|
|
dev = sysbus_create_varargs(TYPE_STELLARIS_ADC, 0x40038000,
|
2015-11-03 14:49:41 +01:00
|
|
|
qdev_get_gpio_in(nvic, 14),
|
|
|
|
qdev_get_gpio_in(nvic, 15),
|
|
|
|
qdev_get_gpio_in(nvic, 16),
|
|
|
|
qdev_get_gpio_in(nvic, 17),
|
|
|
|
NULL);
|
2009-06-03 16:16:49 +02:00
|
|
|
adc = qdev_get_gpio_in(dev, 0);
|
2007-11-11 01:04:49 +01:00
|
|
|
} else {
|
|
|
|
adc = NULL;
|
|
|
|
}
|
|
|
|
for (i = 0; i < 4; i++) {
|
|
|
|
if (board->dc2 & (0x10000 << i)) {
|
2021-08-12 11:33:55 +02:00
|
|
|
SysBusDevice *sbd;
|
|
|
|
|
|
|
|
dev = qdev_new(TYPE_STELLARIS_GPTM);
|
|
|
|
sbd = SYS_BUS_DEVICE(dev);
|
|
|
|
qdev_connect_clock_in(dev, "clk",
|
|
|
|
qdev_get_clock_out(ssys_dev, "SYSCLK"));
|
|
|
|
sysbus_realize_and_unref(sbd, &error_fatal);
|
|
|
|
sysbus_mmio_map(sbd, 0, 0x40030000 + i * 0x1000);
|
|
|
|
sysbus_connect_irq(sbd, 0, qdev_get_gpio_in(nvic, timer_irq[i]));
|
2009-06-03 16:16:49 +02:00
|
|
|
/* TODO: This is incorrect, but we get away with it because
|
|
|
|
the ADC output is only ever pulsed. */
|
|
|
|
qdev_connect_gpio_out(dev, 0, adc);
|
2007-11-11 01:04:49 +01:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2019-03-05 00:16:22 +01:00
|
|
|
if (board->dc1 & (1 << 3)) { /* watchdog present */
|
qdev: Convert uses of qdev_create() with Coccinelle
This is the transformation explained in the commit before previous.
Takes care of just one pattern that needs conversion. More to come in
this series.
Coccinelle script:
@ depends on !(file in "hw/arm/highbank.c")@
expression bus, type_name, dev, expr;
@@
- dev = qdev_create(bus, type_name);
+ dev = qdev_new(type_name);
... when != dev = expr
- qdev_init_nofail(dev);
+ qdev_realize_and_unref(dev, bus, &error_fatal);
@@
expression bus, type_name, dev, expr;
identifier DOWN;
@@
- dev = DOWN(qdev_create(bus, type_name));
+ dev = DOWN(qdev_new(type_name));
... when != dev = expr
- qdev_init_nofail(DEVICE(dev));
+ qdev_realize_and_unref(DEVICE(dev), bus, &error_fatal);
@@
expression bus, type_name, expr;
identifier dev;
@@
- DeviceState *dev = qdev_create(bus, type_name);
+ DeviceState *dev = qdev_new(type_name);
... when != dev = expr
- qdev_init_nofail(dev);
+ qdev_realize_and_unref(dev, bus, &error_fatal);
@@
expression bus, type_name, dev, expr, errp;
symbol true;
@@
- dev = qdev_create(bus, type_name);
+ dev = qdev_new(type_name);
... when != dev = expr
- object_property_set_bool(OBJECT(dev), true, "realized", errp);
+ qdev_realize_and_unref(dev, bus, errp);
@@
expression bus, type_name, expr, errp;
identifier dev;
symbol true;
@@
- DeviceState *dev = qdev_create(bus, type_name);
+ DeviceState *dev = qdev_new(type_name);
... when != dev = expr
- object_property_set_bool(OBJECT(dev), true, "realized", errp);
+ qdev_realize_and_unref(dev, bus, errp);
The first rule exempts hw/arm/highbank.c, because it matches along two
control flow paths there, with different @type_name. Covered by the
next commit's manual conversions.
Missing #include "qapi/error.h" added manually.
Signed-off-by: Markus Armbruster <armbru@redhat.com>
Reviewed-by: Paolo Bonzini <pbonzini@redhat.com>
Message-Id: <20200610053247.1583243-10-armbru@redhat.com>
[Conflicts in hw/misc/empty_slot.c and hw/sparc/leon3.c resolved]
2020-06-10 07:31:58 +02:00
|
|
|
dev = qdev_new(TYPE_LUMINARY_WATCHDOG);
|
2019-03-05 00:16:22 +01:00
|
|
|
|
2021-01-28 12:41:37 +01:00
|
|
|
qdev_connect_clock_in(dev, "WDOGCLK",
|
|
|
|
qdev_get_clock_out(ssys_dev, "SYSCLK"));
|
2019-03-05 00:16:22 +01:00
|
|
|
|
sysbus: Convert to sysbus_realize() etc. with Coccinelle
Convert from qdev_realize(), qdev_realize_and_unref() with null @bus
argument to sysbus_realize(), sysbus_realize_and_unref().
Coccinelle script:
@@
expression dev, errp;
@@
- qdev_realize(DEVICE(dev), NULL, errp);
+ sysbus_realize(SYS_BUS_DEVICE(dev), errp);
@@
expression sysbus_dev, dev, errp;
@@
+ sysbus_dev = SYS_BUS_DEVICE(dev);
- qdev_realize_and_unref(dev, NULL, errp);
+ sysbus_realize_and_unref(sysbus_dev, errp);
- sysbus_dev = SYS_BUS_DEVICE(dev);
@@
expression sysbus_dev, dev, errp;
expression expr;
@@
sysbus_dev = SYS_BUS_DEVICE(dev);
... when != dev = expr;
- qdev_realize_and_unref(dev, NULL, errp);
+ sysbus_realize_and_unref(sysbus_dev, errp);
@@
expression dev, errp;
@@
- qdev_realize_and_unref(DEVICE(dev), NULL, errp);
+ sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), errp);
@@
expression dev, errp;
@@
- qdev_realize_and_unref(dev, NULL, errp);
+ sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), errp);
Whitespace changes minimized manually.
Signed-off-by: Markus Armbruster <armbru@redhat.com>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Reviewed-by: Paolo Bonzini <pbonzini@redhat.com>
Message-Id: <20200610053247.1583243-46-armbru@redhat.com>
[Conflicts in hw/misc/empty_slot.c and hw/sparc/leon3.c resolved]
2020-06-10 07:32:34 +02:00
|
|
|
sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
|
2019-03-05 00:16:22 +01:00
|
|
|
sysbus_mmio_map(SYS_BUS_DEVICE(dev),
|
|
|
|
0,
|
|
|
|
0x40000000u);
|
|
|
|
sysbus_connect_irq(SYS_BUS_DEVICE(dev),
|
|
|
|
0,
|
|
|
|
qdev_get_gpio_in(nvic, 18));
|
|
|
|
}
|
|
|
|
|
|
|
|
|
2007-11-11 01:04:49 +01:00
|
|
|
for (i = 0; i < 7; i++) {
|
|
|
|
if (board->dc4 & (1 << i)) {
|
2011-02-21 21:57:51 +01:00
|
|
|
gpio_dev[i] = sysbus_create_simple("pl061_luminary", gpio_addr[i],
|
2015-11-03 14:49:41 +01:00
|
|
|
qdev_get_gpio_in(nvic,
|
|
|
|
gpio_irq[i]));
|
2009-06-03 16:16:49 +02:00
|
|
|
for (j = 0; j < 8; j++) {
|
|
|
|
gpio_in[i][j] = qdev_get_gpio_in(gpio_dev[i], j);
|
|
|
|
gpio_out[i][j] = NULL;
|
|
|
|
}
|
2007-11-11 01:04:49 +01:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
if (board->dc2 & (1 << 12)) {
|
2015-11-03 14:49:41 +01:00
|
|
|
dev = sysbus_create_simple(TYPE_STELLARIS_I2C, 0x40020000,
|
|
|
|
qdev_get_gpio_in(nvic, 8));
|
2013-08-03 00:18:51 +02:00
|
|
|
i2c = (I2CBus *)qdev_get_child_bus(dev, "i2c");
|
2007-11-18 15:36:08 +01:00
|
|
|
if (board->peripherals & BP_OLED_I2C) {
|
2020-07-06 00:41:53 +02:00
|
|
|
i2c_slave_create_simple(i2c, "ssd0303", 0x3d);
|
2007-11-11 01:04:49 +01:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
for (i = 0; i < 4; i++) {
|
|
|
|
if (board->dc2 & (1 << i)) {
|
2016-06-06 17:59:31 +02:00
|
|
|
pl011_luminary_create(0x4000c000 + i * 0x1000,
|
|
|
|
qdev_get_gpio_in(nvic, uart_irq[i]),
|
2018-04-20 16:52:43 +02:00
|
|
|
serial_hd(i));
|
2007-11-11 01:04:49 +01:00
|
|
|
}
|
|
|
|
}
|
|
|
|
if (board->dc2 & (1 << 4)) {
|
2015-11-03 14:49:41 +01:00
|
|
|
dev = sysbus_create_simple("pl022", 0x40008000,
|
|
|
|
qdev_get_gpio_in(nvic, 7));
|
2007-11-18 15:36:08 +01:00
|
|
|
if (board->peripherals & BP_OLED_SSI) {
|
2009-05-14 23:35:09 +02:00
|
|
|
void *bus;
|
2012-07-31 08:42:04 +02:00
|
|
|
DeviceState *sddev;
|
|
|
|
DeviceState *ssddev;
|
2021-11-17 17:33:57 +01:00
|
|
|
DriveInfo *dinfo;
|
|
|
|
DeviceState *carddev;
|
|
|
|
BlockBackend *blk;
|
2012-07-31 08:42:04 +02:00
|
|
|
|
2021-07-02 12:40:18 +02:00
|
|
|
/*
|
|
|
|
* Some boards have both an OLED controller and SD card connected to
|
2012-07-31 08:42:04 +02:00
|
|
|
* the same SSI port, with the SD card chip select connected to a
|
|
|
|
* GPIO pin. Technically the OLED chip select is connected to the
|
|
|
|
* SSI Fss pin. We do not bother emulating that as both devices
|
|
|
|
* should never be selected simultaneously, and our OLED controller
|
|
|
|
* ignores stray 0xff commands that occur when deselecting the SD
|
|
|
|
* card.
|
2021-07-02 12:40:18 +02:00
|
|
|
*
|
|
|
|
* The h/w wiring is:
|
|
|
|
* - GPIO pin D0 is wired to the active-low SD card chip select
|
|
|
|
* - GPIO pin A3 is wired to the active-low OLED chip select
|
|
|
|
* - The SoC wiring of the PL061 "auxiliary function" for A3 is
|
|
|
|
* SSI0Fss ("frame signal"), which is an output from the SoC's
|
|
|
|
* SSI controller. The SSI controller takes SSI0Fss low when it
|
|
|
|
* transmits a frame, so it can work as a chip-select signal.
|
|
|
|
* - GPIO A4 is aux-function SSI0Rx, and wired to the SD card Tx
|
|
|
|
* (the OLED never sends data to the CPU, so no wiring needed)
|
|
|
|
* - GPIO A5 is aux-function SSI0Tx, and wired to the SD card Rx
|
|
|
|
* and the OLED display-data-in
|
|
|
|
* - GPIO A2 is aux-function SSI0Clk, wired to SD card and OLED
|
|
|
|
* serial-clock input
|
|
|
|
* So a guest that wants to use the OLED can configure the PL061
|
|
|
|
* to make pins A2, A3, A5 aux-function, so they are connected
|
|
|
|
* directly to the SSI controller. When the SSI controller sends
|
|
|
|
* data it asserts SSI0Fss which selects the OLED.
|
|
|
|
* A guest that wants to use the SD card configures A2, A4 and A5
|
|
|
|
* as aux-function, but leaves A3 as a software-controlled GPIO
|
|
|
|
* line. It asserts the SD card chip-select by using the PL061
|
|
|
|
* to control pin D0, and lets the SSI controller handle Clk, Tx
|
|
|
|
* and Rx. (The SSI controller asserts Fss during tx cycles as
|
|
|
|
* usual, but because A3 is not set to aux-function this is not
|
|
|
|
* forwarded to the OLED, and so the OLED stays unselected.)
|
|
|
|
*
|
|
|
|
* The QEMU implementation instead is:
|
|
|
|
* - GPIO pin D0 is wired to the active-low SD card chip select,
|
|
|
|
* and also to the OLED chip-select which is implemented
|
|
|
|
* as *active-high*
|
|
|
|
* - SSI controller signals go to the devices regardless of
|
|
|
|
* whether the guest programs A2, A4, A5 as aux-function or not
|
|
|
|
*
|
|
|
|
* The problem with this implementation is if the guest doesn't
|
|
|
|
* care about the SD card and only uses the OLED. In that case it
|
|
|
|
* may choose never to do anything with D0 (leaving it in its
|
|
|
|
* default floating state, which reliably leaves the card disabled
|
|
|
|
* because an SD card has a pullup on CS within the card itself),
|
|
|
|
* and only set up A2, A3, A5. This for us would mean the OLED
|
|
|
|
* never gets the chip-select assert it needs. We work around
|
|
|
|
* this with a manual raise of D0 here (despite board creation
|
|
|
|
* code being the wrong place to raise IRQ lines) to put the OLED
|
|
|
|
* into an initially selected state.
|
|
|
|
*
|
|
|
|
* In theory the right way to model this would be:
|
|
|
|
* - Implement aux-function support in the PL061, with an
|
|
|
|
* extra set of AFIN and AFOUT GPIO lines (set up so that
|
|
|
|
* if a GPIO line is in auxfn mode the main GPIO in and out
|
|
|
|
* track the AFIN and AFOUT lines)
|
|
|
|
* - Wire the AFOUT for D0 up to either a line from the
|
|
|
|
* SSI controller that's pulled low around every transmit,
|
|
|
|
* or at least to an always-0 line here on the board
|
|
|
|
* - Make the ssd0323 OLED controller chipselect active-low
|
2012-07-31 08:42:04 +02:00
|
|
|
*/
|
2009-05-14 23:35:09 +02:00
|
|
|
bus = qdev_get_child_bus(dev, "ssi");
|
2020-10-12 14:49:55 +02:00
|
|
|
sddev = ssi_create_peripheral(bus, "ssi-sd");
|
2021-11-17 17:33:57 +01:00
|
|
|
|
|
|
|
dinfo = drive_get(IF_SD, 0, 0);
|
|
|
|
blk = dinfo ? blk_by_legacy_dinfo(dinfo) : NULL;
|
|
|
|
carddev = qdev_new(TYPE_SD_CARD);
|
|
|
|
qdev_prop_set_drive_err(carddev, "drive", blk, &error_fatal);
|
|
|
|
qdev_prop_set_bit(carddev, "spi", true);
|
|
|
|
qdev_realize_and_unref(carddev,
|
|
|
|
qdev_get_child_bus(sddev, "sd-bus"),
|
|
|
|
&error_fatal);
|
|
|
|
|
2020-10-12 14:49:55 +02:00
|
|
|
ssddev = ssi_create_peripheral(bus, "ssd0323");
|
2014-05-20 08:31:33 +02:00
|
|
|
gpio_out[GPIO_D][0] = qemu_irq_split(
|
|
|
|
qdev_get_gpio_in_named(sddev, SSI_GPIO_CS, 0),
|
|
|
|
qdev_get_gpio_in_named(ssddev, SSI_GPIO_CS, 0));
|
|
|
|
gpio_out[GPIO_C][7] = qdev_get_gpio_in(ssddev, 0);
|
2007-11-25 00:35:08 +01:00
|
|
|
|
|
|
|
/* Make sure the select pin is high. */
|
|
|
|
qemu_irq_raise(gpio_out[GPIO_D][0]);
|
2007-11-11 01:04:49 +01:00
|
|
|
}
|
|
|
|
}
|
2009-05-14 23:35:07 +02:00
|
|
|
if (board->dc4 & (1 << 28)) {
|
|
|
|
DeviceState *enet;
|
|
|
|
|
|
|
|
qemu_check_nic_model(&nd_table[0], "stellaris");
|
|
|
|
|
qdev: Convert uses of qdev_create() with Coccinelle
This is the transformation explained in the commit before previous.
Takes care of just one pattern that needs conversion. More to come in
this series.
Coccinelle script:
@ depends on !(file in "hw/arm/highbank.c")@
expression bus, type_name, dev, expr;
@@
- dev = qdev_create(bus, type_name);
+ dev = qdev_new(type_name);
... when != dev = expr
- qdev_init_nofail(dev);
+ qdev_realize_and_unref(dev, bus, &error_fatal);
@@
expression bus, type_name, dev, expr;
identifier DOWN;
@@
- dev = DOWN(qdev_create(bus, type_name));
+ dev = DOWN(qdev_new(type_name));
... when != dev = expr
- qdev_init_nofail(DEVICE(dev));
+ qdev_realize_and_unref(DEVICE(dev), bus, &error_fatal);
@@
expression bus, type_name, expr;
identifier dev;
@@
- DeviceState *dev = qdev_create(bus, type_name);
+ DeviceState *dev = qdev_new(type_name);
... when != dev = expr
- qdev_init_nofail(dev);
+ qdev_realize_and_unref(dev, bus, &error_fatal);
@@
expression bus, type_name, dev, expr, errp;
symbol true;
@@
- dev = qdev_create(bus, type_name);
+ dev = qdev_new(type_name);
... when != dev = expr
- object_property_set_bool(OBJECT(dev), true, "realized", errp);
+ qdev_realize_and_unref(dev, bus, errp);
@@
expression bus, type_name, expr, errp;
identifier dev;
symbol true;
@@
- DeviceState *dev = qdev_create(bus, type_name);
+ DeviceState *dev = qdev_new(type_name);
... when != dev = expr
- object_property_set_bool(OBJECT(dev), true, "realized", errp);
+ qdev_realize_and_unref(dev, bus, errp);
The first rule exempts hw/arm/highbank.c, because it matches along two
control flow paths there, with different @type_name. Covered by the
next commit's manual conversions.
Missing #include "qapi/error.h" added manually.
Signed-off-by: Markus Armbruster <armbru@redhat.com>
Reviewed-by: Paolo Bonzini <pbonzini@redhat.com>
Message-Id: <20200610053247.1583243-10-armbru@redhat.com>
[Conflicts in hw/misc/empty_slot.c and hw/sparc/leon3.c resolved]
2020-06-10 07:31:58 +02:00
|
|
|
enet = qdev_new("stellaris_enet");
|
2009-10-21 15:25:39 +02:00
|
|
|
qdev_set_nic_properties(enet, &nd_table[0]);
|
sysbus: Convert to sysbus_realize() etc. with Coccinelle
Convert from qdev_realize(), qdev_realize_and_unref() with null @bus
argument to sysbus_realize(), sysbus_realize_and_unref().
Coccinelle script:
@@
expression dev, errp;
@@
- qdev_realize(DEVICE(dev), NULL, errp);
+ sysbus_realize(SYS_BUS_DEVICE(dev), errp);
@@
expression sysbus_dev, dev, errp;
@@
+ sysbus_dev = SYS_BUS_DEVICE(dev);
- qdev_realize_and_unref(dev, NULL, errp);
+ sysbus_realize_and_unref(sysbus_dev, errp);
- sysbus_dev = SYS_BUS_DEVICE(dev);
@@
expression sysbus_dev, dev, errp;
expression expr;
@@
sysbus_dev = SYS_BUS_DEVICE(dev);
... when != dev = expr;
- qdev_realize_and_unref(dev, NULL, errp);
+ sysbus_realize_and_unref(sysbus_dev, errp);
@@
expression dev, errp;
@@
- qdev_realize_and_unref(DEVICE(dev), NULL, errp);
+ sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), errp);
@@
expression dev, errp;
@@
- qdev_realize_and_unref(dev, NULL, errp);
+ sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), errp);
Whitespace changes minimized manually.
Signed-off-by: Markus Armbruster <armbru@redhat.com>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Reviewed-by: Paolo Bonzini <pbonzini@redhat.com>
Message-Id: <20200610053247.1583243-46-armbru@redhat.com>
[Conflicts in hw/misc/empty_slot.c and hw/sparc/leon3.c resolved]
2020-06-10 07:32:34 +02:00
|
|
|
sysbus_realize_and_unref(SYS_BUS_DEVICE(enet), &error_fatal);
|
2013-01-20 02:47:33 +01:00
|
|
|
sysbus_mmio_map(SYS_BUS_DEVICE(enet), 0, 0x40048000);
|
2015-11-03 14:49:41 +01:00
|
|
|
sysbus_connect_irq(SYS_BUS_DEVICE(enet), 0, qdev_get_gpio_in(nvic, 42));
|
2009-05-14 23:35:07 +02:00
|
|
|
}
|
2007-11-18 15:36:08 +01:00
|
|
|
if (board->peripherals & BP_GAMEPAD) {
|
|
|
|
qemu_irq gpad_irq[5];
|
|
|
|
static const int gpad_keycode[5] = { 0xc8, 0xd0, 0xcb, 0xcd, 0x1d };
|
|
|
|
|
|
|
|
gpad_irq[0] = qemu_irq_invert(gpio_in[GPIO_E][0]); /* up */
|
|
|
|
gpad_irq[1] = qemu_irq_invert(gpio_in[GPIO_E][1]); /* down */
|
|
|
|
gpad_irq[2] = qemu_irq_invert(gpio_in[GPIO_E][2]); /* left */
|
|
|
|
gpad_irq[3] = qemu_irq_invert(gpio_in[GPIO_E][3]); /* right */
|
|
|
|
gpad_irq[4] = qemu_irq_invert(gpio_in[GPIO_F][1]); /* select */
|
|
|
|
|
|
|
|
stellaris_gamepad_init(5, gpad_irq, gpad_keycode);
|
|
|
|
}
|
2009-06-03 16:16:49 +02:00
|
|
|
for (i = 0; i < 7; i++) {
|
|
|
|
if (board->dc4 & (1 << i)) {
|
|
|
|
for (j = 0; j < 8; j++) {
|
|
|
|
if (gpio_out[i][j]) {
|
|
|
|
qdev_connect_gpio_out(gpio_dev[i], j, gpio_out[i][j]);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
2017-02-07 19:30:00 +01:00
|
|
|
|
|
|
|
/* Add dummy regions for the devices we don't implement yet,
|
|
|
|
* so guest accesses don't cause unlogged crashes.
|
|
|
|
*/
|
|
|
|
create_unimplemented_device("i2c-0", 0x40002000, 0x1000);
|
|
|
|
create_unimplemented_device("i2c-2", 0x40021000, 0x1000);
|
|
|
|
create_unimplemented_device("PWM", 0x40028000, 0x1000);
|
|
|
|
create_unimplemented_device("QEI-0", 0x4002c000, 0x1000);
|
|
|
|
create_unimplemented_device("QEI-1", 0x4002d000, 0x1000);
|
|
|
|
create_unimplemented_device("analogue-comparator", 0x4003c000, 0x1000);
|
|
|
|
create_unimplemented_device("hibernation", 0x400fc000, 0x1000);
|
|
|
|
create_unimplemented_device("flash-control", 0x400fd000, 0x1000);
|
2018-06-15 15:57:13 +02:00
|
|
|
|
|
|
|
armv7m_load_kernel(ARM_CPU(first_cpu), ms->kernel_filename, flash_size);
|
2007-11-11 01:04:49 +01:00
|
|
|
}
|
|
|
|
|
|
|
|
/* FIXME: Figure out how to generate these from stellaris_boards. */
|
2014-05-07 16:42:57 +02:00
|
|
|
static void lm3s811evb_init(MachineState *machine)
|
2007-11-11 01:04:49 +01:00
|
|
|
{
|
2017-09-13 18:04:57 +02:00
|
|
|
stellaris_init(machine, &stellaris_boards[0]);
|
2007-11-11 01:04:49 +01:00
|
|
|
}
|
|
|
|
|
2014-05-07 16:42:57 +02:00
|
|
|
static void lm3s6965evb_init(MachineState *machine)
|
2007-11-11 01:04:49 +01:00
|
|
|
{
|
2017-09-13 18:04:57 +02:00
|
|
|
stellaris_init(machine, &stellaris_boards[1]);
|
2007-11-11 01:04:49 +01:00
|
|
|
}
|
|
|
|
|
2015-09-19 10:49:44 +02:00
|
|
|
static void lm3s811evb_class_init(ObjectClass *oc, void *data)
|
2015-09-04 20:37:08 +02:00
|
|
|
{
|
2015-09-19 10:49:44 +02:00
|
|
|
MachineClass *mc = MACHINE_CLASS(oc);
|
|
|
|
|
2021-01-31 19:44:49 +01:00
|
|
|
mc->desc = "Stellaris LM3S811EVB (Cortex-M3)";
|
2015-09-04 20:37:08 +02:00
|
|
|
mc->init = lm3s811evb_init;
|
2017-09-07 14:54:54 +02:00
|
|
|
mc->ignore_memory_transaction_failures = true;
|
2017-09-13 18:04:57 +02:00
|
|
|
mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-m3");
|
2015-09-04 20:37:08 +02:00
|
|
|
}
|
2007-11-11 01:04:49 +01:00
|
|
|
|
2015-09-19 10:49:44 +02:00
|
|
|
static const TypeInfo lm3s811evb_type = {
|
|
|
|
.name = MACHINE_TYPE_NAME("lm3s811evb"),
|
|
|
|
.parent = TYPE_MACHINE,
|
|
|
|
.class_init = lm3s811evb_class_init,
|
|
|
|
};
|
2009-05-14 23:35:09 +02:00
|
|
|
|
2015-09-19 10:49:44 +02:00
|
|
|
static void lm3s6965evb_class_init(ObjectClass *oc, void *data)
|
2009-05-21 01:38:09 +02:00
|
|
|
{
|
2015-09-19 10:49:44 +02:00
|
|
|
MachineClass *mc = MACHINE_CLASS(oc);
|
|
|
|
|
2021-01-31 19:44:49 +01:00
|
|
|
mc->desc = "Stellaris LM3S6965EVB (Cortex-M3)";
|
2015-09-04 20:37:08 +02:00
|
|
|
mc->init = lm3s6965evb_init;
|
2017-09-07 14:54:54 +02:00
|
|
|
mc->ignore_memory_transaction_failures = true;
|
2017-09-13 18:04:57 +02:00
|
|
|
mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-m3");
|
2009-05-21 01:38:09 +02:00
|
|
|
}
|
|
|
|
|
2015-09-19 10:49:44 +02:00
|
|
|
static const TypeInfo lm3s6965evb_type = {
|
|
|
|
.name = MACHINE_TYPE_NAME("lm3s6965evb"),
|
|
|
|
.parent = TYPE_MACHINE,
|
|
|
|
.class_init = lm3s6965evb_class_init,
|
|
|
|
};
|
|
|
|
|
|
|
|
static void stellaris_machine_init(void)
|
|
|
|
{
|
|
|
|
type_register_static(&lm3s811evb_type);
|
|
|
|
type_register_static(&lm3s6965evb_type);
|
|
|
|
}
|
|
|
|
|
2016-02-16 21:59:04 +01:00
|
|
|
type_init(stellaris_machine_init)
|
2009-05-21 01:38:09 +02:00
|
|
|
|
2012-01-24 20:12:29 +01:00
|
|
|
static void stellaris_i2c_class_init(ObjectClass *klass, void *data)
|
|
|
|
{
|
2016-03-07 08:05:48 +01:00
|
|
|
DeviceClass *dc = DEVICE_CLASS(klass);
|
2012-01-24 20:12:29 +01:00
|
|
|
|
2016-03-07 08:05:48 +01:00
|
|
|
dc->vmsd = &vmstate_stellaris_i2c;
|
2012-01-24 20:12:29 +01:00
|
|
|
}
|
|
|
|
|
2013-01-10 16:19:07 +01:00
|
|
|
static const TypeInfo stellaris_i2c_info = {
|
2013-07-24 09:08:23 +02:00
|
|
|
.name = TYPE_STELLARIS_I2C,
|
2011-12-08 04:34:16 +01:00
|
|
|
.parent = TYPE_SYS_BUS_DEVICE,
|
|
|
|
.instance_size = sizeof(stellaris_i2c_state),
|
2016-03-07 08:05:48 +01:00
|
|
|
.instance_init = stellaris_i2c_init,
|
2011-12-08 04:34:16 +01:00
|
|
|
.class_init = stellaris_i2c_class_init,
|
2012-01-24 20:12:29 +01:00
|
|
|
};
|
|
|
|
|
|
|
|
static void stellaris_adc_class_init(ObjectClass *klass, void *data)
|
|
|
|
{
|
2016-03-07 08:05:48 +01:00
|
|
|
DeviceClass *dc = DEVICE_CLASS(klass);
|
2012-01-24 20:12:29 +01:00
|
|
|
|
2016-03-07 08:05:48 +01:00
|
|
|
dc->vmsd = &vmstate_stellaris_adc;
|
2012-01-24 20:12:29 +01:00
|
|
|
}
|
|
|
|
|
2013-01-10 16:19:07 +01:00
|
|
|
static const TypeInfo stellaris_adc_info = {
|
2013-07-24 09:13:06 +02:00
|
|
|
.name = TYPE_STELLARIS_ADC,
|
2011-12-08 04:34:16 +01:00
|
|
|
.parent = TYPE_SYS_BUS_DEVICE,
|
|
|
|
.instance_size = sizeof(stellaris_adc_state),
|
2016-03-07 08:05:48 +01:00
|
|
|
.instance_init = stellaris_adc_init,
|
2011-12-08 04:34:16 +01:00
|
|
|
.class_init = stellaris_adc_class_init,
|
2012-01-24 20:12:29 +01:00
|
|
|
};
|
|
|
|
|
2021-01-28 12:41:36 +01:00
|
|
|
static void stellaris_sys_class_init(ObjectClass *klass, void *data)
|
|
|
|
{
|
|
|
|
DeviceClass *dc = DEVICE_CLASS(klass);
|
|
|
|
ResettableClass *rc = RESETTABLE_CLASS(klass);
|
|
|
|
|
|
|
|
dc->vmsd = &vmstate_stellaris_sys;
|
|
|
|
rc->phases.enter = stellaris_sys_reset_enter;
|
|
|
|
rc->phases.hold = stellaris_sys_reset_hold;
|
|
|
|
rc->phases.exit = stellaris_sys_reset_exit;
|
|
|
|
device_class_set_props(dc, stellaris_sys_properties);
|
|
|
|
}
|
|
|
|
|
|
|
|
static const TypeInfo stellaris_sys_info = {
|
|
|
|
.name = TYPE_STELLARIS_SYS,
|
|
|
|
.parent = TYPE_SYS_BUS_DEVICE,
|
|
|
|
.instance_size = sizeof(ssys_state),
|
|
|
|
.instance_init = stellaris_sys_instance_init,
|
|
|
|
.class_init = stellaris_sys_class_init,
|
|
|
|
};
|
|
|
|
|
2012-02-09 15:20:55 +01:00
|
|
|
static void stellaris_register_types(void)
|
2009-05-14 23:35:09 +02:00
|
|
|
{
|
2011-12-08 04:34:16 +01:00
|
|
|
type_register_static(&stellaris_i2c_info);
|
|
|
|
type_register_static(&stellaris_adc_info);
|
2021-01-28 12:41:36 +01:00
|
|
|
type_register_static(&stellaris_sys_info);
|
2009-05-14 23:35:09 +02:00
|
|
|
}
|
|
|
|
|
2012-02-09 15:20:55 +01:00
|
|
|
type_init(stellaris_register_types)
|