Commit Graph

100148 Commits

Author SHA1 Message Date
Fabiano Rosas cdfea280b3 target/arm: Remove unused includes from helper.c
Signed-off-by: Fabiano Rosas <farosas@suse.de>
Reviewed-by: Claudio Fontana <cfontana@suse.de>
Reviewed-by: Cornelia Huck <cohuck@redhat.com>
Message-id: 20221213190537.511-6-farosas@suse.de
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2023-01-05 12:28:37 +00:00
Fabiano Rosas c6675a857c target/arm: Remove unused includes from m_helper.c
Signed-off-by: Fabiano Rosas <farosas@suse.de>
Reviewed-by: Claudio Fontana <cfontana@suse.de>
Reviewed-by: Cornelia Huck <cohuck@redhat.com>
Message-id: 20221213190537.511-5-farosas@suse.de
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2023-01-05 12:28:37 +00:00
Fabiano Rosas f927dbda86 target/arm: Fix checkpatch brace errors in helper.c
Fix this:
ERROR: braces {} are necessary for all arms of this statement

Signed-off-by: Fabiano Rosas <farosas@suse.de>
Reviewed-by: Claudio Fontana <cfontana@suse.de>
Reviewed-by: Cornelia Huck <cohuck@redhat.com>
Message-id: 20221213190537.511-4-farosas@suse.de
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2023-01-05 12:28:37 +00:00
Fabiano Rosas 04215eb100 target/arm: Fix checkpatch space errors in helper.c
Fix the following:

ERROR: spaces required around that '|' (ctx:VxV)
ERROR: space required before the open parenthesis '('
ERROR: spaces required around that '+' (ctx:VxB)
ERROR: space prohibited between function name and open parenthesis '('

(the last two still have some occurrences in macros which I left
behind because it might impact readability)

Signed-off-by: Fabiano Rosas <farosas@suse.de>
Reviewed-by: Claudio Fontana <cfontana@suse.de>
Reviewed-by: Cornelia Huck <cohuck@redhat.com>
Message-id: 20221213190537.511-3-farosas@suse.de
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2023-01-05 12:28:37 +00:00
Fabiano Rosas 9b37a28c78 target/arm: Fix checkpatch comment style warnings in helper.c
Fix these:

WARNING: Block comments use a leading /* on a separate line
WARNING: Block comments use * on subsequent lines
WARNING: Block comments use a trailing */ on a separate line

Signed-off-by: Fabiano Rosas <farosas@suse.de>
Reviewed-by: Claudio Fontana <cfontana@suse.de>
Reviewed-by: Cornelia Huck <cohuck@redhat.com>
Message-id: 20221213190537.511-2-farosas@suse.de
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2023-01-05 12:28:36 +00:00
Axel Heider 8d71beaf1e hw/timer/imx_epit: fix compare timer handling
- fix #1263 for CR writes
- rework compare time handling
  - The compare timer has to run even if CR.OCIEN is not set,
    as SR.OCIF must be updated.
  - The compare timer fires exactly once when the
    compare value is less than the current value, but the
    reload values is less than the compare value.
  - The compare timer will never fire if the reload value is
    less than the compare value. Disable it in this case.

Signed-off-by: Axel Heider <axel.heider@hensoldt.net>
[PMM: fixed minor style nits]
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2023-01-05 12:14:43 +00:00
Axel Heider e662449aa6 hw/timer/imx_epit: remove explicit fields cnt and freq
The CNT register is a read-only register. There is no need to
store it's value, it can be calculated on demand.
The calculated frequency is needed temporarily only.

Note that this is a migration compatibility break for all boards
types that use the EPIT peripheral.

Signed-off-by: Axel Heider <axel.heider@hensoldt.net>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2023-01-05 12:14:43 +00:00
Axel Heider 793a6ea075 hw/timer/imx_epit: factor out register write handlers
Signed-off-by: Axel Heider <axel.heider@hensoldt.net>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2023-01-05 12:14:43 +00:00
Axel Heider 3d46158125 hw/timer/imx_epit: hard reset initializes CR with 0
Signed-off-by: Axel Heider <axel.heider@hensoldt.net>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2023-01-05 12:14:43 +00:00
Axel Heider 2ca267fd36 hw/timer/imx_epit: update interrupt state on CR write access
The interrupt state can change due to:
- reset clears both SR.OCIF and CR.OCIE
- write to CR.EN or CR.OCIE

Signed-off-by: Axel Heider <axel.heider@hensoldt.net>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2023-01-05 12:14:43 +00:00
Axel Heider 1ead962edf hw/timer/imx_epit: define SR_OCIF
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2023-01-05 12:14:43 +00:00
Axel Heider 018ee7948f hw/timer/imx_epit: cleanup CR defines
remove unused defines, add needed defines

Signed-off-by: Axel Heider <axel.heider@hensoldt.net>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2023-01-05 12:14:43 +00:00
Axel Heider b9c993aaf8 hw/timer/imx_epit: improve comments
Fix typos, add background information

Signed-off-by: Axel Heider <axel.heider@hensoldt.net>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2023-01-05 12:14:43 +00:00
Alex Bennée 9788d4c007 target/arm: fix handling of HLT semihosting in system mode
The check semihosting_enabled() wants to know if the guest is
currently in user mode. Unlike the other cases the test was inverted
causing us to block semihosting calls in non-EL0 modes.

Cc: qemu-stable@nongnu.org
Fixes: 19b26317e9 (target/arm: Honour -semihosting-config userspace=on)
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2023-01-05 11:53:14 +00:00
Tobias Röhmel 5f536d01d1 target/arm: Add ARM Cortex-R52 CPU
All constants are taken from the ARM Cortex-R52 Processor TRM Revision: r1p3

Signed-off-by: Tobias Röhmel <tobias.roehmel@rwth-aachen.de>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20221206102504.165775-8-tobias.roehmel@rwth-aachen.de
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2023-01-05 11:51:09 +00:00
Tobias Röhmel fca45e3467 target/arm: Add PMSAv8r functionality
Add PMSAv8r translation.

Signed-off-by: Tobias Röhmel <tobias.roehmel@rwth-aachen.de>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20221206102504.165775-7-tobias.roehmel@rwth-aachen.de
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2023-01-05 11:51:09 +00:00
Tobias Röhmel 761c46425e target/arm: Add PMSAv8r registers
Signed-off-by: Tobias Röhmel <tobias.roehmel@rwth-aachen.de>
Message-id: 20221206102504.165775-6-tobias.roehmel@rwth-aachen.de
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2023-01-05 11:51:09 +00:00
Tobias Röhmel 452c67a427 target/arm: Enable TTBCR_EAE for ARMv8-R AArch32
ARMv8-R AArch32 CPUs behave as if TTBCR.EAE is always 1 even
tough they don't have the TTBCR register.
See ARM Architecture Reference Manual Supplement - ARMv8, for the ARMv8-R
AArch32 architecture profile Version:A.c section C1.2.

Signed-off-by: Tobias Röhmel <tobias.roehmel@rwth-aachen.de>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20221206102504.165775-5-tobias.roehmel@rwth-aachen.de
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2023-01-05 11:51:09 +00:00
Tobias Röhmel faa1451e7b target/arm: Make stage_2_format for cache attributes optional
The v8R PMSAv8 has a two-stage MPU translation process, but, unlike
VMSAv8, the stage 2 attributes are in the same format as the stage 1
attributes (8-bit MAIR format). Rather than converting the MAIR
format to the format used for VMSA stage 2 (bits [5:2] of a VMSA
stage 2 descriptor) and then converting back to do the attribute
combination, allow combined_attrs_nofwb() to accept s2 attributes
that are already in the MAIR format.

We move the assert() to combined_attrs_fwb(), because that function
really does require a VMSA stage 2 attribute format. (We will never
get there for v8R, because PMSAv8 does not implement FEAT_S2FWB.)

Signed-off-by: Tobias Röhmel <tobias.roehmel@rwth-aachen.de>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20221206102504.165775-4-tobias.roehmel@rwth-aachen.de
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2023-01-05 11:51:09 +00:00
Tobias Röhmel 910e4f2497 target/arm: Make RVBAR available for all ARMv8 CPUs
RVBAR shadows RVBAR_ELx where x is the highest exception
level if the highest EL is not EL3. This patch also allows
ARMv8 CPUs to change the reset address with
the rvbar property.

Signed-off-by: Tobias Röhmel <tobias.roehmel@rwth-aachen.de>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20221206102504.165775-3-tobias.roehmel@rwth-aachen.de
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2023-01-05 11:51:09 +00:00
Tobias Röhmel c7f786abe2 target/arm: Don't add all MIDR aliases for cores that implement PMSA
Cores with PMSA have the MPUIR register which has the
same encoding as the MIDR alias with opc2=4. So we only
add that alias if we are not realizing a core that
implements PMSA.

Signed-off-by: Tobias Röhmel <tobias.roehmel@rwth-aachen.de>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20221206102504.165775-2-tobias.roehmel@rwth-aachen.de
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2023-01-05 11:51:09 +00:00
Peter Maydell 9e65f4e6da target/arm:Set lg_page_size to 0 if either S1 or S2 asks for it
In get_phys_addr_twostage() we set the lg_page_size of the result to
the maximum of the stage 1 and stage 2 page sizes.  This works for
the case where we do want to create a TLB entry, because we know the
common TLB code only creates entries of the TARGET_PAGE_SIZE and
asking for a size larger than that only means that invalidations
invalidate the whole larger area.  However, if lg_page_size is
smaller than TARGET_PAGE_SIZE this effectively means "don't create a
TLB entry"; in this case if either S1 or S2 said "this covers less
than a page and can't go in a TLB" then the final result also should
be marked that way.  Set the resulting page size to 0 if either
stage asked for a less-than-a-page entry, and expand the comment
to explain what's going on.

This has no effect for VMSA because currently the VMSA lookup always
returns results that cover at least TARGET_PAGE_SIZE; however when we
add v8R support it will reuse this code path, and for v8R the S1 and
S2 results can be smaller than TARGET_PAGE_SIZE.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20221212142708.610090-1-peter.maydell@linaro.org
2023-01-05 11:51:09 +00:00
Thomas Huth cb9c6a8e5a .gitlab-ci.d/windows: Work-around timeout and OpenGL problems of the MSYS2 jobs
The windows jobs (especially the 32-bit job) recently started to
hit the timeout limit. Bump it a little bit to ease the situation
(80 minutes is quite long already - OTOH, these jobs do not have to
wait for a job from the container stage to finish, so this should
still be OK).

Additionally, some update on the container side recently enabled
OpenGL in these jobs - but the corresponding code fails to compile.
Thus disable OpenGL here for the time being until someone figured
out the proper fix in the shader code for this.

Signed-off-by: Thomas Huth <thuth@redhat.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Marc-André Lureau <marcandre.lureau@redhat.com>
Message-id: 20230104123559.277586-1-thuth@redhat.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2023-01-04 18:58:33 +00:00
Peter Maydell 9804dcd271 testing updates:
- fix minor shell-ism that can break check-tcg
   - turn off verbose logging on custom runners
   - make configure echo call in CI
   - fix unused variable in linux-test
   - add binary compiler docker image for hexagon
   - disable doc and gui builds for tci and disable-tcg builds
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Merge tag 'pull-testing-next-231222-1' of https://gitlab.com/stsquad/qemu into staging

testing updates:

  - fix minor shell-ism that can break check-tcg
  - turn off verbose logging on custom runners
  - make configure echo call in CI
  - fix unused variable in linux-test
  - add binary compiler docker image for hexagon
  - disable doc and gui builds for tci and disable-tcg builds

# gpg: Signature made Fri 23 Dec 2022 15:18:41 GMT
# gpg:                using RSA key 6685AE99E75167BCAFC8DF35FBD0DB095A9E2A44
# gpg: Good signature from "Alex Bennée (Master Work Key) <alex.bennee@linaro.org>" [full]
# Primary key fingerprint: 6685 AE99 E751 67BC AFC8  DF35 FBD0 DB09 5A9E 2A44

* tag 'pull-testing-next-231222-1' of https://gitlab.com/stsquad/qemu:
  gitlab-ci: Disable docs and GUIs for the build-tci and build-tcg-disabled jobs
  tests/docker: use prebuilt toolchain for debian-hexagon-cross
  tests/tcg: fix unused variable in linux-test
  configure: repeat ourselves for the benefit of CI
  gitlab: turn off verbose logging for make check on custom runners
  configure: Fix check-tcg not executing any tests

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2023-01-04 16:47:37 +00:00
Peter Maydell ecc9a58835 9pfs: Windows host prep, cleanup
* Next preparatory patches for upcoming Windows host support.
 
 * Cleanup patches.
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Merge tag 'pull-9p-20221223' of https://github.com/cschoenebeck/qemu into staging

9pfs: Windows host prep, cleanup

* Next preparatory patches for upcoming Windows host support.

* Cleanup patches.

# gpg: Signature made Fri 23 Dec 2022 11:04:26 GMT
# gpg:                using RSA key 96D8D110CF7AF8084F88590134C2B58765A47395
# gpg:                issuer "qemu_oss@crudebyte.com"
# gpg: Good signature from "Christian Schoenebeck <qemu_oss@crudebyte.com>" [unknown]
# gpg: WARNING: This key is not certified with a trusted signature!
# gpg:          There is no indication that the signature belongs to the owner.
# Primary key fingerprint: ECAB 1A45 4014 1413 BA38  4926 30DB 47C3 A012 D5F4
#      Subkey fingerprint: 96D8 D110 CF7A F808 4F88  5901 34C2 B587 65A4 7395

* tag 'pull-9p-20221223' of https://github.com/cschoenebeck/qemu:
  hw/9pfs: Replace the direct call to xxxat() APIs with a wrapper
  hw/9pfs: Drop unnecessary *xattr wrapper API declarations
  qemu/xattr.h: Exclude <sys/xattr.h> for Windows
  MAINTAINERS: Add 9p test client to section "virtio-9p"
  9pfs: Fix some return statements in the synth backend

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2023-01-04 14:53:59 +00:00
Thomas Huth 3b4f911921 gitlab-ci: Disable docs and GUIs for the build-tci and build-tcg-disabled jobs
These jobs use their own "script:" section and thus do not profit from
the global "--disable-docs" from the template. While we're at it, disable
also some GUI front ends here since we do not gain any additional test
coverage by compiling those here again.

Signed-off-by: Thomas Huth <thuth@redhat.com>
Message-Id: <20221208135945.99975-1-thuth@redhat.com>
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-Id: <20221221090411.1995037-7-alex.bennee@linaro.org>
2022-12-23 15:17:13 +00:00
Mukilan Thiyagarajan b9052d3634 tests/docker: use prebuilt toolchain for debian-hexagon-cross
The current docker image for cross compiling hexagon guests
is manually built since it takes >2 hours to build from source.

This patch:
 1. Solves the above issue by using the prebuilt clang
    toolchain hosted on CodeLinaro [1] and maintained by QUIC [2].
 2. The dockerfile is also switched from multi-stage to single stage
    build to allow the CI docker engine to reuse the layer cache.
 3. Re-enables the hexagon-cross-container job to be always run in
    CI and makes it a non-optional dependency for the
    build-user-hexagon job.

The changes for 1 & 2 together bring down the build time to
~3 minutes in GitLab CI when cache is reused and ~9 minutes
when cache cannot be reused.

[1]: https://github.com/CodeLinaro/hexagon-builder
[2]: https://github.com/quic/toolchain_for_hexagon/releases/

Signed-off-by: Mukilan Thiyagarajan <quic_mthiyaga@quicinc.com>
[AJB: also tweak MAINTAINERS, remove QEMU_JOB_ONLY_FORKS and comment]
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Message-Id: <20221219144354.11659-1-quic_mthiyaga@quicinc.com>
Message-Id: <20221221090411.1995037-6-alex.bennee@linaro.org>
2022-12-23 15:16:31 +00:00
Alex Bennée 2bc6c79417 tests/tcg: fix unused variable in linux-test
The latest hexagon compiler picks up that we never consume wcount.
Given the name of the #define that rcount checks against is WCOUNT_MAX
I figured the check just got missed.

Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-Id: <20221221090411.1995037-5-alex.bennee@linaro.org>
2022-12-23 15:15:57 +00:00
Alex Bennée 7f78877945 configure: repeat ourselves for the benefit of CI
Our CI system echos the lines it executes but not the expansions. For
the sake of a line of extra verbosity during the configure phase lets
echo the invocation of script to stdout as well as the log when on CI.

Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-Id: <20221221090411.1995037-4-alex.bennee@linaro.org>
2022-12-23 15:15:57 +00:00
Alex Bennée fb83fd3b84 gitlab: turn off verbose logging for make check on custom runners
The verbosity adds a lot of unnecessary output to the CI logs which
end up getting truncated anyway. We can always extract information
from the meson test logs on a failure and for the custom runners its
generally easier to re-create failures anyway.

Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Thomas Huth <thuth@redhat.com>
Message-Id: <20221221090411.1995037-3-alex.bennee@linaro.org>
2022-12-23 15:15:57 +00:00
Mukilan Thiyagarajan 73acb87be5 configure: Fix check-tcg not executing any tests
After configuring with --target-list=hexagon-linux-user
running `make check-tcg` just prints the following:

```
make: Nothing to be done for 'check-tcg'
```

In the probe_target_compiler function, the 'break'
command is used incorrectly. There are no lexically
enclosing loops associated with that break command which
is an unspecfied behaviour in the POSIX standard.

The dash shell implementation aborts the currently executing
loop, in this case, causing the rest of the logic for the loop
in line 2490 to be skipped, which means no Makefiles are
generated for the tcg target tests.

Fixes: c3b570b5a9 (configure: don't enable
cross compilers unless in target_list)

Signed-off-by: Mukilan Thiyagarajan <quic_mthiyaga@quicinc.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Link: https://patchew.org/QEMU/20221207082309.9966-1-quic._5Fmthiyaga@quicinc.com/
Message-Id: <20221207082309.9966-1-quic_mthiyaga@quicinc.com>
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Message-Id: <20221221090411.1995037-2-alex.bennee@linaro.org>
2022-12-23 15:15:57 +00:00
Bin Meng 6ca60cd7a3 hw/9pfs: Replace the direct call to xxxat() APIs with a wrapper
xxxat() APIs are only available on POSIX platforms. For future
extension to Windows, let's replace the direct call to xxxat()
APIs with a wrapper.

Signed-off-by: Bin Meng <bin.meng@windriver.com>
Message-Id: <20221219102022.2167736-4-bin.meng@windriver.com>
Signed-off-by: Christian Schoenebeck <qemu_oss@crudebyte.com>
2022-12-23 11:48:13 +01:00
Bin Meng 09f0080ecd hw/9pfs: Drop unnecessary *xattr wrapper API declarations
These are not used anywhere in the source tree. Drop them.

Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Greg Kurz <groug@kaod.org>
Message-Id: <20221219102022.2167736-3-bin.meng@windriver.com>
Signed-off-by: Christian Schoenebeck <qemu_oss@crudebyte.com>
2022-12-23 11:48:13 +01:00
Bin Meng 6888af46c7 qemu/xattr.h: Exclude <sys/xattr.h> for Windows
Windows does not have <sys/xattr.h>.

Signed-off-by: Bin Meng <bin.meng@windriver.com>
Message-Id: <20221219102022.2167736-2-bin.meng@windriver.com>
Signed-off-by: Christian Schoenebeck <qemu_oss@crudebyte.com>
2022-12-23 11:48:13 +01:00
Christian Schoenebeck 818e42fe2f MAINTAINERS: Add 9p test client to section "virtio-9p"
The 9p test cases use a dedicated, lite-weight 9p client implementation
(using virtio transport) under tests/qtest/libqos/ to communicate with
QEMU's 9p server.

It's already there for a long time. Let's officially assign it to 9p
maintainers.

Signed-off-by: Christian Schoenebeck <qemu_oss@crudebyte.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Greg Kurz <groug@kaod.org>
Reviewed-by: Wilfred Mallawa <wilfred.mallawa@wdc.com>
Message-Id: <E1ozhlV-0007BU-0g@lizzy.crudebyte.com>
2022-12-23 11:48:13 +01:00
Greg Kurz ab04d2c557 9pfs: Fix some return statements in the synth backend
The qemu_v9fs_synth_mkdir() and qemu_v9fs_synth_add_file() functions
currently return a positive errno value on failure. This causes
checkpatch.pl to spit several errors like the one below:

ERROR: return of an errno should typically be -ve (return -EAGAIN)
+        return EAGAIN;

Simply change the sign. This has no consequence since callers
assert() the returned value to be equal to 0.

Reported-by: Markus Armbruster <armbru@redhat.com>
Signed-off-by: Greg Kurz <groug@kaod.org>
Message-Id: <166930551818.827792.10663674346122681963.stgit@bahia>
[C.S.: - Resolve conflict with 66997c42e0. ]
Signed-off-by: Christian Schoenebeck <qemu_oss@crudebyte.com>
2022-12-23 11:48:13 +01:00
Peter Maydell 222059a0fc ppc patch queue for 2022-12-21:
This queue contains a MAINTAINERS update, the implementation of the Freescale eSDHC,
 the introduction of the DEXCR/HDEXCR instructions and other assorted fixes (most of
 them for the e500 board).
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Merge tag 'pull-ppc-20221221' of https://gitlab.com/danielhb/qemu into staging

ppc patch queue for 2022-12-21:

This queue contains a MAINTAINERS update, the implementation of the Freescale eSDHC,
the introduction of the DEXCR/HDEXCR instructions and other assorted fixes (most of
them for the e500 board).

# gpg: Signature made Wed 21 Dec 2022 17:18:53 GMT
# gpg:                using EDDSA key 17EBFF9923D01800AF2838193CD9CA96DE033164
# gpg:                issuer "danielhb413@gmail.com"
# gpg: Good signature from "Daniel Henrique Barboza <danielhb413@gmail.com>" [unknown]
# gpg: WARNING: This key is not certified with a trusted signature!
# gpg:          There is no indication that the signature belongs to the owner.
# Primary key fingerprint: 17EB FF99 23D0 1800 AF28  3819 3CD9 CA96 DE03 3164

* tag 'pull-ppc-20221221' of https://gitlab.com/danielhb/qemu:
  target/ppc: Check DEXCR on hash{st, chk} instructions
  target/ppc: Implement the DEXCR and HDEXCR
  hw/ppc/e500: Move comment to more appropriate place
  hw/ppc/e500: Resolve variable shadowing
  hw/ppc/e500: Prefer local variable over qdev_get_machine()
  hw/ppc/virtex_ml507: Prefer local over global variable
  target/ppc/mmu_common: Fix table layout of "info tlb" HMP command
  target/ppc/mmu_common: Log which effective address had no TLB entry found
  hw/ppc/spapr: Reduce "vof.h" inclusion
  hw/ppc/vof: Do not include the full "cpu.h"
  target/ppc/kvm: Add missing "cpu.h" and "exec/hwaddr.h"
  hw/ppc/e500: Add Freescale eSDHC to e500plat
  hw/sd/sdhci: Support big endian SD host controller interfaces
  MAINTAINERS: downgrade PPC KVM/TCG CPUs and pSeries to 'Odd Fixes'

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2022-12-21 18:08:09 +00:00
Nicholas Miehlbradt 4091fabfeb target/ppc: Check DEXCR on hash{st, chk} instructions
Adds checks to the hashst and hashchk instructions to only execute if
enabled by the relevant aspect in the DEXCR and HDEXCR.

This behaviour is guarded behind TARGET_PPC64 since Power10 is
currently the only implementation which has the DEXCR.

Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Signed-off-by: Nicholas Miehlbradt <nicholas@linux.ibm.com>
Message-Id: <20221220042330.2387944-3-nicholas@linux.ibm.com>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
2022-12-21 14:17:55 -03:00
Nicholas Miehlbradt 395b5d5b45 target/ppc: Implement the DEXCR and HDEXCR
Define the DEXCR and HDEXCR as special purpose registers.

Each register occupies two SPR indicies, one which can be read in an
unprivileged state and one which can be modified in the appropriate
priviliged state, however both indicies refer to the same underlying
value.

Note that the ISA uses the abbreviation UDEXCR in two different
contexts: the userspace DEXCR, the SPR index which can be read from
userspace (implemented in this patch), and the ultravisor DEXCR, the
equivalent register for the ultravisor state (not implemented).

Signed-off-by: Nicholas Miehlbradt <nicholas@linux.ibm.com>
Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Message-Id: <20221220042330.2387944-2-nicholas@linux.ibm.com>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
2022-12-21 14:17:55 -03:00
Bernhard Beschow 320c5ad8ff hw/ppc/e500: Move comment to more appropriate place
The TLB entries are set up in mmubooke_create_initial_mapping(), not in
booke206_page_size_to_tlb().

Signed-off-by: Bernhard Beschow <shentey@gmail.com>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20221216145709.271940-7-shentey@gmail.com>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
2022-12-21 14:17:55 -03:00
Bernhard Beschow a80fc80eda hw/ppc/e500: Resolve variable shadowing
Assign to the outer variable instead which even saves some code.

Signed-off-by: Bernhard Beschow <shentey@gmail.com>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20221216145709.271940-6-shentey@gmail.com>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
2022-12-21 14:17:55 -03:00
Bernhard Beschow 1a3e6528ac hw/ppc/e500: Prefer local variable over qdev_get_machine()
Signed-off-by: Bernhard Beschow <shentey@gmail.com>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-Id: <20221216145709.271940-5-shentey@gmail.com>
[danielhb: remove linebreak in object_property_add_child()]
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
2022-12-21 14:17:55 -03:00
Bernhard Beschow 712622385b hw/ppc/virtex_ml507: Prefer local over global variable
Signed-off-by: Bernhard Beschow <shentey@gmail.com>
Reviewed-by: Edgar E. Iglesias <edgar@zeroasic.com>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-Id: <20221216145709.271940-4-shentey@gmail.com>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
2022-12-21 14:17:55 -03:00
Bernhard Beschow 2479abef09 target/ppc/mmu_common: Fix table layout of "info tlb" HMP command
Starting with the URWX columns the columns didn't line up.
Before:

  QEMU 7.2.50 monitor - type 'help' for more information
  (qemu) info tlb

  TLB0:
  Effective          Physical           Size TID   TS SRWX URWX WIMGE U0123
  0x0000000000a80000 0x000000000105d000   4K 117   0  SR--UR-- --M-- U----
  0x0000000000100000 0x000000000114e000   4K 117   0  SR--UR-- --M-- U----
  <snip

  TLB1:
  Effective          Physical           Size TID   TS SRWX URWX WIMGE U0123
  0x00000000c0000000 0x0000000000000000  16M 0     0  SR-XU--- --M-- U----
  0x00000000c1000000 0x0000000001000000  16M 0     0  SRW-U--- --M-- U----
  <snip>
  (qemu)

After:

  QEMU 7.2.50 monitor - type 'help' for more information
  (qemu) info tlb

  TLB0:
  Effective          Physical           Size TID   TS SRWX URWX WIMGE U0123
  0x00000000b7a00000 0x000000000fcf5000   4K 18    0  SR-- UR-- --M-- U----
  0x0000000000800000 0x000000000fd73000   4K 18    0  SR-- UR-X --M-- U----
  <snip>

  TLB1:
  Effective          Physical           Size TID   TS SRWX URWX WIMGE U0123
  0x00000000c0000000 0x0000000000000000  16M 0     0  SR-X U--- --M-- U----
  0x00000000c1000000 0x0000000001000000  16M 0     0  SRW- U--- --M-- U----
  <snip>
  (qemu)

Signed-off-by: Bernhard Beschow <shentey@gmail.com>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-Id: <20221216145709.271940-3-shentey@gmail.com>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
2022-12-21 14:17:55 -03:00
Bernhard Beschow e4cadfbe3c target/ppc/mmu_common: Log which effective address had no TLB entry found
Let's not leave developers in the dark where this log message comes
from.

Signed-off-by: Bernhard Beschow <shentey@gmail.com>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-Id: <20221216145709.271940-2-shentey@gmail.com>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
2022-12-21 14:17:55 -03:00
Philippe Mathieu-Daudé 46d80a56a1 hw/ppc/spapr: Reduce "vof.h" inclusion
Currently objects including "hw/ppc/spapr.h" are forced to be
target specific due to the inclusion of "vof.h" in "spapr.h".

"spapr.h" only uses a Vof pointer, so doesn't require the structure
declaration. The only place where Vof structure is accessed is in
spapr.c, so include "vof.h" there, and forward declare the structure
in "spapr.h".

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Message-Id: <20221213123550.39302-4-philmd@linaro.org>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
2022-12-21 14:17:55 -03:00
Philippe Mathieu-Daudé 31b55f5bda hw/ppc/vof: Do not include the full "cpu.h"
"vof.h" doesn't need the full "cpu.h" to get the target_ulong
definition, including "exec/cpu-defs.h" is enough.

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Message-Id: <20221213123550.39302-3-philmd@linaro.org>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
2022-12-21 14:17:55 -03:00
Philippe Mathieu-Daudé 308fd18142 target/ppc/kvm: Add missing "cpu.h" and "exec/hwaddr.h"
kvm_ppc.h is missing various declarations from "cpu.h":

  target/ppc/kvm_ppc.h:128:40: error: unknown type name 'CPUPPCState'; did you mean 'CPUState'?
  static inline int kvmppc_get_hypercall(CPUPPCState *env,
                                         ^~~~~~~~~~~
                                         CPUState
  include/qemu/typedefs.h:45:25: note: 'CPUState' declared here
  typedef struct CPUState CPUState;
                          ^
  target/ppc/kvm_ppc.h:134:40: error: unknown type name 'PowerPCCPU'
  static inline int kvmppc_set_interrupt(PowerPCCPU *cpu, int irq, int level)
                                         ^
  target/ppc/kvm_ppc.h:285:38: error: unknown type name 'hwaddr'
                                       hwaddr ptex, int n)
                                       ^
  target/ppc/kvm_ppc.h:220:15: error: unknown type name 'target_ulong'
  static inline target_ulong kvmppc_configure_v3_mmu(PowerPCCPU *cpu,
                ^
  target/ppc/kvm_ppc.h:286:38: error: unknown type name 'ppc_hash_pte64_t'
  static inline void kvmppc_read_hptes(ppc_hash_pte64_t *hptes,
                                       ^

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Message-Id: <20221213123550.39302-2-philmd@linaro.org>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
2022-12-21 14:17:55 -03:00
Philippe Mathieu-Daudé 3f288c4b2f hw/ppc/e500: Add Freescale eSDHC to e500plat
Adds missing functionality to e500plat machine which increases the
chance of given "real" firmware images to access SD cards.

Signed-off-by: Bernhard Beschow <shentey@gmail.com>
Message-Id: <20221018210146.193159-8-shentey@gmail.com>
[PMD: Simplify using create_unimplemented_device("esdhc")]
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Tested-by: Bernhard Beschow <shentey@gmail.com>
Reviewed-by: Bernhard Beschow <shentey@gmail.com>
Message-Id: <20221101222934.52444-4-philmd@linaro.org>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
2022-12-21 14:17:55 -03:00
Philippe Mathieu-Daudé c0a55a0c9d hw/sd/sdhci: Support big endian SD host controller interfaces
Some SDHCI IP can be synthetized in various endianness:
https://github.com/u-boot/u-boot/blob/v2021.04/doc/README.fsl-esdhc

 - CONFIG_SYS_FSL_ESDHC_BE

   ESDHC IP is in big-endian mode. Accessing ESDHC registers can be
   determined by ESDHC IP's endian mode or processor's endian mode.

Our current implementation is little-endian. In order to support
big endianness:

- Rename current MemoryRegionOps as sdhci_mmio_le_ops ('le')
- Add an 'endianness' property to SDHCIState (default little endian)
- Set the 'io_ops' field in realize() after checking the property
- Add the sdhci_mmio_be_ops (big-endian) MemoryRegionOps.

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Tested-by: Bernhard Beschow <shentey@gmail.com>
Reviewed-by: Bernhard Beschow <shentey@gmail.com>
Message-Id: <20221101222934.52444-3-philmd@linaro.org>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
2022-12-21 14:17:55 -03:00