1999-05-03 09:29:11 +02:00
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/* tc-mips.c -- assemble code for a MIPS chip.
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2004-01-09 03:16:30 +01:00
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Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002,
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2003, 2004 Free Software Foundation, Inc.
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1999-05-03 09:29:11 +02:00
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Contributed by the OSF and Ralph Campbell.
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Written by Keith Knowles and Ralph Campbell, working independently.
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Modified for ECOFF and R4000 support by Ian Lance Taylor of Cygnus
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Support.
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This file is part of GAS.
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GAS is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 2, or (at your option)
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any later version.
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GAS is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with GAS; see the file COPYING. If not, write to the Free
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Software Foundation, 59 Temple Place - Suite 330, Boston, MA
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02111-1307, USA. */
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#include "as.h"
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#include "config.h"
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#include "subsegs.h"
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2001-09-19 07:33:36 +02:00
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#include "safe-ctype.h"
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1999-05-03 09:29:11 +02:00
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#include <stdarg.h>
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#include "opcode/mips.h"
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#include "itbl-ops.h"
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2002-06-08 07:37:29 +02:00
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#include "dwarf2dbg.h"
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1999-05-03 09:29:11 +02:00
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#ifdef DEBUG
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#define DBG(x) printf x
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#else
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#define DBG(x)
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#endif
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#ifdef OBJ_MAYBE_ELF
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/* Clean up namespace so we can include obj-elf.h too. */
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2003-06-30 14:44:25 +02:00
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static int mips_output_flavor (void);
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static int mips_output_flavor (void) { return OUTPUT_FLAVOR; }
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1999-05-03 09:29:11 +02:00
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#undef OBJ_PROCESS_STAB
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#undef OUTPUT_FLAVOR
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#undef S_GET_ALIGN
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#undef S_GET_SIZE
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#undef S_SET_ALIGN
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#undef S_SET_SIZE
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#undef obj_frob_file
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#undef obj_frob_file_after_relocs
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#undef obj_frob_symbol
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#undef obj_pop_insert
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#undef obj_sec_sym_ok_for_reloc
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#undef OBJ_COPY_SYMBOL_ATTRIBUTES
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#include "obj-elf.h"
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/* Fix any of them that we actually care about. */
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#undef OUTPUT_FLAVOR
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#define OUTPUT_FLAVOR mips_output_flavor()
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#endif
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#if defined (OBJ_ELF)
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#include "elf/mips.h"
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#endif
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#ifndef ECOFF_DEBUGGING
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#define NO_ECOFF_DEBUGGING
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#define ECOFF_DEBUGGING 0
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#endif
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2002-06-14 16:08:54 +02:00
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int mips_flag_mdebug = -1;
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2003-07-28 22:06:27 +02:00
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/* Control generation of .pdr sections. Off by default on IRIX: the native
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linker doesn't know about and discards them, but relocations against them
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remain, leading to rld crashes. */
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#ifdef TE_IRIX
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int mips_flag_pdr = FALSE;
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#else
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int mips_flag_pdr = TRUE;
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#endif
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1999-05-03 09:29:11 +02:00
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#include "ecoff.h"
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#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
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static char *mips_regmask_frag;
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#endif
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2002-06-08 00:54:47 +02:00
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#define ZERO 0
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1999-05-03 09:29:11 +02:00
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#define AT 1
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#define TREG 24
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#define PIC_CALL_REG 25
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#define KT0 26
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#define KT1 27
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#define GP 28
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#define SP 29
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#define FP 30
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#define RA 31
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#define ILLEGAL_REG (32)
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/* Allow override of standard little-endian ECOFF format. */
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#ifndef ECOFF_LITTLE_FORMAT
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#define ECOFF_LITTLE_FORMAT "ecoff-littlemips"
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#endif
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extern int target_big_endian;
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/* The name of the readonly data section. */
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#define RDATA_SECTION_NAME (OUTPUT_FLAVOR == bfd_target_aout_flavour \
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? ".data" \
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: OUTPUT_FLAVOR == bfd_target_ecoff_flavour \
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? ".rdata" \
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2000-02-24 20:49:18 +01:00
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: OUTPUT_FLAVOR == bfd_target_coff_flavour \
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? ".rdata" \
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1999-05-03 09:29:11 +02:00
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: OUTPUT_FLAVOR == bfd_target_elf_flavour \
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? ".rodata" \
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: (abort (), ""))
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2001-11-12 17:54:54 +01:00
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/* The ABI to use. */
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enum mips_abi_level
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{
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NO_ABI = 0,
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O32_ABI,
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O64_ABI,
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N32_ABI,
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N64_ABI,
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EABI_ABI
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};
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/* MIPS ABI we are using for this output file. */
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[gas/]
* doc/c-mips.texi: Remove -mcpu. Document -mabi.
* configure.in (MIPS_CPU_STRING_DEFAULT): New configuration macro.
(USE_E_MIPS_ABI_O32, MIPS_DEFAULT_64BIT): New configuration macros.
* configure, config.in: Regenerate.
* config/tc-mips.c (file_mips_abi): Rename to mips_abi.
(mips_set_options): Remove "abi" field.
(mips_opts): Update accordingly. Replace all uses of mips_opts.abi
with mips_abi.
(mips_cpu): Remove.
(mips_arch_string, mips_arch_info): New vars.
(mips_tune_string, mips_tune_info): New vars.
(ABI_NEEDS_32BIT_REGS, ABI_NEEDS_64BIT_REGS): New macros.
(HAVE_32BIT_GPRS, HAVE_32BIT_FPRS): Don't check the ABI.
(mips_isa_to_str, mips_cpu_to_str): Remove.
(mips_ip): If the selected architecture is a generic ISA rather
than a processor, only mention the ISA level in error messages.
(OPTION_MCPU): Remove.
(OPTION_FP64): New.
(md_longopts): Add -mfp64, remove -mcpu.
(mips_set_option_string): New fn.
(md_parse_option): Make -mipsN update file_mips_isa rather than
mips_opts.isa. Use mips_set_option_string to set -march or -mtune.
Don't let -mgp32 and -mfp32 change the ABI.
(show): Move to end of file. Constify string argument.
(md_show_usage): Move to the end of the file. Read available
architectures from mips_cpu_info_table.
(mips_set_architecture): New fn.
(mips_after_parse_args): Rework. Remove -mcpu handling. -mipsN
is an alias for -march=mipsN. Don't change the ABI based on other
flags. Infer the register size from the ABI as well as the
architecture. Complain about more conflicting arguments.
Unify logic with GCC.
(s_mipsset): Don't change the ABI.
(mips_elf_final_processing): Check USE_E_MIPS_ABI_O32.
(mips_cpu_info_table): Remove Generic-MIPS* entries, keeping just
"mipsN"-type entries. Remove entries that vary only in the
manufacturer's prefix, or that have "000" replaced by "k".
Remove TARGET_CPU entries. Make r2000 entry use CPU_R3000.
(mips_strict_matching_cpu_name_p, mips_matching_cpu_name_p): New fns.
(mips_parse_cpu): New fn.
(mips_cpu_info_from_name, mips_cpu_info_from_cpu): Remove.
(mips_cpu_info_from_isa): Minor formatting tweak.
[gas/testsuite]
* gas/mips/mips-gp32-fp64.d,
* gas/mips/mips-gp32-fp64-pic.d: Add -mfp64.
2002-07-25 11:48:07 +02:00
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static enum mips_abi_level mips_abi = NO_ABI;
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2001-11-12 17:54:54 +01:00
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2003-05-21 23:53:33 +02:00
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/* Whether or not we have code that can call pic code. */
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int mips_abicalls = FALSE;
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1999-05-03 09:29:11 +02:00
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/* This is the set of options which may be modified by the .set
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pseudo-op. We use a struct so that .set push and .set pop are more
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reliable. */
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2000-12-12 20:29:24 +01:00
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struct mips_set_options
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{
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1999-05-03 09:29:11 +02:00
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/* MIPS ISA (Instruction Set Architecture) level. This is set to -1
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if it has not been initialized. Changed by `.set mipsN', and the
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-mipsN command line option, and the default CPU. */
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int isa;
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2002-03-16 04:09:19 +01:00
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/* Enabled Application Specific Extensions (ASEs). These are set to -1
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if they have not been initialized. Changed by `.set <asename>', by
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command line options, and based on the default architecture. */
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int ase_mips3d;
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[ gas/ChangeLog ]
2002-05-30 Chris G. Demetriou <cgd@broadcom.com>
Ed Satterthwaite <ehs@broadcom.com>
* config/tc-mips.c (mips_set_options): New "ase_mdmx" member.
(mips_opts): Initialize "ase_mdmx" member.
(file_ase_mdmx): New variable.
(CPU_HAS_MDMX): New macro.
(md_begin): Initialize mips_opts.ase_mdmx and file_ase_mdmx
based on command line options and configuration defaults.
(macro_build): Note in comment that use of MDMX in macros is
not currently allowed.
(validate_mips_insn): Add support for the "O", "Q", "X", "Y", and
"Z" MDMX operand types.
(mips_ip): Accept MDMX instructions if mips_opts.ase_mdmx is set,
and add support for the "O", "Q", "X", "Y", and "Z" MDMX operand
types.
(OPTION_MDMX, OPTION_NO_MDMX, md_longopts, md_parse_option):
Add support for "-mdmx" and "-no-mdmx" options.
(OPTION_ELF_BASE): Move to accomodate new options.
(s_mipsset): Support ".set mdmx" and ".set nomdmx".
(mips_elf_final_processing): Set MDMX ASE ELF header flag if
file_ase_mdmx was set.
* doc/as.texinfo: Document -mdmx and -no-mdmx options.
* doc/c-mips.texi: Likewise, and document ".set mdmx" and ".set
nomdmx" directives.
[ gas/testsuite/ChangeLog ]
2002-05-30 Chris G. Demetriou <cgd@broadcom.com>
* gas/mips/mips64-mdmx.s: New file.
* gas/mips/mips64-mdmx.d: Likewise.
* gas/mips/mips.exp: Run new "mips64-mdmx" test.
[ include/opcode/ChangeLog ]
2002-05-30 Chris G. Demetriou <cgd@broadcom.com>
* mips.h (OP_SH_ALN, OP_MASK_ALN, OP_SH_VSEL, OP_MASK_VSEL)
(MDMX_FMTSEL_IMM_QH, MDMX_FMTSEL_IMM_OB, MDMX_FMTSEL_VEC_QH)
(MDMX_FMTSEL_VEC_OB, INSN_READ_MDMX_ACC, INSN_WRITE_MDMX_ACC)
(INSN_MDMX): New constants, for MDMX support.
(opcode character list): Add "O", "Q", "X", "Y", and "Z" for MDMX.
[ opcodes/ChangeLog ]
2002-05-30 Chris G. Demetriou <cgd@broadcom.com>
Ed Satterthwaite <ehs@broadcom.com>
* mips-dis.c (print_insn_arg): Add support for 'O', 'Q', 'X', 'Y',
and 'Z' formats, for MDMX.
(mips_isa_type): Add MDMX instructions to the ISA
bit mask for bfd_mach_mipsisa64.
* mips-opc.c: Add support for MDMX instructions.
(MX): New definition.
* mips-dis.c: Update copyright years to include 2002.
2002-05-31 03:17:18 +02:00
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int ase_mdmx;
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1999-05-03 09:29:11 +02:00
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/* Whether we are assembling for the mips16 processor. 0 if we are
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not, 1 if we are, and -1 if the value has not been initialized.
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Changed by `.set mips16' and `.set nomips16', and the -mips16 and
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-nomips16 command line options, and the default CPU. */
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int mips16;
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/* Non-zero if we should not reorder instructions. Changed by `.set
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reorder' and `.set noreorder'. */
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int noreorder;
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/* Non-zero if we should not permit the $at ($1) register to be used
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in instructions. Changed by `.set at' and `.set noat'. */
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int noat;
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/* Non-zero if we should warn when a macro instruction expands into
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more than one machine instruction. Changed by `.set nomacro' and
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`.set macro'. */
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int warn_about_macros;
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/* Non-zero if we should not move instructions. Changed by `.set
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move', `.set volatile', `.set nomove', and `.set novolatile'. */
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int nomove;
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/* Non-zero if we should not optimize branches by moving the target
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of the branch into the delay slot. Actually, we don't perform
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this optimization anyhow. Changed by `.set bopt' and `.set
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nobopt'. */
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int nobopt;
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/* Non-zero if we should not autoextend mips16 instructions.
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Changed by `.set autoextend' and `.set noautoextend'. */
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int noautoextend;
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2001-11-12 17:54:54 +01:00
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/* Restrict general purpose registers and floating point registers
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to 32 bit. This is initially determined when -mgp32 or -mfp32
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is passed but can changed if the assembler code uses .set mipsN. */
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int gp32;
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int fp32;
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2003-06-29 21:41:33 +02:00
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/* MIPS architecture (CPU) type. Changed by .set arch=FOO, the -march
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command line option, and the default CPU. */
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int arch;
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1999-05-03 09:29:11 +02:00
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};
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2001-11-12 17:54:54 +01:00
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/* True if -mgp32 was passed. */
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2001-12-20 22:11:26 +01:00
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static int file_mips_gp32 = -1;
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2001-11-12 17:54:54 +01:00
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/* True if -mfp32 was passed. */
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2001-12-20 22:11:26 +01:00
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static int file_mips_fp32 = -1;
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2001-11-12 17:54:54 +01:00
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1999-05-03 09:29:11 +02:00
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/* This is the struct we use to hold the current set of options. Note
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2002-06-08 01:26:54 +02:00
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that we must set the isa field to ISA_UNKNOWN and the ASE fields to
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2000-12-01 22:35:38 +01:00
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-1 to indicate that they have not been initialized. */
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1999-05-03 09:29:11 +02:00
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2000-12-12 20:29:24 +01:00
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static struct mips_set_options mips_opts =
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{
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2003-06-29 21:41:33 +02:00
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ISA_UNKNOWN, -1, -1, -1, 0, 0, 0, 0, 0, 0, 0, 0, CPU_UNKNOWN
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2000-12-01 22:35:38 +01:00
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};
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1999-05-03 09:29:11 +02:00
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/* These variables are filled in with the masks of registers used.
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The object format code reads them and puts them in the appropriate
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place. */
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unsigned long mips_gprmask;
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unsigned long mips_cprmask[4];
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/* MIPS ISA we are using for this output file. */
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2000-12-01 22:35:38 +01:00
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static int file_mips_isa = ISA_UNKNOWN;
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1999-05-03 09:29:11 +02:00
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2002-06-08 01:26:54 +02:00
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/* True if -mips16 was passed or implied by arguments passed on the
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command line (e.g., by -march). */
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static int file_ase_mips16;
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2002-03-16 04:09:19 +01:00
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/* True if -mips3d was passed or implied by arguments passed on the
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command line (e.g., by -march). */
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static int file_ase_mips3d;
|
|
|
|
|
|
[ gas/ChangeLog ]
2002-05-30 Chris G. Demetriou <cgd@broadcom.com>
Ed Satterthwaite <ehs@broadcom.com>
* config/tc-mips.c (mips_set_options): New "ase_mdmx" member.
(mips_opts): Initialize "ase_mdmx" member.
(file_ase_mdmx): New variable.
(CPU_HAS_MDMX): New macro.
(md_begin): Initialize mips_opts.ase_mdmx and file_ase_mdmx
based on command line options and configuration defaults.
(macro_build): Note in comment that use of MDMX in macros is
not currently allowed.
(validate_mips_insn): Add support for the "O", "Q", "X", "Y", and
"Z" MDMX operand types.
(mips_ip): Accept MDMX instructions if mips_opts.ase_mdmx is set,
and add support for the "O", "Q", "X", "Y", and "Z" MDMX operand
types.
(OPTION_MDMX, OPTION_NO_MDMX, md_longopts, md_parse_option):
Add support for "-mdmx" and "-no-mdmx" options.
(OPTION_ELF_BASE): Move to accomodate new options.
(s_mipsset): Support ".set mdmx" and ".set nomdmx".
(mips_elf_final_processing): Set MDMX ASE ELF header flag if
file_ase_mdmx was set.
* doc/as.texinfo: Document -mdmx and -no-mdmx options.
* doc/c-mips.texi: Likewise, and document ".set mdmx" and ".set
nomdmx" directives.
[ gas/testsuite/ChangeLog ]
2002-05-30 Chris G. Demetriou <cgd@broadcom.com>
* gas/mips/mips64-mdmx.s: New file.
* gas/mips/mips64-mdmx.d: Likewise.
* gas/mips/mips.exp: Run new "mips64-mdmx" test.
[ include/opcode/ChangeLog ]
2002-05-30 Chris G. Demetriou <cgd@broadcom.com>
* mips.h (OP_SH_ALN, OP_MASK_ALN, OP_SH_VSEL, OP_MASK_VSEL)
(MDMX_FMTSEL_IMM_QH, MDMX_FMTSEL_IMM_OB, MDMX_FMTSEL_VEC_QH)
(MDMX_FMTSEL_VEC_OB, INSN_READ_MDMX_ACC, INSN_WRITE_MDMX_ACC)
(INSN_MDMX): New constants, for MDMX support.
(opcode character list): Add "O", "Q", "X", "Y", and "Z" for MDMX.
[ opcodes/ChangeLog ]
2002-05-30 Chris G. Demetriou <cgd@broadcom.com>
Ed Satterthwaite <ehs@broadcom.com>
* mips-dis.c (print_insn_arg): Add support for 'O', 'Q', 'X', 'Y',
and 'Z' formats, for MDMX.
(mips_isa_type): Add MDMX instructions to the ISA
bit mask for bfd_mach_mipsisa64.
* mips-opc.c: Add support for MDMX instructions.
(MX): New definition.
* mips-dis.c: Update copyright years to include 2002.
2002-05-31 03:17:18 +02:00
|
|
|
|
/* True if -mdmx was passed or implied by arguments passed on the
|
|
|
|
|
command line (e.g., by -march). */
|
|
|
|
|
static int file_ase_mdmx;
|
|
|
|
|
|
2001-06-29 23:27:43 +02:00
|
|
|
|
/* The argument of the -march= flag. The architecture we are assembling. */
|
2003-06-29 21:41:33 +02:00
|
|
|
|
static int file_mips_arch = CPU_UNKNOWN;
|
[gas/]
* doc/c-mips.texi: Remove -mcpu. Document -mabi.
* configure.in (MIPS_CPU_STRING_DEFAULT): New configuration macro.
(USE_E_MIPS_ABI_O32, MIPS_DEFAULT_64BIT): New configuration macros.
* configure, config.in: Regenerate.
* config/tc-mips.c (file_mips_abi): Rename to mips_abi.
(mips_set_options): Remove "abi" field.
(mips_opts): Update accordingly. Replace all uses of mips_opts.abi
with mips_abi.
(mips_cpu): Remove.
(mips_arch_string, mips_arch_info): New vars.
(mips_tune_string, mips_tune_info): New vars.
(ABI_NEEDS_32BIT_REGS, ABI_NEEDS_64BIT_REGS): New macros.
(HAVE_32BIT_GPRS, HAVE_32BIT_FPRS): Don't check the ABI.
(mips_isa_to_str, mips_cpu_to_str): Remove.
(mips_ip): If the selected architecture is a generic ISA rather
than a processor, only mention the ISA level in error messages.
(OPTION_MCPU): Remove.
(OPTION_FP64): New.
(md_longopts): Add -mfp64, remove -mcpu.
(mips_set_option_string): New fn.
(md_parse_option): Make -mipsN update file_mips_isa rather than
mips_opts.isa. Use mips_set_option_string to set -march or -mtune.
Don't let -mgp32 and -mfp32 change the ABI.
(show): Move to end of file. Constify string argument.
(md_show_usage): Move to the end of the file. Read available
architectures from mips_cpu_info_table.
(mips_set_architecture): New fn.
(mips_after_parse_args): Rework. Remove -mcpu handling. -mipsN
is an alias for -march=mipsN. Don't change the ABI based on other
flags. Infer the register size from the ABI as well as the
architecture. Complain about more conflicting arguments.
Unify logic with GCC.
(s_mipsset): Don't change the ABI.
(mips_elf_final_processing): Check USE_E_MIPS_ABI_O32.
(mips_cpu_info_table): Remove Generic-MIPS* entries, keeping just
"mipsN"-type entries. Remove entries that vary only in the
manufacturer's prefix, or that have "000" replaced by "k".
Remove TARGET_CPU entries. Make r2000 entry use CPU_R3000.
(mips_strict_matching_cpu_name_p, mips_matching_cpu_name_p): New fns.
(mips_parse_cpu): New fn.
(mips_cpu_info_from_name, mips_cpu_info_from_cpu): Remove.
(mips_cpu_info_from_isa): Minor formatting tweak.
[gas/testsuite]
* gas/mips/mips-gp32-fp64.d,
* gas/mips/mips-gp32-fp64-pic.d: Add -mfp64.
2002-07-25 11:48:07 +02:00
|
|
|
|
static const char *mips_arch_string;
|
2001-06-29 23:27:43 +02:00
|
|
|
|
|
|
|
|
|
/* The argument of the -mtune= flag. The architecture for which we
|
|
|
|
|
are optimizing. */
|
|
|
|
|
static int mips_tune = CPU_UNKNOWN;
|
[gas/]
* doc/c-mips.texi: Remove -mcpu. Document -mabi.
* configure.in (MIPS_CPU_STRING_DEFAULT): New configuration macro.
(USE_E_MIPS_ABI_O32, MIPS_DEFAULT_64BIT): New configuration macros.
* configure, config.in: Regenerate.
* config/tc-mips.c (file_mips_abi): Rename to mips_abi.
(mips_set_options): Remove "abi" field.
(mips_opts): Update accordingly. Replace all uses of mips_opts.abi
with mips_abi.
(mips_cpu): Remove.
(mips_arch_string, mips_arch_info): New vars.
(mips_tune_string, mips_tune_info): New vars.
(ABI_NEEDS_32BIT_REGS, ABI_NEEDS_64BIT_REGS): New macros.
(HAVE_32BIT_GPRS, HAVE_32BIT_FPRS): Don't check the ABI.
(mips_isa_to_str, mips_cpu_to_str): Remove.
(mips_ip): If the selected architecture is a generic ISA rather
than a processor, only mention the ISA level in error messages.
(OPTION_MCPU): Remove.
(OPTION_FP64): New.
(md_longopts): Add -mfp64, remove -mcpu.
(mips_set_option_string): New fn.
(md_parse_option): Make -mipsN update file_mips_isa rather than
mips_opts.isa. Use mips_set_option_string to set -march or -mtune.
Don't let -mgp32 and -mfp32 change the ABI.
(show): Move to end of file. Constify string argument.
(md_show_usage): Move to the end of the file. Read available
architectures from mips_cpu_info_table.
(mips_set_architecture): New fn.
(mips_after_parse_args): Rework. Remove -mcpu handling. -mipsN
is an alias for -march=mipsN. Don't change the ABI based on other
flags. Infer the register size from the ABI as well as the
architecture. Complain about more conflicting arguments.
Unify logic with GCC.
(s_mipsset): Don't change the ABI.
(mips_elf_final_processing): Check USE_E_MIPS_ABI_O32.
(mips_cpu_info_table): Remove Generic-MIPS* entries, keeping just
"mipsN"-type entries. Remove entries that vary only in the
manufacturer's prefix, or that have "000" replaced by "k".
Remove TARGET_CPU entries. Make r2000 entry use CPU_R3000.
(mips_strict_matching_cpu_name_p, mips_matching_cpu_name_p): New fns.
(mips_parse_cpu): New fn.
(mips_cpu_info_from_name, mips_cpu_info_from_cpu): Remove.
(mips_cpu_info_from_isa): Minor formatting tweak.
[gas/testsuite]
* gas/mips/mips-gp32-fp64.d,
* gas/mips/mips-gp32-fp64-pic.d: Add -mfp64.
2002-07-25 11:48:07 +02:00
|
|
|
|
static const char *mips_tune_string;
|
2001-06-29 23:27:43 +02:00
|
|
|
|
|
[gas/]
* doc/c-mips.texi: Remove -mcpu. Document -mabi.
* configure.in (MIPS_CPU_STRING_DEFAULT): New configuration macro.
(USE_E_MIPS_ABI_O32, MIPS_DEFAULT_64BIT): New configuration macros.
* configure, config.in: Regenerate.
* config/tc-mips.c (file_mips_abi): Rename to mips_abi.
(mips_set_options): Remove "abi" field.
(mips_opts): Update accordingly. Replace all uses of mips_opts.abi
with mips_abi.
(mips_cpu): Remove.
(mips_arch_string, mips_arch_info): New vars.
(mips_tune_string, mips_tune_info): New vars.
(ABI_NEEDS_32BIT_REGS, ABI_NEEDS_64BIT_REGS): New macros.
(HAVE_32BIT_GPRS, HAVE_32BIT_FPRS): Don't check the ABI.
(mips_isa_to_str, mips_cpu_to_str): Remove.
(mips_ip): If the selected architecture is a generic ISA rather
than a processor, only mention the ISA level in error messages.
(OPTION_MCPU): Remove.
(OPTION_FP64): New.
(md_longopts): Add -mfp64, remove -mcpu.
(mips_set_option_string): New fn.
(md_parse_option): Make -mipsN update file_mips_isa rather than
mips_opts.isa. Use mips_set_option_string to set -march or -mtune.
Don't let -mgp32 and -mfp32 change the ABI.
(show): Move to end of file. Constify string argument.
(md_show_usage): Move to the end of the file. Read available
architectures from mips_cpu_info_table.
(mips_set_architecture): New fn.
(mips_after_parse_args): Rework. Remove -mcpu handling. -mipsN
is an alias for -march=mipsN. Don't change the ABI based on other
flags. Infer the register size from the ABI as well as the
architecture. Complain about more conflicting arguments.
Unify logic with GCC.
(s_mipsset): Don't change the ABI.
(mips_elf_final_processing): Check USE_E_MIPS_ABI_O32.
(mips_cpu_info_table): Remove Generic-MIPS* entries, keeping just
"mipsN"-type entries. Remove entries that vary only in the
manufacturer's prefix, or that have "000" replaced by "k".
Remove TARGET_CPU entries. Make r2000 entry use CPU_R3000.
(mips_strict_matching_cpu_name_p, mips_matching_cpu_name_p): New fns.
(mips_parse_cpu): New fn.
(mips_cpu_info_from_name, mips_cpu_info_from_cpu): Remove.
(mips_cpu_info_from_isa): Minor formatting tweak.
[gas/testsuite]
* gas/mips/mips-gp32-fp64.d,
* gas/mips/mips-gp32-fp64-pic.d: Add -mfp64.
2002-07-25 11:48:07 +02:00
|
|
|
|
/* True when generating 32-bit code for a 64-bit processor. */
|
1999-05-03 09:29:11 +02:00
|
|
|
|
static int mips_32bitmode = 0;
|
|
|
|
|
|
[gas/]
* doc/c-mips.texi: Remove -mcpu. Document -mabi.
* configure.in (MIPS_CPU_STRING_DEFAULT): New configuration macro.
(USE_E_MIPS_ABI_O32, MIPS_DEFAULT_64BIT): New configuration macros.
* configure, config.in: Regenerate.
* config/tc-mips.c (file_mips_abi): Rename to mips_abi.
(mips_set_options): Remove "abi" field.
(mips_opts): Update accordingly. Replace all uses of mips_opts.abi
with mips_abi.
(mips_cpu): Remove.
(mips_arch_string, mips_arch_info): New vars.
(mips_tune_string, mips_tune_info): New vars.
(ABI_NEEDS_32BIT_REGS, ABI_NEEDS_64BIT_REGS): New macros.
(HAVE_32BIT_GPRS, HAVE_32BIT_FPRS): Don't check the ABI.
(mips_isa_to_str, mips_cpu_to_str): Remove.
(mips_ip): If the selected architecture is a generic ISA rather
than a processor, only mention the ISA level in error messages.
(OPTION_MCPU): Remove.
(OPTION_FP64): New.
(md_longopts): Add -mfp64, remove -mcpu.
(mips_set_option_string): New fn.
(md_parse_option): Make -mipsN update file_mips_isa rather than
mips_opts.isa. Use mips_set_option_string to set -march or -mtune.
Don't let -mgp32 and -mfp32 change the ABI.
(show): Move to end of file. Constify string argument.
(md_show_usage): Move to the end of the file. Read available
architectures from mips_cpu_info_table.
(mips_set_architecture): New fn.
(mips_after_parse_args): Rework. Remove -mcpu handling. -mipsN
is an alias for -march=mipsN. Don't change the ABI based on other
flags. Infer the register size from the ABI as well as the
architecture. Complain about more conflicting arguments.
Unify logic with GCC.
(s_mipsset): Don't change the ABI.
(mips_elf_final_processing): Check USE_E_MIPS_ABI_O32.
(mips_cpu_info_table): Remove Generic-MIPS* entries, keeping just
"mipsN"-type entries. Remove entries that vary only in the
manufacturer's prefix, or that have "000" replaced by "k".
Remove TARGET_CPU entries. Make r2000 entry use CPU_R3000.
(mips_strict_matching_cpu_name_p, mips_matching_cpu_name_p): New fns.
(mips_parse_cpu): New fn.
(mips_cpu_info_from_name, mips_cpu_info_from_cpu): Remove.
(mips_cpu_info_from_isa): Minor formatting tweak.
[gas/testsuite]
* gas/mips/mips-gp32-fp64.d,
* gas/mips/mips-gp32-fp64-pic.d: Add -mfp64.
2002-07-25 11:48:07 +02:00
|
|
|
|
/* True if the given ABI requires 32-bit registers. */
|
|
|
|
|
#define ABI_NEEDS_32BIT_REGS(ABI) ((ABI) == O32_ABI)
|
|
|
|
|
|
|
|
|
|
/* Likewise 64-bit registers. */
|
|
|
|
|
#define ABI_NEEDS_64BIT_REGS(ABI) \
|
|
|
|
|
((ABI) == N32_ABI \
|
|
|
|
|
|| (ABI) == N64_ABI \
|
|
|
|
|
|| (ABI) == O64_ABI)
|
|
|
|
|
|
2000-09-07 14:45:56 +02:00
|
|
|
|
/* Return true if ISA supports 64 bit gp register instructions. */
|
* config/tc-mips.c (ISA_HAS_COPROC_DELAYS) : New.
(ISA_HAS_64_BIT_REGS) New.
(gpr_interlocks,md_begin,reg_needs_delay,append_insn,
mips_emit_delays,macro_build,load_register,load_addresss,
macro,macro2,mips_ip,s_cprestore,s_cpadd): Simplify
and/or use new ISA_xxx macros in expressions involving
ISA, particularly mips_opts.isa.
1999-10-21 15:23:31 +02:00
|
|
|
|
#define ISA_HAS_64BIT_REGS(ISA) ( \
|
2000-12-01 22:35:38 +01:00
|
|
|
|
(ISA) == ISA_MIPS3 \
|
|
|
|
|
|| (ISA) == ISA_MIPS4 \
|
2000-12-02 01:55:22 +01:00
|
|
|
|
|| (ISA) == ISA_MIPS5 \
|
2001-05-23 19:26:40 +02:00
|
|
|
|
|| (ISA) == ISA_MIPS64 \
|
[ bfd/ChangeLog ]
2003-09-30 Chris Demetriou <cgd@broadcom.com>
* archures.c (bfd_mach_mipsisa64r2): New define.
* bfd-in2.h: Regenerate.
* aoutx.h (NAME(aout,machine_type)): Handle bfd_mach_mipsisa64r2.
* cpu-mips.c (I_mipsisa64r2): New enum value.
(arch_info_struct): Add entry for I_mipsisa64r2.
* elfxx-mips.c (_bfd_elf_mips_mach)
(_bfd_mips_elf_print_private_bfd_data): Handle E_MIPS_ARCH_64R2.
(mips_set_isa_flags): Add bfd_mach_mipsisa64r2 case.
(mips_mach_extensions): Add entry for bfd_mach_mipsisa64r2.
[ binutils/ChangeLog ]
2003-09-30 Chris Demetriou <cgd@broadcom.com>
* readelf.c (get_machine_flags): Handle E_MIPS_ARCH_64R2.
[ gas/Changelog ]
2003-09-30 Chris Demetriou <cgd@broadcom.com>
* configure.in (mipsisa64r2, mipsisa64r2el, mipsisa64r2*): New CPUs.
* configure: Regenerate.
* config/tc-mips.c (imm2_expr): New variable.
(md_assemble, mips16_ip): Initialize imm2_expr.
(ISA_HAS_64BIT_REGS, ISA_HAS_DROR, ISA_HAS_ROR): Add ISA_MIPS64R2.
(macro_build): Handle +A, +B, +C, +E, +F, +G, and +H format operands.
(macro): Handle M_DEXT and M_DINS.
(validate_mips_insn): Handle +E, +F, +G, +H, and +I format operands.
(mips_ip): Likewise.
(OPTION_MIPS64R2): New define.
(md_longopts): New entry for -mips64r2 (OPTION_MIPS64R2).
OPTION_ASE_BASE): Increase to compensate for OPTION_MIPS64R2.
(md_parse_option): Handle OPTION_MIPS64R2.
(s_mipsset): Handle setting "mips64r2" ISA.
(mips_cpu_info_table): Add mips64r2.
(md_show_usage): Document -mips64r2 option.
* doc/as.texinfo: Docuemnt -mips64r2 option.
* doc/c-mips.texi: Likewise.
[ gas/testsuite/ChangeLog ]
2003-09-30 Chris Demetriou <cgd@broadcom.com>
* gas/mips/cp0-names-mips64r2.d: New file.
* gas/mips/cp0sel-names-mips64r2.d: New file.
* gas/mips/elf_arch_mips64r2.d: New file.
* gas/mips/hwr-names-mips64r2.d: New file.
* gas/mips/mips32r2-ill-fp64.l: New file.
* gas/mips/mips32r2-ill-fp64.s: New file.
* gas/mips/mips64r2-ill.l: New file.
* gas/mips/mips64r2-ill.s: New file.
* gas/mips/mips64r2.d: New file.
* gas/mips/mips64r2.s: New file.
* gas/mips/mips.exp: Define "mips64r2" arch, and run new tests.
[ include/elf/ChangeLog ]
2003-09-30 Chris Demetriou <cgd@broadcom.com>
* mips.h (E_MIPS_ARCH_64R2): New define.
[ include/opcode/ChangeLog ]
2003-09-30 Chris Demetriou <cgd@broadcom.com>
* mips.h: Document +E, +F, +G, +H, and +I operand types.
Update documentation of I, +B and +C operand types.
(INSN_ISA64R2, ISA_MIPS64R2, CPU_MIPS64R2): New defines.
(M_DEXT, M_DINS): New enum values.
[ ld/ChangeLog ]
2003-09-30 Chris Demetriou <cgd@broadcom.com>
* ldmain.c (get_emulation): Ignore "-mips64r2".
[ ld/testsuite/ChangeLog ]
2003-09-30 Chris Demetriou <cgd@broadcom.com>
* ld-mips-elf/mips-elf-flags.exp: Add tests for combinations
with MIPS64r2.
[ opcodes/ChangeLog ]
2003-09-30 Chris Demetriou <cgd@broadcom.com>
* mips-dis.c (mips_arch_choices): Add entry for "mips64r2"
(print_insn_args): Add handing for +E, +F, +G, and +H.
* mips-opc.c (I65): New define for MIPS64r2.
(mips_builtin_opcodes): Add "dext", "dextm", "dextu", "dins",
"dinsm", "dinsu", "drotl", "drotr", "drotr32", "drotrv", "dsbh",
and "dshd" for MIPS64r2. Adjust "dror", "dror32", and "drorv" to
be supported on MIPS64r2.
2003-09-30 18:17:15 +02:00
|
|
|
|
|| (ISA) == ISA_MIPS64R2 \
|
* config/tc-mips.c (ISA_HAS_COPROC_DELAYS) : New.
(ISA_HAS_64_BIT_REGS) New.
(gpr_interlocks,md_begin,reg_needs_delay,append_insn,
mips_emit_delays,macro_build,load_register,load_addresss,
macro,macro2,mips_ip,s_cprestore,s_cpadd): Simplify
and/or use new ISA_xxx macros in expressions involving
ISA, particularly mips_opts.isa.
1999-10-21 15:23:31 +02:00
|
|
|
|
)
|
|
|
|
|
|
[ bfd/ChangeLog ]
2002-12-30 Chris Demetriou <cgd@broadcom.com>
* aoutx.h (NAME(aout,machine_type)): Add bfd_mach_mipsisa32r2 case.
* archures.c (bfd_mach_mipsisa32r2): New define.
* bfd-in2.h: Regenerate.
* cpu-mips.c (I_mipsisa32r2): New enum value.
(arch_info_struct): Add entry for I_mipsisa32r2.
* elfxx-mips.c (elf_mips_isa, _bfd_elf_mips_mach)
(_bfd_mips_elf_print_private_bfd_data): Handle E_MIPS_ARCH_32R2.
(_bfd_mips_elf_final_write_processing): Add
bfd_mach_mipsisa32r2 case.
(_bfd_mips_elf_merge_private_bfd_data): Handle merging of
binaries marked as using MIPS32 Release 2.
[ binutils/ChangeLog ]
2002-12-30 Chris Demetriou <cgd@broadcom.com>
* doc/binutils.texi (objdump): Note MIPS HWR (Hardware Register)
changes in MIPS -M options.
[ gas/ChangeLog ]
2002-12-30 Chris Demetriou <cgd@broadcom.com>
* configure.in: Recognize mipsisa32r2, mipsisa32r2el, and
CPU variants.
* configure: Regenerate.
* config/tc-mips.c (ISA_HAS_DROR, ISA_HAS_ROR): New defines.
(macro_build): Handle "K" operand.
(macro2): Use ISA_HAS_DROR and ISA_HAS_ROR in the places where
CPU_HAS_DROR and CPU_HAS_ROR are currently used.
(mips_ip): New variable "lastpos", and implement "+A", "+B",
and "+C" operands for MIPS32 Release 2 ins/ext instructions.
Implement "K" operand for MIPS32 Release 2 rdhwr instruction.
(validate_mips_insn): Implement "+" as a way to extend the
allowed operands, and implement "K", "+A", "+B", and "+C"
operands.
(OPTION_MIPS32R2): New define.
(md_longopts): Add entry for OPTION_MIPS32R2.
(OPTION_ELF_BASE): Adjust to accomodate OPTIONS_MIPS32R2.
(md_parse_option): Handle OPTION_MIPS32R2.
(s_mipsset): Reimplement handling of ".set mipsN" options
and add support for ".set mips32r2".
(mips_cpu_info_table): Add entry for "mips32r2" (MIPS32 Release 2).
(md_show_usage): Document "-mips32r2" option.
* doc/as.texinfo: Document "-mips32r2" option.
* doc/c-mips.texi: Likewise.
[ gas/testsuite/ChangeLog ]
2002-12-30 Chris Demetriou <cgd@broadcom.com>
* gas/mips/cp0-names-mips32r2.d: New test.
* gas/mips/hwr-names-mips32r2.d: New test.
* gas/mips/hwr-names-numeric.d: New test.
* gas/mips/hwr-names.s: New test source file.
* gas/mips/mips32r2.d: New test.
* gas/mips/mips32r2.s: New test source file.
* gas/mips/mips32r2-ill.l: New test.
* gas/mips/mips32r2-ill.s: New test source file.
* gas/mips/mips.exp: Add mips32r2 architecture data array
entry. Run new tests mentioned above.
[ include/elf/ChangeLog ]
2002-12-30 Chris Demetriou <cgd@broadcom.com>
* mips.h (E_MIPS_ARCH_32R2): New define.
[ include/opcode/ChangeLog ]
2002-12-30 Chris Demetriou <cgd@broadcom.com>
* mips.h: Document "+" as the start of two-character operand
type names, and add new "K", "+A", "+B", and "+C" operand types.
(OP_MASK_INSMSB, OP_SH_INSMSB, OP_MASK_EXTMSB)
(OP_SH_EXTMSB, INSN_ISA32R2, ISA_MIPS32R2, CPU_MIPS32R2): New
defines.
[ opcodes/ChangeLog ]
2002-12-30 Chris Demetriou <cgd@broadcom.com>
* mips-dis.c (mips_cp0_names_mips3264r2, mips_hwr_names_numeric)
(mips_hwr_names_mips3264r2): New arrays.
(mips_arch_choice): New "hwr_names" member.
(mips_arch_choices): Adjust for structure change, and add a new
entry for "mips32r2" ISA.
(mips_hwr_names): New variable.
(set_default_mips_dis_options): Set mips_hwr_names.
(parse_mips_dis_option): New "hwr-names" option which sets
mips_hwr_names, and adjust "reg-names=ARCH" to set mips_hwr_names.
(print_insn_arg): Change return type to "int"
and use that to indicate number of characters consumed.
Add support for "+" operand extension character, "+A", "+B",
"+C", and "K" operands.
(print_insn_mips): Adjust for changes to print_insn_arg.
(print_mips_disassembler_options): Adjust for "hwr-names"
addition and "reg-names" change.
* mips-opc (I33): New define (shorthand for INSN_ISA32R2).
(mips_builtin_opcodes): Note that "nop" and "ssnop" are special
forms of "sll". Add new MIPS32 Release 2 instructions: ehb,
di, ei, ext, ins, jr.hb, jalr.hb, mfhc1, mfhc2, mthc1, mthc2,
rdhwr, rdpgpr, seb, seh, synci, wrpgpr, wsbh.
Note that hardware rotate instructions (ror, rorv) can be
used on MIPS32 Release 2, and add the official mnemonics
for them (rotr, rotrv) and the similar "rotl" mnemonic for
left-rotate.
2002-12-31 08:29:29 +01:00
|
|
|
|
/* Return true if ISA supports 64-bit right rotate (dror et al.)
|
|
|
|
|
instructions. */
|
|
|
|
|
#define ISA_HAS_DROR(ISA) ( \
|
[ bfd/ChangeLog ]
2003-09-30 Chris Demetriou <cgd@broadcom.com>
* archures.c (bfd_mach_mipsisa64r2): New define.
* bfd-in2.h: Regenerate.
* aoutx.h (NAME(aout,machine_type)): Handle bfd_mach_mipsisa64r2.
* cpu-mips.c (I_mipsisa64r2): New enum value.
(arch_info_struct): Add entry for I_mipsisa64r2.
* elfxx-mips.c (_bfd_elf_mips_mach)
(_bfd_mips_elf_print_private_bfd_data): Handle E_MIPS_ARCH_64R2.
(mips_set_isa_flags): Add bfd_mach_mipsisa64r2 case.
(mips_mach_extensions): Add entry for bfd_mach_mipsisa64r2.
[ binutils/ChangeLog ]
2003-09-30 Chris Demetriou <cgd@broadcom.com>
* readelf.c (get_machine_flags): Handle E_MIPS_ARCH_64R2.
[ gas/Changelog ]
2003-09-30 Chris Demetriou <cgd@broadcom.com>
* configure.in (mipsisa64r2, mipsisa64r2el, mipsisa64r2*): New CPUs.
* configure: Regenerate.
* config/tc-mips.c (imm2_expr): New variable.
(md_assemble, mips16_ip): Initialize imm2_expr.
(ISA_HAS_64BIT_REGS, ISA_HAS_DROR, ISA_HAS_ROR): Add ISA_MIPS64R2.
(macro_build): Handle +A, +B, +C, +E, +F, +G, and +H format operands.
(macro): Handle M_DEXT and M_DINS.
(validate_mips_insn): Handle +E, +F, +G, +H, and +I format operands.
(mips_ip): Likewise.
(OPTION_MIPS64R2): New define.
(md_longopts): New entry for -mips64r2 (OPTION_MIPS64R2).
OPTION_ASE_BASE): Increase to compensate for OPTION_MIPS64R2.
(md_parse_option): Handle OPTION_MIPS64R2.
(s_mipsset): Handle setting "mips64r2" ISA.
(mips_cpu_info_table): Add mips64r2.
(md_show_usage): Document -mips64r2 option.
* doc/as.texinfo: Docuemnt -mips64r2 option.
* doc/c-mips.texi: Likewise.
[ gas/testsuite/ChangeLog ]
2003-09-30 Chris Demetriou <cgd@broadcom.com>
* gas/mips/cp0-names-mips64r2.d: New file.
* gas/mips/cp0sel-names-mips64r2.d: New file.
* gas/mips/elf_arch_mips64r2.d: New file.
* gas/mips/hwr-names-mips64r2.d: New file.
* gas/mips/mips32r2-ill-fp64.l: New file.
* gas/mips/mips32r2-ill-fp64.s: New file.
* gas/mips/mips64r2-ill.l: New file.
* gas/mips/mips64r2-ill.s: New file.
* gas/mips/mips64r2.d: New file.
* gas/mips/mips64r2.s: New file.
* gas/mips/mips.exp: Define "mips64r2" arch, and run new tests.
[ include/elf/ChangeLog ]
2003-09-30 Chris Demetriou <cgd@broadcom.com>
* mips.h (E_MIPS_ARCH_64R2): New define.
[ include/opcode/ChangeLog ]
2003-09-30 Chris Demetriou <cgd@broadcom.com>
* mips.h: Document +E, +F, +G, +H, and +I operand types.
Update documentation of I, +B and +C operand types.
(INSN_ISA64R2, ISA_MIPS64R2, CPU_MIPS64R2): New defines.
(M_DEXT, M_DINS): New enum values.
[ ld/ChangeLog ]
2003-09-30 Chris Demetriou <cgd@broadcom.com>
* ldmain.c (get_emulation): Ignore "-mips64r2".
[ ld/testsuite/ChangeLog ]
2003-09-30 Chris Demetriou <cgd@broadcom.com>
* ld-mips-elf/mips-elf-flags.exp: Add tests for combinations
with MIPS64r2.
[ opcodes/ChangeLog ]
2003-09-30 Chris Demetriou <cgd@broadcom.com>
* mips-dis.c (mips_arch_choices): Add entry for "mips64r2"
(print_insn_args): Add handing for +E, +F, +G, and +H.
* mips-opc.c (I65): New define for MIPS64r2.
(mips_builtin_opcodes): Add "dext", "dextm", "dextu", "dins",
"dinsm", "dinsu", "drotl", "drotr", "drotr32", "drotrv", "dsbh",
and "dshd" for MIPS64r2. Adjust "dror", "dror32", and "drorv" to
be supported on MIPS64r2.
2003-09-30 18:17:15 +02:00
|
|
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|
(ISA) == ISA_MIPS64R2 \
|
[ bfd/ChangeLog ]
2002-12-30 Chris Demetriou <cgd@broadcom.com>
* aoutx.h (NAME(aout,machine_type)): Add bfd_mach_mipsisa32r2 case.
* archures.c (bfd_mach_mipsisa32r2): New define.
* bfd-in2.h: Regenerate.
* cpu-mips.c (I_mipsisa32r2): New enum value.
(arch_info_struct): Add entry for I_mipsisa32r2.
* elfxx-mips.c (elf_mips_isa, _bfd_elf_mips_mach)
(_bfd_mips_elf_print_private_bfd_data): Handle E_MIPS_ARCH_32R2.
(_bfd_mips_elf_final_write_processing): Add
bfd_mach_mipsisa32r2 case.
(_bfd_mips_elf_merge_private_bfd_data): Handle merging of
binaries marked as using MIPS32 Release 2.
[ binutils/ChangeLog ]
2002-12-30 Chris Demetriou <cgd@broadcom.com>
* doc/binutils.texi (objdump): Note MIPS HWR (Hardware Register)
changes in MIPS -M options.
[ gas/ChangeLog ]
2002-12-30 Chris Demetriou <cgd@broadcom.com>
* configure.in: Recognize mipsisa32r2, mipsisa32r2el, and
CPU variants.
* configure: Regenerate.
* config/tc-mips.c (ISA_HAS_DROR, ISA_HAS_ROR): New defines.
(macro_build): Handle "K" operand.
(macro2): Use ISA_HAS_DROR and ISA_HAS_ROR in the places where
CPU_HAS_DROR and CPU_HAS_ROR are currently used.
(mips_ip): New variable "lastpos", and implement "+A", "+B",
and "+C" operands for MIPS32 Release 2 ins/ext instructions.
Implement "K" operand for MIPS32 Release 2 rdhwr instruction.
(validate_mips_insn): Implement "+" as a way to extend the
allowed operands, and implement "K", "+A", "+B", and "+C"
operands.
(OPTION_MIPS32R2): New define.
(md_longopts): Add entry for OPTION_MIPS32R2.
(OPTION_ELF_BASE): Adjust to accomodate OPTIONS_MIPS32R2.
(md_parse_option): Handle OPTION_MIPS32R2.
(s_mipsset): Reimplement handling of ".set mipsN" options
and add support for ".set mips32r2".
(mips_cpu_info_table): Add entry for "mips32r2" (MIPS32 Release 2).
(md_show_usage): Document "-mips32r2" option.
* doc/as.texinfo: Document "-mips32r2" option.
* doc/c-mips.texi: Likewise.
[ gas/testsuite/ChangeLog ]
2002-12-30 Chris Demetriou <cgd@broadcom.com>
* gas/mips/cp0-names-mips32r2.d: New test.
* gas/mips/hwr-names-mips32r2.d: New test.
* gas/mips/hwr-names-numeric.d: New test.
* gas/mips/hwr-names.s: New test source file.
* gas/mips/mips32r2.d: New test.
* gas/mips/mips32r2.s: New test source file.
* gas/mips/mips32r2-ill.l: New test.
* gas/mips/mips32r2-ill.s: New test source file.
* gas/mips/mips.exp: Add mips32r2 architecture data array
entry. Run new tests mentioned above.
[ include/elf/ChangeLog ]
2002-12-30 Chris Demetriou <cgd@broadcom.com>
* mips.h (E_MIPS_ARCH_32R2): New define.
[ include/opcode/ChangeLog ]
2002-12-30 Chris Demetriou <cgd@broadcom.com>
* mips.h: Document "+" as the start of two-character operand
type names, and add new "K", "+A", "+B", and "+C" operand types.
(OP_MASK_INSMSB, OP_SH_INSMSB, OP_MASK_EXTMSB)
(OP_SH_EXTMSB, INSN_ISA32R2, ISA_MIPS32R2, CPU_MIPS32R2): New
defines.
[ opcodes/ChangeLog ]
2002-12-30 Chris Demetriou <cgd@broadcom.com>
* mips-dis.c (mips_cp0_names_mips3264r2, mips_hwr_names_numeric)
(mips_hwr_names_mips3264r2): New arrays.
(mips_arch_choice): New "hwr_names" member.
(mips_arch_choices): Adjust for structure change, and add a new
entry for "mips32r2" ISA.
(mips_hwr_names): New variable.
(set_default_mips_dis_options): Set mips_hwr_names.
(parse_mips_dis_option): New "hwr-names" option which sets
mips_hwr_names, and adjust "reg-names=ARCH" to set mips_hwr_names.
(print_insn_arg): Change return type to "int"
and use that to indicate number of characters consumed.
Add support for "+" operand extension character, "+A", "+B",
"+C", and "K" operands.
(print_insn_mips): Adjust for changes to print_insn_arg.
(print_mips_disassembler_options): Adjust for "hwr-names"
addition and "reg-names" change.
* mips-opc (I33): New define (shorthand for INSN_ISA32R2).
(mips_builtin_opcodes): Note that "nop" and "ssnop" are special
forms of "sll". Add new MIPS32 Release 2 instructions: ehb,
di, ei, ext, ins, jr.hb, jalr.hb, mfhc1, mfhc2, mthc1, mthc2,
rdhwr, rdpgpr, seb, seh, synci, wrpgpr, wsbh.
Note that hardware rotate instructions (ror, rorv) can be
used on MIPS32 Release 2, and add the official mnemonics
for them (rotr, rotrv) and the similar "rotl" mnemonic for
left-rotate.
2002-12-31 08:29:29 +01:00
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)
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/* Return true if ISA supports 32-bit right rotate (ror et al.)
|
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instructions. */
|
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#define ISA_HAS_ROR(ISA) ( \
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(ISA) == ISA_MIPS32R2 \
|
[ bfd/ChangeLog ]
2003-09-30 Chris Demetriou <cgd@broadcom.com>
* archures.c (bfd_mach_mipsisa64r2): New define.
* bfd-in2.h: Regenerate.
* aoutx.h (NAME(aout,machine_type)): Handle bfd_mach_mipsisa64r2.
* cpu-mips.c (I_mipsisa64r2): New enum value.
(arch_info_struct): Add entry for I_mipsisa64r2.
* elfxx-mips.c (_bfd_elf_mips_mach)
(_bfd_mips_elf_print_private_bfd_data): Handle E_MIPS_ARCH_64R2.
(mips_set_isa_flags): Add bfd_mach_mipsisa64r2 case.
(mips_mach_extensions): Add entry for bfd_mach_mipsisa64r2.
[ binutils/ChangeLog ]
2003-09-30 Chris Demetriou <cgd@broadcom.com>
* readelf.c (get_machine_flags): Handle E_MIPS_ARCH_64R2.
[ gas/Changelog ]
2003-09-30 Chris Demetriou <cgd@broadcom.com>
* configure.in (mipsisa64r2, mipsisa64r2el, mipsisa64r2*): New CPUs.
* configure: Regenerate.
* config/tc-mips.c (imm2_expr): New variable.
(md_assemble, mips16_ip): Initialize imm2_expr.
(ISA_HAS_64BIT_REGS, ISA_HAS_DROR, ISA_HAS_ROR): Add ISA_MIPS64R2.
(macro_build): Handle +A, +B, +C, +E, +F, +G, and +H format operands.
(macro): Handle M_DEXT and M_DINS.
(validate_mips_insn): Handle +E, +F, +G, +H, and +I format operands.
(mips_ip): Likewise.
(OPTION_MIPS64R2): New define.
(md_longopts): New entry for -mips64r2 (OPTION_MIPS64R2).
OPTION_ASE_BASE): Increase to compensate for OPTION_MIPS64R2.
(md_parse_option): Handle OPTION_MIPS64R2.
(s_mipsset): Handle setting "mips64r2" ISA.
(mips_cpu_info_table): Add mips64r2.
(md_show_usage): Document -mips64r2 option.
* doc/as.texinfo: Docuemnt -mips64r2 option.
* doc/c-mips.texi: Likewise.
[ gas/testsuite/ChangeLog ]
2003-09-30 Chris Demetriou <cgd@broadcom.com>
* gas/mips/cp0-names-mips64r2.d: New file.
* gas/mips/cp0sel-names-mips64r2.d: New file.
* gas/mips/elf_arch_mips64r2.d: New file.
* gas/mips/hwr-names-mips64r2.d: New file.
* gas/mips/mips32r2-ill-fp64.l: New file.
* gas/mips/mips32r2-ill-fp64.s: New file.
* gas/mips/mips64r2-ill.l: New file.
* gas/mips/mips64r2-ill.s: New file.
* gas/mips/mips64r2.d: New file.
* gas/mips/mips64r2.s: New file.
* gas/mips/mips.exp: Define "mips64r2" arch, and run new tests.
[ include/elf/ChangeLog ]
2003-09-30 Chris Demetriou <cgd@broadcom.com>
* mips.h (E_MIPS_ARCH_64R2): New define.
[ include/opcode/ChangeLog ]
2003-09-30 Chris Demetriou <cgd@broadcom.com>
* mips.h: Document +E, +F, +G, +H, and +I operand types.
Update documentation of I, +B and +C operand types.
(INSN_ISA64R2, ISA_MIPS64R2, CPU_MIPS64R2): New defines.
(M_DEXT, M_DINS): New enum values.
[ ld/ChangeLog ]
2003-09-30 Chris Demetriou <cgd@broadcom.com>
* ldmain.c (get_emulation): Ignore "-mips64r2".
[ ld/testsuite/ChangeLog ]
2003-09-30 Chris Demetriou <cgd@broadcom.com>
* ld-mips-elf/mips-elf-flags.exp: Add tests for combinations
with MIPS64r2.
[ opcodes/ChangeLog ]
2003-09-30 Chris Demetriou <cgd@broadcom.com>
* mips-dis.c (mips_arch_choices): Add entry for "mips64r2"
(print_insn_args): Add handing for +E, +F, +G, and +H.
* mips-opc.c (I65): New define for MIPS64r2.
(mips_builtin_opcodes): Add "dext", "dextm", "dextu", "dins",
"dinsm", "dinsu", "drotl", "drotr", "drotr32", "drotrv", "dsbh",
and "dshd" for MIPS64r2. Adjust "dror", "dror32", and "drorv" to
be supported on MIPS64r2.
2003-09-30 18:17:15 +02:00
|
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|| (ISA) == ISA_MIPS64R2 \
|
[ bfd/ChangeLog ]
2002-12-30 Chris Demetriou <cgd@broadcom.com>
* aoutx.h (NAME(aout,machine_type)): Add bfd_mach_mipsisa32r2 case.
* archures.c (bfd_mach_mipsisa32r2): New define.
* bfd-in2.h: Regenerate.
* cpu-mips.c (I_mipsisa32r2): New enum value.
(arch_info_struct): Add entry for I_mipsisa32r2.
* elfxx-mips.c (elf_mips_isa, _bfd_elf_mips_mach)
(_bfd_mips_elf_print_private_bfd_data): Handle E_MIPS_ARCH_32R2.
(_bfd_mips_elf_final_write_processing): Add
bfd_mach_mipsisa32r2 case.
(_bfd_mips_elf_merge_private_bfd_data): Handle merging of
binaries marked as using MIPS32 Release 2.
[ binutils/ChangeLog ]
2002-12-30 Chris Demetriou <cgd@broadcom.com>
* doc/binutils.texi (objdump): Note MIPS HWR (Hardware Register)
changes in MIPS -M options.
[ gas/ChangeLog ]
2002-12-30 Chris Demetriou <cgd@broadcom.com>
* configure.in: Recognize mipsisa32r2, mipsisa32r2el, and
CPU variants.
* configure: Regenerate.
* config/tc-mips.c (ISA_HAS_DROR, ISA_HAS_ROR): New defines.
(macro_build): Handle "K" operand.
(macro2): Use ISA_HAS_DROR and ISA_HAS_ROR in the places where
CPU_HAS_DROR and CPU_HAS_ROR are currently used.
(mips_ip): New variable "lastpos", and implement "+A", "+B",
and "+C" operands for MIPS32 Release 2 ins/ext instructions.
Implement "K" operand for MIPS32 Release 2 rdhwr instruction.
(validate_mips_insn): Implement "+" as a way to extend the
allowed operands, and implement "K", "+A", "+B", and "+C"
operands.
(OPTION_MIPS32R2): New define.
(md_longopts): Add entry for OPTION_MIPS32R2.
(OPTION_ELF_BASE): Adjust to accomodate OPTIONS_MIPS32R2.
(md_parse_option): Handle OPTION_MIPS32R2.
(s_mipsset): Reimplement handling of ".set mipsN" options
and add support for ".set mips32r2".
(mips_cpu_info_table): Add entry for "mips32r2" (MIPS32 Release 2).
(md_show_usage): Document "-mips32r2" option.
* doc/as.texinfo: Document "-mips32r2" option.
* doc/c-mips.texi: Likewise.
[ gas/testsuite/ChangeLog ]
2002-12-30 Chris Demetriou <cgd@broadcom.com>
* gas/mips/cp0-names-mips32r2.d: New test.
* gas/mips/hwr-names-mips32r2.d: New test.
* gas/mips/hwr-names-numeric.d: New test.
* gas/mips/hwr-names.s: New test source file.
* gas/mips/mips32r2.d: New test.
* gas/mips/mips32r2.s: New test source file.
* gas/mips/mips32r2-ill.l: New test.
* gas/mips/mips32r2-ill.s: New test source file.
* gas/mips/mips.exp: Add mips32r2 architecture data array
entry. Run new tests mentioned above.
[ include/elf/ChangeLog ]
2002-12-30 Chris Demetriou <cgd@broadcom.com>
* mips.h (E_MIPS_ARCH_32R2): New define.
[ include/opcode/ChangeLog ]
2002-12-30 Chris Demetriou <cgd@broadcom.com>
* mips.h: Document "+" as the start of two-character operand
type names, and add new "K", "+A", "+B", and "+C" operand types.
(OP_MASK_INSMSB, OP_SH_INSMSB, OP_MASK_EXTMSB)
(OP_SH_EXTMSB, INSN_ISA32R2, ISA_MIPS32R2, CPU_MIPS32R2): New
defines.
[ opcodes/ChangeLog ]
2002-12-30 Chris Demetriou <cgd@broadcom.com>
* mips-dis.c (mips_cp0_names_mips3264r2, mips_hwr_names_numeric)
(mips_hwr_names_mips3264r2): New arrays.
(mips_arch_choice): New "hwr_names" member.
(mips_arch_choices): Adjust for structure change, and add a new
entry for "mips32r2" ISA.
(mips_hwr_names): New variable.
(set_default_mips_dis_options): Set mips_hwr_names.
(parse_mips_dis_option): New "hwr-names" option which sets
mips_hwr_names, and adjust "reg-names=ARCH" to set mips_hwr_names.
(print_insn_arg): Change return type to "int"
and use that to indicate number of characters consumed.
Add support for "+" operand extension character, "+A", "+B",
"+C", and "K" operands.
(print_insn_mips): Adjust for changes to print_insn_arg.
(print_mips_disassembler_options): Adjust for "hwr-names"
addition and "reg-names" change.
* mips-opc (I33): New define (shorthand for INSN_ISA32R2).
(mips_builtin_opcodes): Note that "nop" and "ssnop" are special
forms of "sll". Add new MIPS32 Release 2 instructions: ehb,
di, ei, ext, ins, jr.hb, jalr.hb, mfhc1, mfhc2, mthc1, mthc2,
rdhwr, rdpgpr, seb, seh, synci, wrpgpr, wsbh.
Note that hardware rotate instructions (ror, rorv) can be
used on MIPS32 Release 2, and add the official mnemonics
for them (rotr, rotrv) and the similar "rotl" mnemonic for
left-rotate.
2002-12-31 08:29:29 +01:00
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)
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2001-10-03 22:30:15 +02:00
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#define HAVE_32BIT_GPRS \
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[gas/]
* doc/c-mips.texi: Remove -mcpu. Document -mabi.
* configure.in (MIPS_CPU_STRING_DEFAULT): New configuration macro.
(USE_E_MIPS_ABI_O32, MIPS_DEFAULT_64BIT): New configuration macros.
* configure, config.in: Regenerate.
* config/tc-mips.c (file_mips_abi): Rename to mips_abi.
(mips_set_options): Remove "abi" field.
(mips_opts): Update accordingly. Replace all uses of mips_opts.abi
with mips_abi.
(mips_cpu): Remove.
(mips_arch_string, mips_arch_info): New vars.
(mips_tune_string, mips_tune_info): New vars.
(ABI_NEEDS_32BIT_REGS, ABI_NEEDS_64BIT_REGS): New macros.
(HAVE_32BIT_GPRS, HAVE_32BIT_FPRS): Don't check the ABI.
(mips_isa_to_str, mips_cpu_to_str): Remove.
(mips_ip): If the selected architecture is a generic ISA rather
than a processor, only mention the ISA level in error messages.
(OPTION_MCPU): Remove.
(OPTION_FP64): New.
(md_longopts): Add -mfp64, remove -mcpu.
(mips_set_option_string): New fn.
(md_parse_option): Make -mipsN update file_mips_isa rather than
mips_opts.isa. Use mips_set_option_string to set -march or -mtune.
Don't let -mgp32 and -mfp32 change the ABI.
(show): Move to end of file. Constify string argument.
(md_show_usage): Move to the end of the file. Read available
architectures from mips_cpu_info_table.
(mips_set_architecture): New fn.
(mips_after_parse_args): Rework. Remove -mcpu handling. -mipsN
is an alias for -march=mipsN. Don't change the ABI based on other
flags. Infer the register size from the ABI as well as the
architecture. Complain about more conflicting arguments.
Unify logic with GCC.
(s_mipsset): Don't change the ABI.
(mips_elf_final_processing): Check USE_E_MIPS_ABI_O32.
(mips_cpu_info_table): Remove Generic-MIPS* entries, keeping just
"mipsN"-type entries. Remove entries that vary only in the
manufacturer's prefix, or that have "000" replaced by "k".
Remove TARGET_CPU entries. Make r2000 entry use CPU_R3000.
(mips_strict_matching_cpu_name_p, mips_matching_cpu_name_p): New fns.
(mips_parse_cpu): New fn.
(mips_cpu_info_from_name, mips_cpu_info_from_cpu): Remove.
(mips_cpu_info_from_isa): Minor formatting tweak.
[gas/testsuite]
* gas/mips/mips-gp32-fp64.d,
* gas/mips/mips-gp32-fp64-pic.d: Add -mfp64.
2002-07-25 11:48:07 +02:00
|
|
|
|
(mips_opts.gp32 || ! ISA_HAS_64BIT_REGS (mips_opts.isa))
|
2001-08-02 12:15:24 +02:00
|
|
|
|
|
2001-10-03 22:30:15 +02:00
|
|
|
|
#define HAVE_32BIT_FPRS \
|
[gas/]
* doc/c-mips.texi: Remove -mcpu. Document -mabi.
* configure.in (MIPS_CPU_STRING_DEFAULT): New configuration macro.
(USE_E_MIPS_ABI_O32, MIPS_DEFAULT_64BIT): New configuration macros.
* configure, config.in: Regenerate.
* config/tc-mips.c (file_mips_abi): Rename to mips_abi.
(mips_set_options): Remove "abi" field.
(mips_opts): Update accordingly. Replace all uses of mips_opts.abi
with mips_abi.
(mips_cpu): Remove.
(mips_arch_string, mips_arch_info): New vars.
(mips_tune_string, mips_tune_info): New vars.
(ABI_NEEDS_32BIT_REGS, ABI_NEEDS_64BIT_REGS): New macros.
(HAVE_32BIT_GPRS, HAVE_32BIT_FPRS): Don't check the ABI.
(mips_isa_to_str, mips_cpu_to_str): Remove.
(mips_ip): If the selected architecture is a generic ISA rather
than a processor, only mention the ISA level in error messages.
(OPTION_MCPU): Remove.
(OPTION_FP64): New.
(md_longopts): Add -mfp64, remove -mcpu.
(mips_set_option_string): New fn.
(md_parse_option): Make -mipsN update file_mips_isa rather than
mips_opts.isa. Use mips_set_option_string to set -march or -mtune.
Don't let -mgp32 and -mfp32 change the ABI.
(show): Move to end of file. Constify string argument.
(md_show_usage): Move to the end of the file. Read available
architectures from mips_cpu_info_table.
(mips_set_architecture): New fn.
(mips_after_parse_args): Rework. Remove -mcpu handling. -mipsN
is an alias for -march=mipsN. Don't change the ABI based on other
flags. Infer the register size from the ABI as well as the
architecture. Complain about more conflicting arguments.
Unify logic with GCC.
(s_mipsset): Don't change the ABI.
(mips_elf_final_processing): Check USE_E_MIPS_ABI_O32.
(mips_cpu_info_table): Remove Generic-MIPS* entries, keeping just
"mipsN"-type entries. Remove entries that vary only in the
manufacturer's prefix, or that have "000" replaced by "k".
Remove TARGET_CPU entries. Make r2000 entry use CPU_R3000.
(mips_strict_matching_cpu_name_p, mips_matching_cpu_name_p): New fns.
(mips_parse_cpu): New fn.
(mips_cpu_info_from_name, mips_cpu_info_from_cpu): Remove.
(mips_cpu_info_from_isa): Minor formatting tweak.
[gas/testsuite]
* gas/mips/mips-gp32-fp64.d,
* gas/mips/mips-gp32-fp64-pic.d: Add -mfp64.
2002-07-25 11:48:07 +02:00
|
|
|
|
(mips_opts.fp32 || ! ISA_HAS_64BIT_REGS (mips_opts.isa))
|
2001-08-02 12:15:24 +02:00
|
|
|
|
|
|
|
|
|
#define HAVE_64BIT_GPRS (! HAVE_32BIT_GPRS)
|
|
|
|
|
#define HAVE_64BIT_FPRS (! HAVE_32BIT_FPRS)
|
|
|
|
|
|
[gas/]
* doc/c-mips.texi: Remove -mcpu. Document -mabi.
* configure.in (MIPS_CPU_STRING_DEFAULT): New configuration macro.
(USE_E_MIPS_ABI_O32, MIPS_DEFAULT_64BIT): New configuration macros.
* configure, config.in: Regenerate.
* config/tc-mips.c (file_mips_abi): Rename to mips_abi.
(mips_set_options): Remove "abi" field.
(mips_opts): Update accordingly. Replace all uses of mips_opts.abi
with mips_abi.
(mips_cpu): Remove.
(mips_arch_string, mips_arch_info): New vars.
(mips_tune_string, mips_tune_info): New vars.
(ABI_NEEDS_32BIT_REGS, ABI_NEEDS_64BIT_REGS): New macros.
(HAVE_32BIT_GPRS, HAVE_32BIT_FPRS): Don't check the ABI.
(mips_isa_to_str, mips_cpu_to_str): Remove.
(mips_ip): If the selected architecture is a generic ISA rather
than a processor, only mention the ISA level in error messages.
(OPTION_MCPU): Remove.
(OPTION_FP64): New.
(md_longopts): Add -mfp64, remove -mcpu.
(mips_set_option_string): New fn.
(md_parse_option): Make -mipsN update file_mips_isa rather than
mips_opts.isa. Use mips_set_option_string to set -march or -mtune.
Don't let -mgp32 and -mfp32 change the ABI.
(show): Move to end of file. Constify string argument.
(md_show_usage): Move to the end of the file. Read available
architectures from mips_cpu_info_table.
(mips_set_architecture): New fn.
(mips_after_parse_args): Rework. Remove -mcpu handling. -mipsN
is an alias for -march=mipsN. Don't change the ABI based on other
flags. Infer the register size from the ABI as well as the
architecture. Complain about more conflicting arguments.
Unify logic with GCC.
(s_mipsset): Don't change the ABI.
(mips_elf_final_processing): Check USE_E_MIPS_ABI_O32.
(mips_cpu_info_table): Remove Generic-MIPS* entries, keeping just
"mipsN"-type entries. Remove entries that vary only in the
manufacturer's prefix, or that have "000" replaced by "k".
Remove TARGET_CPU entries. Make r2000 entry use CPU_R3000.
(mips_strict_matching_cpu_name_p, mips_matching_cpu_name_p): New fns.
(mips_parse_cpu): New fn.
(mips_cpu_info_from_name, mips_cpu_info_from_cpu): Remove.
(mips_cpu_info_from_isa): Minor formatting tweak.
[gas/testsuite]
* gas/mips/mips-gp32-fp64.d,
* gas/mips/mips-gp32-fp64-pic.d: Add -mfp64.
2002-07-25 11:48:07 +02:00
|
|
|
|
#define HAVE_NEWABI (mips_abi == N32_ABI || mips_abi == N64_ABI)
|
2001-10-03 22:30:15 +02:00
|
|
|
|
|
[gas/]
* doc/c-mips.texi: Remove -mcpu. Document -mabi.
* configure.in (MIPS_CPU_STRING_DEFAULT): New configuration macro.
(USE_E_MIPS_ABI_O32, MIPS_DEFAULT_64BIT): New configuration macros.
* configure, config.in: Regenerate.
* config/tc-mips.c (file_mips_abi): Rename to mips_abi.
(mips_set_options): Remove "abi" field.
(mips_opts): Update accordingly. Replace all uses of mips_opts.abi
with mips_abi.
(mips_cpu): Remove.
(mips_arch_string, mips_arch_info): New vars.
(mips_tune_string, mips_tune_info): New vars.
(ABI_NEEDS_32BIT_REGS, ABI_NEEDS_64BIT_REGS): New macros.
(HAVE_32BIT_GPRS, HAVE_32BIT_FPRS): Don't check the ABI.
(mips_isa_to_str, mips_cpu_to_str): Remove.
(mips_ip): If the selected architecture is a generic ISA rather
than a processor, only mention the ISA level in error messages.
(OPTION_MCPU): Remove.
(OPTION_FP64): New.
(md_longopts): Add -mfp64, remove -mcpu.
(mips_set_option_string): New fn.
(md_parse_option): Make -mipsN update file_mips_isa rather than
mips_opts.isa. Use mips_set_option_string to set -march or -mtune.
Don't let -mgp32 and -mfp32 change the ABI.
(show): Move to end of file. Constify string argument.
(md_show_usage): Move to the end of the file. Read available
architectures from mips_cpu_info_table.
(mips_set_architecture): New fn.
(mips_after_parse_args): Rework. Remove -mcpu handling. -mipsN
is an alias for -march=mipsN. Don't change the ABI based on other
flags. Infer the register size from the ABI as well as the
architecture. Complain about more conflicting arguments.
Unify logic with GCC.
(s_mipsset): Don't change the ABI.
(mips_elf_final_processing): Check USE_E_MIPS_ABI_O32.
(mips_cpu_info_table): Remove Generic-MIPS* entries, keeping just
"mipsN"-type entries. Remove entries that vary only in the
manufacturer's prefix, or that have "000" replaced by "k".
Remove TARGET_CPU entries. Make r2000 entry use CPU_R3000.
(mips_strict_matching_cpu_name_p, mips_matching_cpu_name_p): New fns.
(mips_parse_cpu): New fn.
(mips_cpu_info_from_name, mips_cpu_info_from_cpu): Remove.
(mips_cpu_info_from_isa): Minor formatting tweak.
[gas/testsuite]
* gas/mips/mips-gp32-fp64.d,
* gas/mips/mips-gp32-fp64-pic.d: Add -mfp64.
2002-07-25 11:48:07 +02:00
|
|
|
|
#define HAVE_64BIT_OBJECTS (mips_abi == N64_ABI)
|
2001-10-03 22:30:15 +02:00
|
|
|
|
|
|
|
|
|
/* We can only have 64bit addresses if the object file format
|
|
|
|
|
supports it. */
|
2001-11-01 02:33:47 +01:00
|
|
|
|
#define HAVE_32BIT_ADDRESSES \
|
|
|
|
|
(HAVE_32BIT_GPRS \
|
|
|
|
|
|| ((bfd_arch_bits_per_address (stdoutput) == 32 \
|
|
|
|
|
|| ! HAVE_64BIT_OBJECTS) \
|
|
|
|
|
&& mips_pic != EMBEDDED_PIC))
|
2001-10-03 22:30:15 +02:00
|
|
|
|
|
|
|
|
|
#define HAVE_64BIT_ADDRESSES (! HAVE_32BIT_ADDRESSES)
|
2001-08-02 12:15:24 +02:00
|
|
|
|
|
2003-06-21 23:38:04 +02:00
|
|
|
|
/* Addresses are loaded in different ways, depending on the address size
|
|
|
|
|
in use. The n32 ABI Documentation also mandates the use of additions
|
|
|
|
|
with overflow checking, but existing implementations don't follow it. */
|
2003-06-16 14:13:10 +02:00
|
|
|
|
#define ADDRESS_ADD_INSN \
|
2003-06-21 23:38:04 +02:00
|
|
|
|
(HAVE_32BIT_ADDRESSES ? "addu" : "daddu")
|
2003-06-16 14:13:10 +02:00
|
|
|
|
|
|
|
|
|
#define ADDRESS_ADDI_INSN \
|
2003-06-21 23:38:04 +02:00
|
|
|
|
(HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu")
|
2003-06-16 14:13:10 +02:00
|
|
|
|
|
|
|
|
|
#define ADDRESS_LOAD_INSN \
|
|
|
|
|
(HAVE_32BIT_ADDRESSES ? "lw" : "ld")
|
|
|
|
|
|
|
|
|
|
#define ADDRESS_STORE_INSN \
|
|
|
|
|
(HAVE_32BIT_ADDRESSES ? "sw" : "sd")
|
|
|
|
|
|
2002-06-08 01:26:54 +02:00
|
|
|
|
/* Return true if the given CPU supports the MIPS16 ASE. */
|
2002-09-26 11:56:35 +02:00
|
|
|
|
#define CPU_HAS_MIPS16(cpu) \
|
|
|
|
|
(strncmp (TARGET_CPU, "mips16", sizeof ("mips16") - 1) == 0 \
|
|
|
|
|
|| strncmp (TARGET_CANONICAL, "mips-lsi-elf", sizeof ("mips-lsi-elf") - 1) == 0)
|
2002-06-08 01:26:54 +02:00
|
|
|
|
|
2002-03-16 04:09:19 +01:00
|
|
|
|
/* Return true if the given CPU supports the MIPS3D ASE. */
|
|
|
|
|
#define CPU_HAS_MIPS3D(cpu) ((cpu) == CPU_SB1 \
|
|
|
|
|
)
|
|
|
|
|
|
[ gas/ChangeLog ]
2002-05-30 Chris G. Demetriou <cgd@broadcom.com>
Ed Satterthwaite <ehs@broadcom.com>
* config/tc-mips.c (mips_set_options): New "ase_mdmx" member.
(mips_opts): Initialize "ase_mdmx" member.
(file_ase_mdmx): New variable.
(CPU_HAS_MDMX): New macro.
(md_begin): Initialize mips_opts.ase_mdmx and file_ase_mdmx
based on command line options and configuration defaults.
(macro_build): Note in comment that use of MDMX in macros is
not currently allowed.
(validate_mips_insn): Add support for the "O", "Q", "X", "Y", and
"Z" MDMX operand types.
(mips_ip): Accept MDMX instructions if mips_opts.ase_mdmx is set,
and add support for the "O", "Q", "X", "Y", and "Z" MDMX operand
types.
(OPTION_MDMX, OPTION_NO_MDMX, md_longopts, md_parse_option):
Add support for "-mdmx" and "-no-mdmx" options.
(OPTION_ELF_BASE): Move to accomodate new options.
(s_mipsset): Support ".set mdmx" and ".set nomdmx".
(mips_elf_final_processing): Set MDMX ASE ELF header flag if
file_ase_mdmx was set.
* doc/as.texinfo: Document -mdmx and -no-mdmx options.
* doc/c-mips.texi: Likewise, and document ".set mdmx" and ".set
nomdmx" directives.
[ gas/testsuite/ChangeLog ]
2002-05-30 Chris G. Demetriou <cgd@broadcom.com>
* gas/mips/mips64-mdmx.s: New file.
* gas/mips/mips64-mdmx.d: Likewise.
* gas/mips/mips.exp: Run new "mips64-mdmx" test.
[ include/opcode/ChangeLog ]
2002-05-30 Chris G. Demetriou <cgd@broadcom.com>
* mips.h (OP_SH_ALN, OP_MASK_ALN, OP_SH_VSEL, OP_MASK_VSEL)
(MDMX_FMTSEL_IMM_QH, MDMX_FMTSEL_IMM_OB, MDMX_FMTSEL_VEC_QH)
(MDMX_FMTSEL_VEC_OB, INSN_READ_MDMX_ACC, INSN_WRITE_MDMX_ACC)
(INSN_MDMX): New constants, for MDMX support.
(opcode character list): Add "O", "Q", "X", "Y", and "Z" for MDMX.
[ opcodes/ChangeLog ]
2002-05-30 Chris G. Demetriou <cgd@broadcom.com>
Ed Satterthwaite <ehs@broadcom.com>
* mips-dis.c (print_insn_arg): Add support for 'O', 'Q', 'X', 'Y',
and 'Z' formats, for MDMX.
(mips_isa_type): Add MDMX instructions to the ISA
bit mask for bfd_mach_mipsisa64.
* mips-opc.c: Add support for MDMX instructions.
(MX): New definition.
* mips-dis.c: Update copyright years to include 2002.
2002-05-31 03:17:18 +02:00
|
|
|
|
/* Return true if the given CPU supports the MDMX ASE. */
|
2002-11-30 09:39:46 +01:00
|
|
|
|
#define CPU_HAS_MDMX(cpu) (FALSE \
|
[ gas/ChangeLog ]
2002-05-30 Chris G. Demetriou <cgd@broadcom.com>
Ed Satterthwaite <ehs@broadcom.com>
* config/tc-mips.c (mips_set_options): New "ase_mdmx" member.
(mips_opts): Initialize "ase_mdmx" member.
(file_ase_mdmx): New variable.
(CPU_HAS_MDMX): New macro.
(md_begin): Initialize mips_opts.ase_mdmx and file_ase_mdmx
based on command line options and configuration defaults.
(macro_build): Note in comment that use of MDMX in macros is
not currently allowed.
(validate_mips_insn): Add support for the "O", "Q", "X", "Y", and
"Z" MDMX operand types.
(mips_ip): Accept MDMX instructions if mips_opts.ase_mdmx is set,
and add support for the "O", "Q", "X", "Y", and "Z" MDMX operand
types.
(OPTION_MDMX, OPTION_NO_MDMX, md_longopts, md_parse_option):
Add support for "-mdmx" and "-no-mdmx" options.
(OPTION_ELF_BASE): Move to accomodate new options.
(s_mipsset): Support ".set mdmx" and ".set nomdmx".
(mips_elf_final_processing): Set MDMX ASE ELF header flag if
file_ase_mdmx was set.
* doc/as.texinfo: Document -mdmx and -no-mdmx options.
* doc/c-mips.texi: Likewise, and document ".set mdmx" and ".set
nomdmx" directives.
[ gas/testsuite/ChangeLog ]
2002-05-30 Chris G. Demetriou <cgd@broadcom.com>
* gas/mips/mips64-mdmx.s: New file.
* gas/mips/mips64-mdmx.d: Likewise.
* gas/mips/mips.exp: Run new "mips64-mdmx" test.
[ include/opcode/ChangeLog ]
2002-05-30 Chris G. Demetriou <cgd@broadcom.com>
* mips.h (OP_SH_ALN, OP_MASK_ALN, OP_SH_VSEL, OP_MASK_VSEL)
(MDMX_FMTSEL_IMM_QH, MDMX_FMTSEL_IMM_OB, MDMX_FMTSEL_VEC_QH)
(MDMX_FMTSEL_VEC_OB, INSN_READ_MDMX_ACC, INSN_WRITE_MDMX_ACC)
(INSN_MDMX): New constants, for MDMX support.
(opcode character list): Add "O", "Q", "X", "Y", and "Z" for MDMX.
[ opcodes/ChangeLog ]
2002-05-30 Chris G. Demetriou <cgd@broadcom.com>
Ed Satterthwaite <ehs@broadcom.com>
* mips-dis.c (print_insn_arg): Add support for 'O', 'Q', 'X', 'Y',
and 'Z' formats, for MDMX.
(mips_isa_type): Add MDMX instructions to the ISA
bit mask for bfd_mach_mipsisa64.
* mips-opc.c: Add support for MDMX instructions.
(MX): New definition.
* mips-dis.c: Update copyright years to include 2002.
2002-05-31 03:17:18 +02:00
|
|
|
|
)
|
|
|
|
|
|
[gas/]
* doc/c-mips.texi: Add entries for -march=vr4120,vr4130,vr4181,
vr5400 and vr5500. Add entry for -mfix-vr4122-bugs.
* config/tc-mips.c (CPU_HAS_DROR, CPU_HAS_ROR): New macros.
(hilo_interlocks): True for CPU_VR5500.
(gpr_interlocks, cop_interlocks): True for CPU_VR5400 and CPU_VR5500.
(mips_fix_vr4122_bugs): New.
(append_insn): Work around 4122 errors if mips_fix_vr4122_bugs.
(mips_emit_delays): Likewise.
(macro2) [M_DROLI]: Use dror or dror32 if CPU_HAS_DROR.
[M_ROLI]: Likewise ror if CPU_HAS_ROR.
(validate_mips_insn, mips_ip): Handle '[', ']', 'e' and '%'.
(OPTION_FIX_VR4122, OPTION_NO_FIX_VR4122): New options.
(md_longopts): Add -mfix-vr4122-bugs and -no-mfix-vr4122-bugs.
(OPTION_ELF_BASE): Bump.
(md_parse_option): Handle the new options.
(mips_cpu_info_table): Add entries for vr4120, vr4130, vr4181,
vr5400 and vr5500.
[gas/testsuite/]
* gas/mips/mips4100.[sd]: Move dmadd16 and madd16 checks to...
* gas/mips/vr4111.[sd]: ...this new test.
* gas/mips/vr4120.[sd],
* gas/mips/vr4122.[sd],
* gas/mips/vr5400.[sd],
* gas/mips/vr5500.[sd]: New tests.
* mips.exp: Run them.
2002-09-30 14:04:54 +02:00
|
|
|
|
/* True if CPU has a dror instruction. */
|
|
|
|
|
#define CPU_HAS_DROR(CPU) ((CPU) == CPU_VR5400 || (CPU) == CPU_VR5500)
|
|
|
|
|
|
|
|
|
|
/* True if CPU has a ror instruction. */
|
|
|
|
|
#define CPU_HAS_ROR(CPU) CPU_HAS_DROR (CPU)
|
|
|
|
|
|
2000-09-07 14:45:56 +02:00
|
|
|
|
/* Whether the processor uses hardware interlocks to protect
|
1999-05-03 09:29:11 +02:00
|
|
|
|
reads from the HI and LO registers, and thus does not
|
2001-06-29 23:27:43 +02:00
|
|
|
|
require nops to be inserted. */
|
1999-05-03 09:29:11 +02:00
|
|
|
|
|
2003-06-29 21:41:33 +02:00
|
|
|
|
#define hilo_interlocks (mips_opts.arch == CPU_R4010 \
|
|
|
|
|
|| mips_opts.arch == CPU_VR5500 \
|
2003-07-15 09:50:39 +02:00
|
|
|
|
|| mips_opts.arch == CPU_RM7000 \
|
2003-06-29 21:41:33 +02:00
|
|
|
|
|| mips_opts.arch == CPU_SB1 \
|
1999-05-03 09:29:11 +02:00
|
|
|
|
)
|
|
|
|
|
|
|
|
|
|
/* Whether the processor uses hardware interlocks to protect reads
|
2004-01-09 03:16:30 +01:00
|
|
|
|
from the GPRs after they are loaded from memory, and thus does not
|
|
|
|
|
require nops to be inserted. This applies to instructions marked
|
|
|
|
|
INSN_LOAD_MEMORY_DELAY. These nops are only required at MIPS ISA
|
|
|
|
|
level I. */
|
1999-05-03 09:29:11 +02:00
|
|
|
|
#define gpr_interlocks \
|
2000-12-01 22:35:38 +01:00
|
|
|
|
(mips_opts.isa != ISA_MIPS1 \
|
2003-06-29 21:41:33 +02:00
|
|
|
|
|| mips_opts.arch == CPU_VR5400 \
|
|
|
|
|
|| mips_opts.arch == CPU_VR5500 \
|
|
|
|
|
|| mips_opts.arch == CPU_R3900)
|
1999-05-03 09:29:11 +02:00
|
|
|
|
|
2004-01-09 03:16:30 +01:00
|
|
|
|
/* Whether the processor uses hardware interlocks to avoid delays
|
|
|
|
|
required by coprocessor instructions, and thus does not require
|
|
|
|
|
nops to be inserted. This applies to instructions marked
|
|
|
|
|
INSN_LOAD_COPROC_DELAY, INSN_COPROC_MOVE_DELAY, and to delays
|
|
|
|
|
between instructions marked INSN_WRITE_COND_CODE and ones marked
|
|
|
|
|
INSN_READ_COND_CODE. These nops are only required at MIPS ISA
|
|
|
|
|
levels I, II, and III. */
|
2000-09-07 14:45:56 +02:00
|
|
|
|
/* Itbl support may require additional care here. */
|
2004-01-09 03:16:30 +01:00
|
|
|
|
#define cop_interlocks \
|
|
|
|
|
((mips_opts.isa != ISA_MIPS1 \
|
|
|
|
|
&& mips_opts.isa != ISA_MIPS2 \
|
|
|
|
|
&& mips_opts.isa != ISA_MIPS3) \
|
|
|
|
|
|| mips_opts.arch == CPU_R4300 \
|
|
|
|
|
|| mips_opts.arch == CPU_VR5400 \
|
|
|
|
|
|| mips_opts.arch == CPU_VR5500 \
|
|
|
|
|
|| mips_opts.arch == CPU_SB1 \
|
|
|
|
|
)
|
|
|
|
|
|
|
|
|
|
/* Whether the processor uses hardware interlocks to protect reads
|
|
|
|
|
from coprocessor registers after they are loaded from memory, and
|
|
|
|
|
thus does not require nops to be inserted. This applies to
|
|
|
|
|
instructions marked INSN_COPROC_MEMORY_DELAY. These nops are only
|
|
|
|
|
requires at MIPS ISA level I. */
|
|
|
|
|
#define cop_mem_interlocks (mips_opts.isa != ISA_MIPS1)
|
1999-05-03 09:29:11 +02:00
|
|
|
|
|
2000-02-21 21:00:33 +01:00
|
|
|
|
/* Is this a mfhi or mflo instruction? */
|
|
|
|
|
#define MF_HILO_INSN(PINFO) \
|
|
|
|
|
((PINFO & INSN_READ_HI) || (PINFO & INSN_READ_LO))
|
|
|
|
|
|
1999-05-03 09:29:11 +02:00
|
|
|
|
/* MIPS PIC level. */
|
|
|
|
|
|
2002-09-05 02:01:18 +02:00
|
|
|
|
enum mips_pic_level mips_pic;
|
1999-05-03 09:29:11 +02:00
|
|
|
|
|
2002-05-28 21:23:09 +02:00
|
|
|
|
/* 1 if we should generate 32 bit offsets from the $gp register in
|
1999-05-03 09:29:11 +02:00
|
|
|
|
SVR4_PIC mode. Currently has no meaning in other modes. */
|
2002-05-28 21:23:09 +02:00
|
|
|
|
static int mips_big_got = 0;
|
1999-05-03 09:29:11 +02:00
|
|
|
|
|
|
|
|
|
/* 1 if trap instructions should used for overflow rather than break
|
|
|
|
|
instructions. */
|
2002-05-28 21:23:09 +02:00
|
|
|
|
static int mips_trap = 0;
|
1999-05-03 09:29:11 +02:00
|
|
|
|
|
2000-07-15 00:23:33 +02:00
|
|
|
|
/* 1 if double width floating point constants should not be constructed
|
2001-10-12 01:56:33 +02:00
|
|
|
|
by assembling two single width halves into two single width floating
|
2000-07-15 00:23:33 +02:00
|
|
|
|
point registers which just happen to alias the double width destination
|
|
|
|
|
register. On some architectures this aliasing can be disabled by a bit
|
2000-07-15 00:28:24 +02:00
|
|
|
|
in the status register, and the setting of this bit cannot be determined
|
2000-07-15 00:23:33 +02:00
|
|
|
|
automatically at assemble time. */
|
|
|
|
|
static int mips_disable_float_construction;
|
|
|
|
|
|
1999-05-03 09:29:11 +02:00
|
|
|
|
/* Non-zero if any .set noreorder directives were used. */
|
|
|
|
|
|
|
|
|
|
static int mips_any_noreorder;
|
|
|
|
|
|
2000-02-21 21:00:33 +01:00
|
|
|
|
/* Non-zero if nops should be inserted when the register referenced in
|
|
|
|
|
an mfhi/mflo instruction is read in the next two instructions. */
|
|
|
|
|
static int mips_7000_hilo_fix;
|
|
|
|
|
|
1999-05-03 09:29:11 +02:00
|
|
|
|
/* The size of the small data section. */
|
2000-09-14 03:47:38 +02:00
|
|
|
|
static unsigned int g_switch_value = 8;
|
1999-05-03 09:29:11 +02:00
|
|
|
|
/* Whether the -G option was used. */
|
|
|
|
|
static int g_switch_seen = 0;
|
|
|
|
|
|
|
|
|
|
#define N_RMASK 0xc4
|
|
|
|
|
#define N_VFP 0xd4
|
|
|
|
|
|
|
|
|
|
/* If we can determine in advance that GP optimization won't be
|
|
|
|
|
possible, we can skip the relaxation stuff that tries to produce
|
|
|
|
|
GP-relative references. This makes delay slot optimization work
|
|
|
|
|
better.
|
|
|
|
|
|
|
|
|
|
This function can only provide a guess, but it seems to work for
|
1999-09-28 06:13:25 +02:00
|
|
|
|
gcc output. It needs to guess right for gcc, otherwise gcc
|
|
|
|
|
will put what it thinks is a GP-relative instruction in a branch
|
|
|
|
|
delay slot.
|
1999-05-03 09:29:11 +02:00
|
|
|
|
|
|
|
|
|
I don't know if a fix is needed for the SVR4_PIC mode. I've only
|
|
|
|
|
fixed it for the non-PIC mode. KR 95/04/07 */
|
2003-06-30 14:44:25 +02:00
|
|
|
|
static int nopic_need_relax (symbolS *, int);
|
1999-05-03 09:29:11 +02:00
|
|
|
|
|
|
|
|
|
/* handle of the OPCODE hash table */
|
|
|
|
|
static struct hash_control *op_hash = NULL;
|
|
|
|
|
|
|
|
|
|
/* The opcode hash table we use for the mips16. */
|
|
|
|
|
static struct hash_control *mips16_op_hash = NULL;
|
|
|
|
|
|
|
|
|
|
/* This array holds the chars that always start a comment. If the
|
|
|
|
|
pre-processor is disabled, these aren't very useful */
|
|
|
|
|
const char comment_chars[] = "#";
|
|
|
|
|
|
|
|
|
|
/* This array holds the chars that only start a comment at the beginning of
|
|
|
|
|
a line. If the line seems to have the form '# 123 filename'
|
|
|
|
|
.line and .file directives will appear in the pre-processed output */
|
|
|
|
|
/* Note that input_file.c hand checks for '#' at the beginning of the
|
|
|
|
|
first line of the input file. This is because the compiler outputs
|
2000-09-07 14:45:56 +02:00
|
|
|
|
#NO_APP at the beginning of its output. */
|
1999-05-03 09:29:11 +02:00
|
|
|
|
/* Also note that C style comments are always supported. */
|
|
|
|
|
const char line_comment_chars[] = "#";
|
|
|
|
|
|
2000-09-07 14:45:56 +02:00
|
|
|
|
/* This array holds machine specific line separator characters. */
|
2000-06-09 02:00:04 +02:00
|
|
|
|
const char line_separator_chars[] = ";";
|
1999-05-03 09:29:11 +02:00
|
|
|
|
|
|
|
|
|
/* Chars that can be used to separate mant from exp in floating point nums */
|
|
|
|
|
const char EXP_CHARS[] = "eE";
|
|
|
|
|
|
|
|
|
|
/* Chars that mean this number is a floating point constant */
|
|
|
|
|
/* As in 0f12.456 */
|
|
|
|
|
/* or 0d1.2345e12 */
|
|
|
|
|
const char FLT_CHARS[] = "rRsSfFdDxXpP";
|
|
|
|
|
|
|
|
|
|
/* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
|
|
|
|
|
changed in read.c . Ideally it shouldn't have to know about it at all,
|
|
|
|
|
but nothing is ideal around here.
|
|
|
|
|
*/
|
|
|
|
|
|
|
|
|
|
static char *insn_error;
|
|
|
|
|
|
|
|
|
|
static int auto_align = 1;
|
|
|
|
|
|
|
|
|
|
/* When outputting SVR4 PIC code, the assembler needs to know the
|
|
|
|
|
offset in the stack frame from which to restore the $gp register.
|
|
|
|
|
This is set by the .cprestore pseudo-op, and saved in this
|
|
|
|
|
variable. */
|
|
|
|
|
static offsetT mips_cprestore_offset = -1;
|
|
|
|
|
|
2003-11-22 03:35:31 +01:00
|
|
|
|
/* Similar for NewABI PIC code, where $gp is callee-saved. NewABI has some
|
2001-10-10 03:08:35 +02:00
|
|
|
|
more optimizations, it can use a register value instead of a memory-saved
|
2001-12-04 15:38:48 +01:00
|
|
|
|
offset and even an other register than $gp as global pointer. */
|
2001-10-10 03:08:35 +02:00
|
|
|
|
static offsetT mips_cpreturn_offset = -1;
|
|
|
|
|
static int mips_cpreturn_register = -1;
|
|
|
|
|
static int mips_gp_register = GP;
|
2002-05-30 23:06:14 +02:00
|
|
|
|
static int mips_gprel_offset = 0;
|
2001-10-10 03:08:35 +02:00
|
|
|
|
|
2002-01-05 20:06:52 +01:00
|
|
|
|
/* Whether mips_cprestore_offset has been set in the current function
|
|
|
|
|
(or whether it has already been warned about, if not). */
|
|
|
|
|
static int mips_cprestore_valid = 0;
|
|
|
|
|
|
1999-05-03 09:29:11 +02:00
|
|
|
|
/* This is the register which holds the stack frame, as set by the
|
|
|
|
|
.frame pseudo-op. This is needed to implement .cprestore. */
|
|
|
|
|
static int mips_frame_reg = SP;
|
|
|
|
|
|
2002-01-05 20:06:52 +01:00
|
|
|
|
/* Whether mips_frame_reg has been set in the current function
|
|
|
|
|
(or whether it has already been warned about, if not). */
|
|
|
|
|
static int mips_frame_reg_valid = 0;
|
|
|
|
|
|
1999-05-03 09:29:11 +02:00
|
|
|
|
/* To output NOP instructions correctly, we need to keep information
|
|
|
|
|
about the previous two instructions. */
|
|
|
|
|
|
|
|
|
|
/* Whether we are optimizing. The default value of 2 means to remove
|
|
|
|
|
unneeded NOPs and swap branch instructions when possible. A value
|
|
|
|
|
of 1 means to not swap branches. A value of 0 means to always
|
|
|
|
|
insert NOPs. */
|
|
|
|
|
static int mips_optimize = 2;
|
|
|
|
|
|
|
|
|
|
/* Debugging level. -g sets this to 2. -gN sets this to N. -g0 is
|
|
|
|
|
equivalent to seeing no -g option at all. */
|
|
|
|
|
static int mips_debug = 0;
|
|
|
|
|
|
|
|
|
|
/* The previous instruction. */
|
|
|
|
|
static struct mips_cl_insn prev_insn;
|
|
|
|
|
|
|
|
|
|
/* The instruction before prev_insn. */
|
|
|
|
|
static struct mips_cl_insn prev_prev_insn;
|
|
|
|
|
|
|
|
|
|
/* If we don't want information for prev_insn or prev_prev_insn, we
|
|
|
|
|
point the insn_mo field at this dummy integer. */
|
2000-05-30 00:05:27 +02:00
|
|
|
|
static const struct mips_opcode dummy_opcode = { NULL, NULL, 0, 0, 0, 0 };
|
1999-05-03 09:29:11 +02:00
|
|
|
|
|
|
|
|
|
/* Non-zero if prev_insn is valid. */
|
|
|
|
|
static int prev_insn_valid;
|
|
|
|
|
|
|
|
|
|
/* The frag for the previous instruction. */
|
|
|
|
|
static struct frag *prev_insn_frag;
|
|
|
|
|
|
|
|
|
|
/* The offset into prev_insn_frag for the previous instruction. */
|
|
|
|
|
static long prev_insn_where;
|
|
|
|
|
|
|
|
|
|
/* The reloc type for the previous instruction, if any. */
|
2001-10-04 22:07:00 +02:00
|
|
|
|
static bfd_reloc_code_real_type prev_insn_reloc_type[3];
|
1999-05-03 09:29:11 +02:00
|
|
|
|
|
|
|
|
|
/* The reloc for the previous instruction, if any. */
|
2001-10-04 22:07:00 +02:00
|
|
|
|
static fixS *prev_insn_fixp[3];
|
1999-05-03 09:29:11 +02:00
|
|
|
|
|
|
|
|
|
/* Non-zero if the previous instruction was in a delay slot. */
|
|
|
|
|
static int prev_insn_is_delay_slot;
|
|
|
|
|
|
|
|
|
|
/* Non-zero if the previous instruction was in a .set noreorder. */
|
|
|
|
|
static int prev_insn_unreordered;
|
|
|
|
|
|
|
|
|
|
/* Non-zero if the previous instruction uses an extend opcode (if
|
|
|
|
|
mips16). */
|
|
|
|
|
static int prev_insn_extended;
|
|
|
|
|
|
|
|
|
|
/* Non-zero if the previous previous instruction was in a .set
|
|
|
|
|
noreorder. */
|
|
|
|
|
static int prev_prev_insn_unreordered;
|
|
|
|
|
|
|
|
|
|
/* If this is set, it points to a frag holding nop instructions which
|
|
|
|
|
were inserted before the start of a noreorder section. If those
|
|
|
|
|
nops turn out to be unnecessary, the size of the frag can be
|
|
|
|
|
decreased. */
|
|
|
|
|
static fragS *prev_nop_frag;
|
|
|
|
|
|
|
|
|
|
/* The number of nop instructions we created in prev_nop_frag. */
|
|
|
|
|
static int prev_nop_frag_holds;
|
|
|
|
|
|
|
|
|
|
/* The number of nop instructions that we know we need in
|
2000-09-07 14:45:56 +02:00
|
|
|
|
prev_nop_frag. */
|
1999-05-03 09:29:11 +02:00
|
|
|
|
static int prev_nop_frag_required;
|
|
|
|
|
|
|
|
|
|
/* The number of instructions we've seen since prev_nop_frag. */
|
|
|
|
|
static int prev_nop_frag_since;
|
|
|
|
|
|
|
|
|
|
/* For ECOFF and ELF, relocations against symbols are done in two
|
|
|
|
|
parts, with a HI relocation and a LO relocation. Each relocation
|
|
|
|
|
has only 16 bits of space to store an addend. This means that in
|
|
|
|
|
order for the linker to handle carries correctly, it must be able
|
|
|
|
|
to locate both the HI and the LO relocation. This means that the
|
|
|
|
|
relocations must appear in order in the relocation table.
|
|
|
|
|
|
|
|
|
|
In order to implement this, we keep track of each unmatched HI
|
|
|
|
|
relocation. We then sort them so that they immediately precede the
|
2000-09-07 14:45:56 +02:00
|
|
|
|
corresponding LO relocation. */
|
1999-05-03 09:29:11 +02:00
|
|
|
|
|
2000-12-12 20:29:24 +01:00
|
|
|
|
struct mips_hi_fixup
|
|
|
|
|
{
|
1999-05-03 09:29:11 +02:00
|
|
|
|
/* Next HI fixup. */
|
|
|
|
|
struct mips_hi_fixup *next;
|
|
|
|
|
/* This fixup. */
|
|
|
|
|
fixS *fixp;
|
|
|
|
|
/* The section this fixup is in. */
|
|
|
|
|
segT seg;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
/* The list of unmatched HI relocs. */
|
|
|
|
|
|
|
|
|
|
static struct mips_hi_fixup *mips_hi_fixup_list;
|
|
|
|
|
|
2003-02-21 11:28:27 +01:00
|
|
|
|
/* The frag containing the last explicit relocation operator.
|
|
|
|
|
Null if explicit relocations have not been used. */
|
|
|
|
|
|
|
|
|
|
static fragS *prev_reloc_op_frag;
|
|
|
|
|
|
1999-05-03 09:29:11 +02:00
|
|
|
|
/* Map normal MIPS register numbers to mips16 register numbers. */
|
|
|
|
|
|
|
|
|
|
#define X ILLEGAL_REG
|
2000-12-12 20:29:24 +01:00
|
|
|
|
static const int mips32_to_16_reg_map[] =
|
|
|
|
|
{
|
1999-05-03 09:29:11 +02:00
|
|
|
|
X, X, 2, 3, 4, 5, 6, 7,
|
|
|
|
|
X, X, X, X, X, X, X, X,
|
|
|
|
|
0, 1, X, X, X, X, X, X,
|
|
|
|
|
X, X, X, X, X, X, X, X
|
|
|
|
|
};
|
|
|
|
|
#undef X
|
|
|
|
|
|
|
|
|
|
/* Map mips16 register numbers to normal MIPS register numbers. */
|
|
|
|
|
|
2000-12-12 20:29:24 +01:00
|
|
|
|
static const unsigned int mips16_to_32_reg_map[] =
|
|
|
|
|
{
|
1999-05-03 09:29:11 +02:00
|
|
|
|
16, 17, 2, 3, 4, 5, 6, 7
|
|
|
|
|
};
|
[gas/]
* doc/c-mips.texi: Add entries for -march=vr4120,vr4130,vr4181,
vr5400 and vr5500. Add entry for -mfix-vr4122-bugs.
* config/tc-mips.c (CPU_HAS_DROR, CPU_HAS_ROR): New macros.
(hilo_interlocks): True for CPU_VR5500.
(gpr_interlocks, cop_interlocks): True for CPU_VR5400 and CPU_VR5500.
(mips_fix_vr4122_bugs): New.
(append_insn): Work around 4122 errors if mips_fix_vr4122_bugs.
(mips_emit_delays): Likewise.
(macro2) [M_DROLI]: Use dror or dror32 if CPU_HAS_DROR.
[M_ROLI]: Likewise ror if CPU_HAS_ROR.
(validate_mips_insn, mips_ip): Handle '[', ']', 'e' and '%'.
(OPTION_FIX_VR4122, OPTION_NO_FIX_VR4122): New options.
(md_longopts): Add -mfix-vr4122-bugs and -no-mfix-vr4122-bugs.
(OPTION_ELF_BASE): Bump.
(md_parse_option): Handle the new options.
(mips_cpu_info_table): Add entries for vr4120, vr4130, vr4181,
vr5400 and vr5500.
[gas/testsuite/]
* gas/mips/mips4100.[sd]: Move dmadd16 and madd16 checks to...
* gas/mips/vr4111.[sd]: ...this new test.
* gas/mips/vr4120.[sd],
* gas/mips/vr4122.[sd],
* gas/mips/vr5400.[sd],
* gas/mips/vr5500.[sd]: New tests.
* mips.exp: Run them.
2002-09-30 14:04:54 +02:00
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static int mips_fix_4122_bugs;
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2002-10-12 07:23:33 +02:00
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/* We don't relax branches by default, since this causes us to expand
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`la .l2 - .l1' if there's a branch between .l1 and .l2, because we
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fail to compute the offset before expanding the macro to the most
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efficient expansion. */
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static int mips_relax_branch;
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1999-05-03 09:29:11 +02:00
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/* Since the MIPS does not have multiple forms of PC relative
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instructions, we do not have to do relaxing as is done on other
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platforms. However, we do have to handle GP relative addressing
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correctly, which turns out to be a similar problem.
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Every macro that refers to a symbol can occur in (at least) two
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forms, one with GP relative addressing and one without. For
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example, loading a global variable into a register generally uses
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a macro instruction like this:
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lw $4,i
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If i can be addressed off the GP register (this is true if it is in
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the .sbss or .sdata section, or if it is known to be smaller than
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the -G argument) this will generate the following instruction:
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lw $4,i($gp)
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This instruction will use a GPREL reloc. If i can not be addressed
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off the GP register, the following instruction sequence will be used:
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lui $at,i
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lw $4,i($at)
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In this case the first instruction will have a HI16 reloc, and the
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second reloc will have a LO16 reloc. Both relocs will be against
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the symbol i.
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The issue here is that we may not know whether i is GP addressable
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until after we see the instruction that uses it. Therefore, we
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want to be able to choose the final instruction sequence only at
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the end of the assembly. This is similar to the way other
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platforms choose the size of a PC relative instruction only at the
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end of assembly.
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When generating position independent code we do not use GP
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addressing in quite the same way, but the issue still arises as
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external symbols and local symbols must be handled differently.
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We handle these issues by actually generating both possible
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instruction sequences. The longer one is put in a frag_var with
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type rs_machine_dependent. We encode what to do with the frag in
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the subtype field. We encode (1) the number of existing bytes to
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replace, (2) the number of new bytes to use, (3) the offset from
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the start of the existing bytes to the first reloc we must generate
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(that is, the offset is applied from the start of the existing
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bytes after they are replaced by the new bytes, if any), (4) the
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offset from the start of the existing bytes to the second reloc,
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(5) whether a third reloc is needed (the third reloc is always four
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bytes after the second reloc), and (6) whether to warn if this
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variant is used (this is sometimes needed if .set nomacro or .set
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noat is in effect). All these numbers are reasonably small.
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Generating two instruction sequences must be handled carefully to
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ensure that delay slots are handled correctly. Fortunately, there
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are a limited number of cases. When the second instruction
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sequence is generated, append_insn is directed to maintain the
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existing delay slot information, so it continues to apply to any
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code after the second instruction sequence. This means that the
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second instruction sequence must not impose any requirements not
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required by the first instruction sequence.
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These variant frags are then handled in functions called by the
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|
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machine independent code. md_estimate_size_before_relax returns
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the final size of the frag. md_convert_frag sets up the final form
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of the frag. tc_gen_reloc adjust the first reloc and adds a second
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one if needed. */
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#define RELAX_ENCODE(old, new, reloc1, reloc2, reloc3, warn) \
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((relax_substateT) \
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|
(((old) << 23) \
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| ((new) << 16) \
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| (((reloc1) + 64) << 9) \
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| (((reloc2) + 64) << 2) \
|
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| ((reloc3) ? (1 << 1) : 0) \
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|
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| ((warn) ? 1 : 0)))
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|
#define RELAX_OLD(i) (((i) >> 23) & 0x7f)
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#define RELAX_NEW(i) (((i) >> 16) & 0x7f)
|
2001-08-07 15:15:26 +02:00
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#define RELAX_RELOC1(i) ((valueT) (((i) >> 9) & 0x7f) - 64)
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#define RELAX_RELOC2(i) ((valueT) (((i) >> 2) & 0x7f) - 64)
|
1999-05-03 09:29:11 +02:00
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#define RELAX_RELOC3(i) (((i) >> 1) & 1)
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#define RELAX_WARN(i) ((i) & 1)
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|
2002-10-12 07:23:33 +02:00
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/* Branch without likely bit. If label is out of range, we turn:
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beq reg1, reg2, label
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delay slot
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into
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bne reg1, reg2, 0f
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nop
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j label
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0: delay slot
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with the following opcode replacements:
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beq <-> bne
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blez <-> bgtz
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bltz <-> bgez
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bc1f <-> bc1t
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bltzal <-> bgezal (with jal label instead of j label)
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Even though keeping the delay slot instruction in the delay slot of
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the branch would be more efficient, it would be very tricky to do
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correctly, because we'd have to introduce a variable frag *after*
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the delay slot instruction, and expand that instead. Let's do it
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the easy way for now, even if the branch-not-taken case now costs
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one additional instruction. Out-of-range branches are not supposed
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to be common, anyway.
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Branch likely. If label is out of range, we turn:
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beql reg1, reg2, label
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delay slot (annulled if branch not taken)
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into
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beql reg1, reg2, 1f
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nop
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beql $0, $0, 2f
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nop
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1: j[al] label
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delay slot (executed only if branch taken)
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2:
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It would be possible to generate a shorter sequence by losing the
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likely bit, generating something like:
|
2002-11-30 09:39:46 +01:00
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|
2002-10-12 07:23:33 +02:00
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bne reg1, reg2, 0f
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nop
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j[al] label
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delay slot (executed only if branch taken)
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0:
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beql -> bne
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bnel -> beq
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blezl -> bgtz
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bgtzl -> blez
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bltzl -> bgez
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bgezl -> bltz
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bc1fl -> bc1t
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bc1tl -> bc1f
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bltzall -> bgezal (with jal label instead of j label)
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bgezall -> bltzal (ditto)
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but it's not clear that it would actually improve performance. */
|
2002-12-12 05:40:07 +01:00
|
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|
#define RELAX_BRANCH_ENCODE(uncond, likely, link, toofar) \
|
2002-10-12 07:23:33 +02:00
|
|
|
|
((relax_substateT) \
|
|
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|
|
(0xc0000000 \
|
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|
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| ((toofar) ? 1 : 0) \
|
|
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| ((link) ? 2 : 0) \
|
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| ((likely) ? 4 : 0) \
|
2002-12-12 05:40:07 +01:00
|
|
|
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| ((uncond) ? 8 : 0)))
|
2002-10-12 07:23:33 +02:00
|
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|
#define RELAX_BRANCH_P(i) (((i) & 0xf0000000) == 0xc0000000)
|
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#define RELAX_BRANCH_UNCOND(i) (((i) & 8) != 0)
|
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|
|
#define RELAX_BRANCH_LIKELY(i) (((i) & 4) != 0)
|
|
|
|
|
#define RELAX_BRANCH_LINK(i) (((i) & 2) != 0)
|
2003-01-23 13:51:05 +01:00
|
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|
#define RELAX_BRANCH_TOOFAR(i) (((i) & 1) != 0)
|
2002-10-12 07:23:33 +02:00
|
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|
|
|
1999-05-03 09:29:11 +02:00
|
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|
|
/* For mips16 code, we use an entirely different form of relaxation.
|
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|
|
mips16 supports two versions of most instructions which take
|
|
|
|
|
immediate values: a small one which takes some small value, and a
|
|
|
|
|
larger one which takes a 16 bit value. Since branches also follow
|
|
|
|
|
this pattern, relaxing these values is required.
|
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|
|
|
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|
|
We can assemble both mips16 and normal MIPS code in a single
|
|
|
|
|
object. Therefore, we need to support this type of relaxation at
|
|
|
|
|
the same time that we support the relaxation described above. We
|
|
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|
|
use the high bit of the subtype field to distinguish these cases.
|
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|
|
|
|
|
|
|
The information we store for this type of relaxation is the
|
|
|
|
|
argument code found in the opcode file for this relocation, whether
|
|
|
|
|
the user explicitly requested a small or extended form, and whether
|
|
|
|
|
the relocation is in a jump or jal delay slot. That tells us the
|
|
|
|
|
size of the value, and how it should be stored. We also store
|
|
|
|
|
whether the fragment is considered to be extended or not. We also
|
|
|
|
|
store whether this is known to be a branch to a different section,
|
|
|
|
|
whether we have tried to relax this frag yet, and whether we have
|
|
|
|
|
ever extended a PC relative fragment because of a shift count. */
|
|
|
|
|
#define RELAX_MIPS16_ENCODE(type, small, ext, dslot, jal_dslot) \
|
|
|
|
|
(0x80000000 \
|
|
|
|
|
| ((type) & 0xff) \
|
|
|
|
|
| ((small) ? 0x100 : 0) \
|
|
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|
|
| ((ext) ? 0x200 : 0) \
|
|
|
|
|
| ((dslot) ? 0x400 : 0) \
|
|
|
|
|
| ((jal_dslot) ? 0x800 : 0))
|
2002-10-12 07:23:33 +02:00
|
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|
|
#define RELAX_MIPS16_P(i) (((i) & 0xc0000000) == 0x80000000)
|
1999-05-03 09:29:11 +02:00
|
|
|
|
#define RELAX_MIPS16_TYPE(i) ((i) & 0xff)
|
|
|
|
|
#define RELAX_MIPS16_USER_SMALL(i) (((i) & 0x100) != 0)
|
|
|
|
|
#define RELAX_MIPS16_USER_EXT(i) (((i) & 0x200) != 0)
|
|
|
|
|
#define RELAX_MIPS16_DSLOT(i) (((i) & 0x400) != 0)
|
|
|
|
|
#define RELAX_MIPS16_JAL_DSLOT(i) (((i) & 0x800) != 0)
|
|
|
|
|
#define RELAX_MIPS16_EXTENDED(i) (((i) & 0x1000) != 0)
|
|
|
|
|
#define RELAX_MIPS16_MARK_EXTENDED(i) ((i) | 0x1000)
|
|
|
|
|
#define RELAX_MIPS16_CLEAR_EXTENDED(i) ((i) &~ 0x1000)
|
|
|
|
|
#define RELAX_MIPS16_LONG_BRANCH(i) (((i) & 0x2000) != 0)
|
|
|
|
|
#define RELAX_MIPS16_MARK_LONG_BRANCH(i) ((i) | 0x2000)
|
|
|
|
|
#define RELAX_MIPS16_CLEAR_LONG_BRANCH(i) ((i) &~ 0x2000)
|
2002-09-18 23:33:07 +02:00
|
|
|
|
|
|
|
|
|
/* Is the given value a sign-extended 32-bit value? */
|
|
|
|
|
#define IS_SEXT_32BIT_NUM(x) \
|
|
|
|
|
(((x) &~ (offsetT) 0x7fffffff) == 0 \
|
|
|
|
|
|| (((x) &~ (offsetT) 0x7fffffff) == ~ (offsetT) 0x7fffffff))
|
|
|
|
|
|
|
|
|
|
/* Is the given value a sign-extended 16-bit value? */
|
|
|
|
|
#define IS_SEXT_16BIT_NUM(x) \
|
|
|
|
|
(((x) &~ (offsetT) 0x7fff) == 0 \
|
|
|
|
|
|| (((x) &~ (offsetT) 0x7fff) == ~ (offsetT) 0x7fff))
|
|
|
|
|
|
1999-05-03 09:29:11 +02:00
|
|
|
|
|
|
|
|
|
/* Prototypes for static functions. */
|
|
|
|
|
|
2003-06-30 14:44:25 +02:00
|
|
|
|
#define internalError() \
|
1999-05-03 09:29:11 +02:00
|
|
|
|
as_fatal (_("internal Error, line %d, %s"), __LINE__, __FILE__)
|
|
|
|
|
|
|
|
|
|
enum mips_regclass { MIPS_GR_REG, MIPS_FP_REG, MIPS16_REG };
|
|
|
|
|
|
2002-11-30 09:39:46 +01:00
|
|
|
|
static void append_insn
|
2003-06-30 14:44:25 +02:00
|
|
|
|
(char *place, struct mips_cl_insn *ip, expressionS *p,
|
|
|
|
|
bfd_reloc_code_real_type *r);
|
|
|
|
|
static void mips_no_prev_insn (int);
|
2002-11-30 09:39:46 +01:00
|
|
|
|
static void mips16_macro_build
|
2003-06-30 14:44:25 +02:00
|
|
|
|
(char *, int *, expressionS *, const char *, const char *, va_list);
|
|
|
|
|
static void load_register (int *, int, expressionS *, int);
|
|
|
|
|
static void macro (struct mips_cl_insn * ip);
|
|
|
|
|
static void mips16_macro (struct mips_cl_insn * ip);
|
1999-05-03 09:29:11 +02:00
|
|
|
|
#ifdef LOSING_COMPILER
|
2003-06-30 14:44:25 +02:00
|
|
|
|
static void macro2 (struct mips_cl_insn * ip);
|
1999-05-03 09:29:11 +02:00
|
|
|
|
#endif
|
2003-06-30 14:44:25 +02:00
|
|
|
|
static void mips_ip (char *str, struct mips_cl_insn * ip);
|
|
|
|
|
static void mips16_ip (char *str, struct mips_cl_insn * ip);
|
2002-11-30 09:39:46 +01:00
|
|
|
|
static void mips16_immed
|
2003-06-30 14:44:25 +02:00
|
|
|
|
(char *, unsigned int, int, offsetT, bfd_boolean, bfd_boolean, bfd_boolean,
|
|
|
|
|
unsigned long *, bfd_boolean *, unsigned short *);
|
2003-02-02 20:37:20 +01:00
|
|
|
|
static size_t my_getSmallExpression
|
2003-06-30 14:44:25 +02:00
|
|
|
|
(expressionS *, bfd_reloc_code_real_type *, char *);
|
|
|
|
|
static void my_getExpression (expressionS *, char *);
|
|
|
|
|
static void s_align (int);
|
|
|
|
|
static void s_change_sec (int);
|
|
|
|
|
static void s_change_section (int);
|
|
|
|
|
static void s_cons (int);
|
|
|
|
|
static void s_float_cons (int);
|
|
|
|
|
static void s_mips_globl (int);
|
|
|
|
|
static void s_option (int);
|
|
|
|
|
static void s_mipsset (int);
|
|
|
|
|
static void s_abicalls (int);
|
|
|
|
|
static void s_cpload (int);
|
|
|
|
|
static void s_cpsetup (int);
|
|
|
|
|
static void s_cplocal (int);
|
|
|
|
|
static void s_cprestore (int);
|
|
|
|
|
static void s_cpreturn (int);
|
|
|
|
|
static void s_gpvalue (int);
|
|
|
|
|
static void s_gpword (int);
|
|
|
|
|
static void s_gpdword (int);
|
|
|
|
|
static void s_cpadd (int);
|
|
|
|
|
static void s_insn (int);
|
|
|
|
|
static void md_obj_begin (void);
|
|
|
|
|
static void md_obj_end (void);
|
|
|
|
|
static void s_mips_ent (int);
|
|
|
|
|
static void s_mips_end (int);
|
|
|
|
|
static void s_mips_frame (int);
|
|
|
|
|
static void s_mips_mask (int reg_type);
|
|
|
|
|
static void s_mips_stab (int);
|
|
|
|
|
static void s_mips_weakext (int);
|
|
|
|
|
static void s_mips_file (int);
|
|
|
|
|
static void s_mips_loc (int);
|
|
|
|
|
static bfd_boolean pic_need_relax (symbolS *, asection *);
|
2002-10-12 07:23:33 +02:00
|
|
|
|
static int relaxed_branch_length (fragS *, asection *, int);
|
2003-06-30 14:44:25 +02:00
|
|
|
|
static int validate_mips_insn (const struct mips_opcode *);
|
2000-12-01 22:35:38 +01:00
|
|
|
|
|
|
|
|
|
/* Table and functions used to map between CPU/ISA names, and
|
|
|
|
|
ISA levels, and CPU numbers. */
|
|
|
|
|
|
2000-12-12 20:29:24 +01:00
|
|
|
|
struct mips_cpu_info
|
|
|
|
|
{
|
2000-12-01 22:35:38 +01:00
|
|
|
|
const char *name; /* CPU or ISA name. */
|
|
|
|
|
int is_isa; /* Is this an ISA? (If 0, a CPU.) */
|
|
|
|
|
int isa; /* ISA level. */
|
|
|
|
|
int cpu; /* CPU number (default CPU if ISA). */
|
|
|
|
|
};
|
|
|
|
|
|
2003-06-30 14:44:25 +02:00
|
|
|
|
static const struct mips_cpu_info *mips_parse_cpu (const char *, const char *);
|
|
|
|
|
static const struct mips_cpu_info *mips_cpu_info_from_isa (int);
|
|
|
|
|
static const struct mips_cpu_info *mips_cpu_info_from_arch (int);
|
1999-05-03 09:29:11 +02:00
|
|
|
|
|
|
|
|
|
/* Pseudo-op table.
|
|
|
|
|
|
|
|
|
|
The following pseudo-ops from the Kane and Heinrich MIPS book
|
|
|
|
|
should be defined here, but are currently unsupported: .alias,
|
|
|
|
|
.galive, .gjaldef, .gjrlive, .livereg, .noalias.
|
|
|
|
|
|
|
|
|
|
The following pseudo-ops from the Kane and Heinrich MIPS book are
|
|
|
|
|
specific to the type of debugging information being generated, and
|
|
|
|
|
should be defined by the object format: .aent, .begin, .bend,
|
|
|
|
|
.bgnb, .end, .endb, .ent, .fmask, .frame, .loc, .mask, .verstamp,
|
|
|
|
|
.vreg.
|
|
|
|
|
|
|
|
|
|
The following pseudo-ops from the Kane and Heinrich MIPS book are
|
|
|
|
|
not MIPS CPU specific, but are also not specific to the object file
|
|
|
|
|
format. This file is probably the best place to define them, but
|
|
|
|
|
they are not currently supported: .asm0, .endr, .lab, .repeat,
|
|
|
|
|
.struct. */
|
|
|
|
|
|
2000-12-12 20:29:24 +01:00
|
|
|
|
static const pseudo_typeS mips_pseudo_table[] =
|
|
|
|
|
{
|
2000-12-05 19:51:08 +01:00
|
|
|
|
/* MIPS specific pseudo-ops. */
|
1999-05-03 09:29:11 +02:00
|
|
|
|
{"option", s_option, 0},
|
|
|
|
|
{"set", s_mipsset, 0},
|
|
|
|
|
{"rdata", s_change_sec, 'r'},
|
|
|
|
|
{"sdata", s_change_sec, 's'},
|
|
|
|
|
{"livereg", s_ignore, 0},
|
|
|
|
|
{"abicalls", s_abicalls, 0},
|
|
|
|
|
{"cpload", s_cpload, 0},
|
2001-10-10 03:08:35 +02:00
|
|
|
|
{"cpsetup", s_cpsetup, 0},
|
|
|
|
|
{"cplocal", s_cplocal, 0},
|
1999-05-03 09:29:11 +02:00
|
|
|
|
{"cprestore", s_cprestore, 0},
|
2001-10-10 03:08:35 +02:00
|
|
|
|
{"cpreturn", s_cpreturn, 0},
|
|
|
|
|
{"gpvalue", s_gpvalue, 0},
|
1999-05-03 09:29:11 +02:00
|
|
|
|
{"gpword", s_gpword, 0},
|
2002-10-13 23:22:49 +02:00
|
|
|
|
{"gpdword", s_gpdword, 0},
|
1999-05-03 09:29:11 +02:00
|
|
|
|
{"cpadd", s_cpadd, 0},
|
|
|
|
|
{"insn", s_insn, 0},
|
|
|
|
|
|
2000-12-05 19:51:08 +01:00
|
|
|
|
/* Relatively generic pseudo-ops that happen to be used on MIPS
|
1999-05-03 09:29:11 +02:00
|
|
|
|
chips. */
|
|
|
|
|
{"asciiz", stringer, 1},
|
|
|
|
|
{"bss", s_change_sec, 'b'},
|
|
|
|
|
{"err", s_err, 0},
|
|
|
|
|
{"half", s_cons, 1},
|
|
|
|
|
{"dword", s_cons, 3},
|
|
|
|
|
{"weakext", s_mips_weakext, 0},
|
|
|
|
|
|
2000-12-05 19:51:08 +01:00
|
|
|
|
/* These pseudo-ops are defined in read.c, but must be overridden
|
1999-05-03 09:29:11 +02:00
|
|
|
|
here for one reason or another. */
|
|
|
|
|
{"align", s_align, 0},
|
|
|
|
|
{"byte", s_cons, 0},
|
|
|
|
|
{"data", s_change_sec, 'd'},
|
|
|
|
|
{"double", s_float_cons, 'd'},
|
|
|
|
|
{"float", s_float_cons, 'f'},
|
|
|
|
|
{"globl", s_mips_globl, 0},
|
|
|
|
|
{"global", s_mips_globl, 0},
|
|
|
|
|
{"hword", s_cons, 1},
|
|
|
|
|
{"int", s_cons, 2},
|
|
|
|
|
{"long", s_cons, 2},
|
|
|
|
|
{"octa", s_cons, 4},
|
|
|
|
|
{"quad", s_cons, 3},
|
2002-08-17 17:09:29 +02:00
|
|
|
|
{"section", s_change_section, 0},
|
1999-05-03 09:29:11 +02:00
|
|
|
|
{"short", s_cons, 1},
|
|
|
|
|
{"single", s_float_cons, 'f'},
|
|
|
|
|
{"stabn", s_mips_stab, 'n'},
|
|
|
|
|
{"text", s_change_sec, 't'},
|
|
|
|
|
{"word", s_cons, 2},
|
2001-06-07 18:52:19 +02:00
|
|
|
|
|
|
|
|
|
{ "extern", ecoff_directive_extern, 0},
|
|
|
|
|
|
2000-05-30 00:05:27 +02:00
|
|
|
|
{ NULL, NULL, 0 },
|
1999-05-03 09:29:11 +02:00
|
|
|
|
};
|
|
|
|
|
|
2000-12-12 20:29:24 +01:00
|
|
|
|
static const pseudo_typeS mips_nonecoff_pseudo_table[] =
|
|
|
|
|
{
|
2000-12-05 19:51:08 +01:00
|
|
|
|
/* These pseudo-ops should be defined by the object file format.
|
|
|
|
|
However, a.out doesn't support them, so we have versions here. */
|
1999-05-03 09:29:11 +02:00
|
|
|
|
{"aent", s_mips_ent, 1},
|
|
|
|
|
{"bgnb", s_ignore, 0},
|
|
|
|
|
{"end", s_mips_end, 0},
|
|
|
|
|
{"endb", s_ignore, 0},
|
|
|
|
|
{"ent", s_mips_ent, 0},
|
2002-06-08 07:37:29 +02:00
|
|
|
|
{"file", s_mips_file, 0},
|
1999-05-03 09:29:11 +02:00
|
|
|
|
{"fmask", s_mips_mask, 'F'},
|
|
|
|
|
{"frame", s_mips_frame, 0},
|
2002-06-08 07:37:29 +02:00
|
|
|
|
{"loc", s_mips_loc, 0},
|
1999-05-03 09:29:11 +02:00
|
|
|
|
{"mask", s_mips_mask, 'R'},
|
|
|
|
|
{"verstamp", s_ignore, 0},
|
2000-05-30 00:05:27 +02:00
|
|
|
|
{ NULL, NULL, 0 },
|
1999-05-03 09:29:11 +02:00
|
|
|
|
};
|
|
|
|
|
|
2003-06-30 14:44:25 +02:00
|
|
|
|
extern void pop_insert (const pseudo_typeS *);
|
1999-05-03 09:29:11 +02:00
|
|
|
|
|
|
|
|
|
void
|
2003-06-30 14:44:25 +02:00
|
|
|
|
mips_pop_insert (void)
|
1999-05-03 09:29:11 +02:00
|
|
|
|
{
|
|
|
|
|
pop_insert (mips_pseudo_table);
|
|
|
|
|
if (! ECOFF_DEBUGGING)
|
|
|
|
|
pop_insert (mips_nonecoff_pseudo_table);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/* Symbols labelling the current insn. */
|
|
|
|
|
|
2000-12-12 20:29:24 +01:00
|
|
|
|
struct insn_label_list
|
|
|
|
|
{
|
1999-05-03 09:29:11 +02:00
|
|
|
|
struct insn_label_list *next;
|
|
|
|
|
symbolS *label;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
static struct insn_label_list *insn_labels;
|
|
|
|
|
static struct insn_label_list *free_insn_labels;
|
|
|
|
|
|
2003-06-30 14:44:25 +02:00
|
|
|
|
static void mips_clear_insn_labels (void);
|
1999-05-03 09:29:11 +02:00
|
|
|
|
|
|
|
|
|
static inline void
|
2003-06-30 14:44:25 +02:00
|
|
|
|
mips_clear_insn_labels (void)
|
1999-05-03 09:29:11 +02:00
|
|
|
|
{
|
|
|
|
|
register struct insn_label_list **pl;
|
|
|
|
|
|
|
|
|
|
for (pl = &free_insn_labels; *pl != NULL; pl = &(*pl)->next)
|
|
|
|
|
;
|
|
|
|
|
*pl = insn_labels;
|
|
|
|
|
insn_labels = NULL;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static char *expr_end;
|
|
|
|
|
|
|
|
|
|
/* Expressions which appear in instructions. These are set by
|
|
|
|
|
mips_ip. */
|
|
|
|
|
|
|
|
|
|
static expressionS imm_expr;
|
[ bfd/ChangeLog ]
2003-09-30 Chris Demetriou <cgd@broadcom.com>
* archures.c (bfd_mach_mipsisa64r2): New define.
* bfd-in2.h: Regenerate.
* aoutx.h (NAME(aout,machine_type)): Handle bfd_mach_mipsisa64r2.
* cpu-mips.c (I_mipsisa64r2): New enum value.
(arch_info_struct): Add entry for I_mipsisa64r2.
* elfxx-mips.c (_bfd_elf_mips_mach)
(_bfd_mips_elf_print_private_bfd_data): Handle E_MIPS_ARCH_64R2.
(mips_set_isa_flags): Add bfd_mach_mipsisa64r2 case.
(mips_mach_extensions): Add entry for bfd_mach_mipsisa64r2.
[ binutils/ChangeLog ]
2003-09-30 Chris Demetriou <cgd@broadcom.com>
* readelf.c (get_machine_flags): Handle E_MIPS_ARCH_64R2.
[ gas/Changelog ]
2003-09-30 Chris Demetriou <cgd@broadcom.com>
* configure.in (mipsisa64r2, mipsisa64r2el, mipsisa64r2*): New CPUs.
* configure: Regenerate.
* config/tc-mips.c (imm2_expr): New variable.
(md_assemble, mips16_ip): Initialize imm2_expr.
(ISA_HAS_64BIT_REGS, ISA_HAS_DROR, ISA_HAS_ROR): Add ISA_MIPS64R2.
(macro_build): Handle +A, +B, +C, +E, +F, +G, and +H format operands.
(macro): Handle M_DEXT and M_DINS.
(validate_mips_insn): Handle +E, +F, +G, +H, and +I format operands.
(mips_ip): Likewise.
(OPTION_MIPS64R2): New define.
(md_longopts): New entry for -mips64r2 (OPTION_MIPS64R2).
OPTION_ASE_BASE): Increase to compensate for OPTION_MIPS64R2.
(md_parse_option): Handle OPTION_MIPS64R2.
(s_mipsset): Handle setting "mips64r2" ISA.
(mips_cpu_info_table): Add mips64r2.
(md_show_usage): Document -mips64r2 option.
* doc/as.texinfo: Docuemnt -mips64r2 option.
* doc/c-mips.texi: Likewise.
[ gas/testsuite/ChangeLog ]
2003-09-30 Chris Demetriou <cgd@broadcom.com>
* gas/mips/cp0-names-mips64r2.d: New file.
* gas/mips/cp0sel-names-mips64r2.d: New file.
* gas/mips/elf_arch_mips64r2.d: New file.
* gas/mips/hwr-names-mips64r2.d: New file.
* gas/mips/mips32r2-ill-fp64.l: New file.
* gas/mips/mips32r2-ill-fp64.s: New file.
* gas/mips/mips64r2-ill.l: New file.
* gas/mips/mips64r2-ill.s: New file.
* gas/mips/mips64r2.d: New file.
* gas/mips/mips64r2.s: New file.
* gas/mips/mips.exp: Define "mips64r2" arch, and run new tests.
[ include/elf/ChangeLog ]
2003-09-30 Chris Demetriou <cgd@broadcom.com>
* mips.h (E_MIPS_ARCH_64R2): New define.
[ include/opcode/ChangeLog ]
2003-09-30 Chris Demetriou <cgd@broadcom.com>
* mips.h: Document +E, +F, +G, +H, and +I operand types.
Update documentation of I, +B and +C operand types.
(INSN_ISA64R2, ISA_MIPS64R2, CPU_MIPS64R2): New defines.
(M_DEXT, M_DINS): New enum values.
[ ld/ChangeLog ]
2003-09-30 Chris Demetriou <cgd@broadcom.com>
* ldmain.c (get_emulation): Ignore "-mips64r2".
[ ld/testsuite/ChangeLog ]
2003-09-30 Chris Demetriou <cgd@broadcom.com>
* ld-mips-elf/mips-elf-flags.exp: Add tests for combinations
with MIPS64r2.
[ opcodes/ChangeLog ]
2003-09-30 Chris Demetriou <cgd@broadcom.com>
* mips-dis.c (mips_arch_choices): Add entry for "mips64r2"
(print_insn_args): Add handing for +E, +F, +G, and +H.
* mips-opc.c (I65): New define for MIPS64r2.
(mips_builtin_opcodes): Add "dext", "dextm", "dextu", "dins",
"dinsm", "dinsu", "drotl", "drotr", "drotr32", "drotrv", "dsbh",
and "dshd" for MIPS64r2. Adjust "dror", "dror32", and "drorv" to
be supported on MIPS64r2.
2003-09-30 18:17:15 +02:00
|
|
|
|
static expressionS imm2_expr;
|
1999-05-03 09:29:11 +02:00
|
|
|
|
static expressionS offset_expr;
|
|
|
|
|
|
|
|
|
|
/* Relocs associated with imm_expr and offset_expr. */
|
|
|
|
|
|
2001-10-04 22:07:00 +02:00
|
|
|
|
static bfd_reloc_code_real_type imm_reloc[3]
|
|
|
|
|
= {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED};
|
|
|
|
|
static bfd_reloc_code_real_type offset_reloc[3]
|
|
|
|
|
= {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED};
|
1999-05-03 09:29:11 +02:00
|
|
|
|
|
|
|
|
|
/* These are set by mips16_ip if an explicit extension is used. */
|
|
|
|
|
|
2002-11-30 09:39:46 +01:00
|
|
|
|
static bfd_boolean mips16_small, mips16_ext;
|
1999-05-03 09:29:11 +02:00
|
|
|
|
|
2002-09-17 09:43:25 +02:00
|
|
|
|
#ifdef OBJ_ELF
|
2002-06-14 16:08:54 +02:00
|
|
|
|
/* The pdr segment for per procedure frame/regmask info. Not used for
|
|
|
|
|
ECOFF debugging. */
|
1999-05-03 09:29:11 +02:00
|
|
|
|
|
|
|
|
|
static segT pdr_seg;
|
2002-09-17 09:43:25 +02:00
|
|
|
|
#endif
|
1999-05-03 09:29:11 +02:00
|
|
|
|
|
2001-10-03 22:30:15 +02:00
|
|
|
|
/* The default target format to use. */
|
|
|
|
|
|
|
|
|
|
const char *
|
2003-06-30 14:44:25 +02:00
|
|
|
|
mips_target_format (void)
|
2001-10-03 22:30:15 +02:00
|
|
|
|
{
|
|
|
|
|
switch (OUTPUT_FLAVOR)
|
|
|
|
|
{
|
|
|
|
|
case bfd_target_aout_flavour:
|
|
|
|
|
return target_big_endian ? "a.out-mips-big" : "a.out-mips-little";
|
|
|
|
|
case bfd_target_ecoff_flavour:
|
|
|
|
|
return target_big_endian ? "ecoff-bigmips" : ECOFF_LITTLE_FORMAT;
|
|
|
|
|
case bfd_target_coff_flavour:
|
|
|
|
|
return "pe-mips";
|
|
|
|
|
case bfd_target_elf_flavour:
|
|
|
|
|
#ifdef TE_TMIPS
|
2002-07-31 01:56:28 +02:00
|
|
|
|
/* This is traditional mips. */
|
2001-10-03 22:30:15 +02:00
|
|
|
|
return (target_big_endian
|
2002-07-31 01:56:28 +02:00
|
|
|
|
? (HAVE_64BIT_OBJECTS
|
|
|
|
|
? "elf64-tradbigmips"
|
|
|
|
|
: (HAVE_NEWABI
|
|
|
|
|
? "elf32-ntradbigmips" : "elf32-tradbigmips"))
|
|
|
|
|
: (HAVE_64BIT_OBJECTS
|
|
|
|
|
? "elf64-tradlittlemips"
|
|
|
|
|
: (HAVE_NEWABI
|
|
|
|
|
? "elf32-ntradlittlemips" : "elf32-tradlittlemips")));
|
2001-10-03 22:30:15 +02:00
|
|
|
|
#else
|
|
|
|
|
return (target_big_endian
|
2002-07-31 01:56:28 +02:00
|
|
|
|
? (HAVE_64BIT_OBJECTS
|
|
|
|
|
? "elf64-bigmips"
|
|
|
|
|
: (HAVE_NEWABI
|
|
|
|
|
? "elf32-nbigmips" : "elf32-bigmips"))
|
|
|
|
|
: (HAVE_64BIT_OBJECTS
|
|
|
|
|
? "elf64-littlemips"
|
|
|
|
|
: (HAVE_NEWABI
|
|
|
|
|
? "elf32-nlittlemips" : "elf32-littlemips")));
|
2001-10-03 22:30:15 +02:00
|
|
|
|
#endif
|
|
|
|
|
default:
|
|
|
|
|
abort ();
|
|
|
|
|
return NULL;
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
2000-09-14 03:47:38 +02:00
|
|
|
|
/* This function is called once, at assembler startup time. It should
|
|
|
|
|
set up all the tables, etc. that the MD part of the assembler will need. */
|
|
|
|
|
|
1999-05-03 09:29:11 +02:00
|
|
|
|
void
|
2003-06-30 14:44:25 +02:00
|
|
|
|
md_begin (void)
|
1999-05-03 09:29:11 +02:00
|
|
|
|
{
|
|
|
|
|
register const char *retval = NULL;
|
2000-09-14 03:47:38 +02:00
|
|
|
|
int i = 0;
|
1999-05-03 09:29:11 +02:00
|
|
|
|
int broken = 0;
|
2002-03-16 04:09:19 +01:00
|
|
|
|
|
2003-06-29 21:41:33 +02:00
|
|
|
|
if (! bfd_set_arch_mach (stdoutput, bfd_arch_mips, file_mips_arch))
|
1999-05-03 09:29:11 +02:00
|
|
|
|
as_warn (_("Could not set architecture and machine"));
|
|
|
|
|
|
|
|
|
|
op_hash = hash_new ();
|
|
|
|
|
|
|
|
|
|
for (i = 0; i < NUMOPCODES;)
|
|
|
|
|
{
|
|
|
|
|
const char *name = mips_opcodes[i].name;
|
|
|
|
|
|
2003-06-30 14:44:25 +02:00
|
|
|
|
retval = hash_insert (op_hash, name, (void *) &mips_opcodes[i]);
|
1999-05-03 09:29:11 +02:00
|
|
|
|
if (retval != NULL)
|
|
|
|
|
{
|
|
|
|
|
fprintf (stderr, _("internal error: can't hash `%s': %s\n"),
|
|
|
|
|
mips_opcodes[i].name, retval);
|
|
|
|
|
/* Probably a memory allocation problem? Give up now. */
|
|
|
|
|
as_fatal (_("Broken assembler. No assembly attempted."));
|
|
|
|
|
}
|
|
|
|
|
do
|
|
|
|
|
{
|
|
|
|
|
if (mips_opcodes[i].pinfo != INSN_MACRO)
|
|
|
|
|
{
|
|
|
|
|
if (!validate_mips_insn (&mips_opcodes[i]))
|
|
|
|
|
broken = 1;
|
|
|
|
|
}
|
|
|
|
|
++i;
|
|
|
|
|
}
|
|
|
|
|
while ((i < NUMOPCODES) && !strcmp (mips_opcodes[i].name, name));
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
mips16_op_hash = hash_new ();
|
|
|
|
|
|
|
|
|
|
i = 0;
|
|
|
|
|
while (i < bfd_mips16_num_opcodes)
|
|
|
|
|
{
|
|
|
|
|
const char *name = mips16_opcodes[i].name;
|
|
|
|
|
|
2003-06-30 14:44:25 +02:00
|
|
|
|
retval = hash_insert (mips16_op_hash, name, (void *) &mips16_opcodes[i]);
|
1999-05-03 09:29:11 +02:00
|
|
|
|
if (retval != NULL)
|
|
|
|
|
as_fatal (_("internal: can't hash `%s': %s"),
|
|
|
|
|
mips16_opcodes[i].name, retval);
|
|
|
|
|
do
|
|
|
|
|
{
|
|
|
|
|
if (mips16_opcodes[i].pinfo != INSN_MACRO
|
|
|
|
|
&& ((mips16_opcodes[i].match & mips16_opcodes[i].mask)
|
|
|
|
|
!= mips16_opcodes[i].match))
|
|
|
|
|
{
|
|
|
|
|
fprintf (stderr, _("internal error: bad mips16 opcode: %s %s\n"),
|
|
|
|
|
mips16_opcodes[i].name, mips16_opcodes[i].args);
|
|
|
|
|
broken = 1;
|
|
|
|
|
}
|
|
|
|
|
++i;
|
|
|
|
|
}
|
|
|
|
|
while (i < bfd_mips16_num_opcodes
|
|
|
|
|
&& strcmp (mips16_opcodes[i].name, name) == 0);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
if (broken)
|
|
|
|
|
as_fatal (_("Broken assembler. No assembly attempted."));
|
|
|
|
|
|
|
|
|
|
/* We add all the general register names to the symbol table. This
|
|
|
|
|
helps us detect invalid uses of them. */
|
|
|
|
|
for (i = 0; i < 32; i++)
|
|
|
|
|
{
|
|
|
|
|
char buf[5];
|
|
|
|
|
|
|
|
|
|
sprintf (buf, "$%d", i);
|
|
|
|
|
symbol_table_insert (symbol_new (buf, reg_section, i,
|
|
|
|
|
&zero_address_frag));
|
|
|
|
|
}
|
2002-05-31 03:58:18 +02:00
|
|
|
|
symbol_table_insert (symbol_new ("$ra", reg_section, RA,
|
|
|
|
|
&zero_address_frag));
|
1999-05-03 09:29:11 +02:00
|
|
|
|
symbol_table_insert (symbol_new ("$fp", reg_section, FP,
|
|
|
|
|
&zero_address_frag));
|
|
|
|
|
symbol_table_insert (symbol_new ("$sp", reg_section, SP,
|
|
|
|
|
&zero_address_frag));
|
|
|
|
|
symbol_table_insert (symbol_new ("$gp", reg_section, GP,
|
|
|
|
|
&zero_address_frag));
|
|
|
|
|
symbol_table_insert (symbol_new ("$at", reg_section, AT,
|
|
|
|
|
&zero_address_frag));
|
|
|
|
|
symbol_table_insert (symbol_new ("$kt0", reg_section, KT0,
|
|
|
|
|
&zero_address_frag));
|
|
|
|
|
symbol_table_insert (symbol_new ("$kt1", reg_section, KT1,
|
|
|
|
|
&zero_address_frag));
|
2002-06-08 00:54:47 +02:00
|
|
|
|
symbol_table_insert (symbol_new ("$zero", reg_section, ZERO,
|
|
|
|
|
&zero_address_frag));
|
1999-05-03 09:29:11 +02:00
|
|
|
|
symbol_table_insert (symbol_new ("$pc", reg_section, -1,
|
|
|
|
|
&zero_address_frag));
|
|
|
|
|
|
2002-10-19 02:37:50 +02:00
|
|
|
|
/* If we don't add these register names to the symbol table, they
|
|
|
|
|
may end up being added as regular symbols by operand(), and then
|
|
|
|
|
make it to the object file as undefined in case they're not
|
|
|
|
|
regarded as local symbols. They're local in o32, since `$' is a
|
|
|
|
|
local symbol prefix, but not in n32 or n64. */
|
|
|
|
|
for (i = 0; i < 8; i++)
|
|
|
|
|
{
|
|
|
|
|
char buf[6];
|
|
|
|
|
|
|
|
|
|
sprintf (buf, "$fcc%i", i);
|
|
|
|
|
symbol_table_insert (symbol_new (buf, reg_section, -1,
|
|
|
|
|
&zero_address_frag));
|
|
|
|
|
}
|
|
|
|
|
|
2002-11-30 09:39:46 +01:00
|
|
|
|
mips_no_prev_insn (FALSE);
|
1999-05-03 09:29:11 +02:00
|
|
|
|
|
|
|
|
|
mips_gprmask = 0;
|
|
|
|
|
mips_cprmask[0] = 0;
|
|
|
|
|
mips_cprmask[1] = 0;
|
|
|
|
|
mips_cprmask[2] = 0;
|
|
|
|
|
mips_cprmask[3] = 0;
|
|
|
|
|
|
|
|
|
|
/* set the default alignment for the text section (2**2) */
|
|
|
|
|
record_alignment (text_section, 2);
|
|
|
|
|
|
|
|
|
|
if (USE_GLOBAL_POINTER_OPT)
|
|
|
|
|
bfd_set_gp_size (stdoutput, g_switch_value);
|
|
|
|
|
|
|
|
|
|
if (OUTPUT_FLAVOR == bfd_target_elf_flavour)
|
|
|
|
|
{
|
|
|
|
|
/* On a native system, sections must be aligned to 16 byte
|
|
|
|
|
boundaries. When configured for an embedded ELF target, we
|
|
|
|
|
don't bother. */
|
|
|
|
|
if (strcmp (TARGET_OS, "elf") != 0)
|
|
|
|
|
{
|
|
|
|
|
(void) bfd_set_section_alignment (stdoutput, text_section, 4);
|
|
|
|
|
(void) bfd_set_section_alignment (stdoutput, data_section, 4);
|
|
|
|
|
(void) bfd_set_section_alignment (stdoutput, bss_section, 4);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/* Create a .reginfo section for register masks and a .mdebug
|
|
|
|
|
section for debugging information. */
|
|
|
|
|
{
|
|
|
|
|
segT seg;
|
|
|
|
|
subsegT subseg;
|
|
|
|
|
flagword flags;
|
|
|
|
|
segT sec;
|
|
|
|
|
|
|
|
|
|
seg = now_seg;
|
|
|
|
|
subseg = now_subseg;
|
|
|
|
|
|
|
|
|
|
/* The ABI says this section should be loaded so that the
|
|
|
|
|
running program can access it. However, we don't load it
|
|
|
|
|
if we are configured for an embedded target */
|
|
|
|
|
flags = SEC_READONLY | SEC_DATA;
|
|
|
|
|
if (strcmp (TARGET_OS, "elf") != 0)
|
|
|
|
|
flags |= SEC_ALLOC | SEC_LOAD;
|
|
|
|
|
|
[gas/]
* doc/c-mips.texi: Remove -mcpu. Document -mabi.
* configure.in (MIPS_CPU_STRING_DEFAULT): New configuration macro.
(USE_E_MIPS_ABI_O32, MIPS_DEFAULT_64BIT): New configuration macros.
* configure, config.in: Regenerate.
* config/tc-mips.c (file_mips_abi): Rename to mips_abi.
(mips_set_options): Remove "abi" field.
(mips_opts): Update accordingly. Replace all uses of mips_opts.abi
with mips_abi.
(mips_cpu): Remove.
(mips_arch_string, mips_arch_info): New vars.
(mips_tune_string, mips_tune_info): New vars.
(ABI_NEEDS_32BIT_REGS, ABI_NEEDS_64BIT_REGS): New macros.
(HAVE_32BIT_GPRS, HAVE_32BIT_FPRS): Don't check the ABI.
(mips_isa_to_str, mips_cpu_to_str): Remove.
(mips_ip): If the selected architecture is a generic ISA rather
than a processor, only mention the ISA level in error messages.
(OPTION_MCPU): Remove.
(OPTION_FP64): New.
(md_longopts): Add -mfp64, remove -mcpu.
(mips_set_option_string): New fn.
(md_parse_option): Make -mipsN update file_mips_isa rather than
mips_opts.isa. Use mips_set_option_string to set -march or -mtune.
Don't let -mgp32 and -mfp32 change the ABI.
(show): Move to end of file. Constify string argument.
(md_show_usage): Move to the end of the file. Read available
architectures from mips_cpu_info_table.
(mips_set_architecture): New fn.
(mips_after_parse_args): Rework. Remove -mcpu handling. -mipsN
is an alias for -march=mipsN. Don't change the ABI based on other
flags. Infer the register size from the ABI as well as the
architecture. Complain about more conflicting arguments.
Unify logic with GCC.
(s_mipsset): Don't change the ABI.
(mips_elf_final_processing): Check USE_E_MIPS_ABI_O32.
(mips_cpu_info_table): Remove Generic-MIPS* entries, keeping just
"mipsN"-type entries. Remove entries that vary only in the
manufacturer's prefix, or that have "000" replaced by "k".
Remove TARGET_CPU entries. Make r2000 entry use CPU_R3000.
(mips_strict_matching_cpu_name_p, mips_matching_cpu_name_p): New fns.
(mips_parse_cpu): New fn.
(mips_cpu_info_from_name, mips_cpu_info_from_cpu): Remove.
(mips_cpu_info_from_isa): Minor formatting tweak.
[gas/testsuite]
* gas/mips/mips-gp32-fp64.d,
* gas/mips/mips-gp32-fp64-pic.d: Add -mfp64.
2002-07-25 11:48:07 +02:00
|
|
|
|
if (mips_abi != N64_ABI)
|
1999-05-03 09:29:11 +02:00
|
|
|
|
{
|
|
|
|
|
sec = subseg_new (".reginfo", (subsegT) 0);
|
|
|
|
|
|
2002-05-15 01:27:35 +02:00
|
|
|
|
bfd_set_section_flags (stdoutput, sec, flags);
|
|
|
|
|
bfd_set_section_alignment (stdoutput, sec, HAVE_NEWABI ? 3 : 2);
|
2000-09-07 14:45:56 +02:00
|
|
|
|
|
1999-05-03 09:29:11 +02:00
|
|
|
|
#ifdef OBJ_ELF
|
|
|
|
|
mips_regmask_frag = frag_more (sizeof (Elf32_External_RegInfo));
|
|
|
|
|
#endif
|
|
|
|
|
}
|
|
|
|
|
else
|
|
|
|
|
{
|
|
|
|
|
/* The 64-bit ABI uses a .MIPS.options section rather than
|
|
|
|
|
.reginfo section. */
|
|
|
|
|
sec = subseg_new (".MIPS.options", (subsegT) 0);
|
2002-05-15 01:27:35 +02:00
|
|
|
|
bfd_set_section_flags (stdoutput, sec, flags);
|
|
|
|
|
bfd_set_section_alignment (stdoutput, sec, 3);
|
1999-05-03 09:29:11 +02:00
|
|
|
|
|
|
|
|
|
#ifdef OBJ_ELF
|
|
|
|
|
/* Set up the option header. */
|
|
|
|
|
{
|
|
|
|
|
Elf_Internal_Options opthdr;
|
|
|
|
|
char *f;
|
|
|
|
|
|
|
|
|
|
opthdr.kind = ODK_REGINFO;
|
|
|
|
|
opthdr.size = (sizeof (Elf_External_Options)
|
|
|
|
|
+ sizeof (Elf64_External_RegInfo));
|
|
|
|
|
opthdr.section = 0;
|
|
|
|
|
opthdr.info = 0;
|
|
|
|
|
f = frag_more (sizeof (Elf_External_Options));
|
|
|
|
|
bfd_mips_elf_swap_options_out (stdoutput, &opthdr,
|
|
|
|
|
(Elf_External_Options *) f);
|
|
|
|
|
|
|
|
|
|
mips_regmask_frag = frag_more (sizeof (Elf64_External_RegInfo));
|
|
|
|
|
}
|
|
|
|
|
#endif
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
if (ECOFF_DEBUGGING)
|
|
|
|
|
{
|
|
|
|
|
sec = subseg_new (".mdebug", (subsegT) 0);
|
|
|
|
|
(void) bfd_set_section_flags (stdoutput, sec,
|
|
|
|
|
SEC_HAS_CONTENTS | SEC_READONLY);
|
|
|
|
|
(void) bfd_set_section_alignment (stdoutput, sec, 2);
|
|
|
|
|
}
|
2002-06-14 16:08:54 +02:00
|
|
|
|
#ifdef OBJ_ELF
|
2003-07-28 22:06:27 +02:00
|
|
|
|
else if (OUTPUT_FLAVOR == bfd_target_elf_flavour && mips_flag_pdr)
|
2002-06-14 16:08:54 +02:00
|
|
|
|
{
|
|
|
|
|
pdr_seg = subseg_new (".pdr", (subsegT) 0);
|
|
|
|
|
(void) bfd_set_section_flags (stdoutput, pdr_seg,
|
|
|
|
|
SEC_READONLY | SEC_RELOC
|
|
|
|
|
| SEC_DEBUGGING);
|
|
|
|
|
(void) bfd_set_section_alignment (stdoutput, pdr_seg, 2);
|
|
|
|
|
}
|
1999-05-03 09:29:11 +02:00
|
|
|
|
#endif
|
|
|
|
|
|
|
|
|
|
subseg_set (seg, subseg);
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
if (! ECOFF_DEBUGGING)
|
|
|
|
|
md_obj_begin ();
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
void
|
2003-06-30 14:44:25 +02:00
|
|
|
|
md_mips_end (void)
|
1999-05-03 09:29:11 +02:00
|
|
|
|
{
|
|
|
|
|
if (! ECOFF_DEBUGGING)
|
|
|
|
|
md_obj_end ();
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
void
|
2003-06-30 14:44:25 +02:00
|
|
|
|
md_assemble (char *str)
|
1999-05-03 09:29:11 +02:00
|
|
|
|
{
|
|
|
|
|
struct mips_cl_insn insn;
|
2001-10-04 22:07:00 +02:00
|
|
|
|
bfd_reloc_code_real_type unused_reloc[3]
|
|
|
|
|
= {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED};
|
1999-05-03 09:29:11 +02:00
|
|
|
|
|
|
|
|
|
imm_expr.X_op = O_absent;
|
[ bfd/ChangeLog ]
2003-09-30 Chris Demetriou <cgd@broadcom.com>
* archures.c (bfd_mach_mipsisa64r2): New define.
* bfd-in2.h: Regenerate.
* aoutx.h (NAME(aout,machine_type)): Handle bfd_mach_mipsisa64r2.
* cpu-mips.c (I_mipsisa64r2): New enum value.
(arch_info_struct): Add entry for I_mipsisa64r2.
* elfxx-mips.c (_bfd_elf_mips_mach)
(_bfd_mips_elf_print_private_bfd_data): Handle E_MIPS_ARCH_64R2.
(mips_set_isa_flags): Add bfd_mach_mipsisa64r2 case.
(mips_mach_extensions): Add entry for bfd_mach_mipsisa64r2.
[ binutils/ChangeLog ]
2003-09-30 Chris Demetriou <cgd@broadcom.com>
* readelf.c (get_machine_flags): Handle E_MIPS_ARCH_64R2.
[ gas/Changelog ]
2003-09-30 Chris Demetriou <cgd@broadcom.com>
* configure.in (mipsisa64r2, mipsisa64r2el, mipsisa64r2*): New CPUs.
* configure: Regenerate.
* config/tc-mips.c (imm2_expr): New variable.
(md_assemble, mips16_ip): Initialize imm2_expr.
(ISA_HAS_64BIT_REGS, ISA_HAS_DROR, ISA_HAS_ROR): Add ISA_MIPS64R2.
(macro_build): Handle +A, +B, +C, +E, +F, +G, and +H format operands.
(macro): Handle M_DEXT and M_DINS.
(validate_mips_insn): Handle +E, +F, +G, +H, and +I format operands.
(mips_ip): Likewise.
(OPTION_MIPS64R2): New define.
(md_longopts): New entry for -mips64r2 (OPTION_MIPS64R2).
OPTION_ASE_BASE): Increase to compensate for OPTION_MIPS64R2.
(md_parse_option): Handle OPTION_MIPS64R2.
(s_mipsset): Handle setting "mips64r2" ISA.
(mips_cpu_info_table): Add mips64r2.
(md_show_usage): Document -mips64r2 option.
* doc/as.texinfo: Docuemnt -mips64r2 option.
* doc/c-mips.texi: Likewise.
[ gas/testsuite/ChangeLog ]
2003-09-30 Chris Demetriou <cgd@broadcom.com>
* gas/mips/cp0-names-mips64r2.d: New file.
* gas/mips/cp0sel-names-mips64r2.d: New file.
* gas/mips/elf_arch_mips64r2.d: New file.
* gas/mips/hwr-names-mips64r2.d: New file.
* gas/mips/mips32r2-ill-fp64.l: New file.
* gas/mips/mips32r2-ill-fp64.s: New file.
* gas/mips/mips64r2-ill.l: New file.
* gas/mips/mips64r2-ill.s: New file.
* gas/mips/mips64r2.d: New file.
* gas/mips/mips64r2.s: New file.
* gas/mips/mips.exp: Define "mips64r2" arch, and run new tests.
[ include/elf/ChangeLog ]
2003-09-30 Chris Demetriou <cgd@broadcom.com>
* mips.h (E_MIPS_ARCH_64R2): New define.
[ include/opcode/ChangeLog ]
2003-09-30 Chris Demetriou <cgd@broadcom.com>
* mips.h: Document +E, +F, +G, +H, and +I operand types.
Update documentation of I, +B and +C operand types.
(INSN_ISA64R2, ISA_MIPS64R2, CPU_MIPS64R2): New defines.
(M_DEXT, M_DINS): New enum values.
[ ld/ChangeLog ]
2003-09-30 Chris Demetriou <cgd@broadcom.com>
* ldmain.c (get_emulation): Ignore "-mips64r2".
[ ld/testsuite/ChangeLog ]
2003-09-30 Chris Demetriou <cgd@broadcom.com>
* ld-mips-elf/mips-elf-flags.exp: Add tests for combinations
with MIPS64r2.
[ opcodes/ChangeLog ]
2003-09-30 Chris Demetriou <cgd@broadcom.com>
* mips-dis.c (mips_arch_choices): Add entry for "mips64r2"
(print_insn_args): Add handing for +E, +F, +G, and +H.
* mips-opc.c (I65): New define for MIPS64r2.
(mips_builtin_opcodes): Add "dext", "dextm", "dextu", "dins",
"dinsm", "dinsu", "drotl", "drotr", "drotr32", "drotrv", "dsbh",
and "dshd" for MIPS64r2. Adjust "dror", "dror32", and "drorv" to
be supported on MIPS64r2.
2003-09-30 18:17:15 +02:00
|
|
|
|
imm2_expr.X_op = O_absent;
|
1999-05-03 09:29:11 +02:00
|
|
|
|
offset_expr.X_op = O_absent;
|
2001-10-04 22:07:00 +02:00
|
|
|
|
imm_reloc[0] = BFD_RELOC_UNUSED;
|
|
|
|
|
imm_reloc[1] = BFD_RELOC_UNUSED;
|
|
|
|
|
imm_reloc[2] = BFD_RELOC_UNUSED;
|
|
|
|
|
offset_reloc[0] = BFD_RELOC_UNUSED;
|
|
|
|
|
offset_reloc[1] = BFD_RELOC_UNUSED;
|
|
|
|
|
offset_reloc[2] = BFD_RELOC_UNUSED;
|
1999-05-03 09:29:11 +02:00
|
|
|
|
|
|
|
|
|
if (mips_opts.mips16)
|
|
|
|
|
mips16_ip (str, &insn);
|
|
|
|
|
else
|
|
|
|
|
{
|
|
|
|
|
mips_ip (str, &insn);
|
2000-12-05 19:51:08 +01:00
|
|
|
|
DBG ((_("returned from mips_ip(%s) insn_opcode = 0x%x\n"),
|
|
|
|
|
str, insn.insn_opcode));
|
1999-05-03 09:29:11 +02:00
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
if (insn_error)
|
|
|
|
|
{
|
|
|
|
|
as_bad ("%s `%s'", insn_error, str);
|
|
|
|
|
return;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
if (insn.insn_mo->pinfo == INSN_MACRO)
|
|
|
|
|
{
|
|
|
|
|
if (mips_opts.mips16)
|
|
|
|
|
mips16_macro (&insn);
|
|
|
|
|
else
|
|
|
|
|
macro (&insn);
|
|
|
|
|
}
|
|
|
|
|
else
|
|
|
|
|
{
|
|
|
|
|
if (imm_expr.X_op != O_absent)
|
2003-02-02 20:37:20 +01:00
|
|
|
|
append_insn (NULL, &insn, &imm_expr, imm_reloc);
|
1999-05-03 09:29:11 +02:00
|
|
|
|
else if (offset_expr.X_op != O_absent)
|
2003-02-02 20:37:20 +01:00
|
|
|
|
append_insn (NULL, &insn, &offset_expr, offset_reloc);
|
1999-05-03 09:29:11 +02:00
|
|
|
|
else
|
2003-02-02 20:37:20 +01:00
|
|
|
|
append_insn (NULL, &insn, NULL, unused_reloc);
|
1999-05-03 09:29:11 +02:00
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
2003-02-08 18:05:55 +01:00
|
|
|
|
/* Return true if the given relocation might need a matching %lo().
|
|
|
|
|
Note that R_MIPS_GOT16 relocations only need a matching %lo() when
|
|
|
|
|
applied to local symbols. */
|
|
|
|
|
|
|
|
|
|
static inline bfd_boolean
|
2003-06-30 14:44:25 +02:00
|
|
|
|
reloc_needs_lo_p (bfd_reloc_code_real_type reloc)
|
2003-02-08 18:05:55 +01:00
|
|
|
|
{
|
|
|
|
|
return (reloc == BFD_RELOC_HI16_S
|
|
|
|
|
|| reloc == BFD_RELOC_MIPS_GOT16);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/* Return true if the given fixup is followed by a matching R_MIPS_LO16
|
|
|
|
|
relocation. */
|
|
|
|
|
|
|
|
|
|
static inline bfd_boolean
|
2003-06-30 14:44:25 +02:00
|
|
|
|
fixup_has_matching_lo_p (fixS *fixp)
|
2003-02-08 18:05:55 +01:00
|
|
|
|
{
|
|
|
|
|
return (fixp->fx_next != NULL
|
|
|
|
|
&& fixp->fx_next->fx_r_type == BFD_RELOC_LO16
|
|
|
|
|
&& fixp->fx_addsy == fixp->fx_next->fx_addsy
|
|
|
|
|
&& fixp->fx_offset == fixp->fx_next->fx_offset);
|
|
|
|
|
}
|
|
|
|
|
|
1999-05-03 09:29:11 +02:00
|
|
|
|
/* See whether instruction IP reads register REG. CLASS is the type
|
|
|
|
|
of register. */
|
|
|
|
|
|
|
|
|
|
static int
|
2003-06-30 14:44:25 +02:00
|
|
|
|
insn_uses_reg (struct mips_cl_insn *ip, unsigned int reg,
|
|
|
|
|
enum mips_regclass class)
|
1999-05-03 09:29:11 +02:00
|
|
|
|
{
|
|
|
|
|
if (class == MIPS16_REG)
|
|
|
|
|
{
|
|
|
|
|
assert (mips_opts.mips16);
|
|
|
|
|
reg = mips16_to_32_reg_map[reg];
|
|
|
|
|
class = MIPS_GR_REG;
|
|
|
|
|
}
|
|
|
|
|
|
2002-06-08 00:54:47 +02:00
|
|
|
|
/* Don't report on general register ZERO, since it never changes. */
|
|
|
|
|
if (class == MIPS_GR_REG && reg == ZERO)
|
1999-05-03 09:29:11 +02:00
|
|
|
|
return 0;
|
|
|
|
|
|
|
|
|
|
if (class == MIPS_FP_REG)
|
|
|
|
|
{
|
|
|
|
|
assert (! mips_opts.mips16);
|
|
|
|
|
/* If we are called with either $f0 or $f1, we must check $f0.
|
|
|
|
|
This is not optimal, because it will introduce an unnecessary
|
|
|
|
|
NOP between "lwc1 $f0" and "swc1 $f1". To fix this we would
|
|
|
|
|
need to distinguish reading both $f0 and $f1 or just one of
|
|
|
|
|
them. Note that we don't have to check the other way,
|
|
|
|
|
because there is no instruction that sets both $f0 and $f1
|
|
|
|
|
and requires a delay. */
|
|
|
|
|
if ((ip->insn_mo->pinfo & INSN_READ_FPR_S)
|
|
|
|
|
&& ((((ip->insn_opcode >> OP_SH_FS) & OP_MASK_FS) &~(unsigned)1)
|
|
|
|
|
== (reg &~ (unsigned) 1)))
|
|
|
|
|
return 1;
|
|
|
|
|
if ((ip->insn_mo->pinfo & INSN_READ_FPR_T)
|
|
|
|
|
&& ((((ip->insn_opcode >> OP_SH_FT) & OP_MASK_FT) &~(unsigned)1)
|
|
|
|
|
== (reg &~ (unsigned) 1)))
|
|
|
|
|
return 1;
|
|
|
|
|
}
|
|
|
|
|
else if (! mips_opts.mips16)
|
|
|
|
|
{
|
|
|
|
|
if ((ip->insn_mo->pinfo & INSN_READ_GPR_S)
|
|
|
|
|
&& ((ip->insn_opcode >> OP_SH_RS) & OP_MASK_RS) == reg)
|
|
|
|
|
return 1;
|
|
|
|
|
if ((ip->insn_mo->pinfo & INSN_READ_GPR_T)
|
|
|
|
|
&& ((ip->insn_opcode >> OP_SH_RT) & OP_MASK_RT) == reg)
|
|
|
|
|
return 1;
|
|
|
|
|
}
|
|
|
|
|
else
|
|
|
|
|
{
|
|
|
|
|
if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_X)
|
|
|
|
|
&& (mips16_to_32_reg_map[((ip->insn_opcode >> MIPS16OP_SH_RX)
|
|
|
|
|
& MIPS16OP_MASK_RX)]
|
|
|
|
|
== reg))
|
|
|
|
|
return 1;
|
|
|
|
|
if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_Y)
|
|
|
|
|
&& (mips16_to_32_reg_map[((ip->insn_opcode >> MIPS16OP_SH_RY)
|
|
|
|
|
& MIPS16OP_MASK_RY)]
|
|
|
|
|
== reg))
|
|
|
|
|
return 1;
|
|
|
|
|
if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_Z)
|
|
|
|
|
&& (mips16_to_32_reg_map[((ip->insn_opcode >> MIPS16OP_SH_MOVE32Z)
|
|
|
|
|
& MIPS16OP_MASK_MOVE32Z)]
|
|
|
|
|
== reg))
|
|
|
|
|
return 1;
|
|
|
|
|
if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_T) && reg == TREG)
|
|
|
|
|
return 1;
|
|
|
|
|
if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_SP) && reg == SP)
|
|
|
|
|
return 1;
|
|
|
|
|
if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_31) && reg == RA)
|
|
|
|
|
return 1;
|
|
|
|
|
if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_GPR_X)
|
|
|
|
|
&& ((ip->insn_opcode >> MIPS16OP_SH_REGR32)
|
|
|
|
|
& MIPS16OP_MASK_REGR32) == reg)
|
|
|
|
|
return 1;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/* This function returns true if modifying a register requires a
|
|
|
|
|
delay. */
|
|
|
|
|
|
|
|
|
|
static int
|
2003-06-30 14:44:25 +02:00
|
|
|
|
reg_needs_delay (unsigned int reg)
|
1999-05-03 09:29:11 +02:00
|
|
|
|
{
|
|
|
|
|
unsigned long prev_pinfo;
|
|
|
|
|
|
|
|
|
|
prev_pinfo = prev_insn.insn_mo->pinfo;
|
|
|
|
|
if (! mips_opts.noreorder
|
2004-01-09 03:16:30 +01:00
|
|
|
|
&& (((prev_pinfo & INSN_LOAD_MEMORY_DELAY)
|
|
|
|
|
&& ! gpr_interlocks)
|
|
|
|
|
|| ((prev_pinfo & INSN_LOAD_COPROC_DELAY)
|
|
|
|
|
&& ! cop_interlocks)))
|
1999-05-03 09:29:11 +02:00
|
|
|
|
{
|
2004-01-09 03:16:30 +01:00
|
|
|
|
/* A load from a coprocessor or from memory. All load delays
|
|
|
|
|
delay the use of general register rt for one instruction. */
|
2000-09-07 14:45:56 +02:00
|
|
|
|
/* Itbl support may require additional care here. */
|
1999-05-03 09:29:11 +02:00
|
|
|
|
know (prev_pinfo & INSN_WRITE_GPR_T);
|
|
|
|
|
if (reg == ((prev_insn.insn_opcode >> OP_SH_RT) & OP_MASK_RT))
|
|
|
|
|
return 1;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/* Mark instruction labels in mips16 mode. This permits the linker to
|
|
|
|
|
handle them specially, such as generating jalx instructions when
|
|
|
|
|
needed. We also make them odd for the duration of the assembly, in
|
|
|
|
|
order to generate the right sort of code. We will make them even
|
|
|
|
|
in the adjust_symtab routine, while leaving them marked. This is
|
|
|
|
|
convenient for the debugger and the disassembler. The linker knows
|
|
|
|
|
to make them odd again. */
|
|
|
|
|
|
|
|
|
|
static void
|
2003-06-30 14:44:25 +02:00
|
|
|
|
mips16_mark_labels (void)
|
1999-05-03 09:29:11 +02:00
|
|
|
|
{
|
|
|
|
|
if (mips_opts.mips16)
|
|
|
|
|
{
|
|
|
|
|
struct insn_label_list *l;
|
2001-06-08 08:07:13 +02:00
|
|
|
|
valueT val;
|
1999-05-03 09:29:11 +02:00
|
|
|
|
|
|
|
|
|
for (l = insn_labels; l != NULL; l = l->next)
|
|
|
|
|
{
|
|
|
|
|
#ifdef OBJ_ELF
|
|
|
|
|
if (OUTPUT_FLAVOR == bfd_target_elf_flavour)
|
|
|
|
|
S_SET_OTHER (l->label, STO_MIPS16);
|
|
|
|
|
#endif
|
2001-06-08 08:07:13 +02:00
|
|
|
|
val = S_GET_VALUE (l->label);
|
|
|
|
|
if ((val & 1) == 0)
|
|
|
|
|
S_SET_VALUE (l->label, val + 1);
|
1999-05-03 09:29:11 +02:00
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/* Output an instruction. PLACE is where to put the instruction; if
|
|
|
|
|
it is NULL, this uses frag_more to get room. IP is the instruction
|
|
|
|
|
information. ADDRESS_EXPR is an operand of the instruction to be
|
|
|
|
|
used with RELOC_TYPE. */
|
|
|
|
|
|
|
|
|
|
static void
|
2003-06-30 14:44:25 +02:00
|
|
|
|
append_insn (char *place, struct mips_cl_insn *ip, expressionS *address_expr,
|
|
|
|
|
bfd_reloc_code_real_type *reloc_type)
|
1999-05-03 09:29:11 +02:00
|
|
|
|
{
|
|
|
|
|
register unsigned long prev_pinfo, pinfo;
|
|
|
|
|
char *f;
|
2001-10-04 22:07:00 +02:00
|
|
|
|
fixS *fixp[3];
|
1999-05-03 09:29:11 +02:00
|
|
|
|
int nops = 0;
|
2004-01-14 19:01:09 +01:00
|
|
|
|
relax_stateT prev_insn_frag_type = 0;
|
|
|
|
|
bfd_boolean relaxed_branch = FALSE;
|
* config/tc-mips.h (tc_frag_data_type, TC_FRAG_TYPE): New.
* config/tc-mips.c: Use signed add for n32 address arithmetic.
(append_insn): When filling delay slots with instructions
that have fixups that tc_gen_reloc might consider modifyable
in variant frags, start a new frag.
(load_address): Generate GOT_DISP with of without offset
depending on whether symbol is local. For -xgot, use
GOT_PAGE/GOT_OFST or GOT_HI16/GOT_LO16.
(macro) <M_DLA_AB, M_LA_AB>: Likewise.
<M_JAL_A>: In NewABI, use CALL16 or GOT_DISP for small got,
CALL_HI16/CALL_LO16 or GOT_PAGE/GOT_OFST for big got.
<ld_st>: In NewABI with small got, always use
GOT_PAGE/GOT_OFST, with the latter in the load/store
instruction. With big got, use GOT_HI16/GOT_LO16 or
GOT_PAGE/GOT_OFST.
(tc_gen_reloc): Adjust variant frags with GOT_DISP in NewABI.
Add tc_frag_data.tc_fr_offset to addends. Decay CALL16,
GOT_OFST and GOT_DISP to GOT_DISP in NewABI.
(md_convert_frag): Use memmove for safe copying of overlapping
regions.
2003-04-11 03:56:50 +02:00
|
|
|
|
bfd_boolean force_new_frag = FALSE;
|
1999-05-03 09:29:11 +02:00
|
|
|
|
|
|
|
|
|
/* Mark instruction labels in mips16 mode. */
|
2002-05-26 20:46:37 +02:00
|
|
|
|
mips16_mark_labels ();
|
1999-05-03 09:29:11 +02:00
|
|
|
|
|
|
|
|
|
prev_pinfo = prev_insn.insn_mo->pinfo;
|
|
|
|
|
pinfo = ip->insn_mo->pinfo;
|
|
|
|
|
|
|
|
|
|
if (place == NULL && (! mips_opts.noreorder || prev_nop_frag != NULL))
|
|
|
|
|
{
|
|
|
|
|
int prev_prev_nop;
|
|
|
|
|
|
|
|
|
|
/* If the previous insn required any delay slots, see if we need
|
|
|
|
|
to insert a NOP or two. There are eight kinds of possible
|
|
|
|
|
hazards, of which an instruction can have at most one type.
|
|
|
|
|
(1) a load from memory delay
|
|
|
|
|
(2) a load from a coprocessor delay
|
|
|
|
|
(3) an unconditional branch delay
|
|
|
|
|
(4) a conditional branch delay
|
|
|
|
|
(5) a move to coprocessor register delay
|
|
|
|
|
(6) a load coprocessor register from memory delay
|
|
|
|
|
(7) a coprocessor condition code delay
|
|
|
|
|
(8) a HI/LO special register delay
|
|
|
|
|
|
|
|
|
|
There are a lot of optimizations we could do that we don't.
|
|
|
|
|
In particular, we do not, in general, reorder instructions.
|
|
|
|
|
If you use gcc with optimization, it will reorder
|
|
|
|
|
instructions and generally do much more optimization then we
|
|
|
|
|
do here; repeating all that work in the assembler would only
|
|
|
|
|
benefit hand written assembly code, and does not seem worth
|
|
|
|
|
it. */
|
|
|
|
|
|
|
|
|
|
/* This is how a NOP is emitted. */
|
|
|
|
|
#define emit_nop() \
|
|
|
|
|
(mips_opts.mips16 \
|
|
|
|
|
? md_number_to_chars (frag_more (2), 0x6500, 2) \
|
|
|
|
|
: md_number_to_chars (frag_more (4), 0, 4))
|
|
|
|
|
|
|
|
|
|
/* The previous insn might require a delay slot, depending upon
|
|
|
|
|
the contents of the current insn. */
|
|
|
|
|
if (! mips_opts.mips16
|
2004-01-09 03:16:30 +01:00
|
|
|
|
&& (((prev_pinfo & INSN_LOAD_MEMORY_DELAY)
|
|
|
|
|
&& ! gpr_interlocks)
|
|
|
|
|
|| ((prev_pinfo & INSN_LOAD_COPROC_DELAY)
|
|
|
|
|
&& ! cop_interlocks)))
|
1999-05-03 09:29:11 +02:00
|
|
|
|
{
|
|
|
|
|
/* A load from a coprocessor or from memory. All load
|
|
|
|
|
delays delay the use of general register rt for one
|
2004-01-09 03:16:30 +01:00
|
|
|
|
instruction. */
|
2000-12-05 19:51:08 +01:00
|
|
|
|
/* Itbl support may require additional care here. */
|
1999-05-03 09:29:11 +02:00
|
|
|
|
know (prev_pinfo & INSN_WRITE_GPR_T);
|
|
|
|
|
if (mips_optimize == 0
|
|
|
|
|
|| insn_uses_reg (ip,
|
|
|
|
|
((prev_insn.insn_opcode >> OP_SH_RT)
|
|
|
|
|
& OP_MASK_RT),
|
|
|
|
|
MIPS_GR_REG))
|
|
|
|
|
++nops;
|
|
|
|
|
}
|
|
|
|
|
else if (! mips_opts.mips16
|
|
|
|
|
&& (((prev_pinfo & INSN_COPROC_MOVE_DELAY)
|
2000-12-05 19:51:08 +01:00
|
|
|
|
&& ! cop_interlocks)
|
2004-01-09 03:16:30 +01:00
|
|
|
|
|| ((prev_pinfo & INSN_COPROC_MEMORY_DELAY)
|
|
|
|
|
&& ! cop_mem_interlocks)))
|
1999-05-03 09:29:11 +02:00
|
|
|
|
{
|
|
|
|
|
/* A generic coprocessor delay. The previous instruction
|
|
|
|
|
modified a coprocessor general or control register. If
|
|
|
|
|
it modified a control register, we need to avoid any
|
|
|
|
|
coprocessor instruction (this is probably not always
|
|
|
|
|
required, but it sometimes is). If it modified a general
|
|
|
|
|
register, we avoid using that register.
|
|
|
|
|
|
|
|
|
|
This case is not handled very well. There is no special
|
|
|
|
|
knowledge of CP0 handling, and the coprocessors other
|
|
|
|
|
than the floating point unit are not distinguished at
|
|
|
|
|
all. */
|
|
|
|
|
/* Itbl support may require additional care here. FIXME!
|
2000-09-07 14:45:56 +02:00
|
|
|
|
Need to modify this to include knowledge about
|
1999-05-03 09:29:11 +02:00
|
|
|
|
user specified delays! */
|
|
|
|
|
if (prev_pinfo & INSN_WRITE_FPR_T)
|
|
|
|
|
{
|
|
|
|
|
if (mips_optimize == 0
|
|
|
|
|
|| insn_uses_reg (ip,
|
|
|
|
|
((prev_insn.insn_opcode >> OP_SH_FT)
|
|
|
|
|
& OP_MASK_FT),
|
|
|
|
|
MIPS_FP_REG))
|
|
|
|
|
++nops;
|
|
|
|
|
}
|
|
|
|
|
else if (prev_pinfo & INSN_WRITE_FPR_S)
|
|
|
|
|
{
|
|
|
|
|
if (mips_optimize == 0
|
|
|
|
|
|| insn_uses_reg (ip,
|
|
|
|
|
((prev_insn.insn_opcode >> OP_SH_FS)
|
|
|
|
|
& OP_MASK_FS),
|
|
|
|
|
MIPS_FP_REG))
|
|
|
|
|
++nops;
|
|
|
|
|
}
|
|
|
|
|
else
|
|
|
|
|
{
|
|
|
|
|
/* We don't know exactly what the previous instruction
|
|
|
|
|
does. If the current instruction uses a coprocessor
|
|
|
|
|
register, we must insert a NOP. If previous
|
|
|
|
|
instruction may set the condition codes, and the
|
|
|
|
|
current instruction uses them, we must insert two
|
|
|
|
|
NOPS. */
|
2000-09-07 14:45:56 +02:00
|
|
|
|
/* Itbl support may require additional care here. */
|
1999-05-03 09:29:11 +02:00
|
|
|
|
if (mips_optimize == 0
|
|
|
|
|
|| ((prev_pinfo & INSN_WRITE_COND_CODE)
|
|
|
|
|
&& (pinfo & INSN_READ_COND_CODE)))
|
|
|
|
|
nops += 2;
|
|
|
|
|
else if (pinfo & INSN_COP)
|
|
|
|
|
++nops;
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
else if (! mips_opts.mips16
|
|
|
|
|
&& (prev_pinfo & INSN_WRITE_COND_CODE)
|
|
|
|
|
&& ! cop_interlocks)
|
|
|
|
|
{
|
|
|
|
|
/* The previous instruction sets the coprocessor condition
|
|
|
|
|
codes, but does not require a general coprocessor delay
|
|
|
|
|
(this means it is a floating point comparison
|
|
|
|
|
instruction). If this instruction uses the condition
|
|
|
|
|
codes, we need to insert a single NOP. */
|
2000-12-05 19:51:08 +01:00
|
|
|
|
/* Itbl support may require additional care here. */
|
1999-05-03 09:29:11 +02:00
|
|
|
|
if (mips_optimize == 0
|
|
|
|
|
|| (pinfo & INSN_READ_COND_CODE))
|
|
|
|
|
++nops;
|
|
|
|
|
}
|
2000-02-21 21:00:33 +01:00
|
|
|
|
|
|
|
|
|
/* If we're fixing up mfhi/mflo for the r7000 and the
|
|
|
|
|
previous insn was an mfhi/mflo and the current insn
|
|
|
|
|
reads the register that the mfhi/mflo wrote to, then
|
|
|
|
|
insert two nops. */
|
|
|
|
|
|
|
|
|
|
else if (mips_7000_hilo_fix
|
|
|
|
|
&& MF_HILO_INSN (prev_pinfo)
|
|
|
|
|
&& insn_uses_reg (ip, ((prev_insn.insn_opcode >> OP_SH_RD)
|
2000-12-05 19:51:08 +01:00
|
|
|
|
& OP_MASK_RD),
|
|
|
|
|
MIPS_GR_REG))
|
2000-02-21 21:00:33 +01:00
|
|
|
|
{
|
|
|
|
|
nops += 2;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/* If we're fixing up mfhi/mflo for the r7000 and the
|
|
|
|
|
2nd previous insn was an mfhi/mflo and the current insn
|
|
|
|
|
reads the register that the mfhi/mflo wrote to, then
|
|
|
|
|
insert one nop. */
|
|
|
|
|
|
|
|
|
|
else if (mips_7000_hilo_fix
|
|
|
|
|
&& MF_HILO_INSN (prev_prev_insn.insn_opcode)
|
|
|
|
|
&& insn_uses_reg (ip, ((prev_prev_insn.insn_opcode >> OP_SH_RD)
|
|
|
|
|
& OP_MASK_RD),
|
|
|
|
|
MIPS_GR_REG))
|
2000-09-07 14:45:56 +02:00
|
|
|
|
|
2000-02-21 21:00:33 +01:00
|
|
|
|
{
|
2002-05-26 20:46:37 +02:00
|
|
|
|
++nops;
|
2000-02-21 21:00:33 +01:00
|
|
|
|
}
|
2000-09-07 14:45:56 +02:00
|
|
|
|
|
1999-05-03 09:29:11 +02:00
|
|
|
|
else if (prev_pinfo & INSN_READ_LO)
|
|
|
|
|
{
|
|
|
|
|
/* The previous instruction reads the LO register; if the
|
|
|
|
|
current instruction writes to the LO register, we must
|
2000-09-07 14:45:56 +02:00
|
|
|
|
insert two NOPS. Some newer processors have interlocks.
|
2003-11-22 03:35:31 +01:00
|
|
|
|
Also the tx39's multiply instructions can be executed
|
|
|
|
|
immediately after a read from HI/LO (without the delay),
|
2000-09-07 14:45:56 +02:00
|
|
|
|
though the tx39's divide insns still do require the
|
|
|
|
|
delay. */
|
1999-05-03 09:29:11 +02:00
|
|
|
|
if (! (hilo_interlocks
|
2004-01-22 00:25:38 +01:00
|
|
|
|
|| (mips_opts.arch == CPU_R3900 && (pinfo & INSN_MULT)))
|
1999-05-03 09:29:11 +02:00
|
|
|
|
&& (mips_optimize == 0
|
|
|
|
|
|| (pinfo & INSN_WRITE_LO)))
|
|
|
|
|
nops += 2;
|
|
|
|
|
/* Most mips16 branch insns don't have a delay slot.
|
|
|
|
|
If a read from LO is immediately followed by a branch
|
|
|
|
|
to a write to LO we have a read followed by a write
|
|
|
|
|
less than 2 insns away. We assume the target of
|
|
|
|
|
a branch might be a write to LO, and insert a nop
|
2000-09-07 14:45:56 +02:00
|
|
|
|
between a read and an immediately following branch. */
|
1999-05-03 09:29:11 +02:00
|
|
|
|
else if (mips_opts.mips16
|
|
|
|
|
&& (mips_optimize == 0
|
|
|
|
|
|| (pinfo & MIPS16_INSN_BRANCH)))
|
2002-05-26 20:46:37 +02:00
|
|
|
|
++nops;
|
1999-05-03 09:29:11 +02:00
|
|
|
|
}
|
|
|
|
|
else if (prev_insn.insn_mo->pinfo & INSN_READ_HI)
|
|
|
|
|
{
|
|
|
|
|
/* The previous instruction reads the HI register; if the
|
|
|
|
|
current instruction writes to the HI register, we must
|
|
|
|
|
insert a NOP. Some newer processors have interlocks.
|
2000-09-07 14:45:56 +02:00
|
|
|
|
Also the note tx39's multiply above. */
|
1999-05-03 09:29:11 +02:00
|
|
|
|
if (! (hilo_interlocks
|
2004-01-22 00:25:38 +01:00
|
|
|
|
|| (mips_opts.arch == CPU_R3900 && (pinfo & INSN_MULT)))
|
1999-05-03 09:29:11 +02:00
|
|
|
|
&& (mips_optimize == 0
|
|
|
|
|
|| (pinfo & INSN_WRITE_HI)))
|
|
|
|
|
nops += 2;
|
|
|
|
|
/* Most mips16 branch insns don't have a delay slot.
|
|
|
|
|
If a read from HI is immediately followed by a branch
|
|
|
|
|
to a write to HI we have a read followed by a write
|
|
|
|
|
less than 2 insns away. We assume the target of
|
|
|
|
|
a branch might be a write to HI, and insert a nop
|
2000-09-07 14:45:56 +02:00
|
|
|
|
between a read and an immediately following branch. */
|
1999-05-03 09:29:11 +02:00
|
|
|
|
else if (mips_opts.mips16
|
|
|
|
|
&& (mips_optimize == 0
|
|
|
|
|
|| (pinfo & MIPS16_INSN_BRANCH)))
|
2002-05-26 20:46:37 +02:00
|
|
|
|
++nops;
|
1999-05-03 09:29:11 +02:00
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/* If the previous instruction was in a noreorder section, then
|
|
|
|
|
we don't want to insert the nop after all. */
|
2000-09-07 14:45:56 +02:00
|
|
|
|
/* Itbl support may require additional care here. */
|
1999-05-03 09:29:11 +02:00
|
|
|
|
if (prev_insn_unreordered)
|
|
|
|
|
nops = 0;
|
|
|
|
|
|
|
|
|
|
/* There are two cases which require two intervening
|
|
|
|
|
instructions: 1) setting the condition codes using a move to
|
|
|
|
|
coprocessor instruction which requires a general coprocessor
|
|
|
|
|
delay and then reading the condition codes 2) reading the HI
|
|
|
|
|
or LO register and then writing to it (except on processors
|
|
|
|
|
which have interlocks). If we are not already emitting a NOP
|
|
|
|
|
instruction, we must check for these cases compared to the
|
|
|
|
|
instruction previous to the previous instruction. */
|
|
|
|
|
if ((! mips_opts.mips16
|
|
|
|
|
&& (prev_prev_insn.insn_mo->pinfo & INSN_COPROC_MOVE_DELAY)
|
|
|
|
|
&& (prev_prev_insn.insn_mo->pinfo & INSN_WRITE_COND_CODE)
|
|
|
|
|
&& (pinfo & INSN_READ_COND_CODE)
|
|
|
|
|
&& ! cop_interlocks)
|
|
|
|
|
|| ((prev_prev_insn.insn_mo->pinfo & INSN_READ_LO)
|
|
|
|
|
&& (pinfo & INSN_WRITE_LO)
|
|
|
|
|
&& ! (hilo_interlocks
|
2004-01-22 00:25:38 +01:00
|
|
|
|
|| (mips_opts.arch == CPU_R3900 && (pinfo & INSN_MULT))))
|
1999-05-03 09:29:11 +02:00
|
|
|
|
|| ((prev_prev_insn.insn_mo->pinfo & INSN_READ_HI)
|
|
|
|
|
&& (pinfo & INSN_WRITE_HI)
|
|
|
|
|
&& ! (hilo_interlocks
|
2004-01-22 00:25:38 +01:00
|
|
|
|
|| (mips_opts.arch == CPU_R3900 && (pinfo & INSN_MULT)))))
|
1999-05-03 09:29:11 +02:00
|
|
|
|
prev_prev_nop = 1;
|
|
|
|
|
else
|
|
|
|
|
prev_prev_nop = 0;
|
|
|
|
|
|
|
|
|
|
if (prev_prev_insn_unreordered)
|
|
|
|
|
prev_prev_nop = 0;
|
|
|
|
|
|
|
|
|
|
if (prev_prev_nop && nops == 0)
|
|
|
|
|
++nops;
|
|
|
|
|
|
[gas/]
* doc/c-mips.texi: Add entries for -march=vr4120,vr4130,vr4181,
vr5400 and vr5500. Add entry for -mfix-vr4122-bugs.
* config/tc-mips.c (CPU_HAS_DROR, CPU_HAS_ROR): New macros.
(hilo_interlocks): True for CPU_VR5500.
(gpr_interlocks, cop_interlocks): True for CPU_VR5400 and CPU_VR5500.
(mips_fix_vr4122_bugs): New.
(append_insn): Work around 4122 errors if mips_fix_vr4122_bugs.
(mips_emit_delays): Likewise.
(macro2) [M_DROLI]: Use dror or dror32 if CPU_HAS_DROR.
[M_ROLI]: Likewise ror if CPU_HAS_ROR.
(validate_mips_insn, mips_ip): Handle '[', ']', 'e' and '%'.
(OPTION_FIX_VR4122, OPTION_NO_FIX_VR4122): New options.
(md_longopts): Add -mfix-vr4122-bugs and -no-mfix-vr4122-bugs.
(OPTION_ELF_BASE): Bump.
(md_parse_option): Handle the new options.
(mips_cpu_info_table): Add entries for vr4120, vr4130, vr4181,
vr5400 and vr5500.
[gas/testsuite/]
* gas/mips/mips4100.[sd]: Move dmadd16 and madd16 checks to...
* gas/mips/vr4111.[sd]: ...this new test.
* gas/mips/vr4120.[sd],
* gas/mips/vr4122.[sd],
* gas/mips/vr5400.[sd],
* gas/mips/vr5500.[sd]: New tests.
* mips.exp: Run them.
2002-09-30 14:04:54 +02:00
|
|
|
|
if (mips_fix_4122_bugs && prev_insn.insn_mo->name)
|
|
|
|
|
{
|
|
|
|
|
/* We're out of bits in pinfo, so we must resort to string
|
|
|
|
|
ops here. Shortcuts are selected based on opcodes being
|
|
|
|
|
limited to the VR4122 instruction set. */
|
|
|
|
|
int min_nops = 0;
|
|
|
|
|
const char *pn = prev_insn.insn_mo->name;
|
|
|
|
|
const char *tn = ip->insn_mo->name;
|
|
|
|
|
if (strncmp(pn, "macc", 4) == 0
|
|
|
|
|
|| strncmp(pn, "dmacc", 5) == 0)
|
|
|
|
|
{
|
|
|
|
|
/* Errata 21 - [D]DIV[U] after [D]MACC */
|
|
|
|
|
if (strstr (tn, "div"))
|
|
|
|
|
{
|
|
|
|
|
min_nops = 1;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/* Errata 23 - Continuous DMULT[U]/DMACC instructions */
|
|
|
|
|
if (pn[0] == 'd' /* dmacc */
|
|
|
|
|
&& (strncmp(tn, "dmult", 5) == 0
|
|
|
|
|
|| strncmp(tn, "dmacc", 5) == 0))
|
|
|
|
|
{
|
|
|
|
|
min_nops = 1;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/* Errata 24 - MT{LO,HI} after [D]MACC */
|
|
|
|
|
if (strcmp (tn, "mtlo") == 0
|
|
|
|
|
|| strcmp (tn, "mthi") == 0)
|
|
|
|
|
{
|
|
|
|
|
min_nops = 1;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
}
|
|
|
|
|
else if (strncmp(pn, "dmult", 5) == 0
|
|
|
|
|
&& (strncmp(tn, "dmult", 5) == 0
|
|
|
|
|
|| strncmp(tn, "dmacc", 5) == 0))
|
|
|
|
|
{
|
|
|
|
|
/* Here is the rest of errata 23. */
|
|
|
|
|
min_nops = 1;
|
|
|
|
|
}
|
|
|
|
|
if (nops < min_nops)
|
|
|
|
|
nops = min_nops;
|
|
|
|
|
}
|
|
|
|
|
|
1999-05-03 09:29:11 +02:00
|
|
|
|
/* If we are being given a nop instruction, don't bother with
|
|
|
|
|
one of the nops we would otherwise output. This will only
|
|
|
|
|
happen when a nop instruction is used with mips_optimize set
|
|
|
|
|
to 0. */
|
|
|
|
|
if (nops > 0
|
|
|
|
|
&& ! mips_opts.noreorder
|
2000-09-14 03:47:38 +02:00
|
|
|
|
&& ip->insn_opcode == (unsigned) (mips_opts.mips16 ? 0x6500 : 0))
|
1999-05-03 09:29:11 +02:00
|
|
|
|
--nops;
|
|
|
|
|
|
|
|
|
|
/* Now emit the right number of NOP instructions. */
|
|
|
|
|
if (nops > 0 && ! mips_opts.noreorder)
|
|
|
|
|
{
|
|
|
|
|
fragS *old_frag;
|
|
|
|
|
unsigned long old_frag_offset;
|
|
|
|
|
int i;
|
|
|
|
|
struct insn_label_list *l;
|
|
|
|
|
|
|
|
|
|
old_frag = frag_now;
|
|
|
|
|
old_frag_offset = frag_now_fix ();
|
|
|
|
|
|
|
|
|
|
for (i = 0; i < nops; i++)
|
|
|
|
|
emit_nop ();
|
|
|
|
|
|
|
|
|
|
if (listing)
|
|
|
|
|
{
|
|
|
|
|
listing_prev_line ();
|
|
|
|
|
/* We may be at the start of a variant frag. In case we
|
|
|
|
|
are, make sure there is enough space for the frag
|
|
|
|
|
after the frags created by listing_prev_line. The
|
|
|
|
|
argument to frag_grow here must be at least as large
|
|
|
|
|
as the argument to all other calls to frag_grow in
|
|
|
|
|
this file. We don't have to worry about being in the
|
|
|
|
|
middle of a variant frag, because the variants insert
|
|
|
|
|
all needed nop instructions themselves. */
|
|
|
|
|
frag_grow (40);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
for (l = insn_labels; l != NULL; l = l->next)
|
|
|
|
|
{
|
2001-06-08 08:07:13 +02:00
|
|
|
|
valueT val;
|
|
|
|
|
|
1999-05-03 09:29:11 +02:00
|
|
|
|
assert (S_GET_SEGMENT (l->label) == now_seg);
|
Add support for storing local symbols in a small structure to save
memory when assembling large files.
* as.h: Don't include struc-symbol.h.
(symbolS): Add typedef.
* symbols.c: Include struc-symbol.h.
(local_hash): New static variable.
(save_symbol_name): New static function, from symbol_create.
(symbol_create): Call save_symbol_name.
(local_symbol_count): New static variable.
(local_symbol_conversion_count): Likewise.
(LOCAL_SYMBOL_CHECK): Define.
(local_symbol_make): New static function.
(local_symbol_convert): New static function.
(colon): Handle local symbols. Create local symbol for local
label name.
(symbol_table_insert): Handle local symbols.
(symbol_find_or_make): Create local symbol for local label name.
(symbol_find_base): Check for local symbol.
(symbol_append, symbol_insert): Check for local symbols.
(symbol_clear_list_pointers, symbol_remove): Likewise.
(verify_symbol_chain): Likewise.
(copy_symbol_attributes): Likewise.
(resolve_symbol_value): Handle local symbols.
(resolve_local_symbol): New static function.
(resolve_local_symbol_values): New function.
(S_GET_VALUE, S_SET_VALUE): Handle local symbols.
(S_IS_FUNCTION, S_IS_EXTERNAL, S_IS_WEAK, S_IS_COMMON): Likewise.
(S_IS_DEFINED, S_IS_DEBUG, S_IS_LOCAL, S_GET_NAME): Likewise.
(S_GET_SEGMENT, S_SET_SEGMENT, S_SET_EXTERNAL): Likewise.
(S_CLEAR_EXTERNAL, S_SET_WEAK, S_SET_NAME): Likewise.
(symbol_previous, symbol_next): New functions.
(symbol_get_value_expression): Likewise.
(symbol_set_value_expression): Likewise.
(symbol_set_frag, symbol_get_frag): Likewise.
(symbol_mark_used, symbol_clear_used, symbol_used_p): Likewise.
(symbol_mark_used_in_reloc): Likewise.
(symbol_clear_used_in_reloc, symbol_used_in_reloc_p): Likewise.
(symbol_mark_mri_common, symbol_clear_mri_common): Likewise.
(symbol_mri_common_p): Likewise.
(symbol_mark_written, symbol_clear_written): Likewise.
(symbol_written_p): Likewise.
(symbol_mark_resolved, symbol_resolved_p): Likewise.
(symbol_section_p, symbol_equated_p): Likewise.
(symbol_constant_p): Likewise.
(symbol_get_bfdsym, symbol_set_bfdsym): Likewise.
(symbol_get_obj, symbol_set_obj): Likewise.
(symbol_get_tc, symbol_set_tc): Likewise.
(symbol_begin): Initialize local_hash.
(print_symbol_value_1): Handle local symbols.
(symbol_print_statistics): Print local symbol statistics.
* symbols.h: Include "struc-symbol.h" if not BFD_ASSEMBLER.
Declare new symbols.c functions. Move many declarations here from
struc-symbol.h.
(SYMBOLS_NEED_BACKPOINTERS): Define if needed.
* struc-symbol.h (SYMBOLS_NEED_BACKPOINTERS): Don't set.
(struct symbol): Move bsym to make it clearly the first field.
Remove TARGET_SYMBOL_FIELDS.
(symbolS): Don't typedef.
(struct broken_word): Remove.
(N_TYPE_seg, seg_N_TYPE): Move to symbol.h.
(SEGMENT_TO_SYMBOL_TYPE, N_REGISTER): Likewise.
(symbol_clear_list_pointers): Likewise.
(symbol_insert, symbol_remove): Likewise.
(symbol_previous, symbol_append): Likewise.
(verify_symbol_chain, verify_symbol_chain_2): Likewise.
(struct local_symbol): Define.
(local_symbol_converted_p, local_symbol_mark_converted): Define.
(local_symbol_resolved_p, local_symbol_mark_resolved): Define.
(local_symbol_get_frag, local_symbol_set_frag): Define.
(local_symbol_get_real_symbol): Define.
(local_symbol_set_real_symbol): Define.
Define.
* write.c (write_object_file): Call resolve_local_symbol_values.
* config/obj-ecoff.h (OBJ_SYMFIELD_TYPE): Define.
(TARGET_SYMBOL_FIELDS): Don't define.
* config/obj-elf.h (OBJ_SYMFIELD_TYPE): Add local field. If
ECOFF_DEBUGGING, add ECOFF fields.
(ELF_TARGET_SYMBOL_FIELDS, TARGET_SYMBOL_FIELDS): Don't define.
* config/obj-multi.h (struct elf_obj_sy): Add local field. If
ECOFF_DEBUGGING, add ECOFF fields.
(ELF_TARGET_SYMBOL_FIELDS, TARGET_SYMBOL_FIELDS): Don't define.
(ECOFF_DEBUG_TARGET_SYMBOL_FIELDS): Don't define.
* config/tc-mcore.h: Don't include struc-symbol.h.
(TARGET_SYMBOL_FIELDS): Don't define.
(struct mcore_tc_sy): Define.
(TC_SYMFIELD_TYPE): Define.
* Many files: Use symbolS instead of struct symbol. Use new
accessor functions rather than referring to symbolS fields
directly.
* read.c (s_mri_common): Don't add in value of line_label.
* config/tc-mips.c (md_apply_fix): Correct parenthesization when
checking for SEC_LINK_ONCE.
* config/tc-sh.h (sh_fix_adjustable): Declare.
1999-06-03 02:29:48 +02:00
|
|
|
|
symbol_set_frag (l->label, frag_now);
|
2001-06-08 08:07:13 +02:00
|
|
|
|
val = (valueT) frag_now_fix ();
|
1999-05-03 09:29:11 +02:00
|
|
|
|
/* mips16 text labels are stored as odd. */
|
|
|
|
|
if (mips_opts.mips16)
|
2002-05-26 20:46:37 +02:00
|
|
|
|
++val;
|
2001-06-08 08:07:13 +02:00
|
|
|
|
S_SET_VALUE (l->label, val);
|
1999-05-03 09:29:11 +02:00
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
#ifndef NO_ECOFF_DEBUGGING
|
|
|
|
|
if (ECOFF_DEBUGGING)
|
|
|
|
|
ecoff_fix_loc (old_frag, old_frag_offset);
|
|
|
|
|
#endif
|
|
|
|
|
}
|
|
|
|
|
else if (prev_nop_frag != NULL)
|
|
|
|
|
{
|
|
|
|
|
/* We have a frag holding nops we may be able to remove. If
|
|
|
|
|
we don't need any nops, we can decrease the size of
|
|
|
|
|
prev_nop_frag by the size of one instruction. If we do
|
2000-09-07 14:45:56 +02:00
|
|
|
|
need some nops, we count them in prev_nops_required. */
|
1999-05-03 09:29:11 +02:00
|
|
|
|
if (prev_nop_frag_since == 0)
|
|
|
|
|
{
|
|
|
|
|
if (nops == 0)
|
|
|
|
|
{
|
|
|
|
|
prev_nop_frag->fr_fix -= mips_opts.mips16 ? 2 : 4;
|
|
|
|
|
--prev_nop_frag_holds;
|
|
|
|
|
}
|
|
|
|
|
else
|
|
|
|
|
prev_nop_frag_required += nops;
|
|
|
|
|
}
|
|
|
|
|
else
|
|
|
|
|
{
|
|
|
|
|
if (prev_prev_nop == 0)
|
|
|
|
|
{
|
|
|
|
|
prev_nop_frag->fr_fix -= mips_opts.mips16 ? 2 : 4;
|
|
|
|
|
--prev_nop_frag_holds;
|
|
|
|
|
}
|
|
|
|
|
else
|
|
|
|
|
++prev_nop_frag_required;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
if (prev_nop_frag_holds <= prev_nop_frag_required)
|
|
|
|
|
prev_nop_frag = NULL;
|
|
|
|
|
|
|
|
|
|
++prev_nop_frag_since;
|
|
|
|
|
|
|
|
|
|
/* Sanity check: by the time we reach the second instruction
|
|
|
|
|
after prev_nop_frag, we should have used up all the nops
|
|
|
|
|
one way or another. */
|
|
|
|
|
assert (prev_nop_frag_since <= 1 || prev_nop_frag == NULL);
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
2004-01-14 19:01:09 +01:00
|
|
|
|
/* Record the frag type before frag_var. */
|
|
|
|
|
if (prev_insn_frag)
|
|
|
|
|
prev_insn_frag_type = prev_insn_frag->fr_type;
|
|
|
|
|
|
2002-10-12 07:23:33 +02:00
|
|
|
|
if (place == NULL
|
|
|
|
|
&& address_expr
|
2003-03-13 00:06:08 +01:00
|
|
|
|
&& *reloc_type == BFD_RELOC_16_PCREL_S2
|
2002-10-12 07:23:33 +02:00
|
|
|
|
&& (pinfo & INSN_UNCOND_BRANCH_DELAY || pinfo & INSN_COND_BRANCH_DELAY
|
|
|
|
|
|| pinfo & INSN_COND_BRANCH_LIKELY)
|
|
|
|
|
&& mips_relax_branch
|
|
|
|
|
/* Don't try branch relaxation within .set nomacro, or within
|
|
|
|
|
.set noat if we use $at for PIC computations. If it turns
|
|
|
|
|
out that the branch was out-of-range, we'll get an error. */
|
|
|
|
|
&& !mips_opts.warn_about_macros
|
|
|
|
|
&& !(mips_opts.noat && mips_pic != NO_PIC)
|
|
|
|
|
&& !mips_opts.mips16)
|
|
|
|
|
{
|
2004-01-14 19:01:09 +01:00
|
|
|
|
relaxed_branch = TRUE;
|
2002-10-12 07:23:33 +02:00
|
|
|
|
f = frag_var (rs_machine_dependent,
|
|
|
|
|
relaxed_branch_length
|
|
|
|
|
(NULL, NULL,
|
|
|
|
|
(pinfo & INSN_UNCOND_BRANCH_DELAY) ? -1
|
|
|
|
|
: (pinfo & INSN_COND_BRANCH_LIKELY) ? 1 : 0), 4,
|
|
|
|
|
RELAX_BRANCH_ENCODE
|
2002-12-12 05:40:07 +01:00
|
|
|
|
(pinfo & INSN_UNCOND_BRANCH_DELAY,
|
2002-10-12 07:23:33 +02:00
|
|
|
|
pinfo & INSN_COND_BRANCH_LIKELY,
|
|
|
|
|
pinfo & INSN_WRITE_GPR_31,
|
|
|
|
|
0),
|
|
|
|
|
address_expr->X_add_symbol,
|
|
|
|
|
address_expr->X_add_number,
|
|
|
|
|
0);
|
|
|
|
|
*reloc_type = BFD_RELOC_UNUSED;
|
|
|
|
|
}
|
|
|
|
|
else if (*reloc_type > BFD_RELOC_UNUSED)
|
1999-05-03 09:29:11 +02:00
|
|
|
|
{
|
|
|
|
|
/* We need to set up a variant frag. */
|
|
|
|
|
assert (mips_opts.mips16 && address_expr != NULL);
|
|
|
|
|
f = frag_var (rs_machine_dependent, 4, 0,
|
2001-10-04 22:07:00 +02:00
|
|
|
|
RELAX_MIPS16_ENCODE (*reloc_type - BFD_RELOC_UNUSED,
|
1999-05-03 09:29:11 +02:00
|
|
|
|
mips16_small, mips16_ext,
|
|
|
|
|
(prev_pinfo
|
|
|
|
|
& INSN_UNCOND_BRANCH_DELAY),
|
2001-10-04 22:07:00 +02:00
|
|
|
|
(*prev_insn_reloc_type
|
1999-05-03 09:29:11 +02:00
|
|
|
|
== BFD_RELOC_MIPS16_JMP)),
|
2001-11-12 23:19:30 +01:00
|
|
|
|
make_expr_symbol (address_expr), 0, NULL);
|
1999-05-03 09:29:11 +02:00
|
|
|
|
}
|
|
|
|
|
else if (place != NULL)
|
|
|
|
|
f = place;
|
|
|
|
|
else if (mips_opts.mips16
|
|
|
|
|
&& ! ip->use_extend
|
2001-10-04 22:07:00 +02:00
|
|
|
|
&& *reloc_type != BFD_RELOC_MIPS16_JMP)
|
1999-05-03 09:29:11 +02:00
|
|
|
|
{
|
|
|
|
|
/* Make sure there is enough room to swap this instruction with
|
|
|
|
|
a following jump instruction. */
|
|
|
|
|
frag_grow (6);
|
|
|
|
|
f = frag_more (2);
|
|
|
|
|
}
|
|
|
|
|
else
|
|
|
|
|
{
|
|
|
|
|
if (mips_opts.mips16
|
|
|
|
|
&& mips_opts.noreorder
|
|
|
|
|
&& (prev_pinfo & INSN_UNCOND_BRANCH_DELAY) != 0)
|
|
|
|
|
as_warn (_("extended instruction in delay slot"));
|
|
|
|
|
|
|
|
|
|
f = frag_more (4);
|
|
|
|
|
}
|
|
|
|
|
|
2001-10-04 22:07:00 +02:00
|
|
|
|
fixp[0] = fixp[1] = fixp[2] = NULL;
|
|
|
|
|
if (address_expr != NULL && *reloc_type < BFD_RELOC_UNUSED)
|
1999-05-03 09:29:11 +02:00
|
|
|
|
{
|
|
|
|
|
if (address_expr->X_op == O_constant)
|
|
|
|
|
{
|
2002-05-15 01:19:39 +02:00
|
|
|
|
valueT tmp;
|
2001-10-04 22:07:00 +02:00
|
|
|
|
|
|
|
|
|
switch (*reloc_type)
|
1999-05-03 09:29:11 +02:00
|
|
|
|
{
|
|
|
|
|
case BFD_RELOC_32:
|
|
|
|
|
ip->insn_opcode |= address_expr->X_add_number;
|
|
|
|
|
break;
|
|
|
|
|
|
2001-10-04 22:07:00 +02:00
|
|
|
|
case BFD_RELOC_MIPS_HIGHEST:
|
2003-06-30 06:10:48 +02:00
|
|
|
|
tmp = (address_expr->X_add_number
|
|
|
|
|
+ ((valueT) 0x8000 << 32) + 0x80008000) >> 16;
|
2001-10-04 22:07:00 +02:00
|
|
|
|
tmp >>= 16;
|
|
|
|
|
ip->insn_opcode |= (tmp >> 16) & 0xffff;
|
|
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
case BFD_RELOC_MIPS_HIGHER:
|
|
|
|
|
tmp = (address_expr->X_add_number + 0x80008000) >> 16;
|
|
|
|
|
ip->insn_opcode |= (tmp >> 16) & 0xffff;
|
|
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
case BFD_RELOC_HI16_S:
|
|
|
|
|
ip->insn_opcode |= ((address_expr->X_add_number + 0x8000)
|
|
|
|
|
>> 16) & 0xffff;
|
|
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
case BFD_RELOC_HI16:
|
|
|
|
|
ip->insn_opcode |= (address_expr->X_add_number >> 16) & 0xffff;
|
|
|
|
|
break;
|
|
|
|
|
|
1999-05-03 09:29:11 +02:00
|
|
|
|
case BFD_RELOC_LO16:
|
2002-09-18 04:25:19 +02:00
|
|
|
|
case BFD_RELOC_MIPS_GOT_DISP:
|
1999-05-03 09:29:11 +02:00
|
|
|
|
ip->insn_opcode |= address_expr->X_add_number & 0xffff;
|
|
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
case BFD_RELOC_MIPS_JMP:
|
|
|
|
|
if ((address_expr->X_add_number & 3) != 0)
|
|
|
|
|
as_bad (_("jump to misaligned address (0x%lx)"),
|
|
|
|
|
(unsigned long) address_expr->X_add_number);
|
2002-09-26 11:00:08 +02:00
|
|
|
|
if (address_expr->X_add_number & ~0xfffffff)
|
2001-12-04 15:05:54 +01:00
|
|
|
|
as_bad (_("jump address range overflow (0x%lx)"),
|
|
|
|
|
(unsigned long) address_expr->X_add_number);
|
1999-05-03 09:29:11 +02:00
|
|
|
|
ip->insn_opcode |= (address_expr->X_add_number >> 2) & 0x3ffffff;
|
|
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
case BFD_RELOC_MIPS16_JMP:
|
|
|
|
|
if ((address_expr->X_add_number & 3) != 0)
|
|
|
|
|
as_bad (_("jump to misaligned address (0x%lx)"),
|
|
|
|
|
(unsigned long) address_expr->X_add_number);
|
2002-09-26 11:00:08 +02:00
|
|
|
|
if (address_expr->X_add_number & ~0xfffffff)
|
2001-12-04 15:05:54 +01:00
|
|
|
|
as_bad (_("jump address range overflow (0x%lx)"),
|
|
|
|
|
(unsigned long) address_expr->X_add_number);
|
1999-05-03 09:29:11 +02:00
|
|
|
|
ip->insn_opcode |=
|
|
|
|
|
(((address_expr->X_add_number & 0x7c0000) << 3)
|
|
|
|
|
| ((address_expr->X_add_number & 0xf800000) >> 7)
|
|
|
|
|
| ((address_expr->X_add_number & 0x3fffc) >> 2));
|
|
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
case BFD_RELOC_16_PCREL_S2:
|
|
|
|
|
goto need_reloc;
|
|
|
|
|
|
|
|
|
|
default:
|
|
|
|
|
internalError ();
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
else
|
|
|
|
|
{
|
|
|
|
|
need_reloc:
|
2001-10-04 22:07:00 +02:00
|
|
|
|
/* Don't generate a reloc if we are writing into a variant frag. */
|
1999-05-03 09:29:11 +02:00
|
|
|
|
if (place == NULL)
|
|
|
|
|
{
|
2003-06-12 07:45:50 +02:00
|
|
|
|
reloc_howto_type *howto;
|
|
|
|
|
int i;
|
|
|
|
|
|
|
|
|
|
/* In a compound relocation, it is the final (outermost)
|
|
|
|
|
operator that determines the relocated field. */
|
|
|
|
|
for (i = 1; i < 3; i++)
|
|
|
|
|
if (reloc_type[i] == BFD_RELOC_UNUSED)
|
|
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
howto = bfd_reloc_type_lookup (stdoutput, reloc_type[i - 1]);
|
2003-05-22 11:19:33 +02:00
|
|
|
|
fixp[0] = fix_new_exp (frag_now, f - frag_now->fr_literal,
|
|
|
|
|
bfd_get_reloc_size(howto),
|
2001-10-04 22:07:00 +02:00
|
|
|
|
address_expr,
|
2003-05-22 11:19:33 +02:00
|
|
|
|
reloc_type[0] == BFD_RELOC_16_PCREL_S2,
|
2001-10-04 22:07:00 +02:00
|
|
|
|
reloc_type[0]);
|
|
|
|
|
|
2001-10-12 01:56:33 +02:00
|
|
|
|
/* These relocations can have an addend that won't fit in
|
2001-10-04 22:07:00 +02:00
|
|
|
|
4 octets for 64bit assembly. */
|
2003-05-22 11:19:33 +02:00
|
|
|
|
if (HAVE_64BIT_GPRS
|
|
|
|
|
&& ! howto->partial_inplace
|
|
|
|
|
&& (reloc_type[0] == BFD_RELOC_16
|
|
|
|
|
|| reloc_type[0] == BFD_RELOC_32
|
|
|
|
|
|| reloc_type[0] == BFD_RELOC_MIPS_JMP
|
|
|
|
|
|| reloc_type[0] == BFD_RELOC_HI16_S
|
|
|
|
|
|| reloc_type[0] == BFD_RELOC_LO16
|
|
|
|
|
|| reloc_type[0] == BFD_RELOC_GPREL16
|
|
|
|
|
|| reloc_type[0] == BFD_RELOC_MIPS_LITERAL
|
|
|
|
|
|| reloc_type[0] == BFD_RELOC_GPREL32
|
|
|
|
|
|| reloc_type[0] == BFD_RELOC_64
|
|
|
|
|
|| reloc_type[0] == BFD_RELOC_CTOR
|
|
|
|
|
|| reloc_type[0] == BFD_RELOC_MIPS_SUB
|
|
|
|
|
|| reloc_type[0] == BFD_RELOC_MIPS_HIGHEST
|
|
|
|
|
|| reloc_type[0] == BFD_RELOC_MIPS_HIGHER
|
|
|
|
|
|| reloc_type[0] == BFD_RELOC_MIPS_SCN_DISP
|
|
|
|
|
|| reloc_type[0] == BFD_RELOC_MIPS_REL16
|
|
|
|
|
|| reloc_type[0] == BFD_RELOC_MIPS_RELGOT))
|
2001-10-04 22:07:00 +02:00
|
|
|
|
fixp[0]->fx_no_overflow = 1;
|
|
|
|
|
|
2003-02-08 18:05:55 +01:00
|
|
|
|
if (reloc_needs_lo_p (*reloc_type))
|
1999-05-03 09:29:11 +02:00
|
|
|
|
{
|
|
|
|
|
struct mips_hi_fixup *hi_fixup;
|
|
|
|
|
|
2003-02-08 18:05:55 +01:00
|
|
|
|
/* Reuse the last entry if it already has a matching %lo. */
|
|
|
|
|
hi_fixup = mips_hi_fixup_list;
|
|
|
|
|
if (hi_fixup == 0
|
|
|
|
|
|| !fixup_has_matching_lo_p (hi_fixup->fixp))
|
|
|
|
|
{
|
|
|
|
|
hi_fixup = ((struct mips_hi_fixup *)
|
|
|
|
|
xmalloc (sizeof (struct mips_hi_fixup)));
|
|
|
|
|
hi_fixup->next = mips_hi_fixup_list;
|
|
|
|
|
mips_hi_fixup_list = hi_fixup;
|
|
|
|
|
}
|
2001-10-04 22:07:00 +02:00
|
|
|
|
hi_fixup->fixp = fixp[0];
|
1999-05-03 09:29:11 +02:00
|
|
|
|
hi_fixup->seg = now_seg;
|
|
|
|
|
}
|
2001-10-04 22:07:00 +02:00
|
|
|
|
|
2003-06-12 07:45:50 +02:00
|
|
|
|
/* Add fixups for the second and third relocations, if given.
|
|
|
|
|
Note that the ABI allows the second relocation to be
|
|
|
|
|
against RSS_UNDEF, RSS_GP, RSS_GP0 or RSS_LOC. At the
|
|
|
|
|
moment we only use RSS_UNDEF, but we could add support
|
|
|
|
|
for the others if it ever becomes necessary. */
|
|
|
|
|
for (i = 1; i < 3; i++)
|
|
|
|
|
if (reloc_type[i] != BFD_RELOC_UNUSED)
|
|
|
|
|
{
|
|
|
|
|
address_expr->X_op = O_absent;
|
|
|
|
|
address_expr->X_add_symbol = 0;
|
|
|
|
|
address_expr->X_add_number = 0;
|
|
|
|
|
|
|
|
|
|
fixp[i] = fix_new_exp (frag_now, fixp[0]->fx_where,
|
|
|
|
|
fixp[0]->fx_size, address_expr,
|
|
|
|
|
FALSE, reloc_type[i]);
|
|
|
|
|
}
|
1999-05-03 09:29:11 +02:00
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
if (! mips_opts.mips16)
|
2002-06-08 07:37:29 +02:00
|
|
|
|
{
|
|
|
|
|
md_number_to_chars (f, ip->insn_opcode, 4);
|
|
|
|
|
#ifdef OBJ_ELF
|
|
|
|
|
dwarf2_emit_insn (4);
|
|
|
|
|
#endif
|
|
|
|
|
}
|
2001-10-04 22:07:00 +02:00
|
|
|
|
else if (*reloc_type == BFD_RELOC_MIPS16_JMP)
|
1999-05-03 09:29:11 +02:00
|
|
|
|
{
|
|
|
|
|
md_number_to_chars (f, ip->insn_opcode >> 16, 2);
|
|
|
|
|
md_number_to_chars (f + 2, ip->insn_opcode & 0xffff, 2);
|
2002-06-08 07:37:29 +02:00
|
|
|
|
#ifdef OBJ_ELF
|
|
|
|
|
dwarf2_emit_insn (4);
|
|
|
|
|
#endif
|
1999-05-03 09:29:11 +02:00
|
|
|
|
}
|
|
|
|
|
else
|
|
|
|
|
{
|
|
|
|
|
if (ip->use_extend)
|
|
|
|
|
{
|
|
|
|
|
md_number_to_chars (f, 0xf000 | ip->extend, 2);
|
|
|
|
|
f += 2;
|
|
|
|
|
}
|
|
|
|
|
md_number_to_chars (f, ip->insn_opcode, 2);
|
2002-06-08 07:37:29 +02:00
|
|
|
|
#ifdef OBJ_ELF
|
|
|
|
|
dwarf2_emit_insn (ip->use_extend ? 4 : 2);
|
|
|
|
|
#endif
|
1999-05-03 09:29:11 +02:00
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/* Update the register mask information. */
|
|
|
|
|
if (! mips_opts.mips16)
|
|
|
|
|
{
|
|
|
|
|
if (pinfo & INSN_WRITE_GPR_D)
|
|
|
|
|
mips_gprmask |= 1 << ((ip->insn_opcode >> OP_SH_RD) & OP_MASK_RD);
|
|
|
|
|
if ((pinfo & (INSN_WRITE_GPR_T | INSN_READ_GPR_T)) != 0)
|
|
|
|
|
mips_gprmask |= 1 << ((ip->insn_opcode >> OP_SH_RT) & OP_MASK_RT);
|
|
|
|
|
if (pinfo & INSN_READ_GPR_S)
|
|
|
|
|
mips_gprmask |= 1 << ((ip->insn_opcode >> OP_SH_RS) & OP_MASK_RS);
|
|
|
|
|
if (pinfo & INSN_WRITE_GPR_31)
|
2002-05-26 20:46:37 +02:00
|
|
|
|
mips_gprmask |= 1 << RA;
|
1999-05-03 09:29:11 +02:00
|
|
|
|
if (pinfo & INSN_WRITE_FPR_D)
|
|
|
|
|
mips_cprmask[1] |= 1 << ((ip->insn_opcode >> OP_SH_FD) & OP_MASK_FD);
|
|
|
|
|
if ((pinfo & (INSN_WRITE_FPR_S | INSN_READ_FPR_S)) != 0)
|
|
|
|
|
mips_cprmask[1] |= 1 << ((ip->insn_opcode >> OP_SH_FS) & OP_MASK_FS);
|
|
|
|
|
if ((pinfo & (INSN_WRITE_FPR_T | INSN_READ_FPR_T)) != 0)
|
|
|
|
|
mips_cprmask[1] |= 1 << ((ip->insn_opcode >> OP_SH_FT) & OP_MASK_FT);
|
|
|
|
|
if ((pinfo & INSN_READ_FPR_R) != 0)
|
|
|
|
|
mips_cprmask[1] |= 1 << ((ip->insn_opcode >> OP_SH_FR) & OP_MASK_FR);
|
|
|
|
|
if (pinfo & INSN_COP)
|
|
|
|
|
{
|
2000-09-07 14:45:56 +02:00
|
|
|
|
/* We don't keep enough information to sort these cases out.
|
|
|
|
|
The itbl support does keep this information however, although
|
|
|
|
|
we currently don't support itbl fprmats as part of the cop
|
|
|
|
|
instruction. May want to add this support in the future. */
|
1999-05-03 09:29:11 +02:00
|
|
|
|
}
|
|
|
|
|
/* Never set the bit for $0, which is always zero. */
|
2000-12-05 19:51:08 +01:00
|
|
|
|
mips_gprmask &= ~1 << 0;
|
1999-05-03 09:29:11 +02:00
|
|
|
|
}
|
|
|
|
|
else
|
|
|
|
|
{
|
|
|
|
|
if (pinfo & (MIPS16_INSN_WRITE_X | MIPS16_INSN_READ_X))
|
|
|
|
|
mips_gprmask |= 1 << ((ip->insn_opcode >> MIPS16OP_SH_RX)
|
|
|
|
|
& MIPS16OP_MASK_RX);
|
|
|
|
|
if (pinfo & (MIPS16_INSN_WRITE_Y | MIPS16_INSN_READ_Y))
|
|
|
|
|
mips_gprmask |= 1 << ((ip->insn_opcode >> MIPS16OP_SH_RY)
|
|
|
|
|
& MIPS16OP_MASK_RY);
|
|
|
|
|
if (pinfo & MIPS16_INSN_WRITE_Z)
|
|
|
|
|
mips_gprmask |= 1 << ((ip->insn_opcode >> MIPS16OP_SH_RZ)
|
|
|
|
|
& MIPS16OP_MASK_RZ);
|
|
|
|
|
if (pinfo & (MIPS16_INSN_WRITE_T | MIPS16_INSN_READ_T))
|
|
|
|
|
mips_gprmask |= 1 << TREG;
|
|
|
|
|
if (pinfo & (MIPS16_INSN_WRITE_SP | MIPS16_INSN_READ_SP))
|
|
|
|
|
mips_gprmask |= 1 << SP;
|
|
|
|
|
if (pinfo & (MIPS16_INSN_WRITE_31 | MIPS16_INSN_READ_31))
|
|
|
|
|
mips_gprmask |= 1 << RA;
|
|
|
|
|
if (pinfo & MIPS16_INSN_WRITE_GPR_Y)
|
|
|
|
|
mips_gprmask |= 1 << MIPS16OP_EXTRACT_REG32R (ip->insn_opcode);
|
|
|
|
|
if (pinfo & MIPS16_INSN_READ_Z)
|
|
|
|
|
mips_gprmask |= 1 << ((ip->insn_opcode >> MIPS16OP_SH_MOVE32Z)
|
|
|
|
|
& MIPS16OP_MASK_MOVE32Z);
|
|
|
|
|
if (pinfo & MIPS16_INSN_READ_GPR_X)
|
|
|
|
|
mips_gprmask |= 1 << ((ip->insn_opcode >> MIPS16OP_SH_REGR32)
|
|
|
|
|
& MIPS16OP_MASK_REGR32);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
if (place == NULL && ! mips_opts.noreorder)
|
|
|
|
|
{
|
|
|
|
|
/* Filling the branch delay slot is more complex. We try to
|
|
|
|
|
switch the branch with the previous instruction, which we can
|
|
|
|
|
do if the previous instruction does not set up a condition
|
|
|
|
|
that the branch tests and if the branch is not itself the
|
|
|
|
|
target of any branch. */
|
|
|
|
|
if ((pinfo & INSN_UNCOND_BRANCH_DELAY)
|
|
|
|
|
|| (pinfo & INSN_COND_BRANCH_DELAY))
|
|
|
|
|
{
|
|
|
|
|
if (mips_optimize < 2
|
|
|
|
|
/* If we have seen .set volatile or .set nomove, don't
|
|
|
|
|
optimize. */
|
|
|
|
|
|| mips_opts.nomove != 0
|
|
|
|
|
/* If we had to emit any NOP instructions, then we
|
|
|
|
|
already know we can not swap. */
|
|
|
|
|
|| nops != 0
|
|
|
|
|
/* If we don't even know the previous insn, we can not
|
2000-09-07 14:45:56 +02:00
|
|
|
|
swap. */
|
1999-05-03 09:29:11 +02:00
|
|
|
|
|| ! prev_insn_valid
|
|
|
|
|
/* If the previous insn is already in a branch delay
|
|
|
|
|
slot, then we can not swap. */
|
|
|
|
|
|| prev_insn_is_delay_slot
|
|
|
|
|
/* If the previous previous insn was in a .set
|
|
|
|
|
noreorder, we can't swap. Actually, the MIPS
|
|
|
|
|
assembler will swap in this situation. However, gcc
|
|
|
|
|
configured -with-gnu-as will generate code like
|
|
|
|
|
.set noreorder
|
|
|
|
|
lw $4,XXX
|
|
|
|
|
.set reorder
|
|
|
|
|
INSN
|
|
|
|
|
bne $4,$0,foo
|
|
|
|
|
in which we can not swap the bne and INSN. If gcc is
|
|
|
|
|
not configured -with-gnu-as, it does not output the
|
|
|
|
|
.set pseudo-ops. We don't have to check
|
|
|
|
|
prev_insn_unreordered, because prev_insn_valid will
|
|
|
|
|
be 0 in that case. We don't want to use
|
|
|
|
|
prev_prev_insn_valid, because we do want to be able
|
|
|
|
|
to swap at the start of a function. */
|
|
|
|
|
|| prev_prev_insn_unreordered
|
|
|
|
|
/* If the branch is itself the target of a branch, we
|
|
|
|
|
can not swap. We cheat on this; all we check for is
|
|
|
|
|
whether there is a label on this instruction. If
|
|
|
|
|
there are any branches to anything other than a
|
|
|
|
|
label, users must use .set noreorder. */
|
|
|
|
|
|| insn_labels != NULL
|
2004-01-14 19:01:09 +01:00
|
|
|
|
/* If the previous instruction is in a variant frag
|
|
|
|
|
other than this branch's one, we cannot do the swap.
|
|
|
|
|
This does not apply to the mips16, which uses variant
|
|
|
|
|
frags for different purposes. */
|
1999-05-03 09:29:11 +02:00
|
|
|
|
|| (! mips_opts.mips16
|
2004-01-14 19:01:09 +01:00
|
|
|
|
&& prev_insn_frag_type == rs_machine_dependent)
|
1999-05-03 09:29:11 +02:00
|
|
|
|
/* If the branch reads the condition codes, we don't
|
|
|
|
|
even try to swap, because in the sequence
|
|
|
|
|
ctc1 $X,$31
|
|
|
|
|
INSN
|
|
|
|
|
INSN
|
|
|
|
|
bc1t LABEL
|
|
|
|
|
we can not swap, and I don't feel like handling that
|
|
|
|
|
case. */
|
|
|
|
|
|| (! mips_opts.mips16
|
2004-01-09 03:16:30 +01:00
|
|
|
|
&& (pinfo & INSN_READ_COND_CODE)
|
|
|
|
|
&& ! cop_interlocks)
|
1999-05-03 09:29:11 +02:00
|
|
|
|
/* We can not swap with an instruction that requires a
|
2003-11-22 03:35:31 +01:00
|
|
|
|
delay slot, because the target of the branch might
|
1999-05-03 09:29:11 +02:00
|
|
|
|
interfere with that instruction. */
|
|
|
|
|
|| (! mips_opts.mips16
|
|
|
|
|
&& (prev_pinfo
|
2000-09-07 14:45:56 +02:00
|
|
|
|
/* Itbl support may require additional care here. */
|
1999-05-03 09:29:11 +02:00
|
|
|
|
& (INSN_LOAD_COPROC_DELAY
|
|
|
|
|
| INSN_COPROC_MOVE_DELAY
|
2004-01-09 03:16:30 +01:00
|
|
|
|
| INSN_WRITE_COND_CODE))
|
|
|
|
|
&& ! cop_interlocks)
|
1999-05-03 09:29:11 +02:00
|
|
|
|
|| (! (hilo_interlocks
|
2004-01-22 00:25:38 +01:00
|
|
|
|
|| (mips_opts.arch == CPU_R3900 && (pinfo & INSN_MULT)))
|
1999-05-03 09:29:11 +02:00
|
|
|
|
&& (prev_pinfo
|
|
|
|
|
& (INSN_READ_LO
|
|
|
|
|
| INSN_READ_HI)))
|
|
|
|
|
|| (! mips_opts.mips16
|
2004-01-09 03:16:30 +01:00
|
|
|
|
&& (prev_pinfo & INSN_LOAD_MEMORY_DELAY)
|
|
|
|
|
&& ! gpr_interlocks)
|
1999-05-03 09:29:11 +02:00
|
|
|
|
|| (! mips_opts.mips16
|
2000-09-07 14:45:56 +02:00
|
|
|
|
/* Itbl support may require additional care here. */
|
2004-01-09 03:16:30 +01:00
|
|
|
|
&& (prev_pinfo & INSN_COPROC_MEMORY_DELAY)
|
|
|
|
|
&& ! cop_mem_interlocks)
|
1999-05-03 09:29:11 +02:00
|
|
|
|
/* We can not swap with a branch instruction. */
|
|
|
|
|
|| (prev_pinfo
|
|
|
|
|
& (INSN_UNCOND_BRANCH_DELAY
|
|
|
|
|
| INSN_COND_BRANCH_DELAY
|
|
|
|
|
| INSN_COND_BRANCH_LIKELY))
|
|
|
|
|
/* We do not swap with a trap instruction, since it
|
|
|
|
|
complicates trap handlers to have the trap
|
|
|
|
|
instruction be in a delay slot. */
|
|
|
|
|
|| (prev_pinfo & INSN_TRAP)
|
|
|
|
|
/* If the branch reads a register that the previous
|
|
|
|
|
instruction sets, we can not swap. */
|
|
|
|
|
|| (! mips_opts.mips16
|
|
|
|
|
&& (prev_pinfo & INSN_WRITE_GPR_T)
|
|
|
|
|
&& insn_uses_reg (ip,
|
|
|
|
|
((prev_insn.insn_opcode >> OP_SH_RT)
|
|
|
|
|
& OP_MASK_RT),
|
|
|
|
|
MIPS_GR_REG))
|
|
|
|
|
|| (! mips_opts.mips16
|
|
|
|
|
&& (prev_pinfo & INSN_WRITE_GPR_D)
|
|
|
|
|
&& insn_uses_reg (ip,
|
|
|
|
|
((prev_insn.insn_opcode >> OP_SH_RD)
|
|
|
|
|
& OP_MASK_RD),
|
|
|
|
|
MIPS_GR_REG))
|
|
|
|
|
|| (mips_opts.mips16
|
|
|
|
|
&& (((prev_pinfo & MIPS16_INSN_WRITE_X)
|
|
|
|
|
&& insn_uses_reg (ip,
|
|
|
|
|
((prev_insn.insn_opcode
|
|
|
|
|
>> MIPS16OP_SH_RX)
|
|
|
|
|
& MIPS16OP_MASK_RX),
|
|
|
|
|
MIPS16_REG))
|
|
|
|
|
|| ((prev_pinfo & MIPS16_INSN_WRITE_Y)
|
|
|
|
|
&& insn_uses_reg (ip,
|
|
|
|
|
((prev_insn.insn_opcode
|
|
|
|
|
>> MIPS16OP_SH_RY)
|
|
|
|
|
& MIPS16OP_MASK_RY),
|
|
|
|
|
MIPS16_REG))
|
|
|
|
|
|| ((prev_pinfo & MIPS16_INSN_WRITE_Z)
|
|
|
|
|
&& insn_uses_reg (ip,
|
|
|
|
|
((prev_insn.insn_opcode
|
|
|
|
|
>> MIPS16OP_SH_RZ)
|
|
|
|
|
& MIPS16OP_MASK_RZ),
|
|
|
|
|
MIPS16_REG))
|
|
|
|
|
|| ((prev_pinfo & MIPS16_INSN_WRITE_T)
|
|
|
|
|
&& insn_uses_reg (ip, TREG, MIPS_GR_REG))
|
|
|
|
|
|| ((prev_pinfo & MIPS16_INSN_WRITE_31)
|
|
|
|
|
&& insn_uses_reg (ip, RA, MIPS_GR_REG))
|
|
|
|
|
|| ((prev_pinfo & MIPS16_INSN_WRITE_GPR_Y)
|
|
|
|
|
&& insn_uses_reg (ip,
|
|
|
|
|
MIPS16OP_EXTRACT_REG32R (prev_insn.
|
|
|
|
|
insn_opcode),
|
|
|
|
|
MIPS_GR_REG))))
|
|
|
|
|
/* If the branch writes a register that the previous
|
|
|
|
|
instruction sets, we can not swap (we know that
|
|
|
|
|
branches write only to RD or to $31). */
|
|
|
|
|
|| (! mips_opts.mips16
|
|
|
|
|
&& (prev_pinfo & INSN_WRITE_GPR_T)
|
|
|
|
|
&& (((pinfo & INSN_WRITE_GPR_D)
|
|
|
|
|
&& (((prev_insn.insn_opcode >> OP_SH_RT) & OP_MASK_RT)
|
|
|
|
|
== ((ip->insn_opcode >> OP_SH_RD) & OP_MASK_RD)))
|
|
|
|
|
|| ((pinfo & INSN_WRITE_GPR_31)
|
|
|
|
|
&& (((prev_insn.insn_opcode >> OP_SH_RT)
|
|
|
|
|
& OP_MASK_RT)
|
2002-05-26 20:46:37 +02:00
|
|
|
|
== RA))))
|
1999-05-03 09:29:11 +02:00
|
|
|
|
|| (! mips_opts.mips16
|
|
|
|
|
&& (prev_pinfo & INSN_WRITE_GPR_D)
|
|
|
|
|
&& (((pinfo & INSN_WRITE_GPR_D)
|
|
|
|
|
&& (((prev_insn.insn_opcode >> OP_SH_RD) & OP_MASK_RD)
|
|
|
|
|
== ((ip->insn_opcode >> OP_SH_RD) & OP_MASK_RD)))
|
|
|
|
|
|| ((pinfo & INSN_WRITE_GPR_31)
|
|
|
|
|
&& (((prev_insn.insn_opcode >> OP_SH_RD)
|
|
|
|
|
& OP_MASK_RD)
|
2002-05-26 20:46:37 +02:00
|
|
|
|
== RA))))
|
1999-05-03 09:29:11 +02:00
|
|
|
|
|| (mips_opts.mips16
|
|
|
|
|
&& (pinfo & MIPS16_INSN_WRITE_31)
|
|
|
|
|
&& ((prev_pinfo & MIPS16_INSN_WRITE_31)
|
|
|
|
|
|| ((prev_pinfo & MIPS16_INSN_WRITE_GPR_Y)
|
|
|
|
|
&& (MIPS16OP_EXTRACT_REG32R (prev_insn.insn_opcode)
|
|
|
|
|
== RA))))
|
|
|
|
|
/* If the branch writes a register that the previous
|
|
|
|
|
instruction reads, we can not swap (we know that
|
|
|
|
|
branches only write to RD or to $31). */
|
|
|
|
|
|| (! mips_opts.mips16
|
|
|
|
|
&& (pinfo & INSN_WRITE_GPR_D)
|
|
|
|
|
&& insn_uses_reg (&prev_insn,
|
|
|
|
|
((ip->insn_opcode >> OP_SH_RD)
|
|
|
|
|
& OP_MASK_RD),
|
|
|
|
|
MIPS_GR_REG))
|
|
|
|
|
|| (! mips_opts.mips16
|
|
|
|
|
&& (pinfo & INSN_WRITE_GPR_31)
|
2002-05-26 20:46:37 +02:00
|
|
|
|
&& insn_uses_reg (&prev_insn, RA, MIPS_GR_REG))
|
1999-05-03 09:29:11 +02:00
|
|
|
|
|| (mips_opts.mips16
|
|
|
|
|
&& (pinfo & MIPS16_INSN_WRITE_31)
|
|
|
|
|
&& insn_uses_reg (&prev_insn, RA, MIPS_GR_REG))
|
|
|
|
|
/* If we are generating embedded PIC code, the branch
|
|
|
|
|
might be expanded into a sequence which uses $at, so
|
|
|
|
|
we can't swap with an instruction which reads it. */
|
|
|
|
|
|| (mips_pic == EMBEDDED_PIC
|
|
|
|
|
&& insn_uses_reg (&prev_insn, AT, MIPS_GR_REG))
|
|
|
|
|
/* If the previous previous instruction has a load
|
|
|
|
|
delay, and sets a register that the branch reads, we
|
|
|
|
|
can not swap. */
|
|
|
|
|
|| (! mips_opts.mips16
|
2000-09-07 14:45:56 +02:00
|
|
|
|
/* Itbl support may require additional care here. */
|
2004-01-09 03:16:30 +01:00
|
|
|
|
&& (((prev_prev_insn.insn_mo->pinfo & INSN_LOAD_COPROC_DELAY)
|
|
|
|
|
&& ! cop_interlocks)
|
|
|
|
|
|| ((prev_prev_insn.insn_mo->pinfo
|
|
|
|
|
& INSN_LOAD_MEMORY_DELAY)
|
|
|
|
|
&& ! gpr_interlocks))
|
1999-05-03 09:29:11 +02:00
|
|
|
|
&& insn_uses_reg (ip,
|
|
|
|
|
((prev_prev_insn.insn_opcode >> OP_SH_RT)
|
|
|
|
|
& OP_MASK_RT),
|
|
|
|
|
MIPS_GR_REG))
|
|
|
|
|
/* If one instruction sets a condition code and the
|
|
|
|
|
other one uses a condition code, we can not swap. */
|
|
|
|
|
|| ((pinfo & INSN_READ_COND_CODE)
|
|
|
|
|
&& (prev_pinfo & INSN_WRITE_COND_CODE))
|
|
|
|
|
|| ((pinfo & INSN_WRITE_COND_CODE)
|
|
|
|
|
&& (prev_pinfo & INSN_READ_COND_CODE))
|
|
|
|
|
/* If the previous instruction uses the PC, we can not
|
|
|
|
|
swap. */
|
|
|
|
|
|| (mips_opts.mips16
|
|
|
|
|
&& (prev_pinfo & MIPS16_INSN_READ_PC))
|
|
|
|
|
/* If the previous instruction was extended, we can not
|
|
|
|
|
swap. */
|
|
|
|
|
|| (mips_opts.mips16 && prev_insn_extended)
|
|
|
|
|
/* If the previous instruction had a fixup in mips16
|
|
|
|
|
mode, we can not swap. This normally means that the
|
|
|
|
|
previous instruction was a 4 byte branch anyhow. */
|
2001-10-04 22:07:00 +02:00
|
|
|
|
|| (mips_opts.mips16 && prev_insn_fixp[0])
|
2000-09-07 14:45:56 +02:00
|
|
|
|
/* If the previous instruction is a sync, sync.l, or
|
|
|
|
|
sync.p, we can not swap. */
|
1999-08-03 17:22:38 +02:00
|
|
|
|
|| (prev_pinfo & INSN_SYNC))
|
1999-05-03 09:29:11 +02:00
|
|
|
|
{
|
|
|
|
|
/* We could do even better for unconditional branches to
|
|
|
|
|
portions of this object file; we could pick up the
|
|
|
|
|
instruction at the destination, put it in the delay
|
|
|
|
|
slot, and bump the destination address. */
|
|
|
|
|
emit_nop ();
|
|
|
|
|
/* Update the previous insn information. */
|
|
|
|
|
prev_prev_insn = *ip;
|
|
|
|
|
prev_insn.insn_mo = &dummy_opcode;
|
|
|
|
|
}
|
|
|
|
|
else
|
|
|
|
|
{
|
|
|
|
|
/* It looks like we can actually do the swap. */
|
|
|
|
|
if (! mips_opts.mips16)
|
|
|
|
|
{
|
|
|
|
|
char *prev_f;
|
|
|
|
|
char temp[4];
|
|
|
|
|
|
|
|
|
|
prev_f = prev_insn_frag->fr_literal + prev_insn_where;
|
2004-01-14 19:01:09 +01:00
|
|
|
|
if (!relaxed_branch)
|
|
|
|
|
{
|
|
|
|
|
/* If this is not a relaxed branch, then just
|
|
|
|
|
swap the instructions. */
|
|
|
|
|
memcpy (temp, prev_f, 4);
|
|
|
|
|
memcpy (prev_f, f, 4);
|
|
|
|
|
memcpy (f, temp, 4);
|
|
|
|
|
}
|
|
|
|
|
else
|
|
|
|
|
{
|
|
|
|
|
/* If this is a relaxed branch, then we move the
|
|
|
|
|
instruction to be placed in the delay slot to
|
|
|
|
|
the current frag, shrinking the fixed part of
|
|
|
|
|
the originating frag. If the branch occupies
|
|
|
|
|
the tail of the latter, we move it backwards,
|
|
|
|
|
into the space freed by the moved instruction. */
|
|
|
|
|
f = frag_more (4);
|
|
|
|
|
memcpy (f, prev_f, 4);
|
|
|
|
|
prev_insn_frag->fr_fix -= 4;
|
|
|
|
|
if (prev_insn_frag->fr_type == rs_machine_dependent)
|
|
|
|
|
memmove (prev_f, prev_f + 4, prev_insn_frag->fr_var);
|
|
|
|
|
}
|
|
|
|
|
|
2001-10-04 22:07:00 +02:00
|
|
|
|
if (prev_insn_fixp[0])
|
|
|
|
|
{
|
|
|
|
|
prev_insn_fixp[0]->fx_frag = frag_now;
|
|
|
|
|
prev_insn_fixp[0]->fx_where = f - frag_now->fr_literal;
|
|
|
|
|
}
|
|
|
|
|
if (prev_insn_fixp[1])
|
|
|
|
|
{
|
|
|
|
|
prev_insn_fixp[1]->fx_frag = frag_now;
|
|
|
|
|
prev_insn_fixp[1]->fx_where = f - frag_now->fr_literal;
|
|
|
|
|
}
|
|
|
|
|
if (prev_insn_fixp[2])
|
1999-05-03 09:29:11 +02:00
|
|
|
|
{
|
2001-10-04 22:07:00 +02:00
|
|
|
|
prev_insn_fixp[2]->fx_frag = frag_now;
|
|
|
|
|
prev_insn_fixp[2]->fx_where = f - frag_now->fr_literal;
|
1999-05-03 09:29:11 +02:00
|
|
|
|
}
|
* config/tc-mips.h (tc_frag_data_type, TC_FRAG_TYPE): New.
* config/tc-mips.c: Use signed add for n32 address arithmetic.
(append_insn): When filling delay slots with instructions
that have fixups that tc_gen_reloc might consider modifyable
in variant frags, start a new frag.
(load_address): Generate GOT_DISP with of without offset
depending on whether symbol is local. For -xgot, use
GOT_PAGE/GOT_OFST or GOT_HI16/GOT_LO16.
(macro) <M_DLA_AB, M_LA_AB>: Likewise.
<M_JAL_A>: In NewABI, use CALL16 or GOT_DISP for small got,
CALL_HI16/CALL_LO16 or GOT_PAGE/GOT_OFST for big got.
<ld_st>: In NewABI with small got, always use
GOT_PAGE/GOT_OFST, with the latter in the load/store
instruction. With big got, use GOT_HI16/GOT_LO16 or
GOT_PAGE/GOT_OFST.
(tc_gen_reloc): Adjust variant frags with GOT_DISP in NewABI.
Add tc_frag_data.tc_fr_offset to addends. Decay CALL16,
GOT_OFST and GOT_DISP to GOT_DISP in NewABI.
(md_convert_frag): Use memmove for safe copying of overlapping
regions.
2003-04-11 03:56:50 +02:00
|
|
|
|
if (prev_insn_fixp[0] && HAVE_NEWABI
|
|
|
|
|
&& prev_insn_frag != frag_now
|
|
|
|
|
&& (prev_insn_fixp[0]->fx_r_type
|
|
|
|
|
== BFD_RELOC_MIPS_GOT_DISP
|
|
|
|
|
|| (prev_insn_fixp[0]->fx_r_type
|
|
|
|
|
== BFD_RELOC_MIPS_CALL16)))
|
|
|
|
|
{
|
|
|
|
|
/* To avoid confusion in tc_gen_reloc, we must
|
|
|
|
|
ensure that this does not become a variant
|
|
|
|
|
frag. */
|
|
|
|
|
force_new_frag = TRUE;
|
|
|
|
|
}
|
2004-01-14 19:01:09 +01:00
|
|
|
|
|
|
|
|
|
if (!relaxed_branch)
|
2001-10-04 22:07:00 +02:00
|
|
|
|
{
|
2004-01-14 19:01:09 +01:00
|
|
|
|
if (fixp[0])
|
|
|
|
|
{
|
|
|
|
|
fixp[0]->fx_frag = prev_insn_frag;
|
|
|
|
|
fixp[0]->fx_where = prev_insn_where;
|
|
|
|
|
}
|
|
|
|
|
if (fixp[1])
|
|
|
|
|
{
|
|
|
|
|
fixp[1]->fx_frag = prev_insn_frag;
|
|
|
|
|
fixp[1]->fx_where = prev_insn_where;
|
|
|
|
|
}
|
|
|
|
|
if (fixp[2])
|
|
|
|
|
{
|
|
|
|
|
fixp[2]->fx_frag = prev_insn_frag;
|
|
|
|
|
fixp[2]->fx_where = prev_insn_where;
|
|
|
|
|
}
|
2001-10-04 22:07:00 +02:00
|
|
|
|
}
|
2004-01-14 19:01:09 +01:00
|
|
|
|
else if (prev_insn_frag->fr_type == rs_machine_dependent)
|
2001-10-04 22:07:00 +02:00
|
|
|
|
{
|
2004-01-14 19:01:09 +01:00
|
|
|
|
if (fixp[0])
|
|
|
|
|
fixp[0]->fx_where -= 4;
|
|
|
|
|
if (fixp[1])
|
|
|
|
|
fixp[1]->fx_where -= 4;
|
|
|
|
|
if (fixp[2])
|
|
|
|
|
fixp[2]->fx_where -= 4;
|
1999-05-03 09:29:11 +02:00
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
else
|
|
|
|
|
{
|
|
|
|
|
char *prev_f;
|
|
|
|
|
char temp[2];
|
|
|
|
|
|
2001-10-04 22:07:00 +02:00
|
|
|
|
assert (prev_insn_fixp[0] == NULL);
|
|
|
|
|
assert (prev_insn_fixp[1] == NULL);
|
|
|
|
|
assert (prev_insn_fixp[2] == NULL);
|
1999-05-03 09:29:11 +02:00
|
|
|
|
prev_f = prev_insn_frag->fr_literal + prev_insn_where;
|
|
|
|
|
memcpy (temp, prev_f, 2);
|
|
|
|
|
memcpy (prev_f, f, 2);
|
2001-10-04 22:07:00 +02:00
|
|
|
|
if (*reloc_type != BFD_RELOC_MIPS16_JMP)
|
1999-05-03 09:29:11 +02:00
|
|
|
|
{
|
2001-10-04 22:07:00 +02:00
|
|
|
|
assert (*reloc_type == BFD_RELOC_UNUSED);
|
1999-05-03 09:29:11 +02:00
|
|
|
|
memcpy (f, temp, 2);
|
|
|
|
|
}
|
|
|
|
|
else
|
|
|
|
|
{
|
|
|
|
|
memcpy (f, f + 2, 2);
|
|
|
|
|
memcpy (f + 2, temp, 2);
|
|
|
|
|
}
|
2001-10-04 22:07:00 +02:00
|
|
|
|
if (fixp[0])
|
|
|
|
|
{
|
|
|
|
|
fixp[0]->fx_frag = prev_insn_frag;
|
|
|
|
|
fixp[0]->fx_where = prev_insn_where;
|
|
|
|
|
}
|
|
|
|
|
if (fixp[1])
|
|
|
|
|
{
|
|
|
|
|
fixp[1]->fx_frag = prev_insn_frag;
|
|
|
|
|
fixp[1]->fx_where = prev_insn_where;
|
|
|
|
|
}
|
|
|
|
|
if (fixp[2])
|
1999-05-03 09:29:11 +02:00
|
|
|
|
{
|
2001-10-04 22:07:00 +02:00
|
|
|
|
fixp[2]->fx_frag = prev_insn_frag;
|
|
|
|
|
fixp[2]->fx_where = prev_insn_where;
|
1999-05-03 09:29:11 +02:00
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/* Update the previous insn information; leave prev_insn
|
|
|
|
|
unchanged. */
|
|
|
|
|
prev_prev_insn = *ip;
|
|
|
|
|
}
|
|
|
|
|
prev_insn_is_delay_slot = 1;
|
|
|
|
|
|
|
|
|
|
/* If that was an unconditional branch, forget the previous
|
|
|
|
|
insn information. */
|
|
|
|
|
if (pinfo & INSN_UNCOND_BRANCH_DELAY)
|
|
|
|
|
{
|
|
|
|
|
prev_prev_insn.insn_mo = &dummy_opcode;
|
|
|
|
|
prev_insn.insn_mo = &dummy_opcode;
|
|
|
|
|
}
|
|
|
|
|
|
2001-10-04 22:07:00 +02:00
|
|
|
|
prev_insn_fixp[0] = NULL;
|
|
|
|
|
prev_insn_fixp[1] = NULL;
|
|
|
|
|
prev_insn_fixp[2] = NULL;
|
|
|
|
|
prev_insn_reloc_type[0] = BFD_RELOC_UNUSED;
|
|
|
|
|
prev_insn_reloc_type[1] = BFD_RELOC_UNUSED;
|
|
|
|
|
prev_insn_reloc_type[2] = BFD_RELOC_UNUSED;
|
1999-05-03 09:29:11 +02:00
|
|
|
|
prev_insn_extended = 0;
|
|
|
|
|
}
|
|
|
|
|
else if (pinfo & INSN_COND_BRANCH_LIKELY)
|
|
|
|
|
{
|
|
|
|
|
/* We don't yet optimize a branch likely. What we should do
|
|
|
|
|
is look at the target, copy the instruction found there
|
|
|
|
|
into the delay slot, and increment the branch to jump to
|
|
|
|
|
the next instruction. */
|
|
|
|
|
emit_nop ();
|
|
|
|
|
/* Update the previous insn information. */
|
|
|
|
|
prev_prev_insn = *ip;
|
|
|
|
|
prev_insn.insn_mo = &dummy_opcode;
|
2001-10-04 22:07:00 +02:00
|
|
|
|
prev_insn_fixp[0] = NULL;
|
|
|
|
|
prev_insn_fixp[1] = NULL;
|
|
|
|
|
prev_insn_fixp[2] = NULL;
|
|
|
|
|
prev_insn_reloc_type[0] = BFD_RELOC_UNUSED;
|
|
|
|
|
prev_insn_reloc_type[1] = BFD_RELOC_UNUSED;
|
|
|
|
|
prev_insn_reloc_type[2] = BFD_RELOC_UNUSED;
|
1999-05-03 09:29:11 +02:00
|
|
|
|
prev_insn_extended = 0;
|
|
|
|
|
}
|
|
|
|
|
else
|
|
|
|
|
{
|
|
|
|
|
/* Update the previous insn information. */
|
|
|
|
|
if (nops > 0)
|
|
|
|
|
prev_prev_insn.insn_mo = &dummy_opcode;
|
|
|
|
|
else
|
|
|
|
|
prev_prev_insn = prev_insn;
|
|
|
|
|
prev_insn = *ip;
|
|
|
|
|
|
|
|
|
|
/* Any time we see a branch, we always fill the delay slot
|
|
|
|
|
immediately; since this insn is not a branch, we know it
|
|
|
|
|
is not in a delay slot. */
|
|
|
|
|
prev_insn_is_delay_slot = 0;
|
|
|
|
|
|
2001-10-04 22:07:00 +02:00
|
|
|
|
prev_insn_fixp[0] = fixp[0];
|
|
|
|
|
prev_insn_fixp[1] = fixp[1];
|
|
|
|
|
prev_insn_fixp[2] = fixp[2];
|
|
|
|
|
prev_insn_reloc_type[0] = reloc_type[0];
|
|
|
|
|
prev_insn_reloc_type[1] = reloc_type[1];
|
|
|
|
|
prev_insn_reloc_type[2] = reloc_type[2];
|
1999-05-03 09:29:11 +02:00
|
|
|
|
if (mips_opts.mips16)
|
|
|
|
|
prev_insn_extended = (ip->use_extend
|
2001-10-04 22:07:00 +02:00
|
|
|
|
|| *reloc_type > BFD_RELOC_UNUSED);
|
1999-05-03 09:29:11 +02:00
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
prev_prev_insn_unreordered = prev_insn_unreordered;
|
|
|
|
|
prev_insn_unreordered = 0;
|
|
|
|
|
prev_insn_frag = frag_now;
|
|
|
|
|
prev_insn_where = f - frag_now->fr_literal;
|
|
|
|
|
prev_insn_valid = 1;
|
|
|
|
|
}
|
|
|
|
|
else if (place == NULL)
|
|
|
|
|
{
|
|
|
|
|
/* We need to record a bit of information even when we are not
|
|
|
|
|
reordering, in order to determine the base address for mips16
|
|
|
|
|
PC relative relocs. */
|
|
|
|
|
prev_prev_insn = prev_insn;
|
|
|
|
|
prev_insn = *ip;
|
2001-10-04 22:07:00 +02:00
|
|
|
|
prev_insn_reloc_type[0] = reloc_type[0];
|
|
|
|
|
prev_insn_reloc_type[1] = reloc_type[1];
|
|
|
|
|
prev_insn_reloc_type[2] = reloc_type[2];
|
1999-05-03 09:29:11 +02:00
|
|
|
|
prev_prev_insn_unreordered = prev_insn_unreordered;
|
|
|
|
|
prev_insn_unreordered = 1;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/* We just output an insn, so the next one doesn't have a label. */
|
|
|
|
|
mips_clear_insn_labels ();
|
* config/tc-mips.h (tc_frag_data_type, TC_FRAG_TYPE): New.
* config/tc-mips.c: Use signed add for n32 address arithmetic.
(append_insn): When filling delay slots with instructions
that have fixups that tc_gen_reloc might consider modifyable
in variant frags, start a new frag.
(load_address): Generate GOT_DISP with of without offset
depending on whether symbol is local. For -xgot, use
GOT_PAGE/GOT_OFST or GOT_HI16/GOT_LO16.
(macro) <M_DLA_AB, M_LA_AB>: Likewise.
<M_JAL_A>: In NewABI, use CALL16 or GOT_DISP for small got,
CALL_HI16/CALL_LO16 or GOT_PAGE/GOT_OFST for big got.
<ld_st>: In NewABI with small got, always use
GOT_PAGE/GOT_OFST, with the latter in the load/store
instruction. With big got, use GOT_HI16/GOT_LO16 or
GOT_PAGE/GOT_OFST.
(tc_gen_reloc): Adjust variant frags with GOT_DISP in NewABI.
Add tc_frag_data.tc_fr_offset to addends. Decay CALL16,
GOT_OFST and GOT_DISP to GOT_DISP in NewABI.
(md_convert_frag): Use memmove for safe copying of overlapping
regions.
2003-04-11 03:56:50 +02:00
|
|
|
|
|
|
|
|
|
/* We must ensure that the frag to which an instruction that was
|
|
|
|
|
moved from a non-variant frag doesn't become a variant frag,
|
|
|
|
|
otherwise tc_gen_reloc may get confused. */
|
|
|
|
|
if (force_new_frag)
|
|
|
|
|
{
|
|
|
|
|
frag_wane (frag_now);
|
|
|
|
|
frag_new (0);
|
|
|
|
|
}
|
1999-05-03 09:29:11 +02:00
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/* This function forgets that there was any previous instruction or
|
|
|
|
|
label. If PRESERVE is non-zero, it remembers enough information to
|
2000-09-07 14:45:56 +02:00
|
|
|
|
know whether nops are needed before a noreorder section. */
|
1999-05-03 09:29:11 +02:00
|
|
|
|
|
|
|
|
|
static void
|
2003-06-30 14:44:25 +02:00
|
|
|
|
mips_no_prev_insn (int preserve)
|
1999-05-03 09:29:11 +02:00
|
|
|
|
{
|
|
|
|
|
if (! preserve)
|
|
|
|
|
{
|
|
|
|
|
prev_insn.insn_mo = &dummy_opcode;
|
|
|
|
|
prev_prev_insn.insn_mo = &dummy_opcode;
|
|
|
|
|
prev_nop_frag = NULL;
|
|
|
|
|
prev_nop_frag_holds = 0;
|
|
|
|
|
prev_nop_frag_required = 0;
|
|
|
|
|
prev_nop_frag_since = 0;
|
|
|
|
|
}
|
|
|
|
|
prev_insn_valid = 0;
|
|
|
|
|
prev_insn_is_delay_slot = 0;
|
|
|
|
|
prev_insn_unreordered = 0;
|
|
|
|
|
prev_insn_extended = 0;
|
2001-10-04 22:07:00 +02:00
|
|
|
|
prev_insn_reloc_type[0] = BFD_RELOC_UNUSED;
|
|
|
|
|
prev_insn_reloc_type[1] = BFD_RELOC_UNUSED;
|
|
|
|
|
prev_insn_reloc_type[2] = BFD_RELOC_UNUSED;
|
1999-05-03 09:29:11 +02:00
|
|
|
|
prev_prev_insn_unreordered = 0;
|
|
|
|
|
mips_clear_insn_labels ();
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/* This function must be called whenever we turn on noreorder or emit
|
|
|
|
|
something other than instructions. It inserts any NOPS which might
|
|
|
|
|
be needed by the previous instruction, and clears the information
|
|
|
|
|
kept for the previous instructions. The INSNS parameter is true if
|
2000-09-07 14:45:56 +02:00
|
|
|
|
instructions are to follow. */
|
1999-05-03 09:29:11 +02:00
|
|
|
|
|
|
|
|
|
static void
|
2003-06-30 14:44:25 +02:00
|
|
|
|
mips_emit_delays (bfd_boolean insns)
|
1999-05-03 09:29:11 +02:00
|
|
|
|
{
|
|
|
|
|
if (! mips_opts.noreorder)
|
|
|
|
|
{
|
|
|
|
|
int nops;
|
|
|
|
|
|
|
|
|
|
nops = 0;
|
|
|
|
|
if ((! mips_opts.mips16
|
2004-01-09 03:16:30 +01:00
|
|
|
|
&& ((prev_insn.insn_mo->pinfo
|
|
|
|
|
& (INSN_LOAD_COPROC_DELAY
|
|
|
|
|
| INSN_COPROC_MOVE_DELAY
|
|
|
|
|
| INSN_WRITE_COND_CODE))
|
|
|
|
|
&& ! cop_interlocks))
|
1999-05-03 09:29:11 +02:00
|
|
|
|
|| (! hilo_interlocks
|
|
|
|
|
&& (prev_insn.insn_mo->pinfo
|
|
|
|
|
& (INSN_READ_LO
|
|
|
|
|
| INSN_READ_HI)))
|
|
|
|
|
|| (! mips_opts.mips16
|
2004-01-09 03:16:30 +01:00
|
|
|
|
&& (prev_insn.insn_mo->pinfo & INSN_LOAD_MEMORY_DELAY)
|
|
|
|
|
&& ! gpr_interlocks)
|
1999-05-03 09:29:11 +02:00
|
|
|
|
|| (! mips_opts.mips16
|
2004-01-09 03:16:30 +01:00
|
|
|
|
&& (prev_insn.insn_mo->pinfo & INSN_COPROC_MEMORY_DELAY)
|
|
|
|
|
&& ! cop_mem_interlocks))
|
1999-05-03 09:29:11 +02:00
|
|
|
|
{
|
2000-12-05 19:51:08 +01:00
|
|
|
|
/* Itbl support may require additional care here. */
|
1999-05-03 09:29:11 +02:00
|
|
|
|
++nops;
|
|
|
|
|
if ((! mips_opts.mips16
|
2004-01-09 03:16:30 +01:00
|
|
|
|
&& ((prev_insn.insn_mo->pinfo & INSN_WRITE_COND_CODE)
|
|
|
|
|
&& ! cop_interlocks))
|
1999-05-03 09:29:11 +02:00
|
|
|
|
|| (! hilo_interlocks
|
|
|
|
|
&& ((prev_insn.insn_mo->pinfo & INSN_READ_HI)
|
|
|
|
|
|| (prev_insn.insn_mo->pinfo & INSN_READ_LO))))
|
|
|
|
|
++nops;
|
|
|
|
|
|
|
|
|
|
if (prev_insn_unreordered)
|
|
|
|
|
nops = 0;
|
|
|
|
|
}
|
|
|
|
|
else if ((! mips_opts.mips16
|
2004-01-09 03:16:30 +01:00
|
|
|
|
&& ((prev_prev_insn.insn_mo->pinfo & INSN_WRITE_COND_CODE)
|
|
|
|
|
&& ! cop_interlocks))
|
1999-05-03 09:29:11 +02:00
|
|
|
|
|| (! hilo_interlocks
|
|
|
|
|
&& ((prev_prev_insn.insn_mo->pinfo & INSN_READ_HI)
|
|
|
|
|
|| (prev_prev_insn.insn_mo->pinfo & INSN_READ_LO))))
|
|
|
|
|
{
|
2000-12-05 19:51:08 +01:00
|
|
|
|
/* Itbl support may require additional care here. */
|
1999-05-03 09:29:11 +02:00
|
|
|
|
if (! prev_prev_insn_unreordered)
|
|
|
|
|
++nops;
|
|
|
|
|
}
|
|
|
|
|
|
[gas/]
* doc/c-mips.texi: Add entries for -march=vr4120,vr4130,vr4181,
vr5400 and vr5500. Add entry for -mfix-vr4122-bugs.
* config/tc-mips.c (CPU_HAS_DROR, CPU_HAS_ROR): New macros.
(hilo_interlocks): True for CPU_VR5500.
(gpr_interlocks, cop_interlocks): True for CPU_VR5400 and CPU_VR5500.
(mips_fix_vr4122_bugs): New.
(append_insn): Work around 4122 errors if mips_fix_vr4122_bugs.
(mips_emit_delays): Likewise.
(macro2) [M_DROLI]: Use dror or dror32 if CPU_HAS_DROR.
[M_ROLI]: Likewise ror if CPU_HAS_ROR.
(validate_mips_insn, mips_ip): Handle '[', ']', 'e' and '%'.
(OPTION_FIX_VR4122, OPTION_NO_FIX_VR4122): New options.
(md_longopts): Add -mfix-vr4122-bugs and -no-mfix-vr4122-bugs.
(OPTION_ELF_BASE): Bump.
(md_parse_option): Handle the new options.
(mips_cpu_info_table): Add entries for vr4120, vr4130, vr4181,
vr5400 and vr5500.
[gas/testsuite/]
* gas/mips/mips4100.[sd]: Move dmadd16 and madd16 checks to...
* gas/mips/vr4111.[sd]: ...this new test.
* gas/mips/vr4120.[sd],
* gas/mips/vr4122.[sd],
* gas/mips/vr5400.[sd],
* gas/mips/vr5500.[sd]: New tests.
* mips.exp: Run them.
2002-09-30 14:04:54 +02:00
|
|
|
|
if (mips_fix_4122_bugs && prev_insn.insn_mo->name)
|
|
|
|
|
{
|
|
|
|
|
int min_nops = 0;
|
|
|
|
|
const char *pn = prev_insn.insn_mo->name;
|
|
|
|
|
if (strncmp(pn, "macc", 4) == 0
|
|
|
|
|
|| strncmp(pn, "dmacc", 5) == 0
|
|
|
|
|
|| strncmp(pn, "dmult", 5) == 0)
|
|
|
|
|
{
|
|
|
|
|
min_nops = 1;
|
|
|
|
|
}
|
|
|
|
|
if (nops < min_nops)
|
|
|
|
|
nops = min_nops;
|
|
|
|
|
}
|
|
|
|
|
|
1999-05-03 09:29:11 +02:00
|
|
|
|
if (nops > 0)
|
|
|
|
|
{
|
|
|
|
|
struct insn_label_list *l;
|
|
|
|
|
|
|
|
|
|
if (insns)
|
|
|
|
|
{
|
|
|
|
|
/* Record the frag which holds the nop instructions, so
|
|
|
|
|
that we can remove them if we don't need them. */
|
|
|
|
|
frag_grow (mips_opts.mips16 ? nops * 2 : nops * 4);
|
|
|
|
|
prev_nop_frag = frag_now;
|
|
|
|
|
prev_nop_frag_holds = nops;
|
|
|
|
|
prev_nop_frag_required = 0;
|
|
|
|
|
prev_nop_frag_since = 0;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
for (; nops > 0; --nops)
|
|
|
|
|
emit_nop ();
|
|
|
|
|
|
|
|
|
|
if (insns)
|
|
|
|
|
{
|
|
|
|
|
/* Move on to a new frag, so that it is safe to simply
|
2000-09-07 14:45:56 +02:00
|
|
|
|
decrease the size of prev_nop_frag. */
|
1999-05-03 09:29:11 +02:00
|
|
|
|
frag_wane (frag_now);
|
|
|
|
|
frag_new (0);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
for (l = insn_labels; l != NULL; l = l->next)
|
|
|
|
|
{
|
2001-06-08 08:07:13 +02:00
|
|
|
|
valueT val;
|
|
|
|
|
|
1999-05-03 09:29:11 +02:00
|
|
|
|
assert (S_GET_SEGMENT (l->label) == now_seg);
|
Add support for storing local symbols in a small structure to save
memory when assembling large files.
* as.h: Don't include struc-symbol.h.
(symbolS): Add typedef.
* symbols.c: Include struc-symbol.h.
(local_hash): New static variable.
(save_symbol_name): New static function, from symbol_create.
(symbol_create): Call save_symbol_name.
(local_symbol_count): New static variable.
(local_symbol_conversion_count): Likewise.
(LOCAL_SYMBOL_CHECK): Define.
(local_symbol_make): New static function.
(local_symbol_convert): New static function.
(colon): Handle local symbols. Create local symbol for local
label name.
(symbol_table_insert): Handle local symbols.
(symbol_find_or_make): Create local symbol for local label name.
(symbol_find_base): Check for local symbol.
(symbol_append, symbol_insert): Check for local symbols.
(symbol_clear_list_pointers, symbol_remove): Likewise.
(verify_symbol_chain): Likewise.
(copy_symbol_attributes): Likewise.
(resolve_symbol_value): Handle local symbols.
(resolve_local_symbol): New static function.
(resolve_local_symbol_values): New function.
(S_GET_VALUE, S_SET_VALUE): Handle local symbols.
(S_IS_FUNCTION, S_IS_EXTERNAL, S_IS_WEAK, S_IS_COMMON): Likewise.
(S_IS_DEFINED, S_IS_DEBUG, S_IS_LOCAL, S_GET_NAME): Likewise.
(S_GET_SEGMENT, S_SET_SEGMENT, S_SET_EXTERNAL): Likewise.
(S_CLEAR_EXTERNAL, S_SET_WEAK, S_SET_NAME): Likewise.
(symbol_previous, symbol_next): New functions.
(symbol_get_value_expression): Likewise.
(symbol_set_value_expression): Likewise.
(symbol_set_frag, symbol_get_frag): Likewise.
(symbol_mark_used, symbol_clear_used, symbol_used_p): Likewise.
(symbol_mark_used_in_reloc): Likewise.
(symbol_clear_used_in_reloc, symbol_used_in_reloc_p): Likewise.
(symbol_mark_mri_common, symbol_clear_mri_common): Likewise.
(symbol_mri_common_p): Likewise.
(symbol_mark_written, symbol_clear_written): Likewise.
(symbol_written_p): Likewise.
(symbol_mark_resolved, symbol_resolved_p): Likewise.
(symbol_section_p, symbol_equated_p): Likewise.
(symbol_constant_p): Likewise.
(symbol_get_bfdsym, symbol_set_bfdsym): Likewise.
(symbol_get_obj, symbol_set_obj): Likewise.
(symbol_get_tc, symbol_set_tc): Likewise.
(symbol_begin): Initialize local_hash.
(print_symbol_value_1): Handle local symbols.
(symbol_print_statistics): Print local symbol statistics.
* symbols.h: Include "struc-symbol.h" if not BFD_ASSEMBLER.
Declare new symbols.c functions. Move many declarations here from
struc-symbol.h.
(SYMBOLS_NEED_BACKPOINTERS): Define if needed.
* struc-symbol.h (SYMBOLS_NEED_BACKPOINTERS): Don't set.
(struct symbol): Move bsym to make it clearly the first field.
Remove TARGET_SYMBOL_FIELDS.
(symbolS): Don't typedef.
(struct broken_word): Remove.
(N_TYPE_seg, seg_N_TYPE): Move to symbol.h.
(SEGMENT_TO_SYMBOL_TYPE, N_REGISTER): Likewise.
(symbol_clear_list_pointers): Likewise.
(symbol_insert, symbol_remove): Likewise.
(symbol_previous, symbol_append): Likewise.
(verify_symbol_chain, verify_symbol_chain_2): Likewise.
(struct local_symbol): Define.
(local_symbol_converted_p, local_symbol_mark_converted): Define.
(local_symbol_resolved_p, local_symbol_mark_resolved): Define.
(local_symbol_get_frag, local_symbol_set_frag): Define.
(local_symbol_get_real_symbol): Define.
(local_symbol_set_real_symbol): Define.
Define.
* write.c (write_object_file): Call resolve_local_symbol_values.
* config/obj-ecoff.h (OBJ_SYMFIELD_TYPE): Define.
(TARGET_SYMBOL_FIELDS): Don't define.
* config/obj-elf.h (OBJ_SYMFIELD_TYPE): Add local field. If
ECOFF_DEBUGGING, add ECOFF fields.
(ELF_TARGET_SYMBOL_FIELDS, TARGET_SYMBOL_FIELDS): Don't define.
* config/obj-multi.h (struct elf_obj_sy): Add local field. If
ECOFF_DEBUGGING, add ECOFF fields.
(ELF_TARGET_SYMBOL_FIELDS, TARGET_SYMBOL_FIELDS): Don't define.
(ECOFF_DEBUG_TARGET_SYMBOL_FIELDS): Don't define.
* config/tc-mcore.h: Don't include struc-symbol.h.
(TARGET_SYMBOL_FIELDS): Don't define.
(struct mcore_tc_sy): Define.
(TC_SYMFIELD_TYPE): Define.
* Many files: Use symbolS instead of struct symbol. Use new
accessor functions rather than referring to symbolS fields
directly.
* read.c (s_mri_common): Don't add in value of line_label.
* config/tc-mips.c (md_apply_fix): Correct parenthesization when
checking for SEC_LINK_ONCE.
* config/tc-sh.h (sh_fix_adjustable): Declare.
1999-06-03 02:29:48 +02:00
|
|
|
|
symbol_set_frag (l->label, frag_now);
|
2001-06-08 08:07:13 +02:00
|
|
|
|
val = (valueT) frag_now_fix ();
|
1999-05-03 09:29:11 +02:00
|
|
|
|
/* mips16 text labels are stored as odd. */
|
|
|
|
|
if (mips_opts.mips16)
|
2002-05-26 20:46:37 +02:00
|
|
|
|
++val;
|
2001-06-08 08:07:13 +02:00
|
|
|
|
S_SET_VALUE (l->label, val);
|
1999-05-03 09:29:11 +02:00
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/* Mark instruction labels in mips16 mode. */
|
2002-05-26 20:46:37 +02:00
|
|
|
|
if (insns)
|
1999-05-03 09:29:11 +02:00
|
|
|
|
mips16_mark_labels ();
|
|
|
|
|
|
|
|
|
|
mips_no_prev_insn (insns);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/* Build an instruction created by a macro expansion. This is passed
|
|
|
|
|
a pointer to the count of instructions created so far, an
|
|
|
|
|
expression, the name of the instruction to build, an operand format
|
|
|
|
|
string, and corresponding arguments. */
|
|
|
|
|
|
|
|
|
|
static void
|
2003-06-30 14:44:25 +02:00
|
|
|
|
macro_build (char *place, int *counter, expressionS *ep, const char *name,
|
|
|
|
|
const char *fmt, ...)
|
1999-05-03 09:29:11 +02:00
|
|
|
|
{
|
|
|
|
|
struct mips_cl_insn insn;
|
2001-10-04 22:07:00 +02:00
|
|
|
|
bfd_reloc_code_real_type r[3];
|
1999-05-03 09:29:11 +02:00
|
|
|
|
va_list args;
|
|
|
|
|
|
|
|
|
|
va_start (args, fmt);
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* If the macro is about to expand into a second instruction,
|
|
|
|
|
* print a warning if needed. We need to pass ip as a parameter
|
|
|
|
|
* to generate a better warning message here...
|
|
|
|
|
*/
|
|
|
|
|
if (mips_opts.warn_about_macros && place == NULL && *counter == 1)
|
|
|
|
|
as_warn (_("Macro instruction expanded into multiple instructions"));
|
|
|
|
|
|
2002-04-22 23:21:06 +02:00
|
|
|
|
/*
|
|
|
|
|
* If the macro is about to expand into a second instruction,
|
|
|
|
|
* and it is in a delay slot, print a warning.
|
|
|
|
|
*/
|
|
|
|
|
if (place == NULL
|
|
|
|
|
&& *counter == 1
|
|
|
|
|
&& mips_opts.noreorder
|
|
|
|
|
&& (prev_prev_insn.insn_mo->pinfo
|
|
|
|
|
& (INSN_UNCOND_BRANCH_DELAY | INSN_COND_BRANCH_DELAY
|
2002-04-22 23:50:44 +02:00
|
|
|
|
| INSN_COND_BRANCH_LIKELY)) != 0)
|
2002-04-22 23:21:06 +02:00
|
|
|
|
as_warn (_("Macro instruction expanded into multiple instructions in a branch delay slot"));
|
|
|
|
|
|
1999-05-03 09:29:11 +02:00
|
|
|
|
if (place == NULL)
|
2002-05-26 20:46:37 +02:00
|
|
|
|
++*counter; /* bump instruction counter */
|
1999-05-03 09:29:11 +02:00
|
|
|
|
|
|
|
|
|
if (mips_opts.mips16)
|
|
|
|
|
{
|
|
|
|
|
mips16_macro_build (place, counter, ep, name, fmt, args);
|
|
|
|
|
va_end (args);
|
|
|
|
|
return;
|
|
|
|
|
}
|
|
|
|
|
|
2001-10-04 22:07:00 +02:00
|
|
|
|
r[0] = BFD_RELOC_UNUSED;
|
|
|
|
|
r[1] = BFD_RELOC_UNUSED;
|
|
|
|
|
r[2] = BFD_RELOC_UNUSED;
|
1999-05-03 09:29:11 +02:00
|
|
|
|
insn.insn_mo = (struct mips_opcode *) hash_find (op_hash, name);
|
|
|
|
|
assert (insn.insn_mo);
|
|
|
|
|
assert (strcmp (name, insn.insn_mo->name) == 0);
|
|
|
|
|
|
|
|
|
|
/* Search until we get a match for NAME. */
|
|
|
|
|
while (1)
|
|
|
|
|
{
|
2002-11-30 09:39:46 +01:00
|
|
|
|
/* It is assumed here that macros will never generate
|
[ gas/ChangeLog ]
2002-05-30 Chris G. Demetriou <cgd@broadcom.com>
Ed Satterthwaite <ehs@broadcom.com>
* config/tc-mips.c (mips_set_options): New "ase_mdmx" member.
(mips_opts): Initialize "ase_mdmx" member.
(file_ase_mdmx): New variable.
(CPU_HAS_MDMX): New macro.
(md_begin): Initialize mips_opts.ase_mdmx and file_ase_mdmx
based on command line options and configuration defaults.
(macro_build): Note in comment that use of MDMX in macros is
not currently allowed.
(validate_mips_insn): Add support for the "O", "Q", "X", "Y", and
"Z" MDMX operand types.
(mips_ip): Accept MDMX instructions if mips_opts.ase_mdmx is set,
and add support for the "O", "Q", "X", "Y", and "Z" MDMX operand
types.
(OPTION_MDMX, OPTION_NO_MDMX, md_longopts, md_parse_option):
Add support for "-mdmx" and "-no-mdmx" options.
(OPTION_ELF_BASE): Move to accomodate new options.
(s_mipsset): Support ".set mdmx" and ".set nomdmx".
(mips_elf_final_processing): Set MDMX ASE ELF header flag if
file_ase_mdmx was set.
* doc/as.texinfo: Document -mdmx and -no-mdmx options.
* doc/c-mips.texi: Likewise, and document ".set mdmx" and ".set
nomdmx" directives.
[ gas/testsuite/ChangeLog ]
2002-05-30 Chris G. Demetriou <cgd@broadcom.com>
* gas/mips/mips64-mdmx.s: New file.
* gas/mips/mips64-mdmx.d: Likewise.
* gas/mips/mips.exp: Run new "mips64-mdmx" test.
[ include/opcode/ChangeLog ]
2002-05-30 Chris G. Demetriou <cgd@broadcom.com>
* mips.h (OP_SH_ALN, OP_MASK_ALN, OP_SH_VSEL, OP_MASK_VSEL)
(MDMX_FMTSEL_IMM_QH, MDMX_FMTSEL_IMM_OB, MDMX_FMTSEL_VEC_QH)
(MDMX_FMTSEL_VEC_OB, INSN_READ_MDMX_ACC, INSN_WRITE_MDMX_ACC)
(INSN_MDMX): New constants, for MDMX support.
(opcode character list): Add "O", "Q", "X", "Y", and "Z" for MDMX.
[ opcodes/ChangeLog ]
2002-05-30 Chris G. Demetriou <cgd@broadcom.com>
Ed Satterthwaite <ehs@broadcom.com>
* mips-dis.c (print_insn_arg): Add support for 'O', 'Q', 'X', 'Y',
and 'Z' formats, for MDMX.
(mips_isa_type): Add MDMX instructions to the ISA
bit mask for bfd_mach_mipsisa64.
* mips-opc.c: Add support for MDMX instructions.
(MX): New definition.
* mips-dis.c: Update copyright years to include 2002.
2002-05-31 03:17:18 +02:00
|
|
|
|
MDMX or MIPS-3D instructions. */
|
1999-05-03 09:29:11 +02:00
|
|
|
|
if (strcmp (fmt, insn.insn_mo->args) == 0
|
|
|
|
|
&& insn.insn_mo->pinfo != INSN_MACRO
|
2002-07-09 16:21:40 +02:00
|
|
|
|
&& OPCODE_IS_MEMBER (insn.insn_mo,
|
|
|
|
|
(mips_opts.isa
|
2002-09-26 11:56:35 +02:00
|
|
|
|
| (file_ase_mips16 ? INSN_MIPS16 : 0)),
|
2003-06-29 21:41:33 +02:00
|
|
|
|
mips_opts.arch)
|
|
|
|
|
&& (mips_opts.arch != CPU_R4650 || (insn.insn_mo->pinfo & FP_D) == 0))
|
1999-05-03 09:29:11 +02:00
|
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
++insn.insn_mo;
|
|
|
|
|
assert (insn.insn_mo->name);
|
|
|
|
|
assert (strcmp (name, insn.insn_mo->name) == 0);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
insn.insn_opcode = insn.insn_mo->match;
|
|
|
|
|
for (;;)
|
|
|
|
|
{
|
|
|
|
|
switch (*fmt++)
|
|
|
|
|
{
|
|
|
|
|
case '\0':
|
|
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
case ',':
|
|
|
|
|
case '(':
|
|
|
|
|
case ')':
|
|
|
|
|
continue;
|
|
|
|
|
|
[ bfd/ChangeLog ]
2003-09-30 Chris Demetriou <cgd@broadcom.com>
* archures.c (bfd_mach_mipsisa64r2): New define.
* bfd-in2.h: Regenerate.
* aoutx.h (NAME(aout,machine_type)): Handle bfd_mach_mipsisa64r2.
* cpu-mips.c (I_mipsisa64r2): New enum value.
(arch_info_struct): Add entry for I_mipsisa64r2.
* elfxx-mips.c (_bfd_elf_mips_mach)
(_bfd_mips_elf_print_private_bfd_data): Handle E_MIPS_ARCH_64R2.
(mips_set_isa_flags): Add bfd_mach_mipsisa64r2 case.
(mips_mach_extensions): Add entry for bfd_mach_mipsisa64r2.
[ binutils/ChangeLog ]
2003-09-30 Chris Demetriou <cgd@broadcom.com>
* readelf.c (get_machine_flags): Handle E_MIPS_ARCH_64R2.
[ gas/Changelog ]
2003-09-30 Chris Demetriou <cgd@broadcom.com>
* configure.in (mipsisa64r2, mipsisa64r2el, mipsisa64r2*): New CPUs.
* configure: Regenerate.
* config/tc-mips.c (imm2_expr): New variable.
(md_assemble, mips16_ip): Initialize imm2_expr.
(ISA_HAS_64BIT_REGS, ISA_HAS_DROR, ISA_HAS_ROR): Add ISA_MIPS64R2.
(macro_build): Handle +A, +B, +C, +E, +F, +G, and +H format operands.
(macro): Handle M_DEXT and M_DINS.
(validate_mips_insn): Handle +E, +F, +G, +H, and +I format operands.
(mips_ip): Likewise.
(OPTION_MIPS64R2): New define.
(md_longopts): New entry for -mips64r2 (OPTION_MIPS64R2).
OPTION_ASE_BASE): Increase to compensate for OPTION_MIPS64R2.
(md_parse_option): Handle OPTION_MIPS64R2.
(s_mipsset): Handle setting "mips64r2" ISA.
(mips_cpu_info_table): Add mips64r2.
(md_show_usage): Document -mips64r2 option.
* doc/as.texinfo: Docuemnt -mips64r2 option.
* doc/c-mips.texi: Likewise.
[ gas/testsuite/ChangeLog ]
2003-09-30 Chris Demetriou <cgd@broadcom.com>
* gas/mips/cp0-names-mips64r2.d: New file.
* gas/mips/cp0sel-names-mips64r2.d: New file.
* gas/mips/elf_arch_mips64r2.d: New file.
* gas/mips/hwr-names-mips64r2.d: New file.
* gas/mips/mips32r2-ill-fp64.l: New file.
* gas/mips/mips32r2-ill-fp64.s: New file.
* gas/mips/mips64r2-ill.l: New file.
* gas/mips/mips64r2-ill.s: New file.
* gas/mips/mips64r2.d: New file.
* gas/mips/mips64r2.s: New file.
* gas/mips/mips.exp: Define "mips64r2" arch, and run new tests.
[ include/elf/ChangeLog ]
2003-09-30 Chris Demetriou <cgd@broadcom.com>
* mips.h (E_MIPS_ARCH_64R2): New define.
[ include/opcode/ChangeLog ]
2003-09-30 Chris Demetriou <cgd@broadcom.com>
* mips.h: Document +E, +F, +G, +H, and +I operand types.
Update documentation of I, +B and +C operand types.
(INSN_ISA64R2, ISA_MIPS64R2, CPU_MIPS64R2): New defines.
(M_DEXT, M_DINS): New enum values.
[ ld/ChangeLog ]
2003-09-30 Chris Demetriou <cgd@broadcom.com>
* ldmain.c (get_emulation): Ignore "-mips64r2".
[ ld/testsuite/ChangeLog ]
2003-09-30 Chris Demetriou <cgd@broadcom.com>
* ld-mips-elf/mips-elf-flags.exp: Add tests for combinations
with MIPS64r2.
[ opcodes/ChangeLog ]
2003-09-30 Chris Demetriou <cgd@broadcom.com>
* mips-dis.c (mips_arch_choices): Add entry for "mips64r2"
(print_insn_args): Add handing for +E, +F, +G, and +H.
* mips-opc.c (I65): New define for MIPS64r2.
(mips_builtin_opcodes): Add "dext", "dextm", "dextu", "dins",
"dinsm", "dinsu", "drotl", "drotr", "drotr32", "drotrv", "dsbh",
and "dshd" for MIPS64r2. Adjust "dror", "dror32", and "drorv" to
be supported on MIPS64r2.
2003-09-30 18:17:15 +02:00
|
|
|
|
case '+':
|
|
|
|
|
switch (*fmt++)
|
|
|
|
|
{
|
|
|
|
|
case 'A':
|
|
|
|
|
case 'E':
|
|
|
|
|
insn.insn_opcode |= (va_arg (args, int)
|
|
|
|
|
& OP_MASK_SHAMT) << OP_SH_SHAMT;
|
|
|
|
|
continue;
|
|
|
|
|
|
|
|
|
|
case 'B':
|
|
|
|
|
case 'F':
|
|
|
|
|
/* Note that in the macro case, these arguments are already
|
|
|
|
|
in MSB form. (When handling the instruction in the
|
|
|
|
|
non-macro case, these arguments are sizes from which
|
|
|
|
|
MSB values must be calculated.) */
|
|
|
|
|
insn.insn_opcode |= (va_arg (args, int)
|
|
|
|
|
& OP_MASK_INSMSB) << OP_SH_INSMSB;
|
|
|
|
|
continue;
|
|
|
|
|
|
|
|
|
|
case 'C':
|
|
|
|
|
case 'G':
|
|
|
|
|
case 'H':
|
|
|
|
|
/* Note that in the macro case, these arguments are already
|
|
|
|
|
in MSBD form. (When handling the instruction in the
|
|
|
|
|
non-macro case, these arguments are sizes from which
|
|
|
|
|
MSBD values must be calculated.) */
|
|
|
|
|
insn.insn_opcode |= (va_arg (args, int)
|
|
|
|
|
& OP_MASK_EXTMSBD) << OP_SH_EXTMSBD;
|
|
|
|
|
continue;
|
|
|
|
|
|
|
|
|
|
default:
|
|
|
|
|
internalError ();
|
|
|
|
|
}
|
|
|
|
|
continue;
|
|
|
|
|
|
1999-05-03 09:29:11 +02:00
|
|
|
|
case 't':
|
|
|
|
|
case 'w':
|
|
|
|
|
case 'E':
|
2001-08-07 15:22:46 +02:00
|
|
|
|
insn.insn_opcode |= va_arg (args, int) << OP_SH_RT;
|
1999-05-03 09:29:11 +02:00
|
|
|
|
continue;
|
|
|
|
|
|
|
|
|
|
case 'c':
|
2001-08-07 15:22:46 +02:00
|
|
|
|
insn.insn_opcode |= va_arg (args, int) << OP_SH_CODE;
|
|
|
|
|
continue;
|
|
|
|
|
|
1999-05-03 09:29:11 +02:00
|
|
|
|
case 'T':
|
|
|
|
|
case 'W':
|
2001-08-07 15:22:46 +02:00
|
|
|
|
insn.insn_opcode |= va_arg (args, int) << OP_SH_FT;
|
1999-05-03 09:29:11 +02:00
|
|
|
|
continue;
|
|
|
|
|
|
|
|
|
|
case 'd':
|
|
|
|
|
case 'G':
|
[ bfd/ChangeLog ]
2002-12-30 Chris Demetriou <cgd@broadcom.com>
* aoutx.h (NAME(aout,machine_type)): Add bfd_mach_mipsisa32r2 case.
* archures.c (bfd_mach_mipsisa32r2): New define.
* bfd-in2.h: Regenerate.
* cpu-mips.c (I_mipsisa32r2): New enum value.
(arch_info_struct): Add entry for I_mipsisa32r2.
* elfxx-mips.c (elf_mips_isa, _bfd_elf_mips_mach)
(_bfd_mips_elf_print_private_bfd_data): Handle E_MIPS_ARCH_32R2.
(_bfd_mips_elf_final_write_processing): Add
bfd_mach_mipsisa32r2 case.
(_bfd_mips_elf_merge_private_bfd_data): Handle merging of
binaries marked as using MIPS32 Release 2.
[ binutils/ChangeLog ]
2002-12-30 Chris Demetriou <cgd@broadcom.com>
* doc/binutils.texi (objdump): Note MIPS HWR (Hardware Register)
changes in MIPS -M options.
[ gas/ChangeLog ]
2002-12-30 Chris Demetriou <cgd@broadcom.com>
* configure.in: Recognize mipsisa32r2, mipsisa32r2el, and
CPU variants.
* configure: Regenerate.
* config/tc-mips.c (ISA_HAS_DROR, ISA_HAS_ROR): New defines.
(macro_build): Handle "K" operand.
(macro2): Use ISA_HAS_DROR and ISA_HAS_ROR in the places where
CPU_HAS_DROR and CPU_HAS_ROR are currently used.
(mips_ip): New variable "lastpos", and implement "+A", "+B",
and "+C" operands for MIPS32 Release 2 ins/ext instructions.
Implement "K" operand for MIPS32 Release 2 rdhwr instruction.
(validate_mips_insn): Implement "+" as a way to extend the
allowed operands, and implement "K", "+A", "+B", and "+C"
operands.
(OPTION_MIPS32R2): New define.
(md_longopts): Add entry for OPTION_MIPS32R2.
(OPTION_ELF_BASE): Adjust to accomodate OPTIONS_MIPS32R2.
(md_parse_option): Handle OPTION_MIPS32R2.
(s_mipsset): Reimplement handling of ".set mipsN" options
and add support for ".set mips32r2".
(mips_cpu_info_table): Add entry for "mips32r2" (MIPS32 Release 2).
(md_show_usage): Document "-mips32r2" option.
* doc/as.texinfo: Document "-mips32r2" option.
* doc/c-mips.texi: Likewise.
[ gas/testsuite/ChangeLog ]
2002-12-30 Chris Demetriou <cgd@broadcom.com>
* gas/mips/cp0-names-mips32r2.d: New test.
* gas/mips/hwr-names-mips32r2.d: New test.
* gas/mips/hwr-names-numeric.d: New test.
* gas/mips/hwr-names.s: New test source file.
* gas/mips/mips32r2.d: New test.
* gas/mips/mips32r2.s: New test source file.
* gas/mips/mips32r2-ill.l: New test.
* gas/mips/mips32r2-ill.s: New test source file.
* gas/mips/mips.exp: Add mips32r2 architecture data array
entry. Run new tests mentioned above.
[ include/elf/ChangeLog ]
2002-12-30 Chris Demetriou <cgd@broadcom.com>
* mips.h (E_MIPS_ARCH_32R2): New define.
[ include/opcode/ChangeLog ]
2002-12-30 Chris Demetriou <cgd@broadcom.com>
* mips.h: Document "+" as the start of two-character operand
type names, and add new "K", "+A", "+B", and "+C" operand types.
(OP_MASK_INSMSB, OP_SH_INSMSB, OP_MASK_EXTMSB)
(OP_SH_EXTMSB, INSN_ISA32R2, ISA_MIPS32R2, CPU_MIPS32R2): New
defines.
[ opcodes/ChangeLog ]
2002-12-30 Chris Demetriou <cgd@broadcom.com>
* mips-dis.c (mips_cp0_names_mips3264r2, mips_hwr_names_numeric)
(mips_hwr_names_mips3264r2): New arrays.
(mips_arch_choice): New "hwr_names" member.
(mips_arch_choices): Adjust for structure change, and add a new
entry for "mips32r2" ISA.
(mips_hwr_names): New variable.
(set_default_mips_dis_options): Set mips_hwr_names.
(parse_mips_dis_option): New "hwr-names" option which sets
mips_hwr_names, and adjust "reg-names=ARCH" to set mips_hwr_names.
(print_insn_arg): Change return type to "int"
and use that to indicate number of characters consumed.
Add support for "+" operand extension character, "+A", "+B",
"+C", and "K" operands.
(print_insn_mips): Adjust for changes to print_insn_arg.
(print_mips_disassembler_options): Adjust for "hwr-names"
addition and "reg-names" change.
* mips-opc (I33): New define (shorthand for INSN_ISA32R2).
(mips_builtin_opcodes): Note that "nop" and "ssnop" are special
forms of "sll". Add new MIPS32 Release 2 instructions: ehb,
di, ei, ext, ins, jr.hb, jalr.hb, mfhc1, mfhc2, mthc1, mthc2,
rdhwr, rdpgpr, seb, seh, synci, wrpgpr, wsbh.
Note that hardware rotate instructions (ror, rorv) can be
used on MIPS32 Release 2, and add the official mnemonics
for them (rotr, rotrv) and the similar "rotl" mnemonic for
left-rotate.
2002-12-31 08:29:29 +01:00
|
|
|
|
case 'K':
|
2001-08-07 15:22:46 +02:00
|
|
|
|
insn.insn_opcode |= va_arg (args, int) << OP_SH_RD;
|
1999-05-03 09:29:11 +02:00
|
|
|
|
continue;
|
|
|
|
|
|
2000-12-01 21:05:32 +01:00
|
|
|
|
case 'U':
|
|
|
|
|
{
|
|
|
|
|
int tmp = va_arg (args, int);
|
|
|
|
|
|
2001-08-07 15:22:46 +02:00
|
|
|
|
insn.insn_opcode |= tmp << OP_SH_RT;
|
|
|
|
|
insn.insn_opcode |= tmp << OP_SH_RD;
|
2000-12-05 19:51:08 +01:00
|
|
|
|
continue;
|
2000-12-01 21:05:32 +01:00
|
|
|
|
}
|
|
|
|
|
|
1999-05-03 09:29:11 +02:00
|
|
|
|
case 'V':
|
|
|
|
|
case 'S':
|
2001-08-07 15:22:46 +02:00
|
|
|
|
insn.insn_opcode |= va_arg (args, int) << OP_SH_FS;
|
1999-05-03 09:29:11 +02:00
|
|
|
|
continue;
|
|
|
|
|
|
|
|
|
|
case 'z':
|
|
|
|
|
continue;
|
|
|
|
|
|
|
|
|
|
case '<':
|
2001-08-07 15:22:46 +02:00
|
|
|
|
insn.insn_opcode |= va_arg (args, int) << OP_SH_SHAMT;
|
1999-05-03 09:29:11 +02:00
|
|
|
|
continue;
|
|
|
|
|
|
|
|
|
|
case 'D':
|
2001-08-07 15:22:46 +02:00
|
|
|
|
insn.insn_opcode |= va_arg (args, int) << OP_SH_FD;
|
1999-05-03 09:29:11 +02:00
|
|
|
|
continue;
|
|
|
|
|
|
|
|
|
|
case 'B':
|
2001-08-07 15:22:46 +02:00
|
|
|
|
insn.insn_opcode |= va_arg (args, int) << OP_SH_CODE20;
|
1999-05-03 09:29:11 +02:00
|
|
|
|
continue;
|
|
|
|
|
|
2000-12-01 21:05:32 +01:00
|
|
|
|
case 'J':
|
2001-08-07 15:22:46 +02:00
|
|
|
|
insn.insn_opcode |= va_arg (args, int) << OP_SH_CODE19;
|
2000-12-01 21:05:32 +01:00
|
|
|
|
continue;
|
|
|
|
|
|
1999-05-03 09:29:11 +02:00
|
|
|
|
case 'q':
|
2001-08-07 15:22:46 +02:00
|
|
|
|
insn.insn_opcode |= va_arg (args, int) << OP_SH_CODE2;
|
1999-05-03 09:29:11 +02:00
|
|
|
|
continue;
|
|
|
|
|
|
|
|
|
|
case 'b':
|
|
|
|
|
case 's':
|
|
|
|
|
case 'r':
|
|
|
|
|
case 'v':
|
2001-08-07 15:22:46 +02:00
|
|
|
|
insn.insn_opcode |= va_arg (args, int) << OP_SH_RS;
|
1999-05-03 09:29:11 +02:00
|
|
|
|
continue;
|
|
|
|
|
|
|
|
|
|
case 'i':
|
|
|
|
|
case 'j':
|
|
|
|
|
case 'o':
|
2001-10-04 22:07:00 +02:00
|
|
|
|
*r = (bfd_reloc_code_real_type) va_arg (args, int);
|
2001-12-02 14:14:48 +01:00
|
|
|
|
assert (*r == BFD_RELOC_GPREL16
|
2001-10-04 22:07:00 +02:00
|
|
|
|
|| *r == BFD_RELOC_MIPS_LITERAL
|
|
|
|
|
|| *r == BFD_RELOC_MIPS_HIGHER
|
|
|
|
|
|| *r == BFD_RELOC_HI16_S
|
|
|
|
|
|| *r == BFD_RELOC_LO16
|
|
|
|
|
|| *r == BFD_RELOC_MIPS_GOT16
|
|
|
|
|
|| *r == BFD_RELOC_MIPS_CALL16
|
2002-05-31 01:32:47 +02:00
|
|
|
|
|| *r == BFD_RELOC_MIPS_GOT_DISP
|
|
|
|
|
|| *r == BFD_RELOC_MIPS_GOT_PAGE
|
|
|
|
|
|| *r == BFD_RELOC_MIPS_GOT_OFST
|
2001-10-04 22:07:00 +02:00
|
|
|
|
|| *r == BFD_RELOC_MIPS_GOT_LO16
|
|
|
|
|
|| *r == BFD_RELOC_MIPS_CALL_LO16
|
1999-05-03 09:29:11 +02:00
|
|
|
|
|| (ep->X_op == O_subtract
|
2001-10-04 22:07:00 +02:00
|
|
|
|
&& *r == BFD_RELOC_PCREL_LO16));
|
1999-05-03 09:29:11 +02:00
|
|
|
|
continue;
|
|
|
|
|
|
|
|
|
|
case 'u':
|
2001-10-04 22:07:00 +02:00
|
|
|
|
*r = (bfd_reloc_code_real_type) va_arg (args, int);
|
1999-05-03 09:29:11 +02:00
|
|
|
|
assert (ep != NULL
|
|
|
|
|
&& (ep->X_op == O_constant
|
|
|
|
|
|| (ep->X_op == O_symbol
|
2001-10-04 22:07:00 +02:00
|
|
|
|
&& (*r == BFD_RELOC_MIPS_HIGHEST
|
|
|
|
|
|| *r == BFD_RELOC_HI16_S
|
|
|
|
|
|| *r == BFD_RELOC_HI16
|
|
|
|
|
|| *r == BFD_RELOC_GPREL16
|
|
|
|
|
|| *r == BFD_RELOC_MIPS_GOT_HI16
|
|
|
|
|
|| *r == BFD_RELOC_MIPS_CALL_HI16))
|
1999-05-03 09:29:11 +02:00
|
|
|
|
|| (ep->X_op == O_subtract
|
2001-10-04 22:07:00 +02:00
|
|
|
|
&& *r == BFD_RELOC_PCREL_HI16_S)));
|
1999-05-03 09:29:11 +02:00
|
|
|
|
continue;
|
|
|
|
|
|
|
|
|
|
case 'p':
|
|
|
|
|
assert (ep != NULL);
|
|
|
|
|
/*
|
|
|
|
|
* This allows macro() to pass an immediate expression for
|
|
|
|
|
* creating short branches without creating a symbol.
|
2003-03-13 00:06:08 +01:00
|
|
|
|
* Note that the expression still might come from the assembly
|
|
|
|
|
* input, in which case the value is not checked for range nor
|
|
|
|
|
* is a relocation entry generated (yuck).
|
1999-05-03 09:29:11 +02:00
|
|
|
|
*/
|
|
|
|
|
if (ep->X_op == O_constant)
|
|
|
|
|
{
|
|
|
|
|
insn.insn_opcode |= (ep->X_add_number >> 2) & 0xffff;
|
|
|
|
|
ep = NULL;
|
|
|
|
|
}
|
|
|
|
|
else
|
2003-03-13 00:06:08 +01:00
|
|
|
|
*r = BFD_RELOC_16_PCREL_S2;
|
1999-05-03 09:29:11 +02:00
|
|
|
|
continue;
|
|
|
|
|
|
|
|
|
|
case 'a':
|
|
|
|
|
assert (ep != NULL);
|
2001-10-04 22:07:00 +02:00
|
|
|
|
*r = BFD_RELOC_MIPS_JMP;
|
1999-05-03 09:29:11 +02:00
|
|
|
|
continue;
|
|
|
|
|
|
|
|
|
|
case 'C':
|
|
|
|
|
insn.insn_opcode |= va_arg (args, unsigned long);
|
|
|
|
|
continue;
|
|
|
|
|
|
|
|
|
|
default:
|
|
|
|
|
internalError ();
|
|
|
|
|
}
|
|
|
|
|
break;
|
|
|
|
|
}
|
|
|
|
|
va_end (args);
|
2001-10-04 22:07:00 +02:00
|
|
|
|
assert (*r == BFD_RELOC_UNUSED ? ep == NULL : ep != NULL);
|
1999-05-03 09:29:11 +02:00
|
|
|
|
|
2003-02-02 20:37:20 +01:00
|
|
|
|
append_insn (place, &insn, ep, r);
|
1999-05-03 09:29:11 +02:00
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static void
|
2003-06-30 14:44:25 +02:00
|
|
|
|
mips16_macro_build (char *place, int *counter ATTRIBUTE_UNUSED,
|
|
|
|
|
expressionS *ep, const char *name, const char *fmt,
|
|
|
|
|
va_list args)
|
1999-05-03 09:29:11 +02:00
|
|
|
|
{
|
|
|
|
|
struct mips_cl_insn insn;
|
2001-10-04 22:07:00 +02:00
|
|
|
|
bfd_reloc_code_real_type r[3]
|
|
|
|
|
= {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED};
|
1999-05-03 09:29:11 +02:00
|
|
|
|
|
|
|
|
|
insn.insn_mo = (struct mips_opcode *) hash_find (mips16_op_hash, name);
|
|
|
|
|
assert (insn.insn_mo);
|
|
|
|
|
assert (strcmp (name, insn.insn_mo->name) == 0);
|
|
|
|
|
|
|
|
|
|
while (strcmp (fmt, insn.insn_mo->args) != 0
|
|
|
|
|
|| insn.insn_mo->pinfo == INSN_MACRO)
|
|
|
|
|
{
|
|
|
|
|
++insn.insn_mo;
|
|
|
|
|
assert (insn.insn_mo->name);
|
|
|
|
|
assert (strcmp (name, insn.insn_mo->name) == 0);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
insn.insn_opcode = insn.insn_mo->match;
|
2002-11-30 09:39:46 +01:00
|
|
|
|
insn.use_extend = FALSE;
|
1999-05-03 09:29:11 +02:00
|
|
|
|
|
|
|
|
|
for (;;)
|
|
|
|
|
{
|
|
|
|
|
int c;
|
|
|
|
|
|
|
|
|
|
c = *fmt++;
|
|
|
|
|
switch (c)
|
|
|
|
|
{
|
|
|
|
|
case '\0':
|
|
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
case ',':
|
|
|
|
|
case '(':
|
|
|
|
|
case ')':
|
|
|
|
|
continue;
|
|
|
|
|
|
|
|
|
|
case 'y':
|
|
|
|
|
case 'w':
|
|
|
|
|
insn.insn_opcode |= va_arg (args, int) << MIPS16OP_SH_RY;
|
|
|
|
|
continue;
|
|
|
|
|
|
|
|
|
|
case 'x':
|
|
|
|
|
case 'v':
|
|
|
|
|
insn.insn_opcode |= va_arg (args, int) << MIPS16OP_SH_RX;
|
|
|
|
|
continue;
|
|
|
|
|
|
|
|
|
|
case 'z':
|
|
|
|
|
insn.insn_opcode |= va_arg (args, int) << MIPS16OP_SH_RZ;
|
|
|
|
|
continue;
|
|
|
|
|
|
|
|
|
|
case 'Z':
|
|
|
|
|
insn.insn_opcode |= va_arg (args, int) << MIPS16OP_SH_MOVE32Z;
|
|
|
|
|
continue;
|
|
|
|
|
|
|
|
|
|
case '0':
|
|
|
|
|
case 'S':
|
|
|
|
|
case 'P':
|
|
|
|
|
case 'R':
|
|
|
|
|
continue;
|
|
|
|
|
|
|
|
|
|
case 'X':
|
|
|
|
|
insn.insn_opcode |= va_arg (args, int) << MIPS16OP_SH_REGR32;
|
|
|
|
|
continue;
|
|
|
|
|
|
|
|
|
|
case 'Y':
|
|
|
|
|
{
|
|
|
|
|
int regno;
|
|
|
|
|
|
|
|
|
|
regno = va_arg (args, int);
|
|
|
|
|
regno = ((regno & 7) << 2) | ((regno & 0x18) >> 3);
|
|
|
|
|
insn.insn_opcode |= regno << MIPS16OP_SH_REG32R;
|
|
|
|
|
}
|
|
|
|
|
continue;
|
|
|
|
|
|
|
|
|
|
case '<':
|
|
|
|
|
case '>':
|
|
|
|
|
case '4':
|
|
|
|
|
case '5':
|
|
|
|
|
case 'H':
|
|
|
|
|
case 'W':
|
|
|
|
|
case 'D':
|
|
|
|
|
case 'j':
|
|
|
|
|
case '8':
|
|
|
|
|
case 'V':
|
|
|
|
|
case 'C':
|
|
|
|
|
case 'U':
|
|
|
|
|
case 'k':
|
|
|
|
|
case 'K':
|
|
|
|
|
case 'p':
|
|
|
|
|
case 'q':
|
|
|
|
|
{
|
|
|
|
|
assert (ep != NULL);
|
|
|
|
|
|
|
|
|
|
if (ep->X_op != O_constant)
|
2002-04-04 09:43:11 +02:00
|
|
|
|
*r = (int) BFD_RELOC_UNUSED + c;
|
1999-05-03 09:29:11 +02:00
|
|
|
|
else
|
|
|
|
|
{
|
2002-11-30 09:39:46 +01:00
|
|
|
|
mips16_immed (NULL, 0, c, ep->X_add_number, FALSE, FALSE,
|
|
|
|
|
FALSE, &insn.insn_opcode, &insn.use_extend,
|
2001-11-12 23:19:30 +01:00
|
|
|
|
&insn.extend);
|
1999-05-03 09:29:11 +02:00
|
|
|
|
ep = NULL;
|
2001-10-04 22:07:00 +02:00
|
|
|
|
*r = BFD_RELOC_UNUSED;
|
1999-05-03 09:29:11 +02:00
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
continue;
|
|
|
|
|
|
|
|
|
|
case '6':
|
|
|
|
|
insn.insn_opcode |= va_arg (args, int) << MIPS16OP_SH_IMM6;
|
|
|
|
|
continue;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
break;
|
|
|
|
|
}
|
|
|
|
|
|
2001-10-04 22:07:00 +02:00
|
|
|
|
assert (*r == BFD_RELOC_UNUSED ? ep == NULL : ep != NULL);
|
1999-05-03 09:29:11 +02:00
|
|
|
|
|
2003-02-02 20:37:20 +01:00
|
|
|
|
append_insn (place, &insn, ep, r);
|
1999-05-03 09:29:11 +02:00
|
|
|
|
}
|
|
|
|
|
|
2002-05-31 01:32:47 +02:00
|
|
|
|
/*
|
|
|
|
|
* Generate a "jalr" instruction with a relocation hint to the called
|
|
|
|
|
* function. This occurs in NewABI PIC code.
|
|
|
|
|
*/
|
|
|
|
|
static void
|
2003-06-30 14:44:25 +02:00
|
|
|
|
macro_build_jalr (int icnt, expressionS *ep)
|
2002-05-31 01:32:47 +02:00
|
|
|
|
{
|
2003-06-24 13:10:47 +02:00
|
|
|
|
char *f = NULL;
|
2002-11-30 09:39:46 +01:00
|
|
|
|
|
2002-05-31 01:32:47 +02:00
|
|
|
|
if (HAVE_NEWABI)
|
2002-08-16 02:58:11 +02:00
|
|
|
|
{
|
2004-01-12 10:30:49 +01:00
|
|
|
|
frag_grow (8);
|
2002-08-16 02:58:11 +02:00
|
|
|
|
f = frag_more (0);
|
|
|
|
|
}
|
2003-06-30 14:44:25 +02:00
|
|
|
|
macro_build (NULL, &icnt, NULL, "jalr", "d,s", RA, PIC_CALL_REG);
|
2002-05-31 01:32:47 +02:00
|
|
|
|
if (HAVE_NEWABI)
|
2002-08-16 02:58:11 +02:00
|
|
|
|
fix_new_exp (frag_now, f - frag_now->fr_literal,
|
2003-05-22 11:19:33 +02:00
|
|
|
|
4, ep, FALSE, BFD_RELOC_MIPS_JALR);
|
2002-05-31 01:32:47 +02:00
|
|
|
|
}
|
|
|
|
|
|
1999-05-03 09:29:11 +02:00
|
|
|
|
/*
|
|
|
|
|
* Generate a "lui" instruction.
|
|
|
|
|
*/
|
|
|
|
|
static void
|
2003-06-30 14:44:25 +02:00
|
|
|
|
macro_build_lui (char *place, int *counter, expressionS *ep, int regnum)
|
1999-05-03 09:29:11 +02:00
|
|
|
|
{
|
|
|
|
|
expressionS high_expr;
|
|
|
|
|
struct mips_cl_insn insn;
|
2001-10-04 22:07:00 +02:00
|
|
|
|
bfd_reloc_code_real_type r[3]
|
|
|
|
|
= {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED};
|
2002-06-08 09:37:16 +02:00
|
|
|
|
const char *name = "lui";
|
|
|
|
|
const char *fmt = "t,u";
|
1999-05-03 09:29:11 +02:00
|
|
|
|
|
|
|
|
|
assert (! mips_opts.mips16);
|
|
|
|
|
|
|
|
|
|
if (place == NULL)
|
|
|
|
|
high_expr = *ep;
|
|
|
|
|
else
|
|
|
|
|
{
|
|
|
|
|
high_expr.X_op = O_constant;
|
|
|
|
|
high_expr.X_add_number = ep->X_add_number;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
if (high_expr.X_op == O_constant)
|
|
|
|
|
{
|
|
|
|
|
/* we can compute the instruction now without a relocation entry */
|
2001-08-26 12:42:12 +02:00
|
|
|
|
high_expr.X_add_number = ((high_expr.X_add_number + 0x8000)
|
|
|
|
|
>> 16) & 0xffff;
|
2001-10-04 22:07:00 +02:00
|
|
|
|
*r = BFD_RELOC_UNUSED;
|
1999-05-03 09:29:11 +02:00
|
|
|
|
}
|
2002-11-07 03:29:32 +01:00
|
|
|
|
else
|
1999-05-03 09:29:11 +02:00
|
|
|
|
{
|
|
|
|
|
assert (ep->X_op == O_symbol);
|
|
|
|
|
/* _gp_disp is a special case, used from s_cpload. */
|
|
|
|
|
assert (mips_pic == NO_PIC
|
2002-11-07 03:29:32 +01:00
|
|
|
|
|| (! HAVE_NEWABI
|
|
|
|
|
&& strcmp (S_GET_NAME (ep->X_add_symbol), "_gp_disp") == 0));
|
2001-10-04 22:07:00 +02:00
|
|
|
|
*r = BFD_RELOC_HI16_S;
|
1999-05-03 09:29:11 +02:00
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* If the macro is about to expand into a second instruction,
|
|
|
|
|
* print a warning if needed. We need to pass ip as a parameter
|
|
|
|
|
* to generate a better warning message here...
|
|
|
|
|
*/
|
|
|
|
|
if (mips_opts.warn_about_macros && place == NULL && *counter == 1)
|
|
|
|
|
as_warn (_("Macro instruction expanded into multiple instructions"));
|
|
|
|
|
|
|
|
|
|
if (place == NULL)
|
2002-05-26 20:46:37 +02:00
|
|
|
|
++*counter; /* bump instruction counter */
|
1999-05-03 09:29:11 +02:00
|
|
|
|
|
|
|
|
|
insn.insn_mo = (struct mips_opcode *) hash_find (op_hash, name);
|
|
|
|
|
assert (insn.insn_mo);
|
|
|
|
|
assert (strcmp (name, insn.insn_mo->name) == 0);
|
|
|
|
|
assert (strcmp (fmt, insn.insn_mo->args) == 0);
|
|
|
|
|
|
|
|
|
|
insn.insn_opcode = insn.insn_mo->match | (regnum << OP_SH_RT);
|
2001-10-04 22:07:00 +02:00
|
|
|
|
if (*r == BFD_RELOC_UNUSED)
|
1999-05-03 09:29:11 +02:00
|
|
|
|
{
|
|
|
|
|
insn.insn_opcode |= high_expr.X_add_number;
|
2003-02-02 20:37:20 +01:00
|
|
|
|
append_insn (place, &insn, NULL, r);
|
1999-05-03 09:29:11 +02:00
|
|
|
|
}
|
|
|
|
|
else
|
2003-02-02 20:37:20 +01:00
|
|
|
|
append_insn (place, &insn, &high_expr, r);
|
1999-05-03 09:29:11 +02:00
|
|
|
|
}
|
|
|
|
|
|
2002-09-18 23:33:07 +02:00
|
|
|
|
/* Generate a sequence of instructions to do a load or store from a constant
|
|
|
|
|
offset off of a base register (breg) into/from a target register (treg),
|
|
|
|
|
using AT if necessary. */
|
|
|
|
|
static void
|
2003-06-30 14:44:25 +02:00
|
|
|
|
macro_build_ldst_constoffset (char *place, int *counter, expressionS *ep,
|
2003-09-14 17:24:49 +02:00
|
|
|
|
const char *op, int treg, int breg, int dbl)
|
2002-09-18 23:33:07 +02:00
|
|
|
|
{
|
|
|
|
|
assert (ep->X_op == O_constant);
|
|
|
|
|
|
2003-09-14 17:24:49 +02:00
|
|
|
|
/* Sign-extending 32-bit constants makes their handling easier. */
|
2003-10-01 20:57:16 +02:00
|
|
|
|
if (! dbl && ! ((ep->X_add_number & ~((bfd_vma) 0x7fffffff))
|
|
|
|
|
== ~((bfd_vma) 0x7fffffff)))
|
2003-09-18 07:20:04 +02:00
|
|
|
|
{
|
2003-10-01 20:57:16 +02:00
|
|
|
|
if (ep->X_add_number & ~((bfd_vma) 0xffffffff))
|
2003-10-15 13:12:53 +02:00
|
|
|
|
as_bad (_("constant too large"));
|
2003-09-18 07:20:04 +02:00
|
|
|
|
|
2003-10-15 13:12:53 +02:00
|
|
|
|
ep->X_add_number = (((ep->X_add_number & 0xffffffff) ^ 0x80000000)
|
|
|
|
|
- 0x80000000);
|
2003-09-18 07:20:04 +02:00
|
|
|
|
}
|
2003-09-14 17:24:49 +02:00
|
|
|
|
|
2003-11-22 03:35:31 +01:00
|
|
|
|
/* Right now, this routine can only handle signed 32-bit constants. */
|
2003-10-01 04:07:48 +02:00
|
|
|
|
if (! IS_SEXT_32BIT_NUM(ep->X_add_number + 0x8000))
|
2002-09-18 23:33:07 +02:00
|
|
|
|
as_warn (_("operand overflow"));
|
|
|
|
|
|
|
|
|
|
if (IS_SEXT_16BIT_NUM(ep->X_add_number))
|
|
|
|
|
{
|
|
|
|
|
/* Signed 16-bit offset will fit in the op. Easy! */
|
2003-06-30 14:44:25 +02:00
|
|
|
|
macro_build (place, counter, ep, op, "t,o(b)", treg, BFD_RELOC_LO16,
|
|
|
|
|
breg);
|
2002-09-18 23:33:07 +02:00
|
|
|
|
}
|
|
|
|
|
else
|
|
|
|
|
{
|
|
|
|
|
/* 32-bit offset, need multiple instructions and AT, like:
|
|
|
|
|
lui $tempreg,const_hi (BFD_RELOC_HI16_S)
|
|
|
|
|
addu $tempreg,$tempreg,$breg
|
|
|
|
|
<op> $treg,const_lo($tempreg) (BFD_RELOC_LO16)
|
|
|
|
|
to handle the complete offset. */
|
|
|
|
|
macro_build_lui (place, counter, ep, AT);
|
|
|
|
|
if (place != NULL)
|
|
|
|
|
place += 4;
|
2003-06-30 14:44:25 +02:00
|
|
|
|
macro_build (place, counter, NULL, ADDRESS_ADD_INSN, "d,v,t", AT, AT,
|
|
|
|
|
breg);
|
2002-09-18 23:33:07 +02:00
|
|
|
|
if (place != NULL)
|
|
|
|
|
place += 4;
|
2003-06-30 14:44:25 +02:00
|
|
|
|
macro_build (place, counter, ep, op, "t,o(b)", treg, BFD_RELOC_LO16,
|
|
|
|
|
AT);
|
2002-09-18 23:33:07 +02:00
|
|
|
|
|
|
|
|
|
if (mips_opts.noat)
|
|
|
|
|
as_warn (_("Macro used $at after \".set noat\""));
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
1999-05-03 09:29:11 +02:00
|
|
|
|
/* set_at()
|
|
|
|
|
* Generates code to set the $at register to true (one)
|
|
|
|
|
* if reg is less than the immediate expression.
|
|
|
|
|
*/
|
|
|
|
|
static void
|
2003-06-30 14:44:25 +02:00
|
|
|
|
set_at (int *counter, int reg, int unsignedp)
|
1999-05-03 09:29:11 +02:00
|
|
|
|
{
|
|
|
|
|
if (imm_expr.X_op == O_constant
|
|
|
|
|
&& imm_expr.X_add_number >= -0x8000
|
|
|
|
|
&& imm_expr.X_add_number < 0x8000)
|
2003-06-30 14:44:25 +02:00
|
|
|
|
macro_build (NULL, counter, &imm_expr, unsignedp ? "sltiu" : "slti",
|
|
|
|
|
"t,r,j", AT, reg, BFD_RELOC_LO16);
|
1999-05-03 09:29:11 +02:00
|
|
|
|
else
|
|
|
|
|
{
|
2002-02-25 14:21:38 +01:00
|
|
|
|
load_register (counter, AT, &imm_expr, HAVE_64BIT_GPRS);
|
2003-06-30 14:44:25 +02:00
|
|
|
|
macro_build (NULL, counter, NULL, unsignedp ? "sltu" : "slt",
|
1999-05-03 09:29:11 +02:00
|
|
|
|
"d,v,t", AT, reg, AT);
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
2003-10-19 23:50:43 +02:00
|
|
|
|
static void
|
|
|
|
|
normalize_constant_expr (expressionS *ex)
|
|
|
|
|
{
|
|
|
|
|
if (ex->X_op == O_constant && HAVE_32BIT_GPRS)
|
|
|
|
|
ex->X_add_number = (((ex->X_add_number & 0xffffffff) ^ 0x80000000)
|
|
|
|
|
- 0x80000000);
|
|
|
|
|
}
|
|
|
|
|
|
1999-05-03 09:29:11 +02:00
|
|
|
|
/* Warn if an expression is not a constant. */
|
|
|
|
|
|
|
|
|
|
static void
|
2003-06-30 14:44:25 +02:00
|
|
|
|
check_absolute_expr (struct mips_cl_insn *ip, expressionS *ex)
|
1999-05-03 09:29:11 +02:00
|
|
|
|
{
|
|
|
|
|
if (ex->X_op == O_big)
|
|
|
|
|
as_bad (_("unsupported large constant"));
|
|
|
|
|
else if (ex->X_op != O_constant)
|
|
|
|
|
as_bad (_("Instruction %s requires absolute expression"), ip->insn_mo->name);
|
2003-10-19 23:50:43 +02:00
|
|
|
|
|
|
|
|
|
normalize_constant_expr (ex);
|
1999-05-03 09:29:11 +02:00
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/* Count the leading zeroes by performing a binary chop. This is a
|
|
|
|
|
bulky bit of source, but performance is a LOT better for the
|
|
|
|
|
majority of values than a simple loop to count the bits:
|
|
|
|
|
for (lcnt = 0; (lcnt < 32); lcnt++)
|
|
|
|
|
if ((v) & (1 << (31 - lcnt)))
|
|
|
|
|
break;
|
|
|
|
|
However it is not code size friendly, and the gain will drop a bit
|
|
|
|
|
on certain cached systems.
|
|
|
|
|
*/
|
|
|
|
|
#define COUNT_TOP_ZEROES(v) \
|
|
|
|
|
(((v) & ~0xffff) == 0 \
|
|
|
|
|
? ((v) & ~0xff) == 0 \
|
|
|
|
|
? ((v) & ~0xf) == 0 \
|
|
|
|
|
? ((v) & ~0x3) == 0 \
|
|
|
|
|
? ((v) & ~0x1) == 0 \
|
|
|
|
|
? !(v) \
|
|
|
|
|
? 32 \
|
|
|
|
|
: 31 \
|
|
|
|
|
: 30 \
|
|
|
|
|
: ((v) & ~0x7) == 0 \
|
|
|
|
|
? 29 \
|
|
|
|
|
: 28 \
|
|
|
|
|
: ((v) & ~0x3f) == 0 \
|
|
|
|
|
? ((v) & ~0x1f) == 0 \
|
|
|
|
|
? 27 \
|
|
|
|
|
: 26 \
|
|
|
|
|
: ((v) & ~0x7f) == 0 \
|
|
|
|
|
? 25 \
|
|
|
|
|
: 24 \
|
|
|
|
|
: ((v) & ~0xfff) == 0 \
|
|
|
|
|
? ((v) & ~0x3ff) == 0 \
|
|
|
|
|
? ((v) & ~0x1ff) == 0 \
|
|
|
|
|
? 23 \
|
|
|
|
|
: 22 \
|
|
|
|
|
: ((v) & ~0x7ff) == 0 \
|
|
|
|
|
? 21 \
|
|
|
|
|
: 20 \
|
|
|
|
|
: ((v) & ~0x3fff) == 0 \
|
|
|
|
|
? ((v) & ~0x1fff) == 0 \
|
|
|
|
|
? 19 \
|
|
|
|
|
: 18 \
|
|
|
|
|
: ((v) & ~0x7fff) == 0 \
|
|
|
|
|
? 17 \
|
|
|
|
|
: 16 \
|
|
|
|
|
: ((v) & ~0xffffff) == 0 \
|
|
|
|
|
? ((v) & ~0xfffff) == 0 \
|
|
|
|
|
? ((v) & ~0x3ffff) == 0 \
|
|
|
|
|
? ((v) & ~0x1ffff) == 0 \
|
|
|
|
|
? 15 \
|
|
|
|
|
: 14 \
|
|
|
|
|
: ((v) & ~0x7ffff) == 0 \
|
|
|
|
|
? 13 \
|
|
|
|
|
: 12 \
|
|
|
|
|
: ((v) & ~0x3fffff) == 0 \
|
|
|
|
|
? ((v) & ~0x1fffff) == 0 \
|
|
|
|
|
? 11 \
|
|
|
|
|
: 10 \
|
|
|
|
|
: ((v) & ~0x7fffff) == 0 \
|
|
|
|
|
? 9 \
|
|
|
|
|
: 8 \
|
|
|
|
|
: ((v) & ~0xfffffff) == 0 \
|
|
|
|
|
? ((v) & ~0x3ffffff) == 0 \
|
|
|
|
|
? ((v) & ~0x1ffffff) == 0 \
|
|
|
|
|
? 7 \
|
|
|
|
|
: 6 \
|
|
|
|
|
: ((v) & ~0x7ffffff) == 0 \
|
|
|
|
|
? 5 \
|
|
|
|
|
: 4 \
|
|
|
|
|
: ((v) & ~0x3fffffff) == 0 \
|
|
|
|
|
? ((v) & ~0x1fffffff) == 0 \
|
|
|
|
|
? 3 \
|
|
|
|
|
: 2 \
|
|
|
|
|
: ((v) & ~0x7fffffff) == 0 \
|
|
|
|
|
? 1 \
|
|
|
|
|
: 0)
|
|
|
|
|
|
|
|
|
|
/* load_register()
|
2003-11-22 03:35:31 +01:00
|
|
|
|
* This routine generates the least number of instructions necessary to load
|
1999-05-03 09:29:11 +02:00
|
|
|
|
* an absolute expression value into a register.
|
|
|
|
|
*/
|
|
|
|
|
static void
|
2003-06-30 14:44:25 +02:00
|
|
|
|
load_register (int *counter, int reg, expressionS *ep, int dbl)
|
1999-05-03 09:29:11 +02:00
|
|
|
|
{
|
|
|
|
|
int freg;
|
|
|
|
|
expressionS hi32, lo32;
|
|
|
|
|
|
|
|
|
|
if (ep->X_op != O_big)
|
|
|
|
|
{
|
|
|
|
|
assert (ep->X_op == O_constant);
|
2003-09-14 17:24:49 +02:00
|
|
|
|
|
|
|
|
|
/* Sign-extending 32-bit constants makes their handling easier. */
|
2003-10-01 20:57:16 +02:00
|
|
|
|
if (! dbl && ! ((ep->X_add_number & ~((bfd_vma) 0x7fffffff))
|
|
|
|
|
== ~((bfd_vma) 0x7fffffff)))
|
2003-09-18 07:20:04 +02:00
|
|
|
|
{
|
2003-10-01 20:57:16 +02:00
|
|
|
|
if (ep->X_add_number & ~((bfd_vma) 0xffffffff))
|
2003-10-15 13:12:53 +02:00
|
|
|
|
as_bad (_("constant too large"));
|
2003-09-18 07:20:04 +02:00
|
|
|
|
|
2003-10-15 13:12:53 +02:00
|
|
|
|
ep->X_add_number = (((ep->X_add_number & 0xffffffff) ^ 0x80000000)
|
|
|
|
|
- 0x80000000);
|
2003-09-18 07:20:04 +02:00
|
|
|
|
}
|
2003-09-14 17:24:49 +02:00
|
|
|
|
|
|
|
|
|
if (IS_SEXT_16BIT_NUM (ep->X_add_number))
|
1999-05-03 09:29:11 +02:00
|
|
|
|
{
|
|
|
|
|
/* We can handle 16 bit signed values with an addiu to
|
|
|
|
|
$zero. No need to ever use daddiu here, since $zero and
|
|
|
|
|
the result are always correct in 32 bit mode. */
|
2003-06-30 14:44:25 +02:00
|
|
|
|
macro_build (NULL, counter, ep, "addiu", "t,r,j", reg, 0,
|
|
|
|
|
BFD_RELOC_LO16);
|
1999-05-03 09:29:11 +02:00
|
|
|
|
return;
|
|
|
|
|
}
|
|
|
|
|
else if (ep->X_add_number >= 0 && ep->X_add_number < 0x10000)
|
|
|
|
|
{
|
|
|
|
|
/* We can handle 16 bit unsigned values with an ori to
|
|
|
|
|
$zero. */
|
2003-06-30 14:44:25 +02:00
|
|
|
|
macro_build (NULL, counter, ep, "ori", "t,r,i", reg, 0,
|
|
|
|
|
BFD_RELOC_LO16);
|
1999-05-03 09:29:11 +02:00
|
|
|
|
return;
|
|
|
|
|
}
|
2003-09-14 17:24:49 +02:00
|
|
|
|
else if ((IS_SEXT_32BIT_NUM (ep->X_add_number)))
|
1999-05-03 09:29:11 +02:00
|
|
|
|
{
|
|
|
|
|
/* 32 bit values require an lui. */
|
2003-06-30 14:44:25 +02:00
|
|
|
|
macro_build (NULL, counter, ep, "lui", "t,u", reg, BFD_RELOC_HI16);
|
1999-05-03 09:29:11 +02:00
|
|
|
|
if ((ep->X_add_number & 0xffff) != 0)
|
2003-06-30 14:44:25 +02:00
|
|
|
|
macro_build (NULL, counter, ep, "ori", "t,r,i", reg, reg,
|
|
|
|
|
BFD_RELOC_LO16);
|
1999-05-03 09:29:11 +02:00
|
|
|
|
return;
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/* The value is larger than 32 bits. */
|
|
|
|
|
|
2001-08-02 12:15:24 +02:00
|
|
|
|
if (HAVE_32BIT_GPRS)
|
1999-05-03 09:29:11 +02:00
|
|
|
|
{
|
2001-12-04 15:38:48 +01:00
|
|
|
|
as_bad (_("Number (0x%lx) larger than 32 bits"),
|
|
|
|
|
(unsigned long) ep->X_add_number);
|
2003-06-30 14:44:25 +02:00
|
|
|
|
macro_build (NULL, counter, ep, "addiu", "t,r,j", reg, 0,
|
|
|
|
|
BFD_RELOC_LO16);
|
1999-05-03 09:29:11 +02:00
|
|
|
|
return;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
if (ep->X_op != O_big)
|
|
|
|
|
{
|
|
|
|
|
hi32 = *ep;
|
|
|
|
|
hi32.X_add_number = (valueT) hi32.X_add_number >> 16;
|
|
|
|
|
hi32.X_add_number = (valueT) hi32.X_add_number >> 16;
|
|
|
|
|
hi32.X_add_number &= 0xffffffff;
|
|
|
|
|
lo32 = *ep;
|
|
|
|
|
lo32.X_add_number &= 0xffffffff;
|
|
|
|
|
}
|
|
|
|
|
else
|
|
|
|
|
{
|
|
|
|
|
assert (ep->X_add_number > 2);
|
|
|
|
|
if (ep->X_add_number == 3)
|
|
|
|
|
generic_bignum[3] = 0;
|
|
|
|
|
else if (ep->X_add_number > 4)
|
|
|
|
|
as_bad (_("Number larger than 64 bits"));
|
|
|
|
|
lo32.X_op = O_constant;
|
|
|
|
|
lo32.X_add_number = generic_bignum[0] + (generic_bignum[1] << 16);
|
|
|
|
|
hi32.X_op = O_constant;
|
|
|
|
|
hi32.X_add_number = generic_bignum[2] + (generic_bignum[3] << 16);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
if (hi32.X_add_number == 0)
|
|
|
|
|
freg = 0;
|
|
|
|
|
else
|
|
|
|
|
{
|
|
|
|
|
int shift, bit;
|
|
|
|
|
unsigned long hi, lo;
|
|
|
|
|
|
2001-12-04 15:38:48 +01:00
|
|
|
|
if (hi32.X_add_number == (offsetT) 0xffffffff)
|
2000-12-05 19:51:08 +01:00
|
|
|
|
{
|
|
|
|
|
if ((lo32.X_add_number & 0xffff8000) == 0xffff8000)
|
|
|
|
|
{
|
2003-06-30 14:44:25 +02:00
|
|
|
|
macro_build (NULL, counter, &lo32, "addiu", "t,r,j", reg, 0,
|
|
|
|
|
BFD_RELOC_LO16);
|
2000-12-05 19:51:08 +01:00
|
|
|
|
return;
|
|
|
|
|
}
|
|
|
|
|
if (lo32.X_add_number & 0x80000000)
|
|
|
|
|
{
|
2003-06-30 14:44:25 +02:00
|
|
|
|
macro_build (NULL, counter, &lo32, "lui", "t,u", reg,
|
|
|
|
|
BFD_RELOC_HI16);
|
1999-05-03 09:29:11 +02:00
|
|
|
|
if (lo32.X_add_number & 0xffff)
|
2003-06-30 14:44:25 +02:00
|
|
|
|
macro_build (NULL, counter, &lo32, "ori", "t,r,i", reg, reg,
|
|
|
|
|
BFD_RELOC_LO16);
|
2000-12-05 19:51:08 +01:00
|
|
|
|
return;
|
|
|
|
|
}
|
|
|
|
|
}
|
1999-05-03 09:29:11 +02:00
|
|
|
|
|
|
|
|
|
/* Check for 16bit shifted constant. We know that hi32 is
|
|
|
|
|
non-zero, so start the mask on the first bit of the hi32
|
|
|
|
|
value. */
|
|
|
|
|
shift = 17;
|
|
|
|
|
do
|
2000-12-05 19:51:08 +01:00
|
|
|
|
{
|
|
|
|
|
unsigned long himask, lomask;
|
|
|
|
|
|
|
|
|
|
if (shift < 32)
|
|
|
|
|
{
|
|
|
|
|
himask = 0xffff >> (32 - shift);
|
|
|
|
|
lomask = (0xffff << shift) & 0xffffffff;
|
|
|
|
|
}
|
|
|
|
|
else
|
|
|
|
|
{
|
|
|
|
|
himask = 0xffff << (shift - 32);
|
|
|
|
|
lomask = 0;
|
|
|
|
|
}
|
|
|
|
|
if ((hi32.X_add_number & ~(offsetT) himask) == 0
|
|
|
|
|
&& (lo32.X_add_number & ~(offsetT) lomask) == 0)
|
|
|
|
|
{
|
|
|
|
|
expressionS tmp;
|
|
|
|
|
|
|
|
|
|
tmp.X_op = O_constant;
|
|
|
|
|
if (shift < 32)
|
|
|
|
|
tmp.X_add_number = ((hi32.X_add_number << (32 - shift))
|
|
|
|
|
| (lo32.X_add_number >> shift));
|
|
|
|
|
else
|
|
|
|
|
tmp.X_add_number = hi32.X_add_number >> (shift - 32);
|
2003-06-30 14:44:25 +02:00
|
|
|
|
macro_build (NULL, counter, &tmp, "ori", "t,r,i", reg, 0,
|
|
|
|
|
BFD_RELOC_LO16);
|
|
|
|
|
macro_build (NULL, counter, NULL,
|
2000-12-05 19:51:08 +01:00
|
|
|
|
(shift >= 32) ? "dsll32" : "dsll",
|
|
|
|
|
"d,w,<", reg, reg,
|
|
|
|
|
(shift >= 32) ? shift - 32 : shift);
|
|
|
|
|
return;
|
|
|
|
|
}
|
2002-05-26 20:46:37 +02:00
|
|
|
|
++shift;
|
2000-12-05 19:51:08 +01:00
|
|
|
|
}
|
|
|
|
|
while (shift <= (64 - 16));
|
1999-05-03 09:29:11 +02:00
|
|
|
|
|
|
|
|
|
/* Find the bit number of the lowest one bit, and store the
|
|
|
|
|
shifted value in hi/lo. */
|
|
|
|
|
hi = (unsigned long) (hi32.X_add_number & 0xffffffff);
|
|
|
|
|
lo = (unsigned long) (lo32.X_add_number & 0xffffffff);
|
|
|
|
|
if (lo != 0)
|
|
|
|
|
{
|
|
|
|
|
bit = 0;
|
|
|
|
|
while ((lo & 1) == 0)
|
|
|
|
|
{
|
|
|
|
|
lo >>= 1;
|
|
|
|
|
++bit;
|
|
|
|
|
}
|
|
|
|
|
lo |= (hi & (((unsigned long) 1 << bit) - 1)) << (32 - bit);
|
|
|
|
|
hi >>= bit;
|
|
|
|
|
}
|
|
|
|
|
else
|
|
|
|
|
{
|
|
|
|
|
bit = 32;
|
|
|
|
|
while ((hi & 1) == 0)
|
|
|
|
|
{
|
|
|
|
|
hi >>= 1;
|
|
|
|
|
++bit;
|
|
|
|
|
}
|
|
|
|
|
lo = hi;
|
|
|
|
|
hi = 0;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/* Optimize if the shifted value is a (power of 2) - 1. */
|
|
|
|
|
if ((hi == 0 && ((lo + 1) & lo) == 0)
|
|
|
|
|
|| (lo == 0xffffffff && ((hi + 1) & hi) == 0))
|
2000-12-05 19:51:08 +01:00
|
|
|
|
{
|
|
|
|
|
shift = COUNT_TOP_ZEROES ((unsigned int) hi32.X_add_number);
|
1999-05-03 09:29:11 +02:00
|
|
|
|
if (shift != 0)
|
2000-12-05 19:51:08 +01:00
|
|
|
|
{
|
1999-05-03 09:29:11 +02:00
|
|
|
|
expressionS tmp;
|
|
|
|
|
|
|
|
|
|
/* This instruction will set the register to be all
|
|
|
|
|
ones. */
|
2000-12-05 19:51:08 +01:00
|
|
|
|
tmp.X_op = O_constant;
|
|
|
|
|
tmp.X_add_number = (offsetT) -1;
|
2003-06-30 14:44:25 +02:00
|
|
|
|
macro_build (NULL, counter, &tmp, "addiu", "t,r,j", reg, 0,
|
|
|
|
|
BFD_RELOC_LO16);
|
2000-12-05 19:51:08 +01:00
|
|
|
|
if (bit != 0)
|
|
|
|
|
{
|
|
|
|
|
bit += shift;
|
2003-06-30 14:44:25 +02:00
|
|
|
|
macro_build (NULL, counter, NULL,
|
2000-12-05 19:51:08 +01:00
|
|
|
|
(bit >= 32) ? "dsll32" : "dsll",
|
|
|
|
|
"d,w,<", reg, reg,
|
|
|
|
|
(bit >= 32) ? bit - 32 : bit);
|
|
|
|
|
}
|
2003-06-30 14:44:25 +02:00
|
|
|
|
macro_build (NULL, counter, NULL,
|
1999-05-03 09:29:11 +02:00
|
|
|
|
(shift >= 32) ? "dsrl32" : "dsrl",
|
2000-12-05 19:51:08 +01:00
|
|
|
|
"d,w,<", reg, reg,
|
1999-05-03 09:29:11 +02:00
|
|
|
|
(shift >= 32) ? shift - 32 : shift);
|
2000-12-05 19:51:08 +01:00
|
|
|
|
return;
|
|
|
|
|
}
|
|
|
|
|
}
|
1999-05-03 09:29:11 +02:00
|
|
|
|
|
|
|
|
|
/* Sign extend hi32 before calling load_register, because we can
|
|
|
|
|
generally get better code when we load a sign extended value. */
|
|
|
|
|
if ((hi32.X_add_number & 0x80000000) != 0)
|
2000-12-05 19:51:08 +01:00
|
|
|
|
hi32.X_add_number |= ~(offsetT) 0xffffffff;
|
1999-05-03 09:29:11 +02:00
|
|
|
|
load_register (counter, reg, &hi32, 0);
|
|
|
|
|
freg = reg;
|
|
|
|
|
}
|
|
|
|
|
if ((lo32.X_add_number & 0xffff0000) == 0)
|
|
|
|
|
{
|
|
|
|
|
if (freg != 0)
|
|
|
|
|
{
|
2003-06-30 14:44:25 +02:00
|
|
|
|
macro_build (NULL, counter, NULL, "dsll32", "d,w,<", reg, freg, 0);
|
1999-05-03 09:29:11 +02:00
|
|
|
|
freg = reg;
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
else
|
|
|
|
|
{
|
|
|
|
|
expressionS mid16;
|
|
|
|
|
|
2001-12-04 15:38:48 +01:00
|
|
|
|
if ((freg == 0) && (lo32.X_add_number == (offsetT) 0xffffffff))
|
2000-12-05 19:51:08 +01:00
|
|
|
|
{
|
2003-06-30 14:44:25 +02:00
|
|
|
|
macro_build (NULL, counter, &lo32, "lui", "t,u", reg,
|
|
|
|
|
BFD_RELOC_HI16);
|
|
|
|
|
macro_build (NULL, counter, NULL, "dsrl32", "d,w,<", reg, reg, 0);
|
2000-12-05 19:51:08 +01:00
|
|
|
|
return;
|
|
|
|
|
}
|
1999-05-03 09:29:11 +02:00
|
|
|
|
|
|
|
|
|
if (freg != 0)
|
|
|
|
|
{
|
2003-06-30 14:44:25 +02:00
|
|
|
|
macro_build (NULL, counter, NULL, "dsll", "d,w,<", reg, freg, 16);
|
1999-05-03 09:29:11 +02:00
|
|
|
|
freg = reg;
|
|
|
|
|
}
|
|
|
|
|
mid16 = lo32;
|
|
|
|
|
mid16.X_add_number >>= 16;
|
2003-06-30 14:44:25 +02:00
|
|
|
|
macro_build (NULL, counter, &mid16, "ori", "t,r,i", reg, freg,
|
|
|
|
|
BFD_RELOC_LO16);
|
|
|
|
|
macro_build (NULL, counter, NULL, "dsll", "d,w,<", reg, reg, 16);
|
1999-05-03 09:29:11 +02:00
|
|
|
|
freg = reg;
|
|
|
|
|
}
|
|
|
|
|
if ((lo32.X_add_number & 0xffff) != 0)
|
2003-06-30 14:44:25 +02:00
|
|
|
|
macro_build (NULL, counter, &lo32, "ori", "t,r,i", reg, freg,
|
|
|
|
|
BFD_RELOC_LO16);
|
1999-05-03 09:29:11 +02:00
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/* Load an address into a register. */
|
|
|
|
|
|
|
|
|
|
static void
|
2003-06-30 14:44:25 +02:00
|
|
|
|
load_address (int *counter, int reg, expressionS *ep, int *used_at)
|
1999-05-03 09:29:11 +02:00
|
|
|
|
{
|
2002-05-26 20:46:37 +02:00
|
|
|
|
char *p = NULL;
|
1999-05-03 09:29:11 +02:00
|
|
|
|
|
|
|
|
|
if (ep->X_op != O_constant
|
|
|
|
|
&& ep->X_op != O_symbol)
|
|
|
|
|
{
|
|
|
|
|
as_bad (_("expression too complex"));
|
|
|
|
|
ep->X_op = O_constant;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
if (ep->X_op == O_constant)
|
|
|
|
|
{
|
2002-05-28 21:23:09 +02:00
|
|
|
|
load_register (counter, reg, ep, HAVE_64BIT_ADDRESSES);
|
1999-05-03 09:29:11 +02:00
|
|
|
|
return;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
if (mips_pic == NO_PIC)
|
|
|
|
|
{
|
|
|
|
|
/* If this is a reference to a GP relative symbol, we want
|
2001-12-02 14:14:48 +01:00
|
|
|
|
addiu $reg,$gp,<sym> (BFD_RELOC_GPREL16)
|
1999-05-03 09:29:11 +02:00
|
|
|
|
Otherwise we want
|
|
|
|
|
lui $reg,<sym> (BFD_RELOC_HI16_S)
|
|
|
|
|
addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
|
2001-10-10 02:43:36 +02:00
|
|
|
|
If we have an addend, we always use the latter form.
|
2001-11-06 22:39:09 +01:00
|
|
|
|
|
2001-10-10 02:43:36 +02:00
|
|
|
|
With 64bit address space and a usable $at we want
|
|
|
|
|
lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST)
|
|
|
|
|
lui $at,<sym> (BFD_RELOC_HI16_S)
|
|
|
|
|
daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER)
|
|
|
|
|
daddiu $at,<sym> (BFD_RELOC_LO16)
|
|
|
|
|
dsll32 $reg,0
|
2002-07-09 00:42:09 +02:00
|
|
|
|
daddu $reg,$reg,$at
|
2001-11-06 22:39:09 +01:00
|
|
|
|
|
2002-12-17 02:13:56 +01:00
|
|
|
|
If $at is already in use, we use a path which is suboptimal
|
2001-10-10 02:43:36 +02:00
|
|
|
|
on superscalar processors.
|
|
|
|
|
lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST)
|
|
|
|
|
daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER)
|
|
|
|
|
dsll $reg,16
|
|
|
|
|
daddiu $reg,<sym> (BFD_RELOC_HI16_S)
|
|
|
|
|
dsll $reg,16
|
|
|
|
|
daddiu $reg,<sym> (BFD_RELOC_LO16)
|
|
|
|
|
*/
|
2002-05-28 21:23:09 +02:00
|
|
|
|
if (HAVE_64BIT_ADDRESSES)
|
2001-10-10 02:43:36 +02:00
|
|
|
|
{
|
|
|
|
|
/* We don't do GP optimization for now because RELAX_ENCODE can't
|
|
|
|
|
hold the data for such large chunks. */
|
|
|
|
|
|
2002-07-30 21:27:31 +02:00
|
|
|
|
if (*used_at == 0 && ! mips_opts.noat)
|
2001-10-10 02:43:36 +02:00
|
|
|
|
{
|
|
|
|
|
macro_build (p, counter, ep, "lui", "t,u",
|
2003-06-30 14:44:25 +02:00
|
|
|
|
reg, BFD_RELOC_MIPS_HIGHEST);
|
2001-10-10 02:43:36 +02:00
|
|
|
|
macro_build (p, counter, ep, "lui", "t,u",
|
2003-06-30 14:44:25 +02:00
|
|
|
|
AT, BFD_RELOC_HI16_S);
|
2001-10-10 02:43:36 +02:00
|
|
|
|
macro_build (p, counter, ep, "daddiu", "t,r,j",
|
2003-06-30 14:44:25 +02:00
|
|
|
|
reg, reg, BFD_RELOC_MIPS_HIGHER);
|
2001-10-10 02:43:36 +02:00
|
|
|
|
macro_build (p, counter, ep, "daddiu", "t,r,j",
|
2003-06-30 14:44:25 +02:00
|
|
|
|
AT, AT, BFD_RELOC_LO16);
|
|
|
|
|
macro_build (p, counter, NULL, "dsll32", "d,w,<", reg, reg, 0);
|
|
|
|
|
macro_build (p, counter, NULL, "daddu", "d,v,t", reg, reg, AT);
|
2001-10-10 02:43:36 +02:00
|
|
|
|
*used_at = 1;
|
|
|
|
|
}
|
|
|
|
|
else
|
|
|
|
|
{
|
|
|
|
|
macro_build (p, counter, ep, "lui", "t,u",
|
2003-06-30 14:44:25 +02:00
|
|
|
|
reg, BFD_RELOC_MIPS_HIGHEST);
|
2001-10-10 02:43:36 +02:00
|
|
|
|
macro_build (p, counter, ep, "daddiu", "t,r,j",
|
2003-06-30 14:44:25 +02:00
|
|
|
|
reg, reg, BFD_RELOC_MIPS_HIGHER);
|
|
|
|
|
macro_build (p, counter, NULL, "dsll", "d,w,<", reg, reg, 16);
|
2001-10-10 02:43:36 +02:00
|
|
|
|
macro_build (p, counter, ep, "daddiu", "t,r,j",
|
2003-06-30 14:44:25 +02:00
|
|
|
|
reg, reg, BFD_RELOC_HI16_S);
|
|
|
|
|
macro_build (p, counter, NULL, "dsll", "d,w,<", reg, reg, 16);
|
2001-10-10 02:43:36 +02:00
|
|
|
|
macro_build (p, counter, ep, "daddiu", "t,r,j",
|
2003-06-30 14:44:25 +02:00
|
|
|
|
reg, reg, BFD_RELOC_LO16);
|
2001-10-10 02:43:36 +02:00
|
|
|
|
}
|
|
|
|
|
}
|
1999-05-03 09:29:11 +02:00
|
|
|
|
else
|
|
|
|
|
{
|
2001-10-10 02:43:36 +02:00
|
|
|
|
if ((valueT) ep->X_add_number <= MAX_GPREL_OFFSET
|
|
|
|
|
&& ! nopic_need_relax (ep->X_add_symbol, 1))
|
|
|
|
|
{
|
|
|
|
|
frag_grow (20);
|
2003-06-30 14:44:25 +02:00
|
|
|
|
macro_build (NULL, counter, ep, ADDRESS_ADDI_INSN, "t,r,j", reg,
|
|
|
|
|
mips_gp_register, BFD_RELOC_GPREL16);
|
2001-10-10 02:43:36 +02:00
|
|
|
|
p = frag_var (rs_machine_dependent, 8, 0,
|
|
|
|
|
RELAX_ENCODE (4, 8, 0, 4, 0,
|
|
|
|
|
mips_opts.warn_about_macros),
|
2001-12-04 15:38:48 +01:00
|
|
|
|
ep->X_add_symbol, 0, NULL);
|
2001-10-10 02:43:36 +02:00
|
|
|
|
}
|
|
|
|
|
macro_build_lui (p, counter, ep, reg);
|
|
|
|
|
if (p != NULL)
|
|
|
|
|
p += 4;
|
2003-06-30 14:44:25 +02:00
|
|
|
|
macro_build (p, counter, ep, ADDRESS_ADDI_INSN, "t,r,j", reg, reg,
|
|
|
|
|
BFD_RELOC_LO16);
|
2001-10-10 02:43:36 +02:00
|
|
|
|
}
|
1999-05-03 09:29:11 +02:00
|
|
|
|
}
|
|
|
|
|
else if (mips_pic == SVR4_PIC && ! mips_big_got)
|
|
|
|
|
{
|
|
|
|
|
expressionS ex;
|
|
|
|
|
|
|
|
|
|
/* If this is a reference to an external symbol, we want
|
|
|
|
|
lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
|
|
|
|
|
Otherwise we want
|
|
|
|
|
lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
|
|
|
|
|
nop
|
|
|
|
|
addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
|
* config/tc-mips.h (tc_frag_data_type, TC_FRAG_TYPE): New.
* config/tc-mips.c: Use signed add for n32 address arithmetic.
(append_insn): When filling delay slots with instructions
that have fixups that tc_gen_reloc might consider modifyable
in variant frags, start a new frag.
(load_address): Generate GOT_DISP with of without offset
depending on whether symbol is local. For -xgot, use
GOT_PAGE/GOT_OFST or GOT_HI16/GOT_LO16.
(macro) <M_DLA_AB, M_LA_AB>: Likewise.
<M_JAL_A>: In NewABI, use CALL16 or GOT_DISP for small got,
CALL_HI16/CALL_LO16 or GOT_PAGE/GOT_OFST for big got.
<ld_st>: In NewABI with small got, always use
GOT_PAGE/GOT_OFST, with the latter in the load/store
instruction. With big got, use GOT_HI16/GOT_LO16 or
GOT_PAGE/GOT_OFST.
(tc_gen_reloc): Adjust variant frags with GOT_DISP in NewABI.
Add tc_frag_data.tc_fr_offset to addends. Decay CALL16,
GOT_OFST and GOT_DISP to GOT_DISP in NewABI.
(md_convert_frag): Use memmove for safe copying of overlapping
regions.
2003-04-11 03:56:50 +02:00
|
|
|
|
If there is a constant, it must be added in after.
|
|
|
|
|
|
2002-09-18 04:25:19 +02:00
|
|
|
|
If we have NewABI, we want
|
* config/tc-mips.h (tc_frag_data_type, TC_FRAG_TYPE): New.
* config/tc-mips.c: Use signed add for n32 address arithmetic.
(append_insn): When filling delay slots with instructions
that have fixups that tc_gen_reloc might consider modifyable
in variant frags, start a new frag.
(load_address): Generate GOT_DISP with of without offset
depending on whether symbol is local. For -xgot, use
GOT_PAGE/GOT_OFST or GOT_HI16/GOT_LO16.
(macro) <M_DLA_AB, M_LA_AB>: Likewise.
<M_JAL_A>: In NewABI, use CALL16 or GOT_DISP for small got,
CALL_HI16/CALL_LO16 or GOT_PAGE/GOT_OFST for big got.
<ld_st>: In NewABI with small got, always use
GOT_PAGE/GOT_OFST, with the latter in the load/store
instruction. With big got, use GOT_HI16/GOT_LO16 or
GOT_PAGE/GOT_OFST.
(tc_gen_reloc): Adjust variant frags with GOT_DISP in NewABI.
Add tc_frag_data.tc_fr_offset to addends. Decay CALL16,
GOT_OFST and GOT_DISP to GOT_DISP in NewABI.
(md_convert_frag): Use memmove for safe copying of overlapping
regions.
2003-04-11 03:56:50 +02:00
|
|
|
|
lw $reg,<sym+cst>($gp) (BFD_RELOC_MIPS_GOT_DISP)
|
|
|
|
|
unless we're referencing a global symbol with a non-zero
|
|
|
|
|
offset, in which case cst must be added separately. */
|
2002-09-18 04:25:19 +02:00
|
|
|
|
if (HAVE_NEWABI)
|
|
|
|
|
{
|
* config/tc-mips.h (tc_frag_data_type, TC_FRAG_TYPE): New.
* config/tc-mips.c: Use signed add for n32 address arithmetic.
(append_insn): When filling delay slots with instructions
that have fixups that tc_gen_reloc might consider modifyable
in variant frags, start a new frag.
(load_address): Generate GOT_DISP with of without offset
depending on whether symbol is local. For -xgot, use
GOT_PAGE/GOT_OFST or GOT_HI16/GOT_LO16.
(macro) <M_DLA_AB, M_LA_AB>: Likewise.
<M_JAL_A>: In NewABI, use CALL16 or GOT_DISP for small got,
CALL_HI16/CALL_LO16 or GOT_PAGE/GOT_OFST for big got.
<ld_st>: In NewABI with small got, always use
GOT_PAGE/GOT_OFST, with the latter in the load/store
instruction. With big got, use GOT_HI16/GOT_LO16 or
GOT_PAGE/GOT_OFST.
(tc_gen_reloc): Adjust variant frags with GOT_DISP in NewABI.
Add tc_frag_data.tc_fr_offset to addends. Decay CALL16,
GOT_OFST and GOT_DISP to GOT_DISP in NewABI.
(md_convert_frag): Use memmove for safe copying of overlapping
regions.
2003-04-11 03:56:50 +02:00
|
|
|
|
frag_grow (12);
|
2003-04-25 06:40:09 +02:00
|
|
|
|
|
* config/tc-mips.h (tc_frag_data_type, TC_FRAG_TYPE): New.
* config/tc-mips.c: Use signed add for n32 address arithmetic.
(append_insn): When filling delay slots with instructions
that have fixups that tc_gen_reloc might consider modifyable
in variant frags, start a new frag.
(load_address): Generate GOT_DISP with of without offset
depending on whether symbol is local. For -xgot, use
GOT_PAGE/GOT_OFST or GOT_HI16/GOT_LO16.
(macro) <M_DLA_AB, M_LA_AB>: Likewise.
<M_JAL_A>: In NewABI, use CALL16 or GOT_DISP for small got,
CALL_HI16/CALL_LO16 or GOT_PAGE/GOT_OFST for big got.
<ld_st>: In NewABI with small got, always use
GOT_PAGE/GOT_OFST, with the latter in the load/store
instruction. With big got, use GOT_HI16/GOT_LO16 or
GOT_PAGE/GOT_OFST.
(tc_gen_reloc): Adjust variant frags with GOT_DISP in NewABI.
Add tc_frag_data.tc_fr_offset to addends. Decay CALL16,
GOT_OFST and GOT_DISP to GOT_DISP in NewABI.
(md_convert_frag): Use memmove for safe copying of overlapping
regions.
2003-04-11 03:56:50 +02:00
|
|
|
|
if (ep->X_add_number)
|
|
|
|
|
{
|
|
|
|
|
frag_now->tc_frag_data.tc_fr_offset =
|
|
|
|
|
ex.X_add_number = ep->X_add_number;
|
|
|
|
|
ep->X_add_number = 0;
|
2003-06-30 14:44:25 +02:00
|
|
|
|
macro_build (NULL, counter, ep, ADDRESS_LOAD_INSN, "t,o(b)",
|
|
|
|
|
reg, BFD_RELOC_MIPS_GOT_DISP, mips_gp_register);
|
* config/tc-mips.h (tc_frag_data_type, TC_FRAG_TYPE): New.
* config/tc-mips.c: Use signed add for n32 address arithmetic.
(append_insn): When filling delay slots with instructions
that have fixups that tc_gen_reloc might consider modifyable
in variant frags, start a new frag.
(load_address): Generate GOT_DISP with of without offset
depending on whether symbol is local. For -xgot, use
GOT_PAGE/GOT_OFST or GOT_HI16/GOT_LO16.
(macro) <M_DLA_AB, M_LA_AB>: Likewise.
<M_JAL_A>: In NewABI, use CALL16 or GOT_DISP for small got,
CALL_HI16/CALL_LO16 or GOT_PAGE/GOT_OFST for big got.
<ld_st>: In NewABI with small got, always use
GOT_PAGE/GOT_OFST, with the latter in the load/store
instruction. With big got, use GOT_HI16/GOT_LO16 or
GOT_PAGE/GOT_OFST.
(tc_gen_reloc): Adjust variant frags with GOT_DISP in NewABI.
Add tc_frag_data.tc_fr_offset to addends. Decay CALL16,
GOT_OFST and GOT_DISP to GOT_DISP in NewABI.
(md_convert_frag): Use memmove for safe copying of overlapping
regions.
2003-04-11 03:56:50 +02:00
|
|
|
|
if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000)
|
|
|
|
|
as_bad (_("PIC code offset overflow (max 16 signed bits)"));
|
|
|
|
|
ex.X_op = O_constant;
|
2003-06-30 14:44:25 +02:00
|
|
|
|
macro_build (NULL, counter, &ex, ADDRESS_ADDI_INSN, "t,r,j",
|
|
|
|
|
reg, reg, BFD_RELOC_LO16);
|
* config/tc-mips.h (tc_frag_data_type, TC_FRAG_TYPE): New.
* config/tc-mips.c: Use signed add for n32 address arithmetic.
(append_insn): When filling delay slots with instructions
that have fixups that tc_gen_reloc might consider modifyable
in variant frags, start a new frag.
(load_address): Generate GOT_DISP with of without offset
depending on whether symbol is local. For -xgot, use
GOT_PAGE/GOT_OFST or GOT_HI16/GOT_LO16.
(macro) <M_DLA_AB, M_LA_AB>: Likewise.
<M_JAL_A>: In NewABI, use CALL16 or GOT_DISP for small got,
CALL_HI16/CALL_LO16 or GOT_PAGE/GOT_OFST for big got.
<ld_st>: In NewABI with small got, always use
GOT_PAGE/GOT_OFST, with the latter in the load/store
instruction. With big got, use GOT_HI16/GOT_LO16 or
GOT_PAGE/GOT_OFST.
(tc_gen_reloc): Adjust variant frags with GOT_DISP in NewABI.
Add tc_frag_data.tc_fr_offset to addends. Decay CALL16,
GOT_OFST and GOT_DISP to GOT_DISP in NewABI.
(md_convert_frag): Use memmove for safe copying of overlapping
regions.
2003-04-11 03:56:50 +02:00
|
|
|
|
p = frag_var (rs_machine_dependent, 8, 0,
|
|
|
|
|
RELAX_ENCODE (8, 4, 0, 0, 0,
|
|
|
|
|
mips_opts.warn_about_macros),
|
2003-06-30 14:44:25 +02:00
|
|
|
|
ep->X_add_symbol, 0, NULL);
|
* config/tc-mips.h (tc_frag_data_type, TC_FRAG_TYPE): New.
* config/tc-mips.c: Use signed add for n32 address arithmetic.
(append_insn): When filling delay slots with instructions
that have fixups that tc_gen_reloc might consider modifyable
in variant frags, start a new frag.
(load_address): Generate GOT_DISP with of without offset
depending on whether symbol is local. For -xgot, use
GOT_PAGE/GOT_OFST or GOT_HI16/GOT_LO16.
(macro) <M_DLA_AB, M_LA_AB>: Likewise.
<M_JAL_A>: In NewABI, use CALL16 or GOT_DISP for small got,
CALL_HI16/CALL_LO16 or GOT_PAGE/GOT_OFST for big got.
<ld_st>: In NewABI with small got, always use
GOT_PAGE/GOT_OFST, with the latter in the load/store
instruction. With big got, use GOT_HI16/GOT_LO16 or
GOT_PAGE/GOT_OFST.
(tc_gen_reloc): Adjust variant frags with GOT_DISP in NewABI.
Add tc_frag_data.tc_fr_offset to addends. Decay CALL16,
GOT_OFST and GOT_DISP to GOT_DISP in NewABI.
(md_convert_frag): Use memmove for safe copying of overlapping
regions.
2003-04-11 03:56:50 +02:00
|
|
|
|
ep->X_add_number = ex.X_add_number;
|
|
|
|
|
}
|
|
|
|
|
|
2003-06-16 14:13:10 +02:00
|
|
|
|
macro_build (p, counter, ep, ADDRESS_LOAD_INSN, "t,o(b)", reg,
|
2003-06-30 14:44:25 +02:00
|
|
|
|
BFD_RELOC_MIPS_GOT_DISP, mips_gp_register);
|
* config/tc-mips.h (tc_frag_data_type, TC_FRAG_TYPE): New.
* config/tc-mips.c: Use signed add for n32 address arithmetic.
(append_insn): When filling delay slots with instructions
that have fixups that tc_gen_reloc might consider modifyable
in variant frags, start a new frag.
(load_address): Generate GOT_DISP with of without offset
depending on whether symbol is local. For -xgot, use
GOT_PAGE/GOT_OFST or GOT_HI16/GOT_LO16.
(macro) <M_DLA_AB, M_LA_AB>: Likewise.
<M_JAL_A>: In NewABI, use CALL16 or GOT_DISP for small got,
CALL_HI16/CALL_LO16 or GOT_PAGE/GOT_OFST for big got.
<ld_st>: In NewABI with small got, always use
GOT_PAGE/GOT_OFST, with the latter in the load/store
instruction. With big got, use GOT_HI16/GOT_LO16 or
GOT_PAGE/GOT_OFST.
(tc_gen_reloc): Adjust variant frags with GOT_DISP in NewABI.
Add tc_frag_data.tc_fr_offset to addends. Decay CALL16,
GOT_OFST and GOT_DISP to GOT_DISP in NewABI.
(md_convert_frag): Use memmove for safe copying of overlapping
regions.
2003-04-11 03:56:50 +02:00
|
|
|
|
|
|
|
|
|
if (! p)
|
|
|
|
|
{
|
|
|
|
|
/* To avoid confusion in tc_gen_reloc, we must ensure
|
|
|
|
|
that this does not become a variant frag. */
|
|
|
|
|
frag_wane (frag_now);
|
|
|
|
|
frag_new (0);
|
|
|
|
|
}
|
2002-09-18 04:25:19 +02:00
|
|
|
|
}
|
|
|
|
|
else
|
|
|
|
|
{
|
* config/tc-mips.h (tc_frag_data_type, TC_FRAG_TYPE): New.
* config/tc-mips.c: Use signed add for n32 address arithmetic.
(append_insn): When filling delay slots with instructions
that have fixups that tc_gen_reloc might consider modifyable
in variant frags, start a new frag.
(load_address): Generate GOT_DISP with of without offset
depending on whether symbol is local. For -xgot, use
GOT_PAGE/GOT_OFST or GOT_HI16/GOT_LO16.
(macro) <M_DLA_AB, M_LA_AB>: Likewise.
<M_JAL_A>: In NewABI, use CALL16 or GOT_DISP for small got,
CALL_HI16/CALL_LO16 or GOT_PAGE/GOT_OFST for big got.
<ld_st>: In NewABI with small got, always use
GOT_PAGE/GOT_OFST, with the latter in the load/store
instruction. With big got, use GOT_HI16/GOT_LO16 or
GOT_PAGE/GOT_OFST.
(tc_gen_reloc): Adjust variant frags with GOT_DISP in NewABI.
Add tc_frag_data.tc_fr_offset to addends. Decay CALL16,
GOT_OFST and GOT_DISP to GOT_DISP in NewABI.
(md_convert_frag): Use memmove for safe copying of overlapping
regions.
2003-04-11 03:56:50 +02:00
|
|
|
|
ex.X_add_number = ep->X_add_number;
|
|
|
|
|
ep->X_add_number = 0;
|
|
|
|
|
frag_grow (20);
|
2003-06-30 14:44:25 +02:00
|
|
|
|
macro_build (NULL, counter, ep, ADDRESS_LOAD_INSN, "t,o(b)", reg,
|
|
|
|
|
BFD_RELOC_MIPS_GOT16,
|
2003-06-16 14:13:10 +02:00
|
|
|
|
mips_gp_register);
|
2003-06-30 14:44:25 +02:00
|
|
|
|
macro_build (NULL, counter, NULL, "nop", "");
|
2002-09-18 04:25:19 +02:00
|
|
|
|
p = frag_var (rs_machine_dependent, 4, 0,
|
|
|
|
|
RELAX_ENCODE (0, 4, -8, 0, 0, mips_opts.warn_about_macros),
|
2003-06-30 14:44:25 +02:00
|
|
|
|
ep->X_add_symbol, 0, NULL);
|
|
|
|
|
macro_build (p, counter, ep, ADDRESS_ADDI_INSN, "t,r,j", reg, reg,
|
|
|
|
|
BFD_RELOC_LO16);
|
2002-09-18 04:25:19 +02:00
|
|
|
|
|
* config/tc-mips.h (tc_frag_data_type, TC_FRAG_TYPE): New.
* config/tc-mips.c: Use signed add for n32 address arithmetic.
(append_insn): When filling delay slots with instructions
that have fixups that tc_gen_reloc might consider modifyable
in variant frags, start a new frag.
(load_address): Generate GOT_DISP with of without offset
depending on whether symbol is local. For -xgot, use
GOT_PAGE/GOT_OFST or GOT_HI16/GOT_LO16.
(macro) <M_DLA_AB, M_LA_AB>: Likewise.
<M_JAL_A>: In NewABI, use CALL16 or GOT_DISP for small got,
CALL_HI16/CALL_LO16 or GOT_PAGE/GOT_OFST for big got.
<ld_st>: In NewABI with small got, always use
GOT_PAGE/GOT_OFST, with the latter in the load/store
instruction. With big got, use GOT_HI16/GOT_LO16 or
GOT_PAGE/GOT_OFST.
(tc_gen_reloc): Adjust variant frags with GOT_DISP in NewABI.
Add tc_frag_data.tc_fr_offset to addends. Decay CALL16,
GOT_OFST and GOT_DISP to GOT_DISP in NewABI.
(md_convert_frag): Use memmove for safe copying of overlapping
regions.
2003-04-11 03:56:50 +02:00
|
|
|
|
if (ex.X_add_number != 0)
|
|
|
|
|
{
|
|
|
|
|
if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000)
|
|
|
|
|
as_bad (_("PIC code offset overflow (max 16 signed bits)"));
|
|
|
|
|
ex.X_op = O_constant;
|
2003-06-30 14:44:25 +02:00
|
|
|
|
macro_build (NULL, counter, &ex, ADDRESS_ADDI_INSN, "t,r,j",
|
|
|
|
|
reg, reg, BFD_RELOC_LO16);
|
* config/tc-mips.h (tc_frag_data_type, TC_FRAG_TYPE): New.
* config/tc-mips.c: Use signed add for n32 address arithmetic.
(append_insn): When filling delay slots with instructions
that have fixups that tc_gen_reloc might consider modifyable
in variant frags, start a new frag.
(load_address): Generate GOT_DISP with of without offset
depending on whether symbol is local. For -xgot, use
GOT_PAGE/GOT_OFST or GOT_HI16/GOT_LO16.
(macro) <M_DLA_AB, M_LA_AB>: Likewise.
<M_JAL_A>: In NewABI, use CALL16 or GOT_DISP for small got,
CALL_HI16/CALL_LO16 or GOT_PAGE/GOT_OFST for big got.
<ld_st>: In NewABI with small got, always use
GOT_PAGE/GOT_OFST, with the latter in the load/store
instruction. With big got, use GOT_HI16/GOT_LO16 or
GOT_PAGE/GOT_OFST.
(tc_gen_reloc): Adjust variant frags with GOT_DISP in NewABI.
Add tc_frag_data.tc_fr_offset to addends. Decay CALL16,
GOT_OFST and GOT_DISP to GOT_DISP in NewABI.
(md_convert_frag): Use memmove for safe copying of overlapping
regions.
2003-04-11 03:56:50 +02:00
|
|
|
|
}
|
1999-05-03 09:29:11 +02:00
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
else if (mips_pic == SVR4_PIC)
|
|
|
|
|
{
|
|
|
|
|
expressionS ex;
|
|
|
|
|
int off;
|
|
|
|
|
|
|
|
|
|
/* This is the large GOT case. If this is a reference to an
|
|
|
|
|
external symbol, we want
|
|
|
|
|
lui $reg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
|
|
|
|
|
addu $reg,$reg,$gp
|
|
|
|
|
lw $reg,<sym>($reg) (BFD_RELOC_MIPS_GOT_LO16)
|
* config/tc-mips.h (tc_frag_data_type, TC_FRAG_TYPE): New.
* config/tc-mips.c: Use signed add for n32 address arithmetic.
(append_insn): When filling delay slots with instructions
that have fixups that tc_gen_reloc might consider modifyable
in variant frags, start a new frag.
(load_address): Generate GOT_DISP with of without offset
depending on whether symbol is local. For -xgot, use
GOT_PAGE/GOT_OFST or GOT_HI16/GOT_LO16.
(macro) <M_DLA_AB, M_LA_AB>: Likewise.
<M_JAL_A>: In NewABI, use CALL16 or GOT_DISP for small got,
CALL_HI16/CALL_LO16 or GOT_PAGE/GOT_OFST for big got.
<ld_st>: In NewABI with small got, always use
GOT_PAGE/GOT_OFST, with the latter in the load/store
instruction. With big got, use GOT_HI16/GOT_LO16 or
GOT_PAGE/GOT_OFST.
(tc_gen_reloc): Adjust variant frags with GOT_DISP in NewABI.
Add tc_frag_data.tc_fr_offset to addends. Decay CALL16,
GOT_OFST and GOT_DISP to GOT_DISP in NewABI.
(md_convert_frag): Use memmove for safe copying of overlapping
regions.
2003-04-11 03:56:50 +02:00
|
|
|
|
|
|
|
|
|
Otherwise, for a reference to a local symbol in old ABI, we want
|
1999-05-03 09:29:11 +02:00
|
|
|
|
lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
|
|
|
|
|
nop
|
|
|
|
|
addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
|
2003-04-25 06:40:09 +02:00
|
|
|
|
If there is a constant, it must be added in after.
|
* config/tc-mips.h (tc_frag_data_type, TC_FRAG_TYPE): New.
* config/tc-mips.c: Use signed add for n32 address arithmetic.
(append_insn): When filling delay slots with instructions
that have fixups that tc_gen_reloc might consider modifyable
in variant frags, start a new frag.
(load_address): Generate GOT_DISP with of without offset
depending on whether symbol is local. For -xgot, use
GOT_PAGE/GOT_OFST or GOT_HI16/GOT_LO16.
(macro) <M_DLA_AB, M_LA_AB>: Likewise.
<M_JAL_A>: In NewABI, use CALL16 or GOT_DISP for small got,
CALL_HI16/CALL_LO16 or GOT_PAGE/GOT_OFST for big got.
<ld_st>: In NewABI with small got, always use
GOT_PAGE/GOT_OFST, with the latter in the load/store
instruction. With big got, use GOT_HI16/GOT_LO16 or
GOT_PAGE/GOT_OFST.
(tc_gen_reloc): Adjust variant frags with GOT_DISP in NewABI.
Add tc_frag_data.tc_fr_offset to addends. Decay CALL16,
GOT_OFST and GOT_DISP to GOT_DISP in NewABI.
(md_convert_frag): Use memmove for safe copying of overlapping
regions.
2003-04-11 03:56:50 +02:00
|
|
|
|
|
|
|
|
|
In the NewABI, for local symbols, with or without offsets, we want:
|
2002-05-31 01:32:47 +02:00
|
|
|
|
lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
|
|
|
|
|
addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST)
|
* config/tc-mips.h (tc_frag_data_type, TC_FRAG_TYPE): New.
* config/tc-mips.c: Use signed add for n32 address arithmetic.
(append_insn): When filling delay slots with instructions
that have fixups that tc_gen_reloc might consider modifyable
in variant frags, start a new frag.
(load_address): Generate GOT_DISP with of without offset
depending on whether symbol is local. For -xgot, use
GOT_PAGE/GOT_OFST or GOT_HI16/GOT_LO16.
(macro) <M_DLA_AB, M_LA_AB>: Likewise.
<M_JAL_A>: In NewABI, use CALL16 or GOT_DISP for small got,
CALL_HI16/CALL_LO16 or GOT_PAGE/GOT_OFST for big got.
<ld_st>: In NewABI with small got, always use
GOT_PAGE/GOT_OFST, with the latter in the load/store
instruction. With big got, use GOT_HI16/GOT_LO16 or
GOT_PAGE/GOT_OFST.
(tc_gen_reloc): Adjust variant frags with GOT_DISP in NewABI.
Add tc_frag_data.tc_fr_offset to addends. Decay CALL16,
GOT_OFST and GOT_DISP to GOT_DISP in NewABI.
(md_convert_frag): Use memmove for safe copying of overlapping
regions.
2003-04-11 03:56:50 +02:00
|
|
|
|
*/
|
2002-05-31 01:32:47 +02:00
|
|
|
|
if (HAVE_NEWABI)
|
|
|
|
|
{
|
* config/tc-mips.h (tc_frag_data_type, TC_FRAG_TYPE): New.
* config/tc-mips.c: Use signed add for n32 address arithmetic.
(append_insn): When filling delay slots with instructions
that have fixups that tc_gen_reloc might consider modifyable
in variant frags, start a new frag.
(load_address): Generate GOT_DISP with of without offset
depending on whether symbol is local. For -xgot, use
GOT_PAGE/GOT_OFST or GOT_HI16/GOT_LO16.
(macro) <M_DLA_AB, M_LA_AB>: Likewise.
<M_JAL_A>: In NewABI, use CALL16 or GOT_DISP for small got,
CALL_HI16/CALL_LO16 or GOT_PAGE/GOT_OFST for big got.
<ld_st>: In NewABI with small got, always use
GOT_PAGE/GOT_OFST, with the latter in the load/store
instruction. With big got, use GOT_HI16/GOT_LO16 or
GOT_PAGE/GOT_OFST.
(tc_gen_reloc): Adjust variant frags with GOT_DISP in NewABI.
Add tc_frag_data.tc_fr_offset to addends. Decay CALL16,
GOT_OFST and GOT_DISP to GOT_DISP in NewABI.
(md_convert_frag): Use memmove for safe copying of overlapping
regions.
2003-04-11 03:56:50 +02:00
|
|
|
|
frag_grow (24);
|
|
|
|
|
|
|
|
|
|
frag_now->tc_frag_data.tc_fr_offset =
|
|
|
|
|
ex.X_add_number = ep->X_add_number;
|
|
|
|
|
ep->X_add_number = 0;
|
2003-06-30 14:44:25 +02:00
|
|
|
|
macro_build (NULL, counter, ep, "lui", "t,u", reg,
|
|
|
|
|
BFD_RELOC_MIPS_GOT_HI16);
|
|
|
|
|
macro_build (NULL, counter, NULL, ADDRESS_ADD_INSN, "d,v,t", reg,
|
|
|
|
|
reg, mips_gp_register);
|
|
|
|
|
macro_build (NULL, counter, ep, ADDRESS_LOAD_INSN, "t,o(b)", reg,
|
|
|
|
|
BFD_RELOC_MIPS_GOT_LO16, reg);
|
* config/tc-mips.h (tc_frag_data_type, TC_FRAG_TYPE): New.
* config/tc-mips.c: Use signed add for n32 address arithmetic.
(append_insn): When filling delay slots with instructions
that have fixups that tc_gen_reloc might consider modifyable
in variant frags, start a new frag.
(load_address): Generate GOT_DISP with of without offset
depending on whether symbol is local. For -xgot, use
GOT_PAGE/GOT_OFST or GOT_HI16/GOT_LO16.
(macro) <M_DLA_AB, M_LA_AB>: Likewise.
<M_JAL_A>: In NewABI, use CALL16 or GOT_DISP for small got,
CALL_HI16/CALL_LO16 or GOT_PAGE/GOT_OFST for big got.
<ld_st>: In NewABI with small got, always use
GOT_PAGE/GOT_OFST, with the latter in the load/store
instruction. With big got, use GOT_HI16/GOT_LO16 or
GOT_PAGE/GOT_OFST.
(tc_gen_reloc): Adjust variant frags with GOT_DISP in NewABI.
Add tc_frag_data.tc_fr_offset to addends. Decay CALL16,
GOT_OFST and GOT_DISP to GOT_DISP in NewABI.
(md_convert_frag): Use memmove for safe copying of overlapping
regions.
2003-04-11 03:56:50 +02:00
|
|
|
|
if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000)
|
|
|
|
|
as_bad (_("PIC code offset overflow (max 16 signed bits)"));
|
|
|
|
|
else if (ex.X_add_number)
|
|
|
|
|
{
|
|
|
|
|
ex.X_op = O_constant;
|
2003-06-30 14:44:25 +02:00
|
|
|
|
macro_build (NULL, counter, &ex, ADDRESS_ADDI_INSN, "t,r,j",
|
|
|
|
|
reg, reg, BFD_RELOC_LO16);
|
* config/tc-mips.h (tc_frag_data_type, TC_FRAG_TYPE): New.
* config/tc-mips.c: Use signed add for n32 address arithmetic.
(append_insn): When filling delay slots with instructions
that have fixups that tc_gen_reloc might consider modifyable
in variant frags, start a new frag.
(load_address): Generate GOT_DISP with of without offset
depending on whether symbol is local. For -xgot, use
GOT_PAGE/GOT_OFST or GOT_HI16/GOT_LO16.
(macro) <M_DLA_AB, M_LA_AB>: Likewise.
<M_JAL_A>: In NewABI, use CALL16 or GOT_DISP for small got,
CALL_HI16/CALL_LO16 or GOT_PAGE/GOT_OFST for big got.
<ld_st>: In NewABI with small got, always use
GOT_PAGE/GOT_OFST, with the latter in the load/store
instruction. With big got, use GOT_HI16/GOT_LO16 or
GOT_PAGE/GOT_OFST.
(tc_gen_reloc): Adjust variant frags with GOT_DISP in NewABI.
Add tc_frag_data.tc_fr_offset to addends. Decay CALL16,
GOT_OFST and GOT_DISP to GOT_DISP in NewABI.
(md_convert_frag): Use memmove for safe copying of overlapping
regions.
2003-04-11 03:56:50 +02:00
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
ep->X_add_number = ex.X_add_number;
|
|
|
|
|
p = frag_var (rs_machine_dependent, 8, 0,
|
|
|
|
|
RELAX_ENCODE (ex.X_add_number ? 16 : 12, 8, 0, 4, 0,
|
|
|
|
|
mips_opts.warn_about_macros),
|
2003-06-30 14:44:25 +02:00
|
|
|
|
ep->X_add_symbol, 0, NULL);
|
2003-06-16 14:13:10 +02:00
|
|
|
|
macro_build (p, counter, ep, ADDRESS_LOAD_INSN, "t,o(b)", reg,
|
2003-06-30 14:44:25 +02:00
|
|
|
|
BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register);
|
|
|
|
|
macro_build (p + 4, counter, ep, ADDRESS_ADDI_INSN, "t,r,j", reg,
|
|
|
|
|
reg, BFD_RELOC_MIPS_GOT_OFST);
|
2002-05-31 01:32:47 +02:00
|
|
|
|
}
|
1999-05-03 09:29:11 +02:00
|
|
|
|
else
|
2002-05-31 01:32:47 +02:00
|
|
|
|
{
|
* config/tc-mips.h (tc_frag_data_type, TC_FRAG_TYPE): New.
* config/tc-mips.c: Use signed add for n32 address arithmetic.
(append_insn): When filling delay slots with instructions
that have fixups that tc_gen_reloc might consider modifyable
in variant frags, start a new frag.
(load_address): Generate GOT_DISP with of without offset
depending on whether symbol is local. For -xgot, use
GOT_PAGE/GOT_OFST or GOT_HI16/GOT_LO16.
(macro) <M_DLA_AB, M_LA_AB>: Likewise.
<M_JAL_A>: In NewABI, use CALL16 or GOT_DISP for small got,
CALL_HI16/CALL_LO16 or GOT_PAGE/GOT_OFST for big got.
<ld_st>: In NewABI with small got, always use
GOT_PAGE/GOT_OFST, with the latter in the load/store
instruction. With big got, use GOT_HI16/GOT_LO16 or
GOT_PAGE/GOT_OFST.
(tc_gen_reloc): Adjust variant frags with GOT_DISP in NewABI.
Add tc_frag_data.tc_fr_offset to addends. Decay CALL16,
GOT_OFST and GOT_DISP to GOT_DISP in NewABI.
(md_convert_frag): Use memmove for safe copying of overlapping
regions.
2003-04-11 03:56:50 +02:00
|
|
|
|
ex.X_add_number = ep->X_add_number;
|
|
|
|
|
ep->X_add_number = 0;
|
2002-05-31 01:32:47 +02:00
|
|
|
|
if (reg_needs_delay (mips_gp_register))
|
|
|
|
|
off = 4;
|
|
|
|
|
else
|
|
|
|
|
off = 0;
|
|
|
|
|
frag_grow (32);
|
2003-06-30 14:44:25 +02:00
|
|
|
|
macro_build (NULL, counter, ep, "lui", "t,u", reg,
|
|
|
|
|
BFD_RELOC_MIPS_GOT_HI16);
|
|
|
|
|
macro_build (NULL, counter, NULL, ADDRESS_ADD_INSN, "d,v,t", reg,
|
|
|
|
|
reg, mips_gp_register);
|
|
|
|
|
macro_build (NULL, counter, ep, ADDRESS_LOAD_INSN, "t,o(b)", reg,
|
|
|
|
|
BFD_RELOC_MIPS_GOT_LO16, reg);
|
2002-05-31 01:32:47 +02:00
|
|
|
|
p = frag_var (rs_machine_dependent, 12 + off, 0,
|
|
|
|
|
RELAX_ENCODE (12, 12 + off, off, 8 + off, 0,
|
|
|
|
|
mips_opts.warn_about_macros),
|
|
|
|
|
ep->X_add_symbol, 0, NULL);
|
|
|
|
|
if (off > 0)
|
|
|
|
|
{
|
|
|
|
|
/* We need a nop before loading from $gp. This special
|
|
|
|
|
check is required because the lui which starts the main
|
|
|
|
|
instruction stream does not refer to $gp, and so will not
|
|
|
|
|
insert the nop which may be required. */
|
2003-06-30 14:44:25 +02:00
|
|
|
|
macro_build (p, counter, NULL, "nop", "");
|
2002-05-31 01:32:47 +02:00
|
|
|
|
p += 4;
|
|
|
|
|
}
|
2003-06-16 14:13:10 +02:00
|
|
|
|
macro_build (p, counter, ep, ADDRESS_LOAD_INSN, "t,o(b)", reg,
|
2003-06-30 14:44:25 +02:00
|
|
|
|
BFD_RELOC_MIPS_GOT16, mips_gp_register);
|
2002-05-31 01:32:47 +02:00
|
|
|
|
p += 4;
|
2003-06-30 14:44:25 +02:00
|
|
|
|
macro_build (p, counter, NULL, "nop", "");
|
1999-05-03 09:29:11 +02:00
|
|
|
|
p += 4;
|
2003-06-30 14:44:25 +02:00
|
|
|
|
macro_build (p, counter, ep, ADDRESS_ADDI_INSN, "t,r,j", reg, reg,
|
|
|
|
|
BFD_RELOC_LO16);
|
2002-05-31 01:32:47 +02:00
|
|
|
|
|
* config/tc-mips.h (tc_frag_data_type, TC_FRAG_TYPE): New.
* config/tc-mips.c: Use signed add for n32 address arithmetic.
(append_insn): When filling delay slots with instructions
that have fixups that tc_gen_reloc might consider modifyable
in variant frags, start a new frag.
(load_address): Generate GOT_DISP with of without offset
depending on whether symbol is local. For -xgot, use
GOT_PAGE/GOT_OFST or GOT_HI16/GOT_LO16.
(macro) <M_DLA_AB, M_LA_AB>: Likewise.
<M_JAL_A>: In NewABI, use CALL16 or GOT_DISP for small got,
CALL_HI16/CALL_LO16 or GOT_PAGE/GOT_OFST for big got.
<ld_st>: In NewABI with small got, always use
GOT_PAGE/GOT_OFST, with the latter in the load/store
instruction. With big got, use GOT_HI16/GOT_LO16 or
GOT_PAGE/GOT_OFST.
(tc_gen_reloc): Adjust variant frags with GOT_DISP in NewABI.
Add tc_frag_data.tc_fr_offset to addends. Decay CALL16,
GOT_OFST and GOT_DISP to GOT_DISP in NewABI.
(md_convert_frag): Use memmove for safe copying of overlapping
regions.
2003-04-11 03:56:50 +02:00
|
|
|
|
if (ex.X_add_number != 0)
|
|
|
|
|
{
|
|
|
|
|
if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000)
|
|
|
|
|
as_bad (_("PIC code offset overflow (max 16 signed bits)"));
|
|
|
|
|
ex.X_op = O_constant;
|
2003-06-30 14:44:25 +02:00
|
|
|
|
macro_build (NULL, counter, &ex, ADDRESS_ADDI_INSN, "t,r,j",
|
|
|
|
|
reg, reg, BFD_RELOC_LO16);
|
* config/tc-mips.h (tc_frag_data_type, TC_FRAG_TYPE): New.
* config/tc-mips.c: Use signed add for n32 address arithmetic.
(append_insn): When filling delay slots with instructions
that have fixups that tc_gen_reloc might consider modifyable
in variant frags, start a new frag.
(load_address): Generate GOT_DISP with of without offset
depending on whether symbol is local. For -xgot, use
GOT_PAGE/GOT_OFST or GOT_HI16/GOT_LO16.
(macro) <M_DLA_AB, M_LA_AB>: Likewise.
<M_JAL_A>: In NewABI, use CALL16 or GOT_DISP for small got,
CALL_HI16/CALL_LO16 or GOT_PAGE/GOT_OFST for big got.
<ld_st>: In NewABI with small got, always use
GOT_PAGE/GOT_OFST, with the latter in the load/store
instruction. With big got, use GOT_HI16/GOT_LO16 or
GOT_PAGE/GOT_OFST.
(tc_gen_reloc): Adjust variant frags with GOT_DISP in NewABI.
Add tc_frag_data.tc_fr_offset to addends. Decay CALL16,
GOT_OFST and GOT_DISP to GOT_DISP in NewABI.
(md_convert_frag): Use memmove for safe copying of overlapping
regions.
2003-04-11 03:56:50 +02:00
|
|
|
|
}
|
1999-05-03 09:29:11 +02:00
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
else if (mips_pic == EMBEDDED_PIC)
|
|
|
|
|
{
|
|
|
|
|
/* We always do
|
2001-12-02 14:14:48 +01:00
|
|
|
|
addiu $reg,$gp,<sym> (BFD_RELOC_GPREL16)
|
2002-05-28 21:23:09 +02:00
|
|
|
|
*/
|
2003-06-30 14:44:25 +02:00
|
|
|
|
macro_build (NULL, counter, ep, ADDRESS_ADDI_INSN, "t,r,j", reg,
|
|
|
|
|
mips_gp_register, BFD_RELOC_GPREL16);
|
1999-05-03 09:29:11 +02:00
|
|
|
|
}
|
|
|
|
|
else
|
|
|
|
|
abort ();
|
|
|
|
|
}
|
|
|
|
|
|
2001-08-10 18:24:32 +02:00
|
|
|
|
/* Move the contents of register SOURCE into register DEST. */
|
|
|
|
|
|
|
|
|
|
static void
|
2003-06-30 14:44:25 +02:00
|
|
|
|
move_register (int *counter, int dest, int source)
|
2001-08-10 18:24:32 +02:00
|
|
|
|
{
|
2003-06-30 14:44:25 +02:00
|
|
|
|
macro_build (NULL, counter, NULL, HAVE_32BIT_GPRS ? "addu" : "daddu",
|
2001-08-10 18:24:32 +02:00
|
|
|
|
"d,v,t", dest, source, 0);
|
|
|
|
|
}
|
|
|
|
|
|
1999-05-03 09:29:11 +02:00
|
|
|
|
/*
|
|
|
|
|
* Build macros
|
|
|
|
|
* This routine implements the seemingly endless macro or synthesized
|
|
|
|
|
* instructions and addressing modes in the mips assembly language. Many
|
|
|
|
|
* of these macros are simple and are similar to each other. These could
|
2003-11-22 03:35:31 +01:00
|
|
|
|
* probably be handled by some kind of table or grammar approach instead of
|
1999-05-03 09:29:11 +02:00
|
|
|
|
* this verbose method. Others are not simple macros but are more like
|
|
|
|
|
* optimizing code generation.
|
|
|
|
|
* One interesting optimization is when several store macros appear
|
2003-11-22 03:35:31 +01:00
|
|
|
|
* consecutively that would load AT with the upper half of the same address.
|
1999-05-03 09:29:11 +02:00
|
|
|
|
* The ensuing load upper instructions are ommited. This implies some kind
|
|
|
|
|
* of global optimization. We currently only optimize within a single macro.
|
|
|
|
|
* For many of the load and store macros if the address is specified as a
|
|
|
|
|
* constant expression in the first 64k of memory (ie ld $2,0x4000c) we
|
|
|
|
|
* first load register 'at' with zero and use it as the base register. The
|
|
|
|
|
* mips assembler simply uses register $zero. Just one tiny optimization
|
|
|
|
|
* we're missing.
|
|
|
|
|
*/
|
|
|
|
|
static void
|
2003-06-30 14:44:25 +02:00
|
|
|
|
macro (struct mips_cl_insn *ip)
|
1999-05-03 09:29:11 +02:00
|
|
|
|
{
|
|
|
|
|
register int treg, sreg, dreg, breg;
|
|
|
|
|
int tempreg;
|
|
|
|
|
int mask;
|
|
|
|
|
int icnt = 0;
|
2000-05-30 00:05:27 +02:00
|
|
|
|
int used_at = 0;
|
1999-05-03 09:29:11 +02:00
|
|
|
|
expressionS expr1;
|
|
|
|
|
const char *s;
|
|
|
|
|
const char *s2;
|
|
|
|
|
const char *fmt;
|
|
|
|
|
int likely = 0;
|
|
|
|
|
int dbl = 0;
|
|
|
|
|
int coproc = 0;
|
|
|
|
|
int lr = 0;
|
|
|
|
|
int imm = 0;
|
2003-11-18 22:22:57 +01:00
|
|
|
|
int call = 0;
|
1999-05-03 09:29:11 +02:00
|
|
|
|
offsetT maxnum;
|
|
|
|
|
int off;
|
|
|
|
|
bfd_reloc_code_real_type r;
|
|
|
|
|
int hold_mips_optimize;
|
|
|
|
|
|
|
|
|
|
assert (! mips_opts.mips16);
|
|
|
|
|
|
|
|
|
|
treg = (ip->insn_opcode >> 16) & 0x1f;
|
|
|
|
|
dreg = (ip->insn_opcode >> 11) & 0x1f;
|
|
|
|
|
sreg = breg = (ip->insn_opcode >> 21) & 0x1f;
|
|
|
|
|
mask = ip->insn_mo->mask;
|
|
|
|
|
|
|
|
|
|
expr1.X_op = O_constant;
|
|
|
|
|
expr1.X_op_symbol = NULL;
|
|
|
|
|
expr1.X_add_symbol = NULL;
|
|
|
|
|
expr1.X_add_number = 1;
|
|
|
|
|
|
2003-11-22 03:35:31 +01:00
|
|
|
|
/* Unmatched fixups should not be put in the same frag as a relaxable
|
2003-02-08 18:05:55 +01:00
|
|
|
|
macro. For example, suppose we have:
|
|
|
|
|
|
|
|
|
|
lui $4,%hi(l1) # 1
|
|
|
|
|
la $5,l2 # 2
|
|
|
|
|
addiu $4,$4,%lo(l1) # 3
|
|
|
|
|
|
|
|
|
|
If instructions 1 and 2 were put in the same frag, md_frob_file would
|
|
|
|
|
move the fixup for #1 after the fixups for the "unrelaxed" version of
|
|
|
|
|
#2. This would confuse tc_gen_reloc, which expects the relocations
|
|
|
|
|
for #2 to be the last for that frag.
|
|
|
|
|
|
2003-02-21 11:28:27 +01:00
|
|
|
|
Also, if tc_gen_reloc sees certain relocations in a variant frag,
|
|
|
|
|
it assumes that they belong to a relaxable macro. We mustn't put
|
|
|
|
|
other uses of such relocations into a variant frag.
|
|
|
|
|
|
|
|
|
|
To avoid both problems, finish the current frag it contains a
|
|
|
|
|
%reloc() operator. The macro then goes into a new frag. */
|
|
|
|
|
if (prev_reloc_op_frag == frag_now)
|
2003-02-08 18:05:55 +01:00
|
|
|
|
{
|
|
|
|
|
frag_wane (frag_now);
|
|
|
|
|
frag_new (0);
|
|
|
|
|
}
|
|
|
|
|
|
1999-05-03 09:29:11 +02:00
|
|
|
|
switch (mask)
|
|
|
|
|
{
|
|
|
|
|
case M_DABS:
|
|
|
|
|
dbl = 1;
|
|
|
|
|
case M_ABS:
|
|
|
|
|
/* bgez $a0,.+12
|
|
|
|
|
move v0,$a0
|
|
|
|
|
sub v0,$zero,$a0
|
|
|
|
|
*/
|
|
|
|
|
|
2002-11-30 09:39:46 +01:00
|
|
|
|
mips_emit_delays (TRUE);
|
1999-05-03 09:29:11 +02:00
|
|
|
|
++mips_opts.noreorder;
|
|
|
|
|
mips_any_noreorder = 1;
|
|
|
|
|
|
|
|
|
|
expr1.X_add_number = 8;
|
2003-06-30 14:44:25 +02:00
|
|
|
|
macro_build (NULL, &icnt, &expr1, "bgez", "s,p", sreg);
|
1999-05-03 09:29:11 +02:00
|
|
|
|
if (dreg == sreg)
|
2003-06-30 14:44:25 +02:00
|
|
|
|
macro_build (NULL, &icnt, NULL, "nop", "", 0);
|
1999-05-03 09:29:11 +02:00
|
|
|
|
else
|
2001-08-10 18:24:32 +02:00
|
|
|
|
move_register (&icnt, dreg, sreg);
|
2003-06-30 14:44:25 +02:00
|
|
|
|
macro_build (NULL, &icnt, NULL, dbl ? "dsub" : "sub", "d,v,t", dreg, 0,
|
|
|
|
|
sreg);
|
1999-05-03 09:29:11 +02:00
|
|
|
|
|
|
|
|
|
--mips_opts.noreorder;
|
|
|
|
|
return;
|
|
|
|
|
|
|
|
|
|
case M_ADD_I:
|
|
|
|
|
s = "addi";
|
|
|
|
|
s2 = "add";
|
|
|
|
|
goto do_addi;
|
|
|
|
|
case M_ADDU_I:
|
|
|
|
|
s = "addiu";
|
|
|
|
|
s2 = "addu";
|
|
|
|
|
goto do_addi;
|
|
|
|
|
case M_DADD_I:
|
|
|
|
|
dbl = 1;
|
|
|
|
|
s = "daddi";
|
|
|
|
|
s2 = "dadd";
|
|
|
|
|
goto do_addi;
|
|
|
|
|
case M_DADDU_I:
|
|
|
|
|
dbl = 1;
|
|
|
|
|
s = "daddiu";
|
|
|
|
|
s2 = "daddu";
|
|
|
|
|
do_addi:
|
|
|
|
|
if (imm_expr.X_op == O_constant
|
|
|
|
|
&& imm_expr.X_add_number >= -0x8000
|
|
|
|
|
&& imm_expr.X_add_number < 0x8000)
|
|
|
|
|
{
|
2003-06-30 14:44:25 +02:00
|
|
|
|
macro_build (NULL, &icnt, &imm_expr, s, "t,r,j", treg, sreg,
|
|
|
|
|
BFD_RELOC_LO16);
|
1999-05-03 09:29:11 +02:00
|
|
|
|
return;
|
|
|
|
|
}
|
|
|
|
|
load_register (&icnt, AT, &imm_expr, dbl);
|
2003-06-30 14:44:25 +02:00
|
|
|
|
macro_build (NULL, &icnt, NULL, s2, "d,v,t", treg, sreg, AT);
|
1999-05-03 09:29:11 +02:00
|
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
case M_AND_I:
|
|
|
|
|
s = "andi";
|
|
|
|
|
s2 = "and";
|
|
|
|
|
goto do_bit;
|
|
|
|
|
case M_OR_I:
|
|
|
|
|
s = "ori";
|
|
|
|
|
s2 = "or";
|
|
|
|
|
goto do_bit;
|
|
|
|
|
case M_NOR_I:
|
|
|
|
|
s = "";
|
|
|
|
|
s2 = "nor";
|
|
|
|
|
goto do_bit;
|
|
|
|
|
case M_XOR_I:
|
|
|
|
|
s = "xori";
|
|
|
|
|
s2 = "xor";
|
|
|
|
|
do_bit:
|
|
|
|
|
if (imm_expr.X_op == O_constant
|
|
|
|
|
&& imm_expr.X_add_number >= 0
|
|
|
|
|
&& imm_expr.X_add_number < 0x10000)
|
|
|
|
|
{
|
|
|
|
|
if (mask != M_NOR_I)
|
2003-06-30 14:44:25 +02:00
|
|
|
|
macro_build (NULL, &icnt, &imm_expr, s, "t,r,i", treg, sreg,
|
|
|
|
|
BFD_RELOC_LO16);
|
1999-05-03 09:29:11 +02:00
|
|
|
|
else
|
|
|
|
|
{
|
2003-06-30 14:44:25 +02:00
|
|
|
|
macro_build (NULL, &icnt, &imm_expr, "ori", "t,r,i", treg, sreg,
|
|
|
|
|
BFD_RELOC_LO16);
|
|
|
|
|
macro_build (NULL, &icnt, NULL, "nor", "d,v,t", treg, treg, 0);
|
1999-05-03 09:29:11 +02:00
|
|
|
|
}
|
|
|
|
|
return;
|
|
|
|
|
}
|
|
|
|
|
|
2001-10-10 02:43:36 +02:00
|
|
|
|
load_register (&icnt, AT, &imm_expr, HAVE_64BIT_GPRS);
|
2003-06-30 14:44:25 +02:00
|
|
|
|
macro_build (NULL, &icnt, NULL, s2, "d,v,t", treg, sreg, AT);
|
1999-05-03 09:29:11 +02:00
|
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
case M_BEQ_I:
|
|
|
|
|
s = "beq";
|
|
|
|
|
goto beq_i;
|
|
|
|
|
case M_BEQL_I:
|
|
|
|
|
s = "beql";
|
|
|
|
|
likely = 1;
|
|
|
|
|
goto beq_i;
|
|
|
|
|
case M_BNE_I:
|
|
|
|
|
s = "bne";
|
|
|
|
|
goto beq_i;
|
|
|
|
|
case M_BNEL_I:
|
|
|
|
|
s = "bnel";
|
|
|
|
|
likely = 1;
|
|
|
|
|
beq_i:
|
|
|
|
|
if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
|
|
|
|
|
{
|
2003-06-30 14:44:25 +02:00
|
|
|
|
macro_build (NULL, &icnt, &offset_expr, s, "s,t,p", sreg, 0);
|
1999-05-03 09:29:11 +02:00
|
|
|
|
return;
|
|
|
|
|
}
|
2002-02-25 14:21:38 +01:00
|
|
|
|
load_register (&icnt, AT, &imm_expr, HAVE_64BIT_GPRS);
|
2003-06-30 14:44:25 +02:00
|
|
|
|
macro_build (NULL, &icnt, &offset_expr, s, "s,t,p", sreg, AT);
|
1999-05-03 09:29:11 +02:00
|
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
case M_BGEL:
|
|
|
|
|
likely = 1;
|
|
|
|
|
case M_BGE:
|
|
|
|
|
if (treg == 0)
|
|
|
|
|
{
|
2003-06-30 14:44:25 +02:00
|
|
|
|
macro_build (NULL, &icnt, &offset_expr, likely ? "bgezl" : "bgez",
|
|
|
|
|
"s,p", sreg);
|
1999-05-03 09:29:11 +02:00
|
|
|
|
return;
|
|
|
|
|
}
|
|
|
|
|
if (sreg == 0)
|
|
|
|
|
{
|
2003-06-30 14:44:25 +02:00
|
|
|
|
macro_build (NULL, &icnt, &offset_expr, likely ? "blezl" : "blez",
|
|
|
|
|
"s,p", treg);
|
1999-05-03 09:29:11 +02:00
|
|
|
|
return;
|
|
|
|
|
}
|
2003-06-30 14:44:25 +02:00
|
|
|
|
macro_build (NULL, &icnt, NULL, "slt", "d,v,t", AT, sreg, treg);
|
|
|
|
|
macro_build (NULL, &icnt, &offset_expr, likely ? "beql" : "beq",
|
|
|
|
|
"s,t,p", AT, 0);
|
1999-05-03 09:29:11 +02:00
|
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
case M_BGTL_I:
|
|
|
|
|
likely = 1;
|
|
|
|
|
case M_BGT_I:
|
|
|
|
|
/* check for > max integer */
|
|
|
|
|
maxnum = 0x7fffffff;
|
2001-08-02 12:15:24 +02:00
|
|
|
|
if (HAVE_64BIT_GPRS && sizeof (maxnum) > 4)
|
1999-05-03 09:29:11 +02:00
|
|
|
|
{
|
|
|
|
|
maxnum <<= 16;
|
|
|
|
|
maxnum |= 0xffff;
|
|
|
|
|
maxnum <<= 16;
|
|
|
|
|
maxnum |= 0xffff;
|
|
|
|
|
}
|
|
|
|
|
if (imm_expr.X_op == O_constant
|
|
|
|
|
&& imm_expr.X_add_number >= maxnum
|
2001-08-02 12:15:24 +02:00
|
|
|
|
&& (HAVE_32BIT_GPRS || sizeof (maxnum) > 4))
|
1999-05-03 09:29:11 +02:00
|
|
|
|
{
|
|
|
|
|
do_false:
|
|
|
|
|
/* result is always false */
|
|
|
|
|
if (! likely)
|
2004-01-09 03:34:04 +01:00
|
|
|
|
macro_build (NULL, &icnt, NULL, "nop", "", 0);
|
1999-05-03 09:29:11 +02:00
|
|
|
|
else
|
2004-01-09 03:34:04 +01:00
|
|
|
|
macro_build (NULL, &icnt, &offset_expr, "bnel", "s,t,p", 0, 0);
|
1999-05-03 09:29:11 +02:00
|
|
|
|
return;
|
|
|
|
|
}
|
|
|
|
|
if (imm_expr.X_op != O_constant)
|
|
|
|
|
as_bad (_("Unsupported large constant"));
|
2002-05-26 20:46:37 +02:00
|
|
|
|
++imm_expr.X_add_number;
|
1999-05-03 09:29:11 +02:00
|
|
|
|
/* FALLTHROUGH */
|
|
|
|
|
case M_BGE_I:
|
|
|
|
|
case M_BGEL_I:
|
|
|
|
|
if (mask == M_BGEL_I)
|
|
|
|
|
likely = 1;
|
|
|
|
|
if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
|
|
|
|
|
{
|
2003-06-30 14:44:25 +02:00
|
|
|
|
macro_build (NULL, &icnt, &offset_expr, likely ? "bgezl" : "bgez",
|
|
|
|
|
"s,p", sreg);
|
1999-05-03 09:29:11 +02:00
|
|
|
|
return;
|
|
|
|
|
}
|
|
|
|
|
if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1)
|
|
|
|
|
{
|
2003-06-30 14:44:25 +02:00
|
|
|
|
macro_build (NULL, &icnt, &offset_expr, likely ? "bgtzl" : "bgtz",
|
|
|
|
|
"s,p", sreg);
|
1999-05-03 09:29:11 +02:00
|
|
|
|
return;
|
|
|
|
|
}
|
|
|
|
|
maxnum = 0x7fffffff;
|
2001-08-02 12:15:24 +02:00
|
|
|
|
if (HAVE_64BIT_GPRS && sizeof (maxnum) > 4)
|
1999-05-03 09:29:11 +02:00
|
|
|
|
{
|
|
|
|
|
maxnum <<= 16;
|
|
|
|
|
maxnum |= 0xffff;
|
|
|
|
|
maxnum <<= 16;
|
|
|
|
|
maxnum |= 0xffff;
|
|
|
|
|
}
|
|
|
|
|
maxnum = - maxnum - 1;
|
|
|
|
|
if (imm_expr.X_op == O_constant
|
|
|
|
|
&& imm_expr.X_add_number <= maxnum
|
2001-08-02 12:15:24 +02:00
|
|
|
|
&& (HAVE_32BIT_GPRS || sizeof (maxnum) > 4))
|
1999-05-03 09:29:11 +02:00
|
|
|
|
{
|
|
|
|
|
do_true:
|
|
|
|
|
/* result is always true */
|
|
|
|
|
as_warn (_("Branch %s is always true"), ip->insn_mo->name);
|
2003-06-30 14:44:25 +02:00
|
|
|
|
macro_build (NULL, &icnt, &offset_expr, "b", "p");
|
1999-05-03 09:29:11 +02:00
|
|
|
|
return;
|
|
|
|
|
}
|
|
|
|
|
set_at (&icnt, sreg, 0);
|
2003-06-30 14:44:25 +02:00
|
|
|
|
macro_build (NULL, &icnt, &offset_expr, likely ? "beql" : "beq",
|
|
|
|
|
"s,t,p", AT, 0);
|
1999-05-03 09:29:11 +02:00
|
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
case M_BGEUL:
|
|
|
|
|
likely = 1;
|
|
|
|
|
case M_BGEU:
|
|
|
|
|
if (treg == 0)
|
|
|
|
|
goto do_true;
|
|
|
|
|
if (sreg == 0)
|
|
|
|
|
{
|
2003-06-30 14:44:25 +02:00
|
|
|
|
macro_build (NULL, &icnt, &offset_expr, likely ? "beql" : "beq",
|
|
|
|
|
"s,t,p", 0, treg);
|
1999-05-03 09:29:11 +02:00
|
|
|
|
return;
|
|
|
|
|
}
|
2003-06-30 14:44:25 +02:00
|
|
|
|
macro_build (NULL, &icnt, NULL, "sltu", "d,v,t", AT, sreg, treg);
|
|
|
|
|
macro_build (NULL, &icnt, &offset_expr, likely ? "beql" : "beq",
|
|
|
|
|
"s,t,p", AT, 0);
|
1999-05-03 09:29:11 +02:00
|
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
case M_BGTUL_I:
|
|
|
|
|
likely = 1;
|
|
|
|
|
case M_BGTU_I:
|
|
|
|
|
if (sreg == 0
|
2001-08-02 12:15:24 +02:00
|
|
|
|
|| (HAVE_32BIT_GPRS
|
1999-05-03 09:29:11 +02:00
|
|
|
|
&& imm_expr.X_op == O_constant
|
2001-12-04 15:38:48 +01:00
|
|
|
|
&& imm_expr.X_add_number == (offsetT) 0xffffffff))
|
1999-05-03 09:29:11 +02:00
|
|
|
|
goto do_false;
|
|
|
|
|
if (imm_expr.X_op != O_constant)
|
|
|
|
|
as_bad (_("Unsupported large constant"));
|
2002-05-26 20:46:37 +02:00
|
|
|
|
++imm_expr.X_add_number;
|
1999-05-03 09:29:11 +02:00
|
|
|
|
/* FALLTHROUGH */
|
|
|
|
|
case M_BGEU_I:
|
|
|
|
|
case M_BGEUL_I:
|
|
|
|
|
if (mask == M_BGEUL_I)
|
|
|
|
|
likely = 1;
|
|
|
|
|
if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
|
|
|
|
|
goto do_true;
|
|
|
|
|
if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1)
|
|
|
|
|
{
|
2003-06-30 14:44:25 +02:00
|
|
|
|
macro_build (NULL, &icnt, &offset_expr, likely ? "bnel" : "bne",
|
|
|
|
|
"s,t,p", sreg, 0);
|
1999-05-03 09:29:11 +02:00
|
|
|
|
return;
|
|
|
|
|
}
|
|
|
|
|
set_at (&icnt, sreg, 1);
|
2003-06-30 14:44:25 +02:00
|
|
|
|
macro_build (NULL, &icnt, &offset_expr, likely ? "beql" : "beq",
|
|
|
|
|
"s,t,p", AT, 0);
|
1999-05-03 09:29:11 +02:00
|
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
case M_BGTL:
|
|
|
|
|
likely = 1;
|
|
|
|
|
case M_BGT:
|
|
|
|
|
if (treg == 0)
|
|
|
|
|
{
|
2003-06-30 14:44:25 +02:00
|
|
|
|
macro_build (NULL, &icnt, &offset_expr, likely ? "bgtzl" : "bgtz",
|
|
|
|
|
"s,p", sreg);
|
1999-05-03 09:29:11 +02:00
|
|
|
|
return;
|
|
|
|
|
}
|
|
|
|
|
if (sreg == 0)
|
|
|
|
|
{
|
2003-06-30 14:44:25 +02:00
|
|
|
|
macro_build (NULL, &icnt, &offset_expr, likely ? "bltzl" : "bltz",
|
|
|
|
|
"s,p", treg);
|
1999-05-03 09:29:11 +02:00
|
|
|
|
return;
|
|
|
|
|
}
|
2003-06-30 14:44:25 +02:00
|
|
|
|
macro_build (NULL, &icnt, NULL, "slt", "d,v,t", AT, treg, sreg);
|
|
|
|
|
macro_build (NULL, &icnt, &offset_expr, likely ? "bnel" : "bne",
|
|
|
|
|
"s,t,p", AT, 0);
|
1999-05-03 09:29:11 +02:00
|
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
case M_BGTUL:
|
|
|
|
|
likely = 1;
|
|
|
|
|
case M_BGTU:
|
|
|
|
|
if (treg == 0)
|
|
|
|
|
{
|
2003-06-30 14:44:25 +02:00
|
|
|
|
macro_build (NULL, &icnt, &offset_expr, likely ? "bnel" : "bne",
|
|
|
|
|
"s,t,p", sreg, 0);
|
1999-05-03 09:29:11 +02:00
|
|
|
|
return;
|
|
|
|
|
}
|
|
|
|
|
if (sreg == 0)
|
|
|
|
|
goto do_false;
|
2003-06-30 14:44:25 +02:00
|
|
|
|
macro_build (NULL, &icnt, NULL, "sltu", "d,v,t", AT, treg, sreg);
|
|
|
|
|
macro_build (NULL, &icnt, &offset_expr, likely ? "bnel" : "bne",
|
|
|
|
|
"s,t,p", AT, 0);
|
1999-05-03 09:29:11 +02:00
|
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
case M_BLEL:
|
|
|
|
|
likely = 1;
|
|
|
|
|
case M_BLE:
|
|
|
|
|
if (treg == 0)
|
|
|
|
|
{
|
2003-06-30 14:44:25 +02:00
|
|
|
|
macro_build (NULL, &icnt, &offset_expr, likely ? "blezl" : "blez",
|
|
|
|
|
"s,p", sreg);
|
1999-05-03 09:29:11 +02:00
|
|
|
|
return;
|
|
|
|
|
}
|
|
|
|
|
if (sreg == 0)
|
|
|
|
|
{
|
2003-06-30 14:44:25 +02:00
|
|
|
|
macro_build (NULL, &icnt, &offset_expr, likely ? "bgezl" : "bgez",
|
|
|
|
|
"s,p", treg);
|
1999-05-03 09:29:11 +02:00
|
|
|
|
return;
|
|
|
|
|
}
|
2003-06-30 14:44:25 +02:00
|
|
|
|
macro_build (NULL, &icnt, NULL, "slt", "d,v,t", AT, treg, sreg);
|
|
|
|
|
macro_build (NULL, &icnt, &offset_expr, likely ? "beql" : "beq",
|
|
|
|
|
"s,t,p", AT, 0);
|
1999-05-03 09:29:11 +02:00
|
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
case M_BLEL_I:
|
|
|
|
|
likely = 1;
|
|
|
|
|
case M_BLE_I:
|
|
|
|
|
maxnum = 0x7fffffff;
|
2001-08-02 12:15:24 +02:00
|
|
|
|
if (HAVE_64BIT_GPRS && sizeof (maxnum) > 4)
|
1999-05-03 09:29:11 +02:00
|
|
|
|
{
|
|
|
|
|
maxnum <<= 16;
|
|
|
|
|
maxnum |= 0xffff;
|
|
|
|
|
maxnum <<= 16;
|
|
|
|
|
maxnum |= 0xffff;
|
|
|
|
|
}
|
|
|
|
|
if (imm_expr.X_op == O_constant
|
|
|
|
|
&& imm_expr.X_add_number >= maxnum
|
2001-08-02 12:15:24 +02:00
|
|
|
|
&& (HAVE_32BIT_GPRS || sizeof (maxnum) > 4))
|
1999-05-03 09:29:11 +02:00
|
|
|
|
goto do_true;
|
|
|
|
|
if (imm_expr.X_op != O_constant)
|
|
|
|
|
as_bad (_("Unsupported large constant"));
|
2002-05-26 20:46:37 +02:00
|
|
|
|
++imm_expr.X_add_number;
|
1999-05-03 09:29:11 +02:00
|
|
|
|
/* FALLTHROUGH */
|
|
|
|
|
case M_BLT_I:
|
|
|
|
|
case M_BLTL_I:
|
|
|
|
|
if (mask == M_BLTL_I)
|
|
|
|
|
likely = 1;
|
|
|
|
|
if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
|
|
|
|
|
{
|
2003-06-30 14:44:25 +02:00
|
|
|
|
macro_build (NULL, &icnt, &offset_expr, likely ? "bltzl" : "bltz",
|
|
|
|
|
"s,p", sreg);
|
1999-05-03 09:29:11 +02:00
|
|
|
|
return;
|
|
|
|
|
}
|
|
|
|
|
if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1)
|
|
|
|
|
{
|
2003-06-30 14:44:25 +02:00
|
|
|
|
macro_build (NULL, &icnt, &offset_expr, likely ? "blezl" : "blez",
|
|
|
|
|
"s,p", sreg);
|
1999-05-03 09:29:11 +02:00
|
|
|
|
return;
|
|
|
|
|
}
|
|
|
|
|
set_at (&icnt, sreg, 0);
|
2003-06-30 14:44:25 +02:00
|
|
|
|
macro_build (NULL, &icnt, &offset_expr, likely ? "bnel" : "bne",
|
|
|
|
|
"s,t,p", AT, 0);
|
1999-05-03 09:29:11 +02:00
|
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
case M_BLEUL:
|
|
|
|
|
likely = 1;
|
|
|
|
|
case M_BLEU:
|
|
|
|
|
if (treg == 0)
|
|
|
|
|
{
|
2003-06-30 14:44:25 +02:00
|
|
|
|
macro_build (NULL, &icnt, &offset_expr, likely ? "beql" : "beq",
|
|
|
|
|
"s,t,p", sreg, 0);
|
1999-05-03 09:29:11 +02:00
|
|
|
|
return;
|
|
|
|
|
}
|
|
|
|
|
if (sreg == 0)
|
|
|
|
|
goto do_true;
|
2003-06-30 14:44:25 +02:00
|
|
|
|
macro_build (NULL, &icnt, NULL, "sltu", "d,v,t", AT, treg, sreg);
|
|
|
|
|
macro_build (NULL, &icnt, &offset_expr, likely ? "beql" : "beq",
|
|
|
|
|
"s,t,p", AT, 0);
|
1999-05-03 09:29:11 +02:00
|
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
case M_BLEUL_I:
|
|
|
|
|
likely = 1;
|
|
|
|
|
case M_BLEU_I:
|
|
|
|
|
if (sreg == 0
|
2001-08-02 12:15:24 +02:00
|
|
|
|
|| (HAVE_32BIT_GPRS
|
1999-05-03 09:29:11 +02:00
|
|
|
|
&& imm_expr.X_op == O_constant
|
2001-12-04 15:38:48 +01:00
|
|
|
|
&& imm_expr.X_add_number == (offsetT) 0xffffffff))
|
1999-05-03 09:29:11 +02:00
|
|
|
|
goto do_true;
|
|
|
|
|
if (imm_expr.X_op != O_constant)
|
|
|
|
|
as_bad (_("Unsupported large constant"));
|
2002-05-26 20:46:37 +02:00
|
|
|
|
++imm_expr.X_add_number;
|
1999-05-03 09:29:11 +02:00
|
|
|
|
/* FALLTHROUGH */
|
|
|
|
|
case M_BLTU_I:
|
|
|
|
|
case M_BLTUL_I:
|
|
|
|
|
if (mask == M_BLTUL_I)
|
|
|
|
|
likely = 1;
|
|
|
|
|
if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
|
|
|
|
|
goto do_false;
|
|
|
|
|
if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1)
|
|
|
|
|
{
|
2003-06-30 14:44:25 +02:00
|
|
|
|
macro_build (NULL, &icnt, &offset_expr, likely ? "beql" : "beq",
|
1999-05-03 09:29:11 +02:00
|
|
|
|
"s,t,p", sreg, 0);
|
|
|
|
|
return;
|
|
|
|
|
}
|
|
|
|
|
set_at (&icnt, sreg, 1);
|
2003-06-30 14:44:25 +02:00
|
|
|
|
macro_build (NULL, &icnt, &offset_expr, likely ? "bnel" : "bne",
|
|
|
|
|
"s,t,p", AT, 0);
|
1999-05-03 09:29:11 +02:00
|
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
case M_BLTL:
|
|
|
|
|
likely = 1;
|
|
|
|
|
case M_BLT:
|
|
|
|
|
if (treg == 0)
|
|
|
|
|
{
|
2003-06-30 14:44:25 +02:00
|
|
|
|
macro_build (NULL, &icnt, &offset_expr, likely ? "bltzl" : "bltz",
|
|
|
|
|
"s,p", sreg);
|
1999-05-03 09:29:11 +02:00
|
|
|
|
return;
|
|
|
|
|
}
|
|
|
|
|
if (sreg == 0)
|
|
|
|
|
{
|
2003-06-30 14:44:25 +02:00
|
|
|
|
macro_build (NULL, &icnt, &offset_expr, likely ? "bgtzl" : "bgtz",
|
|
|
|
|
"s,p", treg);
|
1999-05-03 09:29:11 +02:00
|
|
|
|
return;
|
|
|
|
|
}
|
2003-06-30 14:44:25 +02:00
|
|
|
|
macro_build (NULL, &icnt, NULL, "slt", "d,v,t", AT, sreg, treg);
|
|
|
|
|
macro_build (NULL, &icnt, &offset_expr, likely ? "bnel" : "bne",
|
|
|
|
|
"s,t,p", AT, 0);
|
1999-05-03 09:29:11 +02:00
|
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
case M_BLTUL:
|
|
|
|
|
likely = 1;
|
|
|
|
|
case M_BLTU:
|
|
|
|
|
if (treg == 0)
|
|
|
|
|
goto do_false;
|
|
|
|
|
if (sreg == 0)
|
|
|
|
|
{
|
2003-06-30 14:44:25 +02:00
|
|
|
|
macro_build (NULL, &icnt, &offset_expr, likely ? "bnel" : "bne",
|
|
|
|
|
"s,t,p", 0, treg);
|
1999-05-03 09:29:11 +02:00
|
|
|
|
return;
|
|
|
|
|
}
|
2003-06-30 14:44:25 +02:00
|
|
|
|
macro_build (NULL, &icnt, NULL, "sltu", "d,v,t", AT, sreg, treg);
|
|
|
|
|
macro_build (NULL, &icnt, &offset_expr, likely ? "bnel" : "bne",
|
|
|
|
|
"s,t,p", AT, 0);
|
1999-05-03 09:29:11 +02:00
|
|
|
|
break;
|
|
|
|
|
|
[ bfd/ChangeLog ]
2003-09-30 Chris Demetriou <cgd@broadcom.com>
* archures.c (bfd_mach_mipsisa64r2): New define.
* bfd-in2.h: Regenerate.
* aoutx.h (NAME(aout,machine_type)): Handle bfd_mach_mipsisa64r2.
* cpu-mips.c (I_mipsisa64r2): New enum value.
(arch_info_struct): Add entry for I_mipsisa64r2.
* elfxx-mips.c (_bfd_elf_mips_mach)
(_bfd_mips_elf_print_private_bfd_data): Handle E_MIPS_ARCH_64R2.
(mips_set_isa_flags): Add bfd_mach_mipsisa64r2 case.
(mips_mach_extensions): Add entry for bfd_mach_mipsisa64r2.
[ binutils/ChangeLog ]
2003-09-30 Chris Demetriou <cgd@broadcom.com>
* readelf.c (get_machine_flags): Handle E_MIPS_ARCH_64R2.
[ gas/Changelog ]
2003-09-30 Chris Demetriou <cgd@broadcom.com>
* configure.in (mipsisa64r2, mipsisa64r2el, mipsisa64r2*): New CPUs.
* configure: Regenerate.
* config/tc-mips.c (imm2_expr): New variable.
(md_assemble, mips16_ip): Initialize imm2_expr.
(ISA_HAS_64BIT_REGS, ISA_HAS_DROR, ISA_HAS_ROR): Add ISA_MIPS64R2.
(macro_build): Handle +A, +B, +C, +E, +F, +G, and +H format operands.
(macro): Handle M_DEXT and M_DINS.
(validate_mips_insn): Handle +E, +F, +G, +H, and +I format operands.
(mips_ip): Likewise.
(OPTION_MIPS64R2): New define.
(md_longopts): New entry for -mips64r2 (OPTION_MIPS64R2).
OPTION_ASE_BASE): Increase to compensate for OPTION_MIPS64R2.
(md_parse_option): Handle OPTION_MIPS64R2.
(s_mipsset): Handle setting "mips64r2" ISA.
(mips_cpu_info_table): Add mips64r2.
(md_show_usage): Document -mips64r2 option.
* doc/as.texinfo: Docuemnt -mips64r2 option.
* doc/c-mips.texi: Likewise.
[ gas/testsuite/ChangeLog ]
2003-09-30 Chris Demetriou <cgd@broadcom.com>
* gas/mips/cp0-names-mips64r2.d: New file.
* gas/mips/cp0sel-names-mips64r2.d: New file.
* gas/mips/elf_arch_mips64r2.d: New file.
* gas/mips/hwr-names-mips64r2.d: New file.
* gas/mips/mips32r2-ill-fp64.l: New file.
* gas/mips/mips32r2-ill-fp64.s: New file.
* gas/mips/mips64r2-ill.l: New file.
* gas/mips/mips64r2-ill.s: New file.
* gas/mips/mips64r2.d: New file.
* gas/mips/mips64r2.s: New file.
* gas/mips/mips.exp: Define "mips64r2" arch, and run new tests.
[ include/elf/ChangeLog ]
2003-09-30 Chris Demetriou <cgd@broadcom.com>
* mips.h (E_MIPS_ARCH_64R2): New define.
[ include/opcode/ChangeLog ]
2003-09-30 Chris Demetriou <cgd@broadcom.com>
* mips.h: Document +E, +F, +G, +H, and +I operand types.
Update documentation of I, +B and +C operand types.
(INSN_ISA64R2, ISA_MIPS64R2, CPU_MIPS64R2): New defines.
(M_DEXT, M_DINS): New enum values.
[ ld/ChangeLog ]
2003-09-30 Chris Demetriou <cgd@broadcom.com>
* ldmain.c (get_emulation): Ignore "-mips64r2".
[ ld/testsuite/ChangeLog ]
2003-09-30 Chris Demetriou <cgd@broadcom.com>
* ld-mips-elf/mips-elf-flags.exp: Add tests for combinations
with MIPS64r2.
[ opcodes/ChangeLog ]
2003-09-30 Chris Demetriou <cgd@broadcom.com>
* mips-dis.c (mips_arch_choices): Add entry for "mips64r2"
(print_insn_args): Add handing for +E, +F, +G, and +H.
* mips-opc.c (I65): New define for MIPS64r2.
(mips_builtin_opcodes): Add "dext", "dextm", "dextu", "dins",
"dinsm", "dinsu", "drotl", "drotr", "drotr32", "drotrv", "dsbh",
and "dshd" for MIPS64r2. Adjust "dror", "dror32", and "drorv" to
be supported on MIPS64r2.
2003-09-30 18:17:15 +02:00
|
|
|
|
case M_DEXT:
|
|
|
|
|
{
|
|
|
|
|
unsigned long pos;
|
|
|
|
|
unsigned long size;
|
|
|
|
|
|
|
|
|
|
if (imm_expr.X_op != O_constant || imm2_expr.X_op != O_constant)
|
|
|
|
|
{
|
|
|
|
|
as_bad (_("Unsupported large constant"));
|
|
|
|
|
pos = size = 1;
|
|
|
|
|
}
|
|
|
|
|
else
|
|
|
|
|
{
|
|
|
|
|
pos = (unsigned long) imm_expr.X_add_number;
|
|
|
|
|
size = (unsigned long) imm2_expr.X_add_number;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
if (pos > 63)
|
|
|
|
|
{
|
|
|
|
|
as_bad (_("Improper position (%lu)"), pos);
|
|
|
|
|
pos = 1;
|
|
|
|
|
}
|
|
|
|
|
if (size == 0 || size > 64
|
|
|
|
|
|| (pos + size - 1) > 63)
|
|
|
|
|
{
|
|
|
|
|
as_bad (_("Improper extract size (%lu, position %lu)"),
|
|
|
|
|
size, pos);
|
|
|
|
|
size = 1;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
if (size <= 32 && pos < 32)
|
|
|
|
|
{
|
|
|
|
|
s = "dext";
|
|
|
|
|
fmt = "t,r,+A,+C";
|
|
|
|
|
}
|
|
|
|
|
else if (size <= 32)
|
|
|
|
|
{
|
|
|
|
|
s = "dextu";
|
|
|
|
|
fmt = "t,r,+E,+H";
|
|
|
|
|
}
|
|
|
|
|
else
|
|
|
|
|
{
|
|
|
|
|
s = "dextm";
|
|
|
|
|
fmt = "t,r,+A,+G";
|
|
|
|
|
}
|
|
|
|
|
macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s,
|
|
|
|
|
fmt, treg, sreg, pos, size - 1);
|
|
|
|
|
}
|
|
|
|
|
return;
|
|
|
|
|
|
|
|
|
|
case M_DINS:
|
|
|
|
|
{
|
|
|
|
|
unsigned long pos;
|
|
|
|
|
unsigned long size;
|
|
|
|
|
|
|
|
|
|
if (imm_expr.X_op != O_constant || imm2_expr.X_op != O_constant)
|
|
|
|
|
{
|
|
|
|
|
as_bad (_("Unsupported large constant"));
|
|
|
|
|
pos = size = 1;
|
|
|
|
|
}
|
|
|
|
|
else
|
|
|
|
|
{
|
|
|
|
|
pos = (unsigned long) imm_expr.X_add_number;
|
|
|
|
|
size = (unsigned long) imm2_expr.X_add_number;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
if (pos > 63)
|
|
|
|
|
{
|
|
|
|
|
as_bad (_("Improper position (%lu)"), pos);
|
|
|
|
|
pos = 1;
|
|
|
|
|
}
|
|
|
|
|
if (size == 0 || size > 64
|
|
|
|
|
|| (pos + size - 1) > 63)
|
|
|
|
|
{
|
|
|
|
|
as_bad (_("Improper insert size (%lu, position %lu)"),
|
|
|
|
|
size, pos);
|
|
|
|
|
size = 1;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
if (pos < 32 && (pos + size - 1) < 32)
|
|
|
|
|
{
|
|
|
|
|
s = "dins";
|
|
|
|
|
fmt = "t,r,+A,+B";
|
|
|
|
|
}
|
|
|
|
|
else if (pos >= 32)
|
|
|
|
|
{
|
|
|
|
|
s = "dinsu";
|
|
|
|
|
fmt = "t,r,+E,+F";
|
|
|
|
|
}
|
|
|
|
|
else
|
|
|
|
|
{
|
|
|
|
|
s = "dinsm";
|
|
|
|
|
fmt = "t,r,+A,+F";
|
|
|
|
|
}
|
|
|
|
|
macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s,
|
|
|
|
|
fmt, treg, sreg, pos, pos + size - 1);
|
|
|
|
|
}
|
|
|
|
|
return;
|
|
|
|
|
|
1999-05-03 09:29:11 +02:00
|
|
|
|
case M_DDIV_3:
|
|
|
|
|
dbl = 1;
|
|
|
|
|
case M_DIV_3:
|
|
|
|
|
s = "mflo";
|
|
|
|
|
goto do_div3;
|
|
|
|
|
case M_DREM_3:
|
|
|
|
|
dbl = 1;
|
|
|
|
|
case M_REM_3:
|
|
|
|
|
s = "mfhi";
|
|
|
|
|
do_div3:
|
|
|
|
|
if (treg == 0)
|
|
|
|
|
{
|
|
|
|
|
as_warn (_("Divide by zero."));
|
|
|
|
|
if (mips_trap)
|
2003-06-30 14:44:25 +02:00
|
|
|
|
macro_build (NULL, &icnt, NULL, "teq", "s,t,q", 0, 0, 7);
|
1999-05-03 09:29:11 +02:00
|
|
|
|
else
|
2003-06-30 14:44:25 +02:00
|
|
|
|
macro_build (NULL, &icnt, NULL, "break", "c", 7);
|
1999-05-03 09:29:11 +02:00
|
|
|
|
return;
|
|
|
|
|
}
|
|
|
|
|
|
2002-11-30 09:39:46 +01:00
|
|
|
|
mips_emit_delays (TRUE);
|
1999-05-03 09:29:11 +02:00
|
|
|
|
++mips_opts.noreorder;
|
|
|
|
|
mips_any_noreorder = 1;
|
|
|
|
|
if (mips_trap)
|
|
|
|
|
{
|
2003-06-30 14:44:25 +02:00
|
|
|
|
macro_build (NULL, &icnt, NULL, "teq", "s,t,q", treg, 0, 7);
|
|
|
|
|
macro_build (NULL, &icnt, NULL, dbl ? "ddiv" : "div", "z,s,t",
|
|
|
|
|
sreg, treg);
|
1999-05-03 09:29:11 +02:00
|
|
|
|
}
|
|
|
|
|
else
|
|
|
|
|
{
|
|
|
|
|
expr1.X_add_number = 8;
|
2003-06-30 14:44:25 +02:00
|
|
|
|
macro_build (NULL, &icnt, &expr1, "bne", "s,t,p", treg, 0);
|
|
|
|
|
macro_build (NULL, &icnt, NULL, dbl ? "ddiv" : "div", "z,s,t",
|
|
|
|
|
sreg, treg);
|
2003-11-15 16:57:14 +01:00
|
|
|
|
macro_build (NULL, &icnt, NULL, "break", "c", 7);
|
1999-05-03 09:29:11 +02:00
|
|
|
|
}
|
|
|
|
|
expr1.X_add_number = -1;
|
2003-06-30 14:44:25 +02:00
|
|
|
|
macro_build (NULL, &icnt, &expr1, dbl ? "daddiu" : "addiu", "t,r,j",
|
|
|
|
|
AT, 0, BFD_RELOC_LO16);
|
1999-05-03 09:29:11 +02:00
|
|
|
|
expr1.X_add_number = mips_trap ? (dbl ? 12 : 8) : (dbl ? 20 : 16);
|
2003-06-30 14:44:25 +02:00
|
|
|
|
macro_build (NULL, &icnt, &expr1, "bne", "s,t,p", treg, AT);
|
1999-05-03 09:29:11 +02:00
|
|
|
|
if (dbl)
|
|
|
|
|
{
|
|
|
|
|
expr1.X_add_number = 1;
|
2003-06-30 14:44:25 +02:00
|
|
|
|
macro_build (NULL, &icnt, &expr1, "daddiu", "t,r,j", AT, 0,
|
|
|
|
|
BFD_RELOC_LO16);
|
|
|
|
|
macro_build (NULL, &icnt, NULL, "dsll32", "d,w,<", AT, AT, 31);
|
1999-05-03 09:29:11 +02:00
|
|
|
|
}
|
|
|
|
|
else
|
|
|
|
|
{
|
|
|
|
|
expr1.X_add_number = 0x80000000;
|
2003-06-30 14:44:25 +02:00
|
|
|
|
macro_build (NULL, &icnt, &expr1, "lui", "t,u", AT,
|
|
|
|
|
BFD_RELOC_HI16);
|
1999-05-03 09:29:11 +02:00
|
|
|
|
}
|
|
|
|
|
if (mips_trap)
|
|
|
|
|
{
|
2003-06-30 14:44:25 +02:00
|
|
|
|
macro_build (NULL, &icnt, NULL, "teq", "s,t,q", sreg, AT, 6);
|
1999-05-03 09:29:11 +02:00
|
|
|
|
/* We want to close the noreorder block as soon as possible, so
|
|
|
|
|
that later insns are available for delay slot filling. */
|
|
|
|
|
--mips_opts.noreorder;
|
|
|
|
|
}
|
|
|
|
|
else
|
|
|
|
|
{
|
|
|
|
|
expr1.X_add_number = 8;
|
2003-06-30 14:44:25 +02:00
|
|
|
|
macro_build (NULL, &icnt, &expr1, "bne", "s,t,p", sreg, AT);
|
|
|
|
|
macro_build (NULL, &icnt, NULL, "nop", "", 0);
|
1999-05-03 09:29:11 +02:00
|
|
|
|
|
|
|
|
|
/* We want to close the noreorder block as soon as possible, so
|
|
|
|
|
that later insns are available for delay slot filling. */
|
|
|
|
|
--mips_opts.noreorder;
|
|
|
|
|
|
2003-06-30 14:44:25 +02:00
|
|
|
|
macro_build (NULL, &icnt, NULL, "break", "c", 6);
|
1999-05-03 09:29:11 +02:00
|
|
|
|
}
|
2003-06-30 14:44:25 +02:00
|
|
|
|
macro_build (NULL, &icnt, NULL, s, "d", dreg);
|
1999-05-03 09:29:11 +02:00
|
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
case M_DIV_3I:
|
|
|
|
|
s = "div";
|
|
|
|
|
s2 = "mflo";
|
|
|
|
|
goto do_divi;
|
|
|
|
|
case M_DIVU_3I:
|
|
|
|
|
s = "divu";
|
|
|
|
|
s2 = "mflo";
|
|
|
|
|
goto do_divi;
|
|
|
|
|
case M_REM_3I:
|
|
|
|
|
s = "div";
|
|
|
|
|
s2 = "mfhi";
|
|
|
|
|
goto do_divi;
|
|
|
|
|
case M_REMU_3I:
|
|
|
|
|
s = "divu";
|
|
|
|
|
s2 = "mfhi";
|
|
|
|
|
goto do_divi;
|
|
|
|
|
case M_DDIV_3I:
|
|
|
|
|
dbl = 1;
|
|
|
|
|
s = "ddiv";
|
|
|
|
|
s2 = "mflo";
|
|
|
|
|
goto do_divi;
|
|
|
|
|
case M_DDIVU_3I:
|
|
|
|
|
dbl = 1;
|
|
|
|
|
s = "ddivu";
|
|
|
|
|
s2 = "mflo";
|
|
|
|
|
goto do_divi;
|
|
|
|
|
case M_DREM_3I:
|
|
|
|
|
dbl = 1;
|
|
|
|
|
s = "ddiv";
|
|
|
|
|
s2 = "mfhi";
|
|
|
|
|
goto do_divi;
|
|
|
|
|
case M_DREMU_3I:
|
|
|
|
|
dbl = 1;
|
|
|
|
|
s = "ddivu";
|
|
|
|
|
s2 = "mfhi";
|
|
|
|
|
do_divi:
|
|
|
|
|
if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
|
|
|
|
|
{
|
|
|
|
|
as_warn (_("Divide by zero."));
|
|
|
|
|
if (mips_trap)
|
2003-06-30 14:44:25 +02:00
|
|
|
|
macro_build (NULL, &icnt, NULL, "teq", "s,t,q", 0, 0, 7);
|
1999-05-03 09:29:11 +02:00
|
|
|
|
else
|
2003-06-30 14:44:25 +02:00
|
|
|
|
macro_build (NULL, &icnt, NULL, "break", "c", 7);
|
1999-05-03 09:29:11 +02:00
|
|
|
|
return;
|
|
|
|
|
}
|
|
|
|
|
if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1)
|
|
|
|
|
{
|
|
|
|
|
if (strcmp (s2, "mflo") == 0)
|
2001-08-10 18:24:32 +02:00
|
|
|
|
move_register (&icnt, dreg, sreg);
|
1999-05-03 09:29:11 +02:00
|
|
|
|
else
|
2001-08-10 18:24:32 +02:00
|
|
|
|
move_register (&icnt, dreg, 0);
|
1999-05-03 09:29:11 +02:00
|
|
|
|
return;
|
|
|
|
|
}
|
|
|
|
|
if (imm_expr.X_op == O_constant
|
|
|
|
|
&& imm_expr.X_add_number == -1
|
|
|
|
|
&& s[strlen (s) - 1] != 'u')
|
|
|
|
|
{
|
|
|
|
|
if (strcmp (s2, "mflo") == 0)
|
|
|
|
|
{
|
2003-06-30 14:44:25 +02:00
|
|
|
|
macro_build (NULL, &icnt, NULL, dbl ? "dneg" : "neg", "d,w",
|
|
|
|
|
dreg, sreg);
|
1999-05-03 09:29:11 +02:00
|
|
|
|
}
|
|
|
|
|
else
|
2001-08-10 18:24:32 +02:00
|
|
|
|
move_register (&icnt, dreg, 0);
|
1999-05-03 09:29:11 +02:00
|
|
|
|
return;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
load_register (&icnt, AT, &imm_expr, dbl);
|
2003-06-30 14:44:25 +02:00
|
|
|
|
macro_build (NULL, &icnt, NULL, s, "z,s,t", sreg, AT);
|
|
|
|
|
macro_build (NULL, &icnt, NULL, s2, "d", dreg);
|
1999-05-03 09:29:11 +02:00
|
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
case M_DIVU_3:
|
|
|
|
|
s = "divu";
|
|
|
|
|
s2 = "mflo";
|
|
|
|
|
goto do_divu3;
|
|
|
|
|
case M_REMU_3:
|
|
|
|
|
s = "divu";
|
|
|
|
|
s2 = "mfhi";
|
|
|
|
|
goto do_divu3;
|
|
|
|
|
case M_DDIVU_3:
|
|
|
|
|
s = "ddivu";
|
|
|
|
|
s2 = "mflo";
|
|
|
|
|
goto do_divu3;
|
|
|
|
|
case M_DREMU_3:
|
|
|
|
|
s = "ddivu";
|
|
|
|
|
s2 = "mfhi";
|
|
|
|
|
do_divu3:
|
2002-11-30 09:39:46 +01:00
|
|
|
|
mips_emit_delays (TRUE);
|
1999-05-03 09:29:11 +02:00
|
|
|
|
++mips_opts.noreorder;
|
|
|
|
|
mips_any_noreorder = 1;
|
|
|
|
|
if (mips_trap)
|
|
|
|
|
{
|
2003-06-30 14:44:25 +02:00
|
|
|
|
macro_build (NULL, &icnt, NULL, "teq", "s,t,q", treg, 0, 7);
|
|
|
|
|
macro_build (NULL, &icnt, NULL, s, "z,s,t", sreg, treg);
|
1999-05-03 09:29:11 +02:00
|
|
|
|
/* We want to close the noreorder block as soon as possible, so
|
|
|
|
|
that later insns are available for delay slot filling. */
|
|
|
|
|
--mips_opts.noreorder;
|
|
|
|
|
}
|
|
|
|
|
else
|
|
|
|
|
{
|
|
|
|
|
expr1.X_add_number = 8;
|
2003-06-30 14:44:25 +02:00
|
|
|
|
macro_build (NULL, &icnt, &expr1, "bne", "s,t,p", treg, 0);
|
|
|
|
|
macro_build (NULL, &icnt, NULL, s, "z,s,t", sreg, treg);
|
1999-05-03 09:29:11 +02:00
|
|
|
|
|
|
|
|
|
/* We want to close the noreorder block as soon as possible, so
|
|
|
|
|
that later insns are available for delay slot filling. */
|
|
|
|
|
--mips_opts.noreorder;
|
2003-06-30 14:44:25 +02:00
|
|
|
|
macro_build (NULL, &icnt, NULL, "break", "c", 7);
|
1999-05-03 09:29:11 +02:00
|
|
|
|
}
|
2003-06-30 14:44:25 +02:00
|
|
|
|
macro_build (NULL, &icnt, NULL, s2, "d", dreg);
|
1999-05-03 09:29:11 +02:00
|
|
|
|
return;
|
|
|
|
|
|
2003-11-18 22:22:57 +01:00
|
|
|
|
case M_DLCA_AB:
|
|
|
|
|
dbl = 1;
|
|
|
|
|
case M_LCA_AB:
|
|
|
|
|
call = 1;
|
|
|
|
|
goto do_la;
|
1999-05-03 09:29:11 +02:00
|
|
|
|
case M_DLA_AB:
|
|
|
|
|
dbl = 1;
|
|
|
|
|
case M_LA_AB:
|
2003-11-18 22:22:57 +01:00
|
|
|
|
do_la:
|
1999-05-03 09:29:11 +02:00
|
|
|
|
/* Load the address of a symbol into a register. If breg is not
|
|
|
|
|
zero, we then add a base register to it. */
|
|
|
|
|
|
2002-05-15 01:35:59 +02:00
|
|
|
|
if (dbl && HAVE_32BIT_GPRS)
|
|
|
|
|
as_warn (_("dla used to load 32-bit register"));
|
|
|
|
|
|
2002-05-22 02:13:13 +02:00
|
|
|
|
if (! dbl && HAVE_64BIT_OBJECTS)
|
2002-05-15 01:35:59 +02:00
|
|
|
|
as_warn (_("la used to load 64-bit address"));
|
|
|
|
|
|
2002-08-09 13:07:24 +02:00
|
|
|
|
if (offset_expr.X_op == O_constant
|
|
|
|
|
&& offset_expr.X_add_number >= -0x8000
|
|
|
|
|
&& offset_expr.X_add_number < 0x8000)
|
|
|
|
|
{
|
2003-06-30 14:44:25 +02:00
|
|
|
|
macro_build (NULL, &icnt, &offset_expr,
|
2003-06-21 23:38:04 +02:00
|
|
|
|
(dbl || HAVE_64BIT_ADDRESSES) ? "daddiu" : "addiu",
|
2003-06-30 14:44:25 +02:00
|
|
|
|
"t,r,j", treg, sreg, BFD_RELOC_LO16);
|
2002-08-09 13:07:24 +02:00
|
|
|
|
return;
|
|
|
|
|
}
|
|
|
|
|
|
2001-11-01 02:33:47 +01:00
|
|
|
|
if (treg == breg)
|
|
|
|
|
{
|
|
|
|
|
tempreg = AT;
|
|
|
|
|
used_at = 1;
|
|
|
|
|
}
|
|
|
|
|
else
|
|
|
|
|
{
|
|
|
|
|
tempreg = treg;
|
|
|
|
|
used_at = 0;
|
|
|
|
|
}
|
|
|
|
|
|
1999-05-03 09:29:11 +02:00
|
|
|
|
/* When generating embedded PIC code, we permit expressions of
|
|
|
|
|
the form
|
2001-11-01 02:33:47 +01:00
|
|
|
|
la $treg,foo-bar
|
|
|
|
|
la $treg,foo-bar($breg)
|
2000-03-11 03:16:25 +01:00
|
|
|
|
where bar is an address in the current section. These are used
|
1999-05-03 09:29:11 +02:00
|
|
|
|
when getting the addresses of functions. We don't permit
|
|
|
|
|
X_add_number to be non-zero, because if the symbol is
|
|
|
|
|
external the relaxing code needs to know that any addend is
|
|
|
|
|
purely the offset to X_op_symbol. */
|
|
|
|
|
if (mips_pic == EMBEDDED_PIC
|
|
|
|
|
&& offset_expr.X_op == O_subtract
|
Add support for storing local symbols in a small structure to save
memory when assembling large files.
* as.h: Don't include struc-symbol.h.
(symbolS): Add typedef.
* symbols.c: Include struc-symbol.h.
(local_hash): New static variable.
(save_symbol_name): New static function, from symbol_create.
(symbol_create): Call save_symbol_name.
(local_symbol_count): New static variable.
(local_symbol_conversion_count): Likewise.
(LOCAL_SYMBOL_CHECK): Define.
(local_symbol_make): New static function.
(local_symbol_convert): New static function.
(colon): Handle local symbols. Create local symbol for local
label name.
(symbol_table_insert): Handle local symbols.
(symbol_find_or_make): Create local symbol for local label name.
(symbol_find_base): Check for local symbol.
(symbol_append, symbol_insert): Check for local symbols.
(symbol_clear_list_pointers, symbol_remove): Likewise.
(verify_symbol_chain): Likewise.
(copy_symbol_attributes): Likewise.
(resolve_symbol_value): Handle local symbols.
(resolve_local_symbol): New static function.
(resolve_local_symbol_values): New function.
(S_GET_VALUE, S_SET_VALUE): Handle local symbols.
(S_IS_FUNCTION, S_IS_EXTERNAL, S_IS_WEAK, S_IS_COMMON): Likewise.
(S_IS_DEFINED, S_IS_DEBUG, S_IS_LOCAL, S_GET_NAME): Likewise.
(S_GET_SEGMENT, S_SET_SEGMENT, S_SET_EXTERNAL): Likewise.
(S_CLEAR_EXTERNAL, S_SET_WEAK, S_SET_NAME): Likewise.
(symbol_previous, symbol_next): New functions.
(symbol_get_value_expression): Likewise.
(symbol_set_value_expression): Likewise.
(symbol_set_frag, symbol_get_frag): Likewise.
(symbol_mark_used, symbol_clear_used, symbol_used_p): Likewise.
(symbol_mark_used_in_reloc): Likewise.
(symbol_clear_used_in_reloc, symbol_used_in_reloc_p): Likewise.
(symbol_mark_mri_common, symbol_clear_mri_common): Likewise.
(symbol_mri_common_p): Likewise.
(symbol_mark_written, symbol_clear_written): Likewise.
(symbol_written_p): Likewise.
(symbol_mark_resolved, symbol_resolved_p): Likewise.
(symbol_section_p, symbol_equated_p): Likewise.
(symbol_constant_p): Likewise.
(symbol_get_bfdsym, symbol_set_bfdsym): Likewise.
(symbol_get_obj, symbol_set_obj): Likewise.
(symbol_get_tc, symbol_set_tc): Likewise.
(symbol_begin): Initialize local_hash.
(print_symbol_value_1): Handle local symbols.
(symbol_print_statistics): Print local symbol statistics.
* symbols.h: Include "struc-symbol.h" if not BFD_ASSEMBLER.
Declare new symbols.c functions. Move many declarations here from
struc-symbol.h.
(SYMBOLS_NEED_BACKPOINTERS): Define if needed.
* struc-symbol.h (SYMBOLS_NEED_BACKPOINTERS): Don't set.
(struct symbol): Move bsym to make it clearly the first field.
Remove TARGET_SYMBOL_FIELDS.
(symbolS): Don't typedef.
(struct broken_word): Remove.
(N_TYPE_seg, seg_N_TYPE): Move to symbol.h.
(SEGMENT_TO_SYMBOL_TYPE, N_REGISTER): Likewise.
(symbol_clear_list_pointers): Likewise.
(symbol_insert, symbol_remove): Likewise.
(symbol_previous, symbol_append): Likewise.
(verify_symbol_chain, verify_symbol_chain_2): Likewise.
(struct local_symbol): Define.
(local_symbol_converted_p, local_symbol_mark_converted): Define.
(local_symbol_resolved_p, local_symbol_mark_resolved): Define.
(local_symbol_get_frag, local_symbol_set_frag): Define.
(local_symbol_get_real_symbol): Define.
(local_symbol_set_real_symbol): Define.
Define.
* write.c (write_object_file): Call resolve_local_symbol_values.
* config/obj-ecoff.h (OBJ_SYMFIELD_TYPE): Define.
(TARGET_SYMBOL_FIELDS): Don't define.
* config/obj-elf.h (OBJ_SYMFIELD_TYPE): Add local field. If
ECOFF_DEBUGGING, add ECOFF fields.
(ELF_TARGET_SYMBOL_FIELDS, TARGET_SYMBOL_FIELDS): Don't define.
* config/obj-multi.h (struct elf_obj_sy): Add local field. If
ECOFF_DEBUGGING, add ECOFF fields.
(ELF_TARGET_SYMBOL_FIELDS, TARGET_SYMBOL_FIELDS): Don't define.
(ECOFF_DEBUG_TARGET_SYMBOL_FIELDS): Don't define.
* config/tc-mcore.h: Don't include struc-symbol.h.
(TARGET_SYMBOL_FIELDS): Don't define.
(struct mcore_tc_sy): Define.
(TC_SYMFIELD_TYPE): Define.
* Many files: Use symbolS instead of struct symbol. Use new
accessor functions rather than referring to symbolS fields
directly.
* read.c (s_mri_common): Don't add in value of line_label.
* config/tc-mips.c (md_apply_fix): Correct parenthesization when
checking for SEC_LINK_ONCE.
* config/tc-sh.h (sh_fix_adjustable): Declare.
1999-06-03 02:29:48 +02:00
|
|
|
|
&& (symbol_constant_p (offset_expr.X_op_symbol)
|
2000-03-11 03:16:25 +01:00
|
|
|
|
? S_GET_SEGMENT (offset_expr.X_op_symbol) == now_seg
|
Add support for storing local symbols in a small structure to save
memory when assembling large files.
* as.h: Don't include struc-symbol.h.
(symbolS): Add typedef.
* symbols.c: Include struc-symbol.h.
(local_hash): New static variable.
(save_symbol_name): New static function, from symbol_create.
(symbol_create): Call save_symbol_name.
(local_symbol_count): New static variable.
(local_symbol_conversion_count): Likewise.
(LOCAL_SYMBOL_CHECK): Define.
(local_symbol_make): New static function.
(local_symbol_convert): New static function.
(colon): Handle local symbols. Create local symbol for local
label name.
(symbol_table_insert): Handle local symbols.
(symbol_find_or_make): Create local symbol for local label name.
(symbol_find_base): Check for local symbol.
(symbol_append, symbol_insert): Check for local symbols.
(symbol_clear_list_pointers, symbol_remove): Likewise.
(verify_symbol_chain): Likewise.
(copy_symbol_attributes): Likewise.
(resolve_symbol_value): Handle local symbols.
(resolve_local_symbol): New static function.
(resolve_local_symbol_values): New function.
(S_GET_VALUE, S_SET_VALUE): Handle local symbols.
(S_IS_FUNCTION, S_IS_EXTERNAL, S_IS_WEAK, S_IS_COMMON): Likewise.
(S_IS_DEFINED, S_IS_DEBUG, S_IS_LOCAL, S_GET_NAME): Likewise.
(S_GET_SEGMENT, S_SET_SEGMENT, S_SET_EXTERNAL): Likewise.
(S_CLEAR_EXTERNAL, S_SET_WEAK, S_SET_NAME): Likewise.
(symbol_previous, symbol_next): New functions.
(symbol_get_value_expression): Likewise.
(symbol_set_value_expression): Likewise.
(symbol_set_frag, symbol_get_frag): Likewise.
(symbol_mark_used, symbol_clear_used, symbol_used_p): Likewise.
(symbol_mark_used_in_reloc): Likewise.
(symbol_clear_used_in_reloc, symbol_used_in_reloc_p): Likewise.
(symbol_mark_mri_common, symbol_clear_mri_common): Likewise.
(symbol_mri_common_p): Likewise.
(symbol_mark_written, symbol_clear_written): Likewise.
(symbol_written_p): Likewise.
(symbol_mark_resolved, symbol_resolved_p): Likewise.
(symbol_section_p, symbol_equated_p): Likewise.
(symbol_constant_p): Likewise.
(symbol_get_bfdsym, symbol_set_bfdsym): Likewise.
(symbol_get_obj, symbol_set_obj): Likewise.
(symbol_get_tc, symbol_set_tc): Likewise.
(symbol_begin): Initialize local_hash.
(print_symbol_value_1): Handle local symbols.
(symbol_print_statistics): Print local symbol statistics.
* symbols.h: Include "struc-symbol.h" if not BFD_ASSEMBLER.
Declare new symbols.c functions. Move many declarations here from
struc-symbol.h.
(SYMBOLS_NEED_BACKPOINTERS): Define if needed.
* struc-symbol.h (SYMBOLS_NEED_BACKPOINTERS): Don't set.
(struct symbol): Move bsym to make it clearly the first field.
Remove TARGET_SYMBOL_FIELDS.
(symbolS): Don't typedef.
(struct broken_word): Remove.
(N_TYPE_seg, seg_N_TYPE): Move to symbol.h.
(SEGMENT_TO_SYMBOL_TYPE, N_REGISTER): Likewise.
(symbol_clear_list_pointers): Likewise.
(symbol_insert, symbol_remove): Likewise.
(symbol_previous, symbol_append): Likewise.
(verify_symbol_chain, verify_symbol_chain_2): Likewise.
(struct local_symbol): Define.
(local_symbol_converted_p, local_symbol_mark_converted): Define.
(local_symbol_resolved_p, local_symbol_mark_resolved): Define.
(local_symbol_get_frag, local_symbol_set_frag): Define.
(local_symbol_get_real_symbol): Define.
(local_symbol_set_real_symbol): Define.
Define.
* write.c (write_object_file): Call resolve_local_symbol_values.
* config/obj-ecoff.h (OBJ_SYMFIELD_TYPE): Define.
(TARGET_SYMBOL_FIELDS): Don't define.
* config/obj-elf.h (OBJ_SYMFIELD_TYPE): Add local field. If
ECOFF_DEBUGGING, add ECOFF fields.
(ELF_TARGET_SYMBOL_FIELDS, TARGET_SYMBOL_FIELDS): Don't define.
* config/obj-multi.h (struct elf_obj_sy): Add local field. If
ECOFF_DEBUGGING, add ECOFF fields.
(ELF_TARGET_SYMBOL_FIELDS, TARGET_SYMBOL_FIELDS): Don't define.
(ECOFF_DEBUG_TARGET_SYMBOL_FIELDS): Don't define.
* config/tc-mcore.h: Don't include struc-symbol.h.
(TARGET_SYMBOL_FIELDS): Don't define.
(struct mcore_tc_sy): Define.
(TC_SYMFIELD_TYPE): Define.
* Many files: Use symbolS instead of struct symbol. Use new
accessor functions rather than referring to symbolS fields
directly.
* read.c (s_mri_common): Don't add in value of line_label.
* config/tc-mips.c (md_apply_fix): Correct parenthesization when
checking for SEC_LINK_ONCE.
* config/tc-sh.h (sh_fix_adjustable): Declare.
1999-06-03 02:29:48 +02:00
|
|
|
|
: (symbol_equated_p (offset_expr.X_op_symbol)
|
|
|
|
|
&& (S_GET_SEGMENT
|
|
|
|
|
(symbol_get_value_expression (offset_expr.X_op_symbol)
|
|
|
|
|
->X_add_symbol)
|
2000-03-11 03:16:25 +01:00
|
|
|
|
== now_seg)))
|
|
|
|
|
&& (offset_expr.X_add_number == 0
|
|
|
|
|
|| OUTPUT_FLAVOR == bfd_target_elf_flavour))
|
1999-05-03 09:29:11 +02:00
|
|
|
|
{
|
2001-11-01 02:33:47 +01:00
|
|
|
|
if (breg == 0)
|
|
|
|
|
{
|
|
|
|
|
tempreg = treg;
|
|
|
|
|
used_at = 0;
|
2003-06-30 14:44:25 +02:00
|
|
|
|
macro_build (NULL, &icnt, &offset_expr, "lui", "t,u", tempreg,
|
|
|
|
|
BFD_RELOC_PCREL_HI16_S);
|
2001-11-01 02:33:47 +01:00
|
|
|
|
}
|
|
|
|
|
else
|
|
|
|
|
{
|
2003-06-30 14:44:25 +02:00
|
|
|
|
macro_build (NULL, &icnt, &offset_expr, "lui", "t,u", tempreg,
|
|
|
|
|
BFD_RELOC_PCREL_HI16_S);
|
|
|
|
|
macro_build (NULL, &icnt, NULL,
|
2002-02-25 14:21:38 +01:00
|
|
|
|
(dbl || HAVE_64BIT_ADDRESSES) ? "daddu" : "addu",
|
2001-11-01 02:33:47 +01:00
|
|
|
|
"d,v,t", tempreg, tempreg, breg);
|
|
|
|
|
}
|
2003-06-30 14:44:25 +02:00
|
|
|
|
macro_build (NULL, &icnt, &offset_expr,
|
2002-02-25 14:21:38 +01:00
|
|
|
|
(dbl || HAVE_64BIT_ADDRESSES) ? "daddiu" : "addiu",
|
2003-06-30 14:44:25 +02:00
|
|
|
|
"t,r,j", treg, tempreg, BFD_RELOC_PCREL_LO16);
|
2001-11-01 02:33:47 +01:00
|
|
|
|
if (! used_at)
|
|
|
|
|
return;
|
|
|
|
|
break;
|
1999-05-03 09:29:11 +02:00
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
if (offset_expr.X_op != O_symbol
|
|
|
|
|
&& offset_expr.X_op != O_constant)
|
|
|
|
|
{
|
|
|
|
|
as_bad (_("expression too complex"));
|
|
|
|
|
offset_expr.X_op = O_constant;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
if (offset_expr.X_op == O_constant)
|
2002-02-25 14:21:38 +01:00
|
|
|
|
load_register (&icnt, tempreg, &offset_expr,
|
|
|
|
|
((mips_pic == EMBEDDED_PIC || mips_pic == NO_PIC)
|
|
|
|
|
? (dbl || HAVE_64BIT_ADDRESSES)
|
|
|
|
|
: HAVE_64BIT_ADDRESSES));
|
1999-05-03 09:29:11 +02:00
|
|
|
|
else if (mips_pic == NO_PIC)
|
|
|
|
|
{
|
2001-10-10 02:43:36 +02:00
|
|
|
|
/* If this is a reference to a GP relative symbol, we want
|
2001-12-02 14:14:48 +01:00
|
|
|
|
addiu $tempreg,$gp,<sym> (BFD_RELOC_GPREL16)
|
1999-05-03 09:29:11 +02:00
|
|
|
|
Otherwise we want
|
|
|
|
|
lui $tempreg,<sym> (BFD_RELOC_HI16_S)
|
|
|
|
|
addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
|
|
|
|
|
If we have a constant, we need two instructions anyhow,
|
2001-10-10 02:43:36 +02:00
|
|
|
|
so we may as well always use the latter form.
|
2001-11-06 22:39:09 +01:00
|
|
|
|
|
2001-10-10 02:43:36 +02:00
|
|
|
|
With 64bit address space and a usable $at we want
|
|
|
|
|
lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
|
|
|
|
|
lui $at,<sym> (BFD_RELOC_HI16_S)
|
|
|
|
|
daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
|
|
|
|
|
daddiu $at,<sym> (BFD_RELOC_LO16)
|
|
|
|
|
dsll32 $tempreg,0
|
2002-07-09 00:42:09 +02:00
|
|
|
|
daddu $tempreg,$tempreg,$at
|
2001-11-06 22:39:09 +01:00
|
|
|
|
|
2002-12-17 02:13:56 +01:00
|
|
|
|
If $at is already in use, we use a path which is suboptimal
|
2001-10-10 02:43:36 +02:00
|
|
|
|
on superscalar processors.
|
|
|
|
|
lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
|
|
|
|
|
daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
|
|
|
|
|
dsll $tempreg,16
|
|
|
|
|
daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
|
|
|
|
|
dsll $tempreg,16
|
|
|
|
|
daddiu $tempreg,<sym> (BFD_RELOC_LO16)
|
|
|
|
|
*/
|
2002-05-26 20:46:37 +02:00
|
|
|
|
char *p = NULL;
|
2001-10-10 02:43:36 +02:00
|
|
|
|
if (HAVE_64BIT_ADDRESSES)
|
1999-05-03 09:29:11 +02:00
|
|
|
|
{
|
2001-10-10 02:43:36 +02:00
|
|
|
|
/* We don't do GP optimization for now because RELAX_ENCODE can't
|
|
|
|
|
hold the data for such large chunks. */
|
|
|
|
|
|
2002-07-30 21:27:31 +02:00
|
|
|
|
if (used_at == 0 && ! mips_opts.noat)
|
2002-05-04 19:38:00 +02:00
|
|
|
|
{
|
|
|
|
|
macro_build (p, &icnt, &offset_expr, "lui", "t,u",
|
2003-06-30 14:44:25 +02:00
|
|
|
|
tempreg, BFD_RELOC_MIPS_HIGHEST);
|
2002-05-04 19:38:00 +02:00
|
|
|
|
macro_build (p, &icnt, &offset_expr, "lui", "t,u",
|
2003-06-30 14:44:25 +02:00
|
|
|
|
AT, BFD_RELOC_HI16_S);
|
2002-05-04 19:38:00 +02:00
|
|
|
|
macro_build (p, &icnt, &offset_expr, "daddiu", "t,r,j",
|
2003-06-30 14:44:25 +02:00
|
|
|
|
tempreg, tempreg, BFD_RELOC_MIPS_HIGHER);
|
2002-05-04 19:38:00 +02:00
|
|
|
|
macro_build (p, &icnt, &offset_expr, "daddiu", "t,r,j",
|
2003-06-30 14:44:25 +02:00
|
|
|
|
AT, AT, BFD_RELOC_LO16);
|
|
|
|
|
macro_build (p, &icnt, NULL, "dsll32", "d,w,<",
|
|
|
|
|
tempreg, tempreg, 0);
|
|
|
|
|
macro_build (p, &icnt, NULL, "daddu", "d,v,t",
|
|
|
|
|
tempreg, tempreg, AT);
|
2002-05-04 19:38:00 +02:00
|
|
|
|
used_at = 1;
|
|
|
|
|
}
|
|
|
|
|
else
|
|
|
|
|
{
|
|
|
|
|
macro_build (p, &icnt, &offset_expr, "lui", "t,u",
|
2003-06-30 14:44:25 +02:00
|
|
|
|
tempreg, BFD_RELOC_MIPS_HIGHEST);
|
2002-05-04 19:38:00 +02:00
|
|
|
|
macro_build (p, &icnt, &offset_expr, "daddiu", "t,r,j",
|
2003-06-30 14:44:25 +02:00
|
|
|
|
tempreg, tempreg, BFD_RELOC_MIPS_HIGHER);
|
|
|
|
|
macro_build (p, &icnt, NULL, "dsll", "d,w,<",
|
2002-05-04 19:38:00 +02:00
|
|
|
|
tempreg, tempreg, 16);
|
|
|
|
|
macro_build (p, &icnt, &offset_expr, "daddiu", "t,r,j",
|
2003-06-30 14:44:25 +02:00
|
|
|
|
tempreg, tempreg, BFD_RELOC_HI16_S);
|
|
|
|
|
macro_build (p, &icnt, NULL, "dsll", "d,w,<",
|
2002-05-04 19:38:00 +02:00
|
|
|
|
tempreg, tempreg, 16);
|
|
|
|
|
macro_build (p, &icnt, &offset_expr, "daddiu", "t,r,j",
|
2003-06-30 14:44:25 +02:00
|
|
|
|
tempreg, tempreg, BFD_RELOC_LO16);
|
2002-05-04 19:38:00 +02:00
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
else
|
|
|
|
|
{
|
|
|
|
|
if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET
|
|
|
|
|
&& ! nopic_need_relax (offset_expr.X_add_symbol, 1))
|
|
|
|
|
{
|
|
|
|
|
frag_grow (20);
|
2003-06-30 14:44:25 +02:00
|
|
|
|
macro_build (NULL, &icnt, &offset_expr, ADDRESS_ADDI_INSN,
|
|
|
|
|
"t,r,j", tempreg, mips_gp_register,
|
|
|
|
|
BFD_RELOC_GPREL16);
|
2002-05-04 19:38:00 +02:00
|
|
|
|
p = frag_var (rs_machine_dependent, 8, 0,
|
|
|
|
|
RELAX_ENCODE (4, 8, 0, 4, 0,
|
|
|
|
|
mips_opts.warn_about_macros),
|
|
|
|
|
offset_expr.X_add_symbol, 0, NULL);
|
|
|
|
|
}
|
|
|
|
|
macro_build_lui (p, &icnt, &offset_expr, tempreg);
|
|
|
|
|
if (p != NULL)
|
|
|
|
|
p += 4;
|
2003-06-16 14:13:10 +02:00
|
|
|
|
macro_build (p, &icnt, &offset_expr, ADDRESS_ADDI_INSN,
|
2003-06-30 14:44:25 +02:00
|
|
|
|
"t,r,j", tempreg, tempreg, BFD_RELOC_LO16);
|
2002-05-04 19:38:00 +02:00
|
|
|
|
}
|
1999-05-03 09:29:11 +02:00
|
|
|
|
}
|
* config/tc-mips.h (tc_frag_data_type, TC_FRAG_TYPE): New.
* config/tc-mips.c: Use signed add for n32 address arithmetic.
(append_insn): When filling delay slots with instructions
that have fixups that tc_gen_reloc might consider modifyable
in variant frags, start a new frag.
(load_address): Generate GOT_DISP with of without offset
depending on whether symbol is local. For -xgot, use
GOT_PAGE/GOT_OFST or GOT_HI16/GOT_LO16.
(macro) <M_DLA_AB, M_LA_AB>: Likewise.
<M_JAL_A>: In NewABI, use CALL16 or GOT_DISP for small got,
CALL_HI16/CALL_LO16 or GOT_PAGE/GOT_OFST for big got.
<ld_st>: In NewABI with small got, always use
GOT_PAGE/GOT_OFST, with the latter in the load/store
instruction. With big got, use GOT_HI16/GOT_LO16 or
GOT_PAGE/GOT_OFST.
(tc_gen_reloc): Adjust variant frags with GOT_DISP in NewABI.
Add tc_frag_data.tc_fr_offset to addends. Decay CALL16,
GOT_OFST and GOT_DISP to GOT_DISP in NewABI.
(md_convert_frag): Use memmove for safe copying of overlapping
regions.
2003-04-11 03:56:50 +02:00
|
|
|
|
else if (mips_pic == SVR4_PIC && ! mips_big_got && ! HAVE_NEWABI)
|
1999-05-03 09:29:11 +02:00
|
|
|
|
{
|
2001-02-12 00:11:41 +01:00
|
|
|
|
int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT16;
|
|
|
|
|
|
1999-05-03 09:29:11 +02:00
|
|
|
|
/* If this is a reference to an external symbol, and there
|
|
|
|
|
is no constant, we want
|
|
|
|
|
lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
|
2003-11-18 22:22:57 +01:00
|
|
|
|
or for lca or if tempreg is PIC_CALL_REG
|
2001-02-12 00:11:41 +01:00
|
|
|
|
lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
|
1999-05-03 09:29:11 +02:00
|
|
|
|
For a local symbol, we want
|
|
|
|
|
lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
|
|
|
|
|
nop
|
|
|
|
|
addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
|
|
|
|
|
|
|
|
|
|
If we have a small constant, and this is a reference to
|
|
|
|
|
an external symbol, we want
|
|
|
|
|
lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
|
|
|
|
|
nop
|
|
|
|
|
addiu $tempreg,$tempreg,<constant>
|
|
|
|
|
For a local symbol, we want the same instruction
|
|
|
|
|
sequence, but we output a BFD_RELOC_LO16 reloc on the
|
|
|
|
|
addiu instruction.
|
|
|
|
|
|
|
|
|
|
If we have a large constant, and this is a reference to
|
|
|
|
|
an external symbol, we want
|
|
|
|
|
lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
|
|
|
|
|
lui $at,<hiconstant>
|
|
|
|
|
addiu $at,$at,<loconstant>
|
|
|
|
|
addu $tempreg,$tempreg,$at
|
|
|
|
|
For a local symbol, we want the same instruction
|
|
|
|
|
sequence, but we output a BFD_RELOC_LO16 reloc on the
|
2002-09-18 04:25:19 +02:00
|
|
|
|
addiu instruction.
|
|
|
|
|
*/
|
|
|
|
|
|
1999-05-03 09:29:11 +02:00
|
|
|
|
expr1.X_add_number = offset_expr.X_add_number;
|
|
|
|
|
offset_expr.X_add_number = 0;
|
|
|
|
|
frag_grow (32);
|
2003-11-18 22:22:57 +01:00
|
|
|
|
if (expr1.X_add_number == 0 && breg == 0
|
|
|
|
|
&& (call || tempreg == PIC_CALL_REG))
|
2001-02-12 00:11:41 +01:00
|
|
|
|
lw_reloc_type = (int) BFD_RELOC_MIPS_CALL16;
|
2003-06-30 14:44:25 +02:00
|
|
|
|
macro_build (NULL, &icnt, &offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
|
|
|
|
|
tempreg, lw_reloc_type, mips_gp_register);
|
1999-05-03 09:29:11 +02:00
|
|
|
|
if (expr1.X_add_number == 0)
|
|
|
|
|
{
|
|
|
|
|
int off;
|
2002-05-26 20:46:37 +02:00
|
|
|
|
char *p;
|
1999-05-03 09:29:11 +02:00
|
|
|
|
|
|
|
|
|
if (breg == 0)
|
|
|
|
|
off = 0;
|
|
|
|
|
else
|
|
|
|
|
{
|
|
|
|
|
/* We're going to put in an addu instruction using
|
|
|
|
|
tempreg, so we may as well insert the nop right
|
|
|
|
|
now. */
|
2003-06-30 14:44:25 +02:00
|
|
|
|
macro_build (NULL, &icnt, NULL, "nop", "");
|
1999-05-03 09:29:11 +02:00
|
|
|
|
off = 4;
|
|
|
|
|
}
|
|
|
|
|
p = frag_var (rs_machine_dependent, 8 - off, 0,
|
|
|
|
|
RELAX_ENCODE (0, 8 - off, -4 - off, 4 - off, 0,
|
|
|
|
|
(breg == 0
|
|
|
|
|
? mips_opts.warn_about_macros
|
|
|
|
|
: 0)),
|
2001-11-12 23:19:30 +01:00
|
|
|
|
offset_expr.X_add_symbol, 0, NULL);
|
1999-05-03 09:29:11 +02:00
|
|
|
|
if (breg == 0)
|
|
|
|
|
{
|
2003-06-30 14:44:25 +02:00
|
|
|
|
macro_build (p, &icnt, NULL, "nop", "");
|
1999-05-03 09:29:11 +02:00
|
|
|
|
p += 4;
|
|
|
|
|
}
|
2003-06-16 14:13:10 +02:00
|
|
|
|
macro_build (p, &icnt, &expr1, ADDRESS_ADDI_INSN,
|
2003-06-30 14:44:25 +02:00
|
|
|
|
"t,r,j", tempreg, tempreg, BFD_RELOC_LO16);
|
1999-05-03 09:29:11 +02:00
|
|
|
|
/* FIXME: If breg == 0, and the next instruction uses
|
|
|
|
|
$tempreg, then if this variant case is used an extra
|
|
|
|
|
nop will be generated. */
|
|
|
|
|
}
|
|
|
|
|
else if (expr1.X_add_number >= -0x8000
|
|
|
|
|
&& expr1.X_add_number < 0x8000)
|
|
|
|
|
{
|
2003-06-30 14:44:25 +02:00
|
|
|
|
macro_build (NULL, &icnt, NULL, "nop", "");
|
|
|
|
|
macro_build (NULL, &icnt, &expr1, ADDRESS_ADDI_INSN,
|
|
|
|
|
"t,r,j", tempreg, tempreg, BFD_RELOC_LO16);
|
2001-11-12 23:19:30 +01:00
|
|
|
|
frag_var (rs_machine_dependent, 0, 0,
|
|
|
|
|
RELAX_ENCODE (0, 0, -12, -4, 0, 0),
|
|
|
|
|
offset_expr.X_add_symbol, 0, NULL);
|
1999-05-03 09:29:11 +02:00
|
|
|
|
}
|
|
|
|
|
else
|
|
|
|
|
{
|
|
|
|
|
int off1;
|
|
|
|
|
|
|
|
|
|
/* If we are going to add in a base register, and the
|
|
|
|
|
target register and the base register are the same,
|
|
|
|
|
then we are using AT as a temporary register. Since
|
|
|
|
|
we want to load the constant into AT, we add our
|
|
|
|
|
current AT (from the global offset table) and the
|
|
|
|
|
register into the register now, and pretend we were
|
|
|
|
|
not using a base register. */
|
|
|
|
|
if (breg != treg)
|
|
|
|
|
off1 = 0;
|
|
|
|
|
else
|
|
|
|
|
{
|
2003-06-30 14:44:25 +02:00
|
|
|
|
macro_build (NULL, &icnt, NULL, "nop", "");
|
|
|
|
|
macro_build (NULL, &icnt, NULL, ADDRESS_ADD_INSN, "d,v,t",
|
|
|
|
|
treg, AT, breg);
|
1999-05-03 09:29:11 +02:00
|
|
|
|
breg = 0;
|
|
|
|
|
tempreg = treg;
|
|
|
|
|
off1 = -8;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/* Set mips_optimize around the lui instruction to avoid
|
|
|
|
|
inserting an unnecessary nop after the lw. */
|
|
|
|
|
hold_mips_optimize = mips_optimize;
|
|
|
|
|
mips_optimize = 2;
|
2001-11-12 23:19:30 +01:00
|
|
|
|
macro_build_lui (NULL, &icnt, &expr1, AT);
|
1999-05-03 09:29:11 +02:00
|
|
|
|
mips_optimize = hold_mips_optimize;
|
|
|
|
|
|
2003-06-30 14:44:25 +02:00
|
|
|
|
macro_build (NULL, &icnt, &expr1, ADDRESS_ADDI_INSN, "t,r,j",
|
|
|
|
|
AT, AT, BFD_RELOC_LO16);
|
|
|
|
|
macro_build (NULL, &icnt, NULL, ADDRESS_ADD_INSN, "d,v,t",
|
|
|
|
|
tempreg, tempreg, AT);
|
2001-11-12 23:19:30 +01:00
|
|
|
|
frag_var (rs_machine_dependent, 0, 0,
|
|
|
|
|
RELAX_ENCODE (0, 0, -16 + off1, -8, 0, 0),
|
|
|
|
|
offset_expr.X_add_symbol, 0, NULL);
|
1999-05-03 09:29:11 +02:00
|
|
|
|
used_at = 1;
|
|
|
|
|
}
|
|
|
|
|
}
|
* config/tc-mips.h (tc_frag_data_type, TC_FRAG_TYPE): New.
* config/tc-mips.c: Use signed add for n32 address arithmetic.
(append_insn): When filling delay slots with instructions
that have fixups that tc_gen_reloc might consider modifyable
in variant frags, start a new frag.
(load_address): Generate GOT_DISP with of without offset
depending on whether symbol is local. For -xgot, use
GOT_PAGE/GOT_OFST or GOT_HI16/GOT_LO16.
(macro) <M_DLA_AB, M_LA_AB>: Likewise.
<M_JAL_A>: In NewABI, use CALL16 or GOT_DISP for small got,
CALL_HI16/CALL_LO16 or GOT_PAGE/GOT_OFST for big got.
<ld_st>: In NewABI with small got, always use
GOT_PAGE/GOT_OFST, with the latter in the load/store
instruction. With big got, use GOT_HI16/GOT_LO16 or
GOT_PAGE/GOT_OFST.
(tc_gen_reloc): Adjust variant frags with GOT_DISP in NewABI.
Add tc_frag_data.tc_fr_offset to addends. Decay CALL16,
GOT_OFST and GOT_DISP to GOT_DISP in NewABI.
(md_convert_frag): Use memmove for safe copying of overlapping
regions.
2003-04-11 03:56:50 +02:00
|
|
|
|
else if (mips_pic == SVR4_PIC && ! mips_big_got && HAVE_NEWABI)
|
|
|
|
|
{
|
|
|
|
|
char *p = NULL;
|
|
|
|
|
int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT_DISP;
|
|
|
|
|
int adj = 0;
|
|
|
|
|
|
|
|
|
|
/* If this is a reference to an external, and there is no
|
|
|
|
|
constant, or local symbol (*), with or without a
|
|
|
|
|
constant, we want
|
|
|
|
|
lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
|
2003-11-18 22:22:57 +01:00
|
|
|
|
or for lca or if tempreg is PIC_CALL_REG
|
* config/tc-mips.h (tc_frag_data_type, TC_FRAG_TYPE): New.
* config/tc-mips.c: Use signed add for n32 address arithmetic.
(append_insn): When filling delay slots with instructions
that have fixups that tc_gen_reloc might consider modifyable
in variant frags, start a new frag.
(load_address): Generate GOT_DISP with of without offset
depending on whether symbol is local. For -xgot, use
GOT_PAGE/GOT_OFST or GOT_HI16/GOT_LO16.
(macro) <M_DLA_AB, M_LA_AB>: Likewise.
<M_JAL_A>: In NewABI, use CALL16 or GOT_DISP for small got,
CALL_HI16/CALL_LO16 or GOT_PAGE/GOT_OFST for big got.
<ld_st>: In NewABI with small got, always use
GOT_PAGE/GOT_OFST, with the latter in the load/store
instruction. With big got, use GOT_HI16/GOT_LO16 or
GOT_PAGE/GOT_OFST.
(tc_gen_reloc): Adjust variant frags with GOT_DISP in NewABI.
Add tc_frag_data.tc_fr_offset to addends. Decay CALL16,
GOT_OFST and GOT_DISP to GOT_DISP in NewABI.
(md_convert_frag): Use memmove for safe copying of overlapping
regions.
2003-04-11 03:56:50 +02:00
|
|
|
|
lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
|
|
|
|
|
|
|
|
|
|
If we have a small constant, and this is a reference to
|
|
|
|
|
an external symbol, we want
|
|
|
|
|
lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
|
|
|
|
|
addiu $tempreg,$tempreg,<constant>
|
|
|
|
|
|
|
|
|
|
If we have a large constant, and this is a reference to
|
|
|
|
|
an external symbol, we want
|
|
|
|
|
lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
|
|
|
|
|
lui $at,<hiconstant>
|
|
|
|
|
addiu $at,$at,<loconstant>
|
|
|
|
|
addu $tempreg,$tempreg,$at
|
|
|
|
|
|
|
|
|
|
(*) Other assemblers seem to prefer GOT_PAGE/GOT_OFST for
|
|
|
|
|
local symbols, even though it introduces an additional
|
|
|
|
|
instruction. */
|
|
|
|
|
|
|
|
|
|
frag_grow (28);
|
2003-11-18 22:22:57 +01:00
|
|
|
|
if (offset_expr.X_add_number == 0 && breg == 0
|
|
|
|
|
&& (call || tempreg == PIC_CALL_REG))
|
* config/tc-mips.h (tc_frag_data_type, TC_FRAG_TYPE): New.
* config/tc-mips.c: Use signed add for n32 address arithmetic.
(append_insn): When filling delay slots with instructions
that have fixups that tc_gen_reloc might consider modifyable
in variant frags, start a new frag.
(load_address): Generate GOT_DISP with of without offset
depending on whether symbol is local. For -xgot, use
GOT_PAGE/GOT_OFST or GOT_HI16/GOT_LO16.
(macro) <M_DLA_AB, M_LA_AB>: Likewise.
<M_JAL_A>: In NewABI, use CALL16 or GOT_DISP for small got,
CALL_HI16/CALL_LO16 or GOT_PAGE/GOT_OFST for big got.
<ld_st>: In NewABI with small got, always use
GOT_PAGE/GOT_OFST, with the latter in the load/store
instruction. With big got, use GOT_HI16/GOT_LO16 or
GOT_PAGE/GOT_OFST.
(tc_gen_reloc): Adjust variant frags with GOT_DISP in NewABI.
Add tc_frag_data.tc_fr_offset to addends. Decay CALL16,
GOT_OFST and GOT_DISP to GOT_DISP in NewABI.
(md_convert_frag): Use memmove for safe copying of overlapping
regions.
2003-04-11 03:56:50 +02:00
|
|
|
|
lw_reloc_type = (int) BFD_RELOC_MIPS_CALL16;
|
|
|
|
|
if (offset_expr.X_add_number)
|
|
|
|
|
{
|
|
|
|
|
frag_now->tc_frag_data.tc_fr_offset =
|
|
|
|
|
expr1.X_add_number = offset_expr.X_add_number;
|
|
|
|
|
offset_expr.X_add_number = 0;
|
|
|
|
|
|
2003-06-30 14:44:25 +02:00
|
|
|
|
macro_build (NULL, &icnt, &offset_expr, ADDRESS_LOAD_INSN,
|
|
|
|
|
"t,o(b)", tempreg, lw_reloc_type,
|
|
|
|
|
mips_gp_register);
|
* config/tc-mips.h (tc_frag_data_type, TC_FRAG_TYPE): New.
* config/tc-mips.c: Use signed add for n32 address arithmetic.
(append_insn): When filling delay slots with instructions
that have fixups that tc_gen_reloc might consider modifyable
in variant frags, start a new frag.
(load_address): Generate GOT_DISP with of without offset
depending on whether symbol is local. For -xgot, use
GOT_PAGE/GOT_OFST or GOT_HI16/GOT_LO16.
(macro) <M_DLA_AB, M_LA_AB>: Likewise.
<M_JAL_A>: In NewABI, use CALL16 or GOT_DISP for small got,
CALL_HI16/CALL_LO16 or GOT_PAGE/GOT_OFST for big got.
<ld_st>: In NewABI with small got, always use
GOT_PAGE/GOT_OFST, with the latter in the load/store
instruction. With big got, use GOT_HI16/GOT_LO16 or
GOT_PAGE/GOT_OFST.
(tc_gen_reloc): Adjust variant frags with GOT_DISP in NewABI.
Add tc_frag_data.tc_fr_offset to addends. Decay CALL16,
GOT_OFST and GOT_DISP to GOT_DISP in NewABI.
(md_convert_frag): Use memmove for safe copying of overlapping
regions.
2003-04-11 03:56:50 +02:00
|
|
|
|
|
|
|
|
|
if (expr1.X_add_number >= -0x8000
|
|
|
|
|
&& expr1.X_add_number < 0x8000)
|
|
|
|
|
{
|
2003-06-30 14:44:25 +02:00
|
|
|
|
macro_build (NULL, &icnt, &expr1, ADDRESS_ADDI_INSN,
|
|
|
|
|
"t,r,j", tempreg, tempreg, BFD_RELOC_LO16);
|
* config/tc-mips.h (tc_frag_data_type, TC_FRAG_TYPE): New.
* config/tc-mips.c: Use signed add for n32 address arithmetic.
(append_insn): When filling delay slots with instructions
that have fixups that tc_gen_reloc might consider modifyable
in variant frags, start a new frag.
(load_address): Generate GOT_DISP with of without offset
depending on whether symbol is local. For -xgot, use
GOT_PAGE/GOT_OFST or GOT_HI16/GOT_LO16.
(macro) <M_DLA_AB, M_LA_AB>: Likewise.
<M_JAL_A>: In NewABI, use CALL16 or GOT_DISP for small got,
CALL_HI16/CALL_LO16 or GOT_PAGE/GOT_OFST for big got.
<ld_st>: In NewABI with small got, always use
GOT_PAGE/GOT_OFST, with the latter in the load/store
instruction. With big got, use GOT_HI16/GOT_LO16 or
GOT_PAGE/GOT_OFST.
(tc_gen_reloc): Adjust variant frags with GOT_DISP in NewABI.
Add tc_frag_data.tc_fr_offset to addends. Decay CALL16,
GOT_OFST and GOT_DISP to GOT_DISP in NewABI.
(md_convert_frag): Use memmove for safe copying of overlapping
regions.
2003-04-11 03:56:50 +02:00
|
|
|
|
p = frag_var (rs_machine_dependent, 4, 0,
|
|
|
|
|
RELAX_ENCODE (8, 4, 0, 0, 0, 0),
|
|
|
|
|
offset_expr.X_add_symbol, 0, NULL);
|
|
|
|
|
}
|
2003-10-01 04:07:48 +02:00
|
|
|
|
else if (IS_SEXT_32BIT_NUM (expr1.X_add_number + 0x8000))
|
* config/tc-mips.h (tc_frag_data_type, TC_FRAG_TYPE): New.
* config/tc-mips.c: Use signed add for n32 address arithmetic.
(append_insn): When filling delay slots with instructions
that have fixups that tc_gen_reloc might consider modifyable
in variant frags, start a new frag.
(load_address): Generate GOT_DISP with of without offset
depending on whether symbol is local. For -xgot, use
GOT_PAGE/GOT_OFST or GOT_HI16/GOT_LO16.
(macro) <M_DLA_AB, M_LA_AB>: Likewise.
<M_JAL_A>: In NewABI, use CALL16 or GOT_DISP for small got,
CALL_HI16/CALL_LO16 or GOT_PAGE/GOT_OFST for big got.
<ld_st>: In NewABI with small got, always use
GOT_PAGE/GOT_OFST, with the latter in the load/store
instruction. With big got, use GOT_HI16/GOT_LO16 or
GOT_PAGE/GOT_OFST.
(tc_gen_reloc): Adjust variant frags with GOT_DISP in NewABI.
Add tc_frag_data.tc_fr_offset to addends. Decay CALL16,
GOT_OFST and GOT_DISP to GOT_DISP in NewABI.
(md_convert_frag): Use memmove for safe copying of overlapping
regions.
2003-04-11 03:56:50 +02:00
|
|
|
|
{
|
|
|
|
|
int dreg;
|
|
|
|
|
|
|
|
|
|
/* If we are going to add in a base register, and the
|
|
|
|
|
target register and the base register are the same,
|
|
|
|
|
then we are using AT as a temporary register. Since
|
|
|
|
|
we want to load the constant into AT, we add our
|
|
|
|
|
current AT (from the global offset table) and the
|
|
|
|
|
register into the register now, and pretend we were
|
|
|
|
|
not using a base register. */
|
|
|
|
|
if (breg != treg)
|
|
|
|
|
dreg = tempreg;
|
|
|
|
|
else
|
|
|
|
|
{
|
|
|
|
|
assert (tempreg == AT);
|
2003-11-15 16:57:14 +01:00
|
|
|
|
macro_build (NULL, &icnt, NULL, ADDRESS_ADD_INSN,
|
2003-06-30 14:44:25 +02:00
|
|
|
|
"d,v,t", treg, AT, breg);
|
* config/tc-mips.h (tc_frag_data_type, TC_FRAG_TYPE): New.
* config/tc-mips.c: Use signed add for n32 address arithmetic.
(append_insn): When filling delay slots with instructions
that have fixups that tc_gen_reloc might consider modifyable
in variant frags, start a new frag.
(load_address): Generate GOT_DISP with of without offset
depending on whether symbol is local. For -xgot, use
GOT_PAGE/GOT_OFST or GOT_HI16/GOT_LO16.
(macro) <M_DLA_AB, M_LA_AB>: Likewise.
<M_JAL_A>: In NewABI, use CALL16 or GOT_DISP for small got,
CALL_HI16/CALL_LO16 or GOT_PAGE/GOT_OFST for big got.
<ld_st>: In NewABI with small got, always use
GOT_PAGE/GOT_OFST, with the latter in the load/store
instruction. With big got, use GOT_HI16/GOT_LO16 or
GOT_PAGE/GOT_OFST.
(tc_gen_reloc): Adjust variant frags with GOT_DISP in NewABI.
Add tc_frag_data.tc_fr_offset to addends. Decay CALL16,
GOT_OFST and GOT_DISP to GOT_DISP in NewABI.
(md_convert_frag): Use memmove for safe copying of overlapping
regions.
2003-04-11 03:56:50 +02:00
|
|
|
|
dreg = treg;
|
|
|
|
|
adj = 4;
|
|
|
|
|
}
|
|
|
|
|
|
2003-06-30 14:44:25 +02:00
|
|
|
|
macro_build_lui (NULL, &icnt, &expr1, AT);
|
|
|
|
|
macro_build (NULL, &icnt, &expr1, ADDRESS_ADDI_INSN,
|
|
|
|
|
"t,r,j", AT, AT, BFD_RELOC_LO16);
|
|
|
|
|
macro_build (NULL, &icnt, NULL, ADDRESS_ADD_INSN, "d,v,t",
|
|
|
|
|
dreg, dreg, AT);
|
* config/tc-mips.h (tc_frag_data_type, TC_FRAG_TYPE): New.
* config/tc-mips.c: Use signed add for n32 address arithmetic.
(append_insn): When filling delay slots with instructions
that have fixups that tc_gen_reloc might consider modifyable
in variant frags, start a new frag.
(load_address): Generate GOT_DISP with of without offset
depending on whether symbol is local. For -xgot, use
GOT_PAGE/GOT_OFST or GOT_HI16/GOT_LO16.
(macro) <M_DLA_AB, M_LA_AB>: Likewise.
<M_JAL_A>: In NewABI, use CALL16 or GOT_DISP for small got,
CALL_HI16/CALL_LO16 or GOT_PAGE/GOT_OFST for big got.
<ld_st>: In NewABI with small got, always use
GOT_PAGE/GOT_OFST, with the latter in the load/store
instruction. With big got, use GOT_HI16/GOT_LO16 or
GOT_PAGE/GOT_OFST.
(tc_gen_reloc): Adjust variant frags with GOT_DISP in NewABI.
Add tc_frag_data.tc_fr_offset to addends. Decay CALL16,
GOT_OFST and GOT_DISP to GOT_DISP in NewABI.
(md_convert_frag): Use memmove for safe copying of overlapping
regions.
2003-04-11 03:56:50 +02:00
|
|
|
|
|
|
|
|
|
p = frag_var (rs_machine_dependent, 4 + adj, 0,
|
|
|
|
|
RELAX_ENCODE (16 + adj, 4 + adj,
|
|
|
|
|
0, 0, 0, 0),
|
|
|
|
|
offset_expr.X_add_symbol, 0, NULL);
|
|
|
|
|
|
|
|
|
|
used_at = 1;
|
|
|
|
|
}
|
|
|
|
|
else
|
|
|
|
|
as_bad (_("PIC code offset overflow (max 32 signed bits)"));
|
|
|
|
|
|
|
|
|
|
offset_expr.X_add_number = expr1.X_add_number;
|
|
|
|
|
|
2003-06-16 14:13:10 +02:00
|
|
|
|
macro_build (p, &icnt, &offset_expr, ADDRESS_LOAD_INSN,
|
2003-06-30 14:44:25 +02:00
|
|
|
|
"t,o(b)", tempreg, BFD_RELOC_MIPS_GOT_DISP,
|
* config/tc-mips.h (tc_frag_data_type, TC_FRAG_TYPE): New.
* config/tc-mips.c: Use signed add for n32 address arithmetic.
(append_insn): When filling delay slots with instructions
that have fixups that tc_gen_reloc might consider modifyable
in variant frags, start a new frag.
(load_address): Generate GOT_DISP with of without offset
depending on whether symbol is local. For -xgot, use
GOT_PAGE/GOT_OFST or GOT_HI16/GOT_LO16.
(macro) <M_DLA_AB, M_LA_AB>: Likewise.
<M_JAL_A>: In NewABI, use CALL16 or GOT_DISP for small got,
CALL_HI16/CALL_LO16 or GOT_PAGE/GOT_OFST for big got.
<ld_st>: In NewABI with small got, always use
GOT_PAGE/GOT_OFST, with the latter in the load/store
instruction. With big got, use GOT_HI16/GOT_LO16 or
GOT_PAGE/GOT_OFST.
(tc_gen_reloc): Adjust variant frags with GOT_DISP in NewABI.
Add tc_frag_data.tc_fr_offset to addends. Decay CALL16,
GOT_OFST and GOT_DISP to GOT_DISP in NewABI.
(md_convert_frag): Use memmove for safe copying of overlapping
regions.
2003-04-11 03:56:50 +02:00
|
|
|
|
mips_gp_register);
|
|
|
|
|
if (adj)
|
|
|
|
|
{
|
2003-06-30 14:44:25 +02:00
|
|
|
|
macro_build (p + 4, &icnt, NULL, ADDRESS_ADD_INSN, "d,v,t",
|
2003-06-16 14:13:10 +02:00
|
|
|
|
treg, tempreg, breg);
|
* config/tc-mips.h (tc_frag_data_type, TC_FRAG_TYPE): New.
* config/tc-mips.c: Use signed add for n32 address arithmetic.
(append_insn): When filling delay slots with instructions
that have fixups that tc_gen_reloc might consider modifyable
in variant frags, start a new frag.
(load_address): Generate GOT_DISP with of without offset
depending on whether symbol is local. For -xgot, use
GOT_PAGE/GOT_OFST or GOT_HI16/GOT_LO16.
(macro) <M_DLA_AB, M_LA_AB>: Likewise.
<M_JAL_A>: In NewABI, use CALL16 or GOT_DISP for small got,
CALL_HI16/CALL_LO16 or GOT_PAGE/GOT_OFST for big got.
<ld_st>: In NewABI with small got, always use
GOT_PAGE/GOT_OFST, with the latter in the load/store
instruction. With big got, use GOT_HI16/GOT_LO16 or
GOT_PAGE/GOT_OFST.
(tc_gen_reloc): Adjust variant frags with GOT_DISP in NewABI.
Add tc_frag_data.tc_fr_offset to addends. Decay CALL16,
GOT_OFST and GOT_DISP to GOT_DISP in NewABI.
(md_convert_frag): Use memmove for safe copying of overlapping
regions.
2003-04-11 03:56:50 +02:00
|
|
|
|
breg = 0;
|
|
|
|
|
tempreg = treg;
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
else
|
|
|
|
|
{
|
2003-06-30 14:44:25 +02:00
|
|
|
|
macro_build (NULL, &icnt, &offset_expr, ADDRESS_LOAD_INSN,
|
|
|
|
|
"t,o(b)", tempreg, lw_reloc_type,
|
|
|
|
|
mips_gp_register);
|
* config/tc-mips.h (tc_frag_data_type, TC_FRAG_TYPE): New.
* config/tc-mips.c: Use signed add for n32 address arithmetic.
(append_insn): When filling delay slots with instructions
that have fixups that tc_gen_reloc might consider modifyable
in variant frags, start a new frag.
(load_address): Generate GOT_DISP with of without offset
depending on whether symbol is local. For -xgot, use
GOT_PAGE/GOT_OFST or GOT_HI16/GOT_LO16.
(macro) <M_DLA_AB, M_LA_AB>: Likewise.
<M_JAL_A>: In NewABI, use CALL16 or GOT_DISP for small got,
CALL_HI16/CALL_LO16 or GOT_PAGE/GOT_OFST for big got.
<ld_st>: In NewABI with small got, always use
GOT_PAGE/GOT_OFST, with the latter in the load/store
instruction. With big got, use GOT_HI16/GOT_LO16 or
GOT_PAGE/GOT_OFST.
(tc_gen_reloc): Adjust variant frags with GOT_DISP in NewABI.
Add tc_frag_data.tc_fr_offset to addends. Decay CALL16,
GOT_OFST and GOT_DISP to GOT_DISP in NewABI.
(md_convert_frag): Use memmove for safe copying of overlapping
regions.
2003-04-11 03:56:50 +02:00
|
|
|
|
if (lw_reloc_type != BFD_RELOC_MIPS_GOT_DISP)
|
|
|
|
|
p = frag_var (rs_machine_dependent, 0, 0,
|
|
|
|
|
RELAX_ENCODE (0, 0, -4, 0, 0, 0),
|
|
|
|
|
offset_expr.X_add_symbol, 0, NULL);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
if (! p)
|
|
|
|
|
{
|
|
|
|
|
/* To avoid confusion in tc_gen_reloc, we must ensure
|
|
|
|
|
that this does not become a variant frag. */
|
|
|
|
|
frag_wane (frag_now);
|
|
|
|
|
frag_new (0);
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
else if (mips_pic == SVR4_PIC && ! HAVE_NEWABI)
|
1999-05-03 09:29:11 +02:00
|
|
|
|
{
|
|
|
|
|
int gpdel;
|
2002-05-26 20:46:37 +02:00
|
|
|
|
char *p;
|
2001-02-12 00:11:41 +01:00
|
|
|
|
int lui_reloc_type = (int) BFD_RELOC_MIPS_GOT_HI16;
|
|
|
|
|
int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT_LO16;
|
2002-09-18 04:25:19 +02:00
|
|
|
|
int local_reloc_type = (int) BFD_RELOC_MIPS_GOT16;
|
1999-05-03 09:29:11 +02:00
|
|
|
|
|
|
|
|
|
/* This is the large GOT case. If this is a reference to an
|
|
|
|
|
external symbol, and there is no constant, we want
|
|
|
|
|
lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
|
|
|
|
|
addu $tempreg,$tempreg,$gp
|
|
|
|
|
lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
|
2003-11-18 22:22:57 +01:00
|
|
|
|
or for lca or if tempreg is PIC_CALL_REG
|
2001-02-12 00:11:41 +01:00
|
|
|
|
lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16)
|
|
|
|
|
addu $tempreg,$tempreg,$gp
|
|
|
|
|
lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16)
|
1999-05-03 09:29:11 +02:00
|
|
|
|
For a local symbol, we want
|
|
|
|
|
lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
|
|
|
|
|
nop
|
|
|
|
|
addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
|
|
|
|
|
|
|
|
|
|
If we have a small constant, and this is a reference to
|
|
|
|
|
an external symbol, we want
|
|
|
|
|
lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
|
|
|
|
|
addu $tempreg,$tempreg,$gp
|
|
|
|
|
lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
|
|
|
|
|
nop
|
|
|
|
|
addiu $tempreg,$tempreg,<constant>
|
|
|
|
|
For a local symbol, we want
|
|
|
|
|
lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
|
|
|
|
|
nop
|
|
|
|
|
addiu $tempreg,$tempreg,<constant> (BFD_RELOC_LO16)
|
|
|
|
|
|
|
|
|
|
If we have a large constant, and this is a reference to
|
|
|
|
|
an external symbol, we want
|
|
|
|
|
lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
|
|
|
|
|
addu $tempreg,$tempreg,$gp
|
|
|
|
|
lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
|
|
|
|
|
lui $at,<hiconstant>
|
|
|
|
|
addiu $at,$at,<loconstant>
|
|
|
|
|
addu $tempreg,$tempreg,$at
|
|
|
|
|
For a local symbol, we want
|
|
|
|
|
lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
|
|
|
|
|
lui $at,<hiconstant>
|
|
|
|
|
addiu $at,$at,<loconstant> (BFD_RELOC_LO16)
|
|
|
|
|
addu $tempreg,$tempreg,$at
|
* config/tc-mips.h (tc_frag_data_type, TC_FRAG_TYPE): New.
* config/tc-mips.c: Use signed add for n32 address arithmetic.
(append_insn): When filling delay slots with instructions
that have fixups that tc_gen_reloc might consider modifyable
in variant frags, start a new frag.
(load_address): Generate GOT_DISP with of without offset
depending on whether symbol is local. For -xgot, use
GOT_PAGE/GOT_OFST or GOT_HI16/GOT_LO16.
(macro) <M_DLA_AB, M_LA_AB>: Likewise.
<M_JAL_A>: In NewABI, use CALL16 or GOT_DISP for small got,
CALL_HI16/CALL_LO16 or GOT_PAGE/GOT_OFST for big got.
<ld_st>: In NewABI with small got, always use
GOT_PAGE/GOT_OFST, with the latter in the load/store
instruction. With big got, use GOT_HI16/GOT_LO16 or
GOT_PAGE/GOT_OFST.
(tc_gen_reloc): Adjust variant frags with GOT_DISP in NewABI.
Add tc_frag_data.tc_fr_offset to addends. Decay CALL16,
GOT_OFST and GOT_DISP to GOT_DISP in NewABI.
(md_convert_frag): Use memmove for safe copying of overlapping
regions.
2003-04-11 03:56:50 +02:00
|
|
|
|
*/
|
2002-05-31 01:32:47 +02:00
|
|
|
|
|
1999-05-03 09:29:11 +02:00
|
|
|
|
expr1.X_add_number = offset_expr.X_add_number;
|
|
|
|
|
offset_expr.X_add_number = 0;
|
|
|
|
|
frag_grow (52);
|
2002-05-31 00:29:20 +02:00
|
|
|
|
if (reg_needs_delay (mips_gp_register))
|
1999-05-03 09:29:11 +02:00
|
|
|
|
gpdel = 4;
|
|
|
|
|
else
|
|
|
|
|
gpdel = 0;
|
2003-11-18 22:22:57 +01:00
|
|
|
|
if (expr1.X_add_number == 0 && breg == 0
|
|
|
|
|
&& (call || tempreg == PIC_CALL_REG))
|
2001-02-12 00:11:41 +01:00
|
|
|
|
{
|
|
|
|
|
lui_reloc_type = (int) BFD_RELOC_MIPS_CALL_HI16;
|
|
|
|
|
lw_reloc_type = (int) BFD_RELOC_MIPS_CALL_LO16;
|
|
|
|
|
}
|
2003-06-30 14:44:25 +02:00
|
|
|
|
macro_build (NULL, &icnt, &offset_expr, "lui", "t,u",
|
2001-02-12 00:11:41 +01:00
|
|
|
|
tempreg, lui_reloc_type);
|
2003-06-30 14:44:25 +02:00
|
|
|
|
macro_build (NULL, &icnt, NULL, ADDRESS_ADD_INSN, "d,v,t",
|
|
|
|
|
tempreg, tempreg, mips_gp_register);
|
|
|
|
|
macro_build (NULL, &icnt, &offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
|
|
|
|
|
tempreg, lw_reloc_type, tempreg);
|
1999-05-03 09:29:11 +02:00
|
|
|
|
if (expr1.X_add_number == 0)
|
|
|
|
|
{
|
|
|
|
|
int off;
|
|
|
|
|
|
|
|
|
|
if (breg == 0)
|
|
|
|
|
off = 0;
|
|
|
|
|
else
|
|
|
|
|
{
|
|
|
|
|
/* We're going to put in an addu instruction using
|
|
|
|
|
tempreg, so we may as well insert the nop right
|
|
|
|
|
now. */
|
2003-06-30 14:44:25 +02:00
|
|
|
|
macro_build (NULL, &icnt, NULL, "nop", "");
|
1999-05-03 09:29:11 +02:00
|
|
|
|
off = 4;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
p = frag_var (rs_machine_dependent, 12 + gpdel, 0,
|
|
|
|
|
RELAX_ENCODE (12 + off, 12 + gpdel, gpdel,
|
|
|
|
|
8 + gpdel, 0,
|
|
|
|
|
(breg == 0
|
|
|
|
|
? mips_opts.warn_about_macros
|
|
|
|
|
: 0)),
|
2001-11-12 23:19:30 +01:00
|
|
|
|
offset_expr.X_add_symbol, 0, NULL);
|
1999-05-03 09:29:11 +02:00
|
|
|
|
}
|
|
|
|
|
else if (expr1.X_add_number >= -0x8000
|
|
|
|
|
&& expr1.X_add_number < 0x8000)
|
|
|
|
|
{
|
2003-06-30 14:44:25 +02:00
|
|
|
|
macro_build (NULL, &icnt, NULL, "nop", "");
|
|
|
|
|
macro_build (NULL, &icnt, &expr1, ADDRESS_ADDI_INSN, "t,r,j",
|
|
|
|
|
tempreg, tempreg, BFD_RELOC_LO16);
|
1999-05-03 09:29:11 +02:00
|
|
|
|
|
|
|
|
|
p = frag_var (rs_machine_dependent, 12 + gpdel, 0,
|
|
|
|
|
RELAX_ENCODE (20, 12 + gpdel, gpdel, 8 + gpdel, 0,
|
|
|
|
|
(breg == 0
|
|
|
|
|
? mips_opts.warn_about_macros
|
|
|
|
|
: 0)),
|
2001-11-12 23:19:30 +01:00
|
|
|
|
offset_expr.X_add_symbol, 0, NULL);
|
1999-05-03 09:29:11 +02:00
|
|
|
|
}
|
|
|
|
|
else
|
|
|
|
|
{
|
|
|
|
|
int adj, dreg;
|
|
|
|
|
|
|
|
|
|
/* If we are going to add in a base register, and the
|
|
|
|
|
target register and the base register are the same,
|
|
|
|
|
then we are using AT as a temporary register. Since
|
|
|
|
|
we want to load the constant into AT, we add our
|
|
|
|
|
current AT (from the global offset table) and the
|
|
|
|
|
register into the register now, and pretend we were
|
|
|
|
|
not using a base register. */
|
|
|
|
|
if (breg != treg)
|
|
|
|
|
{
|
|
|
|
|
adj = 0;
|
|
|
|
|
dreg = tempreg;
|
|
|
|
|
}
|
|
|
|
|
else
|
|
|
|
|
{
|
|
|
|
|
assert (tempreg == AT);
|
2003-06-30 14:44:25 +02:00
|
|
|
|
macro_build (NULL, &icnt, NULL, "nop", "");
|
|
|
|
|
macro_build (NULL, &icnt, NULL, ADDRESS_ADD_INSN, "d,v,t",
|
|
|
|
|
treg, AT, breg);
|
1999-05-03 09:29:11 +02:00
|
|
|
|
dreg = treg;
|
|
|
|
|
adj = 8;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/* Set mips_optimize around the lui instruction to avoid
|
|
|
|
|
inserting an unnecessary nop after the lw. */
|
|
|
|
|
hold_mips_optimize = mips_optimize;
|
|
|
|
|
mips_optimize = 2;
|
2001-11-12 23:19:30 +01:00
|
|
|
|
macro_build_lui (NULL, &icnt, &expr1, AT);
|
1999-05-03 09:29:11 +02:00
|
|
|
|
mips_optimize = hold_mips_optimize;
|
|
|
|
|
|
2003-06-30 14:44:25 +02:00
|
|
|
|
macro_build (NULL, &icnt, &expr1, ADDRESS_ADDI_INSN, "t,r,j",
|
|
|
|
|
AT, AT, BFD_RELOC_LO16);
|
|
|
|
|
macro_build (NULL, &icnt, NULL, ADDRESS_ADD_INSN, "d,v,t",
|
|
|
|
|
dreg, dreg, AT);
|
1999-05-03 09:29:11 +02:00
|
|
|
|
|
|
|
|
|
p = frag_var (rs_machine_dependent, 16 + gpdel + adj, 0,
|
|
|
|
|
RELAX_ENCODE (24 + adj, 16 + gpdel + adj, gpdel,
|
|
|
|
|
8 + gpdel, 0,
|
|
|
|
|
(breg == 0
|
|
|
|
|
? mips_opts.warn_about_macros
|
|
|
|
|
: 0)),
|
2001-11-12 23:19:30 +01:00
|
|
|
|
offset_expr.X_add_symbol, 0, NULL);
|
1999-05-03 09:29:11 +02:00
|
|
|
|
|
|
|
|
|
used_at = 1;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
if (gpdel > 0)
|
|
|
|
|
{
|
|
|
|
|
/* This is needed because this instruction uses $gp, but
|
* config/tc-mips.h (tc_frag_data_type, TC_FRAG_TYPE): New.
* config/tc-mips.c: Use signed add for n32 address arithmetic.
(append_insn): When filling delay slots with instructions
that have fixups that tc_gen_reloc might consider modifyable
in variant frags, start a new frag.
(load_address): Generate GOT_DISP with of without offset
depending on whether symbol is local. For -xgot, use
GOT_PAGE/GOT_OFST or GOT_HI16/GOT_LO16.
(macro) <M_DLA_AB, M_LA_AB>: Likewise.
<M_JAL_A>: In NewABI, use CALL16 or GOT_DISP for small got,
CALL_HI16/CALL_LO16 or GOT_PAGE/GOT_OFST for big got.
<ld_st>: In NewABI with small got, always use
GOT_PAGE/GOT_OFST, with the latter in the load/store
instruction. With big got, use GOT_HI16/GOT_LO16 or
GOT_PAGE/GOT_OFST.
(tc_gen_reloc): Adjust variant frags with GOT_DISP in NewABI.
Add tc_frag_data.tc_fr_offset to addends. Decay CALL16,
GOT_OFST and GOT_DISP to GOT_DISP in NewABI.
(md_convert_frag): Use memmove for safe copying of overlapping
regions.
2003-04-11 03:56:50 +02:00
|
|
|
|
the first instruction on the main stream does not. */
|
2003-06-30 14:44:25 +02:00
|
|
|
|
macro_build (p, &icnt, NULL, "nop", "");
|
1999-05-03 09:29:11 +02:00
|
|
|
|
p += 4;
|
|
|
|
|
}
|
2002-09-18 04:25:19 +02:00
|
|
|
|
|
2003-06-16 14:13:10 +02:00
|
|
|
|
macro_build (p, &icnt, &offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
|
|
|
|
|
tempreg, local_reloc_type, mips_gp_register);
|
1999-05-03 09:29:11 +02:00
|
|
|
|
p += 4;
|
* config/tc-mips.h (tc_frag_data_type, TC_FRAG_TYPE): New.
* config/tc-mips.c: Use signed add for n32 address arithmetic.
(append_insn): When filling delay slots with instructions
that have fixups that tc_gen_reloc might consider modifyable
in variant frags, start a new frag.
(load_address): Generate GOT_DISP with of without offset
depending on whether symbol is local. For -xgot, use
GOT_PAGE/GOT_OFST or GOT_HI16/GOT_LO16.
(macro) <M_DLA_AB, M_LA_AB>: Likewise.
<M_JAL_A>: In NewABI, use CALL16 or GOT_DISP for small got,
CALL_HI16/CALL_LO16 or GOT_PAGE/GOT_OFST for big got.
<ld_st>: In NewABI with small got, always use
GOT_PAGE/GOT_OFST, with the latter in the load/store
instruction. With big got, use GOT_HI16/GOT_LO16 or
GOT_PAGE/GOT_OFST.
(tc_gen_reloc): Adjust variant frags with GOT_DISP in NewABI.
Add tc_frag_data.tc_fr_offset to addends. Decay CALL16,
GOT_OFST and GOT_DISP to GOT_DISP in NewABI.
(md_convert_frag): Use memmove for safe copying of overlapping
regions.
2003-04-11 03:56:50 +02:00
|
|
|
|
if (expr1.X_add_number >= -0x8000
|
1999-05-03 09:29:11 +02:00
|
|
|
|
&& expr1.X_add_number < 0x8000)
|
|
|
|
|
{
|
2003-06-30 14:44:25 +02:00
|
|
|
|
macro_build (p, &icnt, NULL, "nop", "");
|
1999-05-03 09:29:11 +02:00
|
|
|
|
p += 4;
|
2003-06-16 14:13:10 +02:00
|
|
|
|
macro_build (p, &icnt, &expr1, ADDRESS_ADDI_INSN,
|
2003-06-30 14:44:25 +02:00
|
|
|
|
"t,r,j", tempreg, tempreg, BFD_RELOC_LO16);
|
1999-05-03 09:29:11 +02:00
|
|
|
|
/* FIXME: If add_number is 0, and there was no base
|
* config/tc-mips.h (tc_frag_data_type, TC_FRAG_TYPE): New.
* config/tc-mips.c: Use signed add for n32 address arithmetic.
(append_insn): When filling delay slots with instructions
that have fixups that tc_gen_reloc might consider modifyable
in variant frags, start a new frag.
(load_address): Generate GOT_DISP with of without offset
depending on whether symbol is local. For -xgot, use
GOT_PAGE/GOT_OFST or GOT_HI16/GOT_LO16.
(macro) <M_DLA_AB, M_LA_AB>: Likewise.
<M_JAL_A>: In NewABI, use CALL16 or GOT_DISP for small got,
CALL_HI16/CALL_LO16 or GOT_PAGE/GOT_OFST for big got.
<ld_st>: In NewABI with small got, always use
GOT_PAGE/GOT_OFST, with the latter in the load/store
instruction. With big got, use GOT_HI16/GOT_LO16 or
GOT_PAGE/GOT_OFST.
(tc_gen_reloc): Adjust variant frags with GOT_DISP in NewABI.
Add tc_frag_data.tc_fr_offset to addends. Decay CALL16,
GOT_OFST and GOT_DISP to GOT_DISP in NewABI.
(md_convert_frag): Use memmove for safe copying of overlapping
regions.
2003-04-11 03:56:50 +02:00
|
|
|
|
register, the external symbol case ended with a load,
|
|
|
|
|
so if the symbol turns out to not be external, and
|
|
|
|
|
the next instruction uses tempreg, an unnecessary nop
|
|
|
|
|
will be inserted. */
|
1999-05-03 09:29:11 +02:00
|
|
|
|
}
|
|
|
|
|
else
|
|
|
|
|
{
|
|
|
|
|
if (breg == treg)
|
|
|
|
|
{
|
|
|
|
|
/* We must add in the base register now, as in the
|
* config/tc-mips.h (tc_frag_data_type, TC_FRAG_TYPE): New.
* config/tc-mips.c: Use signed add for n32 address arithmetic.
(append_insn): When filling delay slots with instructions
that have fixups that tc_gen_reloc might consider modifyable
in variant frags, start a new frag.
(load_address): Generate GOT_DISP with of without offset
depending on whether symbol is local. For -xgot, use
GOT_PAGE/GOT_OFST or GOT_HI16/GOT_LO16.
(macro) <M_DLA_AB, M_LA_AB>: Likewise.
<M_JAL_A>: In NewABI, use CALL16 or GOT_DISP for small got,
CALL_HI16/CALL_LO16 or GOT_PAGE/GOT_OFST for big got.
<ld_st>: In NewABI with small got, always use
GOT_PAGE/GOT_OFST, with the latter in the load/store
instruction. With big got, use GOT_HI16/GOT_LO16 or
GOT_PAGE/GOT_OFST.
(tc_gen_reloc): Adjust variant frags with GOT_DISP in NewABI.
Add tc_frag_data.tc_fr_offset to addends. Decay CALL16,
GOT_OFST and GOT_DISP to GOT_DISP in NewABI.
(md_convert_frag): Use memmove for safe copying of overlapping
regions.
2003-04-11 03:56:50 +02:00
|
|
|
|
external symbol case. */
|
1999-05-03 09:29:11 +02:00
|
|
|
|
assert (tempreg == AT);
|
2003-06-30 14:44:25 +02:00
|
|
|
|
macro_build (p, &icnt, NULL, "nop", "");
|
1999-05-03 09:29:11 +02:00
|
|
|
|
p += 4;
|
2003-06-30 14:44:25 +02:00
|
|
|
|
macro_build (p, &icnt, NULL, ADDRESS_ADD_INSN, "d,v,t",
|
|
|
|
|
treg, AT, breg);
|
1999-05-03 09:29:11 +02:00
|
|
|
|
p += 4;
|
|
|
|
|
tempreg = treg;
|
|
|
|
|
/* We set breg to 0 because we have arranged to add
|
* config/tc-mips.h (tc_frag_data_type, TC_FRAG_TYPE): New.
* config/tc-mips.c: Use signed add for n32 address arithmetic.
(append_insn): When filling delay slots with instructions
that have fixups that tc_gen_reloc might consider modifyable
in variant frags, start a new frag.
(load_address): Generate GOT_DISP with of without offset
depending on whether symbol is local. For -xgot, use
GOT_PAGE/GOT_OFST or GOT_HI16/GOT_LO16.
(macro) <M_DLA_AB, M_LA_AB>: Likewise.
<M_JAL_A>: In NewABI, use CALL16 or GOT_DISP for small got,
CALL_HI16/CALL_LO16 or GOT_PAGE/GOT_OFST for big got.
<ld_st>: In NewABI with small got, always use
GOT_PAGE/GOT_OFST, with the latter in the load/store
instruction. With big got, use GOT_HI16/GOT_LO16 or
GOT_PAGE/GOT_OFST.
(tc_gen_reloc): Adjust variant frags with GOT_DISP in NewABI.
Add tc_frag_data.tc_fr_offset to addends. Decay CALL16,
GOT_OFST and GOT_DISP to GOT_DISP in NewABI.
(md_convert_frag): Use memmove for safe copying of overlapping
regions.
2003-04-11 03:56:50 +02:00
|
|
|
|
it in in both cases. */
|
1999-05-03 09:29:11 +02:00
|
|
|
|
breg = 0;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
macro_build_lui (p, &icnt, &expr1, AT);
|
|
|
|
|
p += 4;
|
2003-06-30 14:44:25 +02:00
|
|
|
|
macro_build (p, &icnt, &expr1, ADDRESS_ADDI_INSN, "t,r,j",
|
|
|
|
|
AT, AT, BFD_RELOC_LO16);
|
1999-05-03 09:29:11 +02:00
|
|
|
|
p += 4;
|
2003-06-30 14:44:25 +02:00
|
|
|
|
macro_build (p, &icnt, NULL, ADDRESS_ADD_INSN, "d,v,t",
|
|
|
|
|
tempreg, tempreg, AT);
|
1999-05-03 09:29:11 +02:00
|
|
|
|
p += 4;
|
|
|
|
|
}
|
|
|
|
|
}
|
* config/tc-mips.h (tc_frag_data_type, TC_FRAG_TYPE): New.
* config/tc-mips.c: Use signed add for n32 address arithmetic.
(append_insn): When filling delay slots with instructions
that have fixups that tc_gen_reloc might consider modifyable
in variant frags, start a new frag.
(load_address): Generate GOT_DISP with of without offset
depending on whether symbol is local. For -xgot, use
GOT_PAGE/GOT_OFST or GOT_HI16/GOT_LO16.
(macro) <M_DLA_AB, M_LA_AB>: Likewise.
<M_JAL_A>: In NewABI, use CALL16 or GOT_DISP for small got,
CALL_HI16/CALL_LO16 or GOT_PAGE/GOT_OFST for big got.
<ld_st>: In NewABI with small got, always use
GOT_PAGE/GOT_OFST, with the latter in the load/store
instruction. With big got, use GOT_HI16/GOT_LO16 or
GOT_PAGE/GOT_OFST.
(tc_gen_reloc): Adjust variant frags with GOT_DISP in NewABI.
Add tc_frag_data.tc_fr_offset to addends. Decay CALL16,
GOT_OFST and GOT_DISP to GOT_DISP in NewABI.
(md_convert_frag): Use memmove for safe copying of overlapping
regions.
2003-04-11 03:56:50 +02:00
|
|
|
|
else if (mips_pic == SVR4_PIC && HAVE_NEWABI)
|
|
|
|
|
{
|
|
|
|
|
char *p = NULL;
|
|
|
|
|
int lui_reloc_type = (int) BFD_RELOC_MIPS_GOT_HI16;
|
|
|
|
|
int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT_LO16;
|
|
|
|
|
int adj = 0;
|
|
|
|
|
|
|
|
|
|
/* This is the large GOT case. If this is a reference to an
|
|
|
|
|
external symbol, and there is no constant, we want
|
|
|
|
|
lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
|
|
|
|
|
add $tempreg,$tempreg,$gp
|
|
|
|
|
lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
|
2003-11-18 22:22:57 +01:00
|
|
|
|
or for lca or if tempreg is PIC_CALL_REG
|
* config/tc-mips.h (tc_frag_data_type, TC_FRAG_TYPE): New.
* config/tc-mips.c: Use signed add for n32 address arithmetic.
(append_insn): When filling delay slots with instructions
that have fixups that tc_gen_reloc might consider modifyable
in variant frags, start a new frag.
(load_address): Generate GOT_DISP with of without offset
depending on whether symbol is local. For -xgot, use
GOT_PAGE/GOT_OFST or GOT_HI16/GOT_LO16.
(macro) <M_DLA_AB, M_LA_AB>: Likewise.
<M_JAL_A>: In NewABI, use CALL16 or GOT_DISP for small got,
CALL_HI16/CALL_LO16 or GOT_PAGE/GOT_OFST for big got.
<ld_st>: In NewABI with small got, always use
GOT_PAGE/GOT_OFST, with the latter in the load/store
instruction. With big got, use GOT_HI16/GOT_LO16 or
GOT_PAGE/GOT_OFST.
(tc_gen_reloc): Adjust variant frags with GOT_DISP in NewABI.
Add tc_frag_data.tc_fr_offset to addends. Decay CALL16,
GOT_OFST and GOT_DISP to GOT_DISP in NewABI.
(md_convert_frag): Use memmove for safe copying of overlapping
regions.
2003-04-11 03:56:50 +02:00
|
|
|
|
lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16)
|
|
|
|
|
add $tempreg,$tempreg,$gp
|
|
|
|
|
lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16)
|
|
|
|
|
|
|
|
|
|
If we have a small constant, and this is a reference to
|
|
|
|
|
an external symbol, we want
|
|
|
|
|
lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
|
|
|
|
|
add $tempreg,$tempreg,$gp
|
|
|
|
|
lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
|
|
|
|
|
addi $tempreg,$tempreg,<constant>
|
|
|
|
|
|
|
|
|
|
If we have a large constant, and this is a reference to
|
|
|
|
|
an external symbol, we want
|
|
|
|
|
lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
|
|
|
|
|
addu $tempreg,$tempreg,$gp
|
|
|
|
|
lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
|
|
|
|
|
lui $at,<hiconstant>
|
|
|
|
|
addi $at,$at,<loconstant>
|
|
|
|
|
add $tempreg,$tempreg,$at
|
|
|
|
|
|
|
|
|
|
If we have NewABI, and we know it's a local symbol, we want
|
|
|
|
|
lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
|
|
|
|
|
addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST)
|
|
|
|
|
otherwise we have to resort to GOT_HI16/GOT_LO16. */
|
|
|
|
|
|
|
|
|
|
frag_grow (40);
|
|
|
|
|
|
|
|
|
|
frag_now->tc_frag_data.tc_fr_offset =
|
|
|
|
|
expr1.X_add_number = offset_expr.X_add_number;
|
|
|
|
|
offset_expr.X_add_number = 0;
|
|
|
|
|
|
2003-11-18 22:22:57 +01:00
|
|
|
|
if (expr1.X_add_number == 0 && breg == 0
|
|
|
|
|
&& (call || tempreg == PIC_CALL_REG))
|
* config/tc-mips.h (tc_frag_data_type, TC_FRAG_TYPE): New.
* config/tc-mips.c: Use signed add for n32 address arithmetic.
(append_insn): When filling delay slots with instructions
that have fixups that tc_gen_reloc might consider modifyable
in variant frags, start a new frag.
(load_address): Generate GOT_DISP with of without offset
depending on whether symbol is local. For -xgot, use
GOT_PAGE/GOT_OFST or GOT_HI16/GOT_LO16.
(macro) <M_DLA_AB, M_LA_AB>: Likewise.
<M_JAL_A>: In NewABI, use CALL16 or GOT_DISP for small got,
CALL_HI16/CALL_LO16 or GOT_PAGE/GOT_OFST for big got.
<ld_st>: In NewABI with small got, always use
GOT_PAGE/GOT_OFST, with the latter in the load/store
instruction. With big got, use GOT_HI16/GOT_LO16 or
GOT_PAGE/GOT_OFST.
(tc_gen_reloc): Adjust variant frags with GOT_DISP in NewABI.
Add tc_frag_data.tc_fr_offset to addends. Decay CALL16,
GOT_OFST and GOT_DISP to GOT_DISP in NewABI.
(md_convert_frag): Use memmove for safe copying of overlapping
regions.
2003-04-11 03:56:50 +02:00
|
|
|
|
{
|
|
|
|
|
lui_reloc_type = (int) BFD_RELOC_MIPS_CALL_HI16;
|
|
|
|
|
lw_reloc_type = (int) BFD_RELOC_MIPS_CALL_LO16;
|
|
|
|
|
}
|
2003-06-30 14:44:25 +02:00
|
|
|
|
macro_build (NULL, &icnt, &offset_expr, "lui", "t,u",
|
* config/tc-mips.h (tc_frag_data_type, TC_FRAG_TYPE): New.
* config/tc-mips.c: Use signed add for n32 address arithmetic.
(append_insn): When filling delay slots with instructions
that have fixups that tc_gen_reloc might consider modifyable
in variant frags, start a new frag.
(load_address): Generate GOT_DISP with of without offset
depending on whether symbol is local. For -xgot, use
GOT_PAGE/GOT_OFST or GOT_HI16/GOT_LO16.
(macro) <M_DLA_AB, M_LA_AB>: Likewise.
<M_JAL_A>: In NewABI, use CALL16 or GOT_DISP for small got,
CALL_HI16/CALL_LO16 or GOT_PAGE/GOT_OFST for big got.
<ld_st>: In NewABI with small got, always use
GOT_PAGE/GOT_OFST, with the latter in the load/store
instruction. With big got, use GOT_HI16/GOT_LO16 or
GOT_PAGE/GOT_OFST.
(tc_gen_reloc): Adjust variant frags with GOT_DISP in NewABI.
Add tc_frag_data.tc_fr_offset to addends. Decay CALL16,
GOT_OFST and GOT_DISP to GOT_DISP in NewABI.
(md_convert_frag): Use memmove for safe copying of overlapping
regions.
2003-04-11 03:56:50 +02:00
|
|
|
|
tempreg, lui_reloc_type);
|
2003-06-30 14:44:25 +02:00
|
|
|
|
macro_build (NULL, &icnt, NULL, ADDRESS_ADD_INSN, "d,v,t",
|
|
|
|
|
tempreg, tempreg, mips_gp_register);
|
|
|
|
|
macro_build (NULL, &icnt, &offset_expr, ADDRESS_LOAD_INSN,
|
* config/tc-mips.h (tc_frag_data_type, TC_FRAG_TYPE): New.
* config/tc-mips.c: Use signed add for n32 address arithmetic.
(append_insn): When filling delay slots with instructions
that have fixups that tc_gen_reloc might consider modifyable
in variant frags, start a new frag.
(load_address): Generate GOT_DISP with of without offset
depending on whether symbol is local. For -xgot, use
GOT_PAGE/GOT_OFST or GOT_HI16/GOT_LO16.
(macro) <M_DLA_AB, M_LA_AB>: Likewise.
<M_JAL_A>: In NewABI, use CALL16 or GOT_DISP for small got,
CALL_HI16/CALL_LO16 or GOT_PAGE/GOT_OFST for big got.
<ld_st>: In NewABI with small got, always use
GOT_PAGE/GOT_OFST, with the latter in the load/store
instruction. With big got, use GOT_HI16/GOT_LO16 or
GOT_PAGE/GOT_OFST.
(tc_gen_reloc): Adjust variant frags with GOT_DISP in NewABI.
Add tc_frag_data.tc_fr_offset to addends. Decay CALL16,
GOT_OFST and GOT_DISP to GOT_DISP in NewABI.
(md_convert_frag): Use memmove for safe copying of overlapping
regions.
2003-04-11 03:56:50 +02:00
|
|
|
|
"t,o(b)", tempreg, lw_reloc_type, tempreg);
|
|
|
|
|
|
|
|
|
|
if (expr1.X_add_number == 0)
|
|
|
|
|
{
|
|
|
|
|
p = frag_var (rs_machine_dependent, 8, 0,
|
|
|
|
|
RELAX_ENCODE (12, 8, 0, 4, 0,
|
|
|
|
|
mips_opts.warn_about_macros),
|
|
|
|
|
offset_expr.X_add_symbol, 0, NULL);
|
2003-04-25 06:40:09 +02:00
|
|
|
|
}
|
* config/tc-mips.h (tc_frag_data_type, TC_FRAG_TYPE): New.
* config/tc-mips.c: Use signed add for n32 address arithmetic.
(append_insn): When filling delay slots with instructions
that have fixups that tc_gen_reloc might consider modifyable
in variant frags, start a new frag.
(load_address): Generate GOT_DISP with of without offset
depending on whether symbol is local. For -xgot, use
GOT_PAGE/GOT_OFST or GOT_HI16/GOT_LO16.
(macro) <M_DLA_AB, M_LA_AB>: Likewise.
<M_JAL_A>: In NewABI, use CALL16 or GOT_DISP for small got,
CALL_HI16/CALL_LO16 or GOT_PAGE/GOT_OFST for big got.
<ld_st>: In NewABI with small got, always use
GOT_PAGE/GOT_OFST, with the latter in the load/store
instruction. With big got, use GOT_HI16/GOT_LO16 or
GOT_PAGE/GOT_OFST.
(tc_gen_reloc): Adjust variant frags with GOT_DISP in NewABI.
Add tc_frag_data.tc_fr_offset to addends. Decay CALL16,
GOT_OFST and GOT_DISP to GOT_DISP in NewABI.
(md_convert_frag): Use memmove for safe copying of overlapping
regions.
2003-04-11 03:56:50 +02:00
|
|
|
|
else if (expr1.X_add_number >= -0x8000
|
|
|
|
|
&& expr1.X_add_number < 0x8000)
|
|
|
|
|
{
|
2003-06-30 14:44:25 +02:00
|
|
|
|
macro_build (NULL, &icnt, &expr1, ADDRESS_ADDI_INSN, "t,r,j",
|
|
|
|
|
tempreg, tempreg, BFD_RELOC_LO16);
|
* config/tc-mips.h (tc_frag_data_type, TC_FRAG_TYPE): New.
* config/tc-mips.c: Use signed add for n32 address arithmetic.
(append_insn): When filling delay slots with instructions
that have fixups that tc_gen_reloc might consider modifyable
in variant frags, start a new frag.
(load_address): Generate GOT_DISP with of without offset
depending on whether symbol is local. For -xgot, use
GOT_PAGE/GOT_OFST or GOT_HI16/GOT_LO16.
(macro) <M_DLA_AB, M_LA_AB>: Likewise.
<M_JAL_A>: In NewABI, use CALL16 or GOT_DISP for small got,
CALL_HI16/CALL_LO16 or GOT_PAGE/GOT_OFST for big got.
<ld_st>: In NewABI with small got, always use
GOT_PAGE/GOT_OFST, with the latter in the load/store
instruction. With big got, use GOT_HI16/GOT_LO16 or
GOT_PAGE/GOT_OFST.
(tc_gen_reloc): Adjust variant frags with GOT_DISP in NewABI.
Add tc_frag_data.tc_fr_offset to addends. Decay CALL16,
GOT_OFST and GOT_DISP to GOT_DISP in NewABI.
(md_convert_frag): Use memmove for safe copying of overlapping
regions.
2003-04-11 03:56:50 +02:00
|
|
|
|
p = frag_var (rs_machine_dependent, 8, 0,
|
|
|
|
|
RELAX_ENCODE (16, 8, 0, 4, 0,
|
|
|
|
|
mips_opts.warn_about_macros),
|
|
|
|
|
offset_expr.X_add_symbol, 0, NULL);
|
|
|
|
|
}
|
2003-10-01 04:07:48 +02:00
|
|
|
|
else if (IS_SEXT_32BIT_NUM (expr1.X_add_number + 0x8000))
|
* config/tc-mips.h (tc_frag_data_type, TC_FRAG_TYPE): New.
* config/tc-mips.c: Use signed add for n32 address arithmetic.
(append_insn): When filling delay slots with instructions
that have fixups that tc_gen_reloc might consider modifyable
in variant frags, start a new frag.
(load_address): Generate GOT_DISP with of without offset
depending on whether symbol is local. For -xgot, use
GOT_PAGE/GOT_OFST or GOT_HI16/GOT_LO16.
(macro) <M_DLA_AB, M_LA_AB>: Likewise.
<M_JAL_A>: In NewABI, use CALL16 or GOT_DISP for small got,
CALL_HI16/CALL_LO16 or GOT_PAGE/GOT_OFST for big got.
<ld_st>: In NewABI with small got, always use
GOT_PAGE/GOT_OFST, with the latter in the load/store
instruction. With big got, use GOT_HI16/GOT_LO16 or
GOT_PAGE/GOT_OFST.
(tc_gen_reloc): Adjust variant frags with GOT_DISP in NewABI.
Add tc_frag_data.tc_fr_offset to addends. Decay CALL16,
GOT_OFST and GOT_DISP to GOT_DISP in NewABI.
(md_convert_frag): Use memmove for safe copying of overlapping
regions.
2003-04-11 03:56:50 +02:00
|
|
|
|
{
|
|
|
|
|
int dreg;
|
|
|
|
|
|
|
|
|
|
/* If we are going to add in a base register, and the
|
|
|
|
|
target register and the base register are the same,
|
|
|
|
|
then we are using AT as a temporary register. Since
|
|
|
|
|
we want to load the constant into AT, we add our
|
|
|
|
|
current AT (from the global offset table) and the
|
|
|
|
|
register into the register now, and pretend we were
|
|
|
|
|
not using a base register. */
|
|
|
|
|
if (breg != treg)
|
|
|
|
|
dreg = tempreg;
|
|
|
|
|
else
|
|
|
|
|
{
|
|
|
|
|
assert (tempreg == AT);
|
2003-06-30 14:44:25 +02:00
|
|
|
|
macro_build (NULL, &icnt, NULL, ADDRESS_ADD_INSN, "d,v,t",
|
|
|
|
|
treg, AT, breg);
|
* config/tc-mips.h (tc_frag_data_type, TC_FRAG_TYPE): New.
* config/tc-mips.c: Use signed add for n32 address arithmetic.
(append_insn): When filling delay slots with instructions
that have fixups that tc_gen_reloc might consider modifyable
in variant frags, start a new frag.
(load_address): Generate GOT_DISP with of without offset
depending on whether symbol is local. For -xgot, use
GOT_PAGE/GOT_OFST or GOT_HI16/GOT_LO16.
(macro) <M_DLA_AB, M_LA_AB>: Likewise.
<M_JAL_A>: In NewABI, use CALL16 or GOT_DISP for small got,
CALL_HI16/CALL_LO16 or GOT_PAGE/GOT_OFST for big got.
<ld_st>: In NewABI with small got, always use
GOT_PAGE/GOT_OFST, with the latter in the load/store
instruction. With big got, use GOT_HI16/GOT_LO16 or
GOT_PAGE/GOT_OFST.
(tc_gen_reloc): Adjust variant frags with GOT_DISP in NewABI.
Add tc_frag_data.tc_fr_offset to addends. Decay CALL16,
GOT_OFST and GOT_DISP to GOT_DISP in NewABI.
(md_convert_frag): Use memmove for safe copying of overlapping
regions.
2003-04-11 03:56:50 +02:00
|
|
|
|
dreg = treg;
|
|
|
|
|
adj = 4;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/* Set mips_optimize around the lui instruction to avoid
|
|
|
|
|
inserting an unnecessary nop after the lw. */
|
2003-06-30 14:44:25 +02:00
|
|
|
|
macro_build_lui (NULL, &icnt, &expr1, AT);
|
|
|
|
|
macro_build (NULL, &icnt, &expr1, ADDRESS_ADDI_INSN,
|
|
|
|
|
"t,r,j", AT, AT, BFD_RELOC_LO16);
|
|
|
|
|
macro_build (NULL, &icnt, NULL, ADDRESS_ADD_INSN, "d,v,t",
|
|
|
|
|
dreg, dreg, AT);
|
* config/tc-mips.h (tc_frag_data_type, TC_FRAG_TYPE): New.
* config/tc-mips.c: Use signed add for n32 address arithmetic.
(append_insn): When filling delay slots with instructions
that have fixups that tc_gen_reloc might consider modifyable
in variant frags, start a new frag.
(load_address): Generate GOT_DISP with of without offset
depending on whether symbol is local. For -xgot, use
GOT_PAGE/GOT_OFST or GOT_HI16/GOT_LO16.
(macro) <M_DLA_AB, M_LA_AB>: Likewise.
<M_JAL_A>: In NewABI, use CALL16 or GOT_DISP for small got,
CALL_HI16/CALL_LO16 or GOT_PAGE/GOT_OFST for big got.
<ld_st>: In NewABI with small got, always use
GOT_PAGE/GOT_OFST, with the latter in the load/store
instruction. With big got, use GOT_HI16/GOT_LO16 or
GOT_PAGE/GOT_OFST.
(tc_gen_reloc): Adjust variant frags with GOT_DISP in NewABI.
Add tc_frag_data.tc_fr_offset to addends. Decay CALL16,
GOT_OFST and GOT_DISP to GOT_DISP in NewABI.
(md_convert_frag): Use memmove for safe copying of overlapping
regions.
2003-04-11 03:56:50 +02:00
|
|
|
|
|
|
|
|
|
p = frag_var (rs_machine_dependent, 8 + adj, 0,
|
|
|
|
|
RELAX_ENCODE (24 + adj, 8 + adj,
|
|
|
|
|
0, 4, 0,
|
|
|
|
|
(breg == 0
|
|
|
|
|
? mips_opts.warn_about_macros
|
|
|
|
|
: 0)),
|
|
|
|
|
offset_expr.X_add_symbol, 0, NULL);
|
|
|
|
|
|
|
|
|
|
used_at = 1;
|
|
|
|
|
}
|
|
|
|
|
else
|
|
|
|
|
as_bad (_("PIC code offset overflow (max 32 signed bits)"));
|
|
|
|
|
|
|
|
|
|
offset_expr.X_add_number = expr1.X_add_number;
|
2003-06-16 14:13:10 +02:00
|
|
|
|
macro_build (p, &icnt, &offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
|
2003-06-30 14:44:25 +02:00
|
|
|
|
tempreg, BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register);
|
2003-06-16 14:13:10 +02:00
|
|
|
|
macro_build (p + 4, &icnt, &offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
|
2003-06-30 14:44:25 +02:00
|
|
|
|
tempreg, tempreg, BFD_RELOC_MIPS_GOT_OFST);
|
* config/tc-mips.h (tc_frag_data_type, TC_FRAG_TYPE): New.
* config/tc-mips.c: Use signed add for n32 address arithmetic.
(append_insn): When filling delay slots with instructions
that have fixups that tc_gen_reloc might consider modifyable
in variant frags, start a new frag.
(load_address): Generate GOT_DISP with of without offset
depending on whether symbol is local. For -xgot, use
GOT_PAGE/GOT_OFST or GOT_HI16/GOT_LO16.
(macro) <M_DLA_AB, M_LA_AB>: Likewise.
<M_JAL_A>: In NewABI, use CALL16 or GOT_DISP for small got,
CALL_HI16/CALL_LO16 or GOT_PAGE/GOT_OFST for big got.
<ld_st>: In NewABI with small got, always use
GOT_PAGE/GOT_OFST, with the latter in the load/store
instruction. With big got, use GOT_HI16/GOT_LO16 or
GOT_PAGE/GOT_OFST.
(tc_gen_reloc): Adjust variant frags with GOT_DISP in NewABI.
Add tc_frag_data.tc_fr_offset to addends. Decay CALL16,
GOT_OFST and GOT_DISP to GOT_DISP in NewABI.
(md_convert_frag): Use memmove for safe copying of overlapping
regions.
2003-04-11 03:56:50 +02:00
|
|
|
|
if (adj)
|
|
|
|
|
{
|
2003-06-30 14:44:25 +02:00
|
|
|
|
macro_build (p + 8, &icnt, NULL, ADDRESS_ADD_INSN, "d,v,t",
|
|
|
|
|
treg, tempreg, breg);
|
* config/tc-mips.h (tc_frag_data_type, TC_FRAG_TYPE): New.
* config/tc-mips.c: Use signed add for n32 address arithmetic.
(append_insn): When filling delay slots with instructions
that have fixups that tc_gen_reloc might consider modifyable
in variant frags, start a new frag.
(load_address): Generate GOT_DISP with of without offset
depending on whether symbol is local. For -xgot, use
GOT_PAGE/GOT_OFST or GOT_HI16/GOT_LO16.
(macro) <M_DLA_AB, M_LA_AB>: Likewise.
<M_JAL_A>: In NewABI, use CALL16 or GOT_DISP for small got,
CALL_HI16/CALL_LO16 or GOT_PAGE/GOT_OFST for big got.
<ld_st>: In NewABI with small got, always use
GOT_PAGE/GOT_OFST, with the latter in the load/store
instruction. With big got, use GOT_HI16/GOT_LO16 or
GOT_PAGE/GOT_OFST.
(tc_gen_reloc): Adjust variant frags with GOT_DISP in NewABI.
Add tc_frag_data.tc_fr_offset to addends. Decay CALL16,
GOT_OFST and GOT_DISP to GOT_DISP in NewABI.
(md_convert_frag): Use memmove for safe copying of overlapping
regions.
2003-04-11 03:56:50 +02:00
|
|
|
|
breg = 0;
|
|
|
|
|
tempreg = treg;
|
|
|
|
|
}
|
|
|
|
|
}
|
1999-05-03 09:29:11 +02:00
|
|
|
|
else if (mips_pic == EMBEDDED_PIC)
|
|
|
|
|
{
|
|
|
|
|
/* We use
|
2001-12-02 14:14:48 +01:00
|
|
|
|
addiu $tempreg,$gp,<sym> (BFD_RELOC_GPREL16)
|
1999-05-03 09:29:11 +02:00
|
|
|
|
*/
|
2003-06-30 14:44:25 +02:00
|
|
|
|
macro_build (NULL, &icnt, &offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
|
|
|
|
|
tempreg, mips_gp_register, BFD_RELOC_GPREL16);
|
1999-05-03 09:29:11 +02:00
|
|
|
|
}
|
|
|
|
|
else
|
|
|
|
|
abort ();
|
|
|
|
|
|
|
|
|
|
if (breg != 0)
|
2002-02-25 14:21:38 +01:00
|
|
|
|
{
|
|
|
|
|
char *s;
|
|
|
|
|
|
|
|
|
|
if (mips_pic == EMBEDDED_PIC || mips_pic == NO_PIC)
|
2003-06-21 23:38:04 +02:00
|
|
|
|
s = (dbl || HAVE_64BIT_ADDRESSES) ? "daddu" : "addu";
|
2002-02-25 14:21:38 +01:00
|
|
|
|
else
|
2003-06-16 14:13:10 +02:00
|
|
|
|
s = ADDRESS_ADD_INSN;
|
2002-02-25 14:21:38 +01:00
|
|
|
|
|
2003-06-30 14:44:25 +02:00
|
|
|
|
macro_build (NULL, &icnt, NULL, s, "d,v,t", treg, tempreg, breg);
|
2002-02-25 14:21:38 +01:00
|
|
|
|
}
|
1999-05-03 09:29:11 +02:00
|
|
|
|
|
|
|
|
|
if (! used_at)
|
|
|
|
|
return;
|
|
|
|
|
|
|
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
case M_J_A:
|
|
|
|
|
/* The j instruction may not be used in PIC code, since it
|
|
|
|
|
requires an absolute address. We convert it to a b
|
|
|
|
|
instruction. */
|
|
|
|
|
if (mips_pic == NO_PIC)
|
2003-06-30 14:44:25 +02:00
|
|
|
|
macro_build (NULL, &icnt, &offset_expr, "j", "a");
|
1999-05-03 09:29:11 +02:00
|
|
|
|
else
|
2003-06-30 14:44:25 +02:00
|
|
|
|
macro_build (NULL, &icnt, &offset_expr, "b", "p");
|
1999-05-03 09:29:11 +02:00
|
|
|
|
return;
|
|
|
|
|
|
|
|
|
|
/* The jal instructions must be handled as macros because when
|
|
|
|
|
generating PIC code they expand to multi-instruction
|
|
|
|
|
sequences. Normally they are simple instructions. */
|
|
|
|
|
case M_JAL_1:
|
|
|
|
|
dreg = RA;
|
|
|
|
|
/* Fall through. */
|
|
|
|
|
case M_JAL_2:
|
|
|
|
|
if (mips_pic == NO_PIC
|
|
|
|
|
|| mips_pic == EMBEDDED_PIC)
|
2003-06-30 14:44:25 +02:00
|
|
|
|
macro_build (NULL, &icnt, NULL, "jalr", "d,s", dreg, sreg);
|
1999-05-03 09:29:11 +02:00
|
|
|
|
else if (mips_pic == SVR4_PIC)
|
|
|
|
|
{
|
|
|
|
|
if (sreg != PIC_CALL_REG)
|
|
|
|
|
as_warn (_("MIPS PIC call to register other than $25"));
|
2000-09-07 14:45:56 +02:00
|
|
|
|
|
2003-06-30 14:44:25 +02:00
|
|
|
|
macro_build (NULL, &icnt, NULL, "jalr", "d,s", dreg, sreg);
|
2001-10-10 03:08:35 +02:00
|
|
|
|
if (! HAVE_NEWABI)
|
1999-05-03 09:29:11 +02:00
|
|
|
|
{
|
2001-10-10 03:08:35 +02:00
|
|
|
|
if (mips_cprestore_offset < 0)
|
|
|
|
|
as_warn (_("No .cprestore pseudo-op used in PIC code"));
|
|
|
|
|
else
|
|
|
|
|
{
|
2002-01-05 20:06:52 +01:00
|
|
|
|
if (! mips_frame_reg_valid)
|
|
|
|
|
{
|
|
|
|
|
as_warn (_("No .frame pseudo-op used in PIC code"));
|
|
|
|
|
/* Quiet this warning. */
|
|
|
|
|
mips_frame_reg_valid = 1;
|
|
|
|
|
}
|
|
|
|
|
if (! mips_cprestore_valid)
|
|
|
|
|
{
|
|
|
|
|
as_warn (_("No .cprestore pseudo-op used in PIC code"));
|
|
|
|
|
/* Quiet this warning. */
|
|
|
|
|
mips_cprestore_valid = 1;
|
|
|
|
|
}
|
2001-10-10 03:08:35 +02:00
|
|
|
|
expr1.X_add_number = mips_cprestore_offset;
|
2003-06-30 14:44:25 +02:00
|
|
|
|
macro_build_ldst_constoffset (NULL, &icnt, &expr1,
|
2003-06-16 14:13:10 +02:00
|
|
|
|
ADDRESS_LOAD_INSN,
|
|
|
|
|
mips_gp_register,
|
2003-09-14 17:24:49 +02:00
|
|
|
|
mips_frame_reg,
|
|
|
|
|
HAVE_64BIT_ADDRESSES);
|
2001-10-10 03:08:35 +02:00
|
|
|
|
}
|
1999-05-03 09:29:11 +02:00
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
else
|
|
|
|
|
abort ();
|
|
|
|
|
|
|
|
|
|
return;
|
|
|
|
|
|
|
|
|
|
case M_JAL_A:
|
|
|
|
|
if (mips_pic == NO_PIC)
|
2003-06-30 14:44:25 +02:00
|
|
|
|
macro_build (NULL, &icnt, &offset_expr, "jal", "a");
|
1999-05-03 09:29:11 +02:00
|
|
|
|
else if (mips_pic == SVR4_PIC)
|
|
|
|
|
{
|
2002-05-26 20:46:37 +02:00
|
|
|
|
char *p;
|
|
|
|
|
|
1999-05-03 09:29:11 +02:00
|
|
|
|
/* If this is a reference to an external symbol, and we are
|
|
|
|
|
using a small GOT, we want
|
|
|
|
|
lw $25,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
|
|
|
|
|
nop
|
2002-05-26 20:46:37 +02:00
|
|
|
|
jalr $ra,$25
|
1999-05-03 09:29:11 +02:00
|
|
|
|
nop
|
|
|
|
|
lw $gp,cprestore($sp)
|
|
|
|
|
The cprestore value is set using the .cprestore
|
|
|
|
|
pseudo-op. If we are using a big GOT, we want
|
|
|
|
|
lui $25,<sym> (BFD_RELOC_MIPS_CALL_HI16)
|
|
|
|
|
addu $25,$25,$gp
|
|
|
|
|
lw $25,<sym>($25) (BFD_RELOC_MIPS_CALL_LO16)
|
|
|
|
|
nop
|
2002-05-26 20:46:37 +02:00
|
|
|
|
jalr $ra,$25
|
1999-05-03 09:29:11 +02:00
|
|
|
|
nop
|
|
|
|
|
lw $gp,cprestore($sp)
|
|
|
|
|
If the symbol is not external, we want
|
|
|
|
|
lw $25,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
|
|
|
|
|
nop
|
|
|
|
|
addiu $25,$25,<sym> (BFD_RELOC_LO16)
|
2002-05-26 20:46:37 +02:00
|
|
|
|
jalr $ra,$25
|
1999-05-03 09:29:11 +02:00
|
|
|
|
nop
|
2002-05-31 01:32:47 +02:00
|
|
|
|
lw $gp,cprestore($sp)
|
* config/tc-mips.h (tc_frag_data_type, TC_FRAG_TYPE): New.
* config/tc-mips.c: Use signed add for n32 address arithmetic.
(append_insn): When filling delay slots with instructions
that have fixups that tc_gen_reloc might consider modifyable
in variant frags, start a new frag.
(load_address): Generate GOT_DISP with of without offset
depending on whether symbol is local. For -xgot, use
GOT_PAGE/GOT_OFST or GOT_HI16/GOT_LO16.
(macro) <M_DLA_AB, M_LA_AB>: Likewise.
<M_JAL_A>: In NewABI, use CALL16 or GOT_DISP for small got,
CALL_HI16/CALL_LO16 or GOT_PAGE/GOT_OFST for big got.
<ld_st>: In NewABI with small got, always use
GOT_PAGE/GOT_OFST, with the latter in the load/store
instruction. With big got, use GOT_HI16/GOT_LO16 or
GOT_PAGE/GOT_OFST.
(tc_gen_reloc): Adjust variant frags with GOT_DISP in NewABI.
Add tc_frag_data.tc_fr_offset to addends. Decay CALL16,
GOT_OFST and GOT_DISP to GOT_DISP in NewABI.
(md_convert_frag): Use memmove for safe copying of overlapping
regions.
2003-04-11 03:56:50 +02:00
|
|
|
|
|
|
|
|
|
For NewABI, we use the same CALL16 or CALL_HI16/CALL_LO16
|
|
|
|
|
sequences above, minus nops, unless the symbol is local,
|
|
|
|
|
which enables us to use GOT_PAGE/GOT_OFST (big got) or
|
|
|
|
|
GOT_DISP. */
|
2002-05-31 01:32:47 +02:00
|
|
|
|
if (HAVE_NEWABI)
|
1999-05-03 09:29:11 +02:00
|
|
|
|
{
|
* config/tc-mips.h (tc_frag_data_type, TC_FRAG_TYPE): New.
* config/tc-mips.c: Use signed add for n32 address arithmetic.
(append_insn): When filling delay slots with instructions
that have fixups that tc_gen_reloc might consider modifyable
in variant frags, start a new frag.
(load_address): Generate GOT_DISP with of without offset
depending on whether symbol is local. For -xgot, use
GOT_PAGE/GOT_OFST or GOT_HI16/GOT_LO16.
(macro) <M_DLA_AB, M_LA_AB>: Likewise.
<M_JAL_A>: In NewABI, use CALL16 or GOT_DISP for small got,
CALL_HI16/CALL_LO16 or GOT_PAGE/GOT_OFST for big got.
<ld_st>: In NewABI with small got, always use
GOT_PAGE/GOT_OFST, with the latter in the load/store
instruction. With big got, use GOT_HI16/GOT_LO16 or
GOT_PAGE/GOT_OFST.
(tc_gen_reloc): Adjust variant frags with GOT_DISP in NewABI.
Add tc_frag_data.tc_fr_offset to addends. Decay CALL16,
GOT_OFST and GOT_DISP to GOT_DISP in NewABI.
(md_convert_frag): Use memmove for safe copying of overlapping
regions.
2003-04-11 03:56:50 +02:00
|
|
|
|
if (! mips_big_got)
|
|
|
|
|
{
|
|
|
|
|
frag_grow (4);
|
2003-06-30 14:44:25 +02:00
|
|
|
|
macro_build (NULL, &icnt, &offset_expr, ADDRESS_LOAD_INSN,
|
|
|
|
|
"t,o(b)", PIC_CALL_REG, BFD_RELOC_MIPS_CALL16,
|
* config/tc-mips.h (tc_frag_data_type, TC_FRAG_TYPE): New.
* config/tc-mips.c: Use signed add for n32 address arithmetic.
(append_insn): When filling delay slots with instructions
that have fixups that tc_gen_reloc might consider modifyable
in variant frags, start a new frag.
(load_address): Generate GOT_DISP with of without offset
depending on whether symbol is local. For -xgot, use
GOT_PAGE/GOT_OFST or GOT_HI16/GOT_LO16.
(macro) <M_DLA_AB, M_LA_AB>: Likewise.
<M_JAL_A>: In NewABI, use CALL16 or GOT_DISP for small got,
CALL_HI16/CALL_LO16 or GOT_PAGE/GOT_OFST for big got.
<ld_st>: In NewABI with small got, always use
GOT_PAGE/GOT_OFST, with the latter in the load/store
instruction. With big got, use GOT_HI16/GOT_LO16 or
GOT_PAGE/GOT_OFST.
(tc_gen_reloc): Adjust variant frags with GOT_DISP in NewABI.
Add tc_frag_data.tc_fr_offset to addends. Decay CALL16,
GOT_OFST and GOT_DISP to GOT_DISP in NewABI.
(md_convert_frag): Use memmove for safe copying of overlapping
regions.
2003-04-11 03:56:50 +02:00
|
|
|
|
mips_gp_register);
|
|
|
|
|
frag_var (rs_machine_dependent, 0, 0,
|
|
|
|
|
RELAX_ENCODE (0, 0, -4, 0, 0, 0),
|
|
|
|
|
offset_expr.X_add_symbol, 0, NULL);
|
|
|
|
|
}
|
|
|
|
|
else
|
|
|
|
|
{
|
|
|
|
|
frag_grow (20);
|
2003-06-30 14:44:25 +02:00
|
|
|
|
macro_build (NULL, &icnt, &offset_expr, "lui", "t,u",
|
|
|
|
|
PIC_CALL_REG, BFD_RELOC_MIPS_CALL_HI16);
|
|
|
|
|
macro_build (NULL, &icnt, NULL, ADDRESS_ADD_INSN, "d,v,t",
|
|
|
|
|
PIC_CALL_REG, PIC_CALL_REG, mips_gp_register);
|
|
|
|
|
macro_build (NULL, &icnt, &offset_expr, ADDRESS_LOAD_INSN,
|
|
|
|
|
"t,o(b)", PIC_CALL_REG,
|
|
|
|
|
BFD_RELOC_MIPS_CALL_LO16, PIC_CALL_REG);
|
* config/tc-mips.h (tc_frag_data_type, TC_FRAG_TYPE): New.
* config/tc-mips.c: Use signed add for n32 address arithmetic.
(append_insn): When filling delay slots with instructions
that have fixups that tc_gen_reloc might consider modifyable
in variant frags, start a new frag.
(load_address): Generate GOT_DISP with of without offset
depending on whether symbol is local. For -xgot, use
GOT_PAGE/GOT_OFST or GOT_HI16/GOT_LO16.
(macro) <M_DLA_AB, M_LA_AB>: Likewise.
<M_JAL_A>: In NewABI, use CALL16 or GOT_DISP for small got,
CALL_HI16/CALL_LO16 or GOT_PAGE/GOT_OFST for big got.
<ld_st>: In NewABI with small got, always use
GOT_PAGE/GOT_OFST, with the latter in the load/store
instruction. With big got, use GOT_HI16/GOT_LO16 or
GOT_PAGE/GOT_OFST.
(tc_gen_reloc): Adjust variant frags with GOT_DISP in NewABI.
Add tc_frag_data.tc_fr_offset to addends. Decay CALL16,
GOT_OFST and GOT_DISP to GOT_DISP in NewABI.
(md_convert_frag): Use memmove for safe copying of overlapping
regions.
2003-04-11 03:56:50 +02:00
|
|
|
|
p = frag_var (rs_machine_dependent, 8, 0,
|
|
|
|
|
RELAX_ENCODE (12, 8, 0, 4, 0, 0),
|
|
|
|
|
offset_expr.X_add_symbol, 0, NULL);
|
2003-06-16 14:13:10 +02:00
|
|
|
|
macro_build (p, &icnt, &offset_expr, ADDRESS_LOAD_INSN,
|
|
|
|
|
"t,o(b)", PIC_CALL_REG,
|
2003-06-30 14:44:25 +02:00
|
|
|
|
BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register);
|
2003-06-16 14:13:10 +02:00
|
|
|
|
macro_build (p + 4, &icnt, &offset_expr, ADDRESS_ADDI_INSN,
|
2003-05-22 11:15:12 +02:00
|
|
|
|
"t,r,j", PIC_CALL_REG, PIC_CALL_REG,
|
2003-06-30 14:44:25 +02:00
|
|
|
|
BFD_RELOC_MIPS_GOT_OFST);
|
* config/tc-mips.h (tc_frag_data_type, TC_FRAG_TYPE): New.
* config/tc-mips.c: Use signed add for n32 address arithmetic.
(append_insn): When filling delay slots with instructions
that have fixups that tc_gen_reloc might consider modifyable
in variant frags, start a new frag.
(load_address): Generate GOT_DISP with of without offset
depending on whether symbol is local. For -xgot, use
GOT_PAGE/GOT_OFST or GOT_HI16/GOT_LO16.
(macro) <M_DLA_AB, M_LA_AB>: Likewise.
<M_JAL_A>: In NewABI, use CALL16 or GOT_DISP for small got,
CALL_HI16/CALL_LO16 or GOT_PAGE/GOT_OFST for big got.
<ld_st>: In NewABI with small got, always use
GOT_PAGE/GOT_OFST, with the latter in the load/store
instruction. With big got, use GOT_HI16/GOT_LO16 or
GOT_PAGE/GOT_OFST.
(tc_gen_reloc): Adjust variant frags with GOT_DISP in NewABI.
Add tc_frag_data.tc_fr_offset to addends. Decay CALL16,
GOT_OFST and GOT_DISP to GOT_DISP in NewABI.
(md_convert_frag): Use memmove for safe copying of overlapping
regions.
2003-04-11 03:56:50 +02:00
|
|
|
|
}
|
2003-04-25 06:40:09 +02:00
|
|
|
|
|
2002-05-31 01:32:47 +02:00
|
|
|
|
macro_build_jalr (icnt, &offset_expr);
|
1999-05-03 09:29:11 +02:00
|
|
|
|
}
|
|
|
|
|
else
|
|
|
|
|
{
|
2002-05-31 01:32:47 +02:00
|
|
|
|
frag_grow (40);
|
|
|
|
|
if (! mips_big_got)
|
|
|
|
|
{
|
2003-06-30 14:44:25 +02:00
|
|
|
|
macro_build (NULL, &icnt, &offset_expr, ADDRESS_LOAD_INSN,
|
|
|
|
|
"t,o(b)", PIC_CALL_REG, BFD_RELOC_MIPS_CALL16,
|
|
|
|
|
mips_gp_register);
|
|
|
|
|
macro_build (NULL, &icnt, NULL, "nop", "");
|
2002-05-31 01:32:47 +02:00
|
|
|
|
p = frag_var (rs_machine_dependent, 4, 0,
|
|
|
|
|
RELAX_ENCODE (0, 4, -8, 0, 0, 0),
|
|
|
|
|
offset_expr.X_add_symbol, 0, NULL);
|
|
|
|
|
}
|
1999-05-03 09:29:11 +02:00
|
|
|
|
else
|
|
|
|
|
{
|
2002-05-31 01:32:47 +02:00
|
|
|
|
int gpdel;
|
|
|
|
|
|
|
|
|
|
if (reg_needs_delay (mips_gp_register))
|
|
|
|
|
gpdel = 4;
|
|
|
|
|
else
|
|
|
|
|
gpdel = 0;
|
2003-06-30 14:44:25 +02:00
|
|
|
|
macro_build (NULL, &icnt, &offset_expr, "lui", "t,u",
|
|
|
|
|
PIC_CALL_REG, BFD_RELOC_MIPS_CALL_HI16);
|
|
|
|
|
macro_build (NULL, &icnt, NULL, ADDRESS_ADD_INSN, "d,v,t",
|
|
|
|
|
PIC_CALL_REG, PIC_CALL_REG, mips_gp_register);
|
|
|
|
|
macro_build (NULL, &icnt, &offset_expr, ADDRESS_LOAD_INSN,
|
|
|
|
|
"t,o(b)", PIC_CALL_REG,
|
|
|
|
|
BFD_RELOC_MIPS_CALL_LO16, PIC_CALL_REG);
|
|
|
|
|
macro_build (NULL, &icnt, NULL, "nop", "");
|
2002-05-31 01:32:47 +02:00
|
|
|
|
p = frag_var (rs_machine_dependent, 12 + gpdel, 0,
|
|
|
|
|
RELAX_ENCODE (16, 12 + gpdel, gpdel,
|
|
|
|
|
8 + gpdel, 0, 0),
|
|
|
|
|
offset_expr.X_add_symbol, 0, NULL);
|
|
|
|
|
if (gpdel > 0)
|
|
|
|
|
{
|
2003-06-30 14:44:25 +02:00
|
|
|
|
macro_build (p, &icnt, NULL, "nop", "");
|
2002-05-31 01:32:47 +02:00
|
|
|
|
p += 4;
|
|
|
|
|
}
|
2003-06-16 14:13:10 +02:00
|
|
|
|
macro_build (p, &icnt, &offset_expr, ADDRESS_LOAD_INSN,
|
2003-06-30 14:44:25 +02:00
|
|
|
|
"t,o(b)", PIC_CALL_REG, BFD_RELOC_MIPS_GOT16,
|
|
|
|
|
mips_gp_register);
|
2002-05-31 01:32:47 +02:00
|
|
|
|
p += 4;
|
2003-06-30 14:44:25 +02:00
|
|
|
|
macro_build (p, &icnt, NULL, "nop", "");
|
1999-05-03 09:29:11 +02:00
|
|
|
|
p += 4;
|
|
|
|
|
}
|
2003-06-16 14:13:10 +02:00
|
|
|
|
macro_build (p, &icnt, &offset_expr, ADDRESS_ADDI_INSN,
|
2002-05-31 01:32:47 +02:00
|
|
|
|
"t,r,j", PIC_CALL_REG, PIC_CALL_REG,
|
2003-06-30 14:44:25 +02:00
|
|
|
|
BFD_RELOC_LO16);
|
2002-05-31 01:32:47 +02:00
|
|
|
|
macro_build_jalr (icnt, &offset_expr);
|
|
|
|
|
|
2001-10-10 03:08:35 +02:00
|
|
|
|
if (mips_cprestore_offset < 0)
|
|
|
|
|
as_warn (_("No .cprestore pseudo-op used in PIC code"));
|
|
|
|
|
else
|
|
|
|
|
{
|
2002-01-05 20:06:52 +01:00
|
|
|
|
if (! mips_frame_reg_valid)
|
|
|
|
|
{
|
|
|
|
|
as_warn (_("No .frame pseudo-op used in PIC code"));
|
|
|
|
|
/* Quiet this warning. */
|
|
|
|
|
mips_frame_reg_valid = 1;
|
|
|
|
|
}
|
|
|
|
|
if (! mips_cprestore_valid)
|
|
|
|
|
{
|
|
|
|
|
as_warn (_("No .cprestore pseudo-op used in PIC code"));
|
|
|
|
|
/* Quiet this warning. */
|
|
|
|
|
mips_cprestore_valid = 1;
|
|
|
|
|
}
|
2001-10-10 03:08:35 +02:00
|
|
|
|
if (mips_opts.noreorder)
|
2003-06-30 14:44:25 +02:00
|
|
|
|
macro_build (NULL, &icnt, NULL, "nop", "");
|
2001-10-10 03:08:35 +02:00
|
|
|
|
expr1.X_add_number = mips_cprestore_offset;
|
2003-06-30 14:44:25 +02:00
|
|
|
|
macro_build_ldst_constoffset (NULL, &icnt, &expr1,
|
2003-06-16 14:13:10 +02:00
|
|
|
|
ADDRESS_LOAD_INSN,
|
|
|
|
|
mips_gp_register,
|
2003-09-14 17:24:49 +02:00
|
|
|
|
mips_frame_reg,
|
|
|
|
|
HAVE_64BIT_ADDRESSES);
|
2001-10-10 03:08:35 +02:00
|
|
|
|
}
|
1999-05-03 09:29:11 +02:00
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
else if (mips_pic == EMBEDDED_PIC)
|
|
|
|
|
{
|
2003-06-30 14:44:25 +02:00
|
|
|
|
macro_build (NULL, &icnt, &offset_expr, "bal", "p");
|
1999-05-03 09:29:11 +02:00
|
|
|
|
/* The linker may expand the call to a longer sequence which
|
|
|
|
|
uses $at, so we must break rather than return. */
|
|
|
|
|
break;
|
|
|
|
|
}
|
|
|
|
|
else
|
|
|
|
|
abort ();
|
|
|
|
|
|
|
|
|
|
return;
|
|
|
|
|
|
|
|
|
|
case M_LB_AB:
|
|
|
|
|
s = "lb";
|
|
|
|
|
goto ld;
|
|
|
|
|
case M_LBU_AB:
|
|
|
|
|
s = "lbu";
|
|
|
|
|
goto ld;
|
|
|
|
|
case M_LH_AB:
|
|
|
|
|
s = "lh";
|
|
|
|
|
goto ld;
|
|
|
|
|
case M_LHU_AB:
|
|
|
|
|
s = "lhu";
|
|
|
|
|
goto ld;
|
|
|
|
|
case M_LW_AB:
|
|
|
|
|
s = "lw";
|
|
|
|
|
goto ld;
|
|
|
|
|
case M_LWC0_AB:
|
|
|
|
|
s = "lwc0";
|
2000-09-07 14:45:56 +02:00
|
|
|
|
/* Itbl support may require additional care here. */
|
1999-05-03 09:29:11 +02:00
|
|
|
|
coproc = 1;
|
|
|
|
|
goto ld;
|
|
|
|
|
case M_LWC1_AB:
|
|
|
|
|
s = "lwc1";
|
2000-09-07 14:45:56 +02:00
|
|
|
|
/* Itbl support may require additional care here. */
|
1999-05-03 09:29:11 +02:00
|
|
|
|
coproc = 1;
|
|
|
|
|
goto ld;
|
|
|
|
|
case M_LWC2_AB:
|
|
|
|
|
s = "lwc2";
|
2000-09-07 14:45:56 +02:00
|
|
|
|
/* Itbl support may require additional care here. */
|
1999-05-03 09:29:11 +02:00
|
|
|
|
coproc = 1;
|
|
|
|
|
goto ld;
|
|
|
|
|
case M_LWC3_AB:
|
|
|
|
|
s = "lwc3";
|
2000-09-07 14:45:56 +02:00
|
|
|
|
/* Itbl support may require additional care here. */
|
1999-05-03 09:29:11 +02:00
|
|
|
|
coproc = 1;
|
|
|
|
|
goto ld;
|
|
|
|
|
case M_LWL_AB:
|
|
|
|
|
s = "lwl";
|
|
|
|
|
lr = 1;
|
|
|
|
|
goto ld;
|
|
|
|
|
case M_LWR_AB:
|
|
|
|
|
s = "lwr";
|
|
|
|
|
lr = 1;
|
|
|
|
|
goto ld;
|
|
|
|
|
case M_LDC1_AB:
|
2003-06-29 21:41:33 +02:00
|
|
|
|
if (mips_opts.arch == CPU_R4650)
|
1999-05-03 09:29:11 +02:00
|
|
|
|
{
|
|
|
|
|
as_bad (_("opcode not supported on this processor"));
|
|
|
|
|
return;
|
|
|
|
|
}
|
|
|
|
|
s = "ldc1";
|
2000-09-07 14:45:56 +02:00
|
|
|
|
/* Itbl support may require additional care here. */
|
1999-05-03 09:29:11 +02:00
|
|
|
|
coproc = 1;
|
|
|
|
|
goto ld;
|
|
|
|
|
case M_LDC2_AB:
|
|
|
|
|
s = "ldc2";
|
2000-09-07 14:45:56 +02:00
|
|
|
|
/* Itbl support may require additional care here. */
|
1999-05-03 09:29:11 +02:00
|
|
|
|
coproc = 1;
|
|
|
|
|
goto ld;
|
|
|
|
|
case M_LDC3_AB:
|
|
|
|
|
s = "ldc3";
|
2000-09-07 14:45:56 +02:00
|
|
|
|
/* Itbl support may require additional care here. */
|
1999-05-03 09:29:11 +02:00
|
|
|
|
coproc = 1;
|
|
|
|
|
goto ld;
|
|
|
|
|
case M_LDL_AB:
|
|
|
|
|
s = "ldl";
|
|
|
|
|
lr = 1;
|
|
|
|
|
goto ld;
|
|
|
|
|
case M_LDR_AB:
|
|
|
|
|
s = "ldr";
|
|
|
|
|
lr = 1;
|
|
|
|
|
goto ld;
|
|
|
|
|
case M_LL_AB:
|
|
|
|
|
s = "ll";
|
|
|
|
|
goto ld;
|
|
|
|
|
case M_LLD_AB:
|
|
|
|
|
s = "lld";
|
|
|
|
|
goto ld;
|
|
|
|
|
case M_LWU_AB:
|
|
|
|
|
s = "lwu";
|
|
|
|
|
ld:
|
|
|
|
|
if (breg == treg || coproc || lr)
|
|
|
|
|
{
|
|
|
|
|
tempreg = AT;
|
|
|
|
|
used_at = 1;
|
|
|
|
|
}
|
|
|
|
|
else
|
|
|
|
|
{
|
|
|
|
|
tempreg = treg;
|
|
|
|
|
used_at = 0;
|
|
|
|
|
}
|
|
|
|
|
goto ld_st;
|
|
|
|
|
case M_SB_AB:
|
|
|
|
|
s = "sb";
|
|
|
|
|
goto st;
|
|
|
|
|
case M_SH_AB:
|
|
|
|
|
s = "sh";
|
|
|
|
|
goto st;
|
|
|
|
|
case M_SW_AB:
|
|
|
|
|
s = "sw";
|
|
|
|
|
goto st;
|
|
|
|
|
case M_SWC0_AB:
|
|
|
|
|
s = "swc0";
|
2000-09-07 14:45:56 +02:00
|
|
|
|
/* Itbl support may require additional care here. */
|
1999-05-03 09:29:11 +02:00
|
|
|
|
coproc = 1;
|
|
|
|
|
goto st;
|
|
|
|
|
case M_SWC1_AB:
|
|
|
|
|
s = "swc1";
|
2000-09-07 14:45:56 +02:00
|
|
|
|
/* Itbl support may require additional care here. */
|
1999-05-03 09:29:11 +02:00
|
|
|
|
coproc = 1;
|
|
|
|
|
goto st;
|
|
|
|
|
case M_SWC2_AB:
|
|
|
|
|
s = "swc2";
|
2000-09-07 14:45:56 +02:00
|
|
|
|
/* Itbl support may require additional care here. */
|
1999-05-03 09:29:11 +02:00
|
|
|
|
coproc = 1;
|
|
|
|
|
goto st;
|
|
|
|
|
case M_SWC3_AB:
|
|
|
|
|
s = "swc3";
|
2000-09-07 14:45:56 +02:00
|
|
|
|
/* Itbl support may require additional care here. */
|
1999-05-03 09:29:11 +02:00
|
|
|
|
coproc = 1;
|
|
|
|
|
goto st;
|
|
|
|
|
case M_SWL_AB:
|
|
|
|
|
s = "swl";
|
|
|
|
|
goto st;
|
|
|
|
|
case M_SWR_AB:
|
|
|
|
|
s = "swr";
|
|
|
|
|
goto st;
|
|
|
|
|
case M_SC_AB:
|
|
|
|
|
s = "sc";
|
|
|
|
|
goto st;
|
|
|
|
|
case M_SCD_AB:
|
|
|
|
|
s = "scd";
|
|
|
|
|
goto st;
|
|
|
|
|
case M_SDC1_AB:
|
2003-06-29 21:41:33 +02:00
|
|
|
|
if (mips_opts.arch == CPU_R4650)
|
1999-05-03 09:29:11 +02:00
|
|
|
|
{
|
|
|
|
|
as_bad (_("opcode not supported on this processor"));
|
|
|
|
|
return;
|
|
|
|
|
}
|
|
|
|
|
s = "sdc1";
|
|
|
|
|
coproc = 1;
|
2000-09-07 14:45:56 +02:00
|
|
|
|
/* Itbl support may require additional care here. */
|
1999-05-03 09:29:11 +02:00
|
|
|
|
goto st;
|
|
|
|
|
case M_SDC2_AB:
|
|
|
|
|
s = "sdc2";
|
2000-09-07 14:45:56 +02:00
|
|
|
|
/* Itbl support may require additional care here. */
|
1999-05-03 09:29:11 +02:00
|
|
|
|
coproc = 1;
|
|
|
|
|
goto st;
|
|
|
|
|
case M_SDC3_AB:
|
|
|
|
|
s = "sdc3";
|
2000-09-07 14:45:56 +02:00
|
|
|
|
/* Itbl support may require additional care here. */
|
1999-05-03 09:29:11 +02:00
|
|
|
|
coproc = 1;
|
|
|
|
|
goto st;
|
|
|
|
|
case M_SDL_AB:
|
|
|
|
|
s = "sdl";
|
|
|
|
|
goto st;
|
|
|
|
|
case M_SDR_AB:
|
|
|
|
|
s = "sdr";
|
|
|
|
|
st:
|
|
|
|
|
tempreg = AT;
|
|
|
|
|
used_at = 1;
|
|
|
|
|
ld_st:
|
2000-09-07 14:45:56 +02:00
|
|
|
|
/* Itbl support may require additional care here. */
|
1999-05-03 09:29:11 +02:00
|
|
|
|
if (mask == M_LWC1_AB
|
|
|
|
|
|| mask == M_SWC1_AB
|
|
|
|
|
|| mask == M_LDC1_AB
|
|
|
|
|
|| mask == M_SDC1_AB
|
|
|
|
|
|| mask == M_L_DAB
|
|
|
|
|
|| mask == M_S_DAB)
|
|
|
|
|
fmt = "T,o(b)";
|
|
|
|
|
else if (coproc)
|
|
|
|
|
fmt = "E,o(b)";
|
|
|
|
|
else
|
|
|
|
|
fmt = "t,o(b)";
|
|
|
|
|
|
2003-09-14 17:24:49 +02:00
|
|
|
|
/* Sign-extending 32-bit constants makes their handling easier.
|
|
|
|
|
The HAVE_64BIT_GPRS... part is due to the linux kernel hack
|
|
|
|
|
described below. */
|
|
|
|
|
if ((! HAVE_64BIT_ADDRESSES
|
|
|
|
|
&& (! HAVE_64BIT_GPRS && offset_expr.X_op == O_constant))
|
2003-10-01 20:57:16 +02:00
|
|
|
|
&& (offset_expr.X_op == O_constant)
|
|
|
|
|
&& ! ((offset_expr.X_add_number & ~((bfd_vma) 0x7fffffff))
|
|
|
|
|
== ~((bfd_vma) 0x7fffffff)))
|
2003-09-18 07:20:04 +02:00
|
|
|
|
{
|
2003-10-01 20:57:16 +02:00
|
|
|
|
if (offset_expr.X_add_number & ~((bfd_vma) 0xffffffff))
|
2003-10-15 13:12:53 +02:00
|
|
|
|
as_bad (_("constant too large"));
|
2003-09-18 07:20:04 +02:00
|
|
|
|
|
2003-10-15 13:12:53 +02:00
|
|
|
|
offset_expr.X_add_number = (((offset_expr.X_add_number & 0xffffffff)
|
|
|
|
|
^ 0x80000000) - 0x80000000);
|
2003-09-18 07:20:04 +02:00
|
|
|
|
}
|
2003-09-14 17:24:49 +02:00
|
|
|
|
|
2001-11-01 02:33:47 +01:00
|
|
|
|
/* For embedded PIC, we allow loads where the offset is calculated
|
|
|
|
|
by subtracting a symbol in the current segment from an unknown
|
|
|
|
|
symbol, relative to a base register, e.g.:
|
|
|
|
|
<op> $treg, <sym>-<localsym>($breg)
|
|
|
|
|
This is used by the compiler for switch statements. */
|
2001-11-06 22:39:09 +01:00
|
|
|
|
if (mips_pic == EMBEDDED_PIC
|
2001-11-01 02:33:47 +01:00
|
|
|
|
&& offset_expr.X_op == O_subtract
|
|
|
|
|
&& (symbol_constant_p (offset_expr.X_op_symbol)
|
|
|
|
|
? S_GET_SEGMENT (offset_expr.X_op_symbol) == now_seg
|
|
|
|
|
: (symbol_equated_p (offset_expr.X_op_symbol)
|
|
|
|
|
&& (S_GET_SEGMENT
|
|
|
|
|
(symbol_get_value_expression (offset_expr.X_op_symbol)
|
|
|
|
|
->X_add_symbol)
|
|
|
|
|
== now_seg)))
|
|
|
|
|
&& breg != 0
|
|
|
|
|
&& (offset_expr.X_add_number == 0
|
|
|
|
|
|| OUTPUT_FLAVOR == bfd_target_elf_flavour))
|
|
|
|
|
{
|
|
|
|
|
/* For this case, we output the instructions:
|
|
|
|
|
lui $tempreg,<sym> (BFD_RELOC_PCREL_HI16_S)
|
|
|
|
|
addiu $tempreg,$tempreg,$breg
|
|
|
|
|
<op> $treg,<sym>($tempreg) (BFD_RELOC_PCREL_LO16)
|
|
|
|
|
If the relocation would fit entirely in 16 bits, it would be
|
|
|
|
|
nice to emit:
|
|
|
|
|
<op> $treg,<sym>($breg) (BFD_RELOC_PCREL_LO16)
|
|
|
|
|
instead, but that seems quite difficult. */
|
2003-06-30 14:44:25 +02:00
|
|
|
|
macro_build (NULL, &icnt, &offset_expr, "lui", "t,u", tempreg,
|
|
|
|
|
BFD_RELOC_PCREL_HI16_S);
|
|
|
|
|
macro_build (NULL, &icnt, NULL,
|
2001-11-01 02:33:47 +01:00
|
|
|
|
((bfd_arch_bits_per_address (stdoutput) == 32
|
|
|
|
|
|| ! ISA_HAS_64BIT_REGS (mips_opts.isa))
|
2003-06-21 23:38:04 +02:00
|
|
|
|
? "addu" : "daddu"),
|
2001-11-01 02:33:47 +01:00
|
|
|
|
"d,v,t", tempreg, tempreg, breg);
|
2003-06-30 14:44:25 +02:00
|
|
|
|
macro_build (NULL, &icnt, &offset_expr, s, fmt, treg,
|
|
|
|
|
BFD_RELOC_PCREL_LO16, tempreg);
|
2001-11-01 02:33:47 +01:00
|
|
|
|
if (! used_at)
|
|
|
|
|
return;
|
|
|
|
|
break;
|
|
|
|
|
}
|
|
|
|
|
|
1999-05-03 09:29:11 +02:00
|
|
|
|
if (offset_expr.X_op != O_constant
|
|
|
|
|
&& offset_expr.X_op != O_symbol)
|
|
|
|
|
{
|
|
|
|
|
as_bad (_("expression too complex"));
|
|
|
|
|
offset_expr.X_op = O_constant;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/* A constant expression in PIC code can be handled just as it
|
|
|
|
|
is in non PIC code. */
|
|
|
|
|
if (mips_pic == NO_PIC
|
|
|
|
|
|| offset_expr.X_op == O_constant)
|
|
|
|
|
{
|
2002-05-26 20:46:37 +02:00
|
|
|
|
char *p;
|
|
|
|
|
|
1999-05-03 09:29:11 +02:00
|
|
|
|
/* If this is a reference to a GP relative symbol, and there
|
|
|
|
|
is no base register, we want
|
2001-12-02 14:14:48 +01:00
|
|
|
|
<op> $treg,<sym>($gp) (BFD_RELOC_GPREL16)
|
1999-05-03 09:29:11 +02:00
|
|
|
|
Otherwise, if there is no base register, we want
|
|
|
|
|
lui $tempreg,<sym> (BFD_RELOC_HI16_S)
|
|
|
|
|
<op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
|
|
|
|
|
If we have a constant, we need two instructions anyhow,
|
|
|
|
|
so we always use the latter form.
|
|
|
|
|
|
|
|
|
|
If we have a base register, and this is a reference to a
|
|
|
|
|
GP relative symbol, we want
|
|
|
|
|
addu $tempreg,$breg,$gp
|
2001-12-02 14:14:48 +01:00
|
|
|
|
<op> $treg,<sym>($tempreg) (BFD_RELOC_GPREL16)
|
1999-05-03 09:29:11 +02:00
|
|
|
|
Otherwise we want
|
|
|
|
|
lui $tempreg,<sym> (BFD_RELOC_HI16_S)
|
|
|
|
|
addu $tempreg,$tempreg,$breg
|
|
|
|
|
<op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
|
2001-10-10 02:43:36 +02:00
|
|
|
|
With a constant we always use the latter case.
|
2001-11-06 22:39:09 +01:00
|
|
|
|
|
2001-10-10 02:43:36 +02:00
|
|
|
|
With 64bit address space and no base register and $at usable,
|
|
|
|
|
we want
|
|
|
|
|
lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
|
|
|
|
|
lui $at,<sym> (BFD_RELOC_HI16_S)
|
|
|
|
|
daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
|
|
|
|
|
dsll32 $tempreg,0
|
|
|
|
|
daddu $tempreg,$at
|
|
|
|
|
<op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
|
|
|
|
|
If we have a base register, we want
|
|
|
|
|
lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
|
|
|
|
|
lui $at,<sym> (BFD_RELOC_HI16_S)
|
|
|
|
|
daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
|
|
|
|
|
daddu $at,$breg
|
|
|
|
|
dsll32 $tempreg,0
|
|
|
|
|
daddu $tempreg,$at
|
|
|
|
|
<op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
|
|
|
|
|
|
|
|
|
|
Without $at we can't generate the optimal path for superscalar
|
|
|
|
|
processors here since this would require two temporary registers.
|
|
|
|
|
lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
|
|
|
|
|
daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
|
|
|
|
|
dsll $tempreg,16
|
|
|
|
|
daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
|
|
|
|
|
dsll $tempreg,16
|
|
|
|
|
<op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
|
|
|
|
|
If we have a base register, we want
|
|
|
|
|
lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
|
|
|
|
|
daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
|
|
|
|
|
dsll $tempreg,16
|
|
|
|
|
daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
|
|
|
|
|
dsll $tempreg,16
|
|
|
|
|
daddu $tempreg,$tempreg,$breg
|
|
|
|
|
<op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
|
2002-02-08 23:25:36 +01:00
|
|
|
|
|
|
|
|
|
If we have 64-bit addresses, as an optimization, for
|
|
|
|
|
addresses which are 32-bit constants (e.g. kseg0/kseg1
|
|
|
|
|
addresses) we fall back to the 32-bit address generation
|
2002-07-09 02:42:57 +02:00
|
|
|
|
mechanism since it is more efficient. Note that due to
|
|
|
|
|
the signed offset used by memory operations, the 32-bit
|
|
|
|
|
range is shifted down by 32768 here. This code should
|
2002-02-08 23:25:36 +01:00
|
|
|
|
probably attempt to generate 64-bit constants more
|
|
|
|
|
efficiently in general.
|
2003-04-09 05:09:12 +02:00
|
|
|
|
|
|
|
|
|
As an extension for architectures with 64-bit registers,
|
|
|
|
|
we don't truncate 64-bit addresses given as literal
|
|
|
|
|
constants down to 32 bits, to support existing practice
|
|
|
|
|
in the mips64 Linux (the kernel), that compiles source
|
|
|
|
|
files with -mabi=64, assembling them as o32 or n32 (with
|
|
|
|
|
-Wa,-32 or -Wa,-n32). This is not beautiful, but since
|
|
|
|
|
the whole kernel is loaded into a memory region that is
|
2003-11-22 03:35:31 +01:00
|
|
|
|
addressable with sign-extended 32-bit addresses, it is
|
2003-04-09 05:09:12 +02:00
|
|
|
|
wasteful to compute the upper 32 bits of every
|
|
|
|
|
non-literal address, that takes more space and time.
|
|
|
|
|
Some day this should probably be implemented as an
|
|
|
|
|
assembler option, such that the kernel doesn't have to
|
|
|
|
|
use such ugly hacks, even though it will still have to
|
|
|
|
|
end up converting the binary to ELF32 for a number of
|
|
|
|
|
platforms whose boot loaders don't support ELF64
|
|
|
|
|
binaries. */
|
2003-09-14 17:24:49 +02:00
|
|
|
|
if ((HAVE_64BIT_ADDRESSES
|
|
|
|
|
&& ! (offset_expr.X_op == O_constant
|
|
|
|
|
&& IS_SEXT_32BIT_NUM (offset_expr.X_add_number + 0x8000)))
|
|
|
|
|
|| (HAVE_64BIT_GPRS
|
|
|
|
|
&& offset_expr.X_op == O_constant
|
|
|
|
|
&& ! IS_SEXT_32BIT_NUM (offset_expr.X_add_number + 0x8000)))
|
2001-10-10 02:43:36 +02:00
|
|
|
|
{
|
|
|
|
|
p = NULL;
|
|
|
|
|
|
|
|
|
|
/* We don't do GP optimization for now because RELAX_ENCODE can't
|
|
|
|
|
hold the data for such large chunks. */
|
|
|
|
|
|
2002-07-30 21:27:31 +02:00
|
|
|
|
if (used_at == 0 && ! mips_opts.noat)
|
2001-10-10 02:43:36 +02:00
|
|
|
|
{
|
|
|
|
|
macro_build (p, &icnt, &offset_expr, "lui", "t,u",
|
2003-06-30 14:44:25 +02:00
|
|
|
|
tempreg, BFD_RELOC_MIPS_HIGHEST);
|
2001-10-10 02:43:36 +02:00
|
|
|
|
macro_build (p, &icnt, &offset_expr, "lui", "t,u",
|
2003-06-30 14:44:25 +02:00
|
|
|
|
AT, BFD_RELOC_HI16_S);
|
2001-10-10 02:43:36 +02:00
|
|
|
|
macro_build (p, &icnt, &offset_expr, "daddiu", "t,r,j",
|
2003-06-30 14:44:25 +02:00
|
|
|
|
tempreg, tempreg, BFD_RELOC_MIPS_HIGHER);
|
2001-10-10 02:43:36 +02:00
|
|
|
|
if (breg != 0)
|
2003-06-30 14:44:25 +02:00
|
|
|
|
macro_build (p, &icnt, NULL, "daddu", "d,v,t",
|
|
|
|
|
AT, AT, breg);
|
|
|
|
|
macro_build (p, &icnt, NULL, "dsll32", "d,w,<",
|
|
|
|
|
tempreg, tempreg, 0);
|
|
|
|
|
macro_build (p, &icnt, NULL, "daddu", "d,v,t",
|
|
|
|
|
tempreg, tempreg, AT);
|
|
|
|
|
macro_build (p, &icnt, &offset_expr, s, fmt, treg,
|
|
|
|
|
BFD_RELOC_LO16, tempreg);
|
2001-10-10 02:43:36 +02:00
|
|
|
|
used_at = 1;
|
|
|
|
|
}
|
|
|
|
|
else
|
|
|
|
|
{
|
|
|
|
|
macro_build (p, &icnt, &offset_expr, "lui", "t,u",
|
2003-06-30 14:44:25 +02:00
|
|
|
|
tempreg, BFD_RELOC_MIPS_HIGHEST);
|
2001-10-10 02:43:36 +02:00
|
|
|
|
macro_build (p, &icnt, &offset_expr, "daddiu", "t,r,j",
|
2003-06-30 14:44:25 +02:00
|
|
|
|
tempreg, tempreg, BFD_RELOC_MIPS_HIGHER);
|
|
|
|
|
macro_build (p, &icnt, NULL, "dsll", "d,w,<",
|
|
|
|
|
tempreg, tempreg, 16);
|
2001-10-10 02:43:36 +02:00
|
|
|
|
macro_build (p, &icnt, &offset_expr, "daddiu", "t,r,j",
|
2003-06-30 14:44:25 +02:00
|
|
|
|
tempreg, tempreg, BFD_RELOC_HI16_S);
|
|
|
|
|
macro_build (p, &icnt, NULL, "dsll", "d,w,<",
|
|
|
|
|
tempreg, tempreg, 16);
|
2001-10-10 02:43:36 +02:00
|
|
|
|
if (breg != 0)
|
2003-06-30 14:44:25 +02:00
|
|
|
|
macro_build (p, &icnt, NULL, "daddu", "d,v,t",
|
|
|
|
|
tempreg, tempreg, breg);
|
|
|
|
|
macro_build (p, &icnt, &offset_expr, s, fmt, treg,
|
|
|
|
|
BFD_RELOC_LO16, tempreg);
|
2001-10-10 02:43:36 +02:00
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
return;
|
|
|
|
|
}
|
2003-09-14 17:24:49 +02:00
|
|
|
|
|
|
|
|
|
if (offset_expr.X_op == O_constant
|
2003-10-01 04:07:48 +02:00
|
|
|
|
&& ! IS_SEXT_32BIT_NUM (offset_expr.X_add_number + 0x8000))
|
2003-04-06 05:16:20 +02:00
|
|
|
|
as_bad (_("load/store address overflow (max 32 bits)"));
|
2001-11-06 22:39:09 +01:00
|
|
|
|
|
1999-05-03 09:29:11 +02:00
|
|
|
|
if (breg == 0)
|
|
|
|
|
{
|
2001-08-26 12:42:12 +02:00
|
|
|
|
if ((valueT) offset_expr.X_add_number > MAX_GPREL_OFFSET
|
1999-05-03 09:29:11 +02:00
|
|
|
|
|| nopic_need_relax (offset_expr.X_add_symbol, 1))
|
|
|
|
|
p = NULL;
|
|
|
|
|
else
|
|
|
|
|
{
|
|
|
|
|
frag_grow (20);
|
2003-06-30 14:44:25 +02:00
|
|
|
|
macro_build (NULL, &icnt, &offset_expr, s, fmt, treg,
|
|
|
|
|
BFD_RELOC_GPREL16, mips_gp_register);
|
1999-05-03 09:29:11 +02:00
|
|
|
|
p = frag_var (rs_machine_dependent, 8, 0,
|
|
|
|
|
RELAX_ENCODE (4, 8, 0, 4, 0,
|
|
|
|
|
(mips_opts.warn_about_macros
|
|
|
|
|
|| (used_at
|
|
|
|
|
&& mips_opts.noat))),
|
2001-12-04 15:38:48 +01:00
|
|
|
|
offset_expr.X_add_symbol, 0, NULL);
|
1999-05-03 09:29:11 +02:00
|
|
|
|
used_at = 0;
|
|
|
|
|
}
|
|
|
|
|
macro_build_lui (p, &icnt, &offset_expr, tempreg);
|
|
|
|
|
if (p != NULL)
|
|
|
|
|
p += 4;
|
|
|
|
|
macro_build (p, &icnt, &offset_expr, s, fmt, treg,
|
2003-06-30 14:44:25 +02:00
|
|
|
|
BFD_RELOC_LO16, tempreg);
|
1999-05-03 09:29:11 +02:00
|
|
|
|
}
|
|
|
|
|
else
|
|
|
|
|
{
|
2001-08-26 12:42:12 +02:00
|
|
|
|
if ((valueT) offset_expr.X_add_number > MAX_GPREL_OFFSET
|
1999-05-03 09:29:11 +02:00
|
|
|
|
|| nopic_need_relax (offset_expr.X_add_symbol, 1))
|
|
|
|
|
p = NULL;
|
|
|
|
|
else
|
|
|
|
|
{
|
|
|
|
|
frag_grow (28);
|
2003-06-30 14:44:25 +02:00
|
|
|
|
macro_build (NULL, &icnt, NULL, ADDRESS_ADD_INSN, "d,v,t",
|
|
|
|
|
tempreg, breg, mips_gp_register);
|
|
|
|
|
macro_build (NULL, &icnt, &offset_expr, s, fmt, treg,
|
|
|
|
|
BFD_RELOC_GPREL16, tempreg);
|
1999-05-03 09:29:11 +02:00
|
|
|
|
p = frag_var (rs_machine_dependent, 12, 0,
|
|
|
|
|
RELAX_ENCODE (8, 12, 0, 8, 0, 0),
|
2001-12-04 15:38:48 +01:00
|
|
|
|
offset_expr.X_add_symbol, 0, NULL);
|
1999-05-03 09:29:11 +02:00
|
|
|
|
}
|
|
|
|
|
macro_build_lui (p, &icnt, &offset_expr, tempreg);
|
|
|
|
|
if (p != NULL)
|
|
|
|
|
p += 4;
|
2003-06-30 14:44:25 +02:00
|
|
|
|
macro_build (p, &icnt, NULL, ADDRESS_ADD_INSN, "d,v,t",
|
|
|
|
|
tempreg, tempreg, breg);
|
1999-05-03 09:29:11 +02:00
|
|
|
|
if (p != NULL)
|
|
|
|
|
p += 4;
|
|
|
|
|
macro_build (p, &icnt, &offset_expr, s, fmt, treg,
|
2003-06-30 14:44:25 +02:00
|
|
|
|
BFD_RELOC_LO16, tempreg);
|
1999-05-03 09:29:11 +02:00
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
else if (mips_pic == SVR4_PIC && ! mips_big_got)
|
|
|
|
|
{
|
2002-05-26 20:46:37 +02:00
|
|
|
|
char *p;
|
2002-09-18 04:25:19 +02:00
|
|
|
|
int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT16;
|
2002-05-26 20:46:37 +02:00
|
|
|
|
|
1999-05-03 09:29:11 +02:00
|
|
|
|
/* If this is a reference to an external symbol, we want
|
|
|
|
|
lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
|
|
|
|
|
nop
|
|
|
|
|
<op> $treg,0($tempreg)
|
|
|
|
|
Otherwise we want
|
|
|
|
|
lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
|
|
|
|
|
nop
|
|
|
|
|
addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
|
|
|
|
|
<op> $treg,0($tempreg)
|
* config/tc-mips.h (tc_frag_data_type, TC_FRAG_TYPE): New.
* config/tc-mips.c: Use signed add for n32 address arithmetic.
(append_insn): When filling delay slots with instructions
that have fixups that tc_gen_reloc might consider modifyable
in variant frags, start a new frag.
(load_address): Generate GOT_DISP with of without offset
depending on whether symbol is local. For -xgot, use
GOT_PAGE/GOT_OFST or GOT_HI16/GOT_LO16.
(macro) <M_DLA_AB, M_LA_AB>: Likewise.
<M_JAL_A>: In NewABI, use CALL16 or GOT_DISP for small got,
CALL_HI16/CALL_LO16 or GOT_PAGE/GOT_OFST for big got.
<ld_st>: In NewABI with small got, always use
GOT_PAGE/GOT_OFST, with the latter in the load/store
instruction. With big got, use GOT_HI16/GOT_LO16 or
GOT_PAGE/GOT_OFST.
(tc_gen_reloc): Adjust variant frags with GOT_DISP in NewABI.
Add tc_frag_data.tc_fr_offset to addends. Decay CALL16,
GOT_OFST and GOT_DISP to GOT_DISP in NewABI.
(md_convert_frag): Use memmove for safe copying of overlapping
regions.
2003-04-11 03:56:50 +02:00
|
|
|
|
|
|
|
|
|
For NewABI, we want
|
|
|
|
|
lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
|
|
|
|
|
<op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST)
|
|
|
|
|
|
1999-05-03 09:29:11 +02:00
|
|
|
|
If there is a base register, we add it to $tempreg before
|
|
|
|
|
the <op>. If there is a constant, we stick it in the
|
|
|
|
|
<op> instruction. We don't handle constants larger than
|
|
|
|
|
16 bits, because we have no way to load the upper 16 bits
|
|
|
|
|
(actually, we could handle them for the subset of cases
|
|
|
|
|
in which we are not using $at). */
|
|
|
|
|
assert (offset_expr.X_op == O_symbol);
|
* config/tc-mips.h (tc_frag_data_type, TC_FRAG_TYPE): New.
* config/tc-mips.c: Use signed add for n32 address arithmetic.
(append_insn): When filling delay slots with instructions
that have fixups that tc_gen_reloc might consider modifyable
in variant frags, start a new frag.
(load_address): Generate GOT_DISP with of without offset
depending on whether symbol is local. For -xgot, use
GOT_PAGE/GOT_OFST or GOT_HI16/GOT_LO16.
(macro) <M_DLA_AB, M_LA_AB>: Likewise.
<M_JAL_A>: In NewABI, use CALL16 or GOT_DISP for small got,
CALL_HI16/CALL_LO16 or GOT_PAGE/GOT_OFST for big got.
<ld_st>: In NewABI with small got, always use
GOT_PAGE/GOT_OFST, with the latter in the load/store
instruction. With big got, use GOT_HI16/GOT_LO16 or
GOT_PAGE/GOT_OFST.
(tc_gen_reloc): Adjust variant frags with GOT_DISP in NewABI.
Add tc_frag_data.tc_fr_offset to addends. Decay CALL16,
GOT_OFST and GOT_DISP to GOT_DISP in NewABI.
(md_convert_frag): Use memmove for safe copying of overlapping
regions.
2003-04-11 03:56:50 +02:00
|
|
|
|
if (HAVE_NEWABI)
|
|
|
|
|
{
|
2003-06-30 14:44:25 +02:00
|
|
|
|
macro_build (NULL, &icnt, &offset_expr, ADDRESS_LOAD_INSN,
|
|
|
|
|
"t,o(b)", tempreg, BFD_RELOC_MIPS_GOT_PAGE,
|
|
|
|
|
mips_gp_register);
|
* config/tc-mips.h (tc_frag_data_type, TC_FRAG_TYPE): New.
* config/tc-mips.c: Use signed add for n32 address arithmetic.
(append_insn): When filling delay slots with instructions
that have fixups that tc_gen_reloc might consider modifyable
in variant frags, start a new frag.
(load_address): Generate GOT_DISP with of without offset
depending on whether symbol is local. For -xgot, use
GOT_PAGE/GOT_OFST or GOT_HI16/GOT_LO16.
(macro) <M_DLA_AB, M_LA_AB>: Likewise.
<M_JAL_A>: In NewABI, use CALL16 or GOT_DISP for small got,
CALL_HI16/CALL_LO16 or GOT_PAGE/GOT_OFST for big got.
<ld_st>: In NewABI with small got, always use
GOT_PAGE/GOT_OFST, with the latter in the load/store
instruction. With big got, use GOT_HI16/GOT_LO16 or
GOT_PAGE/GOT_OFST.
(tc_gen_reloc): Adjust variant frags with GOT_DISP in NewABI.
Add tc_frag_data.tc_fr_offset to addends. Decay CALL16,
GOT_OFST and GOT_DISP to GOT_DISP in NewABI.
(md_convert_frag): Use memmove for safe copying of overlapping
regions.
2003-04-11 03:56:50 +02:00
|
|
|
|
if (breg != 0)
|
2003-06-30 14:44:25 +02:00
|
|
|
|
macro_build (NULL, &icnt, NULL, ADDRESS_ADD_INSN, "d,v,t",
|
|
|
|
|
tempreg, tempreg, breg);
|
|
|
|
|
macro_build (NULL, &icnt, &offset_expr, s, fmt, treg,
|
|
|
|
|
BFD_RELOC_MIPS_GOT_OFST, tempreg);
|
* config/tc-mips.h (tc_frag_data_type, TC_FRAG_TYPE): New.
* config/tc-mips.c: Use signed add for n32 address arithmetic.
(append_insn): When filling delay slots with instructions
that have fixups that tc_gen_reloc might consider modifyable
in variant frags, start a new frag.
(load_address): Generate GOT_DISP with of without offset
depending on whether symbol is local. For -xgot, use
GOT_PAGE/GOT_OFST or GOT_HI16/GOT_LO16.
(macro) <M_DLA_AB, M_LA_AB>: Likewise.
<M_JAL_A>: In NewABI, use CALL16 or GOT_DISP for small got,
CALL_HI16/CALL_LO16 or GOT_PAGE/GOT_OFST for big got.
<ld_st>: In NewABI with small got, always use
GOT_PAGE/GOT_OFST, with the latter in the load/store
instruction. With big got, use GOT_HI16/GOT_LO16 or
GOT_PAGE/GOT_OFST.
(tc_gen_reloc): Adjust variant frags with GOT_DISP in NewABI.
Add tc_frag_data.tc_fr_offset to addends. Decay CALL16,
GOT_OFST and GOT_DISP to GOT_DISP in NewABI.
(md_convert_frag): Use memmove for safe copying of overlapping
regions.
2003-04-11 03:56:50 +02:00
|
|
|
|
|
|
|
|
|
if (! used_at)
|
|
|
|
|
return;
|
|
|
|
|
|
|
|
|
|
break;
|
|
|
|
|
}
|
1999-05-03 09:29:11 +02:00
|
|
|
|
expr1.X_add_number = offset_expr.X_add_number;
|
|
|
|
|
offset_expr.X_add_number = 0;
|
|
|
|
|
if (expr1.X_add_number < -0x8000
|
|
|
|
|
|| expr1.X_add_number >= 0x8000)
|
|
|
|
|
as_bad (_("PIC code offset overflow (max 16 signed bits)"));
|
|
|
|
|
frag_grow (20);
|
2003-06-30 14:44:25 +02:00
|
|
|
|
macro_build (NULL, &icnt, &offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
|
|
|
|
|
tempreg, lw_reloc_type, mips_gp_register);
|
|
|
|
|
macro_build (NULL, &icnt, NULL, "nop", "");
|
2000-09-07 14:45:56 +02:00
|
|
|
|
p = frag_var (rs_machine_dependent, 4, 0,
|
1999-05-03 09:29:11 +02:00
|
|
|
|
RELAX_ENCODE (0, 4, -8, 0, 0, 0),
|
2001-11-12 23:19:30 +01:00
|
|
|
|
offset_expr.X_add_symbol, 0, NULL);
|
2003-06-16 14:13:10 +02:00
|
|
|
|
macro_build (p, &icnt, &offset_expr, ADDRESS_ADDI_INSN,
|
2003-06-30 14:44:25 +02:00
|
|
|
|
"t,r,j", tempreg, tempreg, BFD_RELOC_LO16);
|
1999-05-03 09:29:11 +02:00
|
|
|
|
if (breg != 0)
|
2003-06-30 14:44:25 +02:00
|
|
|
|
macro_build (NULL, &icnt, NULL, ADDRESS_ADD_INSN, "d,v,t",
|
|
|
|
|
tempreg, tempreg, breg);
|
|
|
|
|
macro_build (NULL, &icnt, &expr1, s, fmt, treg, BFD_RELOC_LO16,
|
|
|
|
|
tempreg);
|
1999-05-03 09:29:11 +02:00
|
|
|
|
}
|
* config/tc-mips.h (tc_frag_data_type, TC_FRAG_TYPE): New.
* config/tc-mips.c: Use signed add for n32 address arithmetic.
(append_insn): When filling delay slots with instructions
that have fixups that tc_gen_reloc might consider modifyable
in variant frags, start a new frag.
(load_address): Generate GOT_DISP with of without offset
depending on whether symbol is local. For -xgot, use
GOT_PAGE/GOT_OFST or GOT_HI16/GOT_LO16.
(macro) <M_DLA_AB, M_LA_AB>: Likewise.
<M_JAL_A>: In NewABI, use CALL16 or GOT_DISP for small got,
CALL_HI16/CALL_LO16 or GOT_PAGE/GOT_OFST for big got.
<ld_st>: In NewABI with small got, always use
GOT_PAGE/GOT_OFST, with the latter in the load/store
instruction. With big got, use GOT_HI16/GOT_LO16 or
GOT_PAGE/GOT_OFST.
(tc_gen_reloc): Adjust variant frags with GOT_DISP in NewABI.
Add tc_frag_data.tc_fr_offset to addends. Decay CALL16,
GOT_OFST and GOT_DISP to GOT_DISP in NewABI.
(md_convert_frag): Use memmove for safe copying of overlapping
regions.
2003-04-11 03:56:50 +02:00
|
|
|
|
else if (mips_pic == SVR4_PIC && ! HAVE_NEWABI)
|
1999-05-03 09:29:11 +02:00
|
|
|
|
{
|
|
|
|
|
int gpdel;
|
2002-05-26 20:46:37 +02:00
|
|
|
|
char *p;
|
1999-05-03 09:29:11 +02:00
|
|
|
|
|
|
|
|
|
/* If this is a reference to an external symbol, we want
|
|
|
|
|
lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
|
|
|
|
|
addu $tempreg,$tempreg,$gp
|
|
|
|
|
lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
|
|
|
|
|
<op> $treg,0($tempreg)
|
|
|
|
|
Otherwise we want
|
|
|
|
|
lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
|
|
|
|
|
nop
|
|
|
|
|
addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
|
|
|
|
|
<op> $treg,0($tempreg)
|
|
|
|
|
If there is a base register, we add it to $tempreg before
|
|
|
|
|
the <op>. If there is a constant, we stick it in the
|
|
|
|
|
<op> instruction. We don't handle constants larger than
|
|
|
|
|
16 bits, because we have no way to load the upper 16 bits
|
|
|
|
|
(actually, we could handle them for the subset of cases
|
* config/tc-mips.h (tc_frag_data_type, TC_FRAG_TYPE): New.
* config/tc-mips.c: Use signed add for n32 address arithmetic.
(append_insn): When filling delay slots with instructions
that have fixups that tc_gen_reloc might consider modifyable
in variant frags, start a new frag.
(load_address): Generate GOT_DISP with of without offset
depending on whether symbol is local. For -xgot, use
GOT_PAGE/GOT_OFST or GOT_HI16/GOT_LO16.
(macro) <M_DLA_AB, M_LA_AB>: Likewise.
<M_JAL_A>: In NewABI, use CALL16 or GOT_DISP for small got,
CALL_HI16/CALL_LO16 or GOT_PAGE/GOT_OFST for big got.
<ld_st>: In NewABI with small got, always use
GOT_PAGE/GOT_OFST, with the latter in the load/store
instruction. With big got, use GOT_HI16/GOT_LO16 or
GOT_PAGE/GOT_OFST.
(tc_gen_reloc): Adjust variant frags with GOT_DISP in NewABI.
Add tc_frag_data.tc_fr_offset to addends. Decay CALL16,
GOT_OFST and GOT_DISP to GOT_DISP in NewABI.
(md_convert_frag): Use memmove for safe copying of overlapping
regions.
2003-04-11 03:56:50 +02:00
|
|
|
|
in which we are not using $at). */
|
1999-05-03 09:29:11 +02:00
|
|
|
|
assert (offset_expr.X_op == O_symbol);
|
|
|
|
|
expr1.X_add_number = offset_expr.X_add_number;
|
|
|
|
|
offset_expr.X_add_number = 0;
|
|
|
|
|
if (expr1.X_add_number < -0x8000
|
|
|
|
|
|| expr1.X_add_number >= 0x8000)
|
|
|
|
|
as_bad (_("PIC code offset overflow (max 16 signed bits)"));
|
2002-05-31 00:29:20 +02:00
|
|
|
|
if (reg_needs_delay (mips_gp_register))
|
1999-05-03 09:29:11 +02:00
|
|
|
|
gpdel = 4;
|
|
|
|
|
else
|
|
|
|
|
gpdel = 0;
|
|
|
|
|
frag_grow (36);
|
2003-06-30 14:44:25 +02:00
|
|
|
|
macro_build (NULL, &icnt, &offset_expr, "lui", "t,u", tempreg,
|
|
|
|
|
BFD_RELOC_MIPS_GOT_HI16);
|
|
|
|
|
macro_build (NULL, &icnt, NULL, ADDRESS_ADD_INSN, "d,v,t",
|
|
|
|
|
tempreg, tempreg, mips_gp_register);
|
|
|
|
|
macro_build (NULL, &icnt, &offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
|
|
|
|
|
tempreg, BFD_RELOC_MIPS_GOT_LO16, tempreg);
|
1999-05-03 09:29:11 +02:00
|
|
|
|
p = frag_var (rs_machine_dependent, 12 + gpdel, 0,
|
|
|
|
|
RELAX_ENCODE (12, 12 + gpdel, gpdel, 8 + gpdel, 0, 0),
|
2001-11-12 23:19:30 +01:00
|
|
|
|
offset_expr.X_add_symbol, 0, NULL);
|
1999-05-03 09:29:11 +02:00
|
|
|
|
if (gpdel > 0)
|
|
|
|
|
{
|
2003-06-30 14:44:25 +02:00
|
|
|
|
macro_build (p, &icnt, NULL, "nop", "");
|
1999-05-03 09:29:11 +02:00
|
|
|
|
p += 4;
|
|
|
|
|
}
|
2003-06-30 14:44:25 +02:00
|
|
|
|
macro_build (p, &icnt, &offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
|
|
|
|
|
tempreg, BFD_RELOC_MIPS_GOT16, mips_gp_register);
|
1999-05-03 09:29:11 +02:00
|
|
|
|
p += 4;
|
2003-06-30 14:44:25 +02:00
|
|
|
|
macro_build (p, &icnt, NULL, "nop", "");
|
1999-05-03 09:29:11 +02:00
|
|
|
|
p += 4;
|
2003-06-30 14:44:25 +02:00
|
|
|
|
macro_build (p, &icnt, &offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
|
|
|
|
|
tempreg, tempreg, BFD_RELOC_LO16);
|
1999-05-03 09:29:11 +02:00
|
|
|
|
if (breg != 0)
|
2003-06-30 14:44:25 +02:00
|
|
|
|
macro_build (NULL, &icnt, NULL, ADDRESS_ADD_INSN, "d,v,t",
|
|
|
|
|
tempreg, tempreg, breg);
|
|
|
|
|
macro_build (NULL, &icnt, &expr1, s, fmt, treg, BFD_RELOC_LO16,
|
|
|
|
|
tempreg);
|
1999-05-03 09:29:11 +02:00
|
|
|
|
}
|
* config/tc-mips.h (tc_frag_data_type, TC_FRAG_TYPE): New.
* config/tc-mips.c: Use signed add for n32 address arithmetic.
(append_insn): When filling delay slots with instructions
that have fixups that tc_gen_reloc might consider modifyable
in variant frags, start a new frag.
(load_address): Generate GOT_DISP with of without offset
depending on whether symbol is local. For -xgot, use
GOT_PAGE/GOT_OFST or GOT_HI16/GOT_LO16.
(macro) <M_DLA_AB, M_LA_AB>: Likewise.
<M_JAL_A>: In NewABI, use CALL16 or GOT_DISP for small got,
CALL_HI16/CALL_LO16 or GOT_PAGE/GOT_OFST for big got.
<ld_st>: In NewABI with small got, always use
GOT_PAGE/GOT_OFST, with the latter in the load/store
instruction. With big got, use GOT_HI16/GOT_LO16 or
GOT_PAGE/GOT_OFST.
(tc_gen_reloc): Adjust variant frags with GOT_DISP in NewABI.
Add tc_frag_data.tc_fr_offset to addends. Decay CALL16,
GOT_OFST and GOT_DISP to GOT_DISP in NewABI.
(md_convert_frag): Use memmove for safe copying of overlapping
regions.
2003-04-11 03:56:50 +02:00
|
|
|
|
else if (mips_pic == SVR4_PIC && HAVE_NEWABI)
|
|
|
|
|
{
|
|
|
|
|
char *p;
|
|
|
|
|
int bregsz = breg != 0 ? 4 : 0;
|
|
|
|
|
|
|
|
|
|
/* If this is a reference to an external symbol, we want
|
|
|
|
|
lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
|
|
|
|
|
add $tempreg,$tempreg,$gp
|
|
|
|
|
lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
|
|
|
|
|
<op> $treg,<ofst>($tempreg)
|
|
|
|
|
Otherwise, for local symbols, we want:
|
|
|
|
|
lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
|
|
|
|
|
<op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST) */
|
|
|
|
|
assert (offset_expr.X_op == O_symbol);
|
2003-12-06 14:52:23 +01:00
|
|
|
|
frag_grow (36);
|
* config/tc-mips.h (tc_frag_data_type, TC_FRAG_TYPE): New.
* config/tc-mips.c: Use signed add for n32 address arithmetic.
(append_insn): When filling delay slots with instructions
that have fixups that tc_gen_reloc might consider modifyable
in variant frags, start a new frag.
(load_address): Generate GOT_DISP with of without offset
depending on whether symbol is local. For -xgot, use
GOT_PAGE/GOT_OFST or GOT_HI16/GOT_LO16.
(macro) <M_DLA_AB, M_LA_AB>: Likewise.
<M_JAL_A>: In NewABI, use CALL16 or GOT_DISP for small got,
CALL_HI16/CALL_LO16 or GOT_PAGE/GOT_OFST for big got.
<ld_st>: In NewABI with small got, always use
GOT_PAGE/GOT_OFST, with the latter in the load/store
instruction. With big got, use GOT_HI16/GOT_LO16 or
GOT_PAGE/GOT_OFST.
(tc_gen_reloc): Adjust variant frags with GOT_DISP in NewABI.
Add tc_frag_data.tc_fr_offset to addends. Decay CALL16,
GOT_OFST and GOT_DISP to GOT_DISP in NewABI.
(md_convert_frag): Use memmove for safe copying of overlapping
regions.
2003-04-11 03:56:50 +02:00
|
|
|
|
frag_now->tc_frag_data.tc_fr_offset =
|
|
|
|
|
expr1.X_add_number = offset_expr.X_add_number;
|
|
|
|
|
offset_expr.X_add_number = 0;
|
|
|
|
|
if (expr1.X_add_number < -0x8000
|
|
|
|
|
|| expr1.X_add_number >= 0x8000)
|
|
|
|
|
as_bad (_("PIC code offset overflow (max 16 signed bits)"));
|
2003-06-30 14:44:25 +02:00
|
|
|
|
macro_build (NULL, &icnt, &offset_expr, "lui", "t,u", tempreg,
|
|
|
|
|
BFD_RELOC_MIPS_GOT_HI16);
|
|
|
|
|
macro_build (NULL, &icnt, NULL, ADDRESS_ADD_INSN, "d,v,t",
|
|
|
|
|
tempreg, tempreg, mips_gp_register);
|
|
|
|
|
macro_build (NULL, &icnt, &offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
|
|
|
|
|
tempreg, BFD_RELOC_MIPS_GOT_LO16, tempreg);
|
* config/tc-mips.h (tc_frag_data_type, TC_FRAG_TYPE): New.
* config/tc-mips.c: Use signed add for n32 address arithmetic.
(append_insn): When filling delay slots with instructions
that have fixups that tc_gen_reloc might consider modifyable
in variant frags, start a new frag.
(load_address): Generate GOT_DISP with of without offset
depending on whether symbol is local. For -xgot, use
GOT_PAGE/GOT_OFST or GOT_HI16/GOT_LO16.
(macro) <M_DLA_AB, M_LA_AB>: Likewise.
<M_JAL_A>: In NewABI, use CALL16 or GOT_DISP for small got,
CALL_HI16/CALL_LO16 or GOT_PAGE/GOT_OFST for big got.
<ld_st>: In NewABI with small got, always use
GOT_PAGE/GOT_OFST, with the latter in the load/store
instruction. With big got, use GOT_HI16/GOT_LO16 or
GOT_PAGE/GOT_OFST.
(tc_gen_reloc): Adjust variant frags with GOT_DISP in NewABI.
Add tc_frag_data.tc_fr_offset to addends. Decay CALL16,
GOT_OFST and GOT_DISP to GOT_DISP in NewABI.
(md_convert_frag): Use memmove for safe copying of overlapping
regions.
2003-04-11 03:56:50 +02:00
|
|
|
|
if (breg != 0)
|
2003-06-30 14:44:25 +02:00
|
|
|
|
macro_build (NULL, &icnt, NULL, ADDRESS_ADD_INSN, "d,v,t",
|
|
|
|
|
tempreg, tempreg, breg);
|
|
|
|
|
macro_build (NULL, &icnt, &expr1, s, fmt, treg, BFD_RELOC_LO16,
|
|
|
|
|
tempreg);
|
2003-04-25 06:40:09 +02:00
|
|
|
|
|
* config/tc-mips.h (tc_frag_data_type, TC_FRAG_TYPE): New.
* config/tc-mips.c: Use signed add for n32 address arithmetic.
(append_insn): When filling delay slots with instructions
that have fixups that tc_gen_reloc might consider modifyable
in variant frags, start a new frag.
(load_address): Generate GOT_DISP with of without offset
depending on whether symbol is local. For -xgot, use
GOT_PAGE/GOT_OFST or GOT_HI16/GOT_LO16.
(macro) <M_DLA_AB, M_LA_AB>: Likewise.
<M_JAL_A>: In NewABI, use CALL16 or GOT_DISP for small got,
CALL_HI16/CALL_LO16 or GOT_PAGE/GOT_OFST for big got.
<ld_st>: In NewABI with small got, always use
GOT_PAGE/GOT_OFST, with the latter in the load/store
instruction. With big got, use GOT_HI16/GOT_LO16 or
GOT_PAGE/GOT_OFST.
(tc_gen_reloc): Adjust variant frags with GOT_DISP in NewABI.
Add tc_frag_data.tc_fr_offset to addends. Decay CALL16,
GOT_OFST and GOT_DISP to GOT_DISP in NewABI.
(md_convert_frag): Use memmove for safe copying of overlapping
regions.
2003-04-11 03:56:50 +02:00
|
|
|
|
offset_expr.X_add_number = expr1.X_add_number;
|
|
|
|
|
p = frag_var (rs_machine_dependent, 12 + bregsz, 0,
|
|
|
|
|
RELAX_ENCODE (16 + bregsz, 8 + bregsz,
|
|
|
|
|
0, 4 + bregsz, 0, 0),
|
|
|
|
|
offset_expr.X_add_symbol, 0, NULL);
|
2003-06-16 14:13:10 +02:00
|
|
|
|
macro_build (p, &icnt, &offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
|
2003-06-30 14:44:25 +02:00
|
|
|
|
tempreg, BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register);
|
* config/tc-mips.h (tc_frag_data_type, TC_FRAG_TYPE): New.
* config/tc-mips.c: Use signed add for n32 address arithmetic.
(append_insn): When filling delay slots with instructions
that have fixups that tc_gen_reloc might consider modifyable
in variant frags, start a new frag.
(load_address): Generate GOT_DISP with of without offset
depending on whether symbol is local. For -xgot, use
GOT_PAGE/GOT_OFST or GOT_HI16/GOT_LO16.
(macro) <M_DLA_AB, M_LA_AB>: Likewise.
<M_JAL_A>: In NewABI, use CALL16 or GOT_DISP for small got,
CALL_HI16/CALL_LO16 or GOT_PAGE/GOT_OFST for big got.
<ld_st>: In NewABI with small got, always use
GOT_PAGE/GOT_OFST, with the latter in the load/store
instruction. With big got, use GOT_HI16/GOT_LO16 or
GOT_PAGE/GOT_OFST.
(tc_gen_reloc): Adjust variant frags with GOT_DISP in NewABI.
Add tc_frag_data.tc_fr_offset to addends. Decay CALL16,
GOT_OFST and GOT_DISP to GOT_DISP in NewABI.
(md_convert_frag): Use memmove for safe copying of overlapping
regions.
2003-04-11 03:56:50 +02:00
|
|
|
|
if (breg != 0)
|
2003-06-30 14:44:25 +02:00
|
|
|
|
macro_build (p + 4, &icnt, NULL, ADDRESS_ADD_INSN, "d,v,t",
|
|
|
|
|
tempreg, tempreg, breg);
|
* config/tc-mips.h (tc_frag_data_type, TC_FRAG_TYPE): New.
* config/tc-mips.c: Use signed add for n32 address arithmetic.
(append_insn): When filling delay slots with instructions
that have fixups that tc_gen_reloc might consider modifyable
in variant frags, start a new frag.
(load_address): Generate GOT_DISP with of without offset
depending on whether symbol is local. For -xgot, use
GOT_PAGE/GOT_OFST or GOT_HI16/GOT_LO16.
(macro) <M_DLA_AB, M_LA_AB>: Likewise.
<M_JAL_A>: In NewABI, use CALL16 or GOT_DISP for small got,
CALL_HI16/CALL_LO16 or GOT_PAGE/GOT_OFST for big got.
<ld_st>: In NewABI with small got, always use
GOT_PAGE/GOT_OFST, with the latter in the load/store
instruction. With big got, use GOT_HI16/GOT_LO16 or
GOT_PAGE/GOT_OFST.
(tc_gen_reloc): Adjust variant frags with GOT_DISP in NewABI.
Add tc_frag_data.tc_fr_offset to addends. Decay CALL16,
GOT_OFST and GOT_DISP to GOT_DISP in NewABI.
(md_convert_frag): Use memmove for safe copying of overlapping
regions.
2003-04-11 03:56:50 +02:00
|
|
|
|
macro_build (p + 4 + bregsz, &icnt, &offset_expr, s, fmt, treg,
|
2003-06-30 14:44:25 +02:00
|
|
|
|
BFD_RELOC_MIPS_GOT_OFST, tempreg);
|
* config/tc-mips.h (tc_frag_data_type, TC_FRAG_TYPE): New.
* config/tc-mips.c: Use signed add for n32 address arithmetic.
(append_insn): When filling delay slots with instructions
that have fixups that tc_gen_reloc might consider modifyable
in variant frags, start a new frag.
(load_address): Generate GOT_DISP with of without offset
depending on whether symbol is local. For -xgot, use
GOT_PAGE/GOT_OFST or GOT_HI16/GOT_LO16.
(macro) <M_DLA_AB, M_LA_AB>: Likewise.
<M_JAL_A>: In NewABI, use CALL16 or GOT_DISP for small got,
CALL_HI16/CALL_LO16 or GOT_PAGE/GOT_OFST for big got.
<ld_st>: In NewABI with small got, always use
GOT_PAGE/GOT_OFST, with the latter in the load/store
instruction. With big got, use GOT_HI16/GOT_LO16 or
GOT_PAGE/GOT_OFST.
(tc_gen_reloc): Adjust variant frags with GOT_DISP in NewABI.
Add tc_frag_data.tc_fr_offset to addends. Decay CALL16,
GOT_OFST and GOT_DISP to GOT_DISP in NewABI.
(md_convert_frag): Use memmove for safe copying of overlapping
regions.
2003-04-11 03:56:50 +02:00
|
|
|
|
}
|
1999-05-03 09:29:11 +02:00
|
|
|
|
else if (mips_pic == EMBEDDED_PIC)
|
|
|
|
|
{
|
|
|
|
|
/* If there is no base register, we want
|
2001-12-02 14:14:48 +01:00
|
|
|
|
<op> $treg,<sym>($gp) (BFD_RELOC_GPREL16)
|
1999-05-03 09:29:11 +02:00
|
|
|
|
If there is a base register, we want
|
|
|
|
|
addu $tempreg,$breg,$gp
|
2001-12-02 14:14:48 +01:00
|
|
|
|
<op> $treg,<sym>($tempreg) (BFD_RELOC_GPREL16)
|
1999-05-03 09:29:11 +02:00
|
|
|
|
*/
|
|
|
|
|
assert (offset_expr.X_op == O_symbol);
|
|
|
|
|
if (breg == 0)
|
|
|
|
|
{
|
2003-06-30 14:44:25 +02:00
|
|
|
|
macro_build (NULL, &icnt, &offset_expr, s, fmt, treg,
|
|
|
|
|
BFD_RELOC_GPREL16, mips_gp_register);
|
1999-05-03 09:29:11 +02:00
|
|
|
|
used_at = 0;
|
|
|
|
|
}
|
|
|
|
|
else
|
|
|
|
|
{
|
2003-06-30 14:44:25 +02:00
|
|
|
|
macro_build (NULL, &icnt, NULL, ADDRESS_ADD_INSN, "d,v,t",
|
|
|
|
|
tempreg, breg, mips_gp_register);
|
|
|
|
|
macro_build (NULL, &icnt, &offset_expr, s, fmt, treg,
|
|
|
|
|
BFD_RELOC_GPREL16, tempreg);
|
1999-05-03 09:29:11 +02:00
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
else
|
|
|
|
|
abort ();
|
|
|
|
|
|
|
|
|
|
if (! used_at)
|
|
|
|
|
return;
|
|
|
|
|
|
|
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
case M_LI:
|
|
|
|
|
case M_LI_S:
|
|
|
|
|
load_register (&icnt, treg, &imm_expr, 0);
|
|
|
|
|
return;
|
|
|
|
|
|
|
|
|
|
case M_DLI:
|
|
|
|
|
load_register (&icnt, treg, &imm_expr, 1);
|
|
|
|
|
return;
|
|
|
|
|
|
|
|
|
|
case M_LI_SS:
|
|
|
|
|
if (imm_expr.X_op == O_constant)
|
|
|
|
|
{
|
|
|
|
|
load_register (&icnt, AT, &imm_expr, 0);
|
2003-06-30 14:44:25 +02:00
|
|
|
|
macro_build (NULL, &icnt, NULL, "mtc1", "t,G", AT, treg);
|
1999-05-03 09:29:11 +02:00
|
|
|
|
break;
|
|
|
|
|
}
|
|
|
|
|
else
|
|
|
|
|
{
|
|
|
|
|
assert (offset_expr.X_op == O_symbol
|
|
|
|
|
&& strcmp (segment_name (S_GET_SEGMENT
|
|
|
|
|
(offset_expr.X_add_symbol)),
|
|
|
|
|
".lit4") == 0
|
|
|
|
|
&& offset_expr.X_add_number == 0);
|
2003-06-30 14:44:25 +02:00
|
|
|
|
macro_build (NULL, &icnt, &offset_expr, "lwc1", "T,o(b)", treg,
|
|
|
|
|
BFD_RELOC_MIPS_LITERAL, mips_gp_register);
|
1999-05-03 09:29:11 +02:00
|
|
|
|
return;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
case M_LI_D:
|
2001-08-02 12:15:24 +02:00
|
|
|
|
/* Check if we have a constant in IMM_EXPR. If the GPRs are 64 bits
|
|
|
|
|
wide, IMM_EXPR is the entire value. Otherwise IMM_EXPR is the high
|
|
|
|
|
order 32 bits of the value and the low order 32 bits are either
|
|
|
|
|
zero or in OFFSET_EXPR. */
|
1999-05-03 09:29:11 +02:00
|
|
|
|
if (imm_expr.X_op == O_constant || imm_expr.X_op == O_big)
|
|
|
|
|
{
|
2001-08-02 12:15:24 +02:00
|
|
|
|
if (HAVE_64BIT_GPRS)
|
1999-05-03 09:29:11 +02:00
|
|
|
|
load_register (&icnt, treg, &imm_expr, 1);
|
|
|
|
|
else
|
|
|
|
|
{
|
|
|
|
|
int hreg, lreg;
|
|
|
|
|
|
|
|
|
|
if (target_big_endian)
|
|
|
|
|
{
|
|
|
|
|
hreg = treg;
|
|
|
|
|
lreg = treg + 1;
|
|
|
|
|
}
|
|
|
|
|
else
|
|
|
|
|
{
|
|
|
|
|
hreg = treg + 1;
|
|
|
|
|
lreg = treg;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
if (hreg <= 31)
|
|
|
|
|
load_register (&icnt, hreg, &imm_expr, 0);
|
|
|
|
|
if (lreg <= 31)
|
|
|
|
|
{
|
|
|
|
|
if (offset_expr.X_op == O_absent)
|
2001-08-10 18:24:32 +02:00
|
|
|
|
move_register (&icnt, lreg, 0);
|
1999-05-03 09:29:11 +02:00
|
|
|
|
else
|
|
|
|
|
{
|
|
|
|
|
assert (offset_expr.X_op == O_constant);
|
|
|
|
|
load_register (&icnt, lreg, &offset_expr, 0);
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
return;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/* We know that sym is in the .rdata section. First we get the
|
|
|
|
|
upper 16 bits of the address. */
|
|
|
|
|
if (mips_pic == NO_PIC)
|
|
|
|
|
{
|
2001-12-04 15:38:48 +01:00
|
|
|
|
macro_build_lui (NULL, &icnt, &offset_expr, AT);
|
1999-05-03 09:29:11 +02:00
|
|
|
|
}
|
|
|
|
|
else if (mips_pic == SVR4_PIC)
|
|
|
|
|
{
|
2003-06-30 14:44:25 +02:00
|
|
|
|
macro_build (NULL, &icnt, &offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
|
|
|
|
|
AT, BFD_RELOC_MIPS_GOT16, mips_gp_register);
|
1999-05-03 09:29:11 +02:00
|
|
|
|
}
|
|
|
|
|
else if (mips_pic == EMBEDDED_PIC)
|
|
|
|
|
{
|
|
|
|
|
/* For embedded PIC we pick up the entire address off $gp in
|
|
|
|
|
a single instruction. */
|
2003-06-30 14:44:25 +02:00
|
|
|
|
macro_build (NULL, &icnt, &offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
|
|
|
|
|
AT, mips_gp_register, BFD_RELOC_GPREL16);
|
1999-05-03 09:29:11 +02:00
|
|
|
|
offset_expr.X_op = O_constant;
|
|
|
|
|
offset_expr.X_add_number = 0;
|
|
|
|
|
}
|
|
|
|
|
else
|
|
|
|
|
abort ();
|
2000-09-07 14:45:56 +02:00
|
|
|
|
|
1999-05-03 09:29:11 +02:00
|
|
|
|
/* Now we load the register(s). */
|
2001-08-02 12:15:24 +02:00
|
|
|
|
if (HAVE_64BIT_GPRS)
|
2003-06-30 14:44:25 +02:00
|
|
|
|
macro_build (NULL, &icnt, &offset_expr, "ld", "t,o(b)", treg,
|
|
|
|
|
BFD_RELOC_LO16, AT);
|
1999-05-03 09:29:11 +02:00
|
|
|
|
else
|
|
|
|
|
{
|
2003-06-30 14:44:25 +02:00
|
|
|
|
macro_build (NULL, &icnt, &offset_expr, "lw", "t,o(b)", treg,
|
|
|
|
|
BFD_RELOC_LO16, AT);
|
2002-05-26 20:46:37 +02:00
|
|
|
|
if (treg != RA)
|
1999-05-03 09:29:11 +02:00
|
|
|
|
{
|
|
|
|
|
/* FIXME: How in the world do we deal with the possible
|
|
|
|
|
overflow here? */
|
|
|
|
|
offset_expr.X_add_number += 4;
|
2003-06-30 14:44:25 +02:00
|
|
|
|
macro_build (NULL, &icnt, &offset_expr, "lw", "t,o(b)",
|
|
|
|
|
treg + 1, BFD_RELOC_LO16, AT);
|
1999-05-03 09:29:11 +02:00
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/* To avoid confusion in tc_gen_reloc, we must ensure that this
|
|
|
|
|
does not become a variant frag. */
|
|
|
|
|
frag_wane (frag_now);
|
|
|
|
|
frag_new (0);
|
|
|
|
|
|
|
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
case M_LI_DD:
|
2001-08-02 12:15:24 +02:00
|
|
|
|
/* Check if we have a constant in IMM_EXPR. If the FPRs are 64 bits
|
|
|
|
|
wide, IMM_EXPR is the entire value and the GPRs are known to be 64
|
|
|
|
|
bits wide as well. Otherwise IMM_EXPR is the high order 32 bits of
|
|
|
|
|
the value and the low order 32 bits are either zero or in
|
|
|
|
|
OFFSET_EXPR. */
|
1999-05-03 09:29:11 +02:00
|
|
|
|
if (imm_expr.X_op == O_constant || imm_expr.X_op == O_big)
|
|
|
|
|
{
|
2001-08-02 12:15:24 +02:00
|
|
|
|
load_register (&icnt, AT, &imm_expr, HAVE_64BIT_FPRS);
|
|
|
|
|
if (HAVE_64BIT_FPRS)
|
|
|
|
|
{
|
|
|
|
|
assert (HAVE_64BIT_GPRS);
|
2003-06-30 14:44:25 +02:00
|
|
|
|
macro_build (NULL, &icnt, NULL, "dmtc1", "t,S", AT, treg);
|
2001-08-02 12:15:24 +02:00
|
|
|
|
}
|
1999-05-03 09:29:11 +02:00
|
|
|
|
else
|
|
|
|
|
{
|
2003-06-30 14:44:25 +02:00
|
|
|
|
macro_build (NULL, &icnt, NULL, "mtc1", "t,G", AT, treg + 1);
|
1999-05-03 09:29:11 +02:00
|
|
|
|
if (offset_expr.X_op == O_absent)
|
2003-06-30 14:44:25 +02:00
|
|
|
|
macro_build (NULL, &icnt, NULL, "mtc1", "t,G", 0, treg);
|
1999-05-03 09:29:11 +02:00
|
|
|
|
else
|
|
|
|
|
{
|
|
|
|
|
assert (offset_expr.X_op == O_constant);
|
|
|
|
|
load_register (&icnt, AT, &offset_expr, 0);
|
2003-06-30 14:44:25 +02:00
|
|
|
|
macro_build (NULL, &icnt, NULL, "mtc1", "t,G", AT, treg);
|
1999-05-03 09:29:11 +02:00
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
break;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
assert (offset_expr.X_op == O_symbol
|
|
|
|
|
&& offset_expr.X_add_number == 0);
|
|
|
|
|
s = segment_name (S_GET_SEGMENT (offset_expr.X_add_symbol));
|
|
|
|
|
if (strcmp (s, ".lit8") == 0)
|
|
|
|
|
{
|
2000-12-01 22:35:38 +01:00
|
|
|
|
if (mips_opts.isa != ISA_MIPS1)
|
1999-05-03 09:29:11 +02:00
|
|
|
|
{
|
2003-06-30 14:44:25 +02:00
|
|
|
|
macro_build (NULL, &icnt, &offset_expr, "ldc1", "T,o(b)", treg,
|
|
|
|
|
BFD_RELOC_MIPS_LITERAL, mips_gp_register);
|
1999-05-03 09:29:11 +02:00
|
|
|
|
return;
|
|
|
|
|
}
|
2002-05-28 21:23:09 +02:00
|
|
|
|
breg = mips_gp_register;
|
1999-05-03 09:29:11 +02:00
|
|
|
|
r = BFD_RELOC_MIPS_LITERAL;
|
|
|
|
|
goto dob;
|
|
|
|
|
}
|
|
|
|
|
else
|
|
|
|
|
{
|
|
|
|
|
assert (strcmp (s, RDATA_SECTION_NAME) == 0);
|
|
|
|
|
if (mips_pic == SVR4_PIC)
|
2003-06-30 14:44:25 +02:00
|
|
|
|
macro_build (NULL, &icnt, &offset_expr, ADDRESS_LOAD_INSN,
|
|
|
|
|
"t,o(b)", AT, BFD_RELOC_MIPS_GOT16,
|
|
|
|
|
mips_gp_register);
|
1999-05-03 09:29:11 +02:00
|
|
|
|
else
|
|
|
|
|
{
|
|
|
|
|
/* FIXME: This won't work for a 64 bit address. */
|
2001-12-04 15:38:48 +01:00
|
|
|
|
macro_build_lui (NULL, &icnt, &offset_expr, AT);
|
1999-05-03 09:29:11 +02:00
|
|
|
|
}
|
2000-09-07 14:45:56 +02:00
|
|
|
|
|
2000-12-01 22:35:38 +01:00
|
|
|
|
if (mips_opts.isa != ISA_MIPS1)
|
1999-05-03 09:29:11 +02:00
|
|
|
|
{
|
2003-06-30 14:44:25 +02:00
|
|
|
|
macro_build (NULL, &icnt, &offset_expr, "ldc1", "T,o(b)", treg,
|
|
|
|
|
BFD_RELOC_LO16, AT);
|
1999-05-03 09:29:11 +02:00
|
|
|
|
|
|
|
|
|
/* To avoid confusion in tc_gen_reloc, we must ensure
|
|
|
|
|
that this does not become a variant frag. */
|
|
|
|
|
frag_wane (frag_now);
|
|
|
|
|
frag_new (0);
|
|
|
|
|
|
|
|
|
|
break;
|
|
|
|
|
}
|
|
|
|
|
breg = AT;
|
|
|
|
|
r = BFD_RELOC_LO16;
|
|
|
|
|
goto dob;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
case M_L_DOB:
|
2003-06-29 21:41:33 +02:00
|
|
|
|
if (mips_opts.arch == CPU_R4650)
|
1999-05-03 09:29:11 +02:00
|
|
|
|
{
|
|
|
|
|
as_bad (_("opcode not supported on this processor"));
|
|
|
|
|
return;
|
|
|
|
|
}
|
|
|
|
|
/* Even on a big endian machine $fn comes before $fn+1. We have
|
|
|
|
|
to adjust when loading from memory. */
|
|
|
|
|
r = BFD_RELOC_LO16;
|
|
|
|
|
dob:
|
2000-12-01 22:35:38 +01:00
|
|
|
|
assert (mips_opts.isa == ISA_MIPS1);
|
2003-06-30 14:44:25 +02:00
|
|
|
|
macro_build (NULL, &icnt, &offset_expr, "lwc1", "T,o(b)",
|
|
|
|
|
target_big_endian ? treg + 1 : treg, r, breg);
|
1999-05-03 09:29:11 +02:00
|
|
|
|
/* FIXME: A possible overflow which I don't know how to deal
|
|
|
|
|
with. */
|
|
|
|
|
offset_expr.X_add_number += 4;
|
2003-06-30 14:44:25 +02:00
|
|
|
|
macro_build (NULL, &icnt, &offset_expr, "lwc1", "T,o(b)",
|
|
|
|
|
target_big_endian ? treg : treg + 1, r, breg);
|
1999-05-03 09:29:11 +02:00
|
|
|
|
|
|
|
|
|
/* To avoid confusion in tc_gen_reloc, we must ensure that this
|
|
|
|
|
does not become a variant frag. */
|
|
|
|
|
frag_wane (frag_now);
|
|
|
|
|
frag_new (0);
|
|
|
|
|
|
|
|
|
|
if (breg != AT)
|
|
|
|
|
return;
|
|
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
case M_L_DAB:
|
|
|
|
|
/*
|
|
|
|
|
* The MIPS assembler seems to check for X_add_number not
|
|
|
|
|
* being double aligned and generating:
|
|
|
|
|
* lui at,%hi(foo+1)
|
|
|
|
|
* addu at,at,v1
|
|
|
|
|
* addiu at,at,%lo(foo+1)
|
|
|
|
|
* lwc1 f2,0(at)
|
|
|
|
|
* lwc1 f3,4(at)
|
|
|
|
|
* But, the resulting address is the same after relocation so why
|
|
|
|
|
* generate the extra instruction?
|
|
|
|
|
*/
|
2003-06-29 21:41:33 +02:00
|
|
|
|
if (mips_opts.arch == CPU_R4650)
|
1999-05-03 09:29:11 +02:00
|
|
|
|
{
|
|
|
|
|
as_bad (_("opcode not supported on this processor"));
|
|
|
|
|
return;
|
|
|
|
|
}
|
2000-09-07 14:45:56 +02:00
|
|
|
|
/* Itbl support may require additional care here. */
|
1999-05-03 09:29:11 +02:00
|
|
|
|
coproc = 1;
|
2000-12-01 22:35:38 +01:00
|
|
|
|
if (mips_opts.isa != ISA_MIPS1)
|
1999-05-03 09:29:11 +02:00
|
|
|
|
{
|
|
|
|
|
s = "ldc1";
|
|
|
|
|
goto ld;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
s = "lwc1";
|
|
|
|
|
fmt = "T,o(b)";
|
|
|
|
|
goto ldd_std;
|
|
|
|
|
|
|
|
|
|
case M_S_DAB:
|
2003-06-29 21:41:33 +02:00
|
|
|
|
if (mips_opts.arch == CPU_R4650)
|
1999-05-03 09:29:11 +02:00
|
|
|
|
{
|
|
|
|
|
as_bad (_("opcode not supported on this processor"));
|
|
|
|
|
return;
|
|
|
|
|
}
|
|
|
|
|
|
2000-12-01 22:35:38 +01:00
|
|
|
|
if (mips_opts.isa != ISA_MIPS1)
|
1999-05-03 09:29:11 +02:00
|
|
|
|
{
|
|
|
|
|
s = "sdc1";
|
|
|
|
|
goto st;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
s = "swc1";
|
|
|
|
|
fmt = "T,o(b)";
|
2000-09-07 14:45:56 +02:00
|
|
|
|
/* Itbl support may require additional care here. */
|
1999-05-03 09:29:11 +02:00
|
|
|
|
coproc = 1;
|
|
|
|
|
goto ldd_std;
|
|
|
|
|
|
|
|
|
|
case M_LD_AB:
|
2001-08-02 12:15:24 +02:00
|
|
|
|
if (HAVE_64BIT_GPRS)
|
1999-05-03 09:29:11 +02:00
|
|
|
|
{
|
|
|
|
|
s = "ld";
|
|
|
|
|
goto ld;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
s = "lw";
|
|
|
|
|
fmt = "t,o(b)";
|
|
|
|
|
goto ldd_std;
|
|
|
|
|
|
|
|
|
|
case M_SD_AB:
|
2001-08-02 12:15:24 +02:00
|
|
|
|
if (HAVE_64BIT_GPRS)
|
1999-05-03 09:29:11 +02:00
|
|
|
|
{
|
|
|
|
|
s = "sd";
|
|
|
|
|
goto st;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
s = "sw";
|
|
|
|
|
fmt = "t,o(b)";
|
|
|
|
|
|
|
|
|
|
ldd_std:
|
2001-11-01 02:33:47 +01:00
|
|
|
|
/* We do _not_ bother to allow embedded PIC (symbol-local_symbol)
|
|
|
|
|
loads for the case of doing a pair of loads to simulate an 'ld'.
|
|
|
|
|
This is not currently done by the compiler, and assembly coders
|
|
|
|
|
writing embedded-pic code can cope. */
|
|
|
|
|
|
1999-05-03 09:29:11 +02:00
|
|
|
|
if (offset_expr.X_op != O_symbol
|
|
|
|
|
&& offset_expr.X_op != O_constant)
|
|
|
|
|
{
|
|
|
|
|
as_bad (_("expression too complex"));
|
|
|
|
|
offset_expr.X_op = O_constant;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/* Even on a big endian machine $fn comes before $fn+1. We have
|
|
|
|
|
to adjust when loading from memory. We set coproc if we must
|
|
|
|
|
load $fn+1 first. */
|
2000-09-07 14:45:56 +02:00
|
|
|
|
/* Itbl support may require additional care here. */
|
1999-05-03 09:29:11 +02:00
|
|
|
|
if (! target_big_endian)
|
|
|
|
|
coproc = 0;
|
|
|
|
|
|
|
|
|
|
if (mips_pic == NO_PIC
|
|
|
|
|
|| offset_expr.X_op == O_constant)
|
|
|
|
|
{
|
2002-05-26 20:46:37 +02:00
|
|
|
|
char *p;
|
|
|
|
|
|
1999-05-03 09:29:11 +02:00
|
|
|
|
/* If this is a reference to a GP relative symbol, we want
|
2001-12-02 14:14:48 +01:00
|
|
|
|
<op> $treg,<sym>($gp) (BFD_RELOC_GPREL16)
|
|
|
|
|
<op> $treg+1,<sym>+4($gp) (BFD_RELOC_GPREL16)
|
1999-05-03 09:29:11 +02:00
|
|
|
|
If we have a base register, we use this
|
|
|
|
|
addu $at,$breg,$gp
|
2001-12-02 14:14:48 +01:00
|
|
|
|
<op> $treg,<sym>($at) (BFD_RELOC_GPREL16)
|
|
|
|
|
<op> $treg+1,<sym>+4($at) (BFD_RELOC_GPREL16)
|
1999-05-03 09:29:11 +02:00
|
|
|
|
If this is not a GP relative symbol, we want
|
|
|
|
|
lui $at,<sym> (BFD_RELOC_HI16_S)
|
|
|
|
|
<op> $treg,<sym>($at) (BFD_RELOC_LO16)
|
|
|
|
|
<op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
|
|
|
|
|
If there is a base register, we add it to $at after the
|
|
|
|
|
lui instruction. If there is a constant, we always use
|
|
|
|
|
the last case. */
|
2001-08-26 12:42:12 +02:00
|
|
|
|
if ((valueT) offset_expr.X_add_number > MAX_GPREL_OFFSET
|
1999-05-03 09:29:11 +02:00
|
|
|
|
|| nopic_need_relax (offset_expr.X_add_symbol, 1))
|
|
|
|
|
{
|
|
|
|
|
p = NULL;
|
|
|
|
|
used_at = 1;
|
|
|
|
|
}
|
|
|
|
|
else
|
|
|
|
|
{
|
|
|
|
|
int off;
|
|
|
|
|
|
|
|
|
|
if (breg == 0)
|
|
|
|
|
{
|
|
|
|
|
frag_grow (28);
|
2002-05-28 21:23:09 +02:00
|
|
|
|
tempreg = mips_gp_register;
|
1999-05-03 09:29:11 +02:00
|
|
|
|
off = 0;
|
|
|
|
|
used_at = 0;
|
|
|
|
|
}
|
|
|
|
|
else
|
|
|
|
|
{
|
|
|
|
|
frag_grow (36);
|
2003-06-30 14:44:25 +02:00
|
|
|
|
macro_build (NULL, &icnt, NULL, ADDRESS_ADD_INSN, "d,v,t",
|
|
|
|
|
AT, breg, mips_gp_register);
|
1999-05-03 09:29:11 +02:00
|
|
|
|
tempreg = AT;
|
|
|
|
|
off = 4;
|
|
|
|
|
used_at = 1;
|
|
|
|
|
}
|
|
|
|
|
|
2000-12-05 19:51:08 +01:00
|
|
|
|
/* Itbl support may require additional care here. */
|
2003-06-30 14:44:25 +02:00
|
|
|
|
macro_build (NULL, &icnt, &offset_expr, s, fmt,
|
1999-05-03 09:29:11 +02:00
|
|
|
|
coproc ? treg + 1 : treg,
|
2003-06-30 14:44:25 +02:00
|
|
|
|
BFD_RELOC_GPREL16, tempreg);
|
1999-05-03 09:29:11 +02:00
|
|
|
|
offset_expr.X_add_number += 4;
|
|
|
|
|
|
|
|
|
|
/* Set mips_optimize to 2 to avoid inserting an
|
|
|
|
|
undesired nop. */
|
|
|
|
|
hold_mips_optimize = mips_optimize;
|
|
|
|
|
mips_optimize = 2;
|
2000-12-05 19:51:08 +01:00
|
|
|
|
/* Itbl support may require additional care here. */
|
2003-06-30 14:44:25 +02:00
|
|
|
|
macro_build (NULL, &icnt, &offset_expr, s, fmt,
|
1999-05-03 09:29:11 +02:00
|
|
|
|
coproc ? treg : treg + 1,
|
2003-06-30 14:44:25 +02:00
|
|
|
|
BFD_RELOC_GPREL16, tempreg);
|
1999-05-03 09:29:11 +02:00
|
|
|
|
mips_optimize = hold_mips_optimize;
|
|
|
|
|
|
|
|
|
|
p = frag_var (rs_machine_dependent, 12 + off, 0,
|
|
|
|
|
RELAX_ENCODE (8 + off, 12 + off, 0, 4 + off, 1,
|
|
|
|
|
used_at && mips_opts.noat),
|
2001-12-04 15:38:48 +01:00
|
|
|
|
offset_expr.X_add_symbol, 0, NULL);
|
1999-05-03 09:29:11 +02:00
|
|
|
|
|
|
|
|
|
/* We just generated two relocs. When tc_gen_reloc
|
|
|
|
|
handles this case, it will skip the first reloc and
|
|
|
|
|
handle the second. The second reloc already has an
|
|
|
|
|
extra addend of 4, which we added above. We must
|
|
|
|
|
subtract it out, and then subtract another 4 to make
|
|
|
|
|
the first reloc come out right. The second reloc
|
|
|
|
|
will come out right because we are going to add 4 to
|
|
|
|
|
offset_expr when we build its instruction below.
|
|
|
|
|
|
|
|
|
|
If we have a symbol, then we don't want to include
|
|
|
|
|
the offset, because it will wind up being included
|
|
|
|
|
when we generate the reloc. */
|
|
|
|
|
|
|
|
|
|
if (offset_expr.X_op == O_constant)
|
|
|
|
|
offset_expr.X_add_number -= 8;
|
|
|
|
|
else
|
|
|
|
|
{
|
|
|
|
|
offset_expr.X_add_number = -4;
|
|
|
|
|
offset_expr.X_op = O_constant;
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
macro_build_lui (p, &icnt, &offset_expr, AT);
|
|
|
|
|
if (p != NULL)
|
|
|
|
|
p += 4;
|
|
|
|
|
if (breg != 0)
|
|
|
|
|
{
|
2003-06-30 14:44:25 +02:00
|
|
|
|
macro_build (p, &icnt, NULL, ADDRESS_ADD_INSN, "d,v,t",
|
|
|
|
|
AT, breg, AT);
|
1999-05-03 09:29:11 +02:00
|
|
|
|
if (p != NULL)
|
|
|
|
|
p += 4;
|
|
|
|
|
}
|
2000-12-05 19:51:08 +01:00
|
|
|
|
/* Itbl support may require additional care here. */
|
1999-05-03 09:29:11 +02:00
|
|
|
|
macro_build (p, &icnt, &offset_expr, s, fmt,
|
|
|
|
|
coproc ? treg + 1 : treg,
|
2003-06-30 14:44:25 +02:00
|
|
|
|
BFD_RELOC_LO16, AT);
|
1999-05-03 09:29:11 +02:00
|
|
|
|
if (p != NULL)
|
|
|
|
|
p += 4;
|
|
|
|
|
/* FIXME: How do we handle overflow here? */
|
|
|
|
|
offset_expr.X_add_number += 4;
|
2000-12-05 19:51:08 +01:00
|
|
|
|
/* Itbl support may require additional care here. */
|
1999-05-03 09:29:11 +02:00
|
|
|
|
macro_build (p, &icnt, &offset_expr, s, fmt,
|
|
|
|
|
coproc ? treg : treg + 1,
|
2003-06-30 14:44:25 +02:00
|
|
|
|
BFD_RELOC_LO16, AT);
|
2000-09-07 14:45:56 +02:00
|
|
|
|
}
|
1999-05-03 09:29:11 +02:00
|
|
|
|
else if (mips_pic == SVR4_PIC && ! mips_big_got)
|
|
|
|
|
{
|
|
|
|
|
int off;
|
|
|
|
|
|
|
|
|
|
/* If this is a reference to an external symbol, we want
|
|
|
|
|
lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
|
|
|
|
|
nop
|
|
|
|
|
<op> $treg,0($at)
|
|
|
|
|
<op> $treg+1,4($at)
|
|
|
|
|
Otherwise we want
|
|
|
|
|
lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
|
|
|
|
|
nop
|
|
|
|
|
<op> $treg,<sym>($at) (BFD_RELOC_LO16)
|
|
|
|
|
<op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
|
|
|
|
|
If there is a base register we add it to $at before the
|
|
|
|
|
lwc1 instructions. If there is a constant we include it
|
|
|
|
|
in the lwc1 instructions. */
|
|
|
|
|
used_at = 1;
|
|
|
|
|
expr1.X_add_number = offset_expr.X_add_number;
|
|
|
|
|
offset_expr.X_add_number = 0;
|
|
|
|
|
if (expr1.X_add_number < -0x8000
|
|
|
|
|
|| expr1.X_add_number >= 0x8000 - 4)
|
|
|
|
|
as_bad (_("PIC code offset overflow (max 16 signed bits)"));
|
|
|
|
|
if (breg == 0)
|
|
|
|
|
off = 0;
|
|
|
|
|
else
|
|
|
|
|
off = 4;
|
|
|
|
|
frag_grow (24 + off);
|
2003-06-30 14:44:25 +02:00
|
|
|
|
macro_build (NULL, &icnt, &offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
|
|
|
|
|
AT, BFD_RELOC_MIPS_GOT16, mips_gp_register);
|
|
|
|
|
macro_build (NULL, &icnt, NULL, "nop", "");
|
1999-05-03 09:29:11 +02:00
|
|
|
|
if (breg != 0)
|
2003-06-30 14:44:25 +02:00
|
|
|
|
macro_build (NULL, &icnt, NULL, ADDRESS_ADD_INSN, "d,v,t",
|
|
|
|
|
AT, breg, AT);
|
2000-12-05 19:51:08 +01:00
|
|
|
|
/* Itbl support may require additional care here. */
|
2003-06-30 14:44:25 +02:00
|
|
|
|
macro_build (NULL, &icnt, &expr1, s, fmt, coproc ? treg + 1 : treg,
|
|
|
|
|
BFD_RELOC_LO16, AT);
|
1999-05-03 09:29:11 +02:00
|
|
|
|
expr1.X_add_number += 4;
|
|
|
|
|
|
|
|
|
|
/* Set mips_optimize to 2 to avoid inserting an undesired
|
|
|
|
|
nop. */
|
|
|
|
|
hold_mips_optimize = mips_optimize;
|
|
|
|
|
mips_optimize = 2;
|
2000-12-05 19:51:08 +01:00
|
|
|
|
/* Itbl support may require additional care here. */
|
2003-06-30 14:44:25 +02:00
|
|
|
|
macro_build (NULL, &icnt, &expr1, s, fmt, coproc ? treg : treg + 1,
|
|
|
|
|
BFD_RELOC_LO16, AT);
|
1999-05-03 09:29:11 +02:00
|
|
|
|
mips_optimize = hold_mips_optimize;
|
|
|
|
|
|
|
|
|
|
(void) frag_var (rs_machine_dependent, 0, 0,
|
|
|
|
|
RELAX_ENCODE (0, 0, -16 - off, -8, 1, 0),
|
2001-11-12 23:19:30 +01:00
|
|
|
|
offset_expr.X_add_symbol, 0, NULL);
|
1999-05-03 09:29:11 +02:00
|
|
|
|
}
|
|
|
|
|
else if (mips_pic == SVR4_PIC)
|
|
|
|
|
{
|
|
|
|
|
int gpdel, off;
|
2002-05-26 20:46:37 +02:00
|
|
|
|
char *p;
|
1999-05-03 09:29:11 +02:00
|
|
|
|
|
|
|
|
|
/* If this is a reference to an external symbol, we want
|
|
|
|
|
lui $at,<sym> (BFD_RELOC_MIPS_GOT_HI16)
|
|
|
|
|
addu $at,$at,$gp
|
|
|
|
|
lw $at,<sym>($at) (BFD_RELOC_MIPS_GOT_LO16)
|
|
|
|
|
nop
|
|
|
|
|
<op> $treg,0($at)
|
|
|
|
|
<op> $treg+1,4($at)
|
|
|
|
|
Otherwise we want
|
|
|
|
|
lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
|
|
|
|
|
nop
|
|
|
|
|
<op> $treg,<sym>($at) (BFD_RELOC_LO16)
|
|
|
|
|
<op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
|
|
|
|
|
If there is a base register we add it to $at before the
|
|
|
|
|
lwc1 instructions. If there is a constant we include it
|
|
|
|
|
in the lwc1 instructions. */
|
|
|
|
|
used_at = 1;
|
|
|
|
|
expr1.X_add_number = offset_expr.X_add_number;
|
|
|
|
|
offset_expr.X_add_number = 0;
|
|
|
|
|
if (expr1.X_add_number < -0x8000
|
|
|
|
|
|| expr1.X_add_number >= 0x8000 - 4)
|
|
|
|
|
as_bad (_("PIC code offset overflow (max 16 signed bits)"));
|
2002-05-28 21:23:09 +02:00
|
|
|
|
if (reg_needs_delay (mips_gp_register))
|
1999-05-03 09:29:11 +02:00
|
|
|
|
gpdel = 4;
|
|
|
|
|
else
|
|
|
|
|
gpdel = 0;
|
|
|
|
|
if (breg == 0)
|
|
|
|
|
off = 0;
|
|
|
|
|
else
|
|
|
|
|
off = 4;
|
|
|
|
|
frag_grow (56);
|
2003-06-30 14:44:25 +02:00
|
|
|
|
macro_build (NULL, &icnt, &offset_expr, "lui", "t,u", AT,
|
|
|
|
|
BFD_RELOC_MIPS_GOT_HI16);
|
|
|
|
|
macro_build (NULL, &icnt, NULL, ADDRESS_ADD_INSN, "d,v,t",
|
|
|
|
|
AT, AT, mips_gp_register);
|
|
|
|
|
macro_build (NULL, &icnt, &offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
|
|
|
|
|
AT, BFD_RELOC_MIPS_GOT_LO16, AT);
|
|
|
|
|
macro_build (NULL, &icnt, NULL, "nop", "");
|
1999-05-03 09:29:11 +02:00
|
|
|
|
if (breg != 0)
|
2003-06-30 14:44:25 +02:00
|
|
|
|
macro_build (NULL, &icnt, NULL, ADDRESS_ADD_INSN, "d,v,t",
|
|
|
|
|
AT, breg, AT);
|
2000-12-05 19:51:08 +01:00
|
|
|
|
/* Itbl support may require additional care here. */
|
2003-06-30 14:44:25 +02:00
|
|
|
|
macro_build (NULL, &icnt, &expr1, s, fmt, coproc ? treg + 1 : treg,
|
|
|
|
|
BFD_RELOC_LO16, AT);
|
1999-05-03 09:29:11 +02:00
|
|
|
|
expr1.X_add_number += 4;
|
|
|
|
|
|
|
|
|
|
/* Set mips_optimize to 2 to avoid inserting an undesired
|
|
|
|
|
nop. */
|
|
|
|
|
hold_mips_optimize = mips_optimize;
|
|
|
|
|
mips_optimize = 2;
|
2000-12-05 19:51:08 +01:00
|
|
|
|
/* Itbl support may require additional care here. */
|
2003-06-30 14:44:25 +02:00
|
|
|
|
macro_build (NULL, &icnt, &expr1, s, fmt, coproc ? treg : treg + 1,
|
|
|
|
|
BFD_RELOC_LO16, AT);
|
1999-05-03 09:29:11 +02:00
|
|
|
|
mips_optimize = hold_mips_optimize;
|
|
|
|
|
expr1.X_add_number -= 4;
|
|
|
|
|
|
|
|
|
|
p = frag_var (rs_machine_dependent, 16 + gpdel + off, 0,
|
|
|
|
|
RELAX_ENCODE (24 + off, 16 + gpdel + off, gpdel,
|
|
|
|
|
8 + gpdel + off, 1, 0),
|
2001-11-12 23:19:30 +01:00
|
|
|
|
offset_expr.X_add_symbol, 0, NULL);
|
1999-05-03 09:29:11 +02:00
|
|
|
|
if (gpdel > 0)
|
|
|
|
|
{
|
2003-06-30 14:44:25 +02:00
|
|
|
|
macro_build (p, &icnt, NULL, "nop", "");
|
1999-05-03 09:29:11 +02:00
|
|
|
|
p += 4;
|
|
|
|
|
}
|
2003-06-30 14:44:25 +02:00
|
|
|
|
macro_build (p, &icnt, &offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
|
|
|
|
|
AT, BFD_RELOC_MIPS_GOT16, mips_gp_register);
|
1999-05-03 09:29:11 +02:00
|
|
|
|
p += 4;
|
2003-06-30 14:44:25 +02:00
|
|
|
|
macro_build (p, &icnt, NULL, "nop", "");
|
1999-05-03 09:29:11 +02:00
|
|
|
|
p += 4;
|
|
|
|
|
if (breg != 0)
|
|
|
|
|
{
|
2003-06-30 14:44:25 +02:00
|
|
|
|
macro_build (p, &icnt, NULL, ADDRESS_ADD_INSN, "d,v,t",
|
|
|
|
|
AT, breg, AT);
|
1999-05-03 09:29:11 +02:00
|
|
|
|
p += 4;
|
|
|
|
|
}
|
2000-12-05 19:51:08 +01:00
|
|
|
|
/* Itbl support may require additional care here. */
|
2003-06-30 14:44:25 +02:00
|
|
|
|
macro_build (p, &icnt, &expr1, s, fmt, coproc ? treg + 1 : treg,
|
|
|
|
|
BFD_RELOC_LO16, AT);
|
1999-05-03 09:29:11 +02:00
|
|
|
|
p += 4;
|
|
|
|
|
expr1.X_add_number += 4;
|
|
|
|
|
|
|
|
|
|
/* Set mips_optimize to 2 to avoid inserting an undesired
|
|
|
|
|
nop. */
|
|
|
|
|
hold_mips_optimize = mips_optimize;
|
|
|
|
|
mips_optimize = 2;
|
2000-12-05 19:51:08 +01:00
|
|
|
|
/* Itbl support may require additional care here. */
|
2003-06-30 14:44:25 +02:00
|
|
|
|
macro_build (p, &icnt, &expr1, s, fmt, coproc ? treg : treg + 1,
|
|
|
|
|
BFD_RELOC_LO16, AT);
|
1999-05-03 09:29:11 +02:00
|
|
|
|
mips_optimize = hold_mips_optimize;
|
|
|
|
|
}
|
|
|
|
|
else if (mips_pic == EMBEDDED_PIC)
|
|
|
|
|
{
|
|
|
|
|
/* If there is no base register, we use
|
2001-12-02 14:14:48 +01:00
|
|
|
|
<op> $treg,<sym>($gp) (BFD_RELOC_GPREL16)
|
|
|
|
|
<op> $treg+1,<sym>+4($gp) (BFD_RELOC_GPREL16)
|
1999-05-03 09:29:11 +02:00
|
|
|
|
If we have a base register, we use
|
|
|
|
|
addu $at,$breg,$gp
|
2001-12-02 14:14:48 +01:00
|
|
|
|
<op> $treg,<sym>($at) (BFD_RELOC_GPREL16)
|
|
|
|
|
<op> $treg+1,<sym>+4($at) (BFD_RELOC_GPREL16)
|
1999-05-03 09:29:11 +02:00
|
|
|
|
*/
|
|
|
|
|
if (breg == 0)
|
|
|
|
|
{
|
2002-05-28 21:23:09 +02:00
|
|
|
|
tempreg = mips_gp_register;
|
1999-05-03 09:29:11 +02:00
|
|
|
|
used_at = 0;
|
|
|
|
|
}
|
|
|
|
|
else
|
|
|
|
|
{
|
2003-06-30 14:44:25 +02:00
|
|
|
|
macro_build (NULL, &icnt, NULL, ADDRESS_ADD_INSN, "d,v,t",
|
|
|
|
|
AT, breg, mips_gp_register);
|
1999-05-03 09:29:11 +02:00
|
|
|
|
tempreg = AT;
|
|
|
|
|
used_at = 1;
|
|
|
|
|
}
|
|
|
|
|
|
2000-12-05 19:51:08 +01:00
|
|
|
|
/* Itbl support may require additional care here. */
|
2003-06-30 14:44:25 +02:00
|
|
|
|
macro_build (NULL, &icnt, &offset_expr, s, fmt,
|
1999-05-03 09:29:11 +02:00
|
|
|
|
coproc ? treg + 1 : treg,
|
2003-06-30 14:44:25 +02:00
|
|
|
|
BFD_RELOC_GPREL16, tempreg);
|
1999-05-03 09:29:11 +02:00
|
|
|
|
offset_expr.X_add_number += 4;
|
2000-12-05 19:51:08 +01:00
|
|
|
|
/* Itbl support may require additional care here. */
|
2003-06-30 14:44:25 +02:00
|
|
|
|
macro_build (NULL, &icnt, &offset_expr, s, fmt,
|
1999-05-03 09:29:11 +02:00
|
|
|
|
coproc ? treg : treg + 1,
|
2003-06-30 14:44:25 +02:00
|
|
|
|
BFD_RELOC_GPREL16, tempreg);
|
1999-05-03 09:29:11 +02:00
|
|
|
|
}
|
|
|
|
|
else
|
|
|
|
|
abort ();
|
|
|
|
|
|
|
|
|
|
if (! used_at)
|
|
|
|
|
return;
|
|
|
|
|
|
|
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
case M_LD_OB:
|
|
|
|
|
s = "lw";
|
|
|
|
|
goto sd_ob;
|
|
|
|
|
case M_SD_OB:
|
|
|
|
|
s = "sw";
|
|
|
|
|
sd_ob:
|
2001-08-02 12:15:24 +02:00
|
|
|
|
assert (HAVE_32BIT_ADDRESSES);
|
2003-06-30 14:44:25 +02:00
|
|
|
|
macro_build (NULL, &icnt, &offset_expr, s, "t,o(b)", treg,
|
|
|
|
|
BFD_RELOC_LO16, breg);
|
1999-05-03 09:29:11 +02:00
|
|
|
|
offset_expr.X_add_number += 4;
|
2003-06-30 14:44:25 +02:00
|
|
|
|
macro_build (NULL, &icnt, &offset_expr, s, "t,o(b)", treg + 1,
|
|
|
|
|
BFD_RELOC_LO16, breg);
|
1999-05-03 09:29:11 +02:00
|
|
|
|
return;
|
|
|
|
|
|
|
|
|
|
/* New code added to support COPZ instructions.
|
|
|
|
|
This code builds table entries out of the macros in mip_opcodes.
|
|
|
|
|
R4000 uses interlocks to handle coproc delays.
|
|
|
|
|
Other chips (like the R3000) require nops to be inserted for delays.
|
|
|
|
|
|
2001-08-11 17:15:15 +02:00
|
|
|
|
FIXME: Currently, we require that the user handle delays.
|
1999-05-03 09:29:11 +02:00
|
|
|
|
In order to fill delay slots for non-interlocked chips,
|
|
|
|
|
we must have a way to specify delays based on the coprocessor.
|
|
|
|
|
Eg. 4 cycles if load coproc reg from memory, 1 if in cache, etc.
|
|
|
|
|
What are the side-effects of the cop instruction?
|
|
|
|
|
What cache support might we have and what are its effects?
|
|
|
|
|
Both coprocessor & memory require delays. how long???
|
2000-09-07 14:45:56 +02:00
|
|
|
|
What registers are read/set/modified?
|
1999-05-03 09:29:11 +02:00
|
|
|
|
|
|
|
|
|
If an itbl is provided to interpret cop instructions,
|
2000-09-07 14:45:56 +02:00
|
|
|
|
this knowledge can be encoded in the itbl spec. */
|
1999-05-03 09:29:11 +02:00
|
|
|
|
|
|
|
|
|
case M_COP0:
|
|
|
|
|
s = "c0";
|
|
|
|
|
goto copz;
|
|
|
|
|
case M_COP1:
|
|
|
|
|
s = "c1";
|
|
|
|
|
goto copz;
|
|
|
|
|
case M_COP2:
|
|
|
|
|
s = "c2";
|
|
|
|
|
goto copz;
|
|
|
|
|
case M_COP3:
|
|
|
|
|
s = "c3";
|
|
|
|
|
copz:
|
|
|
|
|
/* For now we just do C (same as Cz). The parameter will be
|
|
|
|
|
stored in insn_opcode by mips_ip. */
|
2003-06-30 14:44:25 +02:00
|
|
|
|
macro_build (NULL, &icnt, NULL, s, "C", ip->insn_opcode);
|
1999-05-03 09:29:11 +02:00
|
|
|
|
return;
|
|
|
|
|
|
2001-08-10 18:24:32 +02:00
|
|
|
|
case M_MOVE:
|
|
|
|
|
move_register (&icnt, dreg, sreg);
|
|
|
|
|
return;
|
|
|
|
|
|
1999-05-03 09:29:11 +02:00
|
|
|
|
#ifdef LOSING_COMPILER
|
|
|
|
|
default:
|
|
|
|
|
/* Try and see if this is a new itbl instruction.
|
|
|
|
|
This code builds table entries out of the macros in mip_opcodes.
|
|
|
|
|
FIXME: For now we just assemble the expression and pass it's
|
|
|
|
|
value along as a 32-bit immediate.
|
2000-09-07 14:45:56 +02:00
|
|
|
|
We may want to have the assembler assemble this value,
|
1999-05-03 09:29:11 +02:00
|
|
|
|
so that we gain the assembler's knowledge of delay slots,
|
|
|
|
|
symbols, etc.
|
|
|
|
|
Would it be more efficient to use mask (id) here? */
|
2000-09-07 14:45:56 +02:00
|
|
|
|
if (itbl_have_entries
|
1999-05-03 09:29:11 +02:00
|
|
|
|
&& (immed_expr = itbl_assemble (ip->insn_mo->name, "")))
|
2000-12-05 19:51:08 +01:00
|
|
|
|
{
|
1999-05-03 09:29:11 +02:00
|
|
|
|
s = ip->insn_mo->name;
|
|
|
|
|
s2 = "cop3";
|
|
|
|
|
coproc = ITBL_DECODE_PNUM (immed_expr);;
|
2003-06-30 14:44:25 +02:00
|
|
|
|
macro_build (NULL, &icnt, &immed_expr, s, "C");
|
1999-05-03 09:29:11 +02:00
|
|
|
|
return;
|
2000-12-05 19:51:08 +01:00
|
|
|
|
}
|
1999-05-03 09:29:11 +02:00
|
|
|
|
macro2 (ip);
|
|
|
|
|
return;
|
|
|
|
|
}
|
|
|
|
|
if (mips_opts.noat)
|
|
|
|
|
as_warn (_("Macro used $at after \".set noat\""));
|
|
|
|
|
}
|
2000-09-07 14:45:56 +02:00
|
|
|
|
|
1999-05-03 09:29:11 +02:00
|
|
|
|
static void
|
2003-06-30 14:44:25 +02:00
|
|
|
|
macro2 (struct mips_cl_insn *ip)
|
1999-05-03 09:29:11 +02:00
|
|
|
|
{
|
|
|
|
|
register int treg, sreg, dreg, breg;
|
|
|
|
|
int tempreg;
|
|
|
|
|
int mask;
|
|
|
|
|
int icnt = 0;
|
|
|
|
|
int used_at;
|
|
|
|
|
expressionS expr1;
|
|
|
|
|
const char *s;
|
|
|
|
|
const char *s2;
|
|
|
|
|
const char *fmt;
|
|
|
|
|
int likely = 0;
|
|
|
|
|
int dbl = 0;
|
|
|
|
|
int coproc = 0;
|
|
|
|
|
int lr = 0;
|
|
|
|
|
int imm = 0;
|
|
|
|
|
int off;
|
|
|
|
|
offsetT maxnum;
|
|
|
|
|
bfd_reloc_code_real_type r;
|
|
|
|
|
char *p;
|
2000-09-07 14:45:56 +02:00
|
|
|
|
|
1999-05-03 09:29:11 +02:00
|
|
|
|
treg = (ip->insn_opcode >> 16) & 0x1f;
|
|
|
|
|
dreg = (ip->insn_opcode >> 11) & 0x1f;
|
|
|
|
|
sreg = breg = (ip->insn_opcode >> 21) & 0x1f;
|
|
|
|
|
mask = ip->insn_mo->mask;
|
2000-09-07 14:45:56 +02:00
|
|
|
|
|
1999-05-03 09:29:11 +02:00
|
|
|
|
expr1.X_op = O_constant;
|
|
|
|
|
expr1.X_op_symbol = NULL;
|
|
|
|
|
expr1.X_add_symbol = NULL;
|
|
|
|
|
expr1.X_add_number = 1;
|
2000-09-07 14:45:56 +02:00
|
|
|
|
|
1999-05-03 09:29:11 +02:00
|
|
|
|
switch (mask)
|
|
|
|
|
{
|
|
|
|
|
#endif /* LOSING_COMPILER */
|
|
|
|
|
|
|
|
|
|
case M_DMUL:
|
|
|
|
|
dbl = 1;
|
|
|
|
|
case M_MUL:
|
2003-06-30 14:44:25 +02:00
|
|
|
|
macro_build (NULL, &icnt, NULL, dbl ? "dmultu" : "multu", "s,t",
|
|
|
|
|
sreg, treg);
|
|
|
|
|
macro_build (NULL, &icnt, NULL, "mflo", "d", dreg);
|
1999-05-03 09:29:11 +02:00
|
|
|
|
return;
|
|
|
|
|
|
|
|
|
|
case M_DMUL_I:
|
|
|
|
|
dbl = 1;
|
|
|
|
|
case M_MUL_I:
|
|
|
|
|
/* The MIPS assembler some times generates shifts and adds. I'm
|
|
|
|
|
not trying to be that fancy. GCC should do this for us
|
|
|
|
|
anyway. */
|
|
|
|
|
load_register (&icnt, AT, &imm_expr, dbl);
|
2003-06-30 14:44:25 +02:00
|
|
|
|
macro_build (NULL, &icnt, NULL, dbl ? "dmult" : "mult", "s,t",
|
|
|
|
|
sreg, AT);
|
|
|
|
|
macro_build (NULL, &icnt, NULL, "mflo", "d", dreg);
|
1999-05-03 09:29:11 +02:00
|
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
case M_DMULO_I:
|
|
|
|
|
dbl = 1;
|
|
|
|
|
case M_MULO_I:
|
|
|
|
|
imm = 1;
|
|
|
|
|
goto do_mulo;
|
|
|
|
|
|
|
|
|
|
case M_DMULO:
|
|
|
|
|
dbl = 1;
|
|
|
|
|
case M_MULO:
|
|
|
|
|
do_mulo:
|
2002-11-30 09:39:46 +01:00
|
|
|
|
mips_emit_delays (TRUE);
|
1999-05-03 09:29:11 +02:00
|
|
|
|
++mips_opts.noreorder;
|
|
|
|
|
mips_any_noreorder = 1;
|
|
|
|
|
if (imm)
|
|
|
|
|
load_register (&icnt, AT, &imm_expr, dbl);
|
2003-06-30 14:44:25 +02:00
|
|
|
|
macro_build (NULL, &icnt, NULL, dbl ? "dmult" : "mult", "s,t",
|
|
|
|
|
sreg, imm ? AT : treg);
|
|
|
|
|
macro_build (NULL, &icnt, NULL, "mflo", "d", dreg);
|
|
|
|
|
macro_build (NULL, &icnt, NULL, dbl ? "dsra32" : "sra", "d,w,<",
|
|
|
|
|
dreg, dreg, RA);
|
|
|
|
|
macro_build (NULL, &icnt, NULL, "mfhi", "d", AT);
|
1999-05-03 09:29:11 +02:00
|
|
|
|
if (mips_trap)
|
2003-06-30 14:44:25 +02:00
|
|
|
|
macro_build (NULL, &icnt, NULL, "tne", "s,t,q", dreg, AT, 6);
|
1999-05-03 09:29:11 +02:00
|
|
|
|
else
|
|
|
|
|
{
|
|
|
|
|
expr1.X_add_number = 8;
|
2003-06-30 14:44:25 +02:00
|
|
|
|
macro_build (NULL, &icnt, &expr1, "beq", "s,t,p", dreg, AT);
|
|
|
|
|
macro_build (NULL, &icnt, NULL, "nop", "", 0);
|
|
|
|
|
macro_build (NULL, &icnt, NULL, "break", "c", 6);
|
1999-05-03 09:29:11 +02:00
|
|
|
|
}
|
|
|
|
|
--mips_opts.noreorder;
|
2003-06-30 14:44:25 +02:00
|
|
|
|
macro_build (NULL, &icnt, NULL, "mflo", "d", dreg);
|
1999-05-03 09:29:11 +02:00
|
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
case M_DMULOU_I:
|
|
|
|
|
dbl = 1;
|
|
|
|
|
case M_MULOU_I:
|
|
|
|
|
imm = 1;
|
|
|
|
|
goto do_mulou;
|
|
|
|
|
|
|
|
|
|
case M_DMULOU:
|
|
|
|
|
dbl = 1;
|
|
|
|
|
case M_MULOU:
|
|
|
|
|
do_mulou:
|
2002-11-30 09:39:46 +01:00
|
|
|
|
mips_emit_delays (TRUE);
|
1999-05-03 09:29:11 +02:00
|
|
|
|
++mips_opts.noreorder;
|
|
|
|
|
mips_any_noreorder = 1;
|
|
|
|
|
if (imm)
|
|
|
|
|
load_register (&icnt, AT, &imm_expr, dbl);
|
2003-06-30 14:44:25 +02:00
|
|
|
|
macro_build (NULL, &icnt, NULL, dbl ? "dmultu" : "multu", "s,t",
|
|
|
|
|
sreg, imm ? AT : treg);
|
|
|
|
|
macro_build (NULL, &icnt, NULL, "mfhi", "d", AT);
|
|
|
|
|
macro_build (NULL, &icnt, NULL, "mflo", "d", dreg);
|
1999-05-03 09:29:11 +02:00
|
|
|
|
if (mips_trap)
|
2003-06-30 14:44:25 +02:00
|
|
|
|
macro_build (NULL, &icnt, NULL, "tne", "s,t,q", AT, 0, 6);
|
1999-05-03 09:29:11 +02:00
|
|
|
|
else
|
|
|
|
|
{
|
|
|
|
|
expr1.X_add_number = 8;
|
2003-06-30 14:44:25 +02:00
|
|
|
|
macro_build (NULL, &icnt, &expr1, "beq", "s,t,p", AT, 0);
|
|
|
|
|
macro_build (NULL, &icnt, NULL, "nop", "", 0);
|
|
|
|
|
macro_build (NULL, &icnt, NULL, "break", "c", 6);
|
1999-05-03 09:29:11 +02:00
|
|
|
|
}
|
|
|
|
|
--mips_opts.noreorder;
|
|
|
|
|
break;
|
|
|
|
|
|
? gas/testsuite/gas/mips/rol64.d
? gas/testsuite/gas/mips/rol64.s
Index: gas/ChangeLog
===================================================================
RCS file: /cvs/src/src/gas/ChangeLog,v
retrieving revision 1.1334
diff -u -p -r1.1334 ChangeLog
--- gas/ChangeLog 21 May 2002 20:01:51 -0000 1.1334
+++ gas/ChangeLog 21 May 2002 23:32:51 -0000
@@ -1,3 +1,8 @@
+2002-05-22 Thiemo Seufer <seufer@csv.ica.uni-stuttgart.de>
+
+ * config/tc-mips.c (macro2): Add 64 bit drol, dror macros.
+ Optimize the rotate by zero case.
+
2002-05-21 Nick Clifton <nickc@cambridge.redhat.com>
* configure.in: Remove accidental enabling of bfd_gas=yes for
Index: gas/config/tc-mips.c
===================================================================
RCS file: /cvs/src/src/gas/config/tc-mips.c,v
retrieving revision 1.123
diff -u -p -r1.123 tc-mips.c
--- gas/config/tc-mips.c 14 May 2002 23:35:59 -0000 1.123
+++ gas/config/tc-mips.c 21 May 2002 23:32:52 -0000
@@ -6686,6 +6686,17 @@ macro2 (ip)
--mips_opts.noreorder;
break;
+ case M_DROL:
+ macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "dsubu",
+ "d,v,t", AT, 0, treg);
+ macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "dsrlv",
+ "d,t,s", AT, sreg, AT);
+ macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "dsllv",
+ "d,t,s", dreg, sreg, treg);
+ macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "or",
+ "d,v,t", dreg, dreg, AT);
+ break;
+
case M_ROL:
macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "subu",
"d,v,t", AT, 0, treg);
@@ -6697,15 +6708,55 @@ macro2 (ip)
"d,v,t", dreg, dreg, AT);
break;
+ case M_DROL_I:
+ {
+ unsigned int rot;
+ char *l, *r;
+
+ if (imm_expr.X_op != O_constant)
+ as_bad (_("rotate count too large"));
+ rot = imm_expr.X_add_number & 0x3f;
+ if (! rot)
+ break;
+ l = (rot < 0x20) ? "dsll" : "dsll32";
+ r = ((0x40 - rot) < 0x20) ? "dsrl" : "dsrl32";
+ rot &= 0x1f;
+ macro_build ((char *) NULL, &icnt, (expressionS *) NULL, l,
+ "d,w,<", AT, sreg, rot);
+ macro_build ((char *) NULL, &icnt, (expressionS *) NULL, r,
+ "d,w,<", dreg, sreg, (0x20 - rot) & 0x1f);
+ macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "or",
+ "d,v,t", dreg, dreg, AT);
+ }
+ break;
+
case M_ROL_I:
- if (imm_expr.X_op != O_constant)
- as_bad (_("rotate count too large"));
- macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "sll", "d,w,<",
- AT, sreg, (int) (imm_expr.X_add_number & 0x1f));
- macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "srl", "d,w,<",
- dreg, sreg, (int) ((0 - imm_expr.X_add_number) & 0x1f));
- macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "or", "d,v,t",
- dreg, dreg, AT);
+ {
+ unsigned int rot;
+
+ if (imm_expr.X_op != O_constant)
+ as_bad (_("rotate count too large"));
+ rot = imm_expr.X_add_number & 0x1f;
+ if (! rot)
+ break;
+ macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "sll",
+ "d,w,<", AT, sreg, rot);
+ macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "srl",
+ "d,w,<", dreg, sreg, (0x20 - rot) & 0x1f);
+ macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "or",
+ "d,v,t", dreg, dreg, AT);
+ }
+ break;
+
+ case M_DROR:
+ macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "dsubu",
+ "d,v,t", AT, 0, treg);
+ macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "dsllv",
+ "d,t,s", AT, sreg, AT);
+ macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "dsrlv",
+ "d,t,s", dreg, sreg, treg);
+ macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "or",
+ "d,v,t", dreg, dreg, AT);
break;
case M_ROR:
@@ -6719,15 +6770,44 @@ macro2 (ip)
"d,v,t", dreg, dreg, AT);
break;
+ case M_DROR_I:
+ {
+ unsigned int rot;
+ char *l, *r;
+
+ if (imm_expr.X_op != O_constant)
+ as_bad (_("rotate count too large"));
+ rot = imm_expr.X_add_number & 0x3f;
+ if (! rot)
+ break;
+ r = (rot < 0x20) ? "dsrl" : "dsrl32";
+ l = ((0x40 - rot) < 0x20) ? "dsll" : "dsll32";
+ rot &= 0x1f;
+ macro_build ((char *) NULL, &icnt, (expressionS *) NULL, r,
+ "d,w,<", AT, sreg, rot);
+ macro_build ((char *) NULL, &icnt, (expressionS *) NULL, l,
+ "d,w,<", dreg, sreg, (0x20 - rot) & 0x1f);
+ macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "or",
+ "d,v,t", dreg, dreg, AT);
+ }
+ break;
+
case M_ROR_I:
- if (imm_expr.X_op != O_constant)
- as_bad (_("rotate count too large"));
- macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "srl", "d,w,<",
- AT, sreg, (int) (imm_expr.X_add_number & 0x1f));
- macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "sll", "d,w,<",
- dreg, sreg, (int) ((0 - imm_expr.X_add_number) & 0x1f));
- macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "or", "d,v,t",
- dreg, dreg, AT);
+ {
+ unsigned int rot;
+
+ if (imm_expr.X_op != O_constant)
+ as_bad (_("rotate count too large"));
+ rot = imm_expr.X_add_number & 0x1f;
+ if (! rot)
+ break;
+ macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "srl",
+ "d,w,<", AT, sreg, rot);
+ macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "sll",
+ "d,w,<", dreg, sreg, (0x20 - rot) & 0x1f);
+ macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "or",
+ "d,v,t", dreg, dreg, AT);
+ }
break;
case M_S_DOB:
Index: gas/testsuite/ChangeLog
===================================================================
RCS file: /cvs/src/src/gas/testsuite/ChangeLog,v
retrieving revision 1.315
diff -u -p -r1.315 ChangeLog
--- gas/testsuite/ChangeLog 20 May 2002 17:05:34 -0000 1.315
+++ gas/testsuite/ChangeLog 21 May 2002 23:32:54 -0000
@@ -1,3 +1,9 @@
+2002-05-22 Thiemo Seufer <seufer@csv.ica.uni-stuttgart.de>
+
+ * gas/mips/rol64.s: New file, test of drol, dror macros.
+ * gas/mips/rol64.d: Likewise.
+ * gas/mips/mips.exp: Add new test.
+
2002-05-20 Nick Clifton <nickc@cambridge.redhat.com>
* gas/arm/arm.exp: Replace deprecated command line switches
Index: gas/testsuite/gas/mips/mips.exp
===================================================================
RCS file: /cvs/src/src/gas/testsuite/gas/mips/mips.exp,v
retrieving revision 1.32
diff -u -p -r1.32 mips.exp
--- gas/testsuite/gas/mips/mips.exp 4 Apr 2002 08:23:30 -0000 1.32
+++ gas/testsuite/gas/mips/mips.exp 21 May 2002 23:32:54 -0000
@@ -122,6 +122,7 @@ if { [istarget mips*-*-*] } then {
run_dump_test "mul"
}
run_dump_test "rol"
+ run_dump_test "rol64"
if !$aout { run_dump_test "sb" }
run_dump_test "trunc"
if !$aout { run_dump_test "ulh" }
Index: include/opcode/ChangeLog
===================================================================
RCS file: /cvs/src/src/include/opcode/ChangeLog,v
retrieving revision 1.167
diff -u -p -r1.167 ChangeLog
--- include/opcode/ChangeLog 17 May 2002 19:01:03 -0000 1.167
+++ include/opcode/ChangeLog 21 May 2002 23:32:57 -0000
@@ -1,3 +1,7 @@
+2002-05-22 Thiemo Seufer <seufer@csv.ica.uni-stuttgart.de>
+
+ * mips.h: Add M_DROL, M_DROL_I, M_DROR, M_DROR_I macro cases.
+
2002-05-17 Andrey Volkov <avolkov@sources.redhat.com>
* h8300.h: Corrected defs of all control regs
Index: include/opcode/mips.h
===================================================================
RCS file: /cvs/src/src/include/opcode/mips.h,v
retrieving revision 1.24
diff -u -p -r1.24 mips.h
--- include/opcode/mips.h 16 Mar 2002 03:09:18 -0000 1.24
+++ include/opcode/mips.h 21 May 2002 23:32:57 -0000
@@ -526,9 +526,13 @@ enum
M_REM_3I,
M_REMU_3,
M_REMU_3I,
+ M_DROL,
M_ROL,
+ M_DROL_I,
M_ROL_I,
+ M_DROR,
M_ROR,
+ M_DROR_I,
M_ROR_I,
M_S_DA,
M_S_DOB,
Index: opcodes/ChangeLog
===================================================================
RCS file: /cvs/src/src/opcodes/ChangeLog,v
retrieving revision 1.447
diff -u -p -r1.447 ChangeLog
--- opcodes/ChangeLog 17 May 2002 14:36:45 -0000 1.447
+++ opcodes/ChangeLog 21 May 2002 23:33:00 -0000
@@ -1,3 +1,7 @@
+2002-05-22 Thiemo Seufer <seufer@csv.ica.uni-stuttgart.de>
+
+ * mips-opc.c (mips_builtin_opcodes): Add drol, dror macros.
+
Fri May 17 14:26:44 2002 J"orn Rennecke <joern.rennecke@superh.com>
* disassemble.c (disassembler): Just use print_insn_sh for bfd_arch_sh.
Index: opcodes/mips-opc.c
===================================================================
RCS file: /cvs/src/src/opcodes/mips-opc.c,v
retrieving revision 1.32
diff -u -p -r1.32 mips-opc.c
--- opcodes/mips-opc.c 17 Mar 2002 02:42:25 -0000 1.32
+++ opcodes/mips-opc.c 21 May 2002 23:33:00 -0000
@@ -492,6 +492,10 @@ const struct mips_opcode mips_builtin_op
{"dremu", "z,s,t", 0x0000001f, 0xfc00ffff, RD_s|RD_t|WR_HILO, I3 },
{"dremu", "d,v,t", 3, (int) M_DREMU_3, INSN_MACRO, I3 },
{"dremu", "d,v,I", 3, (int) M_DREMU_3I, INSN_MACRO, I3 },
+{"drol", "d,v,t", 0, (int) M_DROL, INSN_MACRO, I3 },
+{"drol", "d,v,I", 0, (int) M_DROL_I, INSN_MACRO, I3 },
+{"dror", "d,v,t", 0, (int) M_DROR, INSN_MACRO, I3 },
+{"dror", "d,v,I", 0, (int) M_DROR_I, INSN_MACRO, I3 },
{"dsllv", "d,t,s", 0x00000014, 0xfc0007ff, WR_d|RD_t|RD_s, I3 },
{"dsll32", "d,w,<", 0x0000003c, 0xffe0003f, WR_d|RD_t, I3 },
{"dsll", "d,w,s", 0x00000014, 0xfc0007ff, WR_d|RD_t|RD_s, I3 }, /* dsllv */
2002-05-22 01:54:48 +02:00
|
|
|
|
case M_DROL:
|
2003-06-29 21:41:33 +02:00
|
|
|
|
if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch))
|
[ opcodes/ChangeLog ]
2002-12-18 Chris Demetriou <cgd@broadcom.com>
* mips-opc.c (mips_builtin_opcodes): Remove one "ror" and two
"dror" entries, and reorder the remaining "dror" and "ror" entries.
[ gas/ChangeLog ]
2002-12-18 Chris Demetriou <cgd@broadcom.com>
* config/tc-mips.c (macro): In M_DROL, M_DROR, M_ROL, and M_ROR,
use hardware rotate ops as appropriate. In M_DROL_I, M_DROR_I,
M_ROL_I, and M_ROR_I, simplify code, clean up warnings, and
arrange not to issue warnings about use of AT when AT is not
actually used.
[ gas/testsuite/ChangeLog ]
2002-12-18 Chris Demetriou <cgd@broadcom.com>
* gas/mips/rol.s: Add ".set noat" and some new instructions to test.
* gas/mips/rol64.s: Likewise.
* gas/mips/rol.l: New file.
* gas/mips/rol.d: Adjust to use rol.l and for rol.s changes.
* gas/mips/rol64.l: New file.
* gas/mips/rol64.d: Adjust to use rol64.l and for rol64.s changes.
* gas/mips/rol-hw.d: New file.
* gas/mips/rol-hw.l: New file.
* gas/mips/rol64-hw.d: New file.
* gas/mips/rol64-hw.l: New file.
* gas/mips/mips.exp: Run rol-hw and rol64-hw tests.
2002-12-18 23:52:48 +01:00
|
|
|
|
{
|
|
|
|
|
if (dreg == sreg)
|
|
|
|
|
{
|
|
|
|
|
tempreg = AT;
|
|
|
|
|
used_at = 1;
|
|
|
|
|
}
|
|
|
|
|
else
|
|
|
|
|
{
|
|
|
|
|
tempreg = dreg;
|
|
|
|
|
used_at = 0;
|
|
|
|
|
}
|
2003-06-30 14:44:25 +02:00
|
|
|
|
macro_build (NULL, &icnt, NULL, "dnegu", "d,w", tempreg, treg);
|
|
|
|
|
macro_build (NULL, &icnt, NULL, "drorv", "d,t,s", dreg, sreg,
|
|
|
|
|
tempreg);
|
[ opcodes/ChangeLog ]
2002-12-18 Chris Demetriou <cgd@broadcom.com>
* mips-opc.c (mips_builtin_opcodes): Remove one "ror" and two
"dror" entries, and reorder the remaining "dror" and "ror" entries.
[ gas/ChangeLog ]
2002-12-18 Chris Demetriou <cgd@broadcom.com>
* config/tc-mips.c (macro): In M_DROL, M_DROR, M_ROL, and M_ROR,
use hardware rotate ops as appropriate. In M_DROL_I, M_DROR_I,
M_ROL_I, and M_ROR_I, simplify code, clean up warnings, and
arrange not to issue warnings about use of AT when AT is not
actually used.
[ gas/testsuite/ChangeLog ]
2002-12-18 Chris Demetriou <cgd@broadcom.com>
* gas/mips/rol.s: Add ".set noat" and some new instructions to test.
* gas/mips/rol64.s: Likewise.
* gas/mips/rol.l: New file.
* gas/mips/rol.d: Adjust to use rol.l and for rol.s changes.
* gas/mips/rol64.l: New file.
* gas/mips/rol64.d: Adjust to use rol64.l and for rol64.s changes.
* gas/mips/rol-hw.d: New file.
* gas/mips/rol-hw.l: New file.
* gas/mips/rol64-hw.d: New file.
* gas/mips/rol64-hw.l: New file.
* gas/mips/mips.exp: Run rol-hw and rol64-hw tests.
2002-12-18 23:52:48 +01:00
|
|
|
|
if (used_at)
|
|
|
|
|
break;
|
|
|
|
|
return;
|
|
|
|
|
}
|
2003-06-30 14:44:25 +02:00
|
|
|
|
macro_build (NULL, &icnt, NULL, "dsubu", "d,v,t", AT, 0, treg);
|
|
|
|
|
macro_build (NULL, &icnt, NULL, "dsrlv", "d,t,s", AT, sreg, AT);
|
|
|
|
|
macro_build (NULL, &icnt, NULL, "dsllv", "d,t,s", dreg, sreg, treg);
|
|
|
|
|
macro_build (NULL, &icnt, NULL, "or", "d,v,t", dreg, dreg, AT);
|
? gas/testsuite/gas/mips/rol64.d
? gas/testsuite/gas/mips/rol64.s
Index: gas/ChangeLog
===================================================================
RCS file: /cvs/src/src/gas/ChangeLog,v
retrieving revision 1.1334
diff -u -p -r1.1334 ChangeLog
--- gas/ChangeLog 21 May 2002 20:01:51 -0000 1.1334
+++ gas/ChangeLog 21 May 2002 23:32:51 -0000
@@ -1,3 +1,8 @@
+2002-05-22 Thiemo Seufer <seufer@csv.ica.uni-stuttgart.de>
+
+ * config/tc-mips.c (macro2): Add 64 bit drol, dror macros.
+ Optimize the rotate by zero case.
+
2002-05-21 Nick Clifton <nickc@cambridge.redhat.com>
* configure.in: Remove accidental enabling of bfd_gas=yes for
Index: gas/config/tc-mips.c
===================================================================
RCS file: /cvs/src/src/gas/config/tc-mips.c,v
retrieving revision 1.123
diff -u -p -r1.123 tc-mips.c
--- gas/config/tc-mips.c 14 May 2002 23:35:59 -0000 1.123
+++ gas/config/tc-mips.c 21 May 2002 23:32:52 -0000
@@ -6686,6 +6686,17 @@ macro2 (ip)
--mips_opts.noreorder;
break;
+ case M_DROL:
+ macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "dsubu",
+ "d,v,t", AT, 0, treg);
+ macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "dsrlv",
+ "d,t,s", AT, sreg, AT);
+ macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "dsllv",
+ "d,t,s", dreg, sreg, treg);
+ macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "or",
+ "d,v,t", dreg, dreg, AT);
+ break;
+
case M_ROL:
macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "subu",
"d,v,t", AT, 0, treg);
@@ -6697,15 +6708,55 @@ macro2 (ip)
"d,v,t", dreg, dreg, AT);
break;
+ case M_DROL_I:
+ {
+ unsigned int rot;
+ char *l, *r;
+
+ if (imm_expr.X_op != O_constant)
+ as_bad (_("rotate count too large"));
+ rot = imm_expr.X_add_number & 0x3f;
+ if (! rot)
+ break;
+ l = (rot < 0x20) ? "dsll" : "dsll32";
+ r = ((0x40 - rot) < 0x20) ? "dsrl" : "dsrl32";
+ rot &= 0x1f;
+ macro_build ((char *) NULL, &icnt, (expressionS *) NULL, l,
+ "d,w,<", AT, sreg, rot);
+ macro_build ((char *) NULL, &icnt, (expressionS *) NULL, r,
+ "d,w,<", dreg, sreg, (0x20 - rot) & 0x1f);
+ macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "or",
+ "d,v,t", dreg, dreg, AT);
+ }
+ break;
+
case M_ROL_I:
- if (imm_expr.X_op != O_constant)
- as_bad (_("rotate count too large"));
- macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "sll", "d,w,<",
- AT, sreg, (int) (imm_expr.X_add_number & 0x1f));
- macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "srl", "d,w,<",
- dreg, sreg, (int) ((0 - imm_expr.X_add_number) & 0x1f));
- macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "or", "d,v,t",
- dreg, dreg, AT);
+ {
+ unsigned int rot;
+
+ if (imm_expr.X_op != O_constant)
+ as_bad (_("rotate count too large"));
+ rot = imm_expr.X_add_number & 0x1f;
+ if (! rot)
+ break;
+ macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "sll",
+ "d,w,<", AT, sreg, rot);
+ macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "srl",
+ "d,w,<", dreg, sreg, (0x20 - rot) & 0x1f);
+ macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "or",
+ "d,v,t", dreg, dreg, AT);
+ }
+ break;
+
+ case M_DROR:
+ macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "dsubu",
+ "d,v,t", AT, 0, treg);
+ macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "dsllv",
+ "d,t,s", AT, sreg, AT);
+ macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "dsrlv",
+ "d,t,s", dreg, sreg, treg);
+ macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "or",
+ "d,v,t", dreg, dreg, AT);
break;
case M_ROR:
@@ -6719,15 +6770,44 @@ macro2 (ip)
"d,v,t", dreg, dreg, AT);
break;
+ case M_DROR_I:
+ {
+ unsigned int rot;
+ char *l, *r;
+
+ if (imm_expr.X_op != O_constant)
+ as_bad (_("rotate count too large"));
+ rot = imm_expr.X_add_number & 0x3f;
+ if (! rot)
+ break;
+ r = (rot < 0x20) ? "dsrl" : "dsrl32";
+ l = ((0x40 - rot) < 0x20) ? "dsll" : "dsll32";
+ rot &= 0x1f;
+ macro_build ((char *) NULL, &icnt, (expressionS *) NULL, r,
+ "d,w,<", AT, sreg, rot);
+ macro_build ((char *) NULL, &icnt, (expressionS *) NULL, l,
+ "d,w,<", dreg, sreg, (0x20 - rot) & 0x1f);
+ macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "or",
+ "d,v,t", dreg, dreg, AT);
+ }
+ break;
+
case M_ROR_I:
- if (imm_expr.X_op != O_constant)
- as_bad (_("rotate count too large"));
- macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "srl", "d,w,<",
- AT, sreg, (int) (imm_expr.X_add_number & 0x1f));
- macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "sll", "d,w,<",
- dreg, sreg, (int) ((0 - imm_expr.X_add_number) & 0x1f));
- macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "or", "d,v,t",
- dreg, dreg, AT);
+ {
+ unsigned int rot;
+
+ if (imm_expr.X_op != O_constant)
+ as_bad (_("rotate count too large"));
+ rot = imm_expr.X_add_number & 0x1f;
+ if (! rot)
+ break;
+ macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "srl",
+ "d,w,<", AT, sreg, rot);
+ macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "sll",
+ "d,w,<", dreg, sreg, (0x20 - rot) & 0x1f);
+ macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "or",
+ "d,v,t", dreg, dreg, AT);
+ }
break;
case M_S_DOB:
Index: gas/testsuite/ChangeLog
===================================================================
RCS file: /cvs/src/src/gas/testsuite/ChangeLog,v
retrieving revision 1.315
diff -u -p -r1.315 ChangeLog
--- gas/testsuite/ChangeLog 20 May 2002 17:05:34 -0000 1.315
+++ gas/testsuite/ChangeLog 21 May 2002 23:32:54 -0000
@@ -1,3 +1,9 @@
+2002-05-22 Thiemo Seufer <seufer@csv.ica.uni-stuttgart.de>
+
+ * gas/mips/rol64.s: New file, test of drol, dror macros.
+ * gas/mips/rol64.d: Likewise.
+ * gas/mips/mips.exp: Add new test.
+
2002-05-20 Nick Clifton <nickc@cambridge.redhat.com>
* gas/arm/arm.exp: Replace deprecated command line switches
Index: gas/testsuite/gas/mips/mips.exp
===================================================================
RCS file: /cvs/src/src/gas/testsuite/gas/mips/mips.exp,v
retrieving revision 1.32
diff -u -p -r1.32 mips.exp
--- gas/testsuite/gas/mips/mips.exp 4 Apr 2002 08:23:30 -0000 1.32
+++ gas/testsuite/gas/mips/mips.exp 21 May 2002 23:32:54 -0000
@@ -122,6 +122,7 @@ if { [istarget mips*-*-*] } then {
run_dump_test "mul"
}
run_dump_test "rol"
+ run_dump_test "rol64"
if !$aout { run_dump_test "sb" }
run_dump_test "trunc"
if !$aout { run_dump_test "ulh" }
Index: include/opcode/ChangeLog
===================================================================
RCS file: /cvs/src/src/include/opcode/ChangeLog,v
retrieving revision 1.167
diff -u -p -r1.167 ChangeLog
--- include/opcode/ChangeLog 17 May 2002 19:01:03 -0000 1.167
+++ include/opcode/ChangeLog 21 May 2002 23:32:57 -0000
@@ -1,3 +1,7 @@
+2002-05-22 Thiemo Seufer <seufer@csv.ica.uni-stuttgart.de>
+
+ * mips.h: Add M_DROL, M_DROL_I, M_DROR, M_DROR_I macro cases.
+
2002-05-17 Andrey Volkov <avolkov@sources.redhat.com>
* h8300.h: Corrected defs of all control regs
Index: include/opcode/mips.h
===================================================================
RCS file: /cvs/src/src/include/opcode/mips.h,v
retrieving revision 1.24
diff -u -p -r1.24 mips.h
--- include/opcode/mips.h 16 Mar 2002 03:09:18 -0000 1.24
+++ include/opcode/mips.h 21 May 2002 23:32:57 -0000
@@ -526,9 +526,13 @@ enum
M_REM_3I,
M_REMU_3,
M_REMU_3I,
+ M_DROL,
M_ROL,
+ M_DROL_I,
M_ROL_I,
+ M_DROR,
M_ROR,
+ M_DROR_I,
M_ROR_I,
M_S_DA,
M_S_DOB,
Index: opcodes/ChangeLog
===================================================================
RCS file: /cvs/src/src/opcodes/ChangeLog,v
retrieving revision 1.447
diff -u -p -r1.447 ChangeLog
--- opcodes/ChangeLog 17 May 2002 14:36:45 -0000 1.447
+++ opcodes/ChangeLog 21 May 2002 23:33:00 -0000
@@ -1,3 +1,7 @@
+2002-05-22 Thiemo Seufer <seufer@csv.ica.uni-stuttgart.de>
+
+ * mips-opc.c (mips_builtin_opcodes): Add drol, dror macros.
+
Fri May 17 14:26:44 2002 J"orn Rennecke <joern.rennecke@superh.com>
* disassemble.c (disassembler): Just use print_insn_sh for bfd_arch_sh.
Index: opcodes/mips-opc.c
===================================================================
RCS file: /cvs/src/src/opcodes/mips-opc.c,v
retrieving revision 1.32
diff -u -p -r1.32 mips-opc.c
--- opcodes/mips-opc.c 17 Mar 2002 02:42:25 -0000 1.32
+++ opcodes/mips-opc.c 21 May 2002 23:33:00 -0000
@@ -492,6 +492,10 @@ const struct mips_opcode mips_builtin_op
{"dremu", "z,s,t", 0x0000001f, 0xfc00ffff, RD_s|RD_t|WR_HILO, I3 },
{"dremu", "d,v,t", 3, (int) M_DREMU_3, INSN_MACRO, I3 },
{"dremu", "d,v,I", 3, (int) M_DREMU_3I, INSN_MACRO, I3 },
+{"drol", "d,v,t", 0, (int) M_DROL, INSN_MACRO, I3 },
+{"drol", "d,v,I", 0, (int) M_DROL_I, INSN_MACRO, I3 },
+{"dror", "d,v,t", 0, (int) M_DROR, INSN_MACRO, I3 },
+{"dror", "d,v,I", 0, (int) M_DROR_I, INSN_MACRO, I3 },
{"dsllv", "d,t,s", 0x00000014, 0xfc0007ff, WR_d|RD_t|RD_s, I3 },
{"dsll32", "d,w,<", 0x0000003c, 0xffe0003f, WR_d|RD_t, I3 },
{"dsll", "d,w,s", 0x00000014, 0xfc0007ff, WR_d|RD_t|RD_s, I3 }, /* dsllv */
2002-05-22 01:54:48 +02:00
|
|
|
|
break;
|
|
|
|
|
|
1999-05-03 09:29:11 +02:00
|
|
|
|
case M_ROL:
|
2003-06-29 21:41:33 +02:00
|
|
|
|
if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch))
|
[ opcodes/ChangeLog ]
2002-12-18 Chris Demetriou <cgd@broadcom.com>
* mips-opc.c (mips_builtin_opcodes): Remove one "ror" and two
"dror" entries, and reorder the remaining "dror" and "ror" entries.
[ gas/ChangeLog ]
2002-12-18 Chris Demetriou <cgd@broadcom.com>
* config/tc-mips.c (macro): In M_DROL, M_DROR, M_ROL, and M_ROR,
use hardware rotate ops as appropriate. In M_DROL_I, M_DROR_I,
M_ROL_I, and M_ROR_I, simplify code, clean up warnings, and
arrange not to issue warnings about use of AT when AT is not
actually used.
[ gas/testsuite/ChangeLog ]
2002-12-18 Chris Demetriou <cgd@broadcom.com>
* gas/mips/rol.s: Add ".set noat" and some new instructions to test.
* gas/mips/rol64.s: Likewise.
* gas/mips/rol.l: New file.
* gas/mips/rol.d: Adjust to use rol.l and for rol.s changes.
* gas/mips/rol64.l: New file.
* gas/mips/rol64.d: Adjust to use rol64.l and for rol64.s changes.
* gas/mips/rol-hw.d: New file.
* gas/mips/rol-hw.l: New file.
* gas/mips/rol64-hw.d: New file.
* gas/mips/rol64-hw.l: New file.
* gas/mips/mips.exp: Run rol-hw and rol64-hw tests.
2002-12-18 23:52:48 +01:00
|
|
|
|
{
|
|
|
|
|
if (dreg == sreg)
|
|
|
|
|
{
|
|
|
|
|
tempreg = AT;
|
|
|
|
|
used_at = 1;
|
|
|
|
|
}
|
|
|
|
|
else
|
|
|
|
|
{
|
|
|
|
|
tempreg = dreg;
|
|
|
|
|
used_at = 0;
|
|
|
|
|
}
|
2003-06-30 14:44:25 +02:00
|
|
|
|
macro_build (NULL, &icnt, NULL, "negu", "d,w", tempreg, treg);
|
|
|
|
|
macro_build (NULL, &icnt, NULL, "rorv", "d,t,s", dreg, sreg,
|
|
|
|
|
tempreg);
|
[ opcodes/ChangeLog ]
2002-12-18 Chris Demetriou <cgd@broadcom.com>
* mips-opc.c (mips_builtin_opcodes): Remove one "ror" and two
"dror" entries, and reorder the remaining "dror" and "ror" entries.
[ gas/ChangeLog ]
2002-12-18 Chris Demetriou <cgd@broadcom.com>
* config/tc-mips.c (macro): In M_DROL, M_DROR, M_ROL, and M_ROR,
use hardware rotate ops as appropriate. In M_DROL_I, M_DROR_I,
M_ROL_I, and M_ROR_I, simplify code, clean up warnings, and
arrange not to issue warnings about use of AT when AT is not
actually used.
[ gas/testsuite/ChangeLog ]
2002-12-18 Chris Demetriou <cgd@broadcom.com>
* gas/mips/rol.s: Add ".set noat" and some new instructions to test.
* gas/mips/rol64.s: Likewise.
* gas/mips/rol.l: New file.
* gas/mips/rol.d: Adjust to use rol.l and for rol.s changes.
* gas/mips/rol64.l: New file.
* gas/mips/rol64.d: Adjust to use rol64.l and for rol64.s changes.
* gas/mips/rol-hw.d: New file.
* gas/mips/rol-hw.l: New file.
* gas/mips/rol64-hw.d: New file.
* gas/mips/rol64-hw.l: New file.
* gas/mips/mips.exp: Run rol-hw and rol64-hw tests.
2002-12-18 23:52:48 +01:00
|
|
|
|
if (used_at)
|
|
|
|
|
break;
|
|
|
|
|
return;
|
|
|
|
|
}
|
2003-06-30 14:44:25 +02:00
|
|
|
|
macro_build (NULL, &icnt, NULL, "subu", "d,v,t", AT, 0, treg);
|
|
|
|
|
macro_build (NULL, &icnt, NULL, "srlv", "d,t,s", AT, sreg, AT);
|
|
|
|
|
macro_build (NULL, &icnt, NULL, "sllv", "d,t,s", dreg, sreg, treg);
|
|
|
|
|
macro_build (NULL, &icnt, NULL, "or", "d,v,t", dreg, dreg, AT);
|
1999-05-03 09:29:11 +02:00
|
|
|
|
break;
|
|
|
|
|
|
? gas/testsuite/gas/mips/rol64.d
? gas/testsuite/gas/mips/rol64.s
Index: gas/ChangeLog
===================================================================
RCS file: /cvs/src/src/gas/ChangeLog,v
retrieving revision 1.1334
diff -u -p -r1.1334 ChangeLog
--- gas/ChangeLog 21 May 2002 20:01:51 -0000 1.1334
+++ gas/ChangeLog 21 May 2002 23:32:51 -0000
@@ -1,3 +1,8 @@
+2002-05-22 Thiemo Seufer <seufer@csv.ica.uni-stuttgart.de>
+
+ * config/tc-mips.c (macro2): Add 64 bit drol, dror macros.
+ Optimize the rotate by zero case.
+
2002-05-21 Nick Clifton <nickc@cambridge.redhat.com>
* configure.in: Remove accidental enabling of bfd_gas=yes for
Index: gas/config/tc-mips.c
===================================================================
RCS file: /cvs/src/src/gas/config/tc-mips.c,v
retrieving revision 1.123
diff -u -p -r1.123 tc-mips.c
--- gas/config/tc-mips.c 14 May 2002 23:35:59 -0000 1.123
+++ gas/config/tc-mips.c 21 May 2002 23:32:52 -0000
@@ -6686,6 +6686,17 @@ macro2 (ip)
--mips_opts.noreorder;
break;
+ case M_DROL:
+ macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "dsubu",
+ "d,v,t", AT, 0, treg);
+ macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "dsrlv",
+ "d,t,s", AT, sreg, AT);
+ macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "dsllv",
+ "d,t,s", dreg, sreg, treg);
+ macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "or",
+ "d,v,t", dreg, dreg, AT);
+ break;
+
case M_ROL:
macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "subu",
"d,v,t", AT, 0, treg);
@@ -6697,15 +6708,55 @@ macro2 (ip)
"d,v,t", dreg, dreg, AT);
break;
+ case M_DROL_I:
+ {
+ unsigned int rot;
+ char *l, *r;
+
+ if (imm_expr.X_op != O_constant)
+ as_bad (_("rotate count too large"));
+ rot = imm_expr.X_add_number & 0x3f;
+ if (! rot)
+ break;
+ l = (rot < 0x20) ? "dsll" : "dsll32";
+ r = ((0x40 - rot) < 0x20) ? "dsrl" : "dsrl32";
+ rot &= 0x1f;
+ macro_build ((char *) NULL, &icnt, (expressionS *) NULL, l,
+ "d,w,<", AT, sreg, rot);
+ macro_build ((char *) NULL, &icnt, (expressionS *) NULL, r,
+ "d,w,<", dreg, sreg, (0x20 - rot) & 0x1f);
+ macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "or",
+ "d,v,t", dreg, dreg, AT);
+ }
+ break;
+
case M_ROL_I:
- if (imm_expr.X_op != O_constant)
- as_bad (_("rotate count too large"));
- macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "sll", "d,w,<",
- AT, sreg, (int) (imm_expr.X_add_number & 0x1f));
- macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "srl", "d,w,<",
- dreg, sreg, (int) ((0 - imm_expr.X_add_number) & 0x1f));
- macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "or", "d,v,t",
- dreg, dreg, AT);
+ {
+ unsigned int rot;
+
+ if (imm_expr.X_op != O_constant)
+ as_bad (_("rotate count too large"));
+ rot = imm_expr.X_add_number & 0x1f;
+ if (! rot)
+ break;
+ macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "sll",
+ "d,w,<", AT, sreg, rot);
+ macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "srl",
+ "d,w,<", dreg, sreg, (0x20 - rot) & 0x1f);
+ macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "or",
+ "d,v,t", dreg, dreg, AT);
+ }
+ break;
+
+ case M_DROR:
+ macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "dsubu",
+ "d,v,t", AT, 0, treg);
+ macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "dsllv",
+ "d,t,s", AT, sreg, AT);
+ macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "dsrlv",
+ "d,t,s", dreg, sreg, treg);
+ macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "or",
+ "d,v,t", dreg, dreg, AT);
break;
case M_ROR:
@@ -6719,15 +6770,44 @@ macro2 (ip)
"d,v,t", dreg, dreg, AT);
break;
+ case M_DROR_I:
+ {
+ unsigned int rot;
+ char *l, *r;
+
+ if (imm_expr.X_op != O_constant)
+ as_bad (_("rotate count too large"));
+ rot = imm_expr.X_add_number & 0x3f;
+ if (! rot)
+ break;
+ r = (rot < 0x20) ? "dsrl" : "dsrl32";
+ l = ((0x40 - rot) < 0x20) ? "dsll" : "dsll32";
+ rot &= 0x1f;
+ macro_build ((char *) NULL, &icnt, (expressionS *) NULL, r,
+ "d,w,<", AT, sreg, rot);
+ macro_build ((char *) NULL, &icnt, (expressionS *) NULL, l,
+ "d,w,<", dreg, sreg, (0x20 - rot) & 0x1f);
+ macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "or",
+ "d,v,t", dreg, dreg, AT);
+ }
+ break;
+
case M_ROR_I:
- if (imm_expr.X_op != O_constant)
- as_bad (_("rotate count too large"));
- macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "srl", "d,w,<",
- AT, sreg, (int) (imm_expr.X_add_number & 0x1f));
- macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "sll", "d,w,<",
- dreg, sreg, (int) ((0 - imm_expr.X_add_number) & 0x1f));
- macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "or", "d,v,t",
- dreg, dreg, AT);
+ {
+ unsigned int rot;
+
+ if (imm_expr.X_op != O_constant)
+ as_bad (_("rotate count too large"));
+ rot = imm_expr.X_add_number & 0x1f;
+ if (! rot)
+ break;
+ macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "srl",
+ "d,w,<", AT, sreg, rot);
+ macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "sll",
+ "d,w,<", dreg, sreg, (0x20 - rot) & 0x1f);
+ macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "or",
+ "d,v,t", dreg, dreg, AT);
+ }
break;
case M_S_DOB:
Index: gas/testsuite/ChangeLog
===================================================================
RCS file: /cvs/src/src/gas/testsuite/ChangeLog,v
retrieving revision 1.315
diff -u -p -r1.315 ChangeLog
--- gas/testsuite/ChangeLog 20 May 2002 17:05:34 -0000 1.315
+++ gas/testsuite/ChangeLog 21 May 2002 23:32:54 -0000
@@ -1,3 +1,9 @@
+2002-05-22 Thiemo Seufer <seufer@csv.ica.uni-stuttgart.de>
+
+ * gas/mips/rol64.s: New file, test of drol, dror macros.
+ * gas/mips/rol64.d: Likewise.
+ * gas/mips/mips.exp: Add new test.
+
2002-05-20 Nick Clifton <nickc@cambridge.redhat.com>
* gas/arm/arm.exp: Replace deprecated command line switches
Index: gas/testsuite/gas/mips/mips.exp
===================================================================
RCS file: /cvs/src/src/gas/testsuite/gas/mips/mips.exp,v
retrieving revision 1.32
diff -u -p -r1.32 mips.exp
--- gas/testsuite/gas/mips/mips.exp 4 Apr 2002 08:23:30 -0000 1.32
+++ gas/testsuite/gas/mips/mips.exp 21 May 2002 23:32:54 -0000
@@ -122,6 +122,7 @@ if { [istarget mips*-*-*] } then {
run_dump_test "mul"
}
run_dump_test "rol"
+ run_dump_test "rol64"
if !$aout { run_dump_test "sb" }
run_dump_test "trunc"
if !$aout { run_dump_test "ulh" }
Index: include/opcode/ChangeLog
===================================================================
RCS file: /cvs/src/src/include/opcode/ChangeLog,v
retrieving revision 1.167
diff -u -p -r1.167 ChangeLog
--- include/opcode/ChangeLog 17 May 2002 19:01:03 -0000 1.167
+++ include/opcode/ChangeLog 21 May 2002 23:32:57 -0000
@@ -1,3 +1,7 @@
+2002-05-22 Thiemo Seufer <seufer@csv.ica.uni-stuttgart.de>
+
+ * mips.h: Add M_DROL, M_DROL_I, M_DROR, M_DROR_I macro cases.
+
2002-05-17 Andrey Volkov <avolkov@sources.redhat.com>
* h8300.h: Corrected defs of all control regs
Index: include/opcode/mips.h
===================================================================
RCS file: /cvs/src/src/include/opcode/mips.h,v
retrieving revision 1.24
diff -u -p -r1.24 mips.h
--- include/opcode/mips.h 16 Mar 2002 03:09:18 -0000 1.24
+++ include/opcode/mips.h 21 May 2002 23:32:57 -0000
@@ -526,9 +526,13 @@ enum
M_REM_3I,
M_REMU_3,
M_REMU_3I,
+ M_DROL,
M_ROL,
+ M_DROL_I,
M_ROL_I,
+ M_DROR,
M_ROR,
+ M_DROR_I,
M_ROR_I,
M_S_DA,
M_S_DOB,
Index: opcodes/ChangeLog
===================================================================
RCS file: /cvs/src/src/opcodes/ChangeLog,v
retrieving revision 1.447
diff -u -p -r1.447 ChangeLog
--- opcodes/ChangeLog 17 May 2002 14:36:45 -0000 1.447
+++ opcodes/ChangeLog 21 May 2002 23:33:00 -0000
@@ -1,3 +1,7 @@
+2002-05-22 Thiemo Seufer <seufer@csv.ica.uni-stuttgart.de>
+
+ * mips-opc.c (mips_builtin_opcodes): Add drol, dror macros.
+
Fri May 17 14:26:44 2002 J"orn Rennecke <joern.rennecke@superh.com>
* disassemble.c (disassembler): Just use print_insn_sh for bfd_arch_sh.
Index: opcodes/mips-opc.c
===================================================================
RCS file: /cvs/src/src/opcodes/mips-opc.c,v
retrieving revision 1.32
diff -u -p -r1.32 mips-opc.c
--- opcodes/mips-opc.c 17 Mar 2002 02:42:25 -0000 1.32
+++ opcodes/mips-opc.c 21 May 2002 23:33:00 -0000
@@ -492,6 +492,10 @@ const struct mips_opcode mips_builtin_op
{"dremu", "z,s,t", 0x0000001f, 0xfc00ffff, RD_s|RD_t|WR_HILO, I3 },
{"dremu", "d,v,t", 3, (int) M_DREMU_3, INSN_MACRO, I3 },
{"dremu", "d,v,I", 3, (int) M_DREMU_3I, INSN_MACRO, I3 },
+{"drol", "d,v,t", 0, (int) M_DROL, INSN_MACRO, I3 },
+{"drol", "d,v,I", 0, (int) M_DROL_I, INSN_MACRO, I3 },
+{"dror", "d,v,t", 0, (int) M_DROR, INSN_MACRO, I3 },
+{"dror", "d,v,I", 0, (int) M_DROR_I, INSN_MACRO, I3 },
{"dsllv", "d,t,s", 0x00000014, 0xfc0007ff, WR_d|RD_t|RD_s, I3 },
{"dsll32", "d,w,<", 0x0000003c, 0xffe0003f, WR_d|RD_t, I3 },
{"dsll", "d,w,s", 0x00000014, 0xfc0007ff, WR_d|RD_t|RD_s, I3 }, /* dsllv */
2002-05-22 01:54:48 +02:00
|
|
|
|
case M_DROL_I:
|
|
|
|
|
{
|
|
|
|
|
unsigned int rot;
|
[ opcodes/ChangeLog ]
2002-12-18 Chris Demetriou <cgd@broadcom.com>
* mips-opc.c (mips_builtin_opcodes): Remove one "ror" and two
"dror" entries, and reorder the remaining "dror" and "ror" entries.
[ gas/ChangeLog ]
2002-12-18 Chris Demetriou <cgd@broadcom.com>
* config/tc-mips.c (macro): In M_DROL, M_DROR, M_ROL, and M_ROR,
use hardware rotate ops as appropriate. In M_DROL_I, M_DROR_I,
M_ROL_I, and M_ROR_I, simplify code, clean up warnings, and
arrange not to issue warnings about use of AT when AT is not
actually used.
[ gas/testsuite/ChangeLog ]
2002-12-18 Chris Demetriou <cgd@broadcom.com>
* gas/mips/rol.s: Add ".set noat" and some new instructions to test.
* gas/mips/rol64.s: Likewise.
* gas/mips/rol.l: New file.
* gas/mips/rol.d: Adjust to use rol.l and for rol.s changes.
* gas/mips/rol64.l: New file.
* gas/mips/rol64.d: Adjust to use rol64.l and for rol64.s changes.
* gas/mips/rol-hw.d: New file.
* gas/mips/rol-hw.l: New file.
* gas/mips/rol64-hw.d: New file.
* gas/mips/rol64-hw.l: New file.
* gas/mips/mips.exp: Run rol-hw and rol64-hw tests.
2002-12-18 23:52:48 +01:00
|
|
|
|
char *l, *r;
|
? gas/testsuite/gas/mips/rol64.d
? gas/testsuite/gas/mips/rol64.s
Index: gas/ChangeLog
===================================================================
RCS file: /cvs/src/src/gas/ChangeLog,v
retrieving revision 1.1334
diff -u -p -r1.1334 ChangeLog
--- gas/ChangeLog 21 May 2002 20:01:51 -0000 1.1334
+++ gas/ChangeLog 21 May 2002 23:32:51 -0000
@@ -1,3 +1,8 @@
+2002-05-22 Thiemo Seufer <seufer@csv.ica.uni-stuttgart.de>
+
+ * config/tc-mips.c (macro2): Add 64 bit drol, dror macros.
+ Optimize the rotate by zero case.
+
2002-05-21 Nick Clifton <nickc@cambridge.redhat.com>
* configure.in: Remove accidental enabling of bfd_gas=yes for
Index: gas/config/tc-mips.c
===================================================================
RCS file: /cvs/src/src/gas/config/tc-mips.c,v
retrieving revision 1.123
diff -u -p -r1.123 tc-mips.c
--- gas/config/tc-mips.c 14 May 2002 23:35:59 -0000 1.123
+++ gas/config/tc-mips.c 21 May 2002 23:32:52 -0000
@@ -6686,6 +6686,17 @@ macro2 (ip)
--mips_opts.noreorder;
break;
+ case M_DROL:
+ macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "dsubu",
+ "d,v,t", AT, 0, treg);
+ macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "dsrlv",
+ "d,t,s", AT, sreg, AT);
+ macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "dsllv",
+ "d,t,s", dreg, sreg, treg);
+ macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "or",
+ "d,v,t", dreg, dreg, AT);
+ break;
+
case M_ROL:
macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "subu",
"d,v,t", AT, 0, treg);
@@ -6697,15 +6708,55 @@ macro2 (ip)
"d,v,t", dreg, dreg, AT);
break;
+ case M_DROL_I:
+ {
+ unsigned int rot;
+ char *l, *r;
+
+ if (imm_expr.X_op != O_constant)
+ as_bad (_("rotate count too large"));
+ rot = imm_expr.X_add_number & 0x3f;
+ if (! rot)
+ break;
+ l = (rot < 0x20) ? "dsll" : "dsll32";
+ r = ((0x40 - rot) < 0x20) ? "dsrl" : "dsrl32";
+ rot &= 0x1f;
+ macro_build ((char *) NULL, &icnt, (expressionS *) NULL, l,
+ "d,w,<", AT, sreg, rot);
+ macro_build ((char *) NULL, &icnt, (expressionS *) NULL, r,
+ "d,w,<", dreg, sreg, (0x20 - rot) & 0x1f);
+ macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "or",
+ "d,v,t", dreg, dreg, AT);
+ }
+ break;
+
case M_ROL_I:
- if (imm_expr.X_op != O_constant)
- as_bad (_("rotate count too large"));
- macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "sll", "d,w,<",
- AT, sreg, (int) (imm_expr.X_add_number & 0x1f));
- macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "srl", "d,w,<",
- dreg, sreg, (int) ((0 - imm_expr.X_add_number) & 0x1f));
- macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "or", "d,v,t",
- dreg, dreg, AT);
+ {
+ unsigned int rot;
+
+ if (imm_expr.X_op != O_constant)
+ as_bad (_("rotate count too large"));
+ rot = imm_expr.X_add_number & 0x1f;
+ if (! rot)
+ break;
+ macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "sll",
+ "d,w,<", AT, sreg, rot);
+ macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "srl",
+ "d,w,<", dreg, sreg, (0x20 - rot) & 0x1f);
+ macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "or",
+ "d,v,t", dreg, dreg, AT);
+ }
+ break;
+
+ case M_DROR:
+ macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "dsubu",
+ "d,v,t", AT, 0, treg);
+ macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "dsllv",
+ "d,t,s", AT, sreg, AT);
+ macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "dsrlv",
+ "d,t,s", dreg, sreg, treg);
+ macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "or",
+ "d,v,t", dreg, dreg, AT);
break;
case M_ROR:
@@ -6719,15 +6770,44 @@ macro2 (ip)
"d,v,t", dreg, dreg, AT);
break;
+ case M_DROR_I:
+ {
+ unsigned int rot;
+ char *l, *r;
+
+ if (imm_expr.X_op != O_constant)
+ as_bad (_("rotate count too large"));
+ rot = imm_expr.X_add_number & 0x3f;
+ if (! rot)
+ break;
+ r = (rot < 0x20) ? "dsrl" : "dsrl32";
+ l = ((0x40 - rot) < 0x20) ? "dsll" : "dsll32";
+ rot &= 0x1f;
+ macro_build ((char *) NULL, &icnt, (expressionS *) NULL, r,
+ "d,w,<", AT, sreg, rot);
+ macro_build ((char *) NULL, &icnt, (expressionS *) NULL, l,
+ "d,w,<", dreg, sreg, (0x20 - rot) & 0x1f);
+ macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "or",
+ "d,v,t", dreg, dreg, AT);
+ }
+ break;
+
case M_ROR_I:
- if (imm_expr.X_op != O_constant)
- as_bad (_("rotate count too large"));
- macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "srl", "d,w,<",
- AT, sreg, (int) (imm_expr.X_add_number & 0x1f));
- macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "sll", "d,w,<",
- dreg, sreg, (int) ((0 - imm_expr.X_add_number) & 0x1f));
- macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "or", "d,v,t",
- dreg, dreg, AT);
+ {
+ unsigned int rot;
+
+ if (imm_expr.X_op != O_constant)
+ as_bad (_("rotate count too large"));
+ rot = imm_expr.X_add_number & 0x1f;
+ if (! rot)
+ break;
+ macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "srl",
+ "d,w,<", AT, sreg, rot);
+ macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "sll",
+ "d,w,<", dreg, sreg, (0x20 - rot) & 0x1f);
+ macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "or",
+ "d,v,t", dreg, dreg, AT);
+ }
break;
case M_S_DOB:
Index: gas/testsuite/ChangeLog
===================================================================
RCS file: /cvs/src/src/gas/testsuite/ChangeLog,v
retrieving revision 1.315
diff -u -p -r1.315 ChangeLog
--- gas/testsuite/ChangeLog 20 May 2002 17:05:34 -0000 1.315
+++ gas/testsuite/ChangeLog 21 May 2002 23:32:54 -0000
@@ -1,3 +1,9 @@
+2002-05-22 Thiemo Seufer <seufer@csv.ica.uni-stuttgart.de>
+
+ * gas/mips/rol64.s: New file, test of drol, dror macros.
+ * gas/mips/rol64.d: Likewise.
+ * gas/mips/mips.exp: Add new test.
+
2002-05-20 Nick Clifton <nickc@cambridge.redhat.com>
* gas/arm/arm.exp: Replace deprecated command line switches
Index: gas/testsuite/gas/mips/mips.exp
===================================================================
RCS file: /cvs/src/src/gas/testsuite/gas/mips/mips.exp,v
retrieving revision 1.32
diff -u -p -r1.32 mips.exp
--- gas/testsuite/gas/mips/mips.exp 4 Apr 2002 08:23:30 -0000 1.32
+++ gas/testsuite/gas/mips/mips.exp 21 May 2002 23:32:54 -0000
@@ -122,6 +122,7 @@ if { [istarget mips*-*-*] } then {
run_dump_test "mul"
}
run_dump_test "rol"
+ run_dump_test "rol64"
if !$aout { run_dump_test "sb" }
run_dump_test "trunc"
if !$aout { run_dump_test "ulh" }
Index: include/opcode/ChangeLog
===================================================================
RCS file: /cvs/src/src/include/opcode/ChangeLog,v
retrieving revision 1.167
diff -u -p -r1.167 ChangeLog
--- include/opcode/ChangeLog 17 May 2002 19:01:03 -0000 1.167
+++ include/opcode/ChangeLog 21 May 2002 23:32:57 -0000
@@ -1,3 +1,7 @@
+2002-05-22 Thiemo Seufer <seufer@csv.ica.uni-stuttgart.de>
+
+ * mips.h: Add M_DROL, M_DROL_I, M_DROR, M_DROR_I macro cases.
+
2002-05-17 Andrey Volkov <avolkov@sources.redhat.com>
* h8300.h: Corrected defs of all control regs
Index: include/opcode/mips.h
===================================================================
RCS file: /cvs/src/src/include/opcode/mips.h,v
retrieving revision 1.24
diff -u -p -r1.24 mips.h
--- include/opcode/mips.h 16 Mar 2002 03:09:18 -0000 1.24
+++ include/opcode/mips.h 21 May 2002 23:32:57 -0000
@@ -526,9 +526,13 @@ enum
M_REM_3I,
M_REMU_3,
M_REMU_3I,
+ M_DROL,
M_ROL,
+ M_DROL_I,
M_ROL_I,
+ M_DROR,
M_ROR,
+ M_DROR_I,
M_ROR_I,
M_S_DA,
M_S_DOB,
Index: opcodes/ChangeLog
===================================================================
RCS file: /cvs/src/src/opcodes/ChangeLog,v
retrieving revision 1.447
diff -u -p -r1.447 ChangeLog
--- opcodes/ChangeLog 17 May 2002 14:36:45 -0000 1.447
+++ opcodes/ChangeLog 21 May 2002 23:33:00 -0000
@@ -1,3 +1,7 @@
+2002-05-22 Thiemo Seufer <seufer@csv.ica.uni-stuttgart.de>
+
+ * mips-opc.c (mips_builtin_opcodes): Add drol, dror macros.
+
Fri May 17 14:26:44 2002 J"orn Rennecke <joern.rennecke@superh.com>
* disassemble.c (disassembler): Just use print_insn_sh for bfd_arch_sh.
Index: opcodes/mips-opc.c
===================================================================
RCS file: /cvs/src/src/opcodes/mips-opc.c,v
retrieving revision 1.32
diff -u -p -r1.32 mips-opc.c
--- opcodes/mips-opc.c 17 Mar 2002 02:42:25 -0000 1.32
+++ opcodes/mips-opc.c 21 May 2002 23:33:00 -0000
@@ -492,6 +492,10 @@ const struct mips_opcode mips_builtin_op
{"dremu", "z,s,t", 0x0000001f, 0xfc00ffff, RD_s|RD_t|WR_HILO, I3 },
{"dremu", "d,v,t", 3, (int) M_DREMU_3, INSN_MACRO, I3 },
{"dremu", "d,v,I", 3, (int) M_DREMU_3I, INSN_MACRO, I3 },
+{"drol", "d,v,t", 0, (int) M_DROL, INSN_MACRO, I3 },
+{"drol", "d,v,I", 0, (int) M_DROL_I, INSN_MACRO, I3 },
+{"dror", "d,v,t", 0, (int) M_DROR, INSN_MACRO, I3 },
+{"dror", "d,v,I", 0, (int) M_DROR_I, INSN_MACRO, I3 },
{"dsllv", "d,t,s", 0x00000014, 0xfc0007ff, WR_d|RD_t|RD_s, I3 },
{"dsll32", "d,w,<", 0x0000003c, 0xffe0003f, WR_d|RD_t, I3 },
{"dsll", "d,w,s", 0x00000014, 0xfc0007ff, WR_d|RD_t|RD_s, I3 }, /* dsllv */
2002-05-22 01:54:48 +02:00
|
|
|
|
|
|
|
|
|
if (imm_expr.X_op != O_constant)
|
[ opcodes/ChangeLog ]
2002-12-18 Chris Demetriou <cgd@broadcom.com>
* mips-opc.c (mips_builtin_opcodes): Remove one "ror" and two
"dror" entries, and reorder the remaining "dror" and "ror" entries.
[ gas/ChangeLog ]
2002-12-18 Chris Demetriou <cgd@broadcom.com>
* config/tc-mips.c (macro): In M_DROL, M_DROR, M_ROL, and M_ROR,
use hardware rotate ops as appropriate. In M_DROL_I, M_DROR_I,
M_ROL_I, and M_ROR_I, simplify code, clean up warnings, and
arrange not to issue warnings about use of AT when AT is not
actually used.
[ gas/testsuite/ChangeLog ]
2002-12-18 Chris Demetriou <cgd@broadcom.com>
* gas/mips/rol.s: Add ".set noat" and some new instructions to test.
* gas/mips/rol64.s: Likewise.
* gas/mips/rol.l: New file.
* gas/mips/rol.d: Adjust to use rol.l and for rol.s changes.
* gas/mips/rol64.l: New file.
* gas/mips/rol64.d: Adjust to use rol64.l and for rol64.s changes.
* gas/mips/rol-hw.d: New file.
* gas/mips/rol-hw.l: New file.
* gas/mips/rol64-hw.d: New file.
* gas/mips/rol64-hw.l: New file.
* gas/mips/mips.exp: Run rol-hw and rol64-hw tests.
2002-12-18 23:52:48 +01:00
|
|
|
|
as_bad (_("Improper rotate count"));
|
? gas/testsuite/gas/mips/rol64.d
? gas/testsuite/gas/mips/rol64.s
Index: gas/ChangeLog
===================================================================
RCS file: /cvs/src/src/gas/ChangeLog,v
retrieving revision 1.1334
diff -u -p -r1.1334 ChangeLog
--- gas/ChangeLog 21 May 2002 20:01:51 -0000 1.1334
+++ gas/ChangeLog 21 May 2002 23:32:51 -0000
@@ -1,3 +1,8 @@
+2002-05-22 Thiemo Seufer <seufer@csv.ica.uni-stuttgart.de>
+
+ * config/tc-mips.c (macro2): Add 64 bit drol, dror macros.
+ Optimize the rotate by zero case.
+
2002-05-21 Nick Clifton <nickc@cambridge.redhat.com>
* configure.in: Remove accidental enabling of bfd_gas=yes for
Index: gas/config/tc-mips.c
===================================================================
RCS file: /cvs/src/src/gas/config/tc-mips.c,v
retrieving revision 1.123
diff -u -p -r1.123 tc-mips.c
--- gas/config/tc-mips.c 14 May 2002 23:35:59 -0000 1.123
+++ gas/config/tc-mips.c 21 May 2002 23:32:52 -0000
@@ -6686,6 +6686,17 @@ macro2 (ip)
--mips_opts.noreorder;
break;
+ case M_DROL:
+ macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "dsubu",
+ "d,v,t", AT, 0, treg);
+ macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "dsrlv",
+ "d,t,s", AT, sreg, AT);
+ macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "dsllv",
+ "d,t,s", dreg, sreg, treg);
+ macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "or",
+ "d,v,t", dreg, dreg, AT);
+ break;
+
case M_ROL:
macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "subu",
"d,v,t", AT, 0, treg);
@@ -6697,15 +6708,55 @@ macro2 (ip)
"d,v,t", dreg, dreg, AT);
break;
+ case M_DROL_I:
+ {
+ unsigned int rot;
+ char *l, *r;
+
+ if (imm_expr.X_op != O_constant)
+ as_bad (_("rotate count too large"));
+ rot = imm_expr.X_add_number & 0x3f;
+ if (! rot)
+ break;
+ l = (rot < 0x20) ? "dsll" : "dsll32";
+ r = ((0x40 - rot) < 0x20) ? "dsrl" : "dsrl32";
+ rot &= 0x1f;
+ macro_build ((char *) NULL, &icnt, (expressionS *) NULL, l,
+ "d,w,<", AT, sreg, rot);
+ macro_build ((char *) NULL, &icnt, (expressionS *) NULL, r,
+ "d,w,<", dreg, sreg, (0x20 - rot) & 0x1f);
+ macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "or",
+ "d,v,t", dreg, dreg, AT);
+ }
+ break;
+
case M_ROL_I:
- if (imm_expr.X_op != O_constant)
- as_bad (_("rotate count too large"));
- macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "sll", "d,w,<",
- AT, sreg, (int) (imm_expr.X_add_number & 0x1f));
- macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "srl", "d,w,<",
- dreg, sreg, (int) ((0 - imm_expr.X_add_number) & 0x1f));
- macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "or", "d,v,t",
- dreg, dreg, AT);
+ {
+ unsigned int rot;
+
+ if (imm_expr.X_op != O_constant)
+ as_bad (_("rotate count too large"));
+ rot = imm_expr.X_add_number & 0x1f;
+ if (! rot)
+ break;
+ macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "sll",
+ "d,w,<", AT, sreg, rot);
+ macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "srl",
+ "d,w,<", dreg, sreg, (0x20 - rot) & 0x1f);
+ macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "or",
+ "d,v,t", dreg, dreg, AT);
+ }
+ break;
+
+ case M_DROR:
+ macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "dsubu",
+ "d,v,t", AT, 0, treg);
+ macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "dsllv",
+ "d,t,s", AT, sreg, AT);
+ macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "dsrlv",
+ "d,t,s", dreg, sreg, treg);
+ macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "or",
+ "d,v,t", dreg, dreg, AT);
break;
case M_ROR:
@@ -6719,15 +6770,44 @@ macro2 (ip)
"d,v,t", dreg, dreg, AT);
break;
+ case M_DROR_I:
+ {
+ unsigned int rot;
+ char *l, *r;
+
+ if (imm_expr.X_op != O_constant)
+ as_bad (_("rotate count too large"));
+ rot = imm_expr.X_add_number & 0x3f;
+ if (! rot)
+ break;
+ r = (rot < 0x20) ? "dsrl" : "dsrl32";
+ l = ((0x40 - rot) < 0x20) ? "dsll" : "dsll32";
+ rot &= 0x1f;
+ macro_build ((char *) NULL, &icnt, (expressionS *) NULL, r,
+ "d,w,<", AT, sreg, rot);
+ macro_build ((char *) NULL, &icnt, (expressionS *) NULL, l,
+ "d,w,<", dreg, sreg, (0x20 - rot) & 0x1f);
+ macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "or",
+ "d,v,t", dreg, dreg, AT);
+ }
+ break;
+
case M_ROR_I:
- if (imm_expr.X_op != O_constant)
- as_bad (_("rotate count too large"));
- macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "srl", "d,w,<",
- AT, sreg, (int) (imm_expr.X_add_number & 0x1f));
- macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "sll", "d,w,<",
- dreg, sreg, (int) ((0 - imm_expr.X_add_number) & 0x1f));
- macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "or", "d,v,t",
- dreg, dreg, AT);
+ {
+ unsigned int rot;
+
+ if (imm_expr.X_op != O_constant)
+ as_bad (_("rotate count too large"));
+ rot = imm_expr.X_add_number & 0x1f;
+ if (! rot)
+ break;
+ macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "srl",
+ "d,w,<", AT, sreg, rot);
+ macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "sll",
+ "d,w,<", dreg, sreg, (0x20 - rot) & 0x1f);
+ macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "or",
+ "d,v,t", dreg, dreg, AT);
+ }
break;
case M_S_DOB:
Index: gas/testsuite/ChangeLog
===================================================================
RCS file: /cvs/src/src/gas/testsuite/ChangeLog,v
retrieving revision 1.315
diff -u -p -r1.315 ChangeLog
--- gas/testsuite/ChangeLog 20 May 2002 17:05:34 -0000 1.315
+++ gas/testsuite/ChangeLog 21 May 2002 23:32:54 -0000
@@ -1,3 +1,9 @@
+2002-05-22 Thiemo Seufer <seufer@csv.ica.uni-stuttgart.de>
+
+ * gas/mips/rol64.s: New file, test of drol, dror macros.
+ * gas/mips/rol64.d: Likewise.
+ * gas/mips/mips.exp: Add new test.
+
2002-05-20 Nick Clifton <nickc@cambridge.redhat.com>
* gas/arm/arm.exp: Replace deprecated command line switches
Index: gas/testsuite/gas/mips/mips.exp
===================================================================
RCS file: /cvs/src/src/gas/testsuite/gas/mips/mips.exp,v
retrieving revision 1.32
diff -u -p -r1.32 mips.exp
--- gas/testsuite/gas/mips/mips.exp 4 Apr 2002 08:23:30 -0000 1.32
+++ gas/testsuite/gas/mips/mips.exp 21 May 2002 23:32:54 -0000
@@ -122,6 +122,7 @@ if { [istarget mips*-*-*] } then {
run_dump_test "mul"
}
run_dump_test "rol"
+ run_dump_test "rol64"
if !$aout { run_dump_test "sb" }
run_dump_test "trunc"
if !$aout { run_dump_test "ulh" }
Index: include/opcode/ChangeLog
===================================================================
RCS file: /cvs/src/src/include/opcode/ChangeLog,v
retrieving revision 1.167
diff -u -p -r1.167 ChangeLog
--- include/opcode/ChangeLog 17 May 2002 19:01:03 -0000 1.167
+++ include/opcode/ChangeLog 21 May 2002 23:32:57 -0000
@@ -1,3 +1,7 @@
+2002-05-22 Thiemo Seufer <seufer@csv.ica.uni-stuttgart.de>
+
+ * mips.h: Add M_DROL, M_DROL_I, M_DROR, M_DROR_I macro cases.
+
2002-05-17 Andrey Volkov <avolkov@sources.redhat.com>
* h8300.h: Corrected defs of all control regs
Index: include/opcode/mips.h
===================================================================
RCS file: /cvs/src/src/include/opcode/mips.h,v
retrieving revision 1.24
diff -u -p -r1.24 mips.h
--- include/opcode/mips.h 16 Mar 2002 03:09:18 -0000 1.24
+++ include/opcode/mips.h 21 May 2002 23:32:57 -0000
@@ -526,9 +526,13 @@ enum
M_REM_3I,
M_REMU_3,
M_REMU_3I,
+ M_DROL,
M_ROL,
+ M_DROL_I,
M_ROL_I,
+ M_DROR,
M_ROR,
+ M_DROR_I,
M_ROR_I,
M_S_DA,
M_S_DOB,
Index: opcodes/ChangeLog
===================================================================
RCS file: /cvs/src/src/opcodes/ChangeLog,v
retrieving revision 1.447
diff -u -p -r1.447 ChangeLog
--- opcodes/ChangeLog 17 May 2002 14:36:45 -0000 1.447
+++ opcodes/ChangeLog 21 May 2002 23:33:00 -0000
@@ -1,3 +1,7 @@
+2002-05-22 Thiemo Seufer <seufer@csv.ica.uni-stuttgart.de>
+
+ * mips-opc.c (mips_builtin_opcodes): Add drol, dror macros.
+
Fri May 17 14:26:44 2002 J"orn Rennecke <joern.rennecke@superh.com>
* disassemble.c (disassembler): Just use print_insn_sh for bfd_arch_sh.
Index: opcodes/mips-opc.c
===================================================================
RCS file: /cvs/src/src/opcodes/mips-opc.c,v
retrieving revision 1.32
diff -u -p -r1.32 mips-opc.c
--- opcodes/mips-opc.c 17 Mar 2002 02:42:25 -0000 1.32
+++ opcodes/mips-opc.c 21 May 2002 23:33:00 -0000
@@ -492,6 +492,10 @@ const struct mips_opcode mips_builtin_op
{"dremu", "z,s,t", 0x0000001f, 0xfc00ffff, RD_s|RD_t|WR_HILO, I3 },
{"dremu", "d,v,t", 3, (int) M_DREMU_3, INSN_MACRO, I3 },
{"dremu", "d,v,I", 3, (int) M_DREMU_3I, INSN_MACRO, I3 },
+{"drol", "d,v,t", 0, (int) M_DROL, INSN_MACRO, I3 },
+{"drol", "d,v,I", 0, (int) M_DROL_I, INSN_MACRO, I3 },
+{"dror", "d,v,t", 0, (int) M_DROR, INSN_MACRO, I3 },
+{"dror", "d,v,I", 0, (int) M_DROR_I, INSN_MACRO, I3 },
{"dsllv", "d,t,s", 0x00000014, 0xfc0007ff, WR_d|RD_t|RD_s, I3 },
{"dsll32", "d,w,<", 0x0000003c, 0xffe0003f, WR_d|RD_t, I3 },
{"dsll", "d,w,s", 0x00000014, 0xfc0007ff, WR_d|RD_t|RD_s, I3 }, /* dsllv */
2002-05-22 01:54:48 +02:00
|
|
|
|
rot = imm_expr.X_add_number & 0x3f;
|
2003-06-29 21:41:33 +02:00
|
|
|
|
if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch))
|
[gas/]
* doc/c-mips.texi: Add entries for -march=vr4120,vr4130,vr4181,
vr5400 and vr5500. Add entry for -mfix-vr4122-bugs.
* config/tc-mips.c (CPU_HAS_DROR, CPU_HAS_ROR): New macros.
(hilo_interlocks): True for CPU_VR5500.
(gpr_interlocks, cop_interlocks): True for CPU_VR5400 and CPU_VR5500.
(mips_fix_vr4122_bugs): New.
(append_insn): Work around 4122 errors if mips_fix_vr4122_bugs.
(mips_emit_delays): Likewise.
(macro2) [M_DROLI]: Use dror or dror32 if CPU_HAS_DROR.
[M_ROLI]: Likewise ror if CPU_HAS_ROR.
(validate_mips_insn, mips_ip): Handle '[', ']', 'e' and '%'.
(OPTION_FIX_VR4122, OPTION_NO_FIX_VR4122): New options.
(md_longopts): Add -mfix-vr4122-bugs and -no-mfix-vr4122-bugs.
(OPTION_ELF_BASE): Bump.
(md_parse_option): Handle the new options.
(mips_cpu_info_table): Add entries for vr4120, vr4130, vr4181,
vr5400 and vr5500.
[gas/testsuite/]
* gas/mips/mips4100.[sd]: Move dmadd16 and madd16 checks to...
* gas/mips/vr4111.[sd]: ...this new test.
* gas/mips/vr4120.[sd],
* gas/mips/vr4122.[sd],
* gas/mips/vr5400.[sd],
* gas/mips/vr5500.[sd]: New tests.
* mips.exp: Run them.
2002-09-30 14:04:54 +02:00
|
|
|
|
{
|
|
|
|
|
rot = (64 - rot) & 0x3f;
|
|
|
|
|
if (rot >= 32)
|
2003-06-30 14:44:25 +02:00
|
|
|
|
macro_build (NULL, &icnt, NULL, "dror32", "d,w,<",
|
|
|
|
|
dreg, sreg, rot - 32);
|
[gas/]
* doc/c-mips.texi: Add entries for -march=vr4120,vr4130,vr4181,
vr5400 and vr5500. Add entry for -mfix-vr4122-bugs.
* config/tc-mips.c (CPU_HAS_DROR, CPU_HAS_ROR): New macros.
(hilo_interlocks): True for CPU_VR5500.
(gpr_interlocks, cop_interlocks): True for CPU_VR5400 and CPU_VR5500.
(mips_fix_vr4122_bugs): New.
(append_insn): Work around 4122 errors if mips_fix_vr4122_bugs.
(mips_emit_delays): Likewise.
(macro2) [M_DROLI]: Use dror or dror32 if CPU_HAS_DROR.
[M_ROLI]: Likewise ror if CPU_HAS_ROR.
(validate_mips_insn, mips_ip): Handle '[', ']', 'e' and '%'.
(OPTION_FIX_VR4122, OPTION_NO_FIX_VR4122): New options.
(md_longopts): Add -mfix-vr4122-bugs and -no-mfix-vr4122-bugs.
(OPTION_ELF_BASE): Bump.
(md_parse_option): Handle the new options.
(mips_cpu_info_table): Add entries for vr4120, vr4130, vr4181,
vr5400 and vr5500.
[gas/testsuite/]
* gas/mips/mips4100.[sd]: Move dmadd16 and madd16 checks to...
* gas/mips/vr4111.[sd]: ...this new test.
* gas/mips/vr4120.[sd],
* gas/mips/vr4122.[sd],
* gas/mips/vr5400.[sd],
* gas/mips/vr5500.[sd]: New tests.
* mips.exp: Run them.
2002-09-30 14:04:54 +02:00
|
|
|
|
else
|
2003-06-30 14:44:25 +02:00
|
|
|
|
macro_build (NULL, &icnt, NULL, "dror", "d,w,<",
|
|
|
|
|
dreg, sreg, rot);
|
[ opcodes/ChangeLog ]
2002-12-18 Chris Demetriou <cgd@broadcom.com>
* mips-opc.c (mips_builtin_opcodes): Remove one "ror" and two
"dror" entries, and reorder the remaining "dror" and "ror" entries.
[ gas/ChangeLog ]
2002-12-18 Chris Demetriou <cgd@broadcom.com>
* config/tc-mips.c (macro): In M_DROL, M_DROR, M_ROL, and M_ROR,
use hardware rotate ops as appropriate. In M_DROL_I, M_DROR_I,
M_ROL_I, and M_ROR_I, simplify code, clean up warnings, and
arrange not to issue warnings about use of AT when AT is not
actually used.
[ gas/testsuite/ChangeLog ]
2002-12-18 Chris Demetriou <cgd@broadcom.com>
* gas/mips/rol.s: Add ".set noat" and some new instructions to test.
* gas/mips/rol64.s: Likewise.
* gas/mips/rol.l: New file.
* gas/mips/rol.d: Adjust to use rol.l and for rol.s changes.
* gas/mips/rol64.l: New file.
* gas/mips/rol64.d: Adjust to use rol64.l and for rol64.s changes.
* gas/mips/rol-hw.d: New file.
* gas/mips/rol-hw.l: New file.
* gas/mips/rol64-hw.d: New file.
* gas/mips/rol64-hw.l: New file.
* gas/mips/mips.exp: Run rol-hw and rol64-hw tests.
2002-12-18 23:52:48 +01:00
|
|
|
|
return;
|
[gas/]
* doc/c-mips.texi: Add entries for -march=vr4120,vr4130,vr4181,
vr5400 and vr5500. Add entry for -mfix-vr4122-bugs.
* config/tc-mips.c (CPU_HAS_DROR, CPU_HAS_ROR): New macros.
(hilo_interlocks): True for CPU_VR5500.
(gpr_interlocks, cop_interlocks): True for CPU_VR5400 and CPU_VR5500.
(mips_fix_vr4122_bugs): New.
(append_insn): Work around 4122 errors if mips_fix_vr4122_bugs.
(mips_emit_delays): Likewise.
(macro2) [M_DROLI]: Use dror or dror32 if CPU_HAS_DROR.
[M_ROLI]: Likewise ror if CPU_HAS_ROR.
(validate_mips_insn, mips_ip): Handle '[', ']', 'e' and '%'.
(OPTION_FIX_VR4122, OPTION_NO_FIX_VR4122): New options.
(md_longopts): Add -mfix-vr4122-bugs and -no-mfix-vr4122-bugs.
(OPTION_ELF_BASE): Bump.
(md_parse_option): Handle the new options.
(mips_cpu_info_table): Add entries for vr4120, vr4130, vr4181,
vr5400 and vr5500.
[gas/testsuite/]
* gas/mips/mips4100.[sd]: Move dmadd16 and madd16 checks to...
* gas/mips/vr4111.[sd]: ...this new test.
* gas/mips/vr4120.[sd],
* gas/mips/vr4122.[sd],
* gas/mips/vr5400.[sd],
* gas/mips/vr5500.[sd]: New tests.
* mips.exp: Run them.
2002-09-30 14:04:54 +02:00
|
|
|
|
}
|
2002-08-20 10:28:35 +02:00
|
|
|
|
if (rot == 0)
|
|
|
|
|
{
|
2003-06-30 14:44:25 +02:00
|
|
|
|
macro_build (NULL, &icnt, NULL, "dsrl", "d,w,<", dreg, sreg, 0);
|
[ opcodes/ChangeLog ]
2002-12-18 Chris Demetriou <cgd@broadcom.com>
* mips-opc.c (mips_builtin_opcodes): Remove one "ror" and two
"dror" entries, and reorder the remaining "dror" and "ror" entries.
[ gas/ChangeLog ]
2002-12-18 Chris Demetriou <cgd@broadcom.com>
* config/tc-mips.c (macro): In M_DROL, M_DROR, M_ROL, and M_ROR,
use hardware rotate ops as appropriate. In M_DROL_I, M_DROR_I,
M_ROL_I, and M_ROR_I, simplify code, clean up warnings, and
arrange not to issue warnings about use of AT when AT is not
actually used.
[ gas/testsuite/ChangeLog ]
2002-12-18 Chris Demetriou <cgd@broadcom.com>
* gas/mips/rol.s: Add ".set noat" and some new instructions to test.
* gas/mips/rol64.s: Likewise.
* gas/mips/rol.l: New file.
* gas/mips/rol.d: Adjust to use rol.l and for rol.s changes.
* gas/mips/rol64.l: New file.
* gas/mips/rol64.d: Adjust to use rol64.l and for rol64.s changes.
* gas/mips/rol-hw.d: New file.
* gas/mips/rol-hw.l: New file.
* gas/mips/rol64-hw.d: New file.
* gas/mips/rol64-hw.l: New file.
* gas/mips/mips.exp: Run rol-hw and rol64-hw tests.
2002-12-18 23:52:48 +01:00
|
|
|
|
return;
|
2002-08-20 10:28:35 +02:00
|
|
|
|
}
|
[ opcodes/ChangeLog ]
2002-12-18 Chris Demetriou <cgd@broadcom.com>
* mips-opc.c (mips_builtin_opcodes): Remove one "ror" and two
"dror" entries, and reorder the remaining "dror" and "ror" entries.
[ gas/ChangeLog ]
2002-12-18 Chris Demetriou <cgd@broadcom.com>
* config/tc-mips.c (macro): In M_DROL, M_DROR, M_ROL, and M_ROR,
use hardware rotate ops as appropriate. In M_DROL_I, M_DROR_I,
M_ROL_I, and M_ROR_I, simplify code, clean up warnings, and
arrange not to issue warnings about use of AT when AT is not
actually used.
[ gas/testsuite/ChangeLog ]
2002-12-18 Chris Demetriou <cgd@broadcom.com>
* gas/mips/rol.s: Add ".set noat" and some new instructions to test.
* gas/mips/rol64.s: Likewise.
* gas/mips/rol.l: New file.
* gas/mips/rol.d: Adjust to use rol.l and for rol.s changes.
* gas/mips/rol64.l: New file.
* gas/mips/rol64.d: Adjust to use rol64.l and for rol64.s changes.
* gas/mips/rol-hw.d: New file.
* gas/mips/rol-hw.l: New file.
* gas/mips/rol64-hw.d: New file.
* gas/mips/rol64-hw.l: New file.
* gas/mips/mips.exp: Run rol-hw and rol64-hw tests.
2002-12-18 23:52:48 +01:00
|
|
|
|
l = (rot < 0x20) ? "dsll" : "dsll32";
|
|
|
|
|
r = ((0x40 - rot) < 0x20) ? "dsrl" : "dsrl32";
|
|
|
|
|
rot &= 0x1f;
|
2003-06-30 14:44:25 +02:00
|
|
|
|
macro_build (NULL, &icnt, NULL, l, "d,w,<", AT, sreg, rot);
|
|
|
|
|
macro_build (NULL, &icnt, NULL, r, "d,w,<", dreg, sreg,
|
|
|
|
|
(0x20 - rot) & 0x1f);
|
|
|
|
|
macro_build (NULL, &icnt, NULL, "or", "d,v,t", dreg, dreg, AT);
|
? gas/testsuite/gas/mips/rol64.d
? gas/testsuite/gas/mips/rol64.s
Index: gas/ChangeLog
===================================================================
RCS file: /cvs/src/src/gas/ChangeLog,v
retrieving revision 1.1334
diff -u -p -r1.1334 ChangeLog
--- gas/ChangeLog 21 May 2002 20:01:51 -0000 1.1334
+++ gas/ChangeLog 21 May 2002 23:32:51 -0000
@@ -1,3 +1,8 @@
+2002-05-22 Thiemo Seufer <seufer@csv.ica.uni-stuttgart.de>
+
+ * config/tc-mips.c (macro2): Add 64 bit drol, dror macros.
+ Optimize the rotate by zero case.
+
2002-05-21 Nick Clifton <nickc@cambridge.redhat.com>
* configure.in: Remove accidental enabling of bfd_gas=yes for
Index: gas/config/tc-mips.c
===================================================================
RCS file: /cvs/src/src/gas/config/tc-mips.c,v
retrieving revision 1.123
diff -u -p -r1.123 tc-mips.c
--- gas/config/tc-mips.c 14 May 2002 23:35:59 -0000 1.123
+++ gas/config/tc-mips.c 21 May 2002 23:32:52 -0000
@@ -6686,6 +6686,17 @@ macro2 (ip)
--mips_opts.noreorder;
break;
+ case M_DROL:
+ macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "dsubu",
+ "d,v,t", AT, 0, treg);
+ macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "dsrlv",
+ "d,t,s", AT, sreg, AT);
+ macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "dsllv",
+ "d,t,s", dreg, sreg, treg);
+ macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "or",
+ "d,v,t", dreg, dreg, AT);
+ break;
+
case M_ROL:
macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "subu",
"d,v,t", AT, 0, treg);
@@ -6697,15 +6708,55 @@ macro2 (ip)
"d,v,t", dreg, dreg, AT);
break;
+ case M_DROL_I:
+ {
+ unsigned int rot;
+ char *l, *r;
+
+ if (imm_expr.X_op != O_constant)
+ as_bad (_("rotate count too large"));
+ rot = imm_expr.X_add_number & 0x3f;
+ if (! rot)
+ break;
+ l = (rot < 0x20) ? "dsll" : "dsll32";
+ r = ((0x40 - rot) < 0x20) ? "dsrl" : "dsrl32";
+ rot &= 0x1f;
+ macro_build ((char *) NULL, &icnt, (expressionS *) NULL, l,
+ "d,w,<", AT, sreg, rot);
+ macro_build ((char *) NULL, &icnt, (expressionS *) NULL, r,
+ "d,w,<", dreg, sreg, (0x20 - rot) & 0x1f);
+ macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "or",
+ "d,v,t", dreg, dreg, AT);
+ }
+ break;
+
case M_ROL_I:
- if (imm_expr.X_op != O_constant)
- as_bad (_("rotate count too large"));
- macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "sll", "d,w,<",
- AT, sreg, (int) (imm_expr.X_add_number & 0x1f));
- macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "srl", "d,w,<",
- dreg, sreg, (int) ((0 - imm_expr.X_add_number) & 0x1f));
- macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "or", "d,v,t",
- dreg, dreg, AT);
+ {
+ unsigned int rot;
+
+ if (imm_expr.X_op != O_constant)
+ as_bad (_("rotate count too large"));
+ rot = imm_expr.X_add_number & 0x1f;
+ if (! rot)
+ break;
+ macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "sll",
+ "d,w,<", AT, sreg, rot);
+ macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "srl",
+ "d,w,<", dreg, sreg, (0x20 - rot) & 0x1f);
+ macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "or",
+ "d,v,t", dreg, dreg, AT);
+ }
+ break;
+
+ case M_DROR:
+ macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "dsubu",
+ "d,v,t", AT, 0, treg);
+ macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "dsllv",
+ "d,t,s", AT, sreg, AT);
+ macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "dsrlv",
+ "d,t,s", dreg, sreg, treg);
+ macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "or",
+ "d,v,t", dreg, dreg, AT);
break;
case M_ROR:
@@ -6719,15 +6770,44 @@ macro2 (ip)
"d,v,t", dreg, dreg, AT);
break;
+ case M_DROR_I:
+ {
+ unsigned int rot;
+ char *l, *r;
+
+ if (imm_expr.X_op != O_constant)
+ as_bad (_("rotate count too large"));
+ rot = imm_expr.X_add_number & 0x3f;
+ if (! rot)
+ break;
+ r = (rot < 0x20) ? "dsrl" : "dsrl32";
+ l = ((0x40 - rot) < 0x20) ? "dsll" : "dsll32";
+ rot &= 0x1f;
+ macro_build ((char *) NULL, &icnt, (expressionS *) NULL, r,
+ "d,w,<", AT, sreg, rot);
+ macro_build ((char *) NULL, &icnt, (expressionS *) NULL, l,
+ "d,w,<", dreg, sreg, (0x20 - rot) & 0x1f);
+ macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "or",
+ "d,v,t", dreg, dreg, AT);
+ }
+ break;
+
case M_ROR_I:
- if (imm_expr.X_op != O_constant)
- as_bad (_("rotate count too large"));
- macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "srl", "d,w,<",
- AT, sreg, (int) (imm_expr.X_add_number & 0x1f));
- macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "sll", "d,w,<",
- dreg, sreg, (int) ((0 - imm_expr.X_add_number) & 0x1f));
- macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "or", "d,v,t",
- dreg, dreg, AT);
+ {
+ unsigned int rot;
+
+ if (imm_expr.X_op != O_constant)
+ as_bad (_("rotate count too large"));
+ rot = imm_expr.X_add_number & 0x1f;
+ if (! rot)
+ break;
+ macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "srl",
+ "d,w,<", AT, sreg, rot);
+ macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "sll",
+ "d,w,<", dreg, sreg, (0x20 - rot) & 0x1f);
+ macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "or",
+ "d,v,t", dreg, dreg, AT);
+ }
break;
case M_S_DOB:
Index: gas/testsuite/ChangeLog
===================================================================
RCS file: /cvs/src/src/gas/testsuite/ChangeLog,v
retrieving revision 1.315
diff -u -p -r1.315 ChangeLog
--- gas/testsuite/ChangeLog 20 May 2002 17:05:34 -0000 1.315
+++ gas/testsuite/ChangeLog 21 May 2002 23:32:54 -0000
@@ -1,3 +1,9 @@
+2002-05-22 Thiemo Seufer <seufer@csv.ica.uni-stuttgart.de>
+
+ * gas/mips/rol64.s: New file, test of drol, dror macros.
+ * gas/mips/rol64.d: Likewise.
+ * gas/mips/mips.exp: Add new test.
+
2002-05-20 Nick Clifton <nickc@cambridge.redhat.com>
* gas/arm/arm.exp: Replace deprecated command line switches
Index: gas/testsuite/gas/mips/mips.exp
===================================================================
RCS file: /cvs/src/src/gas/testsuite/gas/mips/mips.exp,v
retrieving revision 1.32
diff -u -p -r1.32 mips.exp
--- gas/testsuite/gas/mips/mips.exp 4 Apr 2002 08:23:30 -0000 1.32
+++ gas/testsuite/gas/mips/mips.exp 21 May 2002 23:32:54 -0000
@@ -122,6 +122,7 @@ if { [istarget mips*-*-*] } then {
run_dump_test "mul"
}
run_dump_test "rol"
+ run_dump_test "rol64"
if !$aout { run_dump_test "sb" }
run_dump_test "trunc"
if !$aout { run_dump_test "ulh" }
Index: include/opcode/ChangeLog
===================================================================
RCS file: /cvs/src/src/include/opcode/ChangeLog,v
retrieving revision 1.167
diff -u -p -r1.167 ChangeLog
--- include/opcode/ChangeLog 17 May 2002 19:01:03 -0000 1.167
+++ include/opcode/ChangeLog 21 May 2002 23:32:57 -0000
@@ -1,3 +1,7 @@
+2002-05-22 Thiemo Seufer <seufer@csv.ica.uni-stuttgart.de>
+
+ * mips.h: Add M_DROL, M_DROL_I, M_DROR, M_DROR_I macro cases.
+
2002-05-17 Andrey Volkov <avolkov@sources.redhat.com>
* h8300.h: Corrected defs of all control regs
Index: include/opcode/mips.h
===================================================================
RCS file: /cvs/src/src/include/opcode/mips.h,v
retrieving revision 1.24
diff -u -p -r1.24 mips.h
--- include/opcode/mips.h 16 Mar 2002 03:09:18 -0000 1.24
+++ include/opcode/mips.h 21 May 2002 23:32:57 -0000
@@ -526,9 +526,13 @@ enum
M_REM_3I,
M_REMU_3,
M_REMU_3I,
+ M_DROL,
M_ROL,
+ M_DROL_I,
M_ROL_I,
+ M_DROR,
M_ROR,
+ M_DROR_I,
M_ROR_I,
M_S_DA,
M_S_DOB,
Index: opcodes/ChangeLog
===================================================================
RCS file: /cvs/src/src/opcodes/ChangeLog,v
retrieving revision 1.447
diff -u -p -r1.447 ChangeLog
--- opcodes/ChangeLog 17 May 2002 14:36:45 -0000 1.447
+++ opcodes/ChangeLog 21 May 2002 23:33:00 -0000
@@ -1,3 +1,7 @@
+2002-05-22 Thiemo Seufer <seufer@csv.ica.uni-stuttgart.de>
+
+ * mips-opc.c (mips_builtin_opcodes): Add drol, dror macros.
+
Fri May 17 14:26:44 2002 J"orn Rennecke <joern.rennecke@superh.com>
* disassemble.c (disassembler): Just use print_insn_sh for bfd_arch_sh.
Index: opcodes/mips-opc.c
===================================================================
RCS file: /cvs/src/src/opcodes/mips-opc.c,v
retrieving revision 1.32
diff -u -p -r1.32 mips-opc.c
--- opcodes/mips-opc.c 17 Mar 2002 02:42:25 -0000 1.32
+++ opcodes/mips-opc.c 21 May 2002 23:33:00 -0000
@@ -492,6 +492,10 @@ const struct mips_opcode mips_builtin_op
{"dremu", "z,s,t", 0x0000001f, 0xfc00ffff, RD_s|RD_t|WR_HILO, I3 },
{"dremu", "d,v,t", 3, (int) M_DREMU_3, INSN_MACRO, I3 },
{"dremu", "d,v,I", 3, (int) M_DREMU_3I, INSN_MACRO, I3 },
+{"drol", "d,v,t", 0, (int) M_DROL, INSN_MACRO, I3 },
+{"drol", "d,v,I", 0, (int) M_DROL_I, INSN_MACRO, I3 },
+{"dror", "d,v,t", 0, (int) M_DROR, INSN_MACRO, I3 },
+{"dror", "d,v,I", 0, (int) M_DROR_I, INSN_MACRO, I3 },
{"dsllv", "d,t,s", 0x00000014, 0xfc0007ff, WR_d|RD_t|RD_s, I3 },
{"dsll32", "d,w,<", 0x0000003c, 0xffe0003f, WR_d|RD_t, I3 },
{"dsll", "d,w,s", 0x00000014, 0xfc0007ff, WR_d|RD_t|RD_s, I3 }, /* dsllv */
2002-05-22 01:54:48 +02:00
|
|
|
|
}
|
|
|
|
|
break;
|
|
|
|
|
|
1999-05-03 09:29:11 +02:00
|
|
|
|
case M_ROL_I:
|
? gas/testsuite/gas/mips/rol64.d
? gas/testsuite/gas/mips/rol64.s
Index: gas/ChangeLog
===================================================================
RCS file: /cvs/src/src/gas/ChangeLog,v
retrieving revision 1.1334
diff -u -p -r1.1334 ChangeLog
--- gas/ChangeLog 21 May 2002 20:01:51 -0000 1.1334
+++ gas/ChangeLog 21 May 2002 23:32:51 -0000
@@ -1,3 +1,8 @@
+2002-05-22 Thiemo Seufer <seufer@csv.ica.uni-stuttgart.de>
+
+ * config/tc-mips.c (macro2): Add 64 bit drol, dror macros.
+ Optimize the rotate by zero case.
+
2002-05-21 Nick Clifton <nickc@cambridge.redhat.com>
* configure.in: Remove accidental enabling of bfd_gas=yes for
Index: gas/config/tc-mips.c
===================================================================
RCS file: /cvs/src/src/gas/config/tc-mips.c,v
retrieving revision 1.123
diff -u -p -r1.123 tc-mips.c
--- gas/config/tc-mips.c 14 May 2002 23:35:59 -0000 1.123
+++ gas/config/tc-mips.c 21 May 2002 23:32:52 -0000
@@ -6686,6 +6686,17 @@ macro2 (ip)
--mips_opts.noreorder;
break;
+ case M_DROL:
+ macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "dsubu",
+ "d,v,t", AT, 0, treg);
+ macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "dsrlv",
+ "d,t,s", AT, sreg, AT);
+ macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "dsllv",
+ "d,t,s", dreg, sreg, treg);
+ macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "or",
+ "d,v,t", dreg, dreg, AT);
+ break;
+
case M_ROL:
macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "subu",
"d,v,t", AT, 0, treg);
@@ -6697,15 +6708,55 @@ macro2 (ip)
"d,v,t", dreg, dreg, AT);
break;
+ case M_DROL_I:
+ {
+ unsigned int rot;
+ char *l, *r;
+
+ if (imm_expr.X_op != O_constant)
+ as_bad (_("rotate count too large"));
+ rot = imm_expr.X_add_number & 0x3f;
+ if (! rot)
+ break;
+ l = (rot < 0x20) ? "dsll" : "dsll32";
+ r = ((0x40 - rot) < 0x20) ? "dsrl" : "dsrl32";
+ rot &= 0x1f;
+ macro_build ((char *) NULL, &icnt, (expressionS *) NULL, l,
+ "d,w,<", AT, sreg, rot);
+ macro_build ((char *) NULL, &icnt, (expressionS *) NULL, r,
+ "d,w,<", dreg, sreg, (0x20 - rot) & 0x1f);
+ macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "or",
+ "d,v,t", dreg, dreg, AT);
+ }
+ break;
+
case M_ROL_I:
- if (imm_expr.X_op != O_constant)
- as_bad (_("rotate count too large"));
- macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "sll", "d,w,<",
- AT, sreg, (int) (imm_expr.X_add_number & 0x1f));
- macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "srl", "d,w,<",
- dreg, sreg, (int) ((0 - imm_expr.X_add_number) & 0x1f));
- macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "or", "d,v,t",
- dreg, dreg, AT);
+ {
+ unsigned int rot;
+
+ if (imm_expr.X_op != O_constant)
+ as_bad (_("rotate count too large"));
+ rot = imm_expr.X_add_number & 0x1f;
+ if (! rot)
+ break;
+ macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "sll",
+ "d,w,<", AT, sreg, rot);
+ macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "srl",
+ "d,w,<", dreg, sreg, (0x20 - rot) & 0x1f);
+ macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "or",
+ "d,v,t", dreg, dreg, AT);
+ }
+ break;
+
+ case M_DROR:
+ macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "dsubu",
+ "d,v,t", AT, 0, treg);
+ macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "dsllv",
+ "d,t,s", AT, sreg, AT);
+ macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "dsrlv",
+ "d,t,s", dreg, sreg, treg);
+ macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "or",
+ "d,v,t", dreg, dreg, AT);
break;
case M_ROR:
@@ -6719,15 +6770,44 @@ macro2 (ip)
"d,v,t", dreg, dreg, AT);
break;
+ case M_DROR_I:
+ {
+ unsigned int rot;
+ char *l, *r;
+
+ if (imm_expr.X_op != O_constant)
+ as_bad (_("rotate count too large"));
+ rot = imm_expr.X_add_number & 0x3f;
+ if (! rot)
+ break;
+ r = (rot < 0x20) ? "dsrl" : "dsrl32";
+ l = ((0x40 - rot) < 0x20) ? "dsll" : "dsll32";
+ rot &= 0x1f;
+ macro_build ((char *) NULL, &icnt, (expressionS *) NULL, r,
+ "d,w,<", AT, sreg, rot);
+ macro_build ((char *) NULL, &icnt, (expressionS *) NULL, l,
+ "d,w,<", dreg, sreg, (0x20 - rot) & 0x1f);
+ macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "or",
+ "d,v,t", dreg, dreg, AT);
+ }
+ break;
+
case M_ROR_I:
- if (imm_expr.X_op != O_constant)
- as_bad (_("rotate count too large"));
- macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "srl", "d,w,<",
- AT, sreg, (int) (imm_expr.X_add_number & 0x1f));
- macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "sll", "d,w,<",
- dreg, sreg, (int) ((0 - imm_expr.X_add_number) & 0x1f));
- macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "or", "d,v,t",
- dreg, dreg, AT);
+ {
+ unsigned int rot;
+
+ if (imm_expr.X_op != O_constant)
+ as_bad (_("rotate count too large"));
+ rot = imm_expr.X_add_number & 0x1f;
+ if (! rot)
+ break;
+ macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "srl",
+ "d,w,<", AT, sreg, rot);
+ macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "sll",
+ "d,w,<", dreg, sreg, (0x20 - rot) & 0x1f);
+ macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "or",
+ "d,v,t", dreg, dreg, AT);
+ }
break;
case M_S_DOB:
Index: gas/testsuite/ChangeLog
===================================================================
RCS file: /cvs/src/src/gas/testsuite/ChangeLog,v
retrieving revision 1.315
diff -u -p -r1.315 ChangeLog
--- gas/testsuite/ChangeLog 20 May 2002 17:05:34 -0000 1.315
+++ gas/testsuite/ChangeLog 21 May 2002 23:32:54 -0000
@@ -1,3 +1,9 @@
+2002-05-22 Thiemo Seufer <seufer@csv.ica.uni-stuttgart.de>
+
+ * gas/mips/rol64.s: New file, test of drol, dror macros.
+ * gas/mips/rol64.d: Likewise.
+ * gas/mips/mips.exp: Add new test.
+
2002-05-20 Nick Clifton <nickc@cambridge.redhat.com>
* gas/arm/arm.exp: Replace deprecated command line switches
Index: gas/testsuite/gas/mips/mips.exp
===================================================================
RCS file: /cvs/src/src/gas/testsuite/gas/mips/mips.exp,v
retrieving revision 1.32
diff -u -p -r1.32 mips.exp
--- gas/testsuite/gas/mips/mips.exp 4 Apr 2002 08:23:30 -0000 1.32
+++ gas/testsuite/gas/mips/mips.exp 21 May 2002 23:32:54 -0000
@@ -122,6 +122,7 @@ if { [istarget mips*-*-*] } then {
run_dump_test "mul"
}
run_dump_test "rol"
+ run_dump_test "rol64"
if !$aout { run_dump_test "sb" }
run_dump_test "trunc"
if !$aout { run_dump_test "ulh" }
Index: include/opcode/ChangeLog
===================================================================
RCS file: /cvs/src/src/include/opcode/ChangeLog,v
retrieving revision 1.167
diff -u -p -r1.167 ChangeLog
--- include/opcode/ChangeLog 17 May 2002 19:01:03 -0000 1.167
+++ include/opcode/ChangeLog 21 May 2002 23:32:57 -0000
@@ -1,3 +1,7 @@
+2002-05-22 Thiemo Seufer <seufer@csv.ica.uni-stuttgart.de>
+
+ * mips.h: Add M_DROL, M_DROL_I, M_DROR, M_DROR_I macro cases.
+
2002-05-17 Andrey Volkov <avolkov@sources.redhat.com>
* h8300.h: Corrected defs of all control regs
Index: include/opcode/mips.h
===================================================================
RCS file: /cvs/src/src/include/opcode/mips.h,v
retrieving revision 1.24
diff -u -p -r1.24 mips.h
--- include/opcode/mips.h 16 Mar 2002 03:09:18 -0000 1.24
+++ include/opcode/mips.h 21 May 2002 23:32:57 -0000
@@ -526,9 +526,13 @@ enum
M_REM_3I,
M_REMU_3,
M_REMU_3I,
+ M_DROL,
M_ROL,
+ M_DROL_I,
M_ROL_I,
+ M_DROR,
M_ROR,
+ M_DROR_I,
M_ROR_I,
M_S_DA,
M_S_DOB,
Index: opcodes/ChangeLog
===================================================================
RCS file: /cvs/src/src/opcodes/ChangeLog,v
retrieving revision 1.447
diff -u -p -r1.447 ChangeLog
--- opcodes/ChangeLog 17 May 2002 14:36:45 -0000 1.447
+++ opcodes/ChangeLog 21 May 2002 23:33:00 -0000
@@ -1,3 +1,7 @@
+2002-05-22 Thiemo Seufer <seufer@csv.ica.uni-stuttgart.de>
+
+ * mips-opc.c (mips_builtin_opcodes): Add drol, dror macros.
+
Fri May 17 14:26:44 2002 J"orn Rennecke <joern.rennecke@superh.com>
* disassemble.c (disassembler): Just use print_insn_sh for bfd_arch_sh.
Index: opcodes/mips-opc.c
===================================================================
RCS file: /cvs/src/src/opcodes/mips-opc.c,v
retrieving revision 1.32
diff -u -p -r1.32 mips-opc.c
--- opcodes/mips-opc.c 17 Mar 2002 02:42:25 -0000 1.32
+++ opcodes/mips-opc.c 21 May 2002 23:33:00 -0000
@@ -492,6 +492,10 @@ const struct mips_opcode mips_builtin_op
{"dremu", "z,s,t", 0x0000001f, 0xfc00ffff, RD_s|RD_t|WR_HILO, I3 },
{"dremu", "d,v,t", 3, (int) M_DREMU_3, INSN_MACRO, I3 },
{"dremu", "d,v,I", 3, (int) M_DREMU_3I, INSN_MACRO, I3 },
+{"drol", "d,v,t", 0, (int) M_DROL, INSN_MACRO, I3 },
+{"drol", "d,v,I", 0, (int) M_DROL_I, INSN_MACRO, I3 },
+{"dror", "d,v,t", 0, (int) M_DROR, INSN_MACRO, I3 },
+{"dror", "d,v,I", 0, (int) M_DROR_I, INSN_MACRO, I3 },
{"dsllv", "d,t,s", 0x00000014, 0xfc0007ff, WR_d|RD_t|RD_s, I3 },
{"dsll32", "d,w,<", 0x0000003c, 0xffe0003f, WR_d|RD_t, I3 },
{"dsll", "d,w,s", 0x00000014, 0xfc0007ff, WR_d|RD_t|RD_s, I3 }, /* dsllv */
2002-05-22 01:54:48 +02:00
|
|
|
|
{
|
|
|
|
|
unsigned int rot;
|
|
|
|
|
|
|
|
|
|
if (imm_expr.X_op != O_constant)
|
[ opcodes/ChangeLog ]
2002-12-18 Chris Demetriou <cgd@broadcom.com>
* mips-opc.c (mips_builtin_opcodes): Remove one "ror" and two
"dror" entries, and reorder the remaining "dror" and "ror" entries.
[ gas/ChangeLog ]
2002-12-18 Chris Demetriou <cgd@broadcom.com>
* config/tc-mips.c (macro): In M_DROL, M_DROR, M_ROL, and M_ROR,
use hardware rotate ops as appropriate. In M_DROL_I, M_DROR_I,
M_ROL_I, and M_ROR_I, simplify code, clean up warnings, and
arrange not to issue warnings about use of AT when AT is not
actually used.
[ gas/testsuite/ChangeLog ]
2002-12-18 Chris Demetriou <cgd@broadcom.com>
* gas/mips/rol.s: Add ".set noat" and some new instructions to test.
* gas/mips/rol64.s: Likewise.
* gas/mips/rol.l: New file.
* gas/mips/rol.d: Adjust to use rol.l and for rol.s changes.
* gas/mips/rol64.l: New file.
* gas/mips/rol64.d: Adjust to use rol64.l and for rol64.s changes.
* gas/mips/rol-hw.d: New file.
* gas/mips/rol-hw.l: New file.
* gas/mips/rol64-hw.d: New file.
* gas/mips/rol64-hw.l: New file.
* gas/mips/mips.exp: Run rol-hw and rol64-hw tests.
2002-12-18 23:52:48 +01:00
|
|
|
|
as_bad (_("Improper rotate count"));
|
? gas/testsuite/gas/mips/rol64.d
? gas/testsuite/gas/mips/rol64.s
Index: gas/ChangeLog
===================================================================
RCS file: /cvs/src/src/gas/ChangeLog,v
retrieving revision 1.1334
diff -u -p -r1.1334 ChangeLog
--- gas/ChangeLog 21 May 2002 20:01:51 -0000 1.1334
+++ gas/ChangeLog 21 May 2002 23:32:51 -0000
@@ -1,3 +1,8 @@
+2002-05-22 Thiemo Seufer <seufer@csv.ica.uni-stuttgart.de>
+
+ * config/tc-mips.c (macro2): Add 64 bit drol, dror macros.
+ Optimize the rotate by zero case.
+
2002-05-21 Nick Clifton <nickc@cambridge.redhat.com>
* configure.in: Remove accidental enabling of bfd_gas=yes for
Index: gas/config/tc-mips.c
===================================================================
RCS file: /cvs/src/src/gas/config/tc-mips.c,v
retrieving revision 1.123
diff -u -p -r1.123 tc-mips.c
--- gas/config/tc-mips.c 14 May 2002 23:35:59 -0000 1.123
+++ gas/config/tc-mips.c 21 May 2002 23:32:52 -0000
@@ -6686,6 +6686,17 @@ macro2 (ip)
--mips_opts.noreorder;
break;
+ case M_DROL:
+ macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "dsubu",
+ "d,v,t", AT, 0, treg);
+ macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "dsrlv",
+ "d,t,s", AT, sreg, AT);
+ macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "dsllv",
+ "d,t,s", dreg, sreg, treg);
+ macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "or",
+ "d,v,t", dreg, dreg, AT);
+ break;
+
case M_ROL:
macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "subu",
"d,v,t", AT, 0, treg);
@@ -6697,15 +6708,55 @@ macro2 (ip)
"d,v,t", dreg, dreg, AT);
break;
+ case M_DROL_I:
+ {
+ unsigned int rot;
+ char *l, *r;
+
+ if (imm_expr.X_op != O_constant)
+ as_bad (_("rotate count too large"));
+ rot = imm_expr.X_add_number & 0x3f;
+ if (! rot)
+ break;
+ l = (rot < 0x20) ? "dsll" : "dsll32";
+ r = ((0x40 - rot) < 0x20) ? "dsrl" : "dsrl32";
+ rot &= 0x1f;
+ macro_build ((char *) NULL, &icnt, (expressionS *) NULL, l,
+ "d,w,<", AT, sreg, rot);
+ macro_build ((char *) NULL, &icnt, (expressionS *) NULL, r,
+ "d,w,<", dreg, sreg, (0x20 - rot) & 0x1f);
+ macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "or",
+ "d,v,t", dreg, dreg, AT);
+ }
+ break;
+
case M_ROL_I:
- if (imm_expr.X_op != O_constant)
- as_bad (_("rotate count too large"));
- macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "sll", "d,w,<",
- AT, sreg, (int) (imm_expr.X_add_number & 0x1f));
- macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "srl", "d,w,<",
- dreg, sreg, (int) ((0 - imm_expr.X_add_number) & 0x1f));
- macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "or", "d,v,t",
- dreg, dreg, AT);
+ {
+ unsigned int rot;
+
+ if (imm_expr.X_op != O_constant)
+ as_bad (_("rotate count too large"));
+ rot = imm_expr.X_add_number & 0x1f;
+ if (! rot)
+ break;
+ macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "sll",
+ "d,w,<", AT, sreg, rot);
+ macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "srl",
+ "d,w,<", dreg, sreg, (0x20 - rot) & 0x1f);
+ macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "or",
+ "d,v,t", dreg, dreg, AT);
+ }
+ break;
+
+ case M_DROR:
+ macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "dsubu",
+ "d,v,t", AT, 0, treg);
+ macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "dsllv",
+ "d,t,s", AT, sreg, AT);
+ macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "dsrlv",
+ "d,t,s", dreg, sreg, treg);
+ macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "or",
+ "d,v,t", dreg, dreg, AT);
break;
case M_ROR:
@@ -6719,15 +6770,44 @@ macro2 (ip)
"d,v,t", dreg, dreg, AT);
break;
+ case M_DROR_I:
+ {
+ unsigned int rot;
+ char *l, *r;
+
+ if (imm_expr.X_op != O_constant)
+ as_bad (_("rotate count too large"));
+ rot = imm_expr.X_add_number & 0x3f;
+ if (! rot)
+ break;
+ r = (rot < 0x20) ? "dsrl" : "dsrl32";
+ l = ((0x40 - rot) < 0x20) ? "dsll" : "dsll32";
+ rot &= 0x1f;
+ macro_build ((char *) NULL, &icnt, (expressionS *) NULL, r,
+ "d,w,<", AT, sreg, rot);
+ macro_build ((char *) NULL, &icnt, (expressionS *) NULL, l,
+ "d,w,<", dreg, sreg, (0x20 - rot) & 0x1f);
+ macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "or",
+ "d,v,t", dreg, dreg, AT);
+ }
+ break;
+
case M_ROR_I:
- if (imm_expr.X_op != O_constant)
- as_bad (_("rotate count too large"));
- macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "srl", "d,w,<",
- AT, sreg, (int) (imm_expr.X_add_number & 0x1f));
- macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "sll", "d,w,<",
- dreg, sreg, (int) ((0 - imm_expr.X_add_number) & 0x1f));
- macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "or", "d,v,t",
- dreg, dreg, AT);
+ {
+ unsigned int rot;
+
+ if (imm_expr.X_op != O_constant)
+ as_bad (_("rotate count too large"));
+ rot = imm_expr.X_add_number & 0x1f;
+ if (! rot)
+ break;
+ macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "srl",
+ "d,w,<", AT, sreg, rot);
+ macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "sll",
+ "d,w,<", dreg, sreg, (0x20 - rot) & 0x1f);
+ macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "or",
+ "d,v,t", dreg, dreg, AT);
+ }
break;
case M_S_DOB:
Index: gas/testsuite/ChangeLog
===================================================================
RCS file: /cvs/src/src/gas/testsuite/ChangeLog,v
retrieving revision 1.315
diff -u -p -r1.315 ChangeLog
--- gas/testsuite/ChangeLog 20 May 2002 17:05:34 -0000 1.315
+++ gas/testsuite/ChangeLog 21 May 2002 23:32:54 -0000
@@ -1,3 +1,9 @@
+2002-05-22 Thiemo Seufer <seufer@csv.ica.uni-stuttgart.de>
+
+ * gas/mips/rol64.s: New file, test of drol, dror macros.
+ * gas/mips/rol64.d: Likewise.
+ * gas/mips/mips.exp: Add new test.
+
2002-05-20 Nick Clifton <nickc@cambridge.redhat.com>
* gas/arm/arm.exp: Replace deprecated command line switches
Index: gas/testsuite/gas/mips/mips.exp
===================================================================
RCS file: /cvs/src/src/gas/testsuite/gas/mips/mips.exp,v
retrieving revision 1.32
diff -u -p -r1.32 mips.exp
--- gas/testsuite/gas/mips/mips.exp 4 Apr 2002 08:23:30 -0000 1.32
+++ gas/testsuite/gas/mips/mips.exp 21 May 2002 23:32:54 -0000
@@ -122,6 +122,7 @@ if { [istarget mips*-*-*] } then {
run_dump_test "mul"
}
run_dump_test "rol"
+ run_dump_test "rol64"
if !$aout { run_dump_test "sb" }
run_dump_test "trunc"
if !$aout { run_dump_test "ulh" }
Index: include/opcode/ChangeLog
===================================================================
RCS file: /cvs/src/src/include/opcode/ChangeLog,v
retrieving revision 1.167
diff -u -p -r1.167 ChangeLog
--- include/opcode/ChangeLog 17 May 2002 19:01:03 -0000 1.167
+++ include/opcode/ChangeLog 21 May 2002 23:32:57 -0000
@@ -1,3 +1,7 @@
+2002-05-22 Thiemo Seufer <seufer@csv.ica.uni-stuttgart.de>
+
+ * mips.h: Add M_DROL, M_DROL_I, M_DROR, M_DROR_I macro cases.
+
2002-05-17 Andrey Volkov <avolkov@sources.redhat.com>
* h8300.h: Corrected defs of all control regs
Index: include/opcode/mips.h
===================================================================
RCS file: /cvs/src/src/include/opcode/mips.h,v
retrieving revision 1.24
diff -u -p -r1.24 mips.h
--- include/opcode/mips.h 16 Mar 2002 03:09:18 -0000 1.24
+++ include/opcode/mips.h 21 May 2002 23:32:57 -0000
@@ -526,9 +526,13 @@ enum
M_REM_3I,
M_REMU_3,
M_REMU_3I,
+ M_DROL,
M_ROL,
+ M_DROL_I,
M_ROL_I,
+ M_DROR,
M_ROR,
+ M_DROR_I,
M_ROR_I,
M_S_DA,
M_S_DOB,
Index: opcodes/ChangeLog
===================================================================
RCS file: /cvs/src/src/opcodes/ChangeLog,v
retrieving revision 1.447
diff -u -p -r1.447 ChangeLog
--- opcodes/ChangeLog 17 May 2002 14:36:45 -0000 1.447
+++ opcodes/ChangeLog 21 May 2002 23:33:00 -0000
@@ -1,3 +1,7 @@
+2002-05-22 Thiemo Seufer <seufer@csv.ica.uni-stuttgart.de>
+
+ * mips-opc.c (mips_builtin_opcodes): Add drol, dror macros.
+
Fri May 17 14:26:44 2002 J"orn Rennecke <joern.rennecke@superh.com>
* disassemble.c (disassembler): Just use print_insn_sh for bfd_arch_sh.
Index: opcodes/mips-opc.c
===================================================================
RCS file: /cvs/src/src/opcodes/mips-opc.c,v
retrieving revision 1.32
diff -u -p -r1.32 mips-opc.c
--- opcodes/mips-opc.c 17 Mar 2002 02:42:25 -0000 1.32
+++ opcodes/mips-opc.c 21 May 2002 23:33:00 -0000
@@ -492,6 +492,10 @@ const struct mips_opcode mips_builtin_op
{"dremu", "z,s,t", 0x0000001f, 0xfc00ffff, RD_s|RD_t|WR_HILO, I3 },
{"dremu", "d,v,t", 3, (int) M_DREMU_3, INSN_MACRO, I3 },
{"dremu", "d,v,I", 3, (int) M_DREMU_3I, INSN_MACRO, I3 },
+{"drol", "d,v,t", 0, (int) M_DROL, INSN_MACRO, I3 },
+{"drol", "d,v,I", 0, (int) M_DROL_I, INSN_MACRO, I3 },
+{"dror", "d,v,t", 0, (int) M_DROR, INSN_MACRO, I3 },
+{"dror", "d,v,I", 0, (int) M_DROR_I, INSN_MACRO, I3 },
{"dsllv", "d,t,s", 0x00000014, 0xfc0007ff, WR_d|RD_t|RD_s, I3 },
{"dsll32", "d,w,<", 0x0000003c, 0xffe0003f, WR_d|RD_t, I3 },
{"dsll", "d,w,s", 0x00000014, 0xfc0007ff, WR_d|RD_t|RD_s, I3 }, /* dsllv */
2002-05-22 01:54:48 +02:00
|
|
|
|
rot = imm_expr.X_add_number & 0x1f;
|
2003-06-29 21:41:33 +02:00
|
|
|
|
if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch))
|
[gas/]
* doc/c-mips.texi: Add entries for -march=vr4120,vr4130,vr4181,
vr5400 and vr5500. Add entry for -mfix-vr4122-bugs.
* config/tc-mips.c (CPU_HAS_DROR, CPU_HAS_ROR): New macros.
(hilo_interlocks): True for CPU_VR5500.
(gpr_interlocks, cop_interlocks): True for CPU_VR5400 and CPU_VR5500.
(mips_fix_vr4122_bugs): New.
(append_insn): Work around 4122 errors if mips_fix_vr4122_bugs.
(mips_emit_delays): Likewise.
(macro2) [M_DROLI]: Use dror or dror32 if CPU_HAS_DROR.
[M_ROLI]: Likewise ror if CPU_HAS_ROR.
(validate_mips_insn, mips_ip): Handle '[', ']', 'e' and '%'.
(OPTION_FIX_VR4122, OPTION_NO_FIX_VR4122): New options.
(md_longopts): Add -mfix-vr4122-bugs and -no-mfix-vr4122-bugs.
(OPTION_ELF_BASE): Bump.
(md_parse_option): Handle the new options.
(mips_cpu_info_table): Add entries for vr4120, vr4130, vr4181,
vr5400 and vr5500.
[gas/testsuite/]
* gas/mips/mips4100.[sd]: Move dmadd16 and madd16 checks to...
* gas/mips/vr4111.[sd]: ...this new test.
* gas/mips/vr4120.[sd],
* gas/mips/vr4122.[sd],
* gas/mips/vr5400.[sd],
* gas/mips/vr5500.[sd]: New tests.
* mips.exp: Run them.
2002-09-30 14:04:54 +02:00
|
|
|
|
{
|
2003-06-30 14:44:25 +02:00
|
|
|
|
macro_build (NULL, &icnt, NULL, "ror", "d,w,<", dreg, sreg,
|
|
|
|
|
(32 - rot) & 0x1f);
|
[ opcodes/ChangeLog ]
2002-12-18 Chris Demetriou <cgd@broadcom.com>
* mips-opc.c (mips_builtin_opcodes): Remove one "ror" and two
"dror" entries, and reorder the remaining "dror" and "ror" entries.
[ gas/ChangeLog ]
2002-12-18 Chris Demetriou <cgd@broadcom.com>
* config/tc-mips.c (macro): In M_DROL, M_DROR, M_ROL, and M_ROR,
use hardware rotate ops as appropriate. In M_DROL_I, M_DROR_I,
M_ROL_I, and M_ROR_I, simplify code, clean up warnings, and
arrange not to issue warnings about use of AT when AT is not
actually used.
[ gas/testsuite/ChangeLog ]
2002-12-18 Chris Demetriou <cgd@broadcom.com>
* gas/mips/rol.s: Add ".set noat" and some new instructions to test.
* gas/mips/rol64.s: Likewise.
* gas/mips/rol.l: New file.
* gas/mips/rol.d: Adjust to use rol.l and for rol.s changes.
* gas/mips/rol64.l: New file.
* gas/mips/rol64.d: Adjust to use rol64.l and for rol64.s changes.
* gas/mips/rol-hw.d: New file.
* gas/mips/rol-hw.l: New file.
* gas/mips/rol64-hw.d: New file.
* gas/mips/rol64-hw.l: New file.
* gas/mips/mips.exp: Run rol-hw and rol64-hw tests.
2002-12-18 23:52:48 +01:00
|
|
|
|
return;
|
[gas/]
* doc/c-mips.texi: Add entries for -march=vr4120,vr4130,vr4181,
vr5400 and vr5500. Add entry for -mfix-vr4122-bugs.
* config/tc-mips.c (CPU_HAS_DROR, CPU_HAS_ROR): New macros.
(hilo_interlocks): True for CPU_VR5500.
(gpr_interlocks, cop_interlocks): True for CPU_VR5400 and CPU_VR5500.
(mips_fix_vr4122_bugs): New.
(append_insn): Work around 4122 errors if mips_fix_vr4122_bugs.
(mips_emit_delays): Likewise.
(macro2) [M_DROLI]: Use dror or dror32 if CPU_HAS_DROR.
[M_ROLI]: Likewise ror if CPU_HAS_ROR.
(validate_mips_insn, mips_ip): Handle '[', ']', 'e' and '%'.
(OPTION_FIX_VR4122, OPTION_NO_FIX_VR4122): New options.
(md_longopts): Add -mfix-vr4122-bugs and -no-mfix-vr4122-bugs.
(OPTION_ELF_BASE): Bump.
(md_parse_option): Handle the new options.
(mips_cpu_info_table): Add entries for vr4120, vr4130, vr4181,
vr5400 and vr5500.
[gas/testsuite/]
* gas/mips/mips4100.[sd]: Move dmadd16 and madd16 checks to...
* gas/mips/vr4111.[sd]: ...this new test.
* gas/mips/vr4120.[sd],
* gas/mips/vr4122.[sd],
* gas/mips/vr5400.[sd],
* gas/mips/vr5500.[sd]: New tests.
* mips.exp: Run them.
2002-09-30 14:04:54 +02:00
|
|
|
|
}
|
2002-08-20 10:28:35 +02:00
|
|
|
|
if (rot == 0)
|
|
|
|
|
{
|
2003-06-30 14:44:25 +02:00
|
|
|
|
macro_build (NULL, &icnt, NULL, "srl", "d,w,<", dreg, sreg, 0);
|
[ opcodes/ChangeLog ]
2002-12-18 Chris Demetriou <cgd@broadcom.com>
* mips-opc.c (mips_builtin_opcodes): Remove one "ror" and two
"dror" entries, and reorder the remaining "dror" and "ror" entries.
[ gas/ChangeLog ]
2002-12-18 Chris Demetriou <cgd@broadcom.com>
* config/tc-mips.c (macro): In M_DROL, M_DROR, M_ROL, and M_ROR,
use hardware rotate ops as appropriate. In M_DROL_I, M_DROR_I,
M_ROL_I, and M_ROR_I, simplify code, clean up warnings, and
arrange not to issue warnings about use of AT when AT is not
actually used.
[ gas/testsuite/ChangeLog ]
2002-12-18 Chris Demetriou <cgd@broadcom.com>
* gas/mips/rol.s: Add ".set noat" and some new instructions to test.
* gas/mips/rol64.s: Likewise.
* gas/mips/rol.l: New file.
* gas/mips/rol.d: Adjust to use rol.l and for rol.s changes.
* gas/mips/rol64.l: New file.
* gas/mips/rol64.d: Adjust to use rol64.l and for rol64.s changes.
* gas/mips/rol-hw.d: New file.
* gas/mips/rol-hw.l: New file.
* gas/mips/rol64-hw.d: New file.
* gas/mips/rol64-hw.l: New file.
* gas/mips/mips.exp: Run rol-hw and rol64-hw tests.
2002-12-18 23:52:48 +01:00
|
|
|
|
return;
|
2002-08-20 10:28:35 +02:00
|
|
|
|
}
|
2003-06-30 14:44:25 +02:00
|
|
|
|
macro_build (NULL, &icnt, NULL, "sll", "d,w,<", AT, sreg, rot);
|
|
|
|
|
macro_build (NULL, &icnt, NULL, "srl", "d,w,<", dreg, sreg,
|
|
|
|
|
(0x20 - rot) & 0x1f);
|
|
|
|
|
macro_build (NULL, &icnt, NULL, "or", "d,v,t", dreg, dreg, AT);
|
? gas/testsuite/gas/mips/rol64.d
? gas/testsuite/gas/mips/rol64.s
Index: gas/ChangeLog
===================================================================
RCS file: /cvs/src/src/gas/ChangeLog,v
retrieving revision 1.1334
diff -u -p -r1.1334 ChangeLog
--- gas/ChangeLog 21 May 2002 20:01:51 -0000 1.1334
+++ gas/ChangeLog 21 May 2002 23:32:51 -0000
@@ -1,3 +1,8 @@
+2002-05-22 Thiemo Seufer <seufer@csv.ica.uni-stuttgart.de>
+
+ * config/tc-mips.c (macro2): Add 64 bit drol, dror macros.
+ Optimize the rotate by zero case.
+
2002-05-21 Nick Clifton <nickc@cambridge.redhat.com>
* configure.in: Remove accidental enabling of bfd_gas=yes for
Index: gas/config/tc-mips.c
===================================================================
RCS file: /cvs/src/src/gas/config/tc-mips.c,v
retrieving revision 1.123
diff -u -p -r1.123 tc-mips.c
--- gas/config/tc-mips.c 14 May 2002 23:35:59 -0000 1.123
+++ gas/config/tc-mips.c 21 May 2002 23:32:52 -0000
@@ -6686,6 +6686,17 @@ macro2 (ip)
--mips_opts.noreorder;
break;
+ case M_DROL:
+ macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "dsubu",
+ "d,v,t", AT, 0, treg);
+ macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "dsrlv",
+ "d,t,s", AT, sreg, AT);
+ macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "dsllv",
+ "d,t,s", dreg, sreg, treg);
+ macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "or",
+ "d,v,t", dreg, dreg, AT);
+ break;
+
case M_ROL:
macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "subu",
"d,v,t", AT, 0, treg);
@@ -6697,15 +6708,55 @@ macro2 (ip)
"d,v,t", dreg, dreg, AT);
break;
+ case M_DROL_I:
+ {
+ unsigned int rot;
+ char *l, *r;
+
+ if (imm_expr.X_op != O_constant)
+ as_bad (_("rotate count too large"));
+ rot = imm_expr.X_add_number & 0x3f;
+ if (! rot)
+ break;
+ l = (rot < 0x20) ? "dsll" : "dsll32";
+ r = ((0x40 - rot) < 0x20) ? "dsrl" : "dsrl32";
+ rot &= 0x1f;
+ macro_build ((char *) NULL, &icnt, (expressionS *) NULL, l,
+ "d,w,<", AT, sreg, rot);
+ macro_build ((char *) NULL, &icnt, (expressionS *) NULL, r,
+ "d,w,<", dreg, sreg, (0x20 - rot) & 0x1f);
+ macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "or",
+ "d,v,t", dreg, dreg, AT);
+ }
+ break;
+
case M_ROL_I:
- if (imm_expr.X_op != O_constant)
- as_bad (_("rotate count too large"));
- macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "sll", "d,w,<",
- AT, sreg, (int) (imm_expr.X_add_number & 0x1f));
- macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "srl", "d,w,<",
- dreg, sreg, (int) ((0 - imm_expr.X_add_number) & 0x1f));
- macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "or", "d,v,t",
- dreg, dreg, AT);
+ {
+ unsigned int rot;
+
+ if (imm_expr.X_op != O_constant)
+ as_bad (_("rotate count too large"));
+ rot = imm_expr.X_add_number & 0x1f;
+ if (! rot)
+ break;
+ macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "sll",
+ "d,w,<", AT, sreg, rot);
+ macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "srl",
+ "d,w,<", dreg, sreg, (0x20 - rot) & 0x1f);
+ macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "or",
+ "d,v,t", dreg, dreg, AT);
+ }
+ break;
+
+ case M_DROR:
+ macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "dsubu",
+ "d,v,t", AT, 0, treg);
+ macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "dsllv",
+ "d,t,s", AT, sreg, AT);
+ macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "dsrlv",
+ "d,t,s", dreg, sreg, treg);
+ macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "or",
+ "d,v,t", dreg, dreg, AT);
break;
case M_ROR:
@@ -6719,15 +6770,44 @@ macro2 (ip)
"d,v,t", dreg, dreg, AT);
break;
+ case M_DROR_I:
+ {
+ unsigned int rot;
+ char *l, *r;
+
+ if (imm_expr.X_op != O_constant)
+ as_bad (_("rotate count too large"));
+ rot = imm_expr.X_add_number & 0x3f;
+ if (! rot)
+ break;
+ r = (rot < 0x20) ? "dsrl" : "dsrl32";
+ l = ((0x40 - rot) < 0x20) ? "dsll" : "dsll32";
+ rot &= 0x1f;
+ macro_build ((char *) NULL, &icnt, (expressionS *) NULL, r,
+ "d,w,<", AT, sreg, rot);
+ macro_build ((char *) NULL, &icnt, (expressionS *) NULL, l,
+ "d,w,<", dreg, sreg, (0x20 - rot) & 0x1f);
+ macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "or",
+ "d,v,t", dreg, dreg, AT);
+ }
+ break;
+
case M_ROR_I:
- if (imm_expr.X_op != O_constant)
- as_bad (_("rotate count too large"));
- macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "srl", "d,w,<",
- AT, sreg, (int) (imm_expr.X_add_number & 0x1f));
- macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "sll", "d,w,<",
- dreg, sreg, (int) ((0 - imm_expr.X_add_number) & 0x1f));
- macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "or", "d,v,t",
- dreg, dreg, AT);
+ {
+ unsigned int rot;
+
+ if (imm_expr.X_op != O_constant)
+ as_bad (_("rotate count too large"));
+ rot = imm_expr.X_add_number & 0x1f;
+ if (! rot)
+ break;
+ macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "srl",
+ "d,w,<", AT, sreg, rot);
+ macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "sll",
+ "d,w,<", dreg, sreg, (0x20 - rot) & 0x1f);
+ macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "or",
+ "d,v,t", dreg, dreg, AT);
+ }
break;
case M_S_DOB:
Index: gas/testsuite/ChangeLog
===================================================================
RCS file: /cvs/src/src/gas/testsuite/ChangeLog,v
retrieving revision 1.315
diff -u -p -r1.315 ChangeLog
--- gas/testsuite/ChangeLog 20 May 2002 17:05:34 -0000 1.315
+++ gas/testsuite/ChangeLog 21 May 2002 23:32:54 -0000
@@ -1,3 +1,9 @@
+2002-05-22 Thiemo Seufer <seufer@csv.ica.uni-stuttgart.de>
+
+ * gas/mips/rol64.s: New file, test of drol, dror macros.
+ * gas/mips/rol64.d: Likewise.
+ * gas/mips/mips.exp: Add new test.
+
2002-05-20 Nick Clifton <nickc@cambridge.redhat.com>
* gas/arm/arm.exp: Replace deprecated command line switches
Index: gas/testsuite/gas/mips/mips.exp
===================================================================
RCS file: /cvs/src/src/gas/testsuite/gas/mips/mips.exp,v
retrieving revision 1.32
diff -u -p -r1.32 mips.exp
--- gas/testsuite/gas/mips/mips.exp 4 Apr 2002 08:23:30 -0000 1.32
+++ gas/testsuite/gas/mips/mips.exp 21 May 2002 23:32:54 -0000
@@ -122,6 +122,7 @@ if { [istarget mips*-*-*] } then {
run_dump_test "mul"
}
run_dump_test "rol"
+ run_dump_test "rol64"
if !$aout { run_dump_test "sb" }
run_dump_test "trunc"
if !$aout { run_dump_test "ulh" }
Index: include/opcode/ChangeLog
===================================================================
RCS file: /cvs/src/src/include/opcode/ChangeLog,v
retrieving revision 1.167
diff -u -p -r1.167 ChangeLog
--- include/opcode/ChangeLog 17 May 2002 19:01:03 -0000 1.167
+++ include/opcode/ChangeLog 21 May 2002 23:32:57 -0000
@@ -1,3 +1,7 @@
+2002-05-22 Thiemo Seufer <seufer@csv.ica.uni-stuttgart.de>
+
+ * mips.h: Add M_DROL, M_DROL_I, M_DROR, M_DROR_I macro cases.
+
2002-05-17 Andrey Volkov <avolkov@sources.redhat.com>
* h8300.h: Corrected defs of all control regs
Index: include/opcode/mips.h
===================================================================
RCS file: /cvs/src/src/include/opcode/mips.h,v
retrieving revision 1.24
diff -u -p -r1.24 mips.h
--- include/opcode/mips.h 16 Mar 2002 03:09:18 -0000 1.24
+++ include/opcode/mips.h 21 May 2002 23:32:57 -0000
@@ -526,9 +526,13 @@ enum
M_REM_3I,
M_REMU_3,
M_REMU_3I,
+ M_DROL,
M_ROL,
+ M_DROL_I,
M_ROL_I,
+ M_DROR,
M_ROR,
+ M_DROR_I,
M_ROR_I,
M_S_DA,
M_S_DOB,
Index: opcodes/ChangeLog
===================================================================
RCS file: /cvs/src/src/opcodes/ChangeLog,v
retrieving revision 1.447
diff -u -p -r1.447 ChangeLog
--- opcodes/ChangeLog 17 May 2002 14:36:45 -0000 1.447
+++ opcodes/ChangeLog 21 May 2002 23:33:00 -0000
@@ -1,3 +1,7 @@
+2002-05-22 Thiemo Seufer <seufer@csv.ica.uni-stuttgart.de>
+
+ * mips-opc.c (mips_builtin_opcodes): Add drol, dror macros.
+
Fri May 17 14:26:44 2002 J"orn Rennecke <joern.rennecke@superh.com>
* disassemble.c (disassembler): Just use print_insn_sh for bfd_arch_sh.
Index: opcodes/mips-opc.c
===================================================================
RCS file: /cvs/src/src/opcodes/mips-opc.c,v
retrieving revision 1.32
diff -u -p -r1.32 mips-opc.c
--- opcodes/mips-opc.c 17 Mar 2002 02:42:25 -0000 1.32
+++ opcodes/mips-opc.c 21 May 2002 23:33:00 -0000
@@ -492,6 +492,10 @@ const struct mips_opcode mips_builtin_op
{"dremu", "z,s,t", 0x0000001f, 0xfc00ffff, RD_s|RD_t|WR_HILO, I3 },
{"dremu", "d,v,t", 3, (int) M_DREMU_3, INSN_MACRO, I3 },
{"dremu", "d,v,I", 3, (int) M_DREMU_3I, INSN_MACRO, I3 },
+{"drol", "d,v,t", 0, (int) M_DROL, INSN_MACRO, I3 },
+{"drol", "d,v,I", 0, (int) M_DROL_I, INSN_MACRO, I3 },
+{"dror", "d,v,t", 0, (int) M_DROR, INSN_MACRO, I3 },
+{"dror", "d,v,I", 0, (int) M_DROR_I, INSN_MACRO, I3 },
{"dsllv", "d,t,s", 0x00000014, 0xfc0007ff, WR_d|RD_t|RD_s, I3 },
{"dsll32", "d,w,<", 0x0000003c, 0xffe0003f, WR_d|RD_t, I3 },
{"dsll", "d,w,s", 0x00000014, 0xfc0007ff, WR_d|RD_t|RD_s, I3 }, /* dsllv */
2002-05-22 01:54:48 +02:00
|
|
|
|
}
|
|
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
case M_DROR:
|
2003-06-29 21:41:33 +02:00
|
|
|
|
if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch))
|
[ opcodes/ChangeLog ]
2002-12-18 Chris Demetriou <cgd@broadcom.com>
* mips-opc.c (mips_builtin_opcodes): Remove one "ror" and two
"dror" entries, and reorder the remaining "dror" and "ror" entries.
[ gas/ChangeLog ]
2002-12-18 Chris Demetriou <cgd@broadcom.com>
* config/tc-mips.c (macro): In M_DROL, M_DROR, M_ROL, and M_ROR,
use hardware rotate ops as appropriate. In M_DROL_I, M_DROR_I,
M_ROL_I, and M_ROR_I, simplify code, clean up warnings, and
arrange not to issue warnings about use of AT when AT is not
actually used.
[ gas/testsuite/ChangeLog ]
2002-12-18 Chris Demetriou <cgd@broadcom.com>
* gas/mips/rol.s: Add ".set noat" and some new instructions to test.
* gas/mips/rol64.s: Likewise.
* gas/mips/rol.l: New file.
* gas/mips/rol.d: Adjust to use rol.l and for rol.s changes.
* gas/mips/rol64.l: New file.
* gas/mips/rol64.d: Adjust to use rol64.l and for rol64.s changes.
* gas/mips/rol-hw.d: New file.
* gas/mips/rol-hw.l: New file.
* gas/mips/rol64-hw.d: New file.
* gas/mips/rol64-hw.l: New file.
* gas/mips/mips.exp: Run rol-hw and rol64-hw tests.
2002-12-18 23:52:48 +01:00
|
|
|
|
{
|
2003-06-30 14:44:25 +02:00
|
|
|
|
macro_build (NULL, &icnt, NULL, "drorv", "d,t,s", dreg, sreg, treg);
|
[ opcodes/ChangeLog ]
2002-12-18 Chris Demetriou <cgd@broadcom.com>
* mips-opc.c (mips_builtin_opcodes): Remove one "ror" and two
"dror" entries, and reorder the remaining "dror" and "ror" entries.
[ gas/ChangeLog ]
2002-12-18 Chris Demetriou <cgd@broadcom.com>
* config/tc-mips.c (macro): In M_DROL, M_DROR, M_ROL, and M_ROR,
use hardware rotate ops as appropriate. In M_DROL_I, M_DROR_I,
M_ROL_I, and M_ROR_I, simplify code, clean up warnings, and
arrange not to issue warnings about use of AT when AT is not
actually used.
[ gas/testsuite/ChangeLog ]
2002-12-18 Chris Demetriou <cgd@broadcom.com>
* gas/mips/rol.s: Add ".set noat" and some new instructions to test.
* gas/mips/rol64.s: Likewise.
* gas/mips/rol.l: New file.
* gas/mips/rol.d: Adjust to use rol.l and for rol.s changes.
* gas/mips/rol64.l: New file.
* gas/mips/rol64.d: Adjust to use rol64.l and for rol64.s changes.
* gas/mips/rol-hw.d: New file.
* gas/mips/rol-hw.l: New file.
* gas/mips/rol64-hw.d: New file.
* gas/mips/rol64-hw.l: New file.
* gas/mips/mips.exp: Run rol-hw and rol64-hw tests.
2002-12-18 23:52:48 +01:00
|
|
|
|
return;
|
|
|
|
|
}
|
2003-11-15 16:57:14 +01:00
|
|
|
|
macro_build (NULL, &icnt, NULL, "dsubu", "d,v,t", AT, 0, treg);
|
2003-06-30 14:44:25 +02:00
|
|
|
|
macro_build (NULL, &icnt, NULL, "dsllv", "d,t,s", AT, sreg, AT);
|
|
|
|
|
macro_build (NULL, &icnt, NULL, "dsrlv", "d,t,s", dreg, sreg, treg);
|
|
|
|
|
macro_build (NULL, &icnt, NULL, "or", "d,v,t", dreg, dreg, AT);
|
1999-05-03 09:29:11 +02:00
|
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
case M_ROR:
|
2003-06-29 21:41:33 +02:00
|
|
|
|
if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch))
|
[ opcodes/ChangeLog ]
2002-12-18 Chris Demetriou <cgd@broadcom.com>
* mips-opc.c (mips_builtin_opcodes): Remove one "ror" and two
"dror" entries, and reorder the remaining "dror" and "ror" entries.
[ gas/ChangeLog ]
2002-12-18 Chris Demetriou <cgd@broadcom.com>
* config/tc-mips.c (macro): In M_DROL, M_DROR, M_ROL, and M_ROR,
use hardware rotate ops as appropriate. In M_DROL_I, M_DROR_I,
M_ROL_I, and M_ROR_I, simplify code, clean up warnings, and
arrange not to issue warnings about use of AT when AT is not
actually used.
[ gas/testsuite/ChangeLog ]
2002-12-18 Chris Demetriou <cgd@broadcom.com>
* gas/mips/rol.s: Add ".set noat" and some new instructions to test.
* gas/mips/rol64.s: Likewise.
* gas/mips/rol.l: New file.
* gas/mips/rol.d: Adjust to use rol.l and for rol.s changes.
* gas/mips/rol64.l: New file.
* gas/mips/rol64.d: Adjust to use rol64.l and for rol64.s changes.
* gas/mips/rol-hw.d: New file.
* gas/mips/rol-hw.l: New file.
* gas/mips/rol64-hw.d: New file.
* gas/mips/rol64-hw.l: New file.
* gas/mips/mips.exp: Run rol-hw and rol64-hw tests.
2002-12-18 23:52:48 +01:00
|
|
|
|
{
|
2003-06-30 14:44:25 +02:00
|
|
|
|
macro_build (NULL, &icnt, NULL, "rorv", "d,t,s", dreg, sreg, treg);
|
[ opcodes/ChangeLog ]
2002-12-18 Chris Demetriou <cgd@broadcom.com>
* mips-opc.c (mips_builtin_opcodes): Remove one "ror" and two
"dror" entries, and reorder the remaining "dror" and "ror" entries.
[ gas/ChangeLog ]
2002-12-18 Chris Demetriou <cgd@broadcom.com>
* config/tc-mips.c (macro): In M_DROL, M_DROR, M_ROL, and M_ROR,
use hardware rotate ops as appropriate. In M_DROL_I, M_DROR_I,
M_ROL_I, and M_ROR_I, simplify code, clean up warnings, and
arrange not to issue warnings about use of AT when AT is not
actually used.
[ gas/testsuite/ChangeLog ]
2002-12-18 Chris Demetriou <cgd@broadcom.com>
* gas/mips/rol.s: Add ".set noat" and some new instructions to test.
* gas/mips/rol64.s: Likewise.
* gas/mips/rol.l: New file.
* gas/mips/rol.d: Adjust to use rol.l and for rol.s changes.
* gas/mips/rol64.l: New file.
* gas/mips/rol64.d: Adjust to use rol64.l and for rol64.s changes.
* gas/mips/rol-hw.d: New file.
* gas/mips/rol-hw.l: New file.
* gas/mips/rol64-hw.d: New file.
* gas/mips/rol64-hw.l: New file.
* gas/mips/mips.exp: Run rol-hw and rol64-hw tests.
2002-12-18 23:52:48 +01:00
|
|
|
|
return;
|
|
|
|
|
}
|
2003-06-30 14:44:25 +02:00
|
|
|
|
macro_build (NULL, &icnt, NULL, "subu", "d,v,t", AT, 0, treg);
|
|
|
|
|
macro_build (NULL, &icnt, NULL, "sllv", "d,t,s", AT, sreg, AT);
|
|
|
|
|
macro_build (NULL, &icnt, NULL, "srlv", "d,t,s", dreg, sreg, treg);
|
|
|
|
|
macro_build (NULL, &icnt, NULL, "or", "d,v,t", dreg, dreg, AT);
|
1999-05-03 09:29:11 +02:00
|
|
|
|
break;
|
|
|
|
|
|
? gas/testsuite/gas/mips/rol64.d
? gas/testsuite/gas/mips/rol64.s
Index: gas/ChangeLog
===================================================================
RCS file: /cvs/src/src/gas/ChangeLog,v
retrieving revision 1.1334
diff -u -p -r1.1334 ChangeLog
--- gas/ChangeLog 21 May 2002 20:01:51 -0000 1.1334
+++ gas/ChangeLog 21 May 2002 23:32:51 -0000
@@ -1,3 +1,8 @@
+2002-05-22 Thiemo Seufer <seufer@csv.ica.uni-stuttgart.de>
+
+ * config/tc-mips.c (macro2): Add 64 bit drol, dror macros.
+ Optimize the rotate by zero case.
+
2002-05-21 Nick Clifton <nickc@cambridge.redhat.com>
* configure.in: Remove accidental enabling of bfd_gas=yes for
Index: gas/config/tc-mips.c
===================================================================
RCS file: /cvs/src/src/gas/config/tc-mips.c,v
retrieving revision 1.123
diff -u -p -r1.123 tc-mips.c
--- gas/config/tc-mips.c 14 May 2002 23:35:59 -0000 1.123
+++ gas/config/tc-mips.c 21 May 2002 23:32:52 -0000
@@ -6686,6 +6686,17 @@ macro2 (ip)
--mips_opts.noreorder;
break;
+ case M_DROL:
+ macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "dsubu",
+ "d,v,t", AT, 0, treg);
+ macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "dsrlv",
+ "d,t,s", AT, sreg, AT);
+ macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "dsllv",
+ "d,t,s", dreg, sreg, treg);
+ macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "or",
+ "d,v,t", dreg, dreg, AT);
+ break;
+
case M_ROL:
macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "subu",
"d,v,t", AT, 0, treg);
@@ -6697,15 +6708,55 @@ macro2 (ip)
"d,v,t", dreg, dreg, AT);
break;
+ case M_DROL_I:
+ {
+ unsigned int rot;
+ char *l, *r;
+
+ if (imm_expr.X_op != O_constant)
+ as_bad (_("rotate count too large"));
+ rot = imm_expr.X_add_number & 0x3f;
+ if (! rot)
+ break;
+ l = (rot < 0x20) ? "dsll" : "dsll32";
+ r = ((0x40 - rot) < 0x20) ? "dsrl" : "dsrl32";
+ rot &= 0x1f;
+ macro_build ((char *) NULL, &icnt, (expressionS *) NULL, l,
+ "d,w,<", AT, sreg, rot);
+ macro_build ((char *) NULL, &icnt, (expressionS *) NULL, r,
+ "d,w,<", dreg, sreg, (0x20 - rot) & 0x1f);
+ macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "or",
+ "d,v,t", dreg, dreg, AT);
+ }
+ break;
+
case M_ROL_I:
- if (imm_expr.X_op != O_constant)
- as_bad (_("rotate count too large"));
- macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "sll", "d,w,<",
- AT, sreg, (int) (imm_expr.X_add_number & 0x1f));
- macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "srl", "d,w,<",
- dreg, sreg, (int) ((0 - imm_expr.X_add_number) & 0x1f));
- macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "or", "d,v,t",
- dreg, dreg, AT);
+ {
+ unsigned int rot;
+
+ if (imm_expr.X_op != O_constant)
+ as_bad (_("rotate count too large"));
+ rot = imm_expr.X_add_number & 0x1f;
+ if (! rot)
+ break;
+ macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "sll",
+ "d,w,<", AT, sreg, rot);
+ macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "srl",
+ "d,w,<", dreg, sreg, (0x20 - rot) & 0x1f);
+ macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "or",
+ "d,v,t", dreg, dreg, AT);
+ }
+ break;
+
+ case M_DROR:
+ macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "dsubu",
+ "d,v,t", AT, 0, treg);
+ macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "dsllv",
+ "d,t,s", AT, sreg, AT);
+ macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "dsrlv",
+ "d,t,s", dreg, sreg, treg);
+ macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "or",
+ "d,v,t", dreg, dreg, AT);
break;
case M_ROR:
@@ -6719,15 +6770,44 @@ macro2 (ip)
"d,v,t", dreg, dreg, AT);
break;
+ case M_DROR_I:
+ {
+ unsigned int rot;
+ char *l, *r;
+
+ if (imm_expr.X_op != O_constant)
+ as_bad (_("rotate count too large"));
+ rot = imm_expr.X_add_number & 0x3f;
+ if (! rot)
+ break;
+ r = (rot < 0x20) ? "dsrl" : "dsrl32";
+ l = ((0x40 - rot) < 0x20) ? "dsll" : "dsll32";
+ rot &= 0x1f;
+ macro_build ((char *) NULL, &icnt, (expressionS *) NULL, r,
+ "d,w,<", AT, sreg, rot);
+ macro_build ((char *) NULL, &icnt, (expressionS *) NULL, l,
+ "d,w,<", dreg, sreg, (0x20 - rot) & 0x1f);
+ macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "or",
+ "d,v,t", dreg, dreg, AT);
+ }
+ break;
+
case M_ROR_I:
- if (imm_expr.X_op != O_constant)
- as_bad (_("rotate count too large"));
- macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "srl", "d,w,<",
- AT, sreg, (int) (imm_expr.X_add_number & 0x1f));
- macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "sll", "d,w,<",
- dreg, sreg, (int) ((0 - imm_expr.X_add_number) & 0x1f));
- macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "or", "d,v,t",
- dreg, dreg, AT);
+ {
+ unsigned int rot;
+
+ if (imm_expr.X_op != O_constant)
+ as_bad (_("rotate count too large"));
+ rot = imm_expr.X_add_number & 0x1f;
+ if (! rot)
+ break;
+ macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "srl",
+ "d,w,<", AT, sreg, rot);
+ macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "sll",
+ "d,w,<", dreg, sreg, (0x20 - rot) & 0x1f);
+ macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "or",
+ "d,v,t", dreg, dreg, AT);
+ }
break;
case M_S_DOB:
Index: gas/testsuite/ChangeLog
===================================================================
RCS file: /cvs/src/src/gas/testsuite/ChangeLog,v
retrieving revision 1.315
diff -u -p -r1.315 ChangeLog
--- gas/testsuite/ChangeLog 20 May 2002 17:05:34 -0000 1.315
+++ gas/testsuite/ChangeLog 21 May 2002 23:32:54 -0000
@@ -1,3 +1,9 @@
+2002-05-22 Thiemo Seufer <seufer@csv.ica.uni-stuttgart.de>
+
+ * gas/mips/rol64.s: New file, test of drol, dror macros.
+ * gas/mips/rol64.d: Likewise.
+ * gas/mips/mips.exp: Add new test.
+
2002-05-20 Nick Clifton <nickc@cambridge.redhat.com>
* gas/arm/arm.exp: Replace deprecated command line switches
Index: gas/testsuite/gas/mips/mips.exp
===================================================================
RCS file: /cvs/src/src/gas/testsuite/gas/mips/mips.exp,v
retrieving revision 1.32
diff -u -p -r1.32 mips.exp
--- gas/testsuite/gas/mips/mips.exp 4 Apr 2002 08:23:30 -0000 1.32
+++ gas/testsuite/gas/mips/mips.exp 21 May 2002 23:32:54 -0000
@@ -122,6 +122,7 @@ if { [istarget mips*-*-*] } then {
run_dump_test "mul"
}
run_dump_test "rol"
+ run_dump_test "rol64"
if !$aout { run_dump_test "sb" }
run_dump_test "trunc"
if !$aout { run_dump_test "ulh" }
Index: include/opcode/ChangeLog
===================================================================
RCS file: /cvs/src/src/include/opcode/ChangeLog,v
retrieving revision 1.167
diff -u -p -r1.167 ChangeLog
--- include/opcode/ChangeLog 17 May 2002 19:01:03 -0000 1.167
+++ include/opcode/ChangeLog 21 May 2002 23:32:57 -0000
@@ -1,3 +1,7 @@
+2002-05-22 Thiemo Seufer <seufer@csv.ica.uni-stuttgart.de>
+
+ * mips.h: Add M_DROL, M_DROL_I, M_DROR, M_DROR_I macro cases.
+
2002-05-17 Andrey Volkov <avolkov@sources.redhat.com>
* h8300.h: Corrected defs of all control regs
Index: include/opcode/mips.h
===================================================================
RCS file: /cvs/src/src/include/opcode/mips.h,v
retrieving revision 1.24
diff -u -p -r1.24 mips.h
--- include/opcode/mips.h 16 Mar 2002 03:09:18 -0000 1.24
+++ include/opcode/mips.h 21 May 2002 23:32:57 -0000
@@ -526,9 +526,13 @@ enum
M_REM_3I,
M_REMU_3,
M_REMU_3I,
+ M_DROL,
M_ROL,
+ M_DROL_I,
M_ROL_I,
+ M_DROR,
M_ROR,
+ M_DROR_I,
M_ROR_I,
M_S_DA,
M_S_DOB,
Index: opcodes/ChangeLog
===================================================================
RCS file: /cvs/src/src/opcodes/ChangeLog,v
retrieving revision 1.447
diff -u -p -r1.447 ChangeLog
--- opcodes/ChangeLog 17 May 2002 14:36:45 -0000 1.447
+++ opcodes/ChangeLog 21 May 2002 23:33:00 -0000
@@ -1,3 +1,7 @@
+2002-05-22 Thiemo Seufer <seufer@csv.ica.uni-stuttgart.de>
+
+ * mips-opc.c (mips_builtin_opcodes): Add drol, dror macros.
+
Fri May 17 14:26:44 2002 J"orn Rennecke <joern.rennecke@superh.com>
* disassemble.c (disassembler): Just use print_insn_sh for bfd_arch_sh.
Index: opcodes/mips-opc.c
===================================================================
RCS file: /cvs/src/src/opcodes/mips-opc.c,v
retrieving revision 1.32
diff -u -p -r1.32 mips-opc.c
--- opcodes/mips-opc.c 17 Mar 2002 02:42:25 -0000 1.32
+++ opcodes/mips-opc.c 21 May 2002 23:33:00 -0000
@@ -492,6 +492,10 @@ const struct mips_opcode mips_builtin_op
{"dremu", "z,s,t", 0x0000001f, 0xfc00ffff, RD_s|RD_t|WR_HILO, I3 },
{"dremu", "d,v,t", 3, (int) M_DREMU_3, INSN_MACRO, I3 },
{"dremu", "d,v,I", 3, (int) M_DREMU_3I, INSN_MACRO, I3 },
+{"drol", "d,v,t", 0, (int) M_DROL, INSN_MACRO, I3 },
+{"drol", "d,v,I", 0, (int) M_DROL_I, INSN_MACRO, I3 },
+{"dror", "d,v,t", 0, (int) M_DROR, INSN_MACRO, I3 },
+{"dror", "d,v,I", 0, (int) M_DROR_I, INSN_MACRO, I3 },
{"dsllv", "d,t,s", 0x00000014, 0xfc0007ff, WR_d|RD_t|RD_s, I3 },
{"dsll32", "d,w,<", 0x0000003c, 0xffe0003f, WR_d|RD_t, I3 },
{"dsll", "d,w,s", 0x00000014, 0xfc0007ff, WR_d|RD_t|RD_s, I3 }, /* dsllv */
2002-05-22 01:54:48 +02:00
|
|
|
|
case M_DROR_I:
|
|
|
|
|
{
|
|
|
|
|
unsigned int rot;
|
[ opcodes/ChangeLog ]
2002-12-18 Chris Demetriou <cgd@broadcom.com>
* mips-opc.c (mips_builtin_opcodes): Remove one "ror" and two
"dror" entries, and reorder the remaining "dror" and "ror" entries.
[ gas/ChangeLog ]
2002-12-18 Chris Demetriou <cgd@broadcom.com>
* config/tc-mips.c (macro): In M_DROL, M_DROR, M_ROL, and M_ROR,
use hardware rotate ops as appropriate. In M_DROL_I, M_DROR_I,
M_ROL_I, and M_ROR_I, simplify code, clean up warnings, and
arrange not to issue warnings about use of AT when AT is not
actually used.
[ gas/testsuite/ChangeLog ]
2002-12-18 Chris Demetriou <cgd@broadcom.com>
* gas/mips/rol.s: Add ".set noat" and some new instructions to test.
* gas/mips/rol64.s: Likewise.
* gas/mips/rol.l: New file.
* gas/mips/rol.d: Adjust to use rol.l and for rol.s changes.
* gas/mips/rol64.l: New file.
* gas/mips/rol64.d: Adjust to use rol64.l and for rol64.s changes.
* gas/mips/rol-hw.d: New file.
* gas/mips/rol-hw.l: New file.
* gas/mips/rol64-hw.d: New file.
* gas/mips/rol64-hw.l: New file.
* gas/mips/mips.exp: Run rol-hw and rol64-hw tests.
2002-12-18 23:52:48 +01:00
|
|
|
|
char *l, *r;
|
? gas/testsuite/gas/mips/rol64.d
? gas/testsuite/gas/mips/rol64.s
Index: gas/ChangeLog
===================================================================
RCS file: /cvs/src/src/gas/ChangeLog,v
retrieving revision 1.1334
diff -u -p -r1.1334 ChangeLog
--- gas/ChangeLog 21 May 2002 20:01:51 -0000 1.1334
+++ gas/ChangeLog 21 May 2002 23:32:51 -0000
@@ -1,3 +1,8 @@
+2002-05-22 Thiemo Seufer <seufer@csv.ica.uni-stuttgart.de>
+
+ * config/tc-mips.c (macro2): Add 64 bit drol, dror macros.
+ Optimize the rotate by zero case.
+
2002-05-21 Nick Clifton <nickc@cambridge.redhat.com>
* configure.in: Remove accidental enabling of bfd_gas=yes for
Index: gas/config/tc-mips.c
===================================================================
RCS file: /cvs/src/src/gas/config/tc-mips.c,v
retrieving revision 1.123
diff -u -p -r1.123 tc-mips.c
--- gas/config/tc-mips.c 14 May 2002 23:35:59 -0000 1.123
+++ gas/config/tc-mips.c 21 May 2002 23:32:52 -0000
@@ -6686,6 +6686,17 @@ macro2 (ip)
--mips_opts.noreorder;
break;
+ case M_DROL:
+ macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "dsubu",
+ "d,v,t", AT, 0, treg);
+ macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "dsrlv",
+ "d,t,s", AT, sreg, AT);
+ macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "dsllv",
+ "d,t,s", dreg, sreg, treg);
+ macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "or",
+ "d,v,t", dreg, dreg, AT);
+ break;
+
case M_ROL:
macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "subu",
"d,v,t", AT, 0, treg);
@@ -6697,15 +6708,55 @@ macro2 (ip)
"d,v,t", dreg, dreg, AT);
break;
+ case M_DROL_I:
+ {
+ unsigned int rot;
+ char *l, *r;
+
+ if (imm_expr.X_op != O_constant)
+ as_bad (_("rotate count too large"));
+ rot = imm_expr.X_add_number & 0x3f;
+ if (! rot)
+ break;
+ l = (rot < 0x20) ? "dsll" : "dsll32";
+ r = ((0x40 - rot) < 0x20) ? "dsrl" : "dsrl32";
+ rot &= 0x1f;
+ macro_build ((char *) NULL, &icnt, (expressionS *) NULL, l,
+ "d,w,<", AT, sreg, rot);
+ macro_build ((char *) NULL, &icnt, (expressionS *) NULL, r,
+ "d,w,<", dreg, sreg, (0x20 - rot) & 0x1f);
+ macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "or",
+ "d,v,t", dreg, dreg, AT);
+ }
+ break;
+
case M_ROL_I:
- if (imm_expr.X_op != O_constant)
- as_bad (_("rotate count too large"));
- macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "sll", "d,w,<",
- AT, sreg, (int) (imm_expr.X_add_number & 0x1f));
- macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "srl", "d,w,<",
- dreg, sreg, (int) ((0 - imm_expr.X_add_number) & 0x1f));
- macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "or", "d,v,t",
- dreg, dreg, AT);
+ {
+ unsigned int rot;
+
+ if (imm_expr.X_op != O_constant)
+ as_bad (_("rotate count too large"));
+ rot = imm_expr.X_add_number & 0x1f;
+ if (! rot)
+ break;
+ macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "sll",
+ "d,w,<", AT, sreg, rot);
+ macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "srl",
+ "d,w,<", dreg, sreg, (0x20 - rot) & 0x1f);
+ macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "or",
+ "d,v,t", dreg, dreg, AT);
+ }
+ break;
+
+ case M_DROR:
+ macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "dsubu",
+ "d,v,t", AT, 0, treg);
+ macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "dsllv",
+ "d,t,s", AT, sreg, AT);
+ macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "dsrlv",
+ "d,t,s", dreg, sreg, treg);
+ macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "or",
+ "d,v,t", dreg, dreg, AT);
break;
case M_ROR:
@@ -6719,15 +6770,44 @@ macro2 (ip)
"d,v,t", dreg, dreg, AT);
break;
+ case M_DROR_I:
+ {
+ unsigned int rot;
+ char *l, *r;
+
+ if (imm_expr.X_op != O_constant)
+ as_bad (_("rotate count too large"));
+ rot = imm_expr.X_add_number & 0x3f;
+ if (! rot)
+ break;
+ r = (rot < 0x20) ? "dsrl" : "dsrl32";
+ l = ((0x40 - rot) < 0x20) ? "dsll" : "dsll32";
+ rot &= 0x1f;
+ macro_build ((char *) NULL, &icnt, (expressionS *) NULL, r,
+ "d,w,<", AT, sreg, rot);
+ macro_build ((char *) NULL, &icnt, (expressionS *) NULL, l,
+ "d,w,<", dreg, sreg, (0x20 - rot) & 0x1f);
+ macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "or",
+ "d,v,t", dreg, dreg, AT);
+ }
+ break;
+
case M_ROR_I:
- if (imm_expr.X_op != O_constant)
- as_bad (_("rotate count too large"));
- macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "srl", "d,w,<",
- AT, sreg, (int) (imm_expr.X_add_number & 0x1f));
- macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "sll", "d,w,<",
- dreg, sreg, (int) ((0 - imm_expr.X_add_number) & 0x1f));
- macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "or", "d,v,t",
- dreg, dreg, AT);
+ {
+ unsigned int rot;
+
+ if (imm_expr.X_op != O_constant)
+ as_bad (_("rotate count too large"));
+ rot = imm_expr.X_add_number & 0x1f;
+ if (! rot)
+ break;
+ macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "srl",
+ "d,w,<", AT, sreg, rot);
+ macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "sll",
+ "d,w,<", dreg, sreg, (0x20 - rot) & 0x1f);
+ macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "or",
+ "d,v,t", dreg, dreg, AT);
+ }
break;
case M_S_DOB:
Index: gas/testsuite/ChangeLog
===================================================================
RCS file: /cvs/src/src/gas/testsuite/ChangeLog,v
retrieving revision 1.315
diff -u -p -r1.315 ChangeLog
--- gas/testsuite/ChangeLog 20 May 2002 17:05:34 -0000 1.315
+++ gas/testsuite/ChangeLog 21 May 2002 23:32:54 -0000
@@ -1,3 +1,9 @@
+2002-05-22 Thiemo Seufer <seufer@csv.ica.uni-stuttgart.de>
+
+ * gas/mips/rol64.s: New file, test of drol, dror macros.
+ * gas/mips/rol64.d: Likewise.
+ * gas/mips/mips.exp: Add new test.
+
2002-05-20 Nick Clifton <nickc@cambridge.redhat.com>
* gas/arm/arm.exp: Replace deprecated command line switches
Index: gas/testsuite/gas/mips/mips.exp
===================================================================
RCS file: /cvs/src/src/gas/testsuite/gas/mips/mips.exp,v
retrieving revision 1.32
diff -u -p -r1.32 mips.exp
--- gas/testsuite/gas/mips/mips.exp 4 Apr 2002 08:23:30 -0000 1.32
+++ gas/testsuite/gas/mips/mips.exp 21 May 2002 23:32:54 -0000
@@ -122,6 +122,7 @@ if { [istarget mips*-*-*] } then {
run_dump_test "mul"
}
run_dump_test "rol"
+ run_dump_test "rol64"
if !$aout { run_dump_test "sb" }
run_dump_test "trunc"
if !$aout { run_dump_test "ulh" }
Index: include/opcode/ChangeLog
===================================================================
RCS file: /cvs/src/src/include/opcode/ChangeLog,v
retrieving revision 1.167
diff -u -p -r1.167 ChangeLog
--- include/opcode/ChangeLog 17 May 2002 19:01:03 -0000 1.167
+++ include/opcode/ChangeLog 21 May 2002 23:32:57 -0000
@@ -1,3 +1,7 @@
+2002-05-22 Thiemo Seufer <seufer@csv.ica.uni-stuttgart.de>
+
+ * mips.h: Add M_DROL, M_DROL_I, M_DROR, M_DROR_I macro cases.
+
2002-05-17 Andrey Volkov <avolkov@sources.redhat.com>
* h8300.h: Corrected defs of all control regs
Index: include/opcode/mips.h
===================================================================
RCS file: /cvs/src/src/include/opcode/mips.h,v
retrieving revision 1.24
diff -u -p -r1.24 mips.h
--- include/opcode/mips.h 16 Mar 2002 03:09:18 -0000 1.24
+++ include/opcode/mips.h 21 May 2002 23:32:57 -0000
@@ -526,9 +526,13 @@ enum
M_REM_3I,
M_REMU_3,
M_REMU_3I,
+ M_DROL,
M_ROL,
+ M_DROL_I,
M_ROL_I,
+ M_DROR,
M_ROR,
+ M_DROR_I,
M_ROR_I,
M_S_DA,
M_S_DOB,
Index: opcodes/ChangeLog
===================================================================
RCS file: /cvs/src/src/opcodes/ChangeLog,v
retrieving revision 1.447
diff -u -p -r1.447 ChangeLog
--- opcodes/ChangeLog 17 May 2002 14:36:45 -0000 1.447
+++ opcodes/ChangeLog 21 May 2002 23:33:00 -0000
@@ -1,3 +1,7 @@
+2002-05-22 Thiemo Seufer <seufer@csv.ica.uni-stuttgart.de>
+
+ * mips-opc.c (mips_builtin_opcodes): Add drol, dror macros.
+
Fri May 17 14:26:44 2002 J"orn Rennecke <joern.rennecke@superh.com>
* disassemble.c (disassembler): Just use print_insn_sh for bfd_arch_sh.
Index: opcodes/mips-opc.c
===================================================================
RCS file: /cvs/src/src/opcodes/mips-opc.c,v
retrieving revision 1.32
diff -u -p -r1.32 mips-opc.c
--- opcodes/mips-opc.c 17 Mar 2002 02:42:25 -0000 1.32
+++ opcodes/mips-opc.c 21 May 2002 23:33:00 -0000
@@ -492,6 +492,10 @@ const struct mips_opcode mips_builtin_op
{"dremu", "z,s,t", 0x0000001f, 0xfc00ffff, RD_s|RD_t|WR_HILO, I3 },
{"dremu", "d,v,t", 3, (int) M_DREMU_3, INSN_MACRO, I3 },
{"dremu", "d,v,I", 3, (int) M_DREMU_3I, INSN_MACRO, I3 },
+{"drol", "d,v,t", 0, (int) M_DROL, INSN_MACRO, I3 },
+{"drol", "d,v,I", 0, (int) M_DROL_I, INSN_MACRO, I3 },
+{"dror", "d,v,t", 0, (int) M_DROR, INSN_MACRO, I3 },
+{"dror", "d,v,I", 0, (int) M_DROR_I, INSN_MACRO, I3 },
{"dsllv", "d,t,s", 0x00000014, 0xfc0007ff, WR_d|RD_t|RD_s, I3 },
{"dsll32", "d,w,<", 0x0000003c, 0xffe0003f, WR_d|RD_t, I3 },
{"dsll", "d,w,s", 0x00000014, 0xfc0007ff, WR_d|RD_t|RD_s, I3 }, /* dsllv */
2002-05-22 01:54:48 +02:00
|
|
|
|
|
|
|
|
|
if (imm_expr.X_op != O_constant)
|
[ opcodes/ChangeLog ]
2002-12-18 Chris Demetriou <cgd@broadcom.com>
* mips-opc.c (mips_builtin_opcodes): Remove one "ror" and two
"dror" entries, and reorder the remaining "dror" and "ror" entries.
[ gas/ChangeLog ]
2002-12-18 Chris Demetriou <cgd@broadcom.com>
* config/tc-mips.c (macro): In M_DROL, M_DROR, M_ROL, and M_ROR,
use hardware rotate ops as appropriate. In M_DROL_I, M_DROR_I,
M_ROL_I, and M_ROR_I, simplify code, clean up warnings, and
arrange not to issue warnings about use of AT when AT is not
actually used.
[ gas/testsuite/ChangeLog ]
2002-12-18 Chris Demetriou <cgd@broadcom.com>
* gas/mips/rol.s: Add ".set noat" and some new instructions to test.
* gas/mips/rol64.s: Likewise.
* gas/mips/rol.l: New file.
* gas/mips/rol.d: Adjust to use rol.l and for rol.s changes.
* gas/mips/rol64.l: New file.
* gas/mips/rol64.d: Adjust to use rol64.l and for rol64.s changes.
* gas/mips/rol-hw.d: New file.
* gas/mips/rol-hw.l: New file.
* gas/mips/rol64-hw.d: New file.
* gas/mips/rol64-hw.l: New file.
* gas/mips/mips.exp: Run rol-hw and rol64-hw tests.
2002-12-18 23:52:48 +01:00
|
|
|
|
as_bad (_("Improper rotate count"));
|
? gas/testsuite/gas/mips/rol64.d
? gas/testsuite/gas/mips/rol64.s
Index: gas/ChangeLog
===================================================================
RCS file: /cvs/src/src/gas/ChangeLog,v
retrieving revision 1.1334
diff -u -p -r1.1334 ChangeLog
--- gas/ChangeLog 21 May 2002 20:01:51 -0000 1.1334
+++ gas/ChangeLog 21 May 2002 23:32:51 -0000
@@ -1,3 +1,8 @@
+2002-05-22 Thiemo Seufer <seufer@csv.ica.uni-stuttgart.de>
+
+ * config/tc-mips.c (macro2): Add 64 bit drol, dror macros.
+ Optimize the rotate by zero case.
+
2002-05-21 Nick Clifton <nickc@cambridge.redhat.com>
* configure.in: Remove accidental enabling of bfd_gas=yes for
Index: gas/config/tc-mips.c
===================================================================
RCS file: /cvs/src/src/gas/config/tc-mips.c,v
retrieving revision 1.123
diff -u -p -r1.123 tc-mips.c
--- gas/config/tc-mips.c 14 May 2002 23:35:59 -0000 1.123
+++ gas/config/tc-mips.c 21 May 2002 23:32:52 -0000
@@ -6686,6 +6686,17 @@ macro2 (ip)
--mips_opts.noreorder;
break;
+ case M_DROL:
+ macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "dsubu",
+ "d,v,t", AT, 0, treg);
+ macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "dsrlv",
+ "d,t,s", AT, sreg, AT);
+ macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "dsllv",
+ "d,t,s", dreg, sreg, treg);
+ macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "or",
+ "d,v,t", dreg, dreg, AT);
+ break;
+
case M_ROL:
macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "subu",
"d,v,t", AT, 0, treg);
@@ -6697,15 +6708,55 @@ macro2 (ip)
"d,v,t", dreg, dreg, AT);
break;
+ case M_DROL_I:
+ {
+ unsigned int rot;
+ char *l, *r;
+
+ if (imm_expr.X_op != O_constant)
+ as_bad (_("rotate count too large"));
+ rot = imm_expr.X_add_number & 0x3f;
+ if (! rot)
+ break;
+ l = (rot < 0x20) ? "dsll" : "dsll32";
+ r = ((0x40 - rot) < 0x20) ? "dsrl" : "dsrl32";
+ rot &= 0x1f;
+ macro_build ((char *) NULL, &icnt, (expressionS *) NULL, l,
+ "d,w,<", AT, sreg, rot);
+ macro_build ((char *) NULL, &icnt, (expressionS *) NULL, r,
+ "d,w,<", dreg, sreg, (0x20 - rot) & 0x1f);
+ macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "or",
+ "d,v,t", dreg, dreg, AT);
+ }
+ break;
+
case M_ROL_I:
- if (imm_expr.X_op != O_constant)
- as_bad (_("rotate count too large"));
- macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "sll", "d,w,<",
- AT, sreg, (int) (imm_expr.X_add_number & 0x1f));
- macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "srl", "d,w,<",
- dreg, sreg, (int) ((0 - imm_expr.X_add_number) & 0x1f));
- macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "or", "d,v,t",
- dreg, dreg, AT);
+ {
+ unsigned int rot;
+
+ if (imm_expr.X_op != O_constant)
+ as_bad (_("rotate count too large"));
+ rot = imm_expr.X_add_number & 0x1f;
+ if (! rot)
+ break;
+ macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "sll",
+ "d,w,<", AT, sreg, rot);
+ macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "srl",
+ "d,w,<", dreg, sreg, (0x20 - rot) & 0x1f);
+ macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "or",
+ "d,v,t", dreg, dreg, AT);
+ }
+ break;
+
+ case M_DROR:
+ macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "dsubu",
+ "d,v,t", AT, 0, treg);
+ macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "dsllv",
+ "d,t,s", AT, sreg, AT);
+ macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "dsrlv",
+ "d,t,s", dreg, sreg, treg);
+ macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "or",
+ "d,v,t", dreg, dreg, AT);
break;
case M_ROR:
@@ -6719,15 +6770,44 @@ macro2 (ip)
"d,v,t", dreg, dreg, AT);
break;
+ case M_DROR_I:
+ {
+ unsigned int rot;
+ char *l, *r;
+
+ if (imm_expr.X_op != O_constant)
+ as_bad (_("rotate count too large"));
+ rot = imm_expr.X_add_number & 0x3f;
+ if (! rot)
+ break;
+ r = (rot < 0x20) ? "dsrl" : "dsrl32";
+ l = ((0x40 - rot) < 0x20) ? "dsll" : "dsll32";
+ rot &= 0x1f;
+ macro_build ((char *) NULL, &icnt, (expressionS *) NULL, r,
+ "d,w,<", AT, sreg, rot);
+ macro_build ((char *) NULL, &icnt, (expressionS *) NULL, l,
+ "d,w,<", dreg, sreg, (0x20 - rot) & 0x1f);
+ macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "or",
+ "d,v,t", dreg, dreg, AT);
+ }
+ break;
+
case M_ROR_I:
- if (imm_expr.X_op != O_constant)
- as_bad (_("rotate count too large"));
- macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "srl", "d,w,<",
- AT, sreg, (int) (imm_expr.X_add_number & 0x1f));
- macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "sll", "d,w,<",
- dreg, sreg, (int) ((0 - imm_expr.X_add_number) & 0x1f));
- macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "or", "d,v,t",
- dreg, dreg, AT);
+ {
+ unsigned int rot;
+
+ if (imm_expr.X_op != O_constant)
+ as_bad (_("rotate count too large"));
+ rot = imm_expr.X_add_number & 0x1f;
+ if (! rot)
+ break;
+ macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "srl",
+ "d,w,<", AT, sreg, rot);
+ macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "sll",
+ "d,w,<", dreg, sreg, (0x20 - rot) & 0x1f);
+ macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "or",
+ "d,v,t", dreg, dreg, AT);
+ }
break;
case M_S_DOB:
Index: gas/testsuite/ChangeLog
===================================================================
RCS file: /cvs/src/src/gas/testsuite/ChangeLog,v
retrieving revision 1.315
diff -u -p -r1.315 ChangeLog
--- gas/testsuite/ChangeLog 20 May 2002 17:05:34 -0000 1.315
+++ gas/testsuite/ChangeLog 21 May 2002 23:32:54 -0000
@@ -1,3 +1,9 @@
+2002-05-22 Thiemo Seufer <seufer@csv.ica.uni-stuttgart.de>
+
+ * gas/mips/rol64.s: New file, test of drol, dror macros.
+ * gas/mips/rol64.d: Likewise.
+ * gas/mips/mips.exp: Add new test.
+
2002-05-20 Nick Clifton <nickc@cambridge.redhat.com>
* gas/arm/arm.exp: Replace deprecated command line switches
Index: gas/testsuite/gas/mips/mips.exp
===================================================================
RCS file: /cvs/src/src/gas/testsuite/gas/mips/mips.exp,v
retrieving revision 1.32
diff -u -p -r1.32 mips.exp
--- gas/testsuite/gas/mips/mips.exp 4 Apr 2002 08:23:30 -0000 1.32
+++ gas/testsuite/gas/mips/mips.exp 21 May 2002 23:32:54 -0000
@@ -122,6 +122,7 @@ if { [istarget mips*-*-*] } then {
run_dump_test "mul"
}
run_dump_test "rol"
+ run_dump_test "rol64"
if !$aout { run_dump_test "sb" }
run_dump_test "trunc"
if !$aout { run_dump_test "ulh" }
Index: include/opcode/ChangeLog
===================================================================
RCS file: /cvs/src/src/include/opcode/ChangeLog,v
retrieving revision 1.167
diff -u -p -r1.167 ChangeLog
--- include/opcode/ChangeLog 17 May 2002 19:01:03 -0000 1.167
+++ include/opcode/ChangeLog 21 May 2002 23:32:57 -0000
@@ -1,3 +1,7 @@
+2002-05-22 Thiemo Seufer <seufer@csv.ica.uni-stuttgart.de>
+
+ * mips.h: Add M_DROL, M_DROL_I, M_DROR, M_DROR_I macro cases.
+
2002-05-17 Andrey Volkov <avolkov@sources.redhat.com>
* h8300.h: Corrected defs of all control regs
Index: include/opcode/mips.h
===================================================================
RCS file: /cvs/src/src/include/opcode/mips.h,v
retrieving revision 1.24
diff -u -p -r1.24 mips.h
--- include/opcode/mips.h 16 Mar 2002 03:09:18 -0000 1.24
+++ include/opcode/mips.h 21 May 2002 23:32:57 -0000
@@ -526,9 +526,13 @@ enum
M_REM_3I,
M_REMU_3,
M_REMU_3I,
+ M_DROL,
M_ROL,
+ M_DROL_I,
M_ROL_I,
+ M_DROR,
M_ROR,
+ M_DROR_I,
M_ROR_I,
M_S_DA,
M_S_DOB,
Index: opcodes/ChangeLog
===================================================================
RCS file: /cvs/src/src/opcodes/ChangeLog,v
retrieving revision 1.447
diff -u -p -r1.447 ChangeLog
--- opcodes/ChangeLog 17 May 2002 14:36:45 -0000 1.447
+++ opcodes/ChangeLog 21 May 2002 23:33:00 -0000
@@ -1,3 +1,7 @@
+2002-05-22 Thiemo Seufer <seufer@csv.ica.uni-stuttgart.de>
+
+ * mips-opc.c (mips_builtin_opcodes): Add drol, dror macros.
+
Fri May 17 14:26:44 2002 J"orn Rennecke <joern.rennecke@superh.com>
* disassemble.c (disassembler): Just use print_insn_sh for bfd_arch_sh.
Index: opcodes/mips-opc.c
===================================================================
RCS file: /cvs/src/src/opcodes/mips-opc.c,v
retrieving revision 1.32
diff -u -p -r1.32 mips-opc.c
--- opcodes/mips-opc.c 17 Mar 2002 02:42:25 -0000 1.32
+++ opcodes/mips-opc.c 21 May 2002 23:33:00 -0000
@@ -492,6 +492,10 @@ const struct mips_opcode mips_builtin_op
{"dremu", "z,s,t", 0x0000001f, 0xfc00ffff, RD_s|RD_t|WR_HILO, I3 },
{"dremu", "d,v,t", 3, (int) M_DREMU_3, INSN_MACRO, I3 },
{"dremu", "d,v,I", 3, (int) M_DREMU_3I, INSN_MACRO, I3 },
+{"drol", "d,v,t", 0, (int) M_DROL, INSN_MACRO, I3 },
+{"drol", "d,v,I", 0, (int) M_DROL_I, INSN_MACRO, I3 },
+{"dror", "d,v,t", 0, (int) M_DROR, INSN_MACRO, I3 },
+{"dror", "d,v,I", 0, (int) M_DROR_I, INSN_MACRO, I3 },
{"dsllv", "d,t,s", 0x00000014, 0xfc0007ff, WR_d|RD_t|RD_s, I3 },
{"dsll32", "d,w,<", 0x0000003c, 0xffe0003f, WR_d|RD_t, I3 },
{"dsll", "d,w,s", 0x00000014, 0xfc0007ff, WR_d|RD_t|RD_s, I3 }, /* dsllv */
2002-05-22 01:54:48 +02:00
|
|
|
|
rot = imm_expr.X_add_number & 0x3f;
|
2003-06-29 21:41:33 +02:00
|
|
|
|
if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch))
|
[ opcodes/ChangeLog ]
2002-12-18 Chris Demetriou <cgd@broadcom.com>
* mips-opc.c (mips_builtin_opcodes): Remove one "ror" and two
"dror" entries, and reorder the remaining "dror" and "ror" entries.
[ gas/ChangeLog ]
2002-12-18 Chris Demetriou <cgd@broadcom.com>
* config/tc-mips.c (macro): In M_DROL, M_DROR, M_ROL, and M_ROR,
use hardware rotate ops as appropriate. In M_DROL_I, M_DROR_I,
M_ROL_I, and M_ROR_I, simplify code, clean up warnings, and
arrange not to issue warnings about use of AT when AT is not
actually used.
[ gas/testsuite/ChangeLog ]
2002-12-18 Chris Demetriou <cgd@broadcom.com>
* gas/mips/rol.s: Add ".set noat" and some new instructions to test.
* gas/mips/rol64.s: Likewise.
* gas/mips/rol.l: New file.
* gas/mips/rol.d: Adjust to use rol.l and for rol.s changes.
* gas/mips/rol64.l: New file.
* gas/mips/rol64.d: Adjust to use rol64.l and for rol64.s changes.
* gas/mips/rol-hw.d: New file.
* gas/mips/rol-hw.l: New file.
* gas/mips/rol64-hw.d: New file.
* gas/mips/rol64-hw.l: New file.
* gas/mips/mips.exp: Run rol-hw and rol64-hw tests.
2002-12-18 23:52:48 +01:00
|
|
|
|
{
|
|
|
|
|
if (rot >= 32)
|
2003-06-30 14:44:25 +02:00
|
|
|
|
macro_build (NULL, &icnt, NULL, "dror32", "d,w,<",
|
|
|
|
|
dreg, sreg, rot - 32);
|
[ opcodes/ChangeLog ]
2002-12-18 Chris Demetriou <cgd@broadcom.com>
* mips-opc.c (mips_builtin_opcodes): Remove one "ror" and two
"dror" entries, and reorder the remaining "dror" and "ror" entries.
[ gas/ChangeLog ]
2002-12-18 Chris Demetriou <cgd@broadcom.com>
* config/tc-mips.c (macro): In M_DROL, M_DROR, M_ROL, and M_ROR,
use hardware rotate ops as appropriate. In M_DROL_I, M_DROR_I,
M_ROL_I, and M_ROR_I, simplify code, clean up warnings, and
arrange not to issue warnings about use of AT when AT is not
actually used.
[ gas/testsuite/ChangeLog ]
2002-12-18 Chris Demetriou <cgd@broadcom.com>
* gas/mips/rol.s: Add ".set noat" and some new instructions to test.
* gas/mips/rol64.s: Likewise.
* gas/mips/rol.l: New file.
* gas/mips/rol.d: Adjust to use rol.l and for rol.s changes.
* gas/mips/rol64.l: New file.
* gas/mips/rol64.d: Adjust to use rol64.l and for rol64.s changes.
* gas/mips/rol-hw.d: New file.
* gas/mips/rol-hw.l: New file.
* gas/mips/rol64-hw.d: New file.
* gas/mips/rol64-hw.l: New file.
* gas/mips/mips.exp: Run rol-hw and rol64-hw tests.
2002-12-18 23:52:48 +01:00
|
|
|
|
else
|
2003-06-30 14:44:25 +02:00
|
|
|
|
macro_build (NULL, &icnt, NULL, "dror", "d,w,<",
|
|
|
|
|
dreg, sreg, rot);
|
[ opcodes/ChangeLog ]
2002-12-18 Chris Demetriou <cgd@broadcom.com>
* mips-opc.c (mips_builtin_opcodes): Remove one "ror" and two
"dror" entries, and reorder the remaining "dror" and "ror" entries.
[ gas/ChangeLog ]
2002-12-18 Chris Demetriou <cgd@broadcom.com>
* config/tc-mips.c (macro): In M_DROL, M_DROR, M_ROL, and M_ROR,
use hardware rotate ops as appropriate. In M_DROL_I, M_DROR_I,
M_ROL_I, and M_ROR_I, simplify code, clean up warnings, and
arrange not to issue warnings about use of AT when AT is not
actually used.
[ gas/testsuite/ChangeLog ]
2002-12-18 Chris Demetriou <cgd@broadcom.com>
* gas/mips/rol.s: Add ".set noat" and some new instructions to test.
* gas/mips/rol64.s: Likewise.
* gas/mips/rol.l: New file.
* gas/mips/rol.d: Adjust to use rol.l and for rol.s changes.
* gas/mips/rol64.l: New file.
* gas/mips/rol64.d: Adjust to use rol64.l and for rol64.s changes.
* gas/mips/rol-hw.d: New file.
* gas/mips/rol-hw.l: New file.
* gas/mips/rol64-hw.d: New file.
* gas/mips/rol64-hw.l: New file.
* gas/mips/mips.exp: Run rol-hw and rol64-hw tests.
2002-12-18 23:52:48 +01:00
|
|
|
|
return;
|
|
|
|
|
}
|
2002-08-20 10:28:35 +02:00
|
|
|
|
if (rot == 0)
|
|
|
|
|
{
|
2003-06-30 14:44:25 +02:00
|
|
|
|
macro_build (NULL, &icnt, NULL, "dsrl", "d,w,<", dreg, sreg, 0);
|
[ opcodes/ChangeLog ]
2002-12-18 Chris Demetriou <cgd@broadcom.com>
* mips-opc.c (mips_builtin_opcodes): Remove one "ror" and two
"dror" entries, and reorder the remaining "dror" and "ror" entries.
[ gas/ChangeLog ]
2002-12-18 Chris Demetriou <cgd@broadcom.com>
* config/tc-mips.c (macro): In M_DROL, M_DROR, M_ROL, and M_ROR,
use hardware rotate ops as appropriate. In M_DROL_I, M_DROR_I,
M_ROL_I, and M_ROR_I, simplify code, clean up warnings, and
arrange not to issue warnings about use of AT when AT is not
actually used.
[ gas/testsuite/ChangeLog ]
2002-12-18 Chris Demetriou <cgd@broadcom.com>
* gas/mips/rol.s: Add ".set noat" and some new instructions to test.
* gas/mips/rol64.s: Likewise.
* gas/mips/rol.l: New file.
* gas/mips/rol.d: Adjust to use rol.l and for rol.s changes.
* gas/mips/rol64.l: New file.
* gas/mips/rol64.d: Adjust to use rol64.l and for rol64.s changes.
* gas/mips/rol-hw.d: New file.
* gas/mips/rol-hw.l: New file.
* gas/mips/rol64-hw.d: New file.
* gas/mips/rol64-hw.l: New file.
* gas/mips/mips.exp: Run rol-hw and rol64-hw tests.
2002-12-18 23:52:48 +01:00
|
|
|
|
return;
|
2002-08-20 10:28:35 +02:00
|
|
|
|
}
|
[ opcodes/ChangeLog ]
2002-12-18 Chris Demetriou <cgd@broadcom.com>
* mips-opc.c (mips_builtin_opcodes): Remove one "ror" and two
"dror" entries, and reorder the remaining "dror" and "ror" entries.
[ gas/ChangeLog ]
2002-12-18 Chris Demetriou <cgd@broadcom.com>
* config/tc-mips.c (macro): In M_DROL, M_DROR, M_ROL, and M_ROR,
use hardware rotate ops as appropriate. In M_DROL_I, M_DROR_I,
M_ROL_I, and M_ROR_I, simplify code, clean up warnings, and
arrange not to issue warnings about use of AT when AT is not
actually used.
[ gas/testsuite/ChangeLog ]
2002-12-18 Chris Demetriou <cgd@broadcom.com>
* gas/mips/rol.s: Add ".set noat" and some new instructions to test.
* gas/mips/rol64.s: Likewise.
* gas/mips/rol.l: New file.
* gas/mips/rol.d: Adjust to use rol.l and for rol.s changes.
* gas/mips/rol64.l: New file.
* gas/mips/rol64.d: Adjust to use rol64.l and for rol64.s changes.
* gas/mips/rol-hw.d: New file.
* gas/mips/rol-hw.l: New file.
* gas/mips/rol64-hw.d: New file.
* gas/mips/rol64-hw.l: New file.
* gas/mips/mips.exp: Run rol-hw and rol64-hw tests.
2002-12-18 23:52:48 +01:00
|
|
|
|
r = (rot < 0x20) ? "dsrl" : "dsrl32";
|
|
|
|
|
l = ((0x40 - rot) < 0x20) ? "dsll" : "dsll32";
|
|
|
|
|
rot &= 0x1f;
|
2003-11-15 16:57:14 +01:00
|
|
|
|
macro_build (NULL, &icnt, NULL, r, "d,w,<", AT, sreg, rot);
|
2003-06-30 14:44:25 +02:00
|
|
|
|
macro_build (NULL, &icnt, NULL, l, "d,w,<", dreg, sreg,
|
|
|
|
|
(0x20 - rot) & 0x1f);
|
|
|
|
|
macro_build (NULL, &icnt, NULL, "or", "d,v,t", dreg, dreg, AT);
|
? gas/testsuite/gas/mips/rol64.d
? gas/testsuite/gas/mips/rol64.s
Index: gas/ChangeLog
===================================================================
RCS file: /cvs/src/src/gas/ChangeLog,v
retrieving revision 1.1334
diff -u -p -r1.1334 ChangeLog
--- gas/ChangeLog 21 May 2002 20:01:51 -0000 1.1334
+++ gas/ChangeLog 21 May 2002 23:32:51 -0000
@@ -1,3 +1,8 @@
+2002-05-22 Thiemo Seufer <seufer@csv.ica.uni-stuttgart.de>
+
+ * config/tc-mips.c (macro2): Add 64 bit drol, dror macros.
+ Optimize the rotate by zero case.
+
2002-05-21 Nick Clifton <nickc@cambridge.redhat.com>
* configure.in: Remove accidental enabling of bfd_gas=yes for
Index: gas/config/tc-mips.c
===================================================================
RCS file: /cvs/src/src/gas/config/tc-mips.c,v
retrieving revision 1.123
diff -u -p -r1.123 tc-mips.c
--- gas/config/tc-mips.c 14 May 2002 23:35:59 -0000 1.123
+++ gas/config/tc-mips.c 21 May 2002 23:32:52 -0000
@@ -6686,6 +6686,17 @@ macro2 (ip)
--mips_opts.noreorder;
break;
+ case M_DROL:
+ macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "dsubu",
+ "d,v,t", AT, 0, treg);
+ macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "dsrlv",
+ "d,t,s", AT, sreg, AT);
+ macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "dsllv",
+ "d,t,s", dreg, sreg, treg);
+ macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "or",
+ "d,v,t", dreg, dreg, AT);
+ break;
+
case M_ROL:
macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "subu",
"d,v,t", AT, 0, treg);
@@ -6697,15 +6708,55 @@ macro2 (ip)
"d,v,t", dreg, dreg, AT);
break;
+ case M_DROL_I:
+ {
+ unsigned int rot;
+ char *l, *r;
+
+ if (imm_expr.X_op != O_constant)
+ as_bad (_("rotate count too large"));
+ rot = imm_expr.X_add_number & 0x3f;
+ if (! rot)
+ break;
+ l = (rot < 0x20) ? "dsll" : "dsll32";
+ r = ((0x40 - rot) < 0x20) ? "dsrl" : "dsrl32";
+ rot &= 0x1f;
+ macro_build ((char *) NULL, &icnt, (expressionS *) NULL, l,
+ "d,w,<", AT, sreg, rot);
+ macro_build ((char *) NULL, &icnt, (expressionS *) NULL, r,
+ "d,w,<", dreg, sreg, (0x20 - rot) & 0x1f);
+ macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "or",
+ "d,v,t", dreg, dreg, AT);
+ }
+ break;
+
case M_ROL_I:
- if (imm_expr.X_op != O_constant)
- as_bad (_("rotate count too large"));
- macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "sll", "d,w,<",
- AT, sreg, (int) (imm_expr.X_add_number & 0x1f));
- macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "srl", "d,w,<",
- dreg, sreg, (int) ((0 - imm_expr.X_add_number) & 0x1f));
- macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "or", "d,v,t",
- dreg, dreg, AT);
+ {
+ unsigned int rot;
+
+ if (imm_expr.X_op != O_constant)
+ as_bad (_("rotate count too large"));
+ rot = imm_expr.X_add_number & 0x1f;
+ if (! rot)
+ break;
+ macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "sll",
+ "d,w,<", AT, sreg, rot);
+ macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "srl",
+ "d,w,<", dreg, sreg, (0x20 - rot) & 0x1f);
+ macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "or",
+ "d,v,t", dreg, dreg, AT);
+ }
+ break;
+
+ case M_DROR:
+ macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "dsubu",
+ "d,v,t", AT, 0, treg);
+ macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "dsllv",
+ "d,t,s", AT, sreg, AT);
+ macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "dsrlv",
+ "d,t,s", dreg, sreg, treg);
+ macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "or",
+ "d,v,t", dreg, dreg, AT);
break;
case M_ROR:
@@ -6719,15 +6770,44 @@ macro2 (ip)
"d,v,t", dreg, dreg, AT);
break;
+ case M_DROR_I:
+ {
+ unsigned int rot;
+ char *l, *r;
+
+ if (imm_expr.X_op != O_constant)
+ as_bad (_("rotate count too large"));
+ rot = imm_expr.X_add_number & 0x3f;
+ if (! rot)
+ break;
+ r = (rot < 0x20) ? "dsrl" : "dsrl32";
+ l = ((0x40 - rot) < 0x20) ? "dsll" : "dsll32";
+ rot &= 0x1f;
+ macro_build ((char *) NULL, &icnt, (expressionS *) NULL, r,
+ "d,w,<", AT, sreg, rot);
+ macro_build ((char *) NULL, &icnt, (expressionS *) NULL, l,
+ "d,w,<", dreg, sreg, (0x20 - rot) & 0x1f);
+ macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "or",
+ "d,v,t", dreg, dreg, AT);
+ }
+ break;
+
case M_ROR_I:
- if (imm_expr.X_op != O_constant)
- as_bad (_("rotate count too large"));
- macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "srl", "d,w,<",
- AT, sreg, (int) (imm_expr.X_add_number & 0x1f));
- macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "sll", "d,w,<",
- dreg, sreg, (int) ((0 - imm_expr.X_add_number) & 0x1f));
- macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "or", "d,v,t",
- dreg, dreg, AT);
+ {
+ unsigned int rot;
+
+ if (imm_expr.X_op != O_constant)
+ as_bad (_("rotate count too large"));
+ rot = imm_expr.X_add_number & 0x1f;
+ if (! rot)
+ break;
+ macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "srl",
+ "d,w,<", AT, sreg, rot);
+ macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "sll",
+ "d,w,<", dreg, sreg, (0x20 - rot) & 0x1f);
+ macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "or",
+ "d,v,t", dreg, dreg, AT);
+ }
break;
case M_S_DOB:
Index: gas/testsuite/ChangeLog
===================================================================
RCS file: /cvs/src/src/gas/testsuite/ChangeLog,v
retrieving revision 1.315
diff -u -p -r1.315 ChangeLog
--- gas/testsuite/ChangeLog 20 May 2002 17:05:34 -0000 1.315
+++ gas/testsuite/ChangeLog 21 May 2002 23:32:54 -0000
@@ -1,3 +1,9 @@
+2002-05-22 Thiemo Seufer <seufer@csv.ica.uni-stuttgart.de>
+
+ * gas/mips/rol64.s: New file, test of drol, dror macros.
+ * gas/mips/rol64.d: Likewise.
+ * gas/mips/mips.exp: Add new test.
+
2002-05-20 Nick Clifton <nickc@cambridge.redhat.com>
* gas/arm/arm.exp: Replace deprecated command line switches
Index: gas/testsuite/gas/mips/mips.exp
===================================================================
RCS file: /cvs/src/src/gas/testsuite/gas/mips/mips.exp,v
retrieving revision 1.32
diff -u -p -r1.32 mips.exp
--- gas/testsuite/gas/mips/mips.exp 4 Apr 2002 08:23:30 -0000 1.32
+++ gas/testsuite/gas/mips/mips.exp 21 May 2002 23:32:54 -0000
@@ -122,6 +122,7 @@ if { [istarget mips*-*-*] } then {
run_dump_test "mul"
}
run_dump_test "rol"
+ run_dump_test "rol64"
if !$aout { run_dump_test "sb" }
run_dump_test "trunc"
if !$aout { run_dump_test "ulh" }
Index: include/opcode/ChangeLog
===================================================================
RCS file: /cvs/src/src/include/opcode/ChangeLog,v
retrieving revision 1.167
diff -u -p -r1.167 ChangeLog
--- include/opcode/ChangeLog 17 May 2002 19:01:03 -0000 1.167
+++ include/opcode/ChangeLog 21 May 2002 23:32:57 -0000
@@ -1,3 +1,7 @@
+2002-05-22 Thiemo Seufer <seufer@csv.ica.uni-stuttgart.de>
+
+ * mips.h: Add M_DROL, M_DROL_I, M_DROR, M_DROR_I macro cases.
+
2002-05-17 Andrey Volkov <avolkov@sources.redhat.com>
* h8300.h: Corrected defs of all control regs
Index: include/opcode/mips.h
===================================================================
RCS file: /cvs/src/src/include/opcode/mips.h,v
retrieving revision 1.24
diff -u -p -r1.24 mips.h
--- include/opcode/mips.h 16 Mar 2002 03:09:18 -0000 1.24
+++ include/opcode/mips.h 21 May 2002 23:32:57 -0000
@@ -526,9 +526,13 @@ enum
M_REM_3I,
M_REMU_3,
M_REMU_3I,
+ M_DROL,
M_ROL,
+ M_DROL_I,
M_ROL_I,
+ M_DROR,
M_ROR,
+ M_DROR_I,
M_ROR_I,
M_S_DA,
M_S_DOB,
Index: opcodes/ChangeLog
===================================================================
RCS file: /cvs/src/src/opcodes/ChangeLog,v
retrieving revision 1.447
diff -u -p -r1.447 ChangeLog
--- opcodes/ChangeLog 17 May 2002 14:36:45 -0000 1.447
+++ opcodes/ChangeLog 21 May 2002 23:33:00 -0000
@@ -1,3 +1,7 @@
+2002-05-22 Thiemo Seufer <seufer@csv.ica.uni-stuttgart.de>
+
+ * mips-opc.c (mips_builtin_opcodes): Add drol, dror macros.
+
Fri May 17 14:26:44 2002 J"orn Rennecke <joern.rennecke@superh.com>
* disassemble.c (disassembler): Just use print_insn_sh for bfd_arch_sh.
Index: opcodes/mips-opc.c
===================================================================
RCS file: /cvs/src/src/opcodes/mips-opc.c,v
retrieving revision 1.32
diff -u -p -r1.32 mips-opc.c
--- opcodes/mips-opc.c 17 Mar 2002 02:42:25 -0000 1.32
+++ opcodes/mips-opc.c 21 May 2002 23:33:00 -0000
@@ -492,6 +492,10 @@ const struct mips_opcode mips_builtin_op
{"dremu", "z,s,t", 0x0000001f, 0xfc00ffff, RD_s|RD_t|WR_HILO, I3 },
{"dremu", "d,v,t", 3, (int) M_DREMU_3, INSN_MACRO, I3 },
{"dremu", "d,v,I", 3, (int) M_DREMU_3I, INSN_MACRO, I3 },
+{"drol", "d,v,t", 0, (int) M_DROL, INSN_MACRO, I3 },
+{"drol", "d,v,I", 0, (int) M_DROL_I, INSN_MACRO, I3 },
+{"dror", "d,v,t", 0, (int) M_DROR, INSN_MACRO, I3 },
+{"dror", "d,v,I", 0, (int) M_DROR_I, INSN_MACRO, I3 },
{"dsllv", "d,t,s", 0x00000014, 0xfc0007ff, WR_d|RD_t|RD_s, I3 },
{"dsll32", "d,w,<", 0x0000003c, 0xffe0003f, WR_d|RD_t, I3 },
{"dsll", "d,w,s", 0x00000014, 0xfc0007ff, WR_d|RD_t|RD_s, I3 }, /* dsllv */
2002-05-22 01:54:48 +02:00
|
|
|
|
}
|
|
|
|
|
break;
|
|
|
|
|
|
1999-05-03 09:29:11 +02:00
|
|
|
|
case M_ROR_I:
|
? gas/testsuite/gas/mips/rol64.d
? gas/testsuite/gas/mips/rol64.s
Index: gas/ChangeLog
===================================================================
RCS file: /cvs/src/src/gas/ChangeLog,v
retrieving revision 1.1334
diff -u -p -r1.1334 ChangeLog
--- gas/ChangeLog 21 May 2002 20:01:51 -0000 1.1334
+++ gas/ChangeLog 21 May 2002 23:32:51 -0000
@@ -1,3 +1,8 @@
+2002-05-22 Thiemo Seufer <seufer@csv.ica.uni-stuttgart.de>
+
+ * config/tc-mips.c (macro2): Add 64 bit drol, dror macros.
+ Optimize the rotate by zero case.
+
2002-05-21 Nick Clifton <nickc@cambridge.redhat.com>
* configure.in: Remove accidental enabling of bfd_gas=yes for
Index: gas/config/tc-mips.c
===================================================================
RCS file: /cvs/src/src/gas/config/tc-mips.c,v
retrieving revision 1.123
diff -u -p -r1.123 tc-mips.c
--- gas/config/tc-mips.c 14 May 2002 23:35:59 -0000 1.123
+++ gas/config/tc-mips.c 21 May 2002 23:32:52 -0000
@@ -6686,6 +6686,17 @@ macro2 (ip)
--mips_opts.noreorder;
break;
+ case M_DROL:
+ macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "dsubu",
+ "d,v,t", AT, 0, treg);
+ macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "dsrlv",
+ "d,t,s", AT, sreg, AT);
+ macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "dsllv",
+ "d,t,s", dreg, sreg, treg);
+ macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "or",
+ "d,v,t", dreg, dreg, AT);
+ break;
+
case M_ROL:
macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "subu",
"d,v,t", AT, 0, treg);
@@ -6697,15 +6708,55 @@ macro2 (ip)
"d,v,t", dreg, dreg, AT);
break;
+ case M_DROL_I:
+ {
+ unsigned int rot;
+ char *l, *r;
+
+ if (imm_expr.X_op != O_constant)
+ as_bad (_("rotate count too large"));
+ rot = imm_expr.X_add_number & 0x3f;
+ if (! rot)
+ break;
+ l = (rot < 0x20) ? "dsll" : "dsll32";
+ r = ((0x40 - rot) < 0x20) ? "dsrl" : "dsrl32";
+ rot &= 0x1f;
+ macro_build ((char *) NULL, &icnt, (expressionS *) NULL, l,
+ "d,w,<", AT, sreg, rot);
+ macro_build ((char *) NULL, &icnt, (expressionS *) NULL, r,
+ "d,w,<", dreg, sreg, (0x20 - rot) & 0x1f);
+ macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "or",
+ "d,v,t", dreg, dreg, AT);
+ }
+ break;
+
case M_ROL_I:
- if (imm_expr.X_op != O_constant)
- as_bad (_("rotate count too large"));
- macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "sll", "d,w,<",
- AT, sreg, (int) (imm_expr.X_add_number & 0x1f));
- macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "srl", "d,w,<",
- dreg, sreg, (int) ((0 - imm_expr.X_add_number) & 0x1f));
- macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "or", "d,v,t",
- dreg, dreg, AT);
+ {
+ unsigned int rot;
+
+ if (imm_expr.X_op != O_constant)
+ as_bad (_("rotate count too large"));
+ rot = imm_expr.X_add_number & 0x1f;
+ if (! rot)
+ break;
+ macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "sll",
+ "d,w,<", AT, sreg, rot);
+ macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "srl",
+ "d,w,<", dreg, sreg, (0x20 - rot) & 0x1f);
+ macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "or",
+ "d,v,t", dreg, dreg, AT);
+ }
+ break;
+
+ case M_DROR:
+ macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "dsubu",
+ "d,v,t", AT, 0, treg);
+ macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "dsllv",
+ "d,t,s", AT, sreg, AT);
+ macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "dsrlv",
+ "d,t,s", dreg, sreg, treg);
+ macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "or",
+ "d,v,t", dreg, dreg, AT);
break;
case M_ROR:
@@ -6719,15 +6770,44 @@ macro2 (ip)
"d,v,t", dreg, dreg, AT);
break;
+ case M_DROR_I:
+ {
+ unsigned int rot;
+ char *l, *r;
+
+ if (imm_expr.X_op != O_constant)
+ as_bad (_("rotate count too large"));
+ rot = imm_expr.X_add_number & 0x3f;
+ if (! rot)
+ break;
+ r = (rot < 0x20) ? "dsrl" : "dsrl32";
+ l = ((0x40 - rot) < 0x20) ? "dsll" : "dsll32";
+ rot &= 0x1f;
+ macro_build ((char *) NULL, &icnt, (expressionS *) NULL, r,
+ "d,w,<", AT, sreg, rot);
+ macro_build ((char *) NULL, &icnt, (expressionS *) NULL, l,
+ "d,w,<", dreg, sreg, (0x20 - rot) & 0x1f);
+ macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "or",
+ "d,v,t", dreg, dreg, AT);
+ }
+ break;
+
case M_ROR_I:
- if (imm_expr.X_op != O_constant)
- as_bad (_("rotate count too large"));
- macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "srl", "d,w,<",
- AT, sreg, (int) (imm_expr.X_add_number & 0x1f));
- macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "sll", "d,w,<",
- dreg, sreg, (int) ((0 - imm_expr.X_add_number) & 0x1f));
- macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "or", "d,v,t",
- dreg, dreg, AT);
+ {
+ unsigned int rot;
+
+ if (imm_expr.X_op != O_constant)
+ as_bad (_("rotate count too large"));
+ rot = imm_expr.X_add_number & 0x1f;
+ if (! rot)
+ break;
+ macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "srl",
+ "d,w,<", AT, sreg, rot);
+ macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "sll",
+ "d,w,<", dreg, sreg, (0x20 - rot) & 0x1f);
+ macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "or",
+ "d,v,t", dreg, dreg, AT);
+ }
break;
case M_S_DOB:
Index: gas/testsuite/ChangeLog
===================================================================
RCS file: /cvs/src/src/gas/testsuite/ChangeLog,v
retrieving revision 1.315
diff -u -p -r1.315 ChangeLog
--- gas/testsuite/ChangeLog 20 May 2002 17:05:34 -0000 1.315
+++ gas/testsuite/ChangeLog 21 May 2002 23:32:54 -0000
@@ -1,3 +1,9 @@
+2002-05-22 Thiemo Seufer <seufer@csv.ica.uni-stuttgart.de>
+
+ * gas/mips/rol64.s: New file, test of drol, dror macros.
+ * gas/mips/rol64.d: Likewise.
+ * gas/mips/mips.exp: Add new test.
+
2002-05-20 Nick Clifton <nickc@cambridge.redhat.com>
* gas/arm/arm.exp: Replace deprecated command line switches
Index: gas/testsuite/gas/mips/mips.exp
===================================================================
RCS file: /cvs/src/src/gas/testsuite/gas/mips/mips.exp,v
retrieving revision 1.32
diff -u -p -r1.32 mips.exp
--- gas/testsuite/gas/mips/mips.exp 4 Apr 2002 08:23:30 -0000 1.32
+++ gas/testsuite/gas/mips/mips.exp 21 May 2002 23:32:54 -0000
@@ -122,6 +122,7 @@ if { [istarget mips*-*-*] } then {
run_dump_test "mul"
}
run_dump_test "rol"
+ run_dump_test "rol64"
if !$aout { run_dump_test "sb" }
run_dump_test "trunc"
if !$aout { run_dump_test "ulh" }
Index: include/opcode/ChangeLog
===================================================================
RCS file: /cvs/src/src/include/opcode/ChangeLog,v
retrieving revision 1.167
diff -u -p -r1.167 ChangeLog
--- include/opcode/ChangeLog 17 May 2002 19:01:03 -0000 1.167
+++ include/opcode/ChangeLog 21 May 2002 23:32:57 -0000
@@ -1,3 +1,7 @@
+2002-05-22 Thiemo Seufer <seufer@csv.ica.uni-stuttgart.de>
+
+ * mips.h: Add M_DROL, M_DROL_I, M_DROR, M_DROR_I macro cases.
+
2002-05-17 Andrey Volkov <avolkov@sources.redhat.com>
* h8300.h: Corrected defs of all control regs
Index: include/opcode/mips.h
===================================================================
RCS file: /cvs/src/src/include/opcode/mips.h,v
retrieving revision 1.24
diff -u -p -r1.24 mips.h
--- include/opcode/mips.h 16 Mar 2002 03:09:18 -0000 1.24
+++ include/opcode/mips.h 21 May 2002 23:32:57 -0000
@@ -526,9 +526,13 @@ enum
M_REM_3I,
M_REMU_3,
M_REMU_3I,
+ M_DROL,
M_ROL,
+ M_DROL_I,
M_ROL_I,
+ M_DROR,
M_ROR,
+ M_DROR_I,
M_ROR_I,
M_S_DA,
M_S_DOB,
Index: opcodes/ChangeLog
===================================================================
RCS file: /cvs/src/src/opcodes/ChangeLog,v
retrieving revision 1.447
diff -u -p -r1.447 ChangeLog
--- opcodes/ChangeLog 17 May 2002 14:36:45 -0000 1.447
+++ opcodes/ChangeLog 21 May 2002 23:33:00 -0000
@@ -1,3 +1,7 @@
+2002-05-22 Thiemo Seufer <seufer@csv.ica.uni-stuttgart.de>
+
+ * mips-opc.c (mips_builtin_opcodes): Add drol, dror macros.
+
Fri May 17 14:26:44 2002 J"orn Rennecke <joern.rennecke@superh.com>
* disassemble.c (disassembler): Just use print_insn_sh for bfd_arch_sh.
Index: opcodes/mips-opc.c
===================================================================
RCS file: /cvs/src/src/opcodes/mips-opc.c,v
retrieving revision 1.32
diff -u -p -r1.32 mips-opc.c
--- opcodes/mips-opc.c 17 Mar 2002 02:42:25 -0000 1.32
+++ opcodes/mips-opc.c 21 May 2002 23:33:00 -0000
@@ -492,6 +492,10 @@ const struct mips_opcode mips_builtin_op
{"dremu", "z,s,t", 0x0000001f, 0xfc00ffff, RD_s|RD_t|WR_HILO, I3 },
{"dremu", "d,v,t", 3, (int) M_DREMU_3, INSN_MACRO, I3 },
{"dremu", "d,v,I", 3, (int) M_DREMU_3I, INSN_MACRO, I3 },
+{"drol", "d,v,t", 0, (int) M_DROL, INSN_MACRO, I3 },
+{"drol", "d,v,I", 0, (int) M_DROL_I, INSN_MACRO, I3 },
+{"dror", "d,v,t", 0, (int) M_DROR, INSN_MACRO, I3 },
+{"dror", "d,v,I", 0, (int) M_DROR_I, INSN_MACRO, I3 },
{"dsllv", "d,t,s", 0x00000014, 0xfc0007ff, WR_d|RD_t|RD_s, I3 },
{"dsll32", "d,w,<", 0x0000003c, 0xffe0003f, WR_d|RD_t, I3 },
{"dsll", "d,w,s", 0x00000014, 0xfc0007ff, WR_d|RD_t|RD_s, I3 }, /* dsllv */
2002-05-22 01:54:48 +02:00
|
|
|
|
{
|
|
|
|
|
unsigned int rot;
|
|
|
|
|
|
|
|
|
|
if (imm_expr.X_op != O_constant)
|
[ opcodes/ChangeLog ]
2002-12-18 Chris Demetriou <cgd@broadcom.com>
* mips-opc.c (mips_builtin_opcodes): Remove one "ror" and two
"dror" entries, and reorder the remaining "dror" and "ror" entries.
[ gas/ChangeLog ]
2002-12-18 Chris Demetriou <cgd@broadcom.com>
* config/tc-mips.c (macro): In M_DROL, M_DROR, M_ROL, and M_ROR,
use hardware rotate ops as appropriate. In M_DROL_I, M_DROR_I,
M_ROL_I, and M_ROR_I, simplify code, clean up warnings, and
arrange not to issue warnings about use of AT when AT is not
actually used.
[ gas/testsuite/ChangeLog ]
2002-12-18 Chris Demetriou <cgd@broadcom.com>
* gas/mips/rol.s: Add ".set noat" and some new instructions to test.
* gas/mips/rol64.s: Likewise.
* gas/mips/rol.l: New file.
* gas/mips/rol.d: Adjust to use rol.l and for rol.s changes.
* gas/mips/rol64.l: New file.
* gas/mips/rol64.d: Adjust to use rol64.l and for rol64.s changes.
* gas/mips/rol-hw.d: New file.
* gas/mips/rol-hw.l: New file.
* gas/mips/rol64-hw.d: New file.
* gas/mips/rol64-hw.l: New file.
* gas/mips/mips.exp: Run rol-hw and rol64-hw tests.
2002-12-18 23:52:48 +01:00
|
|
|
|
as_bad (_("Improper rotate count"));
|
? gas/testsuite/gas/mips/rol64.d
? gas/testsuite/gas/mips/rol64.s
Index: gas/ChangeLog
===================================================================
RCS file: /cvs/src/src/gas/ChangeLog,v
retrieving revision 1.1334
diff -u -p -r1.1334 ChangeLog
--- gas/ChangeLog 21 May 2002 20:01:51 -0000 1.1334
+++ gas/ChangeLog 21 May 2002 23:32:51 -0000
@@ -1,3 +1,8 @@
+2002-05-22 Thiemo Seufer <seufer@csv.ica.uni-stuttgart.de>
+
+ * config/tc-mips.c (macro2): Add 64 bit drol, dror macros.
+ Optimize the rotate by zero case.
+
2002-05-21 Nick Clifton <nickc@cambridge.redhat.com>
* configure.in: Remove accidental enabling of bfd_gas=yes for
Index: gas/config/tc-mips.c
===================================================================
RCS file: /cvs/src/src/gas/config/tc-mips.c,v
retrieving revision 1.123
diff -u -p -r1.123 tc-mips.c
--- gas/config/tc-mips.c 14 May 2002 23:35:59 -0000 1.123
+++ gas/config/tc-mips.c 21 May 2002 23:32:52 -0000
@@ -6686,6 +6686,17 @@ macro2 (ip)
--mips_opts.noreorder;
break;
+ case M_DROL:
+ macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "dsubu",
+ "d,v,t", AT, 0, treg);
+ macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "dsrlv",
+ "d,t,s", AT, sreg, AT);
+ macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "dsllv",
+ "d,t,s", dreg, sreg, treg);
+ macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "or",
+ "d,v,t", dreg, dreg, AT);
+ break;
+
case M_ROL:
macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "subu",
"d,v,t", AT, 0, treg);
@@ -6697,15 +6708,55 @@ macro2 (ip)
"d,v,t", dreg, dreg, AT);
break;
+ case M_DROL_I:
+ {
+ unsigned int rot;
+ char *l, *r;
+
+ if (imm_expr.X_op != O_constant)
+ as_bad (_("rotate count too large"));
+ rot = imm_expr.X_add_number & 0x3f;
+ if (! rot)
+ break;
+ l = (rot < 0x20) ? "dsll" : "dsll32";
+ r = ((0x40 - rot) < 0x20) ? "dsrl" : "dsrl32";
+ rot &= 0x1f;
+ macro_build ((char *) NULL, &icnt, (expressionS *) NULL, l,
+ "d,w,<", AT, sreg, rot);
+ macro_build ((char *) NULL, &icnt, (expressionS *) NULL, r,
+ "d,w,<", dreg, sreg, (0x20 - rot) & 0x1f);
+ macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "or",
+ "d,v,t", dreg, dreg, AT);
+ }
+ break;
+
case M_ROL_I:
- if (imm_expr.X_op != O_constant)
- as_bad (_("rotate count too large"));
- macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "sll", "d,w,<",
- AT, sreg, (int) (imm_expr.X_add_number & 0x1f));
- macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "srl", "d,w,<",
- dreg, sreg, (int) ((0 - imm_expr.X_add_number) & 0x1f));
- macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "or", "d,v,t",
- dreg, dreg, AT);
+ {
+ unsigned int rot;
+
+ if (imm_expr.X_op != O_constant)
+ as_bad (_("rotate count too large"));
+ rot = imm_expr.X_add_number & 0x1f;
+ if (! rot)
+ break;
+ macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "sll",
+ "d,w,<", AT, sreg, rot);
+ macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "srl",
+ "d,w,<", dreg, sreg, (0x20 - rot) & 0x1f);
+ macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "or",
+ "d,v,t", dreg, dreg, AT);
+ }
+ break;
+
+ case M_DROR:
+ macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "dsubu",
+ "d,v,t", AT, 0, treg);
+ macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "dsllv",
+ "d,t,s", AT, sreg, AT);
+ macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "dsrlv",
+ "d,t,s", dreg, sreg, treg);
+ macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "or",
+ "d,v,t", dreg, dreg, AT);
break;
case M_ROR:
@@ -6719,15 +6770,44 @@ macro2 (ip)
"d,v,t", dreg, dreg, AT);
break;
+ case M_DROR_I:
+ {
+ unsigned int rot;
+ char *l, *r;
+
+ if (imm_expr.X_op != O_constant)
+ as_bad (_("rotate count too large"));
+ rot = imm_expr.X_add_number & 0x3f;
+ if (! rot)
+ break;
+ r = (rot < 0x20) ? "dsrl" : "dsrl32";
+ l = ((0x40 - rot) < 0x20) ? "dsll" : "dsll32";
+ rot &= 0x1f;
+ macro_build ((char *) NULL, &icnt, (expressionS *) NULL, r,
+ "d,w,<", AT, sreg, rot);
+ macro_build ((char *) NULL, &icnt, (expressionS *) NULL, l,
+ "d,w,<", dreg, sreg, (0x20 - rot) & 0x1f);
+ macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "or",
+ "d,v,t", dreg, dreg, AT);
+ }
+ break;
+
case M_ROR_I:
- if (imm_expr.X_op != O_constant)
- as_bad (_("rotate count too large"));
- macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "srl", "d,w,<",
- AT, sreg, (int) (imm_expr.X_add_number & 0x1f));
- macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "sll", "d,w,<",
- dreg, sreg, (int) ((0 - imm_expr.X_add_number) & 0x1f));
- macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "or", "d,v,t",
- dreg, dreg, AT);
+ {
+ unsigned int rot;
+
+ if (imm_expr.X_op != O_constant)
+ as_bad (_("rotate count too large"));
+ rot = imm_expr.X_add_number & 0x1f;
+ if (! rot)
+ break;
+ macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "srl",
+ "d,w,<", AT, sreg, rot);
+ macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "sll",
+ "d,w,<", dreg, sreg, (0x20 - rot) & 0x1f);
+ macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "or",
+ "d,v,t", dreg, dreg, AT);
+ }
break;
case M_S_DOB:
Index: gas/testsuite/ChangeLog
===================================================================
RCS file: /cvs/src/src/gas/testsuite/ChangeLog,v
retrieving revision 1.315
diff -u -p -r1.315 ChangeLog
--- gas/testsuite/ChangeLog 20 May 2002 17:05:34 -0000 1.315
+++ gas/testsuite/ChangeLog 21 May 2002 23:32:54 -0000
@@ -1,3 +1,9 @@
+2002-05-22 Thiemo Seufer <seufer@csv.ica.uni-stuttgart.de>
+
+ * gas/mips/rol64.s: New file, test of drol, dror macros.
+ * gas/mips/rol64.d: Likewise.
+ * gas/mips/mips.exp: Add new test.
+
2002-05-20 Nick Clifton <nickc@cambridge.redhat.com>
* gas/arm/arm.exp: Replace deprecated command line switches
Index: gas/testsuite/gas/mips/mips.exp
===================================================================
RCS file: /cvs/src/src/gas/testsuite/gas/mips/mips.exp,v
retrieving revision 1.32
diff -u -p -r1.32 mips.exp
--- gas/testsuite/gas/mips/mips.exp 4 Apr 2002 08:23:30 -0000 1.32
+++ gas/testsuite/gas/mips/mips.exp 21 May 2002 23:32:54 -0000
@@ -122,6 +122,7 @@ if { [istarget mips*-*-*] } then {
run_dump_test "mul"
}
run_dump_test "rol"
+ run_dump_test "rol64"
if !$aout { run_dump_test "sb" }
run_dump_test "trunc"
if !$aout { run_dump_test "ulh" }
Index: include/opcode/ChangeLog
===================================================================
RCS file: /cvs/src/src/include/opcode/ChangeLog,v
retrieving revision 1.167
diff -u -p -r1.167 ChangeLog
--- include/opcode/ChangeLog 17 May 2002 19:01:03 -0000 1.167
+++ include/opcode/ChangeLog 21 May 2002 23:32:57 -0000
@@ -1,3 +1,7 @@
+2002-05-22 Thiemo Seufer <seufer@csv.ica.uni-stuttgart.de>
+
+ * mips.h: Add M_DROL, M_DROL_I, M_DROR, M_DROR_I macro cases.
+
2002-05-17 Andrey Volkov <avolkov@sources.redhat.com>
* h8300.h: Corrected defs of all control regs
Index: include/opcode/mips.h
===================================================================
RCS file: /cvs/src/src/include/opcode/mips.h,v
retrieving revision 1.24
diff -u -p -r1.24 mips.h
--- include/opcode/mips.h 16 Mar 2002 03:09:18 -0000 1.24
+++ include/opcode/mips.h 21 May 2002 23:32:57 -0000
@@ -526,9 +526,13 @@ enum
M_REM_3I,
M_REMU_3,
M_REMU_3I,
+ M_DROL,
M_ROL,
+ M_DROL_I,
M_ROL_I,
+ M_DROR,
M_ROR,
+ M_DROR_I,
M_ROR_I,
M_S_DA,
M_S_DOB,
Index: opcodes/ChangeLog
===================================================================
RCS file: /cvs/src/src/opcodes/ChangeLog,v
retrieving revision 1.447
diff -u -p -r1.447 ChangeLog
--- opcodes/ChangeLog 17 May 2002 14:36:45 -0000 1.447
+++ opcodes/ChangeLog 21 May 2002 23:33:00 -0000
@@ -1,3 +1,7 @@
+2002-05-22 Thiemo Seufer <seufer@csv.ica.uni-stuttgart.de>
+
+ * mips-opc.c (mips_builtin_opcodes): Add drol, dror macros.
+
Fri May 17 14:26:44 2002 J"orn Rennecke <joern.rennecke@superh.com>
* disassemble.c (disassembler): Just use print_insn_sh for bfd_arch_sh.
Index: opcodes/mips-opc.c
===================================================================
RCS file: /cvs/src/src/opcodes/mips-opc.c,v
retrieving revision 1.32
diff -u -p -r1.32 mips-opc.c
--- opcodes/mips-opc.c 17 Mar 2002 02:42:25 -0000 1.32
+++ opcodes/mips-opc.c 21 May 2002 23:33:00 -0000
@@ -492,6 +492,10 @@ const struct mips_opcode mips_builtin_op
{"dremu", "z,s,t", 0x0000001f, 0xfc00ffff, RD_s|RD_t|WR_HILO, I3 },
{"dremu", "d,v,t", 3, (int) M_DREMU_3, INSN_MACRO, I3 },
{"dremu", "d,v,I", 3, (int) M_DREMU_3I, INSN_MACRO, I3 },
+{"drol", "d,v,t", 0, (int) M_DROL, INSN_MACRO, I3 },
+{"drol", "d,v,I", 0, (int) M_DROL_I, INSN_MACRO, I3 },
+{"dror", "d,v,t", 0, (int) M_DROR, INSN_MACRO, I3 },
+{"dror", "d,v,I", 0, (int) M_DROR_I, INSN_MACRO, I3 },
{"dsllv", "d,t,s", 0x00000014, 0xfc0007ff, WR_d|RD_t|RD_s, I3 },
{"dsll32", "d,w,<", 0x0000003c, 0xffe0003f, WR_d|RD_t, I3 },
{"dsll", "d,w,s", 0x00000014, 0xfc0007ff, WR_d|RD_t|RD_s, I3 }, /* dsllv */
2002-05-22 01:54:48 +02:00
|
|
|
|
rot = imm_expr.X_add_number & 0x1f;
|
2003-06-29 21:41:33 +02:00
|
|
|
|
if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch))
|
[ opcodes/ChangeLog ]
2002-12-18 Chris Demetriou <cgd@broadcom.com>
* mips-opc.c (mips_builtin_opcodes): Remove one "ror" and two
"dror" entries, and reorder the remaining "dror" and "ror" entries.
[ gas/ChangeLog ]
2002-12-18 Chris Demetriou <cgd@broadcom.com>
* config/tc-mips.c (macro): In M_DROL, M_DROR, M_ROL, and M_ROR,
use hardware rotate ops as appropriate. In M_DROL_I, M_DROR_I,
M_ROL_I, and M_ROR_I, simplify code, clean up warnings, and
arrange not to issue warnings about use of AT when AT is not
actually used.
[ gas/testsuite/ChangeLog ]
2002-12-18 Chris Demetriou <cgd@broadcom.com>
* gas/mips/rol.s: Add ".set noat" and some new instructions to test.
* gas/mips/rol64.s: Likewise.
* gas/mips/rol.l: New file.
* gas/mips/rol.d: Adjust to use rol.l and for rol.s changes.
* gas/mips/rol64.l: New file.
* gas/mips/rol64.d: Adjust to use rol64.l and for rol64.s changes.
* gas/mips/rol-hw.d: New file.
* gas/mips/rol-hw.l: New file.
* gas/mips/rol64-hw.d: New file.
* gas/mips/rol64-hw.l: New file.
* gas/mips/mips.exp: Run rol-hw and rol64-hw tests.
2002-12-18 23:52:48 +01:00
|
|
|
|
{
|
2003-06-30 14:44:25 +02:00
|
|
|
|
macro_build (NULL, &icnt, NULL, "ror", "d,w,<", dreg, sreg, rot);
|
[ opcodes/ChangeLog ]
2002-12-18 Chris Demetriou <cgd@broadcom.com>
* mips-opc.c (mips_builtin_opcodes): Remove one "ror" and two
"dror" entries, and reorder the remaining "dror" and "ror" entries.
[ gas/ChangeLog ]
2002-12-18 Chris Demetriou <cgd@broadcom.com>
* config/tc-mips.c (macro): In M_DROL, M_DROR, M_ROL, and M_ROR,
use hardware rotate ops as appropriate. In M_DROL_I, M_DROR_I,
M_ROL_I, and M_ROR_I, simplify code, clean up warnings, and
arrange not to issue warnings about use of AT when AT is not
actually used.
[ gas/testsuite/ChangeLog ]
2002-12-18 Chris Demetriou <cgd@broadcom.com>
* gas/mips/rol.s: Add ".set noat" and some new instructions to test.
* gas/mips/rol64.s: Likewise.
* gas/mips/rol.l: New file.
* gas/mips/rol.d: Adjust to use rol.l and for rol.s changes.
* gas/mips/rol64.l: New file.
* gas/mips/rol64.d: Adjust to use rol64.l and for rol64.s changes.
* gas/mips/rol-hw.d: New file.
* gas/mips/rol-hw.l: New file.
* gas/mips/rol64-hw.d: New file.
* gas/mips/rol64-hw.l: New file.
* gas/mips/mips.exp: Run rol-hw and rol64-hw tests.
2002-12-18 23:52:48 +01:00
|
|
|
|
return;
|
|
|
|
|
}
|
2002-08-20 10:28:35 +02:00
|
|
|
|
if (rot == 0)
|
|
|
|
|
{
|
2003-06-30 14:44:25 +02:00
|
|
|
|
macro_build (NULL, &icnt, NULL, "srl", "d,w,<", dreg, sreg, 0);
|
[ opcodes/ChangeLog ]
2002-12-18 Chris Demetriou <cgd@broadcom.com>
* mips-opc.c (mips_builtin_opcodes): Remove one "ror" and two
"dror" entries, and reorder the remaining "dror" and "ror" entries.
[ gas/ChangeLog ]
2002-12-18 Chris Demetriou <cgd@broadcom.com>
* config/tc-mips.c (macro): In M_DROL, M_DROR, M_ROL, and M_ROR,
use hardware rotate ops as appropriate. In M_DROL_I, M_DROR_I,
M_ROL_I, and M_ROR_I, simplify code, clean up warnings, and
arrange not to issue warnings about use of AT when AT is not
actually used.
[ gas/testsuite/ChangeLog ]
2002-12-18 Chris Demetriou <cgd@broadcom.com>
* gas/mips/rol.s: Add ".set noat" and some new instructions to test.
* gas/mips/rol64.s: Likewise.
* gas/mips/rol.l: New file.
* gas/mips/rol.d: Adjust to use rol.l and for rol.s changes.
* gas/mips/rol64.l: New file.
* gas/mips/rol64.d: Adjust to use rol64.l and for rol64.s changes.
* gas/mips/rol-hw.d: New file.
* gas/mips/rol-hw.l: New file.
* gas/mips/rol64-hw.d: New file.
* gas/mips/rol64-hw.l: New file.
* gas/mips/mips.exp: Run rol-hw and rol64-hw tests.
2002-12-18 23:52:48 +01:00
|
|
|
|
return;
|
2002-08-20 10:28:35 +02:00
|
|
|
|
}
|
2003-06-30 14:44:25 +02:00
|
|
|
|
macro_build (NULL, &icnt, NULL, "srl", "d,w,<", AT, sreg, rot);
|
|
|
|
|
macro_build (NULL, &icnt, NULL, "sll", "d,w,<", dreg, sreg,
|
|
|
|
|
(0x20 - rot) & 0x1f);
|
|
|
|
|
macro_build (NULL, &icnt, NULL, "or", "d,v,t", dreg, dreg, AT);
|
? gas/testsuite/gas/mips/rol64.d
? gas/testsuite/gas/mips/rol64.s
Index: gas/ChangeLog
===================================================================
RCS file: /cvs/src/src/gas/ChangeLog,v
retrieving revision 1.1334
diff -u -p -r1.1334 ChangeLog
--- gas/ChangeLog 21 May 2002 20:01:51 -0000 1.1334
+++ gas/ChangeLog 21 May 2002 23:32:51 -0000
@@ -1,3 +1,8 @@
+2002-05-22 Thiemo Seufer <seufer@csv.ica.uni-stuttgart.de>
+
+ * config/tc-mips.c (macro2): Add 64 bit drol, dror macros.
+ Optimize the rotate by zero case.
+
2002-05-21 Nick Clifton <nickc@cambridge.redhat.com>
* configure.in: Remove accidental enabling of bfd_gas=yes for
Index: gas/config/tc-mips.c
===================================================================
RCS file: /cvs/src/src/gas/config/tc-mips.c,v
retrieving revision 1.123
diff -u -p -r1.123 tc-mips.c
--- gas/config/tc-mips.c 14 May 2002 23:35:59 -0000 1.123
+++ gas/config/tc-mips.c 21 May 2002 23:32:52 -0000
@@ -6686,6 +6686,17 @@ macro2 (ip)
--mips_opts.noreorder;
break;
+ case M_DROL:
+ macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "dsubu",
+ "d,v,t", AT, 0, treg);
+ macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "dsrlv",
+ "d,t,s", AT, sreg, AT);
+ macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "dsllv",
+ "d,t,s", dreg, sreg, treg);
+ macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "or",
+ "d,v,t", dreg, dreg, AT);
+ break;
+
case M_ROL:
macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "subu",
"d,v,t", AT, 0, treg);
@@ -6697,15 +6708,55 @@ macro2 (ip)
"d,v,t", dreg, dreg, AT);
break;
+ case M_DROL_I:
+ {
+ unsigned int rot;
+ char *l, *r;
+
+ if (imm_expr.X_op != O_constant)
+ as_bad (_("rotate count too large"));
+ rot = imm_expr.X_add_number & 0x3f;
+ if (! rot)
+ break;
+ l = (rot < 0x20) ? "dsll" : "dsll32";
+ r = ((0x40 - rot) < 0x20) ? "dsrl" : "dsrl32";
+ rot &= 0x1f;
+ macro_build ((char *) NULL, &icnt, (expressionS *) NULL, l,
+ "d,w,<", AT, sreg, rot);
+ macro_build ((char *) NULL, &icnt, (expressionS *) NULL, r,
+ "d,w,<", dreg, sreg, (0x20 - rot) & 0x1f);
+ macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "or",
+ "d,v,t", dreg, dreg, AT);
+ }
+ break;
+
case M_ROL_I:
- if (imm_expr.X_op != O_constant)
- as_bad (_("rotate count too large"));
- macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "sll", "d,w,<",
- AT, sreg, (int) (imm_expr.X_add_number & 0x1f));
- macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "srl", "d,w,<",
- dreg, sreg, (int) ((0 - imm_expr.X_add_number) & 0x1f));
- macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "or", "d,v,t",
- dreg, dreg, AT);
+ {
+ unsigned int rot;
+
+ if (imm_expr.X_op != O_constant)
+ as_bad (_("rotate count too large"));
+ rot = imm_expr.X_add_number & 0x1f;
+ if (! rot)
+ break;
+ macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "sll",
+ "d,w,<", AT, sreg, rot);
+ macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "srl",
+ "d,w,<", dreg, sreg, (0x20 - rot) & 0x1f);
+ macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "or",
+ "d,v,t", dreg, dreg, AT);
+ }
+ break;
+
+ case M_DROR:
+ macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "dsubu",
+ "d,v,t", AT, 0, treg);
+ macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "dsllv",
+ "d,t,s", AT, sreg, AT);
+ macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "dsrlv",
+ "d,t,s", dreg, sreg, treg);
+ macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "or",
+ "d,v,t", dreg, dreg, AT);
break;
case M_ROR:
@@ -6719,15 +6770,44 @@ macro2 (ip)
"d,v,t", dreg, dreg, AT);
break;
+ case M_DROR_I:
+ {
+ unsigned int rot;
+ char *l, *r;
+
+ if (imm_expr.X_op != O_constant)
+ as_bad (_("rotate count too large"));
+ rot = imm_expr.X_add_number & 0x3f;
+ if (! rot)
+ break;
+ r = (rot < 0x20) ? "dsrl" : "dsrl32";
+ l = ((0x40 - rot) < 0x20) ? "dsll" : "dsll32";
+ rot &= 0x1f;
+ macro_build ((char *) NULL, &icnt, (expressionS *) NULL, r,
+ "d,w,<", AT, sreg, rot);
+ macro_build ((char *) NULL, &icnt, (expressionS *) NULL, l,
+ "d,w,<", dreg, sreg, (0x20 - rot) & 0x1f);
+ macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "or",
+ "d,v,t", dreg, dreg, AT);
+ }
+ break;
+
case M_ROR_I:
- if (imm_expr.X_op != O_constant)
- as_bad (_("rotate count too large"));
- macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "srl", "d,w,<",
- AT, sreg, (int) (imm_expr.X_add_number & 0x1f));
- macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "sll", "d,w,<",
- dreg, sreg, (int) ((0 - imm_expr.X_add_number) & 0x1f));
- macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "or", "d,v,t",
- dreg, dreg, AT);
+ {
+ unsigned int rot;
+
+ if (imm_expr.X_op != O_constant)
+ as_bad (_("rotate count too large"));
+ rot = imm_expr.X_add_number & 0x1f;
+ if (! rot)
+ break;
+ macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "srl",
+ "d,w,<", AT, sreg, rot);
+ macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "sll",
+ "d,w,<", dreg, sreg, (0x20 - rot) & 0x1f);
+ macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "or",
+ "d,v,t", dreg, dreg, AT);
+ }
break;
case M_S_DOB:
Index: gas/testsuite/ChangeLog
===================================================================
RCS file: /cvs/src/src/gas/testsuite/ChangeLog,v
retrieving revision 1.315
diff -u -p -r1.315 ChangeLog
--- gas/testsuite/ChangeLog 20 May 2002 17:05:34 -0000 1.315
+++ gas/testsuite/ChangeLog 21 May 2002 23:32:54 -0000
@@ -1,3 +1,9 @@
+2002-05-22 Thiemo Seufer <seufer@csv.ica.uni-stuttgart.de>
+
+ * gas/mips/rol64.s: New file, test of drol, dror macros.
+ * gas/mips/rol64.d: Likewise.
+ * gas/mips/mips.exp: Add new test.
+
2002-05-20 Nick Clifton <nickc@cambridge.redhat.com>
* gas/arm/arm.exp: Replace deprecated command line switches
Index: gas/testsuite/gas/mips/mips.exp
===================================================================
RCS file: /cvs/src/src/gas/testsuite/gas/mips/mips.exp,v
retrieving revision 1.32
diff -u -p -r1.32 mips.exp
--- gas/testsuite/gas/mips/mips.exp 4 Apr 2002 08:23:30 -0000 1.32
+++ gas/testsuite/gas/mips/mips.exp 21 May 2002 23:32:54 -0000
@@ -122,6 +122,7 @@ if { [istarget mips*-*-*] } then {
run_dump_test "mul"
}
run_dump_test "rol"
+ run_dump_test "rol64"
if !$aout { run_dump_test "sb" }
run_dump_test "trunc"
if !$aout { run_dump_test "ulh" }
Index: include/opcode/ChangeLog
===================================================================
RCS file: /cvs/src/src/include/opcode/ChangeLog,v
retrieving revision 1.167
diff -u -p -r1.167 ChangeLog
--- include/opcode/ChangeLog 17 May 2002 19:01:03 -0000 1.167
+++ include/opcode/ChangeLog 21 May 2002 23:32:57 -0000
@@ -1,3 +1,7 @@
+2002-05-22 Thiemo Seufer <seufer@csv.ica.uni-stuttgart.de>
+
+ * mips.h: Add M_DROL, M_DROL_I, M_DROR, M_DROR_I macro cases.
+
2002-05-17 Andrey Volkov <avolkov@sources.redhat.com>
* h8300.h: Corrected defs of all control regs
Index: include/opcode/mips.h
===================================================================
RCS file: /cvs/src/src/include/opcode/mips.h,v
retrieving revision 1.24
diff -u -p -r1.24 mips.h
--- include/opcode/mips.h 16 Mar 2002 03:09:18 -0000 1.24
+++ include/opcode/mips.h 21 May 2002 23:32:57 -0000
@@ -526,9 +526,13 @@ enum
M_REM_3I,
M_REMU_3,
M_REMU_3I,
+ M_DROL,
M_ROL,
+ M_DROL_I,
M_ROL_I,
+ M_DROR,
M_ROR,
+ M_DROR_I,
M_ROR_I,
M_S_DA,
M_S_DOB,
Index: opcodes/ChangeLog
===================================================================
RCS file: /cvs/src/src/opcodes/ChangeLog,v
retrieving revision 1.447
diff -u -p -r1.447 ChangeLog
--- opcodes/ChangeLog 17 May 2002 14:36:45 -0000 1.447
+++ opcodes/ChangeLog 21 May 2002 23:33:00 -0000
@@ -1,3 +1,7 @@
+2002-05-22 Thiemo Seufer <seufer@csv.ica.uni-stuttgart.de>
+
+ * mips-opc.c (mips_builtin_opcodes): Add drol, dror macros.
+
Fri May 17 14:26:44 2002 J"orn Rennecke <joern.rennecke@superh.com>
* disassemble.c (disassembler): Just use print_insn_sh for bfd_arch_sh.
Index: opcodes/mips-opc.c
===================================================================
RCS file: /cvs/src/src/opcodes/mips-opc.c,v
retrieving revision 1.32
diff -u -p -r1.32 mips-opc.c
--- opcodes/mips-opc.c 17 Mar 2002 02:42:25 -0000 1.32
+++ opcodes/mips-opc.c 21 May 2002 23:33:00 -0000
@@ -492,6 +492,10 @@ const struct mips_opcode mips_builtin_op
{"dremu", "z,s,t", 0x0000001f, 0xfc00ffff, RD_s|RD_t|WR_HILO, I3 },
{"dremu", "d,v,t", 3, (int) M_DREMU_3, INSN_MACRO, I3 },
{"dremu", "d,v,I", 3, (int) M_DREMU_3I, INSN_MACRO, I3 },
+{"drol", "d,v,t", 0, (int) M_DROL, INSN_MACRO, I3 },
+{"drol", "d,v,I", 0, (int) M_DROL_I, INSN_MACRO, I3 },
+{"dror", "d,v,t", 0, (int) M_DROR, INSN_MACRO, I3 },
+{"dror", "d,v,I", 0, (int) M_DROR_I, INSN_MACRO, I3 },
{"dsllv", "d,t,s", 0x00000014, 0xfc0007ff, WR_d|RD_t|RD_s, I3 },
{"dsll32", "d,w,<", 0x0000003c, 0xffe0003f, WR_d|RD_t, I3 },
{"dsll", "d,w,s", 0x00000014, 0xfc0007ff, WR_d|RD_t|RD_s, I3 }, /* dsllv */
2002-05-22 01:54:48 +02:00
|
|
|
|
}
|
1999-05-03 09:29:11 +02:00
|
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
case M_S_DOB:
|
2003-06-29 21:41:33 +02:00
|
|
|
|
if (mips_opts.arch == CPU_R4650)
|
1999-05-03 09:29:11 +02:00
|
|
|
|
{
|
|
|
|
|
as_bad (_("opcode not supported on this processor"));
|
|
|
|
|
return;
|
|
|
|
|
}
|
2000-12-01 22:35:38 +01:00
|
|
|
|
assert (mips_opts.isa == ISA_MIPS1);
|
1999-05-03 09:29:11 +02:00
|
|
|
|
/* Even on a big endian machine $fn comes before $fn+1. We have
|
|
|
|
|
to adjust when storing to memory. */
|
2003-06-30 14:44:25 +02:00
|
|
|
|
macro_build (NULL, &icnt, &offset_expr, "swc1", "T,o(b)",
|
1999-05-03 09:29:11 +02:00
|
|
|
|
target_big_endian ? treg + 1 : treg,
|
2003-06-30 14:44:25 +02:00
|
|
|
|
BFD_RELOC_LO16, breg);
|
1999-05-03 09:29:11 +02:00
|
|
|
|
offset_expr.X_add_number += 4;
|
2003-06-30 14:44:25 +02:00
|
|
|
|
macro_build (NULL, &icnt, &offset_expr, "swc1", "T,o(b)",
|
1999-05-03 09:29:11 +02:00
|
|
|
|
target_big_endian ? treg : treg + 1,
|
2003-06-30 14:44:25 +02:00
|
|
|
|
BFD_RELOC_LO16, breg);
|
1999-05-03 09:29:11 +02:00
|
|
|
|
return;
|
|
|
|
|
|
|
|
|
|
case M_SEQ:
|
|
|
|
|
if (sreg == 0)
|
2003-06-30 14:44:25 +02:00
|
|
|
|
macro_build (NULL, &icnt, &expr1, "sltiu", "t,r,j", dreg, treg,
|
|
|
|
|
BFD_RELOC_LO16);
|
1999-05-03 09:29:11 +02:00
|
|
|
|
else if (treg == 0)
|
2003-06-30 14:44:25 +02:00
|
|
|
|
macro_build (NULL, &icnt, &expr1, "sltiu", "t,r,j", dreg, sreg,
|
|
|
|
|
BFD_RELOC_LO16);
|
1999-05-03 09:29:11 +02:00
|
|
|
|
else
|
|
|
|
|
{
|
2003-06-30 14:44:25 +02:00
|
|
|
|
macro_build (NULL, &icnt, NULL, "xor", "d,v,t", dreg, sreg, treg);
|
|
|
|
|
macro_build (NULL, &icnt, &expr1, "sltiu", "t,r,j", dreg, dreg,
|
|
|
|
|
BFD_RELOC_LO16);
|
1999-05-03 09:29:11 +02:00
|
|
|
|
}
|
|
|
|
|
return;
|
|
|
|
|
|
|
|
|
|
case M_SEQ_I:
|
|
|
|
|
if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
|
|
|
|
|
{
|
2003-06-30 14:44:25 +02:00
|
|
|
|
macro_build (NULL, &icnt, &expr1, "sltiu", "t,r,j", dreg, sreg,
|
|
|
|
|
BFD_RELOC_LO16);
|
1999-05-03 09:29:11 +02:00
|
|
|
|
return;
|
|
|
|
|
}
|
|
|
|
|
if (sreg == 0)
|
|
|
|
|
{
|
|
|
|
|
as_warn (_("Instruction %s: result is always false"),
|
|
|
|
|
ip->insn_mo->name);
|
2001-08-10 18:24:32 +02:00
|
|
|
|
move_register (&icnt, dreg, 0);
|
1999-05-03 09:29:11 +02:00
|
|
|
|
return;
|
|
|
|
|
}
|
|
|
|
|
if (imm_expr.X_op == O_constant
|
|
|
|
|
&& imm_expr.X_add_number >= 0
|
|
|
|
|
&& imm_expr.X_add_number < 0x10000)
|
|
|
|
|
{
|
2003-06-30 14:44:25 +02:00
|
|
|
|
macro_build (NULL, &icnt, &imm_expr, "xori", "t,r,i", dreg, sreg,
|
|
|
|
|
BFD_RELOC_LO16);
|
1999-05-03 09:29:11 +02:00
|
|
|
|
used_at = 0;
|
|
|
|
|
}
|
|
|
|
|
else if (imm_expr.X_op == O_constant
|
|
|
|
|
&& imm_expr.X_add_number > -0x8000
|
|
|
|
|
&& imm_expr.X_add_number < 0)
|
|
|
|
|
{
|
|
|
|
|
imm_expr.X_add_number = -imm_expr.X_add_number;
|
2003-06-30 14:44:25 +02:00
|
|
|
|
macro_build (NULL, &icnt, &imm_expr,
|
2001-08-02 12:15:24 +02:00
|
|
|
|
HAVE_32BIT_GPRS ? "addiu" : "daddiu",
|
2003-06-30 14:44:25 +02:00
|
|
|
|
"t,r,j", dreg, sreg, BFD_RELOC_LO16);
|
1999-05-03 09:29:11 +02:00
|
|
|
|
used_at = 0;
|
|
|
|
|
}
|
|
|
|
|
else
|
|
|
|
|
{
|
2002-02-25 14:21:38 +01:00
|
|
|
|
load_register (&icnt, AT, &imm_expr, HAVE_64BIT_GPRS);
|
2003-06-30 14:44:25 +02:00
|
|
|
|
macro_build (NULL, &icnt, NULL, "xor", "d,v,t", dreg, sreg, AT);
|
1999-05-03 09:29:11 +02:00
|
|
|
|
used_at = 1;
|
|
|
|
|
}
|
2003-06-30 14:44:25 +02:00
|
|
|
|
macro_build (NULL, &icnt, &expr1, "sltiu", "t,r,j", dreg, dreg,
|
|
|
|
|
BFD_RELOC_LO16);
|
1999-05-03 09:29:11 +02:00
|
|
|
|
if (used_at)
|
|
|
|
|
break;
|
|
|
|
|
return;
|
|
|
|
|
|
|
|
|
|
case M_SGE: /* sreg >= treg <==> not (sreg < treg) */
|
|
|
|
|
s = "slt";
|
|
|
|
|
goto sge;
|
|
|
|
|
case M_SGEU:
|
|
|
|
|
s = "sltu";
|
|
|
|
|
sge:
|
2003-06-30 14:44:25 +02:00
|
|
|
|
macro_build (NULL, &icnt, NULL, s, "d,v,t", dreg, sreg, treg);
|
|
|
|
|
macro_build (NULL, &icnt, &expr1, "xori", "t,r,i", dreg, dreg,
|
|
|
|
|
BFD_RELOC_LO16);
|
1999-05-03 09:29:11 +02:00
|
|
|
|
return;
|
|
|
|
|
|
|
|
|
|
case M_SGE_I: /* sreg >= I <==> not (sreg < I) */
|
|
|
|
|
case M_SGEU_I:
|
|
|
|
|
if (imm_expr.X_op == O_constant
|
|
|
|
|
&& imm_expr.X_add_number >= -0x8000
|
|
|
|
|
&& imm_expr.X_add_number < 0x8000)
|
|
|
|
|
{
|
2003-06-30 14:44:25 +02:00
|
|
|
|
macro_build (NULL, &icnt, &imm_expr,
|
1999-05-03 09:29:11 +02:00
|
|
|
|
mask == M_SGE_I ? "slti" : "sltiu",
|
2003-06-30 14:44:25 +02:00
|
|
|
|
"t,r,j", dreg, sreg, BFD_RELOC_LO16);
|
1999-05-03 09:29:11 +02:00
|
|
|
|
used_at = 0;
|
|
|
|
|
}
|
|
|
|
|
else
|
|
|
|
|
{
|
2002-02-25 14:21:38 +01:00
|
|
|
|
load_register (&icnt, AT, &imm_expr, HAVE_64BIT_GPRS);
|
2003-06-30 14:44:25 +02:00
|
|
|
|
macro_build (NULL, &icnt, NULL, mask == M_SGE_I ? "slt" : "sltu",
|
|
|
|
|
"d,v,t", dreg, sreg, AT);
|
1999-05-03 09:29:11 +02:00
|
|
|
|
used_at = 1;
|
|
|
|
|
}
|
2003-06-30 14:44:25 +02:00
|
|
|
|
macro_build (NULL, &icnt, &expr1, "xori", "t,r,i", dreg, dreg,
|
|
|
|
|
BFD_RELOC_LO16);
|
1999-05-03 09:29:11 +02:00
|
|
|
|
if (used_at)
|
|
|
|
|
break;
|
|
|
|
|
return;
|
|
|
|
|
|
|
|
|
|
case M_SGT: /* sreg > treg <==> treg < sreg */
|
|
|
|
|
s = "slt";
|
|
|
|
|
goto sgt;
|
|
|
|
|
case M_SGTU:
|
|
|
|
|
s = "sltu";
|
|
|
|
|
sgt:
|
2003-06-30 14:44:25 +02:00
|
|
|
|
macro_build (NULL, &icnt, NULL, s, "d,v,t", dreg, treg, sreg);
|
1999-05-03 09:29:11 +02:00
|
|
|
|
return;
|
|
|
|
|
|
|
|
|
|
case M_SGT_I: /* sreg > I <==> I < sreg */
|
|
|
|
|
s = "slt";
|
|
|
|
|
goto sgti;
|
|
|
|
|
case M_SGTU_I:
|
|
|
|
|
s = "sltu";
|
|
|
|
|
sgti:
|
2002-02-25 14:21:38 +01:00
|
|
|
|
load_register (&icnt, AT, &imm_expr, HAVE_64BIT_GPRS);
|
2003-06-30 14:44:25 +02:00
|
|
|
|
macro_build (NULL, &icnt, NULL, s, "d,v,t", dreg, AT, sreg);
|
1999-05-03 09:29:11 +02:00
|
|
|
|
break;
|
|
|
|
|
|
2001-11-12 23:20:44 +01:00
|
|
|
|
case M_SLE: /* sreg <= treg <==> treg >= sreg <==> not (treg < sreg) */
|
1999-05-03 09:29:11 +02:00
|
|
|
|
s = "slt";
|
|
|
|
|
goto sle;
|
|
|
|
|
case M_SLEU:
|
|
|
|
|
s = "sltu";
|
|
|
|
|
sle:
|
2003-06-30 14:44:25 +02:00
|
|
|
|
macro_build (NULL, &icnt, NULL, s, "d,v,t", dreg, treg, sreg);
|
|
|
|
|
macro_build (NULL, &icnt, &expr1, "xori", "t,r,i", dreg, dreg,
|
|
|
|
|
BFD_RELOC_LO16);
|
1999-05-03 09:29:11 +02:00
|
|
|
|
return;
|
|
|
|
|
|
2001-11-12 23:20:44 +01:00
|
|
|
|
case M_SLE_I: /* sreg <= I <==> I >= sreg <==> not (I < sreg) */
|
1999-05-03 09:29:11 +02:00
|
|
|
|
s = "slt";
|
|
|
|
|
goto slei;
|
|
|
|
|
case M_SLEU_I:
|
|
|
|
|
s = "sltu";
|
|
|
|
|
slei:
|
2002-02-25 14:21:38 +01:00
|
|
|
|
load_register (&icnt, AT, &imm_expr, HAVE_64BIT_GPRS);
|
2003-06-30 14:44:25 +02:00
|
|
|
|
macro_build (NULL, &icnt, NULL, s, "d,v,t", dreg, AT, sreg);
|
|
|
|
|
macro_build (NULL, &icnt, &expr1, "xori", "t,r,i", dreg, dreg,
|
|
|
|
|
BFD_RELOC_LO16);
|
1999-05-03 09:29:11 +02:00
|
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
case M_SLT_I:
|
|
|
|
|
if (imm_expr.X_op == O_constant
|
|
|
|
|
&& imm_expr.X_add_number >= -0x8000
|
|
|
|
|
&& imm_expr.X_add_number < 0x8000)
|
|
|
|
|
{
|
2003-06-30 14:44:25 +02:00
|
|
|
|
macro_build (NULL, &icnt, &imm_expr, "slti", "t,r,j", dreg, sreg,
|
|
|
|
|
BFD_RELOC_LO16);
|
1999-05-03 09:29:11 +02:00
|
|
|
|
return;
|
|
|
|
|
}
|
2002-02-25 14:21:38 +01:00
|
|
|
|
load_register (&icnt, AT, &imm_expr, HAVE_64BIT_GPRS);
|
2003-06-30 14:44:25 +02:00
|
|
|
|
macro_build (NULL, &icnt, NULL, "slt", "d,v,t", dreg, sreg, AT);
|
1999-05-03 09:29:11 +02:00
|
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
case M_SLTU_I:
|
|
|
|
|
if (imm_expr.X_op == O_constant
|
|
|
|
|
&& imm_expr.X_add_number >= -0x8000
|
|
|
|
|
&& imm_expr.X_add_number < 0x8000)
|
|
|
|
|
{
|
2003-06-30 14:44:25 +02:00
|
|
|
|
macro_build (NULL, &icnt, &imm_expr, "sltiu", "t,r,j", dreg, sreg,
|
|
|
|
|
BFD_RELOC_LO16);
|
1999-05-03 09:29:11 +02:00
|
|
|
|
return;
|
|
|
|
|
}
|
2002-02-25 14:21:38 +01:00
|
|
|
|
load_register (&icnt, AT, &imm_expr, HAVE_64BIT_GPRS);
|
2003-06-30 14:44:25 +02:00
|
|
|
|
macro_build (NULL, &icnt, NULL, "sltu", "d,v,t", dreg, sreg, AT);
|
1999-05-03 09:29:11 +02:00
|
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
case M_SNE:
|
|
|
|
|
if (sreg == 0)
|
2003-11-15 16:57:14 +01:00
|
|
|
|
macro_build (NULL, &icnt, NULL, "sltu","d,v,t", dreg, 0, treg);
|
1999-05-03 09:29:11 +02:00
|
|
|
|
else if (treg == 0)
|
2003-06-30 14:44:25 +02:00
|
|
|
|
macro_build (NULL, &icnt, NULL, "sltu", "d,v,t", dreg, 0, sreg);
|
1999-05-03 09:29:11 +02:00
|
|
|
|
else
|
|
|
|
|
{
|
2003-06-30 14:44:25 +02:00
|
|
|
|
macro_build (NULL, &icnt, NULL, "xor", "d,v,t", dreg, sreg, treg);
|
|
|
|
|
macro_build (NULL, &icnt, NULL, "sltu", "d,v,t", dreg, 0, dreg);
|
1999-05-03 09:29:11 +02:00
|
|
|
|
}
|
|
|
|
|
return;
|
|
|
|
|
|
|
|
|
|
case M_SNE_I:
|
|
|
|
|
if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
|
|
|
|
|
{
|
2003-06-30 14:44:25 +02:00
|
|
|
|
macro_build (NULL, &icnt, NULL, "sltu", "d,v,t", dreg, 0, sreg);
|
1999-05-03 09:29:11 +02:00
|
|
|
|
return;
|
|
|
|
|
}
|
|
|
|
|
if (sreg == 0)
|
|
|
|
|
{
|
|
|
|
|
as_warn (_("Instruction %s: result is always true"),
|
|
|
|
|
ip->insn_mo->name);
|
2003-06-30 14:44:25 +02:00
|
|
|
|
macro_build (NULL, &icnt, &expr1,
|
2001-08-02 12:15:24 +02:00
|
|
|
|
HAVE_32BIT_GPRS ? "addiu" : "daddiu",
|
2003-06-30 14:44:25 +02:00
|
|
|
|
"t,r,j", dreg, 0, BFD_RELOC_LO16);
|
1999-05-03 09:29:11 +02:00
|
|
|
|
return;
|
|
|
|
|
}
|
|
|
|
|
if (imm_expr.X_op == O_constant
|
|
|
|
|
&& imm_expr.X_add_number >= 0
|
|
|
|
|
&& imm_expr.X_add_number < 0x10000)
|
|
|
|
|
{
|
2003-06-30 14:44:25 +02:00
|
|
|
|
macro_build (NULL, &icnt, &imm_expr, "xori", "t,r,i", dreg, sreg,
|
|
|
|
|
BFD_RELOC_LO16);
|
1999-05-03 09:29:11 +02:00
|
|
|
|
used_at = 0;
|
|
|
|
|
}
|
|
|
|
|
else if (imm_expr.X_op == O_constant
|
|
|
|
|
&& imm_expr.X_add_number > -0x8000
|
|
|
|
|
&& imm_expr.X_add_number < 0)
|
|
|
|
|
{
|
|
|
|
|
imm_expr.X_add_number = -imm_expr.X_add_number;
|
2003-06-30 14:44:25 +02:00
|
|
|
|
macro_build (NULL, &icnt, &imm_expr,
|
2001-08-02 12:15:24 +02:00
|
|
|
|
HAVE_32BIT_GPRS ? "addiu" : "daddiu",
|
2003-06-30 14:44:25 +02:00
|
|
|
|
"t,r,j", dreg, sreg, BFD_RELOC_LO16);
|
1999-05-03 09:29:11 +02:00
|
|
|
|
used_at = 0;
|
|
|
|
|
}
|
|
|
|
|
else
|
|
|
|
|
{
|
2002-02-25 14:21:38 +01:00
|
|
|
|
load_register (&icnt, AT, &imm_expr, HAVE_64BIT_GPRS);
|
2003-06-30 14:44:25 +02:00
|
|
|
|
macro_build (NULL, &icnt, NULL, "xor", "d,v,t", dreg, sreg, AT);
|
1999-05-03 09:29:11 +02:00
|
|
|
|
used_at = 1;
|
|
|
|
|
}
|
2003-06-30 14:44:25 +02:00
|
|
|
|
macro_build (NULL, &icnt, NULL, "sltu", "d,v,t", dreg, 0, dreg);
|
1999-05-03 09:29:11 +02:00
|
|
|
|
if (used_at)
|
|
|
|
|
break;
|
|
|
|
|
return;
|
|
|
|
|
|
|
|
|
|
case M_DSUB_I:
|
|
|
|
|
dbl = 1;
|
|
|
|
|
case M_SUB_I:
|
|
|
|
|
if (imm_expr.X_op == O_constant
|
|
|
|
|
&& imm_expr.X_add_number > -0x8000
|
|
|
|
|
&& imm_expr.X_add_number <= 0x8000)
|
|
|
|
|
{
|
|
|
|
|
imm_expr.X_add_number = -imm_expr.X_add_number;
|
2003-06-30 14:44:25 +02:00
|
|
|
|
macro_build (NULL, &icnt, &imm_expr, dbl ? "daddi" : "addi",
|
|
|
|
|
"t,r,j", dreg, sreg, BFD_RELOC_LO16);
|
1999-05-03 09:29:11 +02:00
|
|
|
|
return;
|
|
|
|
|
}
|
|
|
|
|
load_register (&icnt, AT, &imm_expr, dbl);
|
2003-06-30 14:44:25 +02:00
|
|
|
|
macro_build (NULL, &icnt, NULL, dbl ? "dsub" : "sub", "d,v,t",
|
|
|
|
|
dreg, sreg, AT);
|
1999-05-03 09:29:11 +02:00
|
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
case M_DSUBU_I:
|
|
|
|
|
dbl = 1;
|
|
|
|
|
case M_SUBU_I:
|
|
|
|
|
if (imm_expr.X_op == O_constant
|
|
|
|
|
&& imm_expr.X_add_number > -0x8000
|
|
|
|
|
&& imm_expr.X_add_number <= 0x8000)
|
|
|
|
|
{
|
|
|
|
|
imm_expr.X_add_number = -imm_expr.X_add_number;
|
2003-06-30 14:44:25 +02:00
|
|
|
|
macro_build (NULL, &icnt, &imm_expr, dbl ? "daddiu" : "addiu",
|
|
|
|
|
"t,r,j", dreg, sreg, BFD_RELOC_LO16);
|
1999-05-03 09:29:11 +02:00
|
|
|
|
return;
|
|
|
|
|
}
|
|
|
|
|
load_register (&icnt, AT, &imm_expr, dbl);
|
2003-06-30 14:44:25 +02:00
|
|
|
|
macro_build (NULL, &icnt, NULL, dbl ? "dsubu" : "subu", "d,v,t",
|
|
|
|
|
dreg, sreg, AT);
|
1999-05-03 09:29:11 +02:00
|
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
case M_TEQ_I:
|
|
|
|
|
s = "teq";
|
|
|
|
|
goto trap;
|
|
|
|
|
case M_TGE_I:
|
|
|
|
|
s = "tge";
|
|
|
|
|
goto trap;
|
|
|
|
|
case M_TGEU_I:
|
|
|
|
|
s = "tgeu";
|
|
|
|
|
goto trap;
|
|
|
|
|
case M_TLT_I:
|
|
|
|
|
s = "tlt";
|
|
|
|
|
goto trap;
|
|
|
|
|
case M_TLTU_I:
|
|
|
|
|
s = "tltu";
|
|
|
|
|
goto trap;
|
|
|
|
|
case M_TNE_I:
|
|
|
|
|
s = "tne";
|
|
|
|
|
trap:
|
2002-02-25 14:21:38 +01:00
|
|
|
|
load_register (&icnt, AT, &imm_expr, HAVE_64BIT_GPRS);
|
2003-06-30 14:44:25 +02:00
|
|
|
|
macro_build (NULL, &icnt, NULL, s, "s,t", sreg, AT);
|
1999-05-03 09:29:11 +02:00
|
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
case M_TRUNCWS:
|
2000-05-30 00:05:27 +02:00
|
|
|
|
case M_TRUNCWD:
|
2000-12-01 22:35:38 +01:00
|
|
|
|
assert (mips_opts.isa == ISA_MIPS1);
|
1999-05-03 09:29:11 +02:00
|
|
|
|
sreg = (ip->insn_opcode >> 11) & 0x1f; /* floating reg */
|
|
|
|
|
dreg = (ip->insn_opcode >> 06) & 0x1f; /* floating reg */
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* Is the double cfc1 instruction a bug in the mips assembler;
|
|
|
|
|
* or is there a reason for it?
|
|
|
|
|
*/
|
2002-11-30 09:39:46 +01:00
|
|
|
|
mips_emit_delays (TRUE);
|
1999-05-03 09:29:11 +02:00
|
|
|
|
++mips_opts.noreorder;
|
|
|
|
|
mips_any_noreorder = 1;
|
2003-06-30 14:44:25 +02:00
|
|
|
|
macro_build (NULL, &icnt, NULL, "cfc1", "t,G", treg, RA);
|
|
|
|
|
macro_build (NULL, &icnt, NULL, "cfc1", "t,G", treg, RA);
|
|
|
|
|
macro_build (NULL, &icnt, NULL, "nop", "");
|
1999-05-03 09:29:11 +02:00
|
|
|
|
expr1.X_add_number = 3;
|
2003-06-30 14:44:25 +02:00
|
|
|
|
macro_build (NULL, &icnt, &expr1, "ori", "t,r,i", AT, treg,
|
|
|
|
|
BFD_RELOC_LO16);
|
1999-05-03 09:29:11 +02:00
|
|
|
|
expr1.X_add_number = 2;
|
2003-06-30 14:44:25 +02:00
|
|
|
|
macro_build (NULL, &icnt, &expr1, "xori", "t,r,i", AT, AT,
|
|
|
|
|
BFD_RELOC_LO16);
|
|
|
|
|
macro_build (NULL, &icnt, NULL, "ctc1", "t,G", AT, RA);
|
|
|
|
|
macro_build (NULL, &icnt, NULL, "nop", "");
|
|
|
|
|
macro_build (NULL, &icnt, NULL,
|
|
|
|
|
mask == M_TRUNCWD ? "cvt.w.d" : "cvt.w.s",
|
|
|
|
|
"D,S", dreg, sreg);
|
|
|
|
|
macro_build (NULL, &icnt, NULL, "ctc1", "t,G", treg, RA);
|
|
|
|
|
macro_build (NULL, &icnt, NULL, "nop", "");
|
1999-05-03 09:29:11 +02:00
|
|
|
|
--mips_opts.noreorder;
|
|
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
case M_ULH:
|
|
|
|
|
s = "lb";
|
|
|
|
|
goto ulh;
|
|
|
|
|
case M_ULHU:
|
|
|
|
|
s = "lbu";
|
|
|
|
|
ulh:
|
|
|
|
|
if (offset_expr.X_add_number >= 0x7fff)
|
|
|
|
|
as_bad (_("operand overflow"));
|
|
|
|
|
if (! target_big_endian)
|
2002-05-26 20:46:37 +02:00
|
|
|
|
++offset_expr.X_add_number;
|
2003-06-30 14:44:25 +02:00
|
|
|
|
macro_build (NULL, &icnt, &offset_expr, s, "t,o(b)", AT,
|
|
|
|
|
BFD_RELOC_LO16, breg);
|
1999-05-03 09:29:11 +02:00
|
|
|
|
if (! target_big_endian)
|
2002-05-26 20:46:37 +02:00
|
|
|
|
--offset_expr.X_add_number;
|
1999-05-03 09:29:11 +02:00
|
|
|
|
else
|
2002-05-26 20:46:37 +02:00
|
|
|
|
++offset_expr.X_add_number;
|
2003-06-30 14:44:25 +02:00
|
|
|
|
macro_build (NULL, &icnt, &offset_expr, "lbu", "t,o(b)", treg,
|
|
|
|
|
BFD_RELOC_LO16, breg);
|
|
|
|
|
macro_build (NULL, &icnt, NULL, "sll", "d,w,<", AT, AT, 8);
|
|
|
|
|
macro_build (NULL, &icnt, NULL, "or", "d,v,t", treg, treg, AT);
|
1999-05-03 09:29:11 +02:00
|
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
case M_ULD:
|
|
|
|
|
s = "ldl";
|
|
|
|
|
s2 = "ldr";
|
|
|
|
|
off = 7;
|
|
|
|
|
goto ulw;
|
|
|
|
|
case M_ULW:
|
|
|
|
|
s = "lwl";
|
|
|
|
|
s2 = "lwr";
|
|
|
|
|
off = 3;
|
|
|
|
|
ulw:
|
|
|
|
|
if (offset_expr.X_add_number >= 0x8000 - off)
|
|
|
|
|
as_bad (_("operand overflow"));
|
2003-04-02 20:43:16 +02:00
|
|
|
|
if (treg != breg)
|
|
|
|
|
tempreg = treg;
|
|
|
|
|
else
|
|
|
|
|
tempreg = AT;
|
1999-05-03 09:29:11 +02:00
|
|
|
|
if (! target_big_endian)
|
|
|
|
|
offset_expr.X_add_number += off;
|
2003-06-30 14:44:25 +02:00
|
|
|
|
macro_build (NULL, &icnt, &offset_expr, s, "t,o(b)", tempreg,
|
|
|
|
|
BFD_RELOC_LO16, breg);
|
1999-05-03 09:29:11 +02:00
|
|
|
|
if (! target_big_endian)
|
|
|
|
|
offset_expr.X_add_number -= off;
|
|
|
|
|
else
|
|
|
|
|
offset_expr.X_add_number += off;
|
2003-06-30 14:44:25 +02:00
|
|
|
|
macro_build (NULL, &icnt, &offset_expr, s2, "t,o(b)", tempreg,
|
|
|
|
|
BFD_RELOC_LO16, breg);
|
2003-04-02 20:43:16 +02:00
|
|
|
|
|
|
|
|
|
/* If necessary, move the result in tempreg the final destination. */
|
|
|
|
|
if (treg == tempreg)
|
|
|
|
|
return;
|
|
|
|
|
/* Protect second load's delay slot. */
|
|
|
|
|
if (!gpr_interlocks)
|
2003-06-30 14:44:25 +02:00
|
|
|
|
macro_build (NULL, &icnt, NULL, "nop", "");
|
2003-04-02 20:43:16 +02:00
|
|
|
|
move_register (&icnt, treg, tempreg);
|
|
|
|
|
break;
|
1999-05-03 09:29:11 +02:00
|
|
|
|
|
|
|
|
|
case M_ULD_A:
|
|
|
|
|
s = "ldl";
|
|
|
|
|
s2 = "ldr";
|
|
|
|
|
off = 7;
|
|
|
|
|
goto ulwa;
|
|
|
|
|
case M_ULW_A:
|
|
|
|
|
s = "lwl";
|
|
|
|
|
s2 = "lwr";
|
|
|
|
|
off = 3;
|
|
|
|
|
ulwa:
|
2001-10-10 02:43:36 +02:00
|
|
|
|
used_at = 1;
|
2002-05-28 21:23:09 +02:00
|
|
|
|
load_address (&icnt, AT, &offset_expr, &used_at);
|
1999-05-03 09:29:11 +02:00
|
|
|
|
if (breg != 0)
|
2003-06-30 14:44:25 +02:00
|
|
|
|
macro_build (NULL, &icnt, NULL, ADDRESS_ADD_INSN, "d,v,t",
|
|
|
|
|
AT, AT, breg);
|
1999-05-03 09:29:11 +02:00
|
|
|
|
if (! target_big_endian)
|
|
|
|
|
expr1.X_add_number = off;
|
|
|
|
|
else
|
|
|
|
|
expr1.X_add_number = 0;
|
2003-06-30 14:44:25 +02:00
|
|
|
|
macro_build (NULL, &icnt, &expr1, s, "t,o(b)", treg,
|
|
|
|
|
BFD_RELOC_LO16, AT);
|
1999-05-03 09:29:11 +02:00
|
|
|
|
if (! target_big_endian)
|
|
|
|
|
expr1.X_add_number = 0;
|
|
|
|
|
else
|
|
|
|
|
expr1.X_add_number = off;
|
2003-06-30 14:44:25 +02:00
|
|
|
|
macro_build (NULL, &icnt, &expr1, s2, "t,o(b)", treg,
|
|
|
|
|
BFD_RELOC_LO16, AT);
|
1999-05-03 09:29:11 +02:00
|
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
case M_ULH_A:
|
|
|
|
|
case M_ULHU_A:
|
2001-10-10 02:43:36 +02:00
|
|
|
|
used_at = 1;
|
2002-05-28 21:23:09 +02:00
|
|
|
|
load_address (&icnt, AT, &offset_expr, &used_at);
|
1999-05-03 09:29:11 +02:00
|
|
|
|
if (breg != 0)
|
2003-06-30 14:44:25 +02:00
|
|
|
|
macro_build (NULL, &icnt, NULL, ADDRESS_ADD_INSN, "d,v,t",
|
|
|
|
|
AT, AT, breg);
|
1999-05-03 09:29:11 +02:00
|
|
|
|
if (target_big_endian)
|
|
|
|
|
expr1.X_add_number = 0;
|
2003-06-30 14:44:25 +02:00
|
|
|
|
macro_build (NULL, &icnt, &expr1,
|
|
|
|
|
mask == M_ULH_A ? "lb" : "lbu", "t,o(b)",
|
|
|
|
|
treg, BFD_RELOC_LO16, AT);
|
1999-05-03 09:29:11 +02:00
|
|
|
|
if (target_big_endian)
|
|
|
|
|
expr1.X_add_number = 1;
|
|
|
|
|
else
|
|
|
|
|
expr1.X_add_number = 0;
|
2003-06-30 14:44:25 +02:00
|
|
|
|
macro_build (NULL, &icnt, &expr1, "lbu", "t,o(b)",
|
|
|
|
|
AT, BFD_RELOC_LO16, AT);
|
|
|
|
|
macro_build (NULL, &icnt, NULL, "sll", "d,w,<", treg, treg, 8);
|
|
|
|
|
macro_build (NULL, &icnt, NULL, "or", "d,v,t", treg, treg, AT);
|
1999-05-03 09:29:11 +02:00
|
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
case M_USH:
|
|
|
|
|
if (offset_expr.X_add_number >= 0x7fff)
|
|
|
|
|
as_bad (_("operand overflow"));
|
|
|
|
|
if (target_big_endian)
|
2002-05-26 20:46:37 +02:00
|
|
|
|
++offset_expr.X_add_number;
|
2003-06-30 14:44:25 +02:00
|
|
|
|
macro_build (NULL, &icnt, &offset_expr, "sb", "t,o(b)", treg,
|
|
|
|
|
BFD_RELOC_LO16, breg);
|
|
|
|
|
macro_build (NULL, &icnt, NULL, "srl", "d,w,<", AT, treg, 8);
|
1999-05-03 09:29:11 +02:00
|
|
|
|
if (target_big_endian)
|
2002-05-26 20:46:37 +02:00
|
|
|
|
--offset_expr.X_add_number;
|
1999-05-03 09:29:11 +02:00
|
|
|
|
else
|
2002-05-26 20:46:37 +02:00
|
|
|
|
++offset_expr.X_add_number;
|
2003-06-30 14:44:25 +02:00
|
|
|
|
macro_build (NULL, &icnt, &offset_expr, "sb", "t,o(b)", AT,
|
|
|
|
|
BFD_RELOC_LO16, breg);
|
1999-05-03 09:29:11 +02:00
|
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
case M_USD:
|
|
|
|
|
s = "sdl";
|
|
|
|
|
s2 = "sdr";
|
|
|
|
|
off = 7;
|
|
|
|
|
goto usw;
|
|
|
|
|
case M_USW:
|
|
|
|
|
s = "swl";
|
|
|
|
|
s2 = "swr";
|
|
|
|
|
off = 3;
|
|
|
|
|
usw:
|
|
|
|
|
if (offset_expr.X_add_number >= 0x8000 - off)
|
|
|
|
|
as_bad (_("operand overflow"));
|
|
|
|
|
if (! target_big_endian)
|
|
|
|
|
offset_expr.X_add_number += off;
|
2003-06-30 14:44:25 +02:00
|
|
|
|
macro_build (NULL, &icnt, &offset_expr, s, "t,o(b)", treg,
|
|
|
|
|
BFD_RELOC_LO16, breg);
|
1999-05-03 09:29:11 +02:00
|
|
|
|
if (! target_big_endian)
|
|
|
|
|
offset_expr.X_add_number -= off;
|
|
|
|
|
else
|
|
|
|
|
offset_expr.X_add_number += off;
|
2003-06-30 14:44:25 +02:00
|
|
|
|
macro_build (NULL, &icnt, &offset_expr, s2, "t,o(b)", treg,
|
|
|
|
|
BFD_RELOC_LO16, breg);
|
1999-05-03 09:29:11 +02:00
|
|
|
|
return;
|
|
|
|
|
|
|
|
|
|
case M_USD_A:
|
|
|
|
|
s = "sdl";
|
|
|
|
|
s2 = "sdr";
|
|
|
|
|
off = 7;
|
|
|
|
|
goto uswa;
|
|
|
|
|
case M_USW_A:
|
|
|
|
|
s = "swl";
|
|
|
|
|
s2 = "swr";
|
|
|
|
|
off = 3;
|
|
|
|
|
uswa:
|
2001-10-10 02:43:36 +02:00
|
|
|
|
used_at = 1;
|
2002-05-28 21:23:09 +02:00
|
|
|
|
load_address (&icnt, AT, &offset_expr, &used_at);
|
1999-05-03 09:29:11 +02:00
|
|
|
|
if (breg != 0)
|
2003-06-30 14:44:25 +02:00
|
|
|
|
macro_build (NULL, &icnt, NULL, ADDRESS_ADD_INSN, "d,v,t",
|
|
|
|
|
AT, AT, breg);
|
1999-05-03 09:29:11 +02:00
|
|
|
|
if (! target_big_endian)
|
|
|
|
|
expr1.X_add_number = off;
|
|
|
|
|
else
|
|
|
|
|
expr1.X_add_number = 0;
|
2003-06-30 14:44:25 +02:00
|
|
|
|
macro_build (NULL, &icnt, &expr1, s, "t,o(b)", treg,
|
|
|
|
|
BFD_RELOC_LO16, AT);
|
1999-05-03 09:29:11 +02:00
|
|
|
|
if (! target_big_endian)
|
|
|
|
|
expr1.X_add_number = 0;
|
|
|
|
|
else
|
|
|
|
|
expr1.X_add_number = off;
|
2003-06-30 14:44:25 +02:00
|
|
|
|
macro_build (NULL, &icnt, &expr1, s2, "t,o(b)", treg,
|
|
|
|
|
BFD_RELOC_LO16, AT);
|
1999-05-03 09:29:11 +02:00
|
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
case M_USH_A:
|
2001-10-10 02:43:36 +02:00
|
|
|
|
used_at = 1;
|
2002-05-28 21:23:09 +02:00
|
|
|
|
load_address (&icnt, AT, &offset_expr, &used_at);
|
1999-05-03 09:29:11 +02:00
|
|
|
|
if (breg != 0)
|
2003-06-30 14:44:25 +02:00
|
|
|
|
macro_build (NULL, &icnt, NULL, ADDRESS_ADD_INSN, "d,v,t",
|
|
|
|
|
AT, AT, breg);
|
1999-05-03 09:29:11 +02:00
|
|
|
|
if (! target_big_endian)
|
|
|
|
|
expr1.X_add_number = 0;
|
2003-06-30 14:44:25 +02:00
|
|
|
|
macro_build (NULL, &icnt, &expr1, "sb", "t,o(b)", treg,
|
|
|
|
|
BFD_RELOC_LO16, AT);
|
|
|
|
|
macro_build (NULL, &icnt, NULL, "srl", "d,w,<", treg, treg, 8);
|
1999-05-03 09:29:11 +02:00
|
|
|
|
if (! target_big_endian)
|
|
|
|
|
expr1.X_add_number = 1;
|
|
|
|
|
else
|
|
|
|
|
expr1.X_add_number = 0;
|
2003-06-30 14:44:25 +02:00
|
|
|
|
macro_build (NULL, &icnt, &expr1, "sb", "t,o(b)", treg,
|
|
|
|
|
BFD_RELOC_LO16, AT);
|
1999-05-03 09:29:11 +02:00
|
|
|
|
if (! target_big_endian)
|
|
|
|
|
expr1.X_add_number = 0;
|
|
|
|
|
else
|
|
|
|
|
expr1.X_add_number = 1;
|
2003-06-30 14:44:25 +02:00
|
|
|
|
macro_build (NULL, &icnt, &expr1, "lbu", "t,o(b)", AT,
|
|
|
|
|
BFD_RELOC_LO16, AT);
|
|
|
|
|
macro_build (NULL, &icnt, NULL, "sll", "d,w,<", treg, treg, 8);
|
|
|
|
|
macro_build (NULL, &icnt, NULL, "or", "d,v,t", treg, treg, AT);
|
1999-05-03 09:29:11 +02:00
|
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
default:
|
|
|
|
|
/* FIXME: Check if this is one of the itbl macros, since they
|
2000-09-07 14:45:56 +02:00
|
|
|
|
are added dynamically. */
|
1999-05-03 09:29:11 +02:00
|
|
|
|
as_bad (_("Macro %s not implemented yet"), ip->insn_mo->name);
|
|
|
|
|
break;
|
|
|
|
|
}
|
|
|
|
|
if (mips_opts.noat)
|
|
|
|
|
as_warn (_("Macro used $at after \".set noat\""));
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/* Implement macros in mips16 mode. */
|
|
|
|
|
|
|
|
|
|
static void
|
2003-06-30 14:44:25 +02:00
|
|
|
|
mips16_macro (struct mips_cl_insn *ip)
|
1999-05-03 09:29:11 +02:00
|
|
|
|
{
|
|
|
|
|
int mask;
|
|
|
|
|
int xreg, yreg, zreg, tmp;
|
|
|
|
|
int icnt;
|
|
|
|
|
expressionS expr1;
|
|
|
|
|
int dbl;
|
|
|
|
|
const char *s, *s2, *s3;
|
|
|
|
|
|
|
|
|
|
mask = ip->insn_mo->mask;
|
|
|
|
|
|
|
|
|
|
xreg = (ip->insn_opcode >> MIPS16OP_SH_RX) & MIPS16OP_MASK_RX;
|
|
|
|
|
yreg = (ip->insn_opcode >> MIPS16OP_SH_RY) & MIPS16OP_MASK_RY;
|
|
|
|
|
zreg = (ip->insn_opcode >> MIPS16OP_SH_RZ) & MIPS16OP_MASK_RZ;
|
|
|
|
|
|
|
|
|
|
icnt = 0;
|
|
|
|
|
|
|
|
|
|
expr1.X_op = O_constant;
|
|
|
|
|
expr1.X_op_symbol = NULL;
|
|
|
|
|
expr1.X_add_symbol = NULL;
|
|
|
|
|
expr1.X_add_number = 1;
|
|
|
|
|
|
|
|
|
|
dbl = 0;
|
|
|
|
|
|
|
|
|
|
switch (mask)
|
|
|
|
|
{
|
|
|
|
|
default:
|
|
|
|
|
internalError ();
|
|
|
|
|
|
|
|
|
|
case M_DDIV_3:
|
|
|
|
|
dbl = 1;
|
|
|
|
|
case M_DIV_3:
|
|
|
|
|
s = "mflo";
|
|
|
|
|
goto do_div3;
|
|
|
|
|
case M_DREM_3:
|
|
|
|
|
dbl = 1;
|
|
|
|
|
case M_REM_3:
|
|
|
|
|
s = "mfhi";
|
|
|
|
|
do_div3:
|
2002-11-30 09:39:46 +01:00
|
|
|
|
mips_emit_delays (TRUE);
|
1999-05-03 09:29:11 +02:00
|
|
|
|
++mips_opts.noreorder;
|
|
|
|
|
mips_any_noreorder = 1;
|
2003-06-30 14:44:25 +02:00
|
|
|
|
macro_build (NULL, &icnt, NULL, dbl ? "ddiv" : "div", "0,x,y",
|
|
|
|
|
xreg, yreg);
|
1999-05-03 09:29:11 +02:00
|
|
|
|
expr1.X_add_number = 2;
|
2003-06-30 14:44:25 +02:00
|
|
|
|
macro_build (NULL, &icnt, &expr1, "bnez", "x,p", yreg);
|
|
|
|
|
macro_build (NULL, &icnt, NULL, "break", "6", 7);
|
2000-09-07 14:45:56 +02:00
|
|
|
|
|
1999-05-03 09:29:11 +02:00
|
|
|
|
/* FIXME: The normal code checks for of -1 / -0x80000000 here,
|
|
|
|
|
since that causes an overflow. We should do that as well,
|
|
|
|
|
but I don't see how to do the comparisons without a temporary
|
|
|
|
|
register. */
|
|
|
|
|
--mips_opts.noreorder;
|
2003-06-30 14:44:25 +02:00
|
|
|
|
macro_build (NULL, &icnt, NULL, s, "x", zreg);
|
1999-05-03 09:29:11 +02:00
|
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
case M_DIVU_3:
|
|
|
|
|
s = "divu";
|
|
|
|
|
s2 = "mflo";
|
|
|
|
|
goto do_divu3;
|
|
|
|
|
case M_REMU_3:
|
|
|
|
|
s = "divu";
|
|
|
|
|
s2 = "mfhi";
|
|
|
|
|
goto do_divu3;
|
|
|
|
|
case M_DDIVU_3:
|
|
|
|
|
s = "ddivu";
|
|
|
|
|
s2 = "mflo";
|
|
|
|
|
goto do_divu3;
|
|
|
|
|
case M_DREMU_3:
|
|
|
|
|
s = "ddivu";
|
|
|
|
|
s2 = "mfhi";
|
|
|
|
|
do_divu3:
|
2002-11-30 09:39:46 +01:00
|
|
|
|
mips_emit_delays (TRUE);
|
1999-05-03 09:29:11 +02:00
|
|
|
|
++mips_opts.noreorder;
|
|
|
|
|
mips_any_noreorder = 1;
|
2003-06-30 14:44:25 +02:00
|
|
|
|
macro_build (NULL, &icnt, NULL, s, "0,x,y", xreg, yreg);
|
1999-05-03 09:29:11 +02:00
|
|
|
|
expr1.X_add_number = 2;
|
2003-06-30 14:44:25 +02:00
|
|
|
|
macro_build (NULL, &icnt, &expr1, "bnez", "x,p", yreg);
|
|
|
|
|
macro_build (NULL, &icnt, NULL, "break", "6", 7);
|
1999-05-03 09:29:11 +02:00
|
|
|
|
--mips_opts.noreorder;
|
2003-06-30 14:44:25 +02:00
|
|
|
|
macro_build (NULL, &icnt, NULL, s2, "x", zreg);
|
1999-05-03 09:29:11 +02:00
|
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
case M_DMUL:
|
|
|
|
|
dbl = 1;
|
|
|
|
|
case M_MUL:
|
2003-06-30 14:44:25 +02:00
|
|
|
|
macro_build (NULL, &icnt, NULL, dbl ? "dmultu" : "multu", "x,y",
|
|
|
|
|
xreg, yreg);
|
|
|
|
|
macro_build (NULL, &icnt, NULL, "mflo", "x", zreg);
|
1999-05-03 09:29:11 +02:00
|
|
|
|
return;
|
|
|
|
|
|
|
|
|
|
case M_DSUBU_I:
|
|
|
|
|
dbl = 1;
|
|
|
|
|
goto do_subu;
|
|
|
|
|
case M_SUBU_I:
|
|
|
|
|
do_subu:
|
|
|
|
|
if (imm_expr.X_op != O_constant)
|
|
|
|
|
as_bad (_("Unsupported large constant"));
|
|
|
|
|
imm_expr.X_add_number = -imm_expr.X_add_number;
|
2003-06-30 14:44:25 +02:00
|
|
|
|
macro_build (NULL, &icnt, &imm_expr, dbl ? "daddiu" : "addiu", "y,x,4",
|
|
|
|
|
yreg, xreg);
|
1999-05-03 09:29:11 +02:00
|
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
case M_SUBU_I_2:
|
|
|
|
|
if (imm_expr.X_op != O_constant)
|
|
|
|
|
as_bad (_("Unsupported large constant"));
|
|
|
|
|
imm_expr.X_add_number = -imm_expr.X_add_number;
|
2003-06-30 14:44:25 +02:00
|
|
|
|
macro_build (NULL, &icnt, &imm_expr, "addiu", "x,k", xreg);
|
1999-05-03 09:29:11 +02:00
|
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
case M_DSUBU_I_2:
|
|
|
|
|
if (imm_expr.X_op != O_constant)
|
|
|
|
|
as_bad (_("Unsupported large constant"));
|
|
|
|
|
imm_expr.X_add_number = -imm_expr.X_add_number;
|
2003-06-30 14:44:25 +02:00
|
|
|
|
macro_build (NULL, &icnt, &imm_expr, "daddiu", "y,j", yreg);
|
1999-05-03 09:29:11 +02:00
|
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
case M_BEQ:
|
|
|
|
|
s = "cmp";
|
|
|
|
|
s2 = "bteqz";
|
|
|
|
|
goto do_branch;
|
|
|
|
|
case M_BNE:
|
|
|
|
|
s = "cmp";
|
|
|
|
|
s2 = "btnez";
|
|
|
|
|
goto do_branch;
|
|
|
|
|
case M_BLT:
|
|
|
|
|
s = "slt";
|
|
|
|
|
s2 = "btnez";
|
|
|
|
|
goto do_branch;
|
|
|
|
|
case M_BLTU:
|
|
|
|
|
s = "sltu";
|
|
|
|
|
s2 = "btnez";
|
|
|
|
|
goto do_branch;
|
|
|
|
|
case M_BLE:
|
|
|
|
|
s = "slt";
|
|
|
|
|
s2 = "bteqz";
|
|
|
|
|
goto do_reverse_branch;
|
|
|
|
|
case M_BLEU:
|
|
|
|
|
s = "sltu";
|
|
|
|
|
s2 = "bteqz";
|
|
|
|
|
goto do_reverse_branch;
|
|
|
|
|
case M_BGE:
|
|
|
|
|
s = "slt";
|
|
|
|
|
s2 = "bteqz";
|
|
|
|
|
goto do_branch;
|
|
|
|
|
case M_BGEU:
|
|
|
|
|
s = "sltu";
|
|
|
|
|
s2 = "bteqz";
|
|
|
|
|
goto do_branch;
|
|
|
|
|
case M_BGT:
|
|
|
|
|
s = "slt";
|
|
|
|
|
s2 = "btnez";
|
|
|
|
|
goto do_reverse_branch;
|
|
|
|
|
case M_BGTU:
|
|
|
|
|
s = "sltu";
|
|
|
|
|
s2 = "btnez";
|
|
|
|
|
|
|
|
|
|
do_reverse_branch:
|
|
|
|
|
tmp = xreg;
|
|
|
|
|
xreg = yreg;
|
|
|
|
|
yreg = tmp;
|
|
|
|
|
|
|
|
|
|
do_branch:
|
2003-06-30 14:44:25 +02:00
|
|
|
|
macro_build (NULL, &icnt, NULL, s, "x,y", xreg, yreg);
|
|
|
|
|
macro_build (NULL, &icnt, &offset_expr, s2, "p");
|
1999-05-03 09:29:11 +02:00
|
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
case M_BEQ_I:
|
|
|
|
|
s = "cmpi";
|
|
|
|
|
s2 = "bteqz";
|
|
|
|
|
s3 = "x,U";
|
|
|
|
|
goto do_branch_i;
|
|
|
|
|
case M_BNE_I:
|
|
|
|
|
s = "cmpi";
|
|
|
|
|
s2 = "btnez";
|
|
|
|
|
s3 = "x,U";
|
|
|
|
|
goto do_branch_i;
|
|
|
|
|
case M_BLT_I:
|
|
|
|
|
s = "slti";
|
|
|
|
|
s2 = "btnez";
|
|
|
|
|
s3 = "x,8";
|
|
|
|
|
goto do_branch_i;
|
|
|
|
|
case M_BLTU_I:
|
|
|
|
|
s = "sltiu";
|
|
|
|
|
s2 = "btnez";
|
|
|
|
|
s3 = "x,8";
|
|
|
|
|
goto do_branch_i;
|
|
|
|
|
case M_BLE_I:
|
|
|
|
|
s = "slti";
|
|
|
|
|
s2 = "btnez";
|
|
|
|
|
s3 = "x,8";
|
|
|
|
|
goto do_addone_branch_i;
|
|
|
|
|
case M_BLEU_I:
|
|
|
|
|
s = "sltiu";
|
|
|
|
|
s2 = "btnez";
|
|
|
|
|
s3 = "x,8";
|
|
|
|
|
goto do_addone_branch_i;
|
|
|
|
|
case M_BGE_I:
|
|
|
|
|
s = "slti";
|
|
|
|
|
s2 = "bteqz";
|
|
|
|
|
s3 = "x,8";
|
|
|
|
|
goto do_branch_i;
|
|
|
|
|
case M_BGEU_I:
|
|
|
|
|
s = "sltiu";
|
|
|
|
|
s2 = "bteqz";
|
|
|
|
|
s3 = "x,8";
|
|
|
|
|
goto do_branch_i;
|
|
|
|
|
case M_BGT_I:
|
|
|
|
|
s = "slti";
|
|
|
|
|
s2 = "bteqz";
|
|
|
|
|
s3 = "x,8";
|
|
|
|
|
goto do_addone_branch_i;
|
|
|
|
|
case M_BGTU_I:
|
|
|
|
|
s = "sltiu";
|
|
|
|
|
s2 = "bteqz";
|
|
|
|
|
s3 = "x,8";
|
|
|
|
|
|
|
|
|
|
do_addone_branch_i:
|
|
|
|
|
if (imm_expr.X_op != O_constant)
|
|
|
|
|
as_bad (_("Unsupported large constant"));
|
|
|
|
|
++imm_expr.X_add_number;
|
|
|
|
|
|
|
|
|
|
do_branch_i:
|
2003-06-30 14:44:25 +02:00
|
|
|
|
macro_build (NULL, &icnt, &imm_expr, s, s3, xreg);
|
|
|
|
|
macro_build (NULL, &icnt, &offset_expr, s2, "p");
|
1999-05-03 09:29:11 +02:00
|
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
case M_ABS:
|
|
|
|
|
expr1.X_add_number = 0;
|
2003-06-30 14:44:25 +02:00
|
|
|
|
macro_build (NULL, &icnt, &expr1, "slti", "x,8", yreg);
|
1999-05-03 09:29:11 +02:00
|
|
|
|
if (xreg != yreg)
|
2001-08-10 18:24:32 +02:00
|
|
|
|
move_register (&icnt, xreg, yreg);
|
1999-05-03 09:29:11 +02:00
|
|
|
|
expr1.X_add_number = 2;
|
2003-06-30 14:44:25 +02:00
|
|
|
|
macro_build (NULL, &icnt, &expr1, "bteqz", "p");
|
|
|
|
|
macro_build (NULL, &icnt, NULL, "neg", "x,w", xreg, xreg);
|
1999-05-03 09:29:11 +02:00
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/* For consistency checking, verify that all bits are specified either
|
|
|
|
|
by the match/mask part of the instruction definition, or by the
|
|
|
|
|
operand list. */
|
|
|
|
|
static int
|
2003-06-30 14:44:25 +02:00
|
|
|
|
validate_mips_insn (const struct mips_opcode *opc)
|
1999-05-03 09:29:11 +02:00
|
|
|
|
{
|
|
|
|
|
const char *p = opc->args;
|
|
|
|
|
char c;
|
|
|
|
|
unsigned long used_bits = opc->mask;
|
|
|
|
|
|
|
|
|
|
if ((used_bits & opc->match) != opc->match)
|
|
|
|
|
{
|
|
|
|
|
as_bad (_("internal: bad mips opcode (mask error): %s %s"),
|
|
|
|
|
opc->name, opc->args);
|
|
|
|
|
return 0;
|
|
|
|
|
}
|
|
|
|
|
#define USE_BITS(mask,shift) (used_bits |= ((mask) << (shift)))
|
|
|
|
|
while (*p)
|
|
|
|
|
switch (c = *p++)
|
|
|
|
|
{
|
|
|
|
|
case ',': break;
|
|
|
|
|
case '(': break;
|
|
|
|
|
case ')': break;
|
[ bfd/ChangeLog ]
2002-12-30 Chris Demetriou <cgd@broadcom.com>
* aoutx.h (NAME(aout,machine_type)): Add bfd_mach_mipsisa32r2 case.
* archures.c (bfd_mach_mipsisa32r2): New define.
* bfd-in2.h: Regenerate.
* cpu-mips.c (I_mipsisa32r2): New enum value.
(arch_info_struct): Add entry for I_mipsisa32r2.
* elfxx-mips.c (elf_mips_isa, _bfd_elf_mips_mach)
(_bfd_mips_elf_print_private_bfd_data): Handle E_MIPS_ARCH_32R2.
(_bfd_mips_elf_final_write_processing): Add
bfd_mach_mipsisa32r2 case.
(_bfd_mips_elf_merge_private_bfd_data): Handle merging of
binaries marked as using MIPS32 Release 2.
[ binutils/ChangeLog ]
2002-12-30 Chris Demetriou <cgd@broadcom.com>
* doc/binutils.texi (objdump): Note MIPS HWR (Hardware Register)
changes in MIPS -M options.
[ gas/ChangeLog ]
2002-12-30 Chris Demetriou <cgd@broadcom.com>
* configure.in: Recognize mipsisa32r2, mipsisa32r2el, and
CPU variants.
* configure: Regenerate.
* config/tc-mips.c (ISA_HAS_DROR, ISA_HAS_ROR): New defines.
(macro_build): Handle "K" operand.
(macro2): Use ISA_HAS_DROR and ISA_HAS_ROR in the places where
CPU_HAS_DROR and CPU_HAS_ROR are currently used.
(mips_ip): New variable "lastpos", and implement "+A", "+B",
and "+C" operands for MIPS32 Release 2 ins/ext instructions.
Implement "K" operand for MIPS32 Release 2 rdhwr instruction.
(validate_mips_insn): Implement "+" as a way to extend the
allowed operands, and implement "K", "+A", "+B", and "+C"
operands.
(OPTION_MIPS32R2): New define.
(md_longopts): Add entry for OPTION_MIPS32R2.
(OPTION_ELF_BASE): Adjust to accomodate OPTIONS_MIPS32R2.
(md_parse_option): Handle OPTION_MIPS32R2.
(s_mipsset): Reimplement handling of ".set mipsN" options
and add support for ".set mips32r2".
(mips_cpu_info_table): Add entry for "mips32r2" (MIPS32 Release 2).
(md_show_usage): Document "-mips32r2" option.
* doc/as.texinfo: Document "-mips32r2" option.
* doc/c-mips.texi: Likewise.
[ gas/testsuite/ChangeLog ]
2002-12-30 Chris Demetriou <cgd@broadcom.com>
* gas/mips/cp0-names-mips32r2.d: New test.
* gas/mips/hwr-names-mips32r2.d: New test.
* gas/mips/hwr-names-numeric.d: New test.
* gas/mips/hwr-names.s: New test source file.
* gas/mips/mips32r2.d: New test.
* gas/mips/mips32r2.s: New test source file.
* gas/mips/mips32r2-ill.l: New test.
* gas/mips/mips32r2-ill.s: New test source file.
* gas/mips/mips.exp: Add mips32r2 architecture data array
entry. Run new tests mentioned above.
[ include/elf/ChangeLog ]
2002-12-30 Chris Demetriou <cgd@broadcom.com>
* mips.h (E_MIPS_ARCH_32R2): New define.
[ include/opcode/ChangeLog ]
2002-12-30 Chris Demetriou <cgd@broadcom.com>
* mips.h: Document "+" as the start of two-character operand
type names, and add new "K", "+A", "+B", and "+C" operand types.
(OP_MASK_INSMSB, OP_SH_INSMSB, OP_MASK_EXTMSB)
(OP_SH_EXTMSB, INSN_ISA32R2, ISA_MIPS32R2, CPU_MIPS32R2): New
defines.
[ opcodes/ChangeLog ]
2002-12-30 Chris Demetriou <cgd@broadcom.com>
* mips-dis.c (mips_cp0_names_mips3264r2, mips_hwr_names_numeric)
(mips_hwr_names_mips3264r2): New arrays.
(mips_arch_choice): New "hwr_names" member.
(mips_arch_choices): Adjust for structure change, and add a new
entry for "mips32r2" ISA.
(mips_hwr_names): New variable.
(set_default_mips_dis_options): Set mips_hwr_names.
(parse_mips_dis_option): New "hwr-names" option which sets
mips_hwr_names, and adjust "reg-names=ARCH" to set mips_hwr_names.
(print_insn_arg): Change return type to "int"
and use that to indicate number of characters consumed.
Add support for "+" operand extension character, "+A", "+B",
"+C", and "K" operands.
(print_insn_mips): Adjust for changes to print_insn_arg.
(print_mips_disassembler_options): Adjust for "hwr-names"
addition and "reg-names" change.
* mips-opc (I33): New define (shorthand for INSN_ISA32R2).
(mips_builtin_opcodes): Note that "nop" and "ssnop" are special
forms of "sll". Add new MIPS32 Release 2 instructions: ehb,
di, ei, ext, ins, jr.hb, jalr.hb, mfhc1, mfhc2, mthc1, mthc2,
rdhwr, rdpgpr, seb, seh, synci, wrpgpr, wsbh.
Note that hardware rotate instructions (ror, rorv) can be
used on MIPS32 Release 2, and add the official mnemonics
for them (rotr, rotrv) and the similar "rotl" mnemonic for
left-rotate.
2002-12-31 08:29:29 +01:00
|
|
|
|
case '+':
|
|
|
|
|
switch (c = *p++)
|
|
|
|
|
{
|
|
|
|
|
case 'A': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break;
|
|
|
|
|
case 'B': USE_BITS (OP_MASK_INSMSB, OP_SH_INSMSB); break;
|
|
|
|
|
case 'C': USE_BITS (OP_MASK_EXTMSBD, OP_SH_EXTMSBD); break;
|
2002-12-31 09:11:18 +01:00
|
|
|
|
case 'D': USE_BITS (OP_MASK_RD, OP_SH_RD);
|
|
|
|
|
USE_BITS (OP_MASK_SEL, OP_SH_SEL); break;
|
[ bfd/ChangeLog ]
2003-09-30 Chris Demetriou <cgd@broadcom.com>
* archures.c (bfd_mach_mipsisa64r2): New define.
* bfd-in2.h: Regenerate.
* aoutx.h (NAME(aout,machine_type)): Handle bfd_mach_mipsisa64r2.
* cpu-mips.c (I_mipsisa64r2): New enum value.
(arch_info_struct): Add entry for I_mipsisa64r2.
* elfxx-mips.c (_bfd_elf_mips_mach)
(_bfd_mips_elf_print_private_bfd_data): Handle E_MIPS_ARCH_64R2.
(mips_set_isa_flags): Add bfd_mach_mipsisa64r2 case.
(mips_mach_extensions): Add entry for bfd_mach_mipsisa64r2.
[ binutils/ChangeLog ]
2003-09-30 Chris Demetriou <cgd@broadcom.com>
* readelf.c (get_machine_flags): Handle E_MIPS_ARCH_64R2.
[ gas/Changelog ]
2003-09-30 Chris Demetriou <cgd@broadcom.com>
* configure.in (mipsisa64r2, mipsisa64r2el, mipsisa64r2*): New CPUs.
* configure: Regenerate.
* config/tc-mips.c (imm2_expr): New variable.
(md_assemble, mips16_ip): Initialize imm2_expr.
(ISA_HAS_64BIT_REGS, ISA_HAS_DROR, ISA_HAS_ROR): Add ISA_MIPS64R2.
(macro_build): Handle +A, +B, +C, +E, +F, +G, and +H format operands.
(macro): Handle M_DEXT and M_DINS.
(validate_mips_insn): Handle +E, +F, +G, +H, and +I format operands.
(mips_ip): Likewise.
(OPTION_MIPS64R2): New define.
(md_longopts): New entry for -mips64r2 (OPTION_MIPS64R2).
OPTION_ASE_BASE): Increase to compensate for OPTION_MIPS64R2.
(md_parse_option): Handle OPTION_MIPS64R2.
(s_mipsset): Handle setting "mips64r2" ISA.
(mips_cpu_info_table): Add mips64r2.
(md_show_usage): Document -mips64r2 option.
* doc/as.texinfo: Docuemnt -mips64r2 option.
* doc/c-mips.texi: Likewise.
[ gas/testsuite/ChangeLog ]
2003-09-30 Chris Demetriou <cgd@broadcom.com>
* gas/mips/cp0-names-mips64r2.d: New file.
* gas/mips/cp0sel-names-mips64r2.d: New file.
* gas/mips/elf_arch_mips64r2.d: New file.
* gas/mips/hwr-names-mips64r2.d: New file.
* gas/mips/mips32r2-ill-fp64.l: New file.
* gas/mips/mips32r2-ill-fp64.s: New file.
* gas/mips/mips64r2-ill.l: New file.
* gas/mips/mips64r2-ill.s: New file.
* gas/mips/mips64r2.d: New file.
* gas/mips/mips64r2.s: New file.
* gas/mips/mips.exp: Define "mips64r2" arch, and run new tests.
[ include/elf/ChangeLog ]
2003-09-30 Chris Demetriou <cgd@broadcom.com>
* mips.h (E_MIPS_ARCH_64R2): New define.
[ include/opcode/ChangeLog ]
2003-09-30 Chris Demetriou <cgd@broadcom.com>
* mips.h: Document +E, +F, +G, +H, and +I operand types.
Update documentation of I, +B and +C operand types.
(INSN_ISA64R2, ISA_MIPS64R2, CPU_MIPS64R2): New defines.
(M_DEXT, M_DINS): New enum values.
[ ld/ChangeLog ]
2003-09-30 Chris Demetriou <cgd@broadcom.com>
* ldmain.c (get_emulation): Ignore "-mips64r2".
[ ld/testsuite/ChangeLog ]
2003-09-30 Chris Demetriou <cgd@broadcom.com>
* ld-mips-elf/mips-elf-flags.exp: Add tests for combinations
with MIPS64r2.
[ opcodes/ChangeLog ]
2003-09-30 Chris Demetriou <cgd@broadcom.com>
* mips-dis.c (mips_arch_choices): Add entry for "mips64r2"
(print_insn_args): Add handing for +E, +F, +G, and +H.
* mips-opc.c (I65): New define for MIPS64r2.
(mips_builtin_opcodes): Add "dext", "dextm", "dextu", "dins",
"dinsm", "dinsu", "drotl", "drotr", "drotr32", "drotrv", "dsbh",
and "dshd" for MIPS64r2. Adjust "dror", "dror32", and "drorv" to
be supported on MIPS64r2.
2003-09-30 18:17:15 +02:00
|
|
|
|
case 'E': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break;
|
|
|
|
|
case 'F': USE_BITS (OP_MASK_INSMSB, OP_SH_INSMSB); break;
|
|
|
|
|
case 'G': USE_BITS (OP_MASK_EXTMSBD, OP_SH_EXTMSBD); break;
|
|
|
|
|
case 'H': USE_BITS (OP_MASK_EXTMSBD, OP_SH_EXTMSBD); break;
|
|
|
|
|
case 'I': break;
|
[ bfd/ChangeLog ]
2002-12-30 Chris Demetriou <cgd@broadcom.com>
* aoutx.h (NAME(aout,machine_type)): Add bfd_mach_mipsisa32r2 case.
* archures.c (bfd_mach_mipsisa32r2): New define.
* bfd-in2.h: Regenerate.
* cpu-mips.c (I_mipsisa32r2): New enum value.
(arch_info_struct): Add entry for I_mipsisa32r2.
* elfxx-mips.c (elf_mips_isa, _bfd_elf_mips_mach)
(_bfd_mips_elf_print_private_bfd_data): Handle E_MIPS_ARCH_32R2.
(_bfd_mips_elf_final_write_processing): Add
bfd_mach_mipsisa32r2 case.
(_bfd_mips_elf_merge_private_bfd_data): Handle merging of
binaries marked as using MIPS32 Release 2.
[ binutils/ChangeLog ]
2002-12-30 Chris Demetriou <cgd@broadcom.com>
* doc/binutils.texi (objdump): Note MIPS HWR (Hardware Register)
changes in MIPS -M options.
[ gas/ChangeLog ]
2002-12-30 Chris Demetriou <cgd@broadcom.com>
* configure.in: Recognize mipsisa32r2, mipsisa32r2el, and
CPU variants.
* configure: Regenerate.
* config/tc-mips.c (ISA_HAS_DROR, ISA_HAS_ROR): New defines.
(macro_build): Handle "K" operand.
(macro2): Use ISA_HAS_DROR and ISA_HAS_ROR in the places where
CPU_HAS_DROR and CPU_HAS_ROR are currently used.
(mips_ip): New variable "lastpos", and implement "+A", "+B",
and "+C" operands for MIPS32 Release 2 ins/ext instructions.
Implement "K" operand for MIPS32 Release 2 rdhwr instruction.
(validate_mips_insn): Implement "+" as a way to extend the
allowed operands, and implement "K", "+A", "+B", and "+C"
operands.
(OPTION_MIPS32R2): New define.
(md_longopts): Add entry for OPTION_MIPS32R2.
(OPTION_ELF_BASE): Adjust to accomodate OPTIONS_MIPS32R2.
(md_parse_option): Handle OPTION_MIPS32R2.
(s_mipsset): Reimplement handling of ".set mipsN" options
and add support for ".set mips32r2".
(mips_cpu_info_table): Add entry for "mips32r2" (MIPS32 Release 2).
(md_show_usage): Document "-mips32r2" option.
* doc/as.texinfo: Document "-mips32r2" option.
* doc/c-mips.texi: Likewise.
[ gas/testsuite/ChangeLog ]
2002-12-30 Chris Demetriou <cgd@broadcom.com>
* gas/mips/cp0-names-mips32r2.d: New test.
* gas/mips/hwr-names-mips32r2.d: New test.
* gas/mips/hwr-names-numeric.d: New test.
* gas/mips/hwr-names.s: New test source file.
* gas/mips/mips32r2.d: New test.
* gas/mips/mips32r2.s: New test source file.
* gas/mips/mips32r2-ill.l: New test.
* gas/mips/mips32r2-ill.s: New test source file.
* gas/mips/mips.exp: Add mips32r2 architecture data array
entry. Run new tests mentioned above.
[ include/elf/ChangeLog ]
2002-12-30 Chris Demetriou <cgd@broadcom.com>
* mips.h (E_MIPS_ARCH_32R2): New define.
[ include/opcode/ChangeLog ]
2002-12-30 Chris Demetriou <cgd@broadcom.com>
* mips.h: Document "+" as the start of two-character operand
type names, and add new "K", "+A", "+B", and "+C" operand types.
(OP_MASK_INSMSB, OP_SH_INSMSB, OP_MASK_EXTMSB)
(OP_SH_EXTMSB, INSN_ISA32R2, ISA_MIPS32R2, CPU_MIPS32R2): New
defines.
[ opcodes/ChangeLog ]
2002-12-30 Chris Demetriou <cgd@broadcom.com>
* mips-dis.c (mips_cp0_names_mips3264r2, mips_hwr_names_numeric)
(mips_hwr_names_mips3264r2): New arrays.
(mips_arch_choice): New "hwr_names" member.
(mips_arch_choices): Adjust for structure change, and add a new
entry for "mips32r2" ISA.
(mips_hwr_names): New variable.
(set_default_mips_dis_options): Set mips_hwr_names.
(parse_mips_dis_option): New "hwr-names" option which sets
mips_hwr_names, and adjust "reg-names=ARCH" to set mips_hwr_names.
(print_insn_arg): Change return type to "int"
and use that to indicate number of characters consumed.
Add support for "+" operand extension character, "+A", "+B",
"+C", and "K" operands.
(print_insn_mips): Adjust for changes to print_insn_arg.
(print_mips_disassembler_options): Adjust for "hwr-names"
addition and "reg-names" change.
* mips-opc (I33): New define (shorthand for INSN_ISA32R2).
(mips_builtin_opcodes): Note that "nop" and "ssnop" are special
forms of "sll". Add new MIPS32 Release 2 instructions: ehb,
di, ei, ext, ins, jr.hb, jalr.hb, mfhc1, mfhc2, mthc1, mthc2,
rdhwr, rdpgpr, seb, seh, synci, wrpgpr, wsbh.
Note that hardware rotate instructions (ror, rorv) can be
used on MIPS32 Release 2, and add the official mnemonics
for them (rotr, rotrv) and the similar "rotl" mnemonic for
left-rotate.
2002-12-31 08:29:29 +01:00
|
|
|
|
default:
|
|
|
|
|
as_bad (_("internal: bad mips opcode (unknown extension operand type `+%c'): %s %s"),
|
|
|
|
|
c, opc->name, opc->args);
|
|
|
|
|
return 0;
|
|
|
|
|
}
|
|
|
|
|
break;
|
1999-05-03 09:29:11 +02:00
|
|
|
|
case '<': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break;
|
|
|
|
|
case '>': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break;
|
|
|
|
|
case 'A': break;
|
2000-12-01 21:05:32 +01:00
|
|
|
|
case 'B': USE_BITS (OP_MASK_CODE20, OP_SH_CODE20); break;
|
1999-05-03 09:29:11 +02:00
|
|
|
|
case 'C': USE_BITS (OP_MASK_COPZ, OP_SH_COPZ); break;
|
|
|
|
|
case 'D': USE_BITS (OP_MASK_FD, OP_SH_FD); break;
|
|
|
|
|
case 'E': USE_BITS (OP_MASK_RT, OP_SH_RT); break;
|
|
|
|
|
case 'F': break;
|
|
|
|
|
case 'G': USE_BITS (OP_MASK_RD, OP_SH_RD); break;
|
2000-09-14 03:47:38 +02:00
|
|
|
|
case 'H': USE_BITS (OP_MASK_SEL, OP_SH_SEL); break;
|
1999-05-03 09:29:11 +02:00
|
|
|
|
case 'I': break;
|
2000-12-12 20:29:24 +01:00
|
|
|
|
case 'J': USE_BITS (OP_MASK_CODE19, OP_SH_CODE19); break;
|
[ bfd/ChangeLog ]
2002-12-30 Chris Demetriou <cgd@broadcom.com>
* aoutx.h (NAME(aout,machine_type)): Add bfd_mach_mipsisa32r2 case.
* archures.c (bfd_mach_mipsisa32r2): New define.
* bfd-in2.h: Regenerate.
* cpu-mips.c (I_mipsisa32r2): New enum value.
(arch_info_struct): Add entry for I_mipsisa32r2.
* elfxx-mips.c (elf_mips_isa, _bfd_elf_mips_mach)
(_bfd_mips_elf_print_private_bfd_data): Handle E_MIPS_ARCH_32R2.
(_bfd_mips_elf_final_write_processing): Add
bfd_mach_mipsisa32r2 case.
(_bfd_mips_elf_merge_private_bfd_data): Handle merging of
binaries marked as using MIPS32 Release 2.
[ binutils/ChangeLog ]
2002-12-30 Chris Demetriou <cgd@broadcom.com>
* doc/binutils.texi (objdump): Note MIPS HWR (Hardware Register)
changes in MIPS -M options.
[ gas/ChangeLog ]
2002-12-30 Chris Demetriou <cgd@broadcom.com>
* configure.in: Recognize mipsisa32r2, mipsisa32r2el, and
CPU variants.
* configure: Regenerate.
* config/tc-mips.c (ISA_HAS_DROR, ISA_HAS_ROR): New defines.
(macro_build): Handle "K" operand.
(macro2): Use ISA_HAS_DROR and ISA_HAS_ROR in the places where
CPU_HAS_DROR and CPU_HAS_ROR are currently used.
(mips_ip): New variable "lastpos", and implement "+A", "+B",
and "+C" operands for MIPS32 Release 2 ins/ext instructions.
Implement "K" operand for MIPS32 Release 2 rdhwr instruction.
(validate_mips_insn): Implement "+" as a way to extend the
allowed operands, and implement "K", "+A", "+B", and "+C"
operands.
(OPTION_MIPS32R2): New define.
(md_longopts): Add entry for OPTION_MIPS32R2.
(OPTION_ELF_BASE): Adjust to accomodate OPTIONS_MIPS32R2.
(md_parse_option): Handle OPTION_MIPS32R2.
(s_mipsset): Reimplement handling of ".set mipsN" options
and add support for ".set mips32r2".
(mips_cpu_info_table): Add entry for "mips32r2" (MIPS32 Release 2).
(md_show_usage): Document "-mips32r2" option.
* doc/as.texinfo: Document "-mips32r2" option.
* doc/c-mips.texi: Likewise.
[ gas/testsuite/ChangeLog ]
2002-12-30 Chris Demetriou <cgd@broadcom.com>
* gas/mips/cp0-names-mips32r2.d: New test.
* gas/mips/hwr-names-mips32r2.d: New test.
* gas/mips/hwr-names-numeric.d: New test.
* gas/mips/hwr-names.s: New test source file.
* gas/mips/mips32r2.d: New test.
* gas/mips/mips32r2.s: New test source file.
* gas/mips/mips32r2-ill.l: New test.
* gas/mips/mips32r2-ill.s: New test source file.
* gas/mips/mips.exp: Add mips32r2 architecture data array
entry. Run new tests mentioned above.
[ include/elf/ChangeLog ]
2002-12-30 Chris Demetriou <cgd@broadcom.com>
* mips.h (E_MIPS_ARCH_32R2): New define.
[ include/opcode/ChangeLog ]
2002-12-30 Chris Demetriou <cgd@broadcom.com>
* mips.h: Document "+" as the start of two-character operand
type names, and add new "K", "+A", "+B", and "+C" operand types.
(OP_MASK_INSMSB, OP_SH_INSMSB, OP_MASK_EXTMSB)
(OP_SH_EXTMSB, INSN_ISA32R2, ISA_MIPS32R2, CPU_MIPS32R2): New
defines.
[ opcodes/ChangeLog ]
2002-12-30 Chris Demetriou <cgd@broadcom.com>
* mips-dis.c (mips_cp0_names_mips3264r2, mips_hwr_names_numeric)
(mips_hwr_names_mips3264r2): New arrays.
(mips_arch_choice): New "hwr_names" member.
(mips_arch_choices): Adjust for structure change, and add a new
entry for "mips32r2" ISA.
(mips_hwr_names): New variable.
(set_default_mips_dis_options): Set mips_hwr_names.
(parse_mips_dis_option): New "hwr-names" option which sets
mips_hwr_names, and adjust "reg-names=ARCH" to set mips_hwr_names.
(print_insn_arg): Change return type to "int"
and use that to indicate number of characters consumed.
Add support for "+" operand extension character, "+A", "+B",
"+C", and "K" operands.
(print_insn_mips): Adjust for changes to print_insn_arg.
(print_mips_disassembler_options): Adjust for "hwr-names"
addition and "reg-names" change.
* mips-opc (I33): New define (shorthand for INSN_ISA32R2).
(mips_builtin_opcodes): Note that "nop" and "ssnop" are special
forms of "sll". Add new MIPS32 Release 2 instructions: ehb,
di, ei, ext, ins, jr.hb, jalr.hb, mfhc1, mfhc2, mthc1, mthc2,
rdhwr, rdpgpr, seb, seh, synci, wrpgpr, wsbh.
Note that hardware rotate instructions (ror, rorv) can be
used on MIPS32 Release 2, and add the official mnemonics
for them (rotr, rotrv) and the similar "rotl" mnemonic for
left-rotate.
2002-12-31 08:29:29 +01:00
|
|
|
|
case 'K': USE_BITS (OP_MASK_RD, OP_SH_RD); break;
|
1999-05-03 09:29:11 +02:00
|
|
|
|
case 'L': break;
|
|
|
|
|
case 'M': USE_BITS (OP_MASK_CCC, OP_SH_CCC); break;
|
|
|
|
|
case 'N': USE_BITS (OP_MASK_BCC, OP_SH_BCC); break;
|
[ gas/ChangeLog ]
2002-05-30 Chris G. Demetriou <cgd@broadcom.com>
Ed Satterthwaite <ehs@broadcom.com>
* config/tc-mips.c (mips_set_options): New "ase_mdmx" member.
(mips_opts): Initialize "ase_mdmx" member.
(file_ase_mdmx): New variable.
(CPU_HAS_MDMX): New macro.
(md_begin): Initialize mips_opts.ase_mdmx and file_ase_mdmx
based on command line options and configuration defaults.
(macro_build): Note in comment that use of MDMX in macros is
not currently allowed.
(validate_mips_insn): Add support for the "O", "Q", "X", "Y", and
"Z" MDMX operand types.
(mips_ip): Accept MDMX instructions if mips_opts.ase_mdmx is set,
and add support for the "O", "Q", "X", "Y", and "Z" MDMX operand
types.
(OPTION_MDMX, OPTION_NO_MDMX, md_longopts, md_parse_option):
Add support for "-mdmx" and "-no-mdmx" options.
(OPTION_ELF_BASE): Move to accomodate new options.
(s_mipsset): Support ".set mdmx" and ".set nomdmx".
(mips_elf_final_processing): Set MDMX ASE ELF header flag if
file_ase_mdmx was set.
* doc/as.texinfo: Document -mdmx and -no-mdmx options.
* doc/c-mips.texi: Likewise, and document ".set mdmx" and ".set
nomdmx" directives.
[ gas/testsuite/ChangeLog ]
2002-05-30 Chris G. Demetriou <cgd@broadcom.com>
* gas/mips/mips64-mdmx.s: New file.
* gas/mips/mips64-mdmx.d: Likewise.
* gas/mips/mips.exp: Run new "mips64-mdmx" test.
[ include/opcode/ChangeLog ]
2002-05-30 Chris G. Demetriou <cgd@broadcom.com>
* mips.h (OP_SH_ALN, OP_MASK_ALN, OP_SH_VSEL, OP_MASK_VSEL)
(MDMX_FMTSEL_IMM_QH, MDMX_FMTSEL_IMM_OB, MDMX_FMTSEL_VEC_QH)
(MDMX_FMTSEL_VEC_OB, INSN_READ_MDMX_ACC, INSN_WRITE_MDMX_ACC)
(INSN_MDMX): New constants, for MDMX support.
(opcode character list): Add "O", "Q", "X", "Y", and "Z" for MDMX.
[ opcodes/ChangeLog ]
2002-05-30 Chris G. Demetriou <cgd@broadcom.com>
Ed Satterthwaite <ehs@broadcom.com>
* mips-dis.c (print_insn_arg): Add support for 'O', 'Q', 'X', 'Y',
and 'Z' formats, for MDMX.
(mips_isa_type): Add MDMX instructions to the ISA
bit mask for bfd_mach_mipsisa64.
* mips-opc.c: Add support for MDMX instructions.
(MX): New definition.
* mips-dis.c: Update copyright years to include 2002.
2002-05-31 03:17:18 +02:00
|
|
|
|
case 'O': USE_BITS (OP_MASK_ALN, OP_SH_ALN); break;
|
|
|
|
|
case 'Q': USE_BITS (OP_MASK_VSEL, OP_SH_VSEL);
|
|
|
|
|
USE_BITS (OP_MASK_FT, OP_SH_FT); break;
|
1999-05-03 09:29:11 +02:00
|
|
|
|
case 'R': USE_BITS (OP_MASK_FR, OP_SH_FR); break;
|
|
|
|
|
case 'S': USE_BITS (OP_MASK_FS, OP_SH_FS); break;
|
|
|
|
|
case 'T': USE_BITS (OP_MASK_FT, OP_SH_FT); break;
|
|
|
|
|
case 'V': USE_BITS (OP_MASK_FS, OP_SH_FS); break;
|
|
|
|
|
case 'W': USE_BITS (OP_MASK_FT, OP_SH_FT); break;
|
[ gas/ChangeLog ]
2002-05-30 Chris G. Demetriou <cgd@broadcom.com>
Ed Satterthwaite <ehs@broadcom.com>
* config/tc-mips.c (mips_set_options): New "ase_mdmx" member.
(mips_opts): Initialize "ase_mdmx" member.
(file_ase_mdmx): New variable.
(CPU_HAS_MDMX): New macro.
(md_begin): Initialize mips_opts.ase_mdmx and file_ase_mdmx
based on command line options and configuration defaults.
(macro_build): Note in comment that use of MDMX in macros is
not currently allowed.
(validate_mips_insn): Add support for the "O", "Q", "X", "Y", and
"Z" MDMX operand types.
(mips_ip): Accept MDMX instructions if mips_opts.ase_mdmx is set,
and add support for the "O", "Q", "X", "Y", and "Z" MDMX operand
types.
(OPTION_MDMX, OPTION_NO_MDMX, md_longopts, md_parse_option):
Add support for "-mdmx" and "-no-mdmx" options.
(OPTION_ELF_BASE): Move to accomodate new options.
(s_mipsset): Support ".set mdmx" and ".set nomdmx".
(mips_elf_final_processing): Set MDMX ASE ELF header flag if
file_ase_mdmx was set.
* doc/as.texinfo: Document -mdmx and -no-mdmx options.
* doc/c-mips.texi: Likewise, and document ".set mdmx" and ".set
nomdmx" directives.
[ gas/testsuite/ChangeLog ]
2002-05-30 Chris G. Demetriou <cgd@broadcom.com>
* gas/mips/mips64-mdmx.s: New file.
* gas/mips/mips64-mdmx.d: Likewise.
* gas/mips/mips.exp: Run new "mips64-mdmx" test.
[ include/opcode/ChangeLog ]
2002-05-30 Chris G. Demetriou <cgd@broadcom.com>
* mips.h (OP_SH_ALN, OP_MASK_ALN, OP_SH_VSEL, OP_MASK_VSEL)
(MDMX_FMTSEL_IMM_QH, MDMX_FMTSEL_IMM_OB, MDMX_FMTSEL_VEC_QH)
(MDMX_FMTSEL_VEC_OB, INSN_READ_MDMX_ACC, INSN_WRITE_MDMX_ACC)
(INSN_MDMX): New constants, for MDMX support.
(opcode character list): Add "O", "Q", "X", "Y", and "Z" for MDMX.
[ opcodes/ChangeLog ]
2002-05-30 Chris G. Demetriou <cgd@broadcom.com>
Ed Satterthwaite <ehs@broadcom.com>
* mips-dis.c (print_insn_arg): Add support for 'O', 'Q', 'X', 'Y',
and 'Z' formats, for MDMX.
(mips_isa_type): Add MDMX instructions to the ISA
bit mask for bfd_mach_mipsisa64.
* mips-opc.c: Add support for MDMX instructions.
(MX): New definition.
* mips-dis.c: Update copyright years to include 2002.
2002-05-31 03:17:18 +02:00
|
|
|
|
case 'X': USE_BITS (OP_MASK_FD, OP_SH_FD); break;
|
|
|
|
|
case 'Y': USE_BITS (OP_MASK_FS, OP_SH_FS); break;
|
|
|
|
|
case 'Z': USE_BITS (OP_MASK_FT, OP_SH_FT); break;
|
1999-05-03 09:29:11 +02:00
|
|
|
|
case 'a': USE_BITS (OP_MASK_TARGET, OP_SH_TARGET); break;
|
|
|
|
|
case 'b': USE_BITS (OP_MASK_RS, OP_SH_RS); break;
|
|
|
|
|
case 'c': USE_BITS (OP_MASK_CODE, OP_SH_CODE); break;
|
|
|
|
|
case 'd': USE_BITS (OP_MASK_RD, OP_SH_RD); break;
|
|
|
|
|
case 'f': break;
|
|
|
|
|
case 'h': USE_BITS (OP_MASK_PREFX, OP_SH_PREFX); break;
|
|
|
|
|
case 'i': USE_BITS (OP_MASK_IMMEDIATE, OP_SH_IMMEDIATE); break;
|
|
|
|
|
case 'j': USE_BITS (OP_MASK_DELTA, OP_SH_DELTA); break;
|
|
|
|
|
case 'k': USE_BITS (OP_MASK_CACHE, OP_SH_CACHE); break;
|
|
|
|
|
case 'l': break;
|
|
|
|
|
case 'o': USE_BITS (OP_MASK_DELTA, OP_SH_DELTA); break;
|
|
|
|
|
case 'p': USE_BITS (OP_MASK_DELTA, OP_SH_DELTA); break;
|
|
|
|
|
case 'q': USE_BITS (OP_MASK_CODE2, OP_SH_CODE2); break;
|
|
|
|
|
case 'r': USE_BITS (OP_MASK_RS, OP_SH_RS); break;
|
|
|
|
|
case 's': USE_BITS (OP_MASK_RS, OP_SH_RS); break;
|
|
|
|
|
case 't': USE_BITS (OP_MASK_RT, OP_SH_RT); break;
|
|
|
|
|
case 'u': USE_BITS (OP_MASK_IMMEDIATE, OP_SH_IMMEDIATE); break;
|
|
|
|
|
case 'v': USE_BITS (OP_MASK_RS, OP_SH_RS); break;
|
|
|
|
|
case 'w': USE_BITS (OP_MASK_RT, OP_SH_RT); break;
|
|
|
|
|
case 'x': break;
|
|
|
|
|
case 'z': break;
|
|
|
|
|
case 'P': USE_BITS (OP_MASK_PERFREG, OP_SH_PERFREG); break;
|
2000-12-01 21:05:32 +01:00
|
|
|
|
case 'U': USE_BITS (OP_MASK_RD, OP_SH_RD);
|
|
|
|
|
USE_BITS (OP_MASK_RT, OP_SH_RT); break;
|
[gas/]
* doc/c-mips.texi: Add entries for -march=vr4120,vr4130,vr4181,
vr5400 and vr5500. Add entry for -mfix-vr4122-bugs.
* config/tc-mips.c (CPU_HAS_DROR, CPU_HAS_ROR): New macros.
(hilo_interlocks): True for CPU_VR5500.
(gpr_interlocks, cop_interlocks): True for CPU_VR5400 and CPU_VR5500.
(mips_fix_vr4122_bugs): New.
(append_insn): Work around 4122 errors if mips_fix_vr4122_bugs.
(mips_emit_delays): Likewise.
(macro2) [M_DROLI]: Use dror or dror32 if CPU_HAS_DROR.
[M_ROLI]: Likewise ror if CPU_HAS_ROR.
(validate_mips_insn, mips_ip): Handle '[', ']', 'e' and '%'.
(OPTION_FIX_VR4122, OPTION_NO_FIX_VR4122): New options.
(md_longopts): Add -mfix-vr4122-bugs and -no-mfix-vr4122-bugs.
(OPTION_ELF_BASE): Bump.
(md_parse_option): Handle the new options.
(mips_cpu_info_table): Add entries for vr4120, vr4130, vr4181,
vr5400 and vr5500.
[gas/testsuite/]
* gas/mips/mips4100.[sd]: Move dmadd16 and madd16 checks to...
* gas/mips/vr4111.[sd]: ...this new test.
* gas/mips/vr4120.[sd],
* gas/mips/vr4122.[sd],
* gas/mips/vr5400.[sd],
* gas/mips/vr5500.[sd]: New tests.
* mips.exp: Run them.
2002-09-30 14:04:54 +02:00
|
|
|
|
case 'e': USE_BITS (OP_MASK_VECBYTE, OP_SH_VECBYTE); break;
|
|
|
|
|
case '%': USE_BITS (OP_MASK_VECALIGN, OP_SH_VECALIGN); break;
|
|
|
|
|
case '[': break;
|
|
|
|
|
case ']': break;
|
1999-05-03 09:29:11 +02:00
|
|
|
|
default:
|
|
|
|
|
as_bad (_("internal: bad mips opcode (unknown operand type `%c'): %s %s"),
|
|
|
|
|
c, opc->name, opc->args);
|
|
|
|
|
return 0;
|
|
|
|
|
}
|
|
|
|
|
#undef USE_BITS
|
|
|
|
|
if (used_bits != 0xffffffff)
|
|
|
|
|
{
|
|
|
|
|
as_bad (_("internal: bad mips opcode (bits 0x%lx undefined): %s %s"),
|
|
|
|
|
~used_bits & 0xffffffff, opc->name, opc->args);
|
|
|
|
|
return 0;
|
|
|
|
|
}
|
|
|
|
|
return 1;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/* This routine assembles an instruction into its binary format. As a
|
|
|
|
|
side effect, it sets one of the global variables imm_reloc or
|
|
|
|
|
offset_reloc to the type of relocation to do if one of the operands
|
|
|
|
|
is an address expression. */
|
|
|
|
|
|
|
|
|
|
static void
|
2003-06-30 14:44:25 +02:00
|
|
|
|
mips_ip (char *str, struct mips_cl_insn *ip)
|
1999-05-03 09:29:11 +02:00
|
|
|
|
{
|
|
|
|
|
char *s;
|
|
|
|
|
const char *args;
|
2000-05-30 00:05:27 +02:00
|
|
|
|
char c = 0;
|
1999-05-03 09:29:11 +02:00
|
|
|
|
struct mips_opcode *insn;
|
|
|
|
|
char *argsStart;
|
|
|
|
|
unsigned int regno;
|
|
|
|
|
unsigned int lastregno = 0;
|
[ bfd/ChangeLog ]
2002-12-30 Chris Demetriou <cgd@broadcom.com>
* aoutx.h (NAME(aout,machine_type)): Add bfd_mach_mipsisa32r2 case.
* archures.c (bfd_mach_mipsisa32r2): New define.
* bfd-in2.h: Regenerate.
* cpu-mips.c (I_mipsisa32r2): New enum value.
(arch_info_struct): Add entry for I_mipsisa32r2.
* elfxx-mips.c (elf_mips_isa, _bfd_elf_mips_mach)
(_bfd_mips_elf_print_private_bfd_data): Handle E_MIPS_ARCH_32R2.
(_bfd_mips_elf_final_write_processing): Add
bfd_mach_mipsisa32r2 case.
(_bfd_mips_elf_merge_private_bfd_data): Handle merging of
binaries marked as using MIPS32 Release 2.
[ binutils/ChangeLog ]
2002-12-30 Chris Demetriou <cgd@broadcom.com>
* doc/binutils.texi (objdump): Note MIPS HWR (Hardware Register)
changes in MIPS -M options.
[ gas/ChangeLog ]
2002-12-30 Chris Demetriou <cgd@broadcom.com>
* configure.in: Recognize mipsisa32r2, mipsisa32r2el, and
CPU variants.
* configure: Regenerate.
* config/tc-mips.c (ISA_HAS_DROR, ISA_HAS_ROR): New defines.
(macro_build): Handle "K" operand.
(macro2): Use ISA_HAS_DROR and ISA_HAS_ROR in the places where
CPU_HAS_DROR and CPU_HAS_ROR are currently used.
(mips_ip): New variable "lastpos", and implement "+A", "+B",
and "+C" operands for MIPS32 Release 2 ins/ext instructions.
Implement "K" operand for MIPS32 Release 2 rdhwr instruction.
(validate_mips_insn): Implement "+" as a way to extend the
allowed operands, and implement "K", "+A", "+B", and "+C"
operands.
(OPTION_MIPS32R2): New define.
(md_longopts): Add entry for OPTION_MIPS32R2.
(OPTION_ELF_BASE): Adjust to accomodate OPTIONS_MIPS32R2.
(md_parse_option): Handle OPTION_MIPS32R2.
(s_mipsset): Reimplement handling of ".set mipsN" options
and add support for ".set mips32r2".
(mips_cpu_info_table): Add entry for "mips32r2" (MIPS32 Release 2).
(md_show_usage): Document "-mips32r2" option.
* doc/as.texinfo: Document "-mips32r2" option.
* doc/c-mips.texi: Likewise.
[ gas/testsuite/ChangeLog ]
2002-12-30 Chris Demetriou <cgd@broadcom.com>
* gas/mips/cp0-names-mips32r2.d: New test.
* gas/mips/hwr-names-mips32r2.d: New test.
* gas/mips/hwr-names-numeric.d: New test.
* gas/mips/hwr-names.s: New test source file.
* gas/mips/mips32r2.d: New test.
* gas/mips/mips32r2.s: New test source file.
* gas/mips/mips32r2-ill.l: New test.
* gas/mips/mips32r2-ill.s: New test source file.
* gas/mips/mips.exp: Add mips32r2 architecture data array
entry. Run new tests mentioned above.
[ include/elf/ChangeLog ]
2002-12-30 Chris Demetriou <cgd@broadcom.com>
* mips.h (E_MIPS_ARCH_32R2): New define.
[ include/opcode/ChangeLog ]
2002-12-30 Chris Demetriou <cgd@broadcom.com>
* mips.h: Document "+" as the start of two-character operand
type names, and add new "K", "+A", "+B", and "+C" operand types.
(OP_MASK_INSMSB, OP_SH_INSMSB, OP_MASK_EXTMSB)
(OP_SH_EXTMSB, INSN_ISA32R2, ISA_MIPS32R2, CPU_MIPS32R2): New
defines.
[ opcodes/ChangeLog ]
2002-12-30 Chris Demetriou <cgd@broadcom.com>
* mips-dis.c (mips_cp0_names_mips3264r2, mips_hwr_names_numeric)
(mips_hwr_names_mips3264r2): New arrays.
(mips_arch_choice): New "hwr_names" member.
(mips_arch_choices): Adjust for structure change, and add a new
entry for "mips32r2" ISA.
(mips_hwr_names): New variable.
(set_default_mips_dis_options): Set mips_hwr_names.
(parse_mips_dis_option): New "hwr-names" option which sets
mips_hwr_names, and adjust "reg-names=ARCH" to set mips_hwr_names.
(print_insn_arg): Change return type to "int"
and use that to indicate number of characters consumed.
Add support for "+" operand extension character, "+A", "+B",
"+C", and "K" operands.
(print_insn_mips): Adjust for changes to print_insn_arg.
(print_mips_disassembler_options): Adjust for "hwr-names"
addition and "reg-names" change.
* mips-opc (I33): New define (shorthand for INSN_ISA32R2).
(mips_builtin_opcodes): Note that "nop" and "ssnop" are special
forms of "sll". Add new MIPS32 Release 2 instructions: ehb,
di, ei, ext, ins, jr.hb, jalr.hb, mfhc1, mfhc2, mthc1, mthc2,
rdhwr, rdpgpr, seb, seh, synci, wrpgpr, wsbh.
Note that hardware rotate instructions (ror, rorv) can be
used on MIPS32 Release 2, and add the official mnemonics
for them (rotr, rotrv) and the similar "rotl" mnemonic for
left-rotate.
2002-12-31 08:29:29 +01:00
|
|
|
|
unsigned int lastpos = 0;
|
2003-01-02 21:03:09 +01:00
|
|
|
|
unsigned int limlo, limhi;
|
1999-05-03 09:29:11 +02:00
|
|
|
|
char *s_reset;
|
|
|
|
|
char save_c = 0;
|
|
|
|
|
|
|
|
|
|
insn_error = NULL;
|
|
|
|
|
|
|
|
|
|
/* If the instruction contains a '.', we first try to match an instruction
|
|
|
|
|
including the '.'. Then we try again without the '.'. */
|
|
|
|
|
insn = NULL;
|
2001-09-19 07:33:36 +02:00
|
|
|
|
for (s = str; *s != '\0' && !ISSPACE (*s); ++s)
|
1999-05-03 09:29:11 +02:00
|
|
|
|
continue;
|
|
|
|
|
|
|
|
|
|
/* If we stopped on whitespace, then replace the whitespace with null for
|
|
|
|
|
the call to hash_find. Save the character we replaced just in case we
|
|
|
|
|
have to re-parse the instruction. */
|
2001-09-19 07:33:36 +02:00
|
|
|
|
if (ISSPACE (*s))
|
1999-05-03 09:29:11 +02:00
|
|
|
|
{
|
|
|
|
|
save_c = *s;
|
|
|
|
|
*s++ = '\0';
|
|
|
|
|
}
|
2000-09-07 14:45:56 +02:00
|
|
|
|
|
1999-05-03 09:29:11 +02:00
|
|
|
|
insn = (struct mips_opcode *) hash_find (op_hash, str);
|
|
|
|
|
|
|
|
|
|
/* If we didn't find the instruction in the opcode table, try again, but
|
|
|
|
|
this time with just the instruction up to, but not including the
|
|
|
|
|
first '.'. */
|
|
|
|
|
if (insn == NULL)
|
|
|
|
|
{
|
2000-09-07 14:45:56 +02:00
|
|
|
|
/* Restore the character we overwrite above (if any). */
|
1999-05-03 09:29:11 +02:00
|
|
|
|
if (save_c)
|
|
|
|
|
*(--s) = save_c;
|
|
|
|
|
|
|
|
|
|
/* Scan up to the first '.' or whitespace. */
|
2001-09-19 07:33:36 +02:00
|
|
|
|
for (s = str;
|
|
|
|
|
*s != '\0' && *s != '.' && !ISSPACE (*s);
|
|
|
|
|
++s)
|
1999-05-03 09:29:11 +02:00
|
|
|
|
continue;
|
|
|
|
|
|
|
|
|
|
/* If we did not find a '.', then we can quit now. */
|
|
|
|
|
if (*s != '.')
|
|
|
|
|
{
|
|
|
|
|
insn_error = "unrecognized opcode";
|
|
|
|
|
return;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/* Lookup the instruction in the hash table. */
|
|
|
|
|
*s++ = '\0';
|
|
|
|
|
if ((insn = (struct mips_opcode *) hash_find (op_hash, str)) == NULL)
|
|
|
|
|
{
|
|
|
|
|
insn_error = "unrecognized opcode";
|
|
|
|
|
return;
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
argsStart = s;
|
|
|
|
|
for (;;)
|
|
|
|
|
{
|
2002-11-30 09:39:46 +01:00
|
|
|
|
bfd_boolean ok;
|
1999-05-03 09:29:11 +02:00
|
|
|
|
|
|
|
|
|
assert (strcmp (insn->name, str) == 0);
|
|
|
|
|
|
2002-03-16 04:09:19 +01:00
|
|
|
|
if (OPCODE_IS_MEMBER (insn,
|
|
|
|
|
(mips_opts.isa
|
2002-09-26 11:56:35 +02:00
|
|
|
|
| (file_ase_mips16 ? INSN_MIPS16 : 0)
|
[ gas/ChangeLog ]
2002-05-30 Chris G. Demetriou <cgd@broadcom.com>
Ed Satterthwaite <ehs@broadcom.com>
* config/tc-mips.c (mips_set_options): New "ase_mdmx" member.
(mips_opts): Initialize "ase_mdmx" member.
(file_ase_mdmx): New variable.
(CPU_HAS_MDMX): New macro.
(md_begin): Initialize mips_opts.ase_mdmx and file_ase_mdmx
based on command line options and configuration defaults.
(macro_build): Note in comment that use of MDMX in macros is
not currently allowed.
(validate_mips_insn): Add support for the "O", "Q", "X", "Y", and
"Z" MDMX operand types.
(mips_ip): Accept MDMX instructions if mips_opts.ase_mdmx is set,
and add support for the "O", "Q", "X", "Y", and "Z" MDMX operand
types.
(OPTION_MDMX, OPTION_NO_MDMX, md_longopts, md_parse_option):
Add support for "-mdmx" and "-no-mdmx" options.
(OPTION_ELF_BASE): Move to accomodate new options.
(s_mipsset): Support ".set mdmx" and ".set nomdmx".
(mips_elf_final_processing): Set MDMX ASE ELF header flag if
file_ase_mdmx was set.
* doc/as.texinfo: Document -mdmx and -no-mdmx options.
* doc/c-mips.texi: Likewise, and document ".set mdmx" and ".set
nomdmx" directives.
[ gas/testsuite/ChangeLog ]
2002-05-30 Chris G. Demetriou <cgd@broadcom.com>
* gas/mips/mips64-mdmx.s: New file.
* gas/mips/mips64-mdmx.d: Likewise.
* gas/mips/mips.exp: Run new "mips64-mdmx" test.
[ include/opcode/ChangeLog ]
2002-05-30 Chris G. Demetriou <cgd@broadcom.com>
* mips.h (OP_SH_ALN, OP_MASK_ALN, OP_SH_VSEL, OP_MASK_VSEL)
(MDMX_FMTSEL_IMM_QH, MDMX_FMTSEL_IMM_OB, MDMX_FMTSEL_VEC_QH)
(MDMX_FMTSEL_VEC_OB, INSN_READ_MDMX_ACC, INSN_WRITE_MDMX_ACC)
(INSN_MDMX): New constants, for MDMX support.
(opcode character list): Add "O", "Q", "X", "Y", and "Z" for MDMX.
[ opcodes/ChangeLog ]
2002-05-30 Chris G. Demetriou <cgd@broadcom.com>
Ed Satterthwaite <ehs@broadcom.com>
* mips-dis.c (print_insn_arg): Add support for 'O', 'Q', 'X', 'Y',
and 'Z' formats, for MDMX.
(mips_isa_type): Add MDMX instructions to the ISA
bit mask for bfd_mach_mipsisa64.
* mips-opc.c: Add support for MDMX instructions.
(MX): New definition.
* mips-dis.c: Update copyright years to include 2002.
2002-05-31 03:17:18 +02:00
|
|
|
|
| (mips_opts.ase_mdmx ? INSN_MDMX : 0)
|
2002-05-04 19:38:00 +02:00
|
|
|
|
| (mips_opts.ase_mips3d ? INSN_MIPS3D : 0)),
|
2003-06-29 21:41:33 +02:00
|
|
|
|
mips_opts.arch))
|
2002-11-30 09:39:46 +01:00
|
|
|
|
ok = TRUE;
|
2000-09-07 14:45:56 +02:00
|
|
|
|
else
|
2002-11-30 09:39:46 +01:00
|
|
|
|
ok = FALSE;
|
2000-09-07 14:45:56 +02:00
|
|
|
|
|
1999-05-03 09:29:11 +02:00
|
|
|
|
if (insn->pinfo != INSN_MACRO)
|
|
|
|
|
{
|
2003-06-29 21:41:33 +02:00
|
|
|
|
if (mips_opts.arch == CPU_R4650 && (insn->pinfo & FP_D) != 0)
|
2002-11-30 09:39:46 +01:00
|
|
|
|
ok = FALSE;
|
1999-05-03 09:29:11 +02:00
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
if (! ok)
|
|
|
|
|
{
|
|
|
|
|
if (insn + 1 < &mips_opcodes[NUMOPCODES]
|
|
|
|
|
&& strcmp (insn->name, insn[1].name) == 0)
|
|
|
|
|
{
|
|
|
|
|
++insn;
|
|
|
|
|
continue;
|
|
|
|
|
}
|
|
|
|
|
else
|
2000-12-05 19:51:08 +01:00
|
|
|
|
{
|
2001-06-09 07:01:29 +02:00
|
|
|
|
if (!insn_error)
|
|
|
|
|
{
|
|
|
|
|
static char buf[100];
|
2003-06-29 21:41:33 +02:00
|
|
|
|
sprintf (buf,
|
|
|
|
|
_("opcode not supported on this processor: %s (%s)"),
|
|
|
|
|
mips_cpu_info_from_arch (mips_opts.arch)->name,
|
|
|
|
|
mips_cpu_info_from_isa (mips_opts.isa)->name);
|
2001-06-09 07:01:29 +02:00
|
|
|
|
insn_error = buf;
|
|
|
|
|
}
|
|
|
|
|
if (save_c)
|
|
|
|
|
*(--s) = save_c;
|
1999-11-01 20:29:55 +01:00
|
|
|
|
return;
|
1999-05-03 09:29:11 +02:00
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
ip->insn_mo = insn;
|
|
|
|
|
ip->insn_opcode = insn->match;
|
2001-06-09 07:01:29 +02:00
|
|
|
|
insn_error = NULL;
|
1999-05-03 09:29:11 +02:00
|
|
|
|
for (args = insn->args;; ++args)
|
|
|
|
|
{
|
[ gas/ChangeLog ]
2002-05-30 Chris G. Demetriou <cgd@broadcom.com>
Ed Satterthwaite <ehs@broadcom.com>
* config/tc-mips.c (mips_set_options): New "ase_mdmx" member.
(mips_opts): Initialize "ase_mdmx" member.
(file_ase_mdmx): New variable.
(CPU_HAS_MDMX): New macro.
(md_begin): Initialize mips_opts.ase_mdmx and file_ase_mdmx
based on command line options and configuration defaults.
(macro_build): Note in comment that use of MDMX in macros is
not currently allowed.
(validate_mips_insn): Add support for the "O", "Q", "X", "Y", and
"Z" MDMX operand types.
(mips_ip): Accept MDMX instructions if mips_opts.ase_mdmx is set,
and add support for the "O", "Q", "X", "Y", and "Z" MDMX operand
types.
(OPTION_MDMX, OPTION_NO_MDMX, md_longopts, md_parse_option):
Add support for "-mdmx" and "-no-mdmx" options.
(OPTION_ELF_BASE): Move to accomodate new options.
(s_mipsset): Support ".set mdmx" and ".set nomdmx".
(mips_elf_final_processing): Set MDMX ASE ELF header flag if
file_ase_mdmx was set.
* doc/as.texinfo: Document -mdmx and -no-mdmx options.
* doc/c-mips.texi: Likewise, and document ".set mdmx" and ".set
nomdmx" directives.
[ gas/testsuite/ChangeLog ]
2002-05-30 Chris G. Demetriou <cgd@broadcom.com>
* gas/mips/mips64-mdmx.s: New file.
* gas/mips/mips64-mdmx.d: Likewise.
* gas/mips/mips.exp: Run new "mips64-mdmx" test.
[ include/opcode/ChangeLog ]
2002-05-30 Chris G. Demetriou <cgd@broadcom.com>
* mips.h (OP_SH_ALN, OP_MASK_ALN, OP_SH_VSEL, OP_MASK_VSEL)
(MDMX_FMTSEL_IMM_QH, MDMX_FMTSEL_IMM_OB, MDMX_FMTSEL_VEC_QH)
(MDMX_FMTSEL_VEC_OB, INSN_READ_MDMX_ACC, INSN_WRITE_MDMX_ACC)
(INSN_MDMX): New constants, for MDMX support.
(opcode character list): Add "O", "Q", "X", "Y", and "Z" for MDMX.
[ opcodes/ChangeLog ]
2002-05-30 Chris G. Demetriou <cgd@broadcom.com>
Ed Satterthwaite <ehs@broadcom.com>
* mips-dis.c (print_insn_arg): Add support for 'O', 'Q', 'X', 'Y',
and 'Z' formats, for MDMX.
(mips_isa_type): Add MDMX instructions to the ISA
bit mask for bfd_mach_mipsisa64.
* mips-opc.c: Add support for MDMX instructions.
(MX): New definition.
* mips-dis.c: Update copyright years to include 2002.
2002-05-31 03:17:18 +02:00
|
|
|
|
int is_mdmx;
|
|
|
|
|
|
2001-10-10 02:54:53 +02:00
|
|
|
|
s += strspn (s, " \t");
|
[ gas/ChangeLog ]
2002-05-30 Chris G. Demetriou <cgd@broadcom.com>
Ed Satterthwaite <ehs@broadcom.com>
* config/tc-mips.c (mips_set_options): New "ase_mdmx" member.
(mips_opts): Initialize "ase_mdmx" member.
(file_ase_mdmx): New variable.
(CPU_HAS_MDMX): New macro.
(md_begin): Initialize mips_opts.ase_mdmx and file_ase_mdmx
based on command line options and configuration defaults.
(macro_build): Note in comment that use of MDMX in macros is
not currently allowed.
(validate_mips_insn): Add support for the "O", "Q", "X", "Y", and
"Z" MDMX operand types.
(mips_ip): Accept MDMX instructions if mips_opts.ase_mdmx is set,
and add support for the "O", "Q", "X", "Y", and "Z" MDMX operand
types.
(OPTION_MDMX, OPTION_NO_MDMX, md_longopts, md_parse_option):
Add support for "-mdmx" and "-no-mdmx" options.
(OPTION_ELF_BASE): Move to accomodate new options.
(s_mipsset): Support ".set mdmx" and ".set nomdmx".
(mips_elf_final_processing): Set MDMX ASE ELF header flag if
file_ase_mdmx was set.
* doc/as.texinfo: Document -mdmx and -no-mdmx options.
* doc/c-mips.texi: Likewise, and document ".set mdmx" and ".set
nomdmx" directives.
[ gas/testsuite/ChangeLog ]
2002-05-30 Chris G. Demetriou <cgd@broadcom.com>
* gas/mips/mips64-mdmx.s: New file.
* gas/mips/mips64-mdmx.d: Likewise.
* gas/mips/mips.exp: Run new "mips64-mdmx" test.
[ include/opcode/ChangeLog ]
2002-05-30 Chris G. Demetriou <cgd@broadcom.com>
* mips.h (OP_SH_ALN, OP_MASK_ALN, OP_SH_VSEL, OP_MASK_VSEL)
(MDMX_FMTSEL_IMM_QH, MDMX_FMTSEL_IMM_OB, MDMX_FMTSEL_VEC_QH)
(MDMX_FMTSEL_VEC_OB, INSN_READ_MDMX_ACC, INSN_WRITE_MDMX_ACC)
(INSN_MDMX): New constants, for MDMX support.
(opcode character list): Add "O", "Q", "X", "Y", and "Z" for MDMX.
[ opcodes/ChangeLog ]
2002-05-30 Chris G. Demetriou <cgd@broadcom.com>
Ed Satterthwaite <ehs@broadcom.com>
* mips-dis.c (print_insn_arg): Add support for 'O', 'Q', 'X', 'Y',
and 'Z' formats, for MDMX.
(mips_isa_type): Add MDMX instructions to the ISA
bit mask for bfd_mach_mipsisa64.
* mips-opc.c: Add support for MDMX instructions.
(MX): New definition.
* mips-dis.c: Update copyright years to include 2002.
2002-05-31 03:17:18 +02:00
|
|
|
|
is_mdmx = 0;
|
1999-05-03 09:29:11 +02:00
|
|
|
|
switch (*args)
|
|
|
|
|
{
|
|
|
|
|
case '\0': /* end of args */
|
|
|
|
|
if (*s == '\0')
|
|
|
|
|
return;
|
|
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
case ',':
|
|
|
|
|
if (*s++ == *args)
|
|
|
|
|
continue;
|
|
|
|
|
s--;
|
|
|
|
|
switch (*++args)
|
|
|
|
|
{
|
|
|
|
|
case 'r':
|
|
|
|
|
case 'v':
|
2001-08-07 15:22:46 +02:00
|
|
|
|
ip->insn_opcode |= lastregno << OP_SH_RS;
|
1999-05-03 09:29:11 +02:00
|
|
|
|
continue;
|
|
|
|
|
|
|
|
|
|
case 'w':
|
2001-08-07 15:22:46 +02:00
|
|
|
|
ip->insn_opcode |= lastregno << OP_SH_RT;
|
|
|
|
|
continue;
|
|
|
|
|
|
1999-05-03 09:29:11 +02:00
|
|
|
|
case 'W':
|
2001-08-07 15:22:46 +02:00
|
|
|
|
ip->insn_opcode |= lastregno << OP_SH_FT;
|
1999-05-03 09:29:11 +02:00
|
|
|
|
continue;
|
|
|
|
|
|
|
|
|
|
case 'V':
|
2001-08-07 15:22:46 +02:00
|
|
|
|
ip->insn_opcode |= lastregno << OP_SH_FS;
|
1999-05-03 09:29:11 +02:00
|
|
|
|
continue;
|
|
|
|
|
}
|
|
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
case '(':
|
|
|
|
|
/* Handle optional base register.
|
|
|
|
|
Either the base register is omitted or
|
2000-09-07 14:45:56 +02:00
|
|
|
|
we must have a left paren. */
|
1999-05-03 09:29:11 +02:00
|
|
|
|
/* This is dependent on the next operand specifier
|
|
|
|
|
is a base register specification. */
|
|
|
|
|
assert (args[1] == 'b' || args[1] == '5'
|
|
|
|
|
|| args[1] == '-' || args[1] == '4');
|
|
|
|
|
if (*s == '\0')
|
|
|
|
|
return;
|
|
|
|
|
|
|
|
|
|
case ')': /* these must match exactly */
|
[gas/]
* doc/c-mips.texi: Add entries for -march=vr4120,vr4130,vr4181,
vr5400 and vr5500. Add entry for -mfix-vr4122-bugs.
* config/tc-mips.c (CPU_HAS_DROR, CPU_HAS_ROR): New macros.
(hilo_interlocks): True for CPU_VR5500.
(gpr_interlocks, cop_interlocks): True for CPU_VR5400 and CPU_VR5500.
(mips_fix_vr4122_bugs): New.
(append_insn): Work around 4122 errors if mips_fix_vr4122_bugs.
(mips_emit_delays): Likewise.
(macro2) [M_DROLI]: Use dror or dror32 if CPU_HAS_DROR.
[M_ROLI]: Likewise ror if CPU_HAS_ROR.
(validate_mips_insn, mips_ip): Handle '[', ']', 'e' and '%'.
(OPTION_FIX_VR4122, OPTION_NO_FIX_VR4122): New options.
(md_longopts): Add -mfix-vr4122-bugs and -no-mfix-vr4122-bugs.
(OPTION_ELF_BASE): Bump.
(md_parse_option): Handle the new options.
(mips_cpu_info_table): Add entries for vr4120, vr4130, vr4181,
vr5400 and vr5500.
[gas/testsuite/]
* gas/mips/mips4100.[sd]: Move dmadd16 and madd16 checks to...
* gas/mips/vr4111.[sd]: ...this new test.
* gas/mips/vr4120.[sd],
* gas/mips/vr4122.[sd],
* gas/mips/vr5400.[sd],
* gas/mips/vr5500.[sd]: New tests.
* mips.exp: Run them.
2002-09-30 14:04:54 +02:00
|
|
|
|
case '[':
|
|
|
|
|
case ']':
|
1999-05-03 09:29:11 +02:00
|
|
|
|
if (*s++ == *args)
|
|
|
|
|
continue;
|
|
|
|
|
break;
|
|
|
|
|
|
[ bfd/ChangeLog ]
2002-12-30 Chris Demetriou <cgd@broadcom.com>
* aoutx.h (NAME(aout,machine_type)): Add bfd_mach_mipsisa32r2 case.
* archures.c (bfd_mach_mipsisa32r2): New define.
* bfd-in2.h: Regenerate.
* cpu-mips.c (I_mipsisa32r2): New enum value.
(arch_info_struct): Add entry for I_mipsisa32r2.
* elfxx-mips.c (elf_mips_isa, _bfd_elf_mips_mach)
(_bfd_mips_elf_print_private_bfd_data): Handle E_MIPS_ARCH_32R2.
(_bfd_mips_elf_final_write_processing): Add
bfd_mach_mipsisa32r2 case.
(_bfd_mips_elf_merge_private_bfd_data): Handle merging of
binaries marked as using MIPS32 Release 2.
[ binutils/ChangeLog ]
2002-12-30 Chris Demetriou <cgd@broadcom.com>
* doc/binutils.texi (objdump): Note MIPS HWR (Hardware Register)
changes in MIPS -M options.
[ gas/ChangeLog ]
2002-12-30 Chris Demetriou <cgd@broadcom.com>
* configure.in: Recognize mipsisa32r2, mipsisa32r2el, and
CPU variants.
* configure: Regenerate.
* config/tc-mips.c (ISA_HAS_DROR, ISA_HAS_ROR): New defines.
(macro_build): Handle "K" operand.
(macro2): Use ISA_HAS_DROR and ISA_HAS_ROR in the places where
CPU_HAS_DROR and CPU_HAS_ROR are currently used.
(mips_ip): New variable "lastpos", and implement "+A", "+B",
and "+C" operands for MIPS32 Release 2 ins/ext instructions.
Implement "K" operand for MIPS32 Release 2 rdhwr instruction.
(validate_mips_insn): Implement "+" as a way to extend the
allowed operands, and implement "K", "+A", "+B", and "+C"
operands.
(OPTION_MIPS32R2): New define.
(md_longopts): Add entry for OPTION_MIPS32R2.
(OPTION_ELF_BASE): Adjust to accomodate OPTIONS_MIPS32R2.
(md_parse_option): Handle OPTION_MIPS32R2.
(s_mipsset): Reimplement handling of ".set mipsN" options
and add support for ".set mips32r2".
(mips_cpu_info_table): Add entry for "mips32r2" (MIPS32 Release 2).
(md_show_usage): Document "-mips32r2" option.
* doc/as.texinfo: Document "-mips32r2" option.
* doc/c-mips.texi: Likewise.
[ gas/testsuite/ChangeLog ]
2002-12-30 Chris Demetriou <cgd@broadcom.com>
* gas/mips/cp0-names-mips32r2.d: New test.
* gas/mips/hwr-names-mips32r2.d: New test.
* gas/mips/hwr-names-numeric.d: New test.
* gas/mips/hwr-names.s: New test source file.
* gas/mips/mips32r2.d: New test.
* gas/mips/mips32r2.s: New test source file.
* gas/mips/mips32r2-ill.l: New test.
* gas/mips/mips32r2-ill.s: New test source file.
* gas/mips/mips.exp: Add mips32r2 architecture data array
entry. Run new tests mentioned above.
[ include/elf/ChangeLog ]
2002-12-30 Chris Demetriou <cgd@broadcom.com>
* mips.h (E_MIPS_ARCH_32R2): New define.
[ include/opcode/ChangeLog ]
2002-12-30 Chris Demetriou <cgd@broadcom.com>
* mips.h: Document "+" as the start of two-character operand
type names, and add new "K", "+A", "+B", and "+C" operand types.
(OP_MASK_INSMSB, OP_SH_INSMSB, OP_MASK_EXTMSB)
(OP_SH_EXTMSB, INSN_ISA32R2, ISA_MIPS32R2, CPU_MIPS32R2): New
defines.
[ opcodes/ChangeLog ]
2002-12-30 Chris Demetriou <cgd@broadcom.com>
* mips-dis.c (mips_cp0_names_mips3264r2, mips_hwr_names_numeric)
(mips_hwr_names_mips3264r2): New arrays.
(mips_arch_choice): New "hwr_names" member.
(mips_arch_choices): Adjust for structure change, and add a new
entry for "mips32r2" ISA.
(mips_hwr_names): New variable.
(set_default_mips_dis_options): Set mips_hwr_names.
(parse_mips_dis_option): New "hwr-names" option which sets
mips_hwr_names, and adjust "reg-names=ARCH" to set mips_hwr_names.
(print_insn_arg): Change return type to "int"
and use that to indicate number of characters consumed.
Add support for "+" operand extension character, "+A", "+B",
"+C", and "K" operands.
(print_insn_mips): Adjust for changes to print_insn_arg.
(print_mips_disassembler_options): Adjust for "hwr-names"
addition and "reg-names" change.
* mips-opc (I33): New define (shorthand for INSN_ISA32R2).
(mips_builtin_opcodes): Note that "nop" and "ssnop" are special
forms of "sll". Add new MIPS32 Release 2 instructions: ehb,
di, ei, ext, ins, jr.hb, jalr.hb, mfhc1, mfhc2, mthc1, mthc2,
rdhwr, rdpgpr, seb, seh, synci, wrpgpr, wsbh.
Note that hardware rotate instructions (ror, rorv) can be
used on MIPS32 Release 2, and add the official mnemonics
for them (rotr, rotrv) and the similar "rotl" mnemonic for
left-rotate.
2002-12-31 08:29:29 +01:00
|
|
|
|
case '+': /* Opcode extension character. */
|
|
|
|
|
switch (*++args)
|
|
|
|
|
{
|
2003-01-02 21:03:09 +01:00
|
|
|
|
case 'A': /* ins/ext position, becomes LSB. */
|
|
|
|
|
limlo = 0;
|
|
|
|
|
limhi = 31;
|
[ bfd/ChangeLog ]
2003-09-30 Chris Demetriou <cgd@broadcom.com>
* archures.c (bfd_mach_mipsisa64r2): New define.
* bfd-in2.h: Regenerate.
* aoutx.h (NAME(aout,machine_type)): Handle bfd_mach_mipsisa64r2.
* cpu-mips.c (I_mipsisa64r2): New enum value.
(arch_info_struct): Add entry for I_mipsisa64r2.
* elfxx-mips.c (_bfd_elf_mips_mach)
(_bfd_mips_elf_print_private_bfd_data): Handle E_MIPS_ARCH_64R2.
(mips_set_isa_flags): Add bfd_mach_mipsisa64r2 case.
(mips_mach_extensions): Add entry for bfd_mach_mipsisa64r2.
[ binutils/ChangeLog ]
2003-09-30 Chris Demetriou <cgd@broadcom.com>
* readelf.c (get_machine_flags): Handle E_MIPS_ARCH_64R2.
[ gas/Changelog ]
2003-09-30 Chris Demetriou <cgd@broadcom.com>
* configure.in (mipsisa64r2, mipsisa64r2el, mipsisa64r2*): New CPUs.
* configure: Regenerate.
* config/tc-mips.c (imm2_expr): New variable.
(md_assemble, mips16_ip): Initialize imm2_expr.
(ISA_HAS_64BIT_REGS, ISA_HAS_DROR, ISA_HAS_ROR): Add ISA_MIPS64R2.
(macro_build): Handle +A, +B, +C, +E, +F, +G, and +H format operands.
(macro): Handle M_DEXT and M_DINS.
(validate_mips_insn): Handle +E, +F, +G, +H, and +I format operands.
(mips_ip): Likewise.
(OPTION_MIPS64R2): New define.
(md_longopts): New entry for -mips64r2 (OPTION_MIPS64R2).
OPTION_ASE_BASE): Increase to compensate for OPTION_MIPS64R2.
(md_parse_option): Handle OPTION_MIPS64R2.
(s_mipsset): Handle setting "mips64r2" ISA.
(mips_cpu_info_table): Add mips64r2.
(md_show_usage): Document -mips64r2 option.
* doc/as.texinfo: Docuemnt -mips64r2 option.
* doc/c-mips.texi: Likewise.
[ gas/testsuite/ChangeLog ]
2003-09-30 Chris Demetriou <cgd@broadcom.com>
* gas/mips/cp0-names-mips64r2.d: New file.
* gas/mips/cp0sel-names-mips64r2.d: New file.
* gas/mips/elf_arch_mips64r2.d: New file.
* gas/mips/hwr-names-mips64r2.d: New file.
* gas/mips/mips32r2-ill-fp64.l: New file.
* gas/mips/mips32r2-ill-fp64.s: New file.
* gas/mips/mips64r2-ill.l: New file.
* gas/mips/mips64r2-ill.s: New file.
* gas/mips/mips64r2.d: New file.
* gas/mips/mips64r2.s: New file.
* gas/mips/mips.exp: Define "mips64r2" arch, and run new tests.
[ include/elf/ChangeLog ]
2003-09-30 Chris Demetriou <cgd@broadcom.com>
* mips.h (E_MIPS_ARCH_64R2): New define.
[ include/opcode/ChangeLog ]
2003-09-30 Chris Demetriou <cgd@broadcom.com>
* mips.h: Document +E, +F, +G, +H, and +I operand types.
Update documentation of I, +B and +C operand types.
(INSN_ISA64R2, ISA_MIPS64R2, CPU_MIPS64R2): New defines.
(M_DEXT, M_DINS): New enum values.
[ ld/ChangeLog ]
2003-09-30 Chris Demetriou <cgd@broadcom.com>
* ldmain.c (get_emulation): Ignore "-mips64r2".
[ ld/testsuite/ChangeLog ]
2003-09-30 Chris Demetriou <cgd@broadcom.com>
* ld-mips-elf/mips-elf-flags.exp: Add tests for combinations
with MIPS64r2.
[ opcodes/ChangeLog ]
2003-09-30 Chris Demetriou <cgd@broadcom.com>
* mips-dis.c (mips_arch_choices): Add entry for "mips64r2"
(print_insn_args): Add handing for +E, +F, +G, and +H.
* mips-opc.c (I65): New define for MIPS64r2.
(mips_builtin_opcodes): Add "dext", "dextm", "dextu", "dins",
"dinsm", "dinsu", "drotl", "drotr", "drotr32", "drotrv", "dsbh",
and "dshd" for MIPS64r2. Adjust "dror", "dror32", and "drorv" to
be supported on MIPS64r2.
2003-09-30 18:17:15 +02:00
|
|
|
|
goto do_lsb;
|
|
|
|
|
case 'E':
|
|
|
|
|
limlo = 32;
|
|
|
|
|
limhi = 63;
|
|
|
|
|
goto do_lsb;
|
|
|
|
|
do_lsb:
|
2003-01-02 21:03:09 +01:00
|
|
|
|
my_getExpression (&imm_expr, s);
|
|
|
|
|
check_absolute_expr (ip, &imm_expr);
|
|
|
|
|
if ((unsigned long) imm_expr.X_add_number < limlo
|
|
|
|
|
|| (unsigned long) imm_expr.X_add_number > limhi)
|
|
|
|
|
{
|
|
|
|
|
as_bad (_("Improper position (%lu)"),
|
|
|
|
|
(unsigned long) imm_expr.X_add_number);
|
|
|
|
|
imm_expr.X_add_number = limlo;
|
|
|
|
|
}
|
|
|
|
|
lastpos = imm_expr.X_add_number;
|
|
|
|
|
ip->insn_opcode |= (imm_expr.X_add_number
|
|
|
|
|
& OP_MASK_SHAMT) << OP_SH_SHAMT;
|
|
|
|
|
imm_expr.X_op = O_absent;
|
|
|
|
|
s = expr_end;
|
|
|
|
|
continue;
|
|
|
|
|
|
|
|
|
|
case 'B': /* ins size, becomes MSB. */
|
|
|
|
|
limlo = 1;
|
|
|
|
|
limhi = 32;
|
[ bfd/ChangeLog ]
2003-09-30 Chris Demetriou <cgd@broadcom.com>
* archures.c (bfd_mach_mipsisa64r2): New define.
* bfd-in2.h: Regenerate.
* aoutx.h (NAME(aout,machine_type)): Handle bfd_mach_mipsisa64r2.
* cpu-mips.c (I_mipsisa64r2): New enum value.
(arch_info_struct): Add entry for I_mipsisa64r2.
* elfxx-mips.c (_bfd_elf_mips_mach)
(_bfd_mips_elf_print_private_bfd_data): Handle E_MIPS_ARCH_64R2.
(mips_set_isa_flags): Add bfd_mach_mipsisa64r2 case.
(mips_mach_extensions): Add entry for bfd_mach_mipsisa64r2.
[ binutils/ChangeLog ]
2003-09-30 Chris Demetriou <cgd@broadcom.com>
* readelf.c (get_machine_flags): Handle E_MIPS_ARCH_64R2.
[ gas/Changelog ]
2003-09-30 Chris Demetriou <cgd@broadcom.com>
* configure.in (mipsisa64r2, mipsisa64r2el, mipsisa64r2*): New CPUs.
* configure: Regenerate.
* config/tc-mips.c (imm2_expr): New variable.
(md_assemble, mips16_ip): Initialize imm2_expr.
(ISA_HAS_64BIT_REGS, ISA_HAS_DROR, ISA_HAS_ROR): Add ISA_MIPS64R2.
(macro_build): Handle +A, +B, +C, +E, +F, +G, and +H format operands.
(macro): Handle M_DEXT and M_DINS.
(validate_mips_insn): Handle +E, +F, +G, +H, and +I format operands.
(mips_ip): Likewise.
(OPTION_MIPS64R2): New define.
(md_longopts): New entry for -mips64r2 (OPTION_MIPS64R2).
OPTION_ASE_BASE): Increase to compensate for OPTION_MIPS64R2.
(md_parse_option): Handle OPTION_MIPS64R2.
(s_mipsset): Handle setting "mips64r2" ISA.
(mips_cpu_info_table): Add mips64r2.
(md_show_usage): Document -mips64r2 option.
* doc/as.texinfo: Docuemnt -mips64r2 option.
* doc/c-mips.texi: Likewise.
[ gas/testsuite/ChangeLog ]
2003-09-30 Chris Demetriou <cgd@broadcom.com>
* gas/mips/cp0-names-mips64r2.d: New file.
* gas/mips/cp0sel-names-mips64r2.d: New file.
* gas/mips/elf_arch_mips64r2.d: New file.
* gas/mips/hwr-names-mips64r2.d: New file.
* gas/mips/mips32r2-ill-fp64.l: New file.
* gas/mips/mips32r2-ill-fp64.s: New file.
* gas/mips/mips64r2-ill.l: New file.
* gas/mips/mips64r2-ill.s: New file.
* gas/mips/mips64r2.d: New file.
* gas/mips/mips64r2.s: New file.
* gas/mips/mips.exp: Define "mips64r2" arch, and run new tests.
[ include/elf/ChangeLog ]
2003-09-30 Chris Demetriou <cgd@broadcom.com>
* mips.h (E_MIPS_ARCH_64R2): New define.
[ include/opcode/ChangeLog ]
2003-09-30 Chris Demetriou <cgd@broadcom.com>
* mips.h: Document +E, +F, +G, +H, and +I operand types.
Update documentation of I, +B and +C operand types.
(INSN_ISA64R2, ISA_MIPS64R2, CPU_MIPS64R2): New defines.
(M_DEXT, M_DINS): New enum values.
[ ld/ChangeLog ]
2003-09-30 Chris Demetriou <cgd@broadcom.com>
* ldmain.c (get_emulation): Ignore "-mips64r2".
[ ld/testsuite/ChangeLog ]
2003-09-30 Chris Demetriou <cgd@broadcom.com>
* ld-mips-elf/mips-elf-flags.exp: Add tests for combinations
with MIPS64r2.
[ opcodes/ChangeLog ]
2003-09-30 Chris Demetriou <cgd@broadcom.com>
* mips-dis.c (mips_arch_choices): Add entry for "mips64r2"
(print_insn_args): Add handing for +E, +F, +G, and +H.
* mips-opc.c (I65): New define for MIPS64r2.
(mips_builtin_opcodes): Add "dext", "dextm", "dextu", "dins",
"dinsm", "dinsu", "drotl", "drotr", "drotr32", "drotrv", "dsbh",
and "dshd" for MIPS64r2. Adjust "dror", "dror32", and "drorv" to
be supported on MIPS64r2.
2003-09-30 18:17:15 +02:00
|
|
|
|
goto do_msb;
|
|
|
|
|
case 'F':
|
|
|
|
|
limlo = 33;
|
|
|
|
|
limhi = 64;
|
|
|
|
|
goto do_msb;
|
|
|
|
|
do_msb:
|
2003-01-02 21:03:09 +01:00
|
|
|
|
my_getExpression (&imm_expr, s);
|
|
|
|
|
check_absolute_expr (ip, &imm_expr);
|
|
|
|
|
/* Check for negative input so that small negative numbers
|
|
|
|
|
will not succeed incorrectly. The checks against
|
|
|
|
|
(pos+size) transitively check "size" itself,
|
|
|
|
|
assuming that "pos" is reasonable. */
|
|
|
|
|
if ((long) imm_expr.X_add_number < 0
|
|
|
|
|
|| ((unsigned long) imm_expr.X_add_number
|
|
|
|
|
+ lastpos) < limlo
|
|
|
|
|
|| ((unsigned long) imm_expr.X_add_number
|
|
|
|
|
+ lastpos) > limhi)
|
|
|
|
|
{
|
|
|
|
|
as_bad (_("Improper insert size (%lu, position %lu)"),
|
|
|
|
|
(unsigned long) imm_expr.X_add_number,
|
|
|
|
|
(unsigned long) lastpos);
|
|
|
|
|
imm_expr.X_add_number = limlo - lastpos;
|
|
|
|
|
}
|
|
|
|
|
ip->insn_opcode |= ((lastpos + imm_expr.X_add_number - 1)
|
|
|
|
|
& OP_MASK_INSMSB) << OP_SH_INSMSB;
|
|
|
|
|
imm_expr.X_op = O_absent;
|
|
|
|
|
s = expr_end;
|
|
|
|
|
continue;
|
|
|
|
|
|
|
|
|
|
case 'C': /* ext size, becomes MSBD. */
|
|
|
|
|
limlo = 1;
|
|
|
|
|
limhi = 32;
|
[ bfd/ChangeLog ]
2003-09-30 Chris Demetriou <cgd@broadcom.com>
* archures.c (bfd_mach_mipsisa64r2): New define.
* bfd-in2.h: Regenerate.
* aoutx.h (NAME(aout,machine_type)): Handle bfd_mach_mipsisa64r2.
* cpu-mips.c (I_mipsisa64r2): New enum value.
(arch_info_struct): Add entry for I_mipsisa64r2.
* elfxx-mips.c (_bfd_elf_mips_mach)
(_bfd_mips_elf_print_private_bfd_data): Handle E_MIPS_ARCH_64R2.
(mips_set_isa_flags): Add bfd_mach_mipsisa64r2 case.
(mips_mach_extensions): Add entry for bfd_mach_mipsisa64r2.
[ binutils/ChangeLog ]
2003-09-30 Chris Demetriou <cgd@broadcom.com>
* readelf.c (get_machine_flags): Handle E_MIPS_ARCH_64R2.
[ gas/Changelog ]
2003-09-30 Chris Demetriou <cgd@broadcom.com>
* configure.in (mipsisa64r2, mipsisa64r2el, mipsisa64r2*): New CPUs.
* configure: Regenerate.
* config/tc-mips.c (imm2_expr): New variable.
(md_assemble, mips16_ip): Initialize imm2_expr.
(ISA_HAS_64BIT_REGS, ISA_HAS_DROR, ISA_HAS_ROR): Add ISA_MIPS64R2.
(macro_build): Handle +A, +B, +C, +E, +F, +G, and +H format operands.
(macro): Handle M_DEXT and M_DINS.
(validate_mips_insn): Handle +E, +F, +G, +H, and +I format operands.
(mips_ip): Likewise.
(OPTION_MIPS64R2): New define.
(md_longopts): New entry for -mips64r2 (OPTION_MIPS64R2).
OPTION_ASE_BASE): Increase to compensate for OPTION_MIPS64R2.
(md_parse_option): Handle OPTION_MIPS64R2.
(s_mipsset): Handle setting "mips64r2" ISA.
(mips_cpu_info_table): Add mips64r2.
(md_show_usage): Document -mips64r2 option.
* doc/as.texinfo: Docuemnt -mips64r2 option.
* doc/c-mips.texi: Likewise.
[ gas/testsuite/ChangeLog ]
2003-09-30 Chris Demetriou <cgd@broadcom.com>
* gas/mips/cp0-names-mips64r2.d: New file.
* gas/mips/cp0sel-names-mips64r2.d: New file.
* gas/mips/elf_arch_mips64r2.d: New file.
* gas/mips/hwr-names-mips64r2.d: New file.
* gas/mips/mips32r2-ill-fp64.l: New file.
* gas/mips/mips32r2-ill-fp64.s: New file.
* gas/mips/mips64r2-ill.l: New file.
* gas/mips/mips64r2-ill.s: New file.
* gas/mips/mips64r2.d: New file.
* gas/mips/mips64r2.s: New file.
* gas/mips/mips.exp: Define "mips64r2" arch, and run new tests.
[ include/elf/ChangeLog ]
2003-09-30 Chris Demetriou <cgd@broadcom.com>
* mips.h (E_MIPS_ARCH_64R2): New define.
[ include/opcode/ChangeLog ]
2003-09-30 Chris Demetriou <cgd@broadcom.com>
* mips.h: Document +E, +F, +G, +H, and +I operand types.
Update documentation of I, +B and +C operand types.
(INSN_ISA64R2, ISA_MIPS64R2, CPU_MIPS64R2): New defines.
(M_DEXT, M_DINS): New enum values.
[ ld/ChangeLog ]
2003-09-30 Chris Demetriou <cgd@broadcom.com>
* ldmain.c (get_emulation): Ignore "-mips64r2".
[ ld/testsuite/ChangeLog ]
2003-09-30 Chris Demetriou <cgd@broadcom.com>
* ld-mips-elf/mips-elf-flags.exp: Add tests for combinations
with MIPS64r2.
[ opcodes/ChangeLog ]
2003-09-30 Chris Demetriou <cgd@broadcom.com>
* mips-dis.c (mips_arch_choices): Add entry for "mips64r2"
(print_insn_args): Add handing for +E, +F, +G, and +H.
* mips-opc.c (I65): New define for MIPS64r2.
(mips_builtin_opcodes): Add "dext", "dextm", "dextu", "dins",
"dinsm", "dinsu", "drotl", "drotr", "drotr32", "drotrv", "dsbh",
and "dshd" for MIPS64r2. Adjust "dror", "dror32", and "drorv" to
be supported on MIPS64r2.
2003-09-30 18:17:15 +02:00
|
|
|
|
goto do_msbd;
|
|
|
|
|
case 'G':
|
|
|
|
|
limlo = 33;
|
|
|
|
|
limhi = 64;
|
|
|
|
|
goto do_msbd;
|
|
|
|
|
case 'H':
|
|
|
|
|
limlo = 33;
|
|
|
|
|
limhi = 64;
|
|
|
|
|
goto do_msbd;
|
|
|
|
|
do_msbd:
|
2003-01-02 21:03:09 +01:00
|
|
|
|
my_getExpression (&imm_expr, s);
|
|
|
|
|
check_absolute_expr (ip, &imm_expr);
|
|
|
|
|
/* Check for negative input so that small negative numbers
|
|
|
|
|
will not succeed incorrectly. The checks against
|
|
|
|
|
(pos+size) transitively check "size" itself,
|
|
|
|
|
assuming that "pos" is reasonable. */
|
|
|
|
|
if ((long) imm_expr.X_add_number < 0
|
|
|
|
|
|| ((unsigned long) imm_expr.X_add_number
|
|
|
|
|
+ lastpos) < limlo
|
|
|
|
|
|| ((unsigned long) imm_expr.X_add_number
|
|
|
|
|
+ lastpos) > limhi)
|
|
|
|
|
{
|
|
|
|
|
as_bad (_("Improper extract size (%lu, position %lu)"),
|
|
|
|
|
(unsigned long) imm_expr.X_add_number,
|
|
|
|
|
(unsigned long) lastpos);
|
|
|
|
|
imm_expr.X_add_number = limlo - lastpos;
|
|
|
|
|
}
|
|
|
|
|
ip->insn_opcode |= ((imm_expr.X_add_number - 1)
|
|
|
|
|
& OP_MASK_EXTMSBD) << OP_SH_EXTMSBD;
|
|
|
|
|
imm_expr.X_op = O_absent;
|
|
|
|
|
s = expr_end;
|
|
|
|
|
continue;
|
[ bfd/ChangeLog ]
2002-12-30 Chris Demetriou <cgd@broadcom.com>
* aoutx.h (NAME(aout,machine_type)): Add bfd_mach_mipsisa32r2 case.
* archures.c (bfd_mach_mipsisa32r2): New define.
* bfd-in2.h: Regenerate.
* cpu-mips.c (I_mipsisa32r2): New enum value.
(arch_info_struct): Add entry for I_mipsisa32r2.
* elfxx-mips.c (elf_mips_isa, _bfd_elf_mips_mach)
(_bfd_mips_elf_print_private_bfd_data): Handle E_MIPS_ARCH_32R2.
(_bfd_mips_elf_final_write_processing): Add
bfd_mach_mipsisa32r2 case.
(_bfd_mips_elf_merge_private_bfd_data): Handle merging of
binaries marked as using MIPS32 Release 2.
[ binutils/ChangeLog ]
2002-12-30 Chris Demetriou <cgd@broadcom.com>
* doc/binutils.texi (objdump): Note MIPS HWR (Hardware Register)
changes in MIPS -M options.
[ gas/ChangeLog ]
2002-12-30 Chris Demetriou <cgd@broadcom.com>
* configure.in: Recognize mipsisa32r2, mipsisa32r2el, and
CPU variants.
* configure: Regenerate.
* config/tc-mips.c (ISA_HAS_DROR, ISA_HAS_ROR): New defines.
(macro_build): Handle "K" operand.
(macro2): Use ISA_HAS_DROR and ISA_HAS_ROR in the places where
CPU_HAS_DROR and CPU_HAS_ROR are currently used.
(mips_ip): New variable "lastpos", and implement "+A", "+B",
and "+C" operands for MIPS32 Release 2 ins/ext instructions.
Implement "K" operand for MIPS32 Release 2 rdhwr instruction.
(validate_mips_insn): Implement "+" as a way to extend the
allowed operands, and implement "K", "+A", "+B", and "+C"
operands.
(OPTION_MIPS32R2): New define.
(md_longopts): Add entry for OPTION_MIPS32R2.
(OPTION_ELF_BASE): Adjust to accomodate OPTIONS_MIPS32R2.
(md_parse_option): Handle OPTION_MIPS32R2.
(s_mipsset): Reimplement handling of ".set mipsN" options
and add support for ".set mips32r2".
(mips_cpu_info_table): Add entry for "mips32r2" (MIPS32 Release 2).
(md_show_usage): Document "-mips32r2" option.
* doc/as.texinfo: Document "-mips32r2" option.
* doc/c-mips.texi: Likewise.
[ gas/testsuite/ChangeLog ]
2002-12-30 Chris Demetriou <cgd@broadcom.com>
* gas/mips/cp0-names-mips32r2.d: New test.
* gas/mips/hwr-names-mips32r2.d: New test.
* gas/mips/hwr-names-numeric.d: New test.
* gas/mips/hwr-names.s: New test source file.
* gas/mips/mips32r2.d: New test.
* gas/mips/mips32r2.s: New test source file.
* gas/mips/mips32r2-ill.l: New test.
* gas/mips/mips32r2-ill.s: New test source file.
* gas/mips/mips.exp: Add mips32r2 architecture data array
entry. Run new tests mentioned above.
[ include/elf/ChangeLog ]
2002-12-30 Chris Demetriou <cgd@broadcom.com>
* mips.h (E_MIPS_ARCH_32R2): New define.
[ include/opcode/ChangeLog ]
2002-12-30 Chris Demetriou <cgd@broadcom.com>
* mips.h: Document "+" as the start of two-character operand
type names, and add new "K", "+A", "+B", and "+C" operand types.
(OP_MASK_INSMSB, OP_SH_INSMSB, OP_MASK_EXTMSB)
(OP_SH_EXTMSB, INSN_ISA32R2, ISA_MIPS32R2, CPU_MIPS32R2): New
defines.
[ opcodes/ChangeLog ]
2002-12-30 Chris Demetriou <cgd@broadcom.com>
* mips-dis.c (mips_cp0_names_mips3264r2, mips_hwr_names_numeric)
(mips_hwr_names_mips3264r2): New arrays.
(mips_arch_choice): New "hwr_names" member.
(mips_arch_choices): Adjust for structure change, and add a new
entry for "mips32r2" ISA.
(mips_hwr_names): New variable.
(set_default_mips_dis_options): Set mips_hwr_names.
(parse_mips_dis_option): New "hwr-names" option which sets
mips_hwr_names, and adjust "reg-names=ARCH" to set mips_hwr_names.
(print_insn_arg): Change return type to "int"
and use that to indicate number of characters consumed.
Add support for "+" operand extension character, "+A", "+B",
"+C", and "K" operands.
(print_insn_mips): Adjust for changes to print_insn_arg.
(print_mips_disassembler_options): Adjust for "hwr-names"
addition and "reg-names" change.
* mips-opc (I33): New define (shorthand for INSN_ISA32R2).
(mips_builtin_opcodes): Note that "nop" and "ssnop" are special
forms of "sll". Add new MIPS32 Release 2 instructions: ehb,
di, ei, ext, ins, jr.hb, jalr.hb, mfhc1, mfhc2, mthc1, mthc2,
rdhwr, rdpgpr, seb, seh, synci, wrpgpr, wsbh.
Note that hardware rotate instructions (ror, rorv) can be
used on MIPS32 Release 2, and add the official mnemonics
for them (rotr, rotrv) and the similar "rotl" mnemonic for
left-rotate.
2002-12-31 08:29:29 +01:00
|
|
|
|
|
2002-12-31 09:11:18 +01:00
|
|
|
|
case 'D':
|
|
|
|
|
/* +D is for disassembly only; never match. */
|
|
|
|
|
break;
|
|
|
|
|
|
[ bfd/ChangeLog ]
2003-09-30 Chris Demetriou <cgd@broadcom.com>
* archures.c (bfd_mach_mipsisa64r2): New define.
* bfd-in2.h: Regenerate.
* aoutx.h (NAME(aout,machine_type)): Handle bfd_mach_mipsisa64r2.
* cpu-mips.c (I_mipsisa64r2): New enum value.
(arch_info_struct): Add entry for I_mipsisa64r2.
* elfxx-mips.c (_bfd_elf_mips_mach)
(_bfd_mips_elf_print_private_bfd_data): Handle E_MIPS_ARCH_64R2.
(mips_set_isa_flags): Add bfd_mach_mipsisa64r2 case.
(mips_mach_extensions): Add entry for bfd_mach_mipsisa64r2.
[ binutils/ChangeLog ]
2003-09-30 Chris Demetriou <cgd@broadcom.com>
* readelf.c (get_machine_flags): Handle E_MIPS_ARCH_64R2.
[ gas/Changelog ]
2003-09-30 Chris Demetriou <cgd@broadcom.com>
* configure.in (mipsisa64r2, mipsisa64r2el, mipsisa64r2*): New CPUs.
* configure: Regenerate.
* config/tc-mips.c (imm2_expr): New variable.
(md_assemble, mips16_ip): Initialize imm2_expr.
(ISA_HAS_64BIT_REGS, ISA_HAS_DROR, ISA_HAS_ROR): Add ISA_MIPS64R2.
(macro_build): Handle +A, +B, +C, +E, +F, +G, and +H format operands.
(macro): Handle M_DEXT and M_DINS.
(validate_mips_insn): Handle +E, +F, +G, +H, and +I format operands.
(mips_ip): Likewise.
(OPTION_MIPS64R2): New define.
(md_longopts): New entry for -mips64r2 (OPTION_MIPS64R2).
OPTION_ASE_BASE): Increase to compensate for OPTION_MIPS64R2.
(md_parse_option): Handle OPTION_MIPS64R2.
(s_mipsset): Handle setting "mips64r2" ISA.
(mips_cpu_info_table): Add mips64r2.
(md_show_usage): Document -mips64r2 option.
* doc/as.texinfo: Docuemnt -mips64r2 option.
* doc/c-mips.texi: Likewise.
[ gas/testsuite/ChangeLog ]
2003-09-30 Chris Demetriou <cgd@broadcom.com>
* gas/mips/cp0-names-mips64r2.d: New file.
* gas/mips/cp0sel-names-mips64r2.d: New file.
* gas/mips/elf_arch_mips64r2.d: New file.
* gas/mips/hwr-names-mips64r2.d: New file.
* gas/mips/mips32r2-ill-fp64.l: New file.
* gas/mips/mips32r2-ill-fp64.s: New file.
* gas/mips/mips64r2-ill.l: New file.
* gas/mips/mips64r2-ill.s: New file.
* gas/mips/mips64r2.d: New file.
* gas/mips/mips64r2.s: New file.
* gas/mips/mips.exp: Define "mips64r2" arch, and run new tests.
[ include/elf/ChangeLog ]
2003-09-30 Chris Demetriou <cgd@broadcom.com>
* mips.h (E_MIPS_ARCH_64R2): New define.
[ include/opcode/ChangeLog ]
2003-09-30 Chris Demetriou <cgd@broadcom.com>
* mips.h: Document +E, +F, +G, +H, and +I operand types.
Update documentation of I, +B and +C operand types.
(INSN_ISA64R2, ISA_MIPS64R2, CPU_MIPS64R2): New defines.
(M_DEXT, M_DINS): New enum values.
[ ld/ChangeLog ]
2003-09-30 Chris Demetriou <cgd@broadcom.com>
* ldmain.c (get_emulation): Ignore "-mips64r2".
[ ld/testsuite/ChangeLog ]
2003-09-30 Chris Demetriou <cgd@broadcom.com>
* ld-mips-elf/mips-elf-flags.exp: Add tests for combinations
with MIPS64r2.
[ opcodes/ChangeLog ]
2003-09-30 Chris Demetriou <cgd@broadcom.com>
* mips-dis.c (mips_arch_choices): Add entry for "mips64r2"
(print_insn_args): Add handing for +E, +F, +G, and +H.
* mips-opc.c (I65): New define for MIPS64r2.
(mips_builtin_opcodes): Add "dext", "dextm", "dextu", "dins",
"dinsm", "dinsu", "drotl", "drotr", "drotr32", "drotrv", "dsbh",
and "dshd" for MIPS64r2. Adjust "dror", "dror32", and "drorv" to
be supported on MIPS64r2.
2003-09-30 18:17:15 +02:00
|
|
|
|
case 'I':
|
|
|
|
|
/* "+I" is like "I", except that imm2_expr is used. */
|
|
|
|
|
my_getExpression (&imm2_expr, s);
|
|
|
|
|
if (imm2_expr.X_op != O_big
|
|
|
|
|
&& imm2_expr.X_op != O_constant)
|
|
|
|
|
insn_error = _("absolute expression required");
|
2003-10-19 23:50:43 +02:00
|
|
|
|
normalize_constant_expr (&imm2_expr);
|
[ bfd/ChangeLog ]
2003-09-30 Chris Demetriou <cgd@broadcom.com>
* archures.c (bfd_mach_mipsisa64r2): New define.
* bfd-in2.h: Regenerate.
* aoutx.h (NAME(aout,machine_type)): Handle bfd_mach_mipsisa64r2.
* cpu-mips.c (I_mipsisa64r2): New enum value.
(arch_info_struct): Add entry for I_mipsisa64r2.
* elfxx-mips.c (_bfd_elf_mips_mach)
(_bfd_mips_elf_print_private_bfd_data): Handle E_MIPS_ARCH_64R2.
(mips_set_isa_flags): Add bfd_mach_mipsisa64r2 case.
(mips_mach_extensions): Add entry for bfd_mach_mipsisa64r2.
[ binutils/ChangeLog ]
2003-09-30 Chris Demetriou <cgd@broadcom.com>
* readelf.c (get_machine_flags): Handle E_MIPS_ARCH_64R2.
[ gas/Changelog ]
2003-09-30 Chris Demetriou <cgd@broadcom.com>
* configure.in (mipsisa64r2, mipsisa64r2el, mipsisa64r2*): New CPUs.
* configure: Regenerate.
* config/tc-mips.c (imm2_expr): New variable.
(md_assemble, mips16_ip): Initialize imm2_expr.
(ISA_HAS_64BIT_REGS, ISA_HAS_DROR, ISA_HAS_ROR): Add ISA_MIPS64R2.
(macro_build): Handle +A, +B, +C, +E, +F, +G, and +H format operands.
(macro): Handle M_DEXT and M_DINS.
(validate_mips_insn): Handle +E, +F, +G, +H, and +I format operands.
(mips_ip): Likewise.
(OPTION_MIPS64R2): New define.
(md_longopts): New entry for -mips64r2 (OPTION_MIPS64R2).
OPTION_ASE_BASE): Increase to compensate for OPTION_MIPS64R2.
(md_parse_option): Handle OPTION_MIPS64R2.
(s_mipsset): Handle setting "mips64r2" ISA.
(mips_cpu_info_table): Add mips64r2.
(md_show_usage): Document -mips64r2 option.
* doc/as.texinfo: Docuemnt -mips64r2 option.
* doc/c-mips.texi: Likewise.
[ gas/testsuite/ChangeLog ]
2003-09-30 Chris Demetriou <cgd@broadcom.com>
* gas/mips/cp0-names-mips64r2.d: New file.
* gas/mips/cp0sel-names-mips64r2.d: New file.
* gas/mips/elf_arch_mips64r2.d: New file.
* gas/mips/hwr-names-mips64r2.d: New file.
* gas/mips/mips32r2-ill-fp64.l: New file.
* gas/mips/mips32r2-ill-fp64.s: New file.
* gas/mips/mips64r2-ill.l: New file.
* gas/mips/mips64r2-ill.s: New file.
* gas/mips/mips64r2.d: New file.
* gas/mips/mips64r2.s: New file.
* gas/mips/mips.exp: Define "mips64r2" arch, and run new tests.
[ include/elf/ChangeLog ]
2003-09-30 Chris Demetriou <cgd@broadcom.com>
* mips.h (E_MIPS_ARCH_64R2): New define.
[ include/opcode/ChangeLog ]
2003-09-30 Chris Demetriou <cgd@broadcom.com>
* mips.h: Document +E, +F, +G, +H, and +I operand types.
Update documentation of I, +B and +C operand types.
(INSN_ISA64R2, ISA_MIPS64R2, CPU_MIPS64R2): New defines.
(M_DEXT, M_DINS): New enum values.
[ ld/ChangeLog ]
2003-09-30 Chris Demetriou <cgd@broadcom.com>
* ldmain.c (get_emulation): Ignore "-mips64r2".
[ ld/testsuite/ChangeLog ]
2003-09-30 Chris Demetriou <cgd@broadcom.com>
* ld-mips-elf/mips-elf-flags.exp: Add tests for combinations
with MIPS64r2.
[ opcodes/ChangeLog ]
2003-09-30 Chris Demetriou <cgd@broadcom.com>
* mips-dis.c (mips_arch_choices): Add entry for "mips64r2"
(print_insn_args): Add handing for +E, +F, +G, and +H.
* mips-opc.c (I65): New define for MIPS64r2.
(mips_builtin_opcodes): Add "dext", "dextm", "dextu", "dins",
"dinsm", "dinsu", "drotl", "drotr", "drotr32", "drotrv", "dsbh",
and "dshd" for MIPS64r2. Adjust "dror", "dror32", and "drorv" to
be supported on MIPS64r2.
2003-09-30 18:17:15 +02:00
|
|
|
|
s = expr_end;
|
|
|
|
|
continue;
|
|
|
|
|
|
[ bfd/ChangeLog ]
2002-12-30 Chris Demetriou <cgd@broadcom.com>
* aoutx.h (NAME(aout,machine_type)): Add bfd_mach_mipsisa32r2 case.
* archures.c (bfd_mach_mipsisa32r2): New define.
* bfd-in2.h: Regenerate.
* cpu-mips.c (I_mipsisa32r2): New enum value.
(arch_info_struct): Add entry for I_mipsisa32r2.
* elfxx-mips.c (elf_mips_isa, _bfd_elf_mips_mach)
(_bfd_mips_elf_print_private_bfd_data): Handle E_MIPS_ARCH_32R2.
(_bfd_mips_elf_final_write_processing): Add
bfd_mach_mipsisa32r2 case.
(_bfd_mips_elf_merge_private_bfd_data): Handle merging of
binaries marked as using MIPS32 Release 2.
[ binutils/ChangeLog ]
2002-12-30 Chris Demetriou <cgd@broadcom.com>
* doc/binutils.texi (objdump): Note MIPS HWR (Hardware Register)
changes in MIPS -M options.
[ gas/ChangeLog ]
2002-12-30 Chris Demetriou <cgd@broadcom.com>
* configure.in: Recognize mipsisa32r2, mipsisa32r2el, and
CPU variants.
* configure: Regenerate.
* config/tc-mips.c (ISA_HAS_DROR, ISA_HAS_ROR): New defines.
(macro_build): Handle "K" operand.
(macro2): Use ISA_HAS_DROR and ISA_HAS_ROR in the places where
CPU_HAS_DROR and CPU_HAS_ROR are currently used.
(mips_ip): New variable "lastpos", and implement "+A", "+B",
and "+C" operands for MIPS32 Release 2 ins/ext instructions.
Implement "K" operand for MIPS32 Release 2 rdhwr instruction.
(validate_mips_insn): Implement "+" as a way to extend the
allowed operands, and implement "K", "+A", "+B", and "+C"
operands.
(OPTION_MIPS32R2): New define.
(md_longopts): Add entry for OPTION_MIPS32R2.
(OPTION_ELF_BASE): Adjust to accomodate OPTIONS_MIPS32R2.
(md_parse_option): Handle OPTION_MIPS32R2.
(s_mipsset): Reimplement handling of ".set mipsN" options
and add support for ".set mips32r2".
(mips_cpu_info_table): Add entry for "mips32r2" (MIPS32 Release 2).
(md_show_usage): Document "-mips32r2" option.
* doc/as.texinfo: Document "-mips32r2" option.
* doc/c-mips.texi: Likewise.
[ gas/testsuite/ChangeLog ]
2002-12-30 Chris Demetriou <cgd@broadcom.com>
* gas/mips/cp0-names-mips32r2.d: New test.
* gas/mips/hwr-names-mips32r2.d: New test.
* gas/mips/hwr-names-numeric.d: New test.
* gas/mips/hwr-names.s: New test source file.
* gas/mips/mips32r2.d: New test.
* gas/mips/mips32r2.s: New test source file.
* gas/mips/mips32r2-ill.l: New test.
* gas/mips/mips32r2-ill.s: New test source file.
* gas/mips/mips.exp: Add mips32r2 architecture data array
entry. Run new tests mentioned above.
[ include/elf/ChangeLog ]
2002-12-30 Chris Demetriou <cgd@broadcom.com>
* mips.h (E_MIPS_ARCH_32R2): New define.
[ include/opcode/ChangeLog ]
2002-12-30 Chris Demetriou <cgd@broadcom.com>
* mips.h: Document "+" as the start of two-character operand
type names, and add new "K", "+A", "+B", and "+C" operand types.
(OP_MASK_INSMSB, OP_SH_INSMSB, OP_MASK_EXTMSB)
(OP_SH_EXTMSB, INSN_ISA32R2, ISA_MIPS32R2, CPU_MIPS32R2): New
defines.
[ opcodes/ChangeLog ]
2002-12-30 Chris Demetriou <cgd@broadcom.com>
* mips-dis.c (mips_cp0_names_mips3264r2, mips_hwr_names_numeric)
(mips_hwr_names_mips3264r2): New arrays.
(mips_arch_choice): New "hwr_names" member.
(mips_arch_choices): Adjust for structure change, and add a new
entry for "mips32r2" ISA.
(mips_hwr_names): New variable.
(set_default_mips_dis_options): Set mips_hwr_names.
(parse_mips_dis_option): New "hwr-names" option which sets
mips_hwr_names, and adjust "reg-names=ARCH" to set mips_hwr_names.
(print_insn_arg): Change return type to "int"
and use that to indicate number of characters consumed.
Add support for "+" operand extension character, "+A", "+B",
"+C", and "K" operands.
(print_insn_mips): Adjust for changes to print_insn_arg.
(print_mips_disassembler_options): Adjust for "hwr-names"
addition and "reg-names" change.
* mips-opc (I33): New define (shorthand for INSN_ISA32R2).
(mips_builtin_opcodes): Note that "nop" and "ssnop" are special
forms of "sll". Add new MIPS32 Release 2 instructions: ehb,
di, ei, ext, ins, jr.hb, jalr.hb, mfhc1, mfhc2, mthc1, mthc2,
rdhwr, rdpgpr, seb, seh, synci, wrpgpr, wsbh.
Note that hardware rotate instructions (ror, rorv) can be
used on MIPS32 Release 2, and add the official mnemonics
for them (rotr, rotrv) and the similar "rotl" mnemonic for
left-rotate.
2002-12-31 08:29:29 +01:00
|
|
|
|
default:
|
|
|
|
|
as_bad (_("internal: bad mips opcode (unknown extension operand type `+%c'): %s %s"),
|
|
|
|
|
*args, insn->name, insn->args);
|
|
|
|
|
/* Further processing is fruitless. */
|
|
|
|
|
return;
|
|
|
|
|
}
|
|
|
|
|
break;
|
|
|
|
|
|
1999-05-03 09:29:11 +02:00
|
|
|
|
case '<': /* must be at least one digit */
|
|
|
|
|
/*
|
|
|
|
|
* According to the manual, if the shift amount is greater
|
2001-10-12 01:56:33 +02:00
|
|
|
|
* than 31 or less than 0, then the shift amount should be
|
|
|
|
|
* mod 32. In reality the mips assembler issues an error.
|
1999-05-03 09:29:11 +02:00
|
|
|
|
* We issue a warning and mask out all but the low 5 bits.
|
|
|
|
|
*/
|
|
|
|
|
my_getExpression (&imm_expr, s);
|
|
|
|
|
check_absolute_expr (ip, &imm_expr);
|
|
|
|
|
if ((unsigned long) imm_expr.X_add_number > 31)
|
|
|
|
|
{
|
2002-05-31 04:27:15 +02:00
|
|
|
|
as_warn (_("Improper shift amount (%lu)"),
|
|
|
|
|
(unsigned long) imm_expr.X_add_number);
|
2001-08-07 15:22:46 +02:00
|
|
|
|
imm_expr.X_add_number &= OP_MASK_SHAMT;
|
1999-05-03 09:29:11 +02:00
|
|
|
|
}
|
2001-08-07 15:22:46 +02:00
|
|
|
|
ip->insn_opcode |= imm_expr.X_add_number << OP_SH_SHAMT;
|
1999-05-03 09:29:11 +02:00
|
|
|
|
imm_expr.X_op = O_absent;
|
|
|
|
|
s = expr_end;
|
|
|
|
|
continue;
|
|
|
|
|
|
|
|
|
|
case '>': /* shift amount minus 32 */
|
|
|
|
|
my_getExpression (&imm_expr, s);
|
|
|
|
|
check_absolute_expr (ip, &imm_expr);
|
|
|
|
|
if ((unsigned long) imm_expr.X_add_number < 32
|
|
|
|
|
|| (unsigned long) imm_expr.X_add_number > 63)
|
|
|
|
|
break;
|
2001-08-07 15:22:46 +02:00
|
|
|
|
ip->insn_opcode |= (imm_expr.X_add_number - 32) << OP_SH_SHAMT;
|
1999-05-03 09:29:11 +02:00
|
|
|
|
imm_expr.X_op = O_absent;
|
|
|
|
|
s = expr_end;
|
|
|
|
|
continue;
|
|
|
|
|
|
|
|
|
|
case 'k': /* cache code */
|
|
|
|
|
case 'h': /* prefx code */
|
|
|
|
|
my_getExpression (&imm_expr, s);
|
|
|
|
|
check_absolute_expr (ip, &imm_expr);
|
|
|
|
|
if ((unsigned long) imm_expr.X_add_number > 31)
|
|
|
|
|
{
|
|
|
|
|
as_warn (_("Invalid value for `%s' (%lu)"),
|
|
|
|
|
ip->insn_mo->name,
|
|
|
|
|
(unsigned long) imm_expr.X_add_number);
|
|
|
|
|
imm_expr.X_add_number &= 0x1f;
|
|
|
|
|
}
|
|
|
|
|
if (*args == 'k')
|
|
|
|
|
ip->insn_opcode |= imm_expr.X_add_number << OP_SH_CACHE;
|
|
|
|
|
else
|
|
|
|
|
ip->insn_opcode |= imm_expr.X_add_number << OP_SH_PREFX;
|
|
|
|
|
imm_expr.X_op = O_absent;
|
|
|
|
|
s = expr_end;
|
|
|
|
|
continue;
|
|
|
|
|
|
|
|
|
|
case 'c': /* break code */
|
|
|
|
|
my_getExpression (&imm_expr, s);
|
|
|
|
|
check_absolute_expr (ip, &imm_expr);
|
2002-05-31 04:27:15 +02:00
|
|
|
|
if ((unsigned long) imm_expr.X_add_number > 1023)
|
1999-05-03 09:29:11 +02:00
|
|
|
|
{
|
2002-05-31 04:27:15 +02:00
|
|
|
|
as_warn (_("Illegal break code (%lu)"),
|
|
|
|
|
(unsigned long) imm_expr.X_add_number);
|
2001-08-07 15:22:46 +02:00
|
|
|
|
imm_expr.X_add_number &= OP_MASK_CODE;
|
1999-05-03 09:29:11 +02:00
|
|
|
|
}
|
2001-08-07 15:22:46 +02:00
|
|
|
|
ip->insn_opcode |= imm_expr.X_add_number << OP_SH_CODE;
|
1999-05-03 09:29:11 +02:00
|
|
|
|
imm_expr.X_op = O_absent;
|
|
|
|
|
s = expr_end;
|
|
|
|
|
continue;
|
|
|
|
|
|
|
|
|
|
case 'q': /* lower break code */
|
|
|
|
|
my_getExpression (&imm_expr, s);
|
|
|
|
|
check_absolute_expr (ip, &imm_expr);
|
2002-05-31 04:27:15 +02:00
|
|
|
|
if ((unsigned long) imm_expr.X_add_number > 1023)
|
1999-05-03 09:29:11 +02:00
|
|
|
|
{
|
2002-05-31 04:27:15 +02:00
|
|
|
|
as_warn (_("Illegal lower break code (%lu)"),
|
|
|
|
|
(unsigned long) imm_expr.X_add_number);
|
2001-08-07 15:22:46 +02:00
|
|
|
|
imm_expr.X_add_number &= OP_MASK_CODE2;
|
1999-05-03 09:29:11 +02:00
|
|
|
|
}
|
2001-08-07 15:22:46 +02:00
|
|
|
|
ip->insn_opcode |= imm_expr.X_add_number << OP_SH_CODE2;
|
1999-05-03 09:29:11 +02:00
|
|
|
|
imm_expr.X_op = O_absent;
|
|
|
|
|
s = expr_end;
|
|
|
|
|
continue;
|
|
|
|
|
|
2000-12-01 21:05:32 +01:00
|
|
|
|
case 'B': /* 20-bit syscall/break code. */
|
2000-09-14 03:47:38 +02:00
|
|
|
|
my_getExpression (&imm_expr, s);
|
|
|
|
|
check_absolute_expr (ip, &imm_expr);
|
2002-05-31 04:27:15 +02:00
|
|
|
|
if ((unsigned long) imm_expr.X_add_number > OP_MASK_CODE20)
|
|
|
|
|
as_warn (_("Illegal 20-bit code (%lu)"),
|
|
|
|
|
(unsigned long) imm_expr.X_add_number);
|
2001-08-07 15:22:46 +02:00
|
|
|
|
ip->insn_opcode |= imm_expr.X_add_number << OP_SH_CODE20;
|
1999-05-03 09:29:11 +02:00
|
|
|
|
imm_expr.X_op = O_absent;
|
|
|
|
|
s = expr_end;
|
|
|
|
|
continue;
|
|
|
|
|
|
2002-05-04 19:38:00 +02:00
|
|
|
|
case 'C': /* Coprocessor code */
|
2000-12-05 19:51:08 +01:00
|
|
|
|
my_getExpression (&imm_expr, s);
|
1999-05-03 09:29:11 +02:00
|
|
|
|
check_absolute_expr (ip, &imm_expr);
|
2002-05-04 19:38:00 +02:00
|
|
|
|
if ((unsigned long) imm_expr.X_add_number >= (1 << 25))
|
1999-05-03 09:29:11 +02:00
|
|
|
|
{
|
2002-05-31 04:27:15 +02:00
|
|
|
|
as_warn (_("Coproccesor code > 25 bits (%lu)"),
|
|
|
|
|
(unsigned long) imm_expr.X_add_number);
|
2002-05-04 19:38:00 +02:00
|
|
|
|
imm_expr.X_add_number &= ((1 << 25) - 1);
|
1999-05-03 09:29:11 +02:00
|
|
|
|
}
|
2000-12-05 19:51:08 +01:00
|
|
|
|
ip->insn_opcode |= imm_expr.X_add_number;
|
|
|
|
|
imm_expr.X_op = O_absent;
|
|
|
|
|
s = expr_end;
|
|
|
|
|
continue;
|
1999-05-03 09:29:11 +02:00
|
|
|
|
|
2000-12-01 21:05:32 +01:00
|
|
|
|
case 'J': /* 19-bit wait code. */
|
|
|
|
|
my_getExpression (&imm_expr, s);
|
|
|
|
|
check_absolute_expr (ip, &imm_expr);
|
2002-05-31 04:27:15 +02:00
|
|
|
|
if ((unsigned long) imm_expr.X_add_number > OP_MASK_CODE19)
|
|
|
|
|
as_warn (_("Illegal 19-bit code (%lu)"),
|
|
|
|
|
(unsigned long) imm_expr.X_add_number);
|
2001-08-07 15:22:46 +02:00
|
|
|
|
ip->insn_opcode |= imm_expr.X_add_number << OP_SH_CODE19;
|
2000-12-01 21:05:32 +01:00
|
|
|
|
imm_expr.X_op = O_absent;
|
|
|
|
|
s = expr_end;
|
|
|
|
|
continue;
|
|
|
|
|
|
1999-05-03 09:29:11 +02:00
|
|
|
|
case 'P': /* Performance register */
|
2000-12-05 19:51:08 +01:00
|
|
|
|
my_getExpression (&imm_expr, s);
|
1999-05-03 09:29:11 +02:00
|
|
|
|
check_absolute_expr (ip, &imm_expr);
|
2000-12-05 19:51:08 +01:00
|
|
|
|
if (imm_expr.X_add_number != 0 && imm_expr.X_add_number != 1)
|
1999-05-03 09:29:11 +02:00
|
|
|
|
{
|
2002-05-31 04:27:15 +02:00
|
|
|
|
as_warn (_("Invalid performance register (%lu)"),
|
|
|
|
|
(unsigned long) imm_expr.X_add_number);
|
2001-08-07 15:22:46 +02:00
|
|
|
|
imm_expr.X_add_number &= OP_MASK_PERFREG;
|
1999-05-03 09:29:11 +02:00
|
|
|
|
}
|
2001-08-07 15:22:46 +02:00
|
|
|
|
ip->insn_opcode |= (imm_expr.X_add_number << OP_SH_PERFREG);
|
2000-12-05 19:51:08 +01:00
|
|
|
|
imm_expr.X_op = O_absent;
|
|
|
|
|
s = expr_end;
|
|
|
|
|
continue;
|
1999-05-03 09:29:11 +02:00
|
|
|
|
|
|
|
|
|
case 'b': /* base register */
|
|
|
|
|
case 'd': /* destination register */
|
|
|
|
|
case 's': /* source register */
|
|
|
|
|
case 't': /* target register */
|
|
|
|
|
case 'r': /* both target and source */
|
|
|
|
|
case 'v': /* both dest and source */
|
|
|
|
|
case 'w': /* both dest and target */
|
|
|
|
|
case 'E': /* coprocessor target register */
|
|
|
|
|
case 'G': /* coprocessor destination register */
|
[ bfd/ChangeLog ]
2002-12-30 Chris Demetriou <cgd@broadcom.com>
* aoutx.h (NAME(aout,machine_type)): Add bfd_mach_mipsisa32r2 case.
* archures.c (bfd_mach_mipsisa32r2): New define.
* bfd-in2.h: Regenerate.
* cpu-mips.c (I_mipsisa32r2): New enum value.
(arch_info_struct): Add entry for I_mipsisa32r2.
* elfxx-mips.c (elf_mips_isa, _bfd_elf_mips_mach)
(_bfd_mips_elf_print_private_bfd_data): Handle E_MIPS_ARCH_32R2.
(_bfd_mips_elf_final_write_processing): Add
bfd_mach_mipsisa32r2 case.
(_bfd_mips_elf_merge_private_bfd_data): Handle merging of
binaries marked as using MIPS32 Release 2.
[ binutils/ChangeLog ]
2002-12-30 Chris Demetriou <cgd@broadcom.com>
* doc/binutils.texi (objdump): Note MIPS HWR (Hardware Register)
changes in MIPS -M options.
[ gas/ChangeLog ]
2002-12-30 Chris Demetriou <cgd@broadcom.com>
* configure.in: Recognize mipsisa32r2, mipsisa32r2el, and
CPU variants.
* configure: Regenerate.
* config/tc-mips.c (ISA_HAS_DROR, ISA_HAS_ROR): New defines.
(macro_build): Handle "K" operand.
(macro2): Use ISA_HAS_DROR and ISA_HAS_ROR in the places where
CPU_HAS_DROR and CPU_HAS_ROR are currently used.
(mips_ip): New variable "lastpos", and implement "+A", "+B",
and "+C" operands for MIPS32 Release 2 ins/ext instructions.
Implement "K" operand for MIPS32 Release 2 rdhwr instruction.
(validate_mips_insn): Implement "+" as a way to extend the
allowed operands, and implement "K", "+A", "+B", and "+C"
operands.
(OPTION_MIPS32R2): New define.
(md_longopts): Add entry for OPTION_MIPS32R2.
(OPTION_ELF_BASE): Adjust to accomodate OPTIONS_MIPS32R2.
(md_parse_option): Handle OPTION_MIPS32R2.
(s_mipsset): Reimplement handling of ".set mipsN" options
and add support for ".set mips32r2".
(mips_cpu_info_table): Add entry for "mips32r2" (MIPS32 Release 2).
(md_show_usage): Document "-mips32r2" option.
* doc/as.texinfo: Document "-mips32r2" option.
* doc/c-mips.texi: Likewise.
[ gas/testsuite/ChangeLog ]
2002-12-30 Chris Demetriou <cgd@broadcom.com>
* gas/mips/cp0-names-mips32r2.d: New test.
* gas/mips/hwr-names-mips32r2.d: New test.
* gas/mips/hwr-names-numeric.d: New test.
* gas/mips/hwr-names.s: New test source file.
* gas/mips/mips32r2.d: New test.
* gas/mips/mips32r2.s: New test source file.
* gas/mips/mips32r2-ill.l: New test.
* gas/mips/mips32r2-ill.s: New test source file.
* gas/mips/mips.exp: Add mips32r2 architecture data array
entry. Run new tests mentioned above.
[ include/elf/ChangeLog ]
2002-12-30 Chris Demetriou <cgd@broadcom.com>
* mips.h (E_MIPS_ARCH_32R2): New define.
[ include/opcode/ChangeLog ]
2002-12-30 Chris Demetriou <cgd@broadcom.com>
* mips.h: Document "+" as the start of two-character operand
type names, and add new "K", "+A", "+B", and "+C" operand types.
(OP_MASK_INSMSB, OP_SH_INSMSB, OP_MASK_EXTMSB)
(OP_SH_EXTMSB, INSN_ISA32R2, ISA_MIPS32R2, CPU_MIPS32R2): New
defines.
[ opcodes/ChangeLog ]
2002-12-30 Chris Demetriou <cgd@broadcom.com>
* mips-dis.c (mips_cp0_names_mips3264r2, mips_hwr_names_numeric)
(mips_hwr_names_mips3264r2): New arrays.
(mips_arch_choice): New "hwr_names" member.
(mips_arch_choices): Adjust for structure change, and add a new
entry for "mips32r2" ISA.
(mips_hwr_names): New variable.
(set_default_mips_dis_options): Set mips_hwr_names.
(parse_mips_dis_option): New "hwr-names" option which sets
mips_hwr_names, and adjust "reg-names=ARCH" to set mips_hwr_names.
(print_insn_arg): Change return type to "int"
and use that to indicate number of characters consumed.
Add support for "+" operand extension character, "+A", "+B",
"+C", and "K" operands.
(print_insn_mips): Adjust for changes to print_insn_arg.
(print_mips_disassembler_options): Adjust for "hwr-names"
addition and "reg-names" change.
* mips-opc (I33): New define (shorthand for INSN_ISA32R2).
(mips_builtin_opcodes): Note that "nop" and "ssnop" are special
forms of "sll". Add new MIPS32 Release 2 instructions: ehb,
di, ei, ext, ins, jr.hb, jalr.hb, mfhc1, mfhc2, mthc1, mthc2,
rdhwr, rdpgpr, seb, seh, synci, wrpgpr, wsbh.
Note that hardware rotate instructions (ror, rorv) can be
used on MIPS32 Release 2, and add the official mnemonics
for them (rotr, rotrv) and the similar "rotl" mnemonic for
left-rotate.
2002-12-31 08:29:29 +01:00
|
|
|
|
case 'K': /* 'rdhwr' destination register */
|
1999-05-03 09:29:11 +02:00
|
|
|
|
case 'x': /* ignore register name */
|
|
|
|
|
case 'z': /* must be zero register */
|
2000-12-01 21:05:32 +01:00
|
|
|
|
case 'U': /* destination register (clo/clz). */
|
1999-05-03 09:29:11 +02:00
|
|
|
|
s_reset = s;
|
|
|
|
|
if (s[0] == '$')
|
|
|
|
|
{
|
|
|
|
|
|
2001-09-19 07:33:36 +02:00
|
|
|
|
if (ISDIGIT (s[1]))
|
1999-05-03 09:29:11 +02:00
|
|
|
|
{
|
|
|
|
|
++s;
|
|
|
|
|
regno = 0;
|
|
|
|
|
do
|
|
|
|
|
{
|
|
|
|
|
regno *= 10;
|
|
|
|
|
regno += *s - '0';
|
|
|
|
|
++s;
|
|
|
|
|
}
|
2001-09-19 07:33:36 +02:00
|
|
|
|
while (ISDIGIT (*s));
|
1999-05-03 09:29:11 +02:00
|
|
|
|
if (regno > 31)
|
|
|
|
|
as_bad (_("Invalid register number (%d)"), regno);
|
|
|
|
|
}
|
[ bfd/ChangeLog ]
2002-12-30 Chris Demetriou <cgd@broadcom.com>
* aoutx.h (NAME(aout,machine_type)): Add bfd_mach_mipsisa32r2 case.
* archures.c (bfd_mach_mipsisa32r2): New define.
* bfd-in2.h: Regenerate.
* cpu-mips.c (I_mipsisa32r2): New enum value.
(arch_info_struct): Add entry for I_mipsisa32r2.
* elfxx-mips.c (elf_mips_isa, _bfd_elf_mips_mach)
(_bfd_mips_elf_print_private_bfd_data): Handle E_MIPS_ARCH_32R2.
(_bfd_mips_elf_final_write_processing): Add
bfd_mach_mipsisa32r2 case.
(_bfd_mips_elf_merge_private_bfd_data): Handle merging of
binaries marked as using MIPS32 Release 2.
[ binutils/ChangeLog ]
2002-12-30 Chris Demetriou <cgd@broadcom.com>
* doc/binutils.texi (objdump): Note MIPS HWR (Hardware Register)
changes in MIPS -M options.
[ gas/ChangeLog ]
2002-12-30 Chris Demetriou <cgd@broadcom.com>
* configure.in: Recognize mipsisa32r2, mipsisa32r2el, and
CPU variants.
* configure: Regenerate.
* config/tc-mips.c (ISA_HAS_DROR, ISA_HAS_ROR): New defines.
(macro_build): Handle "K" operand.
(macro2): Use ISA_HAS_DROR and ISA_HAS_ROR in the places where
CPU_HAS_DROR and CPU_HAS_ROR are currently used.
(mips_ip): New variable "lastpos", and implement "+A", "+B",
and "+C" operands for MIPS32 Release 2 ins/ext instructions.
Implement "K" operand for MIPS32 Release 2 rdhwr instruction.
(validate_mips_insn): Implement "+" as a way to extend the
allowed operands, and implement "K", "+A", "+B", and "+C"
operands.
(OPTION_MIPS32R2): New define.
(md_longopts): Add entry for OPTION_MIPS32R2.
(OPTION_ELF_BASE): Adjust to accomodate OPTIONS_MIPS32R2.
(md_parse_option): Handle OPTION_MIPS32R2.
(s_mipsset): Reimplement handling of ".set mipsN" options
and add support for ".set mips32r2".
(mips_cpu_info_table): Add entry for "mips32r2" (MIPS32 Release 2).
(md_show_usage): Document "-mips32r2" option.
* doc/as.texinfo: Document "-mips32r2" option.
* doc/c-mips.texi: Likewise.
[ gas/testsuite/ChangeLog ]
2002-12-30 Chris Demetriou <cgd@broadcom.com>
* gas/mips/cp0-names-mips32r2.d: New test.
* gas/mips/hwr-names-mips32r2.d: New test.
* gas/mips/hwr-names-numeric.d: New test.
* gas/mips/hwr-names.s: New test source file.
* gas/mips/mips32r2.d: New test.
* gas/mips/mips32r2.s: New test source file.
* gas/mips/mips32r2-ill.l: New test.
* gas/mips/mips32r2-ill.s: New test source file.
* gas/mips/mips.exp: Add mips32r2 architecture data array
entry. Run new tests mentioned above.
[ include/elf/ChangeLog ]
2002-12-30 Chris Demetriou <cgd@broadcom.com>
* mips.h (E_MIPS_ARCH_32R2): New define.
[ include/opcode/ChangeLog ]
2002-12-30 Chris Demetriou <cgd@broadcom.com>
* mips.h: Document "+" as the start of two-character operand
type names, and add new "K", "+A", "+B", and "+C" operand types.
(OP_MASK_INSMSB, OP_SH_INSMSB, OP_MASK_EXTMSB)
(OP_SH_EXTMSB, INSN_ISA32R2, ISA_MIPS32R2, CPU_MIPS32R2): New
defines.
[ opcodes/ChangeLog ]
2002-12-30 Chris Demetriou <cgd@broadcom.com>
* mips-dis.c (mips_cp0_names_mips3264r2, mips_hwr_names_numeric)
(mips_hwr_names_mips3264r2): New arrays.
(mips_arch_choice): New "hwr_names" member.
(mips_arch_choices): Adjust for structure change, and add a new
entry for "mips32r2" ISA.
(mips_hwr_names): New variable.
(set_default_mips_dis_options): Set mips_hwr_names.
(parse_mips_dis_option): New "hwr-names" option which sets
mips_hwr_names, and adjust "reg-names=ARCH" to set mips_hwr_names.
(print_insn_arg): Change return type to "int"
and use that to indicate number of characters consumed.
Add support for "+" operand extension character, "+A", "+B",
"+C", and "K" operands.
(print_insn_mips): Adjust for changes to print_insn_arg.
(print_mips_disassembler_options): Adjust for "hwr-names"
addition and "reg-names" change.
* mips-opc (I33): New define (shorthand for INSN_ISA32R2).
(mips_builtin_opcodes): Note that "nop" and "ssnop" are special
forms of "sll". Add new MIPS32 Release 2 instructions: ehb,
di, ei, ext, ins, jr.hb, jalr.hb, mfhc1, mfhc2, mthc1, mthc2,
rdhwr, rdpgpr, seb, seh, synci, wrpgpr, wsbh.
Note that hardware rotate instructions (ror, rorv) can be
used on MIPS32 Release 2, and add the official mnemonics
for them (rotr, rotrv) and the similar "rotl" mnemonic for
left-rotate.
2002-12-31 08:29:29 +01:00
|
|
|
|
else if (*args == 'E' || *args == 'G' || *args == 'K')
|
1999-05-03 09:29:11 +02:00
|
|
|
|
goto notreg;
|
|
|
|
|
else
|
|
|
|
|
{
|
2002-05-31 03:58:18 +02:00
|
|
|
|
if (s[1] == 'r' && s[2] == 'a')
|
|
|
|
|
{
|
|
|
|
|
s += 3;
|
|
|
|
|
regno = RA;
|
|
|
|
|
}
|
|
|
|
|
else if (s[1] == 'f' && s[2] == 'p')
|
1999-05-03 09:29:11 +02:00
|
|
|
|
{
|
|
|
|
|
s += 3;
|
|
|
|
|
regno = FP;
|
|
|
|
|
}
|
|
|
|
|
else if (s[1] == 's' && s[2] == 'p')
|
|
|
|
|
{
|
|
|
|
|
s += 3;
|
|
|
|
|
regno = SP;
|
|
|
|
|
}
|
|
|
|
|
else if (s[1] == 'g' && s[2] == 'p')
|
|
|
|
|
{
|
|
|
|
|
s += 3;
|
|
|
|
|
regno = GP;
|
|
|
|
|
}
|
|
|
|
|
else if (s[1] == 'a' && s[2] == 't')
|
|
|
|
|
{
|
|
|
|
|
s += 3;
|
|
|
|
|
regno = AT;
|
|
|
|
|
}
|
|
|
|
|
else if (s[1] == 'k' && s[2] == 't' && s[3] == '0')
|
|
|
|
|
{
|
|
|
|
|
s += 4;
|
|
|
|
|
regno = KT0;
|
|
|
|
|
}
|
|
|
|
|
else if (s[1] == 'k' && s[2] == 't' && s[3] == '1')
|
|
|
|
|
{
|
|
|
|
|
s += 4;
|
|
|
|
|
regno = KT1;
|
|
|
|
|
}
|
2002-06-08 00:54:47 +02:00
|
|
|
|
else if (s[1] == 'z' && s[2] == 'e' && s[3] == 'r' && s[4] == 'o')
|
|
|
|
|
{
|
|
|
|
|
s += 5;
|
|
|
|
|
regno = ZERO;
|
|
|
|
|
}
|
1999-05-03 09:29:11 +02:00
|
|
|
|
else if (itbl_have_entries)
|
|
|
|
|
{
|
|
|
|
|
char *p, *n;
|
1999-06-10 22:35:50 +02:00
|
|
|
|
unsigned long r;
|
1999-05-03 09:29:11 +02:00
|
|
|
|
|
1999-06-10 22:35:50 +02:00
|
|
|
|
p = s + 1; /* advance past '$' */
|
1999-05-03 09:29:11 +02:00
|
|
|
|
n = itbl_get_field (&p); /* n is name */
|
|
|
|
|
|
1999-06-10 22:35:50 +02:00
|
|
|
|
/* See if this is a register defined in an
|
|
|
|
|
itbl entry. */
|
|
|
|
|
if (itbl_get_reg_val (n, &r))
|
1999-05-03 09:29:11 +02:00
|
|
|
|
{
|
|
|
|
|
/* Get_field advances to the start of
|
|
|
|
|
the next field, so we need to back
|
1999-06-10 22:35:50 +02:00
|
|
|
|
rack to the end of the last field. */
|
2000-09-07 14:45:56 +02:00
|
|
|
|
if (p)
|
1999-05-03 09:29:11 +02:00
|
|
|
|
s = p - 1;
|
2000-09-07 14:45:56 +02:00
|
|
|
|
else
|
1999-06-10 22:35:50 +02:00
|
|
|
|
s = strchr (s, '\0');
|
1999-05-03 09:29:11 +02:00
|
|
|
|
regno = r;
|
|
|
|
|
}
|
|
|
|
|
else
|
|
|
|
|
goto notreg;
|
2000-12-05 19:51:08 +01:00
|
|
|
|
}
|
1999-05-03 09:29:11 +02:00
|
|
|
|
else
|
|
|
|
|
goto notreg;
|
|
|
|
|
}
|
|
|
|
|
if (regno == AT
|
|
|
|
|
&& ! mips_opts.noat
|
|
|
|
|
&& *args != 'E'
|
[ bfd/ChangeLog ]
2002-12-30 Chris Demetriou <cgd@broadcom.com>
* aoutx.h (NAME(aout,machine_type)): Add bfd_mach_mipsisa32r2 case.
* archures.c (bfd_mach_mipsisa32r2): New define.
* bfd-in2.h: Regenerate.
* cpu-mips.c (I_mipsisa32r2): New enum value.
(arch_info_struct): Add entry for I_mipsisa32r2.
* elfxx-mips.c (elf_mips_isa, _bfd_elf_mips_mach)
(_bfd_mips_elf_print_private_bfd_data): Handle E_MIPS_ARCH_32R2.
(_bfd_mips_elf_final_write_processing): Add
bfd_mach_mipsisa32r2 case.
(_bfd_mips_elf_merge_private_bfd_data): Handle merging of
binaries marked as using MIPS32 Release 2.
[ binutils/ChangeLog ]
2002-12-30 Chris Demetriou <cgd@broadcom.com>
* doc/binutils.texi (objdump): Note MIPS HWR (Hardware Register)
changes in MIPS -M options.
[ gas/ChangeLog ]
2002-12-30 Chris Demetriou <cgd@broadcom.com>
* configure.in: Recognize mipsisa32r2, mipsisa32r2el, and
CPU variants.
* configure: Regenerate.
* config/tc-mips.c (ISA_HAS_DROR, ISA_HAS_ROR): New defines.
(macro_build): Handle "K" operand.
(macro2): Use ISA_HAS_DROR and ISA_HAS_ROR in the places where
CPU_HAS_DROR and CPU_HAS_ROR are currently used.
(mips_ip): New variable "lastpos", and implement "+A", "+B",
and "+C" operands for MIPS32 Release 2 ins/ext instructions.
Implement "K" operand for MIPS32 Release 2 rdhwr instruction.
(validate_mips_insn): Implement "+" as a way to extend the
allowed operands, and implement "K", "+A", "+B", and "+C"
operands.
(OPTION_MIPS32R2): New define.
(md_longopts): Add entry for OPTION_MIPS32R2.
(OPTION_ELF_BASE): Adjust to accomodate OPTIONS_MIPS32R2.
(md_parse_option): Handle OPTION_MIPS32R2.
(s_mipsset): Reimplement handling of ".set mipsN" options
and add support for ".set mips32r2".
(mips_cpu_info_table): Add entry for "mips32r2" (MIPS32 Release 2).
(md_show_usage): Document "-mips32r2" option.
* doc/as.texinfo: Document "-mips32r2" option.
* doc/c-mips.texi: Likewise.
[ gas/testsuite/ChangeLog ]
2002-12-30 Chris Demetriou <cgd@broadcom.com>
* gas/mips/cp0-names-mips32r2.d: New test.
* gas/mips/hwr-names-mips32r2.d: New test.
* gas/mips/hwr-names-numeric.d: New test.
* gas/mips/hwr-names.s: New test source file.
* gas/mips/mips32r2.d: New test.
* gas/mips/mips32r2.s: New test source file.
* gas/mips/mips32r2-ill.l: New test.
* gas/mips/mips32r2-ill.s: New test source file.
* gas/mips/mips.exp: Add mips32r2 architecture data array
entry. Run new tests mentioned above.
[ include/elf/ChangeLog ]
2002-12-30 Chris Demetriou <cgd@broadcom.com>
* mips.h (E_MIPS_ARCH_32R2): New define.
[ include/opcode/ChangeLog ]
2002-12-30 Chris Demetriou <cgd@broadcom.com>
* mips.h: Document "+" as the start of two-character operand
type names, and add new "K", "+A", "+B", and "+C" operand types.
(OP_MASK_INSMSB, OP_SH_INSMSB, OP_MASK_EXTMSB)
(OP_SH_EXTMSB, INSN_ISA32R2, ISA_MIPS32R2, CPU_MIPS32R2): New
defines.
[ opcodes/ChangeLog ]
2002-12-30 Chris Demetriou <cgd@broadcom.com>
* mips-dis.c (mips_cp0_names_mips3264r2, mips_hwr_names_numeric)
(mips_hwr_names_mips3264r2): New arrays.
(mips_arch_choice): New "hwr_names" member.
(mips_arch_choices): Adjust for structure change, and add a new
entry for "mips32r2" ISA.
(mips_hwr_names): New variable.
(set_default_mips_dis_options): Set mips_hwr_names.
(parse_mips_dis_option): New "hwr-names" option which sets
mips_hwr_names, and adjust "reg-names=ARCH" to set mips_hwr_names.
(print_insn_arg): Change return type to "int"
and use that to indicate number of characters consumed.
Add support for "+" operand extension character, "+A", "+B",
"+C", and "K" operands.
(print_insn_mips): Adjust for changes to print_insn_arg.
(print_mips_disassembler_options): Adjust for "hwr-names"
addition and "reg-names" change.
* mips-opc (I33): New define (shorthand for INSN_ISA32R2).
(mips_builtin_opcodes): Note that "nop" and "ssnop" are special
forms of "sll". Add new MIPS32 Release 2 instructions: ehb,
di, ei, ext, ins, jr.hb, jalr.hb, mfhc1, mfhc2, mthc1, mthc2,
rdhwr, rdpgpr, seb, seh, synci, wrpgpr, wsbh.
Note that hardware rotate instructions (ror, rorv) can be
used on MIPS32 Release 2, and add the official mnemonics
for them (rotr, rotrv) and the similar "rotl" mnemonic for
left-rotate.
2002-12-31 08:29:29 +01:00
|
|
|
|
&& *args != 'G'
|
|
|
|
|
&& *args != 'K')
|
1999-05-03 09:29:11 +02:00
|
|
|
|
as_warn (_("Used $at without \".set noat\""));
|
|
|
|
|
c = *args;
|
|
|
|
|
if (*s == ' ')
|
2002-05-26 20:46:37 +02:00
|
|
|
|
++s;
|
1999-05-03 09:29:11 +02:00
|
|
|
|
if (args[1] != *s)
|
|
|
|
|
{
|
|
|
|
|
if (c == 'r' || c == 'v' || c == 'w')
|
|
|
|
|
{
|
|
|
|
|
regno = lastregno;
|
|
|
|
|
s = s_reset;
|
2002-05-26 20:46:37 +02:00
|
|
|
|
++args;
|
1999-05-03 09:29:11 +02:00
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
/* 'z' only matches $0. */
|
|
|
|
|
if (c == 'z' && regno != 0)
|
|
|
|
|
break;
|
|
|
|
|
|
2000-09-07 14:45:56 +02:00
|
|
|
|
/* Now that we have assembled one operand, we use the args string
|
|
|
|
|
* to figure out where it goes in the instruction. */
|
1999-05-03 09:29:11 +02:00
|
|
|
|
switch (c)
|
|
|
|
|
{
|
|
|
|
|
case 'r':
|
|
|
|
|
case 's':
|
|
|
|
|
case 'v':
|
|
|
|
|
case 'b':
|
2001-08-07 15:22:46 +02:00
|
|
|
|
ip->insn_opcode |= regno << OP_SH_RS;
|
1999-05-03 09:29:11 +02:00
|
|
|
|
break;
|
|
|
|
|
case 'd':
|
|
|
|
|
case 'G':
|
[ bfd/ChangeLog ]
2002-12-30 Chris Demetriou <cgd@broadcom.com>
* aoutx.h (NAME(aout,machine_type)): Add bfd_mach_mipsisa32r2 case.
* archures.c (bfd_mach_mipsisa32r2): New define.
* bfd-in2.h: Regenerate.
* cpu-mips.c (I_mipsisa32r2): New enum value.
(arch_info_struct): Add entry for I_mipsisa32r2.
* elfxx-mips.c (elf_mips_isa, _bfd_elf_mips_mach)
(_bfd_mips_elf_print_private_bfd_data): Handle E_MIPS_ARCH_32R2.
(_bfd_mips_elf_final_write_processing): Add
bfd_mach_mipsisa32r2 case.
(_bfd_mips_elf_merge_private_bfd_data): Handle merging of
binaries marked as using MIPS32 Release 2.
[ binutils/ChangeLog ]
2002-12-30 Chris Demetriou <cgd@broadcom.com>
* doc/binutils.texi (objdump): Note MIPS HWR (Hardware Register)
changes in MIPS -M options.
[ gas/ChangeLog ]
2002-12-30 Chris Demetriou <cgd@broadcom.com>
* configure.in: Recognize mipsisa32r2, mipsisa32r2el, and
CPU variants.
* configure: Regenerate.
* config/tc-mips.c (ISA_HAS_DROR, ISA_HAS_ROR): New defines.
(macro_build): Handle "K" operand.
(macro2): Use ISA_HAS_DROR and ISA_HAS_ROR in the places where
CPU_HAS_DROR and CPU_HAS_ROR are currently used.
(mips_ip): New variable "lastpos", and implement "+A", "+B",
and "+C" operands for MIPS32 Release 2 ins/ext instructions.
Implement "K" operand for MIPS32 Release 2 rdhwr instruction.
(validate_mips_insn): Implement "+" as a way to extend the
allowed operands, and implement "K", "+A", "+B", and "+C"
operands.
(OPTION_MIPS32R2): New define.
(md_longopts): Add entry for OPTION_MIPS32R2.
(OPTION_ELF_BASE): Adjust to accomodate OPTIONS_MIPS32R2.
(md_parse_option): Handle OPTION_MIPS32R2.
(s_mipsset): Reimplement handling of ".set mipsN" options
and add support for ".set mips32r2".
(mips_cpu_info_table): Add entry for "mips32r2" (MIPS32 Release 2).
(md_show_usage): Document "-mips32r2" option.
* doc/as.texinfo: Document "-mips32r2" option.
* doc/c-mips.texi: Likewise.
[ gas/testsuite/ChangeLog ]
2002-12-30 Chris Demetriou <cgd@broadcom.com>
* gas/mips/cp0-names-mips32r2.d: New test.
* gas/mips/hwr-names-mips32r2.d: New test.
* gas/mips/hwr-names-numeric.d: New test.
* gas/mips/hwr-names.s: New test source file.
* gas/mips/mips32r2.d: New test.
* gas/mips/mips32r2.s: New test source file.
* gas/mips/mips32r2-ill.l: New test.
* gas/mips/mips32r2-ill.s: New test source file.
* gas/mips/mips.exp: Add mips32r2 architecture data array
entry. Run new tests mentioned above.
[ include/elf/ChangeLog ]
2002-12-30 Chris Demetriou <cgd@broadcom.com>
* mips.h (E_MIPS_ARCH_32R2): New define.
[ include/opcode/ChangeLog ]
2002-12-30 Chris Demetriou <cgd@broadcom.com>
* mips.h: Document "+" as the start of two-character operand
type names, and add new "K", "+A", "+B", and "+C" operand types.
(OP_MASK_INSMSB, OP_SH_INSMSB, OP_MASK_EXTMSB)
(OP_SH_EXTMSB, INSN_ISA32R2, ISA_MIPS32R2, CPU_MIPS32R2): New
defines.
[ opcodes/ChangeLog ]
2002-12-30 Chris Demetriou <cgd@broadcom.com>
* mips-dis.c (mips_cp0_names_mips3264r2, mips_hwr_names_numeric)
(mips_hwr_names_mips3264r2): New arrays.
(mips_arch_choice): New "hwr_names" member.
(mips_arch_choices): Adjust for structure change, and add a new
entry for "mips32r2" ISA.
(mips_hwr_names): New variable.
(set_default_mips_dis_options): Set mips_hwr_names.
(parse_mips_dis_option): New "hwr-names" option which sets
mips_hwr_names, and adjust "reg-names=ARCH" to set mips_hwr_names.
(print_insn_arg): Change return type to "int"
and use that to indicate number of characters consumed.
Add support for "+" operand extension character, "+A", "+B",
"+C", and "K" operands.
(print_insn_mips): Adjust for changes to print_insn_arg.
(print_mips_disassembler_options): Adjust for "hwr-names"
addition and "reg-names" change.
* mips-opc (I33): New define (shorthand for INSN_ISA32R2).
(mips_builtin_opcodes): Note that "nop" and "ssnop" are special
forms of "sll". Add new MIPS32 Release 2 instructions: ehb,
di, ei, ext, ins, jr.hb, jalr.hb, mfhc1, mfhc2, mthc1, mthc2,
rdhwr, rdpgpr, seb, seh, synci, wrpgpr, wsbh.
Note that hardware rotate instructions (ror, rorv) can be
used on MIPS32 Release 2, and add the official mnemonics
for them (rotr, rotrv) and the similar "rotl" mnemonic for
left-rotate.
2002-12-31 08:29:29 +01:00
|
|
|
|
case 'K':
|
2001-08-07 15:22:46 +02:00
|
|
|
|
ip->insn_opcode |= regno << OP_SH_RD;
|
1999-05-03 09:29:11 +02:00
|
|
|
|
break;
|
2000-12-01 21:05:32 +01:00
|
|
|
|
case 'U':
|
2001-08-07 15:22:46 +02:00
|
|
|
|
ip->insn_opcode |= regno << OP_SH_RD;
|
|
|
|
|
ip->insn_opcode |= regno << OP_SH_RT;
|
2000-12-01 21:05:32 +01:00
|
|
|
|
break;
|
1999-05-03 09:29:11 +02:00
|
|
|
|
case 'w':
|
|
|
|
|
case 't':
|
|
|
|
|
case 'E':
|
2001-08-07 15:22:46 +02:00
|
|
|
|
ip->insn_opcode |= regno << OP_SH_RT;
|
1999-05-03 09:29:11 +02:00
|
|
|
|
break;
|
|
|
|
|
case 'x':
|
|
|
|
|
/* This case exists because on the r3000 trunc
|
|
|
|
|
expands into a macro which requires a gp
|
|
|
|
|
register. On the r6000 or r4000 it is
|
|
|
|
|
assembled into a single instruction which
|
|
|
|
|
ignores the register. Thus the insn version
|
|
|
|
|
is MIPS_ISA2 and uses 'x', and the macro
|
|
|
|
|
version is MIPS_ISA1 and uses 't'. */
|
|
|
|
|
break;
|
|
|
|
|
case 'z':
|
|
|
|
|
/* This case is for the div instruction, which
|
|
|
|
|
acts differently if the destination argument
|
|
|
|
|
is $0. This only matches $0, and is checked
|
|
|
|
|
outside the switch. */
|
|
|
|
|
break;
|
|
|
|
|
case 'D':
|
|
|
|
|
/* Itbl operand; not yet implemented. FIXME ?? */
|
|
|
|
|
break;
|
|
|
|
|
/* What about all other operands like 'i', which
|
|
|
|
|
can be specified in the opcode table? */
|
|
|
|
|
}
|
|
|
|
|
lastregno = regno;
|
|
|
|
|
continue;
|
|
|
|
|
}
|
|
|
|
|
notreg:
|
|
|
|
|
switch (*args++)
|
|
|
|
|
{
|
|
|
|
|
case 'r':
|
|
|
|
|
case 'v':
|
2001-08-07 15:22:46 +02:00
|
|
|
|
ip->insn_opcode |= lastregno << OP_SH_RS;
|
1999-05-03 09:29:11 +02:00
|
|
|
|
continue;
|
|
|
|
|
case 'w':
|
2001-08-07 15:22:46 +02:00
|
|
|
|
ip->insn_opcode |= lastregno << OP_SH_RT;
|
1999-05-03 09:29:11 +02:00
|
|
|
|
continue;
|
|
|
|
|
}
|
|
|
|
|
break;
|
|
|
|
|
|
[ gas/ChangeLog ]
2002-05-30 Chris G. Demetriou <cgd@broadcom.com>
Ed Satterthwaite <ehs@broadcom.com>
* config/tc-mips.c (mips_set_options): New "ase_mdmx" member.
(mips_opts): Initialize "ase_mdmx" member.
(file_ase_mdmx): New variable.
(CPU_HAS_MDMX): New macro.
(md_begin): Initialize mips_opts.ase_mdmx and file_ase_mdmx
based on command line options and configuration defaults.
(macro_build): Note in comment that use of MDMX in macros is
not currently allowed.
(validate_mips_insn): Add support for the "O", "Q", "X", "Y", and
"Z" MDMX operand types.
(mips_ip): Accept MDMX instructions if mips_opts.ase_mdmx is set,
and add support for the "O", "Q", "X", "Y", and "Z" MDMX operand
types.
(OPTION_MDMX, OPTION_NO_MDMX, md_longopts, md_parse_option):
Add support for "-mdmx" and "-no-mdmx" options.
(OPTION_ELF_BASE): Move to accomodate new options.
(s_mipsset): Support ".set mdmx" and ".set nomdmx".
(mips_elf_final_processing): Set MDMX ASE ELF header flag if
file_ase_mdmx was set.
* doc/as.texinfo: Document -mdmx and -no-mdmx options.
* doc/c-mips.texi: Likewise, and document ".set mdmx" and ".set
nomdmx" directives.
[ gas/testsuite/ChangeLog ]
2002-05-30 Chris G. Demetriou <cgd@broadcom.com>
* gas/mips/mips64-mdmx.s: New file.
* gas/mips/mips64-mdmx.d: Likewise.
* gas/mips/mips.exp: Run new "mips64-mdmx" test.
[ include/opcode/ChangeLog ]
2002-05-30 Chris G. Demetriou <cgd@broadcom.com>
* mips.h (OP_SH_ALN, OP_MASK_ALN, OP_SH_VSEL, OP_MASK_VSEL)
(MDMX_FMTSEL_IMM_QH, MDMX_FMTSEL_IMM_OB, MDMX_FMTSEL_VEC_QH)
(MDMX_FMTSEL_VEC_OB, INSN_READ_MDMX_ACC, INSN_WRITE_MDMX_ACC)
(INSN_MDMX): New constants, for MDMX support.
(opcode character list): Add "O", "Q", "X", "Y", and "Z" for MDMX.
[ opcodes/ChangeLog ]
2002-05-30 Chris G. Demetriou <cgd@broadcom.com>
Ed Satterthwaite <ehs@broadcom.com>
* mips-dis.c (print_insn_arg): Add support for 'O', 'Q', 'X', 'Y',
and 'Z' formats, for MDMX.
(mips_isa_type): Add MDMX instructions to the ISA
bit mask for bfd_mach_mipsisa64.
* mips-opc.c: Add support for MDMX instructions.
(MX): New definition.
* mips-dis.c: Update copyright years to include 2002.
2002-05-31 03:17:18 +02:00
|
|
|
|
case 'O': /* MDMX alignment immediate constant. */
|
|
|
|
|
my_getExpression (&imm_expr, s);
|
|
|
|
|
check_absolute_expr (ip, &imm_expr);
|
|
|
|
|
if ((unsigned long) imm_expr.X_add_number > OP_MASK_ALN)
|
|
|
|
|
{
|
|
|
|
|
as_warn ("Improper align amount (%ld), using low bits",
|
|
|
|
|
(long) imm_expr.X_add_number);
|
|
|
|
|
imm_expr.X_add_number &= OP_MASK_ALN;
|
|
|
|
|
}
|
|
|
|
|
ip->insn_opcode |= imm_expr.X_add_number << OP_SH_ALN;
|
|
|
|
|
imm_expr.X_op = O_absent;
|
|
|
|
|
s = expr_end;
|
|
|
|
|
continue;
|
|
|
|
|
|
|
|
|
|
case 'Q': /* MDMX vector, element sel, or const. */
|
|
|
|
|
if (s[0] != '$')
|
|
|
|
|
{
|
|
|
|
|
/* MDMX Immediate. */
|
|
|
|
|
my_getExpression (&imm_expr, s);
|
|
|
|
|
check_absolute_expr (ip, &imm_expr);
|
|
|
|
|
if ((unsigned long) imm_expr.X_add_number > OP_MASK_FT)
|
|
|
|
|
{
|
|
|
|
|
as_warn (_("Invalid MDMX Immediate (%ld)"),
|
|
|
|
|
(long) imm_expr.X_add_number);
|
|
|
|
|
imm_expr.X_add_number &= OP_MASK_FT;
|
|
|
|
|
}
|
|
|
|
|
imm_expr.X_add_number &= OP_MASK_FT;
|
|
|
|
|
if (ip->insn_opcode & (OP_MASK_VSEL << OP_SH_VSEL))
|
|
|
|
|
ip->insn_opcode |= MDMX_FMTSEL_IMM_QH << OP_SH_VSEL;
|
|
|
|
|
else
|
|
|
|
|
ip->insn_opcode |= MDMX_FMTSEL_IMM_OB << OP_SH_VSEL;
|
|
|
|
|
ip->insn_opcode |= imm_expr.X_add_number << OP_SH_FT;
|
|
|
|
|
imm_expr.X_op = O_absent;
|
|
|
|
|
s = expr_end;
|
|
|
|
|
continue;
|
|
|
|
|
}
|
|
|
|
|
/* Not MDMX Immediate. Fall through. */
|
|
|
|
|
case 'X': /* MDMX destination register. */
|
|
|
|
|
case 'Y': /* MDMX source register. */
|
|
|
|
|
case 'Z': /* MDMX target register. */
|
|
|
|
|
is_mdmx = 1;
|
1999-05-03 09:29:11 +02:00
|
|
|
|
case 'D': /* floating point destination register */
|
|
|
|
|
case 'S': /* floating point source register */
|
|
|
|
|
case 'T': /* floating point target register */
|
|
|
|
|
case 'R': /* floating point source register */
|
|
|
|
|
case 'V':
|
|
|
|
|
case 'W':
|
|
|
|
|
s_reset = s;
|
[ gas/ChangeLog ]
2002-05-30 Chris G. Demetriou <cgd@broadcom.com>
Ed Satterthwaite <ehs@broadcom.com>
* config/tc-mips.c (mips_set_options): New "ase_mdmx" member.
(mips_opts): Initialize "ase_mdmx" member.
(file_ase_mdmx): New variable.
(CPU_HAS_MDMX): New macro.
(md_begin): Initialize mips_opts.ase_mdmx and file_ase_mdmx
based on command line options and configuration defaults.
(macro_build): Note in comment that use of MDMX in macros is
not currently allowed.
(validate_mips_insn): Add support for the "O", "Q", "X", "Y", and
"Z" MDMX operand types.
(mips_ip): Accept MDMX instructions if mips_opts.ase_mdmx is set,
and add support for the "O", "Q", "X", "Y", and "Z" MDMX operand
types.
(OPTION_MDMX, OPTION_NO_MDMX, md_longopts, md_parse_option):
Add support for "-mdmx" and "-no-mdmx" options.
(OPTION_ELF_BASE): Move to accomodate new options.
(s_mipsset): Support ".set mdmx" and ".set nomdmx".
(mips_elf_final_processing): Set MDMX ASE ELF header flag if
file_ase_mdmx was set.
* doc/as.texinfo: Document -mdmx and -no-mdmx options.
* doc/c-mips.texi: Likewise, and document ".set mdmx" and ".set
nomdmx" directives.
[ gas/testsuite/ChangeLog ]
2002-05-30 Chris G. Demetriou <cgd@broadcom.com>
* gas/mips/mips64-mdmx.s: New file.
* gas/mips/mips64-mdmx.d: Likewise.
* gas/mips/mips.exp: Run new "mips64-mdmx" test.
[ include/opcode/ChangeLog ]
2002-05-30 Chris G. Demetriou <cgd@broadcom.com>
* mips.h (OP_SH_ALN, OP_MASK_ALN, OP_SH_VSEL, OP_MASK_VSEL)
(MDMX_FMTSEL_IMM_QH, MDMX_FMTSEL_IMM_OB, MDMX_FMTSEL_VEC_QH)
(MDMX_FMTSEL_VEC_OB, INSN_READ_MDMX_ACC, INSN_WRITE_MDMX_ACC)
(INSN_MDMX): New constants, for MDMX support.
(opcode character list): Add "O", "Q", "X", "Y", and "Z" for MDMX.
[ opcodes/ChangeLog ]
2002-05-30 Chris G. Demetriou <cgd@broadcom.com>
Ed Satterthwaite <ehs@broadcom.com>
* mips-dis.c (print_insn_arg): Add support for 'O', 'Q', 'X', 'Y',
and 'Z' formats, for MDMX.
(mips_isa_type): Add MDMX instructions to the ISA
bit mask for bfd_mach_mipsisa64.
* mips-opc.c: Add support for MDMX instructions.
(MX): New definition.
* mips-dis.c: Update copyright years to include 2002.
2002-05-31 03:17:18 +02:00
|
|
|
|
/* Accept $fN for FP and MDMX register numbers, and in
|
|
|
|
|
addition accept $vN for MDMX register numbers. */
|
|
|
|
|
if ((s[0] == '$' && s[1] == 'f' && ISDIGIT (s[2]))
|
|
|
|
|
|| (is_mdmx != 0 && s[0] == '$' && s[1] == 'v'
|
|
|
|
|
&& ISDIGIT (s[2])))
|
1999-05-03 09:29:11 +02:00
|
|
|
|
{
|
|
|
|
|
s += 2;
|
|
|
|
|
regno = 0;
|
|
|
|
|
do
|
|
|
|
|
{
|
|
|
|
|
regno *= 10;
|
|
|
|
|
regno += *s - '0';
|
|
|
|
|
++s;
|
|
|
|
|
}
|
2001-09-19 07:33:36 +02:00
|
|
|
|
while (ISDIGIT (*s));
|
1999-05-03 09:29:11 +02:00
|
|
|
|
|
|
|
|
|
if (regno > 31)
|
|
|
|
|
as_bad (_("Invalid float register number (%d)"), regno);
|
|
|
|
|
|
|
|
|
|
if ((regno & 1) != 0
|
2001-08-02 12:15:24 +02:00
|
|
|
|
&& HAVE_32BIT_FPRS
|
1999-05-03 09:29:11 +02:00
|
|
|
|
&& ! (strcmp (str, "mtc1") == 0
|
|
|
|
|
|| strcmp (str, "mfc1") == 0
|
|
|
|
|
|| strcmp (str, "lwc1") == 0
|
|
|
|
|
|| strcmp (str, "swc1") == 0
|
|
|
|
|
|| strcmp (str, "l.s") == 0
|
|
|
|
|
|| strcmp (str, "s.s") == 0))
|
|
|
|
|
as_warn (_("Float register should be even, was %d"),
|
|
|
|
|
regno);
|
|
|
|
|
|
|
|
|
|
c = *args;
|
|
|
|
|
if (*s == ' ')
|
2002-05-26 20:46:37 +02:00
|
|
|
|
++s;
|
1999-05-03 09:29:11 +02:00
|
|
|
|
if (args[1] != *s)
|
|
|
|
|
{
|
|
|
|
|
if (c == 'V' || c == 'W')
|
|
|
|
|
{
|
|
|
|
|
regno = lastregno;
|
|
|
|
|
s = s_reset;
|
2002-05-26 20:46:37 +02:00
|
|
|
|
++args;
|
1999-05-03 09:29:11 +02:00
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
switch (c)
|
|
|
|
|
{
|
|
|
|
|
case 'D':
|
[ gas/ChangeLog ]
2002-05-30 Chris G. Demetriou <cgd@broadcom.com>
Ed Satterthwaite <ehs@broadcom.com>
* config/tc-mips.c (mips_set_options): New "ase_mdmx" member.
(mips_opts): Initialize "ase_mdmx" member.
(file_ase_mdmx): New variable.
(CPU_HAS_MDMX): New macro.
(md_begin): Initialize mips_opts.ase_mdmx and file_ase_mdmx
based on command line options and configuration defaults.
(macro_build): Note in comment that use of MDMX in macros is
not currently allowed.
(validate_mips_insn): Add support for the "O", "Q", "X", "Y", and
"Z" MDMX operand types.
(mips_ip): Accept MDMX instructions if mips_opts.ase_mdmx is set,
and add support for the "O", "Q", "X", "Y", and "Z" MDMX operand
types.
(OPTION_MDMX, OPTION_NO_MDMX, md_longopts, md_parse_option):
Add support for "-mdmx" and "-no-mdmx" options.
(OPTION_ELF_BASE): Move to accomodate new options.
(s_mipsset): Support ".set mdmx" and ".set nomdmx".
(mips_elf_final_processing): Set MDMX ASE ELF header flag if
file_ase_mdmx was set.
* doc/as.texinfo: Document -mdmx and -no-mdmx options.
* doc/c-mips.texi: Likewise, and document ".set mdmx" and ".set
nomdmx" directives.
[ gas/testsuite/ChangeLog ]
2002-05-30 Chris G. Demetriou <cgd@broadcom.com>
* gas/mips/mips64-mdmx.s: New file.
* gas/mips/mips64-mdmx.d: Likewise.
* gas/mips/mips.exp: Run new "mips64-mdmx" test.
[ include/opcode/ChangeLog ]
2002-05-30 Chris G. Demetriou <cgd@broadcom.com>
* mips.h (OP_SH_ALN, OP_MASK_ALN, OP_SH_VSEL, OP_MASK_VSEL)
(MDMX_FMTSEL_IMM_QH, MDMX_FMTSEL_IMM_OB, MDMX_FMTSEL_VEC_QH)
(MDMX_FMTSEL_VEC_OB, INSN_READ_MDMX_ACC, INSN_WRITE_MDMX_ACC)
(INSN_MDMX): New constants, for MDMX support.
(opcode character list): Add "O", "Q", "X", "Y", and "Z" for MDMX.
[ opcodes/ChangeLog ]
2002-05-30 Chris G. Demetriou <cgd@broadcom.com>
Ed Satterthwaite <ehs@broadcom.com>
* mips-dis.c (print_insn_arg): Add support for 'O', 'Q', 'X', 'Y',
and 'Z' formats, for MDMX.
(mips_isa_type): Add MDMX instructions to the ISA
bit mask for bfd_mach_mipsisa64.
* mips-opc.c: Add support for MDMX instructions.
(MX): New definition.
* mips-dis.c: Update copyright years to include 2002.
2002-05-31 03:17:18 +02:00
|
|
|
|
case 'X':
|
2001-08-07 15:22:46 +02:00
|
|
|
|
ip->insn_opcode |= regno << OP_SH_FD;
|
1999-05-03 09:29:11 +02:00
|
|
|
|
break;
|
|
|
|
|
case 'V':
|
|
|
|
|
case 'S':
|
[ gas/ChangeLog ]
2002-05-30 Chris G. Demetriou <cgd@broadcom.com>
Ed Satterthwaite <ehs@broadcom.com>
* config/tc-mips.c (mips_set_options): New "ase_mdmx" member.
(mips_opts): Initialize "ase_mdmx" member.
(file_ase_mdmx): New variable.
(CPU_HAS_MDMX): New macro.
(md_begin): Initialize mips_opts.ase_mdmx and file_ase_mdmx
based on command line options and configuration defaults.
(macro_build): Note in comment that use of MDMX in macros is
not currently allowed.
(validate_mips_insn): Add support for the "O", "Q", "X", "Y", and
"Z" MDMX operand types.
(mips_ip): Accept MDMX instructions if mips_opts.ase_mdmx is set,
and add support for the "O", "Q", "X", "Y", and "Z" MDMX operand
types.
(OPTION_MDMX, OPTION_NO_MDMX, md_longopts, md_parse_option):
Add support for "-mdmx" and "-no-mdmx" options.
(OPTION_ELF_BASE): Move to accomodate new options.
(s_mipsset): Support ".set mdmx" and ".set nomdmx".
(mips_elf_final_processing): Set MDMX ASE ELF header flag if
file_ase_mdmx was set.
* doc/as.texinfo: Document -mdmx and -no-mdmx options.
* doc/c-mips.texi: Likewise, and document ".set mdmx" and ".set
nomdmx" directives.
[ gas/testsuite/ChangeLog ]
2002-05-30 Chris G. Demetriou <cgd@broadcom.com>
* gas/mips/mips64-mdmx.s: New file.
* gas/mips/mips64-mdmx.d: Likewise.
* gas/mips/mips.exp: Run new "mips64-mdmx" test.
[ include/opcode/ChangeLog ]
2002-05-30 Chris G. Demetriou <cgd@broadcom.com>
* mips.h (OP_SH_ALN, OP_MASK_ALN, OP_SH_VSEL, OP_MASK_VSEL)
(MDMX_FMTSEL_IMM_QH, MDMX_FMTSEL_IMM_OB, MDMX_FMTSEL_VEC_QH)
(MDMX_FMTSEL_VEC_OB, INSN_READ_MDMX_ACC, INSN_WRITE_MDMX_ACC)
(INSN_MDMX): New constants, for MDMX support.
(opcode character list): Add "O", "Q", "X", "Y", and "Z" for MDMX.
[ opcodes/ChangeLog ]
2002-05-30 Chris G. Demetriou <cgd@broadcom.com>
Ed Satterthwaite <ehs@broadcom.com>
* mips-dis.c (print_insn_arg): Add support for 'O', 'Q', 'X', 'Y',
and 'Z' formats, for MDMX.
(mips_isa_type): Add MDMX instructions to the ISA
bit mask for bfd_mach_mipsisa64.
* mips-opc.c: Add support for MDMX instructions.
(MX): New definition.
* mips-dis.c: Update copyright years to include 2002.
2002-05-31 03:17:18 +02:00
|
|
|
|
case 'Y':
|
2001-08-07 15:22:46 +02:00
|
|
|
|
ip->insn_opcode |= regno << OP_SH_FS;
|
1999-05-03 09:29:11 +02:00
|
|
|
|
break;
|
[ gas/ChangeLog ]
2002-05-30 Chris G. Demetriou <cgd@broadcom.com>
Ed Satterthwaite <ehs@broadcom.com>
* config/tc-mips.c (mips_set_options): New "ase_mdmx" member.
(mips_opts): Initialize "ase_mdmx" member.
(file_ase_mdmx): New variable.
(CPU_HAS_MDMX): New macro.
(md_begin): Initialize mips_opts.ase_mdmx and file_ase_mdmx
based on command line options and configuration defaults.
(macro_build): Note in comment that use of MDMX in macros is
not currently allowed.
(validate_mips_insn): Add support for the "O", "Q", "X", "Y", and
"Z" MDMX operand types.
(mips_ip): Accept MDMX instructions if mips_opts.ase_mdmx is set,
and add support for the "O", "Q", "X", "Y", and "Z" MDMX operand
types.
(OPTION_MDMX, OPTION_NO_MDMX, md_longopts, md_parse_option):
Add support for "-mdmx" and "-no-mdmx" options.
(OPTION_ELF_BASE): Move to accomodate new options.
(s_mipsset): Support ".set mdmx" and ".set nomdmx".
(mips_elf_final_processing): Set MDMX ASE ELF header flag if
file_ase_mdmx was set.
* doc/as.texinfo: Document -mdmx and -no-mdmx options.
* doc/c-mips.texi: Likewise, and document ".set mdmx" and ".set
nomdmx" directives.
[ gas/testsuite/ChangeLog ]
2002-05-30 Chris G. Demetriou <cgd@broadcom.com>
* gas/mips/mips64-mdmx.s: New file.
* gas/mips/mips64-mdmx.d: Likewise.
* gas/mips/mips.exp: Run new "mips64-mdmx" test.
[ include/opcode/ChangeLog ]
2002-05-30 Chris G. Demetriou <cgd@broadcom.com>
* mips.h (OP_SH_ALN, OP_MASK_ALN, OP_SH_VSEL, OP_MASK_VSEL)
(MDMX_FMTSEL_IMM_QH, MDMX_FMTSEL_IMM_OB, MDMX_FMTSEL_VEC_QH)
(MDMX_FMTSEL_VEC_OB, INSN_READ_MDMX_ACC, INSN_WRITE_MDMX_ACC)
(INSN_MDMX): New constants, for MDMX support.
(opcode character list): Add "O", "Q", "X", "Y", and "Z" for MDMX.
[ opcodes/ChangeLog ]
2002-05-30 Chris G. Demetriou <cgd@broadcom.com>
Ed Satterthwaite <ehs@broadcom.com>
* mips-dis.c (print_insn_arg): Add support for 'O', 'Q', 'X', 'Y',
and 'Z' formats, for MDMX.
(mips_isa_type): Add MDMX instructions to the ISA
bit mask for bfd_mach_mipsisa64.
* mips-opc.c: Add support for MDMX instructions.
(MX): New definition.
* mips-dis.c: Update copyright years to include 2002.
2002-05-31 03:17:18 +02:00
|
|
|
|
case 'Q':
|
|
|
|
|
/* This is like 'Z', but also needs to fix the MDMX
|
|
|
|
|
vector/scalar select bits. Note that the
|
|
|
|
|
scalar immediate case is handled above. */
|
|
|
|
|
if (*s == '[')
|
|
|
|
|
{
|
|
|
|
|
int is_qh = (ip->insn_opcode & (1 << OP_SH_VSEL));
|
|
|
|
|
int max_el = (is_qh ? 3 : 7);
|
|
|
|
|
s++;
|
|
|
|
|
my_getExpression(&imm_expr, s);
|
|
|
|
|
check_absolute_expr (ip, &imm_expr);
|
|
|
|
|
s = expr_end;
|
|
|
|
|
if (imm_expr.X_add_number > max_el)
|
|
|
|
|
as_bad(_("Bad element selector %ld"),
|
|
|
|
|
(long) imm_expr.X_add_number);
|
|
|
|
|
imm_expr.X_add_number &= max_el;
|
|
|
|
|
ip->insn_opcode |= (imm_expr.X_add_number
|
|
|
|
|
<< (OP_SH_VSEL +
|
|
|
|
|
(is_qh ? 2 : 1)));
|
|
|
|
|
if (*s != ']')
|
|
|
|
|
as_warn(_("Expecting ']' found '%s'"), s);
|
|
|
|
|
else
|
|
|
|
|
s++;
|
|
|
|
|
}
|
|
|
|
|
else
|
|
|
|
|
{
|
|
|
|
|
if (ip->insn_opcode & (OP_MASK_VSEL << OP_SH_VSEL))
|
|
|
|
|
ip->insn_opcode |= (MDMX_FMTSEL_VEC_QH
|
|
|
|
|
<< OP_SH_VSEL);
|
|
|
|
|
else
|
|
|
|
|
ip->insn_opcode |= (MDMX_FMTSEL_VEC_OB <<
|
|
|
|
|
OP_SH_VSEL);
|
|
|
|
|
}
|
|
|
|
|
/* Fall through */
|
1999-05-03 09:29:11 +02:00
|
|
|
|
case 'W':
|
|
|
|
|
case 'T':
|
[ gas/ChangeLog ]
2002-05-30 Chris G. Demetriou <cgd@broadcom.com>
Ed Satterthwaite <ehs@broadcom.com>
* config/tc-mips.c (mips_set_options): New "ase_mdmx" member.
(mips_opts): Initialize "ase_mdmx" member.
(file_ase_mdmx): New variable.
(CPU_HAS_MDMX): New macro.
(md_begin): Initialize mips_opts.ase_mdmx and file_ase_mdmx
based on command line options and configuration defaults.
(macro_build): Note in comment that use of MDMX in macros is
not currently allowed.
(validate_mips_insn): Add support for the "O", "Q", "X", "Y", and
"Z" MDMX operand types.
(mips_ip): Accept MDMX instructions if mips_opts.ase_mdmx is set,
and add support for the "O", "Q", "X", "Y", and "Z" MDMX operand
types.
(OPTION_MDMX, OPTION_NO_MDMX, md_longopts, md_parse_option):
Add support for "-mdmx" and "-no-mdmx" options.
(OPTION_ELF_BASE): Move to accomodate new options.
(s_mipsset): Support ".set mdmx" and ".set nomdmx".
(mips_elf_final_processing): Set MDMX ASE ELF header flag if
file_ase_mdmx was set.
* doc/as.texinfo: Document -mdmx and -no-mdmx options.
* doc/c-mips.texi: Likewise, and document ".set mdmx" and ".set
nomdmx" directives.
[ gas/testsuite/ChangeLog ]
2002-05-30 Chris G. Demetriou <cgd@broadcom.com>
* gas/mips/mips64-mdmx.s: New file.
* gas/mips/mips64-mdmx.d: Likewise.
* gas/mips/mips.exp: Run new "mips64-mdmx" test.
[ include/opcode/ChangeLog ]
2002-05-30 Chris G. Demetriou <cgd@broadcom.com>
* mips.h (OP_SH_ALN, OP_MASK_ALN, OP_SH_VSEL, OP_MASK_VSEL)
(MDMX_FMTSEL_IMM_QH, MDMX_FMTSEL_IMM_OB, MDMX_FMTSEL_VEC_QH)
(MDMX_FMTSEL_VEC_OB, INSN_READ_MDMX_ACC, INSN_WRITE_MDMX_ACC)
(INSN_MDMX): New constants, for MDMX support.
(opcode character list): Add "O", "Q", "X", "Y", and "Z" for MDMX.
[ opcodes/ChangeLog ]
2002-05-30 Chris G. Demetriou <cgd@broadcom.com>
Ed Satterthwaite <ehs@broadcom.com>
* mips-dis.c (print_insn_arg): Add support for 'O', 'Q', 'X', 'Y',
and 'Z' formats, for MDMX.
(mips_isa_type): Add MDMX instructions to the ISA
bit mask for bfd_mach_mipsisa64.
* mips-opc.c: Add support for MDMX instructions.
(MX): New definition.
* mips-dis.c: Update copyright years to include 2002.
2002-05-31 03:17:18 +02:00
|
|
|
|
case 'Z':
|
2001-08-07 15:22:46 +02:00
|
|
|
|
ip->insn_opcode |= regno << OP_SH_FT;
|
1999-05-03 09:29:11 +02:00
|
|
|
|
break;
|
|
|
|
|
case 'R':
|
2001-08-07 15:22:46 +02:00
|
|
|
|
ip->insn_opcode |= regno << OP_SH_FR;
|
1999-05-03 09:29:11 +02:00
|
|
|
|
break;
|
|
|
|
|
}
|
|
|
|
|
lastregno = regno;
|
|
|
|
|
continue;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
switch (*args++)
|
|
|
|
|
{
|
|
|
|
|
case 'V':
|
2001-08-07 15:22:46 +02:00
|
|
|
|
ip->insn_opcode |= lastregno << OP_SH_FS;
|
1999-05-03 09:29:11 +02:00
|
|
|
|
continue;
|
|
|
|
|
case 'W':
|
2001-08-07 15:22:46 +02:00
|
|
|
|
ip->insn_opcode |= lastregno << OP_SH_FT;
|
1999-05-03 09:29:11 +02:00
|
|
|
|
continue;
|
|
|
|
|
}
|
|
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
case 'I':
|
|
|
|
|
my_getExpression (&imm_expr, s);
|
|
|
|
|
if (imm_expr.X_op != O_big
|
|
|
|
|
&& imm_expr.X_op != O_constant)
|
|
|
|
|
insn_error = _("absolute expression required");
|
2003-10-19 23:50:43 +02:00
|
|
|
|
normalize_constant_expr (&imm_expr);
|
1999-05-03 09:29:11 +02:00
|
|
|
|
s = expr_end;
|
|
|
|
|
continue;
|
|
|
|
|
|
|
|
|
|
case 'A':
|
|
|
|
|
my_getExpression (&offset_expr, s);
|
2001-10-04 22:07:00 +02:00
|
|
|
|
*imm_reloc = BFD_RELOC_32;
|
1999-05-03 09:29:11 +02:00
|
|
|
|
s = expr_end;
|
|
|
|
|
continue;
|
|
|
|
|
|
|
|
|
|
case 'F':
|
|
|
|
|
case 'L':
|
|
|
|
|
case 'f':
|
|
|
|
|
case 'l':
|
|
|
|
|
{
|
|
|
|
|
int f64;
|
2001-08-02 12:15:24 +02:00
|
|
|
|
int using_gprs;
|
1999-05-03 09:29:11 +02:00
|
|
|
|
char *save_in;
|
|
|
|
|
char *err;
|
|
|
|
|
unsigned char temp[8];
|
|
|
|
|
int len;
|
|
|
|
|
unsigned int length;
|
|
|
|
|
segT seg;
|
|
|
|
|
subsegT subseg;
|
|
|
|
|
char *p;
|
|
|
|
|
|
|
|
|
|
/* These only appear as the last operand in an
|
|
|
|
|
instruction, and every instruction that accepts
|
|
|
|
|
them in any variant accepts them in all variants.
|
|
|
|
|
This means we don't have to worry about backing out
|
|
|
|
|
any changes if the instruction does not match.
|
|
|
|
|
|
|
|
|
|
The difference between them is the size of the
|
|
|
|
|
floating point constant and where it goes. For 'F'
|
|
|
|
|
and 'L' the constant is 64 bits; for 'f' and 'l' it
|
|
|
|
|
is 32 bits. Where the constant is placed is based
|
|
|
|
|
on how the MIPS assembler does things:
|
|
|
|
|
F -- .rdata
|
|
|
|
|
L -- .lit8
|
|
|
|
|
f -- immediate value
|
|
|
|
|
l -- .lit4
|
|
|
|
|
|
|
|
|
|
The .lit4 and .lit8 sections are only used if
|
|
|
|
|
permitted by the -G argument.
|
|
|
|
|
|
|
|
|
|
When generating embedded PIC code, we use the
|
|
|
|
|
.lit8 section but not the .lit4 section (we can do
|
|
|
|
|
.lit4 inline easily; we need to put .lit8
|
|
|
|
|
somewhere in the data segment, and using .lit8
|
|
|
|
|
permits the linker to eventually combine identical
|
2001-08-02 12:15:24 +02:00
|
|
|
|
.lit8 entries).
|
|
|
|
|
|
|
|
|
|
The code below needs to know whether the target register
|
|
|
|
|
is 32 or 64 bits wide. It relies on the fact 'f' and
|
|
|
|
|
'F' are used with GPR-based instructions and 'l' and
|
|
|
|
|
'L' are used with FPR-based instructions. */
|
1999-05-03 09:29:11 +02:00
|
|
|
|
|
|
|
|
|
f64 = *args == 'F' || *args == 'L';
|
2001-08-02 12:15:24 +02:00
|
|
|
|
using_gprs = *args == 'F' || *args == 'f';
|
1999-05-03 09:29:11 +02:00
|
|
|
|
|
|
|
|
|
save_in = input_line_pointer;
|
|
|
|
|
input_line_pointer = s;
|
|
|
|
|
err = md_atof (f64 ? 'd' : 'f', (char *) temp, &len);
|
|
|
|
|
length = len;
|
|
|
|
|
s = input_line_pointer;
|
|
|
|
|
input_line_pointer = save_in;
|
|
|
|
|
if (err != NULL && *err != '\0')
|
|
|
|
|
{
|
|
|
|
|
as_bad (_("Bad floating point constant: %s"), err);
|
|
|
|
|
memset (temp, '\0', sizeof temp);
|
|
|
|
|
length = f64 ? 8 : 4;
|
|
|
|
|
}
|
|
|
|
|
|
2000-09-14 03:47:38 +02:00
|
|
|
|
assert (length == (unsigned) (f64 ? 8 : 4));
|
1999-05-03 09:29:11 +02:00
|
|
|
|
|
|
|
|
|
if (*args == 'f'
|
|
|
|
|
|| (*args == 'l'
|
|
|
|
|
&& (! USE_GLOBAL_POINTER_OPT
|
|
|
|
|
|| mips_pic == EMBEDDED_PIC
|
|
|
|
|
|| g_switch_value < 4
|
|
|
|
|
|| (temp[0] == 0 && temp[1] == 0)
|
|
|
|
|
|| (temp[2] == 0 && temp[3] == 0))))
|
|
|
|
|
{
|
|
|
|
|
imm_expr.X_op = O_constant;
|
|
|
|
|
if (! target_big_endian)
|
|
|
|
|
imm_expr.X_add_number = bfd_getl32 (temp);
|
|
|
|
|
else
|
|
|
|
|
imm_expr.X_add_number = bfd_getb32 (temp);
|
|
|
|
|
}
|
|
|
|
|
else if (length > 4
|
2000-07-15 00:23:33 +02:00
|
|
|
|
&& ! mips_disable_float_construction
|
2001-08-02 12:15:24 +02:00
|
|
|
|
/* Constants can only be constructed in GPRs and
|
|
|
|
|
copied to FPRs if the GPRs are at least as wide
|
|
|
|
|
as the FPRs. Force the constant into memory if
|
|
|
|
|
we are using 64-bit FPRs but the GPRs are only
|
|
|
|
|
32 bits wide. */
|
|
|
|
|
&& (using_gprs
|
|
|
|
|
|| ! (HAVE_64BIT_FPRS && HAVE_32BIT_GPRS))
|
1999-05-03 09:29:11 +02:00
|
|
|
|
&& ((temp[0] == 0 && temp[1] == 0)
|
|
|
|
|
|| (temp[2] == 0 && temp[3] == 0))
|
|
|
|
|
&& ((temp[4] == 0 && temp[5] == 0)
|
|
|
|
|
|| (temp[6] == 0 && temp[7] == 0)))
|
|
|
|
|
{
|
2001-08-02 12:15:24 +02:00
|
|
|
|
/* The value is simple enough to load with a couple of
|
|
|
|
|
instructions. If using 32-bit registers, set
|
|
|
|
|
imm_expr to the high order 32 bits and offset_expr to
|
|
|
|
|
the low order 32 bits. Otherwise, set imm_expr to
|
|
|
|
|
the entire 64 bit constant. */
|
|
|
|
|
if (using_gprs ? HAVE_32BIT_GPRS : HAVE_32BIT_FPRS)
|
1999-05-03 09:29:11 +02:00
|
|
|
|
{
|
|
|
|
|
imm_expr.X_op = O_constant;
|
|
|
|
|
offset_expr.X_op = O_constant;
|
|
|
|
|
if (! target_big_endian)
|
|
|
|
|
{
|
|
|
|
|
imm_expr.X_add_number = bfd_getl32 (temp + 4);
|
|
|
|
|
offset_expr.X_add_number = bfd_getl32 (temp);
|
|
|
|
|
}
|
|
|
|
|
else
|
|
|
|
|
{
|
|
|
|
|
imm_expr.X_add_number = bfd_getb32 (temp);
|
|
|
|
|
offset_expr.X_add_number = bfd_getb32 (temp + 4);
|
|
|
|
|
}
|
|
|
|
|
if (offset_expr.X_add_number == 0)
|
|
|
|
|
offset_expr.X_op = O_absent;
|
|
|
|
|
}
|
|
|
|
|
else if (sizeof (imm_expr.X_add_number) > 4)
|
|
|
|
|
{
|
|
|
|
|
imm_expr.X_op = O_constant;
|
|
|
|
|
if (! target_big_endian)
|
|
|
|
|
imm_expr.X_add_number = bfd_getl64 (temp);
|
|
|
|
|
else
|
|
|
|
|
imm_expr.X_add_number = bfd_getb64 (temp);
|
|
|
|
|
}
|
|
|
|
|
else
|
|
|
|
|
{
|
|
|
|
|
imm_expr.X_op = O_big;
|
|
|
|
|
imm_expr.X_add_number = 4;
|
|
|
|
|
if (! target_big_endian)
|
|
|
|
|
{
|
|
|
|
|
generic_bignum[0] = bfd_getl16 (temp);
|
|
|
|
|
generic_bignum[1] = bfd_getl16 (temp + 2);
|
|
|
|
|
generic_bignum[2] = bfd_getl16 (temp + 4);
|
|
|
|
|
generic_bignum[3] = bfd_getl16 (temp + 6);
|
|
|
|
|
}
|
|
|
|
|
else
|
|
|
|
|
{
|
|
|
|
|
generic_bignum[0] = bfd_getb16 (temp + 6);
|
|
|
|
|
generic_bignum[1] = bfd_getb16 (temp + 4);
|
|
|
|
|
generic_bignum[2] = bfd_getb16 (temp + 2);
|
|
|
|
|
generic_bignum[3] = bfd_getb16 (temp);
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
else
|
|
|
|
|
{
|
|
|
|
|
const char *newname;
|
|
|
|
|
segT new_seg;
|
|
|
|
|
|
|
|
|
|
/* Switch to the right section. */
|
|
|
|
|
seg = now_seg;
|
|
|
|
|
subseg = now_subseg;
|
|
|
|
|
switch (*args)
|
|
|
|
|
{
|
|
|
|
|
default: /* unused default case avoids warnings. */
|
|
|
|
|
case 'L':
|
|
|
|
|
newname = RDATA_SECTION_NAME;
|
2000-03-11 03:16:25 +01:00
|
|
|
|
if ((USE_GLOBAL_POINTER_OPT && g_switch_value >= 8)
|
|
|
|
|
|| mips_pic == EMBEDDED_PIC)
|
1999-05-03 09:29:11 +02:00
|
|
|
|
newname = ".lit8";
|
|
|
|
|
break;
|
|
|
|
|
case 'F':
|
2000-03-11 03:16:25 +01:00
|
|
|
|
if (mips_pic == EMBEDDED_PIC)
|
|
|
|
|
newname = ".lit8";
|
|
|
|
|
else
|
|
|
|
|
newname = RDATA_SECTION_NAME;
|
1999-05-03 09:29:11 +02:00
|
|
|
|
break;
|
|
|
|
|
case 'l':
|
|
|
|
|
assert (!USE_GLOBAL_POINTER_OPT
|
|
|
|
|
|| g_switch_value >= 4);
|
|
|
|
|
newname = ".lit4";
|
|
|
|
|
break;
|
|
|
|
|
}
|
|
|
|
|
new_seg = subseg_new (newname, (subsegT) 0);
|
|
|
|
|
if (OUTPUT_FLAVOR == bfd_target_elf_flavour)
|
|
|
|
|
bfd_set_section_flags (stdoutput, new_seg,
|
|
|
|
|
(SEC_ALLOC
|
|
|
|
|
| SEC_LOAD
|
|
|
|
|
| SEC_READONLY
|
|
|
|
|
| SEC_DATA));
|
|
|
|
|
frag_align (*args == 'l' ? 2 : 3, 0, 0);
|
|
|
|
|
if (OUTPUT_FLAVOR == bfd_target_elf_flavour
|
|
|
|
|
&& strcmp (TARGET_OS, "elf") != 0)
|
|
|
|
|
record_alignment (new_seg, 4);
|
|
|
|
|
else
|
|
|
|
|
record_alignment (new_seg, *args == 'l' ? 2 : 3);
|
|
|
|
|
if (seg == now_seg)
|
|
|
|
|
as_bad (_("Can't use floating point insn in this section"));
|
|
|
|
|
|
|
|
|
|
/* Set the argument to the current address in the
|
|
|
|
|
section. */
|
|
|
|
|
offset_expr.X_op = O_symbol;
|
|
|
|
|
offset_expr.X_add_symbol =
|
|
|
|
|
symbol_new ("L0\001", now_seg,
|
|
|
|
|
(valueT) frag_now_fix (), frag_now);
|
|
|
|
|
offset_expr.X_add_number = 0;
|
|
|
|
|
|
|
|
|
|
/* Put the floating point number into the section. */
|
|
|
|
|
p = frag_more ((int) length);
|
|
|
|
|
memcpy (p, temp, length);
|
|
|
|
|
|
|
|
|
|
/* Switch back to the original section. */
|
|
|
|
|
subseg_set (seg, subseg);
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
continue;
|
|
|
|
|
|
|
|
|
|
case 'i': /* 16 bit unsigned immediate */
|
|
|
|
|
case 'j': /* 16 bit signed immediate */
|
2001-10-04 22:07:00 +02:00
|
|
|
|
*imm_reloc = BFD_RELOC_LO16;
|
2003-02-02 20:37:20 +01:00
|
|
|
|
if (my_getSmallExpression (&imm_expr, imm_reloc, s) == 0)
|
1999-05-03 09:29:11 +02:00
|
|
|
|
{
|
|
|
|
|
int more;
|
2003-02-02 20:37:20 +01:00
|
|
|
|
offsetT minval, maxval;
|
|
|
|
|
|
|
|
|
|
more = (insn + 1 < &mips_opcodes[NUMOPCODES]
|
|
|
|
|
&& strcmp (insn->name, insn[1].name) == 0);
|
|
|
|
|
|
|
|
|
|
/* If the expression was written as an unsigned number,
|
|
|
|
|
only treat it as signed if there are no more
|
|
|
|
|
alternatives. */
|
|
|
|
|
if (more
|
|
|
|
|
&& *args == 'j'
|
|
|
|
|
&& sizeof (imm_expr.X_add_number) <= 4
|
|
|
|
|
&& imm_expr.X_op == O_constant
|
|
|
|
|
&& imm_expr.X_add_number < 0
|
|
|
|
|
&& imm_expr.X_unsigned
|
|
|
|
|
&& HAVE_64BIT_GPRS)
|
|
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
/* For compatibility with older assemblers, we accept
|
|
|
|
|
0x8000-0xffff as signed 16-bit numbers when only
|
|
|
|
|
signed numbers are allowed. */
|
|
|
|
|
if (*args == 'i')
|
|
|
|
|
minval = 0, maxval = 0xffff;
|
|
|
|
|
else if (more)
|
|
|
|
|
minval = -0x8000, maxval = 0x7fff;
|
1999-05-03 09:29:11 +02:00
|
|
|
|
else
|
2003-02-02 20:37:20 +01:00
|
|
|
|
minval = -0x8000, maxval = 0xffff;
|
|
|
|
|
|
|
|
|
|
if (imm_expr.X_op != O_constant
|
|
|
|
|
|| imm_expr.X_add_number < minval
|
|
|
|
|
|| imm_expr.X_add_number > maxval)
|
1999-05-03 09:29:11 +02:00
|
|
|
|
{
|
|
|
|
|
if (more)
|
|
|
|
|
break;
|
2000-06-28 21:06:25 +02:00
|
|
|
|
if (imm_expr.X_op == O_constant
|
|
|
|
|
|| imm_expr.X_op == O_big)
|
2003-02-02 20:37:20 +01:00
|
|
|
|
as_bad (_("expression out of range"));
|
1999-05-03 09:29:11 +02:00
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
s = expr_end;
|
|
|
|
|
continue;
|
|
|
|
|
|
|
|
|
|
case 'o': /* 16 bit offset */
|
2003-02-02 20:37:20 +01:00
|
|
|
|
/* Check whether there is only a single bracketed expression
|
|
|
|
|
left. If so, it must be the base register and the
|
|
|
|
|
constant must be zero. */
|
|
|
|
|
if (*s == '(' && strchr (s + 1, '(') == 0)
|
|
|
|
|
{
|
|
|
|
|
offset_expr.X_op = O_constant;
|
|
|
|
|
offset_expr.X_add_number = 0;
|
|
|
|
|
continue;
|
|
|
|
|
}
|
1999-05-03 09:29:11 +02:00
|
|
|
|
|
|
|
|
|
/* If this value won't fit into a 16 bit offset, then go
|
|
|
|
|
find a macro that will generate the 32 bit offset
|
2001-11-01 02:33:47 +01:00
|
|
|
|
code pattern. */
|
2003-02-02 20:37:20 +01:00
|
|
|
|
if (my_getSmallExpression (&offset_expr, offset_reloc, s) == 0
|
1999-05-03 09:29:11 +02:00
|
|
|
|
&& (offset_expr.X_op != O_constant
|
|
|
|
|
|| offset_expr.X_add_number >= 0x8000
|
2001-11-01 02:33:47 +01:00
|
|
|
|
|| offset_expr.X_add_number < -0x8000))
|
1999-05-03 09:29:11 +02:00
|
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
s = expr_end;
|
|
|
|
|
continue;
|
|
|
|
|
|
|
|
|
|
case 'p': /* pc relative offset */
|
2003-03-13 00:06:08 +01:00
|
|
|
|
*offset_reloc = BFD_RELOC_16_PCREL_S2;
|
1999-05-03 09:29:11 +02:00
|
|
|
|
my_getExpression (&offset_expr, s);
|
|
|
|
|
s = expr_end;
|
|
|
|
|
continue;
|
|
|
|
|
|
|
|
|
|
case 'u': /* upper 16 bits */
|
2003-02-02 20:37:20 +01:00
|
|
|
|
if (my_getSmallExpression (&imm_expr, imm_reloc, s) == 0
|
|
|
|
|
&& imm_expr.X_op == O_constant
|
|
|
|
|
&& (imm_expr.X_add_number < 0
|
|
|
|
|
|| imm_expr.X_add_number >= 0x10000))
|
1999-05-03 09:29:11 +02:00
|
|
|
|
as_bad (_("lui expression not in range 0..65535"));
|
|
|
|
|
s = expr_end;
|
|
|
|
|
continue;
|
|
|
|
|
|
|
|
|
|
case 'a': /* 26 bit address */
|
|
|
|
|
my_getExpression (&offset_expr, s);
|
|
|
|
|
s = expr_end;
|
2001-10-04 22:07:00 +02:00
|
|
|
|
*offset_reloc = BFD_RELOC_MIPS_JMP;
|
1999-05-03 09:29:11 +02:00
|
|
|
|
continue;
|
|
|
|
|
|
|
|
|
|
case 'N': /* 3 bit branch condition code */
|
|
|
|
|
case 'M': /* 3 bit compare condition code */
|
|
|
|
|
if (strncmp (s, "$fcc", 4) != 0)
|
|
|
|
|
break;
|
|
|
|
|
s += 4;
|
|
|
|
|
regno = 0;
|
|
|
|
|
do
|
|
|
|
|
{
|
|
|
|
|
regno *= 10;
|
|
|
|
|
regno += *s - '0';
|
|
|
|
|
++s;
|
|
|
|
|
}
|
2001-09-19 07:33:36 +02:00
|
|
|
|
while (ISDIGIT (*s));
|
1999-05-03 09:29:11 +02:00
|
|
|
|
if (regno > 7)
|
2003-09-30 23:02:08 +02:00
|
|
|
|
as_bad (_("Invalid condition code register $fcc%d"), regno);
|
|
|
|
|
if ((strcmp(str + strlen(str) - 3, ".ps") == 0
|
|
|
|
|
|| strcmp(str + strlen(str) - 5, "any2f") == 0
|
|
|
|
|
|| strcmp(str + strlen(str) - 5, "any2t") == 0)
|
|
|
|
|
&& (regno & 1) != 0)
|
|
|
|
|
as_warn(_("Condition code register should be even for %s, was %d"),
|
|
|
|
|
str, regno);
|
|
|
|
|
if ((strcmp(str + strlen(str) - 5, "any4f") == 0
|
|
|
|
|
|| strcmp(str + strlen(str) - 5, "any4t") == 0)
|
|
|
|
|
&& (regno & 3) != 0)
|
|
|
|
|
as_warn(_("Condition code register should be 0 or 4 for %s, was %d"),
|
|
|
|
|
str, regno);
|
1999-05-03 09:29:11 +02:00
|
|
|
|
if (*args == 'N')
|
|
|
|
|
ip->insn_opcode |= regno << OP_SH_BCC;
|
|
|
|
|
else
|
|
|
|
|
ip->insn_opcode |= regno << OP_SH_CCC;
|
2000-12-05 19:51:08 +01:00
|
|
|
|
continue;
|
1999-05-03 09:29:11 +02:00
|
|
|
|
|
2000-09-14 03:47:38 +02:00
|
|
|
|
case 'H':
|
|
|
|
|
if (s[0] == '0' && (s[1] == 'x' || s[1] == 'X'))
|
|
|
|
|
s += 2;
|
2001-09-19 07:33:36 +02:00
|
|
|
|
if (ISDIGIT (*s))
|
2000-09-14 03:47:38 +02:00
|
|
|
|
{
|
|
|
|
|
c = 0;
|
|
|
|
|
do
|
|
|
|
|
{
|
|
|
|
|
c *= 10;
|
|
|
|
|
c += *s - '0';
|
|
|
|
|
++s;
|
|
|
|
|
}
|
2001-09-19 07:33:36 +02:00
|
|
|
|
while (ISDIGIT (*s));
|
2000-09-14 03:47:38 +02:00
|
|
|
|
}
|
|
|
|
|
else
|
|
|
|
|
c = 8; /* Invalid sel value. */
|
|
|
|
|
|
|
|
|
|
if (c > 7)
|
|
|
|
|
as_bad (_("invalid coprocessor sub-selection value (0-7)"));
|
|
|
|
|
ip->insn_opcode |= c;
|
|
|
|
|
continue;
|
|
|
|
|
|
[gas/]
* doc/c-mips.texi: Add entries for -march=vr4120,vr4130,vr4181,
vr5400 and vr5500. Add entry for -mfix-vr4122-bugs.
* config/tc-mips.c (CPU_HAS_DROR, CPU_HAS_ROR): New macros.
(hilo_interlocks): True for CPU_VR5500.
(gpr_interlocks, cop_interlocks): True for CPU_VR5400 and CPU_VR5500.
(mips_fix_vr4122_bugs): New.
(append_insn): Work around 4122 errors if mips_fix_vr4122_bugs.
(mips_emit_delays): Likewise.
(macro2) [M_DROLI]: Use dror or dror32 if CPU_HAS_DROR.
[M_ROLI]: Likewise ror if CPU_HAS_ROR.
(validate_mips_insn, mips_ip): Handle '[', ']', 'e' and '%'.
(OPTION_FIX_VR4122, OPTION_NO_FIX_VR4122): New options.
(md_longopts): Add -mfix-vr4122-bugs and -no-mfix-vr4122-bugs.
(OPTION_ELF_BASE): Bump.
(md_parse_option): Handle the new options.
(mips_cpu_info_table): Add entries for vr4120, vr4130, vr4181,
vr5400 and vr5500.
[gas/testsuite/]
* gas/mips/mips4100.[sd]: Move dmadd16 and madd16 checks to...
* gas/mips/vr4111.[sd]: ...this new test.
* gas/mips/vr4120.[sd],
* gas/mips/vr4122.[sd],
* gas/mips/vr5400.[sd],
* gas/mips/vr5500.[sd]: New tests.
* mips.exp: Run them.
2002-09-30 14:04:54 +02:00
|
|
|
|
case 'e':
|
|
|
|
|
/* Must be at least one digit. */
|
|
|
|
|
my_getExpression (&imm_expr, s);
|
|
|
|
|
check_absolute_expr (ip, &imm_expr);
|
|
|
|
|
|
|
|
|
|
if ((unsigned long) imm_expr.X_add_number
|
|
|
|
|
> (unsigned long) OP_MASK_VECBYTE)
|
|
|
|
|
{
|
|
|
|
|
as_bad (_("bad byte vector index (%ld)"),
|
|
|
|
|
(long) imm_expr.X_add_number);
|
|
|
|
|
imm_expr.X_add_number = 0;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
ip->insn_opcode |= imm_expr.X_add_number << OP_SH_VECBYTE;
|
|
|
|
|
imm_expr.X_op = O_absent;
|
|
|
|
|
s = expr_end;
|
|
|
|
|
continue;
|
|
|
|
|
|
|
|
|
|
case '%':
|
|
|
|
|
my_getExpression (&imm_expr, s);
|
|
|
|
|
check_absolute_expr (ip, &imm_expr);
|
|
|
|
|
|
|
|
|
|
if ((unsigned long) imm_expr.X_add_number
|
|
|
|
|
> (unsigned long) OP_MASK_VECALIGN)
|
|
|
|
|
{
|
|
|
|
|
as_bad (_("bad byte vector index (%ld)"),
|
|
|
|
|
(long) imm_expr.X_add_number);
|
|
|
|
|
imm_expr.X_add_number = 0;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
ip->insn_opcode |= imm_expr.X_add_number << OP_SH_VECALIGN;
|
|
|
|
|
imm_expr.X_op = O_absent;
|
|
|
|
|
s = expr_end;
|
|
|
|
|
continue;
|
|
|
|
|
|
1999-05-03 09:29:11 +02:00
|
|
|
|
default:
|
|
|
|
|
as_bad (_("bad char = '%c'\n"), *args);
|
|
|
|
|
internalError ();
|
|
|
|
|
}
|
|
|
|
|
break;
|
|
|
|
|
}
|
|
|
|
|
/* Args don't match. */
|
|
|
|
|
if (insn + 1 < &mips_opcodes[NUMOPCODES] &&
|
|
|
|
|
!strcmp (insn->name, insn[1].name))
|
|
|
|
|
{
|
|
|
|
|
++insn;
|
|
|
|
|
s = argsStart;
|
2001-06-09 07:01:29 +02:00
|
|
|
|
insn_error = _("illegal operands");
|
1999-05-03 09:29:11 +02:00
|
|
|
|
continue;
|
|
|
|
|
}
|
2001-06-09 07:01:29 +02:00
|
|
|
|
if (save_c)
|
|
|
|
|
*(--s) = save_c;
|
1999-05-03 09:29:11 +02:00
|
|
|
|
insn_error = _("illegal operands");
|
|
|
|
|
return;
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/* This routine assembles an instruction into its binary format when
|
|
|
|
|
assembling for the mips16. As a side effect, it sets one of the
|
|
|
|
|
global variables imm_reloc or offset_reloc to the type of
|
|
|
|
|
relocation to do if one of the operands is an address expression.
|
|
|
|
|
It also sets mips16_small and mips16_ext if the user explicitly
|
|
|
|
|
requested a small or extended instruction. */
|
|
|
|
|
|
|
|
|
|
static void
|
2003-06-30 14:44:25 +02:00
|
|
|
|
mips16_ip (char *str, struct mips_cl_insn *ip)
|
1999-05-03 09:29:11 +02:00
|
|
|
|
{
|
|
|
|
|
char *s;
|
|
|
|
|
const char *args;
|
|
|
|
|
struct mips_opcode *insn;
|
|
|
|
|
char *argsstart;
|
|
|
|
|
unsigned int regno;
|
|
|
|
|
unsigned int lastregno = 0;
|
|
|
|
|
char *s_reset;
|
|
|
|
|
|
|
|
|
|
insn_error = NULL;
|
|
|
|
|
|
2002-11-30 09:39:46 +01:00
|
|
|
|
mips16_small = FALSE;
|
|
|
|
|
mips16_ext = FALSE;
|
1999-05-03 09:29:11 +02:00
|
|
|
|
|
2001-09-19 07:33:36 +02:00
|
|
|
|
for (s = str; ISLOWER (*s); ++s)
|
1999-05-03 09:29:11 +02:00
|
|
|
|
;
|
|
|
|
|
switch (*s)
|
|
|
|
|
{
|
|
|
|
|
case '\0':
|
|
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
case ' ':
|
|
|
|
|
*s++ = '\0';
|
|
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
case '.':
|
|
|
|
|
if (s[1] == 't' && s[2] == ' ')
|
|
|
|
|
{
|
|
|
|
|
*s = '\0';
|
2002-11-30 09:39:46 +01:00
|
|
|
|
mips16_small = TRUE;
|
1999-05-03 09:29:11 +02:00
|
|
|
|
s += 3;
|
|
|
|
|
break;
|
|
|
|
|
}
|
|
|
|
|
else if (s[1] == 'e' && s[2] == ' ')
|
|
|
|
|
{
|
|
|
|
|
*s = '\0';
|
2002-11-30 09:39:46 +01:00
|
|
|
|
mips16_ext = TRUE;
|
1999-05-03 09:29:11 +02:00
|
|
|
|
s += 3;
|
|
|
|
|
break;
|
|
|
|
|
}
|
|
|
|
|
/* Fall through. */
|
|
|
|
|
default:
|
|
|
|
|
insn_error = _("unknown opcode");
|
|
|
|
|
return;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
if (mips_opts.noautoextend && ! mips16_ext)
|
2002-11-30 09:39:46 +01:00
|
|
|
|
mips16_small = TRUE;
|
1999-05-03 09:29:11 +02:00
|
|
|
|
|
|
|
|
|
if ((insn = (struct mips_opcode *) hash_find (mips16_op_hash, str)) == NULL)
|
|
|
|
|
{
|
|
|
|
|
insn_error = _("unrecognized opcode");
|
|
|
|
|
return;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
argsstart = s;
|
|
|
|
|
for (;;)
|
|
|
|
|
{
|
|
|
|
|
assert (strcmp (insn->name, str) == 0);
|
|
|
|
|
|
|
|
|
|
ip->insn_mo = insn;
|
|
|
|
|
ip->insn_opcode = insn->match;
|
2002-11-30 09:39:46 +01:00
|
|
|
|
ip->use_extend = FALSE;
|
1999-05-03 09:29:11 +02:00
|
|
|
|
imm_expr.X_op = O_absent;
|
2001-10-04 22:07:00 +02:00
|
|
|
|
imm_reloc[0] = BFD_RELOC_UNUSED;
|
|
|
|
|
imm_reloc[1] = BFD_RELOC_UNUSED;
|
|
|
|
|
imm_reloc[2] = BFD_RELOC_UNUSED;
|
[ bfd/ChangeLog ]
2003-09-30 Chris Demetriou <cgd@broadcom.com>
* archures.c (bfd_mach_mipsisa64r2): New define.
* bfd-in2.h: Regenerate.
* aoutx.h (NAME(aout,machine_type)): Handle bfd_mach_mipsisa64r2.
* cpu-mips.c (I_mipsisa64r2): New enum value.
(arch_info_struct): Add entry for I_mipsisa64r2.
* elfxx-mips.c (_bfd_elf_mips_mach)
(_bfd_mips_elf_print_private_bfd_data): Handle E_MIPS_ARCH_64R2.
(mips_set_isa_flags): Add bfd_mach_mipsisa64r2 case.
(mips_mach_extensions): Add entry for bfd_mach_mipsisa64r2.
[ binutils/ChangeLog ]
2003-09-30 Chris Demetriou <cgd@broadcom.com>
* readelf.c (get_machine_flags): Handle E_MIPS_ARCH_64R2.
[ gas/Changelog ]
2003-09-30 Chris Demetriou <cgd@broadcom.com>
* configure.in (mipsisa64r2, mipsisa64r2el, mipsisa64r2*): New CPUs.
* configure: Regenerate.
* config/tc-mips.c (imm2_expr): New variable.
(md_assemble, mips16_ip): Initialize imm2_expr.
(ISA_HAS_64BIT_REGS, ISA_HAS_DROR, ISA_HAS_ROR): Add ISA_MIPS64R2.
(macro_build): Handle +A, +B, +C, +E, +F, +G, and +H format operands.
(macro): Handle M_DEXT and M_DINS.
(validate_mips_insn): Handle +E, +F, +G, +H, and +I format operands.
(mips_ip): Likewise.
(OPTION_MIPS64R2): New define.
(md_longopts): New entry for -mips64r2 (OPTION_MIPS64R2).
OPTION_ASE_BASE): Increase to compensate for OPTION_MIPS64R2.
(md_parse_option): Handle OPTION_MIPS64R2.
(s_mipsset): Handle setting "mips64r2" ISA.
(mips_cpu_info_table): Add mips64r2.
(md_show_usage): Document -mips64r2 option.
* doc/as.texinfo: Docuemnt -mips64r2 option.
* doc/c-mips.texi: Likewise.
[ gas/testsuite/ChangeLog ]
2003-09-30 Chris Demetriou <cgd@broadcom.com>
* gas/mips/cp0-names-mips64r2.d: New file.
* gas/mips/cp0sel-names-mips64r2.d: New file.
* gas/mips/elf_arch_mips64r2.d: New file.
* gas/mips/hwr-names-mips64r2.d: New file.
* gas/mips/mips32r2-ill-fp64.l: New file.
* gas/mips/mips32r2-ill-fp64.s: New file.
* gas/mips/mips64r2-ill.l: New file.
* gas/mips/mips64r2-ill.s: New file.
* gas/mips/mips64r2.d: New file.
* gas/mips/mips64r2.s: New file.
* gas/mips/mips.exp: Define "mips64r2" arch, and run new tests.
[ include/elf/ChangeLog ]
2003-09-30 Chris Demetriou <cgd@broadcom.com>
* mips.h (E_MIPS_ARCH_64R2): New define.
[ include/opcode/ChangeLog ]
2003-09-30 Chris Demetriou <cgd@broadcom.com>
* mips.h: Document +E, +F, +G, +H, and +I operand types.
Update documentation of I, +B and +C operand types.
(INSN_ISA64R2, ISA_MIPS64R2, CPU_MIPS64R2): New defines.
(M_DEXT, M_DINS): New enum values.
[ ld/ChangeLog ]
2003-09-30 Chris Demetriou <cgd@broadcom.com>
* ldmain.c (get_emulation): Ignore "-mips64r2".
[ ld/testsuite/ChangeLog ]
2003-09-30 Chris Demetriou <cgd@broadcom.com>
* ld-mips-elf/mips-elf-flags.exp: Add tests for combinations
with MIPS64r2.
[ opcodes/ChangeLog ]
2003-09-30 Chris Demetriou <cgd@broadcom.com>
* mips-dis.c (mips_arch_choices): Add entry for "mips64r2"
(print_insn_args): Add handing for +E, +F, +G, and +H.
* mips-opc.c (I65): New define for MIPS64r2.
(mips_builtin_opcodes): Add "dext", "dextm", "dextu", "dins",
"dinsm", "dinsu", "drotl", "drotr", "drotr32", "drotrv", "dsbh",
and "dshd" for MIPS64r2. Adjust "dror", "dror32", and "drorv" to
be supported on MIPS64r2.
2003-09-30 18:17:15 +02:00
|
|
|
|
imm2_expr.X_op = O_absent;
|
1999-05-03 09:29:11 +02:00
|
|
|
|
offset_expr.X_op = O_absent;
|
2001-10-04 22:07:00 +02:00
|
|
|
|
offset_reloc[0] = BFD_RELOC_UNUSED;
|
|
|
|
|
offset_reloc[1] = BFD_RELOC_UNUSED;
|
|
|
|
|
offset_reloc[2] = BFD_RELOC_UNUSED;
|
1999-05-03 09:29:11 +02:00
|
|
|
|
for (args = insn->args; 1; ++args)
|
|
|
|
|
{
|
|
|
|
|
int c;
|
|
|
|
|
|
|
|
|
|
if (*s == ' ')
|
|
|
|
|
++s;
|
|
|
|
|
|
|
|
|
|
/* In this switch statement we call break if we did not find
|
|
|
|
|
a match, continue if we did find a match, or return if we
|
|
|
|
|
are done. */
|
|
|
|
|
|
|
|
|
|
c = *args;
|
|
|
|
|
switch (c)
|
|
|
|
|
{
|
|
|
|
|
case '\0':
|
|
|
|
|
if (*s == '\0')
|
|
|
|
|
{
|
|
|
|
|
/* Stuff the immediate value in now, if we can. */
|
|
|
|
|
if (imm_expr.X_op == O_constant
|
2001-10-04 22:07:00 +02:00
|
|
|
|
&& *imm_reloc > BFD_RELOC_UNUSED
|
1999-05-03 09:29:11 +02:00
|
|
|
|
&& insn->pinfo != INSN_MACRO)
|
|
|
|
|
{
|
2001-11-12 23:19:30 +01:00
|
|
|
|
mips16_immed (NULL, 0, *imm_reloc - BFD_RELOC_UNUSED,
|
2002-11-30 09:39:46 +01:00
|
|
|
|
imm_expr.X_add_number, TRUE, mips16_small,
|
1999-05-03 09:29:11 +02:00
|
|
|
|
mips16_ext, &ip->insn_opcode,
|
|
|
|
|
&ip->use_extend, &ip->extend);
|
|
|
|
|
imm_expr.X_op = O_absent;
|
2001-10-04 22:07:00 +02:00
|
|
|
|
*imm_reloc = BFD_RELOC_UNUSED;
|
1999-05-03 09:29:11 +02:00
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
return;
|
|
|
|
|
}
|
|
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
case ',':
|
|
|
|
|
if (*s++ == c)
|
|
|
|
|
continue;
|
|
|
|
|
s--;
|
|
|
|
|
switch (*++args)
|
|
|
|
|
{
|
|
|
|
|
case 'v':
|
|
|
|
|
ip->insn_opcode |= lastregno << MIPS16OP_SH_RX;
|
|
|
|
|
continue;
|
|
|
|
|
case 'w':
|
|
|
|
|
ip->insn_opcode |= lastregno << MIPS16OP_SH_RY;
|
|
|
|
|
continue;
|
|
|
|
|
}
|
|
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
case '(':
|
|
|
|
|
case ')':
|
|
|
|
|
if (*s++ == c)
|
|
|
|
|
continue;
|
|
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
case 'v':
|
|
|
|
|
case 'w':
|
|
|
|
|
if (s[0] != '$')
|
|
|
|
|
{
|
|
|
|
|
if (c == 'v')
|
|
|
|
|
ip->insn_opcode |= lastregno << MIPS16OP_SH_RX;
|
|
|
|
|
else
|
|
|
|
|
ip->insn_opcode |= lastregno << MIPS16OP_SH_RY;
|
|
|
|
|
++args;
|
|
|
|
|
continue;
|
|
|
|
|
}
|
|
|
|
|
/* Fall through. */
|
|
|
|
|
case 'x':
|
|
|
|
|
case 'y':
|
|
|
|
|
case 'z':
|
|
|
|
|
case 'Z':
|
|
|
|
|
case '0':
|
|
|
|
|
case 'S':
|
|
|
|
|
case 'R':
|
|
|
|
|
case 'X':
|
|
|
|
|
case 'Y':
|
|
|
|
|
if (s[0] != '$')
|
|
|
|
|
break;
|
|
|
|
|
s_reset = s;
|
2001-09-19 07:33:36 +02:00
|
|
|
|
if (ISDIGIT (s[1]))
|
1999-05-03 09:29:11 +02:00
|
|
|
|
{
|
|
|
|
|
++s;
|
|
|
|
|
regno = 0;
|
|
|
|
|
do
|
|
|
|
|
{
|
|
|
|
|
regno *= 10;
|
|
|
|
|
regno += *s - '0';
|
|
|
|
|
++s;
|
|
|
|
|
}
|
2001-09-19 07:33:36 +02:00
|
|
|
|
while (ISDIGIT (*s));
|
1999-05-03 09:29:11 +02:00
|
|
|
|
if (regno > 31)
|
|
|
|
|
{
|
|
|
|
|
as_bad (_("invalid register number (%d)"), regno);
|
|
|
|
|
regno = 2;
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
else
|
|
|
|
|
{
|
2002-05-31 03:58:18 +02:00
|
|
|
|
if (s[1] == 'r' && s[2] == 'a')
|
|
|
|
|
{
|
|
|
|
|
s += 3;
|
|
|
|
|
regno = RA;
|
|
|
|
|
}
|
|
|
|
|
else if (s[1] == 'f' && s[2] == 'p')
|
1999-05-03 09:29:11 +02:00
|
|
|
|
{
|
|
|
|
|
s += 3;
|
|
|
|
|
regno = FP;
|
|
|
|
|
}
|
|
|
|
|
else if (s[1] == 's' && s[2] == 'p')
|
|
|
|
|
{
|
|
|
|
|
s += 3;
|
|
|
|
|
regno = SP;
|
|
|
|
|
}
|
|
|
|
|
else if (s[1] == 'g' && s[2] == 'p')
|
|
|
|
|
{
|
|
|
|
|
s += 3;
|
|
|
|
|
regno = GP;
|
|
|
|
|
}
|
|
|
|
|
else if (s[1] == 'a' && s[2] == 't')
|
|
|
|
|
{
|
|
|
|
|
s += 3;
|
|
|
|
|
regno = AT;
|
|
|
|
|
}
|
|
|
|
|
else if (s[1] == 'k' && s[2] == 't' && s[3] == '0')
|
|
|
|
|
{
|
|
|
|
|
s += 4;
|
|
|
|
|
regno = KT0;
|
|
|
|
|
}
|
|
|
|
|
else if (s[1] == 'k' && s[2] == 't' && s[3] == '1')
|
|
|
|
|
{
|
|
|
|
|
s += 4;
|
|
|
|
|
regno = KT1;
|
|
|
|
|
}
|
2002-06-08 00:54:47 +02:00
|
|
|
|
else if (s[1] == 'z' && s[2] == 'e' && s[3] == 'r' && s[4] == 'o')
|
|
|
|
|
{
|
|
|
|
|
s += 5;
|
|
|
|
|
regno = ZERO;
|
|
|
|
|
}
|
1999-05-03 09:29:11 +02:00
|
|
|
|
else
|
|
|
|
|
break;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
if (*s == ' ')
|
|
|
|
|
++s;
|
|
|
|
|
if (args[1] != *s)
|
|
|
|
|
{
|
|
|
|
|
if (c == 'v' || c == 'w')
|
|
|
|
|
{
|
|
|
|
|
regno = mips16_to_32_reg_map[lastregno];
|
|
|
|
|
s = s_reset;
|
2002-05-26 20:46:37 +02:00
|
|
|
|
++args;
|
1999-05-03 09:29:11 +02:00
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
switch (c)
|
|
|
|
|
{
|
|
|
|
|
case 'x':
|
|
|
|
|
case 'y':
|
|
|
|
|
case 'z':
|
|
|
|
|
case 'v':
|
|
|
|
|
case 'w':
|
|
|
|
|
case 'Z':
|
|
|
|
|
regno = mips32_to_16_reg_map[regno];
|
|
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
case '0':
|
|
|
|
|
if (regno != 0)
|
|
|
|
|
regno = ILLEGAL_REG;
|
|
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
case 'S':
|
|
|
|
|
if (regno != SP)
|
|
|
|
|
regno = ILLEGAL_REG;
|
|
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
case 'R':
|
|
|
|
|
if (regno != RA)
|
|
|
|
|
regno = ILLEGAL_REG;
|
|
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
case 'X':
|
|
|
|
|
case 'Y':
|
|
|
|
|
if (regno == AT && ! mips_opts.noat)
|
|
|
|
|
as_warn (_("used $at without \".set noat\""));
|
|
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
default:
|
|
|
|
|
internalError ();
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
if (regno == ILLEGAL_REG)
|
|
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
switch (c)
|
|
|
|
|
{
|
|
|
|
|
case 'x':
|
|
|
|
|
case 'v':
|
|
|
|
|
ip->insn_opcode |= regno << MIPS16OP_SH_RX;
|
|
|
|
|
break;
|
|
|
|
|
case 'y':
|
|
|
|
|
case 'w':
|
|
|
|
|
ip->insn_opcode |= regno << MIPS16OP_SH_RY;
|
|
|
|
|
break;
|
|
|
|
|
case 'z':
|
|
|
|
|
ip->insn_opcode |= regno << MIPS16OP_SH_RZ;
|
|
|
|
|
break;
|
|
|
|
|
case 'Z':
|
|
|
|
|
ip->insn_opcode |= regno << MIPS16OP_SH_MOVE32Z;
|
|
|
|
|
case '0':
|
|
|
|
|
case 'S':
|
|
|
|
|
case 'R':
|
|
|
|
|
break;
|
|
|
|
|
case 'X':
|
|
|
|
|
ip->insn_opcode |= regno << MIPS16OP_SH_REGR32;
|
|
|
|
|
break;
|
|
|
|
|
case 'Y':
|
|
|
|
|
regno = ((regno & 7) << 2) | ((regno & 0x18) >> 3);
|
|
|
|
|
ip->insn_opcode |= regno << MIPS16OP_SH_REG32R;
|
|
|
|
|
break;
|
|
|
|
|
default:
|
|
|
|
|
internalError ();
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
lastregno = regno;
|
|
|
|
|
continue;
|
|
|
|
|
|
|
|
|
|
case 'P':
|
|
|
|
|
if (strncmp (s, "$pc", 3) == 0)
|
|
|
|
|
{
|
|
|
|
|
s += 3;
|
|
|
|
|
continue;
|
|
|
|
|
}
|
|
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
case '<':
|
|
|
|
|
case '>':
|
|
|
|
|
case '[':
|
|
|
|
|
case ']':
|
|
|
|
|
case '4':
|
|
|
|
|
case '5':
|
|
|
|
|
case 'H':
|
|
|
|
|
case 'W':
|
|
|
|
|
case 'D':
|
|
|
|
|
case 'j':
|
|
|
|
|
case '8':
|
|
|
|
|
case 'V':
|
|
|
|
|
case 'C':
|
|
|
|
|
case 'U':
|
|
|
|
|
case 'k':
|
|
|
|
|
case 'K':
|
|
|
|
|
if (s[0] == '%'
|
|
|
|
|
&& strncmp (s + 1, "gprel(", sizeof "gprel(" - 1) == 0)
|
|
|
|
|
{
|
|
|
|
|
/* This is %gprel(SYMBOL). We need to read SYMBOL,
|
|
|
|
|
and generate the appropriate reloc. If the text
|
|
|
|
|
inside %gprel is not a symbol name with an
|
|
|
|
|
optional offset, then we generate a normal reloc
|
|
|
|
|
and will probably fail later. */
|
|
|
|
|
my_getExpression (&imm_expr, s + sizeof "%gprel" - 1);
|
|
|
|
|
if (imm_expr.X_op == O_symbol)
|
|
|
|
|
{
|
2002-11-30 09:39:46 +01:00
|
|
|
|
mips16_ext = TRUE;
|
2001-10-04 22:07:00 +02:00
|
|
|
|
*imm_reloc = BFD_RELOC_MIPS16_GPREL;
|
1999-05-03 09:29:11 +02:00
|
|
|
|
s = expr_end;
|
2002-11-30 09:39:46 +01:00
|
|
|
|
ip->use_extend = TRUE;
|
1999-05-03 09:29:11 +02:00
|
|
|
|
ip->extend = 0;
|
|
|
|
|
continue;
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
else
|
|
|
|
|
{
|
|
|
|
|
/* Just pick up a normal expression. */
|
|
|
|
|
my_getExpression (&imm_expr, s);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
if (imm_expr.X_op == O_register)
|
|
|
|
|
{
|
|
|
|
|
/* What we thought was an expression turned out to
|
|
|
|
|
be a register. */
|
|
|
|
|
|
|
|
|
|
if (s[0] == '(' && args[1] == '(')
|
|
|
|
|
{
|
|
|
|
|
/* It looks like the expression was omitted
|
|
|
|
|
before a register indirection, which means
|
|
|
|
|
that the expression is implicitly zero. We
|
|
|
|
|
still set up imm_expr, so that we handle
|
|
|
|
|
explicit extensions correctly. */
|
|
|
|
|
imm_expr.X_op = O_constant;
|
|
|
|
|
imm_expr.X_add_number = 0;
|
2001-10-04 22:07:00 +02:00
|
|
|
|
*imm_reloc = (int) BFD_RELOC_UNUSED + c;
|
1999-05-03 09:29:11 +02:00
|
|
|
|
continue;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
break;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/* We need to relax this instruction. */
|
2001-10-04 22:07:00 +02:00
|
|
|
|
*imm_reloc = (int) BFD_RELOC_UNUSED + c;
|
1999-05-03 09:29:11 +02:00
|
|
|
|
s = expr_end;
|
|
|
|
|
continue;
|
|
|
|
|
|
|
|
|
|
case 'p':
|
|
|
|
|
case 'q':
|
|
|
|
|
case 'A':
|
|
|
|
|
case 'B':
|
|
|
|
|
case 'E':
|
|
|
|
|
/* We use offset_reloc rather than imm_reloc for the PC
|
|
|
|
|
relative operands. This lets macros with both
|
|
|
|
|
immediate and address operands work correctly. */
|
|
|
|
|
my_getExpression (&offset_expr, s);
|
|
|
|
|
|
|
|
|
|
if (offset_expr.X_op == O_register)
|
|
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
/* We need to relax this instruction. */
|
2001-10-04 22:07:00 +02:00
|
|
|
|
*offset_reloc = (int) BFD_RELOC_UNUSED + c;
|
1999-05-03 09:29:11 +02:00
|
|
|
|
s = expr_end;
|
|
|
|
|
continue;
|
|
|
|
|
|
|
|
|
|
case '6': /* break code */
|
|
|
|
|
my_getExpression (&imm_expr, s);
|
|
|
|
|
check_absolute_expr (ip, &imm_expr);
|
|
|
|
|
if ((unsigned long) imm_expr.X_add_number > 63)
|
|
|
|
|
{
|
|
|
|
|
as_warn (_("Invalid value for `%s' (%lu)"),
|
|
|
|
|
ip->insn_mo->name,
|
|
|
|
|
(unsigned long) imm_expr.X_add_number);
|
|
|
|
|
imm_expr.X_add_number &= 0x3f;
|
|
|
|
|
}
|
|
|
|
|
ip->insn_opcode |= imm_expr.X_add_number << MIPS16OP_SH_IMM6;
|
|
|
|
|
imm_expr.X_op = O_absent;
|
|
|
|
|
s = expr_end;
|
|
|
|
|
continue;
|
|
|
|
|
|
|
|
|
|
case 'a': /* 26 bit address */
|
|
|
|
|
my_getExpression (&offset_expr, s);
|
|
|
|
|
s = expr_end;
|
2001-10-04 22:07:00 +02:00
|
|
|
|
*offset_reloc = BFD_RELOC_MIPS16_JMP;
|
1999-05-03 09:29:11 +02:00
|
|
|
|
ip->insn_opcode <<= 16;
|
|
|
|
|
continue;
|
|
|
|
|
|
|
|
|
|
case 'l': /* register list for entry macro */
|
|
|
|
|
case 'L': /* register list for exit macro */
|
|
|
|
|
{
|
|
|
|
|
int mask;
|
|
|
|
|
|
|
|
|
|
if (c == 'l')
|
|
|
|
|
mask = 0;
|
|
|
|
|
else
|
|
|
|
|
mask = 7 << 3;
|
|
|
|
|
while (*s != '\0')
|
|
|
|
|
{
|
|
|
|
|
int freg, reg1, reg2;
|
|
|
|
|
|
|
|
|
|
while (*s == ' ' || *s == ',')
|
|
|
|
|
++s;
|
|
|
|
|
if (*s != '$')
|
|
|
|
|
{
|
|
|
|
|
as_bad (_("can't parse register list"));
|
|
|
|
|
break;
|
|
|
|
|
}
|
|
|
|
|
++s;
|
|
|
|
|
if (*s != 'f')
|
|
|
|
|
freg = 0;
|
|
|
|
|
else
|
|
|
|
|
{
|
|
|
|
|
freg = 1;
|
|
|
|
|
++s;
|
|
|
|
|
}
|
|
|
|
|
reg1 = 0;
|
2001-09-19 07:33:36 +02:00
|
|
|
|
while (ISDIGIT (*s))
|
1999-05-03 09:29:11 +02:00
|
|
|
|
{
|
|
|
|
|
reg1 *= 10;
|
|
|
|
|
reg1 += *s - '0';
|
|
|
|
|
++s;
|
|
|
|
|
}
|
|
|
|
|
if (*s == ' ')
|
|
|
|
|
++s;
|
|
|
|
|
if (*s != '-')
|
|
|
|
|
reg2 = reg1;
|
|
|
|
|
else
|
|
|
|
|
{
|
|
|
|
|
++s;
|
|
|
|
|
if (*s != '$')
|
|
|
|
|
break;
|
|
|
|
|
++s;
|
|
|
|
|
if (freg)
|
|
|
|
|
{
|
|
|
|
|
if (*s == 'f')
|
|
|
|
|
++s;
|
|
|
|
|
else
|
|
|
|
|
{
|
|
|
|
|
as_bad (_("invalid register list"));
|
|
|
|
|
break;
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
reg2 = 0;
|
2001-09-19 07:33:36 +02:00
|
|
|
|
while (ISDIGIT (*s))
|
1999-05-03 09:29:11 +02:00
|
|
|
|
{
|
|
|
|
|
reg2 *= 10;
|
|
|
|
|
reg2 += *s - '0';
|
|
|
|
|
++s;
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
if (freg && reg1 == 0 && reg2 == 0 && c == 'L')
|
|
|
|
|
{
|
|
|
|
|
mask &= ~ (7 << 3);
|
|
|
|
|
mask |= 5 << 3;
|
|
|
|
|
}
|
|
|
|
|
else if (freg && reg1 == 0 && reg2 == 1 && c == 'L')
|
|
|
|
|
{
|
|
|
|
|
mask &= ~ (7 << 3);
|
|
|
|
|
mask |= 6 << 3;
|
|
|
|
|
}
|
|
|
|
|
else if (reg1 == 4 && reg2 >= 4 && reg2 <= 7 && c != 'L')
|
|
|
|
|
mask |= (reg2 - 3) << 3;
|
|
|
|
|
else if (reg1 == 16 && reg2 >= 16 && reg2 <= 17)
|
|
|
|
|
mask |= (reg2 - 15) << 1;
|
2002-05-26 20:46:37 +02:00
|
|
|
|
else if (reg1 == RA && reg2 == RA)
|
1999-05-03 09:29:11 +02:00
|
|
|
|
mask |= 1;
|
|
|
|
|
else
|
|
|
|
|
{
|
|
|
|
|
as_bad (_("invalid register list"));
|
|
|
|
|
break;
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
/* The mask is filled in in the opcode table for the
|
|
|
|
|
benefit of the disassembler. We remove it before
|
|
|
|
|
applying the actual mask. */
|
|
|
|
|
ip->insn_opcode &= ~ ((7 << 3) << MIPS16OP_SH_IMM6);
|
|
|
|
|
ip->insn_opcode |= mask << MIPS16OP_SH_IMM6;
|
|
|
|
|
}
|
|
|
|
|
continue;
|
|
|
|
|
|
|
|
|
|
case 'e': /* extend code */
|
|
|
|
|
my_getExpression (&imm_expr, s);
|
|
|
|
|
check_absolute_expr (ip, &imm_expr);
|
|
|
|
|
if ((unsigned long) imm_expr.X_add_number > 0x7ff)
|
|
|
|
|
{
|
|
|
|
|
as_warn (_("Invalid value for `%s' (%lu)"),
|
|
|
|
|
ip->insn_mo->name,
|
|
|
|
|
(unsigned long) imm_expr.X_add_number);
|
|
|
|
|
imm_expr.X_add_number &= 0x7ff;
|
|
|
|
|
}
|
|
|
|
|
ip->insn_opcode |= imm_expr.X_add_number;
|
|
|
|
|
imm_expr.X_op = O_absent;
|
|
|
|
|
s = expr_end;
|
|
|
|
|
continue;
|
|
|
|
|
|
|
|
|
|
default:
|
|
|
|
|
internalError ();
|
|
|
|
|
}
|
|
|
|
|
break;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/* Args don't match. */
|
|
|
|
|
if (insn + 1 < &mips16_opcodes[bfd_mips16_num_opcodes] &&
|
|
|
|
|
strcmp (insn->name, insn[1].name) == 0)
|
|
|
|
|
{
|
|
|
|
|
++insn;
|
|
|
|
|
s = argsstart;
|
|
|
|
|
continue;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
insn_error = _("illegal operands");
|
|
|
|
|
|
|
|
|
|
return;
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/* This structure holds information we know about a mips16 immediate
|
|
|
|
|
argument type. */
|
|
|
|
|
|
2000-12-12 20:29:24 +01:00
|
|
|
|
struct mips16_immed_operand
|
|
|
|
|
{
|
1999-05-03 09:29:11 +02:00
|
|
|
|
/* The type code used in the argument string in the opcode table. */
|
|
|
|
|
int type;
|
|
|
|
|
/* The number of bits in the short form of the opcode. */
|
|
|
|
|
int nbits;
|
|
|
|
|
/* The number of bits in the extended form of the opcode. */
|
|
|
|
|
int extbits;
|
|
|
|
|
/* The amount by which the short form is shifted when it is used;
|
|
|
|
|
for example, the sw instruction has a shift count of 2. */
|
|
|
|
|
int shift;
|
|
|
|
|
/* The amount by which the short form is shifted when it is stored
|
|
|
|
|
into the instruction code. */
|
|
|
|
|
int op_shift;
|
|
|
|
|
/* Non-zero if the short form is unsigned. */
|
|
|
|
|
int unsp;
|
|
|
|
|
/* Non-zero if the extended form is unsigned. */
|
|
|
|
|
int extu;
|
|
|
|
|
/* Non-zero if the value is PC relative. */
|
|
|
|
|
int pcrel;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
/* The mips16 immediate operand types. */
|
|
|
|
|
|
|
|
|
|
static const struct mips16_immed_operand mips16_immed_operands[] =
|
|
|
|
|
{
|
|
|
|
|
{ '<', 3, 5, 0, MIPS16OP_SH_RZ, 1, 1, 0 },
|
|
|
|
|
{ '>', 3, 5, 0, MIPS16OP_SH_RX, 1, 1, 0 },
|
|
|
|
|
{ '[', 3, 6, 0, MIPS16OP_SH_RZ, 1, 1, 0 },
|
|
|
|
|
{ ']', 3, 6, 0, MIPS16OP_SH_RX, 1, 1, 0 },
|
|
|
|
|
{ '4', 4, 15, 0, MIPS16OP_SH_IMM4, 0, 0, 0 },
|
|
|
|
|
{ '5', 5, 16, 0, MIPS16OP_SH_IMM5, 1, 0, 0 },
|
|
|
|
|
{ 'H', 5, 16, 1, MIPS16OP_SH_IMM5, 1, 0, 0 },
|
|
|
|
|
{ 'W', 5, 16, 2, MIPS16OP_SH_IMM5, 1, 0, 0 },
|
|
|
|
|
{ 'D', 5, 16, 3, MIPS16OP_SH_IMM5, 1, 0, 0 },
|
|
|
|
|
{ 'j', 5, 16, 0, MIPS16OP_SH_IMM5, 0, 0, 0 },
|
|
|
|
|
{ '8', 8, 16, 0, MIPS16OP_SH_IMM8, 1, 0, 0 },
|
|
|
|
|
{ 'V', 8, 16, 2, MIPS16OP_SH_IMM8, 1, 0, 0 },
|
|
|
|
|
{ 'C', 8, 16, 3, MIPS16OP_SH_IMM8, 1, 0, 0 },
|
|
|
|
|
{ 'U', 8, 16, 0, MIPS16OP_SH_IMM8, 1, 1, 0 },
|
|
|
|
|
{ 'k', 8, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 0 },
|
|
|
|
|
{ 'K', 8, 16, 3, MIPS16OP_SH_IMM8, 0, 0, 0 },
|
|
|
|
|
{ 'p', 8, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 1 },
|
|
|
|
|
{ 'q', 11, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 1 },
|
|
|
|
|
{ 'A', 8, 16, 2, MIPS16OP_SH_IMM8, 1, 0, 1 },
|
|
|
|
|
{ 'B', 5, 16, 3, MIPS16OP_SH_IMM5, 1, 0, 1 },
|
|
|
|
|
{ 'E', 5, 16, 2, MIPS16OP_SH_IMM5, 1, 0, 1 }
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
#define MIPS16_NUM_IMMED \
|
|
|
|
|
(sizeof mips16_immed_operands / sizeof mips16_immed_operands[0])
|
|
|
|
|
|
|
|
|
|
/* Handle a mips16 instruction with an immediate value. This or's the
|
|
|
|
|
small immediate value into *INSN. It sets *USE_EXTEND to indicate
|
|
|
|
|
whether an extended value is needed; if one is needed, it sets
|
|
|
|
|
*EXTEND to the value. The argument type is TYPE. The value is VAL.
|
|
|
|
|
If SMALL is true, an unextended opcode was explicitly requested.
|
|
|
|
|
If EXT is true, an extended opcode was explicitly requested. If
|
|
|
|
|
WARN is true, warn if EXT does not match reality. */
|
|
|
|
|
|
|
|
|
|
static void
|
2003-06-30 14:44:25 +02:00
|
|
|
|
mips16_immed (char *file, unsigned int line, int type, offsetT val,
|
|
|
|
|
bfd_boolean warn, bfd_boolean small, bfd_boolean ext,
|
|
|
|
|
unsigned long *insn, bfd_boolean *use_extend,
|
|
|
|
|
unsigned short *extend)
|
1999-05-03 09:29:11 +02:00
|
|
|
|
{
|
|
|
|
|
register const struct mips16_immed_operand *op;
|
|
|
|
|
int mintiny, maxtiny;
|
2002-11-30 09:39:46 +01:00
|
|
|
|
bfd_boolean needext;
|
1999-05-03 09:29:11 +02:00
|
|
|
|
|
|
|
|
|
op = mips16_immed_operands;
|
|
|
|
|
while (op->type != type)
|
|
|
|
|
{
|
|
|
|
|
++op;
|
|
|
|
|
assert (op < mips16_immed_operands + MIPS16_NUM_IMMED);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
if (op->unsp)
|
|
|
|
|
{
|
|
|
|
|
if (type == '<' || type == '>' || type == '[' || type == ']')
|
|
|
|
|
{
|
|
|
|
|
mintiny = 1;
|
|
|
|
|
maxtiny = 1 << op->nbits;
|
|
|
|
|
}
|
|
|
|
|
else
|
|
|
|
|
{
|
|
|
|
|
mintiny = 0;
|
|
|
|
|
maxtiny = (1 << op->nbits) - 1;
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
else
|
|
|
|
|
{
|
|
|
|
|
mintiny = - (1 << (op->nbits - 1));
|
|
|
|
|
maxtiny = (1 << (op->nbits - 1)) - 1;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/* Branch offsets have an implicit 0 in the lowest bit. */
|
|
|
|
|
if (type == 'p' || type == 'q')
|
|
|
|
|
val /= 2;
|
|
|
|
|
|
|
|
|
|
if ((val & ((1 << op->shift) - 1)) != 0
|
|
|
|
|
|| val < (mintiny << op->shift)
|
|
|
|
|
|| val > (maxtiny << op->shift))
|
2002-11-30 09:39:46 +01:00
|
|
|
|
needext = TRUE;
|
1999-05-03 09:29:11 +02:00
|
|
|
|
else
|
2002-11-30 09:39:46 +01:00
|
|
|
|
needext = FALSE;
|
1999-05-03 09:29:11 +02:00
|
|
|
|
|
|
|
|
|
if (warn && ext && ! needext)
|
2000-12-05 19:51:08 +01:00
|
|
|
|
as_warn_where (file, line,
|
|
|
|
|
_("extended operand requested but not required"));
|
1999-05-03 09:29:11 +02:00
|
|
|
|
if (small && needext)
|
|
|
|
|
as_bad_where (file, line, _("invalid unextended operand value"));
|
|
|
|
|
|
|
|
|
|
if (small || (! ext && ! needext))
|
|
|
|
|
{
|
|
|
|
|
int insnval;
|
|
|
|
|
|
2002-11-30 09:39:46 +01:00
|
|
|
|
*use_extend = FALSE;
|
1999-05-03 09:29:11 +02:00
|
|
|
|
insnval = ((val >> op->shift) & ((1 << op->nbits) - 1));
|
|
|
|
|
insnval <<= op->op_shift;
|
|
|
|
|
*insn |= insnval;
|
|
|
|
|
}
|
|
|
|
|
else
|
|
|
|
|
{
|
|
|
|
|
long minext, maxext;
|
|
|
|
|
int extval;
|
|
|
|
|
|
|
|
|
|
if (op->extu)
|
|
|
|
|
{
|
|
|
|
|
minext = 0;
|
|
|
|
|
maxext = (1 << op->extbits) - 1;
|
|
|
|
|
}
|
|
|
|
|
else
|
|
|
|
|
{
|
|
|
|
|
minext = - (1 << (op->extbits - 1));
|
|
|
|
|
maxext = (1 << (op->extbits - 1)) - 1;
|
|
|
|
|
}
|
|
|
|
|
if (val < minext || val > maxext)
|
|
|
|
|
as_bad_where (file, line,
|
|
|
|
|
_("operand value out of range for instruction"));
|
|
|
|
|
|
2002-11-30 09:39:46 +01:00
|
|
|
|
*use_extend = TRUE;
|
1999-05-03 09:29:11 +02:00
|
|
|
|
if (op->extbits == 16)
|
|
|
|
|
{
|
|
|
|
|
extval = ((val >> 11) & 0x1f) | (val & 0x7e0);
|
|
|
|
|
val &= 0x1f;
|
|
|
|
|
}
|
|
|
|
|
else if (op->extbits == 15)
|
|
|
|
|
{
|
|
|
|
|
extval = ((val >> 11) & 0xf) | (val & 0x7f0);
|
|
|
|
|
val &= 0xf;
|
|
|
|
|
}
|
|
|
|
|
else
|
|
|
|
|
{
|
|
|
|
|
extval = ((val & 0x1f) << 6) | (val & 0x20);
|
|
|
|
|
val = 0;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
*extend = (unsigned short) extval;
|
|
|
|
|
*insn |= val;
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
2003-02-02 20:37:20 +01:00
|
|
|
|
static const struct percent_op_match
|
2001-10-10 02:54:53 +02:00
|
|
|
|
{
|
2003-02-02 20:37:20 +01:00
|
|
|
|
const char *str;
|
|
|
|
|
bfd_reloc_code_real_type reloc;
|
2001-10-10 02:54:53 +02:00
|
|
|
|
} percent_op[] =
|
|
|
|
|
{
|
2003-02-02 20:37:20 +01:00
|
|
|
|
{"%lo", BFD_RELOC_LO16},
|
2001-10-10 02:54:53 +02:00
|
|
|
|
#ifdef OBJ_ELF
|
2003-02-02 20:37:20 +01:00
|
|
|
|
{"%call_hi", BFD_RELOC_MIPS_CALL_HI16},
|
|
|
|
|
{"%call_lo", BFD_RELOC_MIPS_CALL_LO16},
|
|
|
|
|
{"%call16", BFD_RELOC_MIPS_CALL16},
|
|
|
|
|
{"%got_disp", BFD_RELOC_MIPS_GOT_DISP},
|
|
|
|
|
{"%got_page", BFD_RELOC_MIPS_GOT_PAGE},
|
|
|
|
|
{"%got_ofst", BFD_RELOC_MIPS_GOT_OFST},
|
|
|
|
|
{"%got_hi", BFD_RELOC_MIPS_GOT_HI16},
|
|
|
|
|
{"%got_lo", BFD_RELOC_MIPS_GOT_LO16},
|
|
|
|
|
{"%got", BFD_RELOC_MIPS_GOT16},
|
|
|
|
|
{"%gp_rel", BFD_RELOC_GPREL16},
|
|
|
|
|
{"%half", BFD_RELOC_16},
|
|
|
|
|
{"%highest", BFD_RELOC_MIPS_HIGHEST},
|
|
|
|
|
{"%higher", BFD_RELOC_MIPS_HIGHER},
|
|
|
|
|
{"%neg", BFD_RELOC_MIPS_SUB},
|
2001-10-10 02:54:53 +02:00
|
|
|
|
#endif
|
2003-02-02 20:37:20 +01:00
|
|
|
|
{"%hi", BFD_RELOC_HI16_S}
|
2001-10-10 02:54:53 +02:00
|
|
|
|
};
|
|
|
|
|
|
1999-05-03 09:29:11 +02:00
|
|
|
|
|
2003-02-02 20:37:20 +01:00
|
|
|
|
/* Return true if *STR points to a relocation operator. When returning true,
|
|
|
|
|
move *STR over the operator and store its relocation code in *RELOC.
|
|
|
|
|
Leave both *STR and *RELOC alone when returning false. */
|
|
|
|
|
|
|
|
|
|
static bfd_boolean
|
2003-06-30 14:44:25 +02:00
|
|
|
|
parse_relocation (char **str, bfd_reloc_code_real_type *reloc)
|
1999-05-03 09:29:11 +02:00
|
|
|
|
{
|
2003-02-02 20:37:20 +01:00
|
|
|
|
size_t i;
|
2001-11-06 22:39:09 +01:00
|
|
|
|
|
2003-02-02 20:37:20 +01:00
|
|
|
|
for (i = 0; i < ARRAY_SIZE (percent_op); i++)
|
|
|
|
|
if (strncasecmp (*str, percent_op[i].str, strlen (percent_op[i].str)) == 0)
|
2002-01-16 22:30:47 +01:00
|
|
|
|
{
|
2003-02-02 20:37:20 +01:00
|
|
|
|
*str += strlen (percent_op[i].str);
|
|
|
|
|
*reloc = percent_op[i].reloc;
|
2002-01-16 22:30:47 +01:00
|
|
|
|
|
2003-02-02 20:37:20 +01:00
|
|
|
|
/* Check whether the output BFD supports this relocation.
|
|
|
|
|
If not, issue an error and fall back on something safe. */
|
|
|
|
|
if (!bfd_reloc_type_lookup (stdoutput, percent_op[i].reloc))
|
2002-01-16 22:30:47 +01:00
|
|
|
|
{
|
2003-02-02 20:37:20 +01:00
|
|
|
|
as_bad ("relocation %s isn't supported by the current ABI",
|
|
|
|
|
percent_op[i].str);
|
|
|
|
|
*reloc = BFD_RELOC_LO16;
|
2002-01-16 22:30:47 +01:00
|
|
|
|
}
|
2003-02-02 20:37:20 +01:00
|
|
|
|
return TRUE;
|
2002-01-16 22:30:47 +01:00
|
|
|
|
}
|
2003-02-02 20:37:20 +01:00
|
|
|
|
return FALSE;
|
2002-01-16 22:30:47 +01:00
|
|
|
|
}
|
2001-10-10 02:54:53 +02:00
|
|
|
|
|
|
|
|
|
|
2003-02-02 20:37:20 +01:00
|
|
|
|
/* Parse string STR as a 16-bit relocatable operand. Store the
|
|
|
|
|
expression in *EP and the relocations in the array starting
|
|
|
|
|
at RELOC. Return the number of relocation operators used.
|
2001-10-10 02:54:53 +02:00
|
|
|
|
|
2003-02-02 20:37:20 +01:00
|
|
|
|
On exit, EXPR_END points to the first character after the expression.
|
|
|
|
|
If no relocation operators are used, RELOC[0] is set to BFD_RELOC_LO16. */
|
2001-10-10 02:54:53 +02:00
|
|
|
|
|
2003-02-02 20:37:20 +01:00
|
|
|
|
static size_t
|
2003-06-30 14:44:25 +02:00
|
|
|
|
my_getSmallExpression (expressionS *ep, bfd_reloc_code_real_type *reloc,
|
|
|
|
|
char *str)
|
2001-10-10 02:54:53 +02:00
|
|
|
|
{
|
2003-02-02 20:37:20 +01:00
|
|
|
|
bfd_reloc_code_real_type reversed_reloc[3];
|
|
|
|
|
size_t reloc_index, i;
|
2003-02-07 16:06:33 +01:00
|
|
|
|
int crux_depth, str_depth;
|
|
|
|
|
char *crux;
|
2003-02-02 20:37:20 +01:00
|
|
|
|
|
|
|
|
|
/* Search for the start of the main expression, recoding relocations
|
2003-02-07 16:06:33 +01:00
|
|
|
|
in REVERSED_RELOC. End the loop with CRUX pointing to the start
|
|
|
|
|
of the main expression and with CRUX_DEPTH containing the number
|
|
|
|
|
of open brackets at that point. */
|
|
|
|
|
reloc_index = -1;
|
|
|
|
|
str_depth = 0;
|
|
|
|
|
do
|
2001-08-18 19:24:52 +02:00
|
|
|
|
{
|
2003-02-07 16:06:33 +01:00
|
|
|
|
reloc_index++;
|
|
|
|
|
crux = str;
|
|
|
|
|
crux_depth = str_depth;
|
|
|
|
|
|
|
|
|
|
/* Skip over whitespace and brackets, keeping count of the number
|
|
|
|
|
of brackets. */
|
|
|
|
|
while (*str == ' ' || *str == '\t' || *str == '(')
|
|
|
|
|
if (*str++ == '(')
|
|
|
|
|
str_depth++;
|
2003-02-02 20:37:20 +01:00
|
|
|
|
}
|
2003-02-07 16:06:33 +01:00
|
|
|
|
while (*str == '%'
|
|
|
|
|
&& reloc_index < (HAVE_NEWABI ? 3 : 1)
|
|
|
|
|
&& parse_relocation (&str, &reversed_reloc[reloc_index]));
|
2001-10-10 02:54:53 +02:00
|
|
|
|
|
2003-02-07 16:06:33 +01:00
|
|
|
|
my_getExpression (ep, crux);
|
2003-02-02 20:37:20 +01:00
|
|
|
|
str = expr_end;
|
2002-01-16 22:30:47 +01:00
|
|
|
|
|
2003-02-02 20:37:20 +01:00
|
|
|
|
/* Match every open bracket. */
|
2003-02-07 16:06:33 +01:00
|
|
|
|
while (crux_depth > 0 && (*str == ')' || *str == ' ' || *str == '\t'))
|
2003-02-02 20:37:20 +01:00
|
|
|
|
if (*str++ == ')')
|
2003-02-07 16:06:33 +01:00
|
|
|
|
crux_depth--;
|
2002-01-16 22:30:47 +01:00
|
|
|
|
|
2003-02-07 16:06:33 +01:00
|
|
|
|
if (crux_depth > 0)
|
2003-02-02 20:37:20 +01:00
|
|
|
|
as_bad ("unclosed '('");
|
2002-01-16 22:30:47 +01:00
|
|
|
|
|
2003-02-02 20:37:20 +01:00
|
|
|
|
expr_end = str;
|
1999-05-03 09:29:11 +02:00
|
|
|
|
|
2003-02-21 11:28:27 +01:00
|
|
|
|
if (reloc_index == 0)
|
|
|
|
|
reloc[0] = BFD_RELOC_LO16;
|
|
|
|
|
else
|
|
|
|
|
{
|
|
|
|
|
prev_reloc_op_frag = frag_now;
|
|
|
|
|
for (i = 0; i < reloc_index; i++)
|
|
|
|
|
reloc[i] = reversed_reloc[reloc_index - 1 - i];
|
|
|
|
|
}
|
2001-08-18 19:24:52 +02:00
|
|
|
|
|
2003-02-02 20:37:20 +01:00
|
|
|
|
return reloc_index;
|
1999-05-03 09:29:11 +02:00
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static void
|
2003-06-30 14:44:25 +02:00
|
|
|
|
my_getExpression (expressionS *ep, char *str)
|
1999-05-03 09:29:11 +02:00
|
|
|
|
{
|
|
|
|
|
char *save_in;
|
2001-06-08 08:07:13 +02:00
|
|
|
|
valueT val;
|
1999-05-03 09:29:11 +02:00
|
|
|
|
|
|
|
|
|
save_in = input_line_pointer;
|
|
|
|
|
input_line_pointer = str;
|
|
|
|
|
expression (ep);
|
|
|
|
|
expr_end = input_line_pointer;
|
|
|
|
|
input_line_pointer = save_in;
|
|
|
|
|
|
|
|
|
|
/* If we are in mips16 mode, and this is an expression based on `.',
|
|
|
|
|
then we bump the value of the symbol by 1 since that is how other
|
|
|
|
|
text symbols are handled. We don't bother to handle complex
|
|
|
|
|
expressions, just `.' plus or minus a constant. */
|
|
|
|
|
if (mips_opts.mips16
|
|
|
|
|
&& ep->X_op == O_symbol
|
|
|
|
|
&& strcmp (S_GET_NAME (ep->X_add_symbol), FAKE_LABEL_NAME) == 0
|
|
|
|
|
&& S_GET_SEGMENT (ep->X_add_symbol) == now_seg
|
Add support for storing local symbols in a small structure to save
memory when assembling large files.
* as.h: Don't include struc-symbol.h.
(symbolS): Add typedef.
* symbols.c: Include struc-symbol.h.
(local_hash): New static variable.
(save_symbol_name): New static function, from symbol_create.
(symbol_create): Call save_symbol_name.
(local_symbol_count): New static variable.
(local_symbol_conversion_count): Likewise.
(LOCAL_SYMBOL_CHECK): Define.
(local_symbol_make): New static function.
(local_symbol_convert): New static function.
(colon): Handle local symbols. Create local symbol for local
label name.
(symbol_table_insert): Handle local symbols.
(symbol_find_or_make): Create local symbol for local label name.
(symbol_find_base): Check for local symbol.
(symbol_append, symbol_insert): Check for local symbols.
(symbol_clear_list_pointers, symbol_remove): Likewise.
(verify_symbol_chain): Likewise.
(copy_symbol_attributes): Likewise.
(resolve_symbol_value): Handle local symbols.
(resolve_local_symbol): New static function.
(resolve_local_symbol_values): New function.
(S_GET_VALUE, S_SET_VALUE): Handle local symbols.
(S_IS_FUNCTION, S_IS_EXTERNAL, S_IS_WEAK, S_IS_COMMON): Likewise.
(S_IS_DEFINED, S_IS_DEBUG, S_IS_LOCAL, S_GET_NAME): Likewise.
(S_GET_SEGMENT, S_SET_SEGMENT, S_SET_EXTERNAL): Likewise.
(S_CLEAR_EXTERNAL, S_SET_WEAK, S_SET_NAME): Likewise.
(symbol_previous, symbol_next): New functions.
(symbol_get_value_expression): Likewise.
(symbol_set_value_expression): Likewise.
(symbol_set_frag, symbol_get_frag): Likewise.
(symbol_mark_used, symbol_clear_used, symbol_used_p): Likewise.
(symbol_mark_used_in_reloc): Likewise.
(symbol_clear_used_in_reloc, symbol_used_in_reloc_p): Likewise.
(symbol_mark_mri_common, symbol_clear_mri_common): Likewise.
(symbol_mri_common_p): Likewise.
(symbol_mark_written, symbol_clear_written): Likewise.
(symbol_written_p): Likewise.
(symbol_mark_resolved, symbol_resolved_p): Likewise.
(symbol_section_p, symbol_equated_p): Likewise.
(symbol_constant_p): Likewise.
(symbol_get_bfdsym, symbol_set_bfdsym): Likewise.
(symbol_get_obj, symbol_set_obj): Likewise.
(symbol_get_tc, symbol_set_tc): Likewise.
(symbol_begin): Initialize local_hash.
(print_symbol_value_1): Handle local symbols.
(symbol_print_statistics): Print local symbol statistics.
* symbols.h: Include "struc-symbol.h" if not BFD_ASSEMBLER.
Declare new symbols.c functions. Move many declarations here from
struc-symbol.h.
(SYMBOLS_NEED_BACKPOINTERS): Define if needed.
* struc-symbol.h (SYMBOLS_NEED_BACKPOINTERS): Don't set.
(struct symbol): Move bsym to make it clearly the first field.
Remove TARGET_SYMBOL_FIELDS.
(symbolS): Don't typedef.
(struct broken_word): Remove.
(N_TYPE_seg, seg_N_TYPE): Move to symbol.h.
(SEGMENT_TO_SYMBOL_TYPE, N_REGISTER): Likewise.
(symbol_clear_list_pointers): Likewise.
(symbol_insert, symbol_remove): Likewise.
(symbol_previous, symbol_append): Likewise.
(verify_symbol_chain, verify_symbol_chain_2): Likewise.
(struct local_symbol): Define.
(local_symbol_converted_p, local_symbol_mark_converted): Define.
(local_symbol_resolved_p, local_symbol_mark_resolved): Define.
(local_symbol_get_frag, local_symbol_set_frag): Define.
(local_symbol_get_real_symbol): Define.
(local_symbol_set_real_symbol): Define.
Define.
* write.c (write_object_file): Call resolve_local_symbol_values.
* config/obj-ecoff.h (OBJ_SYMFIELD_TYPE): Define.
(TARGET_SYMBOL_FIELDS): Don't define.
* config/obj-elf.h (OBJ_SYMFIELD_TYPE): Add local field. If
ECOFF_DEBUGGING, add ECOFF fields.
(ELF_TARGET_SYMBOL_FIELDS, TARGET_SYMBOL_FIELDS): Don't define.
* config/obj-multi.h (struct elf_obj_sy): Add local field. If
ECOFF_DEBUGGING, add ECOFF fields.
(ELF_TARGET_SYMBOL_FIELDS, TARGET_SYMBOL_FIELDS): Don't define.
(ECOFF_DEBUG_TARGET_SYMBOL_FIELDS): Don't define.
* config/tc-mcore.h: Don't include struc-symbol.h.
(TARGET_SYMBOL_FIELDS): Don't define.
(struct mcore_tc_sy): Define.
(TC_SYMFIELD_TYPE): Define.
* Many files: Use symbolS instead of struct symbol. Use new
accessor functions rather than referring to symbolS fields
directly.
* read.c (s_mri_common): Don't add in value of line_label.
* config/tc-mips.c (md_apply_fix): Correct parenthesization when
checking for SEC_LINK_ONCE.
* config/tc-sh.h (sh_fix_adjustable): Declare.
1999-06-03 02:29:48 +02:00
|
|
|
|
&& symbol_get_frag (ep->X_add_symbol) == frag_now
|
|
|
|
|
&& symbol_constant_p (ep->X_add_symbol)
|
2001-06-08 08:07:13 +02:00
|
|
|
|
&& (val = S_GET_VALUE (ep->X_add_symbol)) == frag_now_fix ())
|
|
|
|
|
S_SET_VALUE (ep->X_add_symbol, val + 1);
|
1999-05-03 09:29:11 +02:00
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/* Turn a string in input_line_pointer into a floating point constant
|
2000-07-07 18:58:25 +02:00
|
|
|
|
of type TYPE, and store the appropriate bytes in *LITP. The number
|
|
|
|
|
of LITTLENUMS emitted is stored in *SIZEP. An error message is
|
1999-05-03 09:29:11 +02:00
|
|
|
|
returned, or NULL on OK. */
|
|
|
|
|
|
|
|
|
|
char *
|
2003-06-30 14:44:25 +02:00
|
|
|
|
md_atof (int type, char *litP, int *sizeP)
|
1999-05-03 09:29:11 +02:00
|
|
|
|
{
|
|
|
|
|
int prec;
|
|
|
|
|
LITTLENUM_TYPE words[4];
|
|
|
|
|
char *t;
|
|
|
|
|
int i;
|
|
|
|
|
|
|
|
|
|
switch (type)
|
|
|
|
|
{
|
|
|
|
|
case 'f':
|
|
|
|
|
prec = 2;
|
|
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
case 'd':
|
|
|
|
|
prec = 4;
|
|
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
default:
|
|
|
|
|
*sizeP = 0;
|
|
|
|
|
return _("bad call to md_atof");
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
t = atof_ieee (input_line_pointer, type, words);
|
|
|
|
|
if (t)
|
|
|
|
|
input_line_pointer = t;
|
|
|
|
|
|
|
|
|
|
*sizeP = prec * 2;
|
|
|
|
|
|
|
|
|
|
if (! target_big_endian)
|
|
|
|
|
{
|
|
|
|
|
for (i = prec - 1; i >= 0; i--)
|
|
|
|
|
{
|
2003-06-30 14:44:25 +02:00
|
|
|
|
md_number_to_chars (litP, words[i], 2);
|
1999-05-03 09:29:11 +02:00
|
|
|
|
litP += 2;
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
else
|
|
|
|
|
{
|
|
|
|
|
for (i = 0; i < prec; i++)
|
|
|
|
|
{
|
2003-06-30 14:44:25 +02:00
|
|
|
|
md_number_to_chars (litP, words[i], 2);
|
1999-05-03 09:29:11 +02:00
|
|
|
|
litP += 2;
|
|
|
|
|
}
|
|
|
|
|
}
|
2000-09-07 14:45:56 +02:00
|
|
|
|
|
1999-05-03 09:29:11 +02:00
|
|
|
|
return NULL;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
void
|
2003-06-30 14:44:25 +02:00
|
|
|
|
md_number_to_chars (char *buf, valueT val, int n)
|
1999-05-03 09:29:11 +02:00
|
|
|
|
{
|
|
|
|
|
if (target_big_endian)
|
|
|
|
|
number_to_chars_bigendian (buf, val, n);
|
|
|
|
|
else
|
|
|
|
|
number_to_chars_littleendian (buf, val, n);
|
|
|
|
|
}
|
|
|
|
|
|
2001-11-12 23:22:20 +01:00
|
|
|
|
#ifdef OBJ_ELF
|
2001-10-03 22:30:15 +02:00
|
|
|
|
static int support_64bit_objects(void)
|
|
|
|
|
{
|
|
|
|
|
const char **list, **l;
|
2002-11-05 22:53:13 +01:00
|
|
|
|
int yes;
|
2001-10-03 22:30:15 +02:00
|
|
|
|
|
|
|
|
|
list = bfd_target_list ();
|
|
|
|
|
for (l = list; *l != NULL; l++)
|
|
|
|
|
#ifdef TE_TMIPS
|
|
|
|
|
/* This is traditional mips */
|
|
|
|
|
if (strcmp (*l, "elf64-tradbigmips") == 0
|
|
|
|
|
|| strcmp (*l, "elf64-tradlittlemips") == 0)
|
|
|
|
|
#else
|
|
|
|
|
if (strcmp (*l, "elf64-bigmips") == 0
|
|
|
|
|
|| strcmp (*l, "elf64-littlemips") == 0)
|
|
|
|
|
#endif
|
|
|
|
|
break;
|
2002-11-05 22:53:13 +01:00
|
|
|
|
yes = (*l != NULL);
|
2001-10-03 22:30:15 +02:00
|
|
|
|
free (list);
|
2002-11-05 22:53:13 +01:00
|
|
|
|
return yes;
|
2001-10-03 22:30:15 +02:00
|
|
|
|
}
|
2001-11-12 23:22:20 +01:00
|
|
|
|
#endif /* OBJ_ELF */
|
2001-10-03 22:30:15 +02:00
|
|
|
|
|
2004-01-09 03:34:04 +01:00
|
|
|
|
const char *md_shortopts = "O::g::G:";
|
1999-05-03 09:29:11 +02:00
|
|
|
|
|
2000-12-12 20:29:24 +01:00
|
|
|
|
struct option md_longopts[] =
|
|
|
|
|
{
|
2003-06-03 Chris Demetriou <cgd@broadcom.com>
* config/tc-mips.c: (OPTION_ARCH_BASE, OPTION_ASE_BASE)
(OPTION_COMPAT_ARCH_BASE, OPTION_FIX_BASE)
(OPTION_MISC_BASE): New defines.
(OPTION_BREAK, OPTION_CONSTRUCT_FLOATS, OPTION_EB, OPTION_EL)
(OPTION_ELF_BASE, OPTION_FIX_VR4122, OPTION_FP32, OPTION_FP64)
(OPTION_GP32, OPTION_GP64, OPTION_M3900, OPTION_M4010, OPTION_M4100)
(OPTION_M4650, OPTION_M7000_HILO_FIX, OPTION_MARCH, OPTION_MDMX)
(OPTION_MEMBEDDED_PIC, OPTION_MIPS1, OPTION_MIPS16, OPTION_MIPS2)
(OPTION_MIPS3, OPTION_MIPS32, OPTION_MIPS32R2, OPTION_MIPS3D)
(OPTION_MIPS4, OPTION_MIPS5, OPTION_MIPS64)
(OPTION_MNO_7000_HILO_FIX, OPTION_MTUNE, OPTION_NO_CONSTRUCT_FLOATS)
(OPTION_NO_FIX_VR4122, OPTION_NO_M3900, OPTION_NO_M4010)
(OPTION_NO_M4100, OPTION_NO_M4650, OPTION_NO_MDMX, OPTION_NO_MIPS16)
(OPTION_NO_MIPS3D, OPTION_NO_RELAX_BRANCH, OPTION_RELAX_BRANCH)
(OPTION_TRAP): Redefine in terms of new defines.
(md_longopts): Reorder entries.
2003-06-04 08:38:38 +02:00
|
|
|
|
/* Options which specify architecture. */
|
|
|
|
|
#define OPTION_ARCH_BASE (OPTION_MD_BASE)
|
|
|
|
|
#define OPTION_MARCH (OPTION_ARCH_BASE + 0)
|
|
|
|
|
{"march", required_argument, NULL, OPTION_MARCH},
|
|
|
|
|
#define OPTION_MTUNE (OPTION_ARCH_BASE + 1)
|
|
|
|
|
{"mtune", required_argument, NULL, OPTION_MTUNE},
|
|
|
|
|
#define OPTION_MIPS1 (OPTION_ARCH_BASE + 2)
|
1999-05-03 09:29:11 +02:00
|
|
|
|
{"mips0", no_argument, NULL, OPTION_MIPS1},
|
|
|
|
|
{"mips1", no_argument, NULL, OPTION_MIPS1},
|
2003-06-03 Chris Demetriou <cgd@broadcom.com>
* config/tc-mips.c: (OPTION_ARCH_BASE, OPTION_ASE_BASE)
(OPTION_COMPAT_ARCH_BASE, OPTION_FIX_BASE)
(OPTION_MISC_BASE): New defines.
(OPTION_BREAK, OPTION_CONSTRUCT_FLOATS, OPTION_EB, OPTION_EL)
(OPTION_ELF_BASE, OPTION_FIX_VR4122, OPTION_FP32, OPTION_FP64)
(OPTION_GP32, OPTION_GP64, OPTION_M3900, OPTION_M4010, OPTION_M4100)
(OPTION_M4650, OPTION_M7000_HILO_FIX, OPTION_MARCH, OPTION_MDMX)
(OPTION_MEMBEDDED_PIC, OPTION_MIPS1, OPTION_MIPS16, OPTION_MIPS2)
(OPTION_MIPS3, OPTION_MIPS32, OPTION_MIPS32R2, OPTION_MIPS3D)
(OPTION_MIPS4, OPTION_MIPS5, OPTION_MIPS64)
(OPTION_MNO_7000_HILO_FIX, OPTION_MTUNE, OPTION_NO_CONSTRUCT_FLOATS)
(OPTION_NO_FIX_VR4122, OPTION_NO_M3900, OPTION_NO_M4010)
(OPTION_NO_M4100, OPTION_NO_M4650, OPTION_NO_MDMX, OPTION_NO_MIPS16)
(OPTION_NO_MIPS3D, OPTION_NO_RELAX_BRANCH, OPTION_RELAX_BRANCH)
(OPTION_TRAP): Redefine in terms of new defines.
(md_longopts): Reorder entries.
2003-06-04 08:38:38 +02:00
|
|
|
|
#define OPTION_MIPS2 (OPTION_ARCH_BASE + 3)
|
1999-05-03 09:29:11 +02:00
|
|
|
|
{"mips2", no_argument, NULL, OPTION_MIPS2},
|
2003-06-03 Chris Demetriou <cgd@broadcom.com>
* config/tc-mips.c: (OPTION_ARCH_BASE, OPTION_ASE_BASE)
(OPTION_COMPAT_ARCH_BASE, OPTION_FIX_BASE)
(OPTION_MISC_BASE): New defines.
(OPTION_BREAK, OPTION_CONSTRUCT_FLOATS, OPTION_EB, OPTION_EL)
(OPTION_ELF_BASE, OPTION_FIX_VR4122, OPTION_FP32, OPTION_FP64)
(OPTION_GP32, OPTION_GP64, OPTION_M3900, OPTION_M4010, OPTION_M4100)
(OPTION_M4650, OPTION_M7000_HILO_FIX, OPTION_MARCH, OPTION_MDMX)
(OPTION_MEMBEDDED_PIC, OPTION_MIPS1, OPTION_MIPS16, OPTION_MIPS2)
(OPTION_MIPS3, OPTION_MIPS32, OPTION_MIPS32R2, OPTION_MIPS3D)
(OPTION_MIPS4, OPTION_MIPS5, OPTION_MIPS64)
(OPTION_MNO_7000_HILO_FIX, OPTION_MTUNE, OPTION_NO_CONSTRUCT_FLOATS)
(OPTION_NO_FIX_VR4122, OPTION_NO_M3900, OPTION_NO_M4010)
(OPTION_NO_M4100, OPTION_NO_M4650, OPTION_NO_MDMX, OPTION_NO_MIPS16)
(OPTION_NO_MIPS3D, OPTION_NO_RELAX_BRANCH, OPTION_RELAX_BRANCH)
(OPTION_TRAP): Redefine in terms of new defines.
(md_longopts): Reorder entries.
2003-06-04 08:38:38 +02:00
|
|
|
|
#define OPTION_MIPS3 (OPTION_ARCH_BASE + 4)
|
1999-05-03 09:29:11 +02:00
|
|
|
|
{"mips3", no_argument, NULL, OPTION_MIPS3},
|
2003-06-03 Chris Demetriou <cgd@broadcom.com>
* config/tc-mips.c: (OPTION_ARCH_BASE, OPTION_ASE_BASE)
(OPTION_COMPAT_ARCH_BASE, OPTION_FIX_BASE)
(OPTION_MISC_BASE): New defines.
(OPTION_BREAK, OPTION_CONSTRUCT_FLOATS, OPTION_EB, OPTION_EL)
(OPTION_ELF_BASE, OPTION_FIX_VR4122, OPTION_FP32, OPTION_FP64)
(OPTION_GP32, OPTION_GP64, OPTION_M3900, OPTION_M4010, OPTION_M4100)
(OPTION_M4650, OPTION_M7000_HILO_FIX, OPTION_MARCH, OPTION_MDMX)
(OPTION_MEMBEDDED_PIC, OPTION_MIPS1, OPTION_MIPS16, OPTION_MIPS2)
(OPTION_MIPS3, OPTION_MIPS32, OPTION_MIPS32R2, OPTION_MIPS3D)
(OPTION_MIPS4, OPTION_MIPS5, OPTION_MIPS64)
(OPTION_MNO_7000_HILO_FIX, OPTION_MTUNE, OPTION_NO_CONSTRUCT_FLOATS)
(OPTION_NO_FIX_VR4122, OPTION_NO_M3900, OPTION_NO_M4010)
(OPTION_NO_M4100, OPTION_NO_M4650, OPTION_NO_MDMX, OPTION_NO_MIPS16)
(OPTION_NO_MIPS3D, OPTION_NO_RELAX_BRANCH, OPTION_RELAX_BRANCH)
(OPTION_TRAP): Redefine in terms of new defines.
(md_longopts): Reorder entries.
2003-06-04 08:38:38 +02:00
|
|
|
|
#define OPTION_MIPS4 (OPTION_ARCH_BASE + 5)
|
1999-05-03 09:29:11 +02:00
|
|
|
|
{"mips4", no_argument, NULL, OPTION_MIPS4},
|
2003-06-03 Chris Demetriou <cgd@broadcom.com>
* config/tc-mips.c: (OPTION_ARCH_BASE, OPTION_ASE_BASE)
(OPTION_COMPAT_ARCH_BASE, OPTION_FIX_BASE)
(OPTION_MISC_BASE): New defines.
(OPTION_BREAK, OPTION_CONSTRUCT_FLOATS, OPTION_EB, OPTION_EL)
(OPTION_ELF_BASE, OPTION_FIX_VR4122, OPTION_FP32, OPTION_FP64)
(OPTION_GP32, OPTION_GP64, OPTION_M3900, OPTION_M4010, OPTION_M4100)
(OPTION_M4650, OPTION_M7000_HILO_FIX, OPTION_MARCH, OPTION_MDMX)
(OPTION_MEMBEDDED_PIC, OPTION_MIPS1, OPTION_MIPS16, OPTION_MIPS2)
(OPTION_MIPS3, OPTION_MIPS32, OPTION_MIPS32R2, OPTION_MIPS3D)
(OPTION_MIPS4, OPTION_MIPS5, OPTION_MIPS64)
(OPTION_MNO_7000_HILO_FIX, OPTION_MTUNE, OPTION_NO_CONSTRUCT_FLOATS)
(OPTION_NO_FIX_VR4122, OPTION_NO_M3900, OPTION_NO_M4010)
(OPTION_NO_M4100, OPTION_NO_M4650, OPTION_NO_MDMX, OPTION_NO_MIPS16)
(OPTION_NO_MIPS3D, OPTION_NO_RELAX_BRANCH, OPTION_RELAX_BRANCH)
(OPTION_TRAP): Redefine in terms of new defines.
(md_longopts): Reorder entries.
2003-06-04 08:38:38 +02:00
|
|
|
|
#define OPTION_MIPS5 (OPTION_ARCH_BASE + 6)
|
2001-11-12 23:22:20 +01:00
|
|
|
|
{"mips5", no_argument, NULL, OPTION_MIPS5},
|
2003-06-03 Chris Demetriou <cgd@broadcom.com>
* config/tc-mips.c: (OPTION_ARCH_BASE, OPTION_ASE_BASE)
(OPTION_COMPAT_ARCH_BASE, OPTION_FIX_BASE)
(OPTION_MISC_BASE): New defines.
(OPTION_BREAK, OPTION_CONSTRUCT_FLOATS, OPTION_EB, OPTION_EL)
(OPTION_ELF_BASE, OPTION_FIX_VR4122, OPTION_FP32, OPTION_FP64)
(OPTION_GP32, OPTION_GP64, OPTION_M3900, OPTION_M4010, OPTION_M4100)
(OPTION_M4650, OPTION_M7000_HILO_FIX, OPTION_MARCH, OPTION_MDMX)
(OPTION_MEMBEDDED_PIC, OPTION_MIPS1, OPTION_MIPS16, OPTION_MIPS2)
(OPTION_MIPS3, OPTION_MIPS32, OPTION_MIPS32R2, OPTION_MIPS3D)
(OPTION_MIPS4, OPTION_MIPS5, OPTION_MIPS64)
(OPTION_MNO_7000_HILO_FIX, OPTION_MTUNE, OPTION_NO_CONSTRUCT_FLOATS)
(OPTION_NO_FIX_VR4122, OPTION_NO_M3900, OPTION_NO_M4010)
(OPTION_NO_M4100, OPTION_NO_M4650, OPTION_NO_MDMX, OPTION_NO_MIPS16)
(OPTION_NO_MIPS3D, OPTION_NO_RELAX_BRANCH, OPTION_RELAX_BRANCH)
(OPTION_TRAP): Redefine in terms of new defines.
(md_longopts): Reorder entries.
2003-06-04 08:38:38 +02:00
|
|
|
|
#define OPTION_MIPS32 (OPTION_ARCH_BASE + 7)
|
2001-11-12 23:22:20 +01:00
|
|
|
|
{"mips32", no_argument, NULL, OPTION_MIPS32},
|
2003-06-03 Chris Demetriou <cgd@broadcom.com>
* config/tc-mips.c: (OPTION_ARCH_BASE, OPTION_ASE_BASE)
(OPTION_COMPAT_ARCH_BASE, OPTION_FIX_BASE)
(OPTION_MISC_BASE): New defines.
(OPTION_BREAK, OPTION_CONSTRUCT_FLOATS, OPTION_EB, OPTION_EL)
(OPTION_ELF_BASE, OPTION_FIX_VR4122, OPTION_FP32, OPTION_FP64)
(OPTION_GP32, OPTION_GP64, OPTION_M3900, OPTION_M4010, OPTION_M4100)
(OPTION_M4650, OPTION_M7000_HILO_FIX, OPTION_MARCH, OPTION_MDMX)
(OPTION_MEMBEDDED_PIC, OPTION_MIPS1, OPTION_MIPS16, OPTION_MIPS2)
(OPTION_MIPS3, OPTION_MIPS32, OPTION_MIPS32R2, OPTION_MIPS3D)
(OPTION_MIPS4, OPTION_MIPS5, OPTION_MIPS64)
(OPTION_MNO_7000_HILO_FIX, OPTION_MTUNE, OPTION_NO_CONSTRUCT_FLOATS)
(OPTION_NO_FIX_VR4122, OPTION_NO_M3900, OPTION_NO_M4010)
(OPTION_NO_M4100, OPTION_NO_M4650, OPTION_NO_MDMX, OPTION_NO_MIPS16)
(OPTION_NO_MIPS3D, OPTION_NO_RELAX_BRANCH, OPTION_RELAX_BRANCH)
(OPTION_TRAP): Redefine in terms of new defines.
(md_longopts): Reorder entries.
2003-06-04 08:38:38 +02:00
|
|
|
|
#define OPTION_MIPS64 (OPTION_ARCH_BASE + 8)
|
2001-11-12 23:22:20 +01:00
|
|
|
|
{"mips64", no_argument, NULL, OPTION_MIPS64},
|
2003-06-03 Chris Demetriou <cgd@broadcom.com>
* config/tc-mips.c: (OPTION_ARCH_BASE, OPTION_ASE_BASE)
(OPTION_COMPAT_ARCH_BASE, OPTION_FIX_BASE)
(OPTION_MISC_BASE): New defines.
(OPTION_BREAK, OPTION_CONSTRUCT_FLOATS, OPTION_EB, OPTION_EL)
(OPTION_ELF_BASE, OPTION_FIX_VR4122, OPTION_FP32, OPTION_FP64)
(OPTION_GP32, OPTION_GP64, OPTION_M3900, OPTION_M4010, OPTION_M4100)
(OPTION_M4650, OPTION_M7000_HILO_FIX, OPTION_MARCH, OPTION_MDMX)
(OPTION_MEMBEDDED_PIC, OPTION_MIPS1, OPTION_MIPS16, OPTION_MIPS2)
(OPTION_MIPS3, OPTION_MIPS32, OPTION_MIPS32R2, OPTION_MIPS3D)
(OPTION_MIPS4, OPTION_MIPS5, OPTION_MIPS64)
(OPTION_MNO_7000_HILO_FIX, OPTION_MTUNE, OPTION_NO_CONSTRUCT_FLOATS)
(OPTION_NO_FIX_VR4122, OPTION_NO_M3900, OPTION_NO_M4010)
(OPTION_NO_M4100, OPTION_NO_M4650, OPTION_NO_MDMX, OPTION_NO_MIPS16)
(OPTION_NO_MIPS3D, OPTION_NO_RELAX_BRANCH, OPTION_RELAX_BRANCH)
(OPTION_TRAP): Redefine in terms of new defines.
(md_longopts): Reorder entries.
2003-06-04 08:38:38 +02:00
|
|
|
|
#define OPTION_MIPS32R2 (OPTION_ARCH_BASE + 9)
|
|
|
|
|
{"mips32r2", no_argument, NULL, OPTION_MIPS32R2},
|
[ bfd/ChangeLog ]
2003-09-30 Chris Demetriou <cgd@broadcom.com>
* archures.c (bfd_mach_mipsisa64r2): New define.
* bfd-in2.h: Regenerate.
* aoutx.h (NAME(aout,machine_type)): Handle bfd_mach_mipsisa64r2.
* cpu-mips.c (I_mipsisa64r2): New enum value.
(arch_info_struct): Add entry for I_mipsisa64r2.
* elfxx-mips.c (_bfd_elf_mips_mach)
(_bfd_mips_elf_print_private_bfd_data): Handle E_MIPS_ARCH_64R2.
(mips_set_isa_flags): Add bfd_mach_mipsisa64r2 case.
(mips_mach_extensions): Add entry for bfd_mach_mipsisa64r2.
[ binutils/ChangeLog ]
2003-09-30 Chris Demetriou <cgd@broadcom.com>
* readelf.c (get_machine_flags): Handle E_MIPS_ARCH_64R2.
[ gas/Changelog ]
2003-09-30 Chris Demetriou <cgd@broadcom.com>
* configure.in (mipsisa64r2, mipsisa64r2el, mipsisa64r2*): New CPUs.
* configure: Regenerate.
* config/tc-mips.c (imm2_expr): New variable.
(md_assemble, mips16_ip): Initialize imm2_expr.
(ISA_HAS_64BIT_REGS, ISA_HAS_DROR, ISA_HAS_ROR): Add ISA_MIPS64R2.
(macro_build): Handle +A, +B, +C, +E, +F, +G, and +H format operands.
(macro): Handle M_DEXT and M_DINS.
(validate_mips_insn): Handle +E, +F, +G, +H, and +I format operands.
(mips_ip): Likewise.
(OPTION_MIPS64R2): New define.
(md_longopts): New entry for -mips64r2 (OPTION_MIPS64R2).
OPTION_ASE_BASE): Increase to compensate for OPTION_MIPS64R2.
(md_parse_option): Handle OPTION_MIPS64R2.
(s_mipsset): Handle setting "mips64r2" ISA.
(mips_cpu_info_table): Add mips64r2.
(md_show_usage): Document -mips64r2 option.
* doc/as.texinfo: Docuemnt -mips64r2 option.
* doc/c-mips.texi: Likewise.
[ gas/testsuite/ChangeLog ]
2003-09-30 Chris Demetriou <cgd@broadcom.com>
* gas/mips/cp0-names-mips64r2.d: New file.
* gas/mips/cp0sel-names-mips64r2.d: New file.
* gas/mips/elf_arch_mips64r2.d: New file.
* gas/mips/hwr-names-mips64r2.d: New file.
* gas/mips/mips32r2-ill-fp64.l: New file.
* gas/mips/mips32r2-ill-fp64.s: New file.
* gas/mips/mips64r2-ill.l: New file.
* gas/mips/mips64r2-ill.s: New file.
* gas/mips/mips64r2.d: New file.
* gas/mips/mips64r2.s: New file.
* gas/mips/mips.exp: Define "mips64r2" arch, and run new tests.
[ include/elf/ChangeLog ]
2003-09-30 Chris Demetriou <cgd@broadcom.com>
* mips.h (E_MIPS_ARCH_64R2): New define.
[ include/opcode/ChangeLog ]
2003-09-30 Chris Demetriou <cgd@broadcom.com>
* mips.h: Document +E, +F, +G, +H, and +I operand types.
Update documentation of I, +B and +C operand types.
(INSN_ISA64R2, ISA_MIPS64R2, CPU_MIPS64R2): New defines.
(M_DEXT, M_DINS): New enum values.
[ ld/ChangeLog ]
2003-09-30 Chris Demetriou <cgd@broadcom.com>
* ldmain.c (get_emulation): Ignore "-mips64r2".
[ ld/testsuite/ChangeLog ]
2003-09-30 Chris Demetriou <cgd@broadcom.com>
* ld-mips-elf/mips-elf-flags.exp: Add tests for combinations
with MIPS64r2.
[ opcodes/ChangeLog ]
2003-09-30 Chris Demetriou <cgd@broadcom.com>
* mips-dis.c (mips_arch_choices): Add entry for "mips64r2"
(print_insn_args): Add handing for +E, +F, +G, and +H.
* mips-opc.c (I65): New define for MIPS64r2.
(mips_builtin_opcodes): Add "dext", "dextm", "dextu", "dins",
"dinsm", "dinsu", "drotl", "drotr", "drotr32", "drotrv", "dsbh",
and "dshd" for MIPS64r2. Adjust "dror", "dror32", and "drorv" to
be supported on MIPS64r2.
2003-09-30 18:17:15 +02:00
|
|
|
|
#define OPTION_MIPS64R2 (OPTION_ARCH_BASE + 10)
|
|
|
|
|
{"mips64r2", no_argument, NULL, OPTION_MIPS64R2},
|
2003-06-03 Chris Demetriou <cgd@broadcom.com>
* config/tc-mips.c: (OPTION_ARCH_BASE, OPTION_ASE_BASE)
(OPTION_COMPAT_ARCH_BASE, OPTION_FIX_BASE)
(OPTION_MISC_BASE): New defines.
(OPTION_BREAK, OPTION_CONSTRUCT_FLOATS, OPTION_EB, OPTION_EL)
(OPTION_ELF_BASE, OPTION_FIX_VR4122, OPTION_FP32, OPTION_FP64)
(OPTION_GP32, OPTION_GP64, OPTION_M3900, OPTION_M4010, OPTION_M4100)
(OPTION_M4650, OPTION_M7000_HILO_FIX, OPTION_MARCH, OPTION_MDMX)
(OPTION_MEMBEDDED_PIC, OPTION_MIPS1, OPTION_MIPS16, OPTION_MIPS2)
(OPTION_MIPS3, OPTION_MIPS32, OPTION_MIPS32R2, OPTION_MIPS3D)
(OPTION_MIPS4, OPTION_MIPS5, OPTION_MIPS64)
(OPTION_MNO_7000_HILO_FIX, OPTION_MTUNE, OPTION_NO_CONSTRUCT_FLOATS)
(OPTION_NO_FIX_VR4122, OPTION_NO_M3900, OPTION_NO_M4010)
(OPTION_NO_M4100, OPTION_NO_M4650, OPTION_NO_MDMX, OPTION_NO_MIPS16)
(OPTION_NO_MIPS3D, OPTION_NO_RELAX_BRANCH, OPTION_RELAX_BRANCH)
(OPTION_TRAP): Redefine in terms of new defines.
(md_longopts): Reorder entries.
2003-06-04 08:38:38 +02:00
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|
/* Options which specify Application Specific Extensions (ASEs). */
|
[ bfd/ChangeLog ]
2003-09-30 Chris Demetriou <cgd@broadcom.com>
* archures.c (bfd_mach_mipsisa64r2): New define.
* bfd-in2.h: Regenerate.
* aoutx.h (NAME(aout,machine_type)): Handle bfd_mach_mipsisa64r2.
* cpu-mips.c (I_mipsisa64r2): New enum value.
(arch_info_struct): Add entry for I_mipsisa64r2.
* elfxx-mips.c (_bfd_elf_mips_mach)
(_bfd_mips_elf_print_private_bfd_data): Handle E_MIPS_ARCH_64R2.
(mips_set_isa_flags): Add bfd_mach_mipsisa64r2 case.
(mips_mach_extensions): Add entry for bfd_mach_mipsisa64r2.
[ binutils/ChangeLog ]
2003-09-30 Chris Demetriou <cgd@broadcom.com>
* readelf.c (get_machine_flags): Handle E_MIPS_ARCH_64R2.
[ gas/Changelog ]
2003-09-30 Chris Demetriou <cgd@broadcom.com>
* configure.in (mipsisa64r2, mipsisa64r2el, mipsisa64r2*): New CPUs.
* configure: Regenerate.
* config/tc-mips.c (imm2_expr): New variable.
(md_assemble, mips16_ip): Initialize imm2_expr.
(ISA_HAS_64BIT_REGS, ISA_HAS_DROR, ISA_HAS_ROR): Add ISA_MIPS64R2.
(macro_build): Handle +A, +B, +C, +E, +F, +G, and +H format operands.
(macro): Handle M_DEXT and M_DINS.
(validate_mips_insn): Handle +E, +F, +G, +H, and +I format operands.
(mips_ip): Likewise.
(OPTION_MIPS64R2): New define.
(md_longopts): New entry for -mips64r2 (OPTION_MIPS64R2).
OPTION_ASE_BASE): Increase to compensate for OPTION_MIPS64R2.
(md_parse_option): Handle OPTION_MIPS64R2.
(s_mipsset): Handle setting "mips64r2" ISA.
(mips_cpu_info_table): Add mips64r2.
(md_show_usage): Document -mips64r2 option.
* doc/as.texinfo: Docuemnt -mips64r2 option.
* doc/c-mips.texi: Likewise.
[ gas/testsuite/ChangeLog ]
2003-09-30 Chris Demetriou <cgd@broadcom.com>
* gas/mips/cp0-names-mips64r2.d: New file.
* gas/mips/cp0sel-names-mips64r2.d: New file.
* gas/mips/elf_arch_mips64r2.d: New file.
* gas/mips/hwr-names-mips64r2.d: New file.
* gas/mips/mips32r2-ill-fp64.l: New file.
* gas/mips/mips32r2-ill-fp64.s: New file.
* gas/mips/mips64r2-ill.l: New file.
* gas/mips/mips64r2-ill.s: New file.
* gas/mips/mips64r2.d: New file.
* gas/mips/mips64r2.s: New file.
* gas/mips/mips.exp: Define "mips64r2" arch, and run new tests.
[ include/elf/ChangeLog ]
2003-09-30 Chris Demetriou <cgd@broadcom.com>
* mips.h (E_MIPS_ARCH_64R2): New define.
[ include/opcode/ChangeLog ]
2003-09-30 Chris Demetriou <cgd@broadcom.com>
* mips.h: Document +E, +F, +G, +H, and +I operand types.
Update documentation of I, +B and +C operand types.
(INSN_ISA64R2, ISA_MIPS64R2, CPU_MIPS64R2): New defines.
(M_DEXT, M_DINS): New enum values.
[ ld/ChangeLog ]
2003-09-30 Chris Demetriou <cgd@broadcom.com>
* ldmain.c (get_emulation): Ignore "-mips64r2".
[ ld/testsuite/ChangeLog ]
2003-09-30 Chris Demetriou <cgd@broadcom.com>
* ld-mips-elf/mips-elf-flags.exp: Add tests for combinations
with MIPS64r2.
[ opcodes/ChangeLog ]
2003-09-30 Chris Demetriou <cgd@broadcom.com>
* mips-dis.c (mips_arch_choices): Add entry for "mips64r2"
(print_insn_args): Add handing for +E, +F, +G, and +H.
* mips-opc.c (I65): New define for MIPS64r2.
(mips_builtin_opcodes): Add "dext", "dextm", "dextu", "dins",
"dinsm", "dinsu", "drotl", "drotr", "drotr32", "drotrv", "dsbh",
and "dshd" for MIPS64r2. Adjust "dror", "dror32", and "drorv" to
be supported on MIPS64r2.
2003-09-30 18:17:15 +02:00
|
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|
#define OPTION_ASE_BASE (OPTION_ARCH_BASE + 11)
|
2003-06-03 Chris Demetriou <cgd@broadcom.com>
* config/tc-mips.c: (OPTION_ARCH_BASE, OPTION_ASE_BASE)
(OPTION_COMPAT_ARCH_BASE, OPTION_FIX_BASE)
(OPTION_MISC_BASE): New defines.
(OPTION_BREAK, OPTION_CONSTRUCT_FLOATS, OPTION_EB, OPTION_EL)
(OPTION_ELF_BASE, OPTION_FIX_VR4122, OPTION_FP32, OPTION_FP64)
(OPTION_GP32, OPTION_GP64, OPTION_M3900, OPTION_M4010, OPTION_M4100)
(OPTION_M4650, OPTION_M7000_HILO_FIX, OPTION_MARCH, OPTION_MDMX)
(OPTION_MEMBEDDED_PIC, OPTION_MIPS1, OPTION_MIPS16, OPTION_MIPS2)
(OPTION_MIPS3, OPTION_MIPS32, OPTION_MIPS32R2, OPTION_MIPS3D)
(OPTION_MIPS4, OPTION_MIPS5, OPTION_MIPS64)
(OPTION_MNO_7000_HILO_FIX, OPTION_MTUNE, OPTION_NO_CONSTRUCT_FLOATS)
(OPTION_NO_FIX_VR4122, OPTION_NO_M3900, OPTION_NO_M4010)
(OPTION_NO_M4100, OPTION_NO_M4650, OPTION_NO_MDMX, OPTION_NO_MIPS16)
(OPTION_NO_MIPS3D, OPTION_NO_RELAX_BRANCH, OPTION_RELAX_BRANCH)
(OPTION_TRAP): Redefine in terms of new defines.
(md_longopts): Reorder entries.
2003-06-04 08:38:38 +02:00
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#define OPTION_MIPS16 (OPTION_ASE_BASE + 0)
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{"mips16", no_argument, NULL, OPTION_MIPS16},
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#define OPTION_NO_MIPS16 (OPTION_ASE_BASE + 1)
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{"no-mips16", no_argument, NULL, OPTION_NO_MIPS16},
|
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#define OPTION_MIPS3D (OPTION_ASE_BASE + 2)
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{"mips3d", no_argument, NULL, OPTION_MIPS3D},
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#define OPTION_NO_MIPS3D (OPTION_ASE_BASE + 3)
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{"no-mips3d", no_argument, NULL, OPTION_NO_MIPS3D},
|
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#define OPTION_MDMX (OPTION_ASE_BASE + 4)
|
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{"mdmx", no_argument, NULL, OPTION_MDMX},
|
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#define OPTION_NO_MDMX (OPTION_ASE_BASE + 5)
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{"no-mdmx", no_argument, NULL, OPTION_NO_MDMX},
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/* Old-style architecture options. Don't add more of these. */
|
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#define OPTION_COMPAT_ARCH_BASE (OPTION_ASE_BASE + 6)
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#define OPTION_M4650 (OPTION_COMPAT_ARCH_BASE + 0)
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{"m4650", no_argument, NULL, OPTION_M4650},
|
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#define OPTION_NO_M4650 (OPTION_COMPAT_ARCH_BASE + 1)
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{"no-m4650", no_argument, NULL, OPTION_NO_M4650},
|
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#define OPTION_M4010 (OPTION_COMPAT_ARCH_BASE + 2)
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{"m4010", no_argument, NULL, OPTION_M4010},
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#define OPTION_NO_M4010 (OPTION_COMPAT_ARCH_BASE + 3)
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{"no-m4010", no_argument, NULL, OPTION_NO_M4010},
|
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#define OPTION_M4100 (OPTION_COMPAT_ARCH_BASE + 4)
|
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{"m4100", no_argument, NULL, OPTION_M4100},
|
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#define OPTION_NO_M4100 (OPTION_COMPAT_ARCH_BASE + 5)
|
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{"no-m4100", no_argument, NULL, OPTION_NO_M4100},
|
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#define OPTION_M3900 (OPTION_COMPAT_ARCH_BASE + 6)
|
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{"m3900", no_argument, NULL, OPTION_M3900},
|
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#define OPTION_NO_M3900 (OPTION_COMPAT_ARCH_BASE + 7)
|
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{"no-m3900", no_argument, NULL, OPTION_NO_M3900},
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/* Options which enable bug fixes. */
|
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#define OPTION_FIX_BASE (OPTION_COMPAT_ARCH_BASE + 8)
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#define OPTION_M7000_HILO_FIX (OPTION_FIX_BASE + 0)
|
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{"mfix7000", no_argument, NULL, OPTION_M7000_HILO_FIX},
|
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#define OPTION_MNO_7000_HILO_FIX (OPTION_FIX_BASE + 1)
|
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{"no-fix-7000", no_argument, NULL, OPTION_MNO_7000_HILO_FIX},
|
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{"mno-fix7000", no_argument, NULL, OPTION_MNO_7000_HILO_FIX},
|
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#define OPTION_FIX_VR4122 (OPTION_FIX_BASE + 2)
|
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#define OPTION_NO_FIX_VR4122 (OPTION_FIX_BASE + 3)
|
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{"mfix-vr4122-bugs", no_argument, NULL, OPTION_FIX_VR4122},
|
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{"no-mfix-vr4122-bugs", no_argument, NULL, OPTION_NO_FIX_VR4122},
|
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/* Miscellaneous options. */
|
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#define OPTION_MISC_BASE (OPTION_FIX_BASE + 4)
|
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#define OPTION_MEMBEDDED_PIC (OPTION_MISC_BASE + 0)
|
1999-05-03 09:29:11 +02:00
|
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|
{"membedded-pic", no_argument, NULL, OPTION_MEMBEDDED_PIC},
|
2003-06-03 Chris Demetriou <cgd@broadcom.com>
* config/tc-mips.c: (OPTION_ARCH_BASE, OPTION_ASE_BASE)
(OPTION_COMPAT_ARCH_BASE, OPTION_FIX_BASE)
(OPTION_MISC_BASE): New defines.
(OPTION_BREAK, OPTION_CONSTRUCT_FLOATS, OPTION_EB, OPTION_EL)
(OPTION_ELF_BASE, OPTION_FIX_VR4122, OPTION_FP32, OPTION_FP64)
(OPTION_GP32, OPTION_GP64, OPTION_M3900, OPTION_M4010, OPTION_M4100)
(OPTION_M4650, OPTION_M7000_HILO_FIX, OPTION_MARCH, OPTION_MDMX)
(OPTION_MEMBEDDED_PIC, OPTION_MIPS1, OPTION_MIPS16, OPTION_MIPS2)
(OPTION_MIPS3, OPTION_MIPS32, OPTION_MIPS32R2, OPTION_MIPS3D)
(OPTION_MIPS4, OPTION_MIPS5, OPTION_MIPS64)
(OPTION_MNO_7000_HILO_FIX, OPTION_MTUNE, OPTION_NO_CONSTRUCT_FLOATS)
(OPTION_NO_FIX_VR4122, OPTION_NO_M3900, OPTION_NO_M4010)
(OPTION_NO_M4100, OPTION_NO_M4650, OPTION_NO_MDMX, OPTION_NO_MIPS16)
(OPTION_NO_MIPS3D, OPTION_NO_RELAX_BRANCH, OPTION_RELAX_BRANCH)
(OPTION_TRAP): Redefine in terms of new defines.
(md_longopts): Reorder entries.
2003-06-04 08:38:38 +02:00
|
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#define OPTION_TRAP (OPTION_MISC_BASE + 1)
|
1999-05-03 09:29:11 +02:00
|
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|
|
{"trap", no_argument, NULL, OPTION_TRAP},
|
|
|
|
|
{"no-break", no_argument, NULL, OPTION_TRAP},
|
2003-06-03 Chris Demetriou <cgd@broadcom.com>
* config/tc-mips.c: (OPTION_ARCH_BASE, OPTION_ASE_BASE)
(OPTION_COMPAT_ARCH_BASE, OPTION_FIX_BASE)
(OPTION_MISC_BASE): New defines.
(OPTION_BREAK, OPTION_CONSTRUCT_FLOATS, OPTION_EB, OPTION_EL)
(OPTION_ELF_BASE, OPTION_FIX_VR4122, OPTION_FP32, OPTION_FP64)
(OPTION_GP32, OPTION_GP64, OPTION_M3900, OPTION_M4010, OPTION_M4100)
(OPTION_M4650, OPTION_M7000_HILO_FIX, OPTION_MARCH, OPTION_MDMX)
(OPTION_MEMBEDDED_PIC, OPTION_MIPS1, OPTION_MIPS16, OPTION_MIPS2)
(OPTION_MIPS3, OPTION_MIPS32, OPTION_MIPS32R2, OPTION_MIPS3D)
(OPTION_MIPS4, OPTION_MIPS5, OPTION_MIPS64)
(OPTION_MNO_7000_HILO_FIX, OPTION_MTUNE, OPTION_NO_CONSTRUCT_FLOATS)
(OPTION_NO_FIX_VR4122, OPTION_NO_M3900, OPTION_NO_M4010)
(OPTION_NO_M4100, OPTION_NO_M4650, OPTION_NO_MDMX, OPTION_NO_MIPS16)
(OPTION_NO_MIPS3D, OPTION_NO_RELAX_BRANCH, OPTION_RELAX_BRANCH)
(OPTION_TRAP): Redefine in terms of new defines.
(md_longopts): Reorder entries.
2003-06-04 08:38:38 +02:00
|
|
|
|
#define OPTION_BREAK (OPTION_MISC_BASE + 2)
|
1999-05-03 09:29:11 +02:00
|
|
|
|
{"break", no_argument, NULL, OPTION_BREAK},
|
|
|
|
|
{"no-trap", no_argument, NULL, OPTION_BREAK},
|
2003-06-03 Chris Demetriou <cgd@broadcom.com>
* config/tc-mips.c: (OPTION_ARCH_BASE, OPTION_ASE_BASE)
(OPTION_COMPAT_ARCH_BASE, OPTION_FIX_BASE)
(OPTION_MISC_BASE): New defines.
(OPTION_BREAK, OPTION_CONSTRUCT_FLOATS, OPTION_EB, OPTION_EL)
(OPTION_ELF_BASE, OPTION_FIX_VR4122, OPTION_FP32, OPTION_FP64)
(OPTION_GP32, OPTION_GP64, OPTION_M3900, OPTION_M4010, OPTION_M4100)
(OPTION_M4650, OPTION_M7000_HILO_FIX, OPTION_MARCH, OPTION_MDMX)
(OPTION_MEMBEDDED_PIC, OPTION_MIPS1, OPTION_MIPS16, OPTION_MIPS2)
(OPTION_MIPS3, OPTION_MIPS32, OPTION_MIPS32R2, OPTION_MIPS3D)
(OPTION_MIPS4, OPTION_MIPS5, OPTION_MIPS64)
(OPTION_MNO_7000_HILO_FIX, OPTION_MTUNE, OPTION_NO_CONSTRUCT_FLOATS)
(OPTION_NO_FIX_VR4122, OPTION_NO_M3900, OPTION_NO_M4010)
(OPTION_NO_M4100, OPTION_NO_M4650, OPTION_NO_MDMX, OPTION_NO_MIPS16)
(OPTION_NO_MIPS3D, OPTION_NO_RELAX_BRANCH, OPTION_RELAX_BRANCH)
(OPTION_TRAP): Redefine in terms of new defines.
(md_longopts): Reorder entries.
2003-06-04 08:38:38 +02:00
|
|
|
|
#define OPTION_EB (OPTION_MISC_BASE + 3)
|
1999-05-03 09:29:11 +02:00
|
|
|
|
{"EB", no_argument, NULL, OPTION_EB},
|
2003-06-03 Chris Demetriou <cgd@broadcom.com>
* config/tc-mips.c: (OPTION_ARCH_BASE, OPTION_ASE_BASE)
(OPTION_COMPAT_ARCH_BASE, OPTION_FIX_BASE)
(OPTION_MISC_BASE): New defines.
(OPTION_BREAK, OPTION_CONSTRUCT_FLOATS, OPTION_EB, OPTION_EL)
(OPTION_ELF_BASE, OPTION_FIX_VR4122, OPTION_FP32, OPTION_FP64)
(OPTION_GP32, OPTION_GP64, OPTION_M3900, OPTION_M4010, OPTION_M4100)
(OPTION_M4650, OPTION_M7000_HILO_FIX, OPTION_MARCH, OPTION_MDMX)
(OPTION_MEMBEDDED_PIC, OPTION_MIPS1, OPTION_MIPS16, OPTION_MIPS2)
(OPTION_MIPS3, OPTION_MIPS32, OPTION_MIPS32R2, OPTION_MIPS3D)
(OPTION_MIPS4, OPTION_MIPS5, OPTION_MIPS64)
(OPTION_MNO_7000_HILO_FIX, OPTION_MTUNE, OPTION_NO_CONSTRUCT_FLOATS)
(OPTION_NO_FIX_VR4122, OPTION_NO_M3900, OPTION_NO_M4010)
(OPTION_NO_M4100, OPTION_NO_M4650, OPTION_NO_MDMX, OPTION_NO_MIPS16)
(OPTION_NO_MIPS3D, OPTION_NO_RELAX_BRANCH, OPTION_RELAX_BRANCH)
(OPTION_TRAP): Redefine in terms of new defines.
(md_longopts): Reorder entries.
2003-06-04 08:38:38 +02:00
|
|
|
|
#define OPTION_EL (OPTION_MISC_BASE + 4)
|
1999-05-03 09:29:11 +02:00
|
|
|
|
{"EL", no_argument, NULL, OPTION_EL},
|
2003-06-03 Chris Demetriou <cgd@broadcom.com>
* config/tc-mips.c: (OPTION_ARCH_BASE, OPTION_ASE_BASE)
(OPTION_COMPAT_ARCH_BASE, OPTION_FIX_BASE)
(OPTION_MISC_BASE): New defines.
(OPTION_BREAK, OPTION_CONSTRUCT_FLOATS, OPTION_EB, OPTION_EL)
(OPTION_ELF_BASE, OPTION_FIX_VR4122, OPTION_FP32, OPTION_FP64)
(OPTION_GP32, OPTION_GP64, OPTION_M3900, OPTION_M4010, OPTION_M4100)
(OPTION_M4650, OPTION_M7000_HILO_FIX, OPTION_MARCH, OPTION_MDMX)
(OPTION_MEMBEDDED_PIC, OPTION_MIPS1, OPTION_MIPS16, OPTION_MIPS2)
(OPTION_MIPS3, OPTION_MIPS32, OPTION_MIPS32R2, OPTION_MIPS3D)
(OPTION_MIPS4, OPTION_MIPS5, OPTION_MIPS64)
(OPTION_MNO_7000_HILO_FIX, OPTION_MTUNE, OPTION_NO_CONSTRUCT_FLOATS)
(OPTION_NO_FIX_VR4122, OPTION_NO_M3900, OPTION_NO_M4010)
(OPTION_NO_M4100, OPTION_NO_M4650, OPTION_NO_MDMX, OPTION_NO_MIPS16)
(OPTION_NO_MIPS3D, OPTION_NO_RELAX_BRANCH, OPTION_RELAX_BRANCH)
(OPTION_TRAP): Redefine in terms of new defines.
(md_longopts): Reorder entries.
2003-06-04 08:38:38 +02:00
|
|
|
|
#define OPTION_FP32 (OPTION_MISC_BASE + 5)
|
2001-11-12 23:22:20 +01:00
|
|
|
|
{"mfp32", no_argument, NULL, OPTION_FP32},
|
2003-06-03 Chris Demetriou <cgd@broadcom.com>
* config/tc-mips.c: (OPTION_ARCH_BASE, OPTION_ASE_BASE)
(OPTION_COMPAT_ARCH_BASE, OPTION_FIX_BASE)
(OPTION_MISC_BASE): New defines.
(OPTION_BREAK, OPTION_CONSTRUCT_FLOATS, OPTION_EB, OPTION_EL)
(OPTION_ELF_BASE, OPTION_FIX_VR4122, OPTION_FP32, OPTION_FP64)
(OPTION_GP32, OPTION_GP64, OPTION_M3900, OPTION_M4010, OPTION_M4100)
(OPTION_M4650, OPTION_M7000_HILO_FIX, OPTION_MARCH, OPTION_MDMX)
(OPTION_MEMBEDDED_PIC, OPTION_MIPS1, OPTION_MIPS16, OPTION_MIPS2)
(OPTION_MIPS3, OPTION_MIPS32, OPTION_MIPS32R2, OPTION_MIPS3D)
(OPTION_MIPS4, OPTION_MIPS5, OPTION_MIPS64)
(OPTION_MNO_7000_HILO_FIX, OPTION_MTUNE, OPTION_NO_CONSTRUCT_FLOATS)
(OPTION_NO_FIX_VR4122, OPTION_NO_M3900, OPTION_NO_M4010)
(OPTION_NO_M4100, OPTION_NO_M4650, OPTION_NO_MDMX, OPTION_NO_MIPS16)
(OPTION_NO_MIPS3D, OPTION_NO_RELAX_BRANCH, OPTION_RELAX_BRANCH)
(OPTION_TRAP): Redefine in terms of new defines.
(md_longopts): Reorder entries.
2003-06-04 08:38:38 +02:00
|
|
|
|
#define OPTION_GP32 (OPTION_MISC_BASE + 6)
|
2000-02-22 15:43:54 +01:00
|
|
|
|
{"mgp32", no_argument, NULL, OPTION_GP32},
|
2003-06-03 Chris Demetriou <cgd@broadcom.com>
* config/tc-mips.c: (OPTION_ARCH_BASE, OPTION_ASE_BASE)
(OPTION_COMPAT_ARCH_BASE, OPTION_FIX_BASE)
(OPTION_MISC_BASE): New defines.
(OPTION_BREAK, OPTION_CONSTRUCT_FLOATS, OPTION_EB, OPTION_EL)
(OPTION_ELF_BASE, OPTION_FIX_VR4122, OPTION_FP32, OPTION_FP64)
(OPTION_GP32, OPTION_GP64, OPTION_M3900, OPTION_M4010, OPTION_M4100)
(OPTION_M4650, OPTION_M7000_HILO_FIX, OPTION_MARCH, OPTION_MDMX)
(OPTION_MEMBEDDED_PIC, OPTION_MIPS1, OPTION_MIPS16, OPTION_MIPS2)
(OPTION_MIPS3, OPTION_MIPS32, OPTION_MIPS32R2, OPTION_MIPS3D)
(OPTION_MIPS4, OPTION_MIPS5, OPTION_MIPS64)
(OPTION_MNO_7000_HILO_FIX, OPTION_MTUNE, OPTION_NO_CONSTRUCT_FLOATS)
(OPTION_NO_FIX_VR4122, OPTION_NO_M3900, OPTION_NO_M4010)
(OPTION_NO_M4100, OPTION_NO_M4650, OPTION_NO_MDMX, OPTION_NO_MIPS16)
(OPTION_NO_MIPS3D, OPTION_NO_RELAX_BRANCH, OPTION_RELAX_BRANCH)
(OPTION_TRAP): Redefine in terms of new defines.
(md_longopts): Reorder entries.
2003-06-04 08:38:38 +02:00
|
|
|
|
#define OPTION_CONSTRUCT_FLOATS (OPTION_MISC_BASE + 7)
|
2000-07-15 00:23:33 +02:00
|
|
|
|
{"construct-floats", no_argument, NULL, OPTION_CONSTRUCT_FLOATS},
|
2003-06-03 Chris Demetriou <cgd@broadcom.com>
* config/tc-mips.c: (OPTION_ARCH_BASE, OPTION_ASE_BASE)
(OPTION_COMPAT_ARCH_BASE, OPTION_FIX_BASE)
(OPTION_MISC_BASE): New defines.
(OPTION_BREAK, OPTION_CONSTRUCT_FLOATS, OPTION_EB, OPTION_EL)
(OPTION_ELF_BASE, OPTION_FIX_VR4122, OPTION_FP32, OPTION_FP64)
(OPTION_GP32, OPTION_GP64, OPTION_M3900, OPTION_M4010, OPTION_M4100)
(OPTION_M4650, OPTION_M7000_HILO_FIX, OPTION_MARCH, OPTION_MDMX)
(OPTION_MEMBEDDED_PIC, OPTION_MIPS1, OPTION_MIPS16, OPTION_MIPS2)
(OPTION_MIPS3, OPTION_MIPS32, OPTION_MIPS32R2, OPTION_MIPS3D)
(OPTION_MIPS4, OPTION_MIPS5, OPTION_MIPS64)
(OPTION_MNO_7000_HILO_FIX, OPTION_MTUNE, OPTION_NO_CONSTRUCT_FLOATS)
(OPTION_NO_FIX_VR4122, OPTION_NO_M3900, OPTION_NO_M4010)
(OPTION_NO_M4100, OPTION_NO_M4650, OPTION_NO_MDMX, OPTION_NO_MIPS16)
(OPTION_NO_MIPS3D, OPTION_NO_RELAX_BRANCH, OPTION_RELAX_BRANCH)
(OPTION_TRAP): Redefine in terms of new defines.
(md_longopts): Reorder entries.
2003-06-04 08:38:38 +02:00
|
|
|
|
#define OPTION_NO_CONSTRUCT_FLOATS (OPTION_MISC_BASE + 8)
|
2000-07-15 00:23:33 +02:00
|
|
|
|
{"no-construct-floats", no_argument, NULL, OPTION_NO_CONSTRUCT_FLOATS},
|
2003-06-03 Chris Demetriou <cgd@broadcom.com>
* config/tc-mips.c: (OPTION_ARCH_BASE, OPTION_ASE_BASE)
(OPTION_COMPAT_ARCH_BASE, OPTION_FIX_BASE)
(OPTION_MISC_BASE): New defines.
(OPTION_BREAK, OPTION_CONSTRUCT_FLOATS, OPTION_EB, OPTION_EL)
(OPTION_ELF_BASE, OPTION_FIX_VR4122, OPTION_FP32, OPTION_FP64)
(OPTION_GP32, OPTION_GP64, OPTION_M3900, OPTION_M4010, OPTION_M4100)
(OPTION_M4650, OPTION_M7000_HILO_FIX, OPTION_MARCH, OPTION_MDMX)
(OPTION_MEMBEDDED_PIC, OPTION_MIPS1, OPTION_MIPS16, OPTION_MIPS2)
(OPTION_MIPS3, OPTION_MIPS32, OPTION_MIPS32R2, OPTION_MIPS3D)
(OPTION_MIPS4, OPTION_MIPS5, OPTION_MIPS64)
(OPTION_MNO_7000_HILO_FIX, OPTION_MTUNE, OPTION_NO_CONSTRUCT_FLOATS)
(OPTION_NO_FIX_VR4122, OPTION_NO_M3900, OPTION_NO_M4010)
(OPTION_NO_M4100, OPTION_NO_M4650, OPTION_NO_MDMX, OPTION_NO_MIPS16)
(OPTION_NO_MIPS3D, OPTION_NO_RELAX_BRANCH, OPTION_RELAX_BRANCH)
(OPTION_TRAP): Redefine in terms of new defines.
(md_longopts): Reorder entries.
2003-06-04 08:38:38 +02:00
|
|
|
|
#define OPTION_FP64 (OPTION_MISC_BASE + 9)
|
[gas/]
* doc/c-mips.texi: Remove -mcpu. Document -mabi.
* configure.in (MIPS_CPU_STRING_DEFAULT): New configuration macro.
(USE_E_MIPS_ABI_O32, MIPS_DEFAULT_64BIT): New configuration macros.
* configure, config.in: Regenerate.
* config/tc-mips.c (file_mips_abi): Rename to mips_abi.
(mips_set_options): Remove "abi" field.
(mips_opts): Update accordingly. Replace all uses of mips_opts.abi
with mips_abi.
(mips_cpu): Remove.
(mips_arch_string, mips_arch_info): New vars.
(mips_tune_string, mips_tune_info): New vars.
(ABI_NEEDS_32BIT_REGS, ABI_NEEDS_64BIT_REGS): New macros.
(HAVE_32BIT_GPRS, HAVE_32BIT_FPRS): Don't check the ABI.
(mips_isa_to_str, mips_cpu_to_str): Remove.
(mips_ip): If the selected architecture is a generic ISA rather
than a processor, only mention the ISA level in error messages.
(OPTION_MCPU): Remove.
(OPTION_FP64): New.
(md_longopts): Add -mfp64, remove -mcpu.
(mips_set_option_string): New fn.
(md_parse_option): Make -mipsN update file_mips_isa rather than
mips_opts.isa. Use mips_set_option_string to set -march or -mtune.
Don't let -mgp32 and -mfp32 change the ABI.
(show): Move to end of file. Constify string argument.
(md_show_usage): Move to the end of the file. Read available
architectures from mips_cpu_info_table.
(mips_set_architecture): New fn.
(mips_after_parse_args): Rework. Remove -mcpu handling. -mipsN
is an alias for -march=mipsN. Don't change the ABI based on other
flags. Infer the register size from the ABI as well as the
architecture. Complain about more conflicting arguments.
Unify logic with GCC.
(s_mipsset): Don't change the ABI.
(mips_elf_final_processing): Check USE_E_MIPS_ABI_O32.
(mips_cpu_info_table): Remove Generic-MIPS* entries, keeping just
"mipsN"-type entries. Remove entries that vary only in the
manufacturer's prefix, or that have "000" replaced by "k".
Remove TARGET_CPU entries. Make r2000 entry use CPU_R3000.
(mips_strict_matching_cpu_name_p, mips_matching_cpu_name_p): New fns.
(mips_parse_cpu): New fn.
(mips_cpu_info_from_name, mips_cpu_info_from_cpu): Remove.
(mips_cpu_info_from_isa): Minor formatting tweak.
[gas/testsuite]
* gas/mips/mips-gp32-fp64.d,
* gas/mips/mips-gp32-fp64-pic.d: Add -mfp64.
2002-07-25 11:48:07 +02:00
|
|
|
|
{"mfp64", no_argument, NULL, OPTION_FP64},
|
2003-06-03 Chris Demetriou <cgd@broadcom.com>
* config/tc-mips.c: (OPTION_ARCH_BASE, OPTION_ASE_BASE)
(OPTION_COMPAT_ARCH_BASE, OPTION_FIX_BASE)
(OPTION_MISC_BASE): New defines.
(OPTION_BREAK, OPTION_CONSTRUCT_FLOATS, OPTION_EB, OPTION_EL)
(OPTION_ELF_BASE, OPTION_FIX_VR4122, OPTION_FP32, OPTION_FP64)
(OPTION_GP32, OPTION_GP64, OPTION_M3900, OPTION_M4010, OPTION_M4100)
(OPTION_M4650, OPTION_M7000_HILO_FIX, OPTION_MARCH, OPTION_MDMX)
(OPTION_MEMBEDDED_PIC, OPTION_MIPS1, OPTION_MIPS16, OPTION_MIPS2)
(OPTION_MIPS3, OPTION_MIPS32, OPTION_MIPS32R2, OPTION_MIPS3D)
(OPTION_MIPS4, OPTION_MIPS5, OPTION_MIPS64)
(OPTION_MNO_7000_HILO_FIX, OPTION_MTUNE, OPTION_NO_CONSTRUCT_FLOATS)
(OPTION_NO_FIX_VR4122, OPTION_NO_M3900, OPTION_NO_M4010)
(OPTION_NO_M4100, OPTION_NO_M4650, OPTION_NO_MDMX, OPTION_NO_MIPS16)
(OPTION_NO_MIPS3D, OPTION_NO_RELAX_BRANCH, OPTION_RELAX_BRANCH)
(OPTION_TRAP): Redefine in terms of new defines.
(md_longopts): Reorder entries.
2003-06-04 08:38:38 +02:00
|
|
|
|
#define OPTION_GP64 (OPTION_MISC_BASE + 10)
|
2001-11-12 23:22:20 +01:00
|
|
|
|
{"mgp64", no_argument, NULL, OPTION_GP64},
|
2003-06-03 Chris Demetriou <cgd@broadcom.com>
* config/tc-mips.c: (OPTION_ARCH_BASE, OPTION_ASE_BASE)
(OPTION_COMPAT_ARCH_BASE, OPTION_FIX_BASE)
(OPTION_MISC_BASE): New defines.
(OPTION_BREAK, OPTION_CONSTRUCT_FLOATS, OPTION_EB, OPTION_EL)
(OPTION_ELF_BASE, OPTION_FIX_VR4122, OPTION_FP32, OPTION_FP64)
(OPTION_GP32, OPTION_GP64, OPTION_M3900, OPTION_M4010, OPTION_M4100)
(OPTION_M4650, OPTION_M7000_HILO_FIX, OPTION_MARCH, OPTION_MDMX)
(OPTION_MEMBEDDED_PIC, OPTION_MIPS1, OPTION_MIPS16, OPTION_MIPS2)
(OPTION_MIPS3, OPTION_MIPS32, OPTION_MIPS32R2, OPTION_MIPS3D)
(OPTION_MIPS4, OPTION_MIPS5, OPTION_MIPS64)
(OPTION_MNO_7000_HILO_FIX, OPTION_MTUNE, OPTION_NO_CONSTRUCT_FLOATS)
(OPTION_NO_FIX_VR4122, OPTION_NO_M3900, OPTION_NO_M4010)
(OPTION_NO_M4100, OPTION_NO_M4650, OPTION_NO_MDMX, OPTION_NO_MIPS16)
(OPTION_NO_MIPS3D, OPTION_NO_RELAX_BRANCH, OPTION_RELAX_BRANCH)
(OPTION_TRAP): Redefine in terms of new defines.
(md_longopts): Reorder entries.
2003-06-04 08:38:38 +02:00
|
|
|
|
#define OPTION_RELAX_BRANCH (OPTION_MISC_BASE + 11)
|
|
|
|
|
#define OPTION_NO_RELAX_BRANCH (OPTION_MISC_BASE + 12)
|
2002-10-12 07:23:33 +02:00
|
|
|
|
{"relax-branch", no_argument, NULL, OPTION_RELAX_BRANCH},
|
|
|
|
|
{"no-relax-branch", no_argument, NULL, OPTION_NO_RELAX_BRANCH},
|
2003-06-03 Chris Demetriou <cgd@broadcom.com>
* config/tc-mips.c: (OPTION_ARCH_BASE, OPTION_ASE_BASE)
(OPTION_COMPAT_ARCH_BASE, OPTION_FIX_BASE)
(OPTION_MISC_BASE): New defines.
(OPTION_BREAK, OPTION_CONSTRUCT_FLOATS, OPTION_EB, OPTION_EL)
(OPTION_ELF_BASE, OPTION_FIX_VR4122, OPTION_FP32, OPTION_FP64)
(OPTION_GP32, OPTION_GP64, OPTION_M3900, OPTION_M4010, OPTION_M4100)
(OPTION_M4650, OPTION_M7000_HILO_FIX, OPTION_MARCH, OPTION_MDMX)
(OPTION_MEMBEDDED_PIC, OPTION_MIPS1, OPTION_MIPS16, OPTION_MIPS2)
(OPTION_MIPS3, OPTION_MIPS32, OPTION_MIPS32R2, OPTION_MIPS3D)
(OPTION_MIPS4, OPTION_MIPS5, OPTION_MIPS64)
(OPTION_MNO_7000_HILO_FIX, OPTION_MTUNE, OPTION_NO_CONSTRUCT_FLOATS)
(OPTION_NO_FIX_VR4122, OPTION_NO_M3900, OPTION_NO_M4010)
(OPTION_NO_M4100, OPTION_NO_M4650, OPTION_NO_MDMX, OPTION_NO_MIPS16)
(OPTION_NO_MIPS3D, OPTION_NO_RELAX_BRANCH, OPTION_RELAX_BRANCH)
(OPTION_TRAP): Redefine in terms of new defines.
(md_longopts): Reorder entries.
2003-06-04 08:38:38 +02:00
|
|
|
|
|
|
|
|
|
/* ELF-specific options. */
|
2000-09-14 03:47:38 +02:00
|
|
|
|
#ifdef OBJ_ELF
|
2003-06-03 Chris Demetriou <cgd@broadcom.com>
* config/tc-mips.c: (OPTION_ARCH_BASE, OPTION_ASE_BASE)
(OPTION_COMPAT_ARCH_BASE, OPTION_FIX_BASE)
(OPTION_MISC_BASE): New defines.
(OPTION_BREAK, OPTION_CONSTRUCT_FLOATS, OPTION_EB, OPTION_EL)
(OPTION_ELF_BASE, OPTION_FIX_VR4122, OPTION_FP32, OPTION_FP64)
(OPTION_GP32, OPTION_GP64, OPTION_M3900, OPTION_M4010, OPTION_M4100)
(OPTION_M4650, OPTION_M7000_HILO_FIX, OPTION_MARCH, OPTION_MDMX)
(OPTION_MEMBEDDED_PIC, OPTION_MIPS1, OPTION_MIPS16, OPTION_MIPS2)
(OPTION_MIPS3, OPTION_MIPS32, OPTION_MIPS32R2, OPTION_MIPS3D)
(OPTION_MIPS4, OPTION_MIPS5, OPTION_MIPS64)
(OPTION_MNO_7000_HILO_FIX, OPTION_MTUNE, OPTION_NO_CONSTRUCT_FLOATS)
(OPTION_NO_FIX_VR4122, OPTION_NO_M3900, OPTION_NO_M4010)
(OPTION_NO_M4100, OPTION_NO_M4650, OPTION_NO_MDMX, OPTION_NO_MIPS16)
(OPTION_NO_MIPS3D, OPTION_NO_RELAX_BRANCH, OPTION_RELAX_BRANCH)
(OPTION_TRAP): Redefine in terms of new defines.
(md_longopts): Reorder entries.
2003-06-04 08:38:38 +02:00
|
|
|
|
#define OPTION_ELF_BASE (OPTION_MISC_BASE + 13)
|
2000-09-14 03:47:38 +02:00
|
|
|
|
#define OPTION_CALL_SHARED (OPTION_ELF_BASE + 0)
|
|
|
|
|
{"KPIC", no_argument, NULL, OPTION_CALL_SHARED},
|
|
|
|
|
{"call_shared", no_argument, NULL, OPTION_CALL_SHARED},
|
2001-11-12 23:22:20 +01:00
|
|
|
|
#define OPTION_NON_SHARED (OPTION_ELF_BASE + 1)
|
2000-09-14 03:47:38 +02:00
|
|
|
|
{"non_shared", no_argument, NULL, OPTION_NON_SHARED},
|
2001-11-12 23:22:20 +01:00
|
|
|
|
#define OPTION_XGOT (OPTION_ELF_BASE + 2)
|
2000-09-14 03:47:38 +02:00
|
|
|
|
{"xgot", no_argument, NULL, OPTION_XGOT},
|
2001-11-12 23:22:20 +01:00
|
|
|
|
#define OPTION_MABI (OPTION_ELF_BASE + 3)
|
|
|
|
|
{"mabi", required_argument, NULL, OPTION_MABI},
|
|
|
|
|
#define OPTION_32 (OPTION_ELF_BASE + 4)
|
2000-09-14 03:47:38 +02:00
|
|
|
|
{"32", no_argument, NULL, OPTION_32},
|
2001-11-12 23:22:20 +01:00
|
|
|
|
#define OPTION_N32 (OPTION_ELF_BASE + 5)
|
2001-10-03 22:30:15 +02:00
|
|
|
|
{"n32", no_argument, NULL, OPTION_N32},
|
2001-11-12 23:22:20 +01:00
|
|
|
|
#define OPTION_64 (OPTION_ELF_BASE + 6)
|
2000-09-14 03:47:38 +02:00
|
|
|
|
{"64", no_argument, NULL, OPTION_64},
|
2002-06-14 16:08:54 +02:00
|
|
|
|
#define OPTION_MDEBUG (OPTION_ELF_BASE + 7)
|
|
|
|
|
{"mdebug", no_argument, NULL, OPTION_MDEBUG},
|
|
|
|
|
#define OPTION_NO_MDEBUG (OPTION_ELF_BASE + 8)
|
|
|
|
|
{"no-mdebug", no_argument, NULL, OPTION_NO_MDEBUG},
|
2003-07-28 22:06:27 +02:00
|
|
|
|
#define OPTION_PDR (OPTION_ELF_BASE + 9)
|
|
|
|
|
{"mpdr", no_argument, NULL, OPTION_PDR},
|
|
|
|
|
#define OPTION_NO_PDR (OPTION_ELF_BASE + 10)
|
|
|
|
|
{"mno-pdr", no_argument, NULL, OPTION_NO_PDR},
|
2001-11-12 23:22:20 +01:00
|
|
|
|
#endif /* OBJ_ELF */
|
2003-06-03 Chris Demetriou <cgd@broadcom.com>
* config/tc-mips.c: (OPTION_ARCH_BASE, OPTION_ASE_BASE)
(OPTION_COMPAT_ARCH_BASE, OPTION_FIX_BASE)
(OPTION_MISC_BASE): New defines.
(OPTION_BREAK, OPTION_CONSTRUCT_FLOATS, OPTION_EB, OPTION_EL)
(OPTION_ELF_BASE, OPTION_FIX_VR4122, OPTION_FP32, OPTION_FP64)
(OPTION_GP32, OPTION_GP64, OPTION_M3900, OPTION_M4010, OPTION_M4100)
(OPTION_M4650, OPTION_M7000_HILO_FIX, OPTION_MARCH, OPTION_MDMX)
(OPTION_MEMBEDDED_PIC, OPTION_MIPS1, OPTION_MIPS16, OPTION_MIPS2)
(OPTION_MIPS3, OPTION_MIPS32, OPTION_MIPS32R2, OPTION_MIPS3D)
(OPTION_MIPS4, OPTION_MIPS5, OPTION_MIPS64)
(OPTION_MNO_7000_HILO_FIX, OPTION_MTUNE, OPTION_NO_CONSTRUCT_FLOATS)
(OPTION_NO_FIX_VR4122, OPTION_NO_M3900, OPTION_NO_M4010)
(OPTION_NO_M4100, OPTION_NO_M4650, OPTION_NO_MDMX, OPTION_NO_MIPS16)
(OPTION_NO_MIPS3D, OPTION_NO_RELAX_BRANCH, OPTION_RELAX_BRANCH)
(OPTION_TRAP): Redefine in terms of new defines.
(md_longopts): Reorder entries.
2003-06-04 08:38:38 +02:00
|
|
|
|
|
1999-05-03 09:29:11 +02:00
|
|
|
|
{NULL, no_argument, NULL, 0}
|
|
|
|
|
};
|
2000-09-14 03:47:38 +02:00
|
|
|
|
size_t md_longopts_size = sizeof (md_longopts);
|
1999-05-03 09:29:11 +02:00
|
|
|
|
|
[gas/]
* doc/c-mips.texi: Remove -mcpu. Document -mabi.
* configure.in (MIPS_CPU_STRING_DEFAULT): New configuration macro.
(USE_E_MIPS_ABI_O32, MIPS_DEFAULT_64BIT): New configuration macros.
* configure, config.in: Regenerate.
* config/tc-mips.c (file_mips_abi): Rename to mips_abi.
(mips_set_options): Remove "abi" field.
(mips_opts): Update accordingly. Replace all uses of mips_opts.abi
with mips_abi.
(mips_cpu): Remove.
(mips_arch_string, mips_arch_info): New vars.
(mips_tune_string, mips_tune_info): New vars.
(ABI_NEEDS_32BIT_REGS, ABI_NEEDS_64BIT_REGS): New macros.
(HAVE_32BIT_GPRS, HAVE_32BIT_FPRS): Don't check the ABI.
(mips_isa_to_str, mips_cpu_to_str): Remove.
(mips_ip): If the selected architecture is a generic ISA rather
than a processor, only mention the ISA level in error messages.
(OPTION_MCPU): Remove.
(OPTION_FP64): New.
(md_longopts): Add -mfp64, remove -mcpu.
(mips_set_option_string): New fn.
(md_parse_option): Make -mipsN update file_mips_isa rather than
mips_opts.isa. Use mips_set_option_string to set -march or -mtune.
Don't let -mgp32 and -mfp32 change the ABI.
(show): Move to end of file. Constify string argument.
(md_show_usage): Move to the end of the file. Read available
architectures from mips_cpu_info_table.
(mips_set_architecture): New fn.
(mips_after_parse_args): Rework. Remove -mcpu handling. -mipsN
is an alias for -march=mipsN. Don't change the ABI based on other
flags. Infer the register size from the ABI as well as the
architecture. Complain about more conflicting arguments.
Unify logic with GCC.
(s_mipsset): Don't change the ABI.
(mips_elf_final_processing): Check USE_E_MIPS_ABI_O32.
(mips_cpu_info_table): Remove Generic-MIPS* entries, keeping just
"mipsN"-type entries. Remove entries that vary only in the
manufacturer's prefix, or that have "000" replaced by "k".
Remove TARGET_CPU entries. Make r2000 entry use CPU_R3000.
(mips_strict_matching_cpu_name_p, mips_matching_cpu_name_p): New fns.
(mips_parse_cpu): New fn.
(mips_cpu_info_from_name, mips_cpu_info_from_cpu): Remove.
(mips_cpu_info_from_isa): Minor formatting tweak.
[gas/testsuite]
* gas/mips/mips-gp32-fp64.d,
* gas/mips/mips-gp32-fp64-pic.d: Add -mfp64.
2002-07-25 11:48:07 +02:00
|
|
|
|
/* Set STRING_PTR (either &mips_arch_string or &mips_tune_string) to
|
|
|
|
|
NEW_VALUE. Warn if another value was already specified. Note:
|
|
|
|
|
we have to defer parsing the -march and -mtune arguments in order
|
|
|
|
|
to handle 'from-abi' correctly, since the ABI might be specified
|
|
|
|
|
in a later argument. */
|
|
|
|
|
|
|
|
|
|
static void
|
2003-06-30 14:44:25 +02:00
|
|
|
|
mips_set_option_string (const char **string_ptr, const char *new_value)
|
[gas/]
* doc/c-mips.texi: Remove -mcpu. Document -mabi.
* configure.in (MIPS_CPU_STRING_DEFAULT): New configuration macro.
(USE_E_MIPS_ABI_O32, MIPS_DEFAULT_64BIT): New configuration macros.
* configure, config.in: Regenerate.
* config/tc-mips.c (file_mips_abi): Rename to mips_abi.
(mips_set_options): Remove "abi" field.
(mips_opts): Update accordingly. Replace all uses of mips_opts.abi
with mips_abi.
(mips_cpu): Remove.
(mips_arch_string, mips_arch_info): New vars.
(mips_tune_string, mips_tune_info): New vars.
(ABI_NEEDS_32BIT_REGS, ABI_NEEDS_64BIT_REGS): New macros.
(HAVE_32BIT_GPRS, HAVE_32BIT_FPRS): Don't check the ABI.
(mips_isa_to_str, mips_cpu_to_str): Remove.
(mips_ip): If the selected architecture is a generic ISA rather
than a processor, only mention the ISA level in error messages.
(OPTION_MCPU): Remove.
(OPTION_FP64): New.
(md_longopts): Add -mfp64, remove -mcpu.
(mips_set_option_string): New fn.
(md_parse_option): Make -mipsN update file_mips_isa rather than
mips_opts.isa. Use mips_set_option_string to set -march or -mtune.
Don't let -mgp32 and -mfp32 change the ABI.
(show): Move to end of file. Constify string argument.
(md_show_usage): Move to the end of the file. Read available
architectures from mips_cpu_info_table.
(mips_set_architecture): New fn.
(mips_after_parse_args): Rework. Remove -mcpu handling. -mipsN
is an alias for -march=mipsN. Don't change the ABI based on other
flags. Infer the register size from the ABI as well as the
architecture. Complain about more conflicting arguments.
Unify logic with GCC.
(s_mipsset): Don't change the ABI.
(mips_elf_final_processing): Check USE_E_MIPS_ABI_O32.
(mips_cpu_info_table): Remove Generic-MIPS* entries, keeping just
"mipsN"-type entries. Remove entries that vary only in the
manufacturer's prefix, or that have "000" replaced by "k".
Remove TARGET_CPU entries. Make r2000 entry use CPU_R3000.
(mips_strict_matching_cpu_name_p, mips_matching_cpu_name_p): New fns.
(mips_parse_cpu): New fn.
(mips_cpu_info_from_name, mips_cpu_info_from_cpu): Remove.
(mips_cpu_info_from_isa): Minor formatting tweak.
[gas/testsuite]
* gas/mips/mips-gp32-fp64.d,
* gas/mips/mips-gp32-fp64-pic.d: Add -mfp64.
2002-07-25 11:48:07 +02:00
|
|
|
|
{
|
|
|
|
|
if (*string_ptr != 0 && strcasecmp (*string_ptr, new_value) != 0)
|
|
|
|
|
as_warn (_("A different %s was already specified, is now %s"),
|
|
|
|
|
string_ptr == &mips_arch_string ? "-march" : "-mtune",
|
|
|
|
|
new_value);
|
|
|
|
|
|
|
|
|
|
*string_ptr = new_value;
|
|
|
|
|
}
|
|
|
|
|
|
1999-05-03 09:29:11 +02:00
|
|
|
|
int
|
2003-06-30 14:44:25 +02:00
|
|
|
|
md_parse_option (int c, char *arg)
|
1999-05-03 09:29:11 +02:00
|
|
|
|
{
|
|
|
|
|
switch (c)
|
|
|
|
|
{
|
2000-07-15 00:23:33 +02:00
|
|
|
|
case OPTION_CONSTRUCT_FLOATS:
|
|
|
|
|
mips_disable_float_construction = 0;
|
|
|
|
|
break;
|
2000-09-07 14:45:56 +02:00
|
|
|
|
|
2000-07-15 00:23:33 +02:00
|
|
|
|
case OPTION_NO_CONSTRUCT_FLOATS:
|
|
|
|
|
mips_disable_float_construction = 1;
|
|
|
|
|
break;
|
2000-09-07 14:45:56 +02:00
|
|
|
|
|
1999-05-03 09:29:11 +02:00
|
|
|
|
case OPTION_TRAP:
|
|
|
|
|
mips_trap = 1;
|
|
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
case OPTION_BREAK:
|
|
|
|
|
mips_trap = 0;
|
|
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
case OPTION_EB:
|
|
|
|
|
target_big_endian = 1;
|
|
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
case OPTION_EL:
|
|
|
|
|
target_big_endian = 0;
|
|
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
case 'O':
|
|
|
|
|
if (arg && arg[1] == '0')
|
|
|
|
|
mips_optimize = 1;
|
|
|
|
|
else
|
|
|
|
|
mips_optimize = 2;
|
|
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
case 'g':
|
|
|
|
|
if (arg == NULL)
|
|
|
|
|
mips_debug = 2;
|
|
|
|
|
else
|
|
|
|
|
mips_debug = atoi (arg);
|
|
|
|
|
/* When the MIPS assembler sees -g or -g2, it does not do
|
|
|
|
|
optimizations which limit full symbolic debugging. We take
|
|
|
|
|
that to be equivalent to -O0. */
|
|
|
|
|
if (mips_debug == 2)
|
|
|
|
|
mips_optimize = 1;
|
|
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
case OPTION_MIPS1:
|
[gas/]
* doc/c-mips.texi: Remove -mcpu. Document -mabi.
* configure.in (MIPS_CPU_STRING_DEFAULT): New configuration macro.
(USE_E_MIPS_ABI_O32, MIPS_DEFAULT_64BIT): New configuration macros.
* configure, config.in: Regenerate.
* config/tc-mips.c (file_mips_abi): Rename to mips_abi.
(mips_set_options): Remove "abi" field.
(mips_opts): Update accordingly. Replace all uses of mips_opts.abi
with mips_abi.
(mips_cpu): Remove.
(mips_arch_string, mips_arch_info): New vars.
(mips_tune_string, mips_tune_info): New vars.
(ABI_NEEDS_32BIT_REGS, ABI_NEEDS_64BIT_REGS): New macros.
(HAVE_32BIT_GPRS, HAVE_32BIT_FPRS): Don't check the ABI.
(mips_isa_to_str, mips_cpu_to_str): Remove.
(mips_ip): If the selected architecture is a generic ISA rather
than a processor, only mention the ISA level in error messages.
(OPTION_MCPU): Remove.
(OPTION_FP64): New.
(md_longopts): Add -mfp64, remove -mcpu.
(mips_set_option_string): New fn.
(md_parse_option): Make -mipsN update file_mips_isa rather than
mips_opts.isa. Use mips_set_option_string to set -march or -mtune.
Don't let -mgp32 and -mfp32 change the ABI.
(show): Move to end of file. Constify string argument.
(md_show_usage): Move to the end of the file. Read available
architectures from mips_cpu_info_table.
(mips_set_architecture): New fn.
(mips_after_parse_args): Rework. Remove -mcpu handling. -mipsN
is an alias for -march=mipsN. Don't change the ABI based on other
flags. Infer the register size from the ABI as well as the
architecture. Complain about more conflicting arguments.
Unify logic with GCC.
(s_mipsset): Don't change the ABI.
(mips_elf_final_processing): Check USE_E_MIPS_ABI_O32.
(mips_cpu_info_table): Remove Generic-MIPS* entries, keeping just
"mipsN"-type entries. Remove entries that vary only in the
manufacturer's prefix, or that have "000" replaced by "k".
Remove TARGET_CPU entries. Make r2000 entry use CPU_R3000.
(mips_strict_matching_cpu_name_p, mips_matching_cpu_name_p): New fns.
(mips_parse_cpu): New fn.
(mips_cpu_info_from_name, mips_cpu_info_from_cpu): Remove.
(mips_cpu_info_from_isa): Minor formatting tweak.
[gas/testsuite]
* gas/mips/mips-gp32-fp64.d,
* gas/mips/mips-gp32-fp64-pic.d: Add -mfp64.
2002-07-25 11:48:07 +02:00
|
|
|
|
file_mips_isa = ISA_MIPS1;
|
1999-05-03 09:29:11 +02:00
|
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
case OPTION_MIPS2:
|
[gas/]
* doc/c-mips.texi: Remove -mcpu. Document -mabi.
* configure.in (MIPS_CPU_STRING_DEFAULT): New configuration macro.
(USE_E_MIPS_ABI_O32, MIPS_DEFAULT_64BIT): New configuration macros.
* configure, config.in: Regenerate.
* config/tc-mips.c (file_mips_abi): Rename to mips_abi.
(mips_set_options): Remove "abi" field.
(mips_opts): Update accordingly. Replace all uses of mips_opts.abi
with mips_abi.
(mips_cpu): Remove.
(mips_arch_string, mips_arch_info): New vars.
(mips_tune_string, mips_tune_info): New vars.
(ABI_NEEDS_32BIT_REGS, ABI_NEEDS_64BIT_REGS): New macros.
(HAVE_32BIT_GPRS, HAVE_32BIT_FPRS): Don't check the ABI.
(mips_isa_to_str, mips_cpu_to_str): Remove.
(mips_ip): If the selected architecture is a generic ISA rather
than a processor, only mention the ISA level in error messages.
(OPTION_MCPU): Remove.
(OPTION_FP64): New.
(md_longopts): Add -mfp64, remove -mcpu.
(mips_set_option_string): New fn.
(md_parse_option): Make -mipsN update file_mips_isa rather than
mips_opts.isa. Use mips_set_option_string to set -march or -mtune.
Don't let -mgp32 and -mfp32 change the ABI.
(show): Move to end of file. Constify string argument.
(md_show_usage): Move to the end of the file. Read available
architectures from mips_cpu_info_table.
(mips_set_architecture): New fn.
(mips_after_parse_args): Rework. Remove -mcpu handling. -mipsN
is an alias for -march=mipsN. Don't change the ABI based on other
flags. Infer the register size from the ABI as well as the
architecture. Complain about more conflicting arguments.
Unify logic with GCC.
(s_mipsset): Don't change the ABI.
(mips_elf_final_processing): Check USE_E_MIPS_ABI_O32.
(mips_cpu_info_table): Remove Generic-MIPS* entries, keeping just
"mipsN"-type entries. Remove entries that vary only in the
manufacturer's prefix, or that have "000" replaced by "k".
Remove TARGET_CPU entries. Make r2000 entry use CPU_R3000.
(mips_strict_matching_cpu_name_p, mips_matching_cpu_name_p): New fns.
(mips_parse_cpu): New fn.
(mips_cpu_info_from_name, mips_cpu_info_from_cpu): Remove.
(mips_cpu_info_from_isa): Minor formatting tweak.
[gas/testsuite]
* gas/mips/mips-gp32-fp64.d,
* gas/mips/mips-gp32-fp64-pic.d: Add -mfp64.
2002-07-25 11:48:07 +02:00
|
|
|
|
file_mips_isa = ISA_MIPS2;
|
1999-05-03 09:29:11 +02:00
|
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
case OPTION_MIPS3:
|
[gas/]
* doc/c-mips.texi: Remove -mcpu. Document -mabi.
* configure.in (MIPS_CPU_STRING_DEFAULT): New configuration macro.
(USE_E_MIPS_ABI_O32, MIPS_DEFAULT_64BIT): New configuration macros.
* configure, config.in: Regenerate.
* config/tc-mips.c (file_mips_abi): Rename to mips_abi.
(mips_set_options): Remove "abi" field.
(mips_opts): Update accordingly. Replace all uses of mips_opts.abi
with mips_abi.
(mips_cpu): Remove.
(mips_arch_string, mips_arch_info): New vars.
(mips_tune_string, mips_tune_info): New vars.
(ABI_NEEDS_32BIT_REGS, ABI_NEEDS_64BIT_REGS): New macros.
(HAVE_32BIT_GPRS, HAVE_32BIT_FPRS): Don't check the ABI.
(mips_isa_to_str, mips_cpu_to_str): Remove.
(mips_ip): If the selected architecture is a generic ISA rather
than a processor, only mention the ISA level in error messages.
(OPTION_MCPU): Remove.
(OPTION_FP64): New.
(md_longopts): Add -mfp64, remove -mcpu.
(mips_set_option_string): New fn.
(md_parse_option): Make -mipsN update file_mips_isa rather than
mips_opts.isa. Use mips_set_option_string to set -march or -mtune.
Don't let -mgp32 and -mfp32 change the ABI.
(show): Move to end of file. Constify string argument.
(md_show_usage): Move to the end of the file. Read available
architectures from mips_cpu_info_table.
(mips_set_architecture): New fn.
(mips_after_parse_args): Rework. Remove -mcpu handling. -mipsN
is an alias for -march=mipsN. Don't change the ABI based on other
flags. Infer the register size from the ABI as well as the
architecture. Complain about more conflicting arguments.
Unify logic with GCC.
(s_mipsset): Don't change the ABI.
(mips_elf_final_processing): Check USE_E_MIPS_ABI_O32.
(mips_cpu_info_table): Remove Generic-MIPS* entries, keeping just
"mipsN"-type entries. Remove entries that vary only in the
manufacturer's prefix, or that have "000" replaced by "k".
Remove TARGET_CPU entries. Make r2000 entry use CPU_R3000.
(mips_strict_matching_cpu_name_p, mips_matching_cpu_name_p): New fns.
(mips_parse_cpu): New fn.
(mips_cpu_info_from_name, mips_cpu_info_from_cpu): Remove.
(mips_cpu_info_from_isa): Minor formatting tweak.
[gas/testsuite]
* gas/mips/mips-gp32-fp64.d,
* gas/mips/mips-gp32-fp64-pic.d: Add -mfp64.
2002-07-25 11:48:07 +02:00
|
|
|
|
file_mips_isa = ISA_MIPS3;
|
1999-05-03 09:29:11 +02:00
|
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
case OPTION_MIPS4:
|
[gas/]
* doc/c-mips.texi: Remove -mcpu. Document -mabi.
* configure.in (MIPS_CPU_STRING_DEFAULT): New configuration macro.
(USE_E_MIPS_ABI_O32, MIPS_DEFAULT_64BIT): New configuration macros.
* configure, config.in: Regenerate.
* config/tc-mips.c (file_mips_abi): Rename to mips_abi.
(mips_set_options): Remove "abi" field.
(mips_opts): Update accordingly. Replace all uses of mips_opts.abi
with mips_abi.
(mips_cpu): Remove.
(mips_arch_string, mips_arch_info): New vars.
(mips_tune_string, mips_tune_info): New vars.
(ABI_NEEDS_32BIT_REGS, ABI_NEEDS_64BIT_REGS): New macros.
(HAVE_32BIT_GPRS, HAVE_32BIT_FPRS): Don't check the ABI.
(mips_isa_to_str, mips_cpu_to_str): Remove.
(mips_ip): If the selected architecture is a generic ISA rather
than a processor, only mention the ISA level in error messages.
(OPTION_MCPU): Remove.
(OPTION_FP64): New.
(md_longopts): Add -mfp64, remove -mcpu.
(mips_set_option_string): New fn.
(md_parse_option): Make -mipsN update file_mips_isa rather than
mips_opts.isa. Use mips_set_option_string to set -march or -mtune.
Don't let -mgp32 and -mfp32 change the ABI.
(show): Move to end of file. Constify string argument.
(md_show_usage): Move to the end of the file. Read available
architectures from mips_cpu_info_table.
(mips_set_architecture): New fn.
(mips_after_parse_args): Rework. Remove -mcpu handling. -mipsN
is an alias for -march=mipsN. Don't change the ABI based on other
flags. Infer the register size from the ABI as well as the
architecture. Complain about more conflicting arguments.
Unify logic with GCC.
(s_mipsset): Don't change the ABI.
(mips_elf_final_processing): Check USE_E_MIPS_ABI_O32.
(mips_cpu_info_table): Remove Generic-MIPS* entries, keeping just
"mipsN"-type entries. Remove entries that vary only in the
manufacturer's prefix, or that have "000" replaced by "k".
Remove TARGET_CPU entries. Make r2000 entry use CPU_R3000.
(mips_strict_matching_cpu_name_p, mips_matching_cpu_name_p): New fns.
(mips_parse_cpu): New fn.
(mips_cpu_info_from_name, mips_cpu_info_from_cpu): Remove.
(mips_cpu_info_from_isa): Minor formatting tweak.
[gas/testsuite]
* gas/mips/mips-gp32-fp64.d,
* gas/mips/mips-gp32-fp64-pic.d: Add -mfp64.
2002-07-25 11:48:07 +02:00
|
|
|
|
file_mips_isa = ISA_MIPS4;
|
2000-12-01 22:35:38 +01:00
|
|
|
|
break;
|
|
|
|
|
|
2000-12-02 01:55:22 +01:00
|
|
|
|
case OPTION_MIPS5:
|
[gas/]
* doc/c-mips.texi: Remove -mcpu. Document -mabi.
* configure.in (MIPS_CPU_STRING_DEFAULT): New configuration macro.
(USE_E_MIPS_ABI_O32, MIPS_DEFAULT_64BIT): New configuration macros.
* configure, config.in: Regenerate.
* config/tc-mips.c (file_mips_abi): Rename to mips_abi.
(mips_set_options): Remove "abi" field.
(mips_opts): Update accordingly. Replace all uses of mips_opts.abi
with mips_abi.
(mips_cpu): Remove.
(mips_arch_string, mips_arch_info): New vars.
(mips_tune_string, mips_tune_info): New vars.
(ABI_NEEDS_32BIT_REGS, ABI_NEEDS_64BIT_REGS): New macros.
(HAVE_32BIT_GPRS, HAVE_32BIT_FPRS): Don't check the ABI.
(mips_isa_to_str, mips_cpu_to_str): Remove.
(mips_ip): If the selected architecture is a generic ISA rather
than a processor, only mention the ISA level in error messages.
(OPTION_MCPU): Remove.
(OPTION_FP64): New.
(md_longopts): Add -mfp64, remove -mcpu.
(mips_set_option_string): New fn.
(md_parse_option): Make -mipsN update file_mips_isa rather than
mips_opts.isa. Use mips_set_option_string to set -march or -mtune.
Don't let -mgp32 and -mfp32 change the ABI.
(show): Move to end of file. Constify string argument.
(md_show_usage): Move to the end of the file. Read available
architectures from mips_cpu_info_table.
(mips_set_architecture): New fn.
(mips_after_parse_args): Rework. Remove -mcpu handling. -mipsN
is an alias for -march=mipsN. Don't change the ABI based on other
flags. Infer the register size from the ABI as well as the
architecture. Complain about more conflicting arguments.
Unify logic with GCC.
(s_mipsset): Don't change the ABI.
(mips_elf_final_processing): Check USE_E_MIPS_ABI_O32.
(mips_cpu_info_table): Remove Generic-MIPS* entries, keeping just
"mipsN"-type entries. Remove entries that vary only in the
manufacturer's prefix, or that have "000" replaced by "k".
Remove TARGET_CPU entries. Make r2000 entry use CPU_R3000.
(mips_strict_matching_cpu_name_p, mips_matching_cpu_name_p): New fns.
(mips_parse_cpu): New fn.
(mips_cpu_info_from_name, mips_cpu_info_from_cpu): Remove.
(mips_cpu_info_from_isa): Minor formatting tweak.
[gas/testsuite]
* gas/mips/mips-gp32-fp64.d,
* gas/mips/mips-gp32-fp64-pic.d: Add -mfp64.
2002-07-25 11:48:07 +02:00
|
|
|
|
file_mips_isa = ISA_MIPS5;
|
2000-12-02 01:55:22 +01:00
|
|
|
|
break;
|
|
|
|
|
|
2000-12-01 22:35:38 +01:00
|
|
|
|
case OPTION_MIPS32:
|
[gas/]
* doc/c-mips.texi: Remove -mcpu. Document -mabi.
* configure.in (MIPS_CPU_STRING_DEFAULT): New configuration macro.
(USE_E_MIPS_ABI_O32, MIPS_DEFAULT_64BIT): New configuration macros.
* configure, config.in: Regenerate.
* config/tc-mips.c (file_mips_abi): Rename to mips_abi.
(mips_set_options): Remove "abi" field.
(mips_opts): Update accordingly. Replace all uses of mips_opts.abi
with mips_abi.
(mips_cpu): Remove.
(mips_arch_string, mips_arch_info): New vars.
(mips_tune_string, mips_tune_info): New vars.
(ABI_NEEDS_32BIT_REGS, ABI_NEEDS_64BIT_REGS): New macros.
(HAVE_32BIT_GPRS, HAVE_32BIT_FPRS): Don't check the ABI.
(mips_isa_to_str, mips_cpu_to_str): Remove.
(mips_ip): If the selected architecture is a generic ISA rather
than a processor, only mention the ISA level in error messages.
(OPTION_MCPU): Remove.
(OPTION_FP64): New.
(md_longopts): Add -mfp64, remove -mcpu.
(mips_set_option_string): New fn.
(md_parse_option): Make -mipsN update file_mips_isa rather than
mips_opts.isa. Use mips_set_option_string to set -march or -mtune.
Don't let -mgp32 and -mfp32 change the ABI.
(show): Move to end of file. Constify string argument.
(md_show_usage): Move to the end of the file. Read available
architectures from mips_cpu_info_table.
(mips_set_architecture): New fn.
(mips_after_parse_args): Rework. Remove -mcpu handling. -mipsN
is an alias for -march=mipsN. Don't change the ABI based on other
flags. Infer the register size from the ABI as well as the
architecture. Complain about more conflicting arguments.
Unify logic with GCC.
(s_mipsset): Don't change the ABI.
(mips_elf_final_processing): Check USE_E_MIPS_ABI_O32.
(mips_cpu_info_table): Remove Generic-MIPS* entries, keeping just
"mipsN"-type entries. Remove entries that vary only in the
manufacturer's prefix, or that have "000" replaced by "k".
Remove TARGET_CPU entries. Make r2000 entry use CPU_R3000.
(mips_strict_matching_cpu_name_p, mips_matching_cpu_name_p): New fns.
(mips_parse_cpu): New fn.
(mips_cpu_info_from_name, mips_cpu_info_from_cpu): Remove.
(mips_cpu_info_from_isa): Minor formatting tweak.
[gas/testsuite]
* gas/mips/mips-gp32-fp64.d,
* gas/mips/mips-gp32-fp64-pic.d: Add -mfp64.
2002-07-25 11:48:07 +02:00
|
|
|
|
file_mips_isa = ISA_MIPS32;
|
1999-05-03 09:29:11 +02:00
|
|
|
|
break;
|
|
|
|
|
|
[ bfd/ChangeLog ]
2002-12-30 Chris Demetriou <cgd@broadcom.com>
* aoutx.h (NAME(aout,machine_type)): Add bfd_mach_mipsisa32r2 case.
* archures.c (bfd_mach_mipsisa32r2): New define.
* bfd-in2.h: Regenerate.
* cpu-mips.c (I_mipsisa32r2): New enum value.
(arch_info_struct): Add entry for I_mipsisa32r2.
* elfxx-mips.c (elf_mips_isa, _bfd_elf_mips_mach)
(_bfd_mips_elf_print_private_bfd_data): Handle E_MIPS_ARCH_32R2.
(_bfd_mips_elf_final_write_processing): Add
bfd_mach_mipsisa32r2 case.
(_bfd_mips_elf_merge_private_bfd_data): Handle merging of
binaries marked as using MIPS32 Release 2.
[ binutils/ChangeLog ]
2002-12-30 Chris Demetriou <cgd@broadcom.com>
* doc/binutils.texi (objdump): Note MIPS HWR (Hardware Register)
changes in MIPS -M options.
[ gas/ChangeLog ]
2002-12-30 Chris Demetriou <cgd@broadcom.com>
* configure.in: Recognize mipsisa32r2, mipsisa32r2el, and
CPU variants.
* configure: Regenerate.
* config/tc-mips.c (ISA_HAS_DROR, ISA_HAS_ROR): New defines.
(macro_build): Handle "K" operand.
(macro2): Use ISA_HAS_DROR and ISA_HAS_ROR in the places where
CPU_HAS_DROR and CPU_HAS_ROR are currently used.
(mips_ip): New variable "lastpos", and implement "+A", "+B",
and "+C" operands for MIPS32 Release 2 ins/ext instructions.
Implement "K" operand for MIPS32 Release 2 rdhwr instruction.
(validate_mips_insn): Implement "+" as a way to extend the
allowed operands, and implement "K", "+A", "+B", and "+C"
operands.
(OPTION_MIPS32R2): New define.
(md_longopts): Add entry for OPTION_MIPS32R2.
(OPTION_ELF_BASE): Adjust to accomodate OPTIONS_MIPS32R2.
(md_parse_option): Handle OPTION_MIPS32R2.
(s_mipsset): Reimplement handling of ".set mipsN" options
and add support for ".set mips32r2".
(mips_cpu_info_table): Add entry for "mips32r2" (MIPS32 Release 2).
(md_show_usage): Document "-mips32r2" option.
* doc/as.texinfo: Document "-mips32r2" option.
* doc/c-mips.texi: Likewise.
[ gas/testsuite/ChangeLog ]
2002-12-30 Chris Demetriou <cgd@broadcom.com>
* gas/mips/cp0-names-mips32r2.d: New test.
* gas/mips/hwr-names-mips32r2.d: New test.
* gas/mips/hwr-names-numeric.d: New test.
* gas/mips/hwr-names.s: New test source file.
* gas/mips/mips32r2.d: New test.
* gas/mips/mips32r2.s: New test source file.
* gas/mips/mips32r2-ill.l: New test.
* gas/mips/mips32r2-ill.s: New test source file.
* gas/mips/mips.exp: Add mips32r2 architecture data array
entry. Run new tests mentioned above.
[ include/elf/ChangeLog ]
2002-12-30 Chris Demetriou <cgd@broadcom.com>
* mips.h (E_MIPS_ARCH_32R2): New define.
[ include/opcode/ChangeLog ]
2002-12-30 Chris Demetriou <cgd@broadcom.com>
* mips.h: Document "+" as the start of two-character operand
type names, and add new "K", "+A", "+B", and "+C" operand types.
(OP_MASK_INSMSB, OP_SH_INSMSB, OP_MASK_EXTMSB)
(OP_SH_EXTMSB, INSN_ISA32R2, ISA_MIPS32R2, CPU_MIPS32R2): New
defines.
[ opcodes/ChangeLog ]
2002-12-30 Chris Demetriou <cgd@broadcom.com>
* mips-dis.c (mips_cp0_names_mips3264r2, mips_hwr_names_numeric)
(mips_hwr_names_mips3264r2): New arrays.
(mips_arch_choice): New "hwr_names" member.
(mips_arch_choices): Adjust for structure change, and add a new
entry for "mips32r2" ISA.
(mips_hwr_names): New variable.
(set_default_mips_dis_options): Set mips_hwr_names.
(parse_mips_dis_option): New "hwr-names" option which sets
mips_hwr_names, and adjust "reg-names=ARCH" to set mips_hwr_names.
(print_insn_arg): Change return type to "int"
and use that to indicate number of characters consumed.
Add support for "+" operand extension character, "+A", "+B",
"+C", and "K" operands.
(print_insn_mips): Adjust for changes to print_insn_arg.
(print_mips_disassembler_options): Adjust for "hwr-names"
addition and "reg-names" change.
* mips-opc (I33): New define (shorthand for INSN_ISA32R2).
(mips_builtin_opcodes): Note that "nop" and "ssnop" are special
forms of "sll". Add new MIPS32 Release 2 instructions: ehb,
di, ei, ext, ins, jr.hb, jalr.hb, mfhc1, mfhc2, mthc1, mthc2,
rdhwr, rdpgpr, seb, seh, synci, wrpgpr, wsbh.
Note that hardware rotate instructions (ror, rorv) can be
used on MIPS32 Release 2, and add the official mnemonics
for them (rotr, rotrv) and the similar "rotl" mnemonic for
left-rotate.
2002-12-31 08:29:29 +01:00
|
|
|
|
case OPTION_MIPS32R2:
|
|
|
|
|
file_mips_isa = ISA_MIPS32R2;
|
|
|
|
|
break;
|
|
|
|
|
|
[ bfd/ChangeLog ]
2003-09-30 Chris Demetriou <cgd@broadcom.com>
* archures.c (bfd_mach_mipsisa64r2): New define.
* bfd-in2.h: Regenerate.
* aoutx.h (NAME(aout,machine_type)): Handle bfd_mach_mipsisa64r2.
* cpu-mips.c (I_mipsisa64r2): New enum value.
(arch_info_struct): Add entry for I_mipsisa64r2.
* elfxx-mips.c (_bfd_elf_mips_mach)
(_bfd_mips_elf_print_private_bfd_data): Handle E_MIPS_ARCH_64R2.
(mips_set_isa_flags): Add bfd_mach_mipsisa64r2 case.
(mips_mach_extensions): Add entry for bfd_mach_mipsisa64r2.
[ binutils/ChangeLog ]
2003-09-30 Chris Demetriou <cgd@broadcom.com>
* readelf.c (get_machine_flags): Handle E_MIPS_ARCH_64R2.
[ gas/Changelog ]
2003-09-30 Chris Demetriou <cgd@broadcom.com>
* configure.in (mipsisa64r2, mipsisa64r2el, mipsisa64r2*): New CPUs.
* configure: Regenerate.
* config/tc-mips.c (imm2_expr): New variable.
(md_assemble, mips16_ip): Initialize imm2_expr.
(ISA_HAS_64BIT_REGS, ISA_HAS_DROR, ISA_HAS_ROR): Add ISA_MIPS64R2.
(macro_build): Handle +A, +B, +C, +E, +F, +G, and +H format operands.
(macro): Handle M_DEXT and M_DINS.
(validate_mips_insn): Handle +E, +F, +G, +H, and +I format operands.
(mips_ip): Likewise.
(OPTION_MIPS64R2): New define.
(md_longopts): New entry for -mips64r2 (OPTION_MIPS64R2).
OPTION_ASE_BASE): Increase to compensate for OPTION_MIPS64R2.
(md_parse_option): Handle OPTION_MIPS64R2.
(s_mipsset): Handle setting "mips64r2" ISA.
(mips_cpu_info_table): Add mips64r2.
(md_show_usage): Document -mips64r2 option.
* doc/as.texinfo: Docuemnt -mips64r2 option.
* doc/c-mips.texi: Likewise.
[ gas/testsuite/ChangeLog ]
2003-09-30 Chris Demetriou <cgd@broadcom.com>
* gas/mips/cp0-names-mips64r2.d: New file.
* gas/mips/cp0sel-names-mips64r2.d: New file.
* gas/mips/elf_arch_mips64r2.d: New file.
* gas/mips/hwr-names-mips64r2.d: New file.
* gas/mips/mips32r2-ill-fp64.l: New file.
* gas/mips/mips32r2-ill-fp64.s: New file.
* gas/mips/mips64r2-ill.l: New file.
* gas/mips/mips64r2-ill.s: New file.
* gas/mips/mips64r2.d: New file.
* gas/mips/mips64r2.s: New file.
* gas/mips/mips.exp: Define "mips64r2" arch, and run new tests.
[ include/elf/ChangeLog ]
2003-09-30 Chris Demetriou <cgd@broadcom.com>
* mips.h (E_MIPS_ARCH_64R2): New define.
[ include/opcode/ChangeLog ]
2003-09-30 Chris Demetriou <cgd@broadcom.com>
* mips.h: Document +E, +F, +G, +H, and +I operand types.
Update documentation of I, +B and +C operand types.
(INSN_ISA64R2, ISA_MIPS64R2, CPU_MIPS64R2): New defines.
(M_DEXT, M_DINS): New enum values.
[ ld/ChangeLog ]
2003-09-30 Chris Demetriou <cgd@broadcom.com>
* ldmain.c (get_emulation): Ignore "-mips64r2".
[ ld/testsuite/ChangeLog ]
2003-09-30 Chris Demetriou <cgd@broadcom.com>
* ld-mips-elf/mips-elf-flags.exp: Add tests for combinations
with MIPS64r2.
[ opcodes/ChangeLog ]
2003-09-30 Chris Demetriou <cgd@broadcom.com>
* mips-dis.c (mips_arch_choices): Add entry for "mips64r2"
(print_insn_args): Add handing for +E, +F, +G, and +H.
* mips-opc.c (I65): New define for MIPS64r2.
(mips_builtin_opcodes): Add "dext", "dextm", "dextu", "dins",
"dinsm", "dinsu", "drotl", "drotr", "drotr32", "drotrv", "dsbh",
and "dshd" for MIPS64r2. Adjust "dror", "dror32", and "drorv" to
be supported on MIPS64r2.
2003-09-30 18:17:15 +02:00
|
|
|
|
case OPTION_MIPS64R2:
|
|
|
|
|
file_mips_isa = ISA_MIPS64R2;
|
|
|
|
|
break;
|
|
|
|
|
|
2000-12-02 01:55:22 +01:00
|
|
|
|
case OPTION_MIPS64:
|
[gas/]
* doc/c-mips.texi: Remove -mcpu. Document -mabi.
* configure.in (MIPS_CPU_STRING_DEFAULT): New configuration macro.
(USE_E_MIPS_ABI_O32, MIPS_DEFAULT_64BIT): New configuration macros.
* configure, config.in: Regenerate.
* config/tc-mips.c (file_mips_abi): Rename to mips_abi.
(mips_set_options): Remove "abi" field.
(mips_opts): Update accordingly. Replace all uses of mips_opts.abi
with mips_abi.
(mips_cpu): Remove.
(mips_arch_string, mips_arch_info): New vars.
(mips_tune_string, mips_tune_info): New vars.
(ABI_NEEDS_32BIT_REGS, ABI_NEEDS_64BIT_REGS): New macros.
(HAVE_32BIT_GPRS, HAVE_32BIT_FPRS): Don't check the ABI.
(mips_isa_to_str, mips_cpu_to_str): Remove.
(mips_ip): If the selected architecture is a generic ISA rather
than a processor, only mention the ISA level in error messages.
(OPTION_MCPU): Remove.
(OPTION_FP64): New.
(md_longopts): Add -mfp64, remove -mcpu.
(mips_set_option_string): New fn.
(md_parse_option): Make -mipsN update file_mips_isa rather than
mips_opts.isa. Use mips_set_option_string to set -march or -mtune.
Don't let -mgp32 and -mfp32 change the ABI.
(show): Move to end of file. Constify string argument.
(md_show_usage): Move to the end of the file. Read available
architectures from mips_cpu_info_table.
(mips_set_architecture): New fn.
(mips_after_parse_args): Rework. Remove -mcpu handling. -mipsN
is an alias for -march=mipsN. Don't change the ABI based on other
flags. Infer the register size from the ABI as well as the
architecture. Complain about more conflicting arguments.
Unify logic with GCC.
(s_mipsset): Don't change the ABI.
(mips_elf_final_processing): Check USE_E_MIPS_ABI_O32.
(mips_cpu_info_table): Remove Generic-MIPS* entries, keeping just
"mipsN"-type entries. Remove entries that vary only in the
manufacturer's prefix, or that have "000" replaced by "k".
Remove TARGET_CPU entries. Make r2000 entry use CPU_R3000.
(mips_strict_matching_cpu_name_p, mips_matching_cpu_name_p): New fns.
(mips_parse_cpu): New fn.
(mips_cpu_info_from_name, mips_cpu_info_from_cpu): Remove.
(mips_cpu_info_from_isa): Minor formatting tweak.
[gas/testsuite]
* gas/mips/mips-gp32-fp64.d,
* gas/mips/mips-gp32-fp64-pic.d: Add -mfp64.
2002-07-25 11:48:07 +02:00
|
|
|
|
file_mips_isa = ISA_MIPS64;
|
2000-12-02 01:55:22 +01:00
|
|
|
|
break;
|
|
|
|
|
|
2001-06-29 23:27:43 +02:00
|
|
|
|
case OPTION_MTUNE:
|
[gas/]
* doc/c-mips.texi: Remove -mcpu. Document -mabi.
* configure.in (MIPS_CPU_STRING_DEFAULT): New configuration macro.
(USE_E_MIPS_ABI_O32, MIPS_DEFAULT_64BIT): New configuration macros.
* configure, config.in: Regenerate.
* config/tc-mips.c (file_mips_abi): Rename to mips_abi.
(mips_set_options): Remove "abi" field.
(mips_opts): Update accordingly. Replace all uses of mips_opts.abi
with mips_abi.
(mips_cpu): Remove.
(mips_arch_string, mips_arch_info): New vars.
(mips_tune_string, mips_tune_info): New vars.
(ABI_NEEDS_32BIT_REGS, ABI_NEEDS_64BIT_REGS): New macros.
(HAVE_32BIT_GPRS, HAVE_32BIT_FPRS): Don't check the ABI.
(mips_isa_to_str, mips_cpu_to_str): Remove.
(mips_ip): If the selected architecture is a generic ISA rather
than a processor, only mention the ISA level in error messages.
(OPTION_MCPU): Remove.
(OPTION_FP64): New.
(md_longopts): Add -mfp64, remove -mcpu.
(mips_set_option_string): New fn.
(md_parse_option): Make -mipsN update file_mips_isa rather than
mips_opts.isa. Use mips_set_option_string to set -march or -mtune.
Don't let -mgp32 and -mfp32 change the ABI.
(show): Move to end of file. Constify string argument.
(md_show_usage): Move to the end of the file. Read available
architectures from mips_cpu_info_table.
(mips_set_architecture): New fn.
(mips_after_parse_args): Rework. Remove -mcpu handling. -mipsN
is an alias for -march=mipsN. Don't change the ABI based on other
flags. Infer the register size from the ABI as well as the
architecture. Complain about more conflicting arguments.
Unify logic with GCC.
(s_mipsset): Don't change the ABI.
(mips_elf_final_processing): Check USE_E_MIPS_ABI_O32.
(mips_cpu_info_table): Remove Generic-MIPS* entries, keeping just
"mipsN"-type entries. Remove entries that vary only in the
manufacturer's prefix, or that have "000" replaced by "k".
Remove TARGET_CPU entries. Make r2000 entry use CPU_R3000.
(mips_strict_matching_cpu_name_p, mips_matching_cpu_name_p): New fns.
(mips_parse_cpu): New fn.
(mips_cpu_info_from_name, mips_cpu_info_from_cpu): Remove.
(mips_cpu_info_from_isa): Minor formatting tweak.
[gas/testsuite]
* gas/mips/mips-gp32-fp64.d,
* gas/mips/mips-gp32-fp64-pic.d: Add -mfp64.
2002-07-25 11:48:07 +02:00
|
|
|
|
mips_set_option_string (&mips_tune_string, arg);
|
|
|
|
|
break;
|
2001-06-29 23:27:43 +02:00
|
|
|
|
|
[gas/]
* doc/c-mips.texi: Remove -mcpu. Document -mabi.
* configure.in (MIPS_CPU_STRING_DEFAULT): New configuration macro.
(USE_E_MIPS_ABI_O32, MIPS_DEFAULT_64BIT): New configuration macros.
* configure, config.in: Regenerate.
* config/tc-mips.c (file_mips_abi): Rename to mips_abi.
(mips_set_options): Remove "abi" field.
(mips_opts): Update accordingly. Replace all uses of mips_opts.abi
with mips_abi.
(mips_cpu): Remove.
(mips_arch_string, mips_arch_info): New vars.
(mips_tune_string, mips_tune_info): New vars.
(ABI_NEEDS_32BIT_REGS, ABI_NEEDS_64BIT_REGS): New macros.
(HAVE_32BIT_GPRS, HAVE_32BIT_FPRS): Don't check the ABI.
(mips_isa_to_str, mips_cpu_to_str): Remove.
(mips_ip): If the selected architecture is a generic ISA rather
than a processor, only mention the ISA level in error messages.
(OPTION_MCPU): Remove.
(OPTION_FP64): New.
(md_longopts): Add -mfp64, remove -mcpu.
(mips_set_option_string): New fn.
(md_parse_option): Make -mipsN update file_mips_isa rather than
mips_opts.isa. Use mips_set_option_string to set -march or -mtune.
Don't let -mgp32 and -mfp32 change the ABI.
(show): Move to end of file. Constify string argument.
(md_show_usage): Move to the end of the file. Read available
architectures from mips_cpu_info_table.
(mips_set_architecture): New fn.
(mips_after_parse_args): Rework. Remove -mcpu handling. -mipsN
is an alias for -march=mipsN. Don't change the ABI based on other
flags. Infer the register size from the ABI as well as the
architecture. Complain about more conflicting arguments.
Unify logic with GCC.
(s_mipsset): Don't change the ABI.
(mips_elf_final_processing): Check USE_E_MIPS_ABI_O32.
(mips_cpu_info_table): Remove Generic-MIPS* entries, keeping just
"mipsN"-type entries. Remove entries that vary only in the
manufacturer's prefix, or that have "000" replaced by "k".
Remove TARGET_CPU entries. Make r2000 entry use CPU_R3000.
(mips_strict_matching_cpu_name_p, mips_matching_cpu_name_p): New fns.
(mips_parse_cpu): New fn.
(mips_cpu_info_from_name, mips_cpu_info_from_cpu): Remove.
(mips_cpu_info_from_isa): Minor formatting tweak.
[gas/testsuite]
* gas/mips/mips-gp32-fp64.d,
* gas/mips/mips-gp32-fp64-pic.d: Add -mfp64.
2002-07-25 11:48:07 +02:00
|
|
|
|
case OPTION_MARCH:
|
|
|
|
|
mips_set_option_string (&mips_arch_string, arg);
|
1999-05-03 09:29:11 +02:00
|
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
case OPTION_M4650:
|
[gas/]
* doc/c-mips.texi: Remove -mcpu. Document -mabi.
* configure.in (MIPS_CPU_STRING_DEFAULT): New configuration macro.
(USE_E_MIPS_ABI_O32, MIPS_DEFAULT_64BIT): New configuration macros.
* configure, config.in: Regenerate.
* config/tc-mips.c (file_mips_abi): Rename to mips_abi.
(mips_set_options): Remove "abi" field.
(mips_opts): Update accordingly. Replace all uses of mips_opts.abi
with mips_abi.
(mips_cpu): Remove.
(mips_arch_string, mips_arch_info): New vars.
(mips_tune_string, mips_tune_info): New vars.
(ABI_NEEDS_32BIT_REGS, ABI_NEEDS_64BIT_REGS): New macros.
(HAVE_32BIT_GPRS, HAVE_32BIT_FPRS): Don't check the ABI.
(mips_isa_to_str, mips_cpu_to_str): Remove.
(mips_ip): If the selected architecture is a generic ISA rather
than a processor, only mention the ISA level in error messages.
(OPTION_MCPU): Remove.
(OPTION_FP64): New.
(md_longopts): Add -mfp64, remove -mcpu.
(mips_set_option_string): New fn.
(md_parse_option): Make -mipsN update file_mips_isa rather than
mips_opts.isa. Use mips_set_option_string to set -march or -mtune.
Don't let -mgp32 and -mfp32 change the ABI.
(show): Move to end of file. Constify string argument.
(md_show_usage): Move to the end of the file. Read available
architectures from mips_cpu_info_table.
(mips_set_architecture): New fn.
(mips_after_parse_args): Rework. Remove -mcpu handling. -mipsN
is an alias for -march=mipsN. Don't change the ABI based on other
flags. Infer the register size from the ABI as well as the
architecture. Complain about more conflicting arguments.
Unify logic with GCC.
(s_mipsset): Don't change the ABI.
(mips_elf_final_processing): Check USE_E_MIPS_ABI_O32.
(mips_cpu_info_table): Remove Generic-MIPS* entries, keeping just
"mipsN"-type entries. Remove entries that vary only in the
manufacturer's prefix, or that have "000" replaced by "k".
Remove TARGET_CPU entries. Make r2000 entry use CPU_R3000.
(mips_strict_matching_cpu_name_p, mips_matching_cpu_name_p): New fns.
(mips_parse_cpu): New fn.
(mips_cpu_info_from_name, mips_cpu_info_from_cpu): Remove.
(mips_cpu_info_from_isa): Minor formatting tweak.
[gas/testsuite]
* gas/mips/mips-gp32-fp64.d,
* gas/mips/mips-gp32-fp64-pic.d: Add -mfp64.
2002-07-25 11:48:07 +02:00
|
|
|
|
mips_set_option_string (&mips_arch_string, "4650");
|
|
|
|
|
mips_set_option_string (&mips_tune_string, "4650");
|
1999-05-03 09:29:11 +02:00
|
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
case OPTION_NO_M4650:
|
|
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
case OPTION_M4010:
|
[gas/]
* doc/c-mips.texi: Remove -mcpu. Document -mabi.
* configure.in (MIPS_CPU_STRING_DEFAULT): New configuration macro.
(USE_E_MIPS_ABI_O32, MIPS_DEFAULT_64BIT): New configuration macros.
* configure, config.in: Regenerate.
* config/tc-mips.c (file_mips_abi): Rename to mips_abi.
(mips_set_options): Remove "abi" field.
(mips_opts): Update accordingly. Replace all uses of mips_opts.abi
with mips_abi.
(mips_cpu): Remove.
(mips_arch_string, mips_arch_info): New vars.
(mips_tune_string, mips_tune_info): New vars.
(ABI_NEEDS_32BIT_REGS, ABI_NEEDS_64BIT_REGS): New macros.
(HAVE_32BIT_GPRS, HAVE_32BIT_FPRS): Don't check the ABI.
(mips_isa_to_str, mips_cpu_to_str): Remove.
(mips_ip): If the selected architecture is a generic ISA rather
than a processor, only mention the ISA level in error messages.
(OPTION_MCPU): Remove.
(OPTION_FP64): New.
(md_longopts): Add -mfp64, remove -mcpu.
(mips_set_option_string): New fn.
(md_parse_option): Make -mipsN update file_mips_isa rather than
mips_opts.isa. Use mips_set_option_string to set -march or -mtune.
Don't let -mgp32 and -mfp32 change the ABI.
(show): Move to end of file. Constify string argument.
(md_show_usage): Move to the end of the file. Read available
architectures from mips_cpu_info_table.
(mips_set_architecture): New fn.
(mips_after_parse_args): Rework. Remove -mcpu handling. -mipsN
is an alias for -march=mipsN. Don't change the ABI based on other
flags. Infer the register size from the ABI as well as the
architecture. Complain about more conflicting arguments.
Unify logic with GCC.
(s_mipsset): Don't change the ABI.
(mips_elf_final_processing): Check USE_E_MIPS_ABI_O32.
(mips_cpu_info_table): Remove Generic-MIPS* entries, keeping just
"mipsN"-type entries. Remove entries that vary only in the
manufacturer's prefix, or that have "000" replaced by "k".
Remove TARGET_CPU entries. Make r2000 entry use CPU_R3000.
(mips_strict_matching_cpu_name_p, mips_matching_cpu_name_p): New fns.
(mips_parse_cpu): New fn.
(mips_cpu_info_from_name, mips_cpu_info_from_cpu): Remove.
(mips_cpu_info_from_isa): Minor formatting tweak.
[gas/testsuite]
* gas/mips/mips-gp32-fp64.d,
* gas/mips/mips-gp32-fp64-pic.d: Add -mfp64.
2002-07-25 11:48:07 +02:00
|
|
|
|
mips_set_option_string (&mips_arch_string, "4010");
|
|
|
|
|
mips_set_option_string (&mips_tune_string, "4010");
|
1999-05-03 09:29:11 +02:00
|
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
case OPTION_NO_M4010:
|
|
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
case OPTION_M4100:
|
[gas/]
* doc/c-mips.texi: Remove -mcpu. Document -mabi.
* configure.in (MIPS_CPU_STRING_DEFAULT): New configuration macro.
(USE_E_MIPS_ABI_O32, MIPS_DEFAULT_64BIT): New configuration macros.
* configure, config.in: Regenerate.
* config/tc-mips.c (file_mips_abi): Rename to mips_abi.
(mips_set_options): Remove "abi" field.
(mips_opts): Update accordingly. Replace all uses of mips_opts.abi
with mips_abi.
(mips_cpu): Remove.
(mips_arch_string, mips_arch_info): New vars.
(mips_tune_string, mips_tune_info): New vars.
(ABI_NEEDS_32BIT_REGS, ABI_NEEDS_64BIT_REGS): New macros.
(HAVE_32BIT_GPRS, HAVE_32BIT_FPRS): Don't check the ABI.
(mips_isa_to_str, mips_cpu_to_str): Remove.
(mips_ip): If the selected architecture is a generic ISA rather
than a processor, only mention the ISA level in error messages.
(OPTION_MCPU): Remove.
(OPTION_FP64): New.
(md_longopts): Add -mfp64, remove -mcpu.
(mips_set_option_string): New fn.
(md_parse_option): Make -mipsN update file_mips_isa rather than
mips_opts.isa. Use mips_set_option_string to set -march or -mtune.
Don't let -mgp32 and -mfp32 change the ABI.
(show): Move to end of file. Constify string argument.
(md_show_usage): Move to the end of the file. Read available
architectures from mips_cpu_info_table.
(mips_set_architecture): New fn.
(mips_after_parse_args): Rework. Remove -mcpu handling. -mipsN
is an alias for -march=mipsN. Don't change the ABI based on other
flags. Infer the register size from the ABI as well as the
architecture. Complain about more conflicting arguments.
Unify logic with GCC.
(s_mipsset): Don't change the ABI.
(mips_elf_final_processing): Check USE_E_MIPS_ABI_O32.
(mips_cpu_info_table): Remove Generic-MIPS* entries, keeping just
"mipsN"-type entries. Remove entries that vary only in the
manufacturer's prefix, or that have "000" replaced by "k".
Remove TARGET_CPU entries. Make r2000 entry use CPU_R3000.
(mips_strict_matching_cpu_name_p, mips_matching_cpu_name_p): New fns.
(mips_parse_cpu): New fn.
(mips_cpu_info_from_name, mips_cpu_info_from_cpu): Remove.
(mips_cpu_info_from_isa): Minor formatting tweak.
[gas/testsuite]
* gas/mips/mips-gp32-fp64.d,
* gas/mips/mips-gp32-fp64-pic.d: Add -mfp64.
2002-07-25 11:48:07 +02:00
|
|
|
|
mips_set_option_string (&mips_arch_string, "4100");
|
|
|
|
|
mips_set_option_string (&mips_tune_string, "4100");
|
1999-05-03 09:29:11 +02:00
|
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
case OPTION_NO_M4100:
|
|
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
case OPTION_M3900:
|
[gas/]
* doc/c-mips.texi: Remove -mcpu. Document -mabi.
* configure.in (MIPS_CPU_STRING_DEFAULT): New configuration macro.
(USE_E_MIPS_ABI_O32, MIPS_DEFAULT_64BIT): New configuration macros.
* configure, config.in: Regenerate.
* config/tc-mips.c (file_mips_abi): Rename to mips_abi.
(mips_set_options): Remove "abi" field.
(mips_opts): Update accordingly. Replace all uses of mips_opts.abi
with mips_abi.
(mips_cpu): Remove.
(mips_arch_string, mips_arch_info): New vars.
(mips_tune_string, mips_tune_info): New vars.
(ABI_NEEDS_32BIT_REGS, ABI_NEEDS_64BIT_REGS): New macros.
(HAVE_32BIT_GPRS, HAVE_32BIT_FPRS): Don't check the ABI.
(mips_isa_to_str, mips_cpu_to_str): Remove.
(mips_ip): If the selected architecture is a generic ISA rather
than a processor, only mention the ISA level in error messages.
(OPTION_MCPU): Remove.
(OPTION_FP64): New.
(md_longopts): Add -mfp64, remove -mcpu.
(mips_set_option_string): New fn.
(md_parse_option): Make -mipsN update file_mips_isa rather than
mips_opts.isa. Use mips_set_option_string to set -march or -mtune.
Don't let -mgp32 and -mfp32 change the ABI.
(show): Move to end of file. Constify string argument.
(md_show_usage): Move to the end of the file. Read available
architectures from mips_cpu_info_table.
(mips_set_architecture): New fn.
(mips_after_parse_args): Rework. Remove -mcpu handling. -mipsN
is an alias for -march=mipsN. Don't change the ABI based on other
flags. Infer the register size from the ABI as well as the
architecture. Complain about more conflicting arguments.
Unify logic with GCC.
(s_mipsset): Don't change the ABI.
(mips_elf_final_processing): Check USE_E_MIPS_ABI_O32.
(mips_cpu_info_table): Remove Generic-MIPS* entries, keeping just
"mipsN"-type entries. Remove entries that vary only in the
manufacturer's prefix, or that have "000" replaced by "k".
Remove TARGET_CPU entries. Make r2000 entry use CPU_R3000.
(mips_strict_matching_cpu_name_p, mips_matching_cpu_name_p): New fns.
(mips_parse_cpu): New fn.
(mips_cpu_info_from_name, mips_cpu_info_from_cpu): Remove.
(mips_cpu_info_from_isa): Minor formatting tweak.
[gas/testsuite]
* gas/mips/mips-gp32-fp64.d,
* gas/mips/mips-gp32-fp64-pic.d: Add -mfp64.
2002-07-25 11:48:07 +02:00
|
|
|
|
mips_set_option_string (&mips_arch_string, "3900");
|
|
|
|
|
mips_set_option_string (&mips_tune_string, "3900");
|
1999-05-03 09:29:11 +02:00
|
|
|
|
break;
|
2000-09-07 14:45:56 +02:00
|
|
|
|
|
1999-05-03 09:29:11 +02:00
|
|
|
|
case OPTION_NO_M3900:
|
|
|
|
|
break;
|
|
|
|
|
|
[ gas/ChangeLog ]
2002-05-30 Chris G. Demetriou <cgd@broadcom.com>
Ed Satterthwaite <ehs@broadcom.com>
* config/tc-mips.c (mips_set_options): New "ase_mdmx" member.
(mips_opts): Initialize "ase_mdmx" member.
(file_ase_mdmx): New variable.
(CPU_HAS_MDMX): New macro.
(md_begin): Initialize mips_opts.ase_mdmx and file_ase_mdmx
based on command line options and configuration defaults.
(macro_build): Note in comment that use of MDMX in macros is
not currently allowed.
(validate_mips_insn): Add support for the "O", "Q", "X", "Y", and
"Z" MDMX operand types.
(mips_ip): Accept MDMX instructions if mips_opts.ase_mdmx is set,
and add support for the "O", "Q", "X", "Y", and "Z" MDMX operand
types.
(OPTION_MDMX, OPTION_NO_MDMX, md_longopts, md_parse_option):
Add support for "-mdmx" and "-no-mdmx" options.
(OPTION_ELF_BASE): Move to accomodate new options.
(s_mipsset): Support ".set mdmx" and ".set nomdmx".
(mips_elf_final_processing): Set MDMX ASE ELF header flag if
file_ase_mdmx was set.
* doc/as.texinfo: Document -mdmx and -no-mdmx options.
* doc/c-mips.texi: Likewise, and document ".set mdmx" and ".set
nomdmx" directives.
[ gas/testsuite/ChangeLog ]
2002-05-30 Chris G. Demetriou <cgd@broadcom.com>
* gas/mips/mips64-mdmx.s: New file.
* gas/mips/mips64-mdmx.d: Likewise.
* gas/mips/mips.exp: Run new "mips64-mdmx" test.
[ include/opcode/ChangeLog ]
2002-05-30 Chris G. Demetriou <cgd@broadcom.com>
* mips.h (OP_SH_ALN, OP_MASK_ALN, OP_SH_VSEL, OP_MASK_VSEL)
(MDMX_FMTSEL_IMM_QH, MDMX_FMTSEL_IMM_OB, MDMX_FMTSEL_VEC_QH)
(MDMX_FMTSEL_VEC_OB, INSN_READ_MDMX_ACC, INSN_WRITE_MDMX_ACC)
(INSN_MDMX): New constants, for MDMX support.
(opcode character list): Add "O", "Q", "X", "Y", and "Z" for MDMX.
[ opcodes/ChangeLog ]
2002-05-30 Chris G. Demetriou <cgd@broadcom.com>
Ed Satterthwaite <ehs@broadcom.com>
* mips-dis.c (print_insn_arg): Add support for 'O', 'Q', 'X', 'Y',
and 'Z' formats, for MDMX.
(mips_isa_type): Add MDMX instructions to the ISA
bit mask for bfd_mach_mipsisa64.
* mips-opc.c: Add support for MDMX instructions.
(MX): New definition.
* mips-dis.c: Update copyright years to include 2002.
2002-05-31 03:17:18 +02:00
|
|
|
|
case OPTION_MDMX:
|
|
|
|
|
mips_opts.ase_mdmx = 1;
|
|
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
case OPTION_NO_MDMX:
|
|
|
|
|
mips_opts.ase_mdmx = 0;
|
|
|
|
|
break;
|
|
|
|
|
|
1999-05-03 09:29:11 +02:00
|
|
|
|
case OPTION_MIPS16:
|
|
|
|
|
mips_opts.mips16 = 1;
|
2002-11-30 09:39:46 +01:00
|
|
|
|
mips_no_prev_insn (FALSE);
|
1999-05-03 09:29:11 +02:00
|
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
case OPTION_NO_MIPS16:
|
|
|
|
|
mips_opts.mips16 = 0;
|
2002-11-30 09:39:46 +01:00
|
|
|
|
mips_no_prev_insn (FALSE);
|
1999-05-03 09:29:11 +02:00
|
|
|
|
break;
|
|
|
|
|
|
2002-03-16 04:09:19 +01:00
|
|
|
|
case OPTION_MIPS3D:
|
|
|
|
|
mips_opts.ase_mips3d = 1;
|
|
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
case OPTION_NO_MIPS3D:
|
|
|
|
|
mips_opts.ase_mips3d = 0;
|
|
|
|
|
break;
|
|
|
|
|
|
1999-05-03 09:29:11 +02:00
|
|
|
|
case OPTION_MEMBEDDED_PIC:
|
|
|
|
|
mips_pic = EMBEDDED_PIC;
|
|
|
|
|
if (USE_GLOBAL_POINTER_OPT && g_switch_seen)
|
|
|
|
|
{
|
|
|
|
|
as_bad (_("-G may not be used with embedded PIC code"));
|
|
|
|
|
return 0;
|
|
|
|
|
}
|
|
|
|
|
g_switch_value = 0x7fffffff;
|
|
|
|
|
break;
|
|
|
|
|
|
[gas/]
* doc/c-mips.texi: Add entries for -march=vr4120,vr4130,vr4181,
vr5400 and vr5500. Add entry for -mfix-vr4122-bugs.
* config/tc-mips.c (CPU_HAS_DROR, CPU_HAS_ROR): New macros.
(hilo_interlocks): True for CPU_VR5500.
(gpr_interlocks, cop_interlocks): True for CPU_VR5400 and CPU_VR5500.
(mips_fix_vr4122_bugs): New.
(append_insn): Work around 4122 errors if mips_fix_vr4122_bugs.
(mips_emit_delays): Likewise.
(macro2) [M_DROLI]: Use dror or dror32 if CPU_HAS_DROR.
[M_ROLI]: Likewise ror if CPU_HAS_ROR.
(validate_mips_insn, mips_ip): Handle '[', ']', 'e' and '%'.
(OPTION_FIX_VR4122, OPTION_NO_FIX_VR4122): New options.
(md_longopts): Add -mfix-vr4122-bugs and -no-mfix-vr4122-bugs.
(OPTION_ELF_BASE): Bump.
(md_parse_option): Handle the new options.
(mips_cpu_info_table): Add entries for vr4120, vr4130, vr4181,
vr5400 and vr5500.
[gas/testsuite/]
* gas/mips/mips4100.[sd]: Move dmadd16 and madd16 checks to...
* gas/mips/vr4111.[sd]: ...this new test.
* gas/mips/vr4120.[sd],
* gas/mips/vr4122.[sd],
* gas/mips/vr5400.[sd],
* gas/mips/vr5500.[sd]: New tests.
* mips.exp: Run them.
2002-09-30 14:04:54 +02:00
|
|
|
|
case OPTION_FIX_VR4122:
|
|
|
|
|
mips_fix_4122_bugs = 1;
|
|
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
case OPTION_NO_FIX_VR4122:
|
|
|
|
|
mips_fix_4122_bugs = 0;
|
|
|
|
|
break;
|
|
|
|
|
|
2002-10-12 07:23:33 +02:00
|
|
|
|
case OPTION_RELAX_BRANCH:
|
|
|
|
|
mips_relax_branch = 1;
|
|
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
case OPTION_NO_RELAX_BRANCH:
|
|
|
|
|
mips_relax_branch = 0;
|
|
|
|
|
break;
|
|
|
|
|
|
2001-02-10 22:41:12 +01:00
|
|
|
|
#ifdef OBJ_ELF
|
1999-05-03 09:29:11 +02:00
|
|
|
|
/* When generating ELF code, we permit -KPIC and -call_shared to
|
|
|
|
|
select SVR4_PIC, and -non_shared to select no PIC. This is
|
|
|
|
|
intended to be compatible with Irix 5. */
|
|
|
|
|
case OPTION_CALL_SHARED:
|
|
|
|
|
if (OUTPUT_FLAVOR != bfd_target_elf_flavour)
|
|
|
|
|
{
|
|
|
|
|
as_bad (_("-call_shared is supported only for ELF format"));
|
|
|
|
|
return 0;
|
|
|
|
|
}
|
|
|
|
|
mips_pic = SVR4_PIC;
|
2003-05-21 23:53:33 +02:00
|
|
|
|
mips_abicalls = TRUE;
|
1999-05-03 09:29:11 +02:00
|
|
|
|
if (g_switch_seen && g_switch_value != 0)
|
|
|
|
|
{
|
|
|
|
|
as_bad (_("-G may not be used with SVR4 PIC code"));
|
|
|
|
|
return 0;
|
|
|
|
|
}
|
|
|
|
|
g_switch_value = 0;
|
|
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
case OPTION_NON_SHARED:
|
|
|
|
|
if (OUTPUT_FLAVOR != bfd_target_elf_flavour)
|
|
|
|
|
{
|
|
|
|
|
as_bad (_("-non_shared is supported only for ELF format"));
|
|
|
|
|
return 0;
|
|
|
|
|
}
|
|
|
|
|
mips_pic = NO_PIC;
|
2003-05-21 23:53:33 +02:00
|
|
|
|
mips_abicalls = FALSE;
|
1999-05-03 09:29:11 +02:00
|
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
/* The -xgot option tells the assembler to use 32 offsets when
|
|
|
|
|
accessing the got in SVR4_PIC mode. It is for Irix
|
|
|
|
|
compatibility. */
|
|
|
|
|
case OPTION_XGOT:
|
|
|
|
|
mips_big_got = 1;
|
|
|
|
|
break;
|
2001-02-10 22:41:12 +01:00
|
|
|
|
#endif /* OBJ_ELF */
|
1999-05-03 09:29:11 +02:00
|
|
|
|
|
|
|
|
|
case 'G':
|
|
|
|
|
if (! USE_GLOBAL_POINTER_OPT)
|
|
|
|
|
{
|
|
|
|
|
as_bad (_("-G is not supported for this configuration"));
|
|
|
|
|
return 0;
|
|
|
|
|
}
|
|
|
|
|
else if (mips_pic == SVR4_PIC || mips_pic == EMBEDDED_PIC)
|
|
|
|
|
{
|
|
|
|
|
as_bad (_("-G may not be used with SVR4 or embedded PIC code"));
|
|
|
|
|
return 0;
|
|
|
|
|
}
|
|
|
|
|
else
|
|
|
|
|
g_switch_value = atoi (arg);
|
|
|
|
|
g_switch_seen = 1;
|
|
|
|
|
break;
|
|
|
|
|
|
2001-02-10 22:41:12 +01:00
|
|
|
|
#ifdef OBJ_ELF
|
2001-12-04 14:27:56 +01:00
|
|
|
|
/* The -32, -n32 and -64 options are shortcuts for -mabi=32, -mabi=n32
|
|
|
|
|
and -mabi=64. */
|
1999-05-03 09:29:11 +02:00
|
|
|
|
case OPTION_32:
|
2001-12-04 14:27:56 +01:00
|
|
|
|
if (OUTPUT_FLAVOR != bfd_target_elf_flavour)
|
|
|
|
|
{
|
|
|
|
|
as_bad (_("-32 is supported for ELF format only"));
|
|
|
|
|
return 0;
|
|
|
|
|
}
|
[gas/]
* doc/c-mips.texi: Remove -mcpu. Document -mabi.
* configure.in (MIPS_CPU_STRING_DEFAULT): New configuration macro.
(USE_E_MIPS_ABI_O32, MIPS_DEFAULT_64BIT): New configuration macros.
* configure, config.in: Regenerate.
* config/tc-mips.c (file_mips_abi): Rename to mips_abi.
(mips_set_options): Remove "abi" field.
(mips_opts): Update accordingly. Replace all uses of mips_opts.abi
with mips_abi.
(mips_cpu): Remove.
(mips_arch_string, mips_arch_info): New vars.
(mips_tune_string, mips_tune_info): New vars.
(ABI_NEEDS_32BIT_REGS, ABI_NEEDS_64BIT_REGS): New macros.
(HAVE_32BIT_GPRS, HAVE_32BIT_FPRS): Don't check the ABI.
(mips_isa_to_str, mips_cpu_to_str): Remove.
(mips_ip): If the selected architecture is a generic ISA rather
than a processor, only mention the ISA level in error messages.
(OPTION_MCPU): Remove.
(OPTION_FP64): New.
(md_longopts): Add -mfp64, remove -mcpu.
(mips_set_option_string): New fn.
(md_parse_option): Make -mipsN update file_mips_isa rather than
mips_opts.isa. Use mips_set_option_string to set -march or -mtune.
Don't let -mgp32 and -mfp32 change the ABI.
(show): Move to end of file. Constify string argument.
(md_show_usage): Move to the end of the file. Read available
architectures from mips_cpu_info_table.
(mips_set_architecture): New fn.
(mips_after_parse_args): Rework. Remove -mcpu handling. -mipsN
is an alias for -march=mipsN. Don't change the ABI based on other
flags. Infer the register size from the ABI as well as the
architecture. Complain about more conflicting arguments.
Unify logic with GCC.
(s_mipsset): Don't change the ABI.
(mips_elf_final_processing): Check USE_E_MIPS_ABI_O32.
(mips_cpu_info_table): Remove Generic-MIPS* entries, keeping just
"mipsN"-type entries. Remove entries that vary only in the
manufacturer's prefix, or that have "000" replaced by "k".
Remove TARGET_CPU entries. Make r2000 entry use CPU_R3000.
(mips_strict_matching_cpu_name_p, mips_matching_cpu_name_p): New fns.
(mips_parse_cpu): New fn.
(mips_cpu_info_from_name, mips_cpu_info_from_cpu): Remove.
(mips_cpu_info_from_isa): Minor formatting tweak.
[gas/testsuite]
* gas/mips/mips-gp32-fp64.d,
* gas/mips/mips-gp32-fp64-pic.d: Add -mfp64.
2002-07-25 11:48:07 +02:00
|
|
|
|
mips_abi = O32_ABI;
|
1999-05-03 09:29:11 +02:00
|
|
|
|
break;
|
|
|
|
|
|
2001-10-03 22:30:15 +02:00
|
|
|
|
case OPTION_N32:
|
2001-12-04 14:27:56 +01:00
|
|
|
|
if (OUTPUT_FLAVOR != bfd_target_elf_flavour)
|
|
|
|
|
{
|
|
|
|
|
as_bad (_("-n32 is supported for ELF format only"));
|
|
|
|
|
return 0;
|
|
|
|
|
}
|
[gas/]
* doc/c-mips.texi: Remove -mcpu. Document -mabi.
* configure.in (MIPS_CPU_STRING_DEFAULT): New configuration macro.
(USE_E_MIPS_ABI_O32, MIPS_DEFAULT_64BIT): New configuration macros.
* configure, config.in: Regenerate.
* config/tc-mips.c (file_mips_abi): Rename to mips_abi.
(mips_set_options): Remove "abi" field.
(mips_opts): Update accordingly. Replace all uses of mips_opts.abi
with mips_abi.
(mips_cpu): Remove.
(mips_arch_string, mips_arch_info): New vars.
(mips_tune_string, mips_tune_info): New vars.
(ABI_NEEDS_32BIT_REGS, ABI_NEEDS_64BIT_REGS): New macros.
(HAVE_32BIT_GPRS, HAVE_32BIT_FPRS): Don't check the ABI.
(mips_isa_to_str, mips_cpu_to_str): Remove.
(mips_ip): If the selected architecture is a generic ISA rather
than a processor, only mention the ISA level in error messages.
(OPTION_MCPU): Remove.
(OPTION_FP64): New.
(md_longopts): Add -mfp64, remove -mcpu.
(mips_set_option_string): New fn.
(md_parse_option): Make -mipsN update file_mips_isa rather than
mips_opts.isa. Use mips_set_option_string to set -march or -mtune.
Don't let -mgp32 and -mfp32 change the ABI.
(show): Move to end of file. Constify string argument.
(md_show_usage): Move to the end of the file. Read available
architectures from mips_cpu_info_table.
(mips_set_architecture): New fn.
(mips_after_parse_args): Rework. Remove -mcpu handling. -mipsN
is an alias for -march=mipsN. Don't change the ABI based on other
flags. Infer the register size from the ABI as well as the
architecture. Complain about more conflicting arguments.
Unify logic with GCC.
(s_mipsset): Don't change the ABI.
(mips_elf_final_processing): Check USE_E_MIPS_ABI_O32.
(mips_cpu_info_table): Remove Generic-MIPS* entries, keeping just
"mipsN"-type entries. Remove entries that vary only in the
manufacturer's prefix, or that have "000" replaced by "k".
Remove TARGET_CPU entries. Make r2000 entry use CPU_R3000.
(mips_strict_matching_cpu_name_p, mips_matching_cpu_name_p): New fns.
(mips_parse_cpu): New fn.
(mips_cpu_info_from_name, mips_cpu_info_from_cpu): Remove.
(mips_cpu_info_from_isa): Minor formatting tweak.
[gas/testsuite]
* gas/mips/mips-gp32-fp64.d,
* gas/mips/mips-gp32-fp64-pic.d: Add -mfp64.
2002-07-25 11:48:07 +02:00
|
|
|
|
mips_abi = N32_ABI;
|
2001-10-03 22:30:15 +02:00
|
|
|
|
break;
|
1999-05-03 09:29:11 +02:00
|
|
|
|
|
2001-10-03 22:30:15 +02:00
|
|
|
|
case OPTION_64:
|
2001-12-04 14:27:56 +01:00
|
|
|
|
if (OUTPUT_FLAVOR != bfd_target_elf_flavour)
|
|
|
|
|
{
|
|
|
|
|
as_bad (_("-64 is supported for ELF format only"));
|
|
|
|
|
return 0;
|
|
|
|
|
}
|
[gas/]
* doc/c-mips.texi: Remove -mcpu. Document -mabi.
* configure.in (MIPS_CPU_STRING_DEFAULT): New configuration macro.
(USE_E_MIPS_ABI_O32, MIPS_DEFAULT_64BIT): New configuration macros.
* configure, config.in: Regenerate.
* config/tc-mips.c (file_mips_abi): Rename to mips_abi.
(mips_set_options): Remove "abi" field.
(mips_opts): Update accordingly. Replace all uses of mips_opts.abi
with mips_abi.
(mips_cpu): Remove.
(mips_arch_string, mips_arch_info): New vars.
(mips_tune_string, mips_tune_info): New vars.
(ABI_NEEDS_32BIT_REGS, ABI_NEEDS_64BIT_REGS): New macros.
(HAVE_32BIT_GPRS, HAVE_32BIT_FPRS): Don't check the ABI.
(mips_isa_to_str, mips_cpu_to_str): Remove.
(mips_ip): If the selected architecture is a generic ISA rather
than a processor, only mention the ISA level in error messages.
(OPTION_MCPU): Remove.
(OPTION_FP64): New.
(md_longopts): Add -mfp64, remove -mcpu.
(mips_set_option_string): New fn.
(md_parse_option): Make -mipsN update file_mips_isa rather than
mips_opts.isa. Use mips_set_option_string to set -march or -mtune.
Don't let -mgp32 and -mfp32 change the ABI.
(show): Move to end of file. Constify string argument.
(md_show_usage): Move to the end of the file. Read available
architectures from mips_cpu_info_table.
(mips_set_architecture): New fn.
(mips_after_parse_args): Rework. Remove -mcpu handling. -mipsN
is an alias for -march=mipsN. Don't change the ABI based on other
flags. Infer the register size from the ABI as well as the
architecture. Complain about more conflicting arguments.
Unify logic with GCC.
(s_mipsset): Don't change the ABI.
(mips_elf_final_processing): Check USE_E_MIPS_ABI_O32.
(mips_cpu_info_table): Remove Generic-MIPS* entries, keeping just
"mipsN"-type entries. Remove entries that vary only in the
manufacturer's prefix, or that have "000" replaced by "k".
Remove TARGET_CPU entries. Make r2000 entry use CPU_R3000.
(mips_strict_matching_cpu_name_p, mips_matching_cpu_name_p): New fns.
(mips_parse_cpu): New fn.
(mips_cpu_info_from_name, mips_cpu_info_from_cpu): Remove.
(mips_cpu_info_from_isa): Minor formatting tweak.
[gas/testsuite]
* gas/mips/mips-gp32-fp64.d,
* gas/mips/mips-gp32-fp64-pic.d: Add -mfp64.
2002-07-25 11:48:07 +02:00
|
|
|
|
mips_abi = N64_ABI;
|
2001-10-03 22:30:15 +02:00
|
|
|
|
if (! support_64bit_objects())
|
|
|
|
|
as_fatal (_("No compiled in support for 64 bit object file format"));
|
1999-05-03 09:29:11 +02:00
|
|
|
|
break;
|
2001-11-12 23:22:20 +01:00
|
|
|
|
#endif /* OBJ_ELF */
|
1999-05-03 09:29:11 +02:00
|
|
|
|
|
2000-02-22 15:43:54 +01:00
|
|
|
|
case OPTION_GP32:
|
2001-11-12 17:54:54 +01:00
|
|
|
|
file_mips_gp32 = 1;
|
2000-02-22 15:43:54 +01:00
|
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
case OPTION_GP64:
|
2001-11-12 17:54:54 +01:00
|
|
|
|
file_mips_gp32 = 0;
|
2000-02-22 15:43:54 +01:00
|
|
|
|
break;
|
1999-05-03 09:29:11 +02:00
|
|
|
|
|
2001-08-02 12:15:24 +02:00
|
|
|
|
case OPTION_FP32:
|
2001-11-12 17:54:54 +01:00
|
|
|
|
file_mips_fp32 = 1;
|
[gas/]
* doc/c-mips.texi: Remove -mcpu. Document -mabi.
* configure.in (MIPS_CPU_STRING_DEFAULT): New configuration macro.
(USE_E_MIPS_ABI_O32, MIPS_DEFAULT_64BIT): New configuration macros.
* configure, config.in: Regenerate.
* config/tc-mips.c (file_mips_abi): Rename to mips_abi.
(mips_set_options): Remove "abi" field.
(mips_opts): Update accordingly. Replace all uses of mips_opts.abi
with mips_abi.
(mips_cpu): Remove.
(mips_arch_string, mips_arch_info): New vars.
(mips_tune_string, mips_tune_info): New vars.
(ABI_NEEDS_32BIT_REGS, ABI_NEEDS_64BIT_REGS): New macros.
(HAVE_32BIT_GPRS, HAVE_32BIT_FPRS): Don't check the ABI.
(mips_isa_to_str, mips_cpu_to_str): Remove.
(mips_ip): If the selected architecture is a generic ISA rather
than a processor, only mention the ISA level in error messages.
(OPTION_MCPU): Remove.
(OPTION_FP64): New.
(md_longopts): Add -mfp64, remove -mcpu.
(mips_set_option_string): New fn.
(md_parse_option): Make -mipsN update file_mips_isa rather than
mips_opts.isa. Use mips_set_option_string to set -march or -mtune.
Don't let -mgp32 and -mfp32 change the ABI.
(show): Move to end of file. Constify string argument.
(md_show_usage): Move to the end of the file. Read available
architectures from mips_cpu_info_table.
(mips_set_architecture): New fn.
(mips_after_parse_args): Rework. Remove -mcpu handling. -mipsN
is an alias for -march=mipsN. Don't change the ABI based on other
flags. Infer the register size from the ABI as well as the
architecture. Complain about more conflicting arguments.
Unify logic with GCC.
(s_mipsset): Don't change the ABI.
(mips_elf_final_processing): Check USE_E_MIPS_ABI_O32.
(mips_cpu_info_table): Remove Generic-MIPS* entries, keeping just
"mipsN"-type entries. Remove entries that vary only in the
manufacturer's prefix, or that have "000" replaced by "k".
Remove TARGET_CPU entries. Make r2000 entry use CPU_R3000.
(mips_strict_matching_cpu_name_p, mips_matching_cpu_name_p): New fns.
(mips_parse_cpu): New fn.
(mips_cpu_info_from_name, mips_cpu_info_from_cpu): Remove.
(mips_cpu_info_from_isa): Minor formatting tweak.
[gas/testsuite]
* gas/mips/mips-gp32-fp64.d,
* gas/mips/mips-gp32-fp64-pic.d: Add -mfp64.
2002-07-25 11:48:07 +02:00
|
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
case OPTION_FP64:
|
|
|
|
|
file_mips_fp32 = 0;
|
2001-08-02 12:15:24 +02:00
|
|
|
|
break;
|
|
|
|
|
|
2001-11-12 23:22:20 +01:00
|
|
|
|
#ifdef OBJ_ELF
|
1999-05-03 09:29:11 +02:00
|
|
|
|
case OPTION_MABI:
|
2001-12-04 14:27:56 +01:00
|
|
|
|
if (OUTPUT_FLAVOR != bfd_target_elf_flavour)
|
|
|
|
|
{
|
|
|
|
|
as_bad (_("-mabi is supported for ELF format only"));
|
|
|
|
|
return 0;
|
|
|
|
|
}
|
2001-10-03 22:30:15 +02:00
|
|
|
|
if (strcmp (arg, "32") == 0)
|
[gas/]
* doc/c-mips.texi: Remove -mcpu. Document -mabi.
* configure.in (MIPS_CPU_STRING_DEFAULT): New configuration macro.
(USE_E_MIPS_ABI_O32, MIPS_DEFAULT_64BIT): New configuration macros.
* configure, config.in: Regenerate.
* config/tc-mips.c (file_mips_abi): Rename to mips_abi.
(mips_set_options): Remove "abi" field.
(mips_opts): Update accordingly. Replace all uses of mips_opts.abi
with mips_abi.
(mips_cpu): Remove.
(mips_arch_string, mips_arch_info): New vars.
(mips_tune_string, mips_tune_info): New vars.
(ABI_NEEDS_32BIT_REGS, ABI_NEEDS_64BIT_REGS): New macros.
(HAVE_32BIT_GPRS, HAVE_32BIT_FPRS): Don't check the ABI.
(mips_isa_to_str, mips_cpu_to_str): Remove.
(mips_ip): If the selected architecture is a generic ISA rather
than a processor, only mention the ISA level in error messages.
(OPTION_MCPU): Remove.
(OPTION_FP64): New.
(md_longopts): Add -mfp64, remove -mcpu.
(mips_set_option_string): New fn.
(md_parse_option): Make -mipsN update file_mips_isa rather than
mips_opts.isa. Use mips_set_option_string to set -march or -mtune.
Don't let -mgp32 and -mfp32 change the ABI.
(show): Move to end of file. Constify string argument.
(md_show_usage): Move to the end of the file. Read available
architectures from mips_cpu_info_table.
(mips_set_architecture): New fn.
(mips_after_parse_args): Rework. Remove -mcpu handling. -mipsN
is an alias for -march=mipsN. Don't change the ABI based on other
flags. Infer the register size from the ABI as well as the
architecture. Complain about more conflicting arguments.
Unify logic with GCC.
(s_mipsset): Don't change the ABI.
(mips_elf_final_processing): Check USE_E_MIPS_ABI_O32.
(mips_cpu_info_table): Remove Generic-MIPS* entries, keeping just
"mipsN"-type entries. Remove entries that vary only in the
manufacturer's prefix, or that have "000" replaced by "k".
Remove TARGET_CPU entries. Make r2000 entry use CPU_R3000.
(mips_strict_matching_cpu_name_p, mips_matching_cpu_name_p): New fns.
(mips_parse_cpu): New fn.
(mips_cpu_info_from_name, mips_cpu_info_from_cpu): Remove.
(mips_cpu_info_from_isa): Minor formatting tweak.
[gas/testsuite]
* gas/mips/mips-gp32-fp64.d,
* gas/mips/mips-gp32-fp64-pic.d: Add -mfp64.
2002-07-25 11:48:07 +02:00
|
|
|
|
mips_abi = O32_ABI;
|
2001-10-03 22:30:15 +02:00
|
|
|
|
else if (strcmp (arg, "o64") == 0)
|
[gas/]
* doc/c-mips.texi: Remove -mcpu. Document -mabi.
* configure.in (MIPS_CPU_STRING_DEFAULT): New configuration macro.
(USE_E_MIPS_ABI_O32, MIPS_DEFAULT_64BIT): New configuration macros.
* configure, config.in: Regenerate.
* config/tc-mips.c (file_mips_abi): Rename to mips_abi.
(mips_set_options): Remove "abi" field.
(mips_opts): Update accordingly. Replace all uses of mips_opts.abi
with mips_abi.
(mips_cpu): Remove.
(mips_arch_string, mips_arch_info): New vars.
(mips_tune_string, mips_tune_info): New vars.
(ABI_NEEDS_32BIT_REGS, ABI_NEEDS_64BIT_REGS): New macros.
(HAVE_32BIT_GPRS, HAVE_32BIT_FPRS): Don't check the ABI.
(mips_isa_to_str, mips_cpu_to_str): Remove.
(mips_ip): If the selected architecture is a generic ISA rather
than a processor, only mention the ISA level in error messages.
(OPTION_MCPU): Remove.
(OPTION_FP64): New.
(md_longopts): Add -mfp64, remove -mcpu.
(mips_set_option_string): New fn.
(md_parse_option): Make -mipsN update file_mips_isa rather than
mips_opts.isa. Use mips_set_option_string to set -march or -mtune.
Don't let -mgp32 and -mfp32 change the ABI.
(show): Move to end of file. Constify string argument.
(md_show_usage): Move to the end of the file. Read available
architectures from mips_cpu_info_table.
(mips_set_architecture): New fn.
(mips_after_parse_args): Rework. Remove -mcpu handling. -mipsN
is an alias for -march=mipsN. Don't change the ABI based on other
flags. Infer the register size from the ABI as well as the
architecture. Complain about more conflicting arguments.
Unify logic with GCC.
(s_mipsset): Don't change the ABI.
(mips_elf_final_processing): Check USE_E_MIPS_ABI_O32.
(mips_cpu_info_table): Remove Generic-MIPS* entries, keeping just
"mipsN"-type entries. Remove entries that vary only in the
manufacturer's prefix, or that have "000" replaced by "k".
Remove TARGET_CPU entries. Make r2000 entry use CPU_R3000.
(mips_strict_matching_cpu_name_p, mips_matching_cpu_name_p): New fns.
(mips_parse_cpu): New fn.
(mips_cpu_info_from_name, mips_cpu_info_from_cpu): Remove.
(mips_cpu_info_from_isa): Minor formatting tweak.
[gas/testsuite]
* gas/mips/mips-gp32-fp64.d,
* gas/mips/mips-gp32-fp64-pic.d: Add -mfp64.
2002-07-25 11:48:07 +02:00
|
|
|
|
mips_abi = O64_ABI;
|
2001-10-03 22:30:15 +02:00
|
|
|
|
else if (strcmp (arg, "n32") == 0)
|
[gas/]
* doc/c-mips.texi: Remove -mcpu. Document -mabi.
* configure.in (MIPS_CPU_STRING_DEFAULT): New configuration macro.
(USE_E_MIPS_ABI_O32, MIPS_DEFAULT_64BIT): New configuration macros.
* configure, config.in: Regenerate.
* config/tc-mips.c (file_mips_abi): Rename to mips_abi.
(mips_set_options): Remove "abi" field.
(mips_opts): Update accordingly. Replace all uses of mips_opts.abi
with mips_abi.
(mips_cpu): Remove.
(mips_arch_string, mips_arch_info): New vars.
(mips_tune_string, mips_tune_info): New vars.
(ABI_NEEDS_32BIT_REGS, ABI_NEEDS_64BIT_REGS): New macros.
(HAVE_32BIT_GPRS, HAVE_32BIT_FPRS): Don't check the ABI.
(mips_isa_to_str, mips_cpu_to_str): Remove.
(mips_ip): If the selected architecture is a generic ISA rather
than a processor, only mention the ISA level in error messages.
(OPTION_MCPU): Remove.
(OPTION_FP64): New.
(md_longopts): Add -mfp64, remove -mcpu.
(mips_set_option_string): New fn.
(md_parse_option): Make -mipsN update file_mips_isa rather than
mips_opts.isa. Use mips_set_option_string to set -march or -mtune.
Don't let -mgp32 and -mfp32 change the ABI.
(show): Move to end of file. Constify string argument.
(md_show_usage): Move to the end of the file. Read available
architectures from mips_cpu_info_table.
(mips_set_architecture): New fn.
(mips_after_parse_args): Rework. Remove -mcpu handling. -mipsN
is an alias for -march=mipsN. Don't change the ABI based on other
flags. Infer the register size from the ABI as well as the
architecture. Complain about more conflicting arguments.
Unify logic with GCC.
(s_mipsset): Don't change the ABI.
(mips_elf_final_processing): Check USE_E_MIPS_ABI_O32.
(mips_cpu_info_table): Remove Generic-MIPS* entries, keeping just
"mipsN"-type entries. Remove entries that vary only in the
manufacturer's prefix, or that have "000" replaced by "k".
Remove TARGET_CPU entries. Make r2000 entry use CPU_R3000.
(mips_strict_matching_cpu_name_p, mips_matching_cpu_name_p): New fns.
(mips_parse_cpu): New fn.
(mips_cpu_info_from_name, mips_cpu_info_from_cpu): Remove.
(mips_cpu_info_from_isa): Minor formatting tweak.
[gas/testsuite]
* gas/mips/mips-gp32-fp64.d,
* gas/mips/mips-gp32-fp64-pic.d: Add -mfp64.
2002-07-25 11:48:07 +02:00
|
|
|
|
mips_abi = N32_ABI;
|
2001-10-03 22:30:15 +02:00
|
|
|
|
else if (strcmp (arg, "64") == 0)
|
|
|
|
|
{
|
[gas/]
* doc/c-mips.texi: Remove -mcpu. Document -mabi.
* configure.in (MIPS_CPU_STRING_DEFAULT): New configuration macro.
(USE_E_MIPS_ABI_O32, MIPS_DEFAULT_64BIT): New configuration macros.
* configure, config.in: Regenerate.
* config/tc-mips.c (file_mips_abi): Rename to mips_abi.
(mips_set_options): Remove "abi" field.
(mips_opts): Update accordingly. Replace all uses of mips_opts.abi
with mips_abi.
(mips_cpu): Remove.
(mips_arch_string, mips_arch_info): New vars.
(mips_tune_string, mips_tune_info): New vars.
(ABI_NEEDS_32BIT_REGS, ABI_NEEDS_64BIT_REGS): New macros.
(HAVE_32BIT_GPRS, HAVE_32BIT_FPRS): Don't check the ABI.
(mips_isa_to_str, mips_cpu_to_str): Remove.
(mips_ip): If the selected architecture is a generic ISA rather
than a processor, only mention the ISA level in error messages.
(OPTION_MCPU): Remove.
(OPTION_FP64): New.
(md_longopts): Add -mfp64, remove -mcpu.
(mips_set_option_string): New fn.
(md_parse_option): Make -mipsN update file_mips_isa rather than
mips_opts.isa. Use mips_set_option_string to set -march or -mtune.
Don't let -mgp32 and -mfp32 change the ABI.
(show): Move to end of file. Constify string argument.
(md_show_usage): Move to the end of the file. Read available
architectures from mips_cpu_info_table.
(mips_set_architecture): New fn.
(mips_after_parse_args): Rework. Remove -mcpu handling. -mipsN
is an alias for -march=mipsN. Don't change the ABI based on other
flags. Infer the register size from the ABI as well as the
architecture. Complain about more conflicting arguments.
Unify logic with GCC.
(s_mipsset): Don't change the ABI.
(mips_elf_final_processing): Check USE_E_MIPS_ABI_O32.
(mips_cpu_info_table): Remove Generic-MIPS* entries, keeping just
"mipsN"-type entries. Remove entries that vary only in the
manufacturer's prefix, or that have "000" replaced by "k".
Remove TARGET_CPU entries. Make r2000 entry use CPU_R3000.
(mips_strict_matching_cpu_name_p, mips_matching_cpu_name_p): New fns.
(mips_parse_cpu): New fn.
(mips_cpu_info_from_name, mips_cpu_info_from_cpu): Remove.
(mips_cpu_info_from_isa): Minor formatting tweak.
[gas/testsuite]
* gas/mips/mips-gp32-fp64.d,
* gas/mips/mips-gp32-fp64-pic.d: Add -mfp64.
2002-07-25 11:48:07 +02:00
|
|
|
|
mips_abi = N64_ABI;
|
2001-10-03 22:30:15 +02:00
|
|
|
|
if (! support_64bit_objects())
|
|
|
|
|
as_fatal (_("No compiled in support for 64 bit object file "
|
|
|
|
|
"format"));
|
|
|
|
|
}
|
|
|
|
|
else if (strcmp (arg, "eabi") == 0)
|
[gas/]
* doc/c-mips.texi: Remove -mcpu. Document -mabi.
* configure.in (MIPS_CPU_STRING_DEFAULT): New configuration macro.
(USE_E_MIPS_ABI_O32, MIPS_DEFAULT_64BIT): New configuration macros.
* configure, config.in: Regenerate.
* config/tc-mips.c (file_mips_abi): Rename to mips_abi.
(mips_set_options): Remove "abi" field.
(mips_opts): Update accordingly. Replace all uses of mips_opts.abi
with mips_abi.
(mips_cpu): Remove.
(mips_arch_string, mips_arch_info): New vars.
(mips_tune_string, mips_tune_info): New vars.
(ABI_NEEDS_32BIT_REGS, ABI_NEEDS_64BIT_REGS): New macros.
(HAVE_32BIT_GPRS, HAVE_32BIT_FPRS): Don't check the ABI.
(mips_isa_to_str, mips_cpu_to_str): Remove.
(mips_ip): If the selected architecture is a generic ISA rather
than a processor, only mention the ISA level in error messages.
(OPTION_MCPU): Remove.
(OPTION_FP64): New.
(md_longopts): Add -mfp64, remove -mcpu.
(mips_set_option_string): New fn.
(md_parse_option): Make -mipsN update file_mips_isa rather than
mips_opts.isa. Use mips_set_option_string to set -march or -mtune.
Don't let -mgp32 and -mfp32 change the ABI.
(show): Move to end of file. Constify string argument.
(md_show_usage): Move to the end of the file. Read available
architectures from mips_cpu_info_table.
(mips_set_architecture): New fn.
(mips_after_parse_args): Rework. Remove -mcpu handling. -mipsN
is an alias for -march=mipsN. Don't change the ABI based on other
flags. Infer the register size from the ABI as well as the
architecture. Complain about more conflicting arguments.
Unify logic with GCC.
(s_mipsset): Don't change the ABI.
(mips_elf_final_processing): Check USE_E_MIPS_ABI_O32.
(mips_cpu_info_table): Remove Generic-MIPS* entries, keeping just
"mipsN"-type entries. Remove entries that vary only in the
manufacturer's prefix, or that have "000" replaced by "k".
Remove TARGET_CPU entries. Make r2000 entry use CPU_R3000.
(mips_strict_matching_cpu_name_p, mips_matching_cpu_name_p): New fns.
(mips_parse_cpu): New fn.
(mips_cpu_info_from_name, mips_cpu_info_from_cpu): Remove.
(mips_cpu_info_from_isa): Minor formatting tweak.
[gas/testsuite]
* gas/mips/mips-gp32-fp64.d,
* gas/mips/mips-gp32-fp64-pic.d: Add -mfp64.
2002-07-25 11:48:07 +02:00
|
|
|
|
mips_abi = EABI_ABI;
|
2001-10-03 22:30:15 +02:00
|
|
|
|
else
|
2002-02-19 23:59:30 +01:00
|
|
|
|
{
|
|
|
|
|
as_fatal (_("invalid abi -mabi=%s"), arg);
|
|
|
|
|
return 0;
|
|
|
|
|
}
|
1999-05-03 09:29:11 +02:00
|
|
|
|
break;
|
2001-10-03 22:30:15 +02:00
|
|
|
|
#endif /* OBJ_ELF */
|
1999-05-03 09:29:11 +02:00
|
|
|
|
|
2000-02-21 21:00:33 +01:00
|
|
|
|
case OPTION_M7000_HILO_FIX:
|
2002-11-30 09:39:46 +01:00
|
|
|
|
mips_7000_hilo_fix = TRUE;
|
2000-02-21 21:00:33 +01:00
|
|
|
|
break;
|
|
|
|
|
|
2002-05-31 01:38:19 +02:00
|
|
|
|
case OPTION_MNO_7000_HILO_FIX:
|
2002-11-30 09:39:46 +01:00
|
|
|
|
mips_7000_hilo_fix = FALSE;
|
2000-02-21 21:00:33 +01:00
|
|
|
|
break;
|
|
|
|
|
|
2002-06-14 16:08:54 +02:00
|
|
|
|
#ifdef OBJ_ELF
|
|
|
|
|
case OPTION_MDEBUG:
|
2002-11-30 09:39:46 +01:00
|
|
|
|
mips_flag_mdebug = TRUE;
|
2002-06-14 16:08:54 +02:00
|
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
case OPTION_NO_MDEBUG:
|
2002-11-30 09:39:46 +01:00
|
|
|
|
mips_flag_mdebug = FALSE;
|
2002-06-14 16:08:54 +02:00
|
|
|
|
break;
|
2003-07-28 22:06:27 +02:00
|
|
|
|
|
|
|
|
|
case OPTION_PDR:
|
|
|
|
|
mips_flag_pdr = TRUE;
|
|
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
case OPTION_NO_PDR:
|
|
|
|
|
mips_flag_pdr = FALSE;
|
|
|
|
|
break;
|
2002-06-14 16:08:54 +02:00
|
|
|
|
#endif /* OBJ_ELF */
|
|
|
|
|
|
1999-05-03 09:29:11 +02:00
|
|
|
|
default:
|
|
|
|
|
return 0;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
return 1;
|
|
|
|
|
}
|
[gas/]
* doc/c-mips.texi: Remove -mcpu. Document -mabi.
* configure.in (MIPS_CPU_STRING_DEFAULT): New configuration macro.
(USE_E_MIPS_ABI_O32, MIPS_DEFAULT_64BIT): New configuration macros.
* configure, config.in: Regenerate.
* config/tc-mips.c (file_mips_abi): Rename to mips_abi.
(mips_set_options): Remove "abi" field.
(mips_opts): Update accordingly. Replace all uses of mips_opts.abi
with mips_abi.
(mips_cpu): Remove.
(mips_arch_string, mips_arch_info): New vars.
(mips_tune_string, mips_tune_info): New vars.
(ABI_NEEDS_32BIT_REGS, ABI_NEEDS_64BIT_REGS): New macros.
(HAVE_32BIT_GPRS, HAVE_32BIT_FPRS): Don't check the ABI.
(mips_isa_to_str, mips_cpu_to_str): Remove.
(mips_ip): If the selected architecture is a generic ISA rather
than a processor, only mention the ISA level in error messages.
(OPTION_MCPU): Remove.
(OPTION_FP64): New.
(md_longopts): Add -mfp64, remove -mcpu.
(mips_set_option_string): New fn.
(md_parse_option): Make -mipsN update file_mips_isa rather than
mips_opts.isa. Use mips_set_option_string to set -march or -mtune.
Don't let -mgp32 and -mfp32 change the ABI.
(show): Move to end of file. Constify string argument.
(md_show_usage): Move to the end of the file. Read available
architectures from mips_cpu_info_table.
(mips_set_architecture): New fn.
(mips_after_parse_args): Rework. Remove -mcpu handling. -mipsN
is an alias for -march=mipsN. Don't change the ABI based on other
flags. Infer the register size from the ABI as well as the
architecture. Complain about more conflicting arguments.
Unify logic with GCC.
(s_mipsset): Don't change the ABI.
(mips_elf_final_processing): Check USE_E_MIPS_ABI_O32.
(mips_cpu_info_table): Remove Generic-MIPS* entries, keeping just
"mipsN"-type entries. Remove entries that vary only in the
manufacturer's prefix, or that have "000" replaced by "k".
Remove TARGET_CPU entries. Make r2000 entry use CPU_R3000.
(mips_strict_matching_cpu_name_p, mips_matching_cpu_name_p): New fns.
(mips_parse_cpu): New fn.
(mips_cpu_info_from_name, mips_cpu_info_from_cpu): Remove.
(mips_cpu_info_from_isa): Minor formatting tweak.
[gas/testsuite]
* gas/mips/mips-gp32-fp64.d,
* gas/mips/mips-gp32-fp64-pic.d: Add -mfp64.
2002-07-25 11:48:07 +02:00
|
|
|
|
|
|
|
|
|
/* Set up globals to generate code for the ISA or processor
|
|
|
|
|
described by INFO. */
|
1999-05-03 09:29:11 +02:00
|
|
|
|
|
|
|
|
|
static void
|
2003-06-30 14:44:25 +02:00
|
|
|
|
mips_set_architecture (const struct mips_cpu_info *info)
|
1999-05-03 09:29:11 +02:00
|
|
|
|
{
|
[gas/]
* doc/c-mips.texi: Remove -mcpu. Document -mabi.
* configure.in (MIPS_CPU_STRING_DEFAULT): New configuration macro.
(USE_E_MIPS_ABI_O32, MIPS_DEFAULT_64BIT): New configuration macros.
* configure, config.in: Regenerate.
* config/tc-mips.c (file_mips_abi): Rename to mips_abi.
(mips_set_options): Remove "abi" field.
(mips_opts): Update accordingly. Replace all uses of mips_opts.abi
with mips_abi.
(mips_cpu): Remove.
(mips_arch_string, mips_arch_info): New vars.
(mips_tune_string, mips_tune_info): New vars.
(ABI_NEEDS_32BIT_REGS, ABI_NEEDS_64BIT_REGS): New macros.
(HAVE_32BIT_GPRS, HAVE_32BIT_FPRS): Don't check the ABI.
(mips_isa_to_str, mips_cpu_to_str): Remove.
(mips_ip): If the selected architecture is a generic ISA rather
than a processor, only mention the ISA level in error messages.
(OPTION_MCPU): Remove.
(OPTION_FP64): New.
(md_longopts): Add -mfp64, remove -mcpu.
(mips_set_option_string): New fn.
(md_parse_option): Make -mipsN update file_mips_isa rather than
mips_opts.isa. Use mips_set_option_string to set -march or -mtune.
Don't let -mgp32 and -mfp32 change the ABI.
(show): Move to end of file. Constify string argument.
(md_show_usage): Move to the end of the file. Read available
architectures from mips_cpu_info_table.
(mips_set_architecture): New fn.
(mips_after_parse_args): Rework. Remove -mcpu handling. -mipsN
is an alias for -march=mipsN. Don't change the ABI based on other
flags. Infer the register size from the ABI as well as the
architecture. Complain about more conflicting arguments.
Unify logic with GCC.
(s_mipsset): Don't change the ABI.
(mips_elf_final_processing): Check USE_E_MIPS_ABI_O32.
(mips_cpu_info_table): Remove Generic-MIPS* entries, keeping just
"mipsN"-type entries. Remove entries that vary only in the
manufacturer's prefix, or that have "000" replaced by "k".
Remove TARGET_CPU entries. Make r2000 entry use CPU_R3000.
(mips_strict_matching_cpu_name_p, mips_matching_cpu_name_p): New fns.
(mips_parse_cpu): New fn.
(mips_cpu_info_from_name, mips_cpu_info_from_cpu): Remove.
(mips_cpu_info_from_isa): Minor formatting tweak.
[gas/testsuite]
* gas/mips/mips-gp32-fp64.d,
* gas/mips/mips-gp32-fp64-pic.d: Add -mfp64.
2002-07-25 11:48:07 +02:00
|
|
|
|
if (info != 0)
|
1999-05-03 09:29:11 +02:00
|
|
|
|
{
|
2003-06-29 21:41:33 +02:00
|
|
|
|
file_mips_arch = info->cpu;
|
|
|
|
|
mips_opts.arch = info->cpu;
|
[gas/]
* doc/c-mips.texi: Remove -mcpu. Document -mabi.
* configure.in (MIPS_CPU_STRING_DEFAULT): New configuration macro.
(USE_E_MIPS_ABI_O32, MIPS_DEFAULT_64BIT): New configuration macros.
* configure, config.in: Regenerate.
* config/tc-mips.c (file_mips_abi): Rename to mips_abi.
(mips_set_options): Remove "abi" field.
(mips_opts): Update accordingly. Replace all uses of mips_opts.abi
with mips_abi.
(mips_cpu): Remove.
(mips_arch_string, mips_arch_info): New vars.
(mips_tune_string, mips_tune_info): New vars.
(ABI_NEEDS_32BIT_REGS, ABI_NEEDS_64BIT_REGS): New macros.
(HAVE_32BIT_GPRS, HAVE_32BIT_FPRS): Don't check the ABI.
(mips_isa_to_str, mips_cpu_to_str): Remove.
(mips_ip): If the selected architecture is a generic ISA rather
than a processor, only mention the ISA level in error messages.
(OPTION_MCPU): Remove.
(OPTION_FP64): New.
(md_longopts): Add -mfp64, remove -mcpu.
(mips_set_option_string): New fn.
(md_parse_option): Make -mipsN update file_mips_isa rather than
mips_opts.isa. Use mips_set_option_string to set -march or -mtune.
Don't let -mgp32 and -mfp32 change the ABI.
(show): Move to end of file. Constify string argument.
(md_show_usage): Move to the end of the file. Read available
architectures from mips_cpu_info_table.
(mips_set_architecture): New fn.
(mips_after_parse_args): Rework. Remove -mcpu handling. -mipsN
is an alias for -march=mipsN. Don't change the ABI based on other
flags. Infer the register size from the ABI as well as the
architecture. Complain about more conflicting arguments.
Unify logic with GCC.
(s_mipsset): Don't change the ABI.
(mips_elf_final_processing): Check USE_E_MIPS_ABI_O32.
(mips_cpu_info_table): Remove Generic-MIPS* entries, keeping just
"mipsN"-type entries. Remove entries that vary only in the
manufacturer's prefix, or that have "000" replaced by "k".
Remove TARGET_CPU entries. Make r2000 entry use CPU_R3000.
(mips_strict_matching_cpu_name_p, mips_matching_cpu_name_p): New fns.
(mips_parse_cpu): New fn.
(mips_cpu_info_from_name, mips_cpu_info_from_cpu): Remove.
(mips_cpu_info_from_isa): Minor formatting tweak.
[gas/testsuite]
* gas/mips/mips-gp32-fp64.d,
* gas/mips/mips-gp32-fp64-pic.d: Add -mfp64.
2002-07-25 11:48:07 +02:00
|
|
|
|
mips_opts.isa = info->isa;
|
1999-05-03 09:29:11 +02:00
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
[gas/]
* doc/c-mips.texi: Remove -mcpu. Document -mabi.
* configure.in (MIPS_CPU_STRING_DEFAULT): New configuration macro.
(USE_E_MIPS_ABI_O32, MIPS_DEFAULT_64BIT): New configuration macros.
* configure, config.in: Regenerate.
* config/tc-mips.c (file_mips_abi): Rename to mips_abi.
(mips_set_options): Remove "abi" field.
(mips_opts): Update accordingly. Replace all uses of mips_opts.abi
with mips_abi.
(mips_cpu): Remove.
(mips_arch_string, mips_arch_info): New vars.
(mips_tune_string, mips_tune_info): New vars.
(ABI_NEEDS_32BIT_REGS, ABI_NEEDS_64BIT_REGS): New macros.
(HAVE_32BIT_GPRS, HAVE_32BIT_FPRS): Don't check the ABI.
(mips_isa_to_str, mips_cpu_to_str): Remove.
(mips_ip): If the selected architecture is a generic ISA rather
than a processor, only mention the ISA level in error messages.
(OPTION_MCPU): Remove.
(OPTION_FP64): New.
(md_longopts): Add -mfp64, remove -mcpu.
(mips_set_option_string): New fn.
(md_parse_option): Make -mipsN update file_mips_isa rather than
mips_opts.isa. Use mips_set_option_string to set -march or -mtune.
Don't let -mgp32 and -mfp32 change the ABI.
(show): Move to end of file. Constify string argument.
(md_show_usage): Move to the end of the file. Read available
architectures from mips_cpu_info_table.
(mips_set_architecture): New fn.
(mips_after_parse_args): Rework. Remove -mcpu handling. -mipsN
is an alias for -march=mipsN. Don't change the ABI based on other
flags. Infer the register size from the ABI as well as the
architecture. Complain about more conflicting arguments.
Unify logic with GCC.
(s_mipsset): Don't change the ABI.
(mips_elf_final_processing): Check USE_E_MIPS_ABI_O32.
(mips_cpu_info_table): Remove Generic-MIPS* entries, keeping just
"mipsN"-type entries. Remove entries that vary only in the
manufacturer's prefix, or that have "000" replaced by "k".
Remove TARGET_CPU entries. Make r2000 entry use CPU_R3000.
(mips_strict_matching_cpu_name_p, mips_matching_cpu_name_p): New fns.
(mips_parse_cpu): New fn.
(mips_cpu_info_from_name, mips_cpu_info_from_cpu): Remove.
(mips_cpu_info_from_isa): Minor formatting tweak.
[gas/testsuite]
* gas/mips/mips-gp32-fp64.d,
* gas/mips/mips-gp32-fp64-pic.d: Add -mfp64.
2002-07-25 11:48:07 +02:00
|
|
|
|
/* Likewise for tuning. */
|
1999-05-03 09:29:11 +02:00
|
|
|
|
|
[gas/]
* doc/c-mips.texi: Remove -mcpu. Document -mabi.
* configure.in (MIPS_CPU_STRING_DEFAULT): New configuration macro.
(USE_E_MIPS_ABI_O32, MIPS_DEFAULT_64BIT): New configuration macros.
* configure, config.in: Regenerate.
* config/tc-mips.c (file_mips_abi): Rename to mips_abi.
(mips_set_options): Remove "abi" field.
(mips_opts): Update accordingly. Replace all uses of mips_opts.abi
with mips_abi.
(mips_cpu): Remove.
(mips_arch_string, mips_arch_info): New vars.
(mips_tune_string, mips_tune_info): New vars.
(ABI_NEEDS_32BIT_REGS, ABI_NEEDS_64BIT_REGS): New macros.
(HAVE_32BIT_GPRS, HAVE_32BIT_FPRS): Don't check the ABI.
(mips_isa_to_str, mips_cpu_to_str): Remove.
(mips_ip): If the selected architecture is a generic ISA rather
than a processor, only mention the ISA level in error messages.
(OPTION_MCPU): Remove.
(OPTION_FP64): New.
(md_longopts): Add -mfp64, remove -mcpu.
(mips_set_option_string): New fn.
(md_parse_option): Make -mipsN update file_mips_isa rather than
mips_opts.isa. Use mips_set_option_string to set -march or -mtune.
Don't let -mgp32 and -mfp32 change the ABI.
(show): Move to end of file. Constify string argument.
(md_show_usage): Move to the end of the file. Read available
architectures from mips_cpu_info_table.
(mips_set_architecture): New fn.
(mips_after_parse_args): Rework. Remove -mcpu handling. -mipsN
is an alias for -march=mipsN. Don't change the ABI based on other
flags. Infer the register size from the ABI as well as the
architecture. Complain about more conflicting arguments.
Unify logic with GCC.
(s_mipsset): Don't change the ABI.
(mips_elf_final_processing): Check USE_E_MIPS_ABI_O32.
(mips_cpu_info_table): Remove Generic-MIPS* entries, keeping just
"mipsN"-type entries. Remove entries that vary only in the
manufacturer's prefix, or that have "000" replaced by "k".
Remove TARGET_CPU entries. Make r2000 entry use CPU_R3000.
(mips_strict_matching_cpu_name_p, mips_matching_cpu_name_p): New fns.
(mips_parse_cpu): New fn.
(mips_cpu_info_from_name, mips_cpu_info_from_cpu): Remove.
(mips_cpu_info_from_isa): Minor formatting tweak.
[gas/testsuite]
* gas/mips/mips-gp32-fp64.d,
* gas/mips/mips-gp32-fp64-pic.d: Add -mfp64.
2002-07-25 11:48:07 +02:00
|
|
|
|
static void
|
2003-06-30 14:44:25 +02:00
|
|
|
|
mips_set_tune (const struct mips_cpu_info *info)
|
[gas/]
* doc/c-mips.texi: Remove -mcpu. Document -mabi.
* configure.in (MIPS_CPU_STRING_DEFAULT): New configuration macro.
(USE_E_MIPS_ABI_O32, MIPS_DEFAULT_64BIT): New configuration macros.
* configure, config.in: Regenerate.
* config/tc-mips.c (file_mips_abi): Rename to mips_abi.
(mips_set_options): Remove "abi" field.
(mips_opts): Update accordingly. Replace all uses of mips_opts.abi
with mips_abi.
(mips_cpu): Remove.
(mips_arch_string, mips_arch_info): New vars.
(mips_tune_string, mips_tune_info): New vars.
(ABI_NEEDS_32BIT_REGS, ABI_NEEDS_64BIT_REGS): New macros.
(HAVE_32BIT_GPRS, HAVE_32BIT_FPRS): Don't check the ABI.
(mips_isa_to_str, mips_cpu_to_str): Remove.
(mips_ip): If the selected architecture is a generic ISA rather
than a processor, only mention the ISA level in error messages.
(OPTION_MCPU): Remove.
(OPTION_FP64): New.
(md_longopts): Add -mfp64, remove -mcpu.
(mips_set_option_string): New fn.
(md_parse_option): Make -mipsN update file_mips_isa rather than
mips_opts.isa. Use mips_set_option_string to set -march or -mtune.
Don't let -mgp32 and -mfp32 change the ABI.
(show): Move to end of file. Constify string argument.
(md_show_usage): Move to the end of the file. Read available
architectures from mips_cpu_info_table.
(mips_set_architecture): New fn.
(mips_after_parse_args): Rework. Remove -mcpu handling. -mipsN
is an alias for -march=mipsN. Don't change the ABI based on other
flags. Infer the register size from the ABI as well as the
architecture. Complain about more conflicting arguments.
Unify logic with GCC.
(s_mipsset): Don't change the ABI.
(mips_elf_final_processing): Check USE_E_MIPS_ABI_O32.
(mips_cpu_info_table): Remove Generic-MIPS* entries, keeping just
"mipsN"-type entries. Remove entries that vary only in the
manufacturer's prefix, or that have "000" replaced by "k".
Remove TARGET_CPU entries. Make r2000 entry use CPU_R3000.
(mips_strict_matching_cpu_name_p, mips_matching_cpu_name_p): New fns.
(mips_parse_cpu): New fn.
(mips_cpu_info_from_name, mips_cpu_info_from_cpu): Remove.
(mips_cpu_info_from_isa): Minor formatting tweak.
[gas/testsuite]
* gas/mips/mips-gp32-fp64.d,
* gas/mips/mips-gp32-fp64-pic.d: Add -mfp64.
2002-07-25 11:48:07 +02:00
|
|
|
|
{
|
|
|
|
|
if (info != 0)
|
2003-06-29 21:41:33 +02:00
|
|
|
|
mips_tune = info->cpu;
|
[gas/]
* doc/c-mips.texi: Remove -mcpu. Document -mabi.
* configure.in (MIPS_CPU_STRING_DEFAULT): New configuration macro.
(USE_E_MIPS_ABI_O32, MIPS_DEFAULT_64BIT): New configuration macros.
* configure, config.in: Regenerate.
* config/tc-mips.c (file_mips_abi): Rename to mips_abi.
(mips_set_options): Remove "abi" field.
(mips_opts): Update accordingly. Replace all uses of mips_opts.abi
with mips_abi.
(mips_cpu): Remove.
(mips_arch_string, mips_arch_info): New vars.
(mips_tune_string, mips_tune_info): New vars.
(ABI_NEEDS_32BIT_REGS, ABI_NEEDS_64BIT_REGS): New macros.
(HAVE_32BIT_GPRS, HAVE_32BIT_FPRS): Don't check the ABI.
(mips_isa_to_str, mips_cpu_to_str): Remove.
(mips_ip): If the selected architecture is a generic ISA rather
than a processor, only mention the ISA level in error messages.
(OPTION_MCPU): Remove.
(OPTION_FP64): New.
(md_longopts): Add -mfp64, remove -mcpu.
(mips_set_option_string): New fn.
(md_parse_option): Make -mipsN update file_mips_isa rather than
mips_opts.isa. Use mips_set_option_string to set -march or -mtune.
Don't let -mgp32 and -mfp32 change the ABI.
(show): Move to end of file. Constify string argument.
(md_show_usage): Move to the end of the file. Read available
architectures from mips_cpu_info_table.
(mips_set_architecture): New fn.
(mips_after_parse_args): Rework. Remove -mcpu handling. -mipsN
is an alias for -march=mipsN. Don't change the ABI based on other
flags. Infer the register size from the ABI as well as the
architecture. Complain about more conflicting arguments.
Unify logic with GCC.
(s_mipsset): Don't change the ABI.
(mips_elf_final_processing): Check USE_E_MIPS_ABI_O32.
(mips_cpu_info_table): Remove Generic-MIPS* entries, keeping just
"mipsN"-type entries. Remove entries that vary only in the
manufacturer's prefix, or that have "000" replaced by "k".
Remove TARGET_CPU entries. Make r2000 entry use CPU_R3000.
(mips_strict_matching_cpu_name_p, mips_matching_cpu_name_p): New fns.
(mips_parse_cpu): New fn.
(mips_cpu_info_from_name, mips_cpu_info_from_cpu): Remove.
(mips_cpu_info_from_isa): Minor formatting tweak.
[gas/testsuite]
* gas/mips/mips-gp32-fp64.d,
* gas/mips/mips-gp32-fp64-pic.d: Add -mfp64.
2002-07-25 11:48:07 +02:00
|
|
|
|
}
|
2002-04-22 23:21:06 +02:00
|
|
|
|
|
2001-12-04 14:27:56 +01:00
|
|
|
|
|
1999-05-03 09:29:11 +02:00
|
|
|
|
void
|
2003-06-30 14:44:25 +02:00
|
|
|
|
mips_after_parse_args (void)
|
2002-06-04 18:33:56 +02:00
|
|
|
|
{
|
2003-06-29 21:41:33 +02:00
|
|
|
|
const struct mips_cpu_info *arch_info = 0;
|
|
|
|
|
const struct mips_cpu_info *tune_info = 0;
|
|
|
|
|
|
2002-06-04 18:33:56 +02:00
|
|
|
|
/* GP relative stuff not working for PE */
|
|
|
|
|
if (strncmp (TARGET_OS, "pe", 2) == 0
|
|
|
|
|
&& g_switch_value != 0)
|
|
|
|
|
{
|
|
|
|
|
if (g_switch_seen)
|
|
|
|
|
as_bad (_("-G not supported in this configuration."));
|
|
|
|
|
g_switch_value = 0;
|
|
|
|
|
}
|
|
|
|
|
|
2003-05-07 07:10:45 +02:00
|
|
|
|
if (mips_abi == NO_ABI)
|
|
|
|
|
mips_abi = MIPS_DEFAULT_ABI;
|
|
|
|
|
|
2002-07-25 13:07:47 +02:00
|
|
|
|
/* The following code determines the architecture and register size.
|
|
|
|
|
Similar code was added to GCC 3.3 (see override_options() in
|
|
|
|
|
config/mips/mips.c). The GAS and GCC code should be kept in sync
|
|
|
|
|
as much as possible. */
|
2002-06-04 18:33:56 +02:00
|
|
|
|
|
[gas/]
* doc/c-mips.texi: Remove -mcpu. Document -mabi.
* configure.in (MIPS_CPU_STRING_DEFAULT): New configuration macro.
(USE_E_MIPS_ABI_O32, MIPS_DEFAULT_64BIT): New configuration macros.
* configure, config.in: Regenerate.
* config/tc-mips.c (file_mips_abi): Rename to mips_abi.
(mips_set_options): Remove "abi" field.
(mips_opts): Update accordingly. Replace all uses of mips_opts.abi
with mips_abi.
(mips_cpu): Remove.
(mips_arch_string, mips_arch_info): New vars.
(mips_tune_string, mips_tune_info): New vars.
(ABI_NEEDS_32BIT_REGS, ABI_NEEDS_64BIT_REGS): New macros.
(HAVE_32BIT_GPRS, HAVE_32BIT_FPRS): Don't check the ABI.
(mips_isa_to_str, mips_cpu_to_str): Remove.
(mips_ip): If the selected architecture is a generic ISA rather
than a processor, only mention the ISA level in error messages.
(OPTION_MCPU): Remove.
(OPTION_FP64): New.
(md_longopts): Add -mfp64, remove -mcpu.
(mips_set_option_string): New fn.
(md_parse_option): Make -mipsN update file_mips_isa rather than
mips_opts.isa. Use mips_set_option_string to set -march or -mtune.
Don't let -mgp32 and -mfp32 change the ABI.
(show): Move to end of file. Constify string argument.
(md_show_usage): Move to the end of the file. Read available
architectures from mips_cpu_info_table.
(mips_set_architecture): New fn.
(mips_after_parse_args): Rework. Remove -mcpu handling. -mipsN
is an alias for -march=mipsN. Don't change the ABI based on other
flags. Infer the register size from the ABI as well as the
architecture. Complain about more conflicting arguments.
Unify logic with GCC.
(s_mipsset): Don't change the ABI.
(mips_elf_final_processing): Check USE_E_MIPS_ABI_O32.
(mips_cpu_info_table): Remove Generic-MIPS* entries, keeping just
"mipsN"-type entries. Remove entries that vary only in the
manufacturer's prefix, or that have "000" replaced by "k".
Remove TARGET_CPU entries. Make r2000 entry use CPU_R3000.
(mips_strict_matching_cpu_name_p, mips_matching_cpu_name_p): New fns.
(mips_parse_cpu): New fn.
(mips_cpu_info_from_name, mips_cpu_info_from_cpu): Remove.
(mips_cpu_info_from_isa): Minor formatting tweak.
[gas/testsuite]
* gas/mips/mips-gp32-fp64.d,
* gas/mips/mips-gp32-fp64-pic.d: Add -mfp64.
2002-07-25 11:48:07 +02:00
|
|
|
|
if (mips_arch_string != 0)
|
2003-06-29 21:41:33 +02:00
|
|
|
|
arch_info = mips_parse_cpu ("-march", mips_arch_string);
|
2002-06-04 18:33:56 +02:00
|
|
|
|
|
[gas/]
* doc/c-mips.texi: Remove -mcpu. Document -mabi.
* configure.in (MIPS_CPU_STRING_DEFAULT): New configuration macro.
(USE_E_MIPS_ABI_O32, MIPS_DEFAULT_64BIT): New configuration macros.
* configure, config.in: Regenerate.
* config/tc-mips.c (file_mips_abi): Rename to mips_abi.
(mips_set_options): Remove "abi" field.
(mips_opts): Update accordingly. Replace all uses of mips_opts.abi
with mips_abi.
(mips_cpu): Remove.
(mips_arch_string, mips_arch_info): New vars.
(mips_tune_string, mips_tune_info): New vars.
(ABI_NEEDS_32BIT_REGS, ABI_NEEDS_64BIT_REGS): New macros.
(HAVE_32BIT_GPRS, HAVE_32BIT_FPRS): Don't check the ABI.
(mips_isa_to_str, mips_cpu_to_str): Remove.
(mips_ip): If the selected architecture is a generic ISA rather
than a processor, only mention the ISA level in error messages.
(OPTION_MCPU): Remove.
(OPTION_FP64): New.
(md_longopts): Add -mfp64, remove -mcpu.
(mips_set_option_string): New fn.
(md_parse_option): Make -mipsN update file_mips_isa rather than
mips_opts.isa. Use mips_set_option_string to set -march or -mtune.
Don't let -mgp32 and -mfp32 change the ABI.
(show): Move to end of file. Constify string argument.
(md_show_usage): Move to the end of the file. Read available
architectures from mips_cpu_info_table.
(mips_set_architecture): New fn.
(mips_after_parse_args): Rework. Remove -mcpu handling. -mipsN
is an alias for -march=mipsN. Don't change the ABI based on other
flags. Infer the register size from the ABI as well as the
architecture. Complain about more conflicting arguments.
Unify logic with GCC.
(s_mipsset): Don't change the ABI.
(mips_elf_final_processing): Check USE_E_MIPS_ABI_O32.
(mips_cpu_info_table): Remove Generic-MIPS* entries, keeping just
"mipsN"-type entries. Remove entries that vary only in the
manufacturer's prefix, or that have "000" replaced by "k".
Remove TARGET_CPU entries. Make r2000 entry use CPU_R3000.
(mips_strict_matching_cpu_name_p, mips_matching_cpu_name_p): New fns.
(mips_parse_cpu): New fn.
(mips_cpu_info_from_name, mips_cpu_info_from_cpu): Remove.
(mips_cpu_info_from_isa): Minor formatting tweak.
[gas/testsuite]
* gas/mips/mips-gp32-fp64.d,
* gas/mips/mips-gp32-fp64-pic.d: Add -mfp64.
2002-07-25 11:48:07 +02:00
|
|
|
|
if (file_mips_isa != ISA_UNKNOWN)
|
2002-06-04 18:33:56 +02:00
|
|
|
|
{
|
[gas/]
* doc/c-mips.texi: Remove -mcpu. Document -mabi.
* configure.in (MIPS_CPU_STRING_DEFAULT): New configuration macro.
(USE_E_MIPS_ABI_O32, MIPS_DEFAULT_64BIT): New configuration macros.
* configure, config.in: Regenerate.
* config/tc-mips.c (file_mips_abi): Rename to mips_abi.
(mips_set_options): Remove "abi" field.
(mips_opts): Update accordingly. Replace all uses of mips_opts.abi
with mips_abi.
(mips_cpu): Remove.
(mips_arch_string, mips_arch_info): New vars.
(mips_tune_string, mips_tune_info): New vars.
(ABI_NEEDS_32BIT_REGS, ABI_NEEDS_64BIT_REGS): New macros.
(HAVE_32BIT_GPRS, HAVE_32BIT_FPRS): Don't check the ABI.
(mips_isa_to_str, mips_cpu_to_str): Remove.
(mips_ip): If the selected architecture is a generic ISA rather
than a processor, only mention the ISA level in error messages.
(OPTION_MCPU): Remove.
(OPTION_FP64): New.
(md_longopts): Add -mfp64, remove -mcpu.
(mips_set_option_string): New fn.
(md_parse_option): Make -mipsN update file_mips_isa rather than
mips_opts.isa. Use mips_set_option_string to set -march or -mtune.
Don't let -mgp32 and -mfp32 change the ABI.
(show): Move to end of file. Constify string argument.
(md_show_usage): Move to the end of the file. Read available
architectures from mips_cpu_info_table.
(mips_set_architecture): New fn.
(mips_after_parse_args): Rework. Remove -mcpu handling. -mipsN
is an alias for -march=mipsN. Don't change the ABI based on other
flags. Infer the register size from the ABI as well as the
architecture. Complain about more conflicting arguments.
Unify logic with GCC.
(s_mipsset): Don't change the ABI.
(mips_elf_final_processing): Check USE_E_MIPS_ABI_O32.
(mips_cpu_info_table): Remove Generic-MIPS* entries, keeping just
"mipsN"-type entries. Remove entries that vary only in the
manufacturer's prefix, or that have "000" replaced by "k".
Remove TARGET_CPU entries. Make r2000 entry use CPU_R3000.
(mips_strict_matching_cpu_name_p, mips_matching_cpu_name_p): New fns.
(mips_parse_cpu): New fn.
(mips_cpu_info_from_name, mips_cpu_info_from_cpu): Remove.
(mips_cpu_info_from_isa): Minor formatting tweak.
[gas/testsuite]
* gas/mips/mips-gp32-fp64.d,
* gas/mips/mips-gp32-fp64-pic.d: Add -mfp64.
2002-07-25 11:48:07 +02:00
|
|
|
|
/* Handle -mipsN. At this point, file_mips_isa contains the
|
2003-06-29 21:41:33 +02:00
|
|
|
|
ISA level specified by -mipsN, while arch_info->isa contains
|
[gas/]
* doc/c-mips.texi: Remove -mcpu. Document -mabi.
* configure.in (MIPS_CPU_STRING_DEFAULT): New configuration macro.
(USE_E_MIPS_ABI_O32, MIPS_DEFAULT_64BIT): New configuration macros.
* configure, config.in: Regenerate.
* config/tc-mips.c (file_mips_abi): Rename to mips_abi.
(mips_set_options): Remove "abi" field.
(mips_opts): Update accordingly. Replace all uses of mips_opts.abi
with mips_abi.
(mips_cpu): Remove.
(mips_arch_string, mips_arch_info): New vars.
(mips_tune_string, mips_tune_info): New vars.
(ABI_NEEDS_32BIT_REGS, ABI_NEEDS_64BIT_REGS): New macros.
(HAVE_32BIT_GPRS, HAVE_32BIT_FPRS): Don't check the ABI.
(mips_isa_to_str, mips_cpu_to_str): Remove.
(mips_ip): If the selected architecture is a generic ISA rather
than a processor, only mention the ISA level in error messages.
(OPTION_MCPU): Remove.
(OPTION_FP64): New.
(md_longopts): Add -mfp64, remove -mcpu.
(mips_set_option_string): New fn.
(md_parse_option): Make -mipsN update file_mips_isa rather than
mips_opts.isa. Use mips_set_option_string to set -march or -mtune.
Don't let -mgp32 and -mfp32 change the ABI.
(show): Move to end of file. Constify string argument.
(md_show_usage): Move to the end of the file. Read available
architectures from mips_cpu_info_table.
(mips_set_architecture): New fn.
(mips_after_parse_args): Rework. Remove -mcpu handling. -mipsN
is an alias for -march=mipsN. Don't change the ABI based on other
flags. Infer the register size from the ABI as well as the
architecture. Complain about more conflicting arguments.
Unify logic with GCC.
(s_mipsset): Don't change the ABI.
(mips_elf_final_processing): Check USE_E_MIPS_ABI_O32.
(mips_cpu_info_table): Remove Generic-MIPS* entries, keeping just
"mipsN"-type entries. Remove entries that vary only in the
manufacturer's prefix, or that have "000" replaced by "k".
Remove TARGET_CPU entries. Make r2000 entry use CPU_R3000.
(mips_strict_matching_cpu_name_p, mips_matching_cpu_name_p): New fns.
(mips_parse_cpu): New fn.
(mips_cpu_info_from_name, mips_cpu_info_from_cpu): Remove.
(mips_cpu_info_from_isa): Minor formatting tweak.
[gas/testsuite]
* gas/mips/mips-gp32-fp64.d,
* gas/mips/mips-gp32-fp64-pic.d: Add -mfp64.
2002-07-25 11:48:07 +02:00
|
|
|
|
the -march selection (if any). */
|
2003-06-29 21:41:33 +02:00
|
|
|
|
if (arch_info != 0)
|
2002-06-04 18:33:56 +02:00
|
|
|
|
{
|
[gas/]
* doc/c-mips.texi: Remove -mcpu. Document -mabi.
* configure.in (MIPS_CPU_STRING_DEFAULT): New configuration macro.
(USE_E_MIPS_ABI_O32, MIPS_DEFAULT_64BIT): New configuration macros.
* configure, config.in: Regenerate.
* config/tc-mips.c (file_mips_abi): Rename to mips_abi.
(mips_set_options): Remove "abi" field.
(mips_opts): Update accordingly. Replace all uses of mips_opts.abi
with mips_abi.
(mips_cpu): Remove.
(mips_arch_string, mips_arch_info): New vars.
(mips_tune_string, mips_tune_info): New vars.
(ABI_NEEDS_32BIT_REGS, ABI_NEEDS_64BIT_REGS): New macros.
(HAVE_32BIT_GPRS, HAVE_32BIT_FPRS): Don't check the ABI.
(mips_isa_to_str, mips_cpu_to_str): Remove.
(mips_ip): If the selected architecture is a generic ISA rather
than a processor, only mention the ISA level in error messages.
(OPTION_MCPU): Remove.
(OPTION_FP64): New.
(md_longopts): Add -mfp64, remove -mcpu.
(mips_set_option_string): New fn.
(md_parse_option): Make -mipsN update file_mips_isa rather than
mips_opts.isa. Use mips_set_option_string to set -march or -mtune.
Don't let -mgp32 and -mfp32 change the ABI.
(show): Move to end of file. Constify string argument.
(md_show_usage): Move to the end of the file. Read available
architectures from mips_cpu_info_table.
(mips_set_architecture): New fn.
(mips_after_parse_args): Rework. Remove -mcpu handling. -mipsN
is an alias for -march=mipsN. Don't change the ABI based on other
flags. Infer the register size from the ABI as well as the
architecture. Complain about more conflicting arguments.
Unify logic with GCC.
(s_mipsset): Don't change the ABI.
(mips_elf_final_processing): Check USE_E_MIPS_ABI_O32.
(mips_cpu_info_table): Remove Generic-MIPS* entries, keeping just
"mipsN"-type entries. Remove entries that vary only in the
manufacturer's prefix, or that have "000" replaced by "k".
Remove TARGET_CPU entries. Make r2000 entry use CPU_R3000.
(mips_strict_matching_cpu_name_p, mips_matching_cpu_name_p): New fns.
(mips_parse_cpu): New fn.
(mips_cpu_info_from_name, mips_cpu_info_from_cpu): Remove.
(mips_cpu_info_from_isa): Minor formatting tweak.
[gas/testsuite]
* gas/mips/mips-gp32-fp64.d,
* gas/mips/mips-gp32-fp64-pic.d: Add -mfp64.
2002-07-25 11:48:07 +02:00
|
|
|
|
/* -march takes precedence over -mipsN, since it is more descriptive.
|
|
|
|
|
There's no harm in specifying both as long as the ISA levels
|
|
|
|
|
are the same. */
|
2003-06-29 21:41:33 +02:00
|
|
|
|
if (file_mips_isa != arch_info->isa)
|
[gas/]
* doc/c-mips.texi: Remove -mcpu. Document -mabi.
* configure.in (MIPS_CPU_STRING_DEFAULT): New configuration macro.
(USE_E_MIPS_ABI_O32, MIPS_DEFAULT_64BIT): New configuration macros.
* configure, config.in: Regenerate.
* config/tc-mips.c (file_mips_abi): Rename to mips_abi.
(mips_set_options): Remove "abi" field.
(mips_opts): Update accordingly. Replace all uses of mips_opts.abi
with mips_abi.
(mips_cpu): Remove.
(mips_arch_string, mips_arch_info): New vars.
(mips_tune_string, mips_tune_info): New vars.
(ABI_NEEDS_32BIT_REGS, ABI_NEEDS_64BIT_REGS): New macros.
(HAVE_32BIT_GPRS, HAVE_32BIT_FPRS): Don't check the ABI.
(mips_isa_to_str, mips_cpu_to_str): Remove.
(mips_ip): If the selected architecture is a generic ISA rather
than a processor, only mention the ISA level in error messages.
(OPTION_MCPU): Remove.
(OPTION_FP64): New.
(md_longopts): Add -mfp64, remove -mcpu.
(mips_set_option_string): New fn.
(md_parse_option): Make -mipsN update file_mips_isa rather than
mips_opts.isa. Use mips_set_option_string to set -march or -mtune.
Don't let -mgp32 and -mfp32 change the ABI.
(show): Move to end of file. Constify string argument.
(md_show_usage): Move to the end of the file. Read available
architectures from mips_cpu_info_table.
(mips_set_architecture): New fn.
(mips_after_parse_args): Rework. Remove -mcpu handling. -mipsN
is an alias for -march=mipsN. Don't change the ABI based on other
flags. Infer the register size from the ABI as well as the
architecture. Complain about more conflicting arguments.
Unify logic with GCC.
(s_mipsset): Don't change the ABI.
(mips_elf_final_processing): Check USE_E_MIPS_ABI_O32.
(mips_cpu_info_table): Remove Generic-MIPS* entries, keeping just
"mipsN"-type entries. Remove entries that vary only in the
manufacturer's prefix, or that have "000" replaced by "k".
Remove TARGET_CPU entries. Make r2000 entry use CPU_R3000.
(mips_strict_matching_cpu_name_p, mips_matching_cpu_name_p): New fns.
(mips_parse_cpu): New fn.
(mips_cpu_info_from_name, mips_cpu_info_from_cpu): Remove.
(mips_cpu_info_from_isa): Minor formatting tweak.
[gas/testsuite]
* gas/mips/mips-gp32-fp64.d,
* gas/mips/mips-gp32-fp64-pic.d: Add -mfp64.
2002-07-25 11:48:07 +02:00
|
|
|
|
as_bad (_("-%s conflicts with the other architecture options, which imply -%s"),
|
|
|
|
|
mips_cpu_info_from_isa (file_mips_isa)->name,
|
2003-06-29 21:41:33 +02:00
|
|
|
|
mips_cpu_info_from_isa (arch_info->isa)->name);
|
2002-06-04 18:33:56 +02:00
|
|
|
|
}
|
[gas/]
* doc/c-mips.texi: Remove -mcpu. Document -mabi.
* configure.in (MIPS_CPU_STRING_DEFAULT): New configuration macro.
(USE_E_MIPS_ABI_O32, MIPS_DEFAULT_64BIT): New configuration macros.
* configure, config.in: Regenerate.
* config/tc-mips.c (file_mips_abi): Rename to mips_abi.
(mips_set_options): Remove "abi" field.
(mips_opts): Update accordingly. Replace all uses of mips_opts.abi
with mips_abi.
(mips_cpu): Remove.
(mips_arch_string, mips_arch_info): New vars.
(mips_tune_string, mips_tune_info): New vars.
(ABI_NEEDS_32BIT_REGS, ABI_NEEDS_64BIT_REGS): New macros.
(HAVE_32BIT_GPRS, HAVE_32BIT_FPRS): Don't check the ABI.
(mips_isa_to_str, mips_cpu_to_str): Remove.
(mips_ip): If the selected architecture is a generic ISA rather
than a processor, only mention the ISA level in error messages.
(OPTION_MCPU): Remove.
(OPTION_FP64): New.
(md_longopts): Add -mfp64, remove -mcpu.
(mips_set_option_string): New fn.
(md_parse_option): Make -mipsN update file_mips_isa rather than
mips_opts.isa. Use mips_set_option_string to set -march or -mtune.
Don't let -mgp32 and -mfp32 change the ABI.
(show): Move to end of file. Constify string argument.
(md_show_usage): Move to the end of the file. Read available
architectures from mips_cpu_info_table.
(mips_set_architecture): New fn.
(mips_after_parse_args): Rework. Remove -mcpu handling. -mipsN
is an alias for -march=mipsN. Don't change the ABI based on other
flags. Infer the register size from the ABI as well as the
architecture. Complain about more conflicting arguments.
Unify logic with GCC.
(s_mipsset): Don't change the ABI.
(mips_elf_final_processing): Check USE_E_MIPS_ABI_O32.
(mips_cpu_info_table): Remove Generic-MIPS* entries, keeping just
"mipsN"-type entries. Remove entries that vary only in the
manufacturer's prefix, or that have "000" replaced by "k".
Remove TARGET_CPU entries. Make r2000 entry use CPU_R3000.
(mips_strict_matching_cpu_name_p, mips_matching_cpu_name_p): New fns.
(mips_parse_cpu): New fn.
(mips_cpu_info_from_name, mips_cpu_info_from_cpu): Remove.
(mips_cpu_info_from_isa): Minor formatting tweak.
[gas/testsuite]
* gas/mips/mips-gp32-fp64.d,
* gas/mips/mips-gp32-fp64-pic.d: Add -mfp64.
2002-07-25 11:48:07 +02:00
|
|
|
|
else
|
2003-06-29 21:41:33 +02:00
|
|
|
|
arch_info = mips_cpu_info_from_isa (file_mips_isa);
|
2002-06-04 18:33:56 +02:00
|
|
|
|
}
|
|
|
|
|
|
2003-06-29 21:41:33 +02:00
|
|
|
|
if (arch_info == 0)
|
|
|
|
|
arch_info = mips_parse_cpu ("default CPU", MIPS_CPU_STRING_DEFAULT);
|
2002-06-04 18:33:56 +02:00
|
|
|
|
|
2003-06-29 21:41:33 +02:00
|
|
|
|
if (ABI_NEEDS_64BIT_REGS (mips_abi) && !ISA_HAS_64BIT_REGS (arch_info->isa))
|
[gas/]
* doc/c-mips.texi: Remove -mcpu. Document -mabi.
* configure.in (MIPS_CPU_STRING_DEFAULT): New configuration macro.
(USE_E_MIPS_ABI_O32, MIPS_DEFAULT_64BIT): New configuration macros.
* configure, config.in: Regenerate.
* config/tc-mips.c (file_mips_abi): Rename to mips_abi.
(mips_set_options): Remove "abi" field.
(mips_opts): Update accordingly. Replace all uses of mips_opts.abi
with mips_abi.
(mips_cpu): Remove.
(mips_arch_string, mips_arch_info): New vars.
(mips_tune_string, mips_tune_info): New vars.
(ABI_NEEDS_32BIT_REGS, ABI_NEEDS_64BIT_REGS): New macros.
(HAVE_32BIT_GPRS, HAVE_32BIT_FPRS): Don't check the ABI.
(mips_isa_to_str, mips_cpu_to_str): Remove.
(mips_ip): If the selected architecture is a generic ISA rather
than a processor, only mention the ISA level in error messages.
(OPTION_MCPU): Remove.
(OPTION_FP64): New.
(md_longopts): Add -mfp64, remove -mcpu.
(mips_set_option_string): New fn.
(md_parse_option): Make -mipsN update file_mips_isa rather than
mips_opts.isa. Use mips_set_option_string to set -march or -mtune.
Don't let -mgp32 and -mfp32 change the ABI.
(show): Move to end of file. Constify string argument.
(md_show_usage): Move to the end of the file. Read available
architectures from mips_cpu_info_table.
(mips_set_architecture): New fn.
(mips_after_parse_args): Rework. Remove -mcpu handling. -mipsN
is an alias for -march=mipsN. Don't change the ABI based on other
flags. Infer the register size from the ABI as well as the
architecture. Complain about more conflicting arguments.
Unify logic with GCC.
(s_mipsset): Don't change the ABI.
(mips_elf_final_processing): Check USE_E_MIPS_ABI_O32.
(mips_cpu_info_table): Remove Generic-MIPS* entries, keeping just
"mipsN"-type entries. Remove entries that vary only in the
manufacturer's prefix, or that have "000" replaced by "k".
Remove TARGET_CPU entries. Make r2000 entry use CPU_R3000.
(mips_strict_matching_cpu_name_p, mips_matching_cpu_name_p): New fns.
(mips_parse_cpu): New fn.
(mips_cpu_info_from_name, mips_cpu_info_from_cpu): Remove.
(mips_cpu_info_from_isa): Minor formatting tweak.
[gas/testsuite]
* gas/mips/mips-gp32-fp64.d,
* gas/mips/mips-gp32-fp64-pic.d: Add -mfp64.
2002-07-25 11:48:07 +02:00
|
|
|
|
as_bad ("-march=%s is not compatible with the selected ABI",
|
2003-06-29 21:41:33 +02:00
|
|
|
|
arch_info->name);
|
|
|
|
|
|
|
|
|
|
mips_set_architecture (arch_info);
|
|
|
|
|
|
|
|
|
|
/* Optimize for file_mips_arch, unless -mtune selects a different processor. */
|
|
|
|
|
if (mips_tune_string != 0)
|
|
|
|
|
tune_info = mips_parse_cpu ("-mtune", mips_tune_string);
|
2002-06-04 18:33:56 +02:00
|
|
|
|
|
2003-06-29 21:41:33 +02:00
|
|
|
|
if (tune_info == 0)
|
|
|
|
|
mips_set_tune (arch_info);
|
|
|
|
|
else
|
|
|
|
|
mips_set_tune (tune_info);
|
2002-06-04 18:33:56 +02:00
|
|
|
|
|
[gas/]
* doc/c-mips.texi: Remove -mcpu. Document -mabi.
* configure.in (MIPS_CPU_STRING_DEFAULT): New configuration macro.
(USE_E_MIPS_ABI_O32, MIPS_DEFAULT_64BIT): New configuration macros.
* configure, config.in: Regenerate.
* config/tc-mips.c (file_mips_abi): Rename to mips_abi.
(mips_set_options): Remove "abi" field.
(mips_opts): Update accordingly. Replace all uses of mips_opts.abi
with mips_abi.
(mips_cpu): Remove.
(mips_arch_string, mips_arch_info): New vars.
(mips_tune_string, mips_tune_info): New vars.
(ABI_NEEDS_32BIT_REGS, ABI_NEEDS_64BIT_REGS): New macros.
(HAVE_32BIT_GPRS, HAVE_32BIT_FPRS): Don't check the ABI.
(mips_isa_to_str, mips_cpu_to_str): Remove.
(mips_ip): If the selected architecture is a generic ISA rather
than a processor, only mention the ISA level in error messages.
(OPTION_MCPU): Remove.
(OPTION_FP64): New.
(md_longopts): Add -mfp64, remove -mcpu.
(mips_set_option_string): New fn.
(md_parse_option): Make -mipsN update file_mips_isa rather than
mips_opts.isa. Use mips_set_option_string to set -march or -mtune.
Don't let -mgp32 and -mfp32 change the ABI.
(show): Move to end of file. Constify string argument.
(md_show_usage): Move to the end of the file. Read available
architectures from mips_cpu_info_table.
(mips_set_architecture): New fn.
(mips_after_parse_args): Rework. Remove -mcpu handling. -mipsN
is an alias for -march=mipsN. Don't change the ABI based on other
flags. Infer the register size from the ABI as well as the
architecture. Complain about more conflicting arguments.
Unify logic with GCC.
(s_mipsset): Don't change the ABI.
(mips_elf_final_processing): Check USE_E_MIPS_ABI_O32.
(mips_cpu_info_table): Remove Generic-MIPS* entries, keeping just
"mipsN"-type entries. Remove entries that vary only in the
manufacturer's prefix, or that have "000" replaced by "k".
Remove TARGET_CPU entries. Make r2000 entry use CPU_R3000.
(mips_strict_matching_cpu_name_p, mips_matching_cpu_name_p): New fns.
(mips_parse_cpu): New fn.
(mips_cpu_info_from_name, mips_cpu_info_from_cpu): Remove.
(mips_cpu_info_from_isa): Minor formatting tweak.
[gas/testsuite]
* gas/mips/mips-gp32-fp64.d,
* gas/mips/mips-gp32-fp64-pic.d: Add -mfp64.
2002-07-25 11:48:07 +02:00
|
|
|
|
if (file_mips_gp32 >= 0)
|
2002-06-04 18:33:56 +02:00
|
|
|
|
{
|
[gas/]
* doc/c-mips.texi: Remove -mcpu. Document -mabi.
* configure.in (MIPS_CPU_STRING_DEFAULT): New configuration macro.
(USE_E_MIPS_ABI_O32, MIPS_DEFAULT_64BIT): New configuration macros.
* configure, config.in: Regenerate.
* config/tc-mips.c (file_mips_abi): Rename to mips_abi.
(mips_set_options): Remove "abi" field.
(mips_opts): Update accordingly. Replace all uses of mips_opts.abi
with mips_abi.
(mips_cpu): Remove.
(mips_arch_string, mips_arch_info): New vars.
(mips_tune_string, mips_tune_info): New vars.
(ABI_NEEDS_32BIT_REGS, ABI_NEEDS_64BIT_REGS): New macros.
(HAVE_32BIT_GPRS, HAVE_32BIT_FPRS): Don't check the ABI.
(mips_isa_to_str, mips_cpu_to_str): Remove.
(mips_ip): If the selected architecture is a generic ISA rather
than a processor, only mention the ISA level in error messages.
(OPTION_MCPU): Remove.
(OPTION_FP64): New.
(md_longopts): Add -mfp64, remove -mcpu.
(mips_set_option_string): New fn.
(md_parse_option): Make -mipsN update file_mips_isa rather than
mips_opts.isa. Use mips_set_option_string to set -march or -mtune.
Don't let -mgp32 and -mfp32 change the ABI.
(show): Move to end of file. Constify string argument.
(md_show_usage): Move to the end of the file. Read available
architectures from mips_cpu_info_table.
(mips_set_architecture): New fn.
(mips_after_parse_args): Rework. Remove -mcpu handling. -mipsN
is an alias for -march=mipsN. Don't change the ABI based on other
flags. Infer the register size from the ABI as well as the
architecture. Complain about more conflicting arguments.
Unify logic with GCC.
(s_mipsset): Don't change the ABI.
(mips_elf_final_processing): Check USE_E_MIPS_ABI_O32.
(mips_cpu_info_table): Remove Generic-MIPS* entries, keeping just
"mipsN"-type entries. Remove entries that vary only in the
manufacturer's prefix, or that have "000" replaced by "k".
Remove TARGET_CPU entries. Make r2000 entry use CPU_R3000.
(mips_strict_matching_cpu_name_p, mips_matching_cpu_name_p): New fns.
(mips_parse_cpu): New fn.
(mips_cpu_info_from_name, mips_cpu_info_from_cpu): Remove.
(mips_cpu_info_from_isa): Minor formatting tweak.
[gas/testsuite]
* gas/mips/mips-gp32-fp64.d,
* gas/mips/mips-gp32-fp64-pic.d: Add -mfp64.
2002-07-25 11:48:07 +02:00
|
|
|
|
/* The user specified the size of the integer registers. Make sure
|
|
|
|
|
it agrees with the ABI and ISA. */
|
|
|
|
|
if (file_mips_gp32 == 0 && !ISA_HAS_64BIT_REGS (mips_opts.isa))
|
|
|
|
|
as_bad (_("-mgp64 used with a 32-bit processor"));
|
|
|
|
|
else if (file_mips_gp32 == 1 && ABI_NEEDS_64BIT_REGS (mips_abi))
|
|
|
|
|
as_bad (_("-mgp32 used with a 64-bit ABI"));
|
|
|
|
|
else if (file_mips_gp32 == 0 && ABI_NEEDS_32BIT_REGS (mips_abi))
|
|
|
|
|
as_bad (_("-mgp64 used with a 32-bit ABI"));
|
2002-06-04 18:33:56 +02:00
|
|
|
|
}
|
|
|
|
|
else
|
|
|
|
|
{
|
[gas/]
* doc/c-mips.texi: Remove -mcpu. Document -mabi.
* configure.in (MIPS_CPU_STRING_DEFAULT): New configuration macro.
(USE_E_MIPS_ABI_O32, MIPS_DEFAULT_64BIT): New configuration macros.
* configure, config.in: Regenerate.
* config/tc-mips.c (file_mips_abi): Rename to mips_abi.
(mips_set_options): Remove "abi" field.
(mips_opts): Update accordingly. Replace all uses of mips_opts.abi
with mips_abi.
(mips_cpu): Remove.
(mips_arch_string, mips_arch_info): New vars.
(mips_tune_string, mips_tune_info): New vars.
(ABI_NEEDS_32BIT_REGS, ABI_NEEDS_64BIT_REGS): New macros.
(HAVE_32BIT_GPRS, HAVE_32BIT_FPRS): Don't check the ABI.
(mips_isa_to_str, mips_cpu_to_str): Remove.
(mips_ip): If the selected architecture is a generic ISA rather
than a processor, only mention the ISA level in error messages.
(OPTION_MCPU): Remove.
(OPTION_FP64): New.
(md_longopts): Add -mfp64, remove -mcpu.
(mips_set_option_string): New fn.
(md_parse_option): Make -mipsN update file_mips_isa rather than
mips_opts.isa. Use mips_set_option_string to set -march or -mtune.
Don't let -mgp32 and -mfp32 change the ABI.
(show): Move to end of file. Constify string argument.
(md_show_usage): Move to the end of the file. Read available
architectures from mips_cpu_info_table.
(mips_set_architecture): New fn.
(mips_after_parse_args): Rework. Remove -mcpu handling. -mipsN
is an alias for -march=mipsN. Don't change the ABI based on other
flags. Infer the register size from the ABI as well as the
architecture. Complain about more conflicting arguments.
Unify logic with GCC.
(s_mipsset): Don't change the ABI.
(mips_elf_final_processing): Check USE_E_MIPS_ABI_O32.
(mips_cpu_info_table): Remove Generic-MIPS* entries, keeping just
"mipsN"-type entries. Remove entries that vary only in the
manufacturer's prefix, or that have "000" replaced by "k".
Remove TARGET_CPU entries. Make r2000 entry use CPU_R3000.
(mips_strict_matching_cpu_name_p, mips_matching_cpu_name_p): New fns.
(mips_parse_cpu): New fn.
(mips_cpu_info_from_name, mips_cpu_info_from_cpu): Remove.
(mips_cpu_info_from_isa): Minor formatting tweak.
[gas/testsuite]
* gas/mips/mips-gp32-fp64.d,
* gas/mips/mips-gp32-fp64-pic.d: Add -mfp64.
2002-07-25 11:48:07 +02:00
|
|
|
|
/* Infer the integer register size from the ABI and processor.
|
|
|
|
|
Restrict ourselves to 32-bit registers if that's all the
|
|
|
|
|
processor has, or if the ABI cannot handle 64-bit registers. */
|
|
|
|
|
file_mips_gp32 = (ABI_NEEDS_32BIT_REGS (mips_abi)
|
|
|
|
|
|| !ISA_HAS_64BIT_REGS (mips_opts.isa));
|
2002-06-04 18:33:56 +02:00
|
|
|
|
}
|
|
|
|
|
|
[gas/]
* doc/c-mips.texi: Remove -mcpu. Document -mabi.
* configure.in (MIPS_CPU_STRING_DEFAULT): New configuration macro.
(USE_E_MIPS_ABI_O32, MIPS_DEFAULT_64BIT): New configuration macros.
* configure, config.in: Regenerate.
* config/tc-mips.c (file_mips_abi): Rename to mips_abi.
(mips_set_options): Remove "abi" field.
(mips_opts): Update accordingly. Replace all uses of mips_opts.abi
with mips_abi.
(mips_cpu): Remove.
(mips_arch_string, mips_arch_info): New vars.
(mips_tune_string, mips_tune_info): New vars.
(ABI_NEEDS_32BIT_REGS, ABI_NEEDS_64BIT_REGS): New macros.
(HAVE_32BIT_GPRS, HAVE_32BIT_FPRS): Don't check the ABI.
(mips_isa_to_str, mips_cpu_to_str): Remove.
(mips_ip): If the selected architecture is a generic ISA rather
than a processor, only mention the ISA level in error messages.
(OPTION_MCPU): Remove.
(OPTION_FP64): New.
(md_longopts): Add -mfp64, remove -mcpu.
(mips_set_option_string): New fn.
(md_parse_option): Make -mipsN update file_mips_isa rather than
mips_opts.isa. Use mips_set_option_string to set -march or -mtune.
Don't let -mgp32 and -mfp32 change the ABI.
(show): Move to end of file. Constify string argument.
(md_show_usage): Move to the end of the file. Read available
architectures from mips_cpu_info_table.
(mips_set_architecture): New fn.
(mips_after_parse_args): Rework. Remove -mcpu handling. -mipsN
is an alias for -march=mipsN. Don't change the ABI based on other
flags. Infer the register size from the ABI as well as the
architecture. Complain about more conflicting arguments.
Unify logic with GCC.
(s_mipsset): Don't change the ABI.
(mips_elf_final_processing): Check USE_E_MIPS_ABI_O32.
(mips_cpu_info_table): Remove Generic-MIPS* entries, keeping just
"mipsN"-type entries. Remove entries that vary only in the
manufacturer's prefix, or that have "000" replaced by "k".
Remove TARGET_CPU entries. Make r2000 entry use CPU_R3000.
(mips_strict_matching_cpu_name_p, mips_matching_cpu_name_p): New fns.
(mips_parse_cpu): New fn.
(mips_cpu_info_from_name, mips_cpu_info_from_cpu): Remove.
(mips_cpu_info_from_isa): Minor formatting tweak.
[gas/testsuite]
* gas/mips/mips-gp32-fp64.d,
* gas/mips/mips-gp32-fp64-pic.d: Add -mfp64.
2002-07-25 11:48:07 +02:00
|
|
|
|
/* ??? GAS treats single-float processors as though they had 64-bit
|
|
|
|
|
float registers (although it complains when double-precision
|
|
|
|
|
instructions are used). As things stand, saying they have 32-bit
|
|
|
|
|
registers would lead to spurious "register must be even" messages.
|
|
|
|
|
So here we assume float registers are always the same size as
|
|
|
|
|
integer ones, unless the user says otherwise. */
|
|
|
|
|
if (file_mips_fp32 < 0)
|
|
|
|
|
file_mips_fp32 = file_mips_gp32;
|
2002-06-04 18:33:56 +02:00
|
|
|
|
|
[gas/]
* doc/c-mips.texi: Remove -mcpu. Document -mabi.
* configure.in (MIPS_CPU_STRING_DEFAULT): New configuration macro.
(USE_E_MIPS_ABI_O32, MIPS_DEFAULT_64BIT): New configuration macros.
* configure, config.in: Regenerate.
* config/tc-mips.c (file_mips_abi): Rename to mips_abi.
(mips_set_options): Remove "abi" field.
(mips_opts): Update accordingly. Replace all uses of mips_opts.abi
with mips_abi.
(mips_cpu): Remove.
(mips_arch_string, mips_arch_info): New vars.
(mips_tune_string, mips_tune_info): New vars.
(ABI_NEEDS_32BIT_REGS, ABI_NEEDS_64BIT_REGS): New macros.
(HAVE_32BIT_GPRS, HAVE_32BIT_FPRS): Don't check the ABI.
(mips_isa_to_str, mips_cpu_to_str): Remove.
(mips_ip): If the selected architecture is a generic ISA rather
than a processor, only mention the ISA level in error messages.
(OPTION_MCPU): Remove.
(OPTION_FP64): New.
(md_longopts): Add -mfp64, remove -mcpu.
(mips_set_option_string): New fn.
(md_parse_option): Make -mipsN update file_mips_isa rather than
mips_opts.isa. Use mips_set_option_string to set -march or -mtune.
Don't let -mgp32 and -mfp32 change the ABI.
(show): Move to end of file. Constify string argument.
(md_show_usage): Move to the end of the file. Read available
architectures from mips_cpu_info_table.
(mips_set_architecture): New fn.
(mips_after_parse_args): Rework. Remove -mcpu handling. -mipsN
is an alias for -march=mipsN. Don't change the ABI based on other
flags. Infer the register size from the ABI as well as the
architecture. Complain about more conflicting arguments.
Unify logic with GCC.
(s_mipsset): Don't change the ABI.
(mips_elf_final_processing): Check USE_E_MIPS_ABI_O32.
(mips_cpu_info_table): Remove Generic-MIPS* entries, keeping just
"mipsN"-type entries. Remove entries that vary only in the
manufacturer's prefix, or that have "000" replaced by "k".
Remove TARGET_CPU entries. Make r2000 entry use CPU_R3000.
(mips_strict_matching_cpu_name_p, mips_matching_cpu_name_p): New fns.
(mips_parse_cpu): New fn.
(mips_cpu_info_from_name, mips_cpu_info_from_cpu): Remove.
(mips_cpu_info_from_isa): Minor formatting tweak.
[gas/testsuite]
* gas/mips/mips-gp32-fp64.d,
* gas/mips/mips-gp32-fp64-pic.d: Add -mfp64.
2002-07-25 11:48:07 +02:00
|
|
|
|
/* End of GCC-shared inference code. */
|
2002-06-04 18:33:56 +02:00
|
|
|
|
|
2003-06-30 14:44:25 +02:00
|
|
|
|
/* This flag is set when we have a 64-bit capable CPU but use only
|
|
|
|
|
32-bit wide registers. Note that EABI does not use it. */
|
|
|
|
|
if (ISA_HAS_64BIT_REGS (mips_opts.isa)
|
|
|
|
|
&& ((mips_abi == NO_ABI && file_mips_gp32 == 1)
|
|
|
|
|
|| mips_abi == O32_ABI))
|
[gas/]
* doc/c-mips.texi: Remove -mcpu. Document -mabi.
* configure.in (MIPS_CPU_STRING_DEFAULT): New configuration macro.
(USE_E_MIPS_ABI_O32, MIPS_DEFAULT_64BIT): New configuration macros.
* configure, config.in: Regenerate.
* config/tc-mips.c (file_mips_abi): Rename to mips_abi.
(mips_set_options): Remove "abi" field.
(mips_opts): Update accordingly. Replace all uses of mips_opts.abi
with mips_abi.
(mips_cpu): Remove.
(mips_arch_string, mips_arch_info): New vars.
(mips_tune_string, mips_tune_info): New vars.
(ABI_NEEDS_32BIT_REGS, ABI_NEEDS_64BIT_REGS): New macros.
(HAVE_32BIT_GPRS, HAVE_32BIT_FPRS): Don't check the ABI.
(mips_isa_to_str, mips_cpu_to_str): Remove.
(mips_ip): If the selected architecture is a generic ISA rather
than a processor, only mention the ISA level in error messages.
(OPTION_MCPU): Remove.
(OPTION_FP64): New.
(md_longopts): Add -mfp64, remove -mcpu.
(mips_set_option_string): New fn.
(md_parse_option): Make -mipsN update file_mips_isa rather than
mips_opts.isa. Use mips_set_option_string to set -march or -mtune.
Don't let -mgp32 and -mfp32 change the ABI.
(show): Move to end of file. Constify string argument.
(md_show_usage): Move to the end of the file. Read available
architectures from mips_cpu_info_table.
(mips_set_architecture): New fn.
(mips_after_parse_args): Rework. Remove -mcpu handling. -mipsN
is an alias for -march=mipsN. Don't change the ABI based on other
flags. Infer the register size from the ABI as well as the
architecture. Complain about more conflicting arguments.
Unify logic with GCC.
(s_mipsset): Don't change the ABI.
(mips_elf_final_processing): Check USE_E_MIPS_ABI_O32.
(mips_cpu_info_table): Remove Generic-MIPS* entries, keeping just
"mipsN"-type entries. Remove entries that vary only in the
manufacturer's prefix, or that have "000" replaced by "k".
Remove TARGET_CPU entries. Make r2000 entry use CPU_R3000.
(mips_strict_matching_cpu_name_p, mips_matching_cpu_name_p): New fns.
(mips_parse_cpu): New fn.
(mips_cpu_info_from_name, mips_cpu_info_from_cpu): Remove.
(mips_cpu_info_from_isa): Minor formatting tweak.
[gas/testsuite]
* gas/mips/mips-gp32-fp64.d,
* gas/mips/mips-gp32-fp64-pic.d: Add -mfp64.
2002-07-25 11:48:07 +02:00
|
|
|
|
mips_32bitmode = 1;
|
2002-06-04 18:33:56 +02:00
|
|
|
|
|
|
|
|
|
if (mips_opts.isa == ISA_MIPS1 && mips_trap)
|
|
|
|
|
as_bad (_("trap exception not supported at ISA 1"));
|
|
|
|
|
|
|
|
|
|
/* If the selected architecture includes support for ASEs, enable
|
|
|
|
|
generation of code for them. */
|
2002-06-08 01:26:54 +02:00
|
|
|
|
if (mips_opts.mips16 == -1)
|
2003-06-29 21:41:33 +02:00
|
|
|
|
mips_opts.mips16 = (CPU_HAS_MIPS16 (file_mips_arch)) ? 1 : 0;
|
2002-06-06 18:38:01 +02:00
|
|
|
|
if (mips_opts.ase_mips3d == -1)
|
2003-06-29 21:41:33 +02:00
|
|
|
|
mips_opts.ase_mips3d = (CPU_HAS_MIPS3D (file_mips_arch)) ? 1 : 0;
|
2002-06-06 18:38:01 +02:00
|
|
|
|
if (mips_opts.ase_mdmx == -1)
|
2003-06-29 21:41:33 +02:00
|
|
|
|
mips_opts.ase_mdmx = (CPU_HAS_MDMX (file_mips_arch)) ? 1 : 0;
|
2002-06-04 18:33:56 +02:00
|
|
|
|
|
|
|
|
|
file_mips_isa = mips_opts.isa;
|
2002-06-08 01:26:54 +02:00
|
|
|
|
file_ase_mips16 = mips_opts.mips16;
|
2002-06-04 18:33:56 +02:00
|
|
|
|
file_ase_mips3d = mips_opts.ase_mips3d;
|
|
|
|
|
file_ase_mdmx = mips_opts.ase_mdmx;
|
|
|
|
|
mips_opts.gp32 = file_mips_gp32;
|
|
|
|
|
mips_opts.fp32 = file_mips_fp32;
|
|
|
|
|
|
2002-06-14 16:08:54 +02:00
|
|
|
|
if (mips_flag_mdebug < 0)
|
|
|
|
|
{
|
|
|
|
|
#ifdef OBJ_MAYBE_ECOFF
|
|
|
|
|
if (OUTPUT_FLAVOR == bfd_target_ecoff_flavour)
|
|
|
|
|
mips_flag_mdebug = 1;
|
|
|
|
|
else
|
|
|
|
|
#endif /* OBJ_MAYBE_ECOFF */
|
|
|
|
|
mips_flag_mdebug = 0;
|
|
|
|
|
}
|
2002-06-04 18:33:56 +02:00
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
void
|
2003-06-30 14:44:25 +02:00
|
|
|
|
mips_init_after_args (void)
|
1999-05-03 09:29:11 +02:00
|
|
|
|
{
|
|
|
|
|
/* initialize opcodes */
|
|
|
|
|
bfd_mips_num_opcodes = bfd_mips_num_builtin_opcodes;
|
2000-12-05 19:51:08 +01:00
|
|
|
|
mips_opcodes = (struct mips_opcode *) mips_builtin_opcodes;
|
1999-05-03 09:29:11 +02:00
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
long
|
2003-06-30 14:44:25 +02:00
|
|
|
|
md_pcrel_from (fixS *fixP)
|
1999-05-03 09:29:11 +02:00
|
|
|
|
{
|
2003-06-11 18:22:26 +02:00
|
|
|
|
valueT addr = fixP->fx_where + fixP->fx_frag->fr_address;
|
|
|
|
|
switch (fixP->fx_r_type)
|
|
|
|
|
{
|
|
|
|
|
case BFD_RELOC_16_PCREL_S2:
|
|
|
|
|
case BFD_RELOC_MIPS_JMP:
|
|
|
|
|
/* Return the address of the delay slot. */
|
|
|
|
|
return addr + 4;
|
|
|
|
|
default:
|
|
|
|
|
return addr;
|
|
|
|
|
}
|
1999-05-03 09:29:11 +02:00
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/* This is called before the symbol table is processed. In order to
|
|
|
|
|
work with gcc when using mips-tfile, we must keep all local labels.
|
|
|
|
|
However, in other cases, we want to discard them. If we were
|
|
|
|
|
called with -g, but we didn't see any debugging information, it may
|
|
|
|
|
mean that gcc is smuggling debugging information through to
|
|
|
|
|
mips-tfile, in which case we must generate all local labels. */
|
|
|
|
|
|
|
|
|
|
void
|
2003-06-30 14:44:25 +02:00
|
|
|
|
mips_frob_file_before_adjust (void)
|
1999-05-03 09:29:11 +02:00
|
|
|
|
{
|
|
|
|
|
#ifndef NO_ECOFF_DEBUGGING
|
|
|
|
|
if (ECOFF_DEBUGGING
|
|
|
|
|
&& mips_debug != 0
|
|
|
|
|
&& ! ecoff_debugging_seen)
|
|
|
|
|
flag_keep_locals = 1;
|
|
|
|
|
#endif
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/* Sort any unmatched HI16_S relocs so that they immediately precede
|
2001-11-15 22:29:00 +01:00
|
|
|
|
the corresponding LO reloc. This is called before md_apply_fix3 and
|
1999-05-03 09:29:11 +02:00
|
|
|
|
tc_gen_reloc. Unmatched HI16_S relocs can only be generated by
|
|
|
|
|
explicit use of the %hi modifier. */
|
|
|
|
|
|
|
|
|
|
void
|
2003-06-30 14:44:25 +02:00
|
|
|
|
mips_frob_file (void)
|
1999-05-03 09:29:11 +02:00
|
|
|
|
{
|
|
|
|
|
struct mips_hi_fixup *l;
|
|
|
|
|
|
|
|
|
|
for (l = mips_hi_fixup_list; l != NULL; l = l->next)
|
|
|
|
|
{
|
|
|
|
|
segment_info_type *seginfo;
|
|
|
|
|
int pass;
|
|
|
|
|
|
2003-02-08 18:05:55 +01:00
|
|
|
|
assert (reloc_needs_lo_p (l->fixp->fx_r_type));
|
1999-05-03 09:29:11 +02:00
|
|
|
|
|
2003-02-08 18:05:55 +01:00
|
|
|
|
/* If a GOT16 relocation turns out to be against a global symbol,
|
|
|
|
|
there isn't supposed to be a matching LO. */
|
|
|
|
|
if (l->fixp->fx_r_type == BFD_RELOC_MIPS_GOT16
|
|
|
|
|
&& !pic_need_relax (l->fixp->fx_addsy, l->seg))
|
|
|
|
|
continue;
|
|
|
|
|
|
|
|
|
|
/* Check quickly whether the next fixup happens to be a matching %lo. */
|
|
|
|
|
if (fixup_has_matching_lo_p (l->fixp))
|
1999-05-03 09:29:11 +02:00
|
|
|
|
continue;
|
|
|
|
|
|
|
|
|
|
/* Look through the fixups for this segment for a matching %lo.
|
|
|
|
|
When we find one, move the %hi just in front of it. We do
|
|
|
|
|
this in two passes. In the first pass, we try to find a
|
|
|
|
|
unique %lo. In the second pass, we permit multiple %hi
|
|
|
|
|
relocs for a single %lo (this is a GNU extension). */
|
|
|
|
|
seginfo = seg_info (l->seg);
|
|
|
|
|
for (pass = 0; pass < 2; pass++)
|
|
|
|
|
{
|
|
|
|
|
fixS *f, *prev;
|
|
|
|
|
|
|
|
|
|
prev = NULL;
|
|
|
|
|
for (f = seginfo->fix_root; f != NULL; f = f->fx_next)
|
|
|
|
|
{
|
|
|
|
|
/* Check whether this is a %lo fixup which matches l->fixp. */
|
|
|
|
|
if (f->fx_r_type == BFD_RELOC_LO16
|
|
|
|
|
&& f->fx_addsy == l->fixp->fx_addsy
|
|
|
|
|
&& f->fx_offset == l->fixp->fx_offset
|
|
|
|
|
&& (pass == 1
|
|
|
|
|
|| prev == NULL
|
2003-02-08 18:05:55 +01:00
|
|
|
|
|| !reloc_needs_lo_p (prev->fx_r_type)
|
|
|
|
|
|| !fixup_has_matching_lo_p (prev)))
|
1999-05-03 09:29:11 +02:00
|
|
|
|
{
|
|
|
|
|
fixS **pf;
|
|
|
|
|
|
|
|
|
|
/* Move l->fixp before f. */
|
|
|
|
|
for (pf = &seginfo->fix_root;
|
|
|
|
|
*pf != l->fixp;
|
|
|
|
|
pf = &(*pf)->fx_next)
|
|
|
|
|
assert (*pf != NULL);
|
|
|
|
|
|
|
|
|
|
*pf = l->fixp->fx_next;
|
|
|
|
|
|
|
|
|
|
l->fixp->fx_next = f;
|
|
|
|
|
if (prev == NULL)
|
|
|
|
|
seginfo->fix_root = l->fixp;
|
|
|
|
|
else
|
|
|
|
|
prev->fx_next = l->fixp;
|
|
|
|
|
|
|
|
|
|
break;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
prev = f;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
if (f != NULL)
|
|
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
#if 0 /* GCC code motion plus incomplete dead code elimination
|
|
|
|
|
can leave a %hi without a %lo. */
|
|
|
|
|
if (pass == 1)
|
|
|
|
|
as_warn_where (l->fixp->fx_file, l->fixp->fx_line,
|
|
|
|
|
_("Unmatched %%hi reloc"));
|
|
|
|
|
#endif
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/* When generating embedded PIC code we need to use a special
|
|
|
|
|
relocation to represent the difference of two symbols in the .text
|
|
|
|
|
section (switch tables use a difference of this sort). See
|
|
|
|
|
include/coff/mips.h for details. This macro checks whether this
|
|
|
|
|
fixup requires the special reloc. */
|
|
|
|
|
#define SWITCH_TABLE(fixp) \
|
|
|
|
|
((fixp)->fx_r_type == BFD_RELOC_32 \
|
2000-03-11 03:16:25 +01:00
|
|
|
|
&& OUTPUT_FLAVOR != bfd_target_elf_flavour \
|
1999-05-03 09:29:11 +02:00
|
|
|
|
&& (fixp)->fx_addsy != NULL \
|
|
|
|
|
&& (fixp)->fx_subsy != NULL \
|
|
|
|
|
&& S_GET_SEGMENT ((fixp)->fx_addsy) == text_section \
|
|
|
|
|
&& S_GET_SEGMENT ((fixp)->fx_subsy) == text_section)
|
|
|
|
|
|
|
|
|
|
/* When generating embedded PIC code we must keep all PC relative
|
|
|
|
|
relocations, in case the linker has to relax a call. We also need
|
2001-10-04 22:07:00 +02:00
|
|
|
|
to keep relocations for switch table entries.
|
|
|
|
|
|
|
|
|
|
We may have combined relocations without symbols in the N32/N64 ABI.
|
|
|
|
|
We have to prevent gas from dropping them. */
|
1999-05-03 09:29:11 +02:00
|
|
|
|
|
|
|
|
|
int
|
2003-06-30 14:44:25 +02:00
|
|
|
|
mips_force_relocation (fixS *fixp)
|
1999-05-03 09:29:11 +02:00
|
|
|
|
{
|
2003-01-23 13:51:05 +01:00
|
|
|
|
if (generic_force_reloc (fixp))
|
1999-05-03 09:29:11 +02:00
|
|
|
|
return 1;
|
|
|
|
|
|
2001-10-04 22:07:00 +02:00
|
|
|
|
if (HAVE_NEWABI
|
|
|
|
|
&& S_GET_SEGMENT (fixp->fx_addsy) == bfd_abs_section_ptr
|
|
|
|
|
&& (fixp->fx_r_type == BFD_RELOC_MIPS_SUB
|
|
|
|
|
|| fixp->fx_r_type == BFD_RELOC_HI16_S
|
|
|
|
|
|| fixp->fx_r_type == BFD_RELOC_LO16))
|
|
|
|
|
return 1;
|
|
|
|
|
|
1999-05-03 09:29:11 +02:00
|
|
|
|
return (mips_pic == EMBEDDED_PIC
|
|
|
|
|
&& (fixp->fx_pcrel
|
|
|
|
|
|| SWITCH_TABLE (fixp)
|
|
|
|
|
|| fixp->fx_r_type == BFD_RELOC_PCREL_HI16_S
|
|
|
|
|
|| fixp->fx_r_type == BFD_RELOC_PCREL_LO16));
|
|
|
|
|
}
|
|
|
|
|
|
2003-03-13 00:07:38 +01:00
|
|
|
|
/* This hook is called before a fix is simplified. We don't really
|
|
|
|
|
decide whether to skip a fix here. Rather, we turn global symbols
|
|
|
|
|
used as branch targets into local symbols, such that they undergo
|
|
|
|
|
simplification. We can only do this if the symbol is defined and
|
|
|
|
|
it is in the same section as the branch. If this doesn't hold, we
|
|
|
|
|
emit a better error message than just saying the relocation is not
|
|
|
|
|
valid for the selected object format.
|
|
|
|
|
|
|
|
|
|
FIXP is the fix-up we're going to try to simplify, SEG is the
|
|
|
|
|
segment in which the fix up occurs. The return value should be
|
|
|
|
|
non-zero to indicate the fix-up is valid for further
|
|
|
|
|
simplifications. */
|
|
|
|
|
|
|
|
|
|
int
|
2003-06-30 14:44:25 +02:00
|
|
|
|
mips_validate_fix (struct fix *fixP, asection *seg)
|
2003-03-13 00:07:38 +01:00
|
|
|
|
{
|
|
|
|
|
/* There's a lot of discussion on whether it should be possible to
|
|
|
|
|
use R_MIPS_PC16 to represent branch relocations. The outcome
|
|
|
|
|
seems to be that it can, but gas/bfd are very broken in creating
|
|
|
|
|
RELA relocations for this, so for now we only accept branches to
|
|
|
|
|
symbols in the same section. Anything else is of dubious value,
|
|
|
|
|
since there's no guarantee that at link time the symbol would be
|
|
|
|
|
in range. Even for branches to local symbols this is arguably
|
|
|
|
|
wrong, since it we assume the symbol is not going to be
|
|
|
|
|
overridden, which should be possible per ELF library semantics,
|
|
|
|
|
but then, there isn't a dynamic relocation that could be used to
|
|
|
|
|
this effect, and the target would likely be out of range as well.
|
|
|
|
|
|
|
|
|
|
Unfortunately, it seems that there is too much code out there
|
|
|
|
|
that relies on branches to symbols that are global to be resolved
|
|
|
|
|
as if they were local, like the IRIX tools do, so we do it as
|
|
|
|
|
well, but with a warning so that people are reminded to fix their
|
|
|
|
|
code. If we ever get back to using R_MIPS_PC16 for branch
|
|
|
|
|
targets, this entire block should go away (and probably the
|
|
|
|
|
whole function). */
|
|
|
|
|
|
|
|
|
|
if (fixP->fx_r_type == BFD_RELOC_16_PCREL_S2
|
|
|
|
|
&& (((OUTPUT_FLAVOR == bfd_target_ecoff_flavour
|
|
|
|
|
|| OUTPUT_FLAVOR == bfd_target_elf_flavour)
|
|
|
|
|
&& mips_pic != EMBEDDED_PIC)
|
|
|
|
|
|| bfd_reloc_type_lookup (stdoutput, BFD_RELOC_16_PCREL_S2) == NULL)
|
|
|
|
|
&& fixP->fx_addsy)
|
|
|
|
|
{
|
|
|
|
|
if (! S_IS_DEFINED (fixP->fx_addsy))
|
|
|
|
|
{
|
|
|
|
|
as_bad_where (fixP->fx_file, fixP->fx_line,
|
|
|
|
|
_("Cannot branch to undefined symbol."));
|
|
|
|
|
/* Avoid any further errors about this fixup. */
|
|
|
|
|
fixP->fx_done = 1;
|
|
|
|
|
}
|
|
|
|
|
else if (S_GET_SEGMENT (fixP->fx_addsy) != seg)
|
|
|
|
|
{
|
|
|
|
|
as_bad_where (fixP->fx_file, fixP->fx_line,
|
|
|
|
|
_("Cannot branch to symbol in another section."));
|
|
|
|
|
fixP->fx_done = 1;
|
|
|
|
|
}
|
|
|
|
|
else if (S_IS_EXTERNAL (fixP->fx_addsy))
|
|
|
|
|
{
|
|
|
|
|
symbolS *sym = fixP->fx_addsy;
|
|
|
|
|
|
2003-07-09 03:27:30 +02:00
|
|
|
|
if (mips_pic == SVR4_PIC)
|
|
|
|
|
as_warn_where (fixP->fx_file, fixP->fx_line,
|
|
|
|
|
_("Pretending global symbol used as branch target is local."));
|
2003-03-13 00:07:38 +01:00
|
|
|
|
|
|
|
|
|
fixP->fx_addsy = symbol_create (S_GET_NAME (sym),
|
|
|
|
|
S_GET_SEGMENT (sym),
|
|
|
|
|
S_GET_VALUE (sym),
|
|
|
|
|
symbol_get_frag (sym));
|
|
|
|
|
copy_symbol_attributes (fixP->fx_addsy, sym);
|
|
|
|
|
S_CLEAR_EXTERNAL (fixP->fx_addsy);
|
|
|
|
|
assert (symbol_resolved_p (sym));
|
|
|
|
|
symbol_mark_resolved (fixP->fx_addsy);
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
return 1;
|
|
|
|
|
}
|
|
|
|
|
|
1999-05-03 09:29:11 +02:00
|
|
|
|
/* Apply a fixup to the object file. */
|
|
|
|
|
|
2001-11-15 22:29:00 +01:00
|
|
|
|
void
|
2003-06-30 14:44:25 +02:00
|
|
|
|
md_apply_fix3 (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED)
|
1999-05-03 09:29:11 +02:00
|
|
|
|
{
|
2002-04-04 09:43:11 +02:00
|
|
|
|
bfd_byte *buf;
|
2001-06-08 08:07:13 +02:00
|
|
|
|
long insn;
|
2002-09-18 04:25:19 +02:00
|
|
|
|
static int previous_fx_r_type = 0;
|
2003-06-11 18:22:26 +02:00
|
|
|
|
reloc_howto_type *howto;
|
1999-05-03 09:29:11 +02:00
|
|
|
|
|
2003-06-11 18:22:26 +02:00
|
|
|
|
/* We ignore generic BFD relocations we don't know about. */
|
|
|
|
|
howto = bfd_reloc_type_lookup (stdoutput, fixP->fx_r_type);
|
|
|
|
|
if (! howto)
|
|
|
|
|
return;
|
2002-09-18 23:05:59 +02:00
|
|
|
|
|
1999-05-03 09:29:11 +02:00
|
|
|
|
assert (fixP->fx_size == 4
|
|
|
|
|
|| fixP->fx_r_type == BFD_RELOC_16
|
|
|
|
|
|| fixP->fx_r_type == BFD_RELOC_64
|
2001-10-04 22:07:00 +02:00
|
|
|
|
|| fixP->fx_r_type == BFD_RELOC_CTOR
|
|
|
|
|
|| fixP->fx_r_type == BFD_RELOC_MIPS_SUB
|
1999-05-03 09:29:11 +02:00
|
|
|
|
|| fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
|
2003-06-11 18:22:26 +02:00
|
|
|
|
|| fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY);
|
1999-05-03 09:29:11 +02:00
|
|
|
|
|
2003-06-11 18:22:26 +02:00
|
|
|
|
buf = (bfd_byte *) (fixP->fx_frag->fr_literal + fixP->fx_where);
|
1999-05-03 09:29:11 +02:00
|
|
|
|
|
2002-09-18 04:25:19 +02:00
|
|
|
|
/* We are not done if this is a composite relocation to set up gp. */
|
|
|
|
|
if (fixP->fx_addsy == NULL && ! fixP->fx_pcrel
|
|
|
|
|
&& !(fixP->fx_r_type == BFD_RELOC_MIPS_SUB
|
2002-10-13 23:22:49 +02:00
|
|
|
|
|| (fixP->fx_r_type == BFD_RELOC_64
|
|
|
|
|
&& (previous_fx_r_type == BFD_RELOC_GPREL32
|
|
|
|
|
|| previous_fx_r_type == BFD_RELOC_GPREL16))
|
2002-09-18 04:25:19 +02:00
|
|
|
|
|| (previous_fx_r_type == BFD_RELOC_MIPS_SUB
|
|
|
|
|
&& (fixP->fx_r_type == BFD_RELOC_HI16_S
|
|
|
|
|
|| fixP->fx_r_type == BFD_RELOC_LO16))))
|
1999-05-03 09:29:11 +02:00
|
|
|
|
fixP->fx_done = 1;
|
2002-09-18 04:25:19 +02:00
|
|
|
|
previous_fx_r_type = fixP->fx_r_type;
|
1999-05-03 09:29:11 +02:00
|
|
|
|
|
|
|
|
|
switch (fixP->fx_r_type)
|
|
|
|
|
{
|
|
|
|
|
case BFD_RELOC_MIPS_JMP:
|
2001-10-15 21:48:04 +02:00
|
|
|
|
case BFD_RELOC_MIPS_SHIFT5:
|
|
|
|
|
case BFD_RELOC_MIPS_SHIFT6:
|
|
|
|
|
case BFD_RELOC_MIPS_GOT_DISP:
|
|
|
|
|
case BFD_RELOC_MIPS_GOT_PAGE:
|
|
|
|
|
case BFD_RELOC_MIPS_GOT_OFST:
|
|
|
|
|
case BFD_RELOC_MIPS_SUB:
|
|
|
|
|
case BFD_RELOC_MIPS_INSERT_A:
|
|
|
|
|
case BFD_RELOC_MIPS_INSERT_B:
|
|
|
|
|
case BFD_RELOC_MIPS_DELETE:
|
|
|
|
|
case BFD_RELOC_MIPS_HIGHEST:
|
|
|
|
|
case BFD_RELOC_MIPS_HIGHER:
|
|
|
|
|
case BFD_RELOC_MIPS_SCN_DISP:
|
|
|
|
|
case BFD_RELOC_MIPS_REL16:
|
|
|
|
|
case BFD_RELOC_MIPS_RELGOT:
|
|
|
|
|
case BFD_RELOC_MIPS_JALR:
|
1999-05-03 09:29:11 +02:00
|
|
|
|
case BFD_RELOC_HI16:
|
|
|
|
|
case BFD_RELOC_HI16_S:
|
2001-12-02 14:14:48 +01:00
|
|
|
|
case BFD_RELOC_GPREL16:
|
1999-05-03 09:29:11 +02:00
|
|
|
|
case BFD_RELOC_MIPS_LITERAL:
|
|
|
|
|
case BFD_RELOC_MIPS_CALL16:
|
|
|
|
|
case BFD_RELOC_MIPS_GOT16:
|
2001-12-02 14:14:48 +01:00
|
|
|
|
case BFD_RELOC_GPREL32:
|
1999-05-03 09:29:11 +02:00
|
|
|
|
case BFD_RELOC_MIPS_GOT_HI16:
|
|
|
|
|
case BFD_RELOC_MIPS_GOT_LO16:
|
|
|
|
|
case BFD_RELOC_MIPS_CALL_HI16:
|
|
|
|
|
case BFD_RELOC_MIPS_CALL_LO16:
|
|
|
|
|
case BFD_RELOC_MIPS16_GPREL:
|
|
|
|
|
if (fixP->fx_pcrel)
|
|
|
|
|
as_bad_where (fixP->fx_file, fixP->fx_line,
|
|
|
|
|
_("Invalid PC relative reloc"));
|
|
|
|
|
/* Nothing needed to do. The value comes from the reloc entry */
|
|
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
case BFD_RELOC_MIPS16_JMP:
|
|
|
|
|
/* We currently always generate a reloc against a symbol, which
|
|
|
|
|
means that we don't want an addend even if the symbol is
|
|
|
|
|
defined. */
|
2003-06-11 18:22:26 +02:00
|
|
|
|
*valP = 0;
|
1999-05-03 09:29:11 +02:00
|
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
case BFD_RELOC_PCREL_HI16_S:
|
|
|
|
|
/* The addend for this is tricky if it is internal, so we just
|
|
|
|
|
do everything here rather than in bfd_install_relocation. */
|
2003-06-11 18:22:26 +02:00
|
|
|
|
if (OUTPUT_FLAVOR == bfd_target_elf_flavour && !fixP->fx_done)
|
2000-03-11 03:16:25 +01:00
|
|
|
|
break;
|
|
|
|
|
if (fixP->fx_addsy
|
|
|
|
|
&& (symbol_get_bfdsym (fixP->fx_addsy)->flags & BSF_SECTION_SYM) == 0)
|
1999-05-03 09:29:11 +02:00
|
|
|
|
{
|
|
|
|
|
/* For an external symbol adjust by the address to make it
|
|
|
|
|
pcrel_offset. We use the address of the RELLO reloc
|
|
|
|
|
which follows this one. */
|
2003-06-11 18:22:26 +02:00
|
|
|
|
*valP += (fixP->fx_next->fx_frag->fr_address
|
1999-05-03 09:29:11 +02:00
|
|
|
|
+ fixP->fx_next->fx_where);
|
|
|
|
|
}
|
2003-06-11 18:22:26 +02:00
|
|
|
|
*valP = ((*valP + 0x8000) >> 16) & 0xffff;
|
1999-05-03 09:29:11 +02:00
|
|
|
|
if (target_big_endian)
|
|
|
|
|
buf += 2;
|
2003-06-30 14:44:25 +02:00
|
|
|
|
md_number_to_chars (buf, *valP, 2);
|
1999-05-03 09:29:11 +02:00
|
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
case BFD_RELOC_PCREL_LO16:
|
|
|
|
|
/* The addend for this is tricky if it is internal, so we just
|
|
|
|
|
do everything here rather than in bfd_install_relocation. */
|
2003-06-11 18:22:26 +02:00
|
|
|
|
if (OUTPUT_FLAVOR == bfd_target_elf_flavour && !fixP->fx_done)
|
2000-03-11 03:16:25 +01:00
|
|
|
|
break;
|
|
|
|
|
if (fixP->fx_addsy
|
|
|
|
|
&& (symbol_get_bfdsym (fixP->fx_addsy)->flags & BSF_SECTION_SYM) == 0)
|
2003-06-11 18:22:26 +02:00
|
|
|
|
*valP += fixP->fx_frag->fr_address + fixP->fx_where;
|
1999-05-03 09:29:11 +02:00
|
|
|
|
if (target_big_endian)
|
|
|
|
|
buf += 2;
|
2003-06-30 14:44:25 +02:00
|
|
|
|
md_number_to_chars (buf, *valP, 2);
|
1999-05-03 09:29:11 +02:00
|
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
case BFD_RELOC_64:
|
|
|
|
|
/* This is handled like BFD_RELOC_32, but we output a sign
|
|
|
|
|
extended value if we are only 32 bits. */
|
|
|
|
|
if (fixP->fx_done
|
|
|
|
|
|| (mips_pic == EMBEDDED_PIC && SWITCH_TABLE (fixP)))
|
|
|
|
|
{
|
|
|
|
|
if (8 <= sizeof (valueT))
|
2003-06-11 18:22:26 +02:00
|
|
|
|
md_number_to_chars (buf, *valP, 8);
|
1999-05-03 09:29:11 +02:00
|
|
|
|
else
|
|
|
|
|
{
|
2003-06-11 18:22:26 +02:00
|
|
|
|
valueT hiv;
|
1999-05-03 09:29:11 +02:00
|
|
|
|
|
2003-06-11 18:22:26 +02:00
|
|
|
|
if ((*valP & 0x80000000) != 0)
|
1999-05-03 09:29:11 +02:00
|
|
|
|
hiv = 0xffffffff;
|
|
|
|
|
else
|
|
|
|
|
hiv = 0;
|
2003-06-11 18:22:26 +02:00
|
|
|
|
md_number_to_chars ((char *)(buf + target_big_endian ? 4 : 0),
|
|
|
|
|
*valP, 4);
|
|
|
|
|
md_number_to_chars ((char *)(buf + target_big_endian ? 0 : 4),
|
|
|
|
|
hiv, 4);
|
1999-05-03 09:29:11 +02:00
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
break;
|
|
|
|
|
|
2000-02-24 20:49:18 +01:00
|
|
|
|
case BFD_RELOC_RVA:
|
1999-05-03 09:29:11 +02:00
|
|
|
|
case BFD_RELOC_32:
|
|
|
|
|
/* If we are deleting this reloc entry, we must fill in the
|
|
|
|
|
value now. This can happen if we have a .word which is not
|
|
|
|
|
resolved when it appears but is later defined. We also need
|
|
|
|
|
to fill in the value if this is an embedded PIC switch table
|
|
|
|
|
entry. */
|
|
|
|
|
if (fixP->fx_done
|
|
|
|
|
|| (mips_pic == EMBEDDED_PIC && SWITCH_TABLE (fixP)))
|
2003-06-11 18:22:26 +02:00
|
|
|
|
md_number_to_chars (buf, *valP, 4);
|
1999-05-03 09:29:11 +02:00
|
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
case BFD_RELOC_16:
|
|
|
|
|
/* If we are deleting this reloc entry, we must fill in the
|
|
|
|
|
value now. */
|
|
|
|
|
assert (fixP->fx_size == 2);
|
|
|
|
|
if (fixP->fx_done)
|
2003-06-11 18:22:26 +02:00
|
|
|
|
md_number_to_chars (buf, *valP, 2);
|
1999-05-03 09:29:11 +02:00
|
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
case BFD_RELOC_LO16:
|
|
|
|
|
/* When handling an embedded PIC switch statement, we can wind
|
|
|
|
|
up deleting a LO16 reloc. See the 'o' case in mips_ip. */
|
|
|
|
|
if (fixP->fx_done)
|
|
|
|
|
{
|
2003-06-11 18:22:26 +02:00
|
|
|
|
if (*valP + 0x8000 > 0xffff)
|
1999-05-03 09:29:11 +02:00
|
|
|
|
as_bad_where (fixP->fx_file, fixP->fx_line,
|
|
|
|
|
_("relocation overflow"));
|
|
|
|
|
if (target_big_endian)
|
|
|
|
|
buf += 2;
|
2003-06-30 14:44:25 +02:00
|
|
|
|
md_number_to_chars (buf, *valP, 2);
|
1999-05-03 09:29:11 +02:00
|
|
|
|
}
|
|
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
case BFD_RELOC_16_PCREL_S2:
|
2003-06-11 18:22:26 +02:00
|
|
|
|
if ((*valP & 0x3) != 0)
|
2001-09-07 07:00:37 +02:00
|
|
|
|
as_bad_where (fixP->fx_file, fixP->fx_line,
|
2003-06-11 18:22:26 +02:00
|
|
|
|
_("Branch to odd address (%lx)"), (long) *valP);
|
2001-09-07 07:00:37 +02:00
|
|
|
|
|
1999-05-03 09:29:11 +02:00
|
|
|
|
/*
|
|
|
|
|
* We need to save the bits in the instruction since fixup_segment()
|
|
|
|
|
* might be deleting the relocation entry (i.e., a branch within
|
|
|
|
|
* the current segment).
|
|
|
|
|
*/
|
2003-06-11 18:22:26 +02:00
|
|
|
|
if (! fixP->fx_done)
|
2000-03-11 03:16:25 +01:00
|
|
|
|
break;
|
1999-05-03 09:29:11 +02:00
|
|
|
|
|
|
|
|
|
/* update old instruction data */
|
|
|
|
|
if (target_big_endian)
|
|
|
|
|
insn = (buf[0] << 24) | (buf[1] << 16) | (buf[2] << 8) | buf[3];
|
|
|
|
|
else
|
|
|
|
|
insn = (buf[3] << 24) | (buf[2] << 16) | (buf[1] << 8) | buf[0];
|
|
|
|
|
|
2003-06-11 18:22:26 +02:00
|
|
|
|
if (*valP + 0x20000 <= 0x3ffff)
|
|
|
|
|
{
|
|
|
|
|
insn |= (*valP >> 2) & 0xffff;
|
2003-06-30 14:44:25 +02:00
|
|
|
|
md_number_to_chars (buf, insn, 4);
|
2003-06-11 18:22:26 +02:00
|
|
|
|
}
|
|
|
|
|
else if (mips_pic == NO_PIC
|
|
|
|
|
&& fixP->fx_done
|
|
|
|
|
&& fixP->fx_frag->fr_address >= text_section->vma
|
|
|
|
|
&& (fixP->fx_frag->fr_address
|
|
|
|
|
< text_section->vma + text_section->_raw_size)
|
|
|
|
|
&& ((insn & 0xffff0000) == 0x10000000 /* beq $0,$0 */
|
|
|
|
|
|| (insn & 0xffff0000) == 0x04010000 /* bgez $0 */
|
|
|
|
|
|| (insn & 0xffff0000) == 0x04110000)) /* bgezal $0 */
|
1999-05-03 09:29:11 +02:00
|
|
|
|
{
|
|
|
|
|
/* The branch offset is too large. If this is an
|
|
|
|
|
unconditional branch, and we are not generating PIC code,
|
|
|
|
|
we can convert it to an absolute jump instruction. */
|
2003-06-11 18:22:26 +02:00
|
|
|
|
if ((insn & 0xffff0000) == 0x04110000) /* bgezal $0 */
|
|
|
|
|
insn = 0x0c000000; /* jal */
|
1999-05-03 09:29:11 +02:00
|
|
|
|
else
|
2003-06-11 18:22:26 +02:00
|
|
|
|
insn = 0x08000000; /* j */
|
|
|
|
|
fixP->fx_r_type = BFD_RELOC_MIPS_JMP;
|
|
|
|
|
fixP->fx_done = 0;
|
|
|
|
|
fixP->fx_addsy = section_symbol (text_section);
|
|
|
|
|
*valP += md_pcrel_from (fixP);
|
2003-06-30 14:44:25 +02:00
|
|
|
|
md_number_to_chars (buf, insn, 4);
|
2003-06-11 18:22:26 +02:00
|
|
|
|
}
|
|
|
|
|
else
|
|
|
|
|
{
|
|
|
|
|
/* If we got here, we have branch-relaxation disabled,
|
|
|
|
|
and there's nothing we can do to fix this instruction
|
|
|
|
|
without turning it into a longer sequence. */
|
|
|
|
|
as_bad_where (fixP->fx_file, fixP->fx_line,
|
|
|
|
|
_("Branch out of range"));
|
1999-05-03 09:29:11 +02:00
|
|
|
|
}
|
|
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
case BFD_RELOC_VTABLE_INHERIT:
|
|
|
|
|
fixP->fx_done = 0;
|
|
|
|
|
if (fixP->fx_addsy
|
|
|
|
|
&& !S_IS_DEFINED (fixP->fx_addsy)
|
|
|
|
|
&& !S_IS_WEAK (fixP->fx_addsy))
|
|
|
|
|
S_SET_WEAK (fixP->fx_addsy);
|
|
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
case BFD_RELOC_VTABLE_ENTRY:
|
|
|
|
|
fixP->fx_done = 0;
|
|
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
default:
|
|
|
|
|
internalError ();
|
|
|
|
|
}
|
2003-06-11 18:22:26 +02:00
|
|
|
|
|
|
|
|
|
/* Remember value for tc_gen_reloc. */
|
|
|
|
|
fixP->fx_addnumber = *valP;
|
1999-05-03 09:29:11 +02:00
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
#if 0
|
|
|
|
|
void
|
2003-06-30 14:44:25 +02:00
|
|
|
|
printInsn (unsigned long oc)
|
1999-05-03 09:29:11 +02:00
|
|
|
|
{
|
|
|
|
|
const struct mips_opcode *p;
|
|
|
|
|
int treg, sreg, dreg, shamt;
|
|
|
|
|
short imm;
|
|
|
|
|
const char *args;
|
|
|
|
|
int i;
|
|
|
|
|
|
|
|
|
|
for (i = 0; i < NUMOPCODES; ++i)
|
|
|
|
|
{
|
|
|
|
|
p = &mips_opcodes[i];
|
|
|
|
|
if (((oc & p->mask) == p->match) && (p->pinfo != INSN_MACRO))
|
|
|
|
|
{
|
|
|
|
|
printf ("%08lx %s\t", oc, p->name);
|
|
|
|
|
treg = (oc >> 16) & 0x1f;
|
|
|
|
|
sreg = (oc >> 21) & 0x1f;
|
|
|
|
|
dreg = (oc >> 11) & 0x1f;
|
|
|
|
|
shamt = (oc >> 6) & 0x1f;
|
|
|
|
|
imm = oc;
|
|
|
|
|
for (args = p->args;; ++args)
|
|
|
|
|
{
|
|
|
|
|
switch (*args)
|
|
|
|
|
{
|
|
|
|
|
case '\0':
|
|
|
|
|
printf ("\n");
|
|
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
case ',':
|
|
|
|
|
case '(':
|
|
|
|
|
case ')':
|
|
|
|
|
printf ("%c", *args);
|
|
|
|
|
continue;
|
|
|
|
|
|
|
|
|
|
case 'r':
|
|
|
|
|
assert (treg == sreg);
|
|
|
|
|
printf ("$%d,$%d", treg, sreg);
|
|
|
|
|
continue;
|
|
|
|
|
|
|
|
|
|
case 'd':
|
|
|
|
|
case 'G':
|
|
|
|
|
printf ("$%d", dreg);
|
|
|
|
|
continue;
|
|
|
|
|
|
|
|
|
|
case 't':
|
|
|
|
|
case 'E':
|
|
|
|
|
printf ("$%d", treg);
|
|
|
|
|
continue;
|
|
|
|
|
|
|
|
|
|
case 'k':
|
|
|
|
|
printf ("0x%x", treg);
|
|
|
|
|
continue;
|
|
|
|
|
|
|
|
|
|
case 'b':
|
|
|
|
|
case 's':
|
|
|
|
|
printf ("$%d", sreg);
|
|
|
|
|
continue;
|
|
|
|
|
|
|
|
|
|
case 'a':
|
|
|
|
|
printf ("0x%08lx", oc & 0x1ffffff);
|
|
|
|
|
continue;
|
|
|
|
|
|
|
|
|
|
case 'i':
|
|
|
|
|
case 'j':
|
|
|
|
|
case 'o':
|
|
|
|
|
case 'u':
|
|
|
|
|
printf ("%d", imm);
|
|
|
|
|
continue;
|
|
|
|
|
|
|
|
|
|
case '<':
|
|
|
|
|
case '>':
|
|
|
|
|
printf ("$%d", shamt);
|
|
|
|
|
continue;
|
|
|
|
|
|
|
|
|
|
default:
|
|
|
|
|
internalError ();
|
|
|
|
|
}
|
|
|
|
|
break;
|
|
|
|
|
}
|
|
|
|
|
return;
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
printf (_("%08lx UNDEFINED\n"), oc);
|
|
|
|
|
}
|
|
|
|
|
#endif
|
|
|
|
|
|
|
|
|
|
static symbolS *
|
2003-06-30 14:44:25 +02:00
|
|
|
|
get_symbol (void)
|
1999-05-03 09:29:11 +02:00
|
|
|
|
{
|
|
|
|
|
int c;
|
|
|
|
|
char *name;
|
|
|
|
|
symbolS *p;
|
|
|
|
|
|
|
|
|
|
name = input_line_pointer;
|
|
|
|
|
c = get_symbol_end ();
|
|
|
|
|
p = (symbolS *) symbol_find_or_make (name);
|
|
|
|
|
*input_line_pointer = c;
|
|
|
|
|
return p;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/* Align the current frag to a given power of two. The MIPS assembler
|
|
|
|
|
also automatically adjusts any preceding label. */
|
|
|
|
|
|
|
|
|
|
static void
|
2003-06-30 14:44:25 +02:00
|
|
|
|
mips_align (int to, int fill, symbolS *label)
|
1999-05-03 09:29:11 +02:00
|
|
|
|
{
|
2002-11-30 09:39:46 +01:00
|
|
|
|
mips_emit_delays (FALSE);
|
1999-05-03 09:29:11 +02:00
|
|
|
|
frag_align (to, fill, 0);
|
|
|
|
|
record_alignment (now_seg, to);
|
|
|
|
|
if (label != NULL)
|
|
|
|
|
{
|
|
|
|
|
assert (S_GET_SEGMENT (label) == now_seg);
|
Add support for storing local symbols in a small structure to save
memory when assembling large files.
* as.h: Don't include struc-symbol.h.
(symbolS): Add typedef.
* symbols.c: Include struc-symbol.h.
(local_hash): New static variable.
(save_symbol_name): New static function, from symbol_create.
(symbol_create): Call save_symbol_name.
(local_symbol_count): New static variable.
(local_symbol_conversion_count): Likewise.
(LOCAL_SYMBOL_CHECK): Define.
(local_symbol_make): New static function.
(local_symbol_convert): New static function.
(colon): Handle local symbols. Create local symbol for local
label name.
(symbol_table_insert): Handle local symbols.
(symbol_find_or_make): Create local symbol for local label name.
(symbol_find_base): Check for local symbol.
(symbol_append, symbol_insert): Check for local symbols.
(symbol_clear_list_pointers, symbol_remove): Likewise.
(verify_symbol_chain): Likewise.
(copy_symbol_attributes): Likewise.
(resolve_symbol_value): Handle local symbols.
(resolve_local_symbol): New static function.
(resolve_local_symbol_values): New function.
(S_GET_VALUE, S_SET_VALUE): Handle local symbols.
(S_IS_FUNCTION, S_IS_EXTERNAL, S_IS_WEAK, S_IS_COMMON): Likewise.
(S_IS_DEFINED, S_IS_DEBUG, S_IS_LOCAL, S_GET_NAME): Likewise.
(S_GET_SEGMENT, S_SET_SEGMENT, S_SET_EXTERNAL): Likewise.
(S_CLEAR_EXTERNAL, S_SET_WEAK, S_SET_NAME): Likewise.
(symbol_previous, symbol_next): New functions.
(symbol_get_value_expression): Likewise.
(symbol_set_value_expression): Likewise.
(symbol_set_frag, symbol_get_frag): Likewise.
(symbol_mark_used, symbol_clear_used, symbol_used_p): Likewise.
(symbol_mark_used_in_reloc): Likewise.
(symbol_clear_used_in_reloc, symbol_used_in_reloc_p): Likewise.
(symbol_mark_mri_common, symbol_clear_mri_common): Likewise.
(symbol_mri_common_p): Likewise.
(symbol_mark_written, symbol_clear_written): Likewise.
(symbol_written_p): Likewise.
(symbol_mark_resolved, symbol_resolved_p): Likewise.
(symbol_section_p, symbol_equated_p): Likewise.
(symbol_constant_p): Likewise.
(symbol_get_bfdsym, symbol_set_bfdsym): Likewise.
(symbol_get_obj, symbol_set_obj): Likewise.
(symbol_get_tc, symbol_set_tc): Likewise.
(symbol_begin): Initialize local_hash.
(print_symbol_value_1): Handle local symbols.
(symbol_print_statistics): Print local symbol statistics.
* symbols.h: Include "struc-symbol.h" if not BFD_ASSEMBLER.
Declare new symbols.c functions. Move many declarations here from
struc-symbol.h.
(SYMBOLS_NEED_BACKPOINTERS): Define if needed.
* struc-symbol.h (SYMBOLS_NEED_BACKPOINTERS): Don't set.
(struct symbol): Move bsym to make it clearly the first field.
Remove TARGET_SYMBOL_FIELDS.
(symbolS): Don't typedef.
(struct broken_word): Remove.
(N_TYPE_seg, seg_N_TYPE): Move to symbol.h.
(SEGMENT_TO_SYMBOL_TYPE, N_REGISTER): Likewise.
(symbol_clear_list_pointers): Likewise.
(symbol_insert, symbol_remove): Likewise.
(symbol_previous, symbol_append): Likewise.
(verify_symbol_chain, verify_symbol_chain_2): Likewise.
(struct local_symbol): Define.
(local_symbol_converted_p, local_symbol_mark_converted): Define.
(local_symbol_resolved_p, local_symbol_mark_resolved): Define.
(local_symbol_get_frag, local_symbol_set_frag): Define.
(local_symbol_get_real_symbol): Define.
(local_symbol_set_real_symbol): Define.
Define.
* write.c (write_object_file): Call resolve_local_symbol_values.
* config/obj-ecoff.h (OBJ_SYMFIELD_TYPE): Define.
(TARGET_SYMBOL_FIELDS): Don't define.
* config/obj-elf.h (OBJ_SYMFIELD_TYPE): Add local field. If
ECOFF_DEBUGGING, add ECOFF fields.
(ELF_TARGET_SYMBOL_FIELDS, TARGET_SYMBOL_FIELDS): Don't define.
* config/obj-multi.h (struct elf_obj_sy): Add local field. If
ECOFF_DEBUGGING, add ECOFF fields.
(ELF_TARGET_SYMBOL_FIELDS, TARGET_SYMBOL_FIELDS): Don't define.
(ECOFF_DEBUG_TARGET_SYMBOL_FIELDS): Don't define.
* config/tc-mcore.h: Don't include struc-symbol.h.
(TARGET_SYMBOL_FIELDS): Don't define.
(struct mcore_tc_sy): Define.
(TC_SYMFIELD_TYPE): Define.
* Many files: Use symbolS instead of struct symbol. Use new
accessor functions rather than referring to symbolS fields
directly.
* read.c (s_mri_common): Don't add in value of line_label.
* config/tc-mips.c (md_apply_fix): Correct parenthesization when
checking for SEC_LINK_ONCE.
* config/tc-sh.h (sh_fix_adjustable): Declare.
1999-06-03 02:29:48 +02:00
|
|
|
|
symbol_set_frag (label, frag_now);
|
1999-05-03 09:29:11 +02:00
|
|
|
|
S_SET_VALUE (label, (valueT) frag_now_fix ());
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/* Align to a given power of two. .align 0 turns off the automatic
|
|
|
|
|
alignment used by the data creating pseudo-ops. */
|
|
|
|
|
|
|
|
|
|
static void
|
2003-06-30 14:44:25 +02:00
|
|
|
|
s_align (int x ATTRIBUTE_UNUSED)
|
1999-05-03 09:29:11 +02:00
|
|
|
|
{
|
|
|
|
|
register int temp;
|
|
|
|
|
register long temp_fill;
|
|
|
|
|
long max_alignment = 15;
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
|
2003-11-22 03:35:31 +01:00
|
|
|
|
o Note that the assembler pulls down any immediately preceding label
|
1999-05-03 09:29:11 +02:00
|
|
|
|
to the aligned address.
|
|
|
|
|
o It's not documented but auto alignment is reinstated by
|
|
|
|
|
a .align pseudo instruction.
|
|
|
|
|
o Note also that after auto alignment is turned off the mips assembler
|
|
|
|
|
issues an error on attempt to assemble an improperly aligned data item.
|
|
|
|
|
We don't.
|
|
|
|
|
|
|
|
|
|
*/
|
|
|
|
|
|
|
|
|
|
temp = get_absolute_expression ();
|
|
|
|
|
if (temp > max_alignment)
|
|
|
|
|
as_bad (_("Alignment too large: %d. assumed."), temp = max_alignment);
|
|
|
|
|
else if (temp < 0)
|
|
|
|
|
{
|
|
|
|
|
as_warn (_("Alignment negative: 0 assumed."));
|
|
|
|
|
temp = 0;
|
|
|
|
|
}
|
|
|
|
|
if (*input_line_pointer == ',')
|
|
|
|
|
{
|
2002-05-26 20:46:37 +02:00
|
|
|
|
++input_line_pointer;
|
1999-05-03 09:29:11 +02:00
|
|
|
|
temp_fill = get_absolute_expression ();
|
|
|
|
|
}
|
|
|
|
|
else
|
|
|
|
|
temp_fill = 0;
|
|
|
|
|
if (temp)
|
|
|
|
|
{
|
|
|
|
|
auto_align = 1;
|
|
|
|
|
mips_align (temp, (int) temp_fill,
|
|
|
|
|
insn_labels != NULL ? insn_labels->label : NULL);
|
|
|
|
|
}
|
|
|
|
|
else
|
|
|
|
|
{
|
|
|
|
|
auto_align = 0;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
demand_empty_rest_of_line ();
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
void
|
2003-06-30 14:44:25 +02:00
|
|
|
|
mips_flush_pending_output (void)
|
1999-05-03 09:29:11 +02:00
|
|
|
|
{
|
2002-11-30 09:39:46 +01:00
|
|
|
|
mips_emit_delays (FALSE);
|
1999-05-03 09:29:11 +02:00
|
|
|
|
mips_clear_insn_labels ();
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static void
|
2003-06-30 14:44:25 +02:00
|
|
|
|
s_change_sec (int sec)
|
1999-05-03 09:29:11 +02:00
|
|
|
|
{
|
|
|
|
|
segT seg;
|
|
|
|
|
|
|
|
|
|
/* When generating embedded PIC code, we only use the .text, .lit8,
|
|
|
|
|
.sdata and .sbss sections. We change the .data and .rdata
|
|
|
|
|
pseudo-ops to use .sdata. */
|
|
|
|
|
if (mips_pic == EMBEDDED_PIC
|
|
|
|
|
&& (sec == 'd' || sec == 'r'))
|
|
|
|
|
sec = 's';
|
|
|
|
|
|
|
|
|
|
#ifdef OBJ_ELF
|
|
|
|
|
/* The ELF backend needs to know that we are changing sections, so
|
|
|
|
|
that .previous works correctly. We could do something like check
|
2001-10-12 01:56:33 +02:00
|
|
|
|
for an obj_section_change_hook macro, but that might be confusing
|
1999-05-03 09:29:11 +02:00
|
|
|
|
as it would not be appropriate to use it in the section changing
|
|
|
|
|
functions in read.c, since obj-elf.c intercepts those. FIXME:
|
|
|
|
|
This should be cleaner, somehow. */
|
|
|
|
|
obj_elf_section_change_hook ();
|
|
|
|
|
#endif
|
|
|
|
|
|
2002-11-30 09:39:46 +01:00
|
|
|
|
mips_emit_delays (FALSE);
|
1999-05-03 09:29:11 +02:00
|
|
|
|
switch (sec)
|
|
|
|
|
{
|
|
|
|
|
case 't':
|
|
|
|
|
s_text (0);
|
|
|
|
|
break;
|
|
|
|
|
case 'd':
|
|
|
|
|
s_data (0);
|
|
|
|
|
break;
|
|
|
|
|
case 'b':
|
|
|
|
|
subseg_set (bss_section, (subsegT) get_absolute_expression ());
|
|
|
|
|
demand_empty_rest_of_line ();
|
|
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
case 'r':
|
|
|
|
|
if (USE_GLOBAL_POINTER_OPT)
|
|
|
|
|
{
|
|
|
|
|
seg = subseg_new (RDATA_SECTION_NAME,
|
|
|
|
|
(subsegT) get_absolute_expression ());
|
|
|
|
|
if (OUTPUT_FLAVOR == bfd_target_elf_flavour)
|
|
|
|
|
{
|
|
|
|
|
bfd_set_section_flags (stdoutput, seg,
|
|
|
|
|
(SEC_ALLOC
|
|
|
|
|
| SEC_LOAD
|
|
|
|
|
| SEC_READONLY
|
|
|
|
|
| SEC_RELOC
|
|
|
|
|
| SEC_DATA));
|
|
|
|
|
if (strcmp (TARGET_OS, "elf") != 0)
|
2000-04-25 12:02:20 +02:00
|
|
|
|
record_alignment (seg, 4);
|
1999-05-03 09:29:11 +02:00
|
|
|
|
}
|
|
|
|
|
demand_empty_rest_of_line ();
|
|
|
|
|
}
|
|
|
|
|
else
|
|
|
|
|
{
|
|
|
|
|
as_bad (_("No read only data section in this object file format"));
|
|
|
|
|
demand_empty_rest_of_line ();
|
|
|
|
|
return;
|
|
|
|
|
}
|
|
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
case 's':
|
|
|
|
|
if (USE_GLOBAL_POINTER_OPT)
|
|
|
|
|
{
|
|
|
|
|
seg = subseg_new (".sdata", (subsegT) get_absolute_expression ());
|
|
|
|
|
if (OUTPUT_FLAVOR == bfd_target_elf_flavour)
|
|
|
|
|
{
|
|
|
|
|
bfd_set_section_flags (stdoutput, seg,
|
|
|
|
|
SEC_ALLOC | SEC_LOAD | SEC_RELOC
|
|
|
|
|
| SEC_DATA);
|
|
|
|
|
if (strcmp (TARGET_OS, "elf") != 0)
|
2000-04-25 12:02:20 +02:00
|
|
|
|
record_alignment (seg, 4);
|
1999-05-03 09:29:11 +02:00
|
|
|
|
}
|
|
|
|
|
demand_empty_rest_of_line ();
|
|
|
|
|
break;
|
|
|
|
|
}
|
|
|
|
|
else
|
|
|
|
|
{
|
|
|
|
|
as_bad (_("Global pointers not supported; recompile -G 0"));
|
|
|
|
|
demand_empty_rest_of_line ();
|
|
|
|
|
return;
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
auto_align = 1;
|
|
|
|
|
}
|
2002-11-30 09:39:46 +01:00
|
|
|
|
|
2002-08-17 17:09:29 +02:00
|
|
|
|
void
|
2003-06-30 14:44:25 +02:00
|
|
|
|
s_change_section (int ignore ATTRIBUTE_UNUSED)
|
2002-08-17 17:09:29 +02:00
|
|
|
|
{
|
2002-09-17 09:43:25 +02:00
|
|
|
|
#ifdef OBJ_ELF
|
2002-08-17 17:09:29 +02:00
|
|
|
|
char *section_name;
|
|
|
|
|
char c;
|
2003-04-25 06:40:09 +02:00
|
|
|
|
char next_c = 0;
|
2002-08-17 17:09:29 +02:00
|
|
|
|
int section_type;
|
|
|
|
|
int section_flag;
|
|
|
|
|
int section_entry_size;
|
|
|
|
|
int section_alignment;
|
2002-11-30 09:39:46 +01:00
|
|
|
|
|
2002-09-17 09:43:25 +02:00
|
|
|
|
if (OUTPUT_FLAVOR != bfd_target_elf_flavour)
|
|
|
|
|
return;
|
|
|
|
|
|
2002-08-17 17:09:29 +02:00
|
|
|
|
section_name = input_line_pointer;
|
|
|
|
|
c = get_symbol_end ();
|
2002-11-18 21:45:48 +01:00
|
|
|
|
if (c)
|
|
|
|
|
next_c = *(input_line_pointer + 1);
|
2002-08-17 17:09:29 +02:00
|
|
|
|
|
2002-09-18 10:02:22 +02:00
|
|
|
|
/* Do we have .section Name<,"flags">? */
|
|
|
|
|
if (c != ',' || (c == ',' && next_c == '"'))
|
2002-08-17 17:09:29 +02:00
|
|
|
|
{
|
2002-09-18 10:02:22 +02:00
|
|
|
|
/* just after name is now '\0'. */
|
|
|
|
|
*input_line_pointer = c;
|
2002-08-17 17:09:29 +02:00
|
|
|
|
input_line_pointer = section_name;
|
|
|
|
|
obj_elf_section (ignore);
|
|
|
|
|
return;
|
|
|
|
|
}
|
|
|
|
|
input_line_pointer++;
|
|
|
|
|
|
|
|
|
|
/* Do we have .section Name<,type><,flag><,entry_size><,alignment> */
|
|
|
|
|
if (c == ',')
|
|
|
|
|
section_type = get_absolute_expression ();
|
|
|
|
|
else
|
|
|
|
|
section_type = 0;
|
|
|
|
|
if (*input_line_pointer++ == ',')
|
|
|
|
|
section_flag = get_absolute_expression ();
|
|
|
|
|
else
|
|
|
|
|
section_flag = 0;
|
|
|
|
|
if (*input_line_pointer++ == ',')
|
|
|
|
|
section_entry_size = get_absolute_expression ();
|
|
|
|
|
else
|
|
|
|
|
section_entry_size = 0;
|
|
|
|
|
if (*input_line_pointer++ == ',')
|
|
|
|
|
section_alignment = get_absolute_expression ();
|
|
|
|
|
else
|
|
|
|
|
section_alignment = 0;
|
|
|
|
|
|
2002-11-18 21:45:48 +01:00
|
|
|
|
section_name = xstrdup (section_name);
|
|
|
|
|
|
2003-12-18 11:18:17 +01:00
|
|
|
|
/* When using the generic form of .section (as implemented by obj-elf.c),
|
|
|
|
|
there's no way to set the section type to SHT_MIPS_DWARF. Users have
|
|
|
|
|
traditionally had to fall back on the more common @progbits instead.
|
|
|
|
|
|
|
|
|
|
There's nothing really harmful in this, since bfd will correct
|
|
|
|
|
SHT_PROGBITS to SHT_MIPS_DWARF before writing out the file. But it
|
|
|
|
|
means that, for backwards compatibiltiy, the special_section entries
|
|
|
|
|
for dwarf sections must use SHT_PROGBITS rather than SHT_MIPS_DWARF.
|
|
|
|
|
|
|
|
|
|
Even so, we shouldn't force users of the MIPS .section syntax to
|
|
|
|
|
incorrectly label the sections as SHT_PROGBITS. The best compromise
|
|
|
|
|
seems to be to map SHT_MIPS_DWARF to SHT_PROGBITS before calling the
|
|
|
|
|
generic type-checking code. */
|
|
|
|
|
if (section_type == SHT_MIPS_DWARF)
|
|
|
|
|
section_type = SHT_PROGBITS;
|
|
|
|
|
|
2002-08-17 17:09:29 +02:00
|
|
|
|
obj_elf_change_section (section_name, section_type, section_flag,
|
|
|
|
|
section_entry_size, 0, 0, 0);
|
2002-11-18 21:45:48 +01:00
|
|
|
|
|
|
|
|
|
if (now_seg->name != section_name)
|
|
|
|
|
free (section_name);
|
2002-09-17 09:43:25 +02:00
|
|
|
|
#endif /* OBJ_ELF */
|
2002-08-17 17:09:29 +02:00
|
|
|
|
}
|
1999-05-03 09:29:11 +02:00
|
|
|
|
|
|
|
|
|
void
|
2003-06-30 14:44:25 +02:00
|
|
|
|
mips_enable_auto_align (void)
|
1999-05-03 09:29:11 +02:00
|
|
|
|
{
|
|
|
|
|
auto_align = 1;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static void
|
2003-06-30 14:44:25 +02:00
|
|
|
|
s_cons (int log_size)
|
1999-05-03 09:29:11 +02:00
|
|
|
|
{
|
|
|
|
|
symbolS *label;
|
|
|
|
|
|
|
|
|
|
label = insn_labels != NULL ? insn_labels->label : NULL;
|
2002-11-30 09:39:46 +01:00
|
|
|
|
mips_emit_delays (FALSE);
|
1999-05-03 09:29:11 +02:00
|
|
|
|
if (log_size > 0 && auto_align)
|
|
|
|
|
mips_align (log_size, 0, label);
|
|
|
|
|
mips_clear_insn_labels ();
|
|
|
|
|
cons (1 << log_size);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static void
|
2003-06-30 14:44:25 +02:00
|
|
|
|
s_float_cons (int type)
|
1999-05-03 09:29:11 +02:00
|
|
|
|
{
|
|
|
|
|
symbolS *label;
|
|
|
|
|
|
|
|
|
|
label = insn_labels != NULL ? insn_labels->label : NULL;
|
|
|
|
|
|
2002-11-30 09:39:46 +01:00
|
|
|
|
mips_emit_delays (FALSE);
|
1999-05-03 09:29:11 +02:00
|
|
|
|
|
|
|
|
|
if (auto_align)
|
Add support for storing local symbols in a small structure to save
memory when assembling large files.
* as.h: Don't include struc-symbol.h.
(symbolS): Add typedef.
* symbols.c: Include struc-symbol.h.
(local_hash): New static variable.
(save_symbol_name): New static function, from symbol_create.
(symbol_create): Call save_symbol_name.
(local_symbol_count): New static variable.
(local_symbol_conversion_count): Likewise.
(LOCAL_SYMBOL_CHECK): Define.
(local_symbol_make): New static function.
(local_symbol_convert): New static function.
(colon): Handle local symbols. Create local symbol for local
label name.
(symbol_table_insert): Handle local symbols.
(symbol_find_or_make): Create local symbol for local label name.
(symbol_find_base): Check for local symbol.
(symbol_append, symbol_insert): Check for local symbols.
(symbol_clear_list_pointers, symbol_remove): Likewise.
(verify_symbol_chain): Likewise.
(copy_symbol_attributes): Likewise.
(resolve_symbol_value): Handle local symbols.
(resolve_local_symbol): New static function.
(resolve_local_symbol_values): New function.
(S_GET_VALUE, S_SET_VALUE): Handle local symbols.
(S_IS_FUNCTION, S_IS_EXTERNAL, S_IS_WEAK, S_IS_COMMON): Likewise.
(S_IS_DEFINED, S_IS_DEBUG, S_IS_LOCAL, S_GET_NAME): Likewise.
(S_GET_SEGMENT, S_SET_SEGMENT, S_SET_EXTERNAL): Likewise.
(S_CLEAR_EXTERNAL, S_SET_WEAK, S_SET_NAME): Likewise.
(symbol_previous, symbol_next): New functions.
(symbol_get_value_expression): Likewise.
(symbol_set_value_expression): Likewise.
(symbol_set_frag, symbol_get_frag): Likewise.
(symbol_mark_used, symbol_clear_used, symbol_used_p): Likewise.
(symbol_mark_used_in_reloc): Likewise.
(symbol_clear_used_in_reloc, symbol_used_in_reloc_p): Likewise.
(symbol_mark_mri_common, symbol_clear_mri_common): Likewise.
(symbol_mri_common_p): Likewise.
(symbol_mark_written, symbol_clear_written): Likewise.
(symbol_written_p): Likewise.
(symbol_mark_resolved, symbol_resolved_p): Likewise.
(symbol_section_p, symbol_equated_p): Likewise.
(symbol_constant_p): Likewise.
(symbol_get_bfdsym, symbol_set_bfdsym): Likewise.
(symbol_get_obj, symbol_set_obj): Likewise.
(symbol_get_tc, symbol_set_tc): Likewise.
(symbol_begin): Initialize local_hash.
(print_symbol_value_1): Handle local symbols.
(symbol_print_statistics): Print local symbol statistics.
* symbols.h: Include "struc-symbol.h" if not BFD_ASSEMBLER.
Declare new symbols.c functions. Move many declarations here from
struc-symbol.h.
(SYMBOLS_NEED_BACKPOINTERS): Define if needed.
* struc-symbol.h (SYMBOLS_NEED_BACKPOINTERS): Don't set.
(struct symbol): Move bsym to make it clearly the first field.
Remove TARGET_SYMBOL_FIELDS.
(symbolS): Don't typedef.
(struct broken_word): Remove.
(N_TYPE_seg, seg_N_TYPE): Move to symbol.h.
(SEGMENT_TO_SYMBOL_TYPE, N_REGISTER): Likewise.
(symbol_clear_list_pointers): Likewise.
(symbol_insert, symbol_remove): Likewise.
(symbol_previous, symbol_append): Likewise.
(verify_symbol_chain, verify_symbol_chain_2): Likewise.
(struct local_symbol): Define.
(local_symbol_converted_p, local_symbol_mark_converted): Define.
(local_symbol_resolved_p, local_symbol_mark_resolved): Define.
(local_symbol_get_frag, local_symbol_set_frag): Define.
(local_symbol_get_real_symbol): Define.
(local_symbol_set_real_symbol): Define.
Define.
* write.c (write_object_file): Call resolve_local_symbol_values.
* config/obj-ecoff.h (OBJ_SYMFIELD_TYPE): Define.
(TARGET_SYMBOL_FIELDS): Don't define.
* config/obj-elf.h (OBJ_SYMFIELD_TYPE): Add local field. If
ECOFF_DEBUGGING, add ECOFF fields.
(ELF_TARGET_SYMBOL_FIELDS, TARGET_SYMBOL_FIELDS): Don't define.
* config/obj-multi.h (struct elf_obj_sy): Add local field. If
ECOFF_DEBUGGING, add ECOFF fields.
(ELF_TARGET_SYMBOL_FIELDS, TARGET_SYMBOL_FIELDS): Don't define.
(ECOFF_DEBUG_TARGET_SYMBOL_FIELDS): Don't define.
* config/tc-mcore.h: Don't include struc-symbol.h.
(TARGET_SYMBOL_FIELDS): Don't define.
(struct mcore_tc_sy): Define.
(TC_SYMFIELD_TYPE): Define.
* Many files: Use symbolS instead of struct symbol. Use new
accessor functions rather than referring to symbolS fields
directly.
* read.c (s_mri_common): Don't add in value of line_label.
* config/tc-mips.c (md_apply_fix): Correct parenthesization when
checking for SEC_LINK_ONCE.
* config/tc-sh.h (sh_fix_adjustable): Declare.
1999-06-03 02:29:48 +02:00
|
|
|
|
{
|
|
|
|
|
if (type == 'd')
|
|
|
|
|
mips_align (3, 0, label);
|
|
|
|
|
else
|
|
|
|
|
mips_align (2, 0, label);
|
|
|
|
|
}
|
1999-05-03 09:29:11 +02:00
|
|
|
|
|
|
|
|
|
mips_clear_insn_labels ();
|
|
|
|
|
|
|
|
|
|
float_cons (type);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/* Handle .globl. We need to override it because on Irix 5 you are
|
|
|
|
|
permitted to say
|
|
|
|
|
.globl foo .text
|
|
|
|
|
where foo is an undefined symbol, to mean that foo should be
|
|
|
|
|
considered to be the address of a function. */
|
|
|
|
|
|
|
|
|
|
static void
|
2003-06-30 14:44:25 +02:00
|
|
|
|
s_mips_globl (int x ATTRIBUTE_UNUSED)
|
1999-05-03 09:29:11 +02:00
|
|
|
|
{
|
|
|
|
|
char *name;
|
|
|
|
|
int c;
|
|
|
|
|
symbolS *symbolP;
|
|
|
|
|
flagword flag;
|
|
|
|
|
|
|
|
|
|
name = input_line_pointer;
|
|
|
|
|
c = get_symbol_end ();
|
|
|
|
|
symbolP = symbol_find_or_make (name);
|
|
|
|
|
*input_line_pointer = c;
|
|
|
|
|
SKIP_WHITESPACE ();
|
|
|
|
|
|
|
|
|
|
/* On Irix 5, every global symbol that is not explicitly labelled as
|
|
|
|
|
being a function is apparently labelled as being an object. */
|
|
|
|
|
flag = BSF_OBJECT;
|
|
|
|
|
|
|
|
|
|
if (! is_end_of_line[(unsigned char) *input_line_pointer])
|
|
|
|
|
{
|
|
|
|
|
char *secname;
|
|
|
|
|
asection *sec;
|
|
|
|
|
|
|
|
|
|
secname = input_line_pointer;
|
|
|
|
|
c = get_symbol_end ();
|
|
|
|
|
sec = bfd_get_section_by_name (stdoutput, secname);
|
|
|
|
|
if (sec == NULL)
|
|
|
|
|
as_bad (_("%s: no such section"), secname);
|
|
|
|
|
*input_line_pointer = c;
|
|
|
|
|
|
|
|
|
|
if (sec != NULL && (sec->flags & SEC_CODE) != 0)
|
|
|
|
|
flag = BSF_FUNCTION;
|
|
|
|
|
}
|
|
|
|
|
|
Add support for storing local symbols in a small structure to save
memory when assembling large files.
* as.h: Don't include struc-symbol.h.
(symbolS): Add typedef.
* symbols.c: Include struc-symbol.h.
(local_hash): New static variable.
(save_symbol_name): New static function, from symbol_create.
(symbol_create): Call save_symbol_name.
(local_symbol_count): New static variable.
(local_symbol_conversion_count): Likewise.
(LOCAL_SYMBOL_CHECK): Define.
(local_symbol_make): New static function.
(local_symbol_convert): New static function.
(colon): Handle local symbols. Create local symbol for local
label name.
(symbol_table_insert): Handle local symbols.
(symbol_find_or_make): Create local symbol for local label name.
(symbol_find_base): Check for local symbol.
(symbol_append, symbol_insert): Check for local symbols.
(symbol_clear_list_pointers, symbol_remove): Likewise.
(verify_symbol_chain): Likewise.
(copy_symbol_attributes): Likewise.
(resolve_symbol_value): Handle local symbols.
(resolve_local_symbol): New static function.
(resolve_local_symbol_values): New function.
(S_GET_VALUE, S_SET_VALUE): Handle local symbols.
(S_IS_FUNCTION, S_IS_EXTERNAL, S_IS_WEAK, S_IS_COMMON): Likewise.
(S_IS_DEFINED, S_IS_DEBUG, S_IS_LOCAL, S_GET_NAME): Likewise.
(S_GET_SEGMENT, S_SET_SEGMENT, S_SET_EXTERNAL): Likewise.
(S_CLEAR_EXTERNAL, S_SET_WEAK, S_SET_NAME): Likewise.
(symbol_previous, symbol_next): New functions.
(symbol_get_value_expression): Likewise.
(symbol_set_value_expression): Likewise.
(symbol_set_frag, symbol_get_frag): Likewise.
(symbol_mark_used, symbol_clear_used, symbol_used_p): Likewise.
(symbol_mark_used_in_reloc): Likewise.
(symbol_clear_used_in_reloc, symbol_used_in_reloc_p): Likewise.
(symbol_mark_mri_common, symbol_clear_mri_common): Likewise.
(symbol_mri_common_p): Likewise.
(symbol_mark_written, symbol_clear_written): Likewise.
(symbol_written_p): Likewise.
(symbol_mark_resolved, symbol_resolved_p): Likewise.
(symbol_section_p, symbol_equated_p): Likewise.
(symbol_constant_p): Likewise.
(symbol_get_bfdsym, symbol_set_bfdsym): Likewise.
(symbol_get_obj, symbol_set_obj): Likewise.
(symbol_get_tc, symbol_set_tc): Likewise.
(symbol_begin): Initialize local_hash.
(print_symbol_value_1): Handle local symbols.
(symbol_print_statistics): Print local symbol statistics.
* symbols.h: Include "struc-symbol.h" if not BFD_ASSEMBLER.
Declare new symbols.c functions. Move many declarations here from
struc-symbol.h.
(SYMBOLS_NEED_BACKPOINTERS): Define if needed.
* struc-symbol.h (SYMBOLS_NEED_BACKPOINTERS): Don't set.
(struct symbol): Move bsym to make it clearly the first field.
Remove TARGET_SYMBOL_FIELDS.
(symbolS): Don't typedef.
(struct broken_word): Remove.
(N_TYPE_seg, seg_N_TYPE): Move to symbol.h.
(SEGMENT_TO_SYMBOL_TYPE, N_REGISTER): Likewise.
(symbol_clear_list_pointers): Likewise.
(symbol_insert, symbol_remove): Likewise.
(symbol_previous, symbol_append): Likewise.
(verify_symbol_chain, verify_symbol_chain_2): Likewise.
(struct local_symbol): Define.
(local_symbol_converted_p, local_symbol_mark_converted): Define.
(local_symbol_resolved_p, local_symbol_mark_resolved): Define.
(local_symbol_get_frag, local_symbol_set_frag): Define.
(local_symbol_get_real_symbol): Define.
(local_symbol_set_real_symbol): Define.
Define.
* write.c (write_object_file): Call resolve_local_symbol_values.
* config/obj-ecoff.h (OBJ_SYMFIELD_TYPE): Define.
(TARGET_SYMBOL_FIELDS): Don't define.
* config/obj-elf.h (OBJ_SYMFIELD_TYPE): Add local field. If
ECOFF_DEBUGGING, add ECOFF fields.
(ELF_TARGET_SYMBOL_FIELDS, TARGET_SYMBOL_FIELDS): Don't define.
* config/obj-multi.h (struct elf_obj_sy): Add local field. If
ECOFF_DEBUGGING, add ECOFF fields.
(ELF_TARGET_SYMBOL_FIELDS, TARGET_SYMBOL_FIELDS): Don't define.
(ECOFF_DEBUG_TARGET_SYMBOL_FIELDS): Don't define.
* config/tc-mcore.h: Don't include struc-symbol.h.
(TARGET_SYMBOL_FIELDS): Don't define.
(struct mcore_tc_sy): Define.
(TC_SYMFIELD_TYPE): Define.
* Many files: Use symbolS instead of struct symbol. Use new
accessor functions rather than referring to symbolS fields
directly.
* read.c (s_mri_common): Don't add in value of line_label.
* config/tc-mips.c (md_apply_fix): Correct parenthesization when
checking for SEC_LINK_ONCE.
* config/tc-sh.h (sh_fix_adjustable): Declare.
1999-06-03 02:29:48 +02:00
|
|
|
|
symbol_get_bfdsym (symbolP)->flags |= flag;
|
1999-05-03 09:29:11 +02:00
|
|
|
|
|
|
|
|
|
S_SET_EXTERNAL (symbolP);
|
|
|
|
|
demand_empty_rest_of_line ();
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static void
|
2003-06-30 14:44:25 +02:00
|
|
|
|
s_option (int x ATTRIBUTE_UNUSED)
|
1999-05-03 09:29:11 +02:00
|
|
|
|
{
|
|
|
|
|
char *opt;
|
|
|
|
|
char c;
|
|
|
|
|
|
|
|
|
|
opt = input_line_pointer;
|
|
|
|
|
c = get_symbol_end ();
|
|
|
|
|
|
|
|
|
|
if (*opt == 'O')
|
|
|
|
|
{
|
|
|
|
|
/* FIXME: What does this mean? */
|
|
|
|
|
}
|
|
|
|
|
else if (strncmp (opt, "pic", 3) == 0)
|
|
|
|
|
{
|
|
|
|
|
int i;
|
|
|
|
|
|
|
|
|
|
i = atoi (opt + 3);
|
|
|
|
|
if (i == 0)
|
|
|
|
|
mips_pic = NO_PIC;
|
|
|
|
|
else if (i == 2)
|
2003-05-21 23:53:33 +02:00
|
|
|
|
{
|
1999-05-03 09:29:11 +02:00
|
|
|
|
mips_pic = SVR4_PIC;
|
2003-05-21 23:53:33 +02:00
|
|
|
|
mips_abicalls = TRUE;
|
|
|
|
|
}
|
1999-05-03 09:29:11 +02:00
|
|
|
|
else
|
|
|
|
|
as_bad (_(".option pic%d not supported"), i);
|
|
|
|
|
|
|
|
|
|
if (USE_GLOBAL_POINTER_OPT && mips_pic == SVR4_PIC)
|
|
|
|
|
{
|
|
|
|
|
if (g_switch_seen && g_switch_value != 0)
|
|
|
|
|
as_warn (_("-G may not be used with SVR4 PIC code"));
|
|
|
|
|
g_switch_value = 0;
|
|
|
|
|
bfd_set_gp_size (stdoutput, 0);
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
else
|
|
|
|
|
as_warn (_("Unrecognized option \"%s\""), opt);
|
|
|
|
|
|
|
|
|
|
*input_line_pointer = c;
|
|
|
|
|
demand_empty_rest_of_line ();
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/* This structure is used to hold a stack of .set values. */
|
|
|
|
|
|
2000-12-12 20:29:24 +01:00
|
|
|
|
struct mips_option_stack
|
|
|
|
|
{
|
1999-05-03 09:29:11 +02:00
|
|
|
|
struct mips_option_stack *next;
|
|
|
|
|
struct mips_set_options options;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
static struct mips_option_stack *mips_opts_stack;
|
|
|
|
|
|
|
|
|
|
/* Handle the .set pseudo-op. */
|
|
|
|
|
|
|
|
|
|
static void
|
2003-06-30 14:44:25 +02:00
|
|
|
|
s_mipsset (int x ATTRIBUTE_UNUSED)
|
1999-05-03 09:29:11 +02:00
|
|
|
|
{
|
|
|
|
|
char *name = input_line_pointer, ch;
|
|
|
|
|
|
|
|
|
|
while (!is_end_of_line[(unsigned char) *input_line_pointer])
|
2002-05-26 20:46:37 +02:00
|
|
|
|
++input_line_pointer;
|
1999-05-03 09:29:11 +02:00
|
|
|
|
ch = *input_line_pointer;
|
|
|
|
|
*input_line_pointer = '\0';
|
|
|
|
|
|
|
|
|
|
if (strcmp (name, "reorder") == 0)
|
|
|
|
|
{
|
|
|
|
|
if (mips_opts.noreorder && prev_nop_frag != NULL)
|
|
|
|
|
{
|
|
|
|
|
/* If we still have pending nops, we can discard them. The
|
|
|
|
|
usual nop handling will insert any that are still
|
2000-09-07 14:45:56 +02:00
|
|
|
|
needed. */
|
1999-05-03 09:29:11 +02:00
|
|
|
|
prev_nop_frag->fr_fix -= (prev_nop_frag_holds
|
|
|
|
|
* (mips_opts.mips16 ? 2 : 4));
|
|
|
|
|
prev_nop_frag = NULL;
|
|
|
|
|
}
|
|
|
|
|
mips_opts.noreorder = 0;
|
|
|
|
|
}
|
|
|
|
|
else if (strcmp (name, "noreorder") == 0)
|
|
|
|
|
{
|
2002-11-30 09:39:46 +01:00
|
|
|
|
mips_emit_delays (TRUE);
|
1999-05-03 09:29:11 +02:00
|
|
|
|
mips_opts.noreorder = 1;
|
|
|
|
|
mips_any_noreorder = 1;
|
|
|
|
|
}
|
|
|
|
|
else if (strcmp (name, "at") == 0)
|
|
|
|
|
{
|
|
|
|
|
mips_opts.noat = 0;
|
|
|
|
|
}
|
|
|
|
|
else if (strcmp (name, "noat") == 0)
|
|
|
|
|
{
|
|
|
|
|
mips_opts.noat = 1;
|
|
|
|
|
}
|
|
|
|
|
else if (strcmp (name, "macro") == 0)
|
|
|
|
|
{
|
|
|
|
|
mips_opts.warn_about_macros = 0;
|
|
|
|
|
}
|
|
|
|
|
else if (strcmp (name, "nomacro") == 0)
|
|
|
|
|
{
|
|
|
|
|
if (mips_opts.noreorder == 0)
|
|
|
|
|
as_bad (_("`noreorder' must be set before `nomacro'"));
|
|
|
|
|
mips_opts.warn_about_macros = 1;
|
|
|
|
|
}
|
|
|
|
|
else if (strcmp (name, "move") == 0 || strcmp (name, "novolatile") == 0)
|
|
|
|
|
{
|
|
|
|
|
mips_opts.nomove = 0;
|
|
|
|
|
}
|
|
|
|
|
else if (strcmp (name, "nomove") == 0 || strcmp (name, "volatile") == 0)
|
|
|
|
|
{
|
|
|
|
|
mips_opts.nomove = 1;
|
|
|
|
|
}
|
|
|
|
|
else if (strcmp (name, "bopt") == 0)
|
|
|
|
|
{
|
|
|
|
|
mips_opts.nobopt = 0;
|
|
|
|
|
}
|
|
|
|
|
else if (strcmp (name, "nobopt") == 0)
|
|
|
|
|
{
|
|
|
|
|
mips_opts.nobopt = 1;
|
|
|
|
|
}
|
|
|
|
|
else if (strcmp (name, "mips16") == 0
|
|
|
|
|
|| strcmp (name, "MIPS-16") == 0)
|
|
|
|
|
mips_opts.mips16 = 1;
|
|
|
|
|
else if (strcmp (name, "nomips16") == 0
|
|
|
|
|
|| strcmp (name, "noMIPS-16") == 0)
|
|
|
|
|
mips_opts.mips16 = 0;
|
2002-03-16 04:09:19 +01:00
|
|
|
|
else if (strcmp (name, "mips3d") == 0)
|
|
|
|
|
mips_opts.ase_mips3d = 1;
|
|
|
|
|
else if (strcmp (name, "nomips3d") == 0)
|
|
|
|
|
mips_opts.ase_mips3d = 0;
|
2002-06-08 01:26:54 +02:00
|
|
|
|
else if (strcmp (name, "mdmx") == 0)
|
|
|
|
|
mips_opts.ase_mdmx = 1;
|
|
|
|
|
else if (strcmp (name, "nomdmx") == 0)
|
|
|
|
|
mips_opts.ase_mdmx = 0;
|
2003-06-30 23:54:19 +02:00
|
|
|
|
else if (strncmp (name, "mips", 4) == 0 || strncmp (name, "arch=", 5) == 0)
|
1999-05-03 09:29:11 +02:00
|
|
|
|
{
|
[ bfd/ChangeLog ]
2002-12-30 Chris Demetriou <cgd@broadcom.com>
* aoutx.h (NAME(aout,machine_type)): Add bfd_mach_mipsisa32r2 case.
* archures.c (bfd_mach_mipsisa32r2): New define.
* bfd-in2.h: Regenerate.
* cpu-mips.c (I_mipsisa32r2): New enum value.
(arch_info_struct): Add entry for I_mipsisa32r2.
* elfxx-mips.c (elf_mips_isa, _bfd_elf_mips_mach)
(_bfd_mips_elf_print_private_bfd_data): Handle E_MIPS_ARCH_32R2.
(_bfd_mips_elf_final_write_processing): Add
bfd_mach_mipsisa32r2 case.
(_bfd_mips_elf_merge_private_bfd_data): Handle merging of
binaries marked as using MIPS32 Release 2.
[ binutils/ChangeLog ]
2002-12-30 Chris Demetriou <cgd@broadcom.com>
* doc/binutils.texi (objdump): Note MIPS HWR (Hardware Register)
changes in MIPS -M options.
[ gas/ChangeLog ]
2002-12-30 Chris Demetriou <cgd@broadcom.com>
* configure.in: Recognize mipsisa32r2, mipsisa32r2el, and
CPU variants.
* configure: Regenerate.
* config/tc-mips.c (ISA_HAS_DROR, ISA_HAS_ROR): New defines.
(macro_build): Handle "K" operand.
(macro2): Use ISA_HAS_DROR and ISA_HAS_ROR in the places where
CPU_HAS_DROR and CPU_HAS_ROR are currently used.
(mips_ip): New variable "lastpos", and implement "+A", "+B",
and "+C" operands for MIPS32 Release 2 ins/ext instructions.
Implement "K" operand for MIPS32 Release 2 rdhwr instruction.
(validate_mips_insn): Implement "+" as a way to extend the
allowed operands, and implement "K", "+A", "+B", and "+C"
operands.
(OPTION_MIPS32R2): New define.
(md_longopts): Add entry for OPTION_MIPS32R2.
(OPTION_ELF_BASE): Adjust to accomodate OPTIONS_MIPS32R2.
(md_parse_option): Handle OPTION_MIPS32R2.
(s_mipsset): Reimplement handling of ".set mipsN" options
and add support for ".set mips32r2".
(mips_cpu_info_table): Add entry for "mips32r2" (MIPS32 Release 2).
(md_show_usage): Document "-mips32r2" option.
* doc/as.texinfo: Document "-mips32r2" option.
* doc/c-mips.texi: Likewise.
[ gas/testsuite/ChangeLog ]
2002-12-30 Chris Demetriou <cgd@broadcom.com>
* gas/mips/cp0-names-mips32r2.d: New test.
* gas/mips/hwr-names-mips32r2.d: New test.
* gas/mips/hwr-names-numeric.d: New test.
* gas/mips/hwr-names.s: New test source file.
* gas/mips/mips32r2.d: New test.
* gas/mips/mips32r2.s: New test source file.
* gas/mips/mips32r2-ill.l: New test.
* gas/mips/mips32r2-ill.s: New test source file.
* gas/mips/mips.exp: Add mips32r2 architecture data array
entry. Run new tests mentioned above.
[ include/elf/ChangeLog ]
2002-12-30 Chris Demetriou <cgd@broadcom.com>
* mips.h (E_MIPS_ARCH_32R2): New define.
[ include/opcode/ChangeLog ]
2002-12-30 Chris Demetriou <cgd@broadcom.com>
* mips.h: Document "+" as the start of two-character operand
type names, and add new "K", "+A", "+B", and "+C" operand types.
(OP_MASK_INSMSB, OP_SH_INSMSB, OP_MASK_EXTMSB)
(OP_SH_EXTMSB, INSN_ISA32R2, ISA_MIPS32R2, CPU_MIPS32R2): New
defines.
[ opcodes/ChangeLog ]
2002-12-30 Chris Demetriou <cgd@broadcom.com>
* mips-dis.c (mips_cp0_names_mips3264r2, mips_hwr_names_numeric)
(mips_hwr_names_mips3264r2): New arrays.
(mips_arch_choice): New "hwr_names" member.
(mips_arch_choices): Adjust for structure change, and add a new
entry for "mips32r2" ISA.
(mips_hwr_names): New variable.
(set_default_mips_dis_options): Set mips_hwr_names.
(parse_mips_dis_option): New "hwr-names" option which sets
mips_hwr_names, and adjust "reg-names=ARCH" to set mips_hwr_names.
(print_insn_arg): Change return type to "int"
and use that to indicate number of characters consumed.
Add support for "+" operand extension character, "+A", "+B",
"+C", and "K" operands.
(print_insn_mips): Adjust for changes to print_insn_arg.
(print_mips_disassembler_options): Adjust for "hwr-names"
addition and "reg-names" change.
* mips-opc (I33): New define (shorthand for INSN_ISA32R2).
(mips_builtin_opcodes): Note that "nop" and "ssnop" are special
forms of "sll". Add new MIPS32 Release 2 instructions: ehb,
di, ei, ext, ins, jr.hb, jalr.hb, mfhc1, mfhc2, mthc1, mthc2,
rdhwr, rdpgpr, seb, seh, synci, wrpgpr, wsbh.
Note that hardware rotate instructions (ror, rorv) can be
used on MIPS32 Release 2, and add the official mnemonics
for them (rotr, rotrv) and the similar "rotl" mnemonic for
left-rotate.
2002-12-31 08:29:29 +01:00
|
|
|
|
int reset = 0;
|
1999-05-03 09:29:11 +02:00
|
|
|
|
|
2003-06-30 23:54:19 +02:00
|
|
|
|
/* Permit the user to change the ISA and architecture on the fly.
|
|
|
|
|
Needless to say, misuse can cause serious problems. */
|
[ bfd/ChangeLog ]
2002-12-30 Chris Demetriou <cgd@broadcom.com>
* aoutx.h (NAME(aout,machine_type)): Add bfd_mach_mipsisa32r2 case.
* archures.c (bfd_mach_mipsisa32r2): New define.
* bfd-in2.h: Regenerate.
* cpu-mips.c (I_mipsisa32r2): New enum value.
(arch_info_struct): Add entry for I_mipsisa32r2.
* elfxx-mips.c (elf_mips_isa, _bfd_elf_mips_mach)
(_bfd_mips_elf_print_private_bfd_data): Handle E_MIPS_ARCH_32R2.
(_bfd_mips_elf_final_write_processing): Add
bfd_mach_mipsisa32r2 case.
(_bfd_mips_elf_merge_private_bfd_data): Handle merging of
binaries marked as using MIPS32 Release 2.
[ binutils/ChangeLog ]
2002-12-30 Chris Demetriou <cgd@broadcom.com>
* doc/binutils.texi (objdump): Note MIPS HWR (Hardware Register)
changes in MIPS -M options.
[ gas/ChangeLog ]
2002-12-30 Chris Demetriou <cgd@broadcom.com>
* configure.in: Recognize mipsisa32r2, mipsisa32r2el, and
CPU variants.
* configure: Regenerate.
* config/tc-mips.c (ISA_HAS_DROR, ISA_HAS_ROR): New defines.
(macro_build): Handle "K" operand.
(macro2): Use ISA_HAS_DROR and ISA_HAS_ROR in the places where
CPU_HAS_DROR and CPU_HAS_ROR are currently used.
(mips_ip): New variable "lastpos", and implement "+A", "+B",
and "+C" operands for MIPS32 Release 2 ins/ext instructions.
Implement "K" operand for MIPS32 Release 2 rdhwr instruction.
(validate_mips_insn): Implement "+" as a way to extend the
allowed operands, and implement "K", "+A", "+B", and "+C"
operands.
(OPTION_MIPS32R2): New define.
(md_longopts): Add entry for OPTION_MIPS32R2.
(OPTION_ELF_BASE): Adjust to accomodate OPTIONS_MIPS32R2.
(md_parse_option): Handle OPTION_MIPS32R2.
(s_mipsset): Reimplement handling of ".set mipsN" options
and add support for ".set mips32r2".
(mips_cpu_info_table): Add entry for "mips32r2" (MIPS32 Release 2).
(md_show_usage): Document "-mips32r2" option.
* doc/as.texinfo: Document "-mips32r2" option.
* doc/c-mips.texi: Likewise.
[ gas/testsuite/ChangeLog ]
2002-12-30 Chris Demetriou <cgd@broadcom.com>
* gas/mips/cp0-names-mips32r2.d: New test.
* gas/mips/hwr-names-mips32r2.d: New test.
* gas/mips/hwr-names-numeric.d: New test.
* gas/mips/hwr-names.s: New test source file.
* gas/mips/mips32r2.d: New test.
* gas/mips/mips32r2.s: New test source file.
* gas/mips/mips32r2-ill.l: New test.
* gas/mips/mips32r2-ill.s: New test source file.
* gas/mips/mips.exp: Add mips32r2 architecture data array
entry. Run new tests mentioned above.
[ include/elf/ChangeLog ]
2002-12-30 Chris Demetriou <cgd@broadcom.com>
* mips.h (E_MIPS_ARCH_32R2): New define.
[ include/opcode/ChangeLog ]
2002-12-30 Chris Demetriou <cgd@broadcom.com>
* mips.h: Document "+" as the start of two-character operand
type names, and add new "K", "+A", "+B", and "+C" operand types.
(OP_MASK_INSMSB, OP_SH_INSMSB, OP_MASK_EXTMSB)
(OP_SH_EXTMSB, INSN_ISA32R2, ISA_MIPS32R2, CPU_MIPS32R2): New
defines.
[ opcodes/ChangeLog ]
2002-12-30 Chris Demetriou <cgd@broadcom.com>
* mips-dis.c (mips_cp0_names_mips3264r2, mips_hwr_names_numeric)
(mips_hwr_names_mips3264r2): New arrays.
(mips_arch_choice): New "hwr_names" member.
(mips_arch_choices): Adjust for structure change, and add a new
entry for "mips32r2" ISA.
(mips_hwr_names): New variable.
(set_default_mips_dis_options): Set mips_hwr_names.
(parse_mips_dis_option): New "hwr-names" option which sets
mips_hwr_names, and adjust "reg-names=ARCH" to set mips_hwr_names.
(print_insn_arg): Change return type to "int"
and use that to indicate number of characters consumed.
Add support for "+" operand extension character, "+A", "+B",
"+C", and "K" operands.
(print_insn_mips): Adjust for changes to print_insn_arg.
(print_mips_disassembler_options): Adjust for "hwr-names"
addition and "reg-names" change.
* mips-opc (I33): New define (shorthand for INSN_ISA32R2).
(mips_builtin_opcodes): Note that "nop" and "ssnop" are special
forms of "sll". Add new MIPS32 Release 2 instructions: ehb,
di, ei, ext, ins, jr.hb, jalr.hb, mfhc1, mfhc2, mthc1, mthc2,
rdhwr, rdpgpr, seb, seh, synci, wrpgpr, wsbh.
Note that hardware rotate instructions (ror, rorv) can be
used on MIPS32 Release 2, and add the official mnemonics
for them (rotr, rotrv) and the similar "rotl" mnemonic for
left-rotate.
2002-12-31 08:29:29 +01:00
|
|
|
|
if (strcmp (name, "mips0") == 0)
|
|
|
|
|
{
|
|
|
|
|
reset = 1;
|
|
|
|
|
mips_opts.isa = file_mips_isa;
|
|
|
|
|
}
|
|
|
|
|
else if (strcmp (name, "mips1") == 0)
|
|
|
|
|
mips_opts.isa = ISA_MIPS1;
|
|
|
|
|
else if (strcmp (name, "mips2") == 0)
|
|
|
|
|
mips_opts.isa = ISA_MIPS2;
|
|
|
|
|
else if (strcmp (name, "mips3") == 0)
|
|
|
|
|
mips_opts.isa = ISA_MIPS3;
|
|
|
|
|
else if (strcmp (name, "mips4") == 0)
|
|
|
|
|
mips_opts.isa = ISA_MIPS4;
|
|
|
|
|
else if (strcmp (name, "mips5") == 0)
|
|
|
|
|
mips_opts.isa = ISA_MIPS5;
|
|
|
|
|
else if (strcmp (name, "mips32") == 0)
|
|
|
|
|
mips_opts.isa = ISA_MIPS32;
|
|
|
|
|
else if (strcmp (name, "mips32r2") == 0)
|
|
|
|
|
mips_opts.isa = ISA_MIPS32R2;
|
|
|
|
|
else if (strcmp (name, "mips64") == 0)
|
|
|
|
|
mips_opts.isa = ISA_MIPS64;
|
[ bfd/ChangeLog ]
2003-09-30 Chris Demetriou <cgd@broadcom.com>
* archures.c (bfd_mach_mipsisa64r2): New define.
* bfd-in2.h: Regenerate.
* aoutx.h (NAME(aout,machine_type)): Handle bfd_mach_mipsisa64r2.
* cpu-mips.c (I_mipsisa64r2): New enum value.
(arch_info_struct): Add entry for I_mipsisa64r2.
* elfxx-mips.c (_bfd_elf_mips_mach)
(_bfd_mips_elf_print_private_bfd_data): Handle E_MIPS_ARCH_64R2.
(mips_set_isa_flags): Add bfd_mach_mipsisa64r2 case.
(mips_mach_extensions): Add entry for bfd_mach_mipsisa64r2.
[ binutils/ChangeLog ]
2003-09-30 Chris Demetriou <cgd@broadcom.com>
* readelf.c (get_machine_flags): Handle E_MIPS_ARCH_64R2.
[ gas/Changelog ]
2003-09-30 Chris Demetriou <cgd@broadcom.com>
* configure.in (mipsisa64r2, mipsisa64r2el, mipsisa64r2*): New CPUs.
* configure: Regenerate.
* config/tc-mips.c (imm2_expr): New variable.
(md_assemble, mips16_ip): Initialize imm2_expr.
(ISA_HAS_64BIT_REGS, ISA_HAS_DROR, ISA_HAS_ROR): Add ISA_MIPS64R2.
(macro_build): Handle +A, +B, +C, +E, +F, +G, and +H format operands.
(macro): Handle M_DEXT and M_DINS.
(validate_mips_insn): Handle +E, +F, +G, +H, and +I format operands.
(mips_ip): Likewise.
(OPTION_MIPS64R2): New define.
(md_longopts): New entry for -mips64r2 (OPTION_MIPS64R2).
OPTION_ASE_BASE): Increase to compensate for OPTION_MIPS64R2.
(md_parse_option): Handle OPTION_MIPS64R2.
(s_mipsset): Handle setting "mips64r2" ISA.
(mips_cpu_info_table): Add mips64r2.
(md_show_usage): Document -mips64r2 option.
* doc/as.texinfo: Docuemnt -mips64r2 option.
* doc/c-mips.texi: Likewise.
[ gas/testsuite/ChangeLog ]
2003-09-30 Chris Demetriou <cgd@broadcom.com>
* gas/mips/cp0-names-mips64r2.d: New file.
* gas/mips/cp0sel-names-mips64r2.d: New file.
* gas/mips/elf_arch_mips64r2.d: New file.
* gas/mips/hwr-names-mips64r2.d: New file.
* gas/mips/mips32r2-ill-fp64.l: New file.
* gas/mips/mips32r2-ill-fp64.s: New file.
* gas/mips/mips64r2-ill.l: New file.
* gas/mips/mips64r2-ill.s: New file.
* gas/mips/mips64r2.d: New file.
* gas/mips/mips64r2.s: New file.
* gas/mips/mips.exp: Define "mips64r2" arch, and run new tests.
[ include/elf/ChangeLog ]
2003-09-30 Chris Demetriou <cgd@broadcom.com>
* mips.h (E_MIPS_ARCH_64R2): New define.
[ include/opcode/ChangeLog ]
2003-09-30 Chris Demetriou <cgd@broadcom.com>
* mips.h: Document +E, +F, +G, +H, and +I operand types.
Update documentation of I, +B and +C operand types.
(INSN_ISA64R2, ISA_MIPS64R2, CPU_MIPS64R2): New defines.
(M_DEXT, M_DINS): New enum values.
[ ld/ChangeLog ]
2003-09-30 Chris Demetriou <cgd@broadcom.com>
* ldmain.c (get_emulation): Ignore "-mips64r2".
[ ld/testsuite/ChangeLog ]
2003-09-30 Chris Demetriou <cgd@broadcom.com>
* ld-mips-elf/mips-elf-flags.exp: Add tests for combinations
with MIPS64r2.
[ opcodes/ChangeLog ]
2003-09-30 Chris Demetriou <cgd@broadcom.com>
* mips-dis.c (mips_arch_choices): Add entry for "mips64r2"
(print_insn_args): Add handing for +E, +F, +G, and +H.
* mips-opc.c (I65): New define for MIPS64r2.
(mips_builtin_opcodes): Add "dext", "dextm", "dextu", "dins",
"dinsm", "dinsu", "drotl", "drotr", "drotr32", "drotrv", "dsbh",
and "dshd" for MIPS64r2. Adjust "dror", "dror32", and "drorv" to
be supported on MIPS64r2.
2003-09-30 18:17:15 +02:00
|
|
|
|
else if (strcmp (name, "mips64r2") == 0)
|
|
|
|
|
mips_opts.isa = ISA_MIPS64R2;
|
2003-06-30 23:54:19 +02:00
|
|
|
|
else if (strcmp (name, "arch=default") == 0)
|
|
|
|
|
{
|
|
|
|
|
reset = 1;
|
|
|
|
|
mips_opts.arch = file_mips_arch;
|
|
|
|
|
mips_opts.isa = file_mips_isa;
|
|
|
|
|
}
|
|
|
|
|
else if (strncmp (name, "arch=", 5) == 0)
|
|
|
|
|
{
|
|
|
|
|
const struct mips_cpu_info *p;
|
|
|
|
|
|
|
|
|
|
p = mips_parse_cpu("internal use", name + 5);
|
|
|
|
|
if (!p)
|
|
|
|
|
as_bad (_("unknown architecture %s"), name + 5);
|
|
|
|
|
else
|
|
|
|
|
{
|
|
|
|
|
mips_opts.arch = p->cpu;
|
|
|
|
|
mips_opts.isa = p->isa;
|
|
|
|
|
}
|
|
|
|
|
}
|
[ bfd/ChangeLog ]
2002-12-30 Chris Demetriou <cgd@broadcom.com>
* aoutx.h (NAME(aout,machine_type)): Add bfd_mach_mipsisa32r2 case.
* archures.c (bfd_mach_mipsisa32r2): New define.
* bfd-in2.h: Regenerate.
* cpu-mips.c (I_mipsisa32r2): New enum value.
(arch_info_struct): Add entry for I_mipsisa32r2.
* elfxx-mips.c (elf_mips_isa, _bfd_elf_mips_mach)
(_bfd_mips_elf_print_private_bfd_data): Handle E_MIPS_ARCH_32R2.
(_bfd_mips_elf_final_write_processing): Add
bfd_mach_mipsisa32r2 case.
(_bfd_mips_elf_merge_private_bfd_data): Handle merging of
binaries marked as using MIPS32 Release 2.
[ binutils/ChangeLog ]
2002-12-30 Chris Demetriou <cgd@broadcom.com>
* doc/binutils.texi (objdump): Note MIPS HWR (Hardware Register)
changes in MIPS -M options.
[ gas/ChangeLog ]
2002-12-30 Chris Demetriou <cgd@broadcom.com>
* configure.in: Recognize mipsisa32r2, mipsisa32r2el, and
CPU variants.
* configure: Regenerate.
* config/tc-mips.c (ISA_HAS_DROR, ISA_HAS_ROR): New defines.
(macro_build): Handle "K" operand.
(macro2): Use ISA_HAS_DROR and ISA_HAS_ROR in the places where
CPU_HAS_DROR and CPU_HAS_ROR are currently used.
(mips_ip): New variable "lastpos", and implement "+A", "+B",
and "+C" operands for MIPS32 Release 2 ins/ext instructions.
Implement "K" operand for MIPS32 Release 2 rdhwr instruction.
(validate_mips_insn): Implement "+" as a way to extend the
allowed operands, and implement "K", "+A", "+B", and "+C"
operands.
(OPTION_MIPS32R2): New define.
(md_longopts): Add entry for OPTION_MIPS32R2.
(OPTION_ELF_BASE): Adjust to accomodate OPTIONS_MIPS32R2.
(md_parse_option): Handle OPTION_MIPS32R2.
(s_mipsset): Reimplement handling of ".set mipsN" options
and add support for ".set mips32r2".
(mips_cpu_info_table): Add entry for "mips32r2" (MIPS32 Release 2).
(md_show_usage): Document "-mips32r2" option.
* doc/as.texinfo: Document "-mips32r2" option.
* doc/c-mips.texi: Likewise.
[ gas/testsuite/ChangeLog ]
2002-12-30 Chris Demetriou <cgd@broadcom.com>
* gas/mips/cp0-names-mips32r2.d: New test.
* gas/mips/hwr-names-mips32r2.d: New test.
* gas/mips/hwr-names-numeric.d: New test.
* gas/mips/hwr-names.s: New test source file.
* gas/mips/mips32r2.d: New test.
* gas/mips/mips32r2.s: New test source file.
* gas/mips/mips32r2-ill.l: New test.
* gas/mips/mips32r2-ill.s: New test source file.
* gas/mips/mips.exp: Add mips32r2 architecture data array
entry. Run new tests mentioned above.
[ include/elf/ChangeLog ]
2002-12-30 Chris Demetriou <cgd@broadcom.com>
* mips.h (E_MIPS_ARCH_32R2): New define.
[ include/opcode/ChangeLog ]
2002-12-30 Chris Demetriou <cgd@broadcom.com>
* mips.h: Document "+" as the start of two-character operand
type names, and add new "K", "+A", "+B", and "+C" operand types.
(OP_MASK_INSMSB, OP_SH_INSMSB, OP_MASK_EXTMSB)
(OP_SH_EXTMSB, INSN_ISA32R2, ISA_MIPS32R2, CPU_MIPS32R2): New
defines.
[ opcodes/ChangeLog ]
2002-12-30 Chris Demetriou <cgd@broadcom.com>
* mips-dis.c (mips_cp0_names_mips3264r2, mips_hwr_names_numeric)
(mips_hwr_names_mips3264r2): New arrays.
(mips_arch_choice): New "hwr_names" member.
(mips_arch_choices): Adjust for structure change, and add a new
entry for "mips32r2" ISA.
(mips_hwr_names): New variable.
(set_default_mips_dis_options): Set mips_hwr_names.
(parse_mips_dis_option): New "hwr-names" option which sets
mips_hwr_names, and adjust "reg-names=ARCH" to set mips_hwr_names.
(print_insn_arg): Change return type to "int"
and use that to indicate number of characters consumed.
Add support for "+" operand extension character, "+A", "+B",
"+C", and "K" operands.
(print_insn_mips): Adjust for changes to print_insn_arg.
(print_mips_disassembler_options): Adjust for "hwr-names"
addition and "reg-names" change.
* mips-opc (I33): New define (shorthand for INSN_ISA32R2).
(mips_builtin_opcodes): Note that "nop" and "ssnop" are special
forms of "sll". Add new MIPS32 Release 2 instructions: ehb,
di, ei, ext, ins, jr.hb, jalr.hb, mfhc1, mfhc2, mthc1, mthc2,
rdhwr, rdpgpr, seb, seh, synci, wrpgpr, wsbh.
Note that hardware rotate instructions (ror, rorv) can be
used on MIPS32 Release 2, and add the official mnemonics
for them (rotr, rotrv) and the similar "rotl" mnemonic for
left-rotate.
2002-12-31 08:29:29 +01:00
|
|
|
|
else
|
|
|
|
|
as_bad (_("unknown ISA level %s"), name + 4);
|
|
|
|
|
|
|
|
|
|
switch (mips_opts.isa)
|
2002-05-04 19:38:00 +02:00
|
|
|
|
{
|
|
|
|
|
case 0:
|
|
|
|
|
break;
|
[ bfd/ChangeLog ]
2002-12-30 Chris Demetriou <cgd@broadcom.com>
* aoutx.h (NAME(aout,machine_type)): Add bfd_mach_mipsisa32r2 case.
* archures.c (bfd_mach_mipsisa32r2): New define.
* bfd-in2.h: Regenerate.
* cpu-mips.c (I_mipsisa32r2): New enum value.
(arch_info_struct): Add entry for I_mipsisa32r2.
* elfxx-mips.c (elf_mips_isa, _bfd_elf_mips_mach)
(_bfd_mips_elf_print_private_bfd_data): Handle E_MIPS_ARCH_32R2.
(_bfd_mips_elf_final_write_processing): Add
bfd_mach_mipsisa32r2 case.
(_bfd_mips_elf_merge_private_bfd_data): Handle merging of
binaries marked as using MIPS32 Release 2.
[ binutils/ChangeLog ]
2002-12-30 Chris Demetriou <cgd@broadcom.com>
* doc/binutils.texi (objdump): Note MIPS HWR (Hardware Register)
changes in MIPS -M options.
[ gas/ChangeLog ]
2002-12-30 Chris Demetriou <cgd@broadcom.com>
* configure.in: Recognize mipsisa32r2, mipsisa32r2el, and
CPU variants.
* configure: Regenerate.
* config/tc-mips.c (ISA_HAS_DROR, ISA_HAS_ROR): New defines.
(macro_build): Handle "K" operand.
(macro2): Use ISA_HAS_DROR and ISA_HAS_ROR in the places where
CPU_HAS_DROR and CPU_HAS_ROR are currently used.
(mips_ip): New variable "lastpos", and implement "+A", "+B",
and "+C" operands for MIPS32 Release 2 ins/ext instructions.
Implement "K" operand for MIPS32 Release 2 rdhwr instruction.
(validate_mips_insn): Implement "+" as a way to extend the
allowed operands, and implement "K", "+A", "+B", and "+C"
operands.
(OPTION_MIPS32R2): New define.
(md_longopts): Add entry for OPTION_MIPS32R2.
(OPTION_ELF_BASE): Adjust to accomodate OPTIONS_MIPS32R2.
(md_parse_option): Handle OPTION_MIPS32R2.
(s_mipsset): Reimplement handling of ".set mipsN" options
and add support for ".set mips32r2".
(mips_cpu_info_table): Add entry for "mips32r2" (MIPS32 Release 2).
(md_show_usage): Document "-mips32r2" option.
* doc/as.texinfo: Document "-mips32r2" option.
* doc/c-mips.texi: Likewise.
[ gas/testsuite/ChangeLog ]
2002-12-30 Chris Demetriou <cgd@broadcom.com>
* gas/mips/cp0-names-mips32r2.d: New test.
* gas/mips/hwr-names-mips32r2.d: New test.
* gas/mips/hwr-names-numeric.d: New test.
* gas/mips/hwr-names.s: New test source file.
* gas/mips/mips32r2.d: New test.
* gas/mips/mips32r2.s: New test source file.
* gas/mips/mips32r2-ill.l: New test.
* gas/mips/mips32r2-ill.s: New test source file.
* gas/mips/mips.exp: Add mips32r2 architecture data array
entry. Run new tests mentioned above.
[ include/elf/ChangeLog ]
2002-12-30 Chris Demetriou <cgd@broadcom.com>
* mips.h (E_MIPS_ARCH_32R2): New define.
[ include/opcode/ChangeLog ]
2002-12-30 Chris Demetriou <cgd@broadcom.com>
* mips.h: Document "+" as the start of two-character operand
type names, and add new "K", "+A", "+B", and "+C" operand types.
(OP_MASK_INSMSB, OP_SH_INSMSB, OP_MASK_EXTMSB)
(OP_SH_EXTMSB, INSN_ISA32R2, ISA_MIPS32R2, CPU_MIPS32R2): New
defines.
[ opcodes/ChangeLog ]
2002-12-30 Chris Demetriou <cgd@broadcom.com>
* mips-dis.c (mips_cp0_names_mips3264r2, mips_hwr_names_numeric)
(mips_hwr_names_mips3264r2): New arrays.
(mips_arch_choice): New "hwr_names" member.
(mips_arch_choices): Adjust for structure change, and add a new
entry for "mips32r2" ISA.
(mips_hwr_names): New variable.
(set_default_mips_dis_options): Set mips_hwr_names.
(parse_mips_dis_option): New "hwr-names" option which sets
mips_hwr_names, and adjust "reg-names=ARCH" to set mips_hwr_names.
(print_insn_arg): Change return type to "int"
and use that to indicate number of characters consumed.
Add support for "+" operand extension character, "+A", "+B",
"+C", and "K" operands.
(print_insn_mips): Adjust for changes to print_insn_arg.
(print_mips_disassembler_options): Adjust for "hwr-names"
addition and "reg-names" change.
* mips-opc (I33): New define (shorthand for INSN_ISA32R2).
(mips_builtin_opcodes): Note that "nop" and "ssnop" are special
forms of "sll". Add new MIPS32 Release 2 instructions: ehb,
di, ei, ext, ins, jr.hb, jalr.hb, mfhc1, mfhc2, mthc1, mthc2,
rdhwr, rdpgpr, seb, seh, synci, wrpgpr, wsbh.
Note that hardware rotate instructions (ror, rorv) can be
used on MIPS32 Release 2, and add the official mnemonics
for them (rotr, rotrv) and the similar "rotl" mnemonic for
left-rotate.
2002-12-31 08:29:29 +01:00
|
|
|
|
case ISA_MIPS1:
|
|
|
|
|
case ISA_MIPS2:
|
|
|
|
|
case ISA_MIPS32:
|
|
|
|
|
case ISA_MIPS32R2:
|
2002-05-04 19:38:00 +02:00
|
|
|
|
mips_opts.gp32 = 1;
|
|
|
|
|
mips_opts.fp32 = 1;
|
|
|
|
|
break;
|
[ bfd/ChangeLog ]
2002-12-30 Chris Demetriou <cgd@broadcom.com>
* aoutx.h (NAME(aout,machine_type)): Add bfd_mach_mipsisa32r2 case.
* archures.c (bfd_mach_mipsisa32r2): New define.
* bfd-in2.h: Regenerate.
* cpu-mips.c (I_mipsisa32r2): New enum value.
(arch_info_struct): Add entry for I_mipsisa32r2.
* elfxx-mips.c (elf_mips_isa, _bfd_elf_mips_mach)
(_bfd_mips_elf_print_private_bfd_data): Handle E_MIPS_ARCH_32R2.
(_bfd_mips_elf_final_write_processing): Add
bfd_mach_mipsisa32r2 case.
(_bfd_mips_elf_merge_private_bfd_data): Handle merging of
binaries marked as using MIPS32 Release 2.
[ binutils/ChangeLog ]
2002-12-30 Chris Demetriou <cgd@broadcom.com>
* doc/binutils.texi (objdump): Note MIPS HWR (Hardware Register)
changes in MIPS -M options.
[ gas/ChangeLog ]
2002-12-30 Chris Demetriou <cgd@broadcom.com>
* configure.in: Recognize mipsisa32r2, mipsisa32r2el, and
CPU variants.
* configure: Regenerate.
* config/tc-mips.c (ISA_HAS_DROR, ISA_HAS_ROR): New defines.
(macro_build): Handle "K" operand.
(macro2): Use ISA_HAS_DROR and ISA_HAS_ROR in the places where
CPU_HAS_DROR and CPU_HAS_ROR are currently used.
(mips_ip): New variable "lastpos", and implement "+A", "+B",
and "+C" operands for MIPS32 Release 2 ins/ext instructions.
Implement "K" operand for MIPS32 Release 2 rdhwr instruction.
(validate_mips_insn): Implement "+" as a way to extend the
allowed operands, and implement "K", "+A", "+B", and "+C"
operands.
(OPTION_MIPS32R2): New define.
(md_longopts): Add entry for OPTION_MIPS32R2.
(OPTION_ELF_BASE): Adjust to accomodate OPTIONS_MIPS32R2.
(md_parse_option): Handle OPTION_MIPS32R2.
(s_mipsset): Reimplement handling of ".set mipsN" options
and add support for ".set mips32r2".
(mips_cpu_info_table): Add entry for "mips32r2" (MIPS32 Release 2).
(md_show_usage): Document "-mips32r2" option.
* doc/as.texinfo: Document "-mips32r2" option.
* doc/c-mips.texi: Likewise.
[ gas/testsuite/ChangeLog ]
2002-12-30 Chris Demetriou <cgd@broadcom.com>
* gas/mips/cp0-names-mips32r2.d: New test.
* gas/mips/hwr-names-mips32r2.d: New test.
* gas/mips/hwr-names-numeric.d: New test.
* gas/mips/hwr-names.s: New test source file.
* gas/mips/mips32r2.d: New test.
* gas/mips/mips32r2.s: New test source file.
* gas/mips/mips32r2-ill.l: New test.
* gas/mips/mips32r2-ill.s: New test source file.
* gas/mips/mips.exp: Add mips32r2 architecture data array
entry. Run new tests mentioned above.
[ include/elf/ChangeLog ]
2002-12-30 Chris Demetriou <cgd@broadcom.com>
* mips.h (E_MIPS_ARCH_32R2): New define.
[ include/opcode/ChangeLog ]
2002-12-30 Chris Demetriou <cgd@broadcom.com>
* mips.h: Document "+" as the start of two-character operand
type names, and add new "K", "+A", "+B", and "+C" operand types.
(OP_MASK_INSMSB, OP_SH_INSMSB, OP_MASK_EXTMSB)
(OP_SH_EXTMSB, INSN_ISA32R2, ISA_MIPS32R2, CPU_MIPS32R2): New
defines.
[ opcodes/ChangeLog ]
2002-12-30 Chris Demetriou <cgd@broadcom.com>
* mips-dis.c (mips_cp0_names_mips3264r2, mips_hwr_names_numeric)
(mips_hwr_names_mips3264r2): New arrays.
(mips_arch_choice): New "hwr_names" member.
(mips_arch_choices): Adjust for structure change, and add a new
entry for "mips32r2" ISA.
(mips_hwr_names): New variable.
(set_default_mips_dis_options): Set mips_hwr_names.
(parse_mips_dis_option): New "hwr-names" option which sets
mips_hwr_names, and adjust "reg-names=ARCH" to set mips_hwr_names.
(print_insn_arg): Change return type to "int"
and use that to indicate number of characters consumed.
Add support for "+" operand extension character, "+A", "+B",
"+C", and "K" operands.
(print_insn_mips): Adjust for changes to print_insn_arg.
(print_mips_disassembler_options): Adjust for "hwr-names"
addition and "reg-names" change.
* mips-opc (I33): New define (shorthand for INSN_ISA32R2).
(mips_builtin_opcodes): Note that "nop" and "ssnop" are special
forms of "sll". Add new MIPS32 Release 2 instructions: ehb,
di, ei, ext, ins, jr.hb, jalr.hb, mfhc1, mfhc2, mthc1, mthc2,
rdhwr, rdpgpr, seb, seh, synci, wrpgpr, wsbh.
Note that hardware rotate instructions (ror, rorv) can be
used on MIPS32 Release 2, and add the official mnemonics
for them (rotr, rotrv) and the similar "rotl" mnemonic for
left-rotate.
2002-12-31 08:29:29 +01:00
|
|
|
|
case ISA_MIPS3:
|
|
|
|
|
case ISA_MIPS4:
|
|
|
|
|
case ISA_MIPS5:
|
|
|
|
|
case ISA_MIPS64:
|
[ bfd/ChangeLog ]
2003-09-30 Chris Demetriou <cgd@broadcom.com>
* archures.c (bfd_mach_mipsisa64r2): New define.
* bfd-in2.h: Regenerate.
* aoutx.h (NAME(aout,machine_type)): Handle bfd_mach_mipsisa64r2.
* cpu-mips.c (I_mipsisa64r2): New enum value.
(arch_info_struct): Add entry for I_mipsisa64r2.
* elfxx-mips.c (_bfd_elf_mips_mach)
(_bfd_mips_elf_print_private_bfd_data): Handle E_MIPS_ARCH_64R2.
(mips_set_isa_flags): Add bfd_mach_mipsisa64r2 case.
(mips_mach_extensions): Add entry for bfd_mach_mipsisa64r2.
[ binutils/ChangeLog ]
2003-09-30 Chris Demetriou <cgd@broadcom.com>
* readelf.c (get_machine_flags): Handle E_MIPS_ARCH_64R2.
[ gas/Changelog ]
2003-09-30 Chris Demetriou <cgd@broadcom.com>
* configure.in (mipsisa64r2, mipsisa64r2el, mipsisa64r2*): New CPUs.
* configure: Regenerate.
* config/tc-mips.c (imm2_expr): New variable.
(md_assemble, mips16_ip): Initialize imm2_expr.
(ISA_HAS_64BIT_REGS, ISA_HAS_DROR, ISA_HAS_ROR): Add ISA_MIPS64R2.
(macro_build): Handle +A, +B, +C, +E, +F, +G, and +H format operands.
(macro): Handle M_DEXT and M_DINS.
(validate_mips_insn): Handle +E, +F, +G, +H, and +I format operands.
(mips_ip): Likewise.
(OPTION_MIPS64R2): New define.
(md_longopts): New entry for -mips64r2 (OPTION_MIPS64R2).
OPTION_ASE_BASE): Increase to compensate for OPTION_MIPS64R2.
(md_parse_option): Handle OPTION_MIPS64R2.
(s_mipsset): Handle setting "mips64r2" ISA.
(mips_cpu_info_table): Add mips64r2.
(md_show_usage): Document -mips64r2 option.
* doc/as.texinfo: Docuemnt -mips64r2 option.
* doc/c-mips.texi: Likewise.
[ gas/testsuite/ChangeLog ]
2003-09-30 Chris Demetriou <cgd@broadcom.com>
* gas/mips/cp0-names-mips64r2.d: New file.
* gas/mips/cp0sel-names-mips64r2.d: New file.
* gas/mips/elf_arch_mips64r2.d: New file.
* gas/mips/hwr-names-mips64r2.d: New file.
* gas/mips/mips32r2-ill-fp64.l: New file.
* gas/mips/mips32r2-ill-fp64.s: New file.
* gas/mips/mips64r2-ill.l: New file.
* gas/mips/mips64r2-ill.s: New file.
* gas/mips/mips64r2.d: New file.
* gas/mips/mips64r2.s: New file.
* gas/mips/mips.exp: Define "mips64r2" arch, and run new tests.
[ include/elf/ChangeLog ]
2003-09-30 Chris Demetriou <cgd@broadcom.com>
* mips.h (E_MIPS_ARCH_64R2): New define.
[ include/opcode/ChangeLog ]
2003-09-30 Chris Demetriou <cgd@broadcom.com>
* mips.h: Document +E, +F, +G, +H, and +I operand types.
Update documentation of I, +B and +C operand types.
(INSN_ISA64R2, ISA_MIPS64R2, CPU_MIPS64R2): New defines.
(M_DEXT, M_DINS): New enum values.
[ ld/ChangeLog ]
2003-09-30 Chris Demetriou <cgd@broadcom.com>
* ldmain.c (get_emulation): Ignore "-mips64r2".
[ ld/testsuite/ChangeLog ]
2003-09-30 Chris Demetriou <cgd@broadcom.com>
* ld-mips-elf/mips-elf-flags.exp: Add tests for combinations
with MIPS64r2.
[ opcodes/ChangeLog ]
2003-09-30 Chris Demetriou <cgd@broadcom.com>
* mips-dis.c (mips_arch_choices): Add entry for "mips64r2"
(print_insn_args): Add handing for +E, +F, +G, and +H.
* mips-opc.c (I65): New define for MIPS64r2.
(mips_builtin_opcodes): Add "dext", "dextm", "dextu", "dins",
"dinsm", "dinsu", "drotl", "drotr", "drotr32", "drotrv", "dsbh",
and "dshd" for MIPS64r2. Adjust "dror", "dror32", and "drorv" to
be supported on MIPS64r2.
2003-09-30 18:17:15 +02:00
|
|
|
|
case ISA_MIPS64R2:
|
2002-05-04 19:38:00 +02:00
|
|
|
|
mips_opts.gp32 = 0;
|
|
|
|
|
mips_opts.fp32 = 0;
|
|
|
|
|
break;
|
|
|
|
|
default:
|
|
|
|
|
as_bad (_("unknown ISA level %s"), name + 4);
|
|
|
|
|
break;
|
|
|
|
|
}
|
[ bfd/ChangeLog ]
2002-12-30 Chris Demetriou <cgd@broadcom.com>
* aoutx.h (NAME(aout,machine_type)): Add bfd_mach_mipsisa32r2 case.
* archures.c (bfd_mach_mipsisa32r2): New define.
* bfd-in2.h: Regenerate.
* cpu-mips.c (I_mipsisa32r2): New enum value.
(arch_info_struct): Add entry for I_mipsisa32r2.
* elfxx-mips.c (elf_mips_isa, _bfd_elf_mips_mach)
(_bfd_mips_elf_print_private_bfd_data): Handle E_MIPS_ARCH_32R2.
(_bfd_mips_elf_final_write_processing): Add
bfd_mach_mipsisa32r2 case.
(_bfd_mips_elf_merge_private_bfd_data): Handle merging of
binaries marked as using MIPS32 Release 2.
[ binutils/ChangeLog ]
2002-12-30 Chris Demetriou <cgd@broadcom.com>
* doc/binutils.texi (objdump): Note MIPS HWR (Hardware Register)
changes in MIPS -M options.
[ gas/ChangeLog ]
2002-12-30 Chris Demetriou <cgd@broadcom.com>
* configure.in: Recognize mipsisa32r2, mipsisa32r2el, and
CPU variants.
* configure: Regenerate.
* config/tc-mips.c (ISA_HAS_DROR, ISA_HAS_ROR): New defines.
(macro_build): Handle "K" operand.
(macro2): Use ISA_HAS_DROR and ISA_HAS_ROR in the places where
CPU_HAS_DROR and CPU_HAS_ROR are currently used.
(mips_ip): New variable "lastpos", and implement "+A", "+B",
and "+C" operands for MIPS32 Release 2 ins/ext instructions.
Implement "K" operand for MIPS32 Release 2 rdhwr instruction.
(validate_mips_insn): Implement "+" as a way to extend the
allowed operands, and implement "K", "+A", "+B", and "+C"
operands.
(OPTION_MIPS32R2): New define.
(md_longopts): Add entry for OPTION_MIPS32R2.
(OPTION_ELF_BASE): Adjust to accomodate OPTIONS_MIPS32R2.
(md_parse_option): Handle OPTION_MIPS32R2.
(s_mipsset): Reimplement handling of ".set mipsN" options
and add support for ".set mips32r2".
(mips_cpu_info_table): Add entry for "mips32r2" (MIPS32 Release 2).
(md_show_usage): Document "-mips32r2" option.
* doc/as.texinfo: Document "-mips32r2" option.
* doc/c-mips.texi: Likewise.
[ gas/testsuite/ChangeLog ]
2002-12-30 Chris Demetriou <cgd@broadcom.com>
* gas/mips/cp0-names-mips32r2.d: New test.
* gas/mips/hwr-names-mips32r2.d: New test.
* gas/mips/hwr-names-numeric.d: New test.
* gas/mips/hwr-names.s: New test source file.
* gas/mips/mips32r2.d: New test.
* gas/mips/mips32r2.s: New test source file.
* gas/mips/mips32r2-ill.l: New test.
* gas/mips/mips32r2-ill.s: New test source file.
* gas/mips/mips.exp: Add mips32r2 architecture data array
entry. Run new tests mentioned above.
[ include/elf/ChangeLog ]
2002-12-30 Chris Demetriou <cgd@broadcom.com>
* mips.h (E_MIPS_ARCH_32R2): New define.
[ include/opcode/ChangeLog ]
2002-12-30 Chris Demetriou <cgd@broadcom.com>
* mips.h: Document "+" as the start of two-character operand
type names, and add new "K", "+A", "+B", and "+C" operand types.
(OP_MASK_INSMSB, OP_SH_INSMSB, OP_MASK_EXTMSB)
(OP_SH_EXTMSB, INSN_ISA32R2, ISA_MIPS32R2, CPU_MIPS32R2): New
defines.
[ opcodes/ChangeLog ]
2002-12-30 Chris Demetriou <cgd@broadcom.com>
* mips-dis.c (mips_cp0_names_mips3264r2, mips_hwr_names_numeric)
(mips_hwr_names_mips3264r2): New arrays.
(mips_arch_choice): New "hwr_names" member.
(mips_arch_choices): Adjust for structure change, and add a new
entry for "mips32r2" ISA.
(mips_hwr_names): New variable.
(set_default_mips_dis_options): Set mips_hwr_names.
(parse_mips_dis_option): New "hwr-names" option which sets
mips_hwr_names, and adjust "reg-names=ARCH" to set mips_hwr_names.
(print_insn_arg): Change return type to "int"
and use that to indicate number of characters consumed.
Add support for "+" operand extension character, "+A", "+B",
"+C", and "K" operands.
(print_insn_mips): Adjust for changes to print_insn_arg.
(print_mips_disassembler_options): Adjust for "hwr-names"
addition and "reg-names" change.
* mips-opc (I33): New define (shorthand for INSN_ISA32R2).
(mips_builtin_opcodes): Note that "nop" and "ssnop" are special
forms of "sll". Add new MIPS32 Release 2 instructions: ehb,
di, ei, ext, ins, jr.hb, jalr.hb, mfhc1, mfhc2, mthc1, mthc2,
rdhwr, rdpgpr, seb, seh, synci, wrpgpr, wsbh.
Note that hardware rotate instructions (ror, rorv) can be
used on MIPS32 Release 2, and add the official mnemonics
for them (rotr, rotrv) and the similar "rotl" mnemonic for
left-rotate.
2002-12-31 08:29:29 +01:00
|
|
|
|
if (reset)
|
2002-05-04 19:38:00 +02:00
|
|
|
|
{
|
[ bfd/ChangeLog ]
2002-12-30 Chris Demetriou <cgd@broadcom.com>
* aoutx.h (NAME(aout,machine_type)): Add bfd_mach_mipsisa32r2 case.
* archures.c (bfd_mach_mipsisa32r2): New define.
* bfd-in2.h: Regenerate.
* cpu-mips.c (I_mipsisa32r2): New enum value.
(arch_info_struct): Add entry for I_mipsisa32r2.
* elfxx-mips.c (elf_mips_isa, _bfd_elf_mips_mach)
(_bfd_mips_elf_print_private_bfd_data): Handle E_MIPS_ARCH_32R2.
(_bfd_mips_elf_final_write_processing): Add
bfd_mach_mipsisa32r2 case.
(_bfd_mips_elf_merge_private_bfd_data): Handle merging of
binaries marked as using MIPS32 Release 2.
[ binutils/ChangeLog ]
2002-12-30 Chris Demetriou <cgd@broadcom.com>
* doc/binutils.texi (objdump): Note MIPS HWR (Hardware Register)
changes in MIPS -M options.
[ gas/ChangeLog ]
2002-12-30 Chris Demetriou <cgd@broadcom.com>
* configure.in: Recognize mipsisa32r2, mipsisa32r2el, and
CPU variants.
* configure: Regenerate.
* config/tc-mips.c (ISA_HAS_DROR, ISA_HAS_ROR): New defines.
(macro_build): Handle "K" operand.
(macro2): Use ISA_HAS_DROR and ISA_HAS_ROR in the places where
CPU_HAS_DROR and CPU_HAS_ROR are currently used.
(mips_ip): New variable "lastpos", and implement "+A", "+B",
and "+C" operands for MIPS32 Release 2 ins/ext instructions.
Implement "K" operand for MIPS32 Release 2 rdhwr instruction.
(validate_mips_insn): Implement "+" as a way to extend the
allowed operands, and implement "K", "+A", "+B", and "+C"
operands.
(OPTION_MIPS32R2): New define.
(md_longopts): Add entry for OPTION_MIPS32R2.
(OPTION_ELF_BASE): Adjust to accomodate OPTIONS_MIPS32R2.
(md_parse_option): Handle OPTION_MIPS32R2.
(s_mipsset): Reimplement handling of ".set mipsN" options
and add support for ".set mips32r2".
(mips_cpu_info_table): Add entry for "mips32r2" (MIPS32 Release 2).
(md_show_usage): Document "-mips32r2" option.
* doc/as.texinfo: Document "-mips32r2" option.
* doc/c-mips.texi: Likewise.
[ gas/testsuite/ChangeLog ]
2002-12-30 Chris Demetriou <cgd@broadcom.com>
* gas/mips/cp0-names-mips32r2.d: New test.
* gas/mips/hwr-names-mips32r2.d: New test.
* gas/mips/hwr-names-numeric.d: New test.
* gas/mips/hwr-names.s: New test source file.
* gas/mips/mips32r2.d: New test.
* gas/mips/mips32r2.s: New test source file.
* gas/mips/mips32r2-ill.l: New test.
* gas/mips/mips32r2-ill.s: New test source file.
* gas/mips/mips.exp: Add mips32r2 architecture data array
entry. Run new tests mentioned above.
[ include/elf/ChangeLog ]
2002-12-30 Chris Demetriou <cgd@broadcom.com>
* mips.h (E_MIPS_ARCH_32R2): New define.
[ include/opcode/ChangeLog ]
2002-12-30 Chris Demetriou <cgd@broadcom.com>
* mips.h: Document "+" as the start of two-character operand
type names, and add new "K", "+A", "+B", and "+C" operand types.
(OP_MASK_INSMSB, OP_SH_INSMSB, OP_MASK_EXTMSB)
(OP_SH_EXTMSB, INSN_ISA32R2, ISA_MIPS32R2, CPU_MIPS32R2): New
defines.
[ opcodes/ChangeLog ]
2002-12-30 Chris Demetriou <cgd@broadcom.com>
* mips-dis.c (mips_cp0_names_mips3264r2, mips_hwr_names_numeric)
(mips_hwr_names_mips3264r2): New arrays.
(mips_arch_choice): New "hwr_names" member.
(mips_arch_choices): Adjust for structure change, and add a new
entry for "mips32r2" ISA.
(mips_hwr_names): New variable.
(set_default_mips_dis_options): Set mips_hwr_names.
(parse_mips_dis_option): New "hwr-names" option which sets
mips_hwr_names, and adjust "reg-names=ARCH" to set mips_hwr_names.
(print_insn_arg): Change return type to "int"
and use that to indicate number of characters consumed.
Add support for "+" operand extension character, "+A", "+B",
"+C", and "K" operands.
(print_insn_mips): Adjust for changes to print_insn_arg.
(print_mips_disassembler_options): Adjust for "hwr-names"
addition and "reg-names" change.
* mips-opc (I33): New define (shorthand for INSN_ISA32R2).
(mips_builtin_opcodes): Note that "nop" and "ssnop" are special
forms of "sll". Add new MIPS32 Release 2 instructions: ehb,
di, ei, ext, ins, jr.hb, jalr.hb, mfhc1, mfhc2, mthc1, mthc2,
rdhwr, rdpgpr, seb, seh, synci, wrpgpr, wsbh.
Note that hardware rotate instructions (ror, rorv) can be
used on MIPS32 Release 2, and add the official mnemonics
for them (rotr, rotrv) and the similar "rotl" mnemonic for
left-rotate.
2002-12-31 08:29:29 +01:00
|
|
|
|
mips_opts.gp32 = file_mips_gp32;
|
|
|
|
|
mips_opts.fp32 = file_mips_fp32;
|
2002-05-04 19:38:00 +02:00
|
|
|
|
}
|
1999-05-03 09:29:11 +02:00
|
|
|
|
}
|
|
|
|
|
else if (strcmp (name, "autoextend") == 0)
|
|
|
|
|
mips_opts.noautoextend = 0;
|
|
|
|
|
else if (strcmp (name, "noautoextend") == 0)
|
|
|
|
|
mips_opts.noautoextend = 1;
|
|
|
|
|
else if (strcmp (name, "push") == 0)
|
|
|
|
|
{
|
|
|
|
|
struct mips_option_stack *s;
|
|
|
|
|
|
|
|
|
|
s = (struct mips_option_stack *) xmalloc (sizeof *s);
|
|
|
|
|
s->next = mips_opts_stack;
|
|
|
|
|
s->options = mips_opts;
|
|
|
|
|
mips_opts_stack = s;
|
|
|
|
|
}
|
|
|
|
|
else if (strcmp (name, "pop") == 0)
|
|
|
|
|
{
|
|
|
|
|
struct mips_option_stack *s;
|
|
|
|
|
|
|
|
|
|
s = mips_opts_stack;
|
|
|
|
|
if (s == NULL)
|
|
|
|
|
as_bad (_(".set pop with no .set push"));
|
|
|
|
|
else
|
|
|
|
|
{
|
|
|
|
|
/* If we're changing the reorder mode we need to handle
|
|
|
|
|
delay slots correctly. */
|
|
|
|
|
if (s->options.noreorder && ! mips_opts.noreorder)
|
2002-11-30 09:39:46 +01:00
|
|
|
|
mips_emit_delays (TRUE);
|
1999-05-03 09:29:11 +02:00
|
|
|
|
else if (! s->options.noreorder && mips_opts.noreorder)
|
|
|
|
|
{
|
|
|
|
|
if (prev_nop_frag != NULL)
|
|
|
|
|
{
|
|
|
|
|
prev_nop_frag->fr_fix -= (prev_nop_frag_holds
|
|
|
|
|
* (mips_opts.mips16 ? 2 : 4));
|
|
|
|
|
prev_nop_frag = NULL;
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
mips_opts = s->options;
|
|
|
|
|
mips_opts_stack = s->next;
|
|
|
|
|
free (s);
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
else
|
|
|
|
|
{
|
|
|
|
|
as_warn (_("Tried to set unrecognized symbol: %s\n"), name);
|
|
|
|
|
}
|
|
|
|
|
*input_line_pointer = ch;
|
|
|
|
|
demand_empty_rest_of_line ();
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/* Handle the .abicalls pseudo-op. I believe this is equivalent to
|
|
|
|
|
.option pic2. It means to generate SVR4 PIC calls. */
|
|
|
|
|
|
|
|
|
|
static void
|
2003-06-30 14:44:25 +02:00
|
|
|
|
s_abicalls (int ignore ATTRIBUTE_UNUSED)
|
1999-05-03 09:29:11 +02:00
|
|
|
|
{
|
|
|
|
|
mips_pic = SVR4_PIC;
|
2003-05-21 23:53:33 +02:00
|
|
|
|
mips_abicalls = TRUE;
|
1999-05-03 09:29:11 +02:00
|
|
|
|
if (USE_GLOBAL_POINTER_OPT)
|
|
|
|
|
{
|
|
|
|
|
if (g_switch_seen && g_switch_value != 0)
|
|
|
|
|
as_warn (_("-G may not be used with SVR4 PIC code"));
|
|
|
|
|
g_switch_value = 0;
|
|
|
|
|
}
|
|
|
|
|
bfd_set_gp_size (stdoutput, 0);
|
|
|
|
|
demand_empty_rest_of_line ();
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/* Handle the .cpload pseudo-op. This is used when generating SVR4
|
|
|
|
|
PIC code. It sets the $gp register for the function based on the
|
|
|
|
|
function address, which is in the register named in the argument.
|
|
|
|
|
This uses a relocation against _gp_disp, which is handled specially
|
|
|
|
|
by the linker. The result is:
|
|
|
|
|
lui $gp,%hi(_gp_disp)
|
|
|
|
|
addiu $gp,$gp,%lo(_gp_disp)
|
|
|
|
|
addu $gp,$gp,.cpload argument
|
|
|
|
|
The .cpload argument is normally $25 == $t9. */
|
|
|
|
|
|
|
|
|
|
static void
|
2003-06-30 14:44:25 +02:00
|
|
|
|
s_cpload (int ignore ATTRIBUTE_UNUSED)
|
1999-05-03 09:29:11 +02:00
|
|
|
|
{
|
|
|
|
|
expressionS ex;
|
|
|
|
|
int icnt = 0;
|
|
|
|
|
|
2001-10-10 03:08:35 +02:00
|
|
|
|
/* If we are not generating SVR4 PIC code, or if this is NewABI code,
|
|
|
|
|
.cpload is ignored. */
|
|
|
|
|
if (mips_pic != SVR4_PIC || HAVE_NEWABI)
|
1999-05-03 09:29:11 +02:00
|
|
|
|
{
|
|
|
|
|
s_ignore (0);
|
|
|
|
|
return;
|
|
|
|
|
}
|
|
|
|
|
|
2001-10-17 07:51:12 +02:00
|
|
|
|
/* .cpload should be in a .set noreorder section. */
|
1999-05-03 09:29:11 +02:00
|
|
|
|
if (mips_opts.noreorder == 0)
|
|
|
|
|
as_warn (_(".cpload not in noreorder section"));
|
|
|
|
|
|
|
|
|
|
ex.X_op = O_symbol;
|
|
|
|
|
ex.X_add_symbol = symbol_find_or_make ("_gp_disp");
|
|
|
|
|
ex.X_op_symbol = NULL;
|
|
|
|
|
ex.X_add_number = 0;
|
|
|
|
|
|
|
|
|
|
/* In ELF, this symbol is implicitly an STT_OBJECT symbol. */
|
Add support for storing local symbols in a small structure to save
memory when assembling large files.
* as.h: Don't include struc-symbol.h.
(symbolS): Add typedef.
* symbols.c: Include struc-symbol.h.
(local_hash): New static variable.
(save_symbol_name): New static function, from symbol_create.
(symbol_create): Call save_symbol_name.
(local_symbol_count): New static variable.
(local_symbol_conversion_count): Likewise.
(LOCAL_SYMBOL_CHECK): Define.
(local_symbol_make): New static function.
(local_symbol_convert): New static function.
(colon): Handle local symbols. Create local symbol for local
label name.
(symbol_table_insert): Handle local symbols.
(symbol_find_or_make): Create local symbol for local label name.
(symbol_find_base): Check for local symbol.
(symbol_append, symbol_insert): Check for local symbols.
(symbol_clear_list_pointers, symbol_remove): Likewise.
(verify_symbol_chain): Likewise.
(copy_symbol_attributes): Likewise.
(resolve_symbol_value): Handle local symbols.
(resolve_local_symbol): New static function.
(resolve_local_symbol_values): New function.
(S_GET_VALUE, S_SET_VALUE): Handle local symbols.
(S_IS_FUNCTION, S_IS_EXTERNAL, S_IS_WEAK, S_IS_COMMON): Likewise.
(S_IS_DEFINED, S_IS_DEBUG, S_IS_LOCAL, S_GET_NAME): Likewise.
(S_GET_SEGMENT, S_SET_SEGMENT, S_SET_EXTERNAL): Likewise.
(S_CLEAR_EXTERNAL, S_SET_WEAK, S_SET_NAME): Likewise.
(symbol_previous, symbol_next): New functions.
(symbol_get_value_expression): Likewise.
(symbol_set_value_expression): Likewise.
(symbol_set_frag, symbol_get_frag): Likewise.
(symbol_mark_used, symbol_clear_used, symbol_used_p): Likewise.
(symbol_mark_used_in_reloc): Likewise.
(symbol_clear_used_in_reloc, symbol_used_in_reloc_p): Likewise.
(symbol_mark_mri_common, symbol_clear_mri_common): Likewise.
(symbol_mri_common_p): Likewise.
(symbol_mark_written, symbol_clear_written): Likewise.
(symbol_written_p): Likewise.
(symbol_mark_resolved, symbol_resolved_p): Likewise.
(symbol_section_p, symbol_equated_p): Likewise.
(symbol_constant_p): Likewise.
(symbol_get_bfdsym, symbol_set_bfdsym): Likewise.
(symbol_get_obj, symbol_set_obj): Likewise.
(symbol_get_tc, symbol_set_tc): Likewise.
(symbol_begin): Initialize local_hash.
(print_symbol_value_1): Handle local symbols.
(symbol_print_statistics): Print local symbol statistics.
* symbols.h: Include "struc-symbol.h" if not BFD_ASSEMBLER.
Declare new symbols.c functions. Move many declarations here from
struc-symbol.h.
(SYMBOLS_NEED_BACKPOINTERS): Define if needed.
* struc-symbol.h (SYMBOLS_NEED_BACKPOINTERS): Don't set.
(struct symbol): Move bsym to make it clearly the first field.
Remove TARGET_SYMBOL_FIELDS.
(symbolS): Don't typedef.
(struct broken_word): Remove.
(N_TYPE_seg, seg_N_TYPE): Move to symbol.h.
(SEGMENT_TO_SYMBOL_TYPE, N_REGISTER): Likewise.
(symbol_clear_list_pointers): Likewise.
(symbol_insert, symbol_remove): Likewise.
(symbol_previous, symbol_append): Likewise.
(verify_symbol_chain, verify_symbol_chain_2): Likewise.
(struct local_symbol): Define.
(local_symbol_converted_p, local_symbol_mark_converted): Define.
(local_symbol_resolved_p, local_symbol_mark_resolved): Define.
(local_symbol_get_frag, local_symbol_set_frag): Define.
(local_symbol_get_real_symbol): Define.
(local_symbol_set_real_symbol): Define.
Define.
* write.c (write_object_file): Call resolve_local_symbol_values.
* config/obj-ecoff.h (OBJ_SYMFIELD_TYPE): Define.
(TARGET_SYMBOL_FIELDS): Don't define.
* config/obj-elf.h (OBJ_SYMFIELD_TYPE): Add local field. If
ECOFF_DEBUGGING, add ECOFF fields.
(ELF_TARGET_SYMBOL_FIELDS, TARGET_SYMBOL_FIELDS): Don't define.
* config/obj-multi.h (struct elf_obj_sy): Add local field. If
ECOFF_DEBUGGING, add ECOFF fields.
(ELF_TARGET_SYMBOL_FIELDS, TARGET_SYMBOL_FIELDS): Don't define.
(ECOFF_DEBUG_TARGET_SYMBOL_FIELDS): Don't define.
* config/tc-mcore.h: Don't include struc-symbol.h.
(TARGET_SYMBOL_FIELDS): Don't define.
(struct mcore_tc_sy): Define.
(TC_SYMFIELD_TYPE): Define.
* Many files: Use symbolS instead of struct symbol. Use new
accessor functions rather than referring to symbolS fields
directly.
* read.c (s_mri_common): Don't add in value of line_label.
* config/tc-mips.c (md_apply_fix): Correct parenthesization when
checking for SEC_LINK_ONCE.
* config/tc-sh.h (sh_fix_adjustable): Declare.
1999-06-03 02:29:48 +02:00
|
|
|
|
symbol_get_bfdsym (ex.X_add_symbol)->flags |= BSF_OBJECT;
|
1999-05-03 09:29:11 +02:00
|
|
|
|
|
2002-05-28 21:23:09 +02:00
|
|
|
|
macro_build_lui (NULL, &icnt, &ex, mips_gp_register);
|
2003-06-30 14:44:25 +02:00
|
|
|
|
macro_build (NULL, &icnt, &ex, "addiu", "t,r,j", mips_gp_register,
|
|
|
|
|
mips_gp_register, BFD_RELOC_LO16);
|
1999-05-03 09:29:11 +02:00
|
|
|
|
|
2003-06-30 14:44:25 +02:00
|
|
|
|
macro_build (NULL, &icnt, NULL, "addu", "d,v,t", mips_gp_register,
|
|
|
|
|
mips_gp_register, tc_get_register (0));
|
1999-05-03 09:29:11 +02:00
|
|
|
|
|
|
|
|
|
demand_empty_rest_of_line ();
|
|
|
|
|
}
|
|
|
|
|
|
2001-10-10 03:08:35 +02:00
|
|
|
|
/* Handle the .cpsetup pseudo-op defined for NewABI PIC code. The syntax is:
|
|
|
|
|
.cpsetup $reg1, offset|$reg2, label
|
|
|
|
|
|
|
|
|
|
If offset is given, this results in:
|
|
|
|
|
sd $gp, offset($sp)
|
2001-12-04 15:38:48 +01:00
|
|
|
|
lui $gp, %hi(%neg(%gp_rel(label)))
|
2002-05-31 04:04:55 +02:00
|
|
|
|
addiu $gp, $gp, %lo(%neg(%gp_rel(label)))
|
|
|
|
|
daddu $gp, $gp, $reg1
|
2001-10-10 03:08:35 +02:00
|
|
|
|
|
|
|
|
|
If $reg2 is given, this results in:
|
|
|
|
|
daddu $reg2, $gp, $0
|
2001-12-04 15:38:48 +01:00
|
|
|
|
lui $gp, %hi(%neg(%gp_rel(label)))
|
2002-05-31 04:04:55 +02:00
|
|
|
|
addiu $gp, $gp, %lo(%neg(%gp_rel(label)))
|
|
|
|
|
daddu $gp, $gp, $reg1
|
|
|
|
|
$reg1 is normally $25 == $t9. */
|
2001-10-10 03:08:35 +02:00
|
|
|
|
static void
|
2003-06-30 14:44:25 +02:00
|
|
|
|
s_cpsetup (int ignore ATTRIBUTE_UNUSED)
|
2001-10-10 03:08:35 +02:00
|
|
|
|
{
|
|
|
|
|
expressionS ex_off;
|
|
|
|
|
expressionS ex_sym;
|
|
|
|
|
int reg1;
|
|
|
|
|
int icnt = 0;
|
2002-08-16 02:58:11 +02:00
|
|
|
|
char *f;
|
2001-10-10 03:08:35 +02:00
|
|
|
|
|
2002-05-15 01:29:23 +02:00
|
|
|
|
/* If we are not generating SVR4 PIC code, .cpsetup is ignored.
|
2001-10-10 03:08:35 +02:00
|
|
|
|
We also need NewABI support. */
|
|
|
|
|
if (mips_pic != SVR4_PIC || ! HAVE_NEWABI)
|
|
|
|
|
{
|
|
|
|
|
s_ignore (0);
|
|
|
|
|
return;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
reg1 = tc_get_register (0);
|
|
|
|
|
SKIP_WHITESPACE ();
|
|
|
|
|
if (*input_line_pointer != ',')
|
|
|
|
|
{
|
|
|
|
|
as_bad (_("missing argument separator ',' for .cpsetup"));
|
|
|
|
|
return;
|
|
|
|
|
}
|
|
|
|
|
else
|
2002-05-31 04:20:04 +02:00
|
|
|
|
++input_line_pointer;
|
2001-10-10 03:08:35 +02:00
|
|
|
|
SKIP_WHITESPACE ();
|
|
|
|
|
if (*input_line_pointer == '$')
|
2002-05-31 04:20:04 +02:00
|
|
|
|
{
|
|
|
|
|
mips_cpreturn_register = tc_get_register (0);
|
|
|
|
|
mips_cpreturn_offset = -1;
|
|
|
|
|
}
|
2001-10-10 03:08:35 +02:00
|
|
|
|
else
|
2002-05-31 04:20:04 +02:00
|
|
|
|
{
|
|
|
|
|
mips_cpreturn_offset = get_absolute_expression ();
|
|
|
|
|
mips_cpreturn_register = -1;
|
|
|
|
|
}
|
2001-10-10 03:08:35 +02:00
|
|
|
|
SKIP_WHITESPACE ();
|
|
|
|
|
if (*input_line_pointer != ',')
|
|
|
|
|
{
|
|
|
|
|
as_bad (_("missing argument separator ',' for .cpsetup"));
|
|
|
|
|
return;
|
|
|
|
|
}
|
|
|
|
|
else
|
2002-05-26 20:46:37 +02:00
|
|
|
|
++input_line_pointer;
|
2001-10-10 03:08:35 +02:00
|
|
|
|
SKIP_WHITESPACE ();
|
2002-08-16 02:58:11 +02:00
|
|
|
|
expression (&ex_sym);
|
2001-10-10 03:08:35 +02:00
|
|
|
|
|
|
|
|
|
if (mips_cpreturn_register == -1)
|
|
|
|
|
{
|
|
|
|
|
ex_off.X_op = O_constant;
|
|
|
|
|
ex_off.X_add_symbol = NULL;
|
|
|
|
|
ex_off.X_op_symbol = NULL;
|
|
|
|
|
ex_off.X_add_number = mips_cpreturn_offset;
|
|
|
|
|
|
2003-06-30 14:44:25 +02:00
|
|
|
|
macro_build (NULL, &icnt, &ex_off, "sd", "t,o(b)", mips_gp_register,
|
|
|
|
|
BFD_RELOC_LO16, SP);
|
2001-10-10 03:08:35 +02:00
|
|
|
|
}
|
|
|
|
|
else
|
2003-06-30 14:44:25 +02:00
|
|
|
|
macro_build (NULL, &icnt, NULL, "daddu", "d,v,t", mips_cpreturn_register,
|
|
|
|
|
mips_gp_register, 0);
|
2001-10-10 03:08:35 +02:00
|
|
|
|
|
2002-08-16 02:58:11 +02:00
|
|
|
|
/* Ensure there's room for the next two instructions, so that `f'
|
|
|
|
|
doesn't end up with an address in the wrong frag. */
|
|
|
|
|
frag_grow (8);
|
|
|
|
|
f = frag_more (0);
|
2003-06-30 14:44:25 +02:00
|
|
|
|
macro_build (NULL, &icnt, &ex_sym, "lui", "t,u", mips_gp_register,
|
|
|
|
|
BFD_RELOC_GPREL16);
|
2002-08-16 02:58:11 +02:00
|
|
|
|
fix_new (frag_now, f - frag_now->fr_literal,
|
2003-05-22 11:19:33 +02:00
|
|
|
|
8, NULL, 0, 0, BFD_RELOC_MIPS_SUB);
|
2002-08-16 02:58:11 +02:00
|
|
|
|
fix_new (frag_now, f - frag_now->fr_literal,
|
2003-05-22 11:19:33 +02:00
|
|
|
|
4, NULL, 0, 0, BFD_RELOC_HI16_S);
|
2002-08-16 02:58:11 +02:00
|
|
|
|
|
|
|
|
|
f = frag_more (0);
|
2003-06-30 14:44:25 +02:00
|
|
|
|
macro_build (NULL, &icnt, &ex_sym, "addiu", "t,r,j", mips_gp_register,
|
|
|
|
|
mips_gp_register, BFD_RELOC_GPREL16);
|
2002-08-16 02:58:11 +02:00
|
|
|
|
fix_new (frag_now, f - frag_now->fr_literal,
|
2003-05-22 11:19:33 +02:00
|
|
|
|
8, NULL, 0, 0, BFD_RELOC_MIPS_SUB);
|
2002-08-16 02:58:11 +02:00
|
|
|
|
fix_new (frag_now, f - frag_now->fr_literal,
|
2003-05-22 11:19:33 +02:00
|
|
|
|
4, NULL, 0, 0, BFD_RELOC_LO16);
|
2002-08-16 02:58:11 +02:00
|
|
|
|
|
2003-06-30 14:44:25 +02:00
|
|
|
|
macro_build (NULL, &icnt, NULL, ADDRESS_ADD_INSN, "d,v,t", mips_gp_register,
|
|
|
|
|
mips_gp_register, reg1);
|
2001-10-10 03:08:35 +02:00
|
|
|
|
|
|
|
|
|
demand_empty_rest_of_line ();
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static void
|
2003-06-30 14:44:25 +02:00
|
|
|
|
s_cplocal (int ignore ATTRIBUTE_UNUSED)
|
2001-10-10 03:08:35 +02:00
|
|
|
|
{
|
|
|
|
|
/* If we are not generating SVR4 PIC code, or if this is not NewABI code,
|
|
|
|
|
.cplocal is ignored. */
|
|
|
|
|
if (mips_pic != SVR4_PIC || ! HAVE_NEWABI)
|
|
|
|
|
{
|
|
|
|
|
s_ignore (0);
|
|
|
|
|
return;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
mips_gp_register = tc_get_register (0);
|
2002-06-08 00:54:47 +02:00
|
|
|
|
demand_empty_rest_of_line ();
|
2001-10-10 03:08:35 +02:00
|
|
|
|
}
|
|
|
|
|
|
1999-05-03 09:29:11 +02:00
|
|
|
|
/* Handle the .cprestore pseudo-op. This stores $gp into a given
|
|
|
|
|
offset from $sp. The offset is remembered, and after making a PIC
|
|
|
|
|
call $gp is restored from that location. */
|
|
|
|
|
|
|
|
|
|
static void
|
2003-06-30 14:44:25 +02:00
|
|
|
|
s_cprestore (int ignore ATTRIBUTE_UNUSED)
|
1999-05-03 09:29:11 +02:00
|
|
|
|
{
|
|
|
|
|
expressionS ex;
|
|
|
|
|
int icnt = 0;
|
|
|
|
|
|
2001-10-10 03:08:35 +02:00
|
|
|
|
/* If we are not generating SVR4 PIC code, or if this is NewABI code,
|
2002-05-28 21:23:09 +02:00
|
|
|
|
.cprestore is ignored. */
|
2001-10-10 03:08:35 +02:00
|
|
|
|
if (mips_pic != SVR4_PIC || HAVE_NEWABI)
|
1999-05-03 09:29:11 +02:00
|
|
|
|
{
|
|
|
|
|
s_ignore (0);
|
|
|
|
|
return;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
mips_cprestore_offset = get_absolute_expression ();
|
2002-01-05 20:06:52 +01:00
|
|
|
|
mips_cprestore_valid = 1;
|
1999-05-03 09:29:11 +02:00
|
|
|
|
|
|
|
|
|
ex.X_op = O_constant;
|
|
|
|
|
ex.X_add_symbol = NULL;
|
|
|
|
|
ex.X_op_symbol = NULL;
|
|
|
|
|
ex.X_add_number = mips_cprestore_offset;
|
|
|
|
|
|
2003-06-30 14:44:25 +02:00
|
|
|
|
macro_build_ldst_constoffset (NULL, &icnt, &ex, ADDRESS_STORE_INSN,
|
2003-09-14 17:24:49 +02:00
|
|
|
|
mips_gp_register, SP, HAVE_64BIT_ADDRESSES);
|
1999-05-03 09:29:11 +02:00
|
|
|
|
|
|
|
|
|
demand_empty_rest_of_line ();
|
|
|
|
|
}
|
|
|
|
|
|
2001-10-10 03:08:35 +02:00
|
|
|
|
/* Handle the .cpreturn pseudo-op defined for NewABI PIC code. If an offset
|
2003-11-22 03:35:31 +01:00
|
|
|
|
was given in the preceding .cpsetup, it results in:
|
2001-10-10 03:08:35 +02:00
|
|
|
|
ld $gp, offset($sp)
|
2001-11-06 22:39:09 +01:00
|
|
|
|
|
2001-10-10 03:08:35 +02:00
|
|
|
|
If a register $reg2 was given there, it results in:
|
2003-10-01 08:09:31 +02:00
|
|
|
|
daddu $gp, $reg2, $0
|
2001-10-10 03:08:35 +02:00
|
|
|
|
*/
|
|
|
|
|
static void
|
2003-06-30 14:44:25 +02:00
|
|
|
|
s_cpreturn (int ignore ATTRIBUTE_UNUSED)
|
2001-10-10 03:08:35 +02:00
|
|
|
|
{
|
|
|
|
|
expressionS ex;
|
|
|
|
|
int icnt = 0;
|
|
|
|
|
|
|
|
|
|
/* If we are not generating SVR4 PIC code, .cpreturn is ignored.
|
|
|
|
|
We also need NewABI support. */
|
|
|
|
|
if (mips_pic != SVR4_PIC || ! HAVE_NEWABI)
|
|
|
|
|
{
|
|
|
|
|
s_ignore (0);
|
|
|
|
|
return;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
if (mips_cpreturn_register == -1)
|
|
|
|
|
{
|
|
|
|
|
ex.X_op = O_constant;
|
|
|
|
|
ex.X_add_symbol = NULL;
|
|
|
|
|
ex.X_op_symbol = NULL;
|
|
|
|
|
ex.X_add_number = mips_cpreturn_offset;
|
|
|
|
|
|
2003-06-30 14:44:25 +02:00
|
|
|
|
macro_build (NULL, &icnt, &ex, "ld", "t,o(b)", mips_gp_register,
|
|
|
|
|
BFD_RELOC_LO16, SP);
|
2001-10-10 03:08:35 +02:00
|
|
|
|
}
|
|
|
|
|
else
|
2003-06-30 14:44:25 +02:00
|
|
|
|
macro_build (NULL, &icnt, NULL, "daddu", "d,v,t", mips_gp_register,
|
|
|
|
|
mips_cpreturn_register, 0);
|
2001-10-10 03:08:35 +02:00
|
|
|
|
|
|
|
|
|
demand_empty_rest_of_line ();
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/* Handle the .gpvalue pseudo-op. This is used when generating NewABI PIC
|
|
|
|
|
code. It sets the offset to use in gp_rel relocations. */
|
|
|
|
|
|
|
|
|
|
static void
|
2003-06-30 14:44:25 +02:00
|
|
|
|
s_gpvalue (int ignore ATTRIBUTE_UNUSED)
|
2001-10-10 03:08:35 +02:00
|
|
|
|
{
|
|
|
|
|
/* If we are not generating SVR4 PIC code, .gpvalue is ignored.
|
|
|
|
|
We also need NewABI support. */
|
|
|
|
|
if (mips_pic != SVR4_PIC || ! HAVE_NEWABI)
|
|
|
|
|
{
|
|
|
|
|
s_ignore (0);
|
|
|
|
|
return;
|
|
|
|
|
}
|
|
|
|
|
|
2002-05-30 23:06:14 +02:00
|
|
|
|
mips_gprel_offset = get_absolute_expression ();
|
2001-10-10 03:08:35 +02:00
|
|
|
|
|
|
|
|
|
demand_empty_rest_of_line ();
|
|
|
|
|
}
|
|
|
|
|
|
1999-05-03 09:29:11 +02:00
|
|
|
|
/* Handle the .gpword pseudo-op. This is used when generating PIC
|
|
|
|
|
code. It generates a 32 bit GP relative reloc. */
|
|
|
|
|
|
|
|
|
|
static void
|
2003-06-30 14:44:25 +02:00
|
|
|
|
s_gpword (int ignore ATTRIBUTE_UNUSED)
|
1999-05-03 09:29:11 +02:00
|
|
|
|
{
|
|
|
|
|
symbolS *label;
|
|
|
|
|
expressionS ex;
|
|
|
|
|
char *p;
|
|
|
|
|
|
|
|
|
|
/* When not generating PIC code, this is treated as .word. */
|
|
|
|
|
if (mips_pic != SVR4_PIC)
|
|
|
|
|
{
|
|
|
|
|
s_cons (2);
|
|
|
|
|
return;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
label = insn_labels != NULL ? insn_labels->label : NULL;
|
2002-11-30 09:39:46 +01:00
|
|
|
|
mips_emit_delays (TRUE);
|
1999-05-03 09:29:11 +02:00
|
|
|
|
if (auto_align)
|
|
|
|
|
mips_align (2, 0, label);
|
|
|
|
|
mips_clear_insn_labels ();
|
|
|
|
|
|
|
|
|
|
expression (&ex);
|
|
|
|
|
|
|
|
|
|
if (ex.X_op != O_symbol || ex.X_add_number != 0)
|
|
|
|
|
{
|
|
|
|
|
as_bad (_("Unsupported use of .gpword"));
|
|
|
|
|
ignore_rest_of_line ();
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
p = frag_more (4);
|
2003-06-30 14:44:25 +02:00
|
|
|
|
md_number_to_chars (p, 0, 4);
|
2002-11-30 09:39:46 +01:00
|
|
|
|
fix_new_exp (frag_now, p - frag_now->fr_literal, 4, &ex, FALSE,
|
2001-12-02 14:14:48 +01:00
|
|
|
|
BFD_RELOC_GPREL32);
|
1999-05-03 09:29:11 +02:00
|
|
|
|
|
|
|
|
|
demand_empty_rest_of_line ();
|
|
|
|
|
}
|
|
|
|
|
|
2002-10-13 23:22:49 +02:00
|
|
|
|
static void
|
2003-06-30 14:44:25 +02:00
|
|
|
|
s_gpdword (int ignore ATTRIBUTE_UNUSED)
|
2002-10-13 23:22:49 +02:00
|
|
|
|
{
|
|
|
|
|
symbolS *label;
|
|
|
|
|
expressionS ex;
|
|
|
|
|
char *p;
|
|
|
|
|
|
|
|
|
|
/* When not generating PIC code, this is treated as .dword. */
|
|
|
|
|
if (mips_pic != SVR4_PIC)
|
|
|
|
|
{
|
|
|
|
|
s_cons (3);
|
|
|
|
|
return;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
label = insn_labels != NULL ? insn_labels->label : NULL;
|
2002-11-30 09:39:46 +01:00
|
|
|
|
mips_emit_delays (TRUE);
|
2002-10-13 23:22:49 +02:00
|
|
|
|
if (auto_align)
|
|
|
|
|
mips_align (3, 0, label);
|
|
|
|
|
mips_clear_insn_labels ();
|
|
|
|
|
|
|
|
|
|
expression (&ex);
|
|
|
|
|
|
|
|
|
|
if (ex.X_op != O_symbol || ex.X_add_number != 0)
|
|
|
|
|
{
|
|
|
|
|
as_bad (_("Unsupported use of .gpdword"));
|
|
|
|
|
ignore_rest_of_line ();
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
p = frag_more (8);
|
2003-06-30 14:44:25 +02:00
|
|
|
|
md_number_to_chars (p, 0, 8);
|
2003-05-22 11:19:33 +02:00
|
|
|
|
fix_new_exp (frag_now, p - frag_now->fr_literal, 4, &ex, FALSE,
|
2002-10-13 23:22:49 +02:00
|
|
|
|
BFD_RELOC_GPREL32);
|
|
|
|
|
|
|
|
|
|
/* GPREL32 composed with 64 gives a 64-bit GP offset. */
|
|
|
|
|
ex.X_op = O_absent;
|
|
|
|
|
ex.X_add_symbol = 0;
|
|
|
|
|
ex.X_add_number = 0;
|
2002-11-30 09:39:46 +01:00
|
|
|
|
fix_new_exp (frag_now, p - frag_now->fr_literal, 8, &ex, FALSE,
|
2002-10-13 23:22:49 +02:00
|
|
|
|
BFD_RELOC_64);
|
|
|
|
|
|
|
|
|
|
demand_empty_rest_of_line ();
|
|
|
|
|
}
|
|
|
|
|
|
1999-05-03 09:29:11 +02:00
|
|
|
|
/* Handle the .cpadd pseudo-op. This is used when dealing with switch
|
|
|
|
|
tables in SVR4 PIC code. */
|
|
|
|
|
|
|
|
|
|
static void
|
2003-06-30 14:44:25 +02:00
|
|
|
|
s_cpadd (int ignore ATTRIBUTE_UNUSED)
|
1999-05-03 09:29:11 +02:00
|
|
|
|
{
|
|
|
|
|
int icnt = 0;
|
|
|
|
|
int reg;
|
|
|
|
|
|
2002-10-13 23:22:49 +02:00
|
|
|
|
/* This is ignored when not generating SVR4 PIC code. */
|
|
|
|
|
if (mips_pic != SVR4_PIC)
|
1999-05-03 09:29:11 +02:00
|
|
|
|
{
|
|
|
|
|
s_ignore (0);
|
|
|
|
|
return;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/* Add $gp to the register named as an argument. */
|
|
|
|
|
reg = tc_get_register (0);
|
2003-06-30 14:44:25 +02:00
|
|
|
|
macro_build (NULL, &icnt, NULL, ADDRESS_ADD_INSN, "d,v,t",
|
|
|
|
|
reg, reg, mips_gp_register);
|
1999-05-03 09:29:11 +02:00
|
|
|
|
|
2000-09-07 14:45:56 +02:00
|
|
|
|
demand_empty_rest_of_line ();
|
1999-05-03 09:29:11 +02:00
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/* Handle the .insn pseudo-op. This marks instruction labels in
|
|
|
|
|
mips16 mode. This permits the linker to handle them specially,
|
|
|
|
|
such as generating jalx instructions when needed. We also make
|
|
|
|
|
them odd for the duration of the assembly, in order to generate the
|
|
|
|
|
right sort of code. We will make them even in the adjust_symtab
|
|
|
|
|
routine, while leaving them marked. This is convenient for the
|
|
|
|
|
debugger and the disassembler. The linker knows to make them odd
|
|
|
|
|
again. */
|
|
|
|
|
|
|
|
|
|
static void
|
2003-06-30 14:44:25 +02:00
|
|
|
|
s_insn (int ignore ATTRIBUTE_UNUSED)
|
1999-05-03 09:29:11 +02:00
|
|
|
|
{
|
2002-05-26 20:46:37 +02:00
|
|
|
|
mips16_mark_labels ();
|
1999-05-03 09:29:11 +02:00
|
|
|
|
|
|
|
|
|
demand_empty_rest_of_line ();
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/* Handle a .stabn directive. We need these in order to mark a label
|
|
|
|
|
as being a mips16 text label correctly. Sometimes the compiler
|
|
|
|
|
will emit a label, followed by a .stabn, and then switch sections.
|
|
|
|
|
If the label and .stabn are in mips16 mode, then the label is
|
|
|
|
|
really a mips16 text label. */
|
|
|
|
|
|
|
|
|
|
static void
|
2003-06-30 14:44:25 +02:00
|
|
|
|
s_mips_stab (int type)
|
1999-05-03 09:29:11 +02:00
|
|
|
|
{
|
2002-05-26 20:46:37 +02:00
|
|
|
|
if (type == 'n')
|
1999-05-03 09:29:11 +02:00
|
|
|
|
mips16_mark_labels ();
|
|
|
|
|
|
|
|
|
|
s_stab (type);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/* Handle the .weakext pseudo-op as defined in Kane and Heinrich.
|
|
|
|
|
*/
|
|
|
|
|
|
|
|
|
|
static void
|
2003-06-30 14:44:25 +02:00
|
|
|
|
s_mips_weakext (int ignore ATTRIBUTE_UNUSED)
|
1999-05-03 09:29:11 +02:00
|
|
|
|
{
|
|
|
|
|
char *name;
|
|
|
|
|
int c;
|
|
|
|
|
symbolS *symbolP;
|
|
|
|
|
expressionS exp;
|
|
|
|
|
|
|
|
|
|
name = input_line_pointer;
|
|
|
|
|
c = get_symbol_end ();
|
|
|
|
|
symbolP = symbol_find_or_make (name);
|
|
|
|
|
S_SET_WEAK (symbolP);
|
|
|
|
|
*input_line_pointer = c;
|
|
|
|
|
|
|
|
|
|
SKIP_WHITESPACE ();
|
|
|
|
|
|
|
|
|
|
if (! is_end_of_line[(unsigned char) *input_line_pointer])
|
|
|
|
|
{
|
|
|
|
|
if (S_IS_DEFINED (symbolP))
|
|
|
|
|
{
|
2001-12-04 15:38:48 +01:00
|
|
|
|
as_bad ("ignoring attempt to redefine symbol %s",
|
1999-05-03 09:29:11 +02:00
|
|
|
|
S_GET_NAME (symbolP));
|
|
|
|
|
ignore_rest_of_line ();
|
|
|
|
|
return;
|
|
|
|
|
}
|
2000-09-07 14:45:56 +02:00
|
|
|
|
|
1999-05-03 09:29:11 +02:00
|
|
|
|
if (*input_line_pointer == ',')
|
|
|
|
|
{
|
|
|
|
|
++input_line_pointer;
|
|
|
|
|
SKIP_WHITESPACE ();
|
|
|
|
|
}
|
2000-09-07 14:45:56 +02:00
|
|
|
|
|
1999-05-03 09:29:11 +02:00
|
|
|
|
expression (&exp);
|
|
|
|
|
if (exp.X_op != O_symbol)
|
|
|
|
|
{
|
|
|
|
|
as_bad ("bad .weakext directive");
|
2002-05-04 19:38:00 +02:00
|
|
|
|
ignore_rest_of_line ();
|
1999-05-03 09:29:11 +02:00
|
|
|
|
return;
|
|
|
|
|
}
|
Add support for storing local symbols in a small structure to save
memory when assembling large files.
* as.h: Don't include struc-symbol.h.
(symbolS): Add typedef.
* symbols.c: Include struc-symbol.h.
(local_hash): New static variable.
(save_symbol_name): New static function, from symbol_create.
(symbol_create): Call save_symbol_name.
(local_symbol_count): New static variable.
(local_symbol_conversion_count): Likewise.
(LOCAL_SYMBOL_CHECK): Define.
(local_symbol_make): New static function.
(local_symbol_convert): New static function.
(colon): Handle local symbols. Create local symbol for local
label name.
(symbol_table_insert): Handle local symbols.
(symbol_find_or_make): Create local symbol for local label name.
(symbol_find_base): Check for local symbol.
(symbol_append, symbol_insert): Check for local symbols.
(symbol_clear_list_pointers, symbol_remove): Likewise.
(verify_symbol_chain): Likewise.
(copy_symbol_attributes): Likewise.
(resolve_symbol_value): Handle local symbols.
(resolve_local_symbol): New static function.
(resolve_local_symbol_values): New function.
(S_GET_VALUE, S_SET_VALUE): Handle local symbols.
(S_IS_FUNCTION, S_IS_EXTERNAL, S_IS_WEAK, S_IS_COMMON): Likewise.
(S_IS_DEFINED, S_IS_DEBUG, S_IS_LOCAL, S_GET_NAME): Likewise.
(S_GET_SEGMENT, S_SET_SEGMENT, S_SET_EXTERNAL): Likewise.
(S_CLEAR_EXTERNAL, S_SET_WEAK, S_SET_NAME): Likewise.
(symbol_previous, symbol_next): New functions.
(symbol_get_value_expression): Likewise.
(symbol_set_value_expression): Likewise.
(symbol_set_frag, symbol_get_frag): Likewise.
(symbol_mark_used, symbol_clear_used, symbol_used_p): Likewise.
(symbol_mark_used_in_reloc): Likewise.
(symbol_clear_used_in_reloc, symbol_used_in_reloc_p): Likewise.
(symbol_mark_mri_common, symbol_clear_mri_common): Likewise.
(symbol_mri_common_p): Likewise.
(symbol_mark_written, symbol_clear_written): Likewise.
(symbol_written_p): Likewise.
(symbol_mark_resolved, symbol_resolved_p): Likewise.
(symbol_section_p, symbol_equated_p): Likewise.
(symbol_constant_p): Likewise.
(symbol_get_bfdsym, symbol_set_bfdsym): Likewise.
(symbol_get_obj, symbol_set_obj): Likewise.
(symbol_get_tc, symbol_set_tc): Likewise.
(symbol_begin): Initialize local_hash.
(print_symbol_value_1): Handle local symbols.
(symbol_print_statistics): Print local symbol statistics.
* symbols.h: Include "struc-symbol.h" if not BFD_ASSEMBLER.
Declare new symbols.c functions. Move many declarations here from
struc-symbol.h.
(SYMBOLS_NEED_BACKPOINTERS): Define if needed.
* struc-symbol.h (SYMBOLS_NEED_BACKPOINTERS): Don't set.
(struct symbol): Move bsym to make it clearly the first field.
Remove TARGET_SYMBOL_FIELDS.
(symbolS): Don't typedef.
(struct broken_word): Remove.
(N_TYPE_seg, seg_N_TYPE): Move to symbol.h.
(SEGMENT_TO_SYMBOL_TYPE, N_REGISTER): Likewise.
(symbol_clear_list_pointers): Likewise.
(symbol_insert, symbol_remove): Likewise.
(symbol_previous, symbol_append): Likewise.
(verify_symbol_chain, verify_symbol_chain_2): Likewise.
(struct local_symbol): Define.
(local_symbol_converted_p, local_symbol_mark_converted): Define.
(local_symbol_resolved_p, local_symbol_mark_resolved): Define.
(local_symbol_get_frag, local_symbol_set_frag): Define.
(local_symbol_get_real_symbol): Define.
(local_symbol_set_real_symbol): Define.
Define.
* write.c (write_object_file): Call resolve_local_symbol_values.
* config/obj-ecoff.h (OBJ_SYMFIELD_TYPE): Define.
(TARGET_SYMBOL_FIELDS): Don't define.
* config/obj-elf.h (OBJ_SYMFIELD_TYPE): Add local field. If
ECOFF_DEBUGGING, add ECOFF fields.
(ELF_TARGET_SYMBOL_FIELDS, TARGET_SYMBOL_FIELDS): Don't define.
* config/obj-multi.h (struct elf_obj_sy): Add local field. If
ECOFF_DEBUGGING, add ECOFF fields.
(ELF_TARGET_SYMBOL_FIELDS, TARGET_SYMBOL_FIELDS): Don't define.
(ECOFF_DEBUG_TARGET_SYMBOL_FIELDS): Don't define.
* config/tc-mcore.h: Don't include struc-symbol.h.
(TARGET_SYMBOL_FIELDS): Don't define.
(struct mcore_tc_sy): Define.
(TC_SYMFIELD_TYPE): Define.
* Many files: Use symbolS instead of struct symbol. Use new
accessor functions rather than referring to symbolS fields
directly.
* read.c (s_mri_common): Don't add in value of line_label.
* config/tc-mips.c (md_apply_fix): Correct parenthesization when
checking for SEC_LINK_ONCE.
* config/tc-sh.h (sh_fix_adjustable): Declare.
1999-06-03 02:29:48 +02:00
|
|
|
|
symbol_set_value_expression (symbolP, &exp);
|
1999-05-03 09:29:11 +02:00
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
demand_empty_rest_of_line ();
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/* Parse a register string into a number. Called from the ECOFF code
|
|
|
|
|
to parse .frame. The argument is non-zero if this is the frame
|
|
|
|
|
register, so that we can record it in mips_frame_reg. */
|
|
|
|
|
|
|
|
|
|
int
|
2003-06-30 14:44:25 +02:00
|
|
|
|
tc_get_register (int frame)
|
1999-05-03 09:29:11 +02:00
|
|
|
|
{
|
|
|
|
|
int reg;
|
|
|
|
|
|
|
|
|
|
SKIP_WHITESPACE ();
|
|
|
|
|
if (*input_line_pointer++ != '$')
|
|
|
|
|
{
|
|
|
|
|
as_warn (_("expected `$'"));
|
2002-06-08 00:54:47 +02:00
|
|
|
|
reg = ZERO;
|
1999-05-03 09:29:11 +02:00
|
|
|
|
}
|
2001-09-19 07:33:36 +02:00
|
|
|
|
else if (ISDIGIT (*input_line_pointer))
|
1999-05-03 09:29:11 +02:00
|
|
|
|
{
|
|
|
|
|
reg = get_absolute_expression ();
|
|
|
|
|
if (reg < 0 || reg >= 32)
|
|
|
|
|
{
|
|
|
|
|
as_warn (_("Bad register number"));
|
2002-06-08 00:54:47 +02:00
|
|
|
|
reg = ZERO;
|
1999-05-03 09:29:11 +02:00
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
else
|
|
|
|
|
{
|
2002-05-31 03:58:18 +02:00
|
|
|
|
if (strncmp (input_line_pointer, "ra", 2) == 0)
|
2002-06-08 00:54:47 +02:00
|
|
|
|
{
|
|
|
|
|
reg = RA;
|
|
|
|
|
input_line_pointer += 2;
|
|
|
|
|
}
|
2002-05-31 03:58:18 +02:00
|
|
|
|
else if (strncmp (input_line_pointer, "fp", 2) == 0)
|
2002-06-08 00:54:47 +02:00
|
|
|
|
{
|
|
|
|
|
reg = FP;
|
|
|
|
|
input_line_pointer += 2;
|
|
|
|
|
}
|
1999-05-03 09:29:11 +02:00
|
|
|
|
else if (strncmp (input_line_pointer, "sp", 2) == 0)
|
2002-06-08 00:54:47 +02:00
|
|
|
|
{
|
|
|
|
|
reg = SP;
|
|
|
|
|
input_line_pointer += 2;
|
|
|
|
|
}
|
1999-05-03 09:29:11 +02:00
|
|
|
|
else if (strncmp (input_line_pointer, "gp", 2) == 0)
|
2002-06-08 00:54:47 +02:00
|
|
|
|
{
|
|
|
|
|
reg = GP;
|
|
|
|
|
input_line_pointer += 2;
|
|
|
|
|
}
|
1999-05-03 09:29:11 +02:00
|
|
|
|
else if (strncmp (input_line_pointer, "at", 2) == 0)
|
2002-06-08 00:54:47 +02:00
|
|
|
|
{
|
|
|
|
|
reg = AT;
|
|
|
|
|
input_line_pointer += 2;
|
|
|
|
|
}
|
|
|
|
|
else if (strncmp (input_line_pointer, "kt0", 3) == 0)
|
|
|
|
|
{
|
|
|
|
|
reg = KT0;
|
|
|
|
|
input_line_pointer += 3;
|
|
|
|
|
}
|
|
|
|
|
else if (strncmp (input_line_pointer, "kt1", 3) == 0)
|
|
|
|
|
{
|
|
|
|
|
reg = KT1;
|
|
|
|
|
input_line_pointer += 3;
|
|
|
|
|
}
|
|
|
|
|
else if (strncmp (input_line_pointer, "zero", 4) == 0)
|
|
|
|
|
{
|
|
|
|
|
reg = ZERO;
|
|
|
|
|
input_line_pointer += 4;
|
|
|
|
|
}
|
1999-05-03 09:29:11 +02:00
|
|
|
|
else
|
|
|
|
|
{
|
|
|
|
|
as_warn (_("Unrecognized register name"));
|
2002-06-08 00:54:47 +02:00
|
|
|
|
reg = ZERO;
|
|
|
|
|
while (ISALNUM(*input_line_pointer))
|
|
|
|
|
input_line_pointer++;
|
1999-05-03 09:29:11 +02:00
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
if (frame)
|
2002-01-05 20:06:52 +01:00
|
|
|
|
{
|
|
|
|
|
mips_frame_reg = reg != 0 ? reg : SP;
|
|
|
|
|
mips_frame_reg_valid = 1;
|
|
|
|
|
mips_cprestore_valid = 0;
|
|
|
|
|
}
|
1999-05-03 09:29:11 +02:00
|
|
|
|
return reg;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
valueT
|
2003-06-30 14:44:25 +02:00
|
|
|
|
md_section_align (asection *seg, valueT addr)
|
1999-05-03 09:29:11 +02:00
|
|
|
|
{
|
|
|
|
|
int align = bfd_get_section_alignment (stdoutput, seg);
|
|
|
|
|
|
|
|
|
|
#ifdef OBJ_ELF
|
|
|
|
|
/* We don't need to align ELF sections to the full alignment.
|
|
|
|
|
However, Irix 5 may prefer that we align them at least to a 16
|
|
|
|
|
byte boundary. We don't bother to align the sections if we are
|
|
|
|
|
targeted for an embedded system. */
|
|
|
|
|
if (strcmp (TARGET_OS, "elf") == 0)
|
|
|
|
|
return addr;
|
|
|
|
|
if (align > 4)
|
|
|
|
|
align = 4;
|
|
|
|
|
#endif
|
|
|
|
|
|
|
|
|
|
return ((addr + (1 << align) - 1) & (-1 << align));
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/* Utility routine, called from above as well. If called while the
|
|
|
|
|
input file is still being read, it's only an approximation. (For
|
|
|
|
|
example, a symbol may later become defined which appeared to be
|
|
|
|
|
undefined earlier.) */
|
|
|
|
|
|
|
|
|
|
static int
|
2003-06-30 14:44:25 +02:00
|
|
|
|
nopic_need_relax (symbolS *sym, int before_relaxing)
|
1999-05-03 09:29:11 +02:00
|
|
|
|
{
|
|
|
|
|
if (sym == 0)
|
|
|
|
|
return 0;
|
|
|
|
|
|
2001-10-10 03:08:35 +02:00
|
|
|
|
if (USE_GLOBAL_POINTER_OPT && g_switch_value > 0)
|
1999-05-03 09:29:11 +02:00
|
|
|
|
{
|
|
|
|
|
const char *symname;
|
|
|
|
|
int change;
|
|
|
|
|
|
2002-05-28 21:23:09 +02:00
|
|
|
|
/* Find out whether this symbol can be referenced off the $gp
|
1999-05-03 09:29:11 +02:00
|
|
|
|
register. It can be if it is smaller than the -G size or if
|
|
|
|
|
it is in the .sdata or .sbss section. Certain symbols can
|
2002-05-28 21:23:09 +02:00
|
|
|
|
not be referenced off the $gp, although it appears as though
|
1999-05-03 09:29:11 +02:00
|
|
|
|
they can. */
|
|
|
|
|
symname = S_GET_NAME (sym);
|
|
|
|
|
if (symname != (const char *) NULL
|
|
|
|
|
&& (strcmp (symname, "eprol") == 0
|
|
|
|
|
|| strcmp (symname, "etext") == 0
|
|
|
|
|
|| strcmp (symname, "_gp") == 0
|
|
|
|
|
|| strcmp (symname, "edata") == 0
|
|
|
|
|
|| strcmp (symname, "_fbss") == 0
|
|
|
|
|
|| strcmp (symname, "_fdata") == 0
|
|
|
|
|
|| strcmp (symname, "_ftext") == 0
|
|
|
|
|
|| strcmp (symname, "end") == 0
|
|
|
|
|
|| strcmp (symname, "_gp_disp") == 0))
|
|
|
|
|
change = 1;
|
|
|
|
|
else if ((! S_IS_DEFINED (sym) || S_IS_COMMON (sym))
|
|
|
|
|
&& (0
|
|
|
|
|
#ifndef NO_ECOFF_DEBUGGING
|
Add support for storing local symbols in a small structure to save
memory when assembling large files.
* as.h: Don't include struc-symbol.h.
(symbolS): Add typedef.
* symbols.c: Include struc-symbol.h.
(local_hash): New static variable.
(save_symbol_name): New static function, from symbol_create.
(symbol_create): Call save_symbol_name.
(local_symbol_count): New static variable.
(local_symbol_conversion_count): Likewise.
(LOCAL_SYMBOL_CHECK): Define.
(local_symbol_make): New static function.
(local_symbol_convert): New static function.
(colon): Handle local symbols. Create local symbol for local
label name.
(symbol_table_insert): Handle local symbols.
(symbol_find_or_make): Create local symbol for local label name.
(symbol_find_base): Check for local symbol.
(symbol_append, symbol_insert): Check for local symbols.
(symbol_clear_list_pointers, symbol_remove): Likewise.
(verify_symbol_chain): Likewise.
(copy_symbol_attributes): Likewise.
(resolve_symbol_value): Handle local symbols.
(resolve_local_symbol): New static function.
(resolve_local_symbol_values): New function.
(S_GET_VALUE, S_SET_VALUE): Handle local symbols.
(S_IS_FUNCTION, S_IS_EXTERNAL, S_IS_WEAK, S_IS_COMMON): Likewise.
(S_IS_DEFINED, S_IS_DEBUG, S_IS_LOCAL, S_GET_NAME): Likewise.
(S_GET_SEGMENT, S_SET_SEGMENT, S_SET_EXTERNAL): Likewise.
(S_CLEAR_EXTERNAL, S_SET_WEAK, S_SET_NAME): Likewise.
(symbol_previous, symbol_next): New functions.
(symbol_get_value_expression): Likewise.
(symbol_set_value_expression): Likewise.
(symbol_set_frag, symbol_get_frag): Likewise.
(symbol_mark_used, symbol_clear_used, symbol_used_p): Likewise.
(symbol_mark_used_in_reloc): Likewise.
(symbol_clear_used_in_reloc, symbol_used_in_reloc_p): Likewise.
(symbol_mark_mri_common, symbol_clear_mri_common): Likewise.
(symbol_mri_common_p): Likewise.
(symbol_mark_written, symbol_clear_written): Likewise.
(symbol_written_p): Likewise.
(symbol_mark_resolved, symbol_resolved_p): Likewise.
(symbol_section_p, symbol_equated_p): Likewise.
(symbol_constant_p): Likewise.
(symbol_get_bfdsym, symbol_set_bfdsym): Likewise.
(symbol_get_obj, symbol_set_obj): Likewise.
(symbol_get_tc, symbol_set_tc): Likewise.
(symbol_begin): Initialize local_hash.
(print_symbol_value_1): Handle local symbols.
(symbol_print_statistics): Print local symbol statistics.
* symbols.h: Include "struc-symbol.h" if not BFD_ASSEMBLER.
Declare new symbols.c functions. Move many declarations here from
struc-symbol.h.
(SYMBOLS_NEED_BACKPOINTERS): Define if needed.
* struc-symbol.h (SYMBOLS_NEED_BACKPOINTERS): Don't set.
(struct symbol): Move bsym to make it clearly the first field.
Remove TARGET_SYMBOL_FIELDS.
(symbolS): Don't typedef.
(struct broken_word): Remove.
(N_TYPE_seg, seg_N_TYPE): Move to symbol.h.
(SEGMENT_TO_SYMBOL_TYPE, N_REGISTER): Likewise.
(symbol_clear_list_pointers): Likewise.
(symbol_insert, symbol_remove): Likewise.
(symbol_previous, symbol_append): Likewise.
(verify_symbol_chain, verify_symbol_chain_2): Likewise.
(struct local_symbol): Define.
(local_symbol_converted_p, local_symbol_mark_converted): Define.
(local_symbol_resolved_p, local_symbol_mark_resolved): Define.
(local_symbol_get_frag, local_symbol_set_frag): Define.
(local_symbol_get_real_symbol): Define.
(local_symbol_set_real_symbol): Define.
Define.
* write.c (write_object_file): Call resolve_local_symbol_values.
* config/obj-ecoff.h (OBJ_SYMFIELD_TYPE): Define.
(TARGET_SYMBOL_FIELDS): Don't define.
* config/obj-elf.h (OBJ_SYMFIELD_TYPE): Add local field. If
ECOFF_DEBUGGING, add ECOFF fields.
(ELF_TARGET_SYMBOL_FIELDS, TARGET_SYMBOL_FIELDS): Don't define.
* config/obj-multi.h (struct elf_obj_sy): Add local field. If
ECOFF_DEBUGGING, add ECOFF fields.
(ELF_TARGET_SYMBOL_FIELDS, TARGET_SYMBOL_FIELDS): Don't define.
(ECOFF_DEBUG_TARGET_SYMBOL_FIELDS): Don't define.
* config/tc-mcore.h: Don't include struc-symbol.h.
(TARGET_SYMBOL_FIELDS): Don't define.
(struct mcore_tc_sy): Define.
(TC_SYMFIELD_TYPE): Define.
* Many files: Use symbolS instead of struct symbol. Use new
accessor functions rather than referring to symbolS fields
directly.
* read.c (s_mri_common): Don't add in value of line_label.
* config/tc-mips.c (md_apply_fix): Correct parenthesization when
checking for SEC_LINK_ONCE.
* config/tc-sh.h (sh_fix_adjustable): Declare.
1999-06-03 02:29:48 +02:00
|
|
|
|
|| (symbol_get_obj (sym)->ecoff_extern_size != 0
|
|
|
|
|
&& (symbol_get_obj (sym)->ecoff_extern_size
|
|
|
|
|
<= g_switch_value))
|
1999-05-03 09:29:11 +02:00
|
|
|
|
#endif
|
|
|
|
|
/* We must defer this decision until after the whole
|
|
|
|
|
file has been read, since there might be a .extern
|
|
|
|
|
after the first use of this symbol. */
|
|
|
|
|
|| (before_relaxing
|
|
|
|
|
#ifndef NO_ECOFF_DEBUGGING
|
Add support for storing local symbols in a small structure to save
memory when assembling large files.
* as.h: Don't include struc-symbol.h.
(symbolS): Add typedef.
* symbols.c: Include struc-symbol.h.
(local_hash): New static variable.
(save_symbol_name): New static function, from symbol_create.
(symbol_create): Call save_symbol_name.
(local_symbol_count): New static variable.
(local_symbol_conversion_count): Likewise.
(LOCAL_SYMBOL_CHECK): Define.
(local_symbol_make): New static function.
(local_symbol_convert): New static function.
(colon): Handle local symbols. Create local symbol for local
label name.
(symbol_table_insert): Handle local symbols.
(symbol_find_or_make): Create local symbol for local label name.
(symbol_find_base): Check for local symbol.
(symbol_append, symbol_insert): Check for local symbols.
(symbol_clear_list_pointers, symbol_remove): Likewise.
(verify_symbol_chain): Likewise.
(copy_symbol_attributes): Likewise.
(resolve_symbol_value): Handle local symbols.
(resolve_local_symbol): New static function.
(resolve_local_symbol_values): New function.
(S_GET_VALUE, S_SET_VALUE): Handle local symbols.
(S_IS_FUNCTION, S_IS_EXTERNAL, S_IS_WEAK, S_IS_COMMON): Likewise.
(S_IS_DEFINED, S_IS_DEBUG, S_IS_LOCAL, S_GET_NAME): Likewise.
(S_GET_SEGMENT, S_SET_SEGMENT, S_SET_EXTERNAL): Likewise.
(S_CLEAR_EXTERNAL, S_SET_WEAK, S_SET_NAME): Likewise.
(symbol_previous, symbol_next): New functions.
(symbol_get_value_expression): Likewise.
(symbol_set_value_expression): Likewise.
(symbol_set_frag, symbol_get_frag): Likewise.
(symbol_mark_used, symbol_clear_used, symbol_used_p): Likewise.
(symbol_mark_used_in_reloc): Likewise.
(symbol_clear_used_in_reloc, symbol_used_in_reloc_p): Likewise.
(symbol_mark_mri_common, symbol_clear_mri_common): Likewise.
(symbol_mri_common_p): Likewise.
(symbol_mark_written, symbol_clear_written): Likewise.
(symbol_written_p): Likewise.
(symbol_mark_resolved, symbol_resolved_p): Likewise.
(symbol_section_p, symbol_equated_p): Likewise.
(symbol_constant_p): Likewise.
(symbol_get_bfdsym, symbol_set_bfdsym): Likewise.
(symbol_get_obj, symbol_set_obj): Likewise.
(symbol_get_tc, symbol_set_tc): Likewise.
(symbol_begin): Initialize local_hash.
(print_symbol_value_1): Handle local symbols.
(symbol_print_statistics): Print local symbol statistics.
* symbols.h: Include "struc-symbol.h" if not BFD_ASSEMBLER.
Declare new symbols.c functions. Move many declarations here from
struc-symbol.h.
(SYMBOLS_NEED_BACKPOINTERS): Define if needed.
* struc-symbol.h (SYMBOLS_NEED_BACKPOINTERS): Don't set.
(struct symbol): Move bsym to make it clearly the first field.
Remove TARGET_SYMBOL_FIELDS.
(symbolS): Don't typedef.
(struct broken_word): Remove.
(N_TYPE_seg, seg_N_TYPE): Move to symbol.h.
(SEGMENT_TO_SYMBOL_TYPE, N_REGISTER): Likewise.
(symbol_clear_list_pointers): Likewise.
(symbol_insert, symbol_remove): Likewise.
(symbol_previous, symbol_append): Likewise.
(verify_symbol_chain, verify_symbol_chain_2): Likewise.
(struct local_symbol): Define.
(local_symbol_converted_p, local_symbol_mark_converted): Define.
(local_symbol_resolved_p, local_symbol_mark_resolved): Define.
(local_symbol_get_frag, local_symbol_set_frag): Define.
(local_symbol_get_real_symbol): Define.
(local_symbol_set_real_symbol): Define.
Define.
* write.c (write_object_file): Call resolve_local_symbol_values.
* config/obj-ecoff.h (OBJ_SYMFIELD_TYPE): Define.
(TARGET_SYMBOL_FIELDS): Don't define.
* config/obj-elf.h (OBJ_SYMFIELD_TYPE): Add local field. If
ECOFF_DEBUGGING, add ECOFF fields.
(ELF_TARGET_SYMBOL_FIELDS, TARGET_SYMBOL_FIELDS): Don't define.
* config/obj-multi.h (struct elf_obj_sy): Add local field. If
ECOFF_DEBUGGING, add ECOFF fields.
(ELF_TARGET_SYMBOL_FIELDS, TARGET_SYMBOL_FIELDS): Don't define.
(ECOFF_DEBUG_TARGET_SYMBOL_FIELDS): Don't define.
* config/tc-mcore.h: Don't include struc-symbol.h.
(TARGET_SYMBOL_FIELDS): Don't define.
(struct mcore_tc_sy): Define.
(TC_SYMFIELD_TYPE): Define.
* Many files: Use symbolS instead of struct symbol. Use new
accessor functions rather than referring to symbolS fields
directly.
* read.c (s_mri_common): Don't add in value of line_label.
* config/tc-mips.c (md_apply_fix): Correct parenthesization when
checking for SEC_LINK_ONCE.
* config/tc-sh.h (sh_fix_adjustable): Declare.
1999-06-03 02:29:48 +02:00
|
|
|
|
&& symbol_get_obj (sym)->ecoff_extern_size == 0
|
1999-05-03 09:29:11 +02:00
|
|
|
|
#endif
|
|
|
|
|
&& S_GET_VALUE (sym) == 0)
|
|
|
|
|
|| (S_GET_VALUE (sym) != 0
|
|
|
|
|
&& S_GET_VALUE (sym) <= g_switch_value)))
|
|
|
|
|
change = 0;
|
|
|
|
|
else
|
|
|
|
|
{
|
|
|
|
|
const char *segname;
|
|
|
|
|
|
|
|
|
|
segname = segment_name (S_GET_SEGMENT (sym));
|
|
|
|
|
assert (strcmp (segname, ".lit8") != 0
|
|
|
|
|
&& strcmp (segname, ".lit4") != 0);
|
|
|
|
|
change = (strcmp (segname, ".sdata") != 0
|
1999-09-28 06:13:25 +02:00
|
|
|
|
&& strcmp (segname, ".sbss") != 0
|
|
|
|
|
&& strncmp (segname, ".sdata.", 7) != 0
|
|
|
|
|
&& strncmp (segname, ".gnu.linkonce.s.", 16) != 0);
|
1999-05-03 09:29:11 +02:00
|
|
|
|
}
|
|
|
|
|
return change;
|
|
|
|
|
}
|
|
|
|
|
else
|
2002-05-28 21:23:09 +02:00
|
|
|
|
/* We are not optimizing for the $gp register. */
|
1999-05-03 09:29:11 +02:00
|
|
|
|
return 1;
|
|
|
|
|
}
|
|
|
|
|
|
2003-02-08 18:05:55 +01:00
|
|
|
|
|
|
|
|
|
/* Return true if the given symbol should be considered local for SVR4 PIC. */
|
|
|
|
|
|
|
|
|
|
static bfd_boolean
|
2003-06-30 14:44:25 +02:00
|
|
|
|
pic_need_relax (symbolS *sym, asection *segtype)
|
2003-02-08 18:05:55 +01:00
|
|
|
|
{
|
|
|
|
|
asection *symsec;
|
|
|
|
|
bfd_boolean linkonce;
|
|
|
|
|
|
|
|
|
|
/* Handle the case of a symbol equated to another symbol. */
|
|
|
|
|
while (symbol_equated_reloc_p (sym))
|
|
|
|
|
{
|
|
|
|
|
symbolS *n;
|
|
|
|
|
|
|
|
|
|
/* It's possible to get a loop here in a badly written
|
|
|
|
|
program. */
|
|
|
|
|
n = symbol_get_value_expression (sym)->X_add_symbol;
|
|
|
|
|
if (n == sym)
|
|
|
|
|
break;
|
|
|
|
|
sym = n;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
symsec = S_GET_SEGMENT (sym);
|
|
|
|
|
|
|
|
|
|
/* duplicate the test for LINK_ONCE sections as in adjust_reloc_syms */
|
|
|
|
|
linkonce = FALSE;
|
|
|
|
|
if (symsec != segtype && ! S_IS_LOCAL (sym))
|
|
|
|
|
{
|
|
|
|
|
if ((bfd_get_section_flags (stdoutput, symsec) & SEC_LINK_ONCE)
|
|
|
|
|
!= 0)
|
|
|
|
|
linkonce = TRUE;
|
|
|
|
|
|
|
|
|
|
/* The GNU toolchain uses an extension for ELF: a section
|
|
|
|
|
beginning with the magic string .gnu.linkonce is a linkonce
|
|
|
|
|
section. */
|
|
|
|
|
if (strncmp (segment_name (symsec), ".gnu.linkonce",
|
|
|
|
|
sizeof ".gnu.linkonce" - 1) == 0)
|
|
|
|
|
linkonce = TRUE;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/* This must duplicate the test in adjust_reloc_syms. */
|
|
|
|
|
return (symsec != &bfd_und_section
|
|
|
|
|
&& symsec != &bfd_abs_section
|
|
|
|
|
&& ! bfd_is_com_section (symsec)
|
|
|
|
|
&& !linkonce
|
|
|
|
|
#ifdef OBJ_ELF
|
|
|
|
|
/* A global or weak symbol is treated as external. */
|
|
|
|
|
&& (OUTPUT_FLAVOR != bfd_target_elf_flavour
|
|
|
|
|
|| (! S_IS_WEAK (sym)
|
|
|
|
|
&& (! S_IS_EXTERNAL (sym)
|
|
|
|
|
|| mips_pic == EMBEDDED_PIC)))
|
|
|
|
|
#endif
|
|
|
|
|
);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
1999-05-03 09:29:11 +02:00
|
|
|
|
/* Given a mips16 variant frag FRAGP, return non-zero if it needs an
|
|
|
|
|
extended opcode. SEC is the section the frag is in. */
|
|
|
|
|
|
|
|
|
|
static int
|
2003-06-30 14:44:25 +02:00
|
|
|
|
mips16_extended_frag (fragS *fragp, asection *sec, long stretch)
|
1999-05-03 09:29:11 +02:00
|
|
|
|
{
|
|
|
|
|
int type;
|
|
|
|
|
register const struct mips16_immed_operand *op;
|
|
|
|
|
offsetT val;
|
|
|
|
|
int mintiny, maxtiny;
|
|
|
|
|
segT symsec;
|
2001-06-08 08:07:13 +02:00
|
|
|
|
fragS *sym_frag;
|
1999-05-03 09:29:11 +02:00
|
|
|
|
|
|
|
|
|
if (RELAX_MIPS16_USER_SMALL (fragp->fr_subtype))
|
|
|
|
|
return 0;
|
|
|
|
|
if (RELAX_MIPS16_USER_EXT (fragp->fr_subtype))
|
|
|
|
|
return 1;
|
|
|
|
|
|
|
|
|
|
type = RELAX_MIPS16_TYPE (fragp->fr_subtype);
|
|
|
|
|
op = mips16_immed_operands;
|
|
|
|
|
while (op->type != type)
|
|
|
|
|
{
|
|
|
|
|
++op;
|
|
|
|
|
assert (op < mips16_immed_operands + MIPS16_NUM_IMMED);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
if (op->unsp)
|
|
|
|
|
{
|
|
|
|
|
if (type == '<' || type == '>' || type == '[' || type == ']')
|
|
|
|
|
{
|
|
|
|
|
mintiny = 1;
|
|
|
|
|
maxtiny = 1 << op->nbits;
|
|
|
|
|
}
|
|
|
|
|
else
|
|
|
|
|
{
|
|
|
|
|
mintiny = 0;
|
|
|
|
|
maxtiny = (1 << op->nbits) - 1;
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
else
|
|
|
|
|
{
|
|
|
|
|
mintiny = - (1 << (op->nbits - 1));
|
|
|
|
|
maxtiny = (1 << (op->nbits - 1)) - 1;
|
|
|
|
|
}
|
|
|
|
|
|
2001-06-08 08:07:13 +02:00
|
|
|
|
sym_frag = symbol_get_frag (fragp->fr_symbol);
|
* symbols.c (S_GET_VALUE): Don't treat O_constant and local
symbols specially. Always resolve, adding fr_address to value.
* write.c (write_object_file): Don't add fr_address to sym values.
(relax_frag): Likewise.
(relax_segment): Likewise.
* config/obj-ieee.c (do_symbols): Likewise.
* config/tc-cris.c (md_convert_frag): Likewise.
* config/tc-fr30.c (md_convert_frag): Likewise.
* config/tc-i386.c (md_convert_frag): Likewise.
* config/tc-m32r.c (md_convert_frag): Likewise.
* config/tc-m68hc11.c (md_convert_frag): Likewise.
* config/tc-mcore.c (md_convert_frag): Likewise.
* config/tc-mips.c (mips16_extended_frag): Likewise.
* config/tc-ns32k.c (md_convert_frag): Likewise.
* config/tc-m68k.c (md_convert_frag_1): Likewise.
(BRANCHBWL, BRABSJUNC, BRABSJCOND, BRANCHBW, FBRANCH, DBCCLBR,
DBCCABSJ, PCREL1632, PCINDEX, ABSTOPCREL): Decrement.
(md_relax_table): Remove first four entries. Format.
(md_estimate_size_before_relax): Remove old_fix. Don't bother
setting fr_var. Simplify byte branch checks.
2001-07-23 15:03:40 +02:00
|
|
|
|
val = S_GET_VALUE (fragp->fr_symbol);
|
2001-06-08 08:07:13 +02:00
|
|
|
|
symsec = S_GET_SEGMENT (fragp->fr_symbol);
|
1999-05-03 09:29:11 +02:00
|
|
|
|
|
|
|
|
|
if (op->pcrel)
|
|
|
|
|
{
|
|
|
|
|
addressT addr;
|
|
|
|
|
|
|
|
|
|
/* We won't have the section when we are called from
|
|
|
|
|
mips_relax_frag. However, we will always have been called
|
|
|
|
|
from md_estimate_size_before_relax first. If this is a
|
|
|
|
|
branch to a different section, we mark it as such. If SEC is
|
|
|
|
|
NULL, and the frag is not marked, then it must be a branch to
|
|
|
|
|
the same section. */
|
|
|
|
|
if (sec == NULL)
|
|
|
|
|
{
|
|
|
|
|
if (RELAX_MIPS16_LONG_BRANCH (fragp->fr_subtype))
|
|
|
|
|
return 1;
|
|
|
|
|
}
|
|
|
|
|
else
|
|
|
|
|
{
|
2001-06-08 08:07:13 +02:00
|
|
|
|
/* Must have been called from md_estimate_size_before_relax. */
|
1999-05-03 09:29:11 +02:00
|
|
|
|
if (symsec != sec)
|
|
|
|
|
{
|
|
|
|
|
fragp->fr_subtype =
|
|
|
|
|
RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype);
|
|
|
|
|
|
|
|
|
|
/* FIXME: We should support this, and let the linker
|
|
|
|
|
catch branches and loads that are out of range. */
|
|
|
|
|
as_bad_where (fragp->fr_file, fragp->fr_line,
|
|
|
|
|
_("unsupported PC relative reference to different section"));
|
|
|
|
|
|
|
|
|
|
return 1;
|
|
|
|
|
}
|
2001-06-08 08:07:13 +02:00
|
|
|
|
if (fragp != sym_frag && sym_frag->fr_address == 0)
|
|
|
|
|
/* Assume non-extended on the first relaxation pass.
|
|
|
|
|
The address we have calculated will be bogus if this is
|
|
|
|
|
a forward branch to another frag, as the forward frag
|
|
|
|
|
will have fr_address == 0. */
|
|
|
|
|
return 0;
|
1999-05-03 09:29:11 +02:00
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/* In this case, we know for sure that the symbol fragment is in
|
2001-06-08 08:07:13 +02:00
|
|
|
|
the same section. If the relax_marker of the symbol fragment
|
|
|
|
|
differs from the relax_marker of this fragment, we have not
|
|
|
|
|
yet adjusted the symbol fragment fr_address. We want to add
|
1999-05-03 09:29:11 +02:00
|
|
|
|
in STRETCH in order to get a better estimate of the address.
|
|
|
|
|
This particularly matters because of the shift bits. */
|
|
|
|
|
if (stretch != 0
|
2001-06-08 08:07:13 +02:00
|
|
|
|
&& sym_frag->relax_marker != fragp->relax_marker)
|
1999-05-03 09:29:11 +02:00
|
|
|
|
{
|
|
|
|
|
fragS *f;
|
|
|
|
|
|
|
|
|
|
/* Adjust stretch for any alignment frag. Note that if have
|
|
|
|
|
been expanding the earlier code, the symbol may be
|
|
|
|
|
defined in what appears to be an earlier frag. FIXME:
|
|
|
|
|
This doesn't handle the fr_subtype field, which specifies
|
|
|
|
|
a maximum number of bytes to skip when doing an
|
|
|
|
|
alignment. */
|
2001-06-08 08:07:13 +02:00
|
|
|
|
for (f = fragp; f != NULL && f != sym_frag; f = f->fr_next)
|
1999-05-03 09:29:11 +02:00
|
|
|
|
{
|
|
|
|
|
if (f->fr_type == rs_align || f->fr_type == rs_align_code)
|
|
|
|
|
{
|
|
|
|
|
if (stretch < 0)
|
|
|
|
|
stretch = - ((- stretch)
|
|
|
|
|
& ~ ((1 << (int) f->fr_offset) - 1));
|
|
|
|
|
else
|
|
|
|
|
stretch &= ~ ((1 << (int) f->fr_offset) - 1);
|
|
|
|
|
if (stretch == 0)
|
|
|
|
|
break;
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
if (f != NULL)
|
|
|
|
|
val += stretch;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
addr = fragp->fr_address + fragp->fr_fix;
|
|
|
|
|
|
|
|
|
|
/* The base address rules are complicated. The base address of
|
|
|
|
|
a branch is the following instruction. The base address of a
|
|
|
|
|
PC relative load or add is the instruction itself, but if it
|
|
|
|
|
is in a delay slot (in which case it can not be extended) use
|
|
|
|
|
the address of the instruction whose delay slot it is in. */
|
|
|
|
|
if (type == 'p' || type == 'q')
|
|
|
|
|
{
|
|
|
|
|
addr += 2;
|
|
|
|
|
|
|
|
|
|
/* If we are currently assuming that this frag should be
|
|
|
|
|
extended, then, the current address is two bytes
|
2000-09-07 14:45:56 +02:00
|
|
|
|
higher. */
|
1999-05-03 09:29:11 +02:00
|
|
|
|
if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype))
|
|
|
|
|
addr += 2;
|
|
|
|
|
|
|
|
|
|
/* Ignore the low bit in the target, since it will be set
|
|
|
|
|
for a text label. */
|
|
|
|
|
if ((val & 1) != 0)
|
|
|
|
|
--val;
|
|
|
|
|
}
|
|
|
|
|
else if (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype))
|
|
|
|
|
addr -= 4;
|
|
|
|
|
else if (RELAX_MIPS16_DSLOT (fragp->fr_subtype))
|
|
|
|
|
addr -= 2;
|
|
|
|
|
|
|
|
|
|
val -= addr & ~ ((1 << op->shift) - 1);
|
|
|
|
|
|
|
|
|
|
/* Branch offsets have an implicit 0 in the lowest bit. */
|
|
|
|
|
if (type == 'p' || type == 'q')
|
|
|
|
|
val /= 2;
|
|
|
|
|
|
|
|
|
|
/* If any of the shifted bits are set, we must use an extended
|
|
|
|
|
opcode. If the address depends on the size of this
|
|
|
|
|
instruction, this can lead to a loop, so we arrange to always
|
|
|
|
|
use an extended opcode. We only check this when we are in
|
|
|
|
|
the main relaxation loop, when SEC is NULL. */
|
|
|
|
|
if ((val & ((1 << op->shift) - 1)) != 0 && sec == NULL)
|
|
|
|
|
{
|
|
|
|
|
fragp->fr_subtype =
|
|
|
|
|
RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype);
|
|
|
|
|
return 1;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/* If we are about to mark a frag as extended because the value
|
|
|
|
|
is precisely maxtiny + 1, then there is a chance of an
|
|
|
|
|
infinite loop as in the following code:
|
|
|
|
|
la $4,foo
|
|
|
|
|
.skip 1020
|
|
|
|
|
.align 2
|
|
|
|
|
foo:
|
|
|
|
|
In this case when the la is extended, foo is 0x3fc bytes
|
|
|
|
|
away, so the la can be shrunk, but then foo is 0x400 away, so
|
|
|
|
|
the la must be extended. To avoid this loop, we mark the
|
|
|
|
|
frag as extended if it was small, and is about to become
|
|
|
|
|
extended with a value of maxtiny + 1. */
|
|
|
|
|
if (val == ((maxtiny + 1) << op->shift)
|
|
|
|
|
&& ! RELAX_MIPS16_EXTENDED (fragp->fr_subtype)
|
|
|
|
|
&& sec == NULL)
|
|
|
|
|
{
|
|
|
|
|
fragp->fr_subtype =
|
|
|
|
|
RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype);
|
|
|
|
|
return 1;
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
else if (symsec != absolute_section && sec != NULL)
|
|
|
|
|
as_bad_where (fragp->fr_file, fragp->fr_line, _("unsupported relocation"));
|
|
|
|
|
|
|
|
|
|
if ((val & ((1 << op->shift) - 1)) != 0
|
|
|
|
|
|| val < (mintiny << op->shift)
|
|
|
|
|
|| val > (maxtiny << op->shift))
|
|
|
|
|
return 1;
|
|
|
|
|
else
|
|
|
|
|
return 0;
|
|
|
|
|
}
|
|
|
|
|
|
2002-10-12 07:23:33 +02:00
|
|
|
|
/* Compute the length of a branch sequence, and adjust the
|
|
|
|
|
RELAX_BRANCH_TOOFAR bit accordingly. If FRAGP is NULL, the
|
|
|
|
|
worst-case length is computed, with UPDATE being used to indicate
|
|
|
|
|
whether an unconditional (-1), branch-likely (+1) or regular (0)
|
|
|
|
|
branch is to be computed. */
|
|
|
|
|
static int
|
2003-06-30 14:44:25 +02:00
|
|
|
|
relaxed_branch_length (fragS *fragp, asection *sec, int update)
|
2002-10-12 07:23:33 +02:00
|
|
|
|
{
|
2002-11-30 09:39:46 +01:00
|
|
|
|
bfd_boolean toofar;
|
2002-10-12 07:23:33 +02:00
|
|
|
|
int length;
|
|
|
|
|
|
|
|
|
|
if (fragp
|
|
|
|
|
&& S_IS_DEFINED (fragp->fr_symbol)
|
|
|
|
|
&& sec == S_GET_SEGMENT (fragp->fr_symbol))
|
|
|
|
|
{
|
|
|
|
|
addressT addr;
|
|
|
|
|
offsetT val;
|
|
|
|
|
|
|
|
|
|
val = S_GET_VALUE (fragp->fr_symbol) + fragp->fr_offset;
|
|
|
|
|
|
|
|
|
|
addr = fragp->fr_address + fragp->fr_fix + 4;
|
|
|
|
|
|
|
|
|
|
val -= addr;
|
|
|
|
|
|
|
|
|
|
toofar = val < - (0x8000 << 2) || val >= (0x8000 << 2);
|
|
|
|
|
}
|
|
|
|
|
else if (fragp)
|
|
|
|
|
/* If the symbol is not defined or it's in a different segment,
|
|
|
|
|
assume the user knows what's going on and emit a short
|
|
|
|
|
branch. */
|
2002-11-30 09:39:46 +01:00
|
|
|
|
toofar = FALSE;
|
2002-10-12 07:23:33 +02:00
|
|
|
|
else
|
2002-11-30 09:39:46 +01:00
|
|
|
|
toofar = TRUE;
|
2002-10-12 07:23:33 +02:00
|
|
|
|
|
|
|
|
|
if (fragp && update && toofar != RELAX_BRANCH_TOOFAR (fragp->fr_subtype))
|
|
|
|
|
fragp->fr_subtype
|
2002-12-12 05:40:07 +01:00
|
|
|
|
= RELAX_BRANCH_ENCODE (RELAX_BRANCH_UNCOND (fragp->fr_subtype),
|
2002-10-12 07:23:33 +02:00
|
|
|
|
RELAX_BRANCH_LIKELY (fragp->fr_subtype),
|
|
|
|
|
RELAX_BRANCH_LINK (fragp->fr_subtype),
|
|
|
|
|
toofar);
|
|
|
|
|
|
|
|
|
|
length = 4;
|
|
|
|
|
if (toofar)
|
|
|
|
|
{
|
|
|
|
|
if (fragp ? RELAX_BRANCH_LIKELY (fragp->fr_subtype) : (update > 0))
|
|
|
|
|
length += 8;
|
|
|
|
|
|
|
|
|
|
if (mips_pic != NO_PIC)
|
|
|
|
|
{
|
|
|
|
|
/* Additional space for PIC loading of target address. */
|
|
|
|
|
length += 8;
|
|
|
|
|
if (mips_opts.isa == ISA_MIPS1)
|
|
|
|
|
/* Additional space for $at-stabilizing nop. */
|
|
|
|
|
length += 4;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/* If branch is conditional. */
|
|
|
|
|
if (fragp ? !RELAX_BRANCH_UNCOND (fragp->fr_subtype) : (update >= 0))
|
|
|
|
|
length += 8;
|
|
|
|
|
}
|
2002-11-30 09:39:46 +01:00
|
|
|
|
|
2002-10-12 07:23:33 +02:00
|
|
|
|
return length;
|
|
|
|
|
}
|
|
|
|
|
|
1999-05-03 09:29:11 +02:00
|
|
|
|
/* Estimate the size of a frag before relaxing. Unless this is the
|
|
|
|
|
mips16, we are not really relaxing here, and the final size is
|
|
|
|
|
encoded in the subtype information. For the mips16, we have to
|
|
|
|
|
decide whether we are using an extended opcode or not. */
|
|
|
|
|
|
|
|
|
|
int
|
2003-06-30 14:44:25 +02:00
|
|
|
|
md_estimate_size_before_relax (fragS *fragp, asection *segtype)
|
1999-05-03 09:29:11 +02:00
|
|
|
|
{
|
2003-02-08 18:05:55 +01:00
|
|
|
|
int change;
|
1999-05-03 09:29:11 +02:00
|
|
|
|
|
2002-10-12 07:23:33 +02:00
|
|
|
|
if (RELAX_BRANCH_P (fragp->fr_subtype))
|
|
|
|
|
{
|
|
|
|
|
|
2002-11-30 09:39:46 +01:00
|
|
|
|
fragp->fr_var = relaxed_branch_length (fragp, segtype, FALSE);
|
|
|
|
|
|
2002-10-12 07:23:33 +02:00
|
|
|
|
return fragp->fr_var;
|
|
|
|
|
}
|
|
|
|
|
|
1999-05-03 09:29:11 +02:00
|
|
|
|
if (RELAX_MIPS16_P (fragp->fr_subtype))
|
2002-03-18 19:56:18 +01:00
|
|
|
|
/* We don't want to modify the EXTENDED bit here; it might get us
|
|
|
|
|
into infinite loops. We change it only in mips_relax_frag(). */
|
|
|
|
|
return (RELAX_MIPS16_EXTENDED (fragp->fr_subtype) ? 4 : 2);
|
1999-05-03 09:29:11 +02:00
|
|
|
|
|
|
|
|
|
if (mips_pic == NO_PIC)
|
2003-02-08 18:05:55 +01:00
|
|
|
|
change = nopic_need_relax (fragp->fr_symbol, 0);
|
1999-05-03 09:29:11 +02:00
|
|
|
|
else if (mips_pic == SVR4_PIC)
|
2003-02-08 18:05:55 +01:00
|
|
|
|
change = pic_need_relax (fragp->fr_symbol, segtype);
|
1999-05-03 09:29:11 +02:00
|
|
|
|
else
|
|
|
|
|
abort ();
|
|
|
|
|
|
|
|
|
|
if (change)
|
|
|
|
|
{
|
|
|
|
|
/* Record the offset to the first reloc in the fr_opcode field.
|
|
|
|
|
This lets md_convert_frag and tc_gen_reloc know that the code
|
|
|
|
|
must be expanded. */
|
|
|
|
|
fragp->fr_opcode = (fragp->fr_literal
|
|
|
|
|
+ fragp->fr_fix
|
|
|
|
|
- RELAX_OLD (fragp->fr_subtype)
|
|
|
|
|
+ RELAX_RELOC1 (fragp->fr_subtype));
|
|
|
|
|
/* FIXME: This really needs as_warn_where. */
|
|
|
|
|
if (RELAX_WARN (fragp->fr_subtype))
|
2001-08-07 15:15:26 +02:00
|
|
|
|
as_warn (_("AT used after \".set noat\" or macro used after "
|
|
|
|
|
"\".set nomacro\""));
|
|
|
|
|
|
|
|
|
|
return RELAX_NEW (fragp->fr_subtype) - RELAX_OLD (fragp->fr_subtype);
|
1999-05-03 09:29:11 +02:00
|
|
|
|
}
|
|
|
|
|
|
2001-08-07 15:15:26 +02:00
|
|
|
|
return 0;
|
1999-05-03 09:29:11 +02:00
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/* This is called to see whether a reloc against a defined symbol
|
|
|
|
|
should be converted into a reloc against a section. Don't adjust
|
|
|
|
|
MIPS16 jump relocations, so we don't have to worry about the format
|
|
|
|
|
of the offset in the .o file. Don't adjust relocations against
|
|
|
|
|
mips16 symbols, so that the linker can find them if it needs to set
|
|
|
|
|
up a stub. */
|
|
|
|
|
|
|
|
|
|
int
|
2003-06-30 14:44:25 +02:00
|
|
|
|
mips_fix_adjustable (fixS *fixp)
|
1999-05-03 09:29:11 +02:00
|
|
|
|
{
|
|
|
|
|
if (fixp->fx_r_type == BFD_RELOC_MIPS16_JMP)
|
|
|
|
|
return 0;
|
2002-09-05 02:01:18 +02:00
|
|
|
|
|
1999-05-03 09:29:11 +02:00
|
|
|
|
if (fixp->fx_r_type == BFD_RELOC_VTABLE_INHERIT
|
|
|
|
|
|| fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
|
|
|
|
|
return 0;
|
2002-09-05 02:01:18 +02:00
|
|
|
|
|
1999-05-03 09:29:11 +02:00
|
|
|
|
if (fixp->fx_addsy == NULL)
|
|
|
|
|
return 1;
|
2002-09-05 02:01:18 +02:00
|
|
|
|
|
1999-05-03 09:29:11 +02:00
|
|
|
|
#ifdef OBJ_ELF
|
|
|
|
|
if (OUTPUT_FLAVOR == bfd_target_elf_flavour
|
|
|
|
|
&& S_GET_OTHER (fixp->fx_addsy) == STO_MIPS16
|
|
|
|
|
&& fixp->fx_subsy == NULL)
|
|
|
|
|
return 0;
|
|
|
|
|
#endif
|
2002-09-05 02:01:18 +02:00
|
|
|
|
|
1999-05-03 09:29:11 +02:00
|
|
|
|
return 1;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/* Translate internal representation of relocation info to BFD target
|
|
|
|
|
format. */
|
|
|
|
|
|
|
|
|
|
arelent **
|
2003-06-30 14:44:25 +02:00
|
|
|
|
tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixp)
|
1999-05-03 09:29:11 +02:00
|
|
|
|
{
|
|
|
|
|
static arelent *retval[4];
|
|
|
|
|
arelent *reloc;
|
|
|
|
|
bfd_reloc_code_real_type code;
|
|
|
|
|
|
2003-06-11 22:53:32 +02:00
|
|
|
|
memset (retval, 0, sizeof(retval));
|
|
|
|
|
reloc = retval[0] = (arelent *) xcalloc (1, sizeof (arelent));
|
Add support for storing local symbols in a small structure to save
memory when assembling large files.
* as.h: Don't include struc-symbol.h.
(symbolS): Add typedef.
* symbols.c: Include struc-symbol.h.
(local_hash): New static variable.
(save_symbol_name): New static function, from symbol_create.
(symbol_create): Call save_symbol_name.
(local_symbol_count): New static variable.
(local_symbol_conversion_count): Likewise.
(LOCAL_SYMBOL_CHECK): Define.
(local_symbol_make): New static function.
(local_symbol_convert): New static function.
(colon): Handle local symbols. Create local symbol for local
label name.
(symbol_table_insert): Handle local symbols.
(symbol_find_or_make): Create local symbol for local label name.
(symbol_find_base): Check for local symbol.
(symbol_append, symbol_insert): Check for local symbols.
(symbol_clear_list_pointers, symbol_remove): Likewise.
(verify_symbol_chain): Likewise.
(copy_symbol_attributes): Likewise.
(resolve_symbol_value): Handle local symbols.
(resolve_local_symbol): New static function.
(resolve_local_symbol_values): New function.
(S_GET_VALUE, S_SET_VALUE): Handle local symbols.
(S_IS_FUNCTION, S_IS_EXTERNAL, S_IS_WEAK, S_IS_COMMON): Likewise.
(S_IS_DEFINED, S_IS_DEBUG, S_IS_LOCAL, S_GET_NAME): Likewise.
(S_GET_SEGMENT, S_SET_SEGMENT, S_SET_EXTERNAL): Likewise.
(S_CLEAR_EXTERNAL, S_SET_WEAK, S_SET_NAME): Likewise.
(symbol_previous, symbol_next): New functions.
(symbol_get_value_expression): Likewise.
(symbol_set_value_expression): Likewise.
(symbol_set_frag, symbol_get_frag): Likewise.
(symbol_mark_used, symbol_clear_used, symbol_used_p): Likewise.
(symbol_mark_used_in_reloc): Likewise.
(symbol_clear_used_in_reloc, symbol_used_in_reloc_p): Likewise.
(symbol_mark_mri_common, symbol_clear_mri_common): Likewise.
(symbol_mri_common_p): Likewise.
(symbol_mark_written, symbol_clear_written): Likewise.
(symbol_written_p): Likewise.
(symbol_mark_resolved, symbol_resolved_p): Likewise.
(symbol_section_p, symbol_equated_p): Likewise.
(symbol_constant_p): Likewise.
(symbol_get_bfdsym, symbol_set_bfdsym): Likewise.
(symbol_get_obj, symbol_set_obj): Likewise.
(symbol_get_tc, symbol_set_tc): Likewise.
(symbol_begin): Initialize local_hash.
(print_symbol_value_1): Handle local symbols.
(symbol_print_statistics): Print local symbol statistics.
* symbols.h: Include "struc-symbol.h" if not BFD_ASSEMBLER.
Declare new symbols.c functions. Move many declarations here from
struc-symbol.h.
(SYMBOLS_NEED_BACKPOINTERS): Define if needed.
* struc-symbol.h (SYMBOLS_NEED_BACKPOINTERS): Don't set.
(struct symbol): Move bsym to make it clearly the first field.
Remove TARGET_SYMBOL_FIELDS.
(symbolS): Don't typedef.
(struct broken_word): Remove.
(N_TYPE_seg, seg_N_TYPE): Move to symbol.h.
(SEGMENT_TO_SYMBOL_TYPE, N_REGISTER): Likewise.
(symbol_clear_list_pointers): Likewise.
(symbol_insert, symbol_remove): Likewise.
(symbol_previous, symbol_append): Likewise.
(verify_symbol_chain, verify_symbol_chain_2): Likewise.
(struct local_symbol): Define.
(local_symbol_converted_p, local_symbol_mark_converted): Define.
(local_symbol_resolved_p, local_symbol_mark_resolved): Define.
(local_symbol_get_frag, local_symbol_set_frag): Define.
(local_symbol_get_real_symbol): Define.
(local_symbol_set_real_symbol): Define.
Define.
* write.c (write_object_file): Call resolve_local_symbol_values.
* config/obj-ecoff.h (OBJ_SYMFIELD_TYPE): Define.
(TARGET_SYMBOL_FIELDS): Don't define.
* config/obj-elf.h (OBJ_SYMFIELD_TYPE): Add local field. If
ECOFF_DEBUGGING, add ECOFF fields.
(ELF_TARGET_SYMBOL_FIELDS, TARGET_SYMBOL_FIELDS): Don't define.
* config/obj-multi.h (struct elf_obj_sy): Add local field. If
ECOFF_DEBUGGING, add ECOFF fields.
(ELF_TARGET_SYMBOL_FIELDS, TARGET_SYMBOL_FIELDS): Don't define.
(ECOFF_DEBUG_TARGET_SYMBOL_FIELDS): Don't define.
* config/tc-mcore.h: Don't include struc-symbol.h.
(TARGET_SYMBOL_FIELDS): Don't define.
(struct mcore_tc_sy): Define.
(TC_SYMFIELD_TYPE): Define.
* Many files: Use symbolS instead of struct symbol. Use new
accessor functions rather than referring to symbolS fields
directly.
* read.c (s_mri_common): Don't add in value of line_label.
* config/tc-mips.c (md_apply_fix): Correct parenthesization when
checking for SEC_LINK_ONCE.
* config/tc-sh.h (sh_fix_adjustable): Declare.
1999-06-03 02:29:48 +02:00
|
|
|
|
reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
|
|
|
|
|
*reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
|
1999-05-03 09:29:11 +02:00
|
|
|
|
reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
|
|
|
|
|
|
|
|
|
|
if (mips_pic == EMBEDDED_PIC
|
|
|
|
|
&& SWITCH_TABLE (fixp))
|
|
|
|
|
{
|
|
|
|
|
/* For a switch table entry we use a special reloc. The addend
|
|
|
|
|
is actually the difference between the reloc address and the
|
|
|
|
|
subtrahend. */
|
|
|
|
|
reloc->addend = reloc->address - S_GET_VALUE (fixp->fx_subsy);
|
|
|
|
|
if (OUTPUT_FLAVOR != bfd_target_ecoff_flavour)
|
|
|
|
|
as_fatal (_("Double check fx_r_type in tc-mips.c:tc_gen_reloc"));
|
|
|
|
|
fixp->fx_r_type = BFD_RELOC_GPREL32;
|
|
|
|
|
}
|
bfd/
* elf32-mips.c (elf_mips_howto_table_rel): Replace all uses of
mips_elf_generic_reloc with _bfd_mips_elf_generic_reloc. Use
_bfd_mips_elf_hi16_reloc for R_MIPS_HI16 and R_MIPS_GNU_REL_HI16,
_bfd_mips_elf_lo16_reloc for R_MIPS_LO16 and R_MIPS_GNU_REL_LO16,
and _bfd_mips_elf_got16_reloc for R_MIPS_GOT16. Change rightshift
to 16 for R_MIPS_HI16 and R_MIPS_GNU_REL_HI16.
(mips_elf_generic_reloc, struct mips_hi16, mips_elf_hi16_reloc)
(mips_elf_lo16_reloc, mips_elf_got16_reloc): Delete.
(_bfd_mips_elf32_gprel16_reloc): Remove special case.
(mips_elf_gprel32_reloc, mips32_64bit_reloc): Likewise.
* elf64-mips.c (mips_elf64_howto_table_rel): Replace all uses of
mips_elf_generic_reloc with _bfd_mips_elf_generic_reloc. Use
_bfd_mips_elf_hi16_reloc for R_MIPS_HI16, _bfd_mips_elf_lo16_reloc
for R_MIPS_LO16 and _bfd_mips_elf_got16_reloc for R_MIPS_GOT16.
Change R_MIPS_HI16's rightshift to 16.
(mips_elf64_howto_table_rela): Replace all uses of
mips_elf_generic_reloc with _bfd_mips_elf_generic_reloc.
Use _bfd_mips_elf_generic_reloc for R_MIPS_GOT16 as well.
(mips_elf64_hi16_reloc, mips_elf64_got16_reloc): Delete.
(mips_elf64_shift6_reloc): Remove special case. Use
_bfd_mips_elf_generic_reloc instead of returning bfd_reloc_continue.
* elfn32-mips.c (prev_reloc_section): Delete.
(prev_reloc_address, prev_reloc_addend): Delete.
(elf_mips_howto_table_rel, elf_mips_howto_table_rela): As for
elf64-mips.c
(GET_RELOC_ADDEND, SET_RELOC_ADDEND): Delete.
(mips_elf_generic_reloc, struct mips_hi16, mips_elf_hi16_reloc)
(mips_elf_lo16_reloc, mips_elf_got16_reloc): Delete.
(mips_elf_gprel16_reloc): Delete use of GET_RELOC_ADDEND.
(mips_elf_literal_reloc, mips_elf_gprel32_reloc): Likewise.
(mips16_jump_reloc, mips16_gprel_reloc): Likewise.
(mips_elf_shift6_reloc): Likewise. Delete use of SET_RELOC_ADDEND.
* elfxx-mips.c (_bfd_mips_elf_gprel16_with_gp): Use
_bfd_relocate_contents to install an in-place addend.
(mips_hi16): New structure.
(mips_hi16_list): Moved from elf32-mips.c.
(_bfd_mips_elf_hi16_reloc, _bfd_mips_elf_got16_reloc): New functions.
(_bfd_mips_elf_lo16_reloc, _bfd_mips_elf_generic_reloc): New functions.
(mips_elf_calculate_relocation): Assume addend is unshifted.
(_bfd_mips_elf_relocate_section): Don't apply the howto rightshift
on top of the usual high-part shift. Don't shift the addend right
before calling mips_elf_calculate_relocation.
* elfxx-mips.h (_bfd_mips_elf_hi16_reloc): Declare.
(_bfd_mips_elf_got16_reloc, _bfd_mips_elf_lo16_reloc): Declare.
(_bfd_mips_elf_generic_reloc): Declare.
gas/
* config/tc-mips.c (mips_need_elf_addend_fixup): Delete.
(md_apply_fix3): Remove bfd_install_relocation workarounds.
(tc_gen_reloc): Likewise. Factor handling of pc-relative relocations
and treat fx_addnumber as relative to the relocation address.
gas/testsuite/
* gas/mips/mips16-jalx.d: Use -mabi=o64.
* gas/mips/mips16.d: Likewise.
* gas/mips/elf-rel17.[sd]: New test.
* gas/mips/mips.exp: Run it.
2003-12-18 11:23:10 +01:00
|
|
|
|
else if (fixp->fx_pcrel)
|
1999-05-03 09:29:11 +02:00
|
|
|
|
{
|
bfd/
* elf32-mips.c (elf_mips_howto_table_rel): Replace all uses of
mips_elf_generic_reloc with _bfd_mips_elf_generic_reloc. Use
_bfd_mips_elf_hi16_reloc for R_MIPS_HI16 and R_MIPS_GNU_REL_HI16,
_bfd_mips_elf_lo16_reloc for R_MIPS_LO16 and R_MIPS_GNU_REL_LO16,
and _bfd_mips_elf_got16_reloc for R_MIPS_GOT16. Change rightshift
to 16 for R_MIPS_HI16 and R_MIPS_GNU_REL_HI16.
(mips_elf_generic_reloc, struct mips_hi16, mips_elf_hi16_reloc)
(mips_elf_lo16_reloc, mips_elf_got16_reloc): Delete.
(_bfd_mips_elf32_gprel16_reloc): Remove special case.
(mips_elf_gprel32_reloc, mips32_64bit_reloc): Likewise.
* elf64-mips.c (mips_elf64_howto_table_rel): Replace all uses of
mips_elf_generic_reloc with _bfd_mips_elf_generic_reloc. Use
_bfd_mips_elf_hi16_reloc for R_MIPS_HI16, _bfd_mips_elf_lo16_reloc
for R_MIPS_LO16 and _bfd_mips_elf_got16_reloc for R_MIPS_GOT16.
Change R_MIPS_HI16's rightshift to 16.
(mips_elf64_howto_table_rela): Replace all uses of
mips_elf_generic_reloc with _bfd_mips_elf_generic_reloc.
Use _bfd_mips_elf_generic_reloc for R_MIPS_GOT16 as well.
(mips_elf64_hi16_reloc, mips_elf64_got16_reloc): Delete.
(mips_elf64_shift6_reloc): Remove special case. Use
_bfd_mips_elf_generic_reloc instead of returning bfd_reloc_continue.
* elfn32-mips.c (prev_reloc_section): Delete.
(prev_reloc_address, prev_reloc_addend): Delete.
(elf_mips_howto_table_rel, elf_mips_howto_table_rela): As for
elf64-mips.c
(GET_RELOC_ADDEND, SET_RELOC_ADDEND): Delete.
(mips_elf_generic_reloc, struct mips_hi16, mips_elf_hi16_reloc)
(mips_elf_lo16_reloc, mips_elf_got16_reloc): Delete.
(mips_elf_gprel16_reloc): Delete use of GET_RELOC_ADDEND.
(mips_elf_literal_reloc, mips_elf_gprel32_reloc): Likewise.
(mips16_jump_reloc, mips16_gprel_reloc): Likewise.
(mips_elf_shift6_reloc): Likewise. Delete use of SET_RELOC_ADDEND.
* elfxx-mips.c (_bfd_mips_elf_gprel16_with_gp): Use
_bfd_relocate_contents to install an in-place addend.
(mips_hi16): New structure.
(mips_hi16_list): Moved from elf32-mips.c.
(_bfd_mips_elf_hi16_reloc, _bfd_mips_elf_got16_reloc): New functions.
(_bfd_mips_elf_lo16_reloc, _bfd_mips_elf_generic_reloc): New functions.
(mips_elf_calculate_relocation): Assume addend is unshifted.
(_bfd_mips_elf_relocate_section): Don't apply the howto rightshift
on top of the usual high-part shift. Don't shift the addend right
before calling mips_elf_calculate_relocation.
* elfxx-mips.h (_bfd_mips_elf_hi16_reloc): Declare.
(_bfd_mips_elf_got16_reloc, _bfd_mips_elf_lo16_reloc): Declare.
(_bfd_mips_elf_generic_reloc): Declare.
gas/
* config/tc-mips.c (mips_need_elf_addend_fixup): Delete.
(md_apply_fix3): Remove bfd_install_relocation workarounds.
(tc_gen_reloc): Likewise. Factor handling of pc-relative relocations
and treat fx_addnumber as relative to the relocation address.
gas/testsuite/
* gas/mips/mips16-jalx.d: Use -mabi=o64.
* gas/mips/mips16.d: Likewise.
* gas/mips/elf-rel17.[sd]: New test.
* gas/mips/mips.exp: Run it.
2003-12-18 11:23:10 +01:00
|
|
|
|
bfd_vma pcrel_address;
|
|
|
|
|
|
|
|
|
|
/* Set PCREL_ADDRESS to this relocation's "PC". The PC for high
|
|
|
|
|
high-part relocs is the address of the low-part reloc. */
|
|
|
|
|
if (fixp->fx_r_type == BFD_RELOC_PCREL_HI16_S)
|
|
|
|
|
{
|
|
|
|
|
assert (fixp->fx_next != NULL
|
|
|
|
|
&& fixp->fx_next->fx_r_type == BFD_RELOC_PCREL_LO16);
|
|
|
|
|
pcrel_address = (fixp->fx_next->fx_where
|
|
|
|
|
+ fixp->fx_next->fx_frag->fr_address);
|
|
|
|
|
}
|
1999-05-03 09:29:11 +02:00
|
|
|
|
else
|
bfd/
* elf32-mips.c (elf_mips_howto_table_rel): Replace all uses of
mips_elf_generic_reloc with _bfd_mips_elf_generic_reloc. Use
_bfd_mips_elf_hi16_reloc for R_MIPS_HI16 and R_MIPS_GNU_REL_HI16,
_bfd_mips_elf_lo16_reloc for R_MIPS_LO16 and R_MIPS_GNU_REL_LO16,
and _bfd_mips_elf_got16_reloc for R_MIPS_GOT16. Change rightshift
to 16 for R_MIPS_HI16 and R_MIPS_GNU_REL_HI16.
(mips_elf_generic_reloc, struct mips_hi16, mips_elf_hi16_reloc)
(mips_elf_lo16_reloc, mips_elf_got16_reloc): Delete.
(_bfd_mips_elf32_gprel16_reloc): Remove special case.
(mips_elf_gprel32_reloc, mips32_64bit_reloc): Likewise.
* elf64-mips.c (mips_elf64_howto_table_rel): Replace all uses of
mips_elf_generic_reloc with _bfd_mips_elf_generic_reloc. Use
_bfd_mips_elf_hi16_reloc for R_MIPS_HI16, _bfd_mips_elf_lo16_reloc
for R_MIPS_LO16 and _bfd_mips_elf_got16_reloc for R_MIPS_GOT16.
Change R_MIPS_HI16's rightshift to 16.
(mips_elf64_howto_table_rela): Replace all uses of
mips_elf_generic_reloc with _bfd_mips_elf_generic_reloc.
Use _bfd_mips_elf_generic_reloc for R_MIPS_GOT16 as well.
(mips_elf64_hi16_reloc, mips_elf64_got16_reloc): Delete.
(mips_elf64_shift6_reloc): Remove special case. Use
_bfd_mips_elf_generic_reloc instead of returning bfd_reloc_continue.
* elfn32-mips.c (prev_reloc_section): Delete.
(prev_reloc_address, prev_reloc_addend): Delete.
(elf_mips_howto_table_rel, elf_mips_howto_table_rela): As for
elf64-mips.c
(GET_RELOC_ADDEND, SET_RELOC_ADDEND): Delete.
(mips_elf_generic_reloc, struct mips_hi16, mips_elf_hi16_reloc)
(mips_elf_lo16_reloc, mips_elf_got16_reloc): Delete.
(mips_elf_gprel16_reloc): Delete use of GET_RELOC_ADDEND.
(mips_elf_literal_reloc, mips_elf_gprel32_reloc): Likewise.
(mips16_jump_reloc, mips16_gprel_reloc): Likewise.
(mips_elf_shift6_reloc): Likewise. Delete use of SET_RELOC_ADDEND.
* elfxx-mips.c (_bfd_mips_elf_gprel16_with_gp): Use
_bfd_relocate_contents to install an in-place addend.
(mips_hi16): New structure.
(mips_hi16_list): Moved from elf32-mips.c.
(_bfd_mips_elf_hi16_reloc, _bfd_mips_elf_got16_reloc): New functions.
(_bfd_mips_elf_lo16_reloc, _bfd_mips_elf_generic_reloc): New functions.
(mips_elf_calculate_relocation): Assume addend is unshifted.
(_bfd_mips_elf_relocate_section): Don't apply the howto rightshift
on top of the usual high-part shift. Don't shift the addend right
before calling mips_elf_calculate_relocation.
* elfxx-mips.h (_bfd_mips_elf_hi16_reloc): Declare.
(_bfd_mips_elf_got16_reloc, _bfd_mips_elf_lo16_reloc): Declare.
(_bfd_mips_elf_generic_reloc): Declare.
gas/
* config/tc-mips.c (mips_need_elf_addend_fixup): Delete.
(md_apply_fix3): Remove bfd_install_relocation workarounds.
(tc_gen_reloc): Likewise. Factor handling of pc-relative relocations
and treat fx_addnumber as relative to the relocation address.
gas/testsuite/
* gas/mips/mips16-jalx.d: Use -mabi=o64.
* gas/mips/mips16.d: Likewise.
* gas/mips/elf-rel17.[sd]: New test.
* gas/mips/mips.exp: Run it.
2003-12-18 11:23:10 +01:00
|
|
|
|
pcrel_address = reloc->address;
|
|
|
|
|
|
|
|
|
|
if (OUTPUT_FLAVOR == bfd_target_elf_flavour)
|
|
|
|
|
{
|
|
|
|
|
/* At this point, fx_addnumber is "symbol offset - pcrel_address".
|
|
|
|
|
Relocations want only the symbol offset. */
|
|
|
|
|
reloc->addend = fixp->fx_addnumber + pcrel_address;
|
|
|
|
|
}
|
|
|
|
|
else if (fixp->fx_r_type == BFD_RELOC_PCREL_LO16
|
|
|
|
|
|| fixp->fx_r_type == BFD_RELOC_PCREL_HI16_S)
|
2002-01-30 03:14:19 +01:00
|
|
|
|
{
|
bfd/
* elf32-mips.c (elf_mips_howto_table_rel): Replace all uses of
mips_elf_generic_reloc with _bfd_mips_elf_generic_reloc. Use
_bfd_mips_elf_hi16_reloc for R_MIPS_HI16 and R_MIPS_GNU_REL_HI16,
_bfd_mips_elf_lo16_reloc for R_MIPS_LO16 and R_MIPS_GNU_REL_LO16,
and _bfd_mips_elf_got16_reloc for R_MIPS_GOT16. Change rightshift
to 16 for R_MIPS_HI16 and R_MIPS_GNU_REL_HI16.
(mips_elf_generic_reloc, struct mips_hi16, mips_elf_hi16_reloc)
(mips_elf_lo16_reloc, mips_elf_got16_reloc): Delete.
(_bfd_mips_elf32_gprel16_reloc): Remove special case.
(mips_elf_gprel32_reloc, mips32_64bit_reloc): Likewise.
* elf64-mips.c (mips_elf64_howto_table_rel): Replace all uses of
mips_elf_generic_reloc with _bfd_mips_elf_generic_reloc. Use
_bfd_mips_elf_hi16_reloc for R_MIPS_HI16, _bfd_mips_elf_lo16_reloc
for R_MIPS_LO16 and _bfd_mips_elf_got16_reloc for R_MIPS_GOT16.
Change R_MIPS_HI16's rightshift to 16.
(mips_elf64_howto_table_rela): Replace all uses of
mips_elf_generic_reloc with _bfd_mips_elf_generic_reloc.
Use _bfd_mips_elf_generic_reloc for R_MIPS_GOT16 as well.
(mips_elf64_hi16_reloc, mips_elf64_got16_reloc): Delete.
(mips_elf64_shift6_reloc): Remove special case. Use
_bfd_mips_elf_generic_reloc instead of returning bfd_reloc_continue.
* elfn32-mips.c (prev_reloc_section): Delete.
(prev_reloc_address, prev_reloc_addend): Delete.
(elf_mips_howto_table_rel, elf_mips_howto_table_rela): As for
elf64-mips.c
(GET_RELOC_ADDEND, SET_RELOC_ADDEND): Delete.
(mips_elf_generic_reloc, struct mips_hi16, mips_elf_hi16_reloc)
(mips_elf_lo16_reloc, mips_elf_got16_reloc): Delete.
(mips_elf_gprel16_reloc): Delete use of GET_RELOC_ADDEND.
(mips_elf_literal_reloc, mips_elf_gprel32_reloc): Likewise.
(mips16_jump_reloc, mips16_gprel_reloc): Likewise.
(mips_elf_shift6_reloc): Likewise. Delete use of SET_RELOC_ADDEND.
* elfxx-mips.c (_bfd_mips_elf_gprel16_with_gp): Use
_bfd_relocate_contents to install an in-place addend.
(mips_hi16): New structure.
(mips_hi16_list): Moved from elf32-mips.c.
(_bfd_mips_elf_hi16_reloc, _bfd_mips_elf_got16_reloc): New functions.
(_bfd_mips_elf_lo16_reloc, _bfd_mips_elf_generic_reloc): New functions.
(mips_elf_calculate_relocation): Assume addend is unshifted.
(_bfd_mips_elf_relocate_section): Don't apply the howto rightshift
on top of the usual high-part shift. Don't shift the addend right
before calling mips_elf_calculate_relocation.
* elfxx-mips.h (_bfd_mips_elf_hi16_reloc): Declare.
(_bfd_mips_elf_got16_reloc, _bfd_mips_elf_lo16_reloc): Declare.
(_bfd_mips_elf_generic_reloc): Declare.
gas/
* config/tc-mips.c (mips_need_elf_addend_fixup): Delete.
(md_apply_fix3): Remove bfd_install_relocation workarounds.
(tc_gen_reloc): Likewise. Factor handling of pc-relative relocations
and treat fx_addnumber as relative to the relocation address.
gas/testsuite/
* gas/mips/mips16-jalx.d: Use -mabi=o64.
* gas/mips/mips16.d: Likewise.
* gas/mips/elf-rel17.[sd]: New test.
* gas/mips/mips.exp: Run it.
2003-12-18 11:23:10 +01:00
|
|
|
|
/* We use a special addend for an internal RELLO or RELHI reloc. */
|
2002-01-30 03:14:19 +01:00
|
|
|
|
if (symbol_section_p (fixp->fx_addsy))
|
bfd/
* elf32-mips.c (elf_mips_howto_table_rel): Replace all uses of
mips_elf_generic_reloc with _bfd_mips_elf_generic_reloc. Use
_bfd_mips_elf_hi16_reloc for R_MIPS_HI16 and R_MIPS_GNU_REL_HI16,
_bfd_mips_elf_lo16_reloc for R_MIPS_LO16 and R_MIPS_GNU_REL_LO16,
and _bfd_mips_elf_got16_reloc for R_MIPS_GOT16. Change rightshift
to 16 for R_MIPS_HI16 and R_MIPS_GNU_REL_HI16.
(mips_elf_generic_reloc, struct mips_hi16, mips_elf_hi16_reloc)
(mips_elf_lo16_reloc, mips_elf_got16_reloc): Delete.
(_bfd_mips_elf32_gprel16_reloc): Remove special case.
(mips_elf_gprel32_reloc, mips32_64bit_reloc): Likewise.
* elf64-mips.c (mips_elf64_howto_table_rel): Replace all uses of
mips_elf_generic_reloc with _bfd_mips_elf_generic_reloc. Use
_bfd_mips_elf_hi16_reloc for R_MIPS_HI16, _bfd_mips_elf_lo16_reloc
for R_MIPS_LO16 and _bfd_mips_elf_got16_reloc for R_MIPS_GOT16.
Change R_MIPS_HI16's rightshift to 16.
(mips_elf64_howto_table_rela): Replace all uses of
mips_elf_generic_reloc with _bfd_mips_elf_generic_reloc.
Use _bfd_mips_elf_generic_reloc for R_MIPS_GOT16 as well.
(mips_elf64_hi16_reloc, mips_elf64_got16_reloc): Delete.
(mips_elf64_shift6_reloc): Remove special case. Use
_bfd_mips_elf_generic_reloc instead of returning bfd_reloc_continue.
* elfn32-mips.c (prev_reloc_section): Delete.
(prev_reloc_address, prev_reloc_addend): Delete.
(elf_mips_howto_table_rel, elf_mips_howto_table_rela): As for
elf64-mips.c
(GET_RELOC_ADDEND, SET_RELOC_ADDEND): Delete.
(mips_elf_generic_reloc, struct mips_hi16, mips_elf_hi16_reloc)
(mips_elf_lo16_reloc, mips_elf_got16_reloc): Delete.
(mips_elf_gprel16_reloc): Delete use of GET_RELOC_ADDEND.
(mips_elf_literal_reloc, mips_elf_gprel32_reloc): Likewise.
(mips16_jump_reloc, mips16_gprel_reloc): Likewise.
(mips_elf_shift6_reloc): Likewise. Delete use of SET_RELOC_ADDEND.
* elfxx-mips.c (_bfd_mips_elf_gprel16_with_gp): Use
_bfd_relocate_contents to install an in-place addend.
(mips_hi16): New structure.
(mips_hi16_list): Moved from elf32-mips.c.
(_bfd_mips_elf_hi16_reloc, _bfd_mips_elf_got16_reloc): New functions.
(_bfd_mips_elf_lo16_reloc, _bfd_mips_elf_generic_reloc): New functions.
(mips_elf_calculate_relocation): Assume addend is unshifted.
(_bfd_mips_elf_relocate_section): Don't apply the howto rightshift
on top of the usual high-part shift. Don't shift the addend right
before calling mips_elf_calculate_relocation.
* elfxx-mips.h (_bfd_mips_elf_hi16_reloc): Declare.
(_bfd_mips_elf_got16_reloc, _bfd_mips_elf_lo16_reloc): Declare.
(_bfd_mips_elf_generic_reloc): Declare.
gas/
* config/tc-mips.c (mips_need_elf_addend_fixup): Delete.
(md_apply_fix3): Remove bfd_install_relocation workarounds.
(tc_gen_reloc): Likewise. Factor handling of pc-relative relocations
and treat fx_addnumber as relative to the relocation address.
gas/testsuite/
* gas/mips/mips16-jalx.d: Use -mabi=o64.
* gas/mips/mips16.d: Likewise.
* gas/mips/elf-rel17.[sd]: New test.
* gas/mips/mips.exp: Run it.
2003-12-18 11:23:10 +01:00
|
|
|
|
reloc->addend = pcrel_address - S_GET_VALUE (fixp->fx_subsy);
|
2002-01-30 03:14:19 +01:00
|
|
|
|
else
|
bfd/
* elf32-mips.c (elf_mips_howto_table_rel): Replace all uses of
mips_elf_generic_reloc with _bfd_mips_elf_generic_reloc. Use
_bfd_mips_elf_hi16_reloc for R_MIPS_HI16 and R_MIPS_GNU_REL_HI16,
_bfd_mips_elf_lo16_reloc for R_MIPS_LO16 and R_MIPS_GNU_REL_LO16,
and _bfd_mips_elf_got16_reloc for R_MIPS_GOT16. Change rightshift
to 16 for R_MIPS_HI16 and R_MIPS_GNU_REL_HI16.
(mips_elf_generic_reloc, struct mips_hi16, mips_elf_hi16_reloc)
(mips_elf_lo16_reloc, mips_elf_got16_reloc): Delete.
(_bfd_mips_elf32_gprel16_reloc): Remove special case.
(mips_elf_gprel32_reloc, mips32_64bit_reloc): Likewise.
* elf64-mips.c (mips_elf64_howto_table_rel): Replace all uses of
mips_elf_generic_reloc with _bfd_mips_elf_generic_reloc. Use
_bfd_mips_elf_hi16_reloc for R_MIPS_HI16, _bfd_mips_elf_lo16_reloc
for R_MIPS_LO16 and _bfd_mips_elf_got16_reloc for R_MIPS_GOT16.
Change R_MIPS_HI16's rightshift to 16.
(mips_elf64_howto_table_rela): Replace all uses of
mips_elf_generic_reloc with _bfd_mips_elf_generic_reloc.
Use _bfd_mips_elf_generic_reloc for R_MIPS_GOT16 as well.
(mips_elf64_hi16_reloc, mips_elf64_got16_reloc): Delete.
(mips_elf64_shift6_reloc): Remove special case. Use
_bfd_mips_elf_generic_reloc instead of returning bfd_reloc_continue.
* elfn32-mips.c (prev_reloc_section): Delete.
(prev_reloc_address, prev_reloc_addend): Delete.
(elf_mips_howto_table_rel, elf_mips_howto_table_rela): As for
elf64-mips.c
(GET_RELOC_ADDEND, SET_RELOC_ADDEND): Delete.
(mips_elf_generic_reloc, struct mips_hi16, mips_elf_hi16_reloc)
(mips_elf_lo16_reloc, mips_elf_got16_reloc): Delete.
(mips_elf_gprel16_reloc): Delete use of GET_RELOC_ADDEND.
(mips_elf_literal_reloc, mips_elf_gprel32_reloc): Likewise.
(mips16_jump_reloc, mips16_gprel_reloc): Likewise.
(mips_elf_shift6_reloc): Likewise. Delete use of SET_RELOC_ADDEND.
* elfxx-mips.c (_bfd_mips_elf_gprel16_with_gp): Use
_bfd_relocate_contents to install an in-place addend.
(mips_hi16): New structure.
(mips_hi16_list): Moved from elf32-mips.c.
(_bfd_mips_elf_hi16_reloc, _bfd_mips_elf_got16_reloc): New functions.
(_bfd_mips_elf_lo16_reloc, _bfd_mips_elf_generic_reloc): New functions.
(mips_elf_calculate_relocation): Assume addend is unshifted.
(_bfd_mips_elf_relocate_section): Don't apply the howto rightshift
on top of the usual high-part shift. Don't shift the addend right
before calling mips_elf_calculate_relocation.
* elfxx-mips.h (_bfd_mips_elf_hi16_reloc): Declare.
(_bfd_mips_elf_got16_reloc, _bfd_mips_elf_lo16_reloc): Declare.
(_bfd_mips_elf_generic_reloc): Declare.
gas/
* config/tc-mips.c (mips_need_elf_addend_fixup): Delete.
(md_apply_fix3): Remove bfd_install_relocation workarounds.
(tc_gen_reloc): Likewise. Factor handling of pc-relative relocations
and treat fx_addnumber as relative to the relocation address.
gas/testsuite/
* gas/mips/mips16-jalx.d: Use -mabi=o64.
* gas/mips/mips16.d: Likewise.
* gas/mips/elf-rel17.[sd]: New test.
* gas/mips/mips.exp: Run it.
2003-12-18 11:23:10 +01:00
|
|
|
|
reloc->addend = fixp->fx_addnumber + pcrel_address;
|
2002-01-30 03:14:19 +01:00
|
|
|
|
}
|
1999-05-03 09:29:11 +02:00
|
|
|
|
else
|
2002-01-30 03:14:19 +01:00
|
|
|
|
{
|
bfd/
* elf32-mips.c (elf_mips_howto_table_rel): Replace all uses of
mips_elf_generic_reloc with _bfd_mips_elf_generic_reloc. Use
_bfd_mips_elf_hi16_reloc for R_MIPS_HI16 and R_MIPS_GNU_REL_HI16,
_bfd_mips_elf_lo16_reloc for R_MIPS_LO16 and R_MIPS_GNU_REL_LO16,
and _bfd_mips_elf_got16_reloc for R_MIPS_GOT16. Change rightshift
to 16 for R_MIPS_HI16 and R_MIPS_GNU_REL_HI16.
(mips_elf_generic_reloc, struct mips_hi16, mips_elf_hi16_reloc)
(mips_elf_lo16_reloc, mips_elf_got16_reloc): Delete.
(_bfd_mips_elf32_gprel16_reloc): Remove special case.
(mips_elf_gprel32_reloc, mips32_64bit_reloc): Likewise.
* elf64-mips.c (mips_elf64_howto_table_rel): Replace all uses of
mips_elf_generic_reloc with _bfd_mips_elf_generic_reloc. Use
_bfd_mips_elf_hi16_reloc for R_MIPS_HI16, _bfd_mips_elf_lo16_reloc
for R_MIPS_LO16 and _bfd_mips_elf_got16_reloc for R_MIPS_GOT16.
Change R_MIPS_HI16's rightshift to 16.
(mips_elf64_howto_table_rela): Replace all uses of
mips_elf_generic_reloc with _bfd_mips_elf_generic_reloc.
Use _bfd_mips_elf_generic_reloc for R_MIPS_GOT16 as well.
(mips_elf64_hi16_reloc, mips_elf64_got16_reloc): Delete.
(mips_elf64_shift6_reloc): Remove special case. Use
_bfd_mips_elf_generic_reloc instead of returning bfd_reloc_continue.
* elfn32-mips.c (prev_reloc_section): Delete.
(prev_reloc_address, prev_reloc_addend): Delete.
(elf_mips_howto_table_rel, elf_mips_howto_table_rela): As for
elf64-mips.c
(GET_RELOC_ADDEND, SET_RELOC_ADDEND): Delete.
(mips_elf_generic_reloc, struct mips_hi16, mips_elf_hi16_reloc)
(mips_elf_lo16_reloc, mips_elf_got16_reloc): Delete.
(mips_elf_gprel16_reloc): Delete use of GET_RELOC_ADDEND.
(mips_elf_literal_reloc, mips_elf_gprel32_reloc): Likewise.
(mips16_jump_reloc, mips16_gprel_reloc): Likewise.
(mips_elf_shift6_reloc): Likewise. Delete use of SET_RELOC_ADDEND.
* elfxx-mips.c (_bfd_mips_elf_gprel16_with_gp): Use
_bfd_relocate_contents to install an in-place addend.
(mips_hi16): New structure.
(mips_hi16_list): Moved from elf32-mips.c.
(_bfd_mips_elf_hi16_reloc, _bfd_mips_elf_got16_reloc): New functions.
(_bfd_mips_elf_lo16_reloc, _bfd_mips_elf_generic_reloc): New functions.
(mips_elf_calculate_relocation): Assume addend is unshifted.
(_bfd_mips_elf_relocate_section): Don't apply the howto rightshift
on top of the usual high-part shift. Don't shift the addend right
before calling mips_elf_calculate_relocation.
* elfxx-mips.h (_bfd_mips_elf_hi16_reloc): Declare.
(_bfd_mips_elf_got16_reloc, _bfd_mips_elf_lo16_reloc): Declare.
(_bfd_mips_elf_generic_reloc): Declare.
gas/
* config/tc-mips.c (mips_need_elf_addend_fixup): Delete.
(md_apply_fix3): Remove bfd_install_relocation workarounds.
(tc_gen_reloc): Likewise. Factor handling of pc-relative relocations
and treat fx_addnumber as relative to the relocation address.
gas/testsuite/
* gas/mips/mips16-jalx.d: Use -mabi=o64.
* gas/mips/mips16.d: Likewise.
* gas/mips/elf-rel17.[sd]: New test.
* gas/mips/mips.exp: Run it.
2003-12-18 11:23:10 +01:00
|
|
|
|
if (OUTPUT_FLAVOR != bfd_target_aout_flavour)
|
|
|
|
|
/* A gruesome hack which is a result of the gruesome gas reloc
|
|
|
|
|
handling. */
|
|
|
|
|
reloc->addend = pcrel_address;
|
2002-01-30 03:14:19 +01:00
|
|
|
|
else
|
bfd/
* elf32-mips.c (elf_mips_howto_table_rel): Replace all uses of
mips_elf_generic_reloc with _bfd_mips_elf_generic_reloc. Use
_bfd_mips_elf_hi16_reloc for R_MIPS_HI16 and R_MIPS_GNU_REL_HI16,
_bfd_mips_elf_lo16_reloc for R_MIPS_LO16 and R_MIPS_GNU_REL_LO16,
and _bfd_mips_elf_got16_reloc for R_MIPS_GOT16. Change rightshift
to 16 for R_MIPS_HI16 and R_MIPS_GNU_REL_HI16.
(mips_elf_generic_reloc, struct mips_hi16, mips_elf_hi16_reloc)
(mips_elf_lo16_reloc, mips_elf_got16_reloc): Delete.
(_bfd_mips_elf32_gprel16_reloc): Remove special case.
(mips_elf_gprel32_reloc, mips32_64bit_reloc): Likewise.
* elf64-mips.c (mips_elf64_howto_table_rel): Replace all uses of
mips_elf_generic_reloc with _bfd_mips_elf_generic_reloc. Use
_bfd_mips_elf_hi16_reloc for R_MIPS_HI16, _bfd_mips_elf_lo16_reloc
for R_MIPS_LO16 and _bfd_mips_elf_got16_reloc for R_MIPS_GOT16.
Change R_MIPS_HI16's rightshift to 16.
(mips_elf64_howto_table_rela): Replace all uses of
mips_elf_generic_reloc with _bfd_mips_elf_generic_reloc.
Use _bfd_mips_elf_generic_reloc for R_MIPS_GOT16 as well.
(mips_elf64_hi16_reloc, mips_elf64_got16_reloc): Delete.
(mips_elf64_shift6_reloc): Remove special case. Use
_bfd_mips_elf_generic_reloc instead of returning bfd_reloc_continue.
* elfn32-mips.c (prev_reloc_section): Delete.
(prev_reloc_address, prev_reloc_addend): Delete.
(elf_mips_howto_table_rel, elf_mips_howto_table_rela): As for
elf64-mips.c
(GET_RELOC_ADDEND, SET_RELOC_ADDEND): Delete.
(mips_elf_generic_reloc, struct mips_hi16, mips_elf_hi16_reloc)
(mips_elf_lo16_reloc, mips_elf_got16_reloc): Delete.
(mips_elf_gprel16_reloc): Delete use of GET_RELOC_ADDEND.
(mips_elf_literal_reloc, mips_elf_gprel32_reloc): Likewise.
(mips16_jump_reloc, mips16_gprel_reloc): Likewise.
(mips_elf_shift6_reloc): Likewise. Delete use of SET_RELOC_ADDEND.
* elfxx-mips.c (_bfd_mips_elf_gprel16_with_gp): Use
_bfd_relocate_contents to install an in-place addend.
(mips_hi16): New structure.
(mips_hi16_list): Moved from elf32-mips.c.
(_bfd_mips_elf_hi16_reloc, _bfd_mips_elf_got16_reloc): New functions.
(_bfd_mips_elf_lo16_reloc, _bfd_mips_elf_generic_reloc): New functions.
(mips_elf_calculate_relocation): Assume addend is unshifted.
(_bfd_mips_elf_relocate_section): Don't apply the howto rightshift
on top of the usual high-part shift. Don't shift the addend right
before calling mips_elf_calculate_relocation.
* elfxx-mips.h (_bfd_mips_elf_hi16_reloc): Declare.
(_bfd_mips_elf_got16_reloc, _bfd_mips_elf_lo16_reloc): Declare.
(_bfd_mips_elf_generic_reloc): Declare.
gas/
* config/tc-mips.c (mips_need_elf_addend_fixup): Delete.
(md_apply_fix3): Remove bfd_install_relocation workarounds.
(tc_gen_reloc): Likewise. Factor handling of pc-relative relocations
and treat fx_addnumber as relative to the relocation address.
gas/testsuite/
* gas/mips/mips16-jalx.d: Use -mabi=o64.
* gas/mips/mips16.d: Likewise.
* gas/mips/elf-rel17.[sd]: New test.
* gas/mips/mips.exp: Run it.
2003-12-18 11:23:10 +01:00
|
|
|
|
reloc->addend = -pcrel_address;
|
2002-01-30 03:14:19 +01:00
|
|
|
|
}
|
1999-05-03 09:29:11 +02:00
|
|
|
|
}
|
|
|
|
|
else
|
bfd/
* elf32-mips.c (elf_mips_howto_table_rel): Replace all uses of
mips_elf_generic_reloc with _bfd_mips_elf_generic_reloc. Use
_bfd_mips_elf_hi16_reloc for R_MIPS_HI16 and R_MIPS_GNU_REL_HI16,
_bfd_mips_elf_lo16_reloc for R_MIPS_LO16 and R_MIPS_GNU_REL_LO16,
and _bfd_mips_elf_got16_reloc for R_MIPS_GOT16. Change rightshift
to 16 for R_MIPS_HI16 and R_MIPS_GNU_REL_HI16.
(mips_elf_generic_reloc, struct mips_hi16, mips_elf_hi16_reloc)
(mips_elf_lo16_reloc, mips_elf_got16_reloc): Delete.
(_bfd_mips_elf32_gprel16_reloc): Remove special case.
(mips_elf_gprel32_reloc, mips32_64bit_reloc): Likewise.
* elf64-mips.c (mips_elf64_howto_table_rel): Replace all uses of
mips_elf_generic_reloc with _bfd_mips_elf_generic_reloc. Use
_bfd_mips_elf_hi16_reloc for R_MIPS_HI16, _bfd_mips_elf_lo16_reloc
for R_MIPS_LO16 and _bfd_mips_elf_got16_reloc for R_MIPS_GOT16.
Change R_MIPS_HI16's rightshift to 16.
(mips_elf64_howto_table_rela): Replace all uses of
mips_elf_generic_reloc with _bfd_mips_elf_generic_reloc.
Use _bfd_mips_elf_generic_reloc for R_MIPS_GOT16 as well.
(mips_elf64_hi16_reloc, mips_elf64_got16_reloc): Delete.
(mips_elf64_shift6_reloc): Remove special case. Use
_bfd_mips_elf_generic_reloc instead of returning bfd_reloc_continue.
* elfn32-mips.c (prev_reloc_section): Delete.
(prev_reloc_address, prev_reloc_addend): Delete.
(elf_mips_howto_table_rel, elf_mips_howto_table_rela): As for
elf64-mips.c
(GET_RELOC_ADDEND, SET_RELOC_ADDEND): Delete.
(mips_elf_generic_reloc, struct mips_hi16, mips_elf_hi16_reloc)
(mips_elf_lo16_reloc, mips_elf_got16_reloc): Delete.
(mips_elf_gprel16_reloc): Delete use of GET_RELOC_ADDEND.
(mips_elf_literal_reloc, mips_elf_gprel32_reloc): Likewise.
(mips16_jump_reloc, mips16_gprel_reloc): Likewise.
(mips_elf_shift6_reloc): Likewise. Delete use of SET_RELOC_ADDEND.
* elfxx-mips.c (_bfd_mips_elf_gprel16_with_gp): Use
_bfd_relocate_contents to install an in-place addend.
(mips_hi16): New structure.
(mips_hi16_list): Moved from elf32-mips.c.
(_bfd_mips_elf_hi16_reloc, _bfd_mips_elf_got16_reloc): New functions.
(_bfd_mips_elf_lo16_reloc, _bfd_mips_elf_generic_reloc): New functions.
(mips_elf_calculate_relocation): Assume addend is unshifted.
(_bfd_mips_elf_relocate_section): Don't apply the howto rightshift
on top of the usual high-part shift. Don't shift the addend right
before calling mips_elf_calculate_relocation.
* elfxx-mips.h (_bfd_mips_elf_hi16_reloc): Declare.
(_bfd_mips_elf_got16_reloc, _bfd_mips_elf_lo16_reloc): Declare.
(_bfd_mips_elf_generic_reloc): Declare.
gas/
* config/tc-mips.c (mips_need_elf_addend_fixup): Delete.
(md_apply_fix3): Remove bfd_install_relocation workarounds.
(tc_gen_reloc): Likewise. Factor handling of pc-relative relocations
and treat fx_addnumber as relative to the relocation address.
gas/testsuite/
* gas/mips/mips16-jalx.d: Use -mabi=o64.
* gas/mips/mips16.d: Likewise.
* gas/mips/elf-rel17.[sd]: New test.
* gas/mips/mips.exp: Run it.
2003-12-18 11:23:10 +01:00
|
|
|
|
reloc->addend = fixp->fx_addnumber;
|
1999-05-03 09:29:11 +02:00
|
|
|
|
|
|
|
|
|
/* If this is a variant frag, we may need to adjust the existing
|
|
|
|
|
reloc and generate a new one. */
|
|
|
|
|
if (fixp->fx_frag->fr_opcode != NULL
|
2002-09-18 04:25:19 +02:00
|
|
|
|
&& ((fixp->fx_r_type == BFD_RELOC_GPREL16
|
|
|
|
|
&& ! HAVE_NEWABI)
|
* config/tc-mips.h (tc_frag_data_type, TC_FRAG_TYPE): New.
* config/tc-mips.c: Use signed add for n32 address arithmetic.
(append_insn): When filling delay slots with instructions
that have fixups that tc_gen_reloc might consider modifyable
in variant frags, start a new frag.
(load_address): Generate GOT_DISP with of without offset
depending on whether symbol is local. For -xgot, use
GOT_PAGE/GOT_OFST or GOT_HI16/GOT_LO16.
(macro) <M_DLA_AB, M_LA_AB>: Likewise.
<M_JAL_A>: In NewABI, use CALL16 or GOT_DISP for small got,
CALL_HI16/CALL_LO16 or GOT_PAGE/GOT_OFST for big got.
<ld_st>: In NewABI with small got, always use
GOT_PAGE/GOT_OFST, with the latter in the load/store
instruction. With big got, use GOT_HI16/GOT_LO16 or
GOT_PAGE/GOT_OFST.
(tc_gen_reloc): Adjust variant frags with GOT_DISP in NewABI.
Add tc_frag_data.tc_fr_offset to addends. Decay CALL16,
GOT_OFST and GOT_DISP to GOT_DISP in NewABI.
(md_convert_frag): Use memmove for safe copying of overlapping
regions.
2003-04-11 03:56:50 +02:00
|
|
|
|
|| (fixp->fx_r_type == BFD_RELOC_MIPS_GOT_DISP
|
|
|
|
|
&& HAVE_NEWABI)
|
1999-05-03 09:29:11 +02:00
|
|
|
|
|| fixp->fx_r_type == BFD_RELOC_MIPS_GOT16
|
|
|
|
|
|| fixp->fx_r_type == BFD_RELOC_MIPS_CALL16
|
|
|
|
|
|| fixp->fx_r_type == BFD_RELOC_MIPS_GOT_HI16
|
|
|
|
|
|| fixp->fx_r_type == BFD_RELOC_MIPS_GOT_LO16
|
|
|
|
|
|| fixp->fx_r_type == BFD_RELOC_MIPS_CALL_HI16
|
2001-10-10 03:08:35 +02:00
|
|
|
|
|| fixp->fx_r_type == BFD_RELOC_MIPS_CALL_LO16)
|
2002-09-18 04:25:19 +02:00
|
|
|
|
)
|
1999-05-03 09:29:11 +02:00
|
|
|
|
{
|
|
|
|
|
arelent *reloc2;
|
|
|
|
|
|
|
|
|
|
assert (! RELAX_MIPS16_P (fixp->fx_frag->fr_subtype));
|
|
|
|
|
|
|
|
|
|
/* If this is not the last reloc in this frag, then we have two
|
|
|
|
|
GPREL relocs, or a GOT_HI16/GOT_LO16 pair, or a
|
|
|
|
|
CALL_HI16/CALL_LO16, both of which are being replaced. Let
|
|
|
|
|
the second one handle all of them. */
|
|
|
|
|
if (fixp->fx_next != NULL
|
|
|
|
|
&& fixp->fx_frag == fixp->fx_next->fx_frag)
|
|
|
|
|
{
|
2001-12-02 14:14:48 +01:00
|
|
|
|
assert ((fixp->fx_r_type == BFD_RELOC_GPREL16
|
|
|
|
|
&& fixp->fx_next->fx_r_type == BFD_RELOC_GPREL16)
|
1999-05-03 09:29:11 +02:00
|
|
|
|
|| (fixp->fx_r_type == BFD_RELOC_MIPS_GOT_HI16
|
|
|
|
|
&& (fixp->fx_next->fx_r_type
|
|
|
|
|
== BFD_RELOC_MIPS_GOT_LO16))
|
|
|
|
|
|| (fixp->fx_r_type == BFD_RELOC_MIPS_CALL_HI16
|
|
|
|
|
&& (fixp->fx_next->fx_r_type
|
|
|
|
|
== BFD_RELOC_MIPS_CALL_LO16)));
|
|
|
|
|
retval[0] = NULL;
|
|
|
|
|
return retval;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
fixp->fx_where = fixp->fx_frag->fr_opcode - fixp->fx_frag->fr_literal;
|
|
|
|
|
reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
|
* config/tc-mips.h (tc_frag_data_type, TC_FRAG_TYPE): New.
* config/tc-mips.c: Use signed add for n32 address arithmetic.
(append_insn): When filling delay slots with instructions
that have fixups that tc_gen_reloc might consider modifyable
in variant frags, start a new frag.
(load_address): Generate GOT_DISP with of without offset
depending on whether symbol is local. For -xgot, use
GOT_PAGE/GOT_OFST or GOT_HI16/GOT_LO16.
(macro) <M_DLA_AB, M_LA_AB>: Likewise.
<M_JAL_A>: In NewABI, use CALL16 or GOT_DISP for small got,
CALL_HI16/CALL_LO16 or GOT_PAGE/GOT_OFST for big got.
<ld_st>: In NewABI with small got, always use
GOT_PAGE/GOT_OFST, with the latter in the load/store
instruction. With big got, use GOT_HI16/GOT_LO16 or
GOT_PAGE/GOT_OFST.
(tc_gen_reloc): Adjust variant frags with GOT_DISP in NewABI.
Add tc_frag_data.tc_fr_offset to addends. Decay CALL16,
GOT_OFST and GOT_DISP to GOT_DISP in NewABI.
(md_convert_frag): Use memmove for safe copying of overlapping
regions.
2003-04-11 03:56:50 +02:00
|
|
|
|
reloc->addend += fixp->fx_frag->tc_frag_data.tc_fr_offset;
|
1999-05-03 09:29:11 +02:00
|
|
|
|
reloc2 = retval[1] = (arelent *) xmalloc (sizeof (arelent));
|
Add support for storing local symbols in a small structure to save
memory when assembling large files.
* as.h: Don't include struc-symbol.h.
(symbolS): Add typedef.
* symbols.c: Include struc-symbol.h.
(local_hash): New static variable.
(save_symbol_name): New static function, from symbol_create.
(symbol_create): Call save_symbol_name.
(local_symbol_count): New static variable.
(local_symbol_conversion_count): Likewise.
(LOCAL_SYMBOL_CHECK): Define.
(local_symbol_make): New static function.
(local_symbol_convert): New static function.
(colon): Handle local symbols. Create local symbol for local
label name.
(symbol_table_insert): Handle local symbols.
(symbol_find_or_make): Create local symbol for local label name.
(symbol_find_base): Check for local symbol.
(symbol_append, symbol_insert): Check for local symbols.
(symbol_clear_list_pointers, symbol_remove): Likewise.
(verify_symbol_chain): Likewise.
(copy_symbol_attributes): Likewise.
(resolve_symbol_value): Handle local symbols.
(resolve_local_symbol): New static function.
(resolve_local_symbol_values): New function.
(S_GET_VALUE, S_SET_VALUE): Handle local symbols.
(S_IS_FUNCTION, S_IS_EXTERNAL, S_IS_WEAK, S_IS_COMMON): Likewise.
(S_IS_DEFINED, S_IS_DEBUG, S_IS_LOCAL, S_GET_NAME): Likewise.
(S_GET_SEGMENT, S_SET_SEGMENT, S_SET_EXTERNAL): Likewise.
(S_CLEAR_EXTERNAL, S_SET_WEAK, S_SET_NAME): Likewise.
(symbol_previous, symbol_next): New functions.
(symbol_get_value_expression): Likewise.
(symbol_set_value_expression): Likewise.
(symbol_set_frag, symbol_get_frag): Likewise.
(symbol_mark_used, symbol_clear_used, symbol_used_p): Likewise.
(symbol_mark_used_in_reloc): Likewise.
(symbol_clear_used_in_reloc, symbol_used_in_reloc_p): Likewise.
(symbol_mark_mri_common, symbol_clear_mri_common): Likewise.
(symbol_mri_common_p): Likewise.
(symbol_mark_written, symbol_clear_written): Likewise.
(symbol_written_p): Likewise.
(symbol_mark_resolved, symbol_resolved_p): Likewise.
(symbol_section_p, symbol_equated_p): Likewise.
(symbol_constant_p): Likewise.
(symbol_get_bfdsym, symbol_set_bfdsym): Likewise.
(symbol_get_obj, symbol_set_obj): Likewise.
(symbol_get_tc, symbol_set_tc): Likewise.
(symbol_begin): Initialize local_hash.
(print_symbol_value_1): Handle local symbols.
(symbol_print_statistics): Print local symbol statistics.
* symbols.h: Include "struc-symbol.h" if not BFD_ASSEMBLER.
Declare new symbols.c functions. Move many declarations here from
struc-symbol.h.
(SYMBOLS_NEED_BACKPOINTERS): Define if needed.
* struc-symbol.h (SYMBOLS_NEED_BACKPOINTERS): Don't set.
(struct symbol): Move bsym to make it clearly the first field.
Remove TARGET_SYMBOL_FIELDS.
(symbolS): Don't typedef.
(struct broken_word): Remove.
(N_TYPE_seg, seg_N_TYPE): Move to symbol.h.
(SEGMENT_TO_SYMBOL_TYPE, N_REGISTER): Likewise.
(symbol_clear_list_pointers): Likewise.
(symbol_insert, symbol_remove): Likewise.
(symbol_previous, symbol_append): Likewise.
(verify_symbol_chain, verify_symbol_chain_2): Likewise.
(struct local_symbol): Define.
(local_symbol_converted_p, local_symbol_mark_converted): Define.
(local_symbol_resolved_p, local_symbol_mark_resolved): Define.
(local_symbol_get_frag, local_symbol_set_frag): Define.
(local_symbol_get_real_symbol): Define.
(local_symbol_set_real_symbol): Define.
Define.
* write.c (write_object_file): Call resolve_local_symbol_values.
* config/obj-ecoff.h (OBJ_SYMFIELD_TYPE): Define.
(TARGET_SYMBOL_FIELDS): Don't define.
* config/obj-elf.h (OBJ_SYMFIELD_TYPE): Add local field. If
ECOFF_DEBUGGING, add ECOFF fields.
(ELF_TARGET_SYMBOL_FIELDS, TARGET_SYMBOL_FIELDS): Don't define.
* config/obj-multi.h (struct elf_obj_sy): Add local field. If
ECOFF_DEBUGGING, add ECOFF fields.
(ELF_TARGET_SYMBOL_FIELDS, TARGET_SYMBOL_FIELDS): Don't define.
(ECOFF_DEBUG_TARGET_SYMBOL_FIELDS): Don't define.
* config/tc-mcore.h: Don't include struc-symbol.h.
(TARGET_SYMBOL_FIELDS): Don't define.
(struct mcore_tc_sy): Define.
(TC_SYMFIELD_TYPE): Define.
* Many files: Use symbolS instead of struct symbol. Use new
accessor functions rather than referring to symbolS fields
directly.
* read.c (s_mri_common): Don't add in value of line_label.
* config/tc-mips.c (md_apply_fix): Correct parenthesization when
checking for SEC_LINK_ONCE.
* config/tc-sh.h (sh_fix_adjustable): Declare.
1999-06-03 02:29:48 +02:00
|
|
|
|
reloc2->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
|
|
|
|
|
*reloc2->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
|
1999-05-03 09:29:11 +02:00
|
|
|
|
reloc2->address = (reloc->address
|
|
|
|
|
+ (RELAX_RELOC2 (fixp->fx_frag->fr_subtype)
|
|
|
|
|
- RELAX_RELOC1 (fixp->fx_frag->fr_subtype)));
|
bfd/
* elf32-mips.c (elf_mips_howto_table_rel): Replace all uses of
mips_elf_generic_reloc with _bfd_mips_elf_generic_reloc. Use
_bfd_mips_elf_hi16_reloc for R_MIPS_HI16 and R_MIPS_GNU_REL_HI16,
_bfd_mips_elf_lo16_reloc for R_MIPS_LO16 and R_MIPS_GNU_REL_LO16,
and _bfd_mips_elf_got16_reloc for R_MIPS_GOT16. Change rightshift
to 16 for R_MIPS_HI16 and R_MIPS_GNU_REL_HI16.
(mips_elf_generic_reloc, struct mips_hi16, mips_elf_hi16_reloc)
(mips_elf_lo16_reloc, mips_elf_got16_reloc): Delete.
(_bfd_mips_elf32_gprel16_reloc): Remove special case.
(mips_elf_gprel32_reloc, mips32_64bit_reloc): Likewise.
* elf64-mips.c (mips_elf64_howto_table_rel): Replace all uses of
mips_elf_generic_reloc with _bfd_mips_elf_generic_reloc. Use
_bfd_mips_elf_hi16_reloc for R_MIPS_HI16, _bfd_mips_elf_lo16_reloc
for R_MIPS_LO16 and _bfd_mips_elf_got16_reloc for R_MIPS_GOT16.
Change R_MIPS_HI16's rightshift to 16.
(mips_elf64_howto_table_rela): Replace all uses of
mips_elf_generic_reloc with _bfd_mips_elf_generic_reloc.
Use _bfd_mips_elf_generic_reloc for R_MIPS_GOT16 as well.
(mips_elf64_hi16_reloc, mips_elf64_got16_reloc): Delete.
(mips_elf64_shift6_reloc): Remove special case. Use
_bfd_mips_elf_generic_reloc instead of returning bfd_reloc_continue.
* elfn32-mips.c (prev_reloc_section): Delete.
(prev_reloc_address, prev_reloc_addend): Delete.
(elf_mips_howto_table_rel, elf_mips_howto_table_rela): As for
elf64-mips.c
(GET_RELOC_ADDEND, SET_RELOC_ADDEND): Delete.
(mips_elf_generic_reloc, struct mips_hi16, mips_elf_hi16_reloc)
(mips_elf_lo16_reloc, mips_elf_got16_reloc): Delete.
(mips_elf_gprel16_reloc): Delete use of GET_RELOC_ADDEND.
(mips_elf_literal_reloc, mips_elf_gprel32_reloc): Likewise.
(mips16_jump_reloc, mips16_gprel_reloc): Likewise.
(mips_elf_shift6_reloc): Likewise. Delete use of SET_RELOC_ADDEND.
* elfxx-mips.c (_bfd_mips_elf_gprel16_with_gp): Use
_bfd_relocate_contents to install an in-place addend.
(mips_hi16): New structure.
(mips_hi16_list): Moved from elf32-mips.c.
(_bfd_mips_elf_hi16_reloc, _bfd_mips_elf_got16_reloc): New functions.
(_bfd_mips_elf_lo16_reloc, _bfd_mips_elf_generic_reloc): New functions.
(mips_elf_calculate_relocation): Assume addend is unshifted.
(_bfd_mips_elf_relocate_section): Don't apply the howto rightshift
on top of the usual high-part shift. Don't shift the addend right
before calling mips_elf_calculate_relocation.
* elfxx-mips.h (_bfd_mips_elf_hi16_reloc): Declare.
(_bfd_mips_elf_got16_reloc, _bfd_mips_elf_lo16_reloc): Declare.
(_bfd_mips_elf_generic_reloc): Declare.
gas/
* config/tc-mips.c (mips_need_elf_addend_fixup): Delete.
(md_apply_fix3): Remove bfd_install_relocation workarounds.
(tc_gen_reloc): Likewise. Factor handling of pc-relative relocations
and treat fx_addnumber as relative to the relocation address.
gas/testsuite/
* gas/mips/mips16-jalx.d: Use -mabi=o64.
* gas/mips/mips16.d: Likewise.
* gas/mips/elf-rel17.[sd]: New test.
* gas/mips/mips.exp: Run it.
2003-12-18 11:23:10 +01:00
|
|
|
|
reloc2->addend = reloc->addend;
|
1999-05-03 09:29:11 +02:00
|
|
|
|
reloc2->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_LO16);
|
|
|
|
|
assert (reloc2->howto != NULL);
|
|
|
|
|
|
|
|
|
|
if (RELAX_RELOC3 (fixp->fx_frag->fr_subtype))
|
|
|
|
|
{
|
|
|
|
|
arelent *reloc3;
|
|
|
|
|
|
|
|
|
|
reloc3 = retval[2] = (arelent *) xmalloc (sizeof (arelent));
|
|
|
|
|
*reloc3 = *reloc2;
|
|
|
|
|
reloc3->address += 4;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
if (mips_pic == NO_PIC)
|
|
|
|
|
{
|
2001-12-02 14:14:48 +01:00
|
|
|
|
assert (fixp->fx_r_type == BFD_RELOC_GPREL16);
|
1999-05-03 09:29:11 +02:00
|
|
|
|
fixp->fx_r_type = BFD_RELOC_HI16_S;
|
|
|
|
|
}
|
|
|
|
|
else if (mips_pic == SVR4_PIC)
|
|
|
|
|
{
|
|
|
|
|
switch (fixp->fx_r_type)
|
|
|
|
|
{
|
|
|
|
|
default:
|
|
|
|
|
abort ();
|
|
|
|
|
case BFD_RELOC_MIPS_GOT16:
|
|
|
|
|
break;
|
|
|
|
|
case BFD_RELOC_MIPS_GOT_LO16:
|
|
|
|
|
case BFD_RELOC_MIPS_CALL_LO16:
|
2002-09-18 04:25:19 +02:00
|
|
|
|
if (HAVE_NEWABI)
|
|
|
|
|
{
|
|
|
|
|
fixp->fx_r_type = BFD_RELOC_MIPS_GOT_PAGE;
|
|
|
|
|
reloc2->howto = bfd_reloc_type_lookup
|
|
|
|
|
(stdoutput, BFD_RELOC_MIPS_GOT_OFST);
|
|
|
|
|
}
|
|
|
|
|
else
|
|
|
|
|
fixp->fx_r_type = BFD_RELOC_MIPS_GOT16;
|
|
|
|
|
break;
|
* config/tc-mips.h (tc_frag_data_type, TC_FRAG_TYPE): New.
* config/tc-mips.c: Use signed add for n32 address arithmetic.
(append_insn): When filling delay slots with instructions
that have fixups that tc_gen_reloc might consider modifyable
in variant frags, start a new frag.
(load_address): Generate GOT_DISP with of without offset
depending on whether symbol is local. For -xgot, use
GOT_PAGE/GOT_OFST or GOT_HI16/GOT_LO16.
(macro) <M_DLA_AB, M_LA_AB>: Likewise.
<M_JAL_A>: In NewABI, use CALL16 or GOT_DISP for small got,
CALL_HI16/CALL_LO16 or GOT_PAGE/GOT_OFST for big got.
<ld_st>: In NewABI with small got, always use
GOT_PAGE/GOT_OFST, with the latter in the load/store
instruction. With big got, use GOT_HI16/GOT_LO16 or
GOT_PAGE/GOT_OFST.
(tc_gen_reloc): Adjust variant frags with GOT_DISP in NewABI.
Add tc_frag_data.tc_fr_offset to addends. Decay CALL16,
GOT_OFST and GOT_DISP to GOT_DISP in NewABI.
(md_convert_frag): Use memmove for safe copying of overlapping
regions.
2003-04-11 03:56:50 +02:00
|
|
|
|
case BFD_RELOC_MIPS_CALL16:
|
|
|
|
|
case BFD_RELOC_MIPS_GOT_OFST:
|
|
|
|
|
case BFD_RELOC_MIPS_GOT_DISP:
|
|
|
|
|
if (HAVE_NEWABI)
|
|
|
|
|
{
|
|
|
|
|
/* It may seem nonsensical to relax GOT_DISP to
|
|
|
|
|
GOT_DISP, but we're actually turning a GOT_DISP
|
|
|
|
|
without offset into a GOT_DISP with an offset,
|
|
|
|
|
getting rid of the separate addition, which we can
|
|
|
|
|
do when the symbol is found to be local. */
|
|
|
|
|
fixp->fx_r_type = BFD_RELOC_MIPS_GOT_DISP;
|
|
|
|
|
retval[1] = NULL;
|
|
|
|
|
}
|
|
|
|
|
else
|
|
|
|
|
fixp->fx_r_type = BFD_RELOC_MIPS_GOT16;
|
|
|
|
|
break;
|
1999-05-03 09:29:11 +02:00
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
else
|
|
|
|
|
abort ();
|
|
|
|
|
}
|
|
|
|
|
|
2002-05-31 01:32:47 +02:00
|
|
|
|
/* Since the old MIPS ELF ABI uses Rel instead of Rela, encode the vtable
|
|
|
|
|
entry to be used in the relocation's section offset. */
|
|
|
|
|
if (! HAVE_NEWABI && fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
|
1999-05-03 09:29:11 +02:00
|
|
|
|
{
|
|
|
|
|
reloc->address = reloc->addend;
|
|
|
|
|
reloc->addend = 0;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/* Since DIFF_EXPR_OK is defined in tc-mips.h, it is possible that
|
|
|
|
|
fixup_segment converted a non-PC relative reloc into a PC
|
|
|
|
|
relative reloc. In such a case, we need to convert the reloc
|
|
|
|
|
code. */
|
|
|
|
|
code = fixp->fx_r_type;
|
|
|
|
|
if (fixp->fx_pcrel)
|
|
|
|
|
{
|
|
|
|
|
switch (code)
|
|
|
|
|
{
|
|
|
|
|
case BFD_RELOC_8:
|
|
|
|
|
code = BFD_RELOC_8_PCREL;
|
|
|
|
|
break;
|
|
|
|
|
case BFD_RELOC_16:
|
|
|
|
|
code = BFD_RELOC_16_PCREL;
|
|
|
|
|
break;
|
|
|
|
|
case BFD_RELOC_32:
|
|
|
|
|
code = BFD_RELOC_32_PCREL;
|
|
|
|
|
break;
|
|
|
|
|
case BFD_RELOC_64:
|
|
|
|
|
code = BFD_RELOC_64_PCREL;
|
|
|
|
|
break;
|
|
|
|
|
case BFD_RELOC_8_PCREL:
|
|
|
|
|
case BFD_RELOC_16_PCREL:
|
|
|
|
|
case BFD_RELOC_32_PCREL:
|
|
|
|
|
case BFD_RELOC_64_PCREL:
|
|
|
|
|
case BFD_RELOC_16_PCREL_S2:
|
|
|
|
|
case BFD_RELOC_PCREL_HI16_S:
|
|
|
|
|
case BFD_RELOC_PCREL_LO16:
|
|
|
|
|
break;
|
|
|
|
|
default:
|
|
|
|
|
as_bad_where (fixp->fx_file, fixp->fx_line,
|
|
|
|
|
_("Cannot make %s relocation PC relative"),
|
|
|
|
|
bfd_get_reloc_code_name (code));
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
2003-03-13 00:06:08 +01:00
|
|
|
|
/* To support a PC relative reloc when generating embedded PIC code
|
|
|
|
|
for ECOFF, we use a Cygnus extension. We check for that here to
|
|
|
|
|
make sure that we don't let such a reloc escape normally. */
|
|
|
|
|
if ((OUTPUT_FLAVOR == bfd_target_ecoff_flavour
|
|
|
|
|
|| OUTPUT_FLAVOR == bfd_target_elf_flavour)
|
|
|
|
|
&& code == BFD_RELOC_16_PCREL_S2
|
|
|
|
|
&& mips_pic != EMBEDDED_PIC)
|
|
|
|
|
reloc->howto = NULL;
|
|
|
|
|
else
|
|
|
|
|
reloc->howto = bfd_reloc_type_lookup (stdoutput, code);
|
|
|
|
|
|
1999-05-03 09:29:11 +02:00
|
|
|
|
if (reloc->howto == NULL)
|
|
|
|
|
{
|
|
|
|
|
as_bad_where (fixp->fx_file, fixp->fx_line,
|
|
|
|
|
_("Can not represent %s relocation in this object file format"),
|
|
|
|
|
bfd_get_reloc_code_name (code));
|
|
|
|
|
retval[0] = NULL;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
return retval;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/* Relax a machine dependent frag. This returns the amount by which
|
|
|
|
|
the current size of the frag should change. */
|
|
|
|
|
|
|
|
|
|
int
|
2003-06-30 14:44:25 +02:00
|
|
|
|
mips_relax_frag (asection *sec, fragS *fragp, long stretch)
|
1999-05-03 09:29:11 +02:00
|
|
|
|
{
|
2002-10-12 07:23:33 +02:00
|
|
|
|
if (RELAX_BRANCH_P (fragp->fr_subtype))
|
|
|
|
|
{
|
|
|
|
|
offsetT old_var = fragp->fr_var;
|
2002-11-30 09:39:46 +01:00
|
|
|
|
|
|
|
|
|
fragp->fr_var = relaxed_branch_length (fragp, sec, TRUE);
|
2002-10-12 07:23:33 +02:00
|
|
|
|
|
|
|
|
|
return fragp->fr_var - old_var;
|
|
|
|
|
}
|
|
|
|
|
|
1999-05-03 09:29:11 +02:00
|
|
|
|
if (! RELAX_MIPS16_P (fragp->fr_subtype))
|
|
|
|
|
return 0;
|
|
|
|
|
|
2001-11-12 23:19:30 +01:00
|
|
|
|
if (mips16_extended_frag (fragp, NULL, stretch))
|
1999-05-03 09:29:11 +02:00
|
|
|
|
{
|
|
|
|
|
if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype))
|
|
|
|
|
return 0;
|
|
|
|
|
fragp->fr_subtype = RELAX_MIPS16_MARK_EXTENDED (fragp->fr_subtype);
|
|
|
|
|
return 2;
|
|
|
|
|
}
|
|
|
|
|
else
|
|
|
|
|
{
|
|
|
|
|
if (! RELAX_MIPS16_EXTENDED (fragp->fr_subtype))
|
|
|
|
|
return 0;
|
|
|
|
|
fragp->fr_subtype = RELAX_MIPS16_CLEAR_EXTENDED (fragp->fr_subtype);
|
|
|
|
|
return -2;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/* Convert a machine dependent frag. */
|
|
|
|
|
|
|
|
|
|
void
|
2003-06-30 14:44:25 +02:00
|
|
|
|
md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, segT asec, fragS *fragp)
|
1999-05-03 09:29:11 +02:00
|
|
|
|
{
|
|
|
|
|
int old, new;
|
|
|
|
|
char *fixptr;
|
|
|
|
|
|
2002-10-12 07:23:33 +02:00
|
|
|
|
if (RELAX_BRANCH_P (fragp->fr_subtype))
|
|
|
|
|
{
|
|
|
|
|
bfd_byte *buf;
|
|
|
|
|
unsigned long insn;
|
|
|
|
|
expressionS exp;
|
|
|
|
|
fixS *fixp;
|
2002-11-30 09:39:46 +01:00
|
|
|
|
|
2002-10-12 07:23:33 +02:00
|
|
|
|
buf = (bfd_byte *)fragp->fr_literal + fragp->fr_fix;
|
|
|
|
|
|
|
|
|
|
if (target_big_endian)
|
|
|
|
|
insn = bfd_getb32 (buf);
|
|
|
|
|
else
|
|
|
|
|
insn = bfd_getl32 (buf);
|
2002-11-30 09:39:46 +01:00
|
|
|
|
|
2002-10-12 07:23:33 +02:00
|
|
|
|
if (!RELAX_BRANCH_TOOFAR (fragp->fr_subtype))
|
|
|
|
|
{
|
|
|
|
|
/* We generate a fixup instead of applying it right now
|
|
|
|
|
because, if there are linker relaxations, we're going to
|
|
|
|
|
need the relocations. */
|
|
|
|
|
exp.X_op = O_symbol;
|
|
|
|
|
exp.X_add_symbol = fragp->fr_symbol;
|
|
|
|
|
exp.X_add_number = fragp->fr_offset;
|
|
|
|
|
|
|
|
|
|
fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal,
|
2003-03-13 00:06:08 +01:00
|
|
|
|
4, &exp, 1,
|
|
|
|
|
BFD_RELOC_16_PCREL_S2);
|
2002-10-12 07:23:33 +02:00
|
|
|
|
fixp->fx_file = fragp->fr_file;
|
|
|
|
|
fixp->fx_line = fragp->fr_line;
|
2002-11-30 09:39:46 +01:00
|
|
|
|
|
2003-06-30 14:44:25 +02:00
|
|
|
|
md_number_to_chars (buf, insn, 4);
|
2002-10-12 07:23:33 +02:00
|
|
|
|
buf += 4;
|
|
|
|
|
}
|
|
|
|
|
else
|
|
|
|
|
{
|
|
|
|
|
int i;
|
|
|
|
|
|
|
|
|
|
as_warn_where (fragp->fr_file, fragp->fr_line,
|
|
|
|
|
_("relaxed out-of-range branch into a jump"));
|
|
|
|
|
|
|
|
|
|
if (RELAX_BRANCH_UNCOND (fragp->fr_subtype))
|
|
|
|
|
goto uncond;
|
|
|
|
|
|
|
|
|
|
if (!RELAX_BRANCH_LIKELY (fragp->fr_subtype))
|
|
|
|
|
{
|
|
|
|
|
/* Reverse the branch. */
|
|
|
|
|
switch ((insn >> 28) & 0xf)
|
|
|
|
|
{
|
|
|
|
|
case 4:
|
|
|
|
|
/* bc[0-3][tf]l? and bc1any[24][ft] instructions can
|
|
|
|
|
have the condition reversed by tweaking a single
|
|
|
|
|
bit, and their opcodes all have 0x4???????. */
|
|
|
|
|
assert ((insn & 0xf1000000) == 0x41000000);
|
|
|
|
|
insn ^= 0x00010000;
|
|
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
case 0:
|
|
|
|
|
/* bltz 0x04000000 bgez 0x04010000
|
|
|
|
|
bltzal 0x04100000 bgezal 0x04110000 */
|
|
|
|
|
assert ((insn & 0xfc0e0000) == 0x04000000);
|
|
|
|
|
insn ^= 0x00010000;
|
|
|
|
|
break;
|
2002-11-30 09:39:46 +01:00
|
|
|
|
|
2002-10-12 07:23:33 +02:00
|
|
|
|
case 1:
|
|
|
|
|
/* beq 0x10000000 bne 0x14000000
|
|
|
|
|
blez 0x18000000 bgtz 0x1c000000 */
|
|
|
|
|
insn ^= 0x04000000;
|
|
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
default:
|
|
|
|
|
abort ();
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
if (RELAX_BRANCH_LINK (fragp->fr_subtype))
|
|
|
|
|
{
|
|
|
|
|
/* Clear the and-link bit. */
|
|
|
|
|
assert ((insn & 0xfc1c0000) == 0x04100000);
|
|
|
|
|
|
|
|
|
|
/* bltzal 0x04100000 bgezal 0x04110000
|
|
|
|
|
bltzall 0x04120000 bgezall 0x04130000 */
|
|
|
|
|
insn &= ~0x00100000;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/* Branch over the branch (if the branch was likely) or the
|
|
|
|
|
full jump (not likely case). Compute the offset from the
|
|
|
|
|
current instruction to branch to. */
|
|
|
|
|
if (RELAX_BRANCH_LIKELY (fragp->fr_subtype))
|
|
|
|
|
i = 16;
|
|
|
|
|
else
|
|
|
|
|
{
|
|
|
|
|
/* How many bytes in instructions we've already emitted? */
|
|
|
|
|
i = buf - (bfd_byte *)fragp->fr_literal - fragp->fr_fix;
|
|
|
|
|
/* How many bytes in instructions from here to the end? */
|
|
|
|
|
i = fragp->fr_var - i;
|
|
|
|
|
}
|
|
|
|
|
/* Convert to instruction count. */
|
|
|
|
|
i >>= 2;
|
|
|
|
|
/* Branch counts from the next instruction. */
|
2002-11-30 09:39:46 +01:00
|
|
|
|
i--;
|
2002-10-12 07:23:33 +02:00
|
|
|
|
insn |= i;
|
|
|
|
|
/* Branch over the jump. */
|
2003-06-30 14:44:25 +02:00
|
|
|
|
md_number_to_chars (buf, insn, 4);
|
2002-10-12 07:23:33 +02:00
|
|
|
|
buf += 4;
|
|
|
|
|
|
|
|
|
|
/* Nop */
|
2003-06-30 14:44:25 +02:00
|
|
|
|
md_number_to_chars (buf, 0, 4);
|
2002-10-12 07:23:33 +02:00
|
|
|
|
buf += 4;
|
|
|
|
|
|
|
|
|
|
if (RELAX_BRANCH_LIKELY (fragp->fr_subtype))
|
|
|
|
|
{
|
|
|
|
|
/* beql $0, $0, 2f */
|
|
|
|
|
insn = 0x50000000;
|
|
|
|
|
/* Compute the PC offset from the current instruction to
|
|
|
|
|
the end of the variable frag. */
|
|
|
|
|
/* How many bytes in instructions we've already emitted? */
|
|
|
|
|
i = buf - (bfd_byte *)fragp->fr_literal - fragp->fr_fix;
|
|
|
|
|
/* How many bytes in instructions from here to the end? */
|
|
|
|
|
i = fragp->fr_var - i;
|
|
|
|
|
/* Convert to instruction count. */
|
|
|
|
|
i >>= 2;
|
|
|
|
|
/* Don't decrement i, because we want to branch over the
|
|
|
|
|
delay slot. */
|
|
|
|
|
|
|
|
|
|
insn |= i;
|
2003-06-30 14:44:25 +02:00
|
|
|
|
md_number_to_chars (buf, insn, 4);
|
2002-10-12 07:23:33 +02:00
|
|
|
|
buf += 4;
|
|
|
|
|
|
2003-06-30 14:44:25 +02:00
|
|
|
|
md_number_to_chars (buf, 0, 4);
|
2002-10-12 07:23:33 +02:00
|
|
|
|
buf += 4;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
uncond:
|
|
|
|
|
if (mips_pic == NO_PIC)
|
|
|
|
|
{
|
|
|
|
|
/* j or jal. */
|
|
|
|
|
insn = (RELAX_BRANCH_LINK (fragp->fr_subtype)
|
|
|
|
|
? 0x0c000000 : 0x08000000);
|
|
|
|
|
exp.X_op = O_symbol;
|
|
|
|
|
exp.X_add_symbol = fragp->fr_symbol;
|
|
|
|
|
exp.X_add_number = fragp->fr_offset;
|
|
|
|
|
|
|
|
|
|
fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal,
|
|
|
|
|
4, &exp, 0, BFD_RELOC_MIPS_JMP);
|
|
|
|
|
fixp->fx_file = fragp->fr_file;
|
|
|
|
|
fixp->fx_line = fragp->fr_line;
|
|
|
|
|
|
2003-06-30 14:44:25 +02:00
|
|
|
|
md_number_to_chars (buf, insn, 4);
|
2002-10-12 07:23:33 +02:00
|
|
|
|
buf += 4;
|
|
|
|
|
}
|
|
|
|
|
else
|
|
|
|
|
{
|
|
|
|
|
/* lw/ld $at, <sym>($gp) R_MIPS_GOT16 */
|
|
|
|
|
insn = HAVE_64BIT_ADDRESSES ? 0xdf810000 : 0x8f810000;
|
|
|
|
|
exp.X_op = O_symbol;
|
|
|
|
|
exp.X_add_symbol = fragp->fr_symbol;
|
|
|
|
|
exp.X_add_number = fragp->fr_offset;
|
|
|
|
|
|
|
|
|
|
if (fragp->fr_offset)
|
|
|
|
|
{
|
|
|
|
|
exp.X_add_symbol = make_expr_symbol (&exp);
|
|
|
|
|
exp.X_add_number = 0;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal,
|
|
|
|
|
4, &exp, 0, BFD_RELOC_MIPS_GOT16);
|
|
|
|
|
fixp->fx_file = fragp->fr_file;
|
|
|
|
|
fixp->fx_line = fragp->fr_line;
|
|
|
|
|
|
2003-06-30 14:44:25 +02:00
|
|
|
|
md_number_to_chars (buf, insn, 4);
|
2002-10-12 07:23:33 +02:00
|
|
|
|
buf += 4;
|
2002-11-30 09:39:46 +01:00
|
|
|
|
|
2002-10-12 07:23:33 +02:00
|
|
|
|
if (mips_opts.isa == ISA_MIPS1)
|
|
|
|
|
{
|
|
|
|
|
/* nop */
|
2003-06-30 14:44:25 +02:00
|
|
|
|
md_number_to_chars (buf, 0, 4);
|
2002-10-12 07:23:33 +02:00
|
|
|
|
buf += 4;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/* d/addiu $at, $at, <sym> R_MIPS_LO16 */
|
|
|
|
|
insn = HAVE_64BIT_ADDRESSES ? 0x64210000 : 0x24210000;
|
|
|
|
|
|
|
|
|
|
fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal,
|
|
|
|
|
4, &exp, 0, BFD_RELOC_LO16);
|
|
|
|
|
fixp->fx_file = fragp->fr_file;
|
|
|
|
|
fixp->fx_line = fragp->fr_line;
|
2002-11-30 09:39:46 +01:00
|
|
|
|
|
2003-06-30 14:44:25 +02:00
|
|
|
|
md_number_to_chars (buf, insn, 4);
|
2002-10-12 07:23:33 +02:00
|
|
|
|
buf += 4;
|
|
|
|
|
|
|
|
|
|
/* j(al)r $at. */
|
|
|
|
|
if (RELAX_BRANCH_LINK (fragp->fr_subtype))
|
|
|
|
|
insn = 0x0020f809;
|
|
|
|
|
else
|
|
|
|
|
insn = 0x00200008;
|
|
|
|
|
|
2003-06-30 14:44:25 +02:00
|
|
|
|
md_number_to_chars (buf, insn, 4);
|
2002-10-12 07:23:33 +02:00
|
|
|
|
buf += 4;
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
assert (buf == (bfd_byte *)fragp->fr_literal
|
|
|
|
|
+ fragp->fr_fix + fragp->fr_var);
|
|
|
|
|
|
|
|
|
|
fragp->fr_fix += fragp->fr_var;
|
|
|
|
|
|
|
|
|
|
return;
|
|
|
|
|
}
|
|
|
|
|
|
1999-05-03 09:29:11 +02:00
|
|
|
|
if (RELAX_MIPS16_P (fragp->fr_subtype))
|
|
|
|
|
{
|
|
|
|
|
int type;
|
|
|
|
|
register const struct mips16_immed_operand *op;
|
2002-11-30 09:39:46 +01:00
|
|
|
|
bfd_boolean small, ext;
|
1999-05-03 09:29:11 +02:00
|
|
|
|
offsetT val;
|
|
|
|
|
bfd_byte *buf;
|
|
|
|
|
unsigned long insn;
|
2002-11-30 09:39:46 +01:00
|
|
|
|
bfd_boolean use_extend;
|
1999-05-03 09:29:11 +02:00
|
|
|
|
unsigned short extend;
|
|
|
|
|
|
|
|
|
|
type = RELAX_MIPS16_TYPE (fragp->fr_subtype);
|
|
|
|
|
op = mips16_immed_operands;
|
|
|
|
|
while (op->type != type)
|
|
|
|
|
++op;
|
|
|
|
|
|
|
|
|
|
if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype))
|
|
|
|
|
{
|
2002-11-30 09:39:46 +01:00
|
|
|
|
small = FALSE;
|
|
|
|
|
ext = TRUE;
|
1999-05-03 09:29:11 +02:00
|
|
|
|
}
|
|
|
|
|
else
|
|
|
|
|
{
|
2002-11-30 09:39:46 +01:00
|
|
|
|
small = TRUE;
|
|
|
|
|
ext = FALSE;
|
1999-05-03 09:29:11 +02:00
|
|
|
|
}
|
|
|
|
|
|
2001-05-22 12:23:50 +02:00
|
|
|
|
resolve_symbol_value (fragp->fr_symbol);
|
1999-05-03 09:29:11 +02:00
|
|
|
|
val = S_GET_VALUE (fragp->fr_symbol);
|
|
|
|
|
if (op->pcrel)
|
|
|
|
|
{
|
|
|
|
|
addressT addr;
|
|
|
|
|
|
|
|
|
|
addr = fragp->fr_address + fragp->fr_fix;
|
|
|
|
|
|
|
|
|
|
/* The rules for the base address of a PC relative reloc are
|
|
|
|
|
complicated; see mips16_extended_frag. */
|
|
|
|
|
if (type == 'p' || type == 'q')
|
|
|
|
|
{
|
|
|
|
|
addr += 2;
|
|
|
|
|
if (ext)
|
|
|
|
|
addr += 2;
|
|
|
|
|
/* Ignore the low bit in the target, since it will be
|
|
|
|
|
set for a text label. */
|
|
|
|
|
if ((val & 1) != 0)
|
|
|
|
|
--val;
|
|
|
|
|
}
|
|
|
|
|
else if (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype))
|
|
|
|
|
addr -= 4;
|
|
|
|
|
else if (RELAX_MIPS16_DSLOT (fragp->fr_subtype))
|
|
|
|
|
addr -= 2;
|
|
|
|
|
|
|
|
|
|
addr &= ~ (addressT) ((1 << op->shift) - 1);
|
|
|
|
|
val -= addr;
|
|
|
|
|
|
|
|
|
|
/* Make sure the section winds up with the alignment we have
|
|
|
|
|
assumed. */
|
|
|
|
|
if (op->shift > 0)
|
|
|
|
|
record_alignment (asec, op->shift);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
if (ext
|
|
|
|
|
&& (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype)
|
|
|
|
|
|| RELAX_MIPS16_DSLOT (fragp->fr_subtype)))
|
|
|
|
|
as_warn_where (fragp->fr_file, fragp->fr_line,
|
|
|
|
|
_("extended instruction in delay slot"));
|
|
|
|
|
|
|
|
|
|
buf = (bfd_byte *) (fragp->fr_literal + fragp->fr_fix);
|
|
|
|
|
|
|
|
|
|
if (target_big_endian)
|
|
|
|
|
insn = bfd_getb16 (buf);
|
|
|
|
|
else
|
|
|
|
|
insn = bfd_getl16 (buf);
|
|
|
|
|
|
|
|
|
|
mips16_immed (fragp->fr_file, fragp->fr_line, type, val,
|
|
|
|
|
RELAX_MIPS16_USER_EXT (fragp->fr_subtype),
|
|
|
|
|
small, ext, &insn, &use_extend, &extend);
|
|
|
|
|
|
|
|
|
|
if (use_extend)
|
|
|
|
|
{
|
2003-06-30 14:44:25 +02:00
|
|
|
|
md_number_to_chars (buf, 0xf000 | extend, 2);
|
1999-05-03 09:29:11 +02:00
|
|
|
|
fragp->fr_fix += 2;
|
|
|
|
|
buf += 2;
|
|
|
|
|
}
|
|
|
|
|
|
2003-06-30 14:44:25 +02:00
|
|
|
|
md_number_to_chars (buf, insn, 2);
|
1999-05-03 09:29:11 +02:00
|
|
|
|
fragp->fr_fix += 2;
|
|
|
|
|
buf += 2;
|
|
|
|
|
}
|
|
|
|
|
else
|
|
|
|
|
{
|
|
|
|
|
if (fragp->fr_opcode == NULL)
|
|
|
|
|
return;
|
|
|
|
|
|
|
|
|
|
old = RELAX_OLD (fragp->fr_subtype);
|
|
|
|
|
new = RELAX_NEW (fragp->fr_subtype);
|
|
|
|
|
fixptr = fragp->fr_literal + fragp->fr_fix;
|
|
|
|
|
|
|
|
|
|
if (new > 0)
|
* config/tc-mips.h (tc_frag_data_type, TC_FRAG_TYPE): New.
* config/tc-mips.c: Use signed add for n32 address arithmetic.
(append_insn): When filling delay slots with instructions
that have fixups that tc_gen_reloc might consider modifyable
in variant frags, start a new frag.
(load_address): Generate GOT_DISP with of without offset
depending on whether symbol is local. For -xgot, use
GOT_PAGE/GOT_OFST or GOT_HI16/GOT_LO16.
(macro) <M_DLA_AB, M_LA_AB>: Likewise.
<M_JAL_A>: In NewABI, use CALL16 or GOT_DISP for small got,
CALL_HI16/CALL_LO16 or GOT_PAGE/GOT_OFST for big got.
<ld_st>: In NewABI with small got, always use
GOT_PAGE/GOT_OFST, with the latter in the load/store
instruction. With big got, use GOT_HI16/GOT_LO16 or
GOT_PAGE/GOT_OFST.
(tc_gen_reloc): Adjust variant frags with GOT_DISP in NewABI.
Add tc_frag_data.tc_fr_offset to addends. Decay CALL16,
GOT_OFST and GOT_DISP to GOT_DISP in NewABI.
(md_convert_frag): Use memmove for safe copying of overlapping
regions.
2003-04-11 03:56:50 +02:00
|
|
|
|
memmove (fixptr - old, fixptr, new);
|
1999-05-03 09:29:11 +02:00
|
|
|
|
|
|
|
|
|
fragp->fr_fix += new - old;
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
#ifdef OBJ_ELF
|
|
|
|
|
|
|
|
|
|
/* This function is called after the relocs have been generated.
|
|
|
|
|
We've been storing mips16 text labels as odd. Here we convert them
|
|
|
|
|
back to even for the convenience of the debugger. */
|
|
|
|
|
|
|
|
|
|
void
|
2003-06-30 14:44:25 +02:00
|
|
|
|
mips_frob_file_after_relocs (void)
|
1999-05-03 09:29:11 +02:00
|
|
|
|
{
|
|
|
|
|
asymbol **syms;
|
|
|
|
|
unsigned int count, i;
|
|
|
|
|
|
|
|
|
|
if (OUTPUT_FLAVOR != bfd_target_elf_flavour)
|
|
|
|
|
return;
|
|
|
|
|
|
|
|
|
|
syms = bfd_get_outsymbols (stdoutput);
|
|
|
|
|
count = bfd_get_symcount (stdoutput);
|
|
|
|
|
for (i = 0; i < count; i++, syms++)
|
|
|
|
|
{
|
|
|
|
|
if (elf_symbol (*syms)->internal_elf_sym.st_other == STO_MIPS16
|
|
|
|
|
&& ((*syms)->value & 1) != 0)
|
|
|
|
|
{
|
|
|
|
|
(*syms)->value &= ~1;
|
|
|
|
|
/* If the symbol has an odd size, it was probably computed
|
|
|
|
|
incorrectly, so adjust that as well. */
|
|
|
|
|
if ((elf_symbol (*syms)->internal_elf_sym.st_size & 1) != 0)
|
|
|
|
|
++elf_symbol (*syms)->internal_elf_sym.st_size;
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
#endif
|
|
|
|
|
|
|
|
|
|
/* This function is called whenever a label is defined. It is used
|
|
|
|
|
when handling branch delays; if a branch has a label, we assume we
|
|
|
|
|
can not move it. */
|
|
|
|
|
|
|
|
|
|
void
|
2003-06-30 14:44:25 +02:00
|
|
|
|
mips_define_label (symbolS *sym)
|
1999-05-03 09:29:11 +02:00
|
|
|
|
{
|
|
|
|
|
struct insn_label_list *l;
|
|
|
|
|
|
|
|
|
|
if (free_insn_labels == NULL)
|
|
|
|
|
l = (struct insn_label_list *) xmalloc (sizeof *l);
|
|
|
|
|
else
|
|
|
|
|
{
|
|
|
|
|
l = free_insn_labels;
|
|
|
|
|
free_insn_labels = l->next;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
l->label = sym;
|
|
|
|
|
l->next = insn_labels;
|
|
|
|
|
insn_labels = l;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
|
|
|
|
|
|
|
|
|
|
/* Some special processing for a MIPS ELF file. */
|
|
|
|
|
|
|
|
|
|
void
|
2003-06-30 14:44:25 +02:00
|
|
|
|
mips_elf_final_processing (void)
|
1999-05-03 09:29:11 +02:00
|
|
|
|
{
|
|
|
|
|
/* Write out the register information. */
|
[gas/]
* doc/c-mips.texi: Remove -mcpu. Document -mabi.
* configure.in (MIPS_CPU_STRING_DEFAULT): New configuration macro.
(USE_E_MIPS_ABI_O32, MIPS_DEFAULT_64BIT): New configuration macros.
* configure, config.in: Regenerate.
* config/tc-mips.c (file_mips_abi): Rename to mips_abi.
(mips_set_options): Remove "abi" field.
(mips_opts): Update accordingly. Replace all uses of mips_opts.abi
with mips_abi.
(mips_cpu): Remove.
(mips_arch_string, mips_arch_info): New vars.
(mips_tune_string, mips_tune_info): New vars.
(ABI_NEEDS_32BIT_REGS, ABI_NEEDS_64BIT_REGS): New macros.
(HAVE_32BIT_GPRS, HAVE_32BIT_FPRS): Don't check the ABI.
(mips_isa_to_str, mips_cpu_to_str): Remove.
(mips_ip): If the selected architecture is a generic ISA rather
than a processor, only mention the ISA level in error messages.
(OPTION_MCPU): Remove.
(OPTION_FP64): New.
(md_longopts): Add -mfp64, remove -mcpu.
(mips_set_option_string): New fn.
(md_parse_option): Make -mipsN update file_mips_isa rather than
mips_opts.isa. Use mips_set_option_string to set -march or -mtune.
Don't let -mgp32 and -mfp32 change the ABI.
(show): Move to end of file. Constify string argument.
(md_show_usage): Move to the end of the file. Read available
architectures from mips_cpu_info_table.
(mips_set_architecture): New fn.
(mips_after_parse_args): Rework. Remove -mcpu handling. -mipsN
is an alias for -march=mipsN. Don't change the ABI based on other
flags. Infer the register size from the ABI as well as the
architecture. Complain about more conflicting arguments.
Unify logic with GCC.
(s_mipsset): Don't change the ABI.
(mips_elf_final_processing): Check USE_E_MIPS_ABI_O32.
(mips_cpu_info_table): Remove Generic-MIPS* entries, keeping just
"mipsN"-type entries. Remove entries that vary only in the
manufacturer's prefix, or that have "000" replaced by "k".
Remove TARGET_CPU entries. Make r2000 entry use CPU_R3000.
(mips_strict_matching_cpu_name_p, mips_matching_cpu_name_p): New fns.
(mips_parse_cpu): New fn.
(mips_cpu_info_from_name, mips_cpu_info_from_cpu): Remove.
(mips_cpu_info_from_isa): Minor formatting tweak.
[gas/testsuite]
* gas/mips/mips-gp32-fp64.d,
* gas/mips/mips-gp32-fp64-pic.d: Add -mfp64.
2002-07-25 11:48:07 +02:00
|
|
|
|
if (mips_abi != N64_ABI)
|
1999-05-03 09:29:11 +02:00
|
|
|
|
{
|
|
|
|
|
Elf32_RegInfo s;
|
|
|
|
|
|
|
|
|
|
s.ri_gprmask = mips_gprmask;
|
|
|
|
|
s.ri_cprmask[0] = mips_cprmask[0];
|
|
|
|
|
s.ri_cprmask[1] = mips_cprmask[1];
|
|
|
|
|
s.ri_cprmask[2] = mips_cprmask[2];
|
|
|
|
|
s.ri_cprmask[3] = mips_cprmask[3];
|
|
|
|
|
/* The gp_value field is set by the MIPS ELF backend. */
|
|
|
|
|
|
|
|
|
|
bfd_mips_elf32_swap_reginfo_out (stdoutput, &s,
|
|
|
|
|
((Elf32_External_RegInfo *)
|
|
|
|
|
mips_regmask_frag));
|
|
|
|
|
}
|
|
|
|
|
else
|
|
|
|
|
{
|
|
|
|
|
Elf64_Internal_RegInfo s;
|
|
|
|
|
|
|
|
|
|
s.ri_gprmask = mips_gprmask;
|
|
|
|
|
s.ri_pad = 0;
|
|
|
|
|
s.ri_cprmask[0] = mips_cprmask[0];
|
|
|
|
|
s.ri_cprmask[1] = mips_cprmask[1];
|
|
|
|
|
s.ri_cprmask[2] = mips_cprmask[2];
|
|
|
|
|
s.ri_cprmask[3] = mips_cprmask[3];
|
|
|
|
|
/* The gp_value field is set by the MIPS ELF backend. */
|
|
|
|
|
|
|
|
|
|
bfd_mips_elf64_swap_reginfo_out (stdoutput, &s,
|
|
|
|
|
((Elf64_External_RegInfo *)
|
|
|
|
|
mips_regmask_frag));
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/* Set the MIPS ELF flag bits. FIXME: There should probably be some
|
|
|
|
|
sort of BFD interface for this. */
|
|
|
|
|
if (mips_any_noreorder)
|
|
|
|
|
elf_elfheader (stdoutput)->e_flags |= EF_MIPS_NOREORDER;
|
|
|
|
|
if (mips_pic != NO_PIC)
|
2003-05-21 23:53:33 +02:00
|
|
|
|
{
|
1999-05-03 09:29:11 +02:00
|
|
|
|
elf_elfheader (stdoutput)->e_flags |= EF_MIPS_PIC;
|
2003-05-21 23:53:33 +02:00
|
|
|
|
elf_elfheader (stdoutput)->e_flags |= EF_MIPS_CPIC;
|
|
|
|
|
}
|
|
|
|
|
if (mips_abicalls)
|
|
|
|
|
elf_elfheader (stdoutput)->e_flags |= EF_MIPS_CPIC;
|
1999-05-03 09:29:11 +02:00
|
|
|
|
|
2002-05-04 19:38:00 +02:00
|
|
|
|
/* Set MIPS ELF flags for ASEs. */
|
2002-06-08 01:26:54 +02:00
|
|
|
|
if (file_ase_mips16)
|
|
|
|
|
elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ARCH_ASE_M16;
|
2002-03-16 04:09:19 +01:00
|
|
|
|
#if 0 /* XXX FIXME */
|
|
|
|
|
if (file_ase_mips3d)
|
|
|
|
|
elf_elfheader (stdoutput)->e_flags |= ???;
|
|
|
|
|
#endif
|
[ gas/ChangeLog ]
2002-05-30 Chris G. Demetriou <cgd@broadcom.com>
Ed Satterthwaite <ehs@broadcom.com>
* config/tc-mips.c (mips_set_options): New "ase_mdmx" member.
(mips_opts): Initialize "ase_mdmx" member.
(file_ase_mdmx): New variable.
(CPU_HAS_MDMX): New macro.
(md_begin): Initialize mips_opts.ase_mdmx and file_ase_mdmx
based on command line options and configuration defaults.
(macro_build): Note in comment that use of MDMX in macros is
not currently allowed.
(validate_mips_insn): Add support for the "O", "Q", "X", "Y", and
"Z" MDMX operand types.
(mips_ip): Accept MDMX instructions if mips_opts.ase_mdmx is set,
and add support for the "O", "Q", "X", "Y", and "Z" MDMX operand
types.
(OPTION_MDMX, OPTION_NO_MDMX, md_longopts, md_parse_option):
Add support for "-mdmx" and "-no-mdmx" options.
(OPTION_ELF_BASE): Move to accomodate new options.
(s_mipsset): Support ".set mdmx" and ".set nomdmx".
(mips_elf_final_processing): Set MDMX ASE ELF header flag if
file_ase_mdmx was set.
* doc/as.texinfo: Document -mdmx and -no-mdmx options.
* doc/c-mips.texi: Likewise, and document ".set mdmx" and ".set
nomdmx" directives.
[ gas/testsuite/ChangeLog ]
2002-05-30 Chris G. Demetriou <cgd@broadcom.com>
* gas/mips/mips64-mdmx.s: New file.
* gas/mips/mips64-mdmx.d: Likewise.
* gas/mips/mips.exp: Run new "mips64-mdmx" test.
[ include/opcode/ChangeLog ]
2002-05-30 Chris G. Demetriou <cgd@broadcom.com>
* mips.h (OP_SH_ALN, OP_MASK_ALN, OP_SH_VSEL, OP_MASK_VSEL)
(MDMX_FMTSEL_IMM_QH, MDMX_FMTSEL_IMM_OB, MDMX_FMTSEL_VEC_QH)
(MDMX_FMTSEL_VEC_OB, INSN_READ_MDMX_ACC, INSN_WRITE_MDMX_ACC)
(INSN_MDMX): New constants, for MDMX support.
(opcode character list): Add "O", "Q", "X", "Y", and "Z" for MDMX.
[ opcodes/ChangeLog ]
2002-05-30 Chris G. Demetriou <cgd@broadcom.com>
Ed Satterthwaite <ehs@broadcom.com>
* mips-dis.c (print_insn_arg): Add support for 'O', 'Q', 'X', 'Y',
and 'Z' formats, for MDMX.
(mips_isa_type): Add MDMX instructions to the ISA
bit mask for bfd_mach_mipsisa64.
* mips-opc.c: Add support for MDMX instructions.
(MX): New definition.
* mips-dis.c: Update copyright years to include 2002.
2002-05-31 03:17:18 +02:00
|
|
|
|
if (file_ase_mdmx)
|
|
|
|
|
elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ARCH_ASE_MDMX;
|
2002-03-16 04:09:19 +01:00
|
|
|
|
|
2000-09-07 14:45:56 +02:00
|
|
|
|
/* Set the MIPS ELF ABI flags. */
|
[gas/]
* doc/c-mips.texi: Remove -mcpu. Document -mabi.
* configure.in (MIPS_CPU_STRING_DEFAULT): New configuration macro.
(USE_E_MIPS_ABI_O32, MIPS_DEFAULT_64BIT): New configuration macros.
* configure, config.in: Regenerate.
* config/tc-mips.c (file_mips_abi): Rename to mips_abi.
(mips_set_options): Remove "abi" field.
(mips_opts): Update accordingly. Replace all uses of mips_opts.abi
with mips_abi.
(mips_cpu): Remove.
(mips_arch_string, mips_arch_info): New vars.
(mips_tune_string, mips_tune_info): New vars.
(ABI_NEEDS_32BIT_REGS, ABI_NEEDS_64BIT_REGS): New macros.
(HAVE_32BIT_GPRS, HAVE_32BIT_FPRS): Don't check the ABI.
(mips_isa_to_str, mips_cpu_to_str): Remove.
(mips_ip): If the selected architecture is a generic ISA rather
than a processor, only mention the ISA level in error messages.
(OPTION_MCPU): Remove.
(OPTION_FP64): New.
(md_longopts): Add -mfp64, remove -mcpu.
(mips_set_option_string): New fn.
(md_parse_option): Make -mipsN update file_mips_isa rather than
mips_opts.isa. Use mips_set_option_string to set -march or -mtune.
Don't let -mgp32 and -mfp32 change the ABI.
(show): Move to end of file. Constify string argument.
(md_show_usage): Move to the end of the file. Read available
architectures from mips_cpu_info_table.
(mips_set_architecture): New fn.
(mips_after_parse_args): Rework. Remove -mcpu handling. -mipsN
is an alias for -march=mipsN. Don't change the ABI based on other
flags. Infer the register size from the ABI as well as the
architecture. Complain about more conflicting arguments.
Unify logic with GCC.
(s_mipsset): Don't change the ABI.
(mips_elf_final_processing): Check USE_E_MIPS_ABI_O32.
(mips_cpu_info_table): Remove Generic-MIPS* entries, keeping just
"mipsN"-type entries. Remove entries that vary only in the
manufacturer's prefix, or that have "000" replaced by "k".
Remove TARGET_CPU entries. Make r2000 entry use CPU_R3000.
(mips_strict_matching_cpu_name_p, mips_matching_cpu_name_p): New fns.
(mips_parse_cpu): New fn.
(mips_cpu_info_from_name, mips_cpu_info_from_cpu): Remove.
(mips_cpu_info_from_isa): Minor formatting tweak.
[gas/testsuite]
* gas/mips/mips-gp32-fp64.d,
* gas/mips/mips-gp32-fp64-pic.d: Add -mfp64.
2002-07-25 11:48:07 +02:00
|
|
|
|
if (mips_abi == O32_ABI && USE_E_MIPS_ABI_O32)
|
1999-05-03 09:29:11 +02:00
|
|
|
|
elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_O32;
|
[gas/]
* doc/c-mips.texi: Remove -mcpu. Document -mabi.
* configure.in (MIPS_CPU_STRING_DEFAULT): New configuration macro.
(USE_E_MIPS_ABI_O32, MIPS_DEFAULT_64BIT): New configuration macros.
* configure, config.in: Regenerate.
* config/tc-mips.c (file_mips_abi): Rename to mips_abi.
(mips_set_options): Remove "abi" field.
(mips_opts): Update accordingly. Replace all uses of mips_opts.abi
with mips_abi.
(mips_cpu): Remove.
(mips_arch_string, mips_arch_info): New vars.
(mips_tune_string, mips_tune_info): New vars.
(ABI_NEEDS_32BIT_REGS, ABI_NEEDS_64BIT_REGS): New macros.
(HAVE_32BIT_GPRS, HAVE_32BIT_FPRS): Don't check the ABI.
(mips_isa_to_str, mips_cpu_to_str): Remove.
(mips_ip): If the selected architecture is a generic ISA rather
than a processor, only mention the ISA level in error messages.
(OPTION_MCPU): Remove.
(OPTION_FP64): New.
(md_longopts): Add -mfp64, remove -mcpu.
(mips_set_option_string): New fn.
(md_parse_option): Make -mipsN update file_mips_isa rather than
mips_opts.isa. Use mips_set_option_string to set -march or -mtune.
Don't let -mgp32 and -mfp32 change the ABI.
(show): Move to end of file. Constify string argument.
(md_show_usage): Move to the end of the file. Read available
architectures from mips_cpu_info_table.
(mips_set_architecture): New fn.
(mips_after_parse_args): Rework. Remove -mcpu handling. -mipsN
is an alias for -march=mipsN. Don't change the ABI based on other
flags. Infer the register size from the ABI as well as the
architecture. Complain about more conflicting arguments.
Unify logic with GCC.
(s_mipsset): Don't change the ABI.
(mips_elf_final_processing): Check USE_E_MIPS_ABI_O32.
(mips_cpu_info_table): Remove Generic-MIPS* entries, keeping just
"mipsN"-type entries. Remove entries that vary only in the
manufacturer's prefix, or that have "000" replaced by "k".
Remove TARGET_CPU entries. Make r2000 entry use CPU_R3000.
(mips_strict_matching_cpu_name_p, mips_matching_cpu_name_p): New fns.
(mips_parse_cpu): New fn.
(mips_cpu_info_from_name, mips_cpu_info_from_cpu): Remove.
(mips_cpu_info_from_isa): Minor formatting tweak.
[gas/testsuite]
* gas/mips/mips-gp32-fp64.d,
* gas/mips/mips-gp32-fp64-pic.d: Add -mfp64.
2002-07-25 11:48:07 +02:00
|
|
|
|
else if (mips_abi == O64_ABI)
|
1999-05-03 09:29:11 +02:00
|
|
|
|
elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_O64;
|
[gas/]
* doc/c-mips.texi: Remove -mcpu. Document -mabi.
* configure.in (MIPS_CPU_STRING_DEFAULT): New configuration macro.
(USE_E_MIPS_ABI_O32, MIPS_DEFAULT_64BIT): New configuration macros.
* configure, config.in: Regenerate.
* config/tc-mips.c (file_mips_abi): Rename to mips_abi.
(mips_set_options): Remove "abi" field.
(mips_opts): Update accordingly. Replace all uses of mips_opts.abi
with mips_abi.
(mips_cpu): Remove.
(mips_arch_string, mips_arch_info): New vars.
(mips_tune_string, mips_tune_info): New vars.
(ABI_NEEDS_32BIT_REGS, ABI_NEEDS_64BIT_REGS): New macros.
(HAVE_32BIT_GPRS, HAVE_32BIT_FPRS): Don't check the ABI.
(mips_isa_to_str, mips_cpu_to_str): Remove.
(mips_ip): If the selected architecture is a generic ISA rather
than a processor, only mention the ISA level in error messages.
(OPTION_MCPU): Remove.
(OPTION_FP64): New.
(md_longopts): Add -mfp64, remove -mcpu.
(mips_set_option_string): New fn.
(md_parse_option): Make -mipsN update file_mips_isa rather than
mips_opts.isa. Use mips_set_option_string to set -march or -mtune.
Don't let -mgp32 and -mfp32 change the ABI.
(show): Move to end of file. Constify string argument.
(md_show_usage): Move to the end of the file. Read available
architectures from mips_cpu_info_table.
(mips_set_architecture): New fn.
(mips_after_parse_args): Rework. Remove -mcpu handling. -mipsN
is an alias for -march=mipsN. Don't change the ABI based on other
flags. Infer the register size from the ABI as well as the
architecture. Complain about more conflicting arguments.
Unify logic with GCC.
(s_mipsset): Don't change the ABI.
(mips_elf_final_processing): Check USE_E_MIPS_ABI_O32.
(mips_cpu_info_table): Remove Generic-MIPS* entries, keeping just
"mipsN"-type entries. Remove entries that vary only in the
manufacturer's prefix, or that have "000" replaced by "k".
Remove TARGET_CPU entries. Make r2000 entry use CPU_R3000.
(mips_strict_matching_cpu_name_p, mips_matching_cpu_name_p): New fns.
(mips_parse_cpu): New fn.
(mips_cpu_info_from_name, mips_cpu_info_from_cpu): Remove.
(mips_cpu_info_from_isa): Minor formatting tweak.
[gas/testsuite]
* gas/mips/mips-gp32-fp64.d,
* gas/mips/mips-gp32-fp64-pic.d: Add -mfp64.
2002-07-25 11:48:07 +02:00
|
|
|
|
else if (mips_abi == EABI_ABI)
|
1999-05-03 09:29:11 +02:00
|
|
|
|
{
|
[gas/]
* doc/c-mips.texi: Remove -mcpu. Document -mabi.
* configure.in (MIPS_CPU_STRING_DEFAULT): New configuration macro.
(USE_E_MIPS_ABI_O32, MIPS_DEFAULT_64BIT): New configuration macros.
* configure, config.in: Regenerate.
* config/tc-mips.c (file_mips_abi): Rename to mips_abi.
(mips_set_options): Remove "abi" field.
(mips_opts): Update accordingly. Replace all uses of mips_opts.abi
with mips_abi.
(mips_cpu): Remove.
(mips_arch_string, mips_arch_info): New vars.
(mips_tune_string, mips_tune_info): New vars.
(ABI_NEEDS_32BIT_REGS, ABI_NEEDS_64BIT_REGS): New macros.
(HAVE_32BIT_GPRS, HAVE_32BIT_FPRS): Don't check the ABI.
(mips_isa_to_str, mips_cpu_to_str): Remove.
(mips_ip): If the selected architecture is a generic ISA rather
than a processor, only mention the ISA level in error messages.
(OPTION_MCPU): Remove.
(OPTION_FP64): New.
(md_longopts): Add -mfp64, remove -mcpu.
(mips_set_option_string): New fn.
(md_parse_option): Make -mipsN update file_mips_isa rather than
mips_opts.isa. Use mips_set_option_string to set -march or -mtune.
Don't let -mgp32 and -mfp32 change the ABI.
(show): Move to end of file. Constify string argument.
(md_show_usage): Move to the end of the file. Read available
architectures from mips_cpu_info_table.
(mips_set_architecture): New fn.
(mips_after_parse_args): Rework. Remove -mcpu handling. -mipsN
is an alias for -march=mipsN. Don't change the ABI based on other
flags. Infer the register size from the ABI as well as the
architecture. Complain about more conflicting arguments.
Unify logic with GCC.
(s_mipsset): Don't change the ABI.
(mips_elf_final_processing): Check USE_E_MIPS_ABI_O32.
(mips_cpu_info_table): Remove Generic-MIPS* entries, keeping just
"mipsN"-type entries. Remove entries that vary only in the
manufacturer's prefix, or that have "000" replaced by "k".
Remove TARGET_CPU entries. Make r2000 entry use CPU_R3000.
(mips_strict_matching_cpu_name_p, mips_matching_cpu_name_p): New fns.
(mips_parse_cpu): New fn.
(mips_cpu_info_from_name, mips_cpu_info_from_cpu): Remove.
(mips_cpu_info_from_isa): Minor formatting tweak.
[gas/testsuite]
* gas/mips/mips-gp32-fp64.d,
* gas/mips/mips-gp32-fp64-pic.d: Add -mfp64.
2002-07-25 11:48:07 +02:00
|
|
|
|
if (!file_mips_gp32)
|
1999-05-03 09:29:11 +02:00
|
|
|
|
elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_EABI64;
|
|
|
|
|
else
|
|
|
|
|
elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_EABI32;
|
|
|
|
|
}
|
[gas/]
* doc/c-mips.texi: Remove -mcpu. Document -mabi.
* configure.in (MIPS_CPU_STRING_DEFAULT): New configuration macro.
(USE_E_MIPS_ABI_O32, MIPS_DEFAULT_64BIT): New configuration macros.
* configure, config.in: Regenerate.
* config/tc-mips.c (file_mips_abi): Rename to mips_abi.
(mips_set_options): Remove "abi" field.
(mips_opts): Update accordingly. Replace all uses of mips_opts.abi
with mips_abi.
(mips_cpu): Remove.
(mips_arch_string, mips_arch_info): New vars.
(mips_tune_string, mips_tune_info): New vars.
(ABI_NEEDS_32BIT_REGS, ABI_NEEDS_64BIT_REGS): New macros.
(HAVE_32BIT_GPRS, HAVE_32BIT_FPRS): Don't check the ABI.
(mips_isa_to_str, mips_cpu_to_str): Remove.
(mips_ip): If the selected architecture is a generic ISA rather
than a processor, only mention the ISA level in error messages.
(OPTION_MCPU): Remove.
(OPTION_FP64): New.
(md_longopts): Add -mfp64, remove -mcpu.
(mips_set_option_string): New fn.
(md_parse_option): Make -mipsN update file_mips_isa rather than
mips_opts.isa. Use mips_set_option_string to set -march or -mtune.
Don't let -mgp32 and -mfp32 change the ABI.
(show): Move to end of file. Constify string argument.
(md_show_usage): Move to the end of the file. Read available
architectures from mips_cpu_info_table.
(mips_set_architecture): New fn.
(mips_after_parse_args): Rework. Remove -mcpu handling. -mipsN
is an alias for -march=mipsN. Don't change the ABI based on other
flags. Infer the register size from the ABI as well as the
architecture. Complain about more conflicting arguments.
Unify logic with GCC.
(s_mipsset): Don't change the ABI.
(mips_elf_final_processing): Check USE_E_MIPS_ABI_O32.
(mips_cpu_info_table): Remove Generic-MIPS* entries, keeping just
"mipsN"-type entries. Remove entries that vary only in the
manufacturer's prefix, or that have "000" replaced by "k".
Remove TARGET_CPU entries. Make r2000 entry use CPU_R3000.
(mips_strict_matching_cpu_name_p, mips_matching_cpu_name_p): New fns.
(mips_parse_cpu): New fn.
(mips_cpu_info_from_name, mips_cpu_info_from_cpu): Remove.
(mips_cpu_info_from_isa): Minor formatting tweak.
[gas/testsuite]
* gas/mips/mips-gp32-fp64.d,
* gas/mips/mips-gp32-fp64-pic.d: Add -mfp64.
2002-07-25 11:48:07 +02:00
|
|
|
|
else if (mips_abi == N32_ABI)
|
2001-08-16 23:48:28 +02:00
|
|
|
|
elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ABI2;
|
|
|
|
|
|
2002-05-28 21:23:09 +02:00
|
|
|
|
/* Nothing to do for N64_ABI. */
|
1999-05-03 09:29:11 +02:00
|
|
|
|
|
|
|
|
|
if (mips_32bitmode)
|
|
|
|
|
elf_elfheader (stdoutput)->e_flags |= EF_MIPS_32BITMODE;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
#endif /* OBJ_ELF || OBJ_MAYBE_ELF */
|
|
|
|
|
|
2000-12-05 19:51:08 +01:00
|
|
|
|
typedef struct proc {
|
|
|
|
|
symbolS *isym;
|
|
|
|
|
unsigned long reg_mask;
|
|
|
|
|
unsigned long reg_offset;
|
|
|
|
|
unsigned long fpreg_mask;
|
|
|
|
|
unsigned long fpreg_offset;
|
|
|
|
|
unsigned long frame_offset;
|
|
|
|
|
unsigned long frame_reg;
|
|
|
|
|
unsigned long pc_reg;
|
|
|
|
|
} procS;
|
1999-05-03 09:29:11 +02:00
|
|
|
|
|
|
|
|
|
static procS cur_proc;
|
|
|
|
|
static procS *cur_proc_ptr;
|
|
|
|
|
static int numprocs;
|
|
|
|
|
|
2000-12-28 11:07:56 +01:00
|
|
|
|
/* Fill in an rs_align_code fragment. */
|
2000-01-14 18:58:29 +01:00
|
|
|
|
|
2000-12-28 11:07:56 +01:00
|
|
|
|
void
|
2003-06-30 14:44:25 +02:00
|
|
|
|
mips_handle_align (fragS *fragp)
|
2000-01-14 18:58:29 +01:00
|
|
|
|
{
|
2000-12-28 11:07:56 +01:00
|
|
|
|
if (fragp->fr_type != rs_align_code)
|
|
|
|
|
return;
|
|
|
|
|
|
|
|
|
|
if (mips_opts.mips16)
|
2000-01-14 18:58:29 +01:00
|
|
|
|
{
|
|
|
|
|
static const unsigned char be_nop[] = { 0x65, 0x00 };
|
|
|
|
|
static const unsigned char le_nop[] = { 0x00, 0x65 };
|
|
|
|
|
|
2000-12-28 11:07:56 +01:00
|
|
|
|
int bytes;
|
|
|
|
|
char *p;
|
2000-01-14 18:58:29 +01:00
|
|
|
|
|
2000-12-28 11:07:56 +01:00
|
|
|
|
bytes = fragp->fr_next->fr_address - fragp->fr_address - fragp->fr_fix;
|
|
|
|
|
p = fragp->fr_literal + fragp->fr_fix;
|
|
|
|
|
|
|
|
|
|
if (bytes & 1)
|
|
|
|
|
{
|
|
|
|
|
*p++ = 0;
|
2002-05-26 20:46:37 +02:00
|
|
|
|
fragp->fr_fix++;
|
2000-12-28 11:07:56 +01:00
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
memcpy (p, (target_big_endian ? be_nop : le_nop), 2);
|
|
|
|
|
fragp->fr_var = 2;
|
2000-01-14 18:58:29 +01:00
|
|
|
|
}
|
|
|
|
|
|
2000-12-28 11:07:56 +01:00
|
|
|
|
/* For mips32, a nop is a zero, which we trivially get by doing nothing. */
|
2000-01-14 18:58:29 +01:00
|
|
|
|
}
|
|
|
|
|
|
1999-05-03 09:29:11 +02:00
|
|
|
|
static void
|
2003-06-30 14:44:25 +02:00
|
|
|
|
md_obj_begin (void)
|
1999-05-03 09:29:11 +02:00
|
|
|
|
{
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static void
|
2003-06-30 14:44:25 +02:00
|
|
|
|
md_obj_end (void)
|
1999-05-03 09:29:11 +02:00
|
|
|
|
{
|
|
|
|
|
/* check for premature end, nesting errors, etc */
|
|
|
|
|
if (cur_proc_ptr)
|
2001-08-07 15:15:26 +02:00
|
|
|
|
as_warn (_("missing .end at end of assembly"));
|
1999-05-03 09:29:11 +02:00
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static long
|
2003-06-30 14:44:25 +02:00
|
|
|
|
get_number (void)
|
1999-05-03 09:29:11 +02:00
|
|
|
|
{
|
|
|
|
|
int negative = 0;
|
|
|
|
|
long val = 0;
|
|
|
|
|
|
|
|
|
|
if (*input_line_pointer == '-')
|
|
|
|
|
{
|
|
|
|
|
++input_line_pointer;
|
|
|
|
|
negative = 1;
|
|
|
|
|
}
|
2001-09-19 07:33:36 +02:00
|
|
|
|
if (!ISDIGIT (*input_line_pointer))
|
2001-12-04 15:38:48 +01:00
|
|
|
|
as_bad (_("expected simple number"));
|
1999-05-03 09:29:11 +02:00
|
|
|
|
if (input_line_pointer[0] == '0')
|
|
|
|
|
{
|
|
|
|
|
if (input_line_pointer[1] == 'x')
|
|
|
|
|
{
|
|
|
|
|
input_line_pointer += 2;
|
2001-09-19 07:33:36 +02:00
|
|
|
|
while (ISXDIGIT (*input_line_pointer))
|
1999-05-03 09:29:11 +02:00
|
|
|
|
{
|
|
|
|
|
val <<= 4;
|
|
|
|
|
val |= hex_value (*input_line_pointer++);
|
|
|
|
|
}
|
|
|
|
|
return negative ? -val : val;
|
|
|
|
|
}
|
|
|
|
|
else
|
|
|
|
|
{
|
|
|
|
|
++input_line_pointer;
|
2001-09-19 07:33:36 +02:00
|
|
|
|
while (ISDIGIT (*input_line_pointer))
|
1999-05-03 09:29:11 +02:00
|
|
|
|
{
|
|
|
|
|
val <<= 3;
|
|
|
|
|
val |= *input_line_pointer++ - '0';
|
|
|
|
|
}
|
|
|
|
|
return negative ? -val : val;
|
|
|
|
|
}
|
|
|
|
|
}
|
2001-09-19 07:33:36 +02:00
|
|
|
|
if (!ISDIGIT (*input_line_pointer))
|
1999-05-03 09:29:11 +02:00
|
|
|
|
{
|
|
|
|
|
printf (_(" *input_line_pointer == '%c' 0x%02x\n"),
|
|
|
|
|
*input_line_pointer, *input_line_pointer);
|
2001-12-04 15:38:48 +01:00
|
|
|
|
as_warn (_("invalid number"));
|
1999-05-03 09:29:11 +02:00
|
|
|
|
return -1;
|
|
|
|
|
}
|
2001-09-19 07:33:36 +02:00
|
|
|
|
while (ISDIGIT (*input_line_pointer))
|
1999-05-03 09:29:11 +02:00
|
|
|
|
{
|
|
|
|
|
val *= 10;
|
|
|
|
|
val += *input_line_pointer++ - '0';
|
|
|
|
|
}
|
|
|
|
|
return negative ? -val : val;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/* The .file directive; just like the usual .file directive, but there
|
2002-06-08 07:37:29 +02:00
|
|
|
|
is an initial number which is the ECOFF file index. In the non-ECOFF
|
|
|
|
|
case .file implies DWARF-2. */
|
|
|
|
|
|
|
|
|
|
static void
|
2003-06-30 14:44:25 +02:00
|
|
|
|
s_mips_file (int x ATTRIBUTE_UNUSED)
|
2002-06-08 07:37:29 +02:00
|
|
|
|
{
|
2002-06-14 16:08:54 +02:00
|
|
|
|
static int first_file_directive = 0;
|
|
|
|
|
|
2002-06-08 07:37:29 +02:00
|
|
|
|
if (ECOFF_DEBUGGING)
|
|
|
|
|
{
|
|
|
|
|
get_number ();
|
|
|
|
|
s_app_file (0);
|
|
|
|
|
}
|
|
|
|
|
else
|
2002-06-14 16:08:54 +02:00
|
|
|
|
{
|
|
|
|
|
char *filename;
|
|
|
|
|
|
|
|
|
|
filename = dwarf2_directive_file (0);
|
|
|
|
|
|
|
|
|
|
/* Versions of GCC up to 3.1 start files with a ".file"
|
|
|
|
|
directive even for stabs output. Make sure that this
|
|
|
|
|
".file" is handled. Note that you need a version of GCC
|
|
|
|
|
after 3.1 in order to support DWARF-2 on MIPS. */
|
|
|
|
|
if (filename != NULL && ! first_file_directive)
|
|
|
|
|
{
|
|
|
|
|
(void) new_logical_line (filename, -1);
|
|
|
|
|
s_app_file_string (filename);
|
|
|
|
|
}
|
|
|
|
|
first_file_directive = 1;
|
|
|
|
|
}
|
2002-06-08 07:37:29 +02:00
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/* The .loc directive, implying DWARF-2. */
|
1999-05-03 09:29:11 +02:00
|
|
|
|
|
|
|
|
|
static void
|
2003-06-30 14:44:25 +02:00
|
|
|
|
s_mips_loc (int x ATTRIBUTE_UNUSED)
|
1999-05-03 09:29:11 +02:00
|
|
|
|
{
|
2002-06-08 07:37:29 +02:00
|
|
|
|
if (!ECOFF_DEBUGGING)
|
|
|
|
|
dwarf2_directive_loc (0);
|
1999-05-03 09:29:11 +02:00
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/* The .end directive. */
|
|
|
|
|
|
|
|
|
|
static void
|
2003-06-30 14:44:25 +02:00
|
|
|
|
s_mips_end (int x ATTRIBUTE_UNUSED)
|
1999-05-03 09:29:11 +02:00
|
|
|
|
{
|
|
|
|
|
symbolS *p;
|
|
|
|
|
|
2002-01-05 20:06:52 +01:00
|
|
|
|
/* Following functions need their own .frame and .cprestore directives. */
|
|
|
|
|
mips_frame_reg_valid = 0;
|
|
|
|
|
mips_cprestore_valid = 0;
|
|
|
|
|
|
1999-05-03 09:29:11 +02:00
|
|
|
|
if (!is_end_of_line[(unsigned char) *input_line_pointer])
|
|
|
|
|
{
|
|
|
|
|
p = get_symbol ();
|
|
|
|
|
demand_empty_rest_of_line ();
|
|
|
|
|
}
|
|
|
|
|
else
|
|
|
|
|
p = NULL;
|
|
|
|
|
|
2003-03-09 17:16:31 +01:00
|
|
|
|
if ((bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) == 0)
|
1999-05-03 09:29:11 +02:00
|
|
|
|
as_warn (_(".end not in text section"));
|
|
|
|
|
|
|
|
|
|
if (!cur_proc_ptr)
|
|
|
|
|
{
|
|
|
|
|
as_warn (_(".end directive without a preceding .ent directive."));
|
|
|
|
|
demand_empty_rest_of_line ();
|
|
|
|
|
return;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
if (p != NULL)
|
|
|
|
|
{
|
|
|
|
|
assert (S_GET_NAME (p));
|
|
|
|
|
if (strcmp (S_GET_NAME (p), S_GET_NAME (cur_proc_ptr->isym)))
|
|
|
|
|
as_warn (_(".end symbol does not match .ent symbol."));
|
2002-06-14 16:08:54 +02:00
|
|
|
|
|
|
|
|
|
if (debug_type == DEBUG_STABS)
|
|
|
|
|
stabs_generate_asm_endfunc (S_GET_NAME (p),
|
|
|
|
|
S_GET_NAME (p));
|
1999-05-03 09:29:11 +02:00
|
|
|
|
}
|
|
|
|
|
else
|
|
|
|
|
as_warn (_(".end directive missing or unknown symbol"));
|
|
|
|
|
|
2002-06-14 16:08:54 +02:00
|
|
|
|
#ifdef OBJ_ELF
|
|
|
|
|
/* Generate a .pdr section. */
|
2003-07-28 22:06:27 +02:00
|
|
|
|
if (OUTPUT_FLAVOR == bfd_target_elf_flavour && ! ECOFF_DEBUGGING
|
|
|
|
|
&& mips_flag_pdr)
|
2002-06-14 16:08:54 +02:00
|
|
|
|
{
|
|
|
|
|
segT saved_seg = now_seg;
|
|
|
|
|
subsegT saved_subseg = now_subseg;
|
|
|
|
|
valueT dot;
|
|
|
|
|
expressionS exp;
|
|
|
|
|
char *fragp;
|
1999-05-03 09:29:11 +02:00
|
|
|
|
|
2002-06-14 16:08:54 +02:00
|
|
|
|
dot = frag_now_fix ();
|
1999-05-03 09:29:11 +02:00
|
|
|
|
|
|
|
|
|
#ifdef md_flush_pending_output
|
2002-06-14 16:08:54 +02:00
|
|
|
|
md_flush_pending_output ();
|
1999-05-03 09:29:11 +02:00
|
|
|
|
#endif
|
|
|
|
|
|
2002-06-14 16:08:54 +02:00
|
|
|
|
assert (pdr_seg);
|
|
|
|
|
subseg_set (pdr_seg, 0);
|
1999-05-03 09:29:11 +02:00
|
|
|
|
|
2002-06-14 16:08:54 +02:00
|
|
|
|
/* Write the symbol. */
|
|
|
|
|
exp.X_op = O_symbol;
|
|
|
|
|
exp.X_add_symbol = p;
|
|
|
|
|
exp.X_add_number = 0;
|
|
|
|
|
emit_expr (&exp, 4);
|
1999-05-03 09:29:11 +02:00
|
|
|
|
|
2002-06-14 16:08:54 +02:00
|
|
|
|
fragp = frag_more (7 * 4);
|
1999-05-03 09:29:11 +02:00
|
|
|
|
|
2003-06-30 14:44:25 +02:00
|
|
|
|
md_number_to_chars (fragp, cur_proc_ptr->reg_mask, 4);
|
|
|
|
|
md_number_to_chars (fragp + 4, cur_proc_ptr->reg_offset, 4);
|
|
|
|
|
md_number_to_chars (fragp + 8, cur_proc_ptr->fpreg_mask, 4);
|
|
|
|
|
md_number_to_chars (fragp + 12, cur_proc_ptr->fpreg_offset, 4);
|
|
|
|
|
md_number_to_chars (fragp + 16, cur_proc_ptr->frame_offset, 4);
|
|
|
|
|
md_number_to_chars (fragp + 20, cur_proc_ptr->frame_reg, 4);
|
|
|
|
|
md_number_to_chars (fragp + 24, cur_proc_ptr->pc_reg, 4);
|
1999-05-03 09:29:11 +02:00
|
|
|
|
|
2002-06-14 16:08:54 +02:00
|
|
|
|
subseg_set (saved_seg, saved_subseg);
|
|
|
|
|
}
|
|
|
|
|
#endif /* OBJ_ELF */
|
1999-05-03 09:29:11 +02:00
|
|
|
|
|
|
|
|
|
cur_proc_ptr = NULL;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/* The .aent and .ent directives. */
|
|
|
|
|
|
|
|
|
|
static void
|
2003-06-30 14:44:25 +02:00
|
|
|
|
s_mips_ent (int aent)
|
1999-05-03 09:29:11 +02:00
|
|
|
|
{
|
|
|
|
|
symbolS *symbolP;
|
|
|
|
|
|
|
|
|
|
symbolP = get_symbol ();
|
|
|
|
|
if (*input_line_pointer == ',')
|
2002-05-26 20:46:37 +02:00
|
|
|
|
++input_line_pointer;
|
1999-05-03 09:29:11 +02:00
|
|
|
|
SKIP_WHITESPACE ();
|
2001-09-19 07:33:36 +02:00
|
|
|
|
if (ISDIGIT (*input_line_pointer)
|
1999-05-28 17:28:56 +02:00
|
|
|
|
|| *input_line_pointer == '-')
|
2002-04-04 09:43:11 +02:00
|
|
|
|
get_number ();
|
1999-05-03 09:29:11 +02:00
|
|
|
|
|
2003-03-09 17:16:31 +01:00
|
|
|
|
if ((bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) == 0)
|
1999-05-03 09:29:11 +02:00
|
|
|
|
as_warn (_(".ent or .aent not in text section."));
|
|
|
|
|
|
|
|
|
|
if (!aent && cur_proc_ptr)
|
2001-08-07 15:15:26 +02:00
|
|
|
|
as_warn (_("missing .end"));
|
1999-05-03 09:29:11 +02:00
|
|
|
|
|
|
|
|
|
if (!aent)
|
|
|
|
|
{
|
2002-01-05 20:06:52 +01:00
|
|
|
|
/* This function needs its own .frame and .cprestore directives. */
|
|
|
|
|
mips_frame_reg_valid = 0;
|
|
|
|
|
mips_cprestore_valid = 0;
|
|
|
|
|
|
1999-05-03 09:29:11 +02:00
|
|
|
|
cur_proc_ptr = &cur_proc;
|
|
|
|
|
memset (cur_proc_ptr, '\0', sizeof (procS));
|
|
|
|
|
|
|
|
|
|
cur_proc_ptr->isym = symbolP;
|
|
|
|
|
|
Add support for storing local symbols in a small structure to save
memory when assembling large files.
* as.h: Don't include struc-symbol.h.
(symbolS): Add typedef.
* symbols.c: Include struc-symbol.h.
(local_hash): New static variable.
(save_symbol_name): New static function, from symbol_create.
(symbol_create): Call save_symbol_name.
(local_symbol_count): New static variable.
(local_symbol_conversion_count): Likewise.
(LOCAL_SYMBOL_CHECK): Define.
(local_symbol_make): New static function.
(local_symbol_convert): New static function.
(colon): Handle local symbols. Create local symbol for local
label name.
(symbol_table_insert): Handle local symbols.
(symbol_find_or_make): Create local symbol for local label name.
(symbol_find_base): Check for local symbol.
(symbol_append, symbol_insert): Check for local symbols.
(symbol_clear_list_pointers, symbol_remove): Likewise.
(verify_symbol_chain): Likewise.
(copy_symbol_attributes): Likewise.
(resolve_symbol_value): Handle local symbols.
(resolve_local_symbol): New static function.
(resolve_local_symbol_values): New function.
(S_GET_VALUE, S_SET_VALUE): Handle local symbols.
(S_IS_FUNCTION, S_IS_EXTERNAL, S_IS_WEAK, S_IS_COMMON): Likewise.
(S_IS_DEFINED, S_IS_DEBUG, S_IS_LOCAL, S_GET_NAME): Likewise.
(S_GET_SEGMENT, S_SET_SEGMENT, S_SET_EXTERNAL): Likewise.
(S_CLEAR_EXTERNAL, S_SET_WEAK, S_SET_NAME): Likewise.
(symbol_previous, symbol_next): New functions.
(symbol_get_value_expression): Likewise.
(symbol_set_value_expression): Likewise.
(symbol_set_frag, symbol_get_frag): Likewise.
(symbol_mark_used, symbol_clear_used, symbol_used_p): Likewise.
(symbol_mark_used_in_reloc): Likewise.
(symbol_clear_used_in_reloc, symbol_used_in_reloc_p): Likewise.
(symbol_mark_mri_common, symbol_clear_mri_common): Likewise.
(symbol_mri_common_p): Likewise.
(symbol_mark_written, symbol_clear_written): Likewise.
(symbol_written_p): Likewise.
(symbol_mark_resolved, symbol_resolved_p): Likewise.
(symbol_section_p, symbol_equated_p): Likewise.
(symbol_constant_p): Likewise.
(symbol_get_bfdsym, symbol_set_bfdsym): Likewise.
(symbol_get_obj, symbol_set_obj): Likewise.
(symbol_get_tc, symbol_set_tc): Likewise.
(symbol_begin): Initialize local_hash.
(print_symbol_value_1): Handle local symbols.
(symbol_print_statistics): Print local symbol statistics.
* symbols.h: Include "struc-symbol.h" if not BFD_ASSEMBLER.
Declare new symbols.c functions. Move many declarations here from
struc-symbol.h.
(SYMBOLS_NEED_BACKPOINTERS): Define if needed.
* struc-symbol.h (SYMBOLS_NEED_BACKPOINTERS): Don't set.
(struct symbol): Move bsym to make it clearly the first field.
Remove TARGET_SYMBOL_FIELDS.
(symbolS): Don't typedef.
(struct broken_word): Remove.
(N_TYPE_seg, seg_N_TYPE): Move to symbol.h.
(SEGMENT_TO_SYMBOL_TYPE, N_REGISTER): Likewise.
(symbol_clear_list_pointers): Likewise.
(symbol_insert, symbol_remove): Likewise.
(symbol_previous, symbol_append): Likewise.
(verify_symbol_chain, verify_symbol_chain_2): Likewise.
(struct local_symbol): Define.
(local_symbol_converted_p, local_symbol_mark_converted): Define.
(local_symbol_resolved_p, local_symbol_mark_resolved): Define.
(local_symbol_get_frag, local_symbol_set_frag): Define.
(local_symbol_get_real_symbol): Define.
(local_symbol_set_real_symbol): Define.
Define.
* write.c (write_object_file): Call resolve_local_symbol_values.
* config/obj-ecoff.h (OBJ_SYMFIELD_TYPE): Define.
(TARGET_SYMBOL_FIELDS): Don't define.
* config/obj-elf.h (OBJ_SYMFIELD_TYPE): Add local field. If
ECOFF_DEBUGGING, add ECOFF fields.
(ELF_TARGET_SYMBOL_FIELDS, TARGET_SYMBOL_FIELDS): Don't define.
* config/obj-multi.h (struct elf_obj_sy): Add local field. If
ECOFF_DEBUGGING, add ECOFF fields.
(ELF_TARGET_SYMBOL_FIELDS, TARGET_SYMBOL_FIELDS): Don't define.
(ECOFF_DEBUG_TARGET_SYMBOL_FIELDS): Don't define.
* config/tc-mcore.h: Don't include struc-symbol.h.
(TARGET_SYMBOL_FIELDS): Don't define.
(struct mcore_tc_sy): Define.
(TC_SYMFIELD_TYPE): Define.
* Many files: Use symbolS instead of struct symbol. Use new
accessor functions rather than referring to symbolS fields
directly.
* read.c (s_mri_common): Don't add in value of line_label.
* config/tc-mips.c (md_apply_fix): Correct parenthesization when
checking for SEC_LINK_ONCE.
* config/tc-sh.h (sh_fix_adjustable): Declare.
1999-06-03 02:29:48 +02:00
|
|
|
|
symbol_get_bfdsym (symbolP)->flags |= BSF_FUNCTION;
|
1999-05-03 09:29:11 +02:00
|
|
|
|
|
2002-05-26 20:46:37 +02:00
|
|
|
|
++numprocs;
|
2002-06-14 16:08:54 +02:00
|
|
|
|
|
|
|
|
|
if (debug_type == DEBUG_STABS)
|
|
|
|
|
stabs_generate_asm_func (S_GET_NAME (symbolP),
|
|
|
|
|
S_GET_NAME (symbolP));
|
1999-05-03 09:29:11 +02:00
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
demand_empty_rest_of_line ();
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/* The .frame directive. If the mdebug section is present (IRIX 5 native)
|
2000-09-07 14:45:56 +02:00
|
|
|
|
then ecoff.c (ecoff_directive_frame) is used. For embedded targets,
|
1999-05-03 09:29:11 +02:00
|
|
|
|
s_mips_frame is used so that we can set the PDR information correctly.
|
2000-09-07 14:45:56 +02:00
|
|
|
|
We can't use the ecoff routines because they make reference to the ecoff
|
1999-05-03 09:29:11 +02:00
|
|
|
|
symbol table (in the mdebug section). */
|
|
|
|
|
|
|
|
|
|
static void
|
2003-06-30 14:44:25 +02:00
|
|
|
|
s_mips_frame (int ignore ATTRIBUTE_UNUSED)
|
1999-05-03 09:29:11 +02:00
|
|
|
|
{
|
2002-06-14 16:08:54 +02:00
|
|
|
|
#ifdef OBJ_ELF
|
|
|
|
|
if (OUTPUT_FLAVOR == bfd_target_elf_flavour && ! ECOFF_DEBUGGING)
|
|
|
|
|
{
|
|
|
|
|
long val;
|
1999-05-03 09:29:11 +02:00
|
|
|
|
|
2002-06-14 16:08:54 +02:00
|
|
|
|
if (cur_proc_ptr == (procS *) NULL)
|
|
|
|
|
{
|
|
|
|
|
as_warn (_(".frame outside of .ent"));
|
|
|
|
|
demand_empty_rest_of_line ();
|
|
|
|
|
return;
|
|
|
|
|
}
|
1999-05-03 09:29:11 +02:00
|
|
|
|
|
2002-06-14 16:08:54 +02:00
|
|
|
|
cur_proc_ptr->frame_reg = tc_get_register (1);
|
|
|
|
|
|
|
|
|
|
SKIP_WHITESPACE ();
|
|
|
|
|
if (*input_line_pointer++ != ','
|
|
|
|
|
|| get_absolute_expression_and_terminator (&val) != ',')
|
|
|
|
|
{
|
|
|
|
|
as_warn (_("Bad .frame directive"));
|
|
|
|
|
--input_line_pointer;
|
|
|
|
|
demand_empty_rest_of_line ();
|
|
|
|
|
return;
|
|
|
|
|
}
|
1999-05-03 09:29:11 +02:00
|
|
|
|
|
2002-06-14 16:08:54 +02:00
|
|
|
|
cur_proc_ptr->frame_offset = val;
|
|
|
|
|
cur_proc_ptr->pc_reg = tc_get_register (0);
|
1999-05-03 09:29:11 +02:00
|
|
|
|
|
|
|
|
|
demand_empty_rest_of_line ();
|
|
|
|
|
}
|
2002-06-14 16:08:54 +02:00
|
|
|
|
else
|
|
|
|
|
#endif /* OBJ_ELF */
|
|
|
|
|
s_ignore (ignore);
|
1999-05-03 09:29:11 +02:00
|
|
|
|
}
|
|
|
|
|
|
2000-09-07 14:45:56 +02:00
|
|
|
|
/* The .fmask and .mask directives. If the mdebug section is present
|
|
|
|
|
(IRIX 5 native) then ecoff.c (ecoff_directive_mask) is used. For
|
1999-05-03 09:29:11 +02:00
|
|
|
|
embedded targets, s_mips_mask is used so that we can set the PDR
|
2000-09-07 14:45:56 +02:00
|
|
|
|
information correctly. We can't use the ecoff routines because they
|
1999-05-03 09:29:11 +02:00
|
|
|
|
make reference to the ecoff symbol table (in the mdebug section). */
|
|
|
|
|
|
|
|
|
|
static void
|
2003-06-30 14:44:25 +02:00
|
|
|
|
s_mips_mask (int reg_type)
|
1999-05-03 09:29:11 +02:00
|
|
|
|
{
|
2002-06-14 16:08:54 +02:00
|
|
|
|
#ifdef OBJ_ELF
|
|
|
|
|
if (OUTPUT_FLAVOR == bfd_target_elf_flavour && ! ECOFF_DEBUGGING)
|
1999-05-03 09:29:11 +02:00
|
|
|
|
{
|
2002-06-14 16:08:54 +02:00
|
|
|
|
long mask, off;
|
1999-05-03 09:29:11 +02:00
|
|
|
|
|
2002-06-14 16:08:54 +02:00
|
|
|
|
if (cur_proc_ptr == (procS *) NULL)
|
|
|
|
|
{
|
|
|
|
|
as_warn (_(".mask/.fmask outside of .ent"));
|
|
|
|
|
demand_empty_rest_of_line ();
|
|
|
|
|
return;
|
|
|
|
|
}
|
1999-05-03 09:29:11 +02:00
|
|
|
|
|
2002-06-14 16:08:54 +02:00
|
|
|
|
if (get_absolute_expression_and_terminator (&mask) != ',')
|
|
|
|
|
{
|
|
|
|
|
as_warn (_("Bad .mask/.fmask directive"));
|
|
|
|
|
--input_line_pointer;
|
|
|
|
|
demand_empty_rest_of_line ();
|
|
|
|
|
return;
|
|
|
|
|
}
|
1999-05-03 09:29:11 +02:00
|
|
|
|
|
2002-06-14 16:08:54 +02:00
|
|
|
|
off = get_absolute_expression ();
|
|
|
|
|
|
|
|
|
|
if (reg_type == 'F')
|
|
|
|
|
{
|
|
|
|
|
cur_proc_ptr->fpreg_mask = mask;
|
|
|
|
|
cur_proc_ptr->fpreg_offset = off;
|
|
|
|
|
}
|
|
|
|
|
else
|
|
|
|
|
{
|
|
|
|
|
cur_proc_ptr->reg_mask = mask;
|
|
|
|
|
cur_proc_ptr->reg_offset = off;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
demand_empty_rest_of_line ();
|
1999-05-03 09:29:11 +02:00
|
|
|
|
}
|
|
|
|
|
else
|
2002-06-14 16:08:54 +02:00
|
|
|
|
#endif /* OBJ_ELF */
|
|
|
|
|
s_ignore (reg_type);
|
1999-05-03 09:29:11 +02:00
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/* The .loc directive. */
|
|
|
|
|
|
|
|
|
|
#if 0
|
|
|
|
|
static void
|
2003-06-30 14:44:25 +02:00
|
|
|
|
s_loc (int x)
|
1999-05-03 09:29:11 +02:00
|
|
|
|
{
|
|
|
|
|
symbolS *symbolP;
|
|
|
|
|
int lineno;
|
|
|
|
|
int addroff;
|
|
|
|
|
|
|
|
|
|
assert (now_seg == text_section);
|
|
|
|
|
|
|
|
|
|
lineno = get_number ();
|
|
|
|
|
addroff = frag_now_fix ();
|
|
|
|
|
|
|
|
|
|
symbolP = symbol_new ("", N_SLINE, addroff, frag_now);
|
|
|
|
|
S_SET_TYPE (symbolP, N_SLINE);
|
|
|
|
|
S_SET_OTHER (symbolP, 0);
|
|
|
|
|
S_SET_DESC (symbolP, lineno);
|
|
|
|
|
symbolP->sy_segment = now_seg;
|
|
|
|
|
}
|
|
|
|
|
#endif
|
2000-12-01 22:35:38 +01:00
|
|
|
|
|
[gas/]
* doc/c-mips.texi: Remove -mcpu. Document -mabi.
* configure.in (MIPS_CPU_STRING_DEFAULT): New configuration macro.
(USE_E_MIPS_ABI_O32, MIPS_DEFAULT_64BIT): New configuration macros.
* configure, config.in: Regenerate.
* config/tc-mips.c (file_mips_abi): Rename to mips_abi.
(mips_set_options): Remove "abi" field.
(mips_opts): Update accordingly. Replace all uses of mips_opts.abi
with mips_abi.
(mips_cpu): Remove.
(mips_arch_string, mips_arch_info): New vars.
(mips_tune_string, mips_tune_info): New vars.
(ABI_NEEDS_32BIT_REGS, ABI_NEEDS_64BIT_REGS): New macros.
(HAVE_32BIT_GPRS, HAVE_32BIT_FPRS): Don't check the ABI.
(mips_isa_to_str, mips_cpu_to_str): Remove.
(mips_ip): If the selected architecture is a generic ISA rather
than a processor, only mention the ISA level in error messages.
(OPTION_MCPU): Remove.
(OPTION_FP64): New.
(md_longopts): Add -mfp64, remove -mcpu.
(mips_set_option_string): New fn.
(md_parse_option): Make -mipsN update file_mips_isa rather than
mips_opts.isa. Use mips_set_option_string to set -march or -mtune.
Don't let -mgp32 and -mfp32 change the ABI.
(show): Move to end of file. Constify string argument.
(md_show_usage): Move to the end of the file. Read available
architectures from mips_cpu_info_table.
(mips_set_architecture): New fn.
(mips_after_parse_args): Rework. Remove -mcpu handling. -mipsN
is an alias for -march=mipsN. Don't change the ABI based on other
flags. Infer the register size from the ABI as well as the
architecture. Complain about more conflicting arguments.
Unify logic with GCC.
(s_mipsset): Don't change the ABI.
(mips_elf_final_processing): Check USE_E_MIPS_ABI_O32.
(mips_cpu_info_table): Remove Generic-MIPS* entries, keeping just
"mipsN"-type entries. Remove entries that vary only in the
manufacturer's prefix, or that have "000" replaced by "k".
Remove TARGET_CPU entries. Make r2000 entry use CPU_R3000.
(mips_strict_matching_cpu_name_p, mips_matching_cpu_name_p): New fns.
(mips_parse_cpu): New fn.
(mips_cpu_info_from_name, mips_cpu_info_from_cpu): Remove.
(mips_cpu_info_from_isa): Minor formatting tweak.
[gas/testsuite]
* gas/mips/mips-gp32-fp64.d,
* gas/mips/mips-gp32-fp64-pic.d: Add -mfp64.
2002-07-25 11:48:07 +02:00
|
|
|
|
/* A table describing all the processors gas knows about. Names are
|
|
|
|
|
matched in the order listed.
|
2000-12-01 22:35:38 +01:00
|
|
|
|
|
[gas/]
* doc/c-mips.texi: Remove -mcpu. Document -mabi.
* configure.in (MIPS_CPU_STRING_DEFAULT): New configuration macro.
(USE_E_MIPS_ABI_O32, MIPS_DEFAULT_64BIT): New configuration macros.
* configure, config.in: Regenerate.
* config/tc-mips.c (file_mips_abi): Rename to mips_abi.
(mips_set_options): Remove "abi" field.
(mips_opts): Update accordingly. Replace all uses of mips_opts.abi
with mips_abi.
(mips_cpu): Remove.
(mips_arch_string, mips_arch_info): New vars.
(mips_tune_string, mips_tune_info): New vars.
(ABI_NEEDS_32BIT_REGS, ABI_NEEDS_64BIT_REGS): New macros.
(HAVE_32BIT_GPRS, HAVE_32BIT_FPRS): Don't check the ABI.
(mips_isa_to_str, mips_cpu_to_str): Remove.
(mips_ip): If the selected architecture is a generic ISA rather
than a processor, only mention the ISA level in error messages.
(OPTION_MCPU): Remove.
(OPTION_FP64): New.
(md_longopts): Add -mfp64, remove -mcpu.
(mips_set_option_string): New fn.
(md_parse_option): Make -mipsN update file_mips_isa rather than
mips_opts.isa. Use mips_set_option_string to set -march or -mtune.
Don't let -mgp32 and -mfp32 change the ABI.
(show): Move to end of file. Constify string argument.
(md_show_usage): Move to the end of the file. Read available
architectures from mips_cpu_info_table.
(mips_set_architecture): New fn.
(mips_after_parse_args): Rework. Remove -mcpu handling. -mipsN
is an alias for -march=mipsN. Don't change the ABI based on other
flags. Infer the register size from the ABI as well as the
architecture. Complain about more conflicting arguments.
Unify logic with GCC.
(s_mipsset): Don't change the ABI.
(mips_elf_final_processing): Check USE_E_MIPS_ABI_O32.
(mips_cpu_info_table): Remove Generic-MIPS* entries, keeping just
"mipsN"-type entries. Remove entries that vary only in the
manufacturer's prefix, or that have "000" replaced by "k".
Remove TARGET_CPU entries. Make r2000 entry use CPU_R3000.
(mips_strict_matching_cpu_name_p, mips_matching_cpu_name_p): New fns.
(mips_parse_cpu): New fn.
(mips_cpu_info_from_name, mips_cpu_info_from_cpu): Remove.
(mips_cpu_info_from_isa): Minor formatting tweak.
[gas/testsuite]
* gas/mips/mips-gp32-fp64.d,
* gas/mips/mips-gp32-fp64-pic.d: Add -mfp64.
2002-07-25 11:48:07 +02:00
|
|
|
|
To ease comparison, please keep this table in the same order as
|
|
|
|
|
gcc's mips_cpu_info_table[]. */
|
2000-12-12 20:29:24 +01:00
|
|
|
|
static const struct mips_cpu_info mips_cpu_info_table[] =
|
|
|
|
|
{
|
[gas/]
* doc/c-mips.texi: Remove -mcpu. Document -mabi.
* configure.in (MIPS_CPU_STRING_DEFAULT): New configuration macro.
(USE_E_MIPS_ABI_O32, MIPS_DEFAULT_64BIT): New configuration macros.
* configure, config.in: Regenerate.
* config/tc-mips.c (file_mips_abi): Rename to mips_abi.
(mips_set_options): Remove "abi" field.
(mips_opts): Update accordingly. Replace all uses of mips_opts.abi
with mips_abi.
(mips_cpu): Remove.
(mips_arch_string, mips_arch_info): New vars.
(mips_tune_string, mips_tune_info): New vars.
(ABI_NEEDS_32BIT_REGS, ABI_NEEDS_64BIT_REGS): New macros.
(HAVE_32BIT_GPRS, HAVE_32BIT_FPRS): Don't check the ABI.
(mips_isa_to_str, mips_cpu_to_str): Remove.
(mips_ip): If the selected architecture is a generic ISA rather
than a processor, only mention the ISA level in error messages.
(OPTION_MCPU): Remove.
(OPTION_FP64): New.
(md_longopts): Add -mfp64, remove -mcpu.
(mips_set_option_string): New fn.
(md_parse_option): Make -mipsN update file_mips_isa rather than
mips_opts.isa. Use mips_set_option_string to set -march or -mtune.
Don't let -mgp32 and -mfp32 change the ABI.
(show): Move to end of file. Constify string argument.
(md_show_usage): Move to the end of the file. Read available
architectures from mips_cpu_info_table.
(mips_set_architecture): New fn.
(mips_after_parse_args): Rework. Remove -mcpu handling. -mipsN
is an alias for -march=mipsN. Don't change the ABI based on other
flags. Infer the register size from the ABI as well as the
architecture. Complain about more conflicting arguments.
Unify logic with GCC.
(s_mipsset): Don't change the ABI.
(mips_elf_final_processing): Check USE_E_MIPS_ABI_O32.
(mips_cpu_info_table): Remove Generic-MIPS* entries, keeping just
"mipsN"-type entries. Remove entries that vary only in the
manufacturer's prefix, or that have "000" replaced by "k".
Remove TARGET_CPU entries. Make r2000 entry use CPU_R3000.
(mips_strict_matching_cpu_name_p, mips_matching_cpu_name_p): New fns.
(mips_parse_cpu): New fn.
(mips_cpu_info_from_name, mips_cpu_info_from_cpu): Remove.
(mips_cpu_info_from_isa): Minor formatting tweak.
[gas/testsuite]
* gas/mips/mips-gp32-fp64.d,
* gas/mips/mips-gp32-fp64-pic.d: Add -mfp64.
2002-07-25 11:48:07 +02:00
|
|
|
|
/* Entries for generic ISAs */
|
|
|
|
|
{ "mips1", 1, ISA_MIPS1, CPU_R3000 },
|
|
|
|
|
{ "mips2", 1, ISA_MIPS2, CPU_R6000 },
|
|
|
|
|
{ "mips3", 1, ISA_MIPS3, CPU_R4000 },
|
|
|
|
|
{ "mips4", 1, ISA_MIPS4, CPU_R8000 },
|
|
|
|
|
{ "mips5", 1, ISA_MIPS5, CPU_MIPS5 },
|
|
|
|
|
{ "mips32", 1, ISA_MIPS32, CPU_MIPS32 },
|
[ bfd/ChangeLog ]
2002-12-30 Chris Demetriou <cgd@broadcom.com>
* aoutx.h (NAME(aout,machine_type)): Add bfd_mach_mipsisa32r2 case.
* archures.c (bfd_mach_mipsisa32r2): New define.
* bfd-in2.h: Regenerate.
* cpu-mips.c (I_mipsisa32r2): New enum value.
(arch_info_struct): Add entry for I_mipsisa32r2.
* elfxx-mips.c (elf_mips_isa, _bfd_elf_mips_mach)
(_bfd_mips_elf_print_private_bfd_data): Handle E_MIPS_ARCH_32R2.
(_bfd_mips_elf_final_write_processing): Add
bfd_mach_mipsisa32r2 case.
(_bfd_mips_elf_merge_private_bfd_data): Handle merging of
binaries marked as using MIPS32 Release 2.
[ binutils/ChangeLog ]
2002-12-30 Chris Demetriou <cgd@broadcom.com>
* doc/binutils.texi (objdump): Note MIPS HWR (Hardware Register)
changes in MIPS -M options.
[ gas/ChangeLog ]
2002-12-30 Chris Demetriou <cgd@broadcom.com>
* configure.in: Recognize mipsisa32r2, mipsisa32r2el, and
CPU variants.
* configure: Regenerate.
* config/tc-mips.c (ISA_HAS_DROR, ISA_HAS_ROR): New defines.
(macro_build): Handle "K" operand.
(macro2): Use ISA_HAS_DROR and ISA_HAS_ROR in the places where
CPU_HAS_DROR and CPU_HAS_ROR are currently used.
(mips_ip): New variable "lastpos", and implement "+A", "+B",
and "+C" operands for MIPS32 Release 2 ins/ext instructions.
Implement "K" operand for MIPS32 Release 2 rdhwr instruction.
(validate_mips_insn): Implement "+" as a way to extend the
allowed operands, and implement "K", "+A", "+B", and "+C"
operands.
(OPTION_MIPS32R2): New define.
(md_longopts): Add entry for OPTION_MIPS32R2.
(OPTION_ELF_BASE): Adjust to accomodate OPTIONS_MIPS32R2.
(md_parse_option): Handle OPTION_MIPS32R2.
(s_mipsset): Reimplement handling of ".set mipsN" options
and add support for ".set mips32r2".
(mips_cpu_info_table): Add entry for "mips32r2" (MIPS32 Release 2).
(md_show_usage): Document "-mips32r2" option.
* doc/as.texinfo: Document "-mips32r2" option.
* doc/c-mips.texi: Likewise.
[ gas/testsuite/ChangeLog ]
2002-12-30 Chris Demetriou <cgd@broadcom.com>
* gas/mips/cp0-names-mips32r2.d: New test.
* gas/mips/hwr-names-mips32r2.d: New test.
* gas/mips/hwr-names-numeric.d: New test.
* gas/mips/hwr-names.s: New test source file.
* gas/mips/mips32r2.d: New test.
* gas/mips/mips32r2.s: New test source file.
* gas/mips/mips32r2-ill.l: New test.
* gas/mips/mips32r2-ill.s: New test source file.
* gas/mips/mips.exp: Add mips32r2 architecture data array
entry. Run new tests mentioned above.
[ include/elf/ChangeLog ]
2002-12-30 Chris Demetriou <cgd@broadcom.com>
* mips.h (E_MIPS_ARCH_32R2): New define.
[ include/opcode/ChangeLog ]
2002-12-30 Chris Demetriou <cgd@broadcom.com>
* mips.h: Document "+" as the start of two-character operand
type names, and add new "K", "+A", "+B", and "+C" operand types.
(OP_MASK_INSMSB, OP_SH_INSMSB, OP_MASK_EXTMSB)
(OP_SH_EXTMSB, INSN_ISA32R2, ISA_MIPS32R2, CPU_MIPS32R2): New
defines.
[ opcodes/ChangeLog ]
2002-12-30 Chris Demetriou <cgd@broadcom.com>
* mips-dis.c (mips_cp0_names_mips3264r2, mips_hwr_names_numeric)
(mips_hwr_names_mips3264r2): New arrays.
(mips_arch_choice): New "hwr_names" member.
(mips_arch_choices): Adjust for structure change, and add a new
entry for "mips32r2" ISA.
(mips_hwr_names): New variable.
(set_default_mips_dis_options): Set mips_hwr_names.
(parse_mips_dis_option): New "hwr-names" option which sets
mips_hwr_names, and adjust "reg-names=ARCH" to set mips_hwr_names.
(print_insn_arg): Change return type to "int"
and use that to indicate number of characters consumed.
Add support for "+" operand extension character, "+A", "+B",
"+C", and "K" operands.
(print_insn_mips): Adjust for changes to print_insn_arg.
(print_mips_disassembler_options): Adjust for "hwr-names"
addition and "reg-names" change.
* mips-opc (I33): New define (shorthand for INSN_ISA32R2).
(mips_builtin_opcodes): Note that "nop" and "ssnop" are special
forms of "sll". Add new MIPS32 Release 2 instructions: ehb,
di, ei, ext, ins, jr.hb, jalr.hb, mfhc1, mfhc2, mthc1, mthc2,
rdhwr, rdpgpr, seb, seh, synci, wrpgpr, wsbh.
Note that hardware rotate instructions (ror, rorv) can be
used on MIPS32 Release 2, and add the official mnemonics
for them (rotr, rotrv) and the similar "rotl" mnemonic for
left-rotate.
2002-12-31 08:29:29 +01:00
|
|
|
|
{ "mips32r2", 1, ISA_MIPS32R2, CPU_MIPS32R2 },
|
[gas/]
* doc/c-mips.texi: Remove -mcpu. Document -mabi.
* configure.in (MIPS_CPU_STRING_DEFAULT): New configuration macro.
(USE_E_MIPS_ABI_O32, MIPS_DEFAULT_64BIT): New configuration macros.
* configure, config.in: Regenerate.
* config/tc-mips.c (file_mips_abi): Rename to mips_abi.
(mips_set_options): Remove "abi" field.
(mips_opts): Update accordingly. Replace all uses of mips_opts.abi
with mips_abi.
(mips_cpu): Remove.
(mips_arch_string, mips_arch_info): New vars.
(mips_tune_string, mips_tune_info): New vars.
(ABI_NEEDS_32BIT_REGS, ABI_NEEDS_64BIT_REGS): New macros.
(HAVE_32BIT_GPRS, HAVE_32BIT_FPRS): Don't check the ABI.
(mips_isa_to_str, mips_cpu_to_str): Remove.
(mips_ip): If the selected architecture is a generic ISA rather
than a processor, only mention the ISA level in error messages.
(OPTION_MCPU): Remove.
(OPTION_FP64): New.
(md_longopts): Add -mfp64, remove -mcpu.
(mips_set_option_string): New fn.
(md_parse_option): Make -mipsN update file_mips_isa rather than
mips_opts.isa. Use mips_set_option_string to set -march or -mtune.
Don't let -mgp32 and -mfp32 change the ABI.
(show): Move to end of file. Constify string argument.
(md_show_usage): Move to the end of the file. Read available
architectures from mips_cpu_info_table.
(mips_set_architecture): New fn.
(mips_after_parse_args): Rework. Remove -mcpu handling. -mipsN
is an alias for -march=mipsN. Don't change the ABI based on other
flags. Infer the register size from the ABI as well as the
architecture. Complain about more conflicting arguments.
Unify logic with GCC.
(s_mipsset): Don't change the ABI.
(mips_elf_final_processing): Check USE_E_MIPS_ABI_O32.
(mips_cpu_info_table): Remove Generic-MIPS* entries, keeping just
"mipsN"-type entries. Remove entries that vary only in the
manufacturer's prefix, or that have "000" replaced by "k".
Remove TARGET_CPU entries. Make r2000 entry use CPU_R3000.
(mips_strict_matching_cpu_name_p, mips_matching_cpu_name_p): New fns.
(mips_parse_cpu): New fn.
(mips_cpu_info_from_name, mips_cpu_info_from_cpu): Remove.
(mips_cpu_info_from_isa): Minor formatting tweak.
[gas/testsuite]
* gas/mips/mips-gp32-fp64.d,
* gas/mips/mips-gp32-fp64-pic.d: Add -mfp64.
2002-07-25 11:48:07 +02:00
|
|
|
|
{ "mips64", 1, ISA_MIPS64, CPU_MIPS64 },
|
[ bfd/ChangeLog ]
2003-09-30 Chris Demetriou <cgd@broadcom.com>
* archures.c (bfd_mach_mipsisa64r2): New define.
* bfd-in2.h: Regenerate.
* aoutx.h (NAME(aout,machine_type)): Handle bfd_mach_mipsisa64r2.
* cpu-mips.c (I_mipsisa64r2): New enum value.
(arch_info_struct): Add entry for I_mipsisa64r2.
* elfxx-mips.c (_bfd_elf_mips_mach)
(_bfd_mips_elf_print_private_bfd_data): Handle E_MIPS_ARCH_64R2.
(mips_set_isa_flags): Add bfd_mach_mipsisa64r2 case.
(mips_mach_extensions): Add entry for bfd_mach_mipsisa64r2.
[ binutils/ChangeLog ]
2003-09-30 Chris Demetriou <cgd@broadcom.com>
* readelf.c (get_machine_flags): Handle E_MIPS_ARCH_64R2.
[ gas/Changelog ]
2003-09-30 Chris Demetriou <cgd@broadcom.com>
* configure.in (mipsisa64r2, mipsisa64r2el, mipsisa64r2*): New CPUs.
* configure: Regenerate.
* config/tc-mips.c (imm2_expr): New variable.
(md_assemble, mips16_ip): Initialize imm2_expr.
(ISA_HAS_64BIT_REGS, ISA_HAS_DROR, ISA_HAS_ROR): Add ISA_MIPS64R2.
(macro_build): Handle +A, +B, +C, +E, +F, +G, and +H format operands.
(macro): Handle M_DEXT and M_DINS.
(validate_mips_insn): Handle +E, +F, +G, +H, and +I format operands.
(mips_ip): Likewise.
(OPTION_MIPS64R2): New define.
(md_longopts): New entry for -mips64r2 (OPTION_MIPS64R2).
OPTION_ASE_BASE): Increase to compensate for OPTION_MIPS64R2.
(md_parse_option): Handle OPTION_MIPS64R2.
(s_mipsset): Handle setting "mips64r2" ISA.
(mips_cpu_info_table): Add mips64r2.
(md_show_usage): Document -mips64r2 option.
* doc/as.texinfo: Docuemnt -mips64r2 option.
* doc/c-mips.texi: Likewise.
[ gas/testsuite/ChangeLog ]
2003-09-30 Chris Demetriou <cgd@broadcom.com>
* gas/mips/cp0-names-mips64r2.d: New file.
* gas/mips/cp0sel-names-mips64r2.d: New file.
* gas/mips/elf_arch_mips64r2.d: New file.
* gas/mips/hwr-names-mips64r2.d: New file.
* gas/mips/mips32r2-ill-fp64.l: New file.
* gas/mips/mips32r2-ill-fp64.s: New file.
* gas/mips/mips64r2-ill.l: New file.
* gas/mips/mips64r2-ill.s: New file.
* gas/mips/mips64r2.d: New file.
* gas/mips/mips64r2.s: New file.
* gas/mips/mips.exp: Define "mips64r2" arch, and run new tests.
[ include/elf/ChangeLog ]
2003-09-30 Chris Demetriou <cgd@broadcom.com>
* mips.h (E_MIPS_ARCH_64R2): New define.
[ include/opcode/ChangeLog ]
2003-09-30 Chris Demetriou <cgd@broadcom.com>
* mips.h: Document +E, +F, +G, +H, and +I operand types.
Update documentation of I, +B and +C operand types.
(INSN_ISA64R2, ISA_MIPS64R2, CPU_MIPS64R2): New defines.
(M_DEXT, M_DINS): New enum values.
[ ld/ChangeLog ]
2003-09-30 Chris Demetriou <cgd@broadcom.com>
* ldmain.c (get_emulation): Ignore "-mips64r2".
[ ld/testsuite/ChangeLog ]
2003-09-30 Chris Demetriou <cgd@broadcom.com>
* ld-mips-elf/mips-elf-flags.exp: Add tests for combinations
with MIPS64r2.
[ opcodes/ChangeLog ]
2003-09-30 Chris Demetriou <cgd@broadcom.com>
* mips-dis.c (mips_arch_choices): Add entry for "mips64r2"
(print_insn_args): Add handing for +E, +F, +G, and +H.
* mips-opc.c (I65): New define for MIPS64r2.
(mips_builtin_opcodes): Add "dext", "dextm", "dextu", "dins",
"dinsm", "dinsu", "drotl", "drotr", "drotr32", "drotrv", "dsbh",
and "dshd" for MIPS64r2. Adjust "dror", "dror32", and "drorv" to
be supported on MIPS64r2.
2003-09-30 18:17:15 +02:00
|
|
|
|
{ "mips64r2", 1, ISA_MIPS64R2, CPU_MIPS64R2 },
|
[gas/]
* doc/c-mips.texi: Remove -mcpu. Document -mabi.
* configure.in (MIPS_CPU_STRING_DEFAULT): New configuration macro.
(USE_E_MIPS_ABI_O32, MIPS_DEFAULT_64BIT): New configuration macros.
* configure, config.in: Regenerate.
* config/tc-mips.c (file_mips_abi): Rename to mips_abi.
(mips_set_options): Remove "abi" field.
(mips_opts): Update accordingly. Replace all uses of mips_opts.abi
with mips_abi.
(mips_cpu): Remove.
(mips_arch_string, mips_arch_info): New vars.
(mips_tune_string, mips_tune_info): New vars.
(ABI_NEEDS_32BIT_REGS, ABI_NEEDS_64BIT_REGS): New macros.
(HAVE_32BIT_GPRS, HAVE_32BIT_FPRS): Don't check the ABI.
(mips_isa_to_str, mips_cpu_to_str): Remove.
(mips_ip): If the selected architecture is a generic ISA rather
than a processor, only mention the ISA level in error messages.
(OPTION_MCPU): Remove.
(OPTION_FP64): New.
(md_longopts): Add -mfp64, remove -mcpu.
(mips_set_option_string): New fn.
(md_parse_option): Make -mipsN update file_mips_isa rather than
mips_opts.isa. Use mips_set_option_string to set -march or -mtune.
Don't let -mgp32 and -mfp32 change the ABI.
(show): Move to end of file. Constify string argument.
(md_show_usage): Move to the end of the file. Read available
architectures from mips_cpu_info_table.
(mips_set_architecture): New fn.
(mips_after_parse_args): Rework. Remove -mcpu handling. -mipsN
is an alias for -march=mipsN. Don't change the ABI based on other
flags. Infer the register size from the ABI as well as the
architecture. Complain about more conflicting arguments.
Unify logic with GCC.
(s_mipsset): Don't change the ABI.
(mips_elf_final_processing): Check USE_E_MIPS_ABI_O32.
(mips_cpu_info_table): Remove Generic-MIPS* entries, keeping just
"mipsN"-type entries. Remove entries that vary only in the
manufacturer's prefix, or that have "000" replaced by "k".
Remove TARGET_CPU entries. Make r2000 entry use CPU_R3000.
(mips_strict_matching_cpu_name_p, mips_matching_cpu_name_p): New fns.
(mips_parse_cpu): New fn.
(mips_cpu_info_from_name, mips_cpu_info_from_cpu): Remove.
(mips_cpu_info_from_isa): Minor formatting tweak.
[gas/testsuite]
* gas/mips/mips-gp32-fp64.d,
* gas/mips/mips-gp32-fp64-pic.d: Add -mfp64.
2002-07-25 11:48:07 +02:00
|
|
|
|
|
|
|
|
|
/* MIPS I */
|
|
|
|
|
{ "r3000", 0, ISA_MIPS1, CPU_R3000 },
|
|
|
|
|
{ "r2000", 0, ISA_MIPS1, CPU_R3000 },
|
|
|
|
|
{ "r3900", 0, ISA_MIPS1, CPU_R3900 },
|
|
|
|
|
|
|
|
|
|
/* MIPS II */
|
|
|
|
|
{ "r6000", 0, ISA_MIPS2, CPU_R6000 },
|
|
|
|
|
|
|
|
|
|
/* MIPS III */
|
|
|
|
|
{ "r4000", 0, ISA_MIPS3, CPU_R4000 },
|
|
|
|
|
{ "r4010", 0, ISA_MIPS2, CPU_R4010 },
|
|
|
|
|
{ "vr4100", 0, ISA_MIPS3, CPU_VR4100 },
|
|
|
|
|
{ "vr4111", 0, ISA_MIPS3, CPU_R4111 },
|
[gas/]
* doc/c-mips.texi: Add entries for -march=vr4120,vr4130,vr4181,
vr5400 and vr5500. Add entry for -mfix-vr4122-bugs.
* config/tc-mips.c (CPU_HAS_DROR, CPU_HAS_ROR): New macros.
(hilo_interlocks): True for CPU_VR5500.
(gpr_interlocks, cop_interlocks): True for CPU_VR5400 and CPU_VR5500.
(mips_fix_vr4122_bugs): New.
(append_insn): Work around 4122 errors if mips_fix_vr4122_bugs.
(mips_emit_delays): Likewise.
(macro2) [M_DROLI]: Use dror or dror32 if CPU_HAS_DROR.
[M_ROLI]: Likewise ror if CPU_HAS_ROR.
(validate_mips_insn, mips_ip): Handle '[', ']', 'e' and '%'.
(OPTION_FIX_VR4122, OPTION_NO_FIX_VR4122): New options.
(md_longopts): Add -mfix-vr4122-bugs and -no-mfix-vr4122-bugs.
(OPTION_ELF_BASE): Bump.
(md_parse_option): Handle the new options.
(mips_cpu_info_table): Add entries for vr4120, vr4130, vr4181,
vr5400 and vr5500.
[gas/testsuite/]
* gas/mips/mips4100.[sd]: Move dmadd16 and madd16 checks to...
* gas/mips/vr4111.[sd]: ...this new test.
* gas/mips/vr4120.[sd],
* gas/mips/vr4122.[sd],
* gas/mips/vr5400.[sd],
* gas/mips/vr5500.[sd]: New tests.
* mips.exp: Run them.
2002-09-30 14:04:54 +02:00
|
|
|
|
{ "vr4120", 0, ISA_MIPS3, CPU_VR4120 },
|
|
|
|
|
{ "vr4130", 0, ISA_MIPS3, CPU_VR4120 },
|
|
|
|
|
{ "vr4181", 0, ISA_MIPS3, CPU_R4111 },
|
[gas/]
* doc/c-mips.texi: Remove -mcpu. Document -mabi.
* configure.in (MIPS_CPU_STRING_DEFAULT): New configuration macro.
(USE_E_MIPS_ABI_O32, MIPS_DEFAULT_64BIT): New configuration macros.
* configure, config.in: Regenerate.
* config/tc-mips.c (file_mips_abi): Rename to mips_abi.
(mips_set_options): Remove "abi" field.
(mips_opts): Update accordingly. Replace all uses of mips_opts.abi
with mips_abi.
(mips_cpu): Remove.
(mips_arch_string, mips_arch_info): New vars.
(mips_tune_string, mips_tune_info): New vars.
(ABI_NEEDS_32BIT_REGS, ABI_NEEDS_64BIT_REGS): New macros.
(HAVE_32BIT_GPRS, HAVE_32BIT_FPRS): Don't check the ABI.
(mips_isa_to_str, mips_cpu_to_str): Remove.
(mips_ip): If the selected architecture is a generic ISA rather
than a processor, only mention the ISA level in error messages.
(OPTION_MCPU): Remove.
(OPTION_FP64): New.
(md_longopts): Add -mfp64, remove -mcpu.
(mips_set_option_string): New fn.
(md_parse_option): Make -mipsN update file_mips_isa rather than
mips_opts.isa. Use mips_set_option_string to set -march or -mtune.
Don't let -mgp32 and -mfp32 change the ABI.
(show): Move to end of file. Constify string argument.
(md_show_usage): Move to the end of the file. Read available
architectures from mips_cpu_info_table.
(mips_set_architecture): New fn.
(mips_after_parse_args): Rework. Remove -mcpu handling. -mipsN
is an alias for -march=mipsN. Don't change the ABI based on other
flags. Infer the register size from the ABI as well as the
architecture. Complain about more conflicting arguments.
Unify logic with GCC.
(s_mipsset): Don't change the ABI.
(mips_elf_final_processing): Check USE_E_MIPS_ABI_O32.
(mips_cpu_info_table): Remove Generic-MIPS* entries, keeping just
"mipsN"-type entries. Remove entries that vary only in the
manufacturer's prefix, or that have "000" replaced by "k".
Remove TARGET_CPU entries. Make r2000 entry use CPU_R3000.
(mips_strict_matching_cpu_name_p, mips_matching_cpu_name_p): New fns.
(mips_parse_cpu): New fn.
(mips_cpu_info_from_name, mips_cpu_info_from_cpu): Remove.
(mips_cpu_info_from_isa): Minor formatting tweak.
[gas/testsuite]
* gas/mips/mips-gp32-fp64.d,
* gas/mips/mips-gp32-fp64-pic.d: Add -mfp64.
2002-07-25 11:48:07 +02:00
|
|
|
|
{ "vr4300", 0, ISA_MIPS3, CPU_R4300 },
|
|
|
|
|
{ "r4400", 0, ISA_MIPS3, CPU_R4400 },
|
|
|
|
|
{ "r4600", 0, ISA_MIPS3, CPU_R4600 },
|
|
|
|
|
{ "orion", 0, ISA_MIPS3, CPU_R4600 },
|
|
|
|
|
{ "r4650", 0, ISA_MIPS3, CPU_R4650 },
|
|
|
|
|
|
|
|
|
|
/* MIPS IV */
|
|
|
|
|
{ "r8000", 0, ISA_MIPS4, CPU_R8000 },
|
|
|
|
|
{ "r10000", 0, ISA_MIPS4, CPU_R10000 },
|
|
|
|
|
{ "r12000", 0, ISA_MIPS4, CPU_R12000 },
|
|
|
|
|
{ "vr5000", 0, ISA_MIPS4, CPU_R5000 },
|
[gas/]
* doc/c-mips.texi: Add entries for -march=vr4120,vr4130,vr4181,
vr5400 and vr5500. Add entry for -mfix-vr4122-bugs.
* config/tc-mips.c (CPU_HAS_DROR, CPU_HAS_ROR): New macros.
(hilo_interlocks): True for CPU_VR5500.
(gpr_interlocks, cop_interlocks): True for CPU_VR5400 and CPU_VR5500.
(mips_fix_vr4122_bugs): New.
(append_insn): Work around 4122 errors if mips_fix_vr4122_bugs.
(mips_emit_delays): Likewise.
(macro2) [M_DROLI]: Use dror or dror32 if CPU_HAS_DROR.
[M_ROLI]: Likewise ror if CPU_HAS_ROR.
(validate_mips_insn, mips_ip): Handle '[', ']', 'e' and '%'.
(OPTION_FIX_VR4122, OPTION_NO_FIX_VR4122): New options.
(md_longopts): Add -mfix-vr4122-bugs and -no-mfix-vr4122-bugs.
(OPTION_ELF_BASE): Bump.
(md_parse_option): Handle the new options.
(mips_cpu_info_table): Add entries for vr4120, vr4130, vr4181,
vr5400 and vr5500.
[gas/testsuite/]
* gas/mips/mips4100.[sd]: Move dmadd16 and madd16 checks to...
* gas/mips/vr4111.[sd]: ...this new test.
* gas/mips/vr4120.[sd],
* gas/mips/vr4122.[sd],
* gas/mips/vr5400.[sd],
* gas/mips/vr5500.[sd]: New tests.
* mips.exp: Run them.
2002-09-30 14:04:54 +02:00
|
|
|
|
{ "vr5400", 0, ISA_MIPS4, CPU_VR5400 },
|
|
|
|
|
{ "vr5500", 0, ISA_MIPS4, CPU_VR5500 },
|
[gas/]
* doc/c-mips.texi: Remove -mcpu. Document -mabi.
* configure.in (MIPS_CPU_STRING_DEFAULT): New configuration macro.
(USE_E_MIPS_ABI_O32, MIPS_DEFAULT_64BIT): New configuration macros.
* configure, config.in: Regenerate.
* config/tc-mips.c (file_mips_abi): Rename to mips_abi.
(mips_set_options): Remove "abi" field.
(mips_opts): Update accordingly. Replace all uses of mips_opts.abi
with mips_abi.
(mips_cpu): Remove.
(mips_arch_string, mips_arch_info): New vars.
(mips_tune_string, mips_tune_info): New vars.
(ABI_NEEDS_32BIT_REGS, ABI_NEEDS_64BIT_REGS): New macros.
(HAVE_32BIT_GPRS, HAVE_32BIT_FPRS): Don't check the ABI.
(mips_isa_to_str, mips_cpu_to_str): Remove.
(mips_ip): If the selected architecture is a generic ISA rather
than a processor, only mention the ISA level in error messages.
(OPTION_MCPU): Remove.
(OPTION_FP64): New.
(md_longopts): Add -mfp64, remove -mcpu.
(mips_set_option_string): New fn.
(md_parse_option): Make -mipsN update file_mips_isa rather than
mips_opts.isa. Use mips_set_option_string to set -march or -mtune.
Don't let -mgp32 and -mfp32 change the ABI.
(show): Move to end of file. Constify string argument.
(md_show_usage): Move to the end of the file. Read available
architectures from mips_cpu_info_table.
(mips_set_architecture): New fn.
(mips_after_parse_args): Rework. Remove -mcpu handling. -mipsN
is an alias for -march=mipsN. Don't change the ABI based on other
flags. Infer the register size from the ABI as well as the
architecture. Complain about more conflicting arguments.
Unify logic with GCC.
(s_mipsset): Don't change the ABI.
(mips_elf_final_processing): Check USE_E_MIPS_ABI_O32.
(mips_cpu_info_table): Remove Generic-MIPS* entries, keeping just
"mipsN"-type entries. Remove entries that vary only in the
manufacturer's prefix, or that have "000" replaced by "k".
Remove TARGET_CPU entries. Make r2000 entry use CPU_R3000.
(mips_strict_matching_cpu_name_p, mips_matching_cpu_name_p): New fns.
(mips_parse_cpu): New fn.
(mips_cpu_info_from_name, mips_cpu_info_from_cpu): Remove.
(mips_cpu_info_from_isa): Minor formatting tweak.
[gas/testsuite]
* gas/mips/mips-gp32-fp64.d,
* gas/mips/mips-gp32-fp64-pic.d: Add -mfp64.
2002-07-25 11:48:07 +02:00
|
|
|
|
{ "rm5200", 0, ISA_MIPS4, CPU_R5000 },
|
|
|
|
|
{ "rm5230", 0, ISA_MIPS4, CPU_R5000 },
|
|
|
|
|
{ "rm5231", 0, ISA_MIPS4, CPU_R5000 },
|
|
|
|
|
{ "rm5261", 0, ISA_MIPS4, CPU_R5000 },
|
|
|
|
|
{ "rm5721", 0, ISA_MIPS4, CPU_R5000 },
|
2003-07-15 09:50:39 +02:00
|
|
|
|
{ "rm7000", 0, ISA_MIPS4, CPU_RM7000 },
|
|
|
|
|
{ "rm9000", 0, ISA_MIPS4, CPU_RM7000 },
|
[gas/]
* doc/c-mips.texi: Remove -mcpu. Document -mabi.
* configure.in (MIPS_CPU_STRING_DEFAULT): New configuration macro.
(USE_E_MIPS_ABI_O32, MIPS_DEFAULT_64BIT): New configuration macros.
* configure, config.in: Regenerate.
* config/tc-mips.c (file_mips_abi): Rename to mips_abi.
(mips_set_options): Remove "abi" field.
(mips_opts): Update accordingly. Replace all uses of mips_opts.abi
with mips_abi.
(mips_cpu): Remove.
(mips_arch_string, mips_arch_info): New vars.
(mips_tune_string, mips_tune_info): New vars.
(ABI_NEEDS_32BIT_REGS, ABI_NEEDS_64BIT_REGS): New macros.
(HAVE_32BIT_GPRS, HAVE_32BIT_FPRS): Don't check the ABI.
(mips_isa_to_str, mips_cpu_to_str): Remove.
(mips_ip): If the selected architecture is a generic ISA rather
than a processor, only mention the ISA level in error messages.
(OPTION_MCPU): Remove.
(OPTION_FP64): New.
(md_longopts): Add -mfp64, remove -mcpu.
(mips_set_option_string): New fn.
(md_parse_option): Make -mipsN update file_mips_isa rather than
mips_opts.isa. Use mips_set_option_string to set -march or -mtune.
Don't let -mgp32 and -mfp32 change the ABI.
(show): Move to end of file. Constify string argument.
(md_show_usage): Move to the end of the file. Read available
architectures from mips_cpu_info_table.
(mips_set_architecture): New fn.
(mips_after_parse_args): Rework. Remove -mcpu handling. -mipsN
is an alias for -march=mipsN. Don't change the ABI based on other
flags. Infer the register size from the ABI as well as the
architecture. Complain about more conflicting arguments.
Unify logic with GCC.
(s_mipsset): Don't change the ABI.
(mips_elf_final_processing): Check USE_E_MIPS_ABI_O32.
(mips_cpu_info_table): Remove Generic-MIPS* entries, keeping just
"mipsN"-type entries. Remove entries that vary only in the
manufacturer's prefix, or that have "000" replaced by "k".
Remove TARGET_CPU entries. Make r2000 entry use CPU_R3000.
(mips_strict_matching_cpu_name_p, mips_matching_cpu_name_p): New fns.
(mips_parse_cpu): New fn.
(mips_cpu_info_from_name, mips_cpu_info_from_cpu): Remove.
(mips_cpu_info_from_isa): Minor formatting tweak.
[gas/testsuite]
* gas/mips/mips-gp32-fp64.d,
* gas/mips/mips-gp32-fp64-pic.d: Add -mfp64.
2002-07-25 11:48:07 +02:00
|
|
|
|
|
|
|
|
|
/* MIPS 32 */
|
2003-06-29 21:41:33 +02:00
|
|
|
|
{ "4kc", 0, ISA_MIPS32, CPU_MIPS32 },
|
[gas/]
* doc/c-mips.texi: Remove -mcpu. Document -mabi.
* configure.in (MIPS_CPU_STRING_DEFAULT): New configuration macro.
(USE_E_MIPS_ABI_O32, MIPS_DEFAULT_64BIT): New configuration macros.
* configure, config.in: Regenerate.
* config/tc-mips.c (file_mips_abi): Rename to mips_abi.
(mips_set_options): Remove "abi" field.
(mips_opts): Update accordingly. Replace all uses of mips_opts.abi
with mips_abi.
(mips_cpu): Remove.
(mips_arch_string, mips_arch_info): New vars.
(mips_tune_string, mips_tune_info): New vars.
(ABI_NEEDS_32BIT_REGS, ABI_NEEDS_64BIT_REGS): New macros.
(HAVE_32BIT_GPRS, HAVE_32BIT_FPRS): Don't check the ABI.
(mips_isa_to_str, mips_cpu_to_str): Remove.
(mips_ip): If the selected architecture is a generic ISA rather
than a processor, only mention the ISA level in error messages.
(OPTION_MCPU): Remove.
(OPTION_FP64): New.
(md_longopts): Add -mfp64, remove -mcpu.
(mips_set_option_string): New fn.
(md_parse_option): Make -mipsN update file_mips_isa rather than
mips_opts.isa. Use mips_set_option_string to set -march or -mtune.
Don't let -mgp32 and -mfp32 change the ABI.
(show): Move to end of file. Constify string argument.
(md_show_usage): Move to the end of the file. Read available
architectures from mips_cpu_info_table.
(mips_set_architecture): New fn.
(mips_after_parse_args): Rework. Remove -mcpu handling. -mipsN
is an alias for -march=mipsN. Don't change the ABI based on other
flags. Infer the register size from the ABI as well as the
architecture. Complain about more conflicting arguments.
Unify logic with GCC.
(s_mipsset): Don't change the ABI.
(mips_elf_final_processing): Check USE_E_MIPS_ABI_O32.
(mips_cpu_info_table): Remove Generic-MIPS* entries, keeping just
"mipsN"-type entries. Remove entries that vary only in the
manufacturer's prefix, or that have "000" replaced by "k".
Remove TARGET_CPU entries. Make r2000 entry use CPU_R3000.
(mips_strict_matching_cpu_name_p, mips_matching_cpu_name_p): New fns.
(mips_parse_cpu): New fn.
(mips_cpu_info_from_name, mips_cpu_info_from_cpu): Remove.
(mips_cpu_info_from_isa): Minor formatting tweak.
[gas/testsuite]
* gas/mips/mips-gp32-fp64.d,
* gas/mips/mips-gp32-fp64-pic.d: Add -mfp64.
2002-07-25 11:48:07 +02:00
|
|
|
|
{ "4km", 0, ISA_MIPS32, CPU_MIPS32 },
|
|
|
|
|
{ "4kp", 0, ISA_MIPS32, CPU_MIPS32 },
|
2000-12-01 22:35:38 +01:00
|
|
|
|
|
[gas/]
* doc/c-mips.texi: Remove -mcpu. Document -mabi.
* configure.in (MIPS_CPU_STRING_DEFAULT): New configuration macro.
(USE_E_MIPS_ABI_O32, MIPS_DEFAULT_64BIT): New configuration macros.
* configure, config.in: Regenerate.
* config/tc-mips.c (file_mips_abi): Rename to mips_abi.
(mips_set_options): Remove "abi" field.
(mips_opts): Update accordingly. Replace all uses of mips_opts.abi
with mips_abi.
(mips_cpu): Remove.
(mips_arch_string, mips_arch_info): New vars.
(mips_tune_string, mips_tune_info): New vars.
(ABI_NEEDS_32BIT_REGS, ABI_NEEDS_64BIT_REGS): New macros.
(HAVE_32BIT_GPRS, HAVE_32BIT_FPRS): Don't check the ABI.
(mips_isa_to_str, mips_cpu_to_str): Remove.
(mips_ip): If the selected architecture is a generic ISA rather
than a processor, only mention the ISA level in error messages.
(OPTION_MCPU): Remove.
(OPTION_FP64): New.
(md_longopts): Add -mfp64, remove -mcpu.
(mips_set_option_string): New fn.
(md_parse_option): Make -mipsN update file_mips_isa rather than
mips_opts.isa. Use mips_set_option_string to set -march or -mtune.
Don't let -mgp32 and -mfp32 change the ABI.
(show): Move to end of file. Constify string argument.
(md_show_usage): Move to the end of the file. Read available
architectures from mips_cpu_info_table.
(mips_set_architecture): New fn.
(mips_after_parse_args): Rework. Remove -mcpu handling. -mipsN
is an alias for -march=mipsN. Don't change the ABI based on other
flags. Infer the register size from the ABI as well as the
architecture. Complain about more conflicting arguments.
Unify logic with GCC.
(s_mipsset): Don't change the ABI.
(mips_elf_final_processing): Check USE_E_MIPS_ABI_O32.
(mips_cpu_info_table): Remove Generic-MIPS* entries, keeping just
"mipsN"-type entries. Remove entries that vary only in the
manufacturer's prefix, or that have "000" replaced by "k".
Remove TARGET_CPU entries. Make r2000 entry use CPU_R3000.
(mips_strict_matching_cpu_name_p, mips_matching_cpu_name_p): New fns.
(mips_parse_cpu): New fn.
(mips_cpu_info_from_name, mips_cpu_info_from_cpu): Remove.
(mips_cpu_info_from_isa): Minor formatting tweak.
[gas/testsuite]
* gas/mips/mips-gp32-fp64.d,
* gas/mips/mips-gp32-fp64-pic.d: Add -mfp64.
2002-07-25 11:48:07 +02:00
|
|
|
|
/* MIPS 64 */
|
|
|
|
|
{ "5kc", 0, ISA_MIPS64, CPU_MIPS64 },
|
|
|
|
|
{ "20kc", 0, ISA_MIPS64, CPU_MIPS64 },
|
2000-12-01 22:35:38 +01:00
|
|
|
|
|
2002-07-31 07:48:31 +02:00
|
|
|
|
/* Broadcom SB-1 CPU core */
|
[gas/]
* doc/c-mips.texi: Remove -mcpu. Document -mabi.
* configure.in (MIPS_CPU_STRING_DEFAULT): New configuration macro.
(USE_E_MIPS_ABI_O32, MIPS_DEFAULT_64BIT): New configuration macros.
* configure, config.in: Regenerate.
* config/tc-mips.c (file_mips_abi): Rename to mips_abi.
(mips_set_options): Remove "abi" field.
(mips_opts): Update accordingly. Replace all uses of mips_opts.abi
with mips_abi.
(mips_cpu): Remove.
(mips_arch_string, mips_arch_info): New vars.
(mips_tune_string, mips_tune_info): New vars.
(ABI_NEEDS_32BIT_REGS, ABI_NEEDS_64BIT_REGS): New macros.
(HAVE_32BIT_GPRS, HAVE_32BIT_FPRS): Don't check the ABI.
(mips_isa_to_str, mips_cpu_to_str): Remove.
(mips_ip): If the selected architecture is a generic ISA rather
than a processor, only mention the ISA level in error messages.
(OPTION_MCPU): Remove.
(OPTION_FP64): New.
(md_longopts): Add -mfp64, remove -mcpu.
(mips_set_option_string): New fn.
(md_parse_option): Make -mipsN update file_mips_isa rather than
mips_opts.isa. Use mips_set_option_string to set -march or -mtune.
Don't let -mgp32 and -mfp32 change the ABI.
(show): Move to end of file. Constify string argument.
(md_show_usage): Move to the end of the file. Read available
architectures from mips_cpu_info_table.
(mips_set_architecture): New fn.
(mips_after_parse_args): Rework. Remove -mcpu handling. -mipsN
is an alias for -march=mipsN. Don't change the ABI based on other
flags. Infer the register size from the ABI as well as the
architecture. Complain about more conflicting arguments.
Unify logic with GCC.
(s_mipsset): Don't change the ABI.
(mips_elf_final_processing): Check USE_E_MIPS_ABI_O32.
(mips_cpu_info_table): Remove Generic-MIPS* entries, keeping just
"mipsN"-type entries. Remove entries that vary only in the
manufacturer's prefix, or that have "000" replaced by "k".
Remove TARGET_CPU entries. Make r2000 entry use CPU_R3000.
(mips_strict_matching_cpu_name_p, mips_matching_cpu_name_p): New fns.
(mips_parse_cpu): New fn.
(mips_cpu_info_from_name, mips_cpu_info_from_cpu): Remove.
(mips_cpu_info_from_isa): Minor formatting tweak.
[gas/testsuite]
* gas/mips/mips-gp32-fp64.d,
* gas/mips/mips-gp32-fp64-pic.d: Add -mfp64.
2002-07-25 11:48:07 +02:00
|
|
|
|
{ "sb1", 0, ISA_MIPS64, CPU_SB1 },
|
2000-12-01 22:35:38 +01:00
|
|
|
|
|
[gas/]
* doc/c-mips.texi: Remove -mcpu. Document -mabi.
* configure.in (MIPS_CPU_STRING_DEFAULT): New configuration macro.
(USE_E_MIPS_ABI_O32, MIPS_DEFAULT_64BIT): New configuration macros.
* configure, config.in: Regenerate.
* config/tc-mips.c (file_mips_abi): Rename to mips_abi.
(mips_set_options): Remove "abi" field.
(mips_opts): Update accordingly. Replace all uses of mips_opts.abi
with mips_abi.
(mips_cpu): Remove.
(mips_arch_string, mips_arch_info): New vars.
(mips_tune_string, mips_tune_info): New vars.
(ABI_NEEDS_32BIT_REGS, ABI_NEEDS_64BIT_REGS): New macros.
(HAVE_32BIT_GPRS, HAVE_32BIT_FPRS): Don't check the ABI.
(mips_isa_to_str, mips_cpu_to_str): Remove.
(mips_ip): If the selected architecture is a generic ISA rather
than a processor, only mention the ISA level in error messages.
(OPTION_MCPU): Remove.
(OPTION_FP64): New.
(md_longopts): Add -mfp64, remove -mcpu.
(mips_set_option_string): New fn.
(md_parse_option): Make -mipsN update file_mips_isa rather than
mips_opts.isa. Use mips_set_option_string to set -march or -mtune.
Don't let -mgp32 and -mfp32 change the ABI.
(show): Move to end of file. Constify string argument.
(md_show_usage): Move to the end of the file. Read available
architectures from mips_cpu_info_table.
(mips_set_architecture): New fn.
(mips_after_parse_args): Rework. Remove -mcpu handling. -mipsN
is an alias for -march=mipsN. Don't change the ABI based on other
flags. Infer the register size from the ABI as well as the
architecture. Complain about more conflicting arguments.
Unify logic with GCC.
(s_mipsset): Don't change the ABI.
(mips_elf_final_processing): Check USE_E_MIPS_ABI_O32.
(mips_cpu_info_table): Remove Generic-MIPS* entries, keeping just
"mipsN"-type entries. Remove entries that vary only in the
manufacturer's prefix, or that have "000" replaced by "k".
Remove TARGET_CPU entries. Make r2000 entry use CPU_R3000.
(mips_strict_matching_cpu_name_p, mips_matching_cpu_name_p): New fns.
(mips_parse_cpu): New fn.
(mips_cpu_info_from_name, mips_cpu_info_from_cpu): Remove.
(mips_cpu_info_from_isa): Minor formatting tweak.
[gas/testsuite]
* gas/mips/mips-gp32-fp64.d,
* gas/mips/mips-gp32-fp64-pic.d: Add -mfp64.
2002-07-25 11:48:07 +02:00
|
|
|
|
/* End marker */
|
|
|
|
|
{ NULL, 0, 0, 0 }
|
|
|
|
|
};
|
2000-12-01 22:35:38 +01:00
|
|
|
|
|
2000-12-02 01:55:22 +01:00
|
|
|
|
|
[gas/]
* doc/c-mips.texi: Remove -mcpu. Document -mabi.
* configure.in (MIPS_CPU_STRING_DEFAULT): New configuration macro.
(USE_E_MIPS_ABI_O32, MIPS_DEFAULT_64BIT): New configuration macros.
* configure, config.in: Regenerate.
* config/tc-mips.c (file_mips_abi): Rename to mips_abi.
(mips_set_options): Remove "abi" field.
(mips_opts): Update accordingly. Replace all uses of mips_opts.abi
with mips_abi.
(mips_cpu): Remove.
(mips_arch_string, mips_arch_info): New vars.
(mips_tune_string, mips_tune_info): New vars.
(ABI_NEEDS_32BIT_REGS, ABI_NEEDS_64BIT_REGS): New macros.
(HAVE_32BIT_GPRS, HAVE_32BIT_FPRS): Don't check the ABI.
(mips_isa_to_str, mips_cpu_to_str): Remove.
(mips_ip): If the selected architecture is a generic ISA rather
than a processor, only mention the ISA level in error messages.
(OPTION_MCPU): Remove.
(OPTION_FP64): New.
(md_longopts): Add -mfp64, remove -mcpu.
(mips_set_option_string): New fn.
(md_parse_option): Make -mipsN update file_mips_isa rather than
mips_opts.isa. Use mips_set_option_string to set -march or -mtune.
Don't let -mgp32 and -mfp32 change the ABI.
(show): Move to end of file. Constify string argument.
(md_show_usage): Move to the end of the file. Read available
architectures from mips_cpu_info_table.
(mips_set_architecture): New fn.
(mips_after_parse_args): Rework. Remove -mcpu handling. -mipsN
is an alias for -march=mipsN. Don't change the ABI based on other
flags. Infer the register size from the ABI as well as the
architecture. Complain about more conflicting arguments.
Unify logic with GCC.
(s_mipsset): Don't change the ABI.
(mips_elf_final_processing): Check USE_E_MIPS_ABI_O32.
(mips_cpu_info_table): Remove Generic-MIPS* entries, keeping just
"mipsN"-type entries. Remove entries that vary only in the
manufacturer's prefix, or that have "000" replaced by "k".
Remove TARGET_CPU entries. Make r2000 entry use CPU_R3000.
(mips_strict_matching_cpu_name_p, mips_matching_cpu_name_p): New fns.
(mips_parse_cpu): New fn.
(mips_cpu_info_from_name, mips_cpu_info_from_cpu): Remove.
(mips_cpu_info_from_isa): Minor formatting tweak.
[gas/testsuite]
* gas/mips/mips-gp32-fp64.d,
* gas/mips/mips-gp32-fp64-pic.d: Add -mfp64.
2002-07-25 11:48:07 +02:00
|
|
|
|
/* Return true if GIVEN is the same as CANONICAL, or if it is CANONICAL
|
|
|
|
|
with a final "000" replaced by "k". Ignore case.
|
2000-12-01 22:35:38 +01:00
|
|
|
|
|
[gas/]
* doc/c-mips.texi: Remove -mcpu. Document -mabi.
* configure.in (MIPS_CPU_STRING_DEFAULT): New configuration macro.
(USE_E_MIPS_ABI_O32, MIPS_DEFAULT_64BIT): New configuration macros.
* configure, config.in: Regenerate.
* config/tc-mips.c (file_mips_abi): Rename to mips_abi.
(mips_set_options): Remove "abi" field.
(mips_opts): Update accordingly. Replace all uses of mips_opts.abi
with mips_abi.
(mips_cpu): Remove.
(mips_arch_string, mips_arch_info): New vars.
(mips_tune_string, mips_tune_info): New vars.
(ABI_NEEDS_32BIT_REGS, ABI_NEEDS_64BIT_REGS): New macros.
(HAVE_32BIT_GPRS, HAVE_32BIT_FPRS): Don't check the ABI.
(mips_isa_to_str, mips_cpu_to_str): Remove.
(mips_ip): If the selected architecture is a generic ISA rather
than a processor, only mention the ISA level in error messages.
(OPTION_MCPU): Remove.
(OPTION_FP64): New.
(md_longopts): Add -mfp64, remove -mcpu.
(mips_set_option_string): New fn.
(md_parse_option): Make -mipsN update file_mips_isa rather than
mips_opts.isa. Use mips_set_option_string to set -march or -mtune.
Don't let -mgp32 and -mfp32 change the ABI.
(show): Move to end of file. Constify string argument.
(md_show_usage): Move to the end of the file. Read available
architectures from mips_cpu_info_table.
(mips_set_architecture): New fn.
(mips_after_parse_args): Rework. Remove -mcpu handling. -mipsN
is an alias for -march=mipsN. Don't change the ABI based on other
flags. Infer the register size from the ABI as well as the
architecture. Complain about more conflicting arguments.
Unify logic with GCC.
(s_mipsset): Don't change the ABI.
(mips_elf_final_processing): Check USE_E_MIPS_ABI_O32.
(mips_cpu_info_table): Remove Generic-MIPS* entries, keeping just
"mipsN"-type entries. Remove entries that vary only in the
manufacturer's prefix, or that have "000" replaced by "k".
Remove TARGET_CPU entries. Make r2000 entry use CPU_R3000.
(mips_strict_matching_cpu_name_p, mips_matching_cpu_name_p): New fns.
(mips_parse_cpu): New fn.
(mips_cpu_info_from_name, mips_cpu_info_from_cpu): Remove.
(mips_cpu_info_from_isa): Minor formatting tweak.
[gas/testsuite]
* gas/mips/mips-gp32-fp64.d,
* gas/mips/mips-gp32-fp64-pic.d: Add -mfp64.
2002-07-25 11:48:07 +02:00
|
|
|
|
Note: this function is shared between GCC and GAS. */
|
2000-12-02 02:10:33 +01:00
|
|
|
|
|
2002-11-30 09:39:46 +01:00
|
|
|
|
static bfd_boolean
|
2003-06-30 14:44:25 +02:00
|
|
|
|
mips_strict_matching_cpu_name_p (const char *canonical, const char *given)
|
[gas/]
* doc/c-mips.texi: Remove -mcpu. Document -mabi.
* configure.in (MIPS_CPU_STRING_DEFAULT): New configuration macro.
(USE_E_MIPS_ABI_O32, MIPS_DEFAULT_64BIT): New configuration macros.
* configure, config.in: Regenerate.
* config/tc-mips.c (file_mips_abi): Rename to mips_abi.
(mips_set_options): Remove "abi" field.
(mips_opts): Update accordingly. Replace all uses of mips_opts.abi
with mips_abi.
(mips_cpu): Remove.
(mips_arch_string, mips_arch_info): New vars.
(mips_tune_string, mips_tune_info): New vars.
(ABI_NEEDS_32BIT_REGS, ABI_NEEDS_64BIT_REGS): New macros.
(HAVE_32BIT_GPRS, HAVE_32BIT_FPRS): Don't check the ABI.
(mips_isa_to_str, mips_cpu_to_str): Remove.
(mips_ip): If the selected architecture is a generic ISA rather
than a processor, only mention the ISA level in error messages.
(OPTION_MCPU): Remove.
(OPTION_FP64): New.
(md_longopts): Add -mfp64, remove -mcpu.
(mips_set_option_string): New fn.
(md_parse_option): Make -mipsN update file_mips_isa rather than
mips_opts.isa. Use mips_set_option_string to set -march or -mtune.
Don't let -mgp32 and -mfp32 change the ABI.
(show): Move to end of file. Constify string argument.
(md_show_usage): Move to the end of the file. Read available
architectures from mips_cpu_info_table.
(mips_set_architecture): New fn.
(mips_after_parse_args): Rework. Remove -mcpu handling. -mipsN
is an alias for -march=mipsN. Don't change the ABI based on other
flags. Infer the register size from the ABI as well as the
architecture. Complain about more conflicting arguments.
Unify logic with GCC.
(s_mipsset): Don't change the ABI.
(mips_elf_final_processing): Check USE_E_MIPS_ABI_O32.
(mips_cpu_info_table): Remove Generic-MIPS* entries, keeping just
"mipsN"-type entries. Remove entries that vary only in the
manufacturer's prefix, or that have "000" replaced by "k".
Remove TARGET_CPU entries. Make r2000 entry use CPU_R3000.
(mips_strict_matching_cpu_name_p, mips_matching_cpu_name_p): New fns.
(mips_parse_cpu): New fn.
(mips_cpu_info_from_name, mips_cpu_info_from_cpu): Remove.
(mips_cpu_info_from_isa): Minor formatting tweak.
[gas/testsuite]
* gas/mips/mips-gp32-fp64.d,
* gas/mips/mips-gp32-fp64-pic.d: Add -mfp64.
2002-07-25 11:48:07 +02:00
|
|
|
|
{
|
|
|
|
|
while (*given != 0 && TOLOWER (*given) == TOLOWER (*canonical))
|
|
|
|
|
given++, canonical++;
|
|
|
|
|
|
|
|
|
|
return ((*given == 0 && *canonical == 0)
|
|
|
|
|
|| (strcmp (canonical, "000") == 0 && strcasecmp (given, "k") == 0));
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
/* Return true if GIVEN matches CANONICAL, where GIVEN is a user-supplied
|
|
|
|
|
CPU name. We've traditionally allowed a lot of variation here.
|
|
|
|
|
|
|
|
|
|
Note: this function is shared between GCC and GAS. */
|
|
|
|
|
|
2002-11-30 09:39:46 +01:00
|
|
|
|
static bfd_boolean
|
2003-06-30 14:44:25 +02:00
|
|
|
|
mips_matching_cpu_name_p (const char *canonical, const char *given)
|
[gas/]
* doc/c-mips.texi: Remove -mcpu. Document -mabi.
* configure.in (MIPS_CPU_STRING_DEFAULT): New configuration macro.
(USE_E_MIPS_ABI_O32, MIPS_DEFAULT_64BIT): New configuration macros.
* configure, config.in: Regenerate.
* config/tc-mips.c (file_mips_abi): Rename to mips_abi.
(mips_set_options): Remove "abi" field.
(mips_opts): Update accordingly. Replace all uses of mips_opts.abi
with mips_abi.
(mips_cpu): Remove.
(mips_arch_string, mips_arch_info): New vars.
(mips_tune_string, mips_tune_info): New vars.
(ABI_NEEDS_32BIT_REGS, ABI_NEEDS_64BIT_REGS): New macros.
(HAVE_32BIT_GPRS, HAVE_32BIT_FPRS): Don't check the ABI.
(mips_isa_to_str, mips_cpu_to_str): Remove.
(mips_ip): If the selected architecture is a generic ISA rather
than a processor, only mention the ISA level in error messages.
(OPTION_MCPU): Remove.
(OPTION_FP64): New.
(md_longopts): Add -mfp64, remove -mcpu.
(mips_set_option_string): New fn.
(md_parse_option): Make -mipsN update file_mips_isa rather than
mips_opts.isa. Use mips_set_option_string to set -march or -mtune.
Don't let -mgp32 and -mfp32 change the ABI.
(show): Move to end of file. Constify string argument.
(md_show_usage): Move to the end of the file. Read available
architectures from mips_cpu_info_table.
(mips_set_architecture): New fn.
(mips_after_parse_args): Rework. Remove -mcpu handling. -mipsN
is an alias for -march=mipsN. Don't change the ABI based on other
flags. Infer the register size from the ABI as well as the
architecture. Complain about more conflicting arguments.
Unify logic with GCC.
(s_mipsset): Don't change the ABI.
(mips_elf_final_processing): Check USE_E_MIPS_ABI_O32.
(mips_cpu_info_table): Remove Generic-MIPS* entries, keeping just
"mipsN"-type entries. Remove entries that vary only in the
manufacturer's prefix, or that have "000" replaced by "k".
Remove TARGET_CPU entries. Make r2000 entry use CPU_R3000.
(mips_strict_matching_cpu_name_p, mips_matching_cpu_name_p): New fns.
(mips_parse_cpu): New fn.
(mips_cpu_info_from_name, mips_cpu_info_from_cpu): Remove.
(mips_cpu_info_from_isa): Minor formatting tweak.
[gas/testsuite]
* gas/mips/mips-gp32-fp64.d,
* gas/mips/mips-gp32-fp64-pic.d: Add -mfp64.
2002-07-25 11:48:07 +02:00
|
|
|
|
{
|
|
|
|
|
/* First see if the name matches exactly, or with a final "000"
|
|
|
|
|
turned into "k". */
|
|
|
|
|
if (mips_strict_matching_cpu_name_p (canonical, given))
|
2002-11-30 09:39:46 +01:00
|
|
|
|
return TRUE;
|
[gas/]
* doc/c-mips.texi: Remove -mcpu. Document -mabi.
* configure.in (MIPS_CPU_STRING_DEFAULT): New configuration macro.
(USE_E_MIPS_ABI_O32, MIPS_DEFAULT_64BIT): New configuration macros.
* configure, config.in: Regenerate.
* config/tc-mips.c (file_mips_abi): Rename to mips_abi.
(mips_set_options): Remove "abi" field.
(mips_opts): Update accordingly. Replace all uses of mips_opts.abi
with mips_abi.
(mips_cpu): Remove.
(mips_arch_string, mips_arch_info): New vars.
(mips_tune_string, mips_tune_info): New vars.
(ABI_NEEDS_32BIT_REGS, ABI_NEEDS_64BIT_REGS): New macros.
(HAVE_32BIT_GPRS, HAVE_32BIT_FPRS): Don't check the ABI.
(mips_isa_to_str, mips_cpu_to_str): Remove.
(mips_ip): If the selected architecture is a generic ISA rather
than a processor, only mention the ISA level in error messages.
(OPTION_MCPU): Remove.
(OPTION_FP64): New.
(md_longopts): Add -mfp64, remove -mcpu.
(mips_set_option_string): New fn.
(md_parse_option): Make -mipsN update file_mips_isa rather than
mips_opts.isa. Use mips_set_option_string to set -march or -mtune.
Don't let -mgp32 and -mfp32 change the ABI.
(show): Move to end of file. Constify string argument.
(md_show_usage): Move to the end of the file. Read available
architectures from mips_cpu_info_table.
(mips_set_architecture): New fn.
(mips_after_parse_args): Rework. Remove -mcpu handling. -mipsN
is an alias for -march=mipsN. Don't change the ABI based on other
flags. Infer the register size from the ABI as well as the
architecture. Complain about more conflicting arguments.
Unify logic with GCC.
(s_mipsset): Don't change the ABI.
(mips_elf_final_processing): Check USE_E_MIPS_ABI_O32.
(mips_cpu_info_table): Remove Generic-MIPS* entries, keeping just
"mipsN"-type entries. Remove entries that vary only in the
manufacturer's prefix, or that have "000" replaced by "k".
Remove TARGET_CPU entries. Make r2000 entry use CPU_R3000.
(mips_strict_matching_cpu_name_p, mips_matching_cpu_name_p): New fns.
(mips_parse_cpu): New fn.
(mips_cpu_info_from_name, mips_cpu_info_from_cpu): Remove.
(mips_cpu_info_from_isa): Minor formatting tweak.
[gas/testsuite]
* gas/mips/mips-gp32-fp64.d,
* gas/mips/mips-gp32-fp64-pic.d: Add -mfp64.
2002-07-25 11:48:07 +02:00
|
|
|
|
|
|
|
|
|
/* If not, try comparing based on numerical designation alone.
|
|
|
|
|
See if GIVEN is an unadorned number, or 'r' followed by a number. */
|
|
|
|
|
if (TOLOWER (*given) == 'r')
|
|
|
|
|
given++;
|
|
|
|
|
if (!ISDIGIT (*given))
|
2002-11-30 09:39:46 +01:00
|
|
|
|
return FALSE;
|
[gas/]
* doc/c-mips.texi: Remove -mcpu. Document -mabi.
* configure.in (MIPS_CPU_STRING_DEFAULT): New configuration macro.
(USE_E_MIPS_ABI_O32, MIPS_DEFAULT_64BIT): New configuration macros.
* configure, config.in: Regenerate.
* config/tc-mips.c (file_mips_abi): Rename to mips_abi.
(mips_set_options): Remove "abi" field.
(mips_opts): Update accordingly. Replace all uses of mips_opts.abi
with mips_abi.
(mips_cpu): Remove.
(mips_arch_string, mips_arch_info): New vars.
(mips_tune_string, mips_tune_info): New vars.
(ABI_NEEDS_32BIT_REGS, ABI_NEEDS_64BIT_REGS): New macros.
(HAVE_32BIT_GPRS, HAVE_32BIT_FPRS): Don't check the ABI.
(mips_isa_to_str, mips_cpu_to_str): Remove.
(mips_ip): If the selected architecture is a generic ISA rather
than a processor, only mention the ISA level in error messages.
(OPTION_MCPU): Remove.
(OPTION_FP64): New.
(md_longopts): Add -mfp64, remove -mcpu.
(mips_set_option_string): New fn.
(md_parse_option): Make -mipsN update file_mips_isa rather than
mips_opts.isa. Use mips_set_option_string to set -march or -mtune.
Don't let -mgp32 and -mfp32 change the ABI.
(show): Move to end of file. Constify string argument.
(md_show_usage): Move to the end of the file. Read available
architectures from mips_cpu_info_table.
(mips_set_architecture): New fn.
(mips_after_parse_args): Rework. Remove -mcpu handling. -mipsN
is an alias for -march=mipsN. Don't change the ABI based on other
flags. Infer the register size from the ABI as well as the
architecture. Complain about more conflicting arguments.
Unify logic with GCC.
(s_mipsset): Don't change the ABI.
(mips_elf_final_processing): Check USE_E_MIPS_ABI_O32.
(mips_cpu_info_table): Remove Generic-MIPS* entries, keeping just
"mipsN"-type entries. Remove entries that vary only in the
manufacturer's prefix, or that have "000" replaced by "k".
Remove TARGET_CPU entries. Make r2000 entry use CPU_R3000.
(mips_strict_matching_cpu_name_p, mips_matching_cpu_name_p): New fns.
(mips_parse_cpu): New fn.
(mips_cpu_info_from_name, mips_cpu_info_from_cpu): Remove.
(mips_cpu_info_from_isa): Minor formatting tweak.
[gas/testsuite]
* gas/mips/mips-gp32-fp64.d,
* gas/mips/mips-gp32-fp64-pic.d: Add -mfp64.
2002-07-25 11:48:07 +02:00
|
|
|
|
|
|
|
|
|
/* Skip over some well-known prefixes in the canonical name,
|
|
|
|
|
hoping to find a number there too. */
|
|
|
|
|
if (TOLOWER (canonical[0]) == 'v' && TOLOWER (canonical[1]) == 'r')
|
|
|
|
|
canonical += 2;
|
|
|
|
|
else if (TOLOWER (canonical[0]) == 'r' && TOLOWER (canonical[1]) == 'm')
|
|
|
|
|
canonical += 2;
|
|
|
|
|
else if (TOLOWER (canonical[0]) == 'r')
|
|
|
|
|
canonical += 1;
|
|
|
|
|
|
|
|
|
|
return mips_strict_matching_cpu_name_p (canonical, given);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
/* Parse an option that takes the name of a processor as its argument.
|
|
|
|
|
OPTION is the name of the option and CPU_STRING is the argument.
|
|
|
|
|
Return the corresponding processor enumeration if the CPU_STRING is
|
|
|
|
|
recognized, otherwise report an error and return null.
|
|
|
|
|
|
|
|
|
|
A similar function exists in GCC. */
|
2000-12-01 22:35:38 +01:00
|
|
|
|
|
|
|
|
|
static const struct mips_cpu_info *
|
2003-06-30 14:44:25 +02:00
|
|
|
|
mips_parse_cpu (const char *option, const char *cpu_string)
|
2000-12-01 22:35:38 +01:00
|
|
|
|
{
|
[gas/]
* doc/c-mips.texi: Remove -mcpu. Document -mabi.
* configure.in (MIPS_CPU_STRING_DEFAULT): New configuration macro.
(USE_E_MIPS_ABI_O32, MIPS_DEFAULT_64BIT): New configuration macros.
* configure, config.in: Regenerate.
* config/tc-mips.c (file_mips_abi): Rename to mips_abi.
(mips_set_options): Remove "abi" field.
(mips_opts): Update accordingly. Replace all uses of mips_opts.abi
with mips_abi.
(mips_cpu): Remove.
(mips_arch_string, mips_arch_info): New vars.
(mips_tune_string, mips_tune_info): New vars.
(ABI_NEEDS_32BIT_REGS, ABI_NEEDS_64BIT_REGS): New macros.
(HAVE_32BIT_GPRS, HAVE_32BIT_FPRS): Don't check the ABI.
(mips_isa_to_str, mips_cpu_to_str): Remove.
(mips_ip): If the selected architecture is a generic ISA rather
than a processor, only mention the ISA level in error messages.
(OPTION_MCPU): Remove.
(OPTION_FP64): New.
(md_longopts): Add -mfp64, remove -mcpu.
(mips_set_option_string): New fn.
(md_parse_option): Make -mipsN update file_mips_isa rather than
mips_opts.isa. Use mips_set_option_string to set -march or -mtune.
Don't let -mgp32 and -mfp32 change the ABI.
(show): Move to end of file. Constify string argument.
(md_show_usage): Move to the end of the file. Read available
architectures from mips_cpu_info_table.
(mips_set_architecture): New fn.
(mips_after_parse_args): Rework. Remove -mcpu handling. -mipsN
is an alias for -march=mipsN. Don't change the ABI based on other
flags. Infer the register size from the ABI as well as the
architecture. Complain about more conflicting arguments.
Unify logic with GCC.
(s_mipsset): Don't change the ABI.
(mips_elf_final_processing): Check USE_E_MIPS_ABI_O32.
(mips_cpu_info_table): Remove Generic-MIPS* entries, keeping just
"mipsN"-type entries. Remove entries that vary only in the
manufacturer's prefix, or that have "000" replaced by "k".
Remove TARGET_CPU entries. Make r2000 entry use CPU_R3000.
(mips_strict_matching_cpu_name_p, mips_matching_cpu_name_p): New fns.
(mips_parse_cpu): New fn.
(mips_cpu_info_from_name, mips_cpu_info_from_cpu): Remove.
(mips_cpu_info_from_isa): Minor formatting tweak.
[gas/testsuite]
* gas/mips/mips-gp32-fp64.d,
* gas/mips/mips-gp32-fp64-pic.d: Add -mfp64.
2002-07-25 11:48:07 +02:00
|
|
|
|
const struct mips_cpu_info *p;
|
2000-12-01 22:35:38 +01:00
|
|
|
|
|
[gas/]
* doc/c-mips.texi: Remove -mcpu. Document -mabi.
* configure.in (MIPS_CPU_STRING_DEFAULT): New configuration macro.
(USE_E_MIPS_ABI_O32, MIPS_DEFAULT_64BIT): New configuration macros.
* configure, config.in: Regenerate.
* config/tc-mips.c (file_mips_abi): Rename to mips_abi.
(mips_set_options): Remove "abi" field.
(mips_opts): Update accordingly. Replace all uses of mips_opts.abi
with mips_abi.
(mips_cpu): Remove.
(mips_arch_string, mips_arch_info): New vars.
(mips_tune_string, mips_tune_info): New vars.
(ABI_NEEDS_32BIT_REGS, ABI_NEEDS_64BIT_REGS): New macros.
(HAVE_32BIT_GPRS, HAVE_32BIT_FPRS): Don't check the ABI.
(mips_isa_to_str, mips_cpu_to_str): Remove.
(mips_ip): If the selected architecture is a generic ISA rather
than a processor, only mention the ISA level in error messages.
(OPTION_MCPU): Remove.
(OPTION_FP64): New.
(md_longopts): Add -mfp64, remove -mcpu.
(mips_set_option_string): New fn.
(md_parse_option): Make -mipsN update file_mips_isa rather than
mips_opts.isa. Use mips_set_option_string to set -march or -mtune.
Don't let -mgp32 and -mfp32 change the ABI.
(show): Move to end of file. Constify string argument.
(md_show_usage): Move to the end of the file. Read available
architectures from mips_cpu_info_table.
(mips_set_architecture): New fn.
(mips_after_parse_args): Rework. Remove -mcpu handling. -mipsN
is an alias for -march=mipsN. Don't change the ABI based on other
flags. Infer the register size from the ABI as well as the
architecture. Complain about more conflicting arguments.
Unify logic with GCC.
(s_mipsset): Don't change the ABI.
(mips_elf_final_processing): Check USE_E_MIPS_ABI_O32.
(mips_cpu_info_table): Remove Generic-MIPS* entries, keeping just
"mipsN"-type entries. Remove entries that vary only in the
manufacturer's prefix, or that have "000" replaced by "k".
Remove TARGET_CPU entries. Make r2000 entry use CPU_R3000.
(mips_strict_matching_cpu_name_p, mips_matching_cpu_name_p): New fns.
(mips_parse_cpu): New fn.
(mips_cpu_info_from_name, mips_cpu_info_from_cpu): Remove.
(mips_cpu_info_from_isa): Minor formatting tweak.
[gas/testsuite]
* gas/mips/mips-gp32-fp64.d,
* gas/mips/mips-gp32-fp64-pic.d: Add -mfp64.
2002-07-25 11:48:07 +02:00
|
|
|
|
/* 'from-abi' selects the most compatible architecture for the given
|
|
|
|
|
ABI: MIPS I for 32-bit ABIs and MIPS III for 64-bit ABIs. For the
|
|
|
|
|
EABIs, we have to decide whether we're using the 32-bit or 64-bit
|
|
|
|
|
version. Look first at the -mgp options, if given, otherwise base
|
|
|
|
|
the choice on MIPS_DEFAULT_64BIT.
|
2000-12-01 22:35:38 +01:00
|
|
|
|
|
[gas/]
* doc/c-mips.texi: Remove -mcpu. Document -mabi.
* configure.in (MIPS_CPU_STRING_DEFAULT): New configuration macro.
(USE_E_MIPS_ABI_O32, MIPS_DEFAULT_64BIT): New configuration macros.
* configure, config.in: Regenerate.
* config/tc-mips.c (file_mips_abi): Rename to mips_abi.
(mips_set_options): Remove "abi" field.
(mips_opts): Update accordingly. Replace all uses of mips_opts.abi
with mips_abi.
(mips_cpu): Remove.
(mips_arch_string, mips_arch_info): New vars.
(mips_tune_string, mips_tune_info): New vars.
(ABI_NEEDS_32BIT_REGS, ABI_NEEDS_64BIT_REGS): New macros.
(HAVE_32BIT_GPRS, HAVE_32BIT_FPRS): Don't check the ABI.
(mips_isa_to_str, mips_cpu_to_str): Remove.
(mips_ip): If the selected architecture is a generic ISA rather
than a processor, only mention the ISA level in error messages.
(OPTION_MCPU): Remove.
(OPTION_FP64): New.
(md_longopts): Add -mfp64, remove -mcpu.
(mips_set_option_string): New fn.
(md_parse_option): Make -mipsN update file_mips_isa rather than
mips_opts.isa. Use mips_set_option_string to set -march or -mtune.
Don't let -mgp32 and -mfp32 change the ABI.
(show): Move to end of file. Constify string argument.
(md_show_usage): Move to the end of the file. Read available
architectures from mips_cpu_info_table.
(mips_set_architecture): New fn.
(mips_after_parse_args): Rework. Remove -mcpu handling. -mipsN
is an alias for -march=mipsN. Don't change the ABI based on other
flags. Infer the register size from the ABI as well as the
architecture. Complain about more conflicting arguments.
Unify logic with GCC.
(s_mipsset): Don't change the ABI.
(mips_elf_final_processing): Check USE_E_MIPS_ABI_O32.
(mips_cpu_info_table): Remove Generic-MIPS* entries, keeping just
"mipsN"-type entries. Remove entries that vary only in the
manufacturer's prefix, or that have "000" replaced by "k".
Remove TARGET_CPU entries. Make r2000 entry use CPU_R3000.
(mips_strict_matching_cpu_name_p, mips_matching_cpu_name_p): New fns.
(mips_parse_cpu): New fn.
(mips_cpu_info_from_name, mips_cpu_info_from_cpu): Remove.
(mips_cpu_info_from_isa): Minor formatting tweak.
[gas/testsuite]
* gas/mips/mips-gp32-fp64.d,
* gas/mips/mips-gp32-fp64-pic.d: Add -mfp64.
2002-07-25 11:48:07 +02:00
|
|
|
|
Treat NO_ABI like the EABIs. One reason to do this is that the
|
|
|
|
|
plain 'mips' and 'mips64' configs have 'from-abi' as their default
|
|
|
|
|
architecture. This code picks MIPS I for 'mips' and MIPS III for
|
|
|
|
|
'mips64', just as we did in the days before 'from-abi'. */
|
|
|
|
|
if (strcasecmp (cpu_string, "from-abi") == 0)
|
|
|
|
|
{
|
|
|
|
|
if (ABI_NEEDS_32BIT_REGS (mips_abi))
|
|
|
|
|
return mips_cpu_info_from_isa (ISA_MIPS1);
|
|
|
|
|
|
|
|
|
|
if (ABI_NEEDS_64BIT_REGS (mips_abi))
|
|
|
|
|
return mips_cpu_info_from_isa (ISA_MIPS3);
|
|
|
|
|
|
|
|
|
|
if (file_mips_gp32 >= 0)
|
|
|
|
|
return mips_cpu_info_from_isa (file_mips_gp32 ? ISA_MIPS1 : ISA_MIPS3);
|
|
|
|
|
|
|
|
|
|
return mips_cpu_info_from_isa (MIPS_DEFAULT_64BIT
|
|
|
|
|
? ISA_MIPS3
|
|
|
|
|
: ISA_MIPS1);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/* 'default' has traditionally been a no-op. Probably not very useful. */
|
|
|
|
|
if (strcasecmp (cpu_string, "default") == 0)
|
|
|
|
|
return 0;
|
|
|
|
|
|
|
|
|
|
for (p = mips_cpu_info_table; p->name != 0; p++)
|
|
|
|
|
if (mips_matching_cpu_name_p (p->name, cpu_string))
|
|
|
|
|
return p;
|
|
|
|
|
|
|
|
|
|
as_bad ("Bad value (%s) for %s", cpu_string, option);
|
|
|
|
|
return 0;
|
2000-12-01 22:35:38 +01:00
|
|
|
|
}
|
|
|
|
|
|
[gas/]
* doc/c-mips.texi: Remove -mcpu. Document -mabi.
* configure.in (MIPS_CPU_STRING_DEFAULT): New configuration macro.
(USE_E_MIPS_ABI_O32, MIPS_DEFAULT_64BIT): New configuration macros.
* configure, config.in: Regenerate.
* config/tc-mips.c (file_mips_abi): Rename to mips_abi.
(mips_set_options): Remove "abi" field.
(mips_opts): Update accordingly. Replace all uses of mips_opts.abi
with mips_abi.
(mips_cpu): Remove.
(mips_arch_string, mips_arch_info): New vars.
(mips_tune_string, mips_tune_info): New vars.
(ABI_NEEDS_32BIT_REGS, ABI_NEEDS_64BIT_REGS): New macros.
(HAVE_32BIT_GPRS, HAVE_32BIT_FPRS): Don't check the ABI.
(mips_isa_to_str, mips_cpu_to_str): Remove.
(mips_ip): If the selected architecture is a generic ISA rather
than a processor, only mention the ISA level in error messages.
(OPTION_MCPU): Remove.
(OPTION_FP64): New.
(md_longopts): Add -mfp64, remove -mcpu.
(mips_set_option_string): New fn.
(md_parse_option): Make -mipsN update file_mips_isa rather than
mips_opts.isa. Use mips_set_option_string to set -march or -mtune.
Don't let -mgp32 and -mfp32 change the ABI.
(show): Move to end of file. Constify string argument.
(md_show_usage): Move to the end of the file. Read available
architectures from mips_cpu_info_table.
(mips_set_architecture): New fn.
(mips_after_parse_args): Rework. Remove -mcpu handling. -mipsN
is an alias for -march=mipsN. Don't change the ABI based on other
flags. Infer the register size from the ABI as well as the
architecture. Complain about more conflicting arguments.
Unify logic with GCC.
(s_mipsset): Don't change the ABI.
(mips_elf_final_processing): Check USE_E_MIPS_ABI_O32.
(mips_cpu_info_table): Remove Generic-MIPS* entries, keeping just
"mipsN"-type entries. Remove entries that vary only in the
manufacturer's prefix, or that have "000" replaced by "k".
Remove TARGET_CPU entries. Make r2000 entry use CPU_R3000.
(mips_strict_matching_cpu_name_p, mips_matching_cpu_name_p): New fns.
(mips_parse_cpu): New fn.
(mips_cpu_info_from_name, mips_cpu_info_from_cpu): Remove.
(mips_cpu_info_from_isa): Minor formatting tweak.
[gas/testsuite]
* gas/mips/mips-gp32-fp64.d,
* gas/mips/mips-gp32-fp64-pic.d: Add -mfp64.
2002-07-25 11:48:07 +02:00
|
|
|
|
/* Return the canonical processor information for ISA (a member of the
|
|
|
|
|
ISA_MIPS* enumeration). */
|
|
|
|
|
|
2000-12-01 22:35:38 +01:00
|
|
|
|
static const struct mips_cpu_info *
|
2003-06-30 14:44:25 +02:00
|
|
|
|
mips_cpu_info_from_isa (int isa)
|
2000-12-01 22:35:38 +01:00
|
|
|
|
{
|
|
|
|
|
int i;
|
|
|
|
|
|
|
|
|
|
for (i = 0; mips_cpu_info_table[i].name != NULL; i++)
|
|
|
|
|
if (mips_cpu_info_table[i].is_isa
|
[gas/]
* doc/c-mips.texi: Remove -mcpu. Document -mabi.
* configure.in (MIPS_CPU_STRING_DEFAULT): New configuration macro.
(USE_E_MIPS_ABI_O32, MIPS_DEFAULT_64BIT): New configuration macros.
* configure, config.in: Regenerate.
* config/tc-mips.c (file_mips_abi): Rename to mips_abi.
(mips_set_options): Remove "abi" field.
(mips_opts): Update accordingly. Replace all uses of mips_opts.abi
with mips_abi.
(mips_cpu): Remove.
(mips_arch_string, mips_arch_info): New vars.
(mips_tune_string, mips_tune_info): New vars.
(ABI_NEEDS_32BIT_REGS, ABI_NEEDS_64BIT_REGS): New macros.
(HAVE_32BIT_GPRS, HAVE_32BIT_FPRS): Don't check the ABI.
(mips_isa_to_str, mips_cpu_to_str): Remove.
(mips_ip): If the selected architecture is a generic ISA rather
than a processor, only mention the ISA level in error messages.
(OPTION_MCPU): Remove.
(OPTION_FP64): New.
(md_longopts): Add -mfp64, remove -mcpu.
(mips_set_option_string): New fn.
(md_parse_option): Make -mipsN update file_mips_isa rather than
mips_opts.isa. Use mips_set_option_string to set -march or -mtune.
Don't let -mgp32 and -mfp32 change the ABI.
(show): Move to end of file. Constify string argument.
(md_show_usage): Move to the end of the file. Read available
architectures from mips_cpu_info_table.
(mips_set_architecture): New fn.
(mips_after_parse_args): Rework. Remove -mcpu handling. -mipsN
is an alias for -march=mipsN. Don't change the ABI based on other
flags. Infer the register size from the ABI as well as the
architecture. Complain about more conflicting arguments.
Unify logic with GCC.
(s_mipsset): Don't change the ABI.
(mips_elf_final_processing): Check USE_E_MIPS_ABI_O32.
(mips_cpu_info_table): Remove Generic-MIPS* entries, keeping just
"mipsN"-type entries. Remove entries that vary only in the
manufacturer's prefix, or that have "000" replaced by "k".
Remove TARGET_CPU entries. Make r2000 entry use CPU_R3000.
(mips_strict_matching_cpu_name_p, mips_matching_cpu_name_p): New fns.
(mips_parse_cpu): New fn.
(mips_cpu_info_from_name, mips_cpu_info_from_cpu): Remove.
(mips_cpu_info_from_isa): Minor formatting tweak.
[gas/testsuite]
* gas/mips/mips-gp32-fp64.d,
* gas/mips/mips-gp32-fp64-pic.d: Add -mfp64.
2002-07-25 11:48:07 +02:00
|
|
|
|
&& isa == mips_cpu_info_table[i].isa)
|
2000-12-01 22:35:38 +01:00
|
|
|
|
return (&mips_cpu_info_table[i]);
|
|
|
|
|
|
2000-12-12 20:29:24 +01:00
|
|
|
|
return NULL;
|
2000-12-01 22:35:38 +01:00
|
|
|
|
}
|
2003-06-29 21:41:33 +02:00
|
|
|
|
|
|
|
|
|
static const struct mips_cpu_info *
|
2003-06-30 14:44:25 +02:00
|
|
|
|
mips_cpu_info_from_arch (int arch)
|
2003-06-29 21:41:33 +02:00
|
|
|
|
{
|
|
|
|
|
int i;
|
|
|
|
|
|
|
|
|
|
for (i = 0; mips_cpu_info_table[i].name != NULL; i++)
|
|
|
|
|
if (arch == mips_cpu_info_table[i].cpu)
|
|
|
|
|
return (&mips_cpu_info_table[i]);
|
|
|
|
|
|
|
|
|
|
return NULL;
|
|
|
|
|
}
|
[gas/]
* doc/c-mips.texi: Remove -mcpu. Document -mabi.
* configure.in (MIPS_CPU_STRING_DEFAULT): New configuration macro.
(USE_E_MIPS_ABI_O32, MIPS_DEFAULT_64BIT): New configuration macros.
* configure, config.in: Regenerate.
* config/tc-mips.c (file_mips_abi): Rename to mips_abi.
(mips_set_options): Remove "abi" field.
(mips_opts): Update accordingly. Replace all uses of mips_opts.abi
with mips_abi.
(mips_cpu): Remove.
(mips_arch_string, mips_arch_info): New vars.
(mips_tune_string, mips_tune_info): New vars.
(ABI_NEEDS_32BIT_REGS, ABI_NEEDS_64BIT_REGS): New macros.
(HAVE_32BIT_GPRS, HAVE_32BIT_FPRS): Don't check the ABI.
(mips_isa_to_str, mips_cpu_to_str): Remove.
(mips_ip): If the selected architecture is a generic ISA rather
than a processor, only mention the ISA level in error messages.
(OPTION_MCPU): Remove.
(OPTION_FP64): New.
(md_longopts): Add -mfp64, remove -mcpu.
(mips_set_option_string): New fn.
(md_parse_option): Make -mipsN update file_mips_isa rather than
mips_opts.isa. Use mips_set_option_string to set -march or -mtune.
Don't let -mgp32 and -mfp32 change the ABI.
(show): Move to end of file. Constify string argument.
(md_show_usage): Move to the end of the file. Read available
architectures from mips_cpu_info_table.
(mips_set_architecture): New fn.
(mips_after_parse_args): Rework. Remove -mcpu handling. -mipsN
is an alias for -march=mipsN. Don't change the ABI based on other
flags. Infer the register size from the ABI as well as the
architecture. Complain about more conflicting arguments.
Unify logic with GCC.
(s_mipsset): Don't change the ABI.
(mips_elf_final_processing): Check USE_E_MIPS_ABI_O32.
(mips_cpu_info_table): Remove Generic-MIPS* entries, keeping just
"mipsN"-type entries. Remove entries that vary only in the
manufacturer's prefix, or that have "000" replaced by "k".
Remove TARGET_CPU entries. Make r2000 entry use CPU_R3000.
(mips_strict_matching_cpu_name_p, mips_matching_cpu_name_p): New fns.
(mips_parse_cpu): New fn.
(mips_cpu_info_from_name, mips_cpu_info_from_cpu): Remove.
(mips_cpu_info_from_isa): Minor formatting tweak.
[gas/testsuite]
* gas/mips/mips-gp32-fp64.d,
* gas/mips/mips-gp32-fp64-pic.d: Add -mfp64.
2002-07-25 11:48:07 +02:00
|
|
|
|
|
|
|
|
|
static void
|
2003-06-30 14:44:25 +02:00
|
|
|
|
show (FILE *stream, const char *string, int *col_p, int *first_p)
|
[gas/]
* doc/c-mips.texi: Remove -mcpu. Document -mabi.
* configure.in (MIPS_CPU_STRING_DEFAULT): New configuration macro.
(USE_E_MIPS_ABI_O32, MIPS_DEFAULT_64BIT): New configuration macros.
* configure, config.in: Regenerate.
* config/tc-mips.c (file_mips_abi): Rename to mips_abi.
(mips_set_options): Remove "abi" field.
(mips_opts): Update accordingly. Replace all uses of mips_opts.abi
with mips_abi.
(mips_cpu): Remove.
(mips_arch_string, mips_arch_info): New vars.
(mips_tune_string, mips_tune_info): New vars.
(ABI_NEEDS_32BIT_REGS, ABI_NEEDS_64BIT_REGS): New macros.
(HAVE_32BIT_GPRS, HAVE_32BIT_FPRS): Don't check the ABI.
(mips_isa_to_str, mips_cpu_to_str): Remove.
(mips_ip): If the selected architecture is a generic ISA rather
than a processor, only mention the ISA level in error messages.
(OPTION_MCPU): Remove.
(OPTION_FP64): New.
(md_longopts): Add -mfp64, remove -mcpu.
(mips_set_option_string): New fn.
(md_parse_option): Make -mipsN update file_mips_isa rather than
mips_opts.isa. Use mips_set_option_string to set -march or -mtune.
Don't let -mgp32 and -mfp32 change the ABI.
(show): Move to end of file. Constify string argument.
(md_show_usage): Move to the end of the file. Read available
architectures from mips_cpu_info_table.
(mips_set_architecture): New fn.
(mips_after_parse_args): Rework. Remove -mcpu handling. -mipsN
is an alias for -march=mipsN. Don't change the ABI based on other
flags. Infer the register size from the ABI as well as the
architecture. Complain about more conflicting arguments.
Unify logic with GCC.
(s_mipsset): Don't change the ABI.
(mips_elf_final_processing): Check USE_E_MIPS_ABI_O32.
(mips_cpu_info_table): Remove Generic-MIPS* entries, keeping just
"mipsN"-type entries. Remove entries that vary only in the
manufacturer's prefix, or that have "000" replaced by "k".
Remove TARGET_CPU entries. Make r2000 entry use CPU_R3000.
(mips_strict_matching_cpu_name_p, mips_matching_cpu_name_p): New fns.
(mips_parse_cpu): New fn.
(mips_cpu_info_from_name, mips_cpu_info_from_cpu): Remove.
(mips_cpu_info_from_isa): Minor formatting tweak.
[gas/testsuite]
* gas/mips/mips-gp32-fp64.d,
* gas/mips/mips-gp32-fp64-pic.d: Add -mfp64.
2002-07-25 11:48:07 +02:00
|
|
|
|
{
|
|
|
|
|
if (*first_p)
|
|
|
|
|
{
|
|
|
|
|
fprintf (stream, "%24s", "");
|
|
|
|
|
*col_p = 24;
|
|
|
|
|
}
|
|
|
|
|
else
|
|
|
|
|
{
|
|
|
|
|
fprintf (stream, ", ");
|
|
|
|
|
*col_p += 2;
|
|
|
|
|
}
|
2000-12-01 22:35:38 +01:00
|
|
|
|
|
[gas/]
* doc/c-mips.texi: Remove -mcpu. Document -mabi.
* configure.in (MIPS_CPU_STRING_DEFAULT): New configuration macro.
(USE_E_MIPS_ABI_O32, MIPS_DEFAULT_64BIT): New configuration macros.
* configure, config.in: Regenerate.
* config/tc-mips.c (file_mips_abi): Rename to mips_abi.
(mips_set_options): Remove "abi" field.
(mips_opts): Update accordingly. Replace all uses of mips_opts.abi
with mips_abi.
(mips_cpu): Remove.
(mips_arch_string, mips_arch_info): New vars.
(mips_tune_string, mips_tune_info): New vars.
(ABI_NEEDS_32BIT_REGS, ABI_NEEDS_64BIT_REGS): New macros.
(HAVE_32BIT_GPRS, HAVE_32BIT_FPRS): Don't check the ABI.
(mips_isa_to_str, mips_cpu_to_str): Remove.
(mips_ip): If the selected architecture is a generic ISA rather
than a processor, only mention the ISA level in error messages.
(OPTION_MCPU): Remove.
(OPTION_FP64): New.
(md_longopts): Add -mfp64, remove -mcpu.
(mips_set_option_string): New fn.
(md_parse_option): Make -mipsN update file_mips_isa rather than
mips_opts.isa. Use mips_set_option_string to set -march or -mtune.
Don't let -mgp32 and -mfp32 change the ABI.
(show): Move to end of file. Constify string argument.
(md_show_usage): Move to the end of the file. Read available
architectures from mips_cpu_info_table.
(mips_set_architecture): New fn.
(mips_after_parse_args): Rework. Remove -mcpu handling. -mipsN
is an alias for -march=mipsN. Don't change the ABI based on other
flags. Infer the register size from the ABI as well as the
architecture. Complain about more conflicting arguments.
Unify logic with GCC.
(s_mipsset): Don't change the ABI.
(mips_elf_final_processing): Check USE_E_MIPS_ABI_O32.
(mips_cpu_info_table): Remove Generic-MIPS* entries, keeping just
"mipsN"-type entries. Remove entries that vary only in the
manufacturer's prefix, or that have "000" replaced by "k".
Remove TARGET_CPU entries. Make r2000 entry use CPU_R3000.
(mips_strict_matching_cpu_name_p, mips_matching_cpu_name_p): New fns.
(mips_parse_cpu): New fn.
(mips_cpu_info_from_name, mips_cpu_info_from_cpu): Remove.
(mips_cpu_info_from_isa): Minor formatting tweak.
[gas/testsuite]
* gas/mips/mips-gp32-fp64.d,
* gas/mips/mips-gp32-fp64-pic.d: Add -mfp64.
2002-07-25 11:48:07 +02:00
|
|
|
|
if (*col_p + strlen (string) > 72)
|
|
|
|
|
{
|
|
|
|
|
fprintf (stream, "\n%24s", "");
|
|
|
|
|
*col_p = 24;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
fprintf (stream, "%s", string);
|
|
|
|
|
*col_p += strlen (string);
|
|
|
|
|
|
|
|
|
|
*first_p = 0;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
void
|
2003-06-30 14:44:25 +02:00
|
|
|
|
md_show_usage (FILE *stream)
|
2000-12-01 22:35:38 +01:00
|
|
|
|
{
|
[gas/]
* doc/c-mips.texi: Remove -mcpu. Document -mabi.
* configure.in (MIPS_CPU_STRING_DEFAULT): New configuration macro.
(USE_E_MIPS_ABI_O32, MIPS_DEFAULT_64BIT): New configuration macros.
* configure, config.in: Regenerate.
* config/tc-mips.c (file_mips_abi): Rename to mips_abi.
(mips_set_options): Remove "abi" field.
(mips_opts): Update accordingly. Replace all uses of mips_opts.abi
with mips_abi.
(mips_cpu): Remove.
(mips_arch_string, mips_arch_info): New vars.
(mips_tune_string, mips_tune_info): New vars.
(ABI_NEEDS_32BIT_REGS, ABI_NEEDS_64BIT_REGS): New macros.
(HAVE_32BIT_GPRS, HAVE_32BIT_FPRS): Don't check the ABI.
(mips_isa_to_str, mips_cpu_to_str): Remove.
(mips_ip): If the selected architecture is a generic ISA rather
than a processor, only mention the ISA level in error messages.
(OPTION_MCPU): Remove.
(OPTION_FP64): New.
(md_longopts): Add -mfp64, remove -mcpu.
(mips_set_option_string): New fn.
(md_parse_option): Make -mipsN update file_mips_isa rather than
mips_opts.isa. Use mips_set_option_string to set -march or -mtune.
Don't let -mgp32 and -mfp32 change the ABI.
(show): Move to end of file. Constify string argument.
(md_show_usage): Move to the end of the file. Read available
architectures from mips_cpu_info_table.
(mips_set_architecture): New fn.
(mips_after_parse_args): Rework. Remove -mcpu handling. -mipsN
is an alias for -march=mipsN. Don't change the ABI based on other
flags. Infer the register size from the ABI as well as the
architecture. Complain about more conflicting arguments.
Unify logic with GCC.
(s_mipsset): Don't change the ABI.
(mips_elf_final_processing): Check USE_E_MIPS_ABI_O32.
(mips_cpu_info_table): Remove Generic-MIPS* entries, keeping just
"mipsN"-type entries. Remove entries that vary only in the
manufacturer's prefix, or that have "000" replaced by "k".
Remove TARGET_CPU entries. Make r2000 entry use CPU_R3000.
(mips_strict_matching_cpu_name_p, mips_matching_cpu_name_p): New fns.
(mips_parse_cpu): New fn.
(mips_cpu_info_from_name, mips_cpu_info_from_cpu): Remove.
(mips_cpu_info_from_isa): Minor formatting tweak.
[gas/testsuite]
* gas/mips/mips-gp32-fp64.d,
* gas/mips/mips-gp32-fp64-pic.d: Add -mfp64.
2002-07-25 11:48:07 +02:00
|
|
|
|
int column, first;
|
|
|
|
|
size_t i;
|
|
|
|
|
|
|
|
|
|
fprintf (stream, _("\
|
|
|
|
|
MIPS options:\n\
|
|
|
|
|
-membedded-pic generate embedded position independent code\n\
|
|
|
|
|
-EB generate big endian output\n\
|
|
|
|
|
-EL generate little endian output\n\
|
|
|
|
|
-g, -g2 do not remove unneeded NOPs or swap branches\n\
|
|
|
|
|
-G NUM allow referencing objects up to NUM bytes\n\
|
|
|
|
|
implicitly with the gp register [default 8]\n"));
|
|
|
|
|
fprintf (stream, _("\
|
|
|
|
|
-mips1 generate MIPS ISA I instructions\n\
|
|
|
|
|
-mips2 generate MIPS ISA II instructions\n\
|
|
|
|
|
-mips3 generate MIPS ISA III instructions\n\
|
|
|
|
|
-mips4 generate MIPS ISA IV instructions\n\
|
|
|
|
|
-mips5 generate MIPS ISA V instructions\n\
|
|
|
|
|
-mips32 generate MIPS32 ISA instructions\n\
|
[ bfd/ChangeLog ]
2002-12-30 Chris Demetriou <cgd@broadcom.com>
* aoutx.h (NAME(aout,machine_type)): Add bfd_mach_mipsisa32r2 case.
* archures.c (bfd_mach_mipsisa32r2): New define.
* bfd-in2.h: Regenerate.
* cpu-mips.c (I_mipsisa32r2): New enum value.
(arch_info_struct): Add entry for I_mipsisa32r2.
* elfxx-mips.c (elf_mips_isa, _bfd_elf_mips_mach)
(_bfd_mips_elf_print_private_bfd_data): Handle E_MIPS_ARCH_32R2.
(_bfd_mips_elf_final_write_processing): Add
bfd_mach_mipsisa32r2 case.
(_bfd_mips_elf_merge_private_bfd_data): Handle merging of
binaries marked as using MIPS32 Release 2.
[ binutils/ChangeLog ]
2002-12-30 Chris Demetriou <cgd@broadcom.com>
* doc/binutils.texi (objdump): Note MIPS HWR (Hardware Register)
changes in MIPS -M options.
[ gas/ChangeLog ]
2002-12-30 Chris Demetriou <cgd@broadcom.com>
* configure.in: Recognize mipsisa32r2, mipsisa32r2el, and
CPU variants.
* configure: Regenerate.
* config/tc-mips.c (ISA_HAS_DROR, ISA_HAS_ROR): New defines.
(macro_build): Handle "K" operand.
(macro2): Use ISA_HAS_DROR and ISA_HAS_ROR in the places where
CPU_HAS_DROR and CPU_HAS_ROR are currently used.
(mips_ip): New variable "lastpos", and implement "+A", "+B",
and "+C" operands for MIPS32 Release 2 ins/ext instructions.
Implement "K" operand for MIPS32 Release 2 rdhwr instruction.
(validate_mips_insn): Implement "+" as a way to extend the
allowed operands, and implement "K", "+A", "+B", and "+C"
operands.
(OPTION_MIPS32R2): New define.
(md_longopts): Add entry for OPTION_MIPS32R2.
(OPTION_ELF_BASE): Adjust to accomodate OPTIONS_MIPS32R2.
(md_parse_option): Handle OPTION_MIPS32R2.
(s_mipsset): Reimplement handling of ".set mipsN" options
and add support for ".set mips32r2".
(mips_cpu_info_table): Add entry for "mips32r2" (MIPS32 Release 2).
(md_show_usage): Document "-mips32r2" option.
* doc/as.texinfo: Document "-mips32r2" option.
* doc/c-mips.texi: Likewise.
[ gas/testsuite/ChangeLog ]
2002-12-30 Chris Demetriou <cgd@broadcom.com>
* gas/mips/cp0-names-mips32r2.d: New test.
* gas/mips/hwr-names-mips32r2.d: New test.
* gas/mips/hwr-names-numeric.d: New test.
* gas/mips/hwr-names.s: New test source file.
* gas/mips/mips32r2.d: New test.
* gas/mips/mips32r2.s: New test source file.
* gas/mips/mips32r2-ill.l: New test.
* gas/mips/mips32r2-ill.s: New test source file.
* gas/mips/mips.exp: Add mips32r2 architecture data array
entry. Run new tests mentioned above.
[ include/elf/ChangeLog ]
2002-12-30 Chris Demetriou <cgd@broadcom.com>
* mips.h (E_MIPS_ARCH_32R2): New define.
[ include/opcode/ChangeLog ]
2002-12-30 Chris Demetriou <cgd@broadcom.com>
* mips.h: Document "+" as the start of two-character operand
type names, and add new "K", "+A", "+B", and "+C" operand types.
(OP_MASK_INSMSB, OP_SH_INSMSB, OP_MASK_EXTMSB)
(OP_SH_EXTMSB, INSN_ISA32R2, ISA_MIPS32R2, CPU_MIPS32R2): New
defines.
[ opcodes/ChangeLog ]
2002-12-30 Chris Demetriou <cgd@broadcom.com>
* mips-dis.c (mips_cp0_names_mips3264r2, mips_hwr_names_numeric)
(mips_hwr_names_mips3264r2): New arrays.
(mips_arch_choice): New "hwr_names" member.
(mips_arch_choices): Adjust for structure change, and add a new
entry for "mips32r2" ISA.
(mips_hwr_names): New variable.
(set_default_mips_dis_options): Set mips_hwr_names.
(parse_mips_dis_option): New "hwr-names" option which sets
mips_hwr_names, and adjust "reg-names=ARCH" to set mips_hwr_names.
(print_insn_arg): Change return type to "int"
and use that to indicate number of characters consumed.
Add support for "+" operand extension character, "+A", "+B",
"+C", and "K" operands.
(print_insn_mips): Adjust for changes to print_insn_arg.
(print_mips_disassembler_options): Adjust for "hwr-names"
addition and "reg-names" change.
* mips-opc (I33): New define (shorthand for INSN_ISA32R2).
(mips_builtin_opcodes): Note that "nop" and "ssnop" are special
forms of "sll". Add new MIPS32 Release 2 instructions: ehb,
di, ei, ext, ins, jr.hb, jalr.hb, mfhc1, mfhc2, mthc1, mthc2,
rdhwr, rdpgpr, seb, seh, synci, wrpgpr, wsbh.
Note that hardware rotate instructions (ror, rorv) can be
used on MIPS32 Release 2, and add the official mnemonics
for them (rotr, rotrv) and the similar "rotl" mnemonic for
left-rotate.
2002-12-31 08:29:29 +01:00
|
|
|
|
-mips32r2 generate MIPS32 release 2 ISA instructions\n\
|
[gas/]
* doc/c-mips.texi: Remove -mcpu. Document -mabi.
* configure.in (MIPS_CPU_STRING_DEFAULT): New configuration macro.
(USE_E_MIPS_ABI_O32, MIPS_DEFAULT_64BIT): New configuration macros.
* configure, config.in: Regenerate.
* config/tc-mips.c (file_mips_abi): Rename to mips_abi.
(mips_set_options): Remove "abi" field.
(mips_opts): Update accordingly. Replace all uses of mips_opts.abi
with mips_abi.
(mips_cpu): Remove.
(mips_arch_string, mips_arch_info): New vars.
(mips_tune_string, mips_tune_info): New vars.
(ABI_NEEDS_32BIT_REGS, ABI_NEEDS_64BIT_REGS): New macros.
(HAVE_32BIT_GPRS, HAVE_32BIT_FPRS): Don't check the ABI.
(mips_isa_to_str, mips_cpu_to_str): Remove.
(mips_ip): If the selected architecture is a generic ISA rather
than a processor, only mention the ISA level in error messages.
(OPTION_MCPU): Remove.
(OPTION_FP64): New.
(md_longopts): Add -mfp64, remove -mcpu.
(mips_set_option_string): New fn.
(md_parse_option): Make -mipsN update file_mips_isa rather than
mips_opts.isa. Use mips_set_option_string to set -march or -mtune.
Don't let -mgp32 and -mfp32 change the ABI.
(show): Move to end of file. Constify string argument.
(md_show_usage): Move to the end of the file. Read available
architectures from mips_cpu_info_table.
(mips_set_architecture): New fn.
(mips_after_parse_args): Rework. Remove -mcpu handling. -mipsN
is an alias for -march=mipsN. Don't change the ABI based on other
flags. Infer the register size from the ABI as well as the
architecture. Complain about more conflicting arguments.
Unify logic with GCC.
(s_mipsset): Don't change the ABI.
(mips_elf_final_processing): Check USE_E_MIPS_ABI_O32.
(mips_cpu_info_table): Remove Generic-MIPS* entries, keeping just
"mipsN"-type entries. Remove entries that vary only in the
manufacturer's prefix, or that have "000" replaced by "k".
Remove TARGET_CPU entries. Make r2000 entry use CPU_R3000.
(mips_strict_matching_cpu_name_p, mips_matching_cpu_name_p): New fns.
(mips_parse_cpu): New fn.
(mips_cpu_info_from_name, mips_cpu_info_from_cpu): Remove.
(mips_cpu_info_from_isa): Minor formatting tweak.
[gas/testsuite]
* gas/mips/mips-gp32-fp64.d,
* gas/mips/mips-gp32-fp64-pic.d: Add -mfp64.
2002-07-25 11:48:07 +02:00
|
|
|
|
-mips64 generate MIPS64 ISA instructions\n\
|
[ bfd/ChangeLog ]
2003-09-30 Chris Demetriou <cgd@broadcom.com>
* archures.c (bfd_mach_mipsisa64r2): New define.
* bfd-in2.h: Regenerate.
* aoutx.h (NAME(aout,machine_type)): Handle bfd_mach_mipsisa64r2.
* cpu-mips.c (I_mipsisa64r2): New enum value.
(arch_info_struct): Add entry for I_mipsisa64r2.
* elfxx-mips.c (_bfd_elf_mips_mach)
(_bfd_mips_elf_print_private_bfd_data): Handle E_MIPS_ARCH_64R2.
(mips_set_isa_flags): Add bfd_mach_mipsisa64r2 case.
(mips_mach_extensions): Add entry for bfd_mach_mipsisa64r2.
[ binutils/ChangeLog ]
2003-09-30 Chris Demetriou <cgd@broadcom.com>
* readelf.c (get_machine_flags): Handle E_MIPS_ARCH_64R2.
[ gas/Changelog ]
2003-09-30 Chris Demetriou <cgd@broadcom.com>
* configure.in (mipsisa64r2, mipsisa64r2el, mipsisa64r2*): New CPUs.
* configure: Regenerate.
* config/tc-mips.c (imm2_expr): New variable.
(md_assemble, mips16_ip): Initialize imm2_expr.
(ISA_HAS_64BIT_REGS, ISA_HAS_DROR, ISA_HAS_ROR): Add ISA_MIPS64R2.
(macro_build): Handle +A, +B, +C, +E, +F, +G, and +H format operands.
(macro): Handle M_DEXT and M_DINS.
(validate_mips_insn): Handle +E, +F, +G, +H, and +I format operands.
(mips_ip): Likewise.
(OPTION_MIPS64R2): New define.
(md_longopts): New entry for -mips64r2 (OPTION_MIPS64R2).
OPTION_ASE_BASE): Increase to compensate for OPTION_MIPS64R2.
(md_parse_option): Handle OPTION_MIPS64R2.
(s_mipsset): Handle setting "mips64r2" ISA.
(mips_cpu_info_table): Add mips64r2.
(md_show_usage): Document -mips64r2 option.
* doc/as.texinfo: Docuemnt -mips64r2 option.
* doc/c-mips.texi: Likewise.
[ gas/testsuite/ChangeLog ]
2003-09-30 Chris Demetriou <cgd@broadcom.com>
* gas/mips/cp0-names-mips64r2.d: New file.
* gas/mips/cp0sel-names-mips64r2.d: New file.
* gas/mips/elf_arch_mips64r2.d: New file.
* gas/mips/hwr-names-mips64r2.d: New file.
* gas/mips/mips32r2-ill-fp64.l: New file.
* gas/mips/mips32r2-ill-fp64.s: New file.
* gas/mips/mips64r2-ill.l: New file.
* gas/mips/mips64r2-ill.s: New file.
* gas/mips/mips64r2.d: New file.
* gas/mips/mips64r2.s: New file.
* gas/mips/mips.exp: Define "mips64r2" arch, and run new tests.
[ include/elf/ChangeLog ]
2003-09-30 Chris Demetriou <cgd@broadcom.com>
* mips.h (E_MIPS_ARCH_64R2): New define.
[ include/opcode/ChangeLog ]
2003-09-30 Chris Demetriou <cgd@broadcom.com>
* mips.h: Document +E, +F, +G, +H, and +I operand types.
Update documentation of I, +B and +C operand types.
(INSN_ISA64R2, ISA_MIPS64R2, CPU_MIPS64R2): New defines.
(M_DEXT, M_DINS): New enum values.
[ ld/ChangeLog ]
2003-09-30 Chris Demetriou <cgd@broadcom.com>
* ldmain.c (get_emulation): Ignore "-mips64r2".
[ ld/testsuite/ChangeLog ]
2003-09-30 Chris Demetriou <cgd@broadcom.com>
* ld-mips-elf/mips-elf-flags.exp: Add tests for combinations
with MIPS64r2.
[ opcodes/ChangeLog ]
2003-09-30 Chris Demetriou <cgd@broadcom.com>
* mips-dis.c (mips_arch_choices): Add entry for "mips64r2"
(print_insn_args): Add handing for +E, +F, +G, and +H.
* mips-opc.c (I65): New define for MIPS64r2.
(mips_builtin_opcodes): Add "dext", "dextm", "dextu", "dins",
"dinsm", "dinsu", "drotl", "drotr", "drotr32", "drotrv", "dsbh",
and "dshd" for MIPS64r2. Adjust "dror", "dror32", and "drorv" to
be supported on MIPS64r2.
2003-09-30 18:17:15 +02:00
|
|
|
|
-mips64r2 generate MIPS64 release 2 ISA instructions\n\
|
[gas/]
* doc/c-mips.texi: Remove -mcpu. Document -mabi.
* configure.in (MIPS_CPU_STRING_DEFAULT): New configuration macro.
(USE_E_MIPS_ABI_O32, MIPS_DEFAULT_64BIT): New configuration macros.
* configure, config.in: Regenerate.
* config/tc-mips.c (file_mips_abi): Rename to mips_abi.
(mips_set_options): Remove "abi" field.
(mips_opts): Update accordingly. Replace all uses of mips_opts.abi
with mips_abi.
(mips_cpu): Remove.
(mips_arch_string, mips_arch_info): New vars.
(mips_tune_string, mips_tune_info): New vars.
(ABI_NEEDS_32BIT_REGS, ABI_NEEDS_64BIT_REGS): New macros.
(HAVE_32BIT_GPRS, HAVE_32BIT_FPRS): Don't check the ABI.
(mips_isa_to_str, mips_cpu_to_str): Remove.
(mips_ip): If the selected architecture is a generic ISA rather
than a processor, only mention the ISA level in error messages.
(OPTION_MCPU): Remove.
(OPTION_FP64): New.
(md_longopts): Add -mfp64, remove -mcpu.
(mips_set_option_string): New fn.
(md_parse_option): Make -mipsN update file_mips_isa rather than
mips_opts.isa. Use mips_set_option_string to set -march or -mtune.
Don't let -mgp32 and -mfp32 change the ABI.
(show): Move to end of file. Constify string argument.
(md_show_usage): Move to the end of the file. Read available
architectures from mips_cpu_info_table.
(mips_set_architecture): New fn.
(mips_after_parse_args): Rework. Remove -mcpu handling. -mipsN
is an alias for -march=mipsN. Don't change the ABI based on other
flags. Infer the register size from the ABI as well as the
architecture. Complain about more conflicting arguments.
Unify logic with GCC.
(s_mipsset): Don't change the ABI.
(mips_elf_final_processing): Check USE_E_MIPS_ABI_O32.
(mips_cpu_info_table): Remove Generic-MIPS* entries, keeping just
"mipsN"-type entries. Remove entries that vary only in the
manufacturer's prefix, or that have "000" replaced by "k".
Remove TARGET_CPU entries. Make r2000 entry use CPU_R3000.
(mips_strict_matching_cpu_name_p, mips_matching_cpu_name_p): New fns.
(mips_parse_cpu): New fn.
(mips_cpu_info_from_name, mips_cpu_info_from_cpu): Remove.
(mips_cpu_info_from_isa): Minor formatting tweak.
[gas/testsuite]
* gas/mips/mips-gp32-fp64.d,
* gas/mips/mips-gp32-fp64-pic.d: Add -mfp64.
2002-07-25 11:48:07 +02:00
|
|
|
|
-march=CPU/-mtune=CPU generate code/schedule for CPU, where CPU is one of:\n"));
|
|
|
|
|
|
|
|
|
|
first = 1;
|
2000-12-01 22:35:38 +01:00
|
|
|
|
|
|
|
|
|
for (i = 0; mips_cpu_info_table[i].name != NULL; i++)
|
[gas/]
* doc/c-mips.texi: Remove -mcpu. Document -mabi.
* configure.in (MIPS_CPU_STRING_DEFAULT): New configuration macro.
(USE_E_MIPS_ABI_O32, MIPS_DEFAULT_64BIT): New configuration macros.
* configure, config.in: Regenerate.
* config/tc-mips.c (file_mips_abi): Rename to mips_abi.
(mips_set_options): Remove "abi" field.
(mips_opts): Update accordingly. Replace all uses of mips_opts.abi
with mips_abi.
(mips_cpu): Remove.
(mips_arch_string, mips_arch_info): New vars.
(mips_tune_string, mips_tune_info): New vars.
(ABI_NEEDS_32BIT_REGS, ABI_NEEDS_64BIT_REGS): New macros.
(HAVE_32BIT_GPRS, HAVE_32BIT_FPRS): Don't check the ABI.
(mips_isa_to_str, mips_cpu_to_str): Remove.
(mips_ip): If the selected architecture is a generic ISA rather
than a processor, only mention the ISA level in error messages.
(OPTION_MCPU): Remove.
(OPTION_FP64): New.
(md_longopts): Add -mfp64, remove -mcpu.
(mips_set_option_string): New fn.
(md_parse_option): Make -mipsN update file_mips_isa rather than
mips_opts.isa. Use mips_set_option_string to set -march or -mtune.
Don't let -mgp32 and -mfp32 change the ABI.
(show): Move to end of file. Constify string argument.
(md_show_usage): Move to the end of the file. Read available
architectures from mips_cpu_info_table.
(mips_set_architecture): New fn.
(mips_after_parse_args): Rework. Remove -mcpu handling. -mipsN
is an alias for -march=mipsN. Don't change the ABI based on other
flags. Infer the register size from the ABI as well as the
architecture. Complain about more conflicting arguments.
Unify logic with GCC.
(s_mipsset): Don't change the ABI.
(mips_elf_final_processing): Check USE_E_MIPS_ABI_O32.
(mips_cpu_info_table): Remove Generic-MIPS* entries, keeping just
"mipsN"-type entries. Remove entries that vary only in the
manufacturer's prefix, or that have "000" replaced by "k".
Remove TARGET_CPU entries. Make r2000 entry use CPU_R3000.
(mips_strict_matching_cpu_name_p, mips_matching_cpu_name_p): New fns.
(mips_parse_cpu): New fn.
(mips_cpu_info_from_name, mips_cpu_info_from_cpu): Remove.
(mips_cpu_info_from_isa): Minor formatting tweak.
[gas/testsuite]
* gas/mips/mips-gp32-fp64.d,
* gas/mips/mips-gp32-fp64-pic.d: Add -mfp64.
2002-07-25 11:48:07 +02:00
|
|
|
|
show (stream, mips_cpu_info_table[i].name, &column, &first);
|
|
|
|
|
show (stream, "from-abi", &column, &first);
|
|
|
|
|
fputc ('\n', stream);
|
2000-12-01 22:35:38 +01:00
|
|
|
|
|
[gas/]
* doc/c-mips.texi: Remove -mcpu. Document -mabi.
* configure.in (MIPS_CPU_STRING_DEFAULT): New configuration macro.
(USE_E_MIPS_ABI_O32, MIPS_DEFAULT_64BIT): New configuration macros.
* configure, config.in: Regenerate.
* config/tc-mips.c (file_mips_abi): Rename to mips_abi.
(mips_set_options): Remove "abi" field.
(mips_opts): Update accordingly. Replace all uses of mips_opts.abi
with mips_abi.
(mips_cpu): Remove.
(mips_arch_string, mips_arch_info): New vars.
(mips_tune_string, mips_tune_info): New vars.
(ABI_NEEDS_32BIT_REGS, ABI_NEEDS_64BIT_REGS): New macros.
(HAVE_32BIT_GPRS, HAVE_32BIT_FPRS): Don't check the ABI.
(mips_isa_to_str, mips_cpu_to_str): Remove.
(mips_ip): If the selected architecture is a generic ISA rather
than a processor, only mention the ISA level in error messages.
(OPTION_MCPU): Remove.
(OPTION_FP64): New.
(md_longopts): Add -mfp64, remove -mcpu.
(mips_set_option_string): New fn.
(md_parse_option): Make -mipsN update file_mips_isa rather than
mips_opts.isa. Use mips_set_option_string to set -march or -mtune.
Don't let -mgp32 and -mfp32 change the ABI.
(show): Move to end of file. Constify string argument.
(md_show_usage): Move to the end of the file. Read available
architectures from mips_cpu_info_table.
(mips_set_architecture): New fn.
(mips_after_parse_args): Rework. Remove -mcpu handling. -mipsN
is an alias for -march=mipsN. Don't change the ABI based on other
flags. Infer the register size from the ABI as well as the
architecture. Complain about more conflicting arguments.
Unify logic with GCC.
(s_mipsset): Don't change the ABI.
(mips_elf_final_processing): Check USE_E_MIPS_ABI_O32.
(mips_cpu_info_table): Remove Generic-MIPS* entries, keeping just
"mipsN"-type entries. Remove entries that vary only in the
manufacturer's prefix, or that have "000" replaced by "k".
Remove TARGET_CPU entries. Make r2000 entry use CPU_R3000.
(mips_strict_matching_cpu_name_p, mips_matching_cpu_name_p): New fns.
(mips_parse_cpu): New fn.
(mips_cpu_info_from_name, mips_cpu_info_from_cpu): Remove.
(mips_cpu_info_from_isa): Minor formatting tweak.
[gas/testsuite]
* gas/mips/mips-gp32-fp64.d,
* gas/mips/mips-gp32-fp64-pic.d: Add -mfp64.
2002-07-25 11:48:07 +02:00
|
|
|
|
fprintf (stream, _("\
|
|
|
|
|
-mCPU equivalent to -march=CPU -mtune=CPU. Deprecated.\n\
|
|
|
|
|
-no-mCPU don't generate code specific to CPU.\n\
|
|
|
|
|
For -mCPU and -no-mCPU, CPU must be one of:\n"));
|
|
|
|
|
|
|
|
|
|
first = 1;
|
|
|
|
|
|
|
|
|
|
show (stream, "3900", &column, &first);
|
|
|
|
|
show (stream, "4010", &column, &first);
|
|
|
|
|
show (stream, "4100", &column, &first);
|
|
|
|
|
show (stream, "4650", &column, &first);
|
|
|
|
|
fputc ('\n', stream);
|
|
|
|
|
|
|
|
|
|
fprintf (stream, _("\
|
|
|
|
|
-mips16 generate mips16 instructions\n\
|
|
|
|
|
-no-mips16 do not generate mips16 instructions\n"));
|
|
|
|
|
fprintf (stream, _("\
|
|
|
|
|
-mgp32 use 32-bit GPRs, regardless of the chosen ISA\n\
|
|
|
|
|
-mfp32 use 32-bit FPRs, regardless of the chosen ISA\n\
|
|
|
|
|
-O0 remove unneeded NOPs, do not swap branches\n\
|
|
|
|
|
-O remove unneeded NOPs and swap branches\n\
|
|
|
|
|
--[no-]construct-floats [dis]allow floating point values to be constructed\n\
|
|
|
|
|
--trap, --no-break trap exception on div by 0 and mult overflow\n\
|
|
|
|
|
--break, --no-trap break exception on div by 0 and mult overflow\n"));
|
|
|
|
|
#ifdef OBJ_ELF
|
|
|
|
|
fprintf (stream, _("\
|
|
|
|
|
-KPIC, -call_shared generate SVR4 position independent code\n\
|
|
|
|
|
-non_shared do not generate position independent code\n\
|
|
|
|
|
-xgot assume a 32 bit GOT\n\
|
2003-07-28 22:06:27 +02:00
|
|
|
|
-mpdr, -mno-pdr enable/disable creation of .pdr sections\n\
|
[gas/]
* doc/c-mips.texi: Remove -mcpu. Document -mabi.
* configure.in (MIPS_CPU_STRING_DEFAULT): New configuration macro.
(USE_E_MIPS_ABI_O32, MIPS_DEFAULT_64BIT): New configuration macros.
* configure, config.in: Regenerate.
* config/tc-mips.c (file_mips_abi): Rename to mips_abi.
(mips_set_options): Remove "abi" field.
(mips_opts): Update accordingly. Replace all uses of mips_opts.abi
with mips_abi.
(mips_cpu): Remove.
(mips_arch_string, mips_arch_info): New vars.
(mips_tune_string, mips_tune_info): New vars.
(ABI_NEEDS_32BIT_REGS, ABI_NEEDS_64BIT_REGS): New macros.
(HAVE_32BIT_GPRS, HAVE_32BIT_FPRS): Don't check the ABI.
(mips_isa_to_str, mips_cpu_to_str): Remove.
(mips_ip): If the selected architecture is a generic ISA rather
than a processor, only mention the ISA level in error messages.
(OPTION_MCPU): Remove.
(OPTION_FP64): New.
(md_longopts): Add -mfp64, remove -mcpu.
(mips_set_option_string): New fn.
(md_parse_option): Make -mipsN update file_mips_isa rather than
mips_opts.isa. Use mips_set_option_string to set -march or -mtune.
Don't let -mgp32 and -mfp32 change the ABI.
(show): Move to end of file. Constify string argument.
(md_show_usage): Move to the end of the file. Read available
architectures from mips_cpu_info_table.
(mips_set_architecture): New fn.
(mips_after_parse_args): Rework. Remove -mcpu handling. -mipsN
is an alias for -march=mipsN. Don't change the ABI based on other
flags. Infer the register size from the ABI as well as the
architecture. Complain about more conflicting arguments.
Unify logic with GCC.
(s_mipsset): Don't change the ABI.
(mips_elf_final_processing): Check USE_E_MIPS_ABI_O32.
(mips_cpu_info_table): Remove Generic-MIPS* entries, keeping just
"mipsN"-type entries. Remove entries that vary only in the
manufacturer's prefix, or that have "000" replaced by "k".
Remove TARGET_CPU entries. Make r2000 entry use CPU_R3000.
(mips_strict_matching_cpu_name_p, mips_matching_cpu_name_p): New fns.
(mips_parse_cpu): New fn.
(mips_cpu_info_from_name, mips_cpu_info_from_cpu): Remove.
(mips_cpu_info_from_isa): Minor formatting tweak.
[gas/testsuite]
* gas/mips/mips-gp32-fp64.d,
* gas/mips/mips-gp32-fp64-pic.d: Add -mfp64.
2002-07-25 11:48:07 +02:00
|
|
|
|
-mabi=ABI create ABI conformant object file for:\n"));
|
|
|
|
|
|
|
|
|
|
first = 1;
|
|
|
|
|
|
|
|
|
|
show (stream, "32", &column, &first);
|
|
|
|
|
show (stream, "o64", &column, &first);
|
|
|
|
|
show (stream, "n32", &column, &first);
|
|
|
|
|
show (stream, "64", &column, &first);
|
|
|
|
|
show (stream, "eabi", &column, &first);
|
|
|
|
|
|
|
|
|
|
fputc ('\n', stream);
|
|
|
|
|
|
|
|
|
|
fprintf (stream, _("\
|
|
|
|
|
-32 create o32 ABI object file (default)\n\
|
|
|
|
|
-n32 create n32 ABI object file\n\
|
|
|
|
|
-64 create 64 ABI object file\n"));
|
|
|
|
|
#endif
|
2000-12-01 22:35:38 +01:00
|
|
|
|
}
|
2002-11-18 22:08:54 +01:00
|
|
|
|
|
|
|
|
|
enum dwarf2_format
|
2003-06-30 14:44:25 +02:00
|
|
|
|
mips_dwarf2_format (void)
|
2002-11-18 22:08:54 +01:00
|
|
|
|
{
|
|
|
|
|
if (mips_abi == N64_ABI)
|
2003-01-27 23:45:58 +01:00
|
|
|
|
{
|
|
|
|
|
#ifdef TE_IRIX
|
|
|
|
|
return dwarf2_format_64bit_irix;
|
|
|
|
|
#else
|
|
|
|
|
return dwarf2_format_64bit;
|
|
|
|
|
#endif
|
|
|
|
|
}
|
2002-11-18 22:08:54 +01:00
|
|
|
|
else
|
|
|
|
|
return dwarf2_format_32bit;
|
|
|
|
|
}
|