2017-09-11 07:46:27 +02:00
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2017-09-06 Kamil Rytarowski <n54@gmx.com>
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* opcode/nds32.h: Rename __BIT() to N32_BIT().
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2017-09-05 00:52:17 +02:00
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2017-09-05 Alexander Fedotov <alexander.fedotov@nxp.com>
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Edmar Wienskoski <edmar.wienskoski@nxp.com
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* elf/ppc.h (R_PPC_VLE_ADDR20): New relocation.
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2017-08-23 17:08:46 +02:00
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2017-08-23 Alexander Fedotov <alexander.fedotov@nxp.com>
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Edmar Wienskoski <edmar.wienskoski@nxp.com>
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* opcode/ppc.h:
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|
(spe2_opcodes, spe2_num_opcodes): New.
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(PPC_OPCODE_SPE2): New define.
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(PPC_OPCODE_EFS2): Likewise.
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(SPE2_XOP): Likewise.
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(SPE2_XOP_TO_SEG): Likewise.
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2017-02-21 22:32:56 +01:00
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2017-08-23 Jan Kratochvil <jan.kratochvil@redhat.com>
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* gcc-interface.h (enum gcc_base_api_version): Update comment for
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GCC_FE_VERSION_1.
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(struct gcc_base_vtable): Rename set_arguments to set_arguments_v0.
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Add set_arguments, set_triplet_regexp and set_driver_filename.
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2017-02-21 22:32:55 +01:00
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2017-08-23 Jan Kratochvil <jan.kratochvil@redhat.com>
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* gcc-interface.h (enum gcc_base_api_version): Add
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GCC_FE_VERSION_1.
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(struct gcc_base_vtable): Rename compile to compile_v0. Update
|
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comment for compile. New methods set_verbose and compile.
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2017-08-21 14:45:59 +02:00
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2017-08-21 Alexander Fedotov <alexander.fedotov@nxp.com>
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Edmar Wienskoski <edmar.wienskoski@nxp.com>
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* opcode/ppc.h (PPC_OPCODE_LSP): New define.
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2017-08-14 16:48:04 +02:00
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2017-08-14 Gustavo Romero <gromero@linux.vnet.ibm.com>
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* elf/common.h (NT_PPC_TAR): New macro.
|
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(NT_PPC_PPR): Likewise.
|
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(NT_PPC_DSCR): Likewise.
|
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(NT_PPC_EBB): Likewise.
|
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|
(NT_PPC_PMU): Likewise.
|
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|
(NT_PPC_TM_CGPR): Likewise.
|
|
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|
|
(NT_PPC_TM_CFPR): Likewise.
|
|
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|
|
(NT_PPC_TM_CVMX): Likewise.
|
|
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|
|
(NT_PPC_TM_CVSX): Likewise.
|
|
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|
|
(NT_PPC_TM_SPR): Likewise.
|
|
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|
|
(NT_PPC_TM_CTAR): Likewise.
|
|
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|
|
(NT_PPC_TM_CPPR): Likewise.
|
|
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|
|
(NT_PPC_TM_CDSCR): Likewise.
|
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|
2017-08-06 17:18:53 +02:00
|
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|
|
2017-08-06 H.J. Lu <hongjiu.lu@intel.com>
|
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|
PR ld/21903:
|
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|
|
* bfdlink.h (bfd_link_info): Add inhibit_common_definition.
|
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2017-07-31 16:08:32 +02:00
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|
2017-07-31 Nick Clifton <nickc@redhat.com>
|
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|
|
PR 21850
|
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|
|
* ansidecl.h (OVERRIDE): Protect check of __cplusplus value with
|
|
|
|
|
|
#idef __cplusplus.
|
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|
2017-07-19 09:56:55 +02:00
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|
2017-07-19 Claudiu Zissulescu <claziss@synopsys.com>
|
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* opcode/arc.h (SJLI): Add.
|
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|
2017-07-19 09:56:55 +02:00
|
|
|
|
2017-07-19 Claudiu Zissulescu <claziss@synopsys.com>
|
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|
|
|
John Eric Martin <John.Martin@emmicro-us.com>
|
|
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|
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|
|
* elf/arc-reloc.def: Add JLI relocs howto.
|
|
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|
|
* opcode/arc-func.h (replace_jli): New function.
|
|
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|
2017-07-18 17:58:14 +02:00
|
|
|
|
2017-07-18 Nick Clifton <nickc@redhat.com>
|
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|
|
PR 21775
|
|
|
|
|
|
* aout/adobe.h: Fix spelling typos.
|
|
|
|
|
|
* aout/aout64.h: Likewise.
|
|
|
|
|
|
* aout/hp300hpux.h: Likewise.
|
|
|
|
|
|
* elf/hppa.h: Likewise.
|
|
|
|
|
|
* gdb/remote-sim.h: Likewise.
|
|
|
|
|
|
* libiberty.h: Likewise.
|
|
|
|
|
|
* mach-o/arm.h: Likewise.
|
|
|
|
|
|
* opcode/v850.h: Likewise.
|
|
|
|
|
|
|
2017-07-14 09:56:27 +02:00
|
|
|
|
2017-07-14 Ravi Bangoria <ravi.bangoria@linux.vnet.ibm.com>
|
|
|
|
|
|
|
|
|
|
|
|
* dis-asm.h (struct disassemble_info): Change type of buffer_length
|
|
|
|
|
|
field to size_t.
|
|
|
|
|
|
|
2017-06-28 20:41:41 +02:00
|
|
|
|
2017-07-07 John Baldwin <jhb@FreeBSD.org>
|
|
|
|
|
|
|
|
|
|
|
|
* elf/common.h (NT_FREEBSD_PTLWPINFO): Define.
|
|
|
|
|
|
|
Import include/+libiberty/ r249883 from upstream GCC.
include/ChangeLog
2017-07-02 Jan Kratochvil <jan.kratochvil@redhat.com>
* dwarf2.def (DW_IDX_compile_unit, DW_IDX_type_unit, DW_IDX_die_offset)
(DW_IDX_parent, DW_IDX_type_hash, DW_IDX_lo_user, DW_IDX_hi_user)
(DW_IDX_GNU_internal, DW_IDX_GNU_external): New.
* dwarf2.h (DW_IDX, DW_IDX_DUP, DW_FIRST_IDX, DW_END_IDX): New.
(enum dwarf_name_index_attribute): Remove.
(get_DW_IDX_name): New declaration.
libiberty/ChangeLog
2017-07-02 Jan Kratochvil <jan.kratochvil@redhat.com>
* dwarfnames.c (DW_FIRST_IDX, DW_END_IDX, DW_IDX, DW_IDX_DUP): New.
2017-07-02 22:09:52 +02:00
|
|
|
|
2017-07-02 Jan Kratochvil <jan.kratochvil@redhat.com>
|
|
|
|
|
|
|
|
|
|
|
|
* dwarf2.def (DW_IDX_compile_unit, DW_IDX_type_unit, DW_IDX_die_offset)
|
|
|
|
|
|
(DW_IDX_parent, DW_IDX_type_hash, DW_IDX_lo_user, DW_IDX_hi_user)
|
|
|
|
|
|
(DW_IDX_GNU_internal, DW_IDX_GNU_external): New.
|
|
|
|
|
|
* dwarf2.h (DW_IDX, DW_IDX_DUP, DW_FIRST_IDX, DW_END_IDX): New.
|
|
|
|
|
|
(enum dwarf_name_index_attribute): Remove.
|
|
|
|
|
|
(get_DW_IDX_name): New declaration.
|
|
|
|
|
|
|
Add support for a __gcc_isr pseudo isntruction to the AVR assembler.
PR gas/21683
include * opcode/avr.h (AVR_INSN): Add one for __gcc_isr.
gas * doc/c-avr.texi (AVR Options) <-mgcc-isr>: Document it.
(AVR Pseudo Instructions): New node.
* config/tc-avr.h (md_pre_output_hook): Define to avr_pre_output_hook.
(md_undefined_symbol): Define to avr_undefined_symbol.
(avr_pre_output_hook, avr_undefined_symbol): New protos.
* config/tc-avr.c (struc-symbol.h): Include it.
(ISR_CHUNK_Done, ISR_CHUNK_Prologue, ISR_CHUNK_Epilogue): New enums.
(avr_isr, avr_gccisr_opcode)
(avr_no_sreg_hash, avr_no_sreg): New static variables.
(avr_opt_s) <have_gccisr>: Add field.
(avr_opt): Add initializer for have_gccisr.
(enum options) <OPTION_HAVE_GCCISR>: Add enum.
(md_longopts) <"mgcc-isr">: Add entry.
(md_show_usage): Document -mgcc-isr.
(md_parse_option) [OPTION_HAVE_GCCISR]: Handle it.
(md_undefined_symbol): Remove.
(avr_undefined_symbol, avr_pre_output_hook): New fuctions.
(md_begin) <avr_no_sreg_hash, avr_gccisr_opcode>: Initialize them.
(avr_operand) <pregno>: Add argument and set *pregno if function
is called for a register constraint.
[N]: Handle constraint.
(avr_operands) <avr_operand>: Pass 5th parameter to calls.
[avr_opt.have_gccisr]: Call avr_update_gccisr. Call
avr_gccisr_operands instead of avr_operands.
(avr_update_gccisr, avr_emit_insn, avr_patch_gccisr_frag)
(avr_gccisr_operands, avr_check_gccisr_done): New static functions.
* testsuite/gas/avr/gccisr-01.d: New test.
* testsuite/gas/avr/gccisr-01.s: New test.
* testsuite/gas/avr/gccisr-02.d: New test.
* testsuite/gas/avr/gccisr-02.s: New test.
* testsuite/gas/avr/gccisr-03.d: New test.
* testsuite/gas/avr/gccisr-03.s: New test.
2017-06-30 17:37:39 +02:00
|
|
|
|
2017-06-30 Georg-Johann Lay <avr@gjlay.de>
|
|
|
|
|
|
|
|
|
|
|
|
PR gas/21683
|
|
|
|
|
|
* opcode/avr.h (AVR_INSN): Add one for __gcc_isr.
|
|
|
|
|
|
|
2017-06-30 08:21:55 +02:00
|
|
|
|
2017-06-30 Maciej W. Rozycki <macro@imgtec.com>
|
|
|
|
|
|
Andrew Bennett <andrew.bennett@imgtec.com>
|
|
|
|
|
|
|
|
|
|
|
|
* opcode/mips.h (ASE_XPA_VIRT): New macro.
|
|
|
|
|
|
|
2017-06-29 10:30:09 +02:00
|
|
|
|
2017-06-29 Andreas Arnez <arnez@linux.vnet.ibm.com>
|
|
|
|
|
|
|
|
|
|
|
|
* elf/common.h (NT_S390_GS_CB): New macro.
|
|
|
|
|
|
(NT_S390_GS_BC): Likewise.
|
|
|
|
|
|
|
2017-06-28 12:09:01 +02:00
|
|
|
|
2017-06-28 Tamar Christina <tamar.christina@arm.com>
|
|
|
|
|
|
|
|
|
|
|
|
* opcode/aarch64.h: (AARCH64_FEATURE_DOTPROD): New.
|
|
|
|
|
|
(aarch64_insn_class): Added dotprod.
|
|
|
|
|
|
|
2017-06-28 12:00:55 +02:00
|
|
|
|
2017-06-28 Jiong Wang <jiong.wang@arm.com>
|
|
|
|
|
|
|
|
|
|
|
|
* opcode/arm.h (FPU_NEON_EXT_DOTPROD): New macro.
|
|
|
|
|
|
(FPU_ARCH_DOTPROD_NEON_VFP_ARMV8): New macro.
|
|
|
|
|
|
|
MIPS: Add Imagination interAptiv MR2 MIPS32r3 processor support
Add support for the Imagination interAptiv MR2 MIPS32r3 processor with
the MIPS16e2 ASE as per documentation, including in particular:
1. Support for implementation-specific interAptiv MR2 COPYW and UCOPYW
MIPS16e2 instructions[1], for assembly and disassembly,
2. Support for implementation-specific interAptiv MR2 SAVE and RESTORE
regular MIPS instructions[2], for assembly and disassembly,
3. ELF binary file annotation for the interAptiv MR2 MIPS architecture
extension.
4. Support for interAptiv MR2 architecture selection for assembly, in
the form of the `-march=interaptiv-mr2' command-line option and its
corresponding `arch=interaptiv-mr2' setting for the `.set' and
`.module' pseudo-ops.
5. Support for interAptiv MR2 architecture selection for disassembly,
in the form of the `mips:interaptiv-mr2' target architecture, for
use e.g. with the `-m' command-line option for `objdump'.
Parts of this change by Matthew Fortune and Andrew Bennett.
References:
[1] "MIPS32 interAptiv Multiprocessing System Software User's Manual",
Imagination Technologies Ltd., Document Number: MD00904, Revision
02.01, June 15, 2016, Section 24.3 "MIPS16e2 Implementation Specific
Instructions", pp. 878-883
[2] same, Chapter 25 "Implementation-specific Instructions", pp. 911-917
include/
* elf/mips.h (E_MIPS_MACH_IAMR2): New macro.
(AFL_EXT_INTERAPTIV_MR2): Likewise.
* opcode/mips.h: Document new operand codes defined.
(INSN_INTERAPTIV_MR2): New macro.
(INSN_CHIP_MASK): Adjust accordingly.
(CPU_INTERAPTIV_MR2): New macro.
(cpu_is_member) <CPU_INTERAPTIV_MR2>: New case.
(MIPS16_ALL_ARGS): Rename to...
(MIPS_SVRS_ALL_ARGS): ... this.
(MIPS16_ALL_STATICS): Rename to...
(MIPS_SVRS_ALL_STATICS): ... this.
bfd/
* archures.c (bfd_mach_mips_interaptiv_mr2): New macro.
* cpu-mips.c (I_interaptiv_mr2): New enum value.
(arch_info_struct): Add "mips:interaptiv-mr2" entry.
* elfxx-mips.c (_bfd_elf_mips_mach) <E_MIPS_MACH_IAMR2>: New
case.
(mips_set_isa_flags) <bfd_mach_mips_interaptiv_mr2>: Likewise.
(bfd_mips_isa_ext) <bfd_mach_mips_interaptiv_mr2>: Likewise.
(print_mips_isa_ext) <AFL_EXT_INTERAPTIV_MR2>: Likewise.
(mips_mach_extensions): Add `bfd_mach_mipsisa32r3' and
`bfd_mach_mips_interaptiv_mr2' entries.
* bfd-in2.h: Regenerate.
opcodes/
* mips-formats.h (INT_BIAS): New macro.
(INT_ADJ): Redefine in INT_BIAS terms.
* mips-dis.c (mips_arch_choices): Add "interaptiv-mr2" entry.
(mips_print_save_restore): New function.
(print_insn_arg) <OP_SAVE_RESTORE_LIST>: Update comment.
(validate_insn_args) <OP_SAVE_RESTORE_LIST>: Remove `abort'
call.
(print_insn_args): Handle OP_SAVE_RESTORE_LIST.
(print_mips16_insn_arg): Call `mips_print_save_restore' for
OP_SAVE_RESTORE_LIST handling, factored out from here.
* mips-opc.c (decode_mips_operand) <'-'> <'m'>: New case.
(RD_31, RD_SP, WR_SP, MOD_SP, IAMR2): New macros.
(mips_builtin_opcodes): Add "restore" and "save" entries.
* mips16-opc.c (decode_mips16_operand) <'n', 'o'>: New cases.
(IAMR2): New macro.
(mips16_opcodes): Add "copyw" and "ucopyw" entries.
binutils/
* readelf.c (get_machine_flags) <E_MIPS_MACH_IAMR2>: New case.
(print_mips_isa_ext) <AFL_EXT_INTERAPTIV_MR2>: Likewise.
* NEWS: Mention Imagination interAptiv MR2 processor support.
gas/
* config/tc-mips.c (validate_mips_insn): Handle
OP_SAVE_RESTORE_LIST specially.
(mips_encode_save_restore, mips16_encode_save_restore): New
functions.
(match_save_restore_list_operand): Factor out SAVE/RESTORE
operand insertion into the instruction word or halfword to these
new functions.
(mips_cpu_info_table): Add "interaptiv-mr2" entry.
* doc/c-mips.texi (MIPS Options): Add `interaptiv-mr2' to the
`-march=' argument list.
2017-06-28 03:07:36 +02:00
|
|
|
|
2017-06-28 Maciej W. Rozycki <macro@imgtec.com>
|
|
|
|
|
|
Matthew Fortune <matthew.fortune@imgtec.com>
|
|
|
|
|
|
|
|
|
|
|
|
* elf/mips.h (E_MIPS_MACH_IAMR2): New macro.
|
|
|
|
|
|
(AFL_EXT_INTERAPTIV_MR2): Likewise.
|
|
|
|
|
|
* opcode/mips.h: Document new operand codes defined.
|
|
|
|
|
|
(INSN_INTERAPTIV_MR2): New macro.
|
|
|
|
|
|
(INSN_CHIP_MASK): Adjust accordingly.
|
|
|
|
|
|
(CPU_INTERAPTIV_MR2): New macro.
|
|
|
|
|
|
(cpu_is_member) <CPU_INTERAPTIV_MR2>: New case.
|
|
|
|
|
|
(MIPS16_ALL_ARGS): Rename to...
|
|
|
|
|
|
(MIPS_SVRS_ALL_ARGS): ... this.
|
|
|
|
|
|
(MIPS16_ALL_STATICS): Rename to...
|
|
|
|
|
|
(MIPS_SVRS_ALL_STATICS): ... this.
|
|
|
|
|
|
|
2017-06-08 20:54:14 +02:00
|
|
|
|
2017-06-26 Kuan-Lin Chen <rufus@andestech.com>
|
|
|
|
|
|
|
|
|
|
|
|
* elf/riscv.h (R_RISCV_32_PCREL): New.
|
|
|
|
|
|
|
2017-06-24 11:37:47 +02:00
|
|
|
|
2017-06-24 Thomas Preud'homme <thomas.preudhomme@arm.com>
|
|
|
|
|
|
|
|
|
|
|
|
* elf/arm.h (TAG_CPU_ARCH_V8R): New macro.
|
|
|
|
|
|
* opcode/arm.h (ARM_EXT2_V8A): New macro.
|
|
|
|
|
|
(ARM_AEXT2_V8A): Rename into ...
|
|
|
|
|
|
(ARM_AEXT2_V8AR): This.
|
|
|
|
|
|
(ARM_AEXT2_V8A): New macro.
|
|
|
|
|
|
(ARM_AEXT_V8R): New macro.
|
|
|
|
|
|
(ARM_AEXT2_V8R): New macro.
|
|
|
|
|
|
(ARM_ARCH_V8R): New macro.
|
|
|
|
|
|
|
2017-06-24 11:26:41 +02:00
|
|
|
|
2017-06-24 Thomas Preud'homme <thomas.preudhomme@arm.com>
|
|
|
|
|
|
|
|
|
|
|
|
* opcode/arm.h (ARM_AEXT_V4TxM): Add ARM_EXT_OS bit to the set.
|
|
|
|
|
|
(ARM_AEXT_V4T): Likewise.
|
|
|
|
|
|
(ARM_AEXT_V5TxM): Likewise.
|
|
|
|
|
|
(ARM_AEXT_V5T): Likewise.
|
|
|
|
|
|
(ARM_AEXT_V6M): Mask off ARM_EXT_OS bit.
|
|
|
|
|
|
|
2017-06-22 14:50:20 +02:00
|
|
|
|
2017-06-22 H.J. Lu <hongjiu.lu@intel.com>
|
|
|
|
|
|
|
|
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* bfdlink.h (bfd_link_info): Add shstk.
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* elf/common.h (GNU_PROPERTY_X86_FEATURE_1_SHSTK): New.
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x86: Support Intel IBT with IBT property and IBT-enable PLT
To support IBT in Intel Control-flow Enforcement Technology (CET)
instructions:
https://software.intel.com/sites/default/files/managed/4d/2a/control-flow-enforcement-technology-preview.pdf
#define GNU_PROPERTY_X86_FEATURE_1_AND 0xc0000002
#define GNU_PROPERTY_X86_FEATURE_1_IBT (1U << 0)
are added to GNU program properties to indicate that all executable
sections are compatible with IBT when ENDBR instruction starts each
valid target where an indirect branch instruction can land.
GNU_PROPERTY_X86_FEATURE_1_IBT is set on output only if it is set on
all relocatable inputs.
The followings changes are made to the Procedure Linkage Table (PLT):
1. For 64-bit x86-64, PLT is changed to
PLT0: push GOT[1]
bnd jmp *GOT[2]
nop
...
PLTn: endbr64
push namen_reloc_index
bnd jmp PLT0
together with the second PLT section:
PLTn: endbr64
bnd jmp *GOT[namen_index]
nop
BND prefix is also added so that IBT-enabled PLT is compatible with MPX.
2. For 32-bit x86-64 (x32) and i386, PLT is changed to
PLT0: push GOT[1]
jmp *GOT[2]
nop
...
PLTn: endbr64 # endbr32 for i386.
push namen_reloc_index
jmp PLT0
together with the second PLT section:
PLTn: endbr64 # endbr32 for i386.
jmp *GOT[namen_index]
nop
BND prefix isn't used since MPX isn't supported on x32 and BND registers
aren't used in parameter passing on i386.
GOT is an array of addresses. Initially, GOT[namen_index] is filled
with the address of the ENDBR instruction of the corresponding entry
in the first PLT section. The function, namen, is called via the
ENDBR instruction in the second PLT entry. GOT[namen_index] is updated
to the actual address of the function, namen, at run-time.
2 linker command line options are added:
1. -z ibtplt: Generate IBT-enabled PLT.
2. -z ibt: Generate GNU_PROPERTY_X86_FEATURE_1_IBT in GNU program
properties as well as IBT-enabled PLT.
bfd/
* elf32-i386.c (elf_i386_lazy_ibt_plt0_entry): New.
(elf_i386_lazy_ibt_plt_entry): Likewise.
(elf_i386_pic_lazy_ibt_plt0_entry): Likewise.
(elf_i386_non_lazy_ibt_plt_entry): Likewise.
(elf_i386_pic_non_lazy_ibt_plt_entry): Likewise.
(elf_i386_eh_frame_lazy_ibt_plt): Likewise.
(elf_i386_lazy_plt_layout): Likewise.
(elf_i386_non_lazy_plt_layout): Likewise.
(elf_i386_link_hash_entry): Add plt_second.
(elf_i386_link_hash_table): Add plt_second and
plt_second_eh_frame.
(elf_i386_allocate_dynrelocs): Use the second PLT if needed.
(elf_i386_size_dynamic_sections): Use .plt.got unwind info for
the second PLT. Check the second PLT.
(elf_i386_relocate_section): Use the second PLT to resolve
PLT reference if needed.
(elf_i386_finish_dynamic_symbol): Fill and use the second PLT if
needed.
(elf_i386_finish_dynamic_sections): Set sh_entsize on the
second PLT. Generate unwind info for the second PLT.
(elf_i386_plt_type): Add plt_second.
(elf_i386_get_synthetic_symtab): Support the second PLT.
(elf_i386_parse_gnu_properties): Support
GNU_PROPERTY_X86_FEATURE_1_AND.
(elf_i386_merge_gnu_properties): Support
GNU_PROPERTY_X86_FEATURE_1_AND. If info->ibt is set, turn
on GNU_PROPERTY_X86_FEATURE_1_IBT
(elf_i386_link_setup_gnu_properties): If info->ibt is set,
turn on GNU_PROPERTY_X86_FEATURE_1_IBT. Use IBT-enabled PLT
for info->ibtplt, info->ibt or GNU_PROPERTY_X86_FEATURE_1_IBT
is set on all relocatable inputs.
* elf64-x86-64.c (elf_x86_64_lazy_ibt_plt_entry): New.
(elf_x32_lazy_ibt_plt_entry): Likewise.
(elf_x86_64_non_lazy_ibt_plt_entry): Likewise.
(elf_x32_non_lazy_ibt_plt_entry): Likewise.
(elf_x86_64_eh_frame_lazy_ibt_plt): Likewise.
(elf_x32_eh_frame_lazy_ibt_plt): Likewise.
(elf_x86_64_lazy_ibt_plt): Likewise.
(elf_x32_lazy_ibt_plt): Likewise.
(elf_x86_64_non_lazy_ibt_plt): Likewise.
(elf_x32_non_lazy_ibt_plt): Likewise.
(elf_x86_64_get_synthetic_symtab): Support the second PLT.
(elf_x86_64_parse_gnu_properties): Support
GNU_PROPERTY_X86_FEATURE_1_AND.
(elf_x86_64_merge_gnu_properties): Support
GNU_PROPERTY_X86_FEATURE_1_AND. If info->ibt is set, turn
on GNU_PROPERTY_X86_FEATURE_1_IBT
(elf_x86_64_link_setup_gnu_properties): If info->ibt is set,
turn on GNU_PROPERTY_X86_FEATURE_1_IBT. Use IBT-enabled PLT
for info->ibtplt, info->ibt or GNU_PROPERTY_X86_FEATURE_1_IBT
is set on all relocatable inputs.
binutils/
* readelf.c (decode_x86_feature): New.
(print_gnu_property_note): Call decode_x86_feature on
GNU_PROPERTY_X86_FEATURE_1_AND.
* testsuite/binutils-all/i386/empty.d: New file.
* testsuite/binutils-all/i386/empty.s: Likewise.
* testsuite/binutils-all/i386/ibt.d: Likewise.
* testsuite/binutils-all/i386/ibt.s: Likewise.
* testsuite/binutils-all/x86-64/empty-x32.d: Likewise.
* testsuite/binutils-all/x86-64/empty.d: Likewise.
* testsuite/binutils-all/x86-64/empty.s: Likewise.
* testsuite/binutils-all/x86-64/ibt-x32.d: Likewise.
* testsuite/binutils-all/x86-64/ibt.d: Likewise.
* testsuite/binutils-all/x86-64/ibt.s: Likewise.
include/
* bfdlink.h (bfd_link_info): Add ibtplt and ibt.
* elf/common.h (GNU_PROPERTY_X86_FEATURE_1_AND): New.
(GNU_PROPERTY_X86_FEATURE_1_IBT): Likewise.
ld/
* Makefile.am (ELF_X86_DEPS): Add $(srcdir)/emulparams/cet.sh.
* Makefile.in: Regenerated.
* NEWS: Mention GNU_PROPERTY_X86_FEATURE_1_IBT, -z ibtplt
and -z ibt.
* emulparams/cet.sh: New file.
* testsuite/ld-i386/ibt-plt-1.d: Likewise.
* testsuite/ld-i386/ibt-plt-1.s: Likewise.
* testsuite/ld-i386/ibt-plt-2.s: Likewise.
* testsuite/ld-i386/ibt-plt-2a.d: Likewise.
* testsuite/ld-i386/ibt-plt-2b.d: Likewise.
* testsuite/ld-i386/ibt-plt-2c.d: Likewise.
* testsuite/ld-i386/ibt-plt-2d.d: Likewise.
* testsuite/ld-i386/ibt-plt-3.s: Likewise.
* testsuite/ld-i386/ibt-plt-3a.d: Likewise.
* testsuite/ld-i386/ibt-plt-3b.d: Likewise.
* testsuite/ld-i386/ibt-plt-3c.d: Likewise.
* testsuite/ld-i386/ibt-plt-3d.d: Likewise.
* testsuite/ld-i386/plt-main-ibt.dd: Likewise.
* testsuite/ld-i386/plt-pie-ibt.dd: Likewise.
* testsuite/ld-i386/property-x86-empty.s: Likewise.
* testsuite/ld-i386/property-x86-ibt.s: Likewise.
* testsuite/ld-i386/property-x86-ibt1a.d: Likewise.
* testsuite/ld-i386/property-x86-ibt1b.d: Likewise.
* testsuite/ld-i386/property-x86-ibt2.d: Likewise.
* testsuite/ld-i386/property-x86-ibt3a.d: Likewise.
* testsuite/ld-i386/property-x86-ibt3b.d: Likewise.
* testsuite/ld-i386/property-x86-ibt4.d: Likewise.
* testsuite/ld-i386/property-x86-ibt5.d: Likewise.
* testsuite/ld-x86-64/ibt-plt-1-x32.d: Likewise.
* testsuite/ld-x86-64/ibt-plt-1.d: Likewise.
* testsuite/ld-x86-64/ibt-plt-1.s: Likewise.
* testsuite/ld-x86-64/ibt-plt-2.s: Likewise.
* testsuite/ld-x86-64/ibt-plt-2a-x32.d: Likewise.
* testsuite/ld-x86-64/ibt-plt-2a.d: Likewise.
* testsuite/ld-x86-64/ibt-plt-2b-x32.d: Likewise.
* testsuite/ld-x86-64/ibt-plt-2b.d: Likewise.
* testsuite/ld-x86-64/ibt-plt-2c-x32.d: Likewise.
* testsuite/ld-x86-64/ibt-plt-2c.d: Likewise.
* testsuite/ld-x86-64/ibt-plt-2d-x32.d: Likewise.
* testsuite/ld-x86-64/ibt-plt-2d.d: Likewise.
* testsuite/ld-x86-64/ibt-plt-3.s: Likewise.
* testsuite/ld-x86-64/ibt-plt-3a-x32.d: Likewise.
* testsuite/ld-x86-64/ibt-plt-3a.d: Likewise.
* testsuite/ld-x86-64/ibt-plt-3b-x32.d: Likewise.
* testsuite/ld-x86-64/ibt-plt-3b.d: Likewise.
* testsuite/ld-x86-64/ibt-plt-3c-x32.d: Likewise.
* testsuite/ld-x86-64/ibt-plt-3c.d: Likewise.
* testsuite/ld-x86-64/ibt-plt-3d-x32.d: Likewise.
* testsuite/ld-x86-64/ibt-plt-3d.d: Likewise.
* testsuite/ld-x86-64/plt-main-ibt-now.rd: Likewise.
* testsuite/ld-x86-64/plt-main-ibt-x32.dd: Likewise.
* testsuite/ld-x86-64/plt-main-ibt.dd: Likewise.
* testsuite/ld-x86-64/property-x86-empty.s: Likewise.
* testsuite/ld-x86-64/property-x86-ibt.s: Likewise.
* testsuite/ld-x86-64/property-x86-ibt1a-x32.d: Likewise.
* testsuite/ld-x86-64/property-x86-ibt1a.d: Likewise.
* testsuite/ld-x86-64/property-x86-ibt1b-x32.d: Likewise.
* testsuite/ld-x86-64/property-x86-ibt1b.d: Likewise.
* testsuite/ld-x86-64/property-x86-ibt2-x32.d: Likewise.
* testsuite/ld-x86-64/property-x86-ibt2.d: Likewise.
* testsuite/ld-x86-64/property-x86-ibt3a-x32.d: Likewise.
* testsuite/ld-x86-64/property-x86-ibt3a.d: Likewise.
* testsuite/ld-x86-64/property-x86-ibt3b-x32.d: Likewise.
* testsuite/ld-x86-64/property-x86-ibt3b.d: Likewise.
* testsuite/ld-x86-64/property-x86-ibt4-x32.d: Likewise.
* testsuite/ld-x86-64/property-x86-ibt4.d: Likewise.
* testsuite/ld-x86-64/property-x86-ibt5-x32.d: Likewise.
* testsuite/ld-x86-64/property-x86-ibt5.d: Likewise.
* emulparams/elf32_x86_64.sh: Source emulparams/cet.sh.
(TINY_READONLY_SECTION): Add .plt.sec.
* emulparams/elf_i386.sh: Likewise.
* emulparams/elf_x86_64.sh: Source emulparams/cet.sh.
* ld.texinfo: Document -z ibtplt and -z ibt.
* testsuite/ld-i386/i386.exp: Run IBT and IBT PLT tests.
* testsuite/ld-x86-64/x86-64.exp: Likewise.
* testsuite/ld-x86-64/pr21481b.S (check): Updated for x32.
2017-06-22 14:44:37 +02:00
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2017-06-22 H.J. Lu <hongjiu.lu@intel.com>
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* bfdlink.h (bfd_link_info): Add ibtplt and ibt.
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* elf/common.h (GNU_PROPERTY_X86_FEATURE_1_AND): New.
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(GNU_PROPERTY_X86_FEATURE_1_IBT): Likewise.
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2017-06-21 17:32:40 +02:00
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2017-06-21 Thomas Preud'homme <thomas.preudhomme@arm.com>
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* opcode/arm.h (FPU_ANY): New macro.
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2017-06-26 11:07:17 +02:00
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2017-06-20 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
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* elf/s390.h (PT_S390_PGSTE): Define macro.
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Rewrite __start and __stop symbol handling
This arranges for __start and __stop symbols to be defined before
garbage collection, for all target formats. That should allow the
COFF and PE --gc-sections to keep a singleton orphan input section,
a feature lost by 2017-06-13 commit cbd0eecf26. The fancier ELF
treatment of keeping all input sections associated with a __start or
__stop symbol, from 2015-10-23 commit 1cce69b9dc, is retained.
.startof. and .sizeof. symbols are deliberately not defined before
garbage collection, so these won't affect garbage collection of
sections.
The patch also ensures __start, __stop, .startof. and .sizeof. symbols
are defined before target size_dynamic_sections is called, albeit
with a preliminary value, so that target code doesn't need to cope
with a symbol changing from undefined at size_dynamic_sections to
defined at relocate_section.
Also, a number of problems with the testcases have been fixed.
PR ld/20022
PR ld/21557
PR ld/21562
PR ld/21571
include/
* bfdlink.h (struct bfd_link_hash_entry): Delete undef.section.
bfd/
* targets.c (struct bfd_target): Add _bfd_define_start_stop.
(BFD_JUMP_TABLE_LINK): Likewise.
* elf-bfd.h (bfd_elf_define_start_stop): Declare.
* elflink.c (_bfd_elf_gc_mark_rsec): Update comment.
(bfd_elf_define_start_stop): New function.
* linker.c (bfd_generic_define_start_stop): New function.
* coff64-rs6000.c (rs6000_xcoff64_vec, rs6000_xcoff64_aix_vec): Init
new field.
* aout-adobe.c (aout_32_bfd_define_start_stop): Define.
* aout-target.h (MY_bfd_define_start_stop): Define.
* aout-tic30.c (MY_bfd_define_start_stop): Define.
* binary.c (binary_bfd_define_start_stop): Define.
* bout.c (b_out_bfd_define_start_stop): Define.
* coff-alpha.c (_bfd_ecoff_bfd_define_start_stop): Define.
* coff-mips.c (_bfd_ecoff_bfd_define_start_stop): Define.
* coff-rs6000.c (_bfd_xcoff_bfd_define_start_stop): Define.
* coffcode.h (coff_bfd_define_start_stop): Define.
* elfxx-target.h (bfd_elfNN_bfd_define_start_stop): Define.
* i386msdos.c (msdos_bfd_define_start_stop): Define.
* i386os9k.c (os9k_bfd_define_start_stop): Define.
* ieee.c (ieee_bfd_define_start_stop): Define.
* ihex.c (ihex_bfd_define_start_stop): Define.
* libbfd-in.h (_bfd_nolink_bfd_define_start_stop): Define.
* mach-o-target.c (bfd_mach_o_bfd_define_start_stop): Define.
* mmo.c (mmo_bfd_define_start_stop): Define.
* nlm-target.h (nlm_bfd_define_start_stop): Define.
* oasys.c (oasys_bfd_define_start_stop): Define.
* pef.c (bfd_pef_bfd_define_start_stop): Define.
* plugin.c (bfd_plugin_bfd_define_start_stop): Define.
* ppcboot.c (ppcboot_bfd_define_start_stop): Define.
* som.c (som_bfd_define_start_stop): Define.
* srec.c (srec_bfd_define_start_stop): Define.
* tekhex.c (tekhex_bfd_define_start_stop): Define.
* versados.c (versados_bfd_define_start_stop): Define.
* vms-alpha.c (vms_bfd_define_start_stop): Define.
(alpha_vms_bfd_define_start_stop): Define.
* xsym.c (bfd_sym_bfd_define_start_stop): Define.
* bfd-in2.h: Regenerate.
* libbfd.h: Regenerate.
ld/
* emultempl/elf32.em (gld${EMULATION_NAME}_after_open): Don't set
__start/__stop syms here.
* ldlang.c (lang_set_startof): Delete.
(start_stop_syms, start_stop_count, start_stop_alloc): New vars.
(lang_define_start_stop, lang_init_start_stop, foreach_start_stop,
undef_start_stop, lang_undef_start_stop, lang_init_startof_sizeof,
set_start_stop, lang_finalize_start_stop): New functions.
(lang_process): Call _start_stop functions.
* testsuite/ld-elf/pr21562a.d: Use xfail rather than notarget.
Correct typos and list of xfail targets.
* testsuite/ld-elf/pr21562b.d: Likewise.
* testsuite/ld-elf/pr21562c.d: Likewise.
* testsuite/ld-elf/pr21562d.d: Likewise.
* testsuite/ld-elf/pr21562e.d: Likewise.
* testsuite/ld-elf/pr21562f.d: Likewise.
* testsuite/ld-elf/pr21562g.d: Likewise.
* testsuite/ld-elf/pr21562h.d: Likewise.
* testsuite/ld-elf/pr21562i.d: Likewise.
* testsuite/ld-elf/pr21562j.d: Likewise.
* testsuite/ld-elf/pr21562k.d: Likewise.
* testsuite/ld-elf/pr21562l.d: Likewise.
* testsuite/ld-elf/pr21562m.d: Likewise.
* testsuite/ld-elf/pr21562n.d: Likewise.
* testsuite/ld-elf/sizeofa.d: Likewise. Adjust to pass for generic ELF.
* testsuite/ld-elf/sizeofb.d: Likewise.
* testsuite/ld-elf/startofa.d: Likewise.
* testsuite/ld-elf/startofb.d: Likewise.
2017-06-16 12:11:41 +02:00
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2017-06-16 Alan Modra <amodra@gmail.com>
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PR ld/20022
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PR ld/21557
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PR ld/21562
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PR ld/21571
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* bfdlink.h (struct bfd_link_hash_entry): Delete undef.section.
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Don't use print_insn_XXX in GDB
This is a follow-up to
[PATCH 0/6] Unify the disassembler selection in gdb and objdump
https://sourceware.org/ml/binutils/2017-05/msg00192.html
that is, opcodes is able to select the right disassembler, so gdb
doesn't have to select them. Instead, gdb can just use
default_print_insn. As a result, these print_insn_XXX are not used
out of opcodes, so this patch also moves their declarations from
include/dis-asm.h to opcodes/disassemble.h. With this change,
GDB doesn't use any print_insn_XXX directly any more.
gdb:
2017-06-14 Yao Qi <yao.qi@linaro.org>
* aarch64-tdep.c (aarch64_gdb_print_insn): Call
default_print_insn instead of print_insn_aarch64.
* arm-tdep.c (gdb_print_insn_arm): Call
default_print_insn instead of print_insn_big_arm
and print_insn_little_arm.
* i386-tdep.c (i386_print_insn): Call default_print_insn
instead of print_insn_i386.
* ia64-tdep.c (ia64_print_insn): Call
default_print_insn instead of print_insn_ia64.
* mips-tdep.c (gdb_print_insn_mips): Call
default_print_insn instead of print_insn_big_mips
and print_insn_little_mips.
* spu-tdep.c (gdb_print_insn_spu): Call default_print_insn
instead of print_insn_spu.
include:
2017-06-14 Yao Qi <yao.qi@linaro.org>
* dis-asm.h (print_insn_aarch64): Move it to opcodes/disassemble.h.
(print_insn_big_arm, print_insn_big_mips): Likewise.
(print_insn_i386, print_insn_ia64): Likewise.
(print_insn_little_arm, print_insn_little_mips): Likewise.
(print_insn_spu): Likewise.
opcodes:
2017-06-14 Yao Qi <yao.qi@linaro.org>
* aarch64-dis.c: Include disassemble.h instead of dis-asm.h.
* arm-dis.c: Likewise.
* ia64-dis.c: Likewise.
* mips-dis.c: Likewise.
* spu-dis.c: Likewise.
* disassemble.h (print_insn_aarch64): New declaration, moved from
include/dis-asm.h.
(print_insn_big_arm, print_insn_big_mips): Likewise.
(print_insn_i386, print_insn_ia64): Likewise.
(print_insn_little_arm, print_insn_little_mips): Likewise.
2017-06-14 17:28:30 +02:00
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2017-06-14 Yao Qi <yao.qi@linaro.org>
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* dis-asm.h (print_insn_aarch64): Move it to opcodes/disassemble.h.
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(print_insn_big_arm, print_insn_big_mips): Likewise.
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(print_insn_i386, print_insn_ia64): Likewise.
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(print_insn_little_arm, print_insn_little_mips): Likewise.
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(print_insn_spu): Likewise.
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ld: Allow section groups to be resolved as part of a relocatable link
This commit adds a new linker feature: the ability to resolve section
groups as part of a relocatable link.
Currently section groups are automatically resolved when performing a
final link, and are carried through when performing a relocatable link.
By carried through this means that one copy of each section group (from
all the copies that might be found in all the input files) is placed
into the output file. Sections that are part of a section group will
not match input section specifiers within a linker script and are
forcibly kept as separate sections.
There is a slight resemblance between section groups and common
section. Like section groups, common sections are carried through when
performing a relocatable link, and resolved (allocated actual space)
only at final link time.
However, with common sections there is an ability to force the linker to
allocate space for the common sections when performing a relocatable
link, there's currently no such ability for section groups.
This commit adds such a mechanism. This new facility can be accessed in
two ways, first there's a command line switch --force-group-allocation,
second, there's a new linker script command FORCE_GROUP_ALLOCATION. If
one of these is used when performing a relocatable link then the linker
will resolve the section groups as though it were performing a final
link, the section group will be deleted, and the members of the group
will be placed like normal input sections. If there are multiple copies
of the group (from multiple input files) then only one copy of the group
members will be placed, the duplicate copies will be discarded.
Unlike common sections that have the --no-define-common command line
flag, and INHIBIT_COMMON_ALLOCATION linker script command there is no
way to prevent group resolution during a final link, this is because the
ELF gABI specifically prohibits the presence of SHT_GROUP sections in a
fully linked executable. However, the code as written should make
adding such a feature trivial, setting the new resolve_section_groups
flag to false during a final link should work as you'd expect.
bfd/ChangeLog:
* elf.c (_bfd_elf_make_section_from_shdr): Don't initially mark
SEC_GROUP sections as SEC_EXCLUDE.
(bfd_elf_set_group_contents): Replace use of abort with an assert.
(assign_section_numbers): Use resolve_section_groups flag instead
of relocatable link type.
(_bfd_elf_init_private_section_data): Use resolve_section_groups
flag instead of checking the final_link flag for part of the
checks in here. Fix white space as a result.
* elflink.c (elf_link_input_bfd): Use resolve_section_groups flag
instead of relocatable link type.
(bfd_elf_final_link): Likewise.
include/ChangeLog:
* bfdlink.h (struct bfd_link_info): Add new resolve_section_groups
flag.
ld/ChangeLog:
* ld.h (struct args_type): Add force_group_allocation field.
* ldgram.y: Add support for FORCE_GROUP_ALLOCATION.
* ldlex.h: Likewise.
* ldlex.l: Likewise.
* lexsup.c: Likewise.
* ldlang.c (unique_section_p): Check resolve_section_groups flag
not the relaxable link flag.
(lang_add_section): Discard section groups when we're resolving
groups. Clear the SEC_LINK_ONCE flag if we're resolving section
groups.
* ldmain.c (main): Initialise resolve_section_groups flag in
link_info based on command line flags.
* testsuite/ld-elf/group11.d: New file.
* testsuite/ld-elf/group12.d: New file.
* testsuite/ld-elf/group12.ld: New file.
* NEWS: Mention new features.
* ld.texinfo (Options): Document --force-group-allocation.
(Miscellaneous Commands): Document FORCE_GROUP_ALLOCATION.
2017-03-22 18:27:49 +01:00
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2017-06-06 Andrew Burgess <andrew.burgess@embecosm.com>
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* bfdlink.h (struct bfd_link_info): Add new resolve_section_groups
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flag.
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PPC64_OPT_LOCALENTRY
ELFv2 functions with localentry:0 are those with a single entry point,
ie. global entry == local entry, and that have no requirement on r2 or
r12, and guarantee r2 is unchanged on return. Such an external
function can be called via the PLT without saving r2 or restoring it
on return, avoiding a common load-hit-store for small functions. The
optimization is attractive. The TOC pointer load-hit-store is a major
reason why calls to small functions that need no register saves, or
with shrink-wrap, no register saves on a fast path, are slow on
powerpc64le.
To be safe, this optimization needs ld.so support to check that the
run-time matches link-time function implementation. If a function
in a shared library with st_other localentry non-zero is called
without saving and restoring r2, r2 will be trashed on return, leading
to segfaults. For that reason the optimization does not happen for
weak functions since a weak definition is a fairly solid hint that the
function will likely be overridden. I'm also not enabling the
optimization by default unless glibc-2.26 is detected, which should
have the ld.so checks implemented.
bfd/
* elf64-ppc.c (struct ppc_link_hash_table): Add has_plt_localentry0.
(ppc64_elf_merge_symbol_attribute): Merge localentry bits from
dynamic objects.
(is_elfv2_localentry0): New function.
(ppc64_elf_tls_setup): Default params->plt_localentry0.
(plt_stub_size): Adjust size for tls_get_addr_opt stub.
(build_tls_get_addr_stub): Use a simpler stub when r2 is not saved.
(ppc64_elf_size_stubs): Leave stub_type as ppc_stub_plt_call for
optimized localentry:0 stubs.
(ppc64_elf_build_stubs): Save r2 in ELFv2 __glink_PLTresolve.
(ppc64_elf_relocate_section): Leave nop unchanged for optimized
localentry:0 stubs.
(ppc64_elf_finish_dynamic_sections): Set PPC64_OPT_LOCALENTRY in
DT_PPC64_OPT.
* elf64-ppc.h (struct ppc64_elf_params): Add plt_localentry0.
include/
* elf/ppc64.h (PPC64_OPT_LOCALENTRY): Define.
ld/
* emultempl/ppc64elf.em (params): Init plt_localentry0 field.
(enum ppc64_opt): New, replacing OPTION_* defines. Add
OPTION_PLT_LOCALENTRY, and OPTION_NO_PLT_LOCALENTRY.
(PARSE_AND_LIST_*): Support --plt-localentry and --no-plt-localentry.
* testsuite/ld-powerpc/elfv2so.d: Update.
* testsuite/ld-powerpc/powerpc.exp (TLS opt 5): Use --no-plt-localentry.
* testsuite/ld-powerpc/tlsopt5.d: Update.
2017-05-26 02:32:29 +02:00
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2017-06-01 Alan Modra <amodra@gmail.com>
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* elf/ppc64.h (PPC64_OPT_LOCALENTRY): Define.
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2017-05-31 08:35:07 +02:00
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2017-05-31 Eli Zaretskii <eliz@gnu.org>
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* environ.h: Add #ifndef guard.
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2017-04-07 16:22:39 +02:00
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2017-05-30 Anton Kolesov <anton.kolesov@synopsys.com>
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* elf/arc-cpu.def: New file.
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Move print_insn_XXX to an opcodes internal header
With the changes done in previous patches, print_insn_XXX functions
don't have to be external visible out of opcodes, because both gdb
and objdump select disassemblers through a single interface.
This patch moves these print_insn_XXX declarations from
include/dis-asm.h to opcodes/disassemble.h, which is a new header
added by this patch.
include:
2017-05-24 Yao Qi <yao.qi@linaro.org>
* dis-asm.h: Move some function declarations to
opcodes/disassemble.h.
opcodes:
2017-05-24 Yao Qi <yao.qi@linaro.org>
* alpha-dis.c: Include disassemble.h, don't include
dis-asm.h.
* avr-dis.c, bfin-dis.c, cr16-dis.c: Likewise.
* crx-dis.c, d10v-dis.c, d30v-dis.c: Likewise.
* disassemble.c, dlx-dis.c, epiphany-dis.c: Likewise.
* fr30-dis.c, ft32-dis.c, h8300-dis.c, h8500-dis.c: Likewise.
* hppa-dis.c, i370-dis.c, i386-dis.c: Likewise.
* i860-dis.c, i960-dis.c, ip2k-dis.c: Likewise.
* iq2000-dis.c, lm32-dis.c, m10200-dis.c: Likewise.
* m10300-dis.c, m32r-dis.c, m68hc11-dis.c: Likewise.
* m68k-dis.c, m88k-dis.c, mcore-dis.c: Likewise.
* metag-dis.c, microblaze-dis.c, mmix-dis.c: Likewise.
* moxie-dis.c, msp430-dis.c, mt-dis.c:
* nds32-dis.c, nios2-dis.c, ns32k-dis.c: Likewise.
* or1k-dis.c, pdp11-dis.c, pj-dis.c: Likewise.
* ppc-dis.c, pru-dis.c, riscv-dis.c: Likewise.
* rl78-dis.c, s390-dis.c, score-dis.c: Likewise.
* sh-dis.c, sh64-dis.c, tic30-dis.c: Likewise.
* tic4x-dis.c, tic54x-dis.c, tic6x-dis.c: Likewise.
* tic80-dis.c, tilegx-dis.c, tilepro-dis.c: Likewise.
* v850-dis.c, vax-dis.c, visium-dis.c: Likewise.
* w65-dis.c, wasm32-dis.c, xc16x-dis.c: Likewise.
* xgate-dis.c, xstormy16-dis.c, xtensa-dis.c: Likewise.
* z80-dis.c, z8k-dis.c: Likewise.
* disassemble.h: New file.
2017-05-24 18:23:52 +02:00
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2017-05-24 Yao Qi <yao.qi@linaro.org>
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* dis-asm.h: Move some function declarations to
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opcodes/disassemble.h.
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2017-05-24 18:23:52 +02:00
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2017-05-24 Yao Qi <yao.qi@linaro.org>
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* dis-asm.h (disassembler): Update declaration.
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2017-05-23 12:18:10 +02:00
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2017-05-23 Claudiu Zissulescu <claziss@synopsys.com>
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* opcode/arc.h (MAX_INSN_FLGS): Update to 4.
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2017-05-22 20:02:46 +02:00
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2017-05-22 H.J. Lu <hongjiu.lu@intel.com>
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* include/opcode/i386.h (NOTRACK_PREFIX_OPCODE): New.
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binutils: support for the SPARC M8 processor
This patch adds support for the new SPARC M8 processor (implementing OSA
2017) to binutils.
New instructions:
- Dictionary Unpack
+ dictunpack
- Partitioned Compare with shifted result
+ Signed variants: fpcmp{le,gt,eq,ne}{8,16,32}shl
+ Unsigned variants: fpcmpu{le,gt}{8,16,32}shl
- Partitioned Dual-Equal compared, with shifted result
+ fpcmpde{8,16,32}shl
- Partitioned Unsigned Range Compare, with shifted result
+ fpcmpur{8,16,32}shl
- 64-bit shifts on Floating-Point registers
+ fps{ll,ra,rl}64x
- Misaligned loads and stores
+ ldm{sh,uh,sw,uw,x,ux}
+ ldm{sh,uh,sw,uw,x,ux}a
+ ldmf{s,d}
+ ldmf{s,d}a
+ stm{h,w,x}
+ stm{h,w,x}a
+ stmf{s,d}
+ stmf{s,d}a
- Oracle Numbers
+ on{add,sub,mul,div}
- Reverse Bytes/Bits
+ revbitsb
+ revbytes{h,w,x}
- Run-Length instructions
+ rle_burst
+ rle_length
- New crypto instructions
+ sha3
- Instruction to read the new register %entropy
+ rd %entropy
New Alternate Address Identifiers:
- 0x24, #ASI_CORE_COMMIT_COUNT
- 0x24, #ASI_CORE_SELECT_COUNT
- 0x48, #ASI_ARF_ECC_REG
- 0x53, #ASI_ITLB_PROBE
- 0x58, #ASI_DSFAR
- 0x5a, #ASI_DTLB_PROBE_PRIMARY
- 0x5b, #ASI_DTLB_PROBE_REAL
- 0x64, #ASI_CORE_SELECT_COMMIT_NHT
The new assembler command-line options for selecting the M8 architecture
are:
-Av9m8 or -Asparc6 for 64-bit binaries.
-Av8plusm8 for 32-bit (v8+) binaries.
The corresponding disassembler command-line options are:
-msparc:v9m8 for 64-bit binaries.
-msparc:v8plusm8 for 32-bit (v8+) binaries.
Tested for regressions in the following targets:
sparc-aout sparc-linux sparc-vxworks sparc64-linux
bfd/ChangeLog:
2017-05-19 Jose E. Marchesi <jose.marchesi@oracle.com>
* archures.c (bfd_mach_sparc_v9m8): Define.
(bfd_mach_sparc_v8plusm8): Likewise.
(bfd_mach_sparc_v9_p): Adjust to M8.
(bfd_mach_sparc_64bit_p): Likewise.
* aoutx.h (machine_type): Handle bfd_mach_sparc_v9m8 and
bfd_mach_sparc_v8plusm8.
* bfd-in2.h: Regenerated.
* cpu-sparc.c (arch_info_struct): Entries for sparc:v9m8 and
sparc:v8plusm8.
* elfxx-sparc.c (_bfd_sparc_elf_object_p): Handle
bfd_mach_sparc_v8plusm8 and bfd_mach_sparc_v9m8 using the new hw
capabilities ONADDSUB, ONMUL, ONDIV, DICTUNP, FPCPSHL, RLE and
SHA3.
* elf32-sparc.c (elf32_sparc_final_write_processing): Handle
bfd_mach_sparc_v8plusm8.
binutils/ChangeLog:
2017-05-19 Jose E. Marchesi <jose.marchesi@oracle.com>
* NEWS: Mention the SPARC M8 support.
gas/ChangeLog:
2017-05-19 Jose E. Marchesi <jose.marchesi@oracle.com>
* config/tc-sparc.c (sparc_arch_table): Entries for `sparc6',
`v9m8' and `v8plusm8'.
(sparc_md_end): Handle SPARC_OPCODE_ARCH_M8.
(get_hwcap_name): Support the M8 hardware capabilities.
(sparc_ip): Handle new operand types.
* doc/c-sparc.texi (Sparc-Opts): Document -Av9m8, -Av8plusm8 and
-Asparc6, and the corresponding -xarch aliases.
* testsuite/gas/sparc/sparc6.s: New file.
* testsuite/gas/sparc/sparc6.d: Likewise.
* testsuite/gas/sparc/sparc6-diag.s: Likewise.
* testsuite/gas/sparc/sparc6-diag.l: Likewise.
* testsuite/gas/sparc/fpcmpshl.s: Likewise.
* testsuite/gas/sparc/fpcmpshl.d: Likewise.
* testsuite/gas/sparc/fpcmpshl-diag.s: Likewise.
* testsuite/gas/sparc/fpcmpshl-diag.l: Likewise.
* testsuite/gas/sparc/ldm-stm.s: Likewise.
* testsuite/gas/sparc/ldm-stm.d: Likewise.
* testsuite/gas/sparc/ldm-stm-diag.s: Likewise.
* testsuite/gas/sparc/ldm-stm-diag.l: Likewise.
* testsuite/gas/sparc/ldmf-stmf.s: Likewise.
* testsuite/gas/sparc/ldmf-stmf.d: Likewise.
* testsuite/gas/sparc/ldmf-stmf-diag.s: Likewise.
* testsuite/gas/sparc/ldmf-stmf-diag.l: Likewise.
* testsuite/gas/sparc/on.s: Likewise.
* testsuite/gas/sparc/on.d: Likewise.
* testsuite/gas/sparc/on-diag.s: Likewise.
* testsuite/gas/sparc/on-diag.l: Likewise.
* testsuite/gas/sparc/rle.s: Likewise.
* testsuite/gas/sparc/rle.d: Likewise.
* testsuite/gas/sparc/sparc.exp (gas_64_check): Run new tests.
* testsuite/gas/sparc/rdasr.s: Add test for RDENTROPY.
* testsuite/gas/sparc/rdasr.d: Likewise.
include/ChangeLog:
2017-05-19 Jose E. Marchesi <jose.marchesi@oracle.com>
* elf/sparc.h (ELF_SPARC_HWCAP2_SPARC6): Define.
(ELF_SPARC_HWCAP2_ONADDSUB): Likewise.
(ELF_SPARC_HWCAP2_ONMUL): Likewise.
(ELF_SPARC_HWCAP2_ONDIV): Likewise.
(ELF_SPARC_HWCAP2_DICTUNP): Likewise.
(ELF_SPARC_HWCAP2_FPCMPSHL): Likewise.
(ELF_SPARC_HWCAP2_RLE): Likewise.
(ELF_SPARC_HWCAP2_SHA3): Likewise.
* opcode/sparc.h (sparc_opcode_arch_val): Add SPARC_OPCODE_ARCH_M8
and adjust SPARC_OPCODE_ARCH_MAX.
(HWCAP2_SPARC6): Define.
(HWCAP2_ONADDSUB): Likewise.
(HWCAP2_ONMUL): Likewise.
(HWCAP2_ONDIV): Likewise.
(HWCAP2_DICTUNP): Likewise.
(HWCAP2_FPCMPSHL): Likewise.
(HWCAP2_RLE): Likewise.
(HWCAP2_SHA3): Likewise.
(OPM): Likewise.
(OPMI): Likewise.
(ONFCN): Likewise.
(REVFCN): Likewise.
(SIMM10): Likewise.
opcodes/ChangeLog:
2017-05-19 Jose E. Marchesi <jose.marchesi@oracle.com>
* sparc-dis.c (MASK_V9): Include SPARC_OPCODE_ARCH_M8.
(X_IMM2): Define.
(compute_arch_mask): Handle bfd_mach_sparc_v8plusm8 and
bfd_mach_sparc_v9m8.
(print_insn_sparc): Handle new operand types.
* sparc-opc.c (MASK_M8): Define.
(v6): Add MASK_M8.
(v6notlet): Likewise.
(v7): Likewise.
(v8): Likewise.
(v9): Likewise.
(v9a): Likewise.
(v9b): Likewise.
(v9c): Likewise.
(v9d): Likewise.
(v9e): Likewise.
(v9v): Likewise.
(v9m): Likewise.
(v9andleon): Likewise.
(m8): Define.
(HWS_VM8): Define.
(HWS2_VM8): Likewise.
(sparc_opcode_archs): Add entry for "m8".
(sparc_opcodes): Add OSA2017 and M8 instructions
dictunpack, fpcmp{ule,ugt,eq,ne,de,ur}{8,16,32}shl,
fpx{ll,ra,rl}64x,
ldm{sh,uh,sw,uw,x,ux}, ldm{sh,uh,sw,uw,x,ux}a, ldmf{s,d},
ldmf{s,d}a, on{add,sub,mul,div}, rdentropy, revbitsb,
revbytes{h,w,x}, rle_burst, rle_length, sha3, stm{h,w,x},
stm{h,w,x}a, stmf{s,d}, stmf{s,d}a.
(asi_table): New M8 ASIs ASI_CORE_COMMIT_COUNT,
ASI_CORE_SELECT_COUNT, ASI_ARF_ECC_REG, ASI_ITLB_PROBE, ASI_DSFAR,
ASI_DTLB_PROBE_PRIMARY, ASI_DTLB_PROBE_REAL,
ASI_CORE_SELECT_COMMIT_NHT.
2017-05-19 18:27:08 +02:00
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2017-05-19 Jose E. Marchesi <jose.marchesi@oracle.com>
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* elf/sparc.h (ELF_SPARC_HWCAP2_SPARC6): Define.
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(ELF_SPARC_HWCAP2_ONADDSUB): Likewise.
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(ELF_SPARC_HWCAP2_ONMUL): Likewise.
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(ELF_SPARC_HWCAP2_ONDIV): Likewise.
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(ELF_SPARC_HWCAP2_DICTUNP): Likewise.
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(ELF_SPARC_HWCAP2_FPCMPSHL): Likewise.
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(ELF_SPARC_HWCAP2_RLE): Likewise.
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(ELF_SPARC_HWCAP2_SHA3): Likewise.
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* opcode/sparc.h (sparc_opcode_arch_val): Add SPARC_OPCODE_ARCH_M8
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and adjust SPARC_OPCODE_ARCH_MAX.
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(HWCAP2_SPARC6): Define.
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(HWCAP2_ONADDSUB): Likewise.
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(HWCAP2_ONMUL): Likewise.
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(HWCAP2_ONDIV): Likewise.
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(HWCAP2_DICTUNP): Likewise.
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(HWCAP2_FPCMPSHL): Likewise.
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(HWCAP2_RLE): Likewise.
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(HWCAP2_SHA3): Likewise.
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(OPM): Likewise.
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(OPMI): Likewise.
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(ONFCN): Likewise.
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(REVFCN): Likewise.
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(SIMM10): Likewise.
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2017-05-16 00:28:14 +02:00
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2017-05-16 Alan Modra <amodra@gmail.com>
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* bfdlink.h (struct bfd_link_hash_entry <non_ir_ref>): Rename to
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non_ir_ref_regular.
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2017-05-16 00:26:41 +02:00
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2017-05-16 Alan Modra <amodra@gmail.com>
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* bfdlink.h (struct bfd_link_hash_entry): Update non_ir_ref
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comment. Rename dynamic_ref_after_ir_def to non_ir_ref_dynamic.
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MIPS16e2: Add MIPS16e2 ASE support
Add MIPS16e2 ASE support as per the architecture specification[1],
including in particular:
1. A new ELF ASE flag to mark MIPS16e2 binaries.
2. MIPS16e2 instruction assembly support, including a relaxation update
to use LUI rather than an LI/SLL instruction pair for loading the
high part of 32-bit addresses.
3. MIPS16e2 instruction disassembly support, including updated rules for
extended forms of instructions that are now subdecoded and therefore
do not alias to the original MIPS16 ISA revision instructions even
for encodings that are not valid in the MIPS16e2 instruction set.
Add `-mmips16e2' and `-mno-mips16e2' GAS command-line options and their
corresponding `mips16e2' and `no-mips16e2' settings for the `.set' and
`.module' pseudo-ops. Control the availability of the MT ASE subset of
the MIPS16e2 instruction set with a combination of these controls and
the preexisting MT ASE controls.
Parts of this change by Matthew Fortune and Andrew Bennett.
References:
[1] "MIPS32 Architecture for Programmers: MIPS16e2 Application-Specific
Extension Technical Reference Manual", Imagination Technologies
Ltd., Document Number: MD01172, Revision 01.00, April 26, 2016
include/
* elf/mips.h (AFL_ASE_MIPS16E2): New macro.
(AFL_ASE_MASK): Adjust accordingly.
* opcode/mips.h: Document new operand codes defined.
(mips_operand_type): Add OP_REG28 enum value.
(INSN2_SHORT_ONLY): Update description.
(ASE_MIPS16E2, ASE_MIPS16E2_MT): New macros.
bfd/
* elfxx-mips.c (print_mips_ases): Handle MIPS16e2 ASE.
opcodes/
* mips-dis.c (mips_arch_choices): Add ASE_MIPS16E2 and
ASE_MIPS16E2_MT flags to the unnamed MIPS16 entry.
(mips_convert_abiflags_ases): Handle the AFL_ASE_MIPS16E2 flag.
(print_insn_arg) <OP_REG28>: Add handler.
(validate_insn_args) <OP_REG28>: Handle.
(print_mips16_insn_arg): Handle MIPS16 instructions that require
32-bit encoding and 9-bit immediates.
(print_insn_mips16): Handle MIPS16 instructions that require
32-bit encoding and MFC0/MTC0 operand decoding.
* mips16-opc.c (decode_mips16_operand) <'>', '9', 'G', 'N', 'O'>
<'Q', 'T', 'b', 'c', 'd', 'r', 'u'>: Add handlers.
(RD_C0, WR_C0, E2, E2MT): New macros.
(mips16_opcodes): Add entries for MIPS16e2 instructions:
GP-relative "addiu" and its "addu" spelling, "andi", "cache",
"di", "ehb", "ei", "ext", "ins", GP-relative "lb", "lbu", "lh",
"lhu", and "lw" instructions, "ll", "lui", "lwl", "lwr", "mfc0",
"movn", "movtn", "movtz", "movz", "mtc0", "ori", "pause",
"pref", "rdhwr", "sc", GP-relative "sb", "sh" and "sw"
instructions, "swl", "swr", "sync" and its "sync_acquire",
"sync_mb", "sync_release", "sync_rmb" and "sync_wmb" aliases,
"xori", "dmt", "dvpe", "emt" and "evpe". Add split
regular/extended entries for original MIPS16 ISA revision
instructions whose extended forms are subdecoded in the MIPS16e2
ISA revision: "li", "sll" and "srl".
binutils/
* readelf.c (print_mips_ases): Handle MIPS16e2 ASE.
* NEWS: Mention MIPS16e2 ASE support.
gas/
* config/tc-mips.c (RELAX_MIPS16_ENCODE): Add `e2' flag.
(RELAX_MIPS16_E2): New macro.
(RELAX_MIPS16_PIC, RELAX_MIPS16_SYM32, RELAX_MIPS16_NOMACRO)
(RELAX_MIPS16_USER_SMALL, RELAX_MIPS16_USER_EXT)
(RELAX_MIPS16_DSLOT, RELAX_MIPS16_JAL_DSLOT)
(RELAX_MIPS16_EXTENDED, RELAX_MIPS16_MARK_EXTENDED)
(RELAX_MIPS16_CLEAR_EXTENDED, RELAX_MIPS16_ALWAYS_EXTENDED)
(RELAX_MIPS16_MARK_ALWAYS_EXTENDED)
(RELAX_MIPS16_CLEAR_ALWAYS_EXTENDED, RELAX_MIPS16_MACRO)
(RELAX_MIPS16_MARK_MACRO, RELAX_MIPS16_CLEAR_MACRO): Shift bits.
(mips16_immed_extend): New prototype.
(options): Add OPTION_MIPS16E2 and OPTION_NO_MIPS16E2 enum
values.
(md_longopts): Add "mmips16e2" and "mno-mips16e2" options.
(mips_ases): Add "mips16e2" entry.
(mips_set_ase): Handle MIPS16e2 ASE.
(insn_insert_operand): Explicitly handle immediates with MIPS16
instructions that require 32-bit encoding.
(is_opcode_valid_16): Pass enabled ASE bitmask on to
`opcode_is_member'.
(validate_mips_insn): Explicitly handle immediates with MIPS16
instructions that require 32-bit encoding.
(operand_reg_mask) <OP_REG28>: Add handler.
(match_reg28_operand): New function.
(match_operand) <OP_REG28>: Add handler.
(append_insn): Pass ASE_MIPS16E2 setting to RELAX_MIPS16_ENCODE.
(match_mips16_insn): Handle MIPS16 instructions that require
32-bit encoding and `V' and `u' operand codes.
(mips16_ip): Allow any characters except from `.' in opcodes.
(mips16_immed_extend): Handle 9-bit immediates. Do not shuffle
immediates whose width is not one of these listed.
(md_estimate_size_before_relax): Handle MIPS16e2 relaxation.
(mips_relax_frag): Likewise.
(md_convert_frag): Likewise.
(mips_convert_ase_flags): Handle MIPS16e2 ASE.
* doc/as.texinfo (Target MIPS options): Add `-mmips16e2' and
`-mno-mips16e2' options.
(-mmips16e2, -mno-mips16e2): New options.
* doc/c-mips.texi (MIPS Options): Add `-mmips16e2' and
`-mno-mips16e2' options.
(MIPS ASE Instruction Generation Overrides): Add `.set mips16e2'
and `.set nomips16e2'.
2017-05-15 14:26:01 +02:00
|
|
|
|
2017-05-15 Maciej W. Rozycki <macro@imgtec.com>
|
|
|
|
|
|
Matthew Fortune <matthew.fortune@imgtec.com>
|
|
|
|
|
|
|
|
|
|
|
|
* elf/mips.h (AFL_ASE_MIPS16E2): New macro.
|
|
|
|
|
|
(AFL_ASE_MASK): Adjust accordingly.
|
|
|
|
|
|
* opcode/mips.h: Document new operand codes defined.
|
|
|
|
|
|
(mips_operand_type): Add OP_REG28 enum value.
|
|
|
|
|
|
(INSN2_SHORT_ONLY): Update description.
|
|
|
|
|
|
(ASE_MIPS16E2, ASE_MIPS16E2_MT): New macros.
|
|
|
|
|
|
|
2017-05-14 22:06:06 +02:00
|
|
|
|
2017-05-14 John David Anglin <danglin@gcc.gnu.org>
|
|
|
|
|
|
|
|
|
|
|
|
* opcode/hppa.h: Fix match and mask for 64-bit bb opcode.
|
|
|
|
|
|
|
[ARC] Object attributes.
gas/
2017-05-10 Claudiu Zissulescu <claziss@synopsys.com>
* testsuite/gas/arc/attr-arc600.d: New file.
* testsuite/gas/arc/attr-arc600_mul32x16.d: Likewise.
* testsuite/gas/arc/attr-arc600_norm.d: Likewise.
* testsuite/gas/arc/attr-arc601.d: Likewise.
* testsuite/gas/arc/attr-arc601_mul32x16.d: Likewise.
* testsuite/gas/arc/attr-arc601_mul64.d: Likewise.
* testsuite/gas/arc/attr-arc601_norm.d: Likewise.
* testsuite/gas/arc/attr-arc700.d: Likewise.
* testsuite/gas/arc/attr-arcem.d: Likewise.
* testsuite/gas/arc/attr-archs.d: Likewise.
* testsuite/gas/arc/attr-autodetect-1.d: Likewise.
* testsuite/gas/arc/attr-autodetect-1.s: Likewise.
* testsuite/gas/arc/attr-cpu-a601.d: Likewise.
* testsuite/gas/arc/attr-cpu-a601.s: Likewise.
* testsuite/gas/arc/attr-cpu-a700.d: Likewise.
* testsuite/gas/arc/attr-cpu-a700.s: Likewise.
* testsuite/gas/arc/attr-cpu-em.d: Likewise.
* testsuite/gas/arc/attr-cpu-em.s: Likewise.
* testsuite/gas/arc/attr-cpu-hs.d: Likewise.
* testsuite/gas/arc/attr-cpu-hs.s: Likewise.
* testsuite/gas/arc/attr-em.d: Likewise.
* testsuite/gas/arc/attr-em4.d: Likewise.
* testsuite/gas/arc/attr-em4_dmips.d: Likewise.
* testsuite/gas/arc/attr-em4_fpuda.d: Likewise.
* testsuite/gas/arc/attr-em4_fpus.d: Likewise.
* testsuite/gas/arc/attr-hs.d: Likewise.
* testsuite/gas/arc/attr-hs34.d: Likewise.
* testsuite/gas/arc/attr-hs38.d: Likewise.
* testsuite/gas/arc/attr-hs38_linux.d: Likewise.
* testsuite/gas/arc/attr-mul64.d: Likewise.
* testsuite/gas/arc/attr-name.d: Likewise.
* testsuite/gas/arc/attr-name.s: Likewise.
* testsuite/gas/arc/attr-nps400.d: Likewise.
* testsuite/gas/arc/attr-override-mcpu.d: Likewise.
* testsuite/gas/arc/attr-override-mcpu.s
* testsuite/gas/arc/attr-quarkse_em.d: Likewise.
* testsuite/gas/arc/blank.s: Likewise.
* testsuite/gas/elf/section2.e-arc: Likewise.
* testsuite/gas/arc/cpu-pseudop-1.d: Update test.
* testsuite/gas/arc/cpu-pseudop-2.d: Likewise.
* testsuite/gas/arc/nps400-0.d: Likewise.
* testsuite/gas/elf/elf.exp: Set target_machine for ARC.
* config/tc-arc.c (opcode/arc-attrs.h): Include.
(ARC_GET_FLAG, ARC_SET_FLAG, streq): Define.
(arc_attribute): Declare new function.
(md_pseudo_table): Add arc_attribute.
(cpu_types): Rename default cpu features.
(selected_cpu): Set the default OSABI flag.
(mpy_option): New variable.
(pic_option): Likewise.
(sda_option): Likewise.
(tls_option): Likewise.
(feature_type, feature_list): Remove.
(arc_initial_eflag): Likewise.
(attributes_set_explicitly): New variable.
(arc_check_feature): Check also for the conflicting features.
(arc_select_cpu): Refactor assignment of selected_cpu.eflags.
(arc_option): Remove setting of private flags and architecture.
(check_cpu_feature): Refactor feature names.
(autodetect_attributes): New function.
(assemble_tokens): Use above function.
(md_parse_option): Refactor feature names.
(arc_attribute): New function.
(arc_set_attribute_int): Likewise.
(arc_set_attribute_string): Likewise.
(arc_stralloc): Likewise.
(arc_set_public_attributes): Likewise.
(arc_md_end): Likewise.
(arc_copy_symbol_attributes): Likewise.
(rc_convert_symbolic_attribute): Likewise.
* config/tc-arc.h (md_end): Define.
(CONVERT_SYMBOLIC_ATTRIBUTE): Likewise.
(TC_COPY_SYMBOL_ATTRIBUTES): Likewise.
* doc/c-arc.texi: Document ARC object attributes.
binutils/
2017-05-10 Claudiu Zissulescu <claziss@synopsys.com>
* readelf.c (decode_ARC_machine_flags): Recognize OSABI v4.
(get_arc_section_type_name): New function.
(get_section_type_name): Use the above function.
(display_arc_attribute): New function.
(process_arc_specific): Likewise.
(process_arch_specific): Handle ARC specific information.
* testsuite/binutils-all/strip-3.d: Consider ARC.attributes
section.
include/
2017-05-10 Claudiu Zissulescu <claziss@synopsys.com>
* elf/arc.h (SHT_ARC_ATTRIBUTES): Define.
(Tag_ARC_*): Define.
(E_ARC_OSABI_V4): Define.
(E_ARC_OSABI_CURRENT): Reassign it.
(TAG_CPU_*): Define.
* opcode/arc-attrs.h: New file.
* opcode/arc.h (insn_subclass_t): Assign enum values.
(insn_subclass_t): Update enum with QUARKSE1, QUARKSE2, and LL64.
(ARC_EA, ARC_CD, ARC_LLOCK, ARC_ATOMIC, ARC_MPY, ARC_MULT)
(ARC_NPS400, ARC_DPFP, ARC_SPFP, ARC_FPU, ARC_FPUDA, ARC_SWAP)
(ARC_NORM, ARC_BSCAN, ARC_UIX, ARC_TSTAMP, ARC_VBFDW)
(ARC_BARREL, ARC_DSPA, ARC_SHIFT, ARC_INTR, ARC_DIV, ARC_XMAC)
(ARC_CRC): Delete.
bfd/
2017-05-10 Claudiu Zissulescu <claziss@synopsys.com>
* elf32-arc.c (FEATURE_LIST_NAME): Define.
(CONFLICT_LIST): Likewise.
(opcode/arc-attrs.h): Include.
(arc_elf_print_private_bfd_data): Print OSABI v4 flag.
(arc_extract_features): New file.
(arc_stralloc): Likewise.
(arc_elf_merge_attributes): Likewise.
(arc_elf_merge_private_bfd_data): Use object attributes.
(bfd_arc_get_mach_from_attributes): New function.
(arc_elf_object_p): Use object attributes.
(arc_elf_final_write_processing): Likewise.
(elf32_arc_obj_attrs_arg_type): New function.
(elf32_arc_obj_attrs_handle_unknown): Likewise.
(elf32_arc_section_from_shdr): Likewise.
(elf_backend_obj_attrs_vendor): Define.
(elf_backend_obj_attrs_section): Likewise.
(elf_backend_obj_attrs_arg_type): Likewise.
(elf_backend_obj_attrs_section_type): Likewise.
(elf_backend_obj_attrs_handle_unknown): Likewise.
(elf_backend_section_from_shdr): Likewise.
ld/
2017-05-10 Claudiu Zissulescu <claziss@synopsys.com>
* testsuite/ld-arc/attr-merge-0.d: New file.
* testsuite/ld-arc/attr-merge-0.s: Likewise.
* testsuite/ld-arc/attr-merge-0e.s: Likewise.
* testsuite/ld-arc/attr-merge-1.d: Likewise.
* testsuite/ld-arc/attr-merge-1.s: Likewise.
* testsuite/ld-arc/attr-merge-1e.s: Likewise.
* testsuite/ld-arc/attr-merge-2.d: Likewise.
* testsuite/ld-arc/attr-merge-2.s: Likewise.
* testsuite/ld-arc/attr-merge-3.d: Likewise.
* testsuite/ld-arc/attr-merge-3.s: Likewise.
* testsuite/ld-arc/attr-merge-3e.s: Likewise.
* testsuite/ld-arc/attr-merge-4.s: Likewise.
* testsuite/ld-arc/attr-merge-5.d: Likewise.
* testsuite/ld-arc/attr-merge-5a.s: Likewise.
* testsuite/ld-arc/attr-merge-5b.s: Likewise.
* testsuite/ld-arc/attr-merge-conflict-isa.d: Likewise.
* testsuite/ld-arc/attr-merge-err-isa.d: Likewise.
* testsuite/ld-arc/attr-merge-incompatible-cpu.d: Likewise.
* testsuite/ld-arc/got-01.d: Update test.
* testsuite/ld-arc/attr-merge-err-quarkse.d: New file.
* testsuite/ld-arc/attr-quarkse.s: Likewise.
* testsuite/ld-arc/attr-quarkse2.s: Likewise.
opcodes/
2017-05-10 Claudiu Zissulescu <claziss@synopsys.com>
* arc-dis.c (parse_option): Update quarkse_em option..
* arc-ext-tbl.h (dsp_fp_flt2i, dsp_fp_i2flt): Change subclass to
QUARKSE1.
(dsp_fp_div, dsp_fp_cmp): Change subclass to QUARKSE2.
2017-05-10 14:42:22 +02:00
|
|
|
|
2017-05-10 Claudiu Zissulescu <claziss@synopsys.com>
|
|
|
|
|
|
|
|
|
|
|
|
* elf/arc.h (SHT_ARC_ATTRIBUTES): Define.
|
|
|
|
|
|
(Tag_ARC_*): Define.
|
|
|
|
|
|
(E_ARC_OSABI_V4): Define.
|
|
|
|
|
|
(E_ARC_OSABI_CURRENT): Reassign it.
|
|
|
|
|
|
(TAG_CPU_*): Define.
|
|
|
|
|
|
* opcode/arc-attrs.h: New file.
|
|
|
|
|
|
* opcode/arc.h (insn_subclass_t): Assign enum values.
|
|
|
|
|
|
(insn_subclass_t): Update enum with QUARKSE1, QUARKSE2, and LL64.
|
|
|
|
|
|
(ARC_EA, ARC_CD, ARC_LLOCK, ARC_ATOMIC, ARC_MPY, ARC_MULT)
|
|
|
|
|
|
(ARC_NPS400, ARC_DPFP, ARC_SPFP, ARC_FPU, ARC_FPUDA, ARC_SWAP)
|
|
|
|
|
|
(ARC_NORM, ARC_BSCAN, ARC_UIX, ARC_TSTAMP, ARC_VBFDW)
|
|
|
|
|
|
(ARC_BARREL, ARC_DSPA, ARC_SHIFT, ARC_INTR, ARC_DIV, ARC_XMAC)
|
|
|
|
|
|
(ARC_CRC): Delete.
|
|
|
|
|
|
|
2017-04-20 16:48:24 +02:00
|
|
|
|
2017-04-20 H.J. Lu <hongjiu.lu@intel.com>
|
|
|
|
|
|
|
|
|
|
|
|
PR ld/21382
|
|
|
|
|
|
* bfdlink.h (bfd_link_hash_entry): Add dynamic_ref_after_ir_def.
|
|
|
|
|
|
|
2017-04-18 17:56:57 +02:00
|
|
|
|
2017-04-19 Alan Modra <amodra@gmail.com>
|
|
|
|
|
|
|
|
|
|
|
|
* bfdlink.h (struct bfd_link_info <dynamic_undefined_weak>):
|
|
|
|
|
|
Revise comment.
|
|
|
|
|
|
|
2017-04-11 00:03:50 +02:00
|
|
|
|
2017-04-11 Alan Modra <amodra@gmail.com>
|
|
|
|
|
|
|
|
|
|
|
|
* opcode/ppc.h (PPC_OPCODE_ALTIVEC2): Delete.
|
2017-04-11 00:06:43 +02:00
|
|
|
|
(PPC_OPCODE_VSX3): Delete.
|
2017-04-11 00:10:24 +02:00
|
|
|
|
(PPC_OPCODE_HTM): Delete.
|
2017-04-11 00:13:21 +02:00
|
|
|
|
(PPC_OPCODE_*): Renumber and order chronologically.
|
|
|
|
|
|
(PPC_OPCODE_SPE): Comment on this and other bits used for APUinfo.
|
2017-04-11 00:03:50 +02:00
|
|
|
|
|
2017-04-06 18:17:15 +02:00
|
|
|
|
2017-04-06 Pip Cet <pipcet@gmail.com>
|
|
|
|
|
|
|
|
|
|
|
|
* dis-asm.h: Add prototypes for wasm32 disassembler.
|
|
|
|
|
|
|
2017-04-05 20:21:33 +02:00
|
|
|
|
2017-04-05 Pedro Alves <palves@redhat.com>
|
|
|
|
|
|
|
|
|
|
|
|
* dis-asm.h (disassemble_info) <disassembler_options>: Now a
|
|
|
|
|
|
"const char *".
|
|
|
|
|
|
(next_disassembler_option): Constify.
|
|
|
|
|
|
|
Support ELF SHF_GNU_MBIND and PT_GNU_MBIND_XXX
Mark an ALLOC section, which should be placed in special memory area,
with SHF_GNU_MBIND. Its sh_info field indicates the special memory
type. GNU_MBIND section names start with ".mbind" so that they are
placed as orphan sections by linker. All input GNU_MBIND sections
with the same sh_type, sh_flags and sh_info are placed in one output
GNU_MBIND section. In executable and shared object, create a
GNU_MBIND segment for each GNU_MBIND section and its segment type is
PT_GNU_MBIND_LO plus the sh_info value. Each GNU_MBIND segment is
aligned at page boundary.
The assembler syntax:
.section .mbind.foo,"adx",%progbits
^ 0: Special memory type.
|
'd' for SHF_GNU_MBIND.
.section .mbind.foo,"adx",%progbits,0x1
^ 1: Special memory type.
|
'd' for SHF_GNU_MBIND.
.section .mbind.bar,"adG",%progbits,.foo_group,comdat,0x2
^ 2: Special memory type.
|
'd' for SHF_GNU_MBIND.
bfd/
* elf.c (get_program_header_size): Add a GNU_MBIND segment for
each GNU_MBIND section and align GNU_MBIND section to page size.
(_bfd_elf_map_sections_to_segments): Create a GNU_MBIND
segment for each GNU_MBIND section.
(_bfd_elf_init_private_section_data): Copy sh_info from input
for GNU_MBIND section.
binutils/
* NEWS: Mention support for ELF SHF_GNU_MBIND and
PT_GNU_MBIND_XXX.
* readelf.c (get_segment_type): Handle PT_GNU_MBIND_XXX.
(get_elf_section_flags): Handle SHF_GNU_MBIND.
(process_section_headers): Likewise.
* testsuite/binutils-all/mbind1.s: New file.
* testsuite/binutils-all/objcopy.exp: Run readelf test on
mbind1.s.
gas/
* NEWS: Mention support for ELF SHF_GNU_MBIND.
* config/obj-elf.c (section_match): New.
(get_section): Match both sh_info and group name.
(obj_elf_change_section): Add argument for sh_info. Pass both
sh_info and group name to get_section. Issue an error for
SHF_GNU_MBIND section without SHF_ALLOC. Set sh_info.
(obj_elf_parse_section_letters): Set SHF_GNU_MBIND for 'd'.
(obj_elf_section): Support SHF_GNU_MBIND section info.
* config/obj-elf.h (obj_elf_change_section): Add argument for
sh_info.
* config/tc-arm.c (start_unwind_section): Pass 0 as sh_info to
obj_elf_change_section.
* config/tc-ia64.c (obj_elf_vms_common): Likewise.
* config/tc-microblaze.c (microblaze_s_data): Likewise.
(microblaze_s_sdata): Likewise.
(microblaze_s_rdata): Likewise.
(microblaze_s_bss): Likewise.
* config/tc-mips.c (s_change_section): Likewise.
* config/tc-msp430.c (msp430_profiler): Likewise.
* config/tc-rx.c (parse_rx_section): Likewise.
* config/tc-tic6x.c (tic6x_start_unwind_section): Likewise.
* doc/as.texinfo: Document 'd' for SHF_GNU_MBIND.
* testsuite/gas/elf/elf.exp: Run section12a, section12b and
section13.
* testsuite/gas/elf/section10.d: Updated.
* testsuite/gas/elf/section10.s: Likewise.
* testsuite/gas/elf/section12.s: New file.
* testsuite/gas/elf/section12a.d: Likewise.
* testsuite/gas/elf/section12b.d: Likewise.
* testsuite/gas/elf/section13.l: Likewise.
* testsuite/gas/elf/section13.d: Likewise.
* testsuite/gas/elf/section13.s: Likewise.
include/
* elf/common.h (PT_GNU_MBIND_NUM): New.
(PT_GNU_MBIND_LO): Likewise.
(PT_GNU_MBIND_HI): Likewise.
(SHF_GNU_MBIND): Likewise.
ld/
* NEWS: Mention support for ELF SHF_GNU_MBIND and
PT_GNU_MBIND_XXX.
* emultempl/elf32.em (gld${EMULATION_NAME}_place_orphan): Place
input GNU_MBIND sections with the same type, attributes and
sh_info field into a single output GNU_MBIND section.
* testsuite/ld-elf/elf.exp: Run mbind2a and mbind2b.
* testsuite/ld-elf/mbind1.s: New file.
* testsuite/ld-elf/mbind1a.d: Likewise.
* testsuite/ld-elf/mbind1b.d: Likewise.
* testsuite/ld-elf/mbind1c.d: Likewise.
* testsuite/ld-elf/mbind2a.s: Likewise.
* testsuite/ld-elf/mbind2b.c: Likewise.
2017-04-04 18:05:48 +02:00
|
|
|
|
2017-04-04 H.J. Lu <hongjiu.lu@intel.com>
|
|
|
|
|
|
|
|
|
|
|
|
* elf/common.h (PT_GNU_MBIND_NUM): New.
|
|
|
|
|
|
(PT_GNU_MBIND_LO): Likewise.
|
|
|
|
|
|
(PT_GNU_MBIND_HI): Likewise.
|
|
|
|
|
|
(SHF_GNU_MBIND): Likewise.
|
|
|
|
|
|
|
2017-04-03 19:08:29 +02:00
|
|
|
|
2017-04-03 Palmer Dabbelt <palmer@dabbelt.com>
|
|
|
|
|
|
|
|
|
|
|
|
* elf/riscv.h (RISCV_GP_SYMBOL): New define.
|
|
|
|
|
|
|
2017-03-22 10:09:56 +01:00
|
|
|
|
2017-03-27 Andrew Waterman <andrew@sifive.com>
|
|
|
|
|
|
|
|
|
|
|
|
* opcode/riscv-opc.h (CSR_PMPCFG0): New define.
|
|
|
|
|
|
(CSR_PMPCFG1): Likewise.
|
|
|
|
|
|
(CSR_PMPCFG2): Likewise.
|
|
|
|
|
|
(CSR_PMPCFG3): Likewise.
|
|
|
|
|
|
(CSR_PMPADDR0): Likewise.
|
|
|
|
|
|
(CSR_PMPADDR1): Likewise.
|
|
|
|
|
|
(CSR_PMPADDR2): Likewise.
|
|
|
|
|
|
(CSR_PMPADDR3): Likewise.
|
|
|
|
|
|
(CSR_PMPADDR4): Likewise.
|
|
|
|
|
|
(CSR_PMPADDR5): Likewise.
|
|
|
|
|
|
(CSR_PMPADDR6): Likewise.
|
|
|
|
|
|
(CSR_PMPADDR7): Likewise.
|
|
|
|
|
|
(CSR_PMPADDR8): Likewise.
|
|
|
|
|
|
(CSR_PMPADDR9): Likewise.
|
|
|
|
|
|
(CSR_PMPADDR10): Likewise.
|
|
|
|
|
|
(CSR_PMPADDR11): Likewise.
|
|
|
|
|
|
(CSR_PMPADDR12): Likewise.
|
|
|
|
|
|
(CSR_PMPADDR13): Likewise.
|
|
|
|
|
|
(CSR_PMPADDR14): Likewise.
|
|
|
|
|
|
(CSR_PMPADDR15): Likewise.
|
|
|
|
|
|
(pmpcfg0): Declare register.
|
|
|
|
|
|
(pmpcfg1): Likewise.
|
|
|
|
|
|
(pmpcfg2): Likewise.
|
|
|
|
|
|
(pmpcfg3): Likewise.
|
|
|
|
|
|
(pmpaddr0): Likewise.
|
|
|
|
|
|
(pmpaddr1): Likewise.
|
|
|
|
|
|
(pmpaddr2): Likewise.
|
|
|
|
|
|
(pmpaddr3): Likewise.
|
|
|
|
|
|
(pmpaddr4): Likewise.
|
|
|
|
|
|
(pmpaddr5): Likewise.
|
|
|
|
|
|
(pmpaddr6): Likewise.
|
|
|
|
|
|
(pmpaddr7): Likewise.
|
|
|
|
|
|
(pmpaddr8): Likewise.
|
|
|
|
|
|
(pmpaddr9): Likewise.
|
|
|
|
|
|
(pmpaddr10): Likewise.
|
|
|
|
|
|
(pmpaddr11): Likewise.
|
|
|
|
|
|
(pmpaddr12): Likewise.
|
|
|
|
|
|
(pmpaddr13): Likewise.
|
|
|
|
|
|
(pmpaddr14): Likewise.
|
|
|
|
|
|
(pmpaddr15): Likewise.
|
|
|
|
|
|
|
2017-03-30 11:57:21 +02:00
|
|
|
|
2017-03-30 Pip Cet <pipcet@gmail.com>
|
|
|
|
|
|
|
|
|
|
|
|
* opcode/wasm.h: New file to support wasm32 architecture.
|
|
|
|
|
|
* elf/wasm32.h: Add R_WASM32_32 relocation.
|
|
|
|
|
|
|
2017-03-29 05:13:06 +02:00
|
|
|
|
2017-03-29 Alan Modra <amodra@gmail.com>
|
|
|
|
|
|
|
|
|
|
|
|
* opcode/ppc.h (PPC_OPCODE_RAW): Define.
|
|
|
|
|
|
(PPC_OPCODE_*): Make them all unsigned long long constants.
|
|
|
|
|
|
|
2017-03-27 12:39:50 +02:00
|
|
|
|
2017-03-27 Pip Cet <pipcet@gmail.com>
|
|
|
|
|
|
|
|
|
|
|
|
* elf/wasm32.h: New file to support wasm32 architecture.
|
|
|
|
|
|
|
Implement ARC NPS-400 Ultra Ip and Miscellaneous instructions.
opcodes * arc-nps400-tbl.h: Add Ultra Ip and Miscellaneous instructions format.
* arc-opc.c: Add defines. e.g. F_NJ, F_NM , F_NO_T, F_NPS_SR, F_NPS_M, F_NPS_CORE, F_NPS_ALL.
(insert_nps_misc_imm_offset): New function.
(extract_nps_misc imm_offset): New function.
(arc_num_flag_operands): Add F_NJ, F_NM, F_NO_T.
(arc_flag_special_cases): Add F_NJ, F_NM, F_NO_T.
include * opcode/arc.h (insn_class_t): Add ULTRAIP and MISC class.
gas * testsuite/gas/arc/nps400-12.s: New file.
* testsuite/gas/arc/nps400-12.d: New file.
2017-03-27 12:14:30 +02:00
|
|
|
|
2017-03-27 Rinat Zelig <rinat@mellanox.com>
|
|
|
|
|
|
|
|
|
|
|
|
* opcode/arc.h (insn_class_t): Add ULTRAIP and MISC class.
|
|
|
|
|
|
|
2017-03-21 14:21:02 +01:00
|
|
|
|
2017-03-21 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
|
|
|
|
|
|
|
|
|
|
|
|
* opcode/s390.h (S390_INSTR_FLAG_VX2): Remove.
|
|
|
|
|
|
(S390_INSTR_FLAG_FACILITY_MASK): Adjust value.
|
|
|
|
|
|
|
2017-03-21 12:37:33 +01:00
|
|
|
|
2017-03-21 Rinat Zelig <rinat@mellanox.com>
|
|
|
|
|
|
|
|
|
|
|
|
* opcode/arc.h (insn_class_t): Add DMA class.
|
|
|
|
|
|
|
2017-03-16 17:44:55 +01:00
|
|
|
|
2017-03-16 Nick Clifton <nickc@redhat.com>
|
|
|
|
|
|
|
|
|
|
|
|
* elf/common.h (GNU_BUILD_ATTRIBUTE_SHORT_ENUM): New GNU BUILD
|
|
|
|
|
|
note type.
|
|
|
|
|
|
|
2017-03-14 20:56:49 +01:00
|
|
|
|
2017-03-14 Jakub Jelinek <jakub@redhat.com>
|
|
|
|
|
|
|
|
|
|
|
|
PR debug/77589
|
|
|
|
|
|
* dwarf2.def (DW_OP_GNU_variable_value): New opcode.
|
|
|
|
|
|
|
2017-03-13 18:49:32 +01:00
|
|
|
|
2017-03-13 Markus Trippelsdorf <markus@trippelsdorf.de>
|
|
|
|
|
|
|
|
|
|
|
|
PR demangler/70909
|
|
|
|
|
|
PR demangler/67264
|
|
|
|
|
|
* demangle.h (struct demangle_component): Add d_printing field.
|
|
|
|
|
|
(cplus_demangle_print): Remove const qualifier from tree
|
|
|
|
|
|
parameter.
|
|
|
|
|
|
(cplus_demangle_print_callback): Likewise.
|
|
|
|
|
|
|
2017-03-13 10:58:04 +01:00
|
|
|
|
2017-03-13 Nick Clifton <nickc@redhat.com>
|
|
|
|
|
|
|
|
|
|
|
|
PR binutils/21202
|
|
|
|
|
|
* elf/aarch64.h (R_AARCH64_TLSDESC_LD64_LO12_NC): Rename to
|
|
|
|
|
|
R_AARCH64_TLSDESC_LD64_LO12.
|
|
|
|
|
|
(R_AARCH64_TLSDESC_ADD_LO12_NC): Rename to
|
|
|
|
|
|
R_AARCH64_TLSDESC_ADD_LO12_NC.
|
|
|
|
|
|
|
2017-03-10 11:50:34 +01:00
|
|
|
|
2017-03-10 Nick Clifton <nickc@redhat.com>
|
|
|
|
|
|
|
|
|
|
|
|
* elf/common.h (EM_LANAI): New machine number.
|
|
|
|
|
|
(EM_BPF): Likewise.
|
|
|
|
|
|
(EM_WEBASSEMBLY): Likewise.
|
|
|
|
|
|
Move low value, deprecated, numbers to their numerical
|
|
|
|
|
|
equivalents.
|
|
|
|
|
|
|
2017-03-08 16:44:04 +01:00
|
|
|
|
2017-03-08 H.J. Lu <hongjiu.lu@intel.com>
|
|
|
|
|
|
|
|
|
|
|
|
PR binutils/21231
|
|
|
|
|
|
* elf/common.h (GNU_PROPERTY_LOPROC): New.
|
|
|
|
|
|
(GNU_PROPERTY_HIPROC): Likewise.
|
|
|
|
|
|
(GNU_PROPERTY_LOUSER): Likewise.
|
|
|
|
|
|
(GNU_PROPERTY_HIUSER): Likewise.
|
|
|
|
|
|
|
2017-03-01 12:09:46 +01:00
|
|
|
|
2017-03-01 Nick Clifton <nickc@redhat.com>
|
|
|
|
|
|
|
|
|
|
|
|
* elf/common.h (SHF_GNU_BUILD_NOTE): Define.
|
|
|
|
|
|
(NT_GNU_PROPERTY_TYPE_0): Define.
|
|
|
|
|
|
(NT_GNU_BUILD_ATTRIBUTE_OPEN): Define.
|
|
|
|
|
|
(NT_GNU_BUILD_ATTRIBUTE_FUN): Define.
|
|
|
|
|
|
(GNU_BUILD_ATTRIBUTE_TYPE_NUMERIC): Define.
|
|
|
|
|
|
(GNU_BUILD_ATTRIBUTE_TYPE_STRING): Define.
|
|
|
|
|
|
(GNU_BUILD_ATTRIBUTE_TYPE_BOOL_TRUE): Define.
|
|
|
|
|
|
(GNU_BUILD_ATTRIBUTE_TYPE_BOOL_FALSE): Define.
|
|
|
|
|
|
(GNU_BUILD_ATTRIBUTE_VERSION): Define.
|
|
|
|
|
|
(GNU_BUILD_ATTRIBUTE_STACK_PROT): Define.
|
|
|
|
|
|
(GNU_BUILD_ATTRIBUTE_RELRO): Define.
|
|
|
|
|
|
(GNU_BUILD_ATTRIBUTE_STACK_SIZE): Define.
|
|
|
|
|
|
(GNU_BUILD_ATTRIBUTE_TOOL): Define.
|
|
|
|
|
|
(GNU_BUILD_ATTRIBUTE_ABI): Define.
|
|
|
|
|
|
(GNU_BUILD_ATTRIBUTE_PIC): Define.
|
|
|
|
|
|
(NOTE_GNU_PROPERTY_SECTION_NAME): Define.
|
|
|
|
|
|
(GNU_BUILD_ATTRS_SECTION_NAME): Define.
|
|
|
|
|
|
(GNU_PROPERTY_STACK_SIZE): Define.
|
|
|
|
|
|
(GNU_PROPERTY_NO_COPY_ON_PROTECTED): Define.
|
|
|
|
|
|
(GNU_PROPERTY_X86_ISA_1_USED): Define.
|
|
|
|
|
|
(GNU_PROPERTY_X86_ISA_1_NEEDED): Define.
|
|
|
|
|
|
(GNU_PROPERTY_X86_ISA_1_486): Define.
|
|
|
|
|
|
(GNU_PROPERTY_X86_ISA_1_586): Define.
|
|
|
|
|
|
(GNU_PROPERTY_X86_ISA_1_686): Define.
|
|
|
|
|
|
(GNU_PROPERTY_X86_ISA_1_SSE): Define.
|
|
|
|
|
|
(GNU_PROPERTY_X86_ISA_1_SSE2): Define.
|
|
|
|
|
|
(GNU_PROPERTY_X86_ISA_1_SSE3): Define.
|
|
|
|
|
|
(GNU_PROPERTY_X86_ISA_1_SSSE3): Define.
|
|
|
|
|
|
(GNU_PROPERTY_X86_ISA_1_SSE4_1): Define.
|
|
|
|
|
|
(GNU_PROPERTY_X86_ISA_1_SSE4_2): Define.
|
|
|
|
|
|
(GNU_PROPERTY_X86_ISA_1_AVX): Define.
|
|
|
|
|
|
(GNU_PROPERTY_X86_ISA_1_AVX2): Define.
|
|
|
|
|
|
(GNU_PROPERTY_X86_ISA_1_AVX512F): Define.
|
|
|
|
|
|
(GNU_PROPERTY_X86_ISA_1_AVX512CD): Define.
|
|
|
|
|
|
(GNU_PROPERTY_X86_ISA_1_AVX512ER): Define.
|
|
|
|
|
|
(GNU_PROPERTY_X86_ISA_1_AVX512PF): Define.
|
|
|
|
|
|
(GNU_PROPERTY_X86_ISA_1_AVX512VL): Define.
|
|
|
|
|
|
(GNU_PROPERTY_X86_ISA_1_AVX512DQ): Define.
|
|
|
|
|
|
(GNU_PROPERTY_X86_ISA_1_AVX512BW): Define.
|
|
|
|
|
|
|
2017-02-28 19:32:07 +01:00
|
|
|
|
2017-02-28 Peter Bergner <bergner@vnet.ibm.com>
|
|
|
|
|
|
|
|
|
|
|
|
* dis-asm.h (disasm_options_t): New typedef.
|
|
|
|
|
|
(parse_arm_disassembler_option): Remove prototype.
|
|
|
|
|
|
(set_arm_regname_option): Likewise.
|
|
|
|
|
|
(get_arm_regnames): Likewise.
|
|
|
|
|
|
(get_arm_regname_num_options): Likewise.
|
|
|
|
|
|
(disassemble_init_s390): New prototype.
|
|
|
|
|
|
(disassembler_options_powerpc): Likewise.
|
|
|
|
|
|
(disassembler_options_arm): Likewise.
|
|
|
|
|
|
(disassembler_options_s390): Likewise.
|
|
|
|
|
|
(remove_whitespace_and_extra_commas): Likewise.
|
|
|
|
|
|
(disassembler_options_cmp): Likewise.
|
|
|
|
|
|
(next_disassembler_option): New inline function.
|
|
|
|
|
|
(FOR_EACH_DISASSEMBLER_OPTION): New macro.
|
|
|
|
|
|
|
2017-02-27 23:02:36 +01:00
|
|
|
|
2017-02-28 Alan Modra <amodra@gmail.com>
|
|
|
|
|
|
|
|
|
|
|
|
* elf/ppc64.h (R_PPC64_16DX_HA): New. Expand fake reloc comment.
|
|
|
|
|
|
* elf/ppc.h (R_PPC_16DX_HA): Likewise.
|
|
|
|
|
|
|
[AArch64] Additional SVE instructions
This patch supports some additions to the SVE architecture prior to
its public release.
include/
* opcode/aarch64.h (AARCH64_OPND_SVE_ADDR_RI_S4x16)
(AARCH64_OPND_SVE_IMM_ROT1, AARCH64_OPND_SVE_IMM_ROT2)
(AARCH64_OPND_SVE_Zm3_INDEX, AARCH64_OPND_SVE_Zm3_22_INDEX)
(AARCH64_OPND_SVE_Zm4_INDEX): New aarch64_opnds.
opcodes/
* aarch64-tbl.h (OP_SVE_HMH, OP_SVE_VMU_HSD, OP_SVE_VMVU_HSD)
(OP_SVE_VMVV_HSD, OP_SVE_VMVVU_HSD, OP_SVE_VM_HSD, OP_SVE_VUVV_HSD)
(OP_SVE_VUV_HSD, OP_SVE_VU_HSD, OP_SVE_VVVU_H, OP_SVE_VVVU_S)
(OP_SVE_VVVU_HSD, OP_SVE_VVV_D, OP_SVE_VVV_D_H, OP_SVE_VVV_H)
(OP_SVE_VVV_HSD, OP_SVE_VVV_S, OP_SVE_VVV_S_B, OP_SVE_VVV_SD_BH)
(OP_SVE_VV_BHSDQ, OP_SVE_VV_HSD, OP_SVE_VZVV_HSD, OP_SVE_VZV_HSD)
(OP_SVE_V_HSD): New macros.
(OP_SVE_VMU_SD, OP_SVE_VMVU_SD, OP_SVE_VM_SD, OP_SVE_VUVV_SD)
(OP_SVE_VU_SD, OP_SVE_VVVU_SD, OP_SVE_VVV_SD, OP_SVE_VZVV_SD)
(OP_SVE_VZV_SD, OP_SVE_V_SD): Delete.
(aarch64_opcode_table): Add new SVE instructions.
(aarch64_opcode_table): Use imm_rotate{1,2} instead of imm_rotate
for rotation operands. Add new SVE operands.
* aarch64-asm.h (ins_sve_addr_ri_s4): New inserter.
(ins_sve_quad_index): Likewise.
(ins_imm_rotate): Split into...
(ins_imm_rotate1, ins_imm_rotate2): ...these two inserters.
* aarch64-asm.c (aarch64_ins_imm_rotate): Split into...
(aarch64_ins_imm_rotate1, aarch64_ins_imm_rotate2): ...these two
functions.
(aarch64_ins_sve_addr_ri_s4): New function.
(aarch64_ins_sve_quad_index): Likewise.
(do_misc_encoding): Handle "MOV Zn.Q, Qm".
* aarch64-asm-2.c: Regenerate.
* aarch64-dis.h (ext_sve_addr_ri_s4): New extractor.
(ext_sve_quad_index): Likewise.
(ext_imm_rotate): Split into...
(ext_imm_rotate1, ext_imm_rotate2): ...these two extractors.
* aarch64-dis.c (aarch64_ext_imm_rotate): Split into...
(aarch64_ext_imm_rotate1, aarch64_ext_imm_rotate2): ...these two
functions.
(aarch64_ext_sve_addr_ri_s4): New function.
(aarch64_ext_sve_quad_index): Likewise.
(aarch64_ext_sve_index): Allow quad indices.
(do_misc_decoding): Likewise.
* aarch64-dis-2.c: Regenerate.
* aarch64-opc.h (FLD_SVE_i3h, FLD_SVE_rot1, FLD_SVE_rot2): New
aarch64_field_kinds.
(OPD_F_OD_MASK): Widen by one bit.
(OPD_F_NO_ZR): Bump accordingly.
(get_operand_field_width): New function.
* aarch64-opc.c (fields): Add new SVE fields.
(operand_general_constraint_met_p): Handle new SVE operands.
(aarch64_print_operand): Likewise.
* aarch64-opc-2.c: Regenerate.
gas/
* doc/c-aarch64.texi: Document that sve implies fp16, simd and compnum.
* config/tc-aarch64.c (parse_vector_type_for_operand): Allow .q
to be used with SVE registers.
(parse_operands): Handle new SVE operands.
(aarch64_features): Make "sve" require F16 rather than FP. Also
require COMPNUM.
* testsuite/gas/aarch64/sve.s: Add tests for new instructions.
Include compnum tests.
* testsuite/gas/aarch64/sve.d: Update accordingly.
* testsuite/gas/aarch64/sve-invalid.s: Add tests for new instructions.
* testsuite/gas/aarch64/sve-invalid.l: Update accordingly. Also
update expected output for new FMOV and MOV alternatives.
2017-02-24 19:29:00 +01:00
|
|
|
|
2017-02-24 Richard Sandiford <richard.sandiford@arm.com>
|
|
|
|
|
|
|
|
|
|
|
|
* opcode/aarch64.h (AARCH64_OPND_SVE_ADDR_RI_S4x16)
|
|
|
|
|
|
(AARCH64_OPND_SVE_IMM_ROT1, AARCH64_OPND_SVE_IMM_ROT2)
|
|
|
|
|
|
(AARCH64_OPND_SVE_Zm3_INDEX, AARCH64_OPND_SVE_Zm3_22_INDEX)
|
|
|
|
|
|
(AARCH64_OPND_SVE_Zm4_INDEX): New aarch64_opnds.
|
|
|
|
|
|
|
2017-02-24 19:27:26 +01:00
|
|
|
|
2017-02-24 Richard Sandiford <richard.sandiford@arm.com>
|
|
|
|
|
|
|
|
|
|
|
|
* opcode/aarch64.h (AARCH64_FEATURE_COMPNUM): New macro.
|
|
|
|
|
|
(AARCH64_ARCH_V8_3): Include AARCH64_FEATURE_COMPNUM.
|
|
|
|
|
|
|
2017-02-23 06:23:05 +01:00
|
|
|
|
2017-02-22 Andrew Waterman <andrew@sifive.com>
|
|
|
|
|
|
|
|
|
|
|
|
* opcode/riscv-opc.h (CSR_SCOUNTEREN): New define.
|
|
|
|
|
|
(CSR_MCOUNTEREN): Likewise.
|
|
|
|
|
|
(scounteren): Declare register.
|
|
|
|
|
|
(mcounteren): Likewise.
|
|
|
|
|
|
|
2017-02-15 00:37:04 +01:00
|
|
|
|
2017-02-14 Andrew Waterman <andrew@sifive.com>
|
|
|
|
|
|
|
|
|
|
|
|
* opcode/riscv-opc.h (MATCH_SFENCE_VMA): New define.
|
|
|
|
|
|
(MASK_SFENCE_VMA): Likewise.
|
|
|
|
|
|
(sfence_vma): Declare instruction.
|
|
|
|
|
|
|
2017-02-14 11:08:21 +01:00
|
|
|
|
2017-02-14 Alan Modra <amodra@gmail.com>
|
|
|
|
|
|
|
|
|
|
|
|
PR 21118
|
|
|
|
|
|
* opcode/ppc.h (PPC_OPERAND_*): Reassign values, regs first.
|
|
|
|
|
|
(PPC_OPERAND_SPR, PPC_OPERAND_GQR): Define.
|
|
|
|
|
|
|
2017-01-25 13:19:27 +01:00
|
|
|
|
2017-01-24 Dimitar Dimitrov <dimitar@dinux.eu>
|
|
|
|
|
|
|
|
|
|
|
|
* opcode/hppa.h: Clarify that file is part of GNU opcodes.
|
|
|
|
|
|
* opcode/i860.h: Ditto.
|
|
|
|
|
|
* opcode/nios2.h: Ditto.
|
|
|
|
|
|
* opcode/nios2r1.h: Ditto.
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* opcode/nios2r2.h: Ditto.
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* opcode/pru.h: Ditto.
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2017-01-25 13:24:02 +01:00
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2017-01-24 Alan Hayward <alan.hayward@arm.com>
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2017-01-24 11:37:13 +01:00
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* elf/common.h (NT_ARM_SVE): Define.
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2017-01-04 15:27:52 +01:00
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2017-01-04 Jiong Wang <jiong.wang@arm.com>
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* dwarf2.def: Sync with mainline gcc sources.
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2017-01-04 Richard Earnshaw <rearnsha@arm.com>
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Jiong Wang <jiong.wang@arm.com>
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* dwarf2.def (DW_OP_AARCH64_operation): Reserve the number 0xea.
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(DW_CFA_GNU_window_save): Comments the multiplexing on AArch64.
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2017-01-04 13:27:10 +01:00
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2017-01-04 Szabolcs Nagy <szabolcs.nagy@arm.com>
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* opcode/aarch64.h (AARCH64_FEATURE_RCPC): Define.
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(AARCH64_ARCH_V8_3): Update.
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2017-01-03 18:42:01 +01:00
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2017-01-03 Kito Cheng <kito.cheng@gmail.com>
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* opcode/riscv-opc.h: Add support for the "q" ISA extension.
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2017-01-03 16:17:48 +01:00
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2017-01-03 Nick Clifton <nickc@redhat.com>
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* dwarf2.def: Sync with mainline gcc sources
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* dwarf2.h: Likewise.
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2016-12-21 Jakub Jelinek <jakub@redhat.com>
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* dwarf2.def (DW_FORM_ref_sup): Renamed to ...
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(DW_FORM_ref_sup4): ... this. New form.
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(DW_FORM_ref_sup8): New form.
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2016-10-17 Jakub Jelinek <jakub@redhat.com>
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* dwarf2.h (enum dwarf_calling_convention): Add new DWARF5
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calling convention codes.
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(enum dwarf_line_number_content_type): New.
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(enum dwarf_location_list_entry_type): Add DWARF5 DW_LLE_*
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codes.
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(enum dwarf_source_language): Add new DWARF5 DW_LANG_* codes.
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(enum dwarf_macro_record_type): Add DWARF5 DW_MACRO_* codes.
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(enum dwarf_name_index_attribute): New.
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(enum dwarf_range_list_entry): New.
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(enum dwarf_unit_type): New.
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* dwarf2.def: Add new DWARF5 DW_TAG_*, DW_FORM_*, DW_AT_*,
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DW_OP_* and DW_ATE_* entries.
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2016-08-15 Jakub Jelinek <jakub@redhat.com>
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* dwarf2.def (DW_AT_string_length_bit_size,
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DW_AT_string_length_byte_size): New attributes.
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2016-08-12 Alexandre Oliva <aoliva@redhat.com>
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PR debug/63240
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* dwarf2.def (DW_AT_deleted, DW_AT_defaulted): New.
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* dwarf2.h (enum dwarf_defaulted_attribute): New.
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2017-01-02 04:36:43 +01:00
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|
2017-01-02 Alan Modra <amodra@gmail.com>
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Update year range in copyright notice of all files.
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2017-01-02 04:25:05 +01:00
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For older changes see ChangeLog-2016
|
2016-01-01 11:44:31 +01:00
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2017-01-02 04:25:05 +01:00
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Copyright (C) 2017 Free Software Foundation, Inc.
|
2016-01-01 11:44:31 +01:00
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Copying and distribution of this file, with or without modification,
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are permitted in any medium without royalty provided the copyright
|
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|
notice and this notice are preserved.
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Local Variables:
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mode: change-log
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left-margin: 8
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fill-column: 74
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version-control: never
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End:
|
