(insns): Re-arrange instructions by archtitecture. Pld instruction
is part of ARMv5E.
(tinsns): blx and bkpt are part of ARMv5T.
(do_fp_{ctrl,ldst,ldstm,dyadic,monadic,cmp,from_reg,to_reg}): Rename
to do_fpa_*. All callers changed.
* tc-arm.c (insns): Add two temporary instructions to handle
ldrd/strd.
2001-10-31 Chris Demetriou <cgd@demetriou.com>
* elf32-mips.c (_bfd_mips_elf_hi16_reloc): Handle PC-relative
relocations properly.
[ gas/ChangeLog ]
2001-10-31 Chris Demetriou <cgd@broadcom.com>
* config/tc-mips.c (HAVE_32BIT_ADDRESSES): If compiling embedded
PIC code, assume pointers the same size as GPRs.
(macro): In M_LA_AB handling for embedded PIC code, support
"la $treg,foo-bar($breg)". In load/store handling
(label ld_st) support "<op> $treg,<sym>-<local_sym>($breg)"
which is used by the compiler for switch statements.
In load/store double multi-instruction macro handling
(label ldd_std) add a comment that no special handling
is currently done for embedded PIC.
(mips_ip): In 'o' (16-bit offset) case, only accept 16
bit offsets.
[ gas/testsuite/ChangeLog ]
2001-10-31 Chris Demetriou <cgd@broadcom.com>
* gas/mips/empic.s: Undo damage inflicted on 2000-12-02.
* gas/mips/empic.d: Likewise.
* gas/mips/elempic.d: Likewise (it was copied into other files).
* gas/mips/telempic.d: Likewise.
* gas/mips/tempic.d: Likewise.
* gas/mips/empic2.s: New test to check new 'la' and 'lw' (and
related ops) syntax, test loads with large offsets.
* gas/mips/emcic2.d: Likewise.
* gas/mips/mips.exp: Run the new test on ELF platforms.
* tc-arm.c (ARM_EXT_LONGMUL, ARM_EXT_HALFWORD, ARM_EXT_THUMB): Delete.
(ARM_2UP, ARM_ALL, ARM_3UP, ARM_6UP): Delete.
(FPU_CORE, FPU_FPA10, FPA_FPA11, FPU_ALL, FPA_MEMMULTI): Delete.
(ARM_EXT_V{1,2,2S,3,3M,4,4T,5T,5ExP}): New defines.
(ARM_EXT_V{5,5E}): Synchronize with above.
(ARM_ARCH_V*): Define a complete set in terms of above features.
(ARM_{1,2,3,250,6,7,8,9,STRONG}): Define in terms of architecture.
(FPU_FPA_EXT_V[12]): Define.
(FPU_ARCH_FPE, FPU_ARCH_FPA): Define in terms of above.
(FPU_ANY): Define.
(FPU_DEFAULT): Default to FPA.
(CPU_DEFAULT): For XScale, this is now just ARM_ARCH_XSCALE; for
Thumb, this is now ARM_ARCH_V5T.
(insns): Rework for new feature defines.
(tinsns): Likewise.
(opcode_select, do_ldst, md_begin, md_parse_option): Likewise.
(ppc_size): Select PPC_OPCODE_64 if 64 bit.
(md_begin): Don't set ppc_size here.
(ppc_target_format): Test ppc_size as well as BFD_DEFAULT_TARGET_SIZE.
(md_shortopts): Constify.
(md_longopts): Likewise.
(md_longopts_size): Likewise.
(ppc_elf_suffix): Only allow 64-bit relocs when ppc_size specifies
64-bit opcodes.
(ppc_machine): Explain why this function is a nop.
* config/tc-ppc.c (md_parse_option): New -m7410, -m7450 and -m7455
flags, equivalent to -m7400. New -maltivec to enable AltiVec
instructions. New -mbook64 and -mbooke/-mbooke32 flags to enable
64-bit and 32-bit BookE support, respectively. Change -m403 and
-m405 to set PPC403 option.
(md_show_usage): Adjust for new options.
* doc/all.texi: Set PPC.
* doc/as.texinfo: Add PPC support and pull in c-ppc.texi.
* doc/c-ppc.texi: New file.
* doc/Makefile.am (CPU_DOCS): Add c-ppc.texi.
* doc/Makefile.in: Regenerate.
[gas/testsuite/ChangeLog]
* gas/ppc/booke.s: New test for Motorola BookE.
* gas/ppc/booke.d: New file.
* gas/ppc/ppc.exp: Test booke.s.
[include/opcode/ChangeLog]
* ppc.h (PPC_OPCODE_BOOKE, PPC_OPCODE_403): New opcode flags for
BookE and PowerPC403 instructions.
[opcodes/ChangeLog]
* ppc-opc.c (insert_de, extract_de, insert_des, extract_des): New
instruction field instruction/extraction functions for new BookE
DE form instructions.
(CT): New macro for CT field in an X form instruction.
(DE, DES, DEO, DE_MASK): New macros for DE/DES fields in DE form
instructions.
(PPC64): Don't include PPC_OPCODE_PPC.
(403): New opcode macro for PPC403 processors.
(BOOKE): New opcode macro for BookE processors.
(bce, bcel, bcea, bcela, bclre, bclrel: New BookE instructions.
(bcctre, bcctrel, be, bel, bea, bela, icbt, icbte, lwzxe): Likewise.
(dcbste, lwzuxe, luxe, dcbfe, lbzxe, lwarxe, lbzuxe): Likewise.
(stwcxe, stwxe, stxe, stwuxe, stuxe, stbxe, dcbtste, stbuxe): Likewise.
(mfapidi, dcbte, lhzxe, lhzuxe, lhaxe, lhauxe, subfe64): Likewise.
(subfeo64, adde64, addeo64, sthxe, sthuxe, subfze64): Likewise.
(subfzeo64, addze64, addzeo64, dcbie, subfme64, subfmeo64): Likewise.
(addme64, addmeo64, stdcxe., mcrxr64, lwbrxe, lfsxe, lfsuxe): Likewise.
(lfdxe, lfduxe, stwbrxe, stfsxe, stfsuxe, stfdxe, dcbae): Likewise.
(stfduxe, tlbivax, tlbivaxe, lhbrxe, ldxe, lduxe, tlbsx): Likewise.
(tlbsxe, sthbrxe, stdxe, stduxe, icbie, stfiwxe, dcbze, lbze): Likewise.
(lbzue, ldue, lhze, lhzue, lhae, lhaue, lwze, lwzue): Likewise.
(stbe, stbue, sthe, sthue, stwe, stwue, lfse, lfsue, lfde): Likewise.
(lfdue, stde, stdue, stfse, stfsue, stfde, stfdue): Likewise.
* ppc-dis.c (print_insn_big_powerpc, print_insn_little_powerpc): Look
for a disassembler option of `booke', `booke32' or `booke64' to enable
BookE support in the disassembler.
(mips_cpreturn_register): Likewise.
(mips_gp_register): Likewise.
(s_cpsetup): New function prototype.
(s_cplocal): Likewise.
(s_cpreturn): Likewise.
(s_gpvalue): Likewise.
(mips_pseudo_table): Add .cpsetup, .cplocal, .cpreturn, .gpvalue
pseudo-ops.
(macro): Don't warn about .cprestore for NewABI.
(md_pcrel_from): Code cleanup.
(mips_force_relocation): Force output of some NewABI relocations even
without a defined symbol.
(s_cpload): Ignore .cpload for NewABI.
(s_cpsetup): Handle .cpsetup.
(s_cplocal): Handle .cplocal.
(s_cprestore): Ignore .cprestore for NewABI.
(s_cpreturn): Handle .cpreturn.
(s_gpvalue): Handle .gpvalue.
(s_cpadd): Ignore .cpadd for NewABI.
(nopic_need_relax): Take g_switch_value into account as gp
optimization.
(tc_gen_reloc): Don't handle BFD_RELOC_MIPS_{CALL,GOT}* for NewABI.
(small_ex_type): Named this enum, more return values for
my_getSmallExpression.
(mips_ip): Allow SPC and HT between arguments. Handle some NewABI
triple relocations. Protect some parts with ifdef OBJ_ELF.
(percent_op_match): New struct, lookup table for %some_reloc().
(my_getSmallParser): New function, parses nested percent_ops also.
(my_getSmallExpression): Rewite to support nested percent_ops.
(load_address): Support both 32- and 64-bit addresses.
(macro): Call load_register correctly. Expand 64-bit loads ans stores.
(macro2): Call load_address correctly.
throughout file.
(obj_elf_change_section): Rename "group" to "group_name".
(obj_elf_section): Likewise.
(elf_frob_file): Don't use sec->lineno for SHT_GROUP section to store
first member section; Instead use elf_next_in_group.
Set elf_section_data group from it. Warn if group name changed.
(obj_elf_parse_section_letters): Parse 'G' too.
(obj_elf_section): Parse group name.
(struct group_list): New.
(build_group_lists): New function.
(elf_frob_file): Create SEC_GROUP section(s).
* config/obj-elf.c: (elf_copy_symbol_attributes): Zap trailing
whitespace.
capitalise, no final period or newline, don't say "ignoring" for
as_bad messages. In some cases, change the wording to that used
elsewhere for similar messages.
(obj_elf_section_name): New function, split out from ..
(obj_elf_section): .. here. Correctly mask off SHF_MERGE if
entsize not specified.
relocation triple.
(prev_insn_fixp): Likewise.
(append_insn): Changed prototype to accept a relocation pointer.
(imm_reloc): Make it an array.
(offset_reloc): Likewise.
(md_assemble): Handle triple relocations.
(append_insn): Likewise. Add handling for some NewABI relocations.
(mips_no_prev_insn): Handle triple relocations.
(macro_build): Likewise. Add handling for some NewABI relocations.
Move handling for the 'u' case to append_insn().
(mips16_macro_build): Handle triple relocations.
(macro_build_lui): Likewise. Don't handle _gp_disp as special symbol
for NewABI.
(mips_ip): Handle triple relocations.
(mips16_ip): Likewise.
(mips_force_relocation): Force handling of triple relocations
without symbols for NewABI.
(md_apply_fix): Add handling for some NewABI relocations.
(mips_target_format): Move downwards in file, use HAVE_64BIT_OBJECTS
in it.
(mips_abi_level, mips_abi): New enum.
(mips_32bit_abi): Remove.
(HAVE*PRS): Use mips_abi instead of mips_32bit_abi.
(HAVE_NEWABI): New define.
(HAVE_64BIT_OBJECTS): New define.
(HAVE_32BIT_ADDRESSES): Don't return true for 64bit objects.
(HAVE_64BIT_ADDRESSES): New define, inverse of HAVE_32BIT_ADDRESSES.
(support_64bit_objects): New prototype.
(md_begin): Use mips_abi instead of mips_32bit_abi. Don't write
.reginfo section for n32, use .MIPS.options instead.
(support_64bit_objects): New function, code from md_parse_option.
(md_longopts): Add -n32 option.
(md_parse_option): Use mips_abi instead of mips_32bit_abi/mips64.
Add -n32 option. Protect with OBJ_ELF.
(s_mipsset): Use mips_abi instead of mips_32bit_abi.
(mips_elf_final_processing): Likewise. Don't write .reginfo section
for n32, use .MIPS.options instead.
* write.c (set_symtab): Update bfd_alloc declaration. Use a temp
var to ensure bfd_alloc arg is the right type.
(write_object_file): Cast args of bfd_seek. Replace bfd_write with
bfd_bwrite.
* config/obj-coff.c: Replace calls to bfd_write with calls to
bfd_bwrite. Cast args of bfd_seek.
* config/obj-elf.c (obj_elf_change_section): Avoid signed/unsigned
warning.
* config/tc-mn10300.c (set_arch_mach): Make param unsigned.
* config/tc-tic54x.c (tic54x_mlib): Replace bfd_read call with
call to bfd_bread.
and rearrange for efficiency. For "PIC code" subtraction, use
"rightseg" rather than recalculating. For "symbol OP symbol"
subtract, set "retval" to absolute_section if symbols in same
section.
* symbols.c (resolve_symbol_value): Resolve "sym +/- expr" to an
O_symbol. Simplify a +/- b code. Allow equality and non-equality
comparisons on symbols from any section. Allow other comparison
operators as for subtraction.
(symbol_equated_reloc_p): New predicate function.
* symbols.h (symbol_equated_reloc_p): Declare.
* write.c (adjust_reloc_syms): Use symbol_equated_reloc_p.
(write_relocs): Likewise.
(write_object_file): Likewise.
(relax_segment <rs_machine_dependent>): Ensure segment for
expression syms is set correctly.
* config/tc-mips.c (md_estimate_size_before_relax): Likewise.
* config/tc-i386.c (md_assemble <Output jumps>): Don't lose part
of a complex expression when setting up frag_var.
(MACRO_LITERAL, MACRO_BASE, MACRO_BYTOFF, MACRO_JSR): Remove.
(alpha_macros): Remove occurrences of same.
(O_lituse_addr, O_gprel): New.
(DUMMY_RELOC_LITUSE_*): New.
(s_alpha_ucons, s_alpha_arch): Prototype.
(alpha_reloc_op): Construct elements via DEF macro.
(ALPHA_RELOC_SEQUENCE_OK): Remove.
(struct alpha_reloc_tag): Rename from alpha_literal_tag; rename
members to not be literal specific.
(next_sequence_num): New.
(md_apply_fix3): Cope with missing GPDISP_LO16. Adjust for
added/removed BFD relocations.
(alpha_force_relocation, alpha_fix_adjustable): Likewise.
(alpha_adjust_symtab_relocs): Handle GPDISP relocs as well.
(tokenize_arguments): Parse ! relocations properly.
(find_macro_match): Delete unused macro argument types.
(assemble_insn): Add reloc parameter; emit that instead of the
default as appropriate.
(get_alpha_reloc_tag): New. Split from ...
(emit_insn): ... here. Allocate a reloc tag for GPDISP.
(assemble_tokens): Don't search macros if user relocation present.
Copy reloc sequence number to insn struct.
(emit_ldgp): Remove user reloc handling.
(load_expression, emit_lda, emit_ldah, emit_ir_load): Likewise.
(emit_loadstore, emit_ldXu, emit_ldil, emit_stX): Likewise.
(emit_sextX, emit_division, emit_jsrjmp, emit_retjcr): Likewise.
* config/tc-alpha.h (tc_adjust_symtab): Always define.
(struct alpha_fix_tag): Name members less literal specific.
* gas/alpha/alpha.exp: New file.
* gas/alpha/elf-reloc-1.[sd]: New test.
* gas/alpha/elf-reloc-2.[sl]: New test.
* gas/alpha/elf-reloc-3.[sl]: New test.
* gas/alpha/elf-reloc-4.[sd]: New test.
* gas/alpha/fp.exp: Remove file.
* gas/alpha/fp.s: Output to .data not .rdata.
* gas/alpha/fp.d: Adjust to match.
offset match H8 ELF spec.
(md_section_align): Alternate implementation for BFD_ASSEMBLER.
(md_apply_fix): Fix argument and return types for BFD_ASSEMBLER.
(build_bytes): Mark fixups for PCrel branches as signed. For
OBJ_ELF, make sure the reloc's offset points to the first byte
to be modified.
(md_convert_frag): Update definiton based on BFD_ASSEMBLER.
* tc-h8300.h (relocation mappings): Add.
* tc-h8300.c (tc_crawl_symbol_chain, tc_headers_hook): Don't
define for BFD_ASSEMBLER.
(tc_reloc_mangle): Likewise.
(tc_gen_reloc): New function for BFD_ASSEMBLER.
More of Joern's patches with minor changes s/OBJ_ELF/BFD_ASSEMBLER/
assorted coff relocations to the corresponding elf relocations.
* tc-h8300.h (TARGET_ARCH, TARGET_FORMAT): Define appropriately.
More of Joern's patches.
* configure: Regenerate.
* config/tc-ppc.c (PPC_LO, PPC_HI, PPC_HA, PPC_HIGHER,
PPC_HIGHERA, PPC_HIGHEST, PPC_HIGHESTA, SEX16): New macros.
(md_assemble): Use them.
(ppc_machine): Support stub for ELF64 as well as XCOFF.
(md_pseudo_table): Add "llong", "quad".
(md_parse_option): Match default_cpu of powerpc*.
(ppc_arch): Likewise.
(ppc_subseg_align): Only for OBJ_XCOFF.
(ppc_target_format): Return elf64-powerpc strings for 64 bit ELF.
(md_begin): Select PPC_OPCODE_64 for 64 bit.
(ppc_insert_operand): Don't bother testing 'file' before calling
as_bad_where. Use as_bad_where for operand->insert errors.
(mapping): Add ELF64 relocation modifiers.
(ppc_elf_suffix): Replace symbol on BFD_RELOC_PPC64_TOC reloc
expressions with abs_symbol.
(ppc_elf_cons): Correct offset for little endian targets.
(ppc_elf_frob_symbol): New.
(md_assemble): Add support for 64 bit ELF relocs.
(ppc_tc): Ensure 8 byte alignment when 64 bit.
(ppc_is_toc_sym): Only define for OBJ_XCOFF and OBJ_ELF. Match
".toc" section for 64 bit ELF.
(ppc_fix_adjustable): New. Macro body moved from tc-ppc.h.
(md_apply_fix3): Silence warning with ATTRIBUTE_UNUSED. Only do
the ppc_is_toc_sym check for OBJ_XCOFF and OBJ_ELF. For 64 bit,
use BFD_RELOC_PPC64_TOC16_DS instead of BFD_RELOC_PPC_TOC16.
Expand on comments, error message. Add support for 64 bit relocs,
and use PPC_HI etc. macros.
* config/tc-ppc.h (MAX_MEM_FOR_RS_ALIGN_CODE): Define.
(HANDLE_ALIGN): Define to generate nops in code sections rather
than zeros.
(TC_FORCE_RELOCATION): Force for BFD_RELOC_PPC64_TOC.
(ELF_TC_SPECIAL_SECTIONS): Add 64 bit ELF sections.
(tc_fix_adjustable): Move body of macro to tc-ppc.c.
(ppc_fix_adjustable): Declare.
(tc_frob_symbol): Define.
(ppc_elf_frob_symbol): Declare.
value, not the word beyond maximum.
* tc_mips.c (macro_build_lui): Code cleanup.
(macro): Reflect change to MAX_GPREL_OFFSET.
(mips_ip): Check explicitly against S_EX_NONE.
(my_get_SmallExpression): parse for %gp_rel, not %gprel.
(md_apply_fix): Code cleanup.
return values.
(mips_ip): Use the new return values instead of characters. Add
support for %higher and %highest.
(LP): Remove.
(RP): Remove.
(my_getSmallExpression): Make parsing case insensitive and more
reliable. Add support for %higher and %highest. Further support to
parse %gprel and %neg is implemented but currently deactivated.
-mipsX is specified. Make both -mcpu/-march and -mcpu/-mtune pairs
mutually exclusive (if they are different).
(md_parse_option): Warn if an -march/-mtune/-mcpu/-m<cpu> option is
set more than once.
* config/tc-mips.c (mips_fp32, mips_32bit_abi): New static variables.
(md_long_opts): Add -mfp32 option.
(md_parse_option): Handle it. Set mips_32bit_abi given -mabi=32.
(md_show_usage): Show usage for -mfp32 and -mgp32.
(HAVE_32BIT_GPRS, HAVE_32BIT_FPRS): New macros.
(HAVE_64BIT_GPRS, HAVE_64BIT_FPRS): New macros, inverse of the above.
(HAVE_32BIT_ADDRESSES): New macro.
(load_register): Use HAVE_32BIT_GPRS to determine the register width.
(load_address): Use HAVE_32BIT_ADDRESSES to determine the address size.
(s_cprestore, s_cpadd): Likewise.
(macro): Use HAVE_32BIT_GPRS to determine the width of registers
used in branch and M_LI_D macros. Use HAVE_64BIT_FPRS to determine
the width registers used in M_LI_DD macros. Use HAVE_32BIT_ADDRESSES
to determine the width of addresses in load, store and jump macros.
(macro2): Use HAVE_32BIT_GPRS to determine the width of registers
used in set instructions; do not check the address size for them.
Use HAVE_32BIT_ADDRESSES to determine the width of addresses in
unaligned load and store macros.
(mips_ip): Use the new macros to check the width of a register when
processing float constants. Force a constant into memory if it is
destined for an FPR and the FPRs are wider than the GPRs. Warn about
odd FPR numbers if HAVE_32BIT_FPRS. Use HAVE_32BIT_GPRS rather
than mips_gp32 to select synthetic instructions.
(macro_build): Use HAVE_32BIT_GPRS rather than mips_gp32 to select
synthetic instructions.
* config/tc-mips.c (md_estimate_size_before_relax): Make sure
we treat weak like extern only for ELF.
(mips_fix_adjustable): Make sure we don't adjust extern/weak
symbols only for ELF.
"isbranch" param as all calls have it set.
(pa_parse_neg_cmpsub_cmpltr): Likewise.
(pa_parse_nonneg_add_cmpltr): Likewise. Remember result of
strcasecmp in "nullify" var.
(pa_parse_neg_add_cmpltr): Likewise.
(pa_ip): Don't "save_s" unnecessarily. Update calls to above
functions. Don't print wrong conditions in error messages.
* config/obj-elf.c (obj_elf_section): md_elf_section_change_data_hook
added to grab section information after it's been extracted from the
.section directive.
* cgen.c (gas_cgen_save_fixups): Modified to allow more than one
set of fixups to be stored.
(gas_cgen_restore_fixups): Modified to allow the fixup chain to be
restored to be chosen from any that are saved.
(gas_cgen_swap_fixups): Modified to allow the current set of
fixups to be swapped with any other set that has been saved.
(gas_cgen_initialize_saved_fixups_array): New routine.
* cgen.h: Modifed prototypes for gas_cgen_save_fixups,
gas_cgen_restore_fixups, and gas_cgen_swap_fixups. Added definitions
or MAX_SAVED_FIXUP_CHAINS.
* config/tc-m32r.c (assemble_two_insns): Changed calls to fixup
store, swap and restore fuctions to reflect the new interface.
* config/tc-ia64.c (special_section): Add SPECIAL_SECTION_INIT_ARRAY
and SPECIAL_SECTION_FINI_ARRAY.
(special_section_name): Add .init_array and .fini_array.
(md_pseudo_table): Add init_array and fini_array.
(md): Add pointer_size and pointer_size_shift fields.
(setup_unwind_header): New static function.
(output_unw_records): Modify to use setup_unwind_header.
(generate_unwind_image, dot_endp): Modify to use md.pointer_size and
md.pointer_size_shift.
(md_begin): Initialize md.pointer_size and md.pointer_size_shift.
* config/tc-mips.c (md_apply_fix): Prevent addend from becoming zero
if it's expected to be non-zero.
[gas/testsuite]
* gas/mips/elf-rel3.s: Add zero word to end of file.
* config/tc-m88k.c (md_number_to_imm): Remove; unused since 1993.
(emit_relocations): Ditto.
(s_bss): Ditto.
(md_begin): Reformat comments to conform to the GNU standards.
(md_assemble): Ditto.
2001-06-24 Ben Elliston <bje@redhat.com>
* config/tc-m88k.c (get_reg): Adjust type of `reg_prefix' to char.
(md_parse_option): Mark parameters as unused.
(md_show_usage): Ditto.
(calcop): Adjust type of `reg_prefix' to char.
(get_reg): Ditto.
(getval): Adjust type of local `c' to char.
(md_create_short_jump): Mark from_addr, to_addr params as unused.
(md_create_long_jump): Ditto.
(md_estimate_size_before_relax): Mark parameters as unused.
(md_apply_fix): Use it here. Replace printf with equivalent
as_bad_where.
(tc_gen_reloc): Use as_bad_where instead of as_bad.
(md_apply_fix): Here too.
* config/tc-i386.c (tc_gen_reloc): Use as_bad_where instead of as_bad.
* config/tc-m68k.c (tc_gen_reloc): Likewise.
(md_convert_frag_1): Likewise.
* NEWS: Updated for the new -n option for the MIPS assembler.
* config/tc-mips.c (md_show_usage): Add -n.
* doc/as.texinfo: Document the new -n option.
* doc/c-mips.texi: Likewise.
* doc/as.1: Regenerated.
* config/tc-mips.c (warn_nops): New variable. Set to 0 to
disable warning about all NOPS that the assembler generates.
(macro): Warn NOPS generated only if warn_nops is not 0.
(md_shortopts): Add `n'.
(md_parse_option): Set warn_nops to 1 for `n'.
* config/tc-mips.c (md_apply_fix): Don't adjust common
extern/weak symbols for ELF.
(md_estimate_size_before_relax): Treat weak like extern for
ELF.
(mips_fix_adjustable): Don't adjust extern/weak symbols for
ELF.
* Makefile.in: Regenerate.
* config/tc-mips.c (mips16_mark_labels): Reduce number of calls to
S_GET_VALUE by using a temp.
(append_insn): Likewise, and for S_GET_VALUE too.
(mips_emit_delays): Likewise.
(my_getExpression): Likewise.
(md_apply_fix): Likewise. Use "valueT" rather than "long" for "value".
(mips16_extended_frag): Remove code concerned with avoiding
locking in a frag address now that symbols are not finalized until
relaxation is complete. Cater for first relaxation pass having
bogus addresses. Use relax_marker to reliably determine whether a
symbol frag has been reached on the current pass.
as relaxable if embedded system, make weak syms non-relaxable.
Move definition..
(tc_m68k_fix_adjustable): ..so it can be used here.
(md_apply_fix_2): Sign extend without conditional.
optimize differences between symbols in code sections to
constants.
(mn10300_fix_adjustable): Don't adjust to section+offset
relocations pointing at symbols in code sections.
sections as well.
(elfNN_ia64_final_write_processing): Map .gnu.linkonce.ia64unw.FOO
to .gnu.linkonce.t.FOO text section.
* readelf.c (process_unwind): Print all unwind sections, not just
one.
* config/tc-ia64.c (special_linkonce_name): New.
(make_unw_section): Map .gnu.linkonce.t.FOO text section into
.gnu.linkonce.ia64unw{,i}.FOO.
(ia64_elf_section_type): Handle .gnu.linkonce.ia64unw{,i}.FOO.
(dot_endp): Add comment about it.
* elf/ia64.h (ELF_STRING_ia64_unwind_once): Define.
(ELF_STRING_ia64_unwind_info_once): Define.
* emulparams/elf64_ia64.sh (OTHER_READONLY_SECTIONS): Put
.gnu.linkonce.ia64unw{,i} sections into corresponding .IA_64.unwind*
output sections.
* emulparams/elf64_aix.sh (OTHER_READONLY_SECTIONS): Likewise.
* config/tc-mips.c: Support ELF64 for traditional MIPS targets.
* Makefile.am: (TARG_ENV_HFILES): Add tc-mips.h.
* Makefile.in: Regenerated.
* configure.in: Use traditional MIPS targets for Linux/MIPS.
* configure: Regenerated.
(md_assemble): Call cris_insn_first_word_frag to get the first
frag in an insn, not frag_more. Don't call dwarf2_emit_insn at
end. Drop variable insn_size.
(gen_bdap): Call cris_insn_first_word_frag, not frag_more.
(cris_sym_leading_underscore): Wrap first as_bad parameter in _().
(cris_sym_no_leading_underscore, s_cris_file, s_cris_loc): Ditto.
ENCODE_RELAX (STATE_CONDITIONAL_BRANCH, STATE_UNDF)>: Don't emit
32-bit branch, just set fragP->fr_subtype. Set fragP->fr_var.
<all cases>: Always set fragP->fr_var using md_cris_relax_table.
Add cases to cover all relax states.
* config/tc-ia64.c (md): New member keep_pending_output.
(ia64_flush_pending_output): Flush only if md.keep_pending_output
is not set.
(dot_xdata): Turn on md.keep_pending_output for the duration of
this function.
(dot_xfloat_cons): Ditto.
(dot_xstringer): Ditto.
(dot_xdata_ua): Ditto.
(dot_xfloat_cons_ua): Ditto.
* config/tc-ia64.c (ia64_unrecognized_line, case '['): Add local
label support.
(md_assemble [smallest displacement]): Use correct field of i.op[] union.
(md_assemble [JumpInterSegment output]): Use correct i.disp_reloc[].
(md_assemble [immediate output]): Likewise.
* config/tc-i386.c (tc_gen_reloc): Remove ugly hack which is not needed
anymore since we use bfd_elf_generic_reloc now.
(md_apply_fix3): Only apply hack for partial_inplace if not using RELA.
* cpu-ia64-opc.c (elf64_ia64_operands}: Fix typo: error string for
C8 said "1" instead of "8". Clarify error string for IMM22:
"signed integer" instead of just "integer".
* config/tc-ia64.c (enum operand_match_result): New type.
(operand_match): Change return type to operand_match_result.
Fix all returns appropriately, adding support for returning the
out-of-range result.
(parse_operands): New locals result, error_pos, out_of_range_pos,
curr_out_of_range_pos. Rewrite operand matching loop to give better
error messages.
* ia64-opc-d.c (ia64_opcodes_d): Break the "add" pattern into two
separate variants: one for IMM22 and the other for IMM14.
* ia64-asmtab.c: Regenerate.
* config/tc-ia64.c (struct unwind): Add member "prologue_count".
(dot_proc): Clear unwind.prologue_count to zero.
(dot_prologue): Increment unwind.prologue_count.
(dot_restore): If second operand is omitted, use
unwind.prologue_count -1 for "ecount" (# of additional regions to
pop). Decrement unwind.prologue_count by number of regions
popped.
* configure.in (cpu_type, arch): Add a generic FreeBSD specification as
all FreeBSD platforms should look the same at this level.
* configure: Rebuilt.
* config/tc-i386.c: Add support for old FreeBSD a.out hosts.
Approved by: Philip Blundell <philb@gnu.org>
Message-Id: <E14URxF-00023n-00@kings-cross.london.uk.eu.org>
* config/tc-ia64.c (operand_match, case TAG13): Make a BFD_RELOC_UNUSED
reloc instead of a 0 reloc.
(md_apply_fix3): Check for BFD_RELOC_UNUSED instead of 0, and mark it
as done.
* config/tc-ia64.h (TC_RELOC_RTSYM_LOC_FIXUP): Likewise.
larger.
(relax_frag): Add segment parameter. Only call symbol_get_frag
once. Only call is_dnrange if the symbol is in the same segment,
and the symbol address is larger.
(relax_segment): Pass segment to md_relax_frag and relax_frag.
* write.h (relax_frag): Update declaration.
* config/tc-fr30.c (fr30_relax_frag): Add segment parameter. Pass
it to relax_frag.
* config/tc-m32r.c (m32r_relax_frag): Likewise.
* config/tc-m32r.h (md_relax_frag): Add segment parameter.
(m32r_relax_frag): Update declaration.
* config/tc-mips.h (md_relax_frag): Add segment parameter.
* config/tc-tic54x.h (md_relax_frag): Likewise.
* doc/internals.texi (CPU backend): Update documentation for
md_relax_frag.
instruction sequence consisting of a conditional jump of the
opposite sense around an unconditional jump to the target.
Add jumps/nojumps .arch modifier.
(ELF_TC_SPECIAL_SECTIONS): Drop .IA_64.unwind and .IA_64.unwind_info
(they're now handled via ia64_elf_section_type.
* config/tc-ia64.c (unwind): New members saved_text_seg,
saved_text_subseg, and force_unwind_entry.
(optimize_unw_records): New function to optimize away unnecessary
unwind directives.
(ia64_elf_section_type): New function.
(output_unw_records): Generate unwind info only if the size is
non-zero or if it's forced for some other reason (e.g.,
handlerdata or a personality routine).
(generate_unwind_image): Don't switch back to previous
section---stay inside the unwind info section instead so that
handlerdata that may follow goes into the right place.
(dot_handlerdata): Force generation of unwind entry and save the
current active text segment before generating unwind image.
(dot_unwentry): Force generation of unwind entry.
(dot_personality): Ditto.
(dot_endp): Generate unwind table entry only if there is
some unwind info or the unwind entry was forced.
* config/tc-ia64.c (make_unw_section_name): New macro to form
unwind section name.
(generate_unwind_image): Add "text_name" argument. Use it to
form unwind section name.
(dot_handlerdata): Determine current segment (section) name and
pass it to generate_unwind_image().
(dot_endp): Determine current segment (section) name and use
it to determine the appropriate unwind section name.
(ia64_md_do_align): Add missing ATTRIBUTE_UNUSED declarations to
n, fill, and max arguments.
function to select the header according to the cpu.
(md_after_pass_hook, md_do_align): Remove.
(md_cleanup, m68hc11_cleanup): Remove.
(md_pcrel_from_section): Declare.
* config/tc-m68hc11.c (build_dbranch_insn): Remove insn_size.
(build_jump_insn, build_insn): Likewise.
(m68hc11_listing_header): New function.
(m68hc11_cleanup): Remove.
* tc-i386.c (md_assemble): Return after the error message;
move testing for 64bit operands to proper place.
* i386.exp: Add tests for presence of 32bit versus 64bit output
format; run both 64bit and 32bit tests when format is available;
add x86_64 test.
* x86_64.s: New file.
* x86_64.d: New file.
(QWORD_MNEM_SUFFIX): New macro.
(CpuK6,CpuAthlon,CpuSledgehammer, Cpu64, CpuNo64, CpuUnknownFlags):
New macros
(CpuMMX,CpuSSE,Cpu3dnow, CpuUnknown): Renumber.
(IgnoreSize, DefaultSize, No_?Suf, FWait, IsString, regKludge, IsPrefix,
ImmExt): Renumber.
(Size64, No_qSuf, NoRex64, Rex64): New macros.
(Reg64, Imm32S, Imm64, Disp32S, Disp64): New macros.
(Imm8, Imm8S, Imm16, Imm32, Imm1, BaseIndex, Disp8, Disp16, Disp32,
InOutPortReg,ShiftCount, Control, Debug, Test, FloatReg, FloatAcc,
SReg2, SReg3, Acc, JumpAbsolute, RegMMX, RegXMM, EsSeg, InvMem): Renumber.
(Reg, WordReg): Add Reg64.
(Imm): Add Imm32S and Imm64.
(EncImm): New.
(Disp): Add Disp64 and Disp32S.
(AnyMem): Add Disp32S.
(RegRex, RegRex64): New macros.
(rex_byte): New type.
* tc-i386.c (set_16bit_code_flag): Kill.
(fits_in_unsigned_long, fits_in_signed_long): New functions.
(reloc): New parameter "signed"; support x86_64.
(set_code_flag): New.
(DEFAULT_ARCH): New macro; default to "i386".
(default_arch): New static variable.
(struct _i386_insn): New fields Operand_PCrel; rex.
(flag_16bit_code): Kill; All tests replaced to "flag_code == CODE_64BIT";
(flag_code): New enum and static variable.
(use_rela_relocations): New static variable.
(flag_code_names): New static variable.
(cpu_arch_flags): Default to CpuUnknownFlags|CpuNo64.
(cpu_arch): Add "sledgehammer"; Add CPUAthlon to Athlon and CpuK6 to
K6 and Athlon.
(i386_align_code): Return plain "nop" for x86_64.
(mode_from_disp_size): Support Disp32S.
(smallest_imm_type): Support Imm32S and Imm64.
(offset_in_range): Support size of 8.
(set_cpu_arch): Do not clobber to Cpu64/CpuNo64.
(md_pseudo_table): Add "code64"; use set_code_flat.
(md_begin): Emit sane error message on hash failure.
(tc_i386_fix_adjustable): Support x86_64 relocations.
(md_assemble): Support QWORD_MNEM_SUFFIX, REX registers,
instructions supported on particular arch just partially,
output of 64bit immediates, handling of Imm32S and Disp32S type.
(i386_immedaite): Support x86_64 relocations; support 64bit constants.
(i386_displacement): Likewise.
(i386_index_check): Cleanup; support 64bit addresses.
(md_apply_fix3): Support x86_64 relocation and rela.
(md_longopts): Add "32" and "64".
(md_parse_option): Add OPTION_32 and OPTION_64.
(i386_target_format): Call even for ELFs; choose between
elf64-x86-64 and elf32-i386.
(i386_validate_fix): Refuse GOTOFF in 64bit mode.
(tc_gen_reloc): Support rela relocations and x86_64.
(intel_e09_1): Support QWORD.
* i386.h (i386_optab): Replace "Imm" with "EncImm".
(i386_regtab): Add flags field.
* config/tc-i386.c (intel_e09_1): Only flag as a memory operand if
it's not an offset expression.
(intel_e10_1): Ditto. Also, if the operand is an offset expression,
keep the braces '[' and ']' in the output string.
(intel_e11): Ditto. Also remove comparison intel_parser.op_modifier
!= FLAT. There is no such op_modifier.
* elfxx-ia64.c (get_dyn_sym_info): Cast %p argument to void *.
* config/tc-ia64.h (ia64_init): Add prototype.
* gas/ia64/dv-imply.d, gas/ia64/dv-mutex.d, gas/ia64/dv-safe.d,
gas/ia64/dv-srlz.d, gas/ia64/opc-m.d: Update.
* ia64-dis.c (print_insn_ia64): Cast away const on ia64_free_opcode
argument.
* ia64_gen.c (insert_deplist): Cast sizeof result to int.
(print_dependency_table): Print NULL if semantics field not set.
(insert_opcode_dependencies): Mark cmp parameter as unused.
(print_main_table): Use fprintf_vma to print long long fields.
(main): Mark argv paramter as unused. Convert to old style definition.
* ia64-opc.c (ia64_find_dependency): Cast sizeof result to int.
* ia64-asmtab.c: Regnerate.
* tc-i386.c (md_assemble): Swap i.disp_relocs when using intel
syntax.
2000-11-30 Diego Novillo <dnovillo@redhat.com>
* intel.s, intel.d: New test for @GOT references.
jump>: Use as_bad_where instead of as_bad. Tweak error message
accordingly. Stabilize frag by updating fix part and resetting
variant part.
<undefined symbol, unconditional jump>: Ditto.
* config/obj-elf.h (ECOFF_DEBUGGING) [TC_ALPHA]: Adjust for
tri-state definition of alpha_flag_mdebug.
* config/tc-alpha.c (alpha_flag_mdebug): Init to -1.
(s_alpha_file): Store first .file directive.
(s_alpha_stab): New.
(md_pseudo_table): Add stabs and stabn.
* config/obj-elf.c (elf_frob_symbol): Support
".symver name,name2@@@nodename".
(elf_frob_file_before_adjust): Likewise.
* doc/as.texinfo: Updated for ".symver name,name2@@@nodename"
and ".symver name,name2@@@nodename".
Fix a typo.
* config/tc-ia64.c (struct unw_rec_list): Add slot_frag field.
(struct unwind): Add next_slot_frag field.
(slot_index): New parameters slot_frag and first_frag. Add code
to add in frag sizes when different. Add comments.
(fixup_unw_records): New locals first_frag and last_frag. Pass new
arguments to slot_index.
(emit_one_bundle): Set slot_frag field. Set next_slot_number after
loop end. Set next_slot_frag field.
* doc/as.texinfo (.symver): Updated for versioned symbol
reference.
* obj.h (format_ops): Add the frob_file_before_adjust field.
* config/obj-aout.c (aout_format_ops): Set the
frob_file_before_adjust field to 0.
* config/obj-coff.c (coff_format_ops): Likewise.
* config/obj-ecoff.c (ecoff_format_ops): Likewise.
* config/obj-elf.c (obj_elf_symver): Allow duplicated version
name.
(elf_frob_file_before_adjust): New function to remove unneeded
versioned symbols from the symbol table.
(elf_format_ops): Set the frob_file_before_adjust field to
elf_frob_file_before_adjust.
* config/obj-elf.h (obj_frob_file_before_adjust): Defined if
not defined.
* config/obj-multi.h (obj_frob_file_before_adjust): Defined.
* config/tc-ia64.c (md_shortopts, md_parse_option, md_show_usage):
Change M to m for -milp32 or -mlp64 to match gcc.
(dot_endp): Use bytes_per_address instead of 8.
(emit_one_bundle): Use number_to_chars_littleendian instead of
md_number_to_chars.
(fix_insn): Likewise.
(ia64_init): New function.
(ia64_target_format): New function.
(md_begin): Set endianness, arch, and machine as appropriate.
* config/tc-ia64.h: (TARGET_BYTES_BIG_ENDIAN, md_number_to_chars):
Make these macros depend on TE_HPUX macro.
(TARGET_FORMAT): Define.
(HOST_SPECIAL_INIT): Define.
* config/te-hpux.h: New file.
* configure.in: Add "ia64-*-hpux*" target to configure.
* configure: Regenerate.
* config/tc-ia64.c (struct md): New field tag_fixups.
(ia64_flush_insns): Handle tag_fixups. Error if dangling
qualifying predicate.
(emit_one_bundle): Delete spurious multiplication by one. Handle
tag_fixups.
(ia64_start_line): Error if dangling qualifying predicate.
(defining_tag): New static variable.
(ia64_unrecognized_line, case '['): Parse tags.
(ia64_frob_label): Create tag_fixups.
(md_assemble): Reset md.qp.X_op after using it.
* tc-i386.c (i386_operand_modifier): Remove.
(build_displacement_string): Remove.
(i386_parse_seg): Remove.
(i386_intel_memory_operand): Remove.
(i386_intel_operand): Re-write using recursive descent parser based
on MASM documentation.
(struct intel_parser_s): New structure.
(intel_parser): New static variable.
(struct intel_token): New structure.
(cur_token, prev_token): New static variables.
(T_NIL): Define.
(T_CONST): Define.
(T_REG): Define.
(T_BYTE): Define.
(T_WORD): Define.
(T_DWORD): Define.
(T_QWORD): Define.
(T_XWORD): Define.
(T_SHORT): Define.
(T_OFFSET): Define.
(T_PTR): Define.
(T_ID): Define.
(intel_match_token): New function.
(intel_get_token): New function.
(intel_putback_token): New function.
(intel_expr): New function.
(intel_e05): New function.
(intel_e05_1): New function.
(intel_e06): New function.
(intel_e06_1): New function.
(intel_e09): New function.
(intel_e09_1): New function.
(intel_e10): New function.
(intel_e10_1): New function.
(intel_e11): New function.
2000-10-24 Diego Novillo <dnovillo@cygnus.com>
* intel.s, intel.d: Add new tests for intel syntax.
Richard Earnshaw
Stephane Carrez
Chris Demetriou
Nick Clifton
H.J. Lu
Matthew Green
Alan Modra
Hans-Peter Nilsson
Thiemo Seufer
Kazu Hirata
Aldy Hernandez
Tom Rix
Alexandre Oliva
Eric Christopher
Richard Henderson
Jakub Jelinek
Jeff Law
Andreas Jaeger
Richard Sandiford
Geoffrey Keating
Andreas Schwab
John Healy
Jim Wilson
Ben Elliston
Phil Blundell
Jason Eckhardt
Dave Brolley
Timothy Wall
David O'Brien
Ian Lance Taylor
Jan Hubicka
DJ Delorie
Diego Novillo
Bernd Schmidt