1b54b8d7e4
x86: fold RegXMM/RegYMM/RegZMM into RegSIMD
...
... qualified by their respective sizes, allowing to drop FirstXmm0 at
the same time.
2017-12-18 09:36:14 +01:00
dc821c5f9a
x86: replace Reg8, Reg16, Reg32, and Reg64
...
Use a combination of a single new Reg bit and Byte, Word, Dword, or
Qword instead.
Besides shrinking the number of operand type bits this has the benefit
of making register handling more similar to accumulator handling (a
generic flag is being accompanied by a "size qualifier"). It requires,
however, to split a few insn templates, as it is no longer correct to
have combinations like Reg32|Reg64|Byte. This slight growth in size will
hopefully be outweighed by this change paving the road for folding a
presumably much larger number of templates later on.
2017-12-18 09:34:00 +01:00
93b71a2666
x86: drop stray CheckRegSize uses
...
They are relevant only when multiple operands permit registers:
operand_type_register_match() returns true if either operand is not a
register one. IOW
grep -i CheckRegSize i386-opc.tbl | grep -Ev "(Reg[8136]|Acc).*,.*(Reg|Acc)"
should produce no output.
2017-12-15 09:13:54 +01:00
7ac2002247
x86: derive DispN from BaseIndex
...
BaseIndex implies - with the exception of string instructions the
optional presence of a displacement. This is almost completely uniform
for all instructions (the sole exception being MPX ones, which don't
allow 16-bit addressing and hence Disp16), so there's no point in
explicitly stating this in the main opcode table. Drop those explict
specifications in favor of adding logic to i386-gen, shrinking the
table size quite a bit and hence making it more readable.
The opcodes/i386-tbl.h changes are due to a few cases where pointless
Disp* still hadn't been removed from their insns.
2017-11-30 11:48:13 +01:00
b5014f7af2
x86: drop Vec_Disp8
...
This is fully redundant with Disp8MemShift being non-zero, and hence can
be folded with normal Disp8 handling.
2017-11-30 11:47:38 +01:00
be7d1531e1
Add Disp8MemShift for AVX512 VAES instructions.
...
opcodes/
* i386-opc.tbl: Add Disp8MemShift for AVX512 VAES instructions.
* i386-tbl.h: Regenerate.
gas/
* testsuite/gas/i386/avx512f_vaes-intel.d: Regenerate.
* testsuite/gas/i386/avx512f_vaes.d: Likewise.
* testsuite/gas/i386/avx512f_vaes-wig1-intel.d: Likewise.
* testsuite/gas/i386/avx512f_vaes-wig1.d: Likewise.
* testsuite/gas/i386/avx512vl_vaes-intel.d: Likewise.
* testsuite/gas/i386/avx512vl_vaes.d: Likewise.
* testsuite/gas/i386/x86-64-avx512f_vaes.s: Add instructions with disp8*N.
* testsuite/gas/i386/x86-64-avx512f_vaes-intel.d: Regenerate.
* testsuite/gas/i386/x86-64-avx512f_vaes.d: Likewise.
* testsuite/gas/i386/x86-64-avx512f_vaes-wig.s: Add instructions with disp8*N.
* testsuite/gas/i386/x86-64-avx512f_vaes-wig1-intel.d: Regenerate.
* testsuite/gas/i386/x86-64-avx512f_vaes-wig1.d: Likewise.
* testsuite/gas/i386/x86-64-avx512vl_vaes-intel.d: Regenerate.
* testsuite/gas/i386/x86-64-avx512vl_vaes.d: Likewise.
* testsuite/gas/i386/x86-64-avx512vl_vaes-wig.s: Add instructions with disp8*N.
* testsuite/gas/i386/x86-64-avx512vl_vaes-wig1-intel.d: Regenerate.
* testsuite/gas/i386/x86-64-avx512vl_vaes-wig1.d: Regenerate.
2017-11-23 18:25:49 +03:00
66f1eba0b7
x86: correct UDn
...
Make the assembler recognize UD0, supporting only the newer form
expecting a ModR/M byte.
Make assembler and disassembler properly emit / expect a ModR/M byte for
UD1.
For the testsuite, as arch-4 already tests all UDn, avoid producing a
huge delta for other tests using UD2B by making them use UD2 instead.
2017-11-23 10:59:48 +01:00
94b98370de
Remove Vec_Disp8 field for vgf2p8mulb for AVX flavor.
...
* i386-opc.tbl: Remove Vec_Disp8 from vgf2p8mulb.
* i386-tbl.h: Regenerate.
2017-11-22 17:41:04 +03:00
c7478d028e
Remove Vec_Disp8 from vpcompressb and vpexpandb.
...
* i386-opc.tbl: Remove Vec_Disp8 from vpcompressb and vpexpandb.
* i386-tbl.h: Regenerate.
2017-11-22 17:13:55 +03:00
2645e1d079
x86: add support for AVX-512 VPCMP*{B,W} pseudo-ops
...
... matching up with VPCMP*{D,Q}.
2017-11-14 08:42:26 +01:00
df145ef656
x86: string insns don't allow displacements
...
Remove the misleading indicators from the table.
2017-11-14 08:40:48 +01:00
897e603cb9
x86: {f,}xsave64 / {f,}xrstor64 / xsaveopt64 should not allow q suffix
...
Just like is the case for xsave{s,c}64 and xrstors64 already. I wonder
though why xsave{s,c} and xrstors don't allow for the q suffix, other
than the other insns without the "64" suffix do.
2017-11-13 12:21:29 +01:00
ee6872beb1
Enable Intel AVX512_BITALG instructions.
...
Intel has disclosed a set of new instructions. The spec is
https://software.intel.com/sites/default/files/managed/c5/15/architecture-instruction-set-extensions-programming-reference.pdf
gas/
* config/tc-i386.c (cpu_arch): Add .avx512_bitalg.
(cpu_noarch): noavx512_bitalg.
* doc/c-i386.texi: Document .avx512_bitalg, noavx512_bitalg.
* testsuite/gas/i386/i386.exp: Add AVX512_BITALG tests.
* testsuite/gas/i386/avx512f_bitalg-intel.d: New test.
* testsuite/gas/i386/avx512f_bitalg.d: Likewise.
* testsuite/gas/i386/avx512f_bitalg.s: Likewise.
* testsuite/gas/i386/avx512vl_bitalg-intel.d: Likewise.
* testsuite/gas/i386/avx512vl_bitalg.d: Likewise.
* testsuite/gas/i386/avx512vl_bitalg.s: Likewise.
* testsuite/gas/i386/x86-64-avx512f_bitalg-intel.d: Likewise.
* testsuite/gas/i386/x86-64-avx512f_bitalg.d: Likewise.
* testsuite/gas/i386/x86-64-avx512f_bitalg.s: Likewise.
* testsuite/gas/i386/x86-64-avx512vl_bitalg-intel.d: Likewise.
* testsuite/gas/i386/x86-64-avx512vl_bitalg.d: Likewise.
* testsuite/gas/i386/x86-64-avx512vl_bitalg.s: Likewise.
opcodes/
* i386-dis.c (enum): Add PREFIX_EVEX_0F3854, PREFIX_EVEX_0F388F.
(enum): Add EVEX_W_0F3854_P_2.
* i386-dis-evex.h (evex_table): Updated.
* i386-gen.c (cpu_flag_init): Add CPU_AVX512_BITALG,
CPU_ANY_AVX512_BITALG_FLAGS. Update CPU_ANY_AVX512F_FLAGS.
(cpu_flags): Add CpuAVX512_BITALG.
* i386-opc.h (enum): Add CpuAVX512_BITALG.
(i386_cpu_flags): Add cpuavx512_bitalg..
* i386-opc.tbl: Add Intel AVX512_BITALG instructions.
* i386-init.h: Regenerate.
* i386-tbl.h: Likewise.
2017-10-23 15:58:18 +03:00
8cfcb7659c
Enable Intel AVX512_VNNI instructions.
...
Intel has disclosed a set of new instructions. The spec is
https://software.intel.com/sites/default/files/managed/c5/15/architecture-instruction-set-extensions-programming-reference.pdf
gas/
* config/tc-i386.c (cpu_arch): Add .avx512_vnni.
(cpu_noarch): Add noavx512_vnni.
* doc/c-i386.texi: Document .avx512_vnni.
* testsuite/gas/i386/i386.exp: Add AVX512_VNNI tests.
* testsuite/gas/i386/avx512vnni-intel.d: New test.
* testsuite/gas/i386/avx512vnni.d: Likewise.
* testsuite/gas/i386/avx512vnni.s: Likewise.
* testsuite/gas/i386/avx512vnni_vl-intel.d: Likewise.
* testsuite/gas/i386/avx512vnni_vl.d: Likewise.
* testsuite/gas/i386/avx512vnni_vl.s: Likewise.
* testsuite/gas/i386/x86-64-avx512vnni-intel.d: Likewise.
* testsuite/gas/i386/x86-64-avx512vnni.d: Likewise.
* testsuite/gas/i386/x86-64-avx512vnni.s: Likewise.
* testsuite/gas/i386/x86-64-avx512vnni_vl-intel.d: Likewise.
* testsuite/gas/i386/x86-64-avx512vnni_vl.d: Likewise.
* testsuite/gas/i386/x86-64-avx512vnni_vl.s: Likewise.
opcodes/
* i386-dis.c (enum): Add PREFIX_EVEX_0F3850, PREFIX_EVEX_0F3851.
* i386-dis-evex.h (evex_table): Updated.
* i386-gen.c (cpu_flag_init): Add CPU_AVX512_VNNI,
CPU_ANY_AVX512_VNNI_FLAGS. Update CPU_ANY_AVX512F_FLAGS.
(cpu_flags): Add CpuAVX512_VNNI.
* i386-opc.h (enum): Add CpuAVX512_VNNI.
(i386_cpu_flags): Add cpuavx512_vnni.
* i386-opc.tbl Add Intel AVX512_VNNI instructions.
* i386-init.h: Regenerate.
* i386-tbl.h: Likewise.
2017-10-23 15:58:18 +03:00
ff1982d53a
Enable Intel VPCLMULQDQ instruction.
...
Intel has disclosed a set of new instructions. The spec is
https://software.intel.com/sites/default/files/managed/c5/15/architecture-instruction-set-extensions-programming-reference.pdf
gas/
* config/tc-i386.c (cpu_arch): Add VPCLMULQDQ.
* doc/c-i386.texi: Document VPCLMULQDQ.
* testsuite/gas/i386/i386.exp: Run VPCLMULQDQ tests.
* testsuite/gas/i386/avx512f_vpclmulqdq-intel.d: New test.
* testsuite/gas/i386/avx512f_vpclmulqdq-wig.s: Ditto.
* testsuite/gas/i386/avx512f_vpclmulqdq-wig1-intel.d: Ditto.
* testsuite/gas/i386/avx512f_vpclmulqdq-wig1.d: Ditto.
* testsuite/gas/i386/avx512f_vpclmulqdq.d: Ditto.
* testsuite/gas/i386/avx512f_vpclmulqdq.s: Ditto.
* testsuite/gas/i386/avx512vl_vpclmulqdq-intel.d: Ditto.
* testsuite/gas/i386/avx512vl_vpclmulqdq-wig.s: Ditto.
* testsuite/gas/i386/avx512vl_vpclmulqdq-wig1-intel.d: Ditto.
* testsuite/gas/i386/avx512vl_vpclmulqdq-wig1.d: Ditto.
* testsuite/gas/i386/avx512vl_vpclmulqdq.d: Ditto.
* testsuite/gas/i386/avx512vl_vpclmulqdq.s: Ditto.
* testsuite/gas/i386/vpclmulqdq-intel.d: Ditto.
* testsuite/gas/i386/vpclmulqdq.d: Ditto.
* testsuite/gas/i386/vpclmulqdq.s: Ditto.
* testsuite/gas/i386/x86-64-avx512f_vpclmulqdq-intel.d: Ditto.
* testsuite/gas/i386/x86-64-avx512f_vpclmulqdq-wig.s: Ditto.
* testsuite/gas/i386/x86-64-avx512f_vpclmulqdq-wig1-intel.d: Ditto.
* testsuite/gas/i386/x86-64-avx512f_vpclmulqdq-wig1.d: Ditto.
* testsuite/gas/i386/x86-64-avx512f_vpclmulqdq.d: Ditto.
* testsuite/gas/i386/x86-64-avx512f_vpclmulqdq.s: Ditto.
* testsuite/gas/i386/x86-64-avx512vl_vpclmulqdq-intel.d: Ditto.
* testsuite/gas/i386/x86-64-avx512vl_vpclmulqdq-wig.s: Ditto.
* testsuite/gas/i386/x86-64-avx512vl_vpclmulqdq-wig1-intel.d: Ditto.
* testsuite/gas/i386/x86-64-avx512vl_vpclmulqdq-wig1.d: Ditto.
* testsuite/gas/i386/x86-64-avx512vl_vpclmulqdq.d: Ditto.
* testsuite/gas/i386/x86-64-avx512vl_vpclmulqdq.s: Ditto.
* testsuite/gas/i386/x86-64-vpclmulqdq-intel.d: Ditto.
* testsuite/gas/i386/x86-64-vpclmulqdq.d: Ditto.
* testsuite/gas/i386/x86-64-vpclmulqdq.s: Ditto.
opcodes/
* i386-dis.c (enum): Add PREFIX_EVEX_0F3A44.
(enum): Remove VEX_LEN_0F3A44_P_2.
(vex_len_table): Ditto.
(enum): Remove VEX_W_0F3A44_P_2.
(vew_w_table): Ditto.
(prefix_table): Adjust instructions (see prefixes above).
* i386-dis-evex.h (evex_table):
Add new instructions (see prefixes above).
* i386-gen.c (cpu_flag_init): Add VPCLMULQDQ.
(bitfield_cpu_flags): Ditto.
* i386-opc.h (enum): Ditto.
(i386_cpu_flags): Ditto.
(CpuUnused): Comment out to avoid zero-width field problem.
* i386-opc.tbl (vpclmulqdq): New instruction.
* i386-init.h: Regenerate.
* i386-tbl.h: Ditto.
2017-10-23 15:58:18 +03:00
8dcf1fadf2
Enable Intel VAES instructions.
...
Intel has disclosed a set of new instructions. The spec is
https://software.intel.com/sites/default/files/managed/c5/15/architecture-instruction-set-extensions-programming-reference.pdf
gas/
* config/tc-i386.c (cpu_arch): Add VAES.
* doc/c-i386.texi: Document VAES.
* testsuite/gas/i386/i386.exp: Run VAES tests.
* testsuite/gas/i386/avx512f_vaes-intel.d: New test.
* testsuite/gas/i386/avx512f_vaes-wig.s: Ditto.
* testsuite/gas/i386/avx512f_vaes-wig1-intel.d: Ditto.
* testsuite/gas/i386/avx512f_vaes-wig1.d: Ditto.
* testsuite/gas/i386/avx512f_vaes.d: Ditto.
* testsuite/gas/i386/avx512f_vaes.s: Ditto.
* testsuite/gas/i386/avx512vl_vaes-intel.d: Ditto.
* testsuite/gas/i386/avx512vl_vaes-wig.s: Ditto.
* testsuite/gas/i386/avx512vl_vaes-wig1-intel.d: Ditto.
* testsuite/gas/i386/avx512vl_vaes-wig1.d: Ditto.
* testsuite/gas/i386/avx512vl_vaes.d: Ditto.
* testsuite/gas/i386/avx512vl_vaes.s: Ditto.
* testsuite/gas/i386/vaes-intel.d: Ditto.
* testsuite/gas/i386/vaes.d: Ditto.
* testsuite/gas/i386/vaes.s: Ditto.
* testsuite/gas/i386/x86-64-avx512f_vaes-intel.d: Ditto.
* testsuite/gas/i386/x86-64-avx512f_vaes-wig.s: Ditto.
* testsuite/gas/i386/x86-64-avx512f_vaes-wig1-intel.d: Ditto.
* testsuite/gas/i386/x86-64-avx512f_vaes-wig1.d: Ditto.
* testsuite/gas/i386/x86-64-avx512f_vaes.d: Ditto.
* testsuite/gas/i386/x86-64-avx512f_vaes.s: Ditto.
* testsuite/gas/i386/x86-64-avx512vl_vaes-intel.d: Ditto.
* testsuite/gas/i386/x86-64-avx512vl_vaes-wig.s: Ditto.
* testsuite/gas/i386/x86-64-avx512vl_vaes-wig1-intel.d: Ditto.
* testsuite/gas/i386/x86-64-avx512vl_vaes-wig1.d: Ditto.
* testsuite/gas/i386/x86-64-avx512vl_vaes.d: Ditto.
* testsuite/gas/i386/x86-64-avx512vl_vaes.s: Ditto.
* testsuite/gas/i386/x86-64-vaes-intel.d: Ditto.
* testsuite/gas/i386/x86-64-vaes.d: Ditto.
* testsuite/gas/i386/x86-64-vaes.s: Ditto.
opcodes/
* i386-dis.c (enum): Add PREFIX_EVEX_0F38DC, PREFIX_EVEX_0F38DD,
PREFIX_EVEX_0F38DE, PREFIX_EVEX_0F38DF.
(enum): Remove VEX_LEN_0F38DC_P_2, VEX_LEN_0F38DD_P_2,
VEX_LEN_0F38DE_P_2, VEX_LEN_0F38DF_P_2.
(vex_len_table): Ditto.
(enum): Remove VEX_W_0F38DC_P_2, VEX_W_0F38DD_P_2,
VEX_W_0F38DE_P_2, VEX_W_0F38DF_P_2.
(vew_w_table): Ditto.
(prefix_table): Adjust instructions (see prefixes above).
* i386-dis-evex.h (evex_table):
Add new instructions (see prefixes above).
* i386-gen.c (cpu_flag_init): Add VAES.
(bitfield_cpu_flags): Ditto.
* i386-opc.h (enum): Ditto.
(i386_cpu_flags): Ditto.
* i386-opc.tbl (vaes{enc,dec}{last,}): New instructions.
* i386-init.h: Regenerate.
* i386-tbl.h: Ditto.
2017-10-23 15:58:18 +03:00
48521003d5
Enable Intel GFNI instructions.
...
Intel has disclosed a set of new instructions. The spec is
https://software.intel.com/sites/default/files/managed/c5/15/architecture-instruction-set-extensions-programming-reference.pdf
gas/
* config/tc-i386.c (cpu_arch): Add .gfni.
* doc/c-i386.texi: Document .gfni.
* testsuite/gas/i386/i386.exp: Add GFNI tests.
* testsuite/gas/i386/avx.s: New GFNI test.
* testsuite/gas/i386/x86-64-avx.s: Likewise.
* testsuite/gas/i386/avx.d: Adjust.
* testsuite/gas/i386/avx-intel.d: Likewise
* testsuite/gas/i386/ilp32/x86-64-avx-intel.d: Likewise.
* testsuite/gas/i386/ilp32/x86-64-avx.d: Likewise.
* testsuite/gas/i386/avx512f_gfni-intel.d: New test.
* testsuite/gas/i386/avx512f_gfni.d: Likewise.
* testsuite/gas/i386/avx512f_gfni.s: Likewise.
* testsuite/gas/i386/avx512vl_gfni-intel.d: Likewise.
* testsuite/gas/i386/avx512vl_gfni.d: Likewise.
* testsuite/gas/i386/avx512vl_gfni.s: Likewise.
* testsuite/gas/i386/gfni-intel.d: Likewise.
* testsuite/gas/i386/gfni.d: Likewise.
* testsuite/gas/i386/gfni.s: Likewise.
* testsuite/gas/i386/x86-64-avx512f_gfni-intel.d: Likewise.
* testsuite/gas/i386/x86-64-avx512f_gfni.d: Likewise.
* testsuite/gas/i386/x86-64-avx512f_gfni.s: Likewise.
* testsuite/gas/i386/x86-64-avx512vl_gfni-intel.d: Likewise.
* testsuite/gas/i386/x86-64-avx512vl_gfni.d: Likewise.
* testsuite/gas/i386/x86-64-avx512vl_gfni.s: Likewise.
* testsuite/gas/i386/x86-64-avx_gfni-intel.d: Likewise.
* testsuite/gas/i386/x86-64-avx_gfni.d: Likewise.
* testsuite/gas/i386/x86-64-avx_gfni.s: Likewise.
* testsuite/gas/i386/x86-64-gfni-intel.d: Likewise.
* testsuite/gas/i386/x86-64-gfni.d: Likewise.
* testsuite/gas/i386/x86-64-gfni.s: Likewise.
opcodes/
* i386-dis.c (enum): Add PREFIX_0F38CF, PREFIX_0F3ACE, PREFIX_0F3ACF,
PREFIX_VEX_0F38CF, PREFIX_VEX_0F3ACE, PREFIX_VEX_0F3ACF,
PREFIX_EVEX_0F38CF, PREFIX_EVEX_0F3ACE, PREFIX_EVEX_0F3ACF.
(enum): Add VEX_W_0F38CF_P_2, VEX_W_0F3ACE_P_2, VEX_W_0F3ACF_P_2,
EVEX_W_0F3ACE_P_2, EVEX_W_0F3ACF_P_2.
(prefix_table): Updated (see prefixes above).
(three_byte_table): Likewise.
(vex_w_table): Likewise.
* i386-dis-evex.h: Likewise.
* i386-gen.c (cpu_flag_init): Add CPU_GFNI_FLAGS, CpuGFNI.
(cpu_flags): Add CpuGFNI.
* i386-opc.h (enum): Add CpuGFNI.
(i386_cpu_flags): Add cpugfni.
* i386-opc.tbl: Add Intel GFNI instructions.
* i386-init.h: Regenerate.
* i386-tbl.h: Likewise.
2017-10-23 15:58:13 +03:00
53467f5707
Enable Intel AVX512_VBMI2 instructions.
...
Intel has disclosed a set of new instructions. The spec is
https://software.intel.com/sites/default/files/managed/c5/15/architecture-instruction-set-extensions-programming-reference.pdf
gas/
* config/tc-i386.c (cpu_arch): Add .avx512_vbmi2.
(cpu_noarch): noavx512_vbmi2.
* doc/c-i386.texi: Document .avx512_vbmi2, noavx512_vbmi2.
* testsuite/gas/i386/i386.exp: Add AVX512_VBMI2 tests.
* testsuite/gas/i386/avx512vbmi2-intel.d: New test.
* testsuite/gas/i386/avx512vbmi2.d: Likewise.
* testsuite/gas/i386/avx512vbmi2.s: Likewise.
* testsuite/gas/i386/avx512vbmi2_vl-intel.d: Likewise.
* testsuite/gas/i386/avx512vbmi2_vl.d: Likewise.
* testsuite/gas/i386/avx512vbmi2_vl.s: Likewise.
* testsuite/gas/i386/x86-64-avx512vbmi2-intel.d: Likewise.
* testsuite/gas/i386/x86-64-avx512vbmi2.d: Likewise.
* testsuite/gas/i386/x86-64-avx512vbmi2.s: Likewise.
* testsuite/gas/i386/x86-64-avx512vbmi2_vl-intel.d: Likewise.
* testsuite/gas/i386/x86-64-avx512vbmi2_vl.d: Likewise.
* testsuite/gas/i386/x86-64-avx512vbmi2_vl.s: Likewise.
opcodes/
* i386-dis.c (enum): Add b_scalar_mode, w_scalar_mode.
Define EXbScalar and EXwScalar for OP_EX.
(enum): Add PREFIX_EVEX_0F3862, PREFIX_EVEX_0F3863,
PREFIX_EVEX_0F3870, PREFIX_EVEX_0F3871, PREFIX_EVEX_0F3872,
PREFIX_EVEX_0F3873, PREFIX_EVEX_0F3A70, PREFIX_EVEX_0F3A71,
PREFIX_EVEX_0F3A72, PREFIX_EVEX_0F3A73.
(enum): Add EVEX_W_0F3862_P_2, EVEX_W_0F3863_P_2,
EVEX_W_0F3870_P_2, EVEX_W_0F3871_P_2, EVEX_W_0F3872_P_2,
EVEX_W_0F3873_P_2, EVEX_W_0F3A70_P_2, EVEX_W_0F3A71_P_2,
EVEX_W_0F3A72_P_2, EVEX_W_0F3A73_P_2.
(intel_operand_size): Handle b_scalar_mode and w_scalar_mode.
(OP_E_memory): Likewise.
* i386-dis-evex.h: Updated.
* i386-gen.c (cpu_flag_init): Add CPU_AVX512_VBMI2,
CPU_ANY_AVX512_VBMI2_FLAGS. Update CPU_ANY_AVX512F_FLAGS.
(cpu_flags): Add CpuAVX512_VBMI2.
* i386-opc.h (enum): Add CpuAVX512_VBMI2.
(i386_cpu_flags): Add cpuavx512_vbmi2.
* i386-opc.tbl: Add Intel AVX512_VBMI2 instructions.
* i386-init.h: Regenerate.
* i386-tbl.h: Likewise.
2017-10-23 15:58:07 +03:00
2234eee61c
x86: CET v2.0: Update incssp and setssbsy
...
Update x86 assembler and disassembler for CET v2.0:
https://software.intel.com/sites/default/files/managed/4d/2a/control-flow-enforcement-technology-preview.pdf
1. incsspd and incsspq are changed to take a register opeand with a
different opcode.
2. setssbsy is changed to take no opeand with a different opcode.
gas/
* testsuite/gas/i386/cet-intel.d: Updated.
* testsuite/gas/i386/cet.d: Likewise.
* testsuite/gas/i386/x86-64-cet-intel.d: Likewise.
* testsuite/gas/i386/x86-64-cet.d: Likewise.
* testsuite/gas/i386/cet.s: Update incsspd and setssbsy tests.
* testsuite/gas/i386/x86-64-cet.s: Likewise.
opcodes/
* i386-dis.c (RM_0FAE_REG_5): Removed.
(PREFIX_MOD_3_0F01_REG_5_RM_1): Likewise.
(PREFIX_MOD_3_0F01_REG_5_RM_0): New.
(PREFIX_MOD_3_0FAE_REG_5): Likewise.
(prefix_table): Remove PREFIX_MOD_3_0F01_REG_5_RM_1. Add
PREFIX_MOD_3_0F01_REG_5_RM_0.
(prefix_table): Update PREFIX_MOD_0_0FAE_REG_5. Add
PREFIX_MOD_3_0FAE_REG_5.
(mod_table): Update MOD_0FAE_REG_5.
(rm_table): Update RM_0F01_REG_5. Remove RM_0FAE_REG_5.
* i386-opc.tbl: Update incsspd, incsspq and setssbsy.
* i386-tbl.h: Regenerated.
2017-06-21 08:32:51 -07:00
c2f7640243
x86: CET v2.0: Rename savessp to saveprevssp
...
Replace savessp with saveprevssp for CET v2.0:
https://software.intel.com/sites/default/files/managed/4d/2a/control-flow-enforcement-technology-preview.pdf
gas/
* testsuite/gas/i386/cet-intel.d: Updated.
* testsuite/gas/i386/cet.d: Likewise.
* testsuite/gas/i386/x86-64-cet-intel.d: Likewise.
* testsuite/gas/i386/x86-64-cet.d: Likewise.
* testsuite/gas/i386/cet.s: Replace savessp with saveprevssp.
* testsuite/gas/i386/x86-64-cet.s: Likewise.
opcodes/
* i386-dis.c (prefix_table): Replace savessp with saveprevssp.
* i386-opc.tbl: Likewise.
* i386-tbl.h: Regenerated.
2017-06-21 08:30:52 -07:00
04ef582ace
x86: Add NOTRACK prefix support
...
For register indirect branches, NOTRACK prefix (0x3e), which is also
the DS segment register prefix, can be used to ignore the CET indirect
branch track.
gas/
* config/tc-i386.c (REX_PREFIX): Changed to 7.
(NOTRACK_PREFIX): New.
(MAX_PREFIXES): Changed to 8.
(_i386_insn): Add notrack_prefix.
(PREFIX_GROUP): Add PREFIX_DS.
(add_prefix): Return PREFIX_DS for DS_PREFIX_OPCODE.
(md_assemble): Check if NOTRACK prefix is supported.
(parse_insn): Set notrack_prefix and issue an error for
other prefixes after NOTRACK prefix.
* testsuite/gas/i386/i386.exp: Run tests for NOTRACK prefix.
* testsuite/gas/i386/notrack-intel.d: New file.
* testsuite/gas/i386/notrack.d: Likewise.
* testsuite/gas/i386/notrack.s: Likewise.
* testsuite/gas/i386/notrackbad.l: Likewise.
* testsuite/gas/i386/notrackbad.s: Likewise.
* testsuite/gas/i386/x86-64-notrack-intel.d: Likewise.
* testsuite/gas/i386/x86-64-notrack.d: Likewise.
* testsuite/gas/i386/x86-64-notrack.s: Likewise.
* testsuite/gas/i386/x86-64-notrackbad.l: Likewise.
* testsuite/gas/i386/x86-64-notrackbad.s: Likewise.
include/
* include/opcode/i386.h (NOTRACK_PREFIX_OPCODE): New.
opcodes/
* i386-dis.c (NOTRACK_Fixup): New.
(NOTRACK): Likewise.
(NOTRACK_PREFIX): Likewise.
(last_active_prefix): Likewise.
(reg_table): Use NOTRACK on indirect call and jmp.
(ckprefix): Set last_active_prefix.
(prefix_name): Return "notrack" for NOTRACK_PREFIX.
* i386-gen.c (opcode_modifiers): Add NoTrackPrefixOk.
* i386-opc.h (NoTrackPrefixOk): New.
(i386_opcode_modifier): Add notrackprefixok.
* i386-opc.tbl: Add NoTrackPrefixOk to indirect call and jmp.
Add notrack.
* i386-tbl.h: Regenerated.
2017-05-22 11:02:58 -07:00
86fa6981e7
X86: Add pseudo prefixes to control encoding
...
Many x86 instructions have more than one encodings. Assembler picks
the default one, usually the shortest one. Although the ".s", ".d8"
and ".d32" suffixes can be used to swap register operands or specify
displacement size, they aren't very flexible. This patch adds pseudo
prefixes, {xxx}, to control instruction encoding. The available
pseudo prefixes are {disp8}, {disp32}, {load}, {store}, {vex2}, {vex3}
and {evex}. Pseudo prefixes are preferred over the ".s", ".d8" and
".d32" suffixes, which are deprecated.
gas/
* config/tc-i386.c (_i386_insn): Add dir_encoding and
vec_encoding. Remove swap_operand and need_vrex.
(extra_symbol_chars): Add '}'.
(md_begin): Mark '}' with LEX_BEGIN_NAME. Allow '}' in
mnemonic.
(build_vex_prefix): Don't use 2-byte VEX encoding with
{vex3}. Check dir_encoding and load.
(parse_insn): Check pseudo prefixes. Set dir_encoding.
(VEX_check_operands): Likewise.
(match_template): Check dir_encoding and load.
(parse_real_register): Set vec_encoding instead of need_vrex.
(parse_register): Likewise.
* doc/c-i386.texi: Document {disp8}, {disp32}, {load}, {store},
{vex2}, {vex3} and {evex}. Remove ".s", ".d8" and ".d32"
* testsuite/gas/i386/i386.exp: Run pseudos and x86-64-pseudos.
* testsuite/gas/i386/pseudos.d: New file.
* testsuite/gas/i386/pseudos.s: Likewise.
* testsuite/gas/i386/x86-64-pseudos.d: Likewise.
* testsuite/gas/i386/x86-64-pseudos.s: Likewise.
opcodes/
* i386-gen.c (opcode_modifiers): Replace S with Load.
* i386-opc.h (S): Removed.
(Load): New.
(i386_opcode_modifier): Replace s with load.
* i386-opc.tbl: Add {disp8}, {disp32}, {swap}, {vex2}, {vex3}
and {evex}. Replace S with Load.
* i386-tbl.h: Regenerated.
2017-03-09 09:59:00 -08:00
c1fe188b15
Use CpuCET on rdsspq
...
* i386-opc.tbl: Use CpuCET on rdsspq.
* i386-tbl.h: Regenerated.
2017-03-09 07:43:48 -08:00
603555e563
Add support for Intel CET instructions
...
Support Intel Control-flow Enforcement Technology (CET) instructions:
https://software.intel.com/sites/default/files/managed/4d/2a/control-flow-enforcement-technology-preview.pdf
gas/
* config/tc-i386.c (cpu_arch): Add .cet.
* doc/c-i386.texi: Document cet.
* testsuite/gas/i386/cet-intel.d: New file.
* testsuite/gas/i386/cet.d: Likewise.
* testsuite/gas/i386/cet.s: Likewise.
* testsuite/gas/i386/x86-64-cet-intel.d: Likewise.
* testsuite/gas/i386/x86-64-cet.d: Likewise.
* testsuite/gas/i386/x86-64-cet.s: Likewise.
* testsuite/gas/i386/i386.exp: Run Intel CET tests.
opcodes/
* i386-dis.c (REG_0F1E_MOD_3): New enum.
(MOD_0F1E_PREFIX_1): Likewise.
(MOD_0F38F5_PREFIX_2): Likewise.
(MOD_0F38F6_PREFIX_0): Likewise.
(RM_0F1E_MOD_3_REG_7): Likewise.
(PREFIX_MOD_0_0F01_REG_5): Likewise.
(PREFIX_MOD_3_0F01_REG_5_RM_1): Likewise.
(PREFIX_MOD_3_0F01_REG_5_RM_2): Likewise.
(PREFIX_0F1E): Likewise.
(PREFIX_MOD_0_0FAE_REG_5): Likewise.
(PREFIX_0F38F5): Likewise.
(dis386_twobyte): Use PREFIX_0F1E.
(reg_table): Add REG_0F1E_MOD_3.
(prefix_table): Add PREFIX_MOD_0_0F01_REG_5,
PREFIX_MOD_3_0F01_REG_5_RM_1, PREFIX_MOD_3_0F01_REG_5_RM_2,
PREFIX_0F1E, PREFIX_MOD_0_0FAE_REG_5 and PREFIX_0F38F5. Update
PREFIX_0FAE_REG_6 and PREFIX_0F38F6.
(three_byte_table): Use PREFIX_0F38F5.
(mod_table): Use PREFIX_MOD_0_0F01_REG_5, PREFIX_MOD_0_0FAE_REG_5.
Add MOD_0F1E_PREFIX_1, MOD_0F38F5_PREFIX_2, MOD_0F38F6_PREFIX_0.
(rm_table): Add MOD_0F38F5_PREFIX_2, MOD_0F38F6_PREFIX_0,
RM_0F1E_MOD_3_REG_7. Use PREFIX_MOD_3_0F01_REG_5_RM_1 and
PREFIX_MOD_3_0F01_REG_5_RM_2.
* i386-gen.c (cpu_flag_init): Add CPU_CET_FLAGS.
(cpu_flags): Add CpuCET.
* i386-opc.h (CpuCET): New enum.
(CpuUnused): Commented out.
(i386_cpu_flags): Add cpucet.
* i386-opc.tbl: Add Intel CET instructions.
* i386-init.h: Regenerated.
* i386-tbl.h: Likewise.
2017-03-06 15:26:37 -08:00
15c7c1d8a5
x86: fix handling of 64-bit operand size VPCMPESTR{I,M}
...
Just like REX.W affects operand size of the implicit rAX/rDX inputs to
PCMPESTR{I,M}, VEX.W does for VPCMPESTR{I,M}. Allow Q or L suffixes on
the instructions.
Similarly the disassembler needs to be adjusted to no longer require
VEX.W to be zero for the instructions to be valid, and to emit proper
suffixes.
Note, however, that this doesn't address the problem of there being no
way to control (at least) {,E}VEX.W for 32- or 16-bit code. Nor does it
address the problem of the many WIG instructions not getting properly
disassembled when VEX.W=1.
2017-02-28 10:53:35 +01:00
620214f742
Enable Intel AVX512_VPOPCNTDQ instructions
...
gas/
2017-01-12 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
* config/tc-i386.c (cpu_arch): Add .avx512_vpopcntdq.
(cpu_noarch): Add noavx512_vpopcntdq.
* doc/c-i386.texi: Document avx512_vpopcntdq, noavx512_vpopcntdq.
* testsuite/gas/i386/i386.exp: Run AVX512_VPOPCNTDQ tests.
* testsuite/gas/i386/avx512_vpopcntdqd-intel.d: New file.
* testsuite/gas/i386/avx512_vpopcntdqd.d: Ditto.
* testsuite/gas/i386/avx512_vpopcntdqd.s: Ditto.
* testsuite/gas/i386/x86-64-avx512_vpopcntdqd-intel.d: Ditto.
* testsuite/gas/i386/x86-64-avx512_vpopcntdqd.d: Ditto.
* testsuite/gas/i386/x86-64-avx512_vpopcntdqd.s: Ditto.
opcodes/
2017-01-12 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
* i386-dis.c (enum): Add PREFIX_EVEX_0F3855, EVEX_W_0F3855_P_2.
* i386-dis-evex.h (evex_table): Updated.
* i386-gen.c (cpu_flag_init): Add CPU_AVX512_VPOPCNTDQ_FLAGS,
CPU_ANY_AVX512_VPOPCNTDQ_FLAGS. Update CPU_ANY_AVX512F_FLAGS.
(cpu_flags): Add CpuAVX512_VPOPCNTDQ.
* i386-opc.h (enum): (AVX512_VPOPCNTDQ): New.
(i386_cpu_flags): Add cpuavx512_vpopcntdq.
* i386-opc.tbl: Add Intel AVX512_VPOPCNTDQ instructions.
* i386-init.h: Regenerate.
* i386-tbl.h: Ditto.
2017-01-12 08:44:24 -08:00
2571583aed
Update year range in copyright notice of all files.
2017-01-02 14:08:56 +10:30
60227d64dd
X86: Remove the .s suffix from EVEX vpextrw
...
The .s suffix indicates that the instruction is encoded by swapping
2 register operands. Since vpextrw takes an XMM register and an
integer register, the .s suffix should be ignored for EVEX vpextrw.
gas/
PR binutils/20799
* testsuite/gas/i386/opcode.s: Add a test for EVEX vpextrw.
* testsuite/gas/i386/opcode-intel.d: Updated.
* testsuite/gas/i386/opcode-suffix.d: Likewise.
* testsuite/gas/i386/opcode.d: Likewise.
* testsuite/gas/i386/x86-64-avx512bw-opts.s: Remove vpextrw
tests.
* testsuite/gas/i386/x86-64-avx512bw-opts-intel.d: Updated.
* testsuite/gas/i386/x86-64-avx512bw-opts.d: Likewise.
opcodes/
PR binutils/20799
* i386-dis-evex.h (evex_table): Replace EdqwS with Edqw.
* i386-dis.c (EdqwS): Removed.
(dqw_swap_mode): Likewise.
(intel_operand_size): Don't check dqw_swap_mode.
(OP_E_register): Likewise.
(OP_E_memory): Likewise.
(OP_G): Likewise.
(OP_EX): Likewise.
* i386-opc.tbl: Remove "S" from EVEX vpextrw.
* i386-tbl.h: Regerated.
2016-11-09 14:00:18 -08:00
7efeed176a
X86: Merge AVX512F vmovq
...
AVX512F vmovq doesn't support masking. We can't swap register operand
in AVX512F vmovq with Reg64 since Reg64 != RegXMM. This patch merges
AVX512F vmovq.
* i386-opc.tbl: Merge AVX512F vmovq.
2016-11-09 10:20:13 -08:00
47acf0bd9f
Enable Intel AVX512_4VNNIW instructions
...
gas/
* config/tc-i386.c: (cpu_arch) Add .avx512_4vnniw.
(cpu_noarch): Add noavx512_4vnniw.
* doc/c-i386.texi: Document avx512_4vnniw, noavx512_4vnniw.
* testsuite/gas/i386/i386.exp: Run AVX512_4VNNIW tests.
* testsuite/gas/i386/avx512_4vnniwd_vl-intel.d: New test.
* testsuite/gas/i386/avx512_4vnniwd_vl.d: Ditto.
* testsuite/gas/i386/avx512_4vnniwd_vl.s: Ditto.
* testsuite/gas/i386/avx512_4vnniwd-intel.d: Ditto.
* testsuite/gas/i386/avx512_4vnniwd.d: Ditto.
* testsuite/gas/i386/avx512_4vnniwd.s: Ditto.
* testsuite/gas/i386/x86-64-avx512_4vnniwd_vl-intel.d: Ditto.
* testsuite/gas/i386/x86-64-avx512_4vnniwd_vl.d: Ditto.
* testsuite/gas/i386/x86-64-avx512_4vnniwd_vl.s: Ditto.
* testsuite/gas/i386/x86-64-avx512_4vnniwd-intel.d: Ditto.
* testsuite/gas/i386/x86-64-avx512_4vnniwd.d: Ditto.
* testsuite/gas/i386/x86-64-avx512_4vnniwd.s: Ditto.
opcodes/
* i386-dis.c (enum): Add PREFIX_EVEX_0F3852, PREFIX_EVEX_0F3853.
* i386-dis-evex.h (evex_table): Updated.
* i386-gen.c (cpu_flag_init): Add CPU_AVX512_4VNNIW_FLAGS,
CPU_ANY_AVX512_4VNNIW_FLAGS. Update CPU_ANY_AVX512F_FLAGS.
(cpu_flags): Add CpuAVX512_4VNNIW.
* i386-opc.h (enum): (AVX512_4VNNIW): New.
(i386_cpu_flags): Add cpuavx512_4vnniw.
* i386-opc.tbl: Add Intel AVX512_4VNNIW instructions.
* i386-init.h: Regenerate.
* i386-tbl.h: Ditto.
2016-11-02 12:31:25 -07:00
920d2ddccb
Enable Intel AVX512_4FMAPS instructions
...
gas/
* config/tc-i386.c (cpu_arch): Add .avx512_4fmaps.
(cpu_noarch): Add noavx512_4fmaps.
(process_operands): Handle implicit quad group.
* doc/c-i386.texi: Document avx512_4fmaps, noavx512_4fmaps.
* testsuite/gas/i386/i386.exp: Add AVX512_4FMAPS tests.
* testsuite/gas/i386/avx512_4fmaps_vl-intel.d: New test.
* testsuite/gas/i386/avx512_4fmaps_vl.d: Ditto.
* testsuite/gas/i386/avx512_4fmaps_vl.s: Ditto.
* testsuite/gas/i386/avx512_4fmaps-intel.d: Ditto.
* testsuite/gas/i386/avx512_4fmaps.d: Ditto.
* testsuite/gas/i386/avx512_4fmaps.s: Ditto.
* testsuite/gas/i386/avx512_4fmaps-warn.l: Ditto.
* testsuite/gas/i386/avx512_4fmaps-warn.s: Ditto.
* testsuite/gas/i386/avx512_4fmaps_vl-warn.l: Ditto.
* testsuite/gas/i386/avx512_4fmaps_vl-warn.s: Ditto.
* testsuite/gas/i386/x86-64-avx512_4fmaps_vl-intel.d: Ditto.
* testsuite/gas/i386/x86-64-avx512_4fmaps_vl.d: Ditto.
* testsuite/gas/i386/x86-64-avx512_4fmaps_vl.s: Ditto.
* testsuite/gas/i386/x86-64-avx512_4fmaps-intel.d: Ditto.
* testsuite/gas/i386/x86-64-avx512_4fmaps.d: Ditto.
* testsuite/gas/i386/x86-64-avx512_4fmaps.s: Ditto.
* testsuite/gas/i386/x86-64-avx512_4fmaps-warn.l: Ditto.
* testsuite/gas/i386/x86-64-avx512_4fmaps-warn.s: Ditto.
* testsuite/gas/i386/x86-64-avx512_4fmaps_vl-warn.l: Ditto.
* testsuite/gas/i386/x86-64-avx512_4fmaps_vl-warn.s: Ditto.
opcodes/
* i386-dis.c. (enum): Add PREFIX_EVEX_0F389A,
PREFIX_EVEX_0F389B, PREFIX_EVEX_0F38AA, PREFIX_EVEX_0F38AB.
* i386-dis-evex.h (evex_table): Updated.
* i386-gen.c (cpu_flag_init): Add CPU_AVX512_4FMAPS_FLAGS,
CPU_ANY_AVX512_4FMAPS_FLAGS. Update CPU_ANY_AVX512F_FLAGS.
(cpu_flags): Add CpuAVX512_4FMAPS.
(opcode_modifiers): Add ImplicitQuadGroup modifier.
* i386-opc.h (AVX512_4FMAP): New.
(i386_cpu_flags): Add cpuavx512_4fmaps.
(ImplicitQuadGroup): New.
(i386_opcode_modifier): Add implicitquadgroup.
* i386-opc.tbl: Add Intel AVX512_4FMAPS instructions.
* i386-init.h: Regenerate.
* i386-tbl.h: Ditto.
2016-11-02 12:25:34 -07:00
b5cefccad8
X86: Remove pcommit instruction
...
Remove x86 pcommit instruction support, which has been deprecated:
https://software.intel.com/en-us/blogs/2016/09/12/deprecate-pcommit-instruction
gas/
* config/tc-i386.c (cpu_arch): Remove .pcommit.
* doc/c-i386.texi: Likewise.
* testsuite/gas/i386/i386.exp: Remove pcommit tests.
* testsuite/gas/i386/pcommit-intel.d: Removed.
* testsuite/gas/i386/pcommit.d: Likewise.
* testsuite/gas/i386/pcommit.s: Likewise.
* testsuite/gas/i386/x86-64-pcommit-intel.d: Likewise.
* testsuite/gas/i386/x86-64-pcommit.d: Likewise.
* testsuite/gas/i386/x86-64-pcommit.s: Likewise.
opcodes/
* i386-dis.c (PREFIX_RM_0_0FAE_REG_7): Removed.
(prefix_table): Remove the PREFIX_RM_0_0FAE_REG_7 entry.
(rm_table): Update the RM_0FAE_REG_7 entry.
* i386-gen.c (cpu_flag_init): Remove CPU_PCOMMIT_FLAGS.
(cpu_flags): Remove CpuPCOMMIT.
* i386-opc.h (CpuPCOMMIT): Removed.
(i386_cpu_flags): Remove cpupcommit.
* i386-opc.tbl: Remove pcommit.
* i386-init.h: Regenerated.
* i386-tbl.h: Likewise.
2016-10-21 12:16:32 -07:00
6b40c46231
X86: Add ptwrite instruction
...
Implement ptwrite instruction defined in Intel64 and IA-32 Architectures
Software Developer’s Manual, June 2016.
gas/
* config/tc-i386.c (cpu_arch): Add .ptwrite.
* doc/c-i386.texi: Document ptwrite and .ptwrite.
* testsuite/gas/i386/i386.exp: Run ptwrite, ptwrite-intel,
x86-64-ptwrite and x86-64-ptwrite-intel.
* testsuite/gas/i386/ptwrite-intel.d: New file.
* testsuite/gas/i386/ptwrite.d: Likewise.
* testsuite/gas/i386/ptwrite.s: Likewise.
* testsuite/gas/i386/x86-64-ptwrite-intel.d: Likewise.
* testsuite/gas/i386/x86-64-ptwrite.d: Likewise.
* testsuite/gas/i386/x86-64-ptwrite.s: Likewise.
opcodes/
* i386-dis.c (PREFIX_MOD_0_0FAE_REG_4): New.
(PREFIX_MOD_3_0FAE_REG_4): Likewise.
(prefix_table): Add PREFIX_MOD_0_0FAE_REG_4 and
PREFIX_MOD_3_0FAE_REG_4.
(mod_table): Use PREFIX_MOD_0_0FAE_REG_4 and
PREFIX_MOD_3_0FAE_REG_4.
* i386-gen.c (cpu_flag_init): Add CPU_PTWRITE_FLAGS.
(cpu_flags): Add CpuPTWRITE.
* i386-opc.h (CpuPTWRITE): New.
(i386_cpu_flags): Add cpuptwrite.
* i386-opc.tbl: Add ptwrite instruction.
* i386-init.h: Regenerated.
* i386-tbl.h: Likewise.
2016-08-24 15:29:39 -07:00
c07315e0c6
x86: allow suffix-less movzw and 64-bit movzb
...
... just like is already the case for 16- and 32-bit movzb: I can't see
why omitting suffixes on this (and movs{b,w,l}) is not allowed, when it
is allowed for all other instructions where the suffix is redundant
with (one of) the operands.
2016-07-01 09:01:41 +02:00
9243100aef
x86: remove stray instruction attributes
...
- with Cpu64 Disp16 makes no sense for memory operands
- with CpuNo64 Disp32S makes no sense
- non-64-bit lgdt doesn't allow 10-byte operands
2016-07-01 08:57:21 +02:00
8325cc6398
x86/Intel: fix operand checking for MOVSD
...
The dual purpose mnemonic (string move vs scalar double move) breaks
the assumption that the isstring flag would be set on both the first
and last entry in the current set of templates, which results in bogus
or missing diagnostics for the string move variant of the mnemonic.
Short of mostly rewriting i386_index_check() and its interaction with
the rest of the code, simply shrink the template set to just string
instructions when encountering the second memory operand, and run
i386_index_check() a second time for the first memory operand after
that reduction.
2016-07-01 08:56:13 +02:00
07f5af7d3c
Handle indirect branches for AMD64 and Intel64
...
AMD64 spec and Intel64 spec differ in indirect branches in 64-bit mode.
AMD64 supports indirect branches with 16-bit address via the data size
prefix while the data size prefix is ignored by Intel64.
gas/
PR binutis/18386
* testsuite/gas/i386/i386.exp: Run x86-64-branch-4.
* testsuite/gas/i386/x86-64-branch.d: Updated.
* testsuite/gas/i386/ilp32/x86-64-branch.d: Likewise.
* testsuite/gas/i386/x86-64-branch-4.l: New file.
* testsuite/gas/i386/x86-64-branch-4.s: Likewise.
opcodes/
PR binutis/18386
* i386-dis.c (indirEv): Replace stack_v_mode with indir_v_mode.
(indir_v_mode): New.
Add comments for '&'.
(reg_table): Replace "{T|}" with "{&|}" on call and jmp.
(putop): Handle '&'.
(intel_operand_size): Handle indir_v_mode.
(OP_E_register): Likewise.
* i386-opc.tbl: Mark 64-bit indirect call/jmp as AMD64. Add
64-bit indirect call/jmp for AMD64.
* i386-tbl.h: Regenerated
2016-06-03 15:55:29 -07:00
e92bae6260
Replace CpuAMD64/CpuIntel64 with AMD64/Intel64
...
AMD64 vs CpuIntel64 ISA should be handled similar as AT&T vs Intel
syntax. Since cpu_flags isn't sorted by position, we need to check
the whole cpu_flags array for the maximum position when verifying
CpuMax.
gas/
PR gas/20154
* config/tc-i386.c (cpu_flags_match): Don't set cpuamd64 nor
cpuintel64.
(match_template): Check Intel64/AMD64 ISA.
opcodes/
PR gas/20154
* i386-gen.c (cpu_flags): Remove CpuAMD64 and CpuIntel64.
(opcode_modifiers): Add AMD64 and Intel64.
(main): Properly verify CpuMax.
* i386-opc.h (CpuAMD64): Removed.
(CpuIntel64): Likewise.
(CpuMax): Set to CpuNo64.
(i386_cpu_flags): Remove cpuamd64 and cpuintel64.
(AMD64): New.
(Intel64): Likewise.
(i386_opcode_modifier): Add amd64 and intel64.
(i386-opc.tbl): Replace CpuAMD64/CpuIntel64 with AMD64/Intel64
on call and jmp.
* i386-init.h: Regenerated.
* i386-tbl.h: Likewise.
2016-05-27 08:03:17 -07:00
8bc526963e
Enable Intel RDPID instruction.
...
This patch enables Intel RDPID instruction described in Intel64 and
IA-32 Architectures Software Developer's Manual, April 2016.
gas/
* config/tc-i386.c (cpu_arch): Add RDPID.
* doc/c-i386.texi: Document RDPID.
gas/testsuite/
* gas/i386/i386.exp: Run RDPID tests.
* gas/i386/prefix.d: Adjust.
* gas/i386/rdpid.s: New test.
* gas/i386/rdpid.d: Ditto.
* gas/i386/rdpid-intel.d: Ditto.
* gas/i386/x86-64-rdpid.s: Ditto.
* gas/i386/x86-64-rdpid.d: Ditto.
* gas/i386/x86-64-rdpid-intel.d: Ditto.
opcodes/
* i386-dis.c (prefix_table): Add RDPID instruction.
* i386-gen.c (cpu_flag_init): Add RDPID flag.
(cpu_flags): Add RDPID bitfield.
* i386-opc.h (enum): Add RDPID element.
(i386_cpu_flags): Add RDPID field.
* i386-opc.tbl: Add RDPID instruction.
* i386-init.h: Regenerate.
* i386-tbl.h: Regenerate.
2016-05-10 21:38:39 +03:00
6f2750feaf
Copyright update for binutils
2016-01-01 23:00:01 +10:30
8eab413676
Implement Intel OSPKE instructions
...
This patch implements Intel OSPKE instructions documented in Intel64
and IA-32 Architectures Software Developer’s Manual Volume 2, September
2015.
gas/testsuite/
* gas/i386/i386.exp: Run ospke and x86-64-ospke.
* gas/i386/ospke.d: New file.
* gas/i386/ospke.s: Likewise.
* gas/i386/x86-64-ospke.d: Likewise.
opcodes/
* i386-dis.c (MOD_0F01_REG_5): New.
(RM_0F01_REG_5): Likewise.
(reg_table): Use MOD_0F01_REG_5.
(mod_table): Add MOD_0F01_REG_5.
(rm_table): Add RM_0F01_REG_5.
* i386-gen.c (cpu_flag_init): Add CPU_OSPKE_FLAGS.
(cpu_flags): Add CpuOSPKE.
* i386-opc.h (CpuOSPKE): New.
(i386_cpu_flags): Add cpuospke.
* i386-opc.tbl: Add rdpkru and wrpkru instructions.
* i386-init.h: Regenerated.
* i386-tbl.h: Likewise.
2015-12-09 08:01:57 -08:00
9916071f8d
Add support for monitorx/mwaitx instructions
...
gas/
* config/tc-i386.c (cpu_arch): Add .mwaitx.
(process_immext): Check operands for monitorx/mwaitx instructions.
* doc/c-i386.texi: Document mwaitx.
gas/testsuite/
* gas/i386/i386.exp: Add new mwaitx test cases.
* gas/i386/mwaitx.s: New.
* gas/i386/mwaitx-bdver4.d: New.
* gas/i386/x86-64-mwaitx.s: New.
* gas/i386/x86-64-mwaitx-bdver4.d: New.
* gas/i386/mwaitx-reg.s: New.
* gas/i386/mwaitx-reg.l: New.
* gas/i386/x86-64-mwaitx-reg.l: New.
* gas/i386/x86-64-mwaitx-reg.s: New.
* gas/i386/arch-13.s: Updated.
* gas/i386/arch-13.d: Updated.
* gas/i386/arch-13-znver1.d: Updated.
* gas/i386/x86-64-arch-3.s: Updated.
* gas/i386/x86-64-arch-3.d: Updated.
* gas/i386/x86-64-arch-3-znver1.d: Updated.
opcodes/
* i386-dis.c (OP_Mwaitx): New.
(rm_table): Add monitorx/mwaitx.
* i386-gen.c (cpu_flag_init): Add CpuMWAITX to CPU_BDVER4_FLAGS
and CPU_ZNVER1_FLAGS. Add CPU_MWAITX_FLAGS.
(operand_type_init): Add CpuMWAITX.
* i386-opc.h (CpuMWAITX): New.
(i386_cpu_flags): Add cpumwaitx.
* i386-opc.tbl: Add monitorx and mwaitx.
* i386-init.h: Regenerated.
* i386-tbl.h: Likewise.
2015-06-30 07:50:12 -07:00
015c54d5a6
x86/Intel: accept mandated operand order for vcvt{,u}si2s{d,s}
...
As pointed out before, the documentation mandates the rounding mode to
follow the GPR, so gas should accept such input. As the brojen code got
released already we sadly will need to continue to also accept the
badly ordered operands.
gas/testsuite/
2015-06-01 Jan Beulich <jbeulich@suse.com>
* gas/i386/avx512f-intel.d: Adjust expectations on operand order.
* gas/i386/evex-lig256-intel.d: Likewise.
* gas/i386/evex-lig512-intel.d: Likewise.
* gas/i386/x86-64-avx512f-intel.d: Likewise.
* gas/i386/x86-64-evex-lig256-intel.d: Likewise.
* gas/i386/x86-64-evex-lig512-intel.d: Likewise.
opcodes/
2015-06-01 Jan Beulich <jbeulich@suse.com>
* i386-opc.tbl: New IntelSyntax entries for vcvt{,u}si2s{d,s}.
* i386-tbl.h: Regenerate.
2015-06-01 09:50:00 +02:00
071f0063b4
Remove Disp32 from AMD64 direct call/jmp
...
* i386-opc.tbl: Remove Disp32 from AMD64 direct call/jmp.
* i386-init.h: Regenerated.
2015-05-18 04:17:12 -07:00
5db04b0965
Support AMD64/Intel ISAs in assembler/disassembler
...
AMD64 spec and Intel64 spec differ in direct unconditional branches in
64-bit mode. AMD64 supports direct unconditional branches with 16-bit
offset via the data size prefix, which truncates RIP to 16 bits, while
the data size prefix is ignored by Intel64.
This patch adds -mamd64/-mintel64 option to x86-64 assembler and
-Mamd64/-Mintel64 option to x86-64 disassembler. The most permissive
ISA, which is AMD64, is the default.
GDB can add an option, similar to
(gdb) help set disassembly-flavor
Set the disassembly flavor.
The valid values are "att" and "intel", and the default value is "att".
to select which ISA to disassemble.
binutils/
PR binutis/18386
* doc/binutils.texi: Document -Mamd64 and -Mintel64.
gas/
PR binutis/18386
* config/tc-i386.c (OPTION_MAMD64): New.
(OPTION_MINTEL64): Likewise.
(md_longopts): Add -mamd64 and -mintel64.
(md_parse_option): Handle OPTION_MAMD64 and OPTION_MINTEL64.
(md_show_usage): Add -mamd64 and -mintel64.
* doc/c-i386.texi: Document -mamd64 and -mintel64.
gas/testsuite/
PR binutis/18386
* gas/i386/i386.exp: Run x86-64-branch-2 and x86-64-branch-3.
* gas/i386/x86-64-branch.d: Also pass -Mintel64 to objdump.
* gas/i386/ilp32/x86-64-branch.d: Likewise.
* gas/i386/x86-64-branch-2.d: New file.
* gas/i386/x86-64-branch-2.s: Likewise.
* gas/i386/x86-64-branch-3.l: Likewise.
* gas/i386/x86-64-branch-3.s: Likewise.
ld/testsuite/
PR binutis/18386
* ld-x86-64/tlsgdesc.dd: Also pass -Mintel64 to objdump.
* ld-x86-64/tlspic.dd: Likewise.
* ld-x86-64/x86-64.exp (x86_64tests): Also pass -Mintel64 to
objdump for tlspic.dd and tlsgdesc.dd.
opcodes/
PR binutis/18386
* i386-dis.c: Add comments for '@'.
(x86_64_table): Use '@' on call/jmp for X86_64_E8/X86_64_E9.
(enum x86_64_isa): New.
(isa64): Likewise.
(print_i386_disassembler_options): Add amd64 and intel64.
(print_insn): Handle amd64 and intel64.
(putop): Handle '@'.
(OP_J): Don't ignore the operand size prefix for AMD64 in 64-bit.
* i386-gen.c (cpu_flags): Add CpuAMD64 and CpuIntel64.
* i386-opc.h (AMD64): New.
(CpuIntel64): Likewise.
(i386_cpu_flags): Add cpuamd64 and cpuintel64.
* i386-opc.tbl: Add direct call/jmp with Disp16|Disp32 for AMD64.
Mark direct call/jmp without Disp16|Disp32 as Intel64.
* i386-init.h: Regenerated.
* i386-tbl.h: Likewise.
2015-05-15 09:48:10 -07:00
70cead0767
Remove Disp16|Disp32 from 64-bit direct branches
...
Disp16 and Disp32 aren't supported by direct branches in 64-bit mode.
This patch removes them from 64-bit direct branches.
* opcodes/i386-opc.tbl (call): Remove Disp16|Disp32 from 64-bit
direct branch.
(jmp): Likewise.
* i386-tbl.h: Regenerated.
2015-05-11 14:20:37 -07:00
029f352261
Add znver1 processor
2015-03-17 21:49:15 +05:30
b90efa5b79
ChangeLog rotatation and copyright year update
2015-01-02 00:53:45 +10:30
14f195c9a0
Add AVX512VBMI instructions
...
gas/
* config/tc-i386.c (cpu_arch): Add .avx512vbmi.
* doc/c-i386.texi: Document it.
opcodes/
* i386-dis-evex.c (evex_table): Add vpermi2b, vpermt2b, vpermb,
vpmultishiftqb.
* i386-dis.c (PREFIX enum): Add PREFIX_EVEX_0F3883, EVEX_W_0F3883_P_2.
* i386-gen.c (cpu_flag_init): Add CPU_AVX512VBMI_FLAGS.
(cpu_flags): Add CpuAVX512VBMI.
* i386-opc.h (enum): Add CpuAVX512VBMI.
(i386_cpu_flags): Add cpuavx512vbmi.
* i386-opc.tbl: Add vpmadd52luq, vpmultishiftqb, vpermb, vpermi2b,
vpermt2b.
* i386-init.h: Regenerated.
* i386-tbl.h: Likewise.
/gas/testsuite/
* gas/i386/i386.exp: Run new tests.
* gas/i386/avx512vbmi-intel.d: New file.
* gas/i386/avx512vbmi.d: Likewise.
* gas/i386/avx512vbmi.s: Likewise.
* gas/i386/avx512vbmi_vl-intel.d: Likewise.
* gas/i386/avx512vbmi_vl.d: Likewise.
* gas/i386/avx512vbmi_vl.s: Likewise.
* gas/i386/x86-64-avx512vbmi-intel.d: Likewise.
* gas/i386/x86-64-avx512vbmi.d: Likewise.
* gas/i386/x86-64-avx512vbmi.s: Likewise.
* gas/i386/x86-64-avx512vbmi_vl-intel.d: Likewise.
* gas/i386/x86-64-avx512vbmi_vl.d: Likewise.
* gas/i386/x86-64-avx512vbmi_vl.s: Likewise.
2014-11-17 06:03:41 -08:00
2cc1b5aad8
Add AVX512IFMA instructions
...
gas/
* config/tc-i386.c (cpu_arch): Add .avx512ifma.
* doc/c-i386.texi: Document it.
opcodes/
* i386-dis-evex.c (evex_table): Add vpmadd52luq, vpmadd52huq.
* i386-dis.c (PREFIX enum): Add PREFIX_EVEX_0F38B4,
PREFIX_EVEX_0F38B5.
* i386-gen.c (cpu_flag_init): Add CPU_AVX512IFMA_FLAGS.
(cpu_flags): Add CpuAVX512IFMA.
* i386-opc.h (enum): Add CpuAVX512IFMA.
(i386_cpu_flags): Add cpuavx512ifma.
* i386-opc.tbl: Add vpmadd52huq, vpmadd52luq.
* i386-init.h: Regenerated.
* i386-tbl.h: Likewise.
/gas/testsuite/
* gas/i386/i386.exp: Run new tests.
* gas/i386/avx512ifma-intel.d: New file.
* gas/i386/avx512ifma.d: Likewise.
* gas/i386/avx512ifma.s: Likewise.
* gas/i386/avx512ifma_vl-intel.d: Likewise.
* gas/i386/avx512ifma_vl.d: Likewise.
* gas/i386/avx512ifma_vl.s: Likewise.
* gas/i386/x86-64-avx512ifma-intel.d: Likewise.
* gas/i386/x86-64-avx512ifma.d: Likewise.
* gas/i386/x86-64-avx512ifma.s: Likewise.
* gas/i386/x86-64-avx512ifma_vl-intel.d: Likewise.
* gas/i386/x86-64-avx512ifma_vl.d: Likewise.
* gas/i386/x86-64-avx512ifma_vl.s: Likewise.
2014-11-17 06:03:24 -08:00
Jan Beulich
Igor Tsimbalist
H.J. Lu
Alan Modra
Alexander Fomin
Amit Pawar
Ganesh Gopalasubramanian
Ilya Tocar