Committed by Kei Sakamoto.
* traps-linux.c (m32r_trap): Add entries of the following dummy system
calls: __NR_mmap2, __NR_lchown32, __NR_getuid32, __NR_getgid32,
__NR_geteuid32, __NR_getegid32, __NR_getgroups32, __NR_fchown32,
__NR_setfsuid32, __NR_setfsgid32, __NR_getresuid32,
__NR_getresgid32 and __NR_chown32.
* syscall.h: Add new definitions of system call number.
* sim-options.c (STANDARD_OPTIONS): New member OPTION_SYSROOT.
(standard_options): Support --sysroot=<path>.
(standard_option_handler): Handle OPTION_SYSROOT.
* syscall.c (simulator_sysroot): Define, initialized empty.
(get_path): Prepend simulator_sysroot to absolute file path.
[HAVE_STRING_H]: Include string.h.
[!HAVE_STRING_H && HAVE_STRINGS_H]: Include strings.h.
* nrun.c [HAVE_UNISTD_H]: Include unistd.h.
(main): If simulator_sysroot is not empty, chdir there.
* sim-config.h (simulator_sysroot): Declare.
st_dev, st_ino, st_mode, st_nlink, st_uid, st_gid, st_rdev,
st_size, st_blksize, st_blocks, st_atime, st_mtime and st_ctime.
* aclocal.m4 (SIM_CHECK_MEMBER, SIM_CHECK_MEMBERS_1)
(SIM_CHECK_MEMBERS): New macros.
* callback.c (cb_host_to_target_stat): Use temporary macro ST_x
for struct stat member test and write. Add ST_x calls for each
struct stat member tested in configure.in. Wrap each ST_x call in
#ifdef of configure macro for that member.
* configure, config.in: Regenerate.
add sub-dependencies for other sim files that they include.
(sim_main_headers): Use sim-*_h rules.
(sim-load.o): Depend on sim-basics_h, not sim_main_headers.
Committed by Andrew Cagney.
* traps-linux.c: Don't include linux/module.h.
(m32r_trap): Remove dummy systemcall's entry of __NR_ustat and
__NR_get_kernel_syms.
Committed by Andrew Cagney.
* configure.in: Check for sys/mount.h, sys/vfs.h, sys/statfs.h.
Check for struct statfs.
* emul_netbsd.c: If not HAVE_STRUCT_STATFS, #undef HAVE_FSTATFS.
* configure, config.in: Regenerate.
* bandor.s: New file.
* bandornot.s: New file.
* bclr.s: New file.
* bld.s: New file.
* bldnot.s: New file.
* bset.s: New file.
* bst.s: New file.
* bxor.s: New file.
* clip.s: New file.
* div.s: New file.
* fail.s: New file, make sure fail works.
* fsca.s: New file.
* fsrra.s: New file.
* mov.s: New file.
* mulr.s: New file.
* pass.s: New file, make sure pass works.
* pushpop.s: New file.
* resbank.s: New file.
* testutils.inc (bf8k, bt8k, assertmem): New macros.
* interp.c (RAISE_EXCEPTION_IF_IN_DELAY_SLOT): New macro.
(in_delay_slot): New flag variable.
(Delay_Slot): Set in_delay_slot.
(sim_resume): Reset in_delay_slot after leaving code switch.
* gencode.c (op tab): Call RAISE_EXCEPTION_IF_IN_DELAY_SLOT for all
instructions not allowed in delay slots.
Commited by Corinna Vinschen <vinschen@redhat.com>
Introduce SH2a support.
* interp.c: Change type of jump table to short. Add various macros.
(sim_load): Save the bfd machine code.
(sim_create_inferior): Ditto.
(union saved_state_type): Add tbr, ibnr and ibcr registers.
Move bfd_mach to end of struct. Add regstack pointer.
(init_dsp): Don't swap contents of sh_dsp_table any more. Instead
use it directly in its own switch statement. Allocate space for 512
register banks.
(do_long_move_insn): New function.
(do_blog_insn): Ditto.
(trap): Use trap #13 and trap #14 to set ibnr and ibcr.
* gencode.c: Move movx/movy insns into separate switch statement.
(op tab): Add sh2a insns. Reject instructions that are disabled
on that chip.
(gensim_caselist): Generate default case here instead of in caller.
(gensim): Generate two separate switch statements. Call
gensim_caselist once for each (for movsxy_tab and for tab).
Add tokens for r15 and multiple regs.
(conflict_warn, warn_conflicts): Add for debugging.
2004-07-20 Jim Blandy <jimb@redhat.com>
Use a fixed register numbering when communicating with the PowerPC
simulator.
* ppc-tdep.h (struct gdbarch_tdep): New member: 'sim_regno'.
* rs6000-tdep.c: #include "sim-regno.h" and "gdb/sim-ppc.h".
(set_sim_regno, init_sim_regno_table, rs6000_register_sim_regno):
New functions.
(rs6000_gdbarch_init): Register rs6000_register_sim_regno. Call
init_sim_regno_table.
* Makefile.in (gdb_sim_ppc_h): New variable.
(rs6000-tdep.o): Update dependencies.
include/gdb/ChangeLog:
2004-07-20 Jim Blandy <jimb@redhat.com>
* sim-ppc.h: New file.
sim/ppc/ChangeLog:
2004-07-20 Jim Blandy <jimb@redhat.com>
Use a fixed register numbering when communicating with the PowerPC
simulator.
* sim_calls.c: #include "registers.h" and "gdb/sim-ppc.h"; do not
include GDB's "defs.h".
(gdb_register_name_table): New variable.
(gdb_register_name_table_size): New enum constant.
(gdb_register_name): New function.
(sim_fetch_register, sim_store_register): Use gdb_register_name,
instead of calling gdbarch_register_name.
* Makefile.in (GDB_SIM_PPC_H): New variable.
(DEFS_H): Delete variable.
(sim_calls.o): Update dependencies.
2004-07-26 Andrew Cagney <cagney@gnu.org>
Problem from Olaf Hering <olh@suse.de>.
* Makefile.in (install-man, installdirs): Add DESTDIR prefix.
Index: ppc/ChangeLog
2004-07-26 Andrew Cagney <cagney@gnu.org>
Problem from Olaf Hering <olh@suse.de>.
* Makefile.in (install, installdirs): Add DESTDIR.
2003-07-23 Richard Sandiford <rsandifo@redhat.com>
* compile.c (sim_resume): Make sure that dst.reg refers to the
right register byte in mova/sz.l @(dd,RnL),ERn.
2003-07-21 Richard Sandiford <rsandifo@redhat.com>
* compile.c (sim_resume): Zero-extend immediate to muls, mulsu,
mulxs, divs and divxs.
sim/testsuite/sim/h8300/ChangeLog:
2003-07-22 Michael Snyder <msnyder@redhat.com>
* mul.s: Don't try to use negative immediate (it's always
unsigned).
* div.s: Ditto.
* utils-fpu.inc (enable_fpu, ckm_fp_cc): New macros.
(clrset_fp_cc): Fix mask used for upper 7 condition codes.
* utils-mdmx.inc: Include utils-fpu.inc.
(enable_mdmx): Use enable_fpu.
* utils-fpu.inc: New file.
* utils-mdmx.inc: New file.
* mdmx-ob.s: New file.
* mdmx-ob-sb1.s: New file.
* basic.exp: Run new mdmx-ob and mdmx-ob-sb1 tests.
* sim/mips/basic.exp (run_hilo_test): New procedure.
(models): Only list models that are included in the configuration.
(submodels): New variable, set to submodels of the above.
(mips64vr-*-elf, mips64vrel-*-elf): New configuration stanza.
Run hilo-hazard-[123].s.
(MIPS_MACH_HAS_MULT_HILO_HAZARD, MIPS_MACH_HAS_DIV_HILO_HAZARD): New.
* mips.igen (check_mt_hilo, check_mult_hilo, check_div_hilo): Provide
separate implementations for mipsIV and mipsV. Use new macros to
determine whether the restrictions apply.
* frv.c (frvbf_iacc_cut): Rework, taking rounding into account.
testsuite/
* sim/frv/fr400/scutss.cgs: Fix tests to account for rounding.
Add some new ones.
* gencode.c (table): Change from char to short.
(dumptable): Change generated table from char to short.
* interp.c (sh_jump_table, sh_dsp_table, ppi_table): char to short.
(init_dsp): Compute size of sh_dsp_table.
(sim_resume): Change jump_table from char to short.
Committed by Andrew Cagney.
* mloopx.in: Update copyright.
(xextract-pbb): Fixed trap for system calls operation in parallel.
* mloop2.in (xextract-pbb): Ditto.
2004-01-26 Chris Demetriou <cgd@broadcom.com>
* configure.in (mips*-*-*): Configure in testsuite.
* configure: Regenerate.
[ sim/testsuite/ChangeLog ]
2004-01-26 Chris Demetriou <cgd@broadcom.com>
* sim/mips: New directory. Tests for the MIPS simulator.
[ sim/testsuite/sim/mips/ChangeLog ]
2004-01-26 Chris Demetriou <cgd@broadcom.com>
* basic.exp: New file.
* testutils.inc: New file.
* sanity.s: New file.
* mips.igen (check_mf_cycles, check_mt_hilo, check_mf_hilo)
(check_mult_hilo): Improve comments.
(check_div_hilo): Likewise. Also, fork off a new version
to handle mips32/mips64 (since there are no hazards to check
in MIPS32/MIPS64).
* gencode.c (expand_opcode): Simplify and reorganize.
Eliminate "shift" parameter. Eliminate "4 bits at a time"
assumption. Flatten switch statement to a single level.
Add "eeee" token for even-numbered registers.
(bton): Delete.
(fsca): Use "eeee" token.
(ppi_moves): Rename to "expand_ppi_movxy". Do the ddt
[movx/movy] expansion here, as well as the ppi expansion.
(gensim_caselist): Accept 'eeee' along with 'nnnn'.
(O_RDONLY): Do not define.
(O_WRONLY): Likewise.
(O_RDWR): Likewise.
(targ-vals.h): Include it.
(translate_open_mode): Use TARGET_O_* instead of O_*.
(SWIopen): Likewise.
* Makefile.in (armos.o): Depend on targ-vals.h.
(SPR_REGNUM_MAX): Delete.
* frv.c (gdb/sim-frv.h): Include.
(frvbf_fetch_register, frvbf_store_register): Use register number
constants from gdb/sim-frv.h. Check availability of general
purpose and float registers.
* frv-sim.h (REGNUM_LR): Removed.
(REGNUM_SPR_MIN,REGNUM_SPR_MAX): New macros.
* frv.c (frvbf_fetch_register): Fetch SPR registers based on
REGNUM_SPR_MIN and REGNUM_SPR_MAX. Check whether SPRs are implemented.
Return 0 for an unimplemented register. Return the length of the data
for an implemented register.
(frvbf_store_register): Ditto.
* h8300/compile.c : Addition of extern variable h8300_normal_mode
(SP) : Handle normal mode
(bitfrom) : Use normal mode flag to return suitable value
(lvalue) : Use normal mode flag to return command line location
(decode) : Decode instruction correctly for normal mode
(init_pointers) : Initialise memory correctly for normal mode
(sim_resume) : Handle cases for normal mode using h8300_normal_mode flag
(sim_store_register) : Handle 2 byte PC for normal mode
(sim_fetch_register) : Handle 2 byte PC for normal mode
(set_h8300h) : Set normal mode flag as per architechture
(sim_load) : Allocate 64K for normal mode instead of bigger memory
* callback.h (struct host_callback_struct): New members ftruncate
and truncate.
gdb:
sim/common:
* callback.c (os_ftruncate, os_truncate): New functions.
(default_callback): Initialize ftruncate and truncate members.
sim/sh:
* syscall.h (SYS_truncate, SYS_ftruncate): Define.
* interp.c (trap): Add support for SYS_ftruncate and SYS_truncate.
* sim/frv/testutils.inc (or_gr_immed): New macro.
* sim/frv/fp_exception-fr550.cgs: Write insns using
unaligned registers into the program in order to
cause the required exceptions.
* sim/frv/fp_exception.cgs: Ditto.
* sim/frv/regalign.cgs: Ditto.
* sim/frv/fr550: New subdirectory.
* sim/frv/fr400/*.cgs: Add fr550 as appropriate.
* sim/frv/fr500/*.cgs: Add fr550 as appropriate.
* sim/frv/interrupts/*.cgs: Add fr550 as appropriate.
* sim/frv/interrupts/*-fr550.cgs: New test cases for fr550.
* profile.h (update_FR_ptime): New prototype.
(update_FRdouble_ptime): Ditto.
(update_SPR_ptime): Ditto.
(increase_ACC_busy): Ditto.
(enforce_full_acc_latency): Ditto.
(post_wait_for_SPR): Ditto.
* profile.c (update_FR_ptime): Moved here from profile-fr500.c.
(update_FRdouble_ptime): Ditto.
(update_SPR_ptime): New function.
(increase_ACC_busy): Ditto.
(enforce_full_acc_latency): Ditto.
(vliw_wait_for_fdiv_resource): Correct resource name.
(vliw_wait_for_fsqrt_resource): Ditto.
(post_wait_for_SPR): New function.
* profile-fr500.c (frvbf_model_fr500_u_commit): New function.
(frvbf_model_fr500_u_gr2fr): Pass out_FRk as output register to
adjust_float_register_busy.
(frvbf_model_fr500_u_gr_load): Record latency of SPR registers.
(frvbf_model_fr500_u_fr_load): Wait for and record latency of SPR
registers.
(frvbf_model_fr500_u_float_arith): Ditto.
(frvbf_model_fr500_u_float_dual_arith): Ditto.
(frvbf_model_fr500_u_float_div): Ditto.
(frvbf_model_fr500_u_float_sqrt): Ditto.
(frvbf_model_fr500_u_float_convert): Ditto.
(update_FR_ptime): Moved to profile.c
(update_FRdouble_ptime): Moved to profile.c
* profile-fr400.c (update_FR_ptime): Removed. Identical to functions
for other machines.
(update_FRdouble_ptime): Ditto.
* arch.h,cpu.h,sem.c,decode.[ch],model.c,sem.c: Regenerated.
* registers.c (frv_check_spr_read_access): Check for access to
ACC4-ACC63 and ACCG4-ACCG63.
* profile.h (frv-desc.h): #include it.
(spr_busy): New member of FRV_PROFILE_STATE.
(spr_latency): Ditto.
(GNER_FOR_GR): New macro.
(FNER_FOR_FR): New maccro.
(update_SPR_latency): New function.
(vliw_wait_for_SPR): New function.
* profile.c (profile-fr550.h): #include it.
(update_latencies): Update SPR latencies.
(update_target_latencies): Ditto.
(update_SPR_latency): New function.
(vliw_wait_for_SPR): New function.
* profile-fr500.c (frvbf_model_fr500_u_idiv): Record GNER latency.
(frvbf_model_fr500_u_trap): Removed unused variable, ps.
(frvbf_model_fr500_u_check): Ditto.
(frvbf_model_fr500_u_clrgr): New unit modeller for fr500.
(frvbf_model_fr500_u_clrfr): Ditto.
(frvbf_model_fr500_u_spr2gr): Wait for SPR.
(frvbf_model_fr500_u_gr2spr): Ditto.
* frv-sim.h (H_SPR_ACC4): New macro.
(H_SPR_ACCG4): New macro;
(H_SPR_ACC0): Removed.
(H_SPR_ACCG0): Removed.
* arch.h,model.c,sem[ch],decode.[ch]: Regenerated.
* profile.c (slot_names): FM1 was listed twice. Changed first
instance to FM0. Added IALL, FMALL and FMLOW.
(print_parallel): Don't examine slots with no insns.
On behalf of Doug Evans <dje@sebabeach.org>
* Makefile.in (stamp-arch,stamp-cpu): Pass archfile to cgen.
Remove copying of .cpu file to cgen/cpu, no longer needed.
On behalf of Doug Evans <dje@sebabeach.org>
* cgen.sh: New arg archfile.
* Make-common.in (cgen-arch,cgen-cpu,cgen-defs,cgen-decode,
cgen-cpu-decode,cgen-desc): Update call to cgen.sh.
* sim/frv/interrupts/Ipipe-fr400.cgs: New file.
* sim/frv/interrupts/Ipipe-fr500.cgs: New file.
* sim/frv/interrupts/Ipipe.cgs: Remove (replaced by above).
Dave Brolley <brolley@redhat.com>
* frv/: New directory, simulator for the Fujitsu FR-V.
* testsuite/frv-elf/: New directory.
* testsuite/sim/frv/: New directory.
* configure.in: Add frv configury.
* configure: Regenerate.
2003-08-28 Andrew Cagney <cagney@redhat.com>
* dv-glue.c (hw_glue_finish): Change %d to %ld to match sizeof.
* sim-options.c (print_help): Cast the format with specifier to
"int".
Index: mn10300/ChangeLog
2003-08-28 Andrew Cagney <cagney@redhat.com>
* dv-mn103ser.c (do_polling_event): Change type of "serial_reg" to
"long".
(read_status_reg): Cast "serial_reg" to "long".
* dv-mn103tim.c (do_counter_event): Change type of "timer_nr" to
"long".
(do_counter6_event, write_mode_reg, write_tm6md): Ditto.
* sim/sh/gencode.c ( tab[] ): Addition of MAC.L handler and
correction for MAC.W handler
* sim/sh/interp.c ( macl ): New Function. Implementation of
MAC.L handler.
* MAINTAINERS: Andrew Cagney (mips) and Geoff Keating (ppc) drop
maintenance. List igen and sh maintainers. Mention that target
and global maintainers pick up the slack.
the physical address in virtual address.
(struct _sim_cpu): Add memory bank members.
* m68hc11_sim.c (cpu_initialize): Clear memory bank parameters.
* interp.c (sim_hw_configure): Create memory bank according to memory
bank parameters.
(sim_get_bank_parameters): New function to obtain memory bank config
from the symbol table.
(sim_prepare_for_program): Call it to obtain the memory bank parameters.
(sim_open): Call sim_prepare_for_program.
* dv-m68hc11.c (m68hc11cpu_io_write_buffer): Use memory bank parameters
to check if address is within bank window.
(m68hc11cpu_io_read_buffer): Likewise.
(attach_m68hc11_regs): Map the memory bank according to memory bank
parameters.
* cmpw.s: Add test for less-than-zero immediate.
* shll.s: Test for shll reg, reg.
* shlr.s: Test for shlr reg, reg.
* mova.s: Add dozens of new mova tests.
* compile.c (decode): Enhancements for mova.
Initialize cst, reg, and rdisp inside the loop, for each
new instruction. Defer correction of the disp2 values until
later, and then adjust them by the size of the first operand,
rather than the size of the instruction.
(sim_resume): For mova, adjust the size of the second operand
according to the type of the first operand (INDEXB vs. INDEXW).
In cases where there is only one operand, the other two must
both be composed on the fly.
* gencode.c (pshl): Change < to <= (shift by 16 is allowed).
Cast argument of >> to unsigned to prevent sign extension.
(psha): Change < to <= (shift by 32 is allowed).
* gencode.c: A few more fix-ups of refs and defs.
(frchg): Raise SIGILL if in double-precision mode.
(ldtlb): We don't simulate cache, so this is a no-op.
(movsxy_tab): Correct a few bit pattern errors.
* gencode.c (ppi_gensim): For a conditional ppi insn, if the
condition is false, we want to return (not break). A break
will take us to the end of the function where registers will
be updated, whereas the desired outcome is for nothing to change.
* gencode.c (op tab): Some fix-ups of refs and defs.
(ocbi, ocbp): Cache not simulated, but may cause memory fault.
(gensym_caselist): Add default case to switch statement.
(expand_ppi_code): Add default case to switch statement.
Written by matthew green <mrg@redhat.com>, with fixes from Aldy
Hernandez <aldyh@redhat.com>, Jim Wilson <wilson@redhat.com>, and
Nick Clifton <nickc@redhat.com>.
* ppc-instructions: Include altivec.igen and e500.igen.
(model_busy, model_data): Add vr_busy and vscr_busy.
(model_trace_release): Trace vr_busy and vscr_busy.
(model_new_cycle): Update vr_busy and vscr_busy.
(model_make_busy): Update vr_busy and vscr_busy.
* registers.c (register_description): Add Altivec and e500
registers.
* psim.c (psim_read_register, psim_read_register): Handle Altivec
and e500 registers.
* ppc-spr-table (SPEFSCR): Add VRSAVE and SPEFSCR registers.
* configure.in (sim_filter): When *altivec* add "av". When *spe*
or *simd* add e500.
(sim_float): When *altivec* define WITH_ALTIVEC. When *spe* add
WITH_E500.
* configure: Re-generate.
* e500.igen, altivec.igen: New files.
* e500_expression.h, altivec_expression.h: New files.
* idecode_expression.h: Update copyright. Include
"e500_expression.h" and "altivec_expression.h".
* e500_registers.h, altivec_registers.h: New files.
* registers.h: Update copyright. Include "e500_registers.h" and
"altivec_registers.h".
(registers): Add Altivec and e500 specific registers.
* Makefile.in (IDECODE_H): Add "idecode_e500.h" and
"idecode_altivec.h".
(REGISTERS_H): Add "e500_registers.h" and "altivec_registers.h".
(tmp-igen): Add dependencies on altivec.igen and e500.igen .
From matthew green <mrg@redhat.com>:
* sim-fpu.h: Update copyright.
(sim_fpu_fraction, sim_fpu_guard): New prototypes.
* sim-fpu.c: Update copyright.
(sim_fpu_fraction, sim_fpu_guard): New inline functions.
Kazuhiro Inaoka
Hans-Peter Nilsson
Andrew Cagney
Richard Earnshaw
Andreas Schwab
Nick Clifton
Frank Ch. Eigler
DJ Delorie
Corinna Vinschen
Richard Sandiford
Chris Demetriou
Joern Rennecke
Nathanael Nerode
Jim Blandy
Ben Elliston
Alexandre Oliva
Alan Modra
Michael Snyder
Daniel Jacobowitz
Mark Kettenis
Mark Mitchell
Dhananjay Deshpande
Kevin Buettner
Kazu Hirata
Dave Brolley
Shrinivas Atre
Stephane Carrez