* Makefile.in (SIM_EXTRA_CFLAGS): Add -lm.
* armdefs.h (ARMdval, ARMfval): New types.
(ARM_VFP_reg): New union.
(struct ARMul_State): Add VFP_Reg and FPSCR fields.
(VFP_fval, VFP_uword, VFP_sword, VFP_dval, VFP_dword): Accessor
macros for the new VFP_Reg field.
* armemu.c (handle_v6_insn): Add code to handle MOVW, MOVT,
QADD16, QASX, QSAX, QSUB16, QADD8, QSUB8, UADD16, USUB16, UADD8,
USUB8, SEL, REV, REV16, RBIT, BFC, BFI, SBFX and UBFX
instructions.
(handle_VFP_move): New function.
(ARMul_Emulate16): Add checks for newly supported v6
instructions. Add support for VMRS, VMOV and MRC instructions.
(Multiply64): Allow nRdHi == nRm and/or nRdLo == nRm when
operating in v6 mode.
* armemu.h (t_resolved): Define.
* armsupp.c: Include math.h.
(handle_VFP_xfer): New function. Handles VMOV, VSTM, VSTR, VPUSH,
VSTM, VLDM and VPOP instructions.
(ARMul_LDC): Test for co-processor 10 or 11 and pass call to the
new handle_VFP_xfer function.
(ARMul_STC): Likewise.
(handle_VFP_op): New function. Handles VMLA, VMLS, VNMLA, VNMLS,
VNMUL, VMUL, VADD, VSUB, VDIV, VMOV, VABS, VNEG, VSQRT, VCMP,
VCMPE and VCVT instructions.
(ARMul_CDP): Test for co-processor 10 or 11 and pass call to the
new handle_VFP_op function.
* thumbemu.c (tBIT, tBITS, ntBIT, ntBITS): New macros.
(test_cond): New function. Tests a condition and returns non-zero
if the condition has been met.
(handle_IT_block): New function.
(in_IT_block): New function.
(IT_block_allow): New function.
(ThumbExpandImm): New function.
(handle_T2_insn): New function. Handles T2 thumb instructions.
(handle_v6_thumb_insn): Add next_instr and pc parameters.
(ARMul_ThumbDecode): Add support for IT blocks. Add support for
v6 instructions.
* wrapper.c (sim_create_inferior): Detect a thumb address and call
SETT appropriately.
The bfin/msp430 ports already had trace logic set up for reading/writing
cpu registers, albeit using different unrelated levels (core & vpu). Add
a proper register class for these and for other ports.
This helper macro has largely the same behavior as libiberty's lbasename.
There is a slight nuance related to colons, but it's not clear what the
point of that is, and the code implies that it just wants the basename.
Since --trace-debug is for people hacking on the sim sources rather than
people just using the sim, default it to off. This matches the behavior
of other debug knobs we have.
Since we always include the raw syscall number when tracing, also
including it in the name when it's unknown is redundant. Simplify
the code by using a constant string.
The new helpers for walking the maps tested the wrong value for exiting
the for loop. This caused crashes when looking up entries that were not
in the map.
Many ports have the same sim syscall logic, so add some helpers to handle
all the common details. The arches still have to deal with the unpacking
and packing of the syscall arguments, but the rest of the sim<->callback
glue is now shared.
When tracing, we often want to display the human readable name for the
various syscall/errno values. Rather than make each target duplicate
the lookup, extend the existing maps to include the string directly,
and add helper functions to look up the constants.
While most targets are autogenerated (from libgloss), the bfin/cris
targets have custom maps for the Linux ABI which need to be updated
by hand.
The Blackfin port had some TRACE_xxx macros for easily logging trace data.
Use these as a base for common ones that have a simple form and match the
existing sets of helper macros.
The cgen code declares some macros/funcs using the trace_xxx prefix, but
the code isn't generic and only works with cgen targets. This is blocking
the creation of new common trace functions.
Let's blindly add cgen_xxx prefixes to all these symbols. Some already
use this convention to avoid conflicts, so it makes sense to align them.
In the future we might want to move some to the common trace core, but
one thing at a time.
First we convert the ETRACE_P to STRACE_EVENTS_P. This means we move from
using the sim_events.trace storage to the common sim_state_base.trace_data
array. With that deleted, the common trace init code can be simplified so
the sim state works the same as the sim cpu.
This is the only sim that sets up its own WITH_TRACE mask and it conflicts
with the user setting their own list at configure time. Drop it to match
all the other sims.
The syscall path was the only code checking the custom exception state
after recent cleanups. Once we change that to the common engine halt
function, we can delete that state entirely.
This also helps highlight some other dead code that we can cull.
These printf statements are showing "word" objects which are typedefed
from long, so make sure to use l with %x when printing them to avoid
warnings from gcc.
Re-use the existing memory core that handles reads/writes.
The verbose command is converted to the common --verbose flag
since only a few call sites use it now.
In preparation for converting to the common memory framework, the custom
commands get in our way. But when we realize that gdb support has been
dropped for mcore, it makes things a bit easier: the main runner does not
let you run arbitrary commands once simulation starts.
So lets disable watchpoint support until it can be converted to the common
watchpoint logic. There's already an ifdef to let us do that.
We straight up drop support for the dumpmem command (no other sim supports
this, and if it's a feature people want, we can add a common func) and the
clearstats command (not a big deal -- just restart your simulation).
We leave in place the verbose check points as a follow up commit will cut
that over to common logic.
Now that libgloss has a header tracking the syscalls for this arch, we
can update the database to include it for the symbolic constants/maps.
Then we can switch the mcore syscall callbacks over to the common ones.
Since newlib no longer shares the same repo as binutils/gdb, we have to go
searching further afield to locate the sources. We still look at the top
level for newlib, but if that is not found, we also try up one dir outside
of this source tree. It sucks, but better than the status quo (no workie).
Change data ordering in emulated memory from target order (big endian)
to host order. Improves performance and simplifies most memory
operations. Requires some byte twisting during stores on little
endian hosts (intel). Also removed support for little-endian binaries.
Now that we've unified sim-cpu, we can delete the duplicate sim-engine
hooks -- these targets defined these only because they didn't fully
implement the sim-cpu callbacks.
Since every target typedefs this the same way, move it to the common code.
We have to leave Blackfin behind here for now because of inter-dependencies
on types and headers: sim-base.h includes sim-model.h which needs types in
machs.h which needs types in bfim-sim.h which needs SIM_CPU.
Almost every target defines sim_cia the same way -- either using the
address_word type directly, or a type of equivalent size. The only
odd one out is sh64 (who has 32bit address_word and 64bit cia), and
even that case doesn't seem to make sense. We'll put off clean up
though of sh64 and at least set up a sensible default for everyone.
Re-use the existing memory core that handles reads/writes.
This drops support for the dumpmem command, but gdb itself has
support for dumping memory regions.
The verbose command is converted to the common --verbose flag
since only two call sites use it now.
Support for the clearstats command is dropped entirely, but no
other sim really does this, and the same thing can be done by
reloading. If it's important (clearing cycle stats) to someone,
we can add a common function for it.
The CIA_{GET,SET} macros serve the same function as CPU_PC_{GET,SET}
except the latter adds a layer of indirection via the sim state. This
lets models set up different functions at runtime and doesn't reach so
directly into the arch-specific cpu state.
It also doesn't make sense to have two sets of macros that do exactly
the same thing, so lets standardize on the one that gets us more.
Now that all the targets are utilizing CPU_PC_{FETCH,STORE}, and the
cpu state is multicore, and the STATE_CPU defines match, we can move
it all to the common code.
This sets up the sim_state structure and the cpu member to match what we
do in most other sims, and what the common code suggests. This is a step
to unifying on the sim-cpu.o object.
The old run frontend had a --version option, but the new common
sim-options file does not. Restore support for that so we can
get version info out of `run` when using the new frontend.
With sim-hrw.o being built & linked in the common list, some people are
getting linking errors now for these targets. Move the main objects that
provide these functions before the common list to avoid that.
The nrun conversion was slightly incorrect in how it stopped when an
exception occurred. We still set cpu.asregs.exception, but nothing
was checking it anymore. Convert all of that to sim_engine_halt.
To keep things from regressing again, add a basic testsuite too.
Way back in aba6488e0b, a bunch of signal
defines were changed to TARGET_SIGNAL_xxx. For d10v, the transition was
incomplete which lead to sim_stop_reason using the new set but sim_resume
still using the old set. Which meant in some cases, the sim would never
actually stop.
Convert all the remaining SIGxxx defines in here to TARGET_SIGNAL_xxx.
This has the nice side effect of fixing the testsuite.
Now that all targets have been converted to nrun, we can finally punt
this old inconsistent interface.
A few stray references to the old run were sprinkled about; clean them
up in the process.
We leave behind the run(1) man page mostly so that we get it updated for
the new nrun interface.
With newer versions of gcc (5.x), the extern inline we're using with the
cgen-{mem,ops} modules no longer work. Since this code really wants the
gnu inline semantics, use that attribute explicitly.
H.J. Lu