6f2f06bea8
x86: make JumpAbsolute an insn attribute
...
... instead of an operand one: There's only ever one operand here
anyway.
2019-11-14 08:47:03 +01:00
51c8edf68b
x86: fold EsSeg into IsString
...
EsSeg (a per-operand bit) is used with IsString (a per-insn attribute)
only. Extend the attribute to 2 bits, thus allowing to encode
- not a string insn,
- string insn with neither operand requiring use of %es:,
- string insn with 1st operand requiring use of %es:,
- string insn with 2nd operand requiring use of %es:,
which covers all possible cases, allowing to drop EsSeg.
The (transient) need to comment out the OTUnused #define did uncover an
oversight in the earlier OTMax -> OTNum conversion, which is being taken
care of here.
2019-11-12 09:09:31 +01:00
75e5731b8f
x86: introduce operand type "instance"
...
Special register "class" instances can't be combined with one another
(neither in templates nor in register entries), and hence it is not a
good use of resources (memory as well as execution time) to represent
them as individual bits of a bit field.
Furthermore the generalization becoming possible will allow
improvements to the handling of insns accepting only individual
registers as their operands.
2019-11-12 09:07:34 +01:00
f74a630727
x86: convert RegMask and RegBND from bitfield to enumerator
...
This is to further shrink the operand type representation.
2019-11-08 09:06:24 +01:00
3528c362d9
x86: convert RegSIMD and RegMMX from bitfield to enumerator
...
This is to further shrink the operand type representation.
2019-11-08 09:05:36 +01:00
4a5c67ed84
x86: convert Control/Debug/Test from bitfield to enumerator
...
This is to further shrink the operand type representation.
2019-11-08 09:04:53 +01:00
00cee14fba
x86: convert SReg from bitfield to enumerator
...
This is to further shrink the operand type representation.
2019-11-08 09:04:09 +01:00
bab6aec125
x86: introduce operand type "class"
...
Many operand types, in particular the various kinds of registers, can't
be combined with one another (neither in templates nor in register
entries), and hence it is not a good use of resources (memory as well as
execution time) to represent them as individual bits of a bit field.
2019-11-08 09:03:23 +01:00
142861dfd5
x86: support further AMD Zen2 instructions
...
Both RDPRU and MCOMMIT have been publicly documented meanwhile:
https://www.amd.com/system/files/TechDocs/24594.pdf .
2019-11-07 09:29:14 +01:00
dfd6917457
x86: make RegMem an opcode modifier
...
... instead of an operand type bit: It's an insn property, not an
operand one. There's just one actual change to be made to the
templates: Most are now required to have the (unswapped) destination go
into ModR/M.rm, so VMOVD template needs its opcode adjusted accordingly
and its operands swapped. {,V}MOVS{S,D}, otoh, are left alone in this
regard, as otherwise generated code would differ from what we've been
producing so far (which I don't think is wanted).
Take the opportunity and add a missing IgnoreSize to pextrb (leading to
an error in 16-bit mode), and take the liberty to once again drop stray
IgnoreSize attributes from lines changed and neighboring related ones.
2019-07-16 09:31:36 +02:00
21df382b91
x86: fold SReg{2,3}
...
They're the only exception to there generally being no mix of register
kinds possible in an insn operand template, and there being two bits per
operand for their representation is also quite wasteful, considering the
low number of uses. Fold both bits and deal with the little bit of
fallout.
Also take the liberty and drop dead code trying to set REX_B: No segment
register has RegRex set on it.
Additionally I was quite surprised that PUSH/POP with the permitted
segment registers is not covered by the test cases. Add the missing
pieces.
2019-07-16 09:30:29 +02:00
9d3bf266fd
x86: drop Vec_Imm4
...
It is pretty wasteful to have a per-operand flag which is used in
exactly 4 cases. It can be relatively easily replaced, and by doing so
I've actually found some dead code to remove at the same time (there's
no case of ImmExt set at the same time as Vec_Imm4).
2019-07-01 08:38:50 +02:00
2c70385689
x86: correct / adjust debug printing
...
For quite some time we've been using combinations of bits for
specifying various registers in operands and templates. I think it was
Alan who had indicated that likely the debug printing would need
adjustment as a result. Here we go.
Accumulator handling for GPRs gets changed to match that for FPU regs.
For this to work, OPERAND_TYPE_ACC{32,64} get repurposed, with their
original uses replaced by direct checks of the two bits of interest,
which is cheaper than operand_type_equal() invocations.
For SIMD registers nothing similar appears to be needed, as respective
operands get stripped from the (copy of the) template before pt() is
reached.
The type change on pi() is to silence a compiler diagnostic. Arguably
its other parameter could also be const-qualified.
2019-06-25 09:41:33 +02:00
9186c494a3
Enable Intel AVX512_VP2INTERSECT insn
...
This patch enables support for VP2INTERSECT in binutils. Please refer to
https://software.intel.com/sites/default/files/managed/c5/15/architecture-instruction-set-extensions-programming-reference.pdf
for VP2INTERSECT details.
Make check-gas is ok.
gas/
2019-06-04 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
Lili Cui <lili.cui@intel.com>
* config/tc-i386.c (cpu_arch): Add .avx512_vp2intersect.
(cpu_noarch): Likewise.
* doc/c-i386.texi: Document avx512_vp2intersect.
* testsuite/gas/i386/i386.exp: Run vp2intersect tests.
* testsuite/gas/i386/vp2intersect-intel.d: New test.
* testsuite/gas/i386/vp2intersect.d: Likewise.
* testsuite/gas/i386/vp2intersect.s: Likewise.
* testsuite/gas/i386/vp2intersect-inval-bcast.l: Likewise.
* testsuite/gas/i386/vp2intersect-inval-bcast.s: Likewise.
* testsuite/gas/i386/x86-64-vp2intersect-intel.d: Likewise.
* testsuite/gas/i386/x86-64-vp2intersect.d: Likewise.
* testsuite/gas/i386/x86-64-vp2intersect.s: Likewise.
* testsuite/gas/i386/x86-64-vp2intersect-inval-bcast.l: Likewise.
* testsuite/gas/i386/x86-64-vp2intersect-inval-bcast.s: Likewise.
opcodes/
2019-06-04 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
Lili Cui <lili.cui@intel.com>
* i386-dis.c (enum): Add PREFIX_EVEX_0F3868, EVEX_W_0F3868_P_3.
* i386-dis-evex.h (evex_table): Add AVX512_VP2INTERSECT
instructions.
* i386-gen.c (cpu_flag_init): Add CPU_AVX512_VP2INTERSECT_FLAGS,
CPU_ANY_AVX512_VP2INTERSECT_FLAGS.
(cpu_flags): Add CpuAVX512_VP2INTERSECT.
* i386-opc.h (enum): Add CpuAVX512_VP2INTERSECT.
(i386_cpu_flags): Add cpuavx512_vp2intersect.
* i386-opc.tbl: Add AVX512_VP2INTERSECT insns.
* i386-init.h: Regenerated.
* i386-tbl.h: Likewise.
2019-06-04 08:58:31 -07:00
5d79adc4b2
Add support for Intel ENQCMD[S] instructions
...
This patch enables support for ENQCMD[S] in binutils. Please refer to
https://software.intel.com/sites/default/files/managed/c5/15/architecture-instruction-set-extensions-programming-reference.pdf
for ENQCMD[S] details.
Make check-gas is ok.
gas/ChangeLog:
2019-06-04 Xuepeng Guo <xuepeng.guo@intel.com>
Lili Cui <lili.cui@intel.com>
* doc/c-i386.texi: Document enqcmd.
* testsuite/gas/i386/enqcmd-intel.d: New file.
* testsuite/gas/i386/enqcmd-inval.l: Likewise.
* testsuite/gas/i386/enqcmd-inval.s: Likewise.
* testsuite/gas/i386/enqcmd.d: Likewise.
* testsuite/gas/i386/enqcmd.s: Likewise.
* testsuite/gas/i386/x86-64-enqcmd-intel.d: Likewise.
* testsuite/gas/i386/x86-64-enqcmd-inval.l: Likewise.
* testsuite/gas/i386/x86-64-enqcmd-inval.s: Likewise.
* testsuite/gas/i386/x86-64-enqcmd.d: Likewise.
* testsuite/gas/i386/x86-64-enqcmd.s: Likewise.
* testsuite/gas/i386/i386.exp: Run enqcmd-intel, enqcmd-inval,
enqcmd, x86-64-enqcmd-intel, x86-64-enqcmd-inval,
and x86-64-enqcmd.
opcodes/ChangeLog:
2019-06-04 Xuepeng Guo <xuepeng.guo@intel.com>
Lili Cui <lili.cui@intel.com>
* i386-dis.c (enum): Add MOD_0F38F8_PREFIX_1 and
MOD_0F38F8_PREFIX_3.
(prefix_table): New instructions (see prefix above).
(mod_table): New instructions (see prefix above).
* i386-gen.c (cpu_flag_init): Add entries for enqcmd.
(cpu_flags): Add a bitfield for enqmcd.
* i386-init.h: Regenerated.
* i386-opc.h (enum): Add CpuENQCMD.
(i386_cpu_flags): Add a bitfield for cpuenqcmd.
* i386-opc.tbl: Add enqcmd and enqcmds instructions.
* i386-init.h: Regenerated.
* i386-tbl.h: Regenerated.
2019-06-04 08:50:46 -07:00
d6aab7a11b
x86: Support Intel AVX512 BF16
...
Add assembler and disassembler support Intel AVX512 BF16:
https://software.intel.com/en-us/download/intel-architecture-instruction-set-extensions-programming-reference
gas/
2019-04-05 Xuepeng Guo <xuepeng.guo@intel.com>
* config/tc-i386.c (cpu_arch): Add .avx512_bf16.
(cpu_noarch): Add noavx512_bf16.
* doc/c-i386.texi: Document avx512_bf16.
* testsuite/gas/i386/avx512_bf16.d: New file.
* testsuite/gas/i386/avx512_bf16.s: Likewise.
* testsuite/gas/i386/avx512_bf16_vl-inval.l: Likewise.
* testsuite/gas/i386/avx512_bf16_vl-inval.s: Likewise.
* testsuite/gas/i386/avx512_bf16_vl.d: Likewise.
* testsuite/gas/i386/avx512_bf16_vl.s: Likewise.
* testsuite/gas/i386/x86-64-avx512_bf16.d: Likewise.
* testsuite/gas/i386/x86-64-avx512_bf16.s: Likewise.
* testsuite/gas/i386/x86-64-avx512_bf16_vl-inval.l: Likesie.
* testsuite/gas/i386/x86-64-avx512_bf16_vl-inval.s: Likewise.
* testsuite/gas/i386/x86-64-avx512_bf16_vl.d: Likewise.
* testsuite/gas/i386/x86-64-avx512_bf16_vl.s: Likewise.
* testsuite/gas/i386/i386.exp: Add BF16 related tests.
opcodes/
2019-04-05 Xuepeng Guo <xuepeng.guo@intel.com>
* i386-dis-evex.h (evex_table): Updated to support BF16
instructions.
* i386-dis.c (enum): Add EVEX_W_0F3852_P_1, EVEX_W_0F3872_P_1
and EVEX_W_0F3872_P_3.
* i386-gen.c (cpu_flag_init): Add CPU_AVX512_BF16_FLAGS.
(cpu_flags): Add bitfield for CpuAVX512_BF16.
* i386-opc.h (enum): Add CpuAVX512_BF16.
(i386_cpu_flags): Add bitfield for cpuavx512_bf16.
* i386-opc.tbl: Add AVX512 BF16 instructions.
* i386-init.h: Regenerated.
* i386-tbl.h: Likewise.
2019-04-05 11:03:13 -07:00
89199bb5a0
ix86: Disable AVX512F when disabling AVX2
...
Since AVX2 is required for AVX512F, we should disable AVX512F when AVX2
is disabled.
gas/
PR gas/24359
* testsuite/gas/i386/i386.exp: Change optimize-6a, optimize-7,
x86-64-optimize-7a and x86-64-optimize-8 tests to run_list_test.
Remove optimize-6c and x86-64-optimize-7c tests.
* testsuite/gas/i386/noavx-3.l: Updated.
* testsuite/gas/i386/noavx-4.d: Likewise.
* testsuite/gas/i386/noavx-5.d: Likewise.
* testsuite/gas/i386/noavx-3.s: Add AVX512F tests.
* testsuite/gas/i386/noavx-4.s: Remove AVX512F tests.
* testsuite/gas/i386/nosse-5.s: Likewise.
* testsuite/gas/i386/optimize-6a.d: Removed.
* testsuite/gas/i386/optimize-6c.d: Likewise.
* testsuite/gas/i386/optimize-7.d: Likewise.
* testsuite/gas/i386/x86-64-optimize-7a.d: Likewise.
* testsuite/gas/i386/x86-64-optimize-7c.d: Likewise.
* testsuite/gas/i386/x86-64-optimize-8.d: Likewise.
* testsuite/gas/i386/optimize-6a.l: New file.
* testsuite/gas/i386/optimize-6a.s: Likewise.
* testsuite/gas/i386/optimize-7.l: Likewise.
* testsuite/gas/i386/x86-64-optimize-7a.l: Likewise.
* testsuite/gas/i386/x86-64-optimize-7a.s: Likewise.
* testsuite/gas/i386/x86-64-optimize-8.l: Likewise.
opcodes/
PR gas/24359
* i386-gen.c (cpu_flag_init): Add CPU_ANY_AVX512F_FLAGS to
CPU_ANY_AVX2_FLAGS.
* i386-init.h: Regenerated.
2019-03-19 21:08:31 +08:00
827041555a
Update year range in copyright notice of binutils files
2019-01-01 22:06:53 +10:30
d871f3f483
x86: Add CpuCMOV and CpuFXSR
...
There are separate CPUID feature bits for fxsave/fxrstor and cmovCC
instructions. This patch adds CpuCMOV and CpuFXSR to replace Cpu686
on corresponding instructions.
gas/
* config/tc-i386.c (cpu_arch): Add .cmov and .fxsr.
(cpu_noarch): Add nocmov and nofxsr.
* doc/c-i386.texi: Document cmov and fxsr.
opcodes/
* i386-gen.c (cpu_flag_init): Add CpuCMOV and CpuFXSR to
CPU_I686_FLAGS. Add CPU_CMOV_FLAGS, CPU_FXSR_FLAGS,
CPU_ANY_CMOV_FLAGS and CPU_ANY_FXSR_FLAGS.
(cpu_flags): Add CpuCMOV and CpuFXSR.
* i386-opc.tbl: Replace Cpu686 with CpuFXSR on fxsave, fxsave64,
fxrstor and fxrstor64. Replace Cpu686 with CpuCMOV on cmovCC.
* i386-init.h: Regenerated.
* i386-tbl.h: Likewise.
2018-08-11 14:37:32 -07:00
c48dadc9a8
x86: drop "mem" operand type attribute
...
No template specifies this bit, so there's no point recording it in the
templates. Use a flags[] bit instead.
2018-08-03 09:30:02 +02:00
e951d5ca3d
x86: drop CpuVREX
...
It is fully redundant with CpuAVX512F.
2018-07-31 10:52:37 +02:00
2fb5be8dac
x86: drop {,reg16_}inoutportreg variables
...
The checking against reg16_inoutportreg can be had with a simple test of
a bit, and the value setting from inoutportreg can be replaced by using
the actual register's reg_type field.
Note that the so far redundant 2nd instance of OPERAND_TYPE_INOUTPORTREG
is left in place, for its use in type_names[].
2018-07-11 10:28:56 +02:00
a9660a6f40
Add znver2 support.
...
gas/
* config/tc-i386.c (cpu_flag_init): Add CPU_ZNVER2_FLAGS.
* doc/c-i386.texi : Document znver2.
* gas/testsuite/gas/i386/arch-13.s: Updated for znver2.
* gas/testsuite/gas/i386/arch-13.d: Updated.
* gas/testsuite/gas/i386/arch-13-znver1.d: Updated.
* gas/testsuite/gas/i386/arch-13-znver2.d: New file.
* gas/testsuite/gas/i386/x86-64-arch-3.s: Updated for znver2.
* gas/testsuite/gas/i386/x86-64-arch-3.d: Updated.
* gas/testsuite/gas/i386/x86-64-arch-3-znver1.d: Updated.
* gas/testsuite/gas/i386/x86-64-arch-3-znver2.d: New file.
* gas/testsuite/gas/i386/i386.exp: Updated for new test.
opcode/
* i386-gen.c (cpu_flag_init): Add CPU_ZNVER2_FLAGS.
* i386-init.h : Regenerated.
2018-05-30 12:27:35 +05:30
c0a30a9f0a
Enable Intel MOVDIRI, MOVDIR64B instructions
...
gas/
* config/tc-i386.c (cpu_arch): Add .movdir, .movdir64b.
(cpu_noarch): Likewise.
(process_suffix): Add check for register size.
* doc/c-i386.texi: Document movdiri, movdir64b.
* testsuite/gas/i386/i386.exp: Run MOVDIR{I,64B} tests.
* testsuite/gas/i386/movdir-intel.d: New file.
* testsuite/gas/i386/movdir.d: Likewise.
* testsuite/gas/i386/movdir.s: Likewise.
* testsuite/gas/i386/movdir64b-reg.s: Likewise.
* testsuite/gas/i386/movdir64b-reg.l: Likewise.
* testsuite/gas/i386/x86-64-movdir-intel.d: Likewise.
* testsuite/gas/i386/x86-64-movdir.d: Likewise.
* testsuite/gas/i386/x86-64-movdir.s: Likewise.
* testsuite/gas/i386/x86-64-movdir64b-reg.s: Likewise.
* testsuite/gas/i386/x86-64-movdir64b-reg.l: Likewise.
opcodes/
* i386-dis.c (Gva): New.
(enum): Add PREFIX_0F38F8, PREFIX_0F38F9,
MOD_0F38F8_PREFIX_2, MOD_0F38F9_PREFIX_0.
(prefix_table): New instructions (see prefix above).
(mod_table): New instructions (see prefix above).
(OP_G): Handle va_mode.
* i386-gen.c (cpu_flag_init): Add CPU_MOVDIRI_FLAGS,
CPU_MOVDIR64B_FLAGS.
(cpu_flags): Add CpuMOVDIRI and CpuMOVDIR64B.
* i386-opc.h (enum): Add CpuMOVDIRI, CpuMOVDIR64B.
(i386_cpu_flags): Add cpumovdiri and cpumovdir64b.
* i386-opc.tbl: Add movidir{i,64b}.
* i386-init.h: Regenerated.
* i386-tbl.h: Likewise.
2018-05-07 16:57:48 -07:00
aa17843739
Revert "Enable Intel MOVDIRI, MOVDIR64B instructions."
...
This reverts commit a914a7c958
2018-04-27 14:34:13 +02:00
a914a7c958
Enable Intel MOVDIRI, MOVDIR64B instructions.
...
gas/
* config/tc-i386.c (cpu_arch): Add .movdir, .movdir64b.
(cpu_noarch): Likewise.
(process_suffix): Add check for register size.
* doc/c-i386.texi: Document movdiri, movdir64b.
* testsuite/gas/i386/i386.exp: Run MOVDIR{I,64B} tests.
* testsuite/gas/i386/movdir-intel.d: New test.
* testsuite/gas/i386/movdir.d: Likewise.
* testsuite/gas/i386/movdir.s: Likewise.
* testsuite/gas/i386/movdir64b-reg.s: Likewise.
* testsuite/gas/i386/movdir64b-reg.l: Likewise.
* testsuite/gas/i386/x86-64-movdir-intel.d: Likewise.
* testsuite/gas/i386/x86-64-movdir.d: Likewise.
* testsuite/gas/i386/x86-64-movdir.s: Likewise.
* testsuite/gas/i386/x86-64-movdir64b-reg.s: Likewise.
* testsuite/gas/i386/x86-64-movdir64b-reg.l: Likewise.
opcodes/
* i386-dis.c (enum): Add PREFIX_0F38F8, PREFIX_0F38F9.
(prefix_table): New instructions (see prefix above).
Add Gva macro and handling in OP_G.
* i386-gen.c (cpu_flag_init): Add CPU_MOVDIRI_FLAGS,
CPU_MOVDIR64B_FLAGS.
(cpu_flags): Likewise.
(opcode_modifiers): Add AddrPrefixOpReg.
(i386_opcode_modifier): Likewise.
* i386-opc.h (enum): Add CpuMOVDIRI, CpuMOVDIR64B.
(i386_cpu_flags): Likewise.
* i386-opc.tbl: Add movidir{i,64b}.
* i386-init.h: Regenerate.
* i386-tbl.h: Likewise.
2018-04-26 23:34:04 +02:00
59ef5df41e
x86: CpuXSAVE is a prereq for various other features
...
All of AVX, LWP, MPX, and PKU require XSAVE, and hence it as well as
XRSTOR should be enabled when enabling these ISA extensions. Leverage
these implications to shorten some of the cpu_flag_init[] entries.
2018-04-26 08:48:56 +02:00
6e041cf4b0
x86: drop CpuRegMMX, CpuReg[XYZ]MM, and CpuRegMask
...
It's not clear to me why they had been introduced - the respective
comments in opcodes/i386-gen.c are certainly wrong: ymm<N> registers
are very well supported (and necessary) with just AVX512F.
2018-04-26 08:48:01 +02:00
0e0eea7820
x86: x87-related adjustments
...
Neither 287 wrt 8087 nor 387 wrt 287 are proper supersets - in each case
some insns get removed from the ISA (they become NOPs, but code intended
for newer co-processors should not use them).
Furthermore with .no87, ST should not be recognized as a register name.
2018-04-26 08:45:35 +02:00
c48935d75f
Enable Intel CLDEMOTE instruction.
...
gas/
* config/tc-i386.c (cpu_arch): Add .cldemote.
* doc/c-i386.texi: Document cldemote/.cldemote.
* testsuite/gas/i386/cldemote-intel.d: New.
* testsuite/gas/i386/cldemote.d: Likewise.
* testsuite/gas/i386/cldemote.s: Likewise.
* testsuite/gas/i386/i386.exp: Run new tests.
* testsuite/gas/i386/x86-64-cldemote-intel.d: New.
* testsuite/gas/i386/x86-64-cldemote.d: Likewise.
* testsuite/gas/i386/x86-64-cldemote.s: Likewise.
* testsuite/gas/i386/ilp32/x86-64-nops.d: Remove 0x0f1c
NOP encoding that maps to cldemote.
* testsuite/gas/i386/nops.d: Likewise.
* testsuite/gas/i386/nops.s: Likewise.
* testsuite/gas/i386/x86-64-nops.d: Likewise.
* testsuite/gas/i386/x86-64-nops.s: Likewise.
opcode/
* i386-dis.c: Add REG_0F1C_MOD_0, MOD_0F1C_PREFIX_0,
PREFIX_0F1C.
* i386-gen.c (cpu_flag_init): Add CPU_CLDEMOTE_FLAGS,
(cpu_flags): Add CpuCLDEMOTE.
* i386-init.h: Regenerate.
* i386-opc.h (enum): Add CpuCLDEMOTE,
(i386_cpu_flags): Add cpucldemote.
* i386-opc.tbl: Add cldemote.
* i386-tbl.h: Regenerate.
2018-04-17 11:56:34 +02:00
de89d0a34d
Enable Intel WAITPKG instructions.
...
Intel has disclosed a set of new instructions for Tremont processor.
The spec is
https://software.intel.com/en-us/intel-architecture-instruction-set-extensions-programming-reference
This patch enables Intel WAITPKG instructions.
gas/
* config/tc-i386.c (cpu_arch): Add WAITPKG.
(cpu_noarch): Likewise.
* doc/c-i386.texi: Document WAITPKG.
* i386/i386.exp: Run WAITPKG tests.
* testsuite/gas/i386/waitpkg-intel.d: New test.
* testsuite/gas/i386/waitpkg.d: Likewise.
* testsuite/gas/i386/waitpkg.s: Likewise.
* testsuite/gas/i386/x86-64-waitpkg-intel.d: Likewise.
* testsuite/gas/i386/x86-64-waitpkg.d: Likewise.
* testsuite/gas/i386/x86-64-waitpkg.s: Likewise.
opcodes/
* i386-dis.c (enum): Add PREFIX_MOD_0_0FAE_REG_6,
PREFIX_MOD_1_0FAE_REG_6.
(va_mode): New.
(OP_E_register): Use va_mode.
* i386-dis-evex.h (prefix_table):
New instructions (see prefixes above).
* i386-gen.c (cpu_flag_init): Add WAITPKG.
(cpu_flags): Likewise.
* i386-opc.h (enum): Likewise.
(i386_cpu_flags): Likewise.
* i386-opc.tbl: Add umonitor, umwait, tpause.
* i386-init.h: Regenerate.
* i386-tbl.h: Likewise.
2018-04-11 21:37:12 +02:00
be3a8dca2d
Enable Intel PCONFIG instruction.
...
Intel has disclosed a set of new instructions for Icelake processor.
The spec is
https://software.intel.com/sites/default/files/managed/c5/15/architecture-instruction-set-extensions-programming-reference.pdf
This patch enables Intel PCONFIG instruction.
gas/
* config/tc-i386.c (cpu_arch): Add .pconfig.
* doc/c-i386.texi: Document .pconfig.
* testsuite/gas/i386/i386.exp: Add PCONFIG tests.
* testsuite/gas/i386/pconfig-intel.d: New test.
* testsuite/gas/i386/pconfig.d: Likewise.
* testsuite/gas/i386/pconfig.s: Likewise.
* testsuite/gas/i386/x86-64-pconfig-intel.d: Likewise.
* testsuite/gas/i386/x86-64-pconfig.d: Likewise.
* testsuite/gas/i386/x86-64-pconfig.s: Likewise.
opcodes/
* i386-dis.c (enum): Add pconfig.
* i386-gen.c (cpu_flag_init): Add CPU_PCONFIG_FLAGS.
(cpu_flags): Add CpuPCONFIG.
* i386-opc.h (enum): Add CpuPCONFIG.
(i386_cpu_flags): Add cpupconfig.
* i386-opc.tbl: Add PCONFIG instruction.
* i386-init.h: Regenerate.
* i386-tbl.h: Likewise.
2018-01-23 20:09:35 +03:00
3233d7d074
Enable Intel WBNOINVD instruction.
...
Intel has disclosed a set of new instructions for Icelake processor.
The spec is
https://software.intel.com/sites/default/files/managed/c5/15/architecture-instruction-set-extensions-programming-reference.pdf
This patch enables Intel WBNOINVD instruction.
gas/
* config/tc-i386.c (cpu_arch): Add .wbnoinvd.
* doc/c-i386.texi: Document .wbnoinvd.
* testsuite/gas/i386/i386.exp: Add WBNOINVD tests.
* testsuite/gas/i386/wbnoinvd-intel.d: New test.
* testsuite/gas/i386/wbnoinvd.d: Likewise.
* testsuite/gas/i386/wbnoinvd.s: Likewise.
* testsuite/gas/i386/x86-64-wbnoinvd-intel.d: Likewise.
* testsuite/gas/i386/x86-64-wbnoinvd.d: Likewise.
* testsuite/gas/i386/x86-64-wbnoinvd.s: Likewise.
opcodes/
* i386-dis.c (enum): Add PREFIX_0F09.
* i386-gen.c (cpu_flag_init): Add CPU_WBNOINVD_FLAGS.
(cpu_flags): Add CpuWBNOINVD.
* i386-opc.h (enum): Add CpuWBNOINVD.
(i386_cpu_flags): Add cpuwbnoinvd.
* i386-opc.tbl: Add WBNOINVD instruction.
* i386-init.h: Regenerate.
* i386-tbl.h: Likewise.
2018-01-23 20:05:33 +03:00
d777820bf5
Replace CET bit with IBT and SHSTK bits.
...
The latest specification for Intel CET technology defined two
new bits instead of previously used CET bit. These are IBT and
SHSTK bits. The patch replaces CET bit with IBT and SHSTK bits.
gas/
* config/tc-i386.c (cpu_arch): Delete .cet. Add .ibt, .shstk.
(cpu_noarch): Add noibt, noshstk.
(parse_insn): Change cpucet to cpuibt.
* doc/c-i386.texi: Delete .cet. Add .ibt, .shstk.
* testsuite/gas/i386/cet-ibt-inval.l: New test.
* testsuite/gas/i386/cet-ibt-inval.s: Likewise.
* testsuite/gas/i386/cet-shstk-inval.l: Likewise.
* testsuite/gas/i386/cet-shstk-inval.s: Likewise.
* testsuite/gas/i386/x86-64-cet-ibt-inval.l: Likewise.
* testsuite/gas/i386/x86-64-cet-ibt-inval.s: Likewise.
* testsuite/gas/i386/x86-64-cet-shstk-inval.l: Likewise.
* testsuite/gas/i386/x86-64-cet-shstk-inval.s: Likewise.
opcodes/
* i386-gen.c (cpu_flag_init): Delete CPU_CET_FLAGS,
CpuCET. Add CPU_IBT_FLAGS, CPU_SHSTK_FLAGS, CPY_ANY_IBT_FLAGS,
CPU_ANY_SHSTK_FLAGS, CpuIBT, CpuSHSTK.
(cpu_flags): Add CpuIBT, CpuSHSTK.
* i386-opc.h (enum): Add CpuIBT, CpuSHSTK.
(i386_cpu_flags): Add cpuibt, cpushstk.
* i386-opc.tbl: Change CpuCET to CpuSHSTK and CpuIBT.
* i386-init.h: Regenerate.
* i386-tbl.h: Likewise.
2018-01-17 19:48:28 +03:00
219d1afa89
Update year range in copyright notice of binutils files
2018-01-03 17:49:56 +10:30
1b54b8d7e4
x86: fold RegXMM/RegYMM/RegZMM into RegSIMD
...
... qualified by their respective sizes, allowing to drop FirstXmm0 at
the same time.
2017-12-18 09:36:14 +01:00
ca0d63fe07
x86: drop FloatReg and FloatAcc
...
Express them as Reg|Tbyte and Acc|Tbyte respectively.
2017-12-18 09:35:01 +01:00
dc821c5f9a
x86: replace Reg8, Reg16, Reg32, and Reg64
...
Use a combination of a single new Reg bit and Byte, Word, Dword, or
Qword instead.
Besides shrinking the number of operand type bits this has the benefit
of making register handling more similar to accumulator handling (a
generic flag is being accompanied by a "size qualifier"). It requires,
however, to split a few insn templates, as it is no longer correct to
have combinations like Reg32|Reg64|Byte. This slight growth in size will
hopefully be outweighed by this change paving the road for folding a
presumably much larger number of templates later on.
2017-12-18 09:34:00 +01:00
b5014f7af2
x86: drop Vec_Disp8
...
This is fully redundant with Disp8MemShift being non-zero, and hence can
be folded with normal Disp8 handling.
2017-11-30 11:47:38 +01:00
fe4e2a3c92
Fix the master due to bad regenerated files
...
* i386-init.h: Regenerate
* i386-tbl.h: Likewise
2017-10-23 19:58:03 +03:00
8dcf1fadf2
Enable Intel VAES instructions.
...
Intel has disclosed a set of new instructions. The spec is
https://software.intel.com/sites/default/files/managed/c5/15/architecture-instruction-set-extensions-programming-reference.pdf
gas/
* config/tc-i386.c (cpu_arch): Add VAES.
* doc/c-i386.texi: Document VAES.
* testsuite/gas/i386/i386.exp: Run VAES tests.
* testsuite/gas/i386/avx512f_vaes-intel.d: New test.
* testsuite/gas/i386/avx512f_vaes-wig.s: Ditto.
* testsuite/gas/i386/avx512f_vaes-wig1-intel.d: Ditto.
* testsuite/gas/i386/avx512f_vaes-wig1.d: Ditto.
* testsuite/gas/i386/avx512f_vaes.d: Ditto.
* testsuite/gas/i386/avx512f_vaes.s: Ditto.
* testsuite/gas/i386/avx512vl_vaes-intel.d: Ditto.
* testsuite/gas/i386/avx512vl_vaes-wig.s: Ditto.
* testsuite/gas/i386/avx512vl_vaes-wig1-intel.d: Ditto.
* testsuite/gas/i386/avx512vl_vaes-wig1.d: Ditto.
* testsuite/gas/i386/avx512vl_vaes.d: Ditto.
* testsuite/gas/i386/avx512vl_vaes.s: Ditto.
* testsuite/gas/i386/vaes-intel.d: Ditto.
* testsuite/gas/i386/vaes.d: Ditto.
* testsuite/gas/i386/vaes.s: Ditto.
* testsuite/gas/i386/x86-64-avx512f_vaes-intel.d: Ditto.
* testsuite/gas/i386/x86-64-avx512f_vaes-wig.s: Ditto.
* testsuite/gas/i386/x86-64-avx512f_vaes-wig1-intel.d: Ditto.
* testsuite/gas/i386/x86-64-avx512f_vaes-wig1.d: Ditto.
* testsuite/gas/i386/x86-64-avx512f_vaes.d: Ditto.
* testsuite/gas/i386/x86-64-avx512f_vaes.s: Ditto.
* testsuite/gas/i386/x86-64-avx512vl_vaes-intel.d: Ditto.
* testsuite/gas/i386/x86-64-avx512vl_vaes-wig.s: Ditto.
* testsuite/gas/i386/x86-64-avx512vl_vaes-wig1-intel.d: Ditto.
* testsuite/gas/i386/x86-64-avx512vl_vaes-wig1.d: Ditto.
* testsuite/gas/i386/x86-64-avx512vl_vaes.d: Ditto.
* testsuite/gas/i386/x86-64-avx512vl_vaes.s: Ditto.
* testsuite/gas/i386/x86-64-vaes-intel.d: Ditto.
* testsuite/gas/i386/x86-64-vaes.d: Ditto.
* testsuite/gas/i386/x86-64-vaes.s: Ditto.
opcodes/
* i386-dis.c (enum): Add PREFIX_EVEX_0F38DC, PREFIX_EVEX_0F38DD,
PREFIX_EVEX_0F38DE, PREFIX_EVEX_0F38DF.
(enum): Remove VEX_LEN_0F38DC_P_2, VEX_LEN_0F38DD_P_2,
VEX_LEN_0F38DE_P_2, VEX_LEN_0F38DF_P_2.
(vex_len_table): Ditto.
(enum): Remove VEX_W_0F38DC_P_2, VEX_W_0F38DD_P_2,
VEX_W_0F38DE_P_2, VEX_W_0F38DF_P_2.
(vew_w_table): Ditto.
(prefix_table): Adjust instructions (see prefixes above).
* i386-dis-evex.h (evex_table):
Add new instructions (see prefixes above).
* i386-gen.c (cpu_flag_init): Add VAES.
(bitfield_cpu_flags): Ditto.
* i386-opc.h (enum): Ditto.
(i386_cpu_flags): Ditto.
* i386-opc.tbl (vaes{enc,dec}{last,}): New instructions.
* i386-init.h: Regenerate.
* i386-tbl.h: Ditto.
2017-10-23 15:58:18 +03:00
48521003d5
Enable Intel GFNI instructions.
...
Intel has disclosed a set of new instructions. The spec is
https://software.intel.com/sites/default/files/managed/c5/15/architecture-instruction-set-extensions-programming-reference.pdf
gas/
* config/tc-i386.c (cpu_arch): Add .gfni.
* doc/c-i386.texi: Document .gfni.
* testsuite/gas/i386/i386.exp: Add GFNI tests.
* testsuite/gas/i386/avx.s: New GFNI test.
* testsuite/gas/i386/x86-64-avx.s: Likewise.
* testsuite/gas/i386/avx.d: Adjust.
* testsuite/gas/i386/avx-intel.d: Likewise
* testsuite/gas/i386/ilp32/x86-64-avx-intel.d: Likewise.
* testsuite/gas/i386/ilp32/x86-64-avx.d: Likewise.
* testsuite/gas/i386/avx512f_gfni-intel.d: New test.
* testsuite/gas/i386/avx512f_gfni.d: Likewise.
* testsuite/gas/i386/avx512f_gfni.s: Likewise.
* testsuite/gas/i386/avx512vl_gfni-intel.d: Likewise.
* testsuite/gas/i386/avx512vl_gfni.d: Likewise.
* testsuite/gas/i386/avx512vl_gfni.s: Likewise.
* testsuite/gas/i386/gfni-intel.d: Likewise.
* testsuite/gas/i386/gfni.d: Likewise.
* testsuite/gas/i386/gfni.s: Likewise.
* testsuite/gas/i386/x86-64-avx512f_gfni-intel.d: Likewise.
* testsuite/gas/i386/x86-64-avx512f_gfni.d: Likewise.
* testsuite/gas/i386/x86-64-avx512f_gfni.s: Likewise.
* testsuite/gas/i386/x86-64-avx512vl_gfni-intel.d: Likewise.
* testsuite/gas/i386/x86-64-avx512vl_gfni.d: Likewise.
* testsuite/gas/i386/x86-64-avx512vl_gfni.s: Likewise.
* testsuite/gas/i386/x86-64-avx_gfni-intel.d: Likewise.
* testsuite/gas/i386/x86-64-avx_gfni.d: Likewise.
* testsuite/gas/i386/x86-64-avx_gfni.s: Likewise.
* testsuite/gas/i386/x86-64-gfni-intel.d: Likewise.
* testsuite/gas/i386/x86-64-gfni.d: Likewise.
* testsuite/gas/i386/x86-64-gfni.s: Likewise.
opcodes/
* i386-dis.c (enum): Add PREFIX_0F38CF, PREFIX_0F3ACE, PREFIX_0F3ACF,
PREFIX_VEX_0F38CF, PREFIX_VEX_0F3ACE, PREFIX_VEX_0F3ACF,
PREFIX_EVEX_0F38CF, PREFIX_EVEX_0F3ACE, PREFIX_EVEX_0F3ACF.
(enum): Add VEX_W_0F38CF_P_2, VEX_W_0F3ACE_P_2, VEX_W_0F3ACF_P_2,
EVEX_W_0F3ACE_P_2, EVEX_W_0F3ACF_P_2.
(prefix_table): Updated (see prefixes above).
(three_byte_table): Likewise.
(vex_w_table): Likewise.
* i386-dis-evex.h: Likewise.
* i386-gen.c (cpu_flag_init): Add CPU_GFNI_FLAGS, CpuGFNI.
(cpu_flags): Add CpuGFNI.
* i386-opc.h (enum): Add CpuGFNI.
(i386_cpu_flags): Add cpugfni.
* i386-opc.tbl: Add Intel GFNI instructions.
* i386-init.h: Regenerate.
* i386-tbl.h: Likewise.
2017-10-23 15:58:13 +03:00
53467f5707
Enable Intel AVX512_VBMI2 instructions.
...
Intel has disclosed a set of new instructions. The spec is
https://software.intel.com/sites/default/files/managed/c5/15/architecture-instruction-set-extensions-programming-reference.pdf
gas/
* config/tc-i386.c (cpu_arch): Add .avx512_vbmi2.
(cpu_noarch): noavx512_vbmi2.
* doc/c-i386.texi: Document .avx512_vbmi2, noavx512_vbmi2.
* testsuite/gas/i386/i386.exp: Add AVX512_VBMI2 tests.
* testsuite/gas/i386/avx512vbmi2-intel.d: New test.
* testsuite/gas/i386/avx512vbmi2.d: Likewise.
* testsuite/gas/i386/avx512vbmi2.s: Likewise.
* testsuite/gas/i386/avx512vbmi2_vl-intel.d: Likewise.
* testsuite/gas/i386/avx512vbmi2_vl.d: Likewise.
* testsuite/gas/i386/avx512vbmi2_vl.s: Likewise.
* testsuite/gas/i386/x86-64-avx512vbmi2-intel.d: Likewise.
* testsuite/gas/i386/x86-64-avx512vbmi2.d: Likewise.
* testsuite/gas/i386/x86-64-avx512vbmi2.s: Likewise.
* testsuite/gas/i386/x86-64-avx512vbmi2_vl-intel.d: Likewise.
* testsuite/gas/i386/x86-64-avx512vbmi2_vl.d: Likewise.
* testsuite/gas/i386/x86-64-avx512vbmi2_vl.s: Likewise.
opcodes/
* i386-dis.c (enum): Add b_scalar_mode, w_scalar_mode.
Define EXbScalar and EXwScalar for OP_EX.
(enum): Add PREFIX_EVEX_0F3862, PREFIX_EVEX_0F3863,
PREFIX_EVEX_0F3870, PREFIX_EVEX_0F3871, PREFIX_EVEX_0F3872,
PREFIX_EVEX_0F3873, PREFIX_EVEX_0F3A70, PREFIX_EVEX_0F3A71,
PREFIX_EVEX_0F3A72, PREFIX_EVEX_0F3A73.
(enum): Add EVEX_W_0F3862_P_2, EVEX_W_0F3863_P_2,
EVEX_W_0F3870_P_2, EVEX_W_0F3871_P_2, EVEX_W_0F3872_P_2,
EVEX_W_0F3873_P_2, EVEX_W_0F3A70_P_2, EVEX_W_0F3A71_P_2,
EVEX_W_0F3A72_P_2, EVEX_W_0F3A73_P_2.
(intel_operand_size): Handle b_scalar_mode and w_scalar_mode.
(OP_E_memory): Likewise.
* i386-dis-evex.h: Updated.
* i386-gen.c (cpu_flag_init): Add CPU_AVX512_VBMI2,
CPU_ANY_AVX512_VBMI2_FLAGS. Update CPU_ANY_AVX512F_FLAGS.
(cpu_flags): Add CpuAVX512_VBMI2.
* i386-opc.h (enum): Add CpuAVX512_VBMI2.
(i386_cpu_flags): Add cpuavx512_vbmi2.
* i386-opc.tbl: Add Intel AVX512_VBMI2 instructions.
* i386-init.h: Regenerate.
* i386-tbl.h: Likewise.
2017-10-23 15:58:07 +03:00
603555e563
Add support for Intel CET instructions
...
Support Intel Control-flow Enforcement Technology (CET) instructions:
https://software.intel.com/sites/default/files/managed/4d/2a/control-flow-enforcement-technology-preview.pdf
gas/
* config/tc-i386.c (cpu_arch): Add .cet.
* doc/c-i386.texi: Document cet.
* testsuite/gas/i386/cet-intel.d: New file.
* testsuite/gas/i386/cet.d: Likewise.
* testsuite/gas/i386/cet.s: Likewise.
* testsuite/gas/i386/x86-64-cet-intel.d: Likewise.
* testsuite/gas/i386/x86-64-cet.d: Likewise.
* testsuite/gas/i386/x86-64-cet.s: Likewise.
* testsuite/gas/i386/i386.exp: Run Intel CET tests.
opcodes/
* i386-dis.c (REG_0F1E_MOD_3): New enum.
(MOD_0F1E_PREFIX_1): Likewise.
(MOD_0F38F5_PREFIX_2): Likewise.
(MOD_0F38F6_PREFIX_0): Likewise.
(RM_0F1E_MOD_3_REG_7): Likewise.
(PREFIX_MOD_0_0F01_REG_5): Likewise.
(PREFIX_MOD_3_0F01_REG_5_RM_1): Likewise.
(PREFIX_MOD_3_0F01_REG_5_RM_2): Likewise.
(PREFIX_0F1E): Likewise.
(PREFIX_MOD_0_0FAE_REG_5): Likewise.
(PREFIX_0F38F5): Likewise.
(dis386_twobyte): Use PREFIX_0F1E.
(reg_table): Add REG_0F1E_MOD_3.
(prefix_table): Add PREFIX_MOD_0_0F01_REG_5,
PREFIX_MOD_3_0F01_REG_5_RM_1, PREFIX_MOD_3_0F01_REG_5_RM_2,
PREFIX_0F1E, PREFIX_MOD_0_0FAE_REG_5 and PREFIX_0F38F5. Update
PREFIX_0FAE_REG_6 and PREFIX_0F38F6.
(three_byte_table): Use PREFIX_0F38F5.
(mod_table): Use PREFIX_MOD_0_0F01_REG_5, PREFIX_MOD_0_0FAE_REG_5.
Add MOD_0F1E_PREFIX_1, MOD_0F38F5_PREFIX_2, MOD_0F38F6_PREFIX_0.
(rm_table): Add MOD_0F38F5_PREFIX_2, MOD_0F38F6_PREFIX_0,
RM_0F1E_MOD_3_REG_7. Use PREFIX_MOD_3_0F01_REG_5_RM_1 and
PREFIX_MOD_3_0F01_REG_5_RM_2.
* i386-gen.c (cpu_flag_init): Add CPU_CET_FLAGS.
(cpu_flags): Add CpuCET.
* i386-opc.h (CpuCET): New enum.
(CpuUnused): Commented out.
(i386_cpu_flags): Add cpucet.
* i386-opc.tbl: Add Intel CET instructions.
* i386-init.h: Regenerated.
* i386-tbl.h: Likewise.
2017-03-06 15:26:37 -08:00
620214f742
Enable Intel AVX512_VPOPCNTDQ instructions
...
gas/
2017-01-12 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
* config/tc-i386.c (cpu_arch): Add .avx512_vpopcntdq.
(cpu_noarch): Add noavx512_vpopcntdq.
* doc/c-i386.texi: Document avx512_vpopcntdq, noavx512_vpopcntdq.
* testsuite/gas/i386/i386.exp: Run AVX512_VPOPCNTDQ tests.
* testsuite/gas/i386/avx512_vpopcntdqd-intel.d: New file.
* testsuite/gas/i386/avx512_vpopcntdqd.d: Ditto.
* testsuite/gas/i386/avx512_vpopcntdqd.s: Ditto.
* testsuite/gas/i386/x86-64-avx512_vpopcntdqd-intel.d: Ditto.
* testsuite/gas/i386/x86-64-avx512_vpopcntdqd.d: Ditto.
* testsuite/gas/i386/x86-64-avx512_vpopcntdqd.s: Ditto.
opcodes/
2017-01-12 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
* i386-dis.c (enum): Add PREFIX_EVEX_0F3855, EVEX_W_0F3855_P_2.
* i386-dis-evex.h (evex_table): Updated.
* i386-gen.c (cpu_flag_init): Add CPU_AVX512_VPOPCNTDQ_FLAGS,
CPU_ANY_AVX512_VPOPCNTDQ_FLAGS. Update CPU_ANY_AVX512F_FLAGS.
(cpu_flags): Add CpuAVX512_VPOPCNTDQ.
* i386-opc.h (enum): (AVX512_VPOPCNTDQ): New.
(i386_cpu_flags): Add cpuavx512_vpopcntdq.
* i386-opc.tbl: Add Intel AVX512_VPOPCNTDQ instructions.
* i386-init.h: Regenerate.
* i386-tbl.h: Ditto.
2017-01-12 08:44:24 -08:00
2571583aed
Update year range in copyright notice of all files.
2017-01-02 14:08:56 +10:30
47acf0bd9f
Enable Intel AVX512_4VNNIW instructions
...
gas/
* config/tc-i386.c: (cpu_arch) Add .avx512_4vnniw.
(cpu_noarch): Add noavx512_4vnniw.
* doc/c-i386.texi: Document avx512_4vnniw, noavx512_4vnniw.
* testsuite/gas/i386/i386.exp: Run AVX512_4VNNIW tests.
* testsuite/gas/i386/avx512_4vnniwd_vl-intel.d: New test.
* testsuite/gas/i386/avx512_4vnniwd_vl.d: Ditto.
* testsuite/gas/i386/avx512_4vnniwd_vl.s: Ditto.
* testsuite/gas/i386/avx512_4vnniwd-intel.d: Ditto.
* testsuite/gas/i386/avx512_4vnniwd.d: Ditto.
* testsuite/gas/i386/avx512_4vnniwd.s: Ditto.
* testsuite/gas/i386/x86-64-avx512_4vnniwd_vl-intel.d: Ditto.
* testsuite/gas/i386/x86-64-avx512_4vnniwd_vl.d: Ditto.
* testsuite/gas/i386/x86-64-avx512_4vnniwd_vl.s: Ditto.
* testsuite/gas/i386/x86-64-avx512_4vnniwd-intel.d: Ditto.
* testsuite/gas/i386/x86-64-avx512_4vnniwd.d: Ditto.
* testsuite/gas/i386/x86-64-avx512_4vnniwd.s: Ditto.
opcodes/
* i386-dis.c (enum): Add PREFIX_EVEX_0F3852, PREFIX_EVEX_0F3853.
* i386-dis-evex.h (evex_table): Updated.
* i386-gen.c (cpu_flag_init): Add CPU_AVX512_4VNNIW_FLAGS,
CPU_ANY_AVX512_4VNNIW_FLAGS. Update CPU_ANY_AVX512F_FLAGS.
(cpu_flags): Add CpuAVX512_4VNNIW.
* i386-opc.h (enum): (AVX512_4VNNIW): New.
(i386_cpu_flags): Add cpuavx512_4vnniw.
* i386-opc.tbl: Add Intel AVX512_4VNNIW instructions.
* i386-init.h: Regenerate.
* i386-tbl.h: Ditto.
2016-11-02 12:31:25 -07:00
920d2ddccb
Enable Intel AVX512_4FMAPS instructions
...
gas/
* config/tc-i386.c (cpu_arch): Add .avx512_4fmaps.
(cpu_noarch): Add noavx512_4fmaps.
(process_operands): Handle implicit quad group.
* doc/c-i386.texi: Document avx512_4fmaps, noavx512_4fmaps.
* testsuite/gas/i386/i386.exp: Add AVX512_4FMAPS tests.
* testsuite/gas/i386/avx512_4fmaps_vl-intel.d: New test.
* testsuite/gas/i386/avx512_4fmaps_vl.d: Ditto.
* testsuite/gas/i386/avx512_4fmaps_vl.s: Ditto.
* testsuite/gas/i386/avx512_4fmaps-intel.d: Ditto.
* testsuite/gas/i386/avx512_4fmaps.d: Ditto.
* testsuite/gas/i386/avx512_4fmaps.s: Ditto.
* testsuite/gas/i386/avx512_4fmaps-warn.l: Ditto.
* testsuite/gas/i386/avx512_4fmaps-warn.s: Ditto.
* testsuite/gas/i386/avx512_4fmaps_vl-warn.l: Ditto.
* testsuite/gas/i386/avx512_4fmaps_vl-warn.s: Ditto.
* testsuite/gas/i386/x86-64-avx512_4fmaps_vl-intel.d: Ditto.
* testsuite/gas/i386/x86-64-avx512_4fmaps_vl.d: Ditto.
* testsuite/gas/i386/x86-64-avx512_4fmaps_vl.s: Ditto.
* testsuite/gas/i386/x86-64-avx512_4fmaps-intel.d: Ditto.
* testsuite/gas/i386/x86-64-avx512_4fmaps.d: Ditto.
* testsuite/gas/i386/x86-64-avx512_4fmaps.s: Ditto.
* testsuite/gas/i386/x86-64-avx512_4fmaps-warn.l: Ditto.
* testsuite/gas/i386/x86-64-avx512_4fmaps-warn.s: Ditto.
* testsuite/gas/i386/x86-64-avx512_4fmaps_vl-warn.l: Ditto.
* testsuite/gas/i386/x86-64-avx512_4fmaps_vl-warn.s: Ditto.
opcodes/
* i386-dis.c. (enum): Add PREFIX_EVEX_0F389A,
PREFIX_EVEX_0F389B, PREFIX_EVEX_0F38AA, PREFIX_EVEX_0F38AB.
* i386-dis-evex.h (evex_table): Updated.
* i386-gen.c (cpu_flag_init): Add CPU_AVX512_4FMAPS_FLAGS,
CPU_ANY_AVX512_4FMAPS_FLAGS. Update CPU_ANY_AVX512F_FLAGS.
(cpu_flags): Add CpuAVX512_4FMAPS.
(opcode_modifiers): Add ImplicitQuadGroup modifier.
* i386-opc.h (AVX512_4FMAP): New.
(i386_cpu_flags): Add cpuavx512_4fmaps.
(ImplicitQuadGroup): New.
(i386_opcode_modifier): Add implicitquadgroup.
* i386-opc.tbl: Add Intel AVX512_4FMAPS instructions.
* i386-init.h: Regenerate.
* i386-tbl.h: Ditto.
2016-11-02 12:25:34 -07:00
b5cefccad8
X86: Remove pcommit instruction
...
Remove x86 pcommit instruction support, which has been deprecated:
https://software.intel.com/en-us/blogs/2016/09/12/deprecate-pcommit-instruction
gas/
* config/tc-i386.c (cpu_arch): Remove .pcommit.
* doc/c-i386.texi: Likewise.
* testsuite/gas/i386/i386.exp: Remove pcommit tests.
* testsuite/gas/i386/pcommit-intel.d: Removed.
* testsuite/gas/i386/pcommit.d: Likewise.
* testsuite/gas/i386/pcommit.s: Likewise.
* testsuite/gas/i386/x86-64-pcommit-intel.d: Likewise.
* testsuite/gas/i386/x86-64-pcommit.d: Likewise.
* testsuite/gas/i386/x86-64-pcommit.s: Likewise.
opcodes/
* i386-dis.c (PREFIX_RM_0_0FAE_REG_7): Removed.
(prefix_table): Remove the PREFIX_RM_0_0FAE_REG_7 entry.
(rm_table): Update the RM_0FAE_REG_7 entry.
* i386-gen.c (cpu_flag_init): Remove CPU_PCOMMIT_FLAGS.
(cpu_flags): Remove CpuPCOMMIT.
* i386-opc.h (CpuPCOMMIT): Removed.
(i386_cpu_flags): Remove cpupcommit.
* i386-opc.tbl: Remove pcommit.
* i386-init.h: Regenerated.
* i386-tbl.h: Likewise.
2016-10-21 12:16:32 -07:00
5b64d091e9
X86: Allow additional ISAs for IAMCU in assembler
...
Originally only Pentium integer instructions are allowed for IAMCU.
This patch removes such a restriction. For example, 387 and SSE2
instructions can be enabled by passing "-march=iamcu+sse2+387" to
assembler.
gas/
* config/tc-i386.c (valid_iamcu_cpu_flags): Removed.
(set_cpu_arch): Updated.
(md_parse_option): Likewise.
* testsuite/gas/i386/i386.exp: Run iamcu-4 and iamcu-5. Remove
iamcu-inval-2 and iamcu-inval-3.
* testsuite/gas/i386/iamcu-4.d: New file.
* testsuite/gas/i386/iamcu-4.s: Likewise.
* testsuite/gas/i386/iamcu-5.d: Likewise.
* testsuite/gas/i386/iamcu-5.s: Likewise.
* testsuite/gas/i386/iamcu-inval-2.l: Removed.
* testsuite/gas/i386/iamcu-inval-2.s: Likewise.
* testsuite/gas/i386/iamcu-inval-3.l: Likewise.
* testsuite/gas/i386/iamcu-inval-3.s: Likewise.
opcodes/
* i386-gen.c (cpu_flag_init): Remove CPU_IAMCU_COMPAT_FLAGS.
* i386-init.h: Regenerated.
2016-09-07 09:22:19 -07:00
Jan Beulich
Jan Beulich
H.J. Lu
Xuepeng Guo
Alan Modra
Amit Pawar
Igor Tsimbalist