#1- Check that the warning is emitted.
#2- Avoid overriding INTERNAL_GDBFLAGS, as per documentated in
gdb/testsuite/README:
~~~
The testsuite does not override a value provided by the user.
~~~
We don't actually need to tweak INTERNAL_GDBFLAGS, we just need to
append out -data-directory to GDBFLAGS, because each passed
-data-directory option leads to a call to the warning:
$ ./gdb -data-directory=foo -data-directory=bar
Warning: foo: No such file or directory.
Warning: bar: No such file or directory.
[...]
gdb/ChangeLog
2018-11-19 Pedro Alves <palves@redhat.com>
* gdb.base/warning.exp: Don't override INTERNAL_FLAGS. Use
gdb_spawn_with_cmdline_opts instead of gdb_start. Check that we
see the expected warning.
PR build/23814 points out that ia64-linux-nat.c will not compile any
more. This patch fixes the problem. Thanks to Andreas Schwab for
trying the patch.
gdb/ChangeLog
2018-11-18 Tom Tromey <tom@tromey.com>
PR build/23814:
* target-delegates.c: Rebuild.
* ia64-linux-nat.c (class ia64_linux_nat_target)
<have_steppable_watchpoint>: Use override. Return true, not 1.
(ia64_linux_nat_target::can_use_hw_breakpoint): Rename. Remove
"self" argument.
(ia64_linux_nat_target::low_new_thread): Rename.
(class ia64_linux_nat_target) <read_description>: Don't declare.
* target.h (struct target_ops) <have_steppable_watchpoint>: Return
bool.
The following will segfault on aarch64 if foo is in another object,
was compiled as c++ and has no debug symbols:
(gdb) p (int)foo()
This is because aarch64_push_dummy_call determines the return type
of the function and then does not check for null pointer.
A null pointer for the return type means the call has no debug
information. For the code to get here, then the call must have
been cast, otherwise we'd error out sooner. In the case of a
no-debug-info call cast, the return type is the type the user
had cast the call to, but we do not have that information
available here.
However, aarch64_push_dummy_call only requires the return type in
order to calculate lang_struct_return. This information is available
in the return_method enum. The fix is to simply use this instead.
Adds testcase to check calls across objects, with all combinations
of c, c++, debug and no debug.
gdb/ChangeLog:
PR gdb/22736:
* aarch64-tdep.c (aarch64_push_dummy_call): Remove
lang_struct_return code.
gdb/testsuite/ChangeLog:
PR gdb/22736:
* gdb.cp/infcall-nodebug-lib.c: New test.
* gdb.cp/infcall-nodebug-main.c: New test.
* gdb.cp/infcall-nodebug.exp: New file.
In call_function_by_hand_dummy, struct_return and hidden_first_param_p
are used to represent a single concept. Replace with an enum.
gdb/ChangeLog:
* gdbarch.sh (enum function_call_return_method): Add enum.
* gdbarch.h: Regenerate.
* infcall.c (call_function_by_hand_dummy): Replace vars with enum.
Now that copy_bitwise has been made public, and considering that
its implementation could move to a different file again in the future,
this patch moves its unittest to its own file in gdb/unittests.
gdb/ChangeLog:
* unittests/copy_bitwise-selftests.c: New file.
* utils.c (selftests::bits_to_str, selftests::check_copy_bitwise)
(selftests::copy_bitwise_tests): Delete, moving this code to
unittests/copy_bitwise-selftests.c instead.
(_initialize_utils): Do not register copy_bitwise tests.
* Makefile.in (SUBDIR_UNITTESTS_SRCS): Add
unittests/copy_bitwise-selftests.c.
Tested on x86_64-linux using the official testsuite, but also by
verifying that "maintenance selftests" still runs the copy_bitwise
tests.
This patch deletes ada-lang.c's move_bits function entirely, and
replaces all calls to it by calls to copy_bitwise instead. Because
the latter function was declared locally inside dwarf2loc.c, this
patch also move the function to a common area, and makes it non-static.
gdb/ChangeLog:
* ada-lang.c (move_bits): Delete. Update all callers to use
copy_bitwise instead.
* dwarf2loc.c (copy_bitwise, bits_to_str::bits_to_str)
(selftests::check_copy_bitwise, selftests::copy_bitwise_tests):
Move from here to utils.c.
(_initialize_dwarf2loc): Remove call to register copy_bitwise
selftests.
* utils.h (copy_bitwise): Add declaration.
* utils.c (copy_bitwise, bits_to_str::bits_to_str)
(selftests::check_copy_bitwise, selftests::copy_bitwise_tests):
Moved here from dwarf2loc.c.
(_initialize_utils): Register copy_bitwise selftests.
Tested on x86_64-linux, no regression. Also tested using AdaCore's
testsuite on a collection of small endian and big endian platforms.
For riscv64-linux target, second half of fix for
FAIL: gdb.base/gnu_vector.exp: call add_various_floatvecs
Unnamed arguments with 2*XLEN alignment are passed in aligned register pairs.
gdb/
* riscv-tdep.c (struct riscv_arg_info): New field is_unnamed.
(riscv_call_arg_scalar_int): If unnamed arg with twice xlen alignment,
then increment next_regnum if odd.
(riscv_arg_location): New arg is_unnamed. Set ainfo->is_unnamed.
(riscv_push_dummy_call): New local ftype. Call check_typedef to set
function type. Pass new arg to riscv_arg_location based on function
type.
(riscv_return_value): Pass new arg to riscv_arg_location.
For riscv64-linux target, first half of fix for
FAIL: gdb.base/gnu_vector.exp: call add_various_floatvecs
GCC gives vectors natural aligment based on total size, not element size,
bounded by the maximum supported type alignment.
gdb/
* riscv-tdep.c (BIGGEST_ALIGNMENT): New.
(riscv_type_alignment) <TYPE_CODE_ARRAY>: If TYPE_VECTOR, return min
of TYPE_LENGTH and BIGGEST_ALIGNMENT.
For riscv64-linux target, fixes
FAIL: gdb.base/gnu_vector.exp: call add_many_charvecs
Ensure that stack slots are always the same alignment as XLEN by rounding
up arg align to xlen.
gdb/
* riscv-tdep.c (riscv_call_arg_scalar_int): Use std::min when
setting len. New local align, set to max of arg align and xlen,
and pass to first riscv_assign_stack_location call.
The decoding of the CRC operation in alu instructions was using bits
from the instruction word directly, instead of srcA which would be
different if the swap bit was set.
Signed-off-by: Francois H. Theron <francois.theron@netronome.com>
Glibc commit:
commit a15529fda8d132621328c3fe32997a3d9c55aef4
Author: H.J. Lu <hjl.tools@gmail.com>
Date: Mon May 14 09:23:55 2018 -0700
i386: Replace PREINIT_FUNCTION@PLT with *%eax in call
Since we have loaded address of PREINIT_FUNCTION into %eax, we can
avoid extra branch to PLT slot.
changed __gmon_start__ relocations in crt1.o from
00000015 0000092b R_386_GOT32X 00000000 __gmon_start__
0000001e 00000904 R_386_PLT32 00000000 __gmon_start__
to
00000015 00000a2b R_386_GOT32X 00000000 __gmon_start__
As the result, .plt.sec section may be generated instead of .plt.got
section, depending on __gmon_start__ relocations.
* testsuite/ld-i386/plt-main-ibt.dd: Accept both .plt.got and
.plt.sec sections.
Add completer to various commands that accept skip numbers:
- skip enable
- skip disable
- skip delete
- info skip
These commands also accept ranges, the completer works for that but is
not very smart. It will suggest invalid ranges, for example when doing
"2-<TAB>" it will suggest "1", which would not result in a valid range.
Also, it will keep suggesting when doing "1-2-<TAB>", even though it's
an invalid syntax.
A future idea would be to make a re-usable and well-tested completer for
numbers and ranges. I think it could at least be re-used for breakpoint
and thread numbers (for example with the "enable breakpoints" command).
gdb/ChangeLog:
* skip.c (complete_skip_number): New function.
(_initialize_step_skip): Add completers to some skip commands.
gdb/testsuite/ChangeLog:
* gdb.base/skip.exp: Add standard_testfile. Add "skip delete"
completer tests.
This patch is part of the patch series to add support for ARMv8.5-A
Memory Tagging Extensions which is an optional extension to
ARMv8.5-A and is enabled using the +memtag command line option.
This patch adds all the data cache instructions that are part of this
extension:
- DC IGVAC, Xt
- DC IGSW, Xt
- DC CGSW, Xt
- DC CIGSW, Xt
- DC CGVAC, Xt
- DC CGVAP, Xt
- DC CGVADP, Xt
- DC CIGVAC, Xt
- DC GVA, Xt
- DC IGDVAC, Xt
- DC IGDSW, Xt
- DC CGDSW, Xt
- DC CIGDSW, Xt
- DC CGDVAC, Xt
- DC CGDVAP, Xt
- DC CGDVADP, Xt
- DC CIGDVAC, Xt
- DC GZVA, Xt
*** opcodes/ChangeLog ***
2018-11-12 Sudakshina Das <sudi.das@arm.com>
* aarch64-opc.c (aarch64_sys_regs_dc): New entries for
IGVAC, IGSW, CGSW, CIGSW, CGVAC, CGVAP, CGVADP, CIGVAC, GVA,
IGDVAC, IGDSW, CGDSW, CIGDSW, CGDVAC, CGDVAP, CGDVADP,
CIGDVAC and GZVA.
(aarch64_sys_ins_reg_supported_p): New check for above.
*** gas/ChangeLog ***
2018-11-12 Sudakshina Das <sudi.das@arm.com>
* testsuite/gas/aarch64/sysreg-4.s: Test IGVAC, IGSW,
CGSW, CIGSW, CGVAC, CGVAP, CGVADP, CIGVAC, GVA,
IGDVAC, IGDSW, CGDSW, CIGDSW, CGDVAC, CGDVAP, CGDVADP,
CIGDVAC and GZVA with DC.
* testsuite/gas/aarch64/sysreg-4.d: Likewise.
* testsuite/gas/aarch64/illegal-sysreg-4.l: Likewise.
This patch is part of the patch series to add support for ARMv8.5-A
Memory Tagging Extensions which is an optional extension to
ARMv8.5-A and is enabled using the +memtag command line option.
This patch adds all the system registers that are part of this
extension and are accessible via the MRS/MSR instructions:
- TCO
- TFSRE0_SL1
- TFSR_EL1
- TFSR_EL2
- TFSR_EL3
- TFSR_EL12
- RGSR_EL1
- GCR_EL1
TCO is also accessible with the MSR(immediate) instruction.
*** opcodes/ChangeLog ***
2018-11-12 Sudakshina Das <sudi.das@arm.com>
* aarch64-opc.c (aarch64_sys_regs): New entries for TCO,
TFSRE0_SL1, TFSR_EL1, TFSR_EL2, TFSR_EL3, TFSR_EL12,
RGSR_EL1 and GCR_EL1.
(aarch64_sys_reg_supported_p): New check for above.
(aarch64_pstatefields): New entry for TCO.
(aarch64_pstatefield_supported_p): New check for above.
*** gas/ChangeLog ***
2018-11-12 Sudakshina Das <sudi.das@arm.com>
* testsuite/gas/aarch64/sysreg-4.s: Test TCO, TFSRE0_SL1,
TFSR_EL1, TFSR_EL2, TFSR_EL3, TFSR_EL12, RGSR_EL1 and
GCR_EL1 MSR and MRS.
* testsuite/gas/aarch64/sysreg-4.d: Likewise.
* testsuite/gas/aarch64/illegal-sysreg-4.l: Likewise.
This patch is part of the patch series to add support for ARMv8.5-A
Memory Tagging Extensions which is an optional extension to
ARMv8.5-A and is enabled using the +memtag command line option.
This patch add support to the Bulk Allocation Tag instructions from
MTE. These are the following instructions added in this patch:
- LDGV <Xt>, [<Xn|SP>]!
- STGV <Xt>, [<Xn|SP>]!
This needed a new kind of operand for the new addressing [<Xn|SP>]!
since this has no offset and only takes a pre-indexed version.
Hence AARCH64_OPND_ADDR_SIMPLE_2 and ldtdgv_indexed are introduced.
(AARCH64_OPND_ADDR_SIMPLE fulfilled the no offset criteria but does
not allow writeback). We also needed new encoding and decoding
functions to be able to do the same.
where
<Xt> : Is the 64-bit destination GPR.
<Xn|SP> : Is the 64-bit first source GPR or Stack pointer.
*** include/ChangeLog ***
2018-11-12 Sudakshina Das <sudi.das@arm.com>
* opcode/aarch64.h (aarch64_opnd): Add AARCH64_OPND_ADDR_SIMPLE_2.
(aarch64_insn_class): Add ldstgv_indexed.
*** opcodes/ChangeLog ***
2018-11-12 Sudakshina Das <sudi.das@arm.com>
* aarch64-asm.c (aarch64_ins_addr_simple_2): New.
* aarch64-asm.h (ins_addr_simple_2): Declare the above.
* aarch64-dis.c (aarch64_ext_addr_simple_2): New.
* aarch64-dis.h (ext_addr_simple_2): Declare the above.
* aarch64-opc.c (operand_general_constraint_met_p): Add case for
AARCH64_OPND_ADDR_SIMPLE_2 and ldstgv_indexed.
(aarch64_print_operand): Add case for AARCH64_OPND_ADDR_SIMPLE_2.
* aarch64-tbl.h (aarch64_opcode_table): Add stgv and ldgv.
(AARCH64_OPERANDS): Define ADDR_SIMPLE_2.
* aarch64-asm-2.c: Regenerated.
* aarch64-dis-2.c: Regenerated.
* aarch64-opc-2.c: Regenerated.
*** gas/ChangeLog ***
2018-11-12 Sudakshina Das <sudi.das@arm.com>
* config/tc-aarch64.c (parse_operands): Add switch case for
AARCH64_OPND_ADDR_SIMPLE_2 and allow [base]! for it.
(warn_unpredictable_ldst): Exempt ldstgv_indexed for ldgv.
* testsuite/gas/aarch64/armv8_5-a-memtag.s: Add tests for ldgv and stgv.
* testsuite/gas/aarch64/armv8_5-a-memtag.d: Likewise.
* testsuite/gas/aarch64/illegal-memtag.s: Likewise.
* testsuite/gas/aarch64/illegal-memtag.l: Likewise.
This patch is part of the patch series to add support for ARMv8.5-A
Memory Tagging Extensions which is an optional extension to
ARMv8.5-A and is enabled using the +memtag command line option.
This patch add support to the Tag Getting instruction from Memory Tagging
Extension.
- LDG <Xt>, [<Xn|SP>, #<simm>]
where
<Xt> : Is the 64-bit destination GPR.
<Xn|SP> : Is the 64-bit first source GPR or Stack pointer.
<simm> : Is the optional signed immediate offset, a multiple of 16
in the range of -4096 and 4080, defaulting to 0.
*** opcodes/ChangeLog ***
2018-11-12 Sudakshina Das <sudi.das@arm.com>
* aarch64-tbl.h (QL_LDG): New.
(aarch64_opcode_table): Add ldg.
* aarch64-asm-2.c: Regenerated.
* aarch64-dis-2.c: Regenerated.
* aarch64-opc-2.c: Regenerated.
*** gas/ChangeLog ***
2018-11-12 Sudakshina Das <sudi.das@arm.com>
* testsuite/gas/aarch64/armv8_5-a-memtag.s: Add tests for ldg.
* testsuite/gas/aarch64/armv8_5-a-memtag.d: Likewise.
* testsuite/gas/aarch64/illegal-memtag.s: Likewise.
* testsuite/gas/aarch64/illegal-memtag.l: Likewise.
This patch is part of the patch series to add support for ARMv8.5-A
Memory Tagging Extensions which is an optional extension to
ARMv8.5-A and is enabled using the +memtag command line option.
This patch add support to the Tag setting instructions from
MTE which consists of the following instructions:
- STG [<Xn|SP>, #<simm>]
- STG [<Xn|SP>, #<simm>]!
- STG [<Xn|SP>], #<simm>
- STZG [<Xn|SP>, #<simm>]
- STZG [<Xn|SP>, #<simm>]!
- STZG [<Xn|SP>], #<simm>
- ST2G [<Xn|SP>, #<simm>]
- ST2G [<Xn|SP>, #<simm>]!
- ST2G [<Xn|SP>], #<simm>
- STZ2G [<Xn|SP>, #<simm>]
- STZ2G [<Xn|SP>, #<simm>]!
- STZ2G [<Xn|SP>], #<simm>
- STGP <Xt>, <Xt2>, [<Xn|SP>, #<imm>]
- STGP <Xt>, <Xt2>, [<Xn|SP>, #<imm>]!
- STGP <Xt>, <Xt2>, [<Xn|SP>], #<imm>
where
<Xn|SP> : Is the 64-bit GPR or Stack pointer.
<simm> : Is the optional signed immediate offset, a multiple of 16
in the range -4096 to 4080, defaulting to 0.
*** include/ChangeLog ***
2018-11-12 Sudakshina Das <sudi.das@arm.com>
* opcode/aarch64.h (aarch64_opnd): Add AARCH64_OPND_ADDR_SIMM11
and AARCH64_OPND_ADDR_SIMM13.
(aarch64_opnd_qualifier): Add new AARCH64_OPND_QLF_imm_tag.
*** opcodes/ChangeLog ***
2018-11-12 Sudakshina Das <sudi.das@arm.com>
* aarch64-opc.c (aarch64_opnd_qualifiers): Add new data
for AARCH64_OPND_QLF_imm_tag.
(operand_general_constraint_met_p): Add case for
AARCH64_OPND_ADDR_SIMM11 and AARCH64_OPND_ADDR_SIMM13.
(aarch64_print_operand): Likewise.
* aarch64-tbl.h (QL_LDST_AT, QL_STGP): New.
(aarch64_opcode_table): Add stg, stzg, st2g, stz2g and stgp
for both offset and pre/post indexed versions.
(AARCH64_OPERANDS): Define ADDR_SIMM11 and ADDR_SIMM13.
* aarch64-asm-2.c: Regenerated.
* aarch64-dis-2.c: Regenerated.
* aarch64-opc-2.c: Regenerated.
*** gas/ChangeLog ***
2018-11-12 Sudakshina Das <sudi.das@arm.com>
* config/tc-aarch64.c (parse_operands): Add switch case for
AARCH64_OPND_ADDR_SIMM11 and AARCH64_OPND_ADDR_SIMM13.
(fix_insn): Likewise.
(warn_unpredictable_ldst): Exempt STGP.
* testsuite/gas/aarch64/armv8_5-a-memtag.s: Add tests for stg, st2g,
stzg, stz2g and stgp.
* testsuite/gas/aarch64/armv8_5-a-memtag.d: Likewise.
* testsuite/gas/aarch64/illegal-memtag.s: Likewise.
* testsuite/gas/aarch64/illegal-memtag.l: Likewise.
This patch is part of the patch series to add support for ARMv8.5-A
Memory Tagging Extensions which is an optional extension to
ARMv8.5-A and is enabled using the +memtag command line option.
This patch add support to the Pointer Arithmetic instructions from
MTE. These are the following instructions added in this patch:
- SUBP <Xd>, <Xn|SP>, <Xm|SP>
- SUBPS <Xd>, <Xn|SP>, <Xm|SP>
- CMPP <Xn|SP>, <Xm|SP>
where CMPP is an alias to SUBPS XZR, <Xn|SP>, <Xm|SP>
where
<Xd> : Is the 64-bit destination GPR.
<Xn|SP> : Is the 64-bit first source GPR or Stack pointer.
<Xm|SP> : Is the 64-bit second source GPR or Stack pointer.
*** opcodes/ChangeLog ***
2018-11-12 Sudakshina Das <sudi.das@arm.com>
* aarch64-tbl.h (aarch64_opcode_table): Add subp, subps and cmpp.
* aarch64-asm-2.c: Regenerated.
* aarch64-dis-2.c: Regenerated.
* aarch64-opc-2.c: Regenerated.
*** gas/ChangeLog ***
2018-11-12 Sudakshina Das <sudi.das@arm.com>
* testsuite/gas/aarch64/armv8_5-a-memtag.s: Add tests for subp,
subps and cmpp.
* testsuite/gas/aarch64/armv8_5-a-memtag.d: Likewise.
* testsuite/gas/aarch64/illegal-memtag.s: Likewise.
* testsuite/gas/aarch64/illegal-memtag.l: Likewise.
This patch is part of the patch series to add support for ARMv8.5-A
Memory Tagging Extensions which is an optional extension to
ARMv8.5-A and is enabled using the +memtag command line option.
This patch add support to the Tag generation instructions from
MTE. These are the following instructions added in this patch:
- IRG <Xd|SP>, <Xn|SP>{, Xm}
- ADDG <Xd|SP>, <Xn|SP>, #<uimm1>. #<uimm2>
- SUBG <Xd|SP>, <Xn|SP>, #<uimm1>. #<uimm2>
- GMI <Xd>, <Xn|SP>, <Xm>
where
<Xd|SP> : Is the 64-bit destination GPR or Stack pointer.
<Xn|SP> : Is the 64-bit source GPR or Stack pointer.
<uimm6> : Is the unsigned immediate, a multiple of 16
in the range 0 to 1008.
<uimm4> : Is the unsigned immediate, in the range 0 to 15.
*** include/ChangeLog ***
2018-11-12 Sudakshina Das <sudi.das@arm.com>
* opcode/aarch64.h (aarch64_opnd): Add
AARCH64_OPND_UIMM4_ADDG and AARCH64_OPND_UIMM10 as new enums.
*** opcodes/ChangeLog ***
2018-11-12 Sudakshina Das <sudi.das@arm.com>
* aarch64-opc.h (aarch64_field_kind): New FLD_imm4_3.
(OPD_F_SHIFT_BY_4, operand_need_shift_by_four): New.
* aarch64-opc.c (fields): Add entry for imm4_3.
(operand_general_constraint_met_p): Add cases for
AARCH64_OPND_UIMM4_ADDG and AARCH64_OPND_UIMM10.
(aarch64_print_operand): Likewise.
* aarch64-tbl.h (QL_ADDG): New.
(aarch64_opcode_table): Add addg, subg, irg and gmi.
(AARCH64_OPERANDS): Define UIMM4_ADDG and UIMM10.
* aarch64-asm.c (aarch64_ins_imm): Add case for
operand_need_shift_by_four.
* aarch64-asm-2.c: Regenerated.
* aarch64-dis-2.c: Regenerated.
* aarch64-opc-2.c: Regenerated.
*** gas/ChangeLog ***
2018-11-12 Sudakshina Das <sudi.das@arm.com>
* config/tc-aarch64.c (parse_operands): Add switch case for
AARCH64_OPND_UIMM4_ADDG and AARCH64_OPND_UIMM10.
* testsuite/gas/aarch64/armv8_5-a-memtag.s: New.
* testsuite/gas/aarch64/armv8_5-a-memtag.d: Likewise.
* testsuite/gas/aarch64/illegal-memtag.s: Likewise.
* testsuite/gas/aarch64/illegal-memtag.l: Likewise.
* testsuite/gas/aarch64/illegal-memtag.d: Likewise.
This patch is part of the patch series to add support for ARMv8.5-A
Memory Tagging Extensions. Memory Tagging Extension is an optional extension to
ARMv8.5-A and is enabled using the +memtag command line option.
This patch adds the new command line option and the new feature macros.
*** include/ChangeLog ***
2018-11-12 Sudakshina Das <sudi.das@arm.com>
* opcode/aarch64.h (AARCH64_FEATURE_MEMTAG): New.
*** opcodes/ChangeLog ***
2018-11-12 Sudakshina Das <sudi.das@arm.com>
* aarch64-tbl.h (aarch64_feature_memtag): New.
(MEMTAG, MEMTAG_INSN): New.
*** gas/ChangeLog ***
2018-11-12 Sudakshina Das <sudi.das@arm.com>
* config/tc-aarch64.c (aarch64_features): Add "memtag"
as a new option.
* doc/c-aarch64.texi: Document the same.
This removes the VEC from remote_g_packet_data, replacing it with a
std::vector. This is a bit odd in that this object is never
destroyed, and is obstack-allocated. I believe a gdbarch is never
destroyed, so this seemed ok.
Tested by the buildbot.
gdb/ChangeLog
2018-11-09 Tom Tromey <tom@tromey.com>
* remote.c (remote_g_packet_guess_s): Remove typedef and DEF_VEC.
(struct remote_g_packet_data): Derive from allocate_on_obstack.
<guesses>: Now a std::vector.
(remote_g_packet_data_init, register_remote_g_packet_guess):
Update.
(remote_read_description_p): Update. Return bool.
(remote_target::read_description): Update.
(struct remote_g_packet_guess): Add constructor.
Use a ssize_t helper variable for the number of bytes to shrink the
msymbols obstack rather than relying on unsigned overflow to shrink
the size of the obstack.
gdb/ChangeLog:
* minsyms.c (minimal_symbol_reader::install): Fix unsigned
overflow.
As suggested in
https://sourceware.org/ml/gdb-patches/2018-10/msg00510.html, this
patch changes the documentation for the VSX tdesc feature to make it
clear that the altivec and FPU features are requirements.
gdb/doc/ChangeLog:
2018-11-09 Pedro Franco de Carvalho <pedromfc@linux.ibm.com>
* gdb.texinfo (PowerPC Features): Document the altivec and fpu
requirements for the org.gnu.gdb.power.vsx feature.
Added warning for static TLS reloc.
Fixed issue related to TLS and partial static linking of libraries:
This issue was detected when throwing exceptions in C++ while linking with
-static-libstdc++.
TLS relocation from the libstdc++ wasn't being patched as local now that it was
static linked with the executable.
Fix for TLS with static and pie. Problem introduced by earlier patch:
Fixes the following glibc tests:
- elf/tst-tls1-static
bfd/
xxxx-xx-xx Cupertino Miranda <cmiranda@synopsys.com>
* arc-got.h (arc_got_entry_type_for_reloc): Changed to
correct static TLS relocs.
* elf32-arc.c (elf_arc_check_relocs): Introduced warning to
TLS relocs which require -fPIC.
(arc_create_forced_local_got_entries_for_tls): Created.
Traverses list of GOT entries to be resolved statically
when needed.
(elf_arc_finish_dynamic_sections): Changed. Calls
arc_create_forced_local_got_entries_for_tls for each known
possibly GOT symbol.
* strings.c (print_strings): Check for multibyte encodings.
* binutils-all/strings-1.bin: New file. Test binary for string decoding.
* testsuite/binutils-all/strings.exp: New file. Test the strings program.
* testsuite/config/default.exp (STRINGS): Define if not provided
by the environment.
(STRINGSFLAGS): Likewise.
Pedro Alves
GDB Administrator
Tom Tromey
Alan Hayward
Nick Clifton
Joel Brobecker
Jim Wilson
Francois H. Theron
Thomas Preud'homme
H.J. Lu
Simon Marchi
Sudakshina Das
John Baldwin
Pedro Franco de Carvalho
Hafiz Abid Qadeer
Bernhard M. Wiedemann
Cupertino Miranda
rhn
Claudiu Zissulescu