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142 Commits

Author SHA1 Message Date
H.J. Lu
bd5dea8822 x86: Remove support for old (<= 2.8.1) versions of gcc 
Old (<= 2.8.1) versions of gcc generate broken fsubp, fsubrp, fdivp and
fdivrp instructions.  Assembler translates them to correct ones with a
warning:

[hjl@gnu-cfl-1 gas]$ cat x.s
	fsubp %st(3),%st
[hjl@gnu-cfl-1 gas]$ gcc -c x.s
x.s: Assembler messages:
x.s:1: Warning: translating to `fsubp %st,%st(3)'
[hjl@gnu-cfl-1 gas]$

This patch removes support for old (<= 2.8.1) versions of gcc:

[hjl@gnu-cfl-1 gas]$ ./as-new -o x.o x.s
x.s: Assembler messages:
x.s:1: Error: operand type mismatch for `fsubp'
[hjl@gnu-cfl-1 gas]$

gas/

	* NEWS: Mention -mold-gcc removal.
	* config/tc-i386.c (i386_error): Remove old_gcc_only.
	(old_gcc): Removed.
	(match_template): Remove old gcc support.
	(OPTION_MOLD_GCC): Removed.
	(OPTION_MRELAX_RELOCATIONS): Updated.
	(md_longopts): Remove OPTION_MOLD_GCC.
	(md_parse_option): Likewise.
	(md_show_usage): Remove -mold-gcc.
	* testsuite/gas/i386/general.s: Convert fsub/fdiv tests for old
	(<= 2.8.1) versions of gcc.
	* testsuite/gas/i386/intel.s: Likewise.
	* testsuite/gas/i386/general.l: Updated.
	* testsuite/gas/i386/intel-intel.d: Likewise.
	* testsuite/gas/i386/intel.d: Likewise.
	* testsuite/gas/i386/intel.e: Likewise.
	* testsuite/gas/i386/i386.exp: Don't pass -mold-gcc to general.

include/

	* opcode/i386 (OLDGCC_COMPAT): Removed.

opcodes/

	* i386-gen.c (opcode_modifiers): Remove OldGcc.
	* i386-opc.h (OldGcc): Removed.
	(i386_opcode_modifier): Remove oldgcc.
	* i386-opc.tbl: Remove fsubp, fsubrp, fdivp and fdivrp
	instructions for old (<= 2.8.1) versions of gcc.
	* i386-tbl.h: Regenerated.
 2018-03-08 06:31:52 -08:00
Jan Beulich
e771e7c9fb x86: fold several AVX512VL templates 
The differences between some of the register and memory forms of the
same insn often don't really require the templates to be separate. For
example, Disp8MemShift is simply irrelevant to register forms. Fold
these as far as possible, and also fold register-only forms. Further
folding is possible, but needs other prereq work done first.

A note regarding EVEXDYN: This is intended to be used only when no other
properties of the template would make is_evex_encoding() return true. In
all "normal" cases I think it is preferable to omit this indicator, to
keep the table half way readable.
 2018-03-08 08:58:55 +01:00
Jan Beulich
38e314eb06 x86: drop FloatD 
It can be expressed by D, when making the consumer look at operand size
to tell apart both uses.
 2018-03-08 08:34:09 +01:00
H.J. Lu
b6f8c7c452 x86: Add -O[2|s] assembler command-line options 
On x86, some instructions have alternate shorter encodings:

1. When the upper 32 bits of destination registers of

andq $imm31, %r64
testq $imm31, %r64
xorq %r64, %r64
subq %r64, %r64

known to be zero, we can encode them without the REX_W bit:

andl $imm31, %r32
testl $imm31, %r32
xorl %r32, %r32
subl %r32, %r32

This optimization is enabled with -O, -O2 and -Os.
2. Since 0xb0 mov with 32-bit destination registers zero-extends 32-bit
immediate to 64-bit destination register, we can use it to encode 64-bit
mov with 32-bit immediates.  This optimization is enabled with -O, -O2
and -Os.
3. Since the upper bits of destination registers of VEX128 and EVEX128
instructions are extended to zero, if all bits of destination registers
of AVX256 or AVX512 instructions are zero, we can use VEX128 or EVEX128
encoding to encode AVX256 or AVX512 instructions.  When 2 source
registers are identical, AVX256 and AVX512 andn and xor instructions:

VOP %reg, %reg, %dest_reg

can be encoded with

VOP128 %reg, %reg, %dest_reg

This optimization is enabled with -O2 and -Os.
4. 16-bit, 32-bit and 64-bit register tests with immediate may be
encoded as 8-bit register test with immediate.  This optimization is
enabled with -Os.

This patch does:

1. Add {nooptimize} pseudo prefix to disable instruction size
optimization.
2. Add optimize to i386_opcode_modifier to tell assembler that encoding
of an instruction may be optimized.

gas/

	PR gas/22871
	* NEWS: Mention -O[2|s].
	* config/tc-i386.c (_i386_insn): Add no_optimize.
	(optimize): New.
	(optimize_for_space): Likewise.
	(fits_in_imm7): New function.
	(fits_in_imm31): Likewise.
	(optimize_encoding): Likewise.
	(md_assemble): Call optimize_encoding to optimize encoding.
	(parse_insn): Handle {nooptimize}.
	(md_shortopts): Append "O::".
	(md_parse_option): Handle -On.
	* doc/c-i386.texi: Document -O0, -O, -O1, -O2 and -Os as well
	as {nooptimize}.
	* testsuite/gas/cfi/cfi-x86_64.d: Pass -O0 to assembler.
	* testsuite/gas/i386/ilp32/cfi/cfi-x86_64.d: Likewise.
	* testsuite/gas/i386/i386.exp: Run optimize-1, optimize-2,
	optimize-3, x86-64-optimize-1, x86-64-optimize-2,
	x86-64-optimize-3 and x86-64-optimize-4.
	* testsuite/gas/i386/optimize-1.d: New file.
	* testsuite/gas/i386/optimize-1.s: Likewise.
	* testsuite/gas/i386/optimize-2.d: Likewise.
	* testsuite/gas/i386/optimize-2.s: Likewise.
	* testsuite/gas/i386/optimize-3.d: Likewise.
	* testsuite/gas/i386/optimize-3.s: Likewise.
	* testsuite/gas/i386/x86-64-optimize-1.s: Likewise.
	* testsuite/gas/i386/x86-64-optimize-1.d: Likewise.
	* testsuite/gas/i386/x86-64-optimize-2.d: Likewise.
	* testsuite/gas/i386/x86-64-optimize-2.s: Likewise.
	* testsuite/gas/i386/x86-64-optimize-3.d: Likewise.
	* testsuite/gas/i386/x86-64-optimize-3.s: Likewise.
	* testsuite/gas/i386/x86-64-optimize-4.d: Likewise.
	* testsuite/gas/i386/x86-64-optimize-4.s: Likewise.

opcodes/

	PR gas/22871
	* i386-gen.c (opcode_modifiers): Add Optimize.
	* i386-opc.h (Optimize): New enum.
	(i386_opcode_modifier): Add optimize.
	* i386-opc.tbl: Add "Optimize" to "mov $imm, reg",
	"sub reg, reg/mem", "test $imm, acc", "test $imm, reg/mem",
	"and $imm, acc", "and $imm, reg/mem", "xor reg, reg/mem",
	"movq $imm, reg" and AVX256 and AVX512 versions of vandnps,
	vandnpd, vpandn, vpandnd, vpandnq, vxorps, vxorpd, vpxor,
	vpxord and vpxorq.
	* i386-tbl.h: Regenerated.
 2018-02-27 07:36:43 -08:00
Igor Tsimbalist
be3a8dca2d Enable Intel PCONFIG instruction. 
Intel has disclosed a set of new instructions for Icelake processor.
The spec is
https://software.intel.com/sites/default/files/managed/c5/15/architecture-instruction-set-extensions-programming-reference.pdf

This patch enables Intel PCONFIG instruction.

gas/
	* config/tc-i386.c (cpu_arch): Add .pconfig.
	* doc/c-i386.texi: Document .pconfig.
	* testsuite/gas/i386/i386.exp: Add PCONFIG tests.
	* testsuite/gas/i386/pconfig-intel.d: New test.
	* testsuite/gas/i386/pconfig.d: Likewise.
	* testsuite/gas/i386/pconfig.s: Likewise.
	* testsuite/gas/i386/x86-64-pconfig-intel.d: Likewise.
	* testsuite/gas/i386/x86-64-pconfig.d: Likewise.
	* testsuite/gas/i386/x86-64-pconfig.s: Likewise.
opcodes/
	* i386-dis.c (enum): Add pconfig.
	* i386-gen.c (cpu_flag_init): Add CPU_PCONFIG_FLAGS.
	(cpu_flags): Add CpuPCONFIG.
	* i386-opc.h (enum): Add CpuPCONFIG.
	(i386_cpu_flags): Add cpupconfig.
	* i386-opc.tbl: Add PCONFIG instruction.
	* i386-init.h: Regenerate.
	* i386-tbl.h: Likewise.
 2018-01-23 20:09:35 +03:00
Igor Tsimbalist
3233d7d074 Enable Intel WBNOINVD instruction. 
Intel has disclosed a set of new instructions for Icelake processor.
The spec is
https://software.intel.com/sites/default/files/managed/c5/15/architecture-instruction-set-extensions-programming-reference.pdf

This patch enables Intel WBNOINVD instruction.

gas/
	* config/tc-i386.c (cpu_arch): Add .wbnoinvd.
	* doc/c-i386.texi: Document .wbnoinvd.
	* testsuite/gas/i386/i386.exp: Add WBNOINVD tests.
	* testsuite/gas/i386/wbnoinvd-intel.d: New test.
	* testsuite/gas/i386/wbnoinvd.d: Likewise.
	* testsuite/gas/i386/wbnoinvd.s: Likewise.
	* testsuite/gas/i386/x86-64-wbnoinvd-intel.d: Likewise.
	* testsuite/gas/i386/x86-64-wbnoinvd.d: Likewise.
	* testsuite/gas/i386/x86-64-wbnoinvd.s: Likewise.
opcodes/
	* i386-dis.c (enum): Add PREFIX_0F09.
	* i386-gen.c (cpu_flag_init): Add CPU_WBNOINVD_FLAGS.
	(cpu_flags): Add CpuWBNOINVD.
	* i386-opc.h (enum): Add CpuWBNOINVD.
	(i386_cpu_flags): Add cpuwbnoinvd.
	* i386-opc.tbl: Add WBNOINVD instruction.
	* i386-init.h: Regenerate.
	* i386-tbl.h: Likewise.
 2018-01-23 20:05:33 +03:00
Igor Tsimbalist
d777820bf5 Replace CET bit with IBT and SHSTK bits. 
The latest specification for Intel CET technology defined two
new bits instead of previously used CET bit. These are IBT and
SHSTK bits. The patch replaces CET bit with IBT and SHSTK bits.

gas/
	* config/tc-i386.c (cpu_arch): Delete .cet. Add .ibt, .shstk.
	(cpu_noarch): Add noibt, noshstk.
	(parse_insn): Change cpucet to cpuibt.
	* doc/c-i386.texi: Delete .cet. Add .ibt, .shstk.
	* testsuite/gas/i386/cet-ibt-inval.l: New test.
	* testsuite/gas/i386/cet-ibt-inval.s: Likewise.
	* testsuite/gas/i386/cet-shstk-inval.l: Likewise.
	* testsuite/gas/i386/cet-shstk-inval.s: Likewise.
	* testsuite/gas/i386/x86-64-cet-ibt-inval.l: Likewise.
	* testsuite/gas/i386/x86-64-cet-ibt-inval.s: Likewise.
	* testsuite/gas/i386/x86-64-cet-shstk-inval.l: Likewise.
	* testsuite/gas/i386/x86-64-cet-shstk-inval.s: Likewise.

opcodes/
	* i386-gen.c (cpu_flag_init): Delete CPU_CET_FLAGS,
	CpuCET. Add CPU_IBT_FLAGS, CPU_SHSTK_FLAGS, CPY_ANY_IBT_FLAGS,
	CPU_ANY_SHSTK_FLAGS, CpuIBT, CpuSHSTK.
	(cpu_flags): Add CpuIBT, CpuSHSTK.
	* i386-opc.h (enum): Add CpuIBT, CpuSHSTK.
	(i386_cpu_flags): Add cpuibt, cpushstk.
	* i386-opc.tbl: Change CpuCET to CpuSHSTK and CpuIBT.
	* i386-init.h: Regenerate.
	* i386-tbl.h: Likewise.
 2018-01-17 19:48:28 +03:00
Alan Modra
219d1afa89 Update year range in copyright notice of binutils files 2018-01-03 17:49:56 +10:30
Jan Beulich
10c17abdd0 x86: fold certain AVX and AVX2 templates 
Just like for instructions in GPRs, there's no need to have separate
templates for otherwise identical insns acting on XMM or YMM registers
(or memory of the same size).
 2017-12-18 09:37:15 +01:00
Jan Beulich
1b54b8d7e4 x86: fold RegXMM/RegYMM/RegZMM into RegSIMD 
... qualified by their respective sizes, allowing to drop FirstXmm0 at
the same time.
 2017-12-18 09:36:14 +01:00
Jan Beulich
ca0d63fe07 x86: drop FloatReg and FloatAcc 
Express them as Reg|Tbyte and Acc|Tbyte respectively.
 2017-12-18 09:35:01 +01:00
Jan Beulich
dc821c5f9a x86: replace Reg8, Reg16, Reg32, and Reg64 
Use a combination of a single new Reg bit and Byte, Word, Dword, or
Qword instead.

Besides shrinking the number of operand type bits this has the benefit
of making register handling more similar to accumulator handling (a
generic flag is being accompanied by a "size qualifier"). It requires,
however, to split a few insn templates, as it is no longer correct to
have combinations like Reg32|Reg64|Byte. This slight growth in size will
hopefully be outweighed by this change paving the road for folding a
presumably much larger number of templates later on.
 2017-12-18 09:34:00 +01:00
Jan Beulich
b5014f7af2 x86: drop Vec_Disp8 
This is fully redundant with Disp8MemShift being non-zero, and hence can
be folded with normal Disp8 handling.
 2017-11-30 11:47:38 +01:00
Igor Tsimbalist
ee6872beb1 Enable Intel AVX512_BITALG instructions. 
Intel has disclosed a set of new instructions. The spec is
https://software.intel.com/sites/default/files/managed/c5/15/architecture-instruction-set-extensions-programming-reference.pdf

gas/

	* config/tc-i386.c (cpu_arch): Add .avx512_bitalg.
	(cpu_noarch): noavx512_bitalg.
	* doc/c-i386.texi: Document .avx512_bitalg, noavx512_bitalg.
	* testsuite/gas/i386/i386.exp: Add AVX512_BITALG tests.
	* testsuite/gas/i386/avx512f_bitalg-intel.d: New test.
	* testsuite/gas/i386/avx512f_bitalg.d: Likewise.
	* testsuite/gas/i386/avx512f_bitalg.s: Likewise.
	* testsuite/gas/i386/avx512vl_bitalg-intel.d: Likewise.
	* testsuite/gas/i386/avx512vl_bitalg.d: Likewise.
	* testsuite/gas/i386/avx512vl_bitalg.s: Likewise.
	* testsuite/gas/i386/x86-64-avx512f_bitalg-intel.d: Likewise.
	* testsuite/gas/i386/x86-64-avx512f_bitalg.d: Likewise.
	* testsuite/gas/i386/x86-64-avx512f_bitalg.s: Likewise.
	* testsuite/gas/i386/x86-64-avx512vl_bitalg-intel.d: Likewise.
	* testsuite/gas/i386/x86-64-avx512vl_bitalg.d: Likewise.
	* testsuite/gas/i386/x86-64-avx512vl_bitalg.s: Likewise.

opcodes/

	* i386-dis.c (enum): Add PREFIX_EVEX_0F3854, PREFIX_EVEX_0F388F.
	(enum): Add EVEX_W_0F3854_P_2.
	* i386-dis-evex.h (evex_table): Updated.
	* i386-gen.c (cpu_flag_init): Add CPU_AVX512_BITALG,
	CPU_ANY_AVX512_BITALG_FLAGS. Update CPU_ANY_AVX512F_FLAGS.
	(cpu_flags): Add CpuAVX512_BITALG.
	* i386-opc.h (enum): Add CpuAVX512_BITALG.
	(i386_cpu_flags): Add cpuavx512_bitalg..
	* i386-opc.tbl: Add Intel AVX512_BITALG instructions.
	* i386-init.h: Regenerate.
	* i386-tbl.h: Likewise.
 2017-10-23 15:58:18 +03:00
Igor Tsimbalist
8cfcb7659c Enable Intel AVX512_VNNI instructions. 
Intel has disclosed a set of new instructions. The spec is
https://software.intel.com/sites/default/files/managed/c5/15/architecture-instruction-set-extensions-programming-reference.pdf

gas/

	* config/tc-i386.c (cpu_arch): Add .avx512_vnni.
	(cpu_noarch): Add noavx512_vnni.
	* doc/c-i386.texi: Document .avx512_vnni.
	* testsuite/gas/i386/i386.exp: Add AVX512_VNNI tests.
	* testsuite/gas/i386/avx512vnni-intel.d: New test.
	* testsuite/gas/i386/avx512vnni.d: Likewise.
	* testsuite/gas/i386/avx512vnni.s: Likewise.
	* testsuite/gas/i386/avx512vnni_vl-intel.d: Likewise.
	* testsuite/gas/i386/avx512vnni_vl.d: Likewise.
	* testsuite/gas/i386/avx512vnni_vl.s: Likewise.
	* testsuite/gas/i386/x86-64-avx512vnni-intel.d: Likewise.
	* testsuite/gas/i386/x86-64-avx512vnni.d: Likewise.
	* testsuite/gas/i386/x86-64-avx512vnni.s: Likewise.
	* testsuite/gas/i386/x86-64-avx512vnni_vl-intel.d: Likewise.
	* testsuite/gas/i386/x86-64-avx512vnni_vl.d: Likewise.
	* testsuite/gas/i386/x86-64-avx512vnni_vl.s: Likewise.

opcodes/

	* i386-dis.c (enum): Add PREFIX_EVEX_0F3850, PREFIX_EVEX_0F3851.
	* i386-dis-evex.h (evex_table): Updated.
	* i386-gen.c (cpu_flag_init): Add CPU_AVX512_VNNI,
	CPU_ANY_AVX512_VNNI_FLAGS. Update CPU_ANY_AVX512F_FLAGS.
	(cpu_flags): Add CpuAVX512_VNNI.
	* i386-opc.h (enum): Add CpuAVX512_VNNI.
	(i386_cpu_flags): Add cpuavx512_vnni.
	* i386-opc.tbl Add Intel AVX512_VNNI instructions.
	* i386-init.h: Regenerate.
	* i386-tbl.h: Likewise.
 2017-10-23 15:58:18 +03:00
Igor Tsimbalist
ff1982d53a Enable Intel VPCLMULQDQ instruction. 
Intel has disclosed a set of new instructions. The spec is
https://software.intel.com/sites/default/files/managed/c5/15/architecture-instruction-set-extensions-programming-reference.pdf

gas/

	* config/tc-i386.c (cpu_arch): Add VPCLMULQDQ.
	* doc/c-i386.texi: Document VPCLMULQDQ.
	* testsuite/gas/i386/i386.exp: Run VPCLMULQDQ tests.
	* testsuite/gas/i386/avx512f_vpclmulqdq-intel.d: New test.
	* testsuite/gas/i386/avx512f_vpclmulqdq-wig.s: Ditto.
	* testsuite/gas/i386/avx512f_vpclmulqdq-wig1-intel.d: Ditto.
	* testsuite/gas/i386/avx512f_vpclmulqdq-wig1.d: Ditto.
	* testsuite/gas/i386/avx512f_vpclmulqdq.d: Ditto.
	* testsuite/gas/i386/avx512f_vpclmulqdq.s: Ditto.
	* testsuite/gas/i386/avx512vl_vpclmulqdq-intel.d: Ditto.
	* testsuite/gas/i386/avx512vl_vpclmulqdq-wig.s: Ditto.
	* testsuite/gas/i386/avx512vl_vpclmulqdq-wig1-intel.d: Ditto.
	* testsuite/gas/i386/avx512vl_vpclmulqdq-wig1.d: Ditto.
	* testsuite/gas/i386/avx512vl_vpclmulqdq.d: Ditto.
	* testsuite/gas/i386/avx512vl_vpclmulqdq.s: Ditto.
	* testsuite/gas/i386/vpclmulqdq-intel.d: Ditto.
	* testsuite/gas/i386/vpclmulqdq.d: Ditto.
	* testsuite/gas/i386/vpclmulqdq.s: Ditto.
	* testsuite/gas/i386/x86-64-avx512f_vpclmulqdq-intel.d: Ditto.
	* testsuite/gas/i386/x86-64-avx512f_vpclmulqdq-wig.s: Ditto.
	* testsuite/gas/i386/x86-64-avx512f_vpclmulqdq-wig1-intel.d: Ditto.
	* testsuite/gas/i386/x86-64-avx512f_vpclmulqdq-wig1.d: Ditto.
	* testsuite/gas/i386/x86-64-avx512f_vpclmulqdq.d: Ditto.
	* testsuite/gas/i386/x86-64-avx512f_vpclmulqdq.s: Ditto.
	* testsuite/gas/i386/x86-64-avx512vl_vpclmulqdq-intel.d: Ditto.
	* testsuite/gas/i386/x86-64-avx512vl_vpclmulqdq-wig.s: Ditto.
	* testsuite/gas/i386/x86-64-avx512vl_vpclmulqdq-wig1-intel.d: Ditto.
	* testsuite/gas/i386/x86-64-avx512vl_vpclmulqdq-wig1.d: Ditto.
	* testsuite/gas/i386/x86-64-avx512vl_vpclmulqdq.d: Ditto.
	* testsuite/gas/i386/x86-64-avx512vl_vpclmulqdq.s: Ditto.
	* testsuite/gas/i386/x86-64-vpclmulqdq-intel.d: Ditto.
	* testsuite/gas/i386/x86-64-vpclmulqdq.d: Ditto.
	* testsuite/gas/i386/x86-64-vpclmulqdq.s: Ditto.

opcodes/

	* i386-dis.c (enum): Add PREFIX_EVEX_0F3A44.
	(enum): Remove VEX_LEN_0F3A44_P_2.
	(vex_len_table): Ditto.
	(enum): Remove VEX_W_0F3A44_P_2.
	(vew_w_table): Ditto.
	(prefix_table): Adjust instructions (see prefixes above).
	* i386-dis-evex.h (evex_table):
	Add new instructions (see prefixes above).
	* i386-gen.c (cpu_flag_init): Add VPCLMULQDQ.
	(bitfield_cpu_flags): Ditto.
	* i386-opc.h (enum): Ditto.
	(i386_cpu_flags): Ditto.
	(CpuUnused): Comment out to avoid zero-width field problem.
	* i386-opc.tbl (vpclmulqdq): New instruction.
	* i386-init.h: Regenerate.
	* i386-tbl.h: Ditto.
 2017-10-23 15:58:18 +03:00
Igor Tsimbalist
8dcf1fadf2 Enable Intel VAES instructions. 
Intel has disclosed a set of new instructions. The spec is
https://software.intel.com/sites/default/files/managed/c5/15/architecture-instruction-set-extensions-programming-reference.pdf

gas/

	* config/tc-i386.c (cpu_arch): Add VAES.
	* doc/c-i386.texi: Document VAES.
	* testsuite/gas/i386/i386.exp: Run VAES tests.
	* testsuite/gas/i386/avx512f_vaes-intel.d: New test.
	* testsuite/gas/i386/avx512f_vaes-wig.s: Ditto.
	* testsuite/gas/i386/avx512f_vaes-wig1-intel.d: Ditto.
	* testsuite/gas/i386/avx512f_vaes-wig1.d: Ditto.
	* testsuite/gas/i386/avx512f_vaes.d: Ditto.
	* testsuite/gas/i386/avx512f_vaes.s: Ditto.
	* testsuite/gas/i386/avx512vl_vaes-intel.d: Ditto.
	* testsuite/gas/i386/avx512vl_vaes-wig.s: Ditto.
	* testsuite/gas/i386/avx512vl_vaes-wig1-intel.d: Ditto.
	* testsuite/gas/i386/avx512vl_vaes-wig1.d: Ditto.
	* testsuite/gas/i386/avx512vl_vaes.d: Ditto.
	* testsuite/gas/i386/avx512vl_vaes.s: Ditto.
	* testsuite/gas/i386/vaes-intel.d: Ditto.
	* testsuite/gas/i386/vaes.d: Ditto.
	* testsuite/gas/i386/vaes.s: Ditto.
	* testsuite/gas/i386/x86-64-avx512f_vaes-intel.d: Ditto.
	* testsuite/gas/i386/x86-64-avx512f_vaes-wig.s: Ditto.
	* testsuite/gas/i386/x86-64-avx512f_vaes-wig1-intel.d: Ditto.
	* testsuite/gas/i386/x86-64-avx512f_vaes-wig1.d: Ditto.
	* testsuite/gas/i386/x86-64-avx512f_vaes.d: Ditto.
	* testsuite/gas/i386/x86-64-avx512f_vaes.s: Ditto.
	* testsuite/gas/i386/x86-64-avx512vl_vaes-intel.d: Ditto.
	* testsuite/gas/i386/x86-64-avx512vl_vaes-wig.s: Ditto.
	* testsuite/gas/i386/x86-64-avx512vl_vaes-wig1-intel.d: Ditto.
	* testsuite/gas/i386/x86-64-avx512vl_vaes-wig1.d: Ditto.
	* testsuite/gas/i386/x86-64-avx512vl_vaes.d: Ditto.
	* testsuite/gas/i386/x86-64-avx512vl_vaes.s: Ditto.
	* testsuite/gas/i386/x86-64-vaes-intel.d: Ditto.
	* testsuite/gas/i386/x86-64-vaes.d: Ditto.
	* testsuite/gas/i386/x86-64-vaes.s: Ditto.

opcodes/

	* i386-dis.c (enum): Add PREFIX_EVEX_0F38DC, PREFIX_EVEX_0F38DD,
	PREFIX_EVEX_0F38DE, PREFIX_EVEX_0F38DF.
	(enum): Remove VEX_LEN_0F38DC_P_2, VEX_LEN_0F38DD_P_2,
	VEX_LEN_0F38DE_P_2, VEX_LEN_0F38DF_P_2.
	(vex_len_table): Ditto.
	(enum): Remove VEX_W_0F38DC_P_2, VEX_W_0F38DD_P_2,
	VEX_W_0F38DE_P_2, VEX_W_0F38DF_P_2.
	(vew_w_table): Ditto.
	(prefix_table): Adjust instructions (see prefixes above).
	* i386-dis-evex.h (evex_table):
	Add new instructions (see prefixes above).
	* i386-gen.c (cpu_flag_init): Add VAES.
	(bitfield_cpu_flags): Ditto.
	* i386-opc.h (enum): Ditto.
	(i386_cpu_flags): Ditto.
	* i386-opc.tbl (vaes{enc,dec}{last,}): New instructions.
	* i386-init.h: Regenerate.
	* i386-tbl.h: Ditto.
 2017-10-23 15:58:18 +03:00
Igor Tsimbalist
48521003d5 Enable Intel GFNI instructions. 
Intel has disclosed a set of new instructions. The spec is
https://software.intel.com/sites/default/files/managed/c5/15/architecture-instruction-set-extensions-programming-reference.pdf

gas/

	* config/tc-i386.c (cpu_arch): Add .gfni.
	* doc/c-i386.texi: Document .gfni.
	* testsuite/gas/i386/i386.exp: Add GFNI tests.
	* testsuite/gas/i386/avx.s: New GFNI test.
	* testsuite/gas/i386/x86-64-avx.s: Likewise.
	* testsuite/gas/i386/avx.d: Adjust.
	* testsuite/gas/i386/avx-intel.d: Likewise
	* testsuite/gas/i386/ilp32/x86-64-avx-intel.d: Likewise.
	* testsuite/gas/i386/ilp32/x86-64-avx.d: Likewise.
	* testsuite/gas/i386/avx512f_gfni-intel.d: New test.
	* testsuite/gas/i386/avx512f_gfni.d: Likewise.
	* testsuite/gas/i386/avx512f_gfni.s: Likewise.
	* testsuite/gas/i386/avx512vl_gfni-intel.d: Likewise.
	* testsuite/gas/i386/avx512vl_gfni.d: Likewise.
	* testsuite/gas/i386/avx512vl_gfni.s: Likewise.
	* testsuite/gas/i386/gfni-intel.d: Likewise.
	* testsuite/gas/i386/gfni.d: Likewise.
	* testsuite/gas/i386/gfni.s: Likewise.
	* testsuite/gas/i386/x86-64-avx512f_gfni-intel.d: Likewise.
	* testsuite/gas/i386/x86-64-avx512f_gfni.d: Likewise.
	* testsuite/gas/i386/x86-64-avx512f_gfni.s: Likewise.
	* testsuite/gas/i386/x86-64-avx512vl_gfni-intel.d: Likewise.
	* testsuite/gas/i386/x86-64-avx512vl_gfni.d: Likewise.
	* testsuite/gas/i386/x86-64-avx512vl_gfni.s: Likewise.
	* testsuite/gas/i386/x86-64-avx_gfni-intel.d: Likewise.
	* testsuite/gas/i386/x86-64-avx_gfni.d: Likewise.
	* testsuite/gas/i386/x86-64-avx_gfni.s: Likewise.
	* testsuite/gas/i386/x86-64-gfni-intel.d: Likewise.
	* testsuite/gas/i386/x86-64-gfni.d: Likewise.
	* testsuite/gas/i386/x86-64-gfni.s: Likewise.

opcodes/

	* i386-dis.c (enum): Add PREFIX_0F38CF, PREFIX_0F3ACE, PREFIX_0F3ACF,
	PREFIX_VEX_0F38CF, PREFIX_VEX_0F3ACE, PREFIX_VEX_0F3ACF,
	PREFIX_EVEX_0F38CF, PREFIX_EVEX_0F3ACE, PREFIX_EVEX_0F3ACF.
	(enum): Add VEX_W_0F38CF_P_2, VEX_W_0F3ACE_P_2, VEX_W_0F3ACF_P_2,
	EVEX_W_0F3ACE_P_2, EVEX_W_0F3ACF_P_2.
	(prefix_table): Updated (see prefixes above).
	(three_byte_table): Likewise.
	(vex_w_table): Likewise.
	* i386-dis-evex.h: Likewise.
	* i386-gen.c (cpu_flag_init): Add CPU_GFNI_FLAGS, CpuGFNI.
	(cpu_flags): Add CpuGFNI.
	* i386-opc.h (enum): Add CpuGFNI.
	(i386_cpu_flags): Add cpugfni.
	* i386-opc.tbl: Add Intel GFNI instructions.
	* i386-init.h: Regenerate.
	* i386-tbl.h: Likewise.
 2017-10-23 15:58:13 +03:00
Igor Tsimbalist
53467f5707 Enable Intel AVX512_VBMI2 instructions. 
Intel has disclosed a set of new instructions. The spec is
https://software.intel.com/sites/default/files/managed/c5/15/architecture-instruction-set-extensions-programming-reference.pdf

gas/

	* config/tc-i386.c (cpu_arch): Add .avx512_vbmi2.
	(cpu_noarch): noavx512_vbmi2.
	* doc/c-i386.texi: Document .avx512_vbmi2, noavx512_vbmi2.
	* testsuite/gas/i386/i386.exp: Add AVX512_VBMI2 tests.
	* testsuite/gas/i386/avx512vbmi2-intel.d: New test.
	* testsuite/gas/i386/avx512vbmi2.d: Likewise.
	* testsuite/gas/i386/avx512vbmi2.s: Likewise.
	* testsuite/gas/i386/avx512vbmi2_vl-intel.d: Likewise.
	* testsuite/gas/i386/avx512vbmi2_vl.d: Likewise.
	* testsuite/gas/i386/avx512vbmi2_vl.s: Likewise.
	* testsuite/gas/i386/x86-64-avx512vbmi2-intel.d: Likewise.
	* testsuite/gas/i386/x86-64-avx512vbmi2.d: Likewise.
	* testsuite/gas/i386/x86-64-avx512vbmi2.s: Likewise.
	* testsuite/gas/i386/x86-64-avx512vbmi2_vl-intel.d: Likewise.
	* testsuite/gas/i386/x86-64-avx512vbmi2_vl.d: Likewise.
	* testsuite/gas/i386/x86-64-avx512vbmi2_vl.s: Likewise.

opcodes/

	* i386-dis.c (enum): Add b_scalar_mode, w_scalar_mode.
	Define EXbScalar and EXwScalar for OP_EX.
	(enum): Add PREFIX_EVEX_0F3862, PREFIX_EVEX_0F3863,
	PREFIX_EVEX_0F3870, PREFIX_EVEX_0F3871, PREFIX_EVEX_0F3872,
	PREFIX_EVEX_0F3873, PREFIX_EVEX_0F3A70, PREFIX_EVEX_0F3A71,
	PREFIX_EVEX_0F3A72, PREFIX_EVEX_0F3A73.
	(enum): Add EVEX_W_0F3862_P_2, EVEX_W_0F3863_P_2,
	EVEX_W_0F3870_P_2, EVEX_W_0F3871_P_2, EVEX_W_0F3872_P_2,
	EVEX_W_0F3873_P_2, EVEX_W_0F3A70_P_2, EVEX_W_0F3A71_P_2,
	EVEX_W_0F3A72_P_2, EVEX_W_0F3A73_P_2.
	(intel_operand_size): Handle b_scalar_mode and w_scalar_mode.
	(OP_E_memory): Likewise.
	* i386-dis-evex.h: Updated.
	* i386-gen.c (cpu_flag_init): Add CPU_AVX512_VBMI2,
	CPU_ANY_AVX512_VBMI2_FLAGS. Update CPU_ANY_AVX512F_FLAGS.
	(cpu_flags): Add CpuAVX512_VBMI2.
	* i386-opc.h (enum): Add CpuAVX512_VBMI2.
	(i386_cpu_flags): Add cpuavx512_vbmi2.
	* i386-opc.tbl: Add Intel AVX512_VBMI2 instructions.
	* i386-init.h: Regenerate.
	* i386-tbl.h: Likewise.
 2017-10-23 15:58:07 +03:00
H.J. Lu
04ef582ace x86: Add NOTRACK prefix support 
For register indirect branches, NOTRACK prefix (0x3e), which is also
the DS segment register prefix, can be used to ignore the CET indirect
branch track.

gas/

	* config/tc-i386.c (REX_PREFIX): Changed to 7.
	(NOTRACK_PREFIX): New.
	(MAX_PREFIXES): Changed to 8.
	(_i386_insn): Add notrack_prefix.
	(PREFIX_GROUP): Add PREFIX_DS.
	(add_prefix): Return PREFIX_DS for DS_PREFIX_OPCODE.
	(md_assemble): Check if NOTRACK prefix is supported.
	(parse_insn): Set notrack_prefix and issue an error for
	other prefixes after NOTRACK prefix.
	* testsuite/gas/i386/i386.exp: Run tests for NOTRACK prefix.
	* testsuite/gas/i386/notrack-intel.d: New file.
	* testsuite/gas/i386/notrack.d: Likewise.
	* testsuite/gas/i386/notrack.s: Likewise.
	* testsuite/gas/i386/notrackbad.l: Likewise.
	* testsuite/gas/i386/notrackbad.s: Likewise.
	* testsuite/gas/i386/x86-64-notrack-intel.d: Likewise.
	* testsuite/gas/i386/x86-64-notrack.d: Likewise.
	* testsuite/gas/i386/x86-64-notrack.s: Likewise.
	* testsuite/gas/i386/x86-64-notrackbad.l: Likewise.
	* testsuite/gas/i386/x86-64-notrackbad.s: Likewise.

include/

	* include/opcode/i386.h (NOTRACK_PREFIX_OPCODE): New.

opcodes/

	* i386-dis.c (NOTRACK_Fixup): New.
	(NOTRACK): Likewise.
	(NOTRACK_PREFIX): Likewise.
	(last_active_prefix): Likewise.
	(reg_table): Use NOTRACK on indirect call and jmp.
	(ckprefix): Set last_active_prefix.
	(prefix_name): Return "notrack" for NOTRACK_PREFIX.
	* i386-gen.c (opcode_modifiers): Add NoTrackPrefixOk.
	* i386-opc.h (NoTrackPrefixOk): New.
	(i386_opcode_modifier): Add notrackprefixok.
	* i386-opc.tbl: Add NoTrackPrefixOk to indirect call and jmp.
	Add notrack.
	* i386-tbl.h: Regenerated.
 2017-05-22 11:02:58 -07:00
H.J. Lu
86fa6981e7 X86: Add pseudo prefixes to control encoding 
Many x86 instructions have more than one encodings.  Assembler picks
the default one, usually the shortest one.  Although the ".s", ".d8"
and ".d32" suffixes can be used to swap register operands or specify
displacement size, they aren't very flexible.  This patch adds pseudo
prefixes, {xxx}, to control instruction encoding.  The available
pseudo prefixes are {disp8}, {disp32}, {load}, {store}, {vex2}, {vex3}
and {evex}.  Pseudo prefixes are preferred over the ".s", ".d8" and
".d32" suffixes, which are deprecated.

gas/

	* config/tc-i386.c (_i386_insn): Add dir_encoding and
	vec_encoding.  Remove swap_operand and need_vrex.
	(extra_symbol_chars): Add '}'.
	(md_begin): Mark '}' with LEX_BEGIN_NAME.  Allow '}' in
	mnemonic.
	(build_vex_prefix): Don't use 2-byte VEX encoding with
	{vex3}.  Check dir_encoding and load.
	(parse_insn): Check pseudo prefixes.  Set dir_encoding.
	(VEX_check_operands): Likewise.
	(match_template): Check dir_encoding and load.
	(parse_real_register): Set vec_encoding instead of need_vrex.
	(parse_register): Likewise.
	* doc/c-i386.texi: Document {disp8}, {disp32}, {load}, {store},
	{vex2}, {vex3} and {evex}.  Remove ".s", ".d8" and ".d32"
	* testsuite/gas/i386/i386.exp: Run pseudos and x86-64-pseudos.
	* testsuite/gas/i386/pseudos.d: New file.
	* testsuite/gas/i386/pseudos.s: Likewise.
	* testsuite/gas/i386/x86-64-pseudos.d: Likewise.
	* testsuite/gas/i386/x86-64-pseudos.s: Likewise.

opcodes/

	* i386-gen.c (opcode_modifiers): Replace S with Load.
	* i386-opc.h (S): Removed.
	(Load): New.
	(i386_opcode_modifier): Replace s with load.
	* i386-opc.tbl: Add {disp8}, {disp32}, {swap}, {vex2}, {vex3}
	and {evex}.  Replace S with Load.
	* i386-tbl.h: Regenerated.
 2017-03-09 09:59:00 -08:00
H.J. Lu
603555e563 Add support for Intel CET instructions 
Support Intel Control-flow Enforcement Technology (CET) instructions:

https://software.intel.com/sites/default/files/managed/4d/2a/control-flow-enforcement-technology-preview.pdf

gas/

	* config/tc-i386.c (cpu_arch): Add .cet.
	* doc/c-i386.texi: Document cet.
	* testsuite/gas/i386/cet-intel.d: New file.
	* testsuite/gas/i386/cet.d: Likewise.
	* testsuite/gas/i386/cet.s: Likewise.
	* testsuite/gas/i386/x86-64-cet-intel.d: Likewise.
	* testsuite/gas/i386/x86-64-cet.d: Likewise.
	* testsuite/gas/i386/x86-64-cet.s: Likewise.
	* testsuite/gas/i386/i386.exp: Run Intel CET tests.

opcodes/

	* i386-dis.c (REG_0F1E_MOD_3): New enum.
	(MOD_0F1E_PREFIX_1): Likewise.
	(MOD_0F38F5_PREFIX_2): Likewise.
	(MOD_0F38F6_PREFIX_0): Likewise.
	(RM_0F1E_MOD_3_REG_7): Likewise.
	(PREFIX_MOD_0_0F01_REG_5): Likewise.
	(PREFIX_MOD_3_0F01_REG_5_RM_1): Likewise.
	(PREFIX_MOD_3_0F01_REG_5_RM_2): Likewise.
	(PREFIX_0F1E): Likewise.
	(PREFIX_MOD_0_0FAE_REG_5): Likewise.
	(PREFIX_0F38F5): Likewise.
	(dis386_twobyte): Use PREFIX_0F1E.
	(reg_table): Add REG_0F1E_MOD_3.
	(prefix_table): Add PREFIX_MOD_0_0F01_REG_5,
	PREFIX_MOD_3_0F01_REG_5_RM_1, PREFIX_MOD_3_0F01_REG_5_RM_2,
	PREFIX_0F1E, PREFIX_MOD_0_0FAE_REG_5 and PREFIX_0F38F5.  Update
	PREFIX_0FAE_REG_6 and PREFIX_0F38F6.
	(three_byte_table): Use PREFIX_0F38F5.
	(mod_table): Use PREFIX_MOD_0_0F01_REG_5, PREFIX_MOD_0_0FAE_REG_5.
	Add MOD_0F1E_PREFIX_1, MOD_0F38F5_PREFIX_2, MOD_0F38F6_PREFIX_0.
	(rm_table): Add MOD_0F38F5_PREFIX_2, MOD_0F38F6_PREFIX_0,
	RM_0F1E_MOD_3_REG_7.  Use PREFIX_MOD_3_0F01_REG_5_RM_1 and
	PREFIX_MOD_3_0F01_REG_5_RM_2.
	* i386-gen.c (cpu_flag_init): Add CPU_CET_FLAGS.
	(cpu_flags): Add CpuCET.
	* i386-opc.h (CpuCET): New enum.
	(CpuUnused): Commented out.
	(i386_cpu_flags): Add cpucet.
	* i386-opc.tbl: Add Intel CET instructions.
	* i386-init.h: Regenerated.
	* i386-tbl.h: Likewise.
 2017-03-06 15:26:37 -08:00
Igor Tsimbalist
620214f742 Enable Intel AVX512_VPOPCNTDQ instructions 
gas/

2017-01-12  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>

	* config/tc-i386.c (cpu_arch): Add .avx512_vpopcntdq.
	(cpu_noarch): Add noavx512_vpopcntdq.
	* doc/c-i386.texi: Document avx512_vpopcntdq, noavx512_vpopcntdq.
	* testsuite/gas/i386/i386.exp: Run AVX512_VPOPCNTDQ tests.
	* testsuite/gas/i386/avx512_vpopcntdqd-intel.d: New file.
	* testsuite/gas/i386/avx512_vpopcntdqd.d: Ditto.
	* testsuite/gas/i386/avx512_vpopcntdqd.s: Ditto.
	* testsuite/gas/i386/x86-64-avx512_vpopcntdqd-intel.d: Ditto.
	* testsuite/gas/i386/x86-64-avx512_vpopcntdqd.d: Ditto.
	* testsuite/gas/i386/x86-64-avx512_vpopcntdqd.s: Ditto.

opcodes/

2017-01-12  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>

	* i386-dis.c (enum): Add PREFIX_EVEX_0F3855, EVEX_W_0F3855_P_2.
	* i386-dis-evex.h (evex_table): Updated.
	* i386-gen.c (cpu_flag_init): Add CPU_AVX512_VPOPCNTDQ_FLAGS,
	CPU_ANY_AVX512_VPOPCNTDQ_FLAGS. Update CPU_ANY_AVX512F_FLAGS.
	(cpu_flags): Add CpuAVX512_VPOPCNTDQ.
	* i386-opc.h (enum): (AVX512_VPOPCNTDQ): New.
	(i386_cpu_flags): Add cpuavx512_vpopcntdq.
	* i386-opc.tbl: Add Intel AVX512_VPOPCNTDQ instructions.
	* i386-init.h: Regenerate.
	* i386-tbl.h: Ditto.
 2017-01-12 08:44:24 -08:00
Alan Modra
2571583aed Update year range in copyright notice of all files. 2017-01-02 14:08:56 +10:30
Igor Tsimbalist
47acf0bd9f Enable Intel AVX512_4VNNIW instructions 
gas/

	* config/tc-i386.c: (cpu_arch) Add .avx512_4vnniw.
	(cpu_noarch): Add noavx512_4vnniw.
	* doc/c-i386.texi: Document avx512_4vnniw, noavx512_4vnniw.
	* testsuite/gas/i386/i386.exp: Run AVX512_4VNNIW tests.
	* testsuite/gas/i386/avx512_4vnniwd_vl-intel.d: New test.
	* testsuite/gas/i386/avx512_4vnniwd_vl.d: Ditto.
	* testsuite/gas/i386/avx512_4vnniwd_vl.s: Ditto.
	* testsuite/gas/i386/avx512_4vnniwd-intel.d: Ditto.
	* testsuite/gas/i386/avx512_4vnniwd.d: Ditto.
	* testsuite/gas/i386/avx512_4vnniwd.s: Ditto.
	* testsuite/gas/i386/x86-64-avx512_4vnniwd_vl-intel.d: Ditto.
	* testsuite/gas/i386/x86-64-avx512_4vnniwd_vl.d: Ditto.
	* testsuite/gas/i386/x86-64-avx512_4vnniwd_vl.s: Ditto.
	* testsuite/gas/i386/x86-64-avx512_4vnniwd-intel.d: Ditto.
	* testsuite/gas/i386/x86-64-avx512_4vnniwd.d: Ditto.
	* testsuite/gas/i386/x86-64-avx512_4vnniwd.s: Ditto.

opcodes/

	* i386-dis.c (enum): Add PREFIX_EVEX_0F3852, PREFIX_EVEX_0F3853.
	* i386-dis-evex.h (evex_table): Updated.
	* i386-gen.c (cpu_flag_init): Add CPU_AVX512_4VNNIW_FLAGS,
	CPU_ANY_AVX512_4VNNIW_FLAGS. Update CPU_ANY_AVX512F_FLAGS.
	(cpu_flags): Add CpuAVX512_4VNNIW.
	* i386-opc.h (enum): (AVX512_4VNNIW): New.
	(i386_cpu_flags): Add cpuavx512_4vnniw.
	* i386-opc.tbl: Add Intel AVX512_4VNNIW instructions.
	* i386-init.h: Regenerate.
	* i386-tbl.h: Ditto.
 2016-11-02 12:31:25 -07:00
Igor Tsimbalist
920d2ddccb Enable Intel AVX512_4FMAPS instructions 
gas/

	* config/tc-i386.c (cpu_arch): Add .avx512_4fmaps.
	(cpu_noarch): Add noavx512_4fmaps.
	(process_operands): Handle implicit quad group.
	* doc/c-i386.texi: Document avx512_4fmaps, noavx512_4fmaps.
	* testsuite/gas/i386/i386.exp: Add AVX512_4FMAPS tests.
	* testsuite/gas/i386/avx512_4fmaps_vl-intel.d: New test.
	* testsuite/gas/i386/avx512_4fmaps_vl.d: Ditto.
	* testsuite/gas/i386/avx512_4fmaps_vl.s: Ditto.
	* testsuite/gas/i386/avx512_4fmaps-intel.d: Ditto.
	* testsuite/gas/i386/avx512_4fmaps.d: Ditto.
	* testsuite/gas/i386/avx512_4fmaps.s: Ditto.
	* testsuite/gas/i386/avx512_4fmaps-warn.l: Ditto.
	* testsuite/gas/i386/avx512_4fmaps-warn.s: Ditto.
	* testsuite/gas/i386/avx512_4fmaps_vl-warn.l: Ditto.
	* testsuite/gas/i386/avx512_4fmaps_vl-warn.s: Ditto.
	* testsuite/gas/i386/x86-64-avx512_4fmaps_vl-intel.d: Ditto.
	* testsuite/gas/i386/x86-64-avx512_4fmaps_vl.d: Ditto.
	* testsuite/gas/i386/x86-64-avx512_4fmaps_vl.s: Ditto.
	* testsuite/gas/i386/x86-64-avx512_4fmaps-intel.d: Ditto.
	* testsuite/gas/i386/x86-64-avx512_4fmaps.d: Ditto.
	* testsuite/gas/i386/x86-64-avx512_4fmaps.s: Ditto.
	* testsuite/gas/i386/x86-64-avx512_4fmaps-warn.l: Ditto.
	* testsuite/gas/i386/x86-64-avx512_4fmaps-warn.s: Ditto.
	* testsuite/gas/i386/x86-64-avx512_4fmaps_vl-warn.l: Ditto.
	* testsuite/gas/i386/x86-64-avx512_4fmaps_vl-warn.s: Ditto.

opcodes/

	* i386-dis.c. (enum): Add PREFIX_EVEX_0F389A,
	PREFIX_EVEX_0F389B, PREFIX_EVEX_0F38AA, PREFIX_EVEX_0F38AB.
	* i386-dis-evex.h (evex_table): Updated.
	* i386-gen.c (cpu_flag_init): Add CPU_AVX512_4FMAPS_FLAGS,
	CPU_ANY_AVX512_4FMAPS_FLAGS. Update CPU_ANY_AVX512F_FLAGS.
	(cpu_flags): Add CpuAVX512_4FMAPS.
	(opcode_modifiers): Add ImplicitQuadGroup modifier.
	* i386-opc.h (AVX512_4FMAP): New.
	(i386_cpu_flags): Add cpuavx512_4fmaps.
	(ImplicitQuadGroup): New.
	(i386_opcode_modifier): Add implicitquadgroup.
	* i386-opc.tbl: Add Intel AVX512_4FMAPS instructions.
	* i386-init.h: Regenerate.
	* i386-tbl.h: Ditto.
 2016-11-02 12:25:34 -07:00
H.J. Lu
b5cefccad8 X86: Remove pcommit instruction 
Remove x86 pcommit instruction support, which has been deprecated:

https://software.intel.com/en-us/blogs/2016/09/12/deprecate-pcommit-instruction

gas/

	* config/tc-i386.c (cpu_arch): Remove .pcommit.
	* doc/c-i386.texi: Likewise.
	* testsuite/gas/i386/i386.exp: Remove pcommit tests.
	* testsuite/gas/i386/pcommit-intel.d: Removed.
	* testsuite/gas/i386/pcommit.d: Likewise.
	* testsuite/gas/i386/pcommit.s: Likewise.
	* testsuite/gas/i386/x86-64-pcommit-intel.d: Likewise.
	* testsuite/gas/i386/x86-64-pcommit.d: Likewise.
	* testsuite/gas/i386/x86-64-pcommit.s: Likewise.

opcodes/

	* i386-dis.c (PREFIX_RM_0_0FAE_REG_7): Removed.
	(prefix_table): Remove the PREFIX_RM_0_0FAE_REG_7 entry.
	(rm_table): Update the RM_0FAE_REG_7 entry.
	* i386-gen.c (cpu_flag_init): Remove CPU_PCOMMIT_FLAGS.
	(cpu_flags): Remove CpuPCOMMIT.
	* i386-opc.h (CpuPCOMMIT): Removed.
	(i386_cpu_flags): Remove cpupcommit.
	* i386-opc.tbl: Remove pcommit.
	* i386-init.h: Regenerated.
	* i386-tbl.h: Likewise.
 2016-10-21 12:16:32 -07:00
H.J. Lu
6b40c46231 X86: Add ptwrite instruction 
Implement ptwrite instruction defined in Intel64 and IA-32 Architectures
Software Developer’s Manual, June 2016.

gas/

	* config/tc-i386.c (cpu_arch): Add .ptwrite.
	* doc/c-i386.texi: Document ptwrite and .ptwrite.
	* testsuite/gas/i386/i386.exp: Run ptwrite, ptwrite-intel,
	x86-64-ptwrite and x86-64-ptwrite-intel.
	* testsuite/gas/i386/ptwrite-intel.d: New file.
	* testsuite/gas/i386/ptwrite.d: Likewise.
	* testsuite/gas/i386/ptwrite.s: Likewise.
	* testsuite/gas/i386/x86-64-ptwrite-intel.d: Likewise.
	* testsuite/gas/i386/x86-64-ptwrite.d: Likewise.
	* testsuite/gas/i386/x86-64-ptwrite.s: Likewise.

opcodes/

	* i386-dis.c (PREFIX_MOD_0_0FAE_REG_4): New.
	(PREFIX_MOD_3_0FAE_REG_4): Likewise.
	(prefix_table): Add PREFIX_MOD_0_0FAE_REG_4 and
	PREFIX_MOD_3_0FAE_REG_4.
	(mod_table): Use PREFIX_MOD_0_0FAE_REG_4 and
	PREFIX_MOD_3_0FAE_REG_4.
	* i386-gen.c (cpu_flag_init): Add CPU_PTWRITE_FLAGS.
	(cpu_flags): Add CpuPTWRITE.
	* i386-opc.h (CpuPTWRITE): New.
	(i386_cpu_flags): Add cpuptwrite.
	* i386-opc.tbl: Add ptwrite instruction.
	* i386-init.h: Regenerated.
	* i386-tbl.h: Likewise.
 2016-08-24 15:29:39 -07:00
H.J. Lu
1848e56734 Update x86 CPU_XXX_FLAGS handling 
Support defining CPU_XXX_FLAGS with other CPU_XXX_FLAGS.  Update
CPU_XXX_FLAGS to enable more bits like x87 and SYSCALL.  Don't enable
MMX when enabling SSE, AVX or AVX512.  Don't disable AVX nor AVX512 when
disabling SSE.  Don't disable AVX512 when disabling AVX.  Disable F16C,
FMA, FMA4 and XOP when disabling AVX.  Add 87, no287, no387, no687,
nosse2, nosse3, nossse3, nosse4.1, nosse4.2, nosse4 and noavx2 directives
to x86 assembler.

TODO: Add more .noXXX, like .noavx512f, directives to x86 assembler.

gas/

	PR gas/20145
	* config/tc-i386.c (cpu_arch): Add 687.
	(cpu_noarch): Add no287, no387, no687, nosse2, nosse3, nossse3,
	nosse4.1, nosse4.2, nosse4 and noavx2.
	(parse_real_register): Check cpuregmmx instead of cpummx for MMX
	register.  Check cpuregxmm instead of cpusse for XMM register.
	Check cpuregymm instead of cpuavx for YMM register.  Check
	cpuregzmm/cpuregmask instead of cpuavx512f for ZMMM/mask register.
	* doc/c-i386.texi: Mention 687, no287, no387, no687, nosse2,
	nosse3, nossse3, nosse4.1, nosse4.2, nosse4 and noavx2.
	* testsuite/gas/i386/arch-10-prefetchw.d (as): Add mmx.
	* testsuite/gas/i386/arch-10.d (as): Likewise.
	* testsuite/gas/i386/arch-11.s: Add ".arch .mmx".
	* testsuite/gas/i386/i386.exp: Pass mmx to assembler for
	arch-10-3 and arch-10-4.  Run no87-3, nosse-4, nosse-5, noavx-3
	and noavx-4.
	* testsuite/gas/i386/no87-3.l: New file.
	* testsuite/gas/i386/no87-3.s: Likewise.
	* testsuite/gas/i386/noavx-3.l: Likewise.
	* testsuite/gas/i386/noavx-3.s: Likewise.
	* testsuite/gas/i386/noavx-4.d: Likewise.
	* testsuite/gas/i386/noavx-4.s: Likewise.
	* testsuite/gas/i386/nosse-4.l: Likewise.
	* testsuite/gas/i386/nosse-4.s: Likewise.
	* testsuite/gas/i386/nosse-5.d: Likewise.
	* testsuite/gas/i386/nosse-5.s: Likewise.

opcodes/

	PR gas/20145
	* i386-gen.c (cpu_flag_init): Update CPU_XXX_FLAGS.  Remove
	CpuMMX from CPU_SSE_FLAGS.  Remove AVX and AVX512 bits from
	CPU_ANY_SSE_FLAGS.  Remove AVX512 bits from CPU_ANY_AVX_FLAGS.
	Add CPU_XSAVE_FLAGS to CPU_XSAVEOPT_FLAGS, CPU_XSAVE_FLAGS and
	CpuXSAVEC.  Add CPU_AVX_FLAGS to CpuF16C.  Remove CpuMMX from
	CPU_AVX512F_FLAGS, CPU_AVX512CD_FLAGS, CPU_AVX512ER_FLAGS,
	CPU_AVX512PF_FLAGS, CPU_AVX512DQ_FLAGS and CPU_AVX512BW_FLAGS.
	Add CPU_SSE2_FLAGS to CPU_SHA_FLAGS.   Add CPU_ANY_287_FLAGS,
	CPU_ANY_387_FLAGS, CPU_ANY_687_FLAGS, CPU_ANY_SSE2_FLAGS,
	CPU_ANY_SSE3_FLAGS, CPU_ANY_SSSE3_FLAGS, CPU_ANY_SSE4_1_FLAGS,
	CPU_ANY_SSE4_2_FLAGS and CPU_ANY_AVX2_FLAGS.  Enable CpuRegMMX
	for MMX.  Enable CpuRegXMM for SSE, AVX and AVX512.  Enable
	CpuRegYMM for AVX and AVX512VL,  Enable CpuRegZMM and
	CpuRegMask for AVX512.
	(cpu_flags): Add CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM
	and CpuRegMask.
	(set_bitfield_from_cpu_flag_init): New function.
	(set_bitfield): Remove const on f.  Call
	set_bitfield_from_cpu_flag_init to handle CPU_XXX_FLAGS.
	* i386-opc.h (CpuRegMMX): New.
	(CpuRegXMM): Likewise.
	(CpuRegYMM): Likewise.
	(CpuRegZMM): Likewise.
	(CpuRegMask): Likewise.
	(i386_cpu_flags): Add cpuregmmx, cpuregxmm, cpuregymm, cpuregzmm
	and cpuregmask.
	* i386-init.h: Regenerated.
	* i386-tbl.h: Likewise.
 2016-05-27 10:05:57 -07:00
H.J. Lu
e92bae6260 Replace CpuAMD64/CpuIntel64 with AMD64/Intel64 
AMD64 vs CpuIntel64 ISA should be handled similar as AT&T vs Intel
syntax.  Since cpu_flags isn't sorted by position, we need to check
the whole cpu_flags array for the maximum position when verifying
CpuMax.

gas/

	PR gas/20154
	* config/tc-i386.c (cpu_flags_match): Don't set cpuamd64 nor
	cpuintel64.
	(match_template): Check Intel64/AMD64 ISA.

opcodes/

	PR gas/20154
	* i386-gen.c (cpu_flags): Remove CpuAMD64 and CpuIntel64.
	(opcode_modifiers): Add AMD64 and Intel64.
	(main): Properly verify CpuMax.
	* i386-opc.h (CpuAMD64): Removed.
	(CpuIntel64): Likewise.
	(CpuMax): Set to CpuNo64.
	(i386_cpu_flags): Remove cpuamd64 and cpuintel64.
	(AMD64): New.
	(Intel64): Likewise.
	(i386_opcode_modifier): Add amd64 and intel64.
	(i386-opc.tbl): Replace CpuAMD64/CpuIntel64 with AMD64/Intel64
	on call and jmp.
	* i386-init.h: Regenerated.
	* i386-tbl.h: Likewise.
 2016-05-27 08:03:17 -07:00
H.J. Lu
e89c5eaa72 Correct CpuMax in i386-opc.h 
CpuMax should be CpuIntel64, not CpuNo64.  i386-gen.c is updated to
verify that CpuMax is correct.  X86 assembler is updated to properly
set cpuamd64 and cpuintel64.

gas/

	PR gas/20154
	* config/tc-i386.c (intel64): New.
	(cpu_flags_match): Set cpuamd64 and cpuintel64.
	(md_parse_option): Set intel64 instead of cpuamd64 and
	cpuintel64.

opcodes/

	PR gas/20154
	* i386-gen.c (main): Fail if CpuMax is incorrect.
	* i386-opc.h (CpuMax): Set to CpuIntel64.
	* i386-tbl.h: Regenerated.
 2016-05-27 06:55:53 -07:00
Alexander Fomin
8bc526963e Enable Intel RDPID instruction. 
This patch enables Intel RDPID instruction described in Intel64 and
IA-32 Architectures Software Developer's Manual, April 2016.

gas/

	* config/tc-i386.c (cpu_arch): Add RDPID.
	* doc/c-i386.texi: Document RDPID.

gas/testsuite/

	* gas/i386/i386.exp: Run RDPID tests.
	* gas/i386/prefix.d: Adjust.
	* gas/i386/rdpid.s: New test.
	* gas/i386/rdpid.d: Ditto.
	* gas/i386/rdpid-intel.d: Ditto.
	* gas/i386/x86-64-rdpid.s: Ditto.
	* gas/i386/x86-64-rdpid.d: Ditto.
	* gas/i386/x86-64-rdpid-intel.d: Ditto.

opcodes/

	* i386-dis.c (prefix_table): Add RDPID instruction.
	* i386-gen.c (cpu_flag_init): Add RDPID flag.
	(cpu_flags): Add RDPID bitfield.
	* i386-opc.h (enum): Add RDPID element.
	(i386_cpu_flags): Add RDPID field.
	* i386-opc.tbl: Add RDPID instruction.
	* i386-init.h: Regenerate.
	* i386-tbl.h: Regenerate.
 2016-05-10 21:38:39 +03:00
Alan Modra
6f2750feaf Copyright update for binutils 2016-01-01 23:00:01 +10:30
H.J. Lu
8eab413676 Implement Intel OSPKE instructions 
This patch implements Intel OSPKE instructions documented in Intel64
and IA-32 Architectures Software Developer’s Manual Volume 2, September
2015.

gas/testsuite/

	* gas/i386/i386.exp: Run ospke and x86-64-ospke.
	* gas/i386/ospke.d: New file.
	* gas/i386/ospke.s: Likewise.
	* gas/i386/x86-64-ospke.d: Likewise.

opcodes/

	* i386-dis.c (MOD_0F01_REG_5): New.
	(RM_0F01_REG_5): Likewise.
	(reg_table): Use MOD_0F01_REG_5.
	(mod_table): Add MOD_0F01_REG_5.
	(rm_table): Add RM_0F01_REG_5.
	* i386-gen.c (cpu_flag_init): Add CPU_OSPKE_FLAGS.
	(cpu_flags): Add CpuOSPKE.
	* i386-opc.h (CpuOSPKE): New.
	(i386_cpu_flags): Add cpuospke.
	* i386-opc.tbl: Add rdpkru and wrpkru instructions.
	* i386-init.h: Regenerated.
	* i386-tbl.h: Likewise.
 2015-12-09 08:01:57 -08:00
H.J. Lu
43e65147c0 Remove trailing spaces in opcodes 2015-08-12 04:45:07 -07:00
Amit Pawar
9916071f8d Add support for monitorx/mwaitx instructions 
gas/

	* config/tc-i386.c (cpu_arch): Add .mwaitx.
	(process_immext): Check operands for monitorx/mwaitx instructions.
	* doc/c-i386.texi: Document mwaitx.

gas/testsuite/

	* gas/i386/i386.exp: Add new mwaitx test cases.
	* gas/i386/mwaitx.s: New.
	* gas/i386/mwaitx-bdver4.d: New.
	* gas/i386/x86-64-mwaitx.s: New.
	* gas/i386/x86-64-mwaitx-bdver4.d: New.
	* gas/i386/mwaitx-reg.s: New.
	* gas/i386/mwaitx-reg.l: New.
	* gas/i386/x86-64-mwaitx-reg.l: New.
	* gas/i386/x86-64-mwaitx-reg.s: New.
	* gas/i386/arch-13.s: Updated.
	* gas/i386/arch-13.d: Updated.
	* gas/i386/arch-13-znver1.d: Updated.
	* gas/i386/x86-64-arch-3.s: Updated.
	* gas/i386/x86-64-arch-3.d: Updated.
	* gas/i386/x86-64-arch-3-znver1.d: Updated.

opcodes/

	* i386-dis.c (OP_Mwaitx): New.
	(rm_table): Add monitorx/mwaitx.
	* i386-gen.c (cpu_flag_init): Add CpuMWAITX to CPU_BDVER4_FLAGS
	and CPU_ZNVER1_FLAGS.  Add CPU_MWAITX_FLAGS.
	(operand_type_init): Add CpuMWAITX.
	* i386-opc.h (CpuMWAITX): New.
	(i386_cpu_flags): Add cpumwaitx.
	* i386-opc.tbl: Add monitorx and mwaitx.
	* i386-init.h: Regenerated.
	* i386-tbl.h: Likewise.
 2015-06-30 07:50:12 -07:00
H.J. Lu
5db04b0965 Support AMD64/Intel ISAs in assembler/disassembler 
AMD64 spec and Intel64 spec differ in direct unconditional branches in
64-bit mode.  AMD64 supports direct unconditional branches with 16-bit
offset via the data size prefix, which truncates RIP to 16 bits, while
the data size prefix is ignored by Intel64.

This patch adds -mamd64/-mintel64 option to x86-64 assembler and
-Mamd64/-Mintel64 option to x86-64 disassembler.  The most permissive
ISA, which is AMD64, is the default.

GDB can add an option, similar to

(gdb) help set disassembly-flavor
Set the disassembly flavor.
The valid values are "att" and "intel", and the default value is "att".

to select which ISA to disassemble.

binutils/

	PR binutis/18386
	* doc/binutils.texi: Document -Mamd64 and -Mintel64.

gas/

	PR binutis/18386
	* config/tc-i386.c (OPTION_MAMD64): New.
	(OPTION_MINTEL64): Likewise.
	(md_longopts): Add -mamd64 and -mintel64.
	(md_parse_option): Handle OPTION_MAMD64 and OPTION_MINTEL64.
	(md_show_usage): Add -mamd64 and -mintel64.
	* doc/c-i386.texi: Document -mamd64 and -mintel64.

gas/testsuite/

	PR binutis/18386
	* gas/i386/i386.exp: Run x86-64-branch-2 and x86-64-branch-3.
	* gas/i386/x86-64-branch.d: Also pass -Mintel64 to objdump.
	* gas/i386/ilp32/x86-64-branch.d: Likewise.
	* gas/i386/x86-64-branch-2.d: New file.
	* gas/i386/x86-64-branch-2.s: Likewise.
	* gas/i386/x86-64-branch-3.l: Likewise.
	* gas/i386/x86-64-branch-3.s: Likewise.

ld/testsuite/

	PR binutis/18386
	* ld-x86-64/tlsgdesc.dd: Also pass -Mintel64 to objdump.
	* ld-x86-64/tlspic.dd: Likewise.
	* ld-x86-64/x86-64.exp (x86_64tests): Also pass -Mintel64 to
	objdump for tlspic.dd and tlsgdesc.dd.

opcodes/

	PR binutis/18386
	* i386-dis.c: Add comments for '@'.
	(x86_64_table): Use '@' on call/jmp for X86_64_E8/X86_64_E9.
	(enum x86_64_isa): New.
	(isa64): Likewise.
	(print_i386_disassembler_options): Add amd64 and intel64.
	(print_insn): Handle amd64 and intel64.
	(putop): Handle '@'.
	(OP_J): Don't ignore the operand size prefix for AMD64 in 64-bit.
	* i386-gen.c (cpu_flags): Add CpuAMD64 and CpuIntel64.
	* i386-opc.h (AMD64): New.
	(CpuIntel64): Likewise.
	(i386_cpu_flags): Add cpuamd64 and cpuintel64.
	* i386-opc.tbl: Add direct call/jmp with Disp16|Disp32 for AMD64.
	Mark direct call/jmp without Disp16|Disp32 as Intel64.
	* i386-init.h: Regenerated.
	* i386-tbl.h: Likewise.
 2015-05-15 09:48:10 -07:00
H.J. Lu
7b6d09fbc6 Add Intel MCU support to opcodes 
* configure.ac: Support bfd_iamcu_arch.
	* disassemble.c (disassembler): Support bfd_iamcu_arch.
	* i386-gen.c (cpu_flag_init): Add CPU_IAMCU_FLAGS and
	CPU_IAMCU_COMPAT_FLAGS.
	(cpu_flags): Add CpuIAMCU.
	* i386-opc.h (CpuIAMCU): New.
	(i386_cpu_flags): Add cpuiamcu.
	* configure: Regenerated.
	* i386-init.h: Likewise.
	* i386-tbl.h: Likewise.
 2015-05-11 10:48:21 -07:00
Ganesh Gopalasubramanian
029f352261 Add znver1 processor 2015-03-17 21:49:15 +05:30
Alan Modra
b90efa5b79 ChangeLog rotatation and copyright year update 2015-01-02 00:53:45 +10:30
Ilya Tocar
14f195c9a0 Add AVX512VBMI instructions 
gas/

	* config/tc-i386.c (cpu_arch): Add .avx512vbmi.
	* doc/c-i386.texi: Document it.

opcodes/

	* i386-dis-evex.c (evex_table): Add vpermi2b, vpermt2b, vpermb,
	vpmultishiftqb.
	* i386-dis.c (PREFIX enum): Add PREFIX_EVEX_0F3883, EVEX_W_0F3883_P_2.
	* i386-gen.c (cpu_flag_init): Add CPU_AVX512VBMI_FLAGS.
	(cpu_flags): Add CpuAVX512VBMI.
	* i386-opc.h (enum): Add CpuAVX512VBMI.
	(i386_cpu_flags): Add cpuavx512vbmi.
	* i386-opc.tbl: Add vpmadd52luq, vpmultishiftqb, vpermb, vpermi2b,
	vpermt2b.
	* i386-init.h: Regenerated.
	* i386-tbl.h: Likewise.

/gas/testsuite/

	* gas/i386/i386.exp: Run new tests.
	* gas/i386/avx512vbmi-intel.d: New file.
	* gas/i386/avx512vbmi.d: Likewise.
	* gas/i386/avx512vbmi.s: Likewise.
	* gas/i386/avx512vbmi_vl-intel.d: Likewise.
	* gas/i386/avx512vbmi_vl.d: Likewise.
	* gas/i386/avx512vbmi_vl.s: Likewise.
	* gas/i386/x86-64-avx512vbmi-intel.d: Likewise.
	* gas/i386/x86-64-avx512vbmi.d: Likewise.
	* gas/i386/x86-64-avx512vbmi.s: Likewise.
	* gas/i386/x86-64-avx512vbmi_vl-intel.d: Likewise.
	* gas/i386/x86-64-avx512vbmi_vl.d: Likewise.
	* gas/i386/x86-64-avx512vbmi_vl.s: Likewise.
 2014-11-17 06:03:41 -08:00
Ilya Tocar
2cc1b5aad8 Add AVX512IFMA instructions 
gas/

	* config/tc-i386.c (cpu_arch): Add .avx512ifma.
	* doc/c-i386.texi: Document it.

opcodes/

	* i386-dis-evex.c (evex_table): Add vpmadd52luq, vpmadd52huq.
	* i386-dis.c (PREFIX enum): Add PREFIX_EVEX_0F38B4,
	PREFIX_EVEX_0F38B5.
	* i386-gen.c (cpu_flag_init): Add CPU_AVX512IFMA_FLAGS.
	(cpu_flags): Add CpuAVX512IFMA.
	* i386-opc.h (enum): Add CpuAVX512IFMA.
	(i386_cpu_flags): Add cpuavx512ifma.
	* i386-opc.tbl: Add vpmadd52huq, vpmadd52luq.
	* i386-init.h: Regenerated.
	* i386-tbl.h: Likewise.

/gas/testsuite/

	* gas/i386/i386.exp: Run new tests.
	* gas/i386/avx512ifma-intel.d: New file.
	* gas/i386/avx512ifma.d: Likewise.
	* gas/i386/avx512ifma.s: Likewise.
	* gas/i386/avx512ifma_vl-intel.d: Likewise.
	* gas/i386/avx512ifma_vl.d: Likewise.
	* gas/i386/avx512ifma_vl.s: Likewise.
	* gas/i386/x86-64-avx512ifma-intel.d: Likewise.
	* gas/i386/x86-64-avx512ifma.d: Likewise.
	* gas/i386/x86-64-avx512ifma.s: Likewise.
	* gas/i386/x86-64-avx512ifma_vl-intel.d: Likewise.
	* gas/i386/x86-64-avx512ifma_vl.d: Likewise.
	* gas/i386/x86-64-avx512ifma_vl.s: Likewise.
 2014-11-17 06:03:24 -08:00
Ilya Tocar
9d8596f079 Add pcommit instruction 
gas/

	* config/tc-i386.c (cpu_arch): Add .pcommit.
	* doc/c-i386.texi: Document it.

/opcodes

	* i386-dis.c (PREFIX enum): Add PREFIX_RM_0_0FAE_REG_7.
	(prefix_table): Add pcommit.
	* i386-gen.c (cpu_flag_init): Add CPU_PCOMMIT_FLAGS.
	(cpu_flags): Add CpuPCOMMIT.
	* i386-opc.h (enum): Add CpuPCOMMIT.
	(i386_cpu_flags): Add cpupcommit.
	* i386-opc.tbl: Add pcommit.
	* i386-init.h: Regenerated.
	* i386-tbl.h: Likewise.

/gas/testsuite/

	* gas/i386/i386.exp: Run new tests.
	* gas/i386/pcommit-intel.d: New file.
	* gas/i386/pcommit.d: Likewise.
	* gas/i386/pcommit.s: Likewise.
	* gas/i386/x86-64-pcommit-intel.d: Likewise.
	* gas/i386/x86-64-pcommit.d: Likewise.
	* gas/i386/x86-64-pcommit.s: Likewise.
 2014-11-17 05:56:47 -08:00
Ilya Tocar
c5e7287a1a Add clwb instruction 
gas/

	* config/tc-i386.c (cpu_arch): Add .clwb.
	* doc/c-i386.texi: Document it.

opcodes/
	* i386-dis.c (PREFIX enum): Add PREFIX_0FAE_REG_6.
	(prefix_table): Add clwb.
	* i386-gen.c (cpu_flag_init): Add CPU_CLWB_FLAGS.
	(cpu_flags): Add CpuCLWB.
	* i386-opc.h (enum): Add CpuCLWB.
	(i386_cpu_flags): Add cpuclwb.
	* i386-opc.tbl: Add clwb.
	* i386-init.h: Regenerated.
	* i386-tbl.h: Likewise.

gas/testsuite/

	* gas/i386/i386.exp: Run new tests.
	* gas/i386/clwb-intel.d: New file.
	* gas/i386/clwb.d: Likewise.
	* gas/i386/clwb.s: Likewise.
	* gas/i386/x86-64-clwb-intel.d: Likewise.
	* gas/i386/x86-64-clwb.d: Likewise.
	* gas/i386/x86-64-clwb.s: Likewise.
 2014-11-17 05:56:37 -08:00
Ilya Tocar
90a915bf0c Add AVX512DQ instructions and their AVX512VL variants. 
gas/

	* config/tc-i386.c (cpu_arch): Add .avx512dq, CPU_AVX512DQ_FLAGS.
	* doc/c-i386.texi: Document avx512dq/.avx512dq.

gas/testsuite/

	* gas/i386/avx512dq-intel.d: New.
	* gas/i386/avx512dq.d: New.
	* gas/i386/avx512dq.s: New.
	* gas/i386/avx512dq_vl-intel.d: New.
	* gas/i386/avx512dq_vl.d: New.
	* gas/i386/avx512dq_vl.s: New.
	* gas/i386/i386.exp: Run new AVX-512 tests.
	* gas/i386/x86-64-avx512dq-intel.d: New.
	* gas/i386/x86-64-avx512dq.d: New.
	* gas/i386/x86-64-avx512dq.s: New.
	* gas/i386/x86-64-avx512dq_vl-intel.d: New.
	* gas/i386/x86-64-avx512dq_vl.d: New.
	* gas/i386/x86-64-avx512dq_vl.s: New.

opcodes/

	* i386-dis-evex.h: Updated.
	* i386-dis.c (PREFIX enum): Add PREFIX_EVEX_0F54, PREFIX_EVEX_0F55,
	PREFIX_EVEX_0F56, PREFIX_EVEX_0F57, PREFIX_EVEX_0F3A16,
	PREFIX_EVEX_0F3A22, PREFIX_EVEX_0F3A50, PREFIX_EVEX_0F3A51,
	PREFIX_EVEX_0F3A56, PREFIX_EVEX_0F3A57, PREFIX_EVEX_0F3A66,
	PREFIX_EVEX_0F3A67.
	(VEX_LEN enum): Add VEX_LEN_0F92_P_2, VEX_LEN_0F93_P_2,
	VEX_W_0F92_P_2_LEN_0, VEX_W_0F93_P_2_LEN_0.
	(VEX_W enum): Add EVEX_W_0F54_P_0, EVEX_W_0F54_P_2, EVEX_W_0F55_P_0,
	EVEX_W_0F55_P_2, EVEX_W_0F56_P_0, EVEX_W_0F56_P_2, EVEX_W_0F57_P_0,
	EVEX_W_0F57_P_2, EVEX_W_0F78_P_2, EVEX_W_0F79_P_2, EVEX_W_0F7A_P_2,
	EVEX_W_0F7B_P_2, EVEX_W_0F3838_P_1, EVEX_W_0F3839_P_1,
	EVEX_W_0F3A16_P_2, EVEX_W_0F3A22_P_2, EVEX_W_0F3A50_P_2,
	EVEX_W_0F3A51_P_2, EVEX_W_0F3A56_P_2, EVEX_W_0F3A57_P_2,
	EVEX_W_0F3A66_P_2, EVEX_W_0F3A67_P_2.
	(prefix_table): Add entries for new instructions.
	(vex_len_table): Ditto.
	(vex_w_table): Ditto.
	(OP_E_memory): Update xmmq_mode handling.
	* i386-gen.c (cpu_flag_init): Add CPU_AVX512DQ_FLAGS.
	(cpu_flags): Add CpuAVX512DQ.
	* i386-init.h: Regenerared.
	* i386-opc.h (CpuAVX512DQ): New.
	(i386_cpu_flags): Add cpuavx512dq.
	* i386-opc.tbl: Add AVX512DQ instructions.
	* i386-tbl.h: Regenerate.
 2014-07-22 10:23:49 -07:00
Ilya Tocar
1ba585e8f4 Add support for AVX512BW instructions and their AVX512VL versions. 
gas/

	* config/tc-i386.c (cpu_arch): Add .avx512bw, CPU_AVX512BW_FLAGS.
	* doc/c-i386.texi: Document avx512bw/.avx512bw.

gas/testsuite/

	* gas/i386/avx512bw-intel.d: New.
	* gas/i386/avx512bw-opts-intel.d: New.
	* gas/i386/avx512bw-opts.d: New.
	* gas/i386/avx512bw-opts.s: New.
	* gas/i386/avx512bw-wig.s: New.
	* gas/i386/avx512bw-wig1-intel.d: New.
	* gas/i386/avx512bw-wig1.d: New.
	* gas/i386/avx512bw.d: New.
	* gas/i386/avx512bw.s: New.
	* gas/i386/avx512bw_vl-intel.d: New.
	* gas/i386/avx512bw_vl-opts-intel.d: New.
	* gas/i386/avx512bw_vl-opts.d: New.
	* gas/i386/avx512bw_vl-opts.s: New.
	* gas/i386/avx512bw_vl-wig.s: New.
	* gas/i386/avx512bw_vl-wig1-intel.d: New.
	* gas/i386/avx512bw_vl-wig1.d: New.
	* gas/i386/avx512bw_vl.d: New.
	* gas/i386/avx512bw_vl.s: New.
	* gas/i386/i386.exp: Run new AVX-512 tests.
	* gas/i386/x86-64-avx512bw-intel.d: New.
	* gas/i386/x86-64-avx512bw-opts-intel.d: New.
	* gas/i386/x86-64-avx512bw-opts.d: New.
	* gas/i386/x86-64-avx512bw-opts.s: New.
	* gas/i386/x86-64-avx512bw-wig.s: New.
	* gas/i386/x86-64-avx512bw-wig1-intel.d: New.
	* gas/i386/x86-64-avx512bw-wig1.d: New.
	* gas/i386/x86-64-avx512bw.d: New.
	* gas/i386/x86-64-avx512bw.s: New.
	* gas/i386/x86-64-avx512bw_vl-intel.d: New.
	* gas/i386/x86-64-avx512bw_vl-opts-intel.d: New.
	* gas/i386/x86-64-avx512bw_vl-opts.d: New.
	* gas/i386/x86-64-avx512bw_vl-opts.s: New.
	* gas/i386/x86-64-avx512bw_vl-wig.s: New.
	* gas/i386/x86-64-avx512bw_vl-wig1-intel.d: New.
	* gas/i386/x86-64-avx512bw_vl-wig1.d: New.
	* gas/i386/x86-64-avx512bw_vl.d: New.
	* gas/i386/x86-64-avx512bw_vl.s: New.

opcodes/

	* i386-dis-evex.h: Add new instructions (prefixes bellow).
	* i386-dis.c (fetch_data): Add EdqwS, Edb, Edw, MaskBDE.
	(enum): Add dqw_swap_mode, db_mode, dw_mode, mask_bd_mode, REG_EVEX_0F71.
	(PREFIX enum): Add PREFIX_VEX_0F4A, PREFIX_VEX_0F99, PREFIX_VEX_0F3A31,
	PREFIX_VEX_0F3A33, PREFIX_EVEX_0F60, PREFIX_EVEX_0F61, PREFIX_EVEX_0F63,
	PREFIX_EVEX_0F64, PREFIX_EVEX_0F65, PREFIX_EVEX_0F67, PREFIX_EVEX_0F68,
	PREFIX_EVEX_0F69, PREFIX_EVEX_0F6B, PREFIX_EVEX_0F71_REG_2, PREFIX_EVEX_0F71_REG_4,
	PREFIX_EVEX_0F71_REG_6, PREFIX_EVEX_0F73_REG_3, PREFIX_EVEX_0F73_REG_7,
	PREFIX_EVEX_0F74, PREFIX_EVEX_0F75, PREFIX_EVEX_0FC4, PREFIX_EVEX_0FC5,
	PREFIX_EVEX_0FD1, PREFIX_EVEX_0FD5, PREFIX_EVEX_0FD8, PREFIX_EVEX_0FD9,
	PREFIX_EVEX_0FDA, PREFIX_EVEX_0FDC, PREFIX_EVEX_0FDD, PREFIX_EVEX_0FDE,
	PREFIX_EVEX_0FE0, PREFIX_EVEX_0FE1, PREFIX_EVEX_0FE3, PREFIX_EVEX_0FE4,
	PREFIX_EVEX_0FE5, PREFIX_EVEX_0FE8, PREFIX_EVEX_0FE9, PREFIX_EVEX_0FEA,
	PREFIX_EVEX_0FEC, PREFIX_EVEX_0FED, PREFIX_EVEX_0FEE, PREFIX_EVEX_0FF1,
	PREFIX_EVEX_0FF5, PREFIX_EVEX_0FF6, PREFIX_EVEX_0FF8, PREFIX_EVEX_0FF9,
	PREFIX_EVEX_0FFC, PREFIX_EVEX_0FFD, PREFIX_EVEX_0F3800, PREFIX_EVEX_0F3804,
	PREFIX_EVEX_0F380B, PREFIX_EVEX_0F3810, PREFIX_EVEX_0F381C, PREFIX_EVEX_0F381D,
	PREFIX_EVEX_0F3820, PREFIX_EVEX_0F3826, PREFIX_EVEX_0F382B, PREFIX_EVEX_0F3830,
	PREFIX_EVEX_0F3838, PREFIX_EVEX_0F383C, PREFIX_EVEX_0F383E, PREFIX_EVEX_0F3866,
	PREFIX_EVEX_0F3875, PREFIX_EVEX_0F3878, PREFIX_EVEX_0F3879, PREFIX_EVEX_0F387A,
	PREFIX_EVEX_0F387B, PREFIX_EVEX_0F387D, PREFIX_EVEX_0F388D, PREFIX_EVEX_0F3A0F,
	PREFIX_EVEX_0F3A14, PREFIX_EVEX_0F3A15, PREFIX_EVEX_0F3A20, PREFIX_EVEX_0F3A3E,
	PREFIX_EVEX_0F3A3F, PREFIX_EVEX_0F3A42.
	(VEX_LEN enum): Add VEX_LEN_0F41_P_2, VEX_LEN_0F42_P_2, VEX_LEN_0F44_P_2,
	VEX_LEN_0F45_P_2, VEX_LEN_0F46_P_2, VEX_LEN_0F47_P_2, VEX_LEN_0F4A_P_0,
	VEX_LEN_0F4A_P_2, VEX_LEN_0F4B_P_0, VEX_LEN_0F90_P_2, VEX_LEN_0F91_P_2,
	VEX_LEN_0F92_P_3, VEX_LEN_0F93_P_3, VEX_LEN_0F98_P_2, VEX_LEN_0F99_P_0,
	VEX_LEN_0F99_P_2, VEX_LEN_0F3A31_P_2, VEX_LEN_0F3A33_P_2, VEX_W_0F41_P_2_LEN_1,
	VEX_W_0F42_P_2_LEN_1, VEX_W_0F44_P_2_LEN_0, VEX_W_0F45_P_2_LEN_1,
	VEX_W_0F46_P_2_LEN_1, VEX_W_0F47_P_2_LEN_1, VEX_W_0F4A_P_0_LEN_1,
	VEX_W_0F4A_P_2_LEN_1, VEX_W_0F4B_P_0_LEN_1, VEX_W_0F90_P_2_LEN_0,
	VEX_W_0F91_P_2_LEN_0, VEX_W_0F92_P_3_LEN_0, VEX_W_0F93_P_3_LEN_0,
	VEX_W_0F98_P_2_LEN_0, VEX_W_0F99_P_0_LEN_0, VEX_W_0F99_P_2_LEN_0,
	VEX_W_0F3A31_P_2_LEN_0, VEX_W_0F3A33_P_2_LEN_0.
	(VEX_W enum): Add EVEX_W_0F6B_P_2, EVEX_W_0F6F_P_3, EVEX_W_0F7F_P_3,
	EVEX_W_0F3810_P_1, EVEX_W_0F3810_P_2, EVEX_W_0F3811_P_2, EVEX_W_0F3812_P_2,
	EVEX_W_0F3820_P_1, EVEX_W_0F3826_P_1, EVEX_W_0F3826_P_2, EVEX_W_0F3828_P_1,
	EVEX_W_0F3829_P_1, EVEX_W_0F382B_P_2, EVEX_W_0F3830_P_1, EVEX_W_0F3866_P_2,
	EVEX_W_0F3875_P_2, EVEX_W_0F3878_P_2, EVEX_W_0F3879_P_2, EVEX_W_0F387A_P_2,
	EVEX_W_0F387B_P_2, EVEX_W_0F387D_P_2, EVEX_W_0F388D_P_2, EVEX_W_0F3A3E_P_2,
	EVEX_W_0F3A3F_P_2, EVEX_W_0F3A42_P_2.
	(prefix_table): Add entries for new instructions.
	(vex_table) : Ditto.
	(vex_len_table): Ditto.
	(vex_w_table): Ditto.
	(intel_operand_size): Add db_mode, dw_mode, dqw_swap_mode,
	mask_bd_mode handling.
	(OP_E_register): Add dqw_swap_mode, dw_mode, db_mode, mask_bd_mode
	handling.
	(OP_E_memory): Add dqw_mode, dw_mode, dqw_swap_mode, dqb_mode, db_mode
	handling.
	(OP_G): Add db_mode, dw_mode, dqw_swap_mode, mask_bd_mode handling.
	(OP_EX): Add dqw_swap_mode handling.
	(OP_VEX): Add mask_bd_mode handling.
	(OP_Mask): Add mask_bd_mode handling.
	* i386-gen.c (cpu_flag_init): Add CPU_AVX512BW_FLAGS.
	(cpu_flags): Add CpuAVX512BW.
	* i386-init.h: Regenerated.
	* i386-opc.h (CpuAVX512BW): New.
	(i386_cpu_flags): Add cpuavx512bw.
	* i386-opc.tbl: Add AVX512BW instructions.
	* i386-tbl.h: Regenerate.
 2014-07-22 10:23:44 -07:00
Ilya Tocar
b28d1bda54 Add support for AVX512VL. Add AVX512VL versions of AVX512F instructions. 
gas/

	* config/tc-i386.c (cpu_arch): Add .avx512vl, CPU_AVX512VL_FLAGS.
	(build_vex_prefix): Don't abort on VEX.W.
	(check_VecOperands): Support BROADCAST_1TO4 and BROADCAST_1TO2.
	(check_VecOperations): Ditto.
	* doc/c-i386.texi: Document avx512vl/.avx512vl.

gas/testsuite/

	* gas/i386/avx512f_vl-intel.d: New.
	* gas/i386/avx512f_vl-opts-intel.d: New.
	* gas/i386/avx512f_vl-opts.d: New.
	* gas/i386/avx512f_vl-opts.s: New.
	* gas/i386/avx512f_vl-wig.s: New.
	* gas/i386/avx512f_vl-wig1-intel.d: New.
	* gas/i386/avx512f_vl-wig1.d: New.
	* gas/i386/avx512f_vl.d: New.
	* gas/i386/avx512f_vl.s: New.
	* gas/i386/i386.exp: Run new AVX-512 tests.
	* gas/i386/x86-64-avx512f_vl-intel.d: New.
	* gas/i386/x86-64-avx512f_vl-opts-intel.d: New.
	* gas/i386/x86-64-avx512f_vl-opts.d: New.
	* gas/i386/x86-64-avx512f_vl-opts.s: New.
	* gas/i386/x86-64-avx512f_vl-wig.s: New.
	* gas/i386/x86-64-avx512f_vl-wig1-intel.d: New.
	* gas/i386/x86-64-avx512f_vl-wig1.d: New.
	* gas/i386/x86-64-avx512f_vl.d: New.
	* gas/i386/x86-64-avx512f_vl.s: New.

opcodes/

	* i386-dis.c (intel_operand_size): Support 128/256 length in
	vex_vsib_q_w_dq_mode.
	(OP_E_memory): Add ymmq_mode handling, handle new broadcast.
	* i386-gen.c (cpu_flag_init): Add CPU_AVX512VL_FLAGS.
	(cpu_flags): Add CpuAVX512VL.
	* i386-init.h: Regenerated.
	* i386-opc.h (CpuAVX512VL): New.
	(i386_cpu_flags): Add cpuavx512vl.
	(BROADCAST_1TO4, BROADCAST_1TO2): Define.
	* i386-opc.tbl: Add AVX512VL instructions.
	* i386-tbl.h: Regenerate.
 2014-07-22 10:23:40 -07:00
Ilya Tocar
2cf200a4c8 Add support for Intel SGX instructions 
Add Intel SGX instructions support to assembler and disassembler.

gas/

	* config/tc-i386.c (cpu_arch): Add .se1.
	* doc/c-i386.texi: Document .se1/se1.

gas/testsuite/

	* gas/i386/i386.exp: Run SE1 tests.
	* gas/i386/se1.d: New file.
	* gas/i386/se1.s: Ditto.
	* gas/i386/x86-64-se1.d: Ditto.
	* gas/i386/x86-64-se1.s: Ditto.

opcodes/

	* i386-dis.c (rm_table): Add encls, enclu.
	* i386-gen.c (cpu_flag_init): Add CPU_SE1_FLAGS,
	(cpu_flags): Add CpuSE1.
	* i386-opc.h (enum): Add CpuSE1.
	(i386_cpu_flags): Add cpuse1.
	* i386-opc.tbl: Add encls, enclu.
	* i386-init.h: Regenerated.
	* i386-tbl.h: Likewise.
 2014-04-04 08:24:47 -07:00
Alan Modra
4b95cf5c0c Update copyright years 2014-03-05 22:16:15 +10:30
Ilya Tocar
dcf893b581 Add support for CPUID PREFETCHWT1 
Latest AVX512 spec
http://download-software.intel.com/sites/default/files/managed/50/1a/319433-018.pdf
Has CPUID PREFETCHWT1 for prefetchwt1 instruction, which we list as AVX512PF.
This patch introduces CPUID PREFETCHWT1.

gas/

        * config/tc-i386.c (cpu_arch): Add .prefetchwt1.
        * doc/c-i386.texi: Document .prefetchwt1/prefetchwt1.

opcodes/

        * i386-gen.c (cpu_flag_init): Add CPU_PREFETCHWT1_FLAGS/
        (cpu_flags): Add CpuPREFETCHWT1.
        * i386-init.h: Regenerate.
        * i386-opc.h (CpuPREFETCHWT1): New.
        (i386_cpu_flags): Add cpuprefetchwt1.
        * i386-opc.tbl: Cahnge CPU of prefetchwt1 from CpuAVX512PF to CpuPREFETCHWT1.
        * i386-tbl.h: Regenerate.

gas/testsuite

        * gas/i386/avx512pf-intel.d: Remove prefetchwt1.
        * gas/i386/avx512pf.s: Ditto.
        * gas/i386/avx512pf.d: Ditto.
        * gas/i386/x86-64-avx512pf-intel.d: Ditto.
        * gas/i386/x86-64-avx512pf.s: Ditto.
        * gas/i386/x86-64-avx512pf.d: Ditto.
        * gas/i386/prefetchwt1-intel.d: New file.
        * gas/i386/prefetchwt1.s: Ditto.
        * gas/i386/prefetchwt1.d: Ditto.
        * gas/i386/x86-64-prefetchwt1-intel.d: Ditto.
        * gas/i386/x86-64-prefetchwt1.s: Ditto.
        * gas/i386/x86-64-prefetchwt1.d: Ditto.
 2014-02-21 08:04:00 -08:00