Commit Graph

8577 Commits

Author SHA1 Message Date
H.J. Lu
385e5b9039 Treat SHT_FINI_ARRAY and SHT_PREINIT_ARRAY as relocatable sections
Since SHT_FINI_ARRAY and SHT_PREINIT_ARRAY sections are relocatable,
this patch fixes readelf and adds a testcase.

binutils/

	* readelf.c (process_section_headers): Treat SHT_FINI_ARRAY and
	SHT_PREINIT_ARRAY as relocatable sections.

gas/

	* testsuite/gas/elf/elf.exp: Run section14.
	* testsuite/gas/elf/section14.d: New file.
	* testsuite/gas/elf/section14.s: Likewise.
2018-08-30 08:03:34 -07:00
Martin Aberg
df28970fcc sparc/leon: add support for partial write psr instruction
Partial write %PSR (PWRPSR) is a SPARC V8e option that allows the WRPSR
instruction to only affect the %PSR.ET field. When available it is enabled
by setting the rd field of the WRPSR instruction to a value other than 0.
For Leon processors with support for partial write %PSR (currently GR740
and GR716) the rd value must be 1.

opcodes/ChangeLog:

2018-08-29  Martin Aberg  <maberg@gaisler.com>

        * sparc-opc.c (sparc_opcodes): Add Leon specific partial write
        psr (PWRPSR) instruction.

gas/ChangeLog:

2018-08-29  Daniel Cederman  <cederman@gaisler.com>

        * testsuite/gas/sparc/leon.d: New test.
        * testsuite/gas/sparc/leon.s: New test.
        * testsuite/gas/sparc/sparc.exp: Execute the pwrpsr test.
2018-08-29 20:52:28 +02:00
Chenghua Xu
9108bc33b1 [MIPS] Add Loongson 2K1000 proccessor support.
bfd/
	* archures.c (bfd_architecture): New machine
	bfd_mach_mips_gs264e.
	* bfd-in2.h (bfd_architecture): Likewise.
	* cpu-mips.c (enum I_xxx): Likewise.
	(arch_info_struct): Likewise.
	* elfxx-mips.c (_bfd_elf_mips_mach): Handle
	E_MIPS_MACH_GS264E.
	(mips_set_isa_flags): Likewise.
	(mips_mach_extensions): Map bfd_mach_mips_gs264e to
	bfd_mach_mips_gs464e extension.

binutils/
	* NEWS: Mention Loongson 2K1000 proccessor support.
	* readelf.c (get_machine_flags): Handle gs264e.

elfcpp/
	* mips.c (EF_MIPS_MACH): New E_MIPS_MACH_GS264E.

gas/
	* config/tc-mips.c (ISA_HAS_ODD_SINGLE_FPR): Exclude CPU_GS264E.
	(mips_cpu_info_table): Add gs264e descriptors.
	* doc/as.texi (march table): Add gs264e.

include/
	* elf/mips.h (E_MIPS_MACH_XXX): New E_MIPS_MACH_GS264E.
	* opcode/mips.h (CPU_XXX): New CPU_GS264E.

ld/
	* testsuite/ld-mips-elf/mips-elf-flags.exp: Run good_combination
	gs264e and gs464e.

opcodes/
	* mips-dis.c (mips_arch_choices): Add gs264e descriptors.
2018-08-29 20:55:25 +08:00
Chenghua Xu
bd782c07b9 [MIPS] Add Loongson 3A2000/3A3000 proccessor support.
bfd/
	* archures.c (bfd_architecture): New machine
	bfd_mach_mips_gs464e.
	* bfd-in2.h (bfd_architecture): Likewise.
	* cpu-mips.c (enum I_xxx): Likewise.
	(arch_info_struct): Likewise.
	* elfxx-mips.c (_bfd_elf_mips_mach): Handle
	E_MIPS_MACH_GS464E.
	(mips_set_isa_flags): Likewise.
	(mips_mach_extensions): Map bfd_mach_mips_gs464e to
	bfd_mach_mips_gs464 extension.

binutils/
	* NEWS: Mention Loongson 3A2000/3A3000 proccessor support.
	* readelf.c (get_machine_flags): Handle gs464e.

elfcpp/
	* mips.c (EF_MIPS_MACH): New E_MIPS_MACH_GS464E.

gas/
	* config/tc-mips.c (ISA_HAS_ODD_SINGLE_FPR): Exclude CPU_GS464E.
	(mips_cpu_info_table): Add gs464e descriptors.
	* doc/as.texi (march table): Add gs464e.

include/
	* elf/mips.h (E_MIPS_MACH_XXX): New E_MIPS_MACH_GS464E.
	* opcode/mips.h (CPU_XXX): New CPU_GS464E.

ld/
	* testsuite/ld-mips-elf/mips-elf-flags.exp: Run good_combination
	gs464e and gs464.

opcodes/
	* mips-dis.c (mips_arch_choices): Add gs464e descriptors.
2018-08-29 20:43:19 +08:00
Chenghua Xu
ac8cb70f36 [MIPS] Add Loongson 3A1000 proccessor support.
bfd/
	* archures.c (bfd_architecture): Rename
	bfd_mach_mips_loongson_3a to bfd_mach_mips_gs464.
	* bfd-in2.h (bfd_architecture): Likewise.
	* cpu-mips.c (enum I_xxx): Likewise.
	(arch_info_struct): Likewise.
	* elfxx-mips.c (_bfd_elf_mips_mach): Likewise.
	(mips_set_isa_flags): Likewise.
	(mips_mach_extensions): Likewise.
	(bfd_mips_isa_ext_mach): Likewise.
	(bfd_mips_isa_ext): Likewise.
	(print_mips_isa_ext): Delete AFL_EXT_LOONGSON_3A.

binutils/
	* NEWS: Mention Loongson 3A1000 proccessor support.
	* readelf.c (get_machine_flags): Rename loongson-3a to gs464.
	(print_mips_isa_ext): Delete AFL_EXT_LOONGSON_3A.

elfcpp/
	* mips.c (EF_MIPS_MACH): Rename E_MIPS_MACH_LS3A to
	E_MIPS_MACH_GS464.

gas/
	* config/tc-mips.c (ISA_HAS_ODD_SINGLE_FPR): Rename
	CPU_LOONGSON_3A to CPU_GS464.
	(mips_cpu_info_table): Add gs464 descriptors, Keep
	loongson3a as an alias of gs464 for compatibility.
	* doc/as.texi (march table): Rename loongson3a to gs464.
	* testsuite/gas/mips/loongson-3a-mmi.d: Set "ISA Extension"
	flag to None.

gold/
	* mips.cc (Mips_mach, add_machine_extensions, elf_mips_mach):
	Rename loongson3a to gs464.
	(mips_isa_ext_mach, mips_isa_ext): Delete loongson3a.
	(infer_abiflags): Use ases instead of isa_ext for infer ABI
flags.
	(elf_mips_mach_name): Rename loongson3a to gs464.

include/
	* elf/mips.h (E_MIPS_MACH_XXX): Rename E_MIPS_MACH_LS3A to
	E_MIPS_MACH_GS464.
	(AFL_EXT_XXX): Delete AFL_EXT_LOONGSON_3A.
	* opcode/mips.h (INSN_XXX): Delete INSN_LOONGSON_3A.
	(CPU_XXX): Rename CPU_LOONGSON_3A to CPU_GS464.
	* opcode/mips.h (mips_isa_table): Delete CPU_LOONGSON_3A case.

ld/
	* testsuite/ld-mips-elf/mips-elf-flags.exp: Rename loongson3a
	to gs464.

opcodes/
	* mips-dis.c (mips_arch_choices): Add gs464 descriptors, Keep
	loongson3a as an alias of gs464 for compatibility.
	* mips-opc.c (mips_opcodes): Change Comments.
2018-08-29 20:32:30 +08:00
Chenghua Xu
a693765e23 [MIPS/GAS] Add Loongson EXT2 Instructions support.
bfd/
	* elfxx-mips.c (print_mips_ases): Add Loongson EXT2 extension.

binutils/
	* readelf.c (print_mips_ases): Add Loongson EXT2 extension.

gas/
	* NEWS: Mention Loongson EXTensions R2 (EXT2) support.
	* config/tc-mips.c (options): Add OPTION_LOONGSON_EXT2 and
	OPTION_NO_LOONGSON_EXT2.
	(md_longopts): Likewise.
	(mips_ases): Define availability for EXT.
	(mips_convert_ase_flags): Map ASE_LOONGSON_EXT2 to
	AFL_ASE_LOONGSON_EXT2.
	(md_show_usage): Add help for -mloongson-ext2 and
	-mno-loongson-ext2.
	* doc/as.texi: Document -mloongson-ext2, -mno-loongson-ext2.
	* doc/c-mips.texi: Document -mloongson-ext2, -mno-loongson-ext2,
	.set loongson-ext2 and .set noloongson-ext2.
	* testsuite/gas/mips/loongson-ext2.d: New test.
	* testsuite/gas/mips/loongson-ext2.s: New test.
	* testsuite/gas/mips/mips.exp: Run loongson-ext2 test.

include/
	* elf/mips.h (AFL_ASE_LOONGSON_EXT2): New macro.
	(AFL_ASE_MASK): Update to include AFL_ASE_LOONGSON_EXT2.
	* opcode/mips.h (ASE_LOONGSON_EXT2): New macro.

opcodes/
	* mips-dis.c (parse_mips_ase_option): Handle -M loongson-ext
	option.
	(print_mips_disassembler_options): Document -M loongson-ext.
	* mips-opc.c (LEXT2): New macro.
	(mips_opcodes): Add cto, ctz, dcto, dctz instructions.
2018-08-29 20:08:58 +08:00
Chenghua Xu
bdc6c06e3b [MIPS/GAS] Split Loongson EXT Instructions from loongson3a.
bfd/
	 * elfxx-mips.c (infer_mips_abiflags): Use ases instead of
	 isa_ext for infer ABI flags.
	 (print_mips_ases): Add Loongson EXT extension.

binutils/
	 * readelf.c (print_mips_ases): Add Loongson EXT extension.

elfcpp/
	 * mips.h (AFL_ASE_LOONGSON_EXT): New enum.

gas/
	 * NEWS: Mention Loongson EXTensions (EXT) support.
	 * config/tc-mips.c (options): Add OPTION_LOONGSON_EXT and
	 OPTION_NO_LOONGSON_EXT.
	 (md_longopts): Likewise.
	 (mips_ases): Define availability for EXT.
	 (mips_convert_ase_flags): Map ASE_LOONGSON_EXT to
	 AFL_ASE_LOONGSON_EXT.
	 (mips_cpu_info_table): Add ASE_LOONGSON_EXT for loongson3a.
	 (md_show_usage): Add help for -mloongson-ext and
	 -mno-loongson-ext.
	 * doc/as.texi: Document -mloongson-ext, -mno-loongson-ext.
	 * doc/c-mips.texi: Document -mloongson-ext, -mno-loongson-ext,
	 .set loongson-ext and .set noloongson-ext.
	 * testsuite/gas/mips/loongson-mmi.d: Add ASE flag.

include/
	 * elf/mips.h (AFL_ASE_LOONGSON_EXT): New macro.
	 (AFL_ASE_MASK): Update to include AFL_ASE_LOONGSON_EXT.
	 * opcode/mips.h (ASE_LOONGSON_EXT): New macro.

opcodes/
	 * mips-dis.c (mips_arch_choices): Add EXT to loongson3a
	 descriptors.
	 (parse_mips_ase_option): Handle -M loongson-ext option.
	 (print_mips_disassembler_options): Document -M loongson-ext.
	 * mips-opc.c (IL3A): Delete.
	 * mips-opc.c (LEXT): New macro.
	 (mips_opcodes): Replace IL2F|IL3A marking with LEXT for EXT
	 instructions.
2018-08-29 19:57:39 +08:00
Chenghua Xu
716c08de28 [MIPS/GAS] Split Loongson CAM Instructions from loongson3a
bfd/
	* elfxx-mips.c (print_mips_ases): Add CAM extension.

binutils/
	* readelf.c (print_mips_ases): Add CAM extension.

gas/
	* NEWS: Mention Loongson Content Address Memory (CAM)
	support.
	* config/tc-mips.c (options): Add OPTION_LOONGSON_CAM and
	OPTION_NO_LOONGSON_CAM.
	(md_longopts): Likewise.
	(mips_ases): Define availability for CAM.
	(mips_convert_ase_flags): Map ASE_LOONGSON_CAM to
	AFL_ASE_LOONGSON_CAM.
	(mips_cpu_info_table): Add ASE_LOONGSON_CAM for loongson3a.
	(md_show_usage): Add help for -mloongson-cam and
	-mno-loongson-cam.
	* doc/as.texi: Document -mloongson-cam, -mno-loongson-cam.
	* doc/c-mips.texi: Document -mloongson-cam, -mno-loongson-cam,
	.set loongson-cam and .set noloongson-cam.
	* testsuite/gas/mips/loongson-3a-2.d: Move cam test to ...
	* testsuite/gas/mips/loongson-cam.d: Here.  Add ISA/ASE
	flag verification.
	* testsuite/gas/mips/loongson-3a-2.s: Move cam test to ...
	* testsuite/gas/mips/loongson-cam.s: Here.
	* testsuite/gas/mips/loongson-3a-mmi.d: Add ASE flag.
	* testsuite/gas/mips/mips.exp: Run loongson-cam test.

include/
	* elf/mips.h (AFL_ASE_LOONGSON_CAM): New macro.
	(AFL_ASE_MASK): Update to include AFL_ASE_LOONGSON_CAM.
	* opcode/mips.h (ASE_LOONGSON_CAM): New macro.

opcodes/
	* mips-dis.c (mips_arch_choices): Add CAM to loongson3a
	descriptors.
	(parse_mips_ase_option): Handle -M loongson-cam option.
	(print_mips_disassembler_options): Document -M loongson-cam.
	* mips-opc.c (LCAM): New macro.
	(mips_opcodes): Replace IL2F|IL3A marking with LCAM for CAM
	instructions.
2018-08-29 19:33:09 +08:00
H.J. Lu
90c745dc54 x86: Don't mask out the GNU_PROPERTY_X86_UINT32_VALID bit
Since only the GNU_PROPERTY_X86_UINT32_VALID bit may be set in data-only
relocatable objects which don't contain any instructions, linker
shouldn't mask out the GNU_PROPERTY_X86_UINT32_VALID bit when merging
GNU_PROPERTY_X86_XXX bits.  Otherwise, linker output doesn't contain
GNU_PROPERTY_X86_XXX property with any data-only relocatable inputs.
This patch keeps the GNU_PROPERTY_X86_UINT32_VALID bit and updates
readelf to print "<None>" if GNU_PROPERTY_X86_XXX property only has
the GNU_PROPERTY_X86_UINT32_VALID bit.

bfd/

	* elfxx-x86.c (_bfd_x86_elf_parse_gnu_properties): Don't mask
	out the GNU_PROPERTY_X86_UINT32_VALID bit.

binutils/

	* readelf.c (decode_x86_isa): Print <None> if bitmask only
	contains the GNU_PROPERTY_X86_UINT32_VALID bit.
	(decode_x86_feature_1): Likewise.
	(decode_x86_feature_2): Likewise.
	(print_gnu_property_note): Don't mask out the
	GNU_PROPERTY_X86_UINT32_VALID bit.
	* testsuite/binutils-all/i386/pr21231b.d: Updated.
	* testsuite/binutils-all/x86-64/pr21231b.d: Likewise.

gas/

	* testsuite/gas/i386/i386.exp: Run property-1 and
	x86-64-property-1.
	* testsuite/gas/i386/property-1.d: New file.
	* testsuite/gas/i386/property-1.s: Likewise.
	* testsuite/gas/i386/x86-64-property-1.d: Likewise.

ld/

	* testsuite/ld-i386/i386.exp: Run property-x86-5.
	* testsuite/ld-i386/property-x86-5.d: New file.
	* testsuite/ld-x86-64/property-x86-5-x32.d: Likewise.
	* testsuite/ld-x86-64/property-x86-5.d: Likewise.
	* testsuite/ld-x86-64/property-x86-5a.s: Likewise.
	* testsuite/ld-x86-64/property-x86-5b.s: Likewise.
	* testsuite/ld-x86-64/x86-64.exp: Run property-x86-5 and
	property-x86-5-x32.
2018-08-27 15:42:14 -07:00
Jim Wilson
bfb218e3e4 RISC-V: Reject empty rouding mode and fence operand.
gas/
	2018-08-23  Kito Cheng  <kito@andestech.com>
	* config/tc-riscv.c (arg_lookup): Checking
	length before look up.
	* testsuite/gas/riscv/fence-fail.d: New file.
	* testsuite/gas/riscv/fence-fail.l: Likewise.
	* testsuite/gas/riscv/fence-fail.s: Likewise.
	* testsuite/gas/riscv/rouding-fail.d: Likewise.
	* testsuite/gas/riscv/rouding-fail.l: Likewise.
	* testsuite/gas/riscv/rouding-fail.s: Likewise.
2018-08-23 13:26:48 -07:00
H.J. Lu
7dd36a6f1c Prune BFD warnings for unknown GNU properties
When glibc is enabled with the new GNU_PROPERTY_X86_XXX bits:

https://groups.google.com/forum/#!topic/x86-64-abi/-D05GQ3kWrA

BFD will issue an unknown GNU property warning like

warning: tmpdir/ld1: unsupported GNU_PROPERTY_TYPE (5) type: 0xc0010001

and ignore such GNU properties.  This patch adds prune_warnings_extra to
prune such warnings on release branches and updates prune_warnings to
call prune_warnings_extra.

binutils/

	PR ld/23536
	* Makefile.am (development.exp): New target.
	(EXTRA_DEJAGNU_SITE_CONFIG): New.
	(DISTCLEANFILES): Add development.exp.
	* Makefile.in: Regenerated.
	* testsuite/binutils-all/objcopy.exp (strip_test): Call
	prune_warnings to prune BFD output.
	(strip_test_with_saving_a_symbol): Likewise.
	(objcopy_test_without_global_symbol): Likewise.
	* testsuite/lib/binutils-common.exp (prune_warnings_extra):
	New proc.
	(prune_warnings): Likewise.

gas/

	PR ld/23536
	* Makefile.am (development.exp): New target.
	(EXTRA_DEJAGNU_SITE_CONFIG): New.
	(DISTCLEANFILES): Add development.exp.
	* Makefile.in: Regenerated.

ld/

	PR ld/23536
	* Makefile.am (development.exp): New target.
	(EXTRA_DEJAGNU_SITE_CONFIG): New.
	(DISTCLEANFILES): Add development.exp.
	* Makefile.in: Regenerated.
	* testsuite/ld-bootstrap/bootstrap.exp: Call prune_warnings to
	prune BFD output.
	* testsuite/ld-plugin/lto.exp: Likewise.
	* testsuite/lib/ld-lib.exp (prune_warnings): Removed.
	* testsuite/ld-elf/shared.exp: Allow "\n" in linker warnings.
2018-08-23 06:12:50 -07:00
Nick Clifton
d000b7630e Fix typo in changelog entry for handling of undocumnented Z80 SLI instruction. 2018-08-22 09:58:32 +01:00
Alan Modra
86b9fea102 Re: Pack reloc_howto_struct
Fix fallout when using gcc-4.

	* dw2gencfi.c (emit_expr_encoded, output_fde): Warning fixes.
2018-08-22 15:38:37 +09:30
Arnold Metselaar
6efa941c38 Fix handling of undocumented SLL instruction for the Z80 target.
* config/tc-z80.c: Correct treatment of undocumented instruction
	sli/sll.
	(emit_mr): Add argument unportable.
	(emit_bit): Adapt call to emit_mr.
	(emit_mr_z80): New function.
	(emit_mr_unportable): New function.
	(instab[]): Replace emit_mr with emit_mr_z80 or emit_mr_unportable
	as appropriate.
2018-08-21 15:50:49 +01:00
Andreas Schwab
9dcbfff1e0 Fix invalid strcpy on unterminated buffer
* read.c (do_repeat_with_expander): Use memmove instead of strcpy
on unterminated string buffer.
2018-08-21 10:34:02 +02:00
Alan Modra
9cf7e5687f Use operand->extract to provide defaults for optional PowerPC operands
Most optional operands to powerpc instructions use a default value of
zero, but there are a few exceptions.  Those have been handled by
PPC_OPERAND_OPTIONAL_VALUE and an entry in the powerpc_operands table
for the default value, smuggled in the shift field.  This patch
changes that to using the operand extract function to provide non-zero
defaults.

I've also moved the code determining whether optional operands are
provided or omitted, to the point the first optional operand is seen,
and allowed for the possibility of optional base register operands
in a future patch.

The patch does change the error you get on invalid assembly like

  ld 3,4

You'll now see "missing operand" rather than
"syntax error; end of line, expected `('".

gas/
	* config/tc-ppc.c (md_assemble): Delay counting of optional
	operands until one is encountered.  Allow for the possibility
	of optional base regs, ie. PPC_OPERAND_PARENS.  Call
	ppc_optional_operand_value with extra args.
include/
	* opcode/ppc.h (struct powerpc_operand): Correct "insert" comment.
	Mention use of "extract" function to provide default value.
	(PPC_OPERAND_OPTIONAL_VALUE): Delete.
	(ppc_optional_operand_value): Rewrite to use extract function.
opcodes/
	* ppc-dis.c (operand_value_powerpc): Init "invalid".
	(skip_optional_operands): Count optional operands, and update
	ppc_optional_operand_value call.
	* ppc-opc.c (extract_dxdn): Remove ATTRIBUTE_UNUSED from used arg.
	(extract_vlensi): Likewise.
	(extract_fxm): Return default value for missing optional operand.
	(extract_ls, extract_raq, extract_tbr): Likewise.
	(insert_sxl, extract_sxl): New functions.
	(insert_esync, extract_esync): Remove Power9 handling and simplify.
	(powerpc_operands <FXM4, TBR>): Delete PPC_OPERAND_OPTIONAL_VALUE
	flag and extra entry.
	(powerpc_operands <SXL>): Likewise, and use insert_sxl and
	extract_sxl.
2018-08-21 16:05:36 +09:30
Alan Modra
08a8fe2ffd Fix s12z test regexps
Fixes
ERROR: tcl error sourcing .../gas/testsuite/gas/s12z/s12z.exp.
ERROR: couldn't compile regular expression pattern: quantifier operand invalid

run_dump_test expected output lines are regexps.

	* testsuite/gas/s12z/bit-manip-invalid.d: Correct regexps.
2018-08-21 14:59:53 +09:30
Alan Modra
d203b41ac7 Tidy bit twiddling
* sh-opc.h (MASK): Simplify.
2018-08-20 09:54:20 +09:30
John Darrington
f41078422a Opcodes: (BRCLR / BRSET) Disassemble reserved codes instead of aborting.
Bit manipulation instructions which are not normally generated by the
assembler, should nevertheless be decoded by the disassembler.

opcodes/
	* s12z-dis.c: BM_RESERVED1 to behave like BM_OPR_REG, and
	BM_RESERVED0 like BM_REG_IMM.
2018-08-18 07:50:57 +02:00
John Darrington
7ba3ba91a3 S12Z: Move opcode header to public include directory.
opcodes/
        * s12z.h: Delete.
	* s12z-dis.c: Adjust path of included file.

include/
        * opcode/s12z.h: New file.

gas/
	* config/tc-s12z.c: Adjust path of included file.
2018-08-18 07:50:03 +02:00
H.J. Lu
1bc60e5624 x86-64: Display eiz for address with the addr32 prefix
In 64-bit mode, display eiz for address with the addr32 prefix and without
base nor index registers.  For

	mov -0xccddef(,%eiz,), %rax

disassembler now displays:

	67 48 8b 04 25 11 22 33 ff 	mov -0xccddef(,%eiz,1),%rax

instead of

	67 48 8b 04 25 11 22 33 ff 	addr32 mov 0xffffffffff332211,%rax

gas/

	* testsuite/gas/i386/evex-no-scale-64.d: Updated.
	* testsuite/gas/i386/x86-64-addr32-intel.d: Likewise.
	* testsuite/gas/i386/x86-64-addr32.d: Likewise.
	* testsuite/gas/i386/ilp32/x86-64-addr32-intel.d: Likewise.
	* testsuite/gas/i386/ilp32/x86-64-addr32.d: Likewise.
	* testsuite/gas/i386/x86-64-addr32.s: Add %eiz tests.

opcodes/

	* i386-dis.c (OP_E_memory): In 64-bit mode, display eiz for
	address with the addr32 prefix and without base nor index
	registers.
2018-08-14 09:56:00 -07:00
Robert Yang
2a50366ded When the assembler reports that the input and output are the same, report the file names involved, in order to help debugging. Also do not equate two files are the same if the have the same inode value but reside on different file systems.
* as.c (main): Improve check for input file matching output file.
2018-08-14 12:22:35 +01:00
H.J. Lu
d871f3f483 x86: Add CpuCMOV and CpuFXSR
There are separate CPUID feature bits for fxsave/fxrstor and cmovCC
instructions.  This patch adds CpuCMOV and CpuFXSR to replace Cpu686
on corresponding instructions.

gas/

	* config/tc-i386.c (cpu_arch): Add .cmov and .fxsr.
	(cpu_noarch): Add nocmov and nofxsr.
	* doc/c-i386.texi: Document cmov and fxsr.

opcodes/

	* i386-gen.c (cpu_flag_init): Add CpuCMOV and CpuFXSR to
	CPU_I686_FLAGS.  Add CPU_CMOV_FLAGS, CPU_FXSR_FLAGS,
	CPU_ANY_CMOV_FLAGS and CPU_ANY_FXSR_FLAGS.
	(cpu_flags): Add CpuCMOV and CpuFXSR.
	* i386-opc.tbl: Replace Cpu686 with CpuFXSR on fxsave, fxsave64,
	fxrstor and fxrstor64.  Replace Cpu686 with CpuCMOV on cmovCC.
	* i386-init.h: Regenerated.
	* i386-tbl.h: Likewise.
2018-08-11 14:37:32 -07:00
H.J. Lu
d7f449c026 x86: Don't display --32/--64/--x32 without BFD64
For 32-bit x86 assembler, --64 and --x32 are unsupported if BFD64 is
undefined.  Even if BFD64 is defined, --64 and --x32 still may not be
supported if x86-64 support isn't compiled in:

[hjl@gnu-hsw-1 gas]$ ./as-new --64 -o x.o x.s
Assembler messages:
Fatal error: no compiled in support for x86_64
[hjl@gnu-hsw-1 gas]$ ./as-new --x32 -o x.o x.s
Assembler messages:
Fatal error: no compiled in support for 32bit x86_64
[hjl@gnu-hsw-1 gas]$

This patch removes --32/--64/--x32 from md_show_usage if BFD64 is
undefined and runs code64-inval only if BFD64 is undefined.

	* config/tc-i386.c (md_show_usage): Don't display --32/--64/--x32
	if BFD64 is undefined.
	* testsuite/gas/i386/i386.exp (gas_bfd64_check): New.
	Run code64-inval if gas_bfd64_check fails.
2018-08-10 11:03:50 -07:00
H.J. Lu
19449d7c67 x86: Replace evex-no-scale.s with evex-no-scale-[32|64].s
.if is_64bit
	vmovaps	-1024(%rip), %zmm0
	vmovaps	64(,%rax), %zmm0
	vmovaps	64(,%riz), %zmm0
.endif

doesn't with i686-elf cross binutils on 64-bit hosts:

evex-no-scale.s: Assembler messages:
evex-no-scale.s:10: Error: bad register name `%rip)'
evex-no-scale.s:11: Error: bad register name `%rax)'
evex-no-scale.s:12: Error: bad register name `%riz)'

This patch replaces evex-no-scale.s with evex-no-scale-32.s and
evex-no-scale-64.s.

	* testsuite/gas/i386/evex-no-scale-32.d: Don't use
	evex-no-scale.s.
	* testsuite/gas/i386/evex-no-scale-64.d: Likewise.
	* testsuite/gas/i386/evex-no-scale-32.s: New file.
	* testsuite/gas/i386/evex-no-scale-64.s: Likewise.
	* testsuite/gas/i386/evex-no-scale.s: Removed.
2018-08-10 10:23:11 -07:00
H.J. Lu
3a53fb12c8 as --help: Display default option for --elf-stt-common=
* as.c (show_usage): Display default option for --elf-stt-common=.
2018-08-09 09:57:11 -07:00
H.J. Lu
7c5c05effd x86: Display default x86-specific options for "as --help"
* config/tc-i386.c (md_show_usage): Display default options.
2018-08-09 09:52:43 -07:00
James Patrick Conlon
8f9ea98beb Correct the parsing of derferred register addressing in the PDP11 assembler.
PR 23481
	* config/tc-pdp11.c (parse_op_noreg): Check for deferred register
	addressing before assuming non-deferred addressing.
	* testsuite/gas/pdp11/pr23481.s: New test source file.
	* testsuite/gas/pdp11/pr23481.d: New test driver file.
	* testsuite/gas/pdp11/pdp11.exp: Run the new test.
2018-08-07 08:34:08 +01:00
claziss
63741043bd [ARC] Check if an input asm file is rf16 compliant
Check if an input asm file is rf16 compliant; if not, and the tag says
otherwise, fix the tag and emit a warning.

gas/
2017-09-20  Claudiu Zissulescu <claziss@synopsys.com>

	* config/tc-arc.c (rf16_only): New static variable.
	(autodetect_attributes): Check if we are rf16 compliant.
	(arc_set_public_attributes): Fix and emit the warning is required.
	* testsuite/gas/arc/attr-rf16.d: New file.
	* testsuite/gas/arc/attr-rf16.err: Likewise.
	* testsuite/gas/arc/attr-rf16.s: Likewise.
2018-08-06 16:41:32 +03:00
claziss
db1e1b45b4 [ARC] Add Tag_ARC_ATR_version.
Add a new tag (Tag_ARC_ATR_version) used to indicate if current
attributes are interpreted in GNU way. This attribute is used by
Synopsys custom compiler to correctly identify and interpret the
object attributes section as generated by GNU tools.

gas/
2017-08-02  Claudiu Zissulescu <claziss@synopsys.com>

	* config/tc-arc.c (arc_set_public_attributes): Add
	Tag_ARC_ATR_version.
	(arc_convert_symbolic_attribute): Likewise.
	* testsuite/gas/arc/attr-arc600.d: Update test.
	* testsuite/gas/arc/attr-arc600_mul32x16.d: Likewise.
	* testsuite/gas/arc/attr-arc600_norm.d: Likewise.
	* testsuite/gas/arc/attr-arc601.d: Likewise.
	* testsuite/gas/arc/attr-arc601_mul32x16.d: Likewise.
	* testsuite/gas/arc/attr-arc601_mul64.d: Likewise.
	* testsuite/gas/arc/attr-arc601_norm.d: Likewise.
	* testsuite/gas/arc/attr-arc700.d: Likewise.
	* testsuite/gas/arc/attr-arcem.d: Likewise.
	* testsuite/gas/arc/attr-archs.d: Likewise.
	* testsuite/gas/arc/attr-autodetect-1.d: Likewise.
	* testsuite/gas/arc/attr-cpu-a601.d: Likewise.
	* testsuite/gas/arc/attr-cpu-a700.d: Likewise.
	* testsuite/gas/arc/attr-cpu-em.d: Likewise.
	* testsuite/gas/arc/attr-cpu-hs.d: Likewise.
	* testsuite/gas/arc/attr-em.d: Likewise.
	* testsuite/gas/arc/attr-em4.d: Likewise.
	* testsuite/gas/arc/attr-em4_dmips.d: Likewise.
	* testsuite/gas/arc/attr-em4_fpuda.d: Likewise.
	* testsuite/gas/arc/attr-em4_fpus.d: Likewise.
	* testsuite/gas/arc/attr-hs.d: Likewise.
	* testsuite/gas/arc/attr-hs34.d: Likewise.
	* testsuite/gas/arc/attr-hs38.d: Likewise.
	* testsuite/gas/arc/attr-hs38_linux.d: Likewise.
	* testsuite/gas/arc/attr-mul64.d: Likewise.
	* testsuite/gas/arc/attr-name.d: Likewise.
	* testsuite/gas/arc/attr-nps400.d: Likewise.
	* testsuite/gas/arc/attr-override-mcpu.d: Likewise.
	* testsuite/gas/arc/attr-quarkse_em.d: Likewise.

bfd/
2017-08-02  Claudiu Zissulescu <claziss@synopsys.com>

	* elf32-arc.c (arc_elf_merge_attributes): Handle
	Tag_ARC_ATR_version.

binutils/
2017-08-02  Claudiu Zissulescu <claziss@synopsys.com>

	* readelf.c (display_arc_attribute): Print Tag_ARC_ATR_version.

include/
2017-08-02  Claudiu Zissulescu <claziss@synopsys.com>

	* elf/arc.h (Tag_ARC_ATR_version): New tag.

ld/
2017-08-02  Claudiu Zissulescu <claziss@synopsys.com>

	* testsuite/ld-arc/attr-merge-0.d: Update test.
	* testsuite/ld-arc/attr-merge-1.d: Likewise.
	* testsuite/ld-arc/attr-merge-2.d: Likewise.
	* testsuite/ld-arc/attr-merge-3.d: Likewise.
	* testsuite/ld-arc/attr-merge-5.d: Likewise.
2018-08-06 16:41:32 +03:00
claziss
b6523c37fb [ARC] Update handling AUX-registers.
Update aux-registers data-base, and accept aux-registers names with
upper/lowercase names.

opcode/
2017-07-18  Claudiu Zissulescu  <claziss@synopsys.com>

	* arc-regs.h: Update aux-registers.

gas/
2017-07-18  Claudiu Zissulescu  <claziss@synopsys.com>

	* config/tc-arc.c (find_opcode_match): Accept uppercase aux-regs
	names.
	* testsuite/gas/arc/ld2.d: Update test.
	* testsuite/gas/arc/taux.d: Likewise.
	* testsuite/gas/arc/taux.s: Likewise.

include/
2017-07-18  Claudiu Zissulescu  <claziss@synopsys.com>

	* opcode/arc.h (ARC_OPCODE_ARCV1): Define.
2018-08-06 16:41:32 +03:00
Jan Beulich
e968fc9b63 x86: fold RegEip/RegRip and RegEiz/RegRiz
This allows to simplify the code in a number of places.
2018-08-06 08:34:36 +02:00
H.J. Lu
99c2d522f7 x86: Update assembler tests for non-ELF targets
evex-no-scale.s has ELF directive:

.section .probe, "", @progbits

and non-ELF targets may pad text sections.

	* testsuite/gas/i386/i386.exp: Run evex-no-scale-32 and
	evex-no-scale-64 only for ELF targets.
	* testsuite/gas/i386/prefix32.s: Append ".p2align 4,0".
	* testsuite/gas/i386/prefix64.s: Likewise.
	* testsuite/gas/i386/prefix32.l: Updated.
	* testsuite/gas/i386/prefix64.l: Likewise.
2018-08-05 10:05:52 -07:00
Alan Modra
05d0e962f0 R_PPC64_REL24_NOTOC support
R_PPC64_REL24_NOTOC is used on calls like "bl foo@notoc" to tell the
linker that linkage stubs for PLT calls or long branches can't use r2
for pic addressing.  Instead, new stubs that generate pc-relative
addresses are used.  One complication is that pc-relative offsets to
the PLT may need to be 64-bit in large programs, in contrast to the
toc-relative addressing used by older PLT linkage stubs where a 32-bit
offset is sufficient until the PLT itself exceeds 2G in size.

.eh_frame info to cover the _notoc stubs is yet to be implemented.

bfd/
	* elf64-ppc.c (ADDI_R12_R11, ADDI_R12_R12, LIS_R12),
	(ADDIS_R12_R11, ORIS_R12_R12_0, ORI_R12_R12_0),
	(SLDI_R12_R12_32, LDX_R12_R11_R12, ADD_R12_R11_R12): Define.
	(ppc64_elf_howto_raw): Add R_PPC64_REL24_NOTOC entry.
	(ppc64_elf_reloc_type_lookup): Support R_PPC64_REL24_NOTOC.
	(ppc_stub_type): Add ppc_stub_long_branch_notoc,
	ppc_stub_long_branch_both, ppc_stub_plt_branch_notoc,
	ppc_stub_plt_branch_both, ppc_stub_plt_call_notoc, and
	ppc_stub_plt_call_both.
	(is_branch_reloc): Add R_PPC64_REL24_NOTOC.
	(build_offset, size_offset): New functions.
	(plt_stub_size): Support plt_call_notoc and plt_call_both.
	(ppc_build_one_stub, ppc_size_one_stub): Support new stubs.
	(toc_adjusting_stub_needed): Handle R_PPC64_REL24_NOTOC.
	(ppc64_elf_size_stubs): Likewise, and new stubs.
	(ppc64_elf_build_stubs, ppc64_elf_relocate_section): Likewise.
	* reloc.c: Add BFD_RELOC_PPC64_REL24_NOTOC.
	* bfd-in2.h: Regenerate.
	* libbfd.h: Regenerate.
gas/
	* config/tc-ppc.c (ppc_elf_suffix): Support @notoc.
	(ppc_force_relocation, ppc_fix_adjustable): Handle REL24_NOTOC.
ld/
	* testsuite/ld-powerpc/ext.d,
	* testsuite/ld-powerpc/ext.s,
	* testsuite/ld-powerpc/ext.lnk,
	* testsuite/ld-powerpc/notoc.d,
	* testsuite/ld-powerpc/notoc.s: New tests.
	* testsuite/ld-powerpc/powerpc.exp: Run them.
2018-08-05 12:11:51 +09:30
Dimitar Dimitrov
2688aab226 Update PRU assembler to corect hardware register numbering for DWARF.
A small rework of the PRU GCC port exposed that CIE data alignment is
erroneously set to 4 for PRU in GAS. In fact PRU stack must be aligned to 1.
Set the macro to -1, to allow output from GCC to be assembled without errors.

Also, while at it, set DWARF2 HW register numbering to follow latest

	* config/tc-pru.c (pru_regname_to_dw2regnum): Return the starting HW
	byte-register number.
	(pru_frame_initial_instructions): Use byte-numbering for FP index.
	* config/tc-pru.h (DWARF2_DEFAULT_RETURN_COLUMN): Use number from
	latest GCC.
	(DWARF2_CIE_DATA_ALIGNMENT): Set to -1.
2018-08-03 10:02:39 +01:00
Jan Beulich
c48dadc9a8 x86: drop "mem" operand type attribute
No template specifies this bit, so there's no point recording it in the
templates. Use a flags[] bit instead.
2018-08-03 09:30:02 +02:00
James Patrick Conlon
3cf2b6691c Fix bug in PDP11 assembler when handling a JSr instruction with deferred auto increment.
PR 14480
	* config/tc-pdp11.c (parse_op_noreg): Check for and handle auto
	increment deferred.
	* testsuite/gas/pdp11/pr14480.d: New test driver file.
	* testsuite/gas/pdp11/pr14480.s: New test source file file.
	* testsuite/gas/pdp11/pdp11.exp: Run the new test.
2018-08-01 15:14:46 +01:00
Nick Clifton
f03fb29221 Fix compile time warning problem with gcc 8 and the NS32K assembler sources.
* config/tc-ns32k.c (addr_mode): Replace "Drop through" comment
	with "Fall through" so that it will be recognised by gcc's switch
	statment error checker.
2018-08-01 14:36:50 +01:00
Alan Modra
cb86a42aba csky regen
bfd/
	* po/SRC-POTFILES.in: Regenerate.
gas/
	* po/POTFILES.in: Regenerate.
ld/
	* po/BLD-POTFILES.in: Regenerate.
opcodes/
	* po/POTFILES.in: Regenerate.
2018-08-01 10:32:56 +09:30
Jan Beulich
1424ad8677 x86: also optimize KXOR{D,Q} and KANDN{D,Q}
These can be converted to 2-byte VEX encoding when both source registers
are the same, by using KXORW / KANDNW as replacement.
2018-07-31 10:58:05 +02:00
Jan Beulich
ae2387feae x86: fold various AVX512 templates with so far differing Masking attributes
There's no insn allowing ZEROING_MASKING alone. Re-purpose its value for
handling the not uncommon case of insns allowing either form of masking
with register operands, but only merging masking with a memory operand.
2018-07-31 10:57:09 +02:00
Jan Beulich
fa77b93ab7 x86: add more exhaustive tests for invalid AVX512 zeroing-masking
Before changing how things get handled, install a full set of tests,
such that it can be demonstrated that the subsequent change doesn't
break things.
2018-07-31 10:56:09 +02:00
Jan Beulich
6ff00b5e12 x86/Intel: correct permitted operand sizes for AVX512 scatter/gather
AVX gather insns correctly allow the element size to be specified rather
than the full vector size. Make AVX512 ones match.
2018-07-31 10:55:17 +02:00
Jan Beulich
7a8655d2bb x86: don't abort() upon DATA16 prefix on (E)VEX encoded insn
Instead of hitting the abort() in output_insn() (commented by "There
should be no other prefixes for instructions with VEX prefix"), report
a proper diagnostic instead, just like we do e.g. for invalid REP
prefixes.
2018-07-31 10:54:05 +02:00
Jan Beulich
e951d5ca3d x86: drop CpuVREX
It is fully redundant with CpuAVX512F.
2018-07-31 10:52:37 +02:00
Jan Beulich
629cfaf1b0 x86: don't mistakenly scale non-8-bit displacements
In commit b5014f7af2 I've removed (instead of replaced) a conditional,
resulting in addressing forms not allowing 8-bit displacements to now
get their displacements scaled under certain circumstances. Re-add the
missing conditional.
2018-07-30 17:25:05 +02:00
Andrew Jenner
b8891f8d62 Add support for the C_SKY series of processors.
This patch series is a new binutils port for C-SKY processors, including support for both the V1 and V2 processor variants.  V1 is derived from the MCore architecture while V2 is substantially different, with mixed 16- and 32-bit instructions, a larger register set, a different (but overlapping) ABI, etc.  There is support for bare-metal ELF targets and Linux with both glibc and uClibc.

This code is being contributed jointly by C-SKY Microsystems and Mentor Graphics.  C-SKY is responsible for the technical content and has proposed Lifang Xia and Yunhai Shang as port maintainers.  (Note that C-SKY does have a corporate copyright assignment on file with the FSF.) Mentor Graphics' role has been cleaning up the code, adding documentation and additional test cases, etc, to address issues we anticipated reviewers would complain about.

bfd     * Makefile.am (ALL_MACHINES, ALL_MACHINES_CFILES): Add C-SKY.
        (BFD32_BACKENDS, BFD_BACKENDS_CFILES): Likewise.
        * Makefile.in: Regenerated.
        * archures.c (enum bfd_architecture): Add bfd_arch_csky and
        related bfd_mach defines.
        (bfd_csky_arch): Declare.
        (bfd_archures_list): Add C-SKY.
        * bfd-in.h (elf32_csky_build_stubs): Declare.
        (elf32_csky_size_stubs): Declare.
        (elf32_csky_next_input_section: Declare.
        (elf32_csky_setup_section_lists): Declare.
        * bfd-in2.h: Regenerated.
        * config.bfd: Add C-SKY.
        * configure.ac: Likewise.
        * configure: Regenerated.
        * cpu-csky.c: New file.
        * elf-bfd.h (enum elf_target_id): Add C-SKY.
        * elf32-csky.c: New file.
        * libbfd.h: Regenerated.
        * reloc.c: Add C-SKY relocations.
        * targets.c (csky_elf32_be_vec, csky_elf32_le_vec): Declare.
        (_bfd_target_vector): Add C-SKY target vector entries.

binutils* readelf.c: Include elf/csky.h.
        (guess_is_rela): Handle EM_CSKY.
        (dump_relocations): Likewise.
        (get_machine_name): Likewise.
        (is_32bit_abs_reloc): Likewise.

include  * dis-asm.h (csky_symbol_is_valid): Declare.
         * opcode/csky.h: New file.

opcodes  * Makefile.am (TARGET_LIBOPCODES_CFILES): Add csky-dis.c.
         * Makefile.in: Regenerated.
         * configure.ac: Add C-SKY.
         * configure: Regenerated.
         * csky-dis.c: New file.
         * csky-opc.h: New file.
         * disassemble.c (ARCH_csky): Define.
         (disassembler, disassemble_init_for_target): Add case for ARCH_csky.
         * disassemble.h (print_insn_csky, csky_get_disassembler): Declare.

gas      * Makefile.am (TARGET_CPU_CFILES): Add entry for C-SKY.
         (TARGET_CPU_HFILES, TARGET_ENV_HFILES): Likewise.
         * Makefile.in: Regenerated.
         * config/tc-csky.c: New file.
         * config/tc-csky.h: New file.
         * config/te-csky_abiv1.h: New file.
         * config/te-csky_abiv1_linux.h: New file.
         * config/te-csky_abiv2.h: New file.
         * config/te-csky_abiv2_linux.h: New file.
         * configure.tgt: Add C-SKY.
         * doc/Makefile.am (CPU_DOCS): Add entry for C-SKY.
         * doc/Makefile.in: Regenerated.
         * doc/all.texi: Set CSKY feature.
         * doc/as.texi (Overview): Add C-SKY options.
         (Machine Dependencies): Likewise.
         * doc/c-csky.texi: New file.
         * testsuite/gas/csky/*: New test cases.

ld      * Makefile.am (ALL_EMULATION_SOURCES): Add C-SKY emulations.
        (ecskyelf.c, ecskyelf_linux.c): New rules.
        * Makefile.in: Regenerated.
        * configure.tgt: Add C-SKY.
        * emulparams/cskyelf.sh: New file.
        * emulparams/cskyelf_linux.sh: New file.
        * emultempl/cskyelf.em: New file.
        * gen-doc.texi: Add C-SKY.
        * ld.texi: Likewise.
        (Options specific to C-SKY targets): New section.
        * testsuite/ld-csky/*: New tests.
2018-07-30 12:24:14 +01:00
John David Anglin
29e6f4745e Fix unwind offset for start_symbol.
* config/tc-hppa.c: Include "struc-symbol.h".
	(pa_build_unwind_subspace): Use call_info->start_symbol->sy_frag
	instead of frag_now for local symbol replacement.
2018-07-29 12:51:23 -04:00
Jim Wilson
d19969ffbf RISC-V: Fix gas configure support for riscv*-*-*.
gas/
	* configure.tgt (riscv*): Accept as alias for riscv32*.
2018-07-27 14:35:29 -07:00
H.J. Lu
1286ab7881 x86: Check for more than 2 memory references
For

movsd (%esi), %ss:(%edi), %ss:(%eax)

we got

[hjl@gnu-tools-1 tmp]$ as -o x.o x.s
x.s: Assembler messages:
x.s:1: Error: too many memory references for `movsd'
munmap_chunk(): invalid pointer
x.s:1: Internal error (Aborted).
Please report this bug.
[hjl@gnu-tools-1 tmp]$

struct _i386_insn has

const seg_entry *seg[2];

3 memory references will overflow the seg array.  We should issue an
error if there are more than 2 memory references.

	PR gas/23453
	* config/tc-i386.c (parse_operands): Check for more than 2
	memory references.
	* testsuite/gas/i386/inval.s: Add a movsd test with 3 memory
	references.
	* testsuite/gas/i386/x86-64-inval.s: Likewise.
	* testsuite/gas/i386/inval.l: Updated.
	* testsuite/gas/i386/x86-64-inval.l: Likewise.
2018-07-27 06:35:09 -07:00