This is the testsuite for the or1k sim, it tests running many of the
basic architecture instructions on the openrisc sim.
sim/testsuite/sim/or1k/ChangeLog:
2017-12-12 Peter Gavin <pgavin@gmail.com>
Stafford Horne <shorne@gmail.com>
* add.S: New file.
* alltests.exp: New file.
* and.S: New file.
* basic.S: New file.
* div.S: New file.
* ext.S: New file.
* find.S: New file.
* flag.S: New file.
* fpu.S: New file.
* jump.S: New file.
* load.S: New file.
* mac.S: New file.
* mfspr.S: New file.
* mul.S: New file.
* or.S: New file.
* or1k-asm-test-env.h: New file.
* or1k-asm-test-helpers.h: New file.
* or1k-asm-test.h: New file.
* or1k-asm.h: New file.
* or1k-test.ld: New file.
* ror.S: New file.
* shift.S: New file.
* spr-defs.h: New file.
* sub.S: New file.
* xor.S: New file.
sim/testsuite/ChangeLog:
2017-12-12 Stafford Horne <shorne@gmail.com>
Peter Gavin <pgavin@gmail.com>
* configure: Regenerated.
These are separted out to make the patch easier to read and smaller.
sim/ChangeLog:
2017-12-12 Stafford Horne <shorne@gmail.com>
Peter Gavin <pgavin@gmail.com>
* configure: Regenerated.
* or1k/aclocal.m4: Generated.
* or1k/config.in: Generated.
* or1k/configure: Generated.
These are the simulator files generated by cgen. These are split out
from the main sim patch to make the patch easier to review and smaller.
sim/ChangeLog:
2017-12-12 Stafford Horne <shorne@gmail.com>
Peter Gavin <pgavin@gmail.com>
* or1k/arch.c: Generated.
* or1k/arch.h: Generated.
* or1k/cpu.c: Generated.
* or1k/cpu.h: Generated.
* or1k/cpuall.h: Generated.
* or1k/decode.c: Generated.
* or1k/decode.h: Generated.
* or1k/model.c: Generated.
* or1k/sem-switch.c: Generated.
* or1k/sem.c: Generated.
This adds the OpenRISC 32-bit sim target. The OpenRISC sim is a CGEN
based sim so the bulk of the code is generated from the .cpu files by
CGEN. The engine decode and execute logic in mloop uses scache with
pseudo-basic-block extraction and supports both full and fast (switch)
modes.
The sim does not implement an mmu at the moment. The sim does implement
fpu instructions via the common sim-fpu implementation.
sim/ChangeLog:
2017-12-12 Stafford Horne <shorne@gmail.com>
Peter Gavin <pgavin@gmail.com>
* configure.tgt: Add or1k sim.
* or1k/README: New file.
* or1k/Makefile.in: New file.
* or1k/configure.ac: New file.
* or1k/mloop.in: New file.
* or1k/or1k-sim.h: New file.
* or1k/or1k.c: New file.
* or1k/sim-if.c: New file.
* or1k/sim-main.h: New file.
* or1k/traps.c: New file.
FT32B is a new FT32 family member.
This patch adds support for the compressed instructions to gdb and sim.
gdb/ChangeLog:
* ft32-tdep.c (ft32_fetch_instruction): New function.
(ft32_analyze_prologue): Use ft32_fetch_instruction().
sim/ChangeLog:
* ft32/interp.c (step_once): Add ft32 shortcode decoder.
FT32B is a new FT32 family member. It has a code
compression scheme, which requires the use of linker
relaxations. The change is quite large, so submission
is in several parts.
Part 1 adds a 15-bit instruction field, and CPU-specific functions for
the code compression that are used in binutils and GDB.
bfd/ChangeLog:
2017-10-12 James Bowman <james.bowman@ftdichip.com>
* bfd-in2.h: Regenerate.
* libbfd.h: Regenerate.
* elf32-ft32.c: Add HOWTO R_FT32_15.
* reloc.c: Add BFD_RELOC_FT32_15.
gas/ChangeLog:
2017-10-12 James Bowman <james.bowman@ftdichip.com>
* config/tc-ft32.c (md_assemble): Replace FT32_FLD_K8 with
K15.
(md_apply_fix, tc_gen_reloc): Add BFD_RELOC_FT32_15.
include/ChangeLog:
2017-10-12 James Bowman <james.bowman@ftdichip.com>
* elf/ft32.h: Add R_FT32_15.
* opcode/ft32.h: Replace FT32_FLD_K8 with K15.
(ft32_shortcode, sc_compar, ft32_split_shortcode,
ft32_merge_shortcode, ft32_merge_shortcode): New functions.
opcodes/ChangeLog:
2017-10-12 James Bowman <james.bowman@ftdichip.com>
* opcodes/ft32-dis.c (print_insn_ft32): Replace FT32_FLD_K8 with K15.
* opcodes/ft32-opc.c (ft32_opc_info): Replace FT32_FLD_K8 with
K15. Add jmpix pattern.
sim/ChangeLog:
2017-10-12 James Bowman <james.bowman@ftdichip.com>
* sim/ft32/interp.c (step_once): Replace FT32_FLD_K8 with K15.
This patch fixes the build failure by using disassembler to get
disassemble function pointer, and do the disassembly, because
print_insn_little_arm is no longer visible outside opcodes/
binutils-gdb/sim/arm/wrapper.c:98:10: error: implicit declaration of function 'print_insn_little_arm' [-Werror=implicit-function-declaration]
size = print_insn_little_arm (0, & info);
^
sim/arm:
2017-09-21 Yao Qi <yao.qi@linaro.org>
* wrapper.c (print_insn): Use disassembler instead of
print_insn_little_arm.
Previously this used the error function from GDB directly when linked
against GDB instead of the error method in the host callbacks
structure. This was exposed via a link error when GDB was converted
to C++. The error function invokes the error callback similar to
sim_io_error.
Note that there are also error functions in sim/ppc/main.c and
sim/ppc/misc.c. The ppc libsim.a expects each consumer to provide
several symbols used by the library including "error". sim-calls.c
provides these symbols when the library is linked into gdb. The dgen,
igen, tmp-filter, tmp-ld-decode, tmp-ld-cache, and tmp-ld-insn programs
use the functions from misc.c. psim uses the functions from main.c.
sim/ppc/ChangeLog:
PR sim/20863
* sim_calls.c (error): New function.
Nowadays, opcodes/disassemble.c:disassembler selects the proper
disassembler according to ABFD only. However, it actually
selects disassemblers according to arch, mach, endianess, and
abfd. This patch adds them to the parameters of disassembler,
so that its caller can still select disassemblers in case that
abfd is NULL (a typical case in GDB).
There isn't any functionality change.
binutils:
2017-05-24 Yao Qi <yao.qi@linaro.org>
* objdump.c (disassemble_data): Caller update.
include:
2017-05-24 Yao Qi <yao.qi@linaro.org>
* dis-asm.h (disassembler): Update declaration.
opcodes:
2017-05-24 Yao Qi <yao.qi@linaro.org>
* disassemble.c (disassembler): Add arguments a, big and mach.
Use them.
sim/common:
2017-05-24 Yao Qi <yao.qi@linaro.org>
* sim-trace.c (trace_disasm): Caller update.
sim/aarch64/
* simulator.c (vec_load): Add M argument. Rewrite to iterate over
registers based on structure size.
(LD4, LD3, LD2, LD1_2, LD1_3, LD1_4): Pass new arg to vec_load.
(LD1_1): Replace with call to vec_load.
(vec_store): Add new M argument. Rewrite to iterate over registers
based on structure size.
(ST4, ST3, ST2, ST1_2, ST1_3, ST1_4): Pass new arg to vec_store.
(ST1_1): Replace with call to vec_store.
sim/testsuite/sim/aarch64/
* fcvtz.s, fstur.s, ldn_single.s, ldnr.s, mla.s, mls.s, uzp.s: Align
data.
* sumulh.s: Delete unnecessary data alignment.
* stn_single.s: Align data. Fix unaligned ldr insns. Adjust cmp
arguments to match change.
* ldn_multiple.s, stn_multiple.s: New.
sim/aarch64/
* simulator.c (set_flags_for_add32): Cast result to uint32_t in carry
flag check.
sim/testsuite/sim/aarch64/
* adds.s: Add checks for values -2 and 1, where C is not set.
sim/aarch64/
* simulator.c (mul64hi): Shift carry left by 32.
(smulh): Change signum to negate. If negate, invert result, and add
carry bit if low part of multiply result is zero.
sim/testsuite/sim/aarch64/
* sumov.s: Correct compare test values.
* sumulh.s: New.
sim/aarch64/
* simulator.c (do_vec_ADDV): Mov val declaration inside each case,
with type set to input type size.
(do_vec_xtl): Change bias from 3 to 4 for byte case.
sim/testsuite/sim/aarch64/
* bit.s: Change cmp immediates to account for addv bug fix.
* cmtst.s, ldn_single.s, stn_single.s: Likewise.
* xtl.s: New.
sim/aarch64/
* simulator.c (do_vec_bit): Change loop limits from 16 and 8 to 4 and
2. Move test_false if inside loop. Fix logic for computing result
stored to vd.
sim/testsuite/sim/aarch64
* bit.s: New.
sim/aarch64/
* simulator.c: (LDn_STn_SINGLE_LANE_AND_SIZE): New.
(do_vec_LDn_single, do_vec_STn_single): New.
(do_vec_LDnR): Add and set new nregs var. Replace switch on nregs with
loop over nregs using new var n. Add n times size to address in loop.
Add n to vd in loop.
(do_vec_load_store): Add comment for instruction bit 24. New var
single to hold instruction bit 24. Add new code to use single. Move
ldnr support inside single if statements. Fix ldnr register counts
inside post if statement. Change HALT_NYI calls to HALT_UNALLOC.
sim/testsuite/sim/aarch64/
* ldn_single.s: New.
* ldnr.s: New.
* stn_single.s: New.
sim/aarch64/
* simulator.c (do_vec_ADDV): Call aarch64_set_vec_u64 instead of
aarch64_set_reg_u64. In case 2, call HALT_UNALLOC if not full. In
case 3, call HALT_UNALLOC unconditionally.
(do_vec_XTN): Delete shifts. In case 2, change index from i + 4 to
i + 2. Delete if on bias, change index to i + bias * X.
sim/testsuite/sim/aarch64/
* addv.s: New.
* xtn.s: New.
sim/aarch64/
* cpustate.c: Include math.h.
(aarch64_set_FP_float): Use signbit to check for signed zero.
(aarch64_set_FP_double): Likewise.
* simulator.c (do_vec_MOV_immediate, case 0x8): Add missing break.
(do_vec_mul): In all DO_VEC_WIDENING_MUL calls, make second and fourth
args same size as third arg.
(fmaxnm): Use isnan instead of fpclassify.
(fminnm, dmaxnm, dminnm): Likewise.
(do_vec_MLS): Reverse order of subtraction operands.
(dexSimpleFPCondSelect): Call aarch64_get_FP_double or
aarch64_get_FP_float to get source register contents.
(UINT_MIN, ULONG_MIN, FLOAT_UINT_MAX, FLOAT_UINT_MIN,
DOUBLE_UINT_MAX, DOUBLE_UINT_MIN, FLOAT_ULONG_MAX, FLOAT_ULONG_MIN,
DOUBLE_ULONG_MAX, DOUBLE_ULONG_MIN): New.
(do_fcvtzu): Use ULONG instead of LONG, and UINT instead of INT in
raise_exception calls.
sim/testsuite/sim/aarch64/
* fcsel.s: New.
* fcvtz.s: New.
* fminnm.s: New.
* mls.s: New.
* mul.s: New.
This applies the second part of GDB's End of Year Procedure, which
updates the copyright year range in all of GDB's files.
gdb/ChangeLog:
Update copyright year range in all GDB files.
sim/aarch64
* simulator.c (NEG, POS): Move before set_flags_for_add64.
(set_flags_for_add64): Replace with a modified copy of
set_flags_for_sub64.
sim/testsuite/sim/aarch64
* testutils.inc (pass): Move .Lpass to start.
(fail): Move .Lfail to start. Return 1 instead of 0.
(start): Moved .Lpass and .Lfail to here.
* adds.s: New.
* fstur.s: New.
* tbnz.s: New.
When building for mipstx39-rtems4.12 targets, some funcs use SD and CPU
implicitly. Restore the defines for these to the local sd and cpu vars.
This was broken by the clean up in commit d47f5b30d8.
Reported-by: Joel Sherrill <joel.sherrill@oarcorp.com>
The common sim tracing code already handles loading and tracking of
symbols from the target program so that it can show symbol info in
trace/disassembly calls. Once we touch up the trace code and add a
few API callbacks, ports don't need to do loading and searching of
symbol tables themselves anymore.
A few funcs are only used locally, so mark them static to avoid warnings
due to -Wmissing-prototypes.
Some funcs cast the return value wrong, so drop them (and let void * just
work by default).
Update some prototypes to be new style.
The current machs.h mixes common enums with Blackfin-specific defines.
This causes us troubles with header inclusion order such that we can't
drop the old SIM_CPU typedef (which is duplicated in common code). By
splitting the two up, we can unwind this dependency chain, and drop the
old typedef. It also fixes building with older gcc versions.
* simulator.c (aarch64_step): Revert pervious delta.
(aarch64_run): Call sim_events_tick after each
instruction is simulated, and if necessary call
sim_events_process.
* simulator.h: Revert previous delta.
* interp.c (sim_create_inferior): Allow for being called with a
NULL abfd parameter. If a bfd is provided, initialise the sim
with that start address.
* simulator.c (HALT_NYI): Just print out the numeric value of the
instruction when not tracing.
(aarch64_step): Change from static to global.
* simulator.h: Add a prototype for aarch64_step().
The major reason this header was needed, bfd_default_set_arch_mach,
has now moved to bfd.h.
gdb/
* amd64-darwin-tdep.c: Don't include libbfd.h.
* i386-darwin-tdep.c: Likewise.
* rs6000-nat.c: Likewise.
* rs6000-tdep.c: Likewise.
sim/aarch64/
* memory.c: Don't include libbfd.h.
sim/rl78/
* load.c: Don't include libbfd.h.
(rl78_load): Don't use private iovec seek or read.
sim/rx/
* load.c: Don't include libbfd.h.
(rx_load): Don't use private iovec seek or read.
PR target/ 19401
* avr/interp.c (step_once): Pass break instruction address to
sim_engine_halt function which writes that to PC. Remove code that
follows that function call as it is unreachable.
* armemu.c (Multiply64): Only issue error messages about invalid
arguments if debugging is enabled.
* armos.c (ARMul_OSHandleSWI): Ignore invalid flags.
* cpustate.h: Include config.h.
(union GRegisterValue): Add WORDS_BIGENDIAN check. For big endian code
use anonymous structs to align members.
* simulator.c (aarch64_step): Use sim_core_read_buffer and
endian_le2h_4 to read instruction from pc.
sim/sh/
* interp.c (dmul): Split into dmul_s and dmul_u. Use explicit integer
width types and simplify implementation.
* gencode.c (dmuls.l, dmulu.l): Use new functions dmul_s and dmul_u.
PR 19872
bfd * dwarf2.c (parse_comp_unit): Skip warning about unrecognised
version number if the version is zero.
bin * dwarf.c (display_debug_aranges): Skip warning about unrecognised
version number if the version is zero.
* cpustate.c (aarch64_set_reg_s32): New function.
(aarch64_set_reg_u32): New function.
(aarch64_get_FP_half): Place half precision value into the correct
slot of the union.
(aarch64_set_FP_half): Likewise.
* cpustate.h: Add prototypes for aarch64_set_reg_s32 and
aarch64_set_reg_u32.
* memory.c (FETCH_FUNC): Cast the read value to the access type
before converting it to the return type. Rename to FETCH_FUNC64.
(FETCH_FUNC32): New macro. Duplicates FETCH_FUNC64 but for 32-bit
accesses. Use for 32-bit memory access functions.
* simulator.c (ldrsb_wb): Use sign extension not zero extension.
(ldrb_scale_ext, ldrsh32_abs, ldrsh32_wb): Likewise.
(ldrsh32_scale_ext, ldrsh_abs, ldrsh64_wb): Likewise.
(ldrsh_scale_ext, ldrsw_abs): Likewise.
(ldrh32_abs): Store 32 bit value not 64-bits.
(ldrh32_wb, ldrh32_scale_ext): Likewise.
(do_vec_MOV_immediate): Fix computation of val.
(do_vec_MVNI): Likewise.
(DO_VEC_WIDENING_MUL): New macro.
(do_vec_mull): Use new macro.
(do_vec_mul): Use new macro.
(do_vec_MLA): Read values before writing.
(do_vec_xtl): Likewise.
(do_vec_SSHL): Select correct shift value.
(do_vec_USHL): Likewise.
(do_scalar_UCVTF): New function.
(do_scalar_vec): Call new function.
(store_pair_u64): Treat reads of SP as reads of XZR.
* cpustate.c: Remove space after asterisk in function parameters.
* decode.h (greg): Delete unused function.
(vreg, shift, extension, scaling, writeback, condcode): Likewise.
* simulator.c: Use INSTR macro in more places.
(HALT_NYI): Use sim_io_eprintf in place of fprintf.
Remove extraneous whitespace.
* cpustate.c (aarch64_get_FP_half): New function. Read a vector
register as a half precision floating point number.
(aarch64_set_FP_half): New function. Similar, but for setting
a half precision register.
(aarch64_get_thread_id): New function. Returns the value of the
CPU's TPIDR register.
(aarch64_get_FPCR): New function. Returns the value of the CPU's
floating point control register.
(aarch64_set_FPCR): New function. Set the value of the CPU's FPCR
register.
* cpustate.h: Add prototypes for new functions.
* sim-main.h (struct _sim_cpu): Add FPCR and tpidr fields.
* memory.c: Use unaligned core access functions for all memory
reads and writes.
* simulator.c (HALT_NYI): Generate an error message if tracing
will not tell the user why the simulator is halting.
(HALT_UNREACHABLE): Delete. Delete (unneeded) uses of the macro.
(INSTR): New time-saver macro.
(fldrb_abs): New function. Loads an 8-bit value using a scaled
offset.
(fldrh_abs): New function. Likewise for 16-bit values.
(do_vec_SSHL): Allow for negative shift values.
(do_vec_USHL): Likewise.
(do_vec_SHL): Correct computation of shift amount.
(do_vec_SSHR_USHR): Correct decision of signed vs unsigned
shifts and computation of shift value.
(clz): New function. Counts leading zero bits.
(do_vec_CLZ): New function. Implements CLZ (vector).
(do_vec_MOV_element): Call do_vec_CLZ.
(dexSimpleFPCondCompare): Implement.
(do_FCVT_half_to_single): New function. Implements one of the
FCVT operations.
(do_FCVT_half_to_double): New function. Likewise.
(do_FCVT_single_to_half): New function. Likewise.
(do_FCVT_double_to_half): New function. Likewise.
(dexSimpleFPDataProc1Source): Call new FCVT functions.
(do_scalar_SHL): Handle negative shifts.
(do_scalar_shift): Handle SSHR.
(do_scalar_USHL): New function.
(do_double_add): Simplify to just performing a double precision
add operation. Move remaining code into...
(do_scalar_vec): ... New function.
(dexLoadUnsignedImmediate): Call new fldrb_abs and fldrh_abs
functions.
(system_get): Add support for TPIDR, CTR, FPCR, FPSR and CPSR
registers.
(system_set): New function.
(do_MSR_immediate): New function. Stub for now.
(do_MSR_reg): New function. Likewise. Partially implements MSR
instruction.
(do_SYS): New function. Stub for now,
(dexSystem): Call new functions.
* simulator.c (set_flags_for_sub32): Correct type of signbit.
(CondCompare): Swap interpretation of bit 30.
(DO_ADDP): Delete macro.
(do_vec_ADDP): Copy source registers before starting to update
destination register.
(do_vec_FADDP): Likewise.
(do_vec_load_store): Fix computation of sizeof_operation.
(rbit64): Fix type of constant.
(aarch64_step): When displaying insn value, display all 32 bits.
* cgen-scache.c (scache_option_handler): Prevent possible
undefined behaviour computing the size of the scache by using
unsigned integers instead of signed integers.
This fixes PR sim/19441. In the MIPS simulator the microMIPS
functions in micromips.igen were not predicated on the microMIPS
models. This was causing build issues for some target triples.
This patch sets all the microMIPS specific functions to only be built if
the micromips32, micromips64 or micromipsdsp models are used.
PR sim/19441
* micromips.igen (delayslot_micromips): Enable for `micromips32',
`micromips64' and `micromipsdsp' only.
(process_isa_mode): Enable for `micromips32' and `micromips64' only.
(do_micromips_jalr, do_micromips_jal): Likewise.
(compute_movep_src_reg): Likewise.
(compute_andi16_imm): Likewise.
(convert_fmt_micromips): Likewise.
(convert_fmt_micromips_cvt_d): Likewise.
(convert_fmt_micromips_cvt_s): Likewise.
(FMT_MICROMIPS): Likewise.
(FMT_MICROMIPS_CVT_D): Likewise.
(FMT_MICROMIPS_CVT_S): Likewise.
This patch makes a fair number of fixes in the various comments of
sim-fpu.c, mostly to either better conform to the GNU Coding Standards
(sentences start with a capital letter, end with a period), or to
fix spelling mistakes.
sim/common/ChangeLog:
* sim-fpu.c: Minor comment fixes throughout.
This patch just makes a copy of formatting changes to better conform
with the GNU Coding Style.
sim/common/ChangeLog:
* sim-fpu.c (print_bits): Minor reformatting (no code change).
(sim_fpu_map): Likewise.
The mips bfd will sign extend 32-bit addresses into 64-bit values,
so if the entry happens to be 0x80000000 or higher, it is turned to
0xffffffff80000000 which points to memory that doesn't exist.
This wasn't an issue until commit 26f8bf63bf
as all addresses were automatically truncated there in the translate
function to 32-bits. When we cleaned up that code, the full 64-bits
were checked leading to many test failures for mips-sde-elf targets
and such.
Rather than stuffing the command line with a bunch of -D flags, start
moving things to config.h which is managed by autoheader. This makes
the makefile a bit simpler and the build output tighter, and it makes
the migration to automake easier as there are fewer vars to juggle.
We'll want to move the other options out too, but it'll take more work.
This was imported from the ppc sim, but that was only used to control
a single file, and that is already governed by the hw models. There's
no need to have a sep configure option here, especially since none of
the other sims are using it. Even when the code is enabled, there's
no runtime overhead.
Currently ports have to call SIM_AC_OPTION_ENVIRONMENT explicitly in
order to make the configure flag available. There's no real reason
to not allow this flag for all ports, so move it to the common sim
macro. This way we get standard behavior across all ports too.
Currently ports have to call SIM_AC_OPTION_ASSERT explicitly in order
to make the configure flag available, which none of them do. There's
no real reason to not allow this flag for all ports, so move it to the
common sim macro. This way we get standard behavior across all ports.
We don't have alternative nltvals.def files, so always symlinking
the targ-vals.def file to it doesn't gain us anything. It does
make the build more complicated though and a pain to convert to
something newer (like automake). Drop the symlinking entirely.
In the future, we'll want to explode this file anyways into the
respective arch dirs so things can be selected dynamically at
runtime, so it's not like we'll be bringing this back.
No other port calls this macro directly, and mips has it hardcoded
to the default -- disabling smp. In the future we'll enable this
for all targets in common code, so tidy up the mips code now.
Currently ports have to call SIM_AC_OPTION_INLINE explicitly in order
to make the configure flag available. There's no real reason to not
allow this flag for all ports, so move it to the common sim macro.
This way we get standard behavior across all ports too.
These options were never exposed for most sims (just the ppc one),
and they are really only useful on 32-bit x86 systems. Considering
modern systems tend to be 64-bit x86_64 and how well modern compilers
are at optimizing code, these have outlived their usefulness.
No other sub directory provides such a configuration option, so
drop it from the sim dir as well. This cleans up a good bit of
code in the process.
If people want to use custom flags for just the sim, they can
still run configure+make by hand in the sim subdir and use the
normal CFLAGS settings.
Now that cconfig.h doesn't exist, there's no need to build in the common
subdir anymore. We leave the configure/Makefile files in there as there
is a helper for developers to generate the nltvals.def file. Once that
gets cleaned up in the future though, we can drop the build logic too.
The common subdir sets up a cconfig.h file to hold checks for the common
code. In practice, most files still end up using config.h instead which
just leads to confusion.
Merge all the configure checks that went into cconfig.h into SIM_AC_COMMON
so we can drop the cconfig.h file altogether. Now there is only a single
config.h file like normal.
Some targets have started to add support for calling the disassembler
automatically when executing code. Add support for that directly into
the trace core.
