PPC_INT_FMT is redundant now that bfd.h pulls in inttypes.h if
available. Apparently MacOS Mojave defines int64_t as long long even
though long is also 64 bits, which confuses the logic selecting
PPC_INT_FMT (and BFD_PRI64 too). Hopefully inttypes.h is available on
Mojave.
PR 24028
include/
* opcode/ppc.h (PPC_INT_FMT): Delete.
opcodes/
* ppc-dis.c (print_insn_powerpc): Replace PPC_INT_FMT uses with
PRId64/PRIx64.
Linkers group input note sections with the same name into one output
note section with the same name. One output note section is placed in
one PT_NOTE segment. New linkers merge all input .note.gnu.property
sections into one output .note.gnu.property section with a single
NT_GNU_PROPERTY_TYPE_0 note in a single PT_NOTE segment. Since older
linkers treat input .note.gnu.property section as a generic note section
and just concatenate all input .note.gnu.property sections into one
output .note.gnu.property section without merging them, we may
see one or more NT_GNU_PROPERTY_TYPE_0 notes in PT_NOTE segment, which
are invalid.
GNU_PROPERTY_X86_UINT32_VALID was defined to address this issue such
that linker sets the bit for non-relocatable outputs. But it isn't
sufficient:
1. It doesn't cover generic properties.
2. When -mx86-used-note=yes is passed to x86 assembler, the
GNU_PROPERTY_X86_UINT32_VALID bit is set in GNU_PROPERTY_X86_ISA_1_USED
property in object file and older linkers generate invalid
NT_GNU_PROPERTY_TYPE_0 notes with the GNU_PROPERTY_X86_UINT32_VALID bit
set.
I am proposing the following changes:
1. Add PT_GNU_PROPERTY segment type:
# define PT_GNU_PROPERTY (PT_LOOS + 0x474e553)
which covers .note.gnu.property section.
2. Remove GNU_PROPERTY_X86_UINT32_VALID.
bfd/
PR ld/23900
* elf.c (get_program_header_size): Add a PT_GNU_PROPERTY
segment for NOTE_GNU_PROPERTY_SECTION_NAME.
(_bfd_elf_map_sections_to_segments): Create a PT_GNU_PROPERTY
segment for NOTE_GNU_PROPERTY_SECTION_NAME.
* elfxx-x86.c (_bfd_elf_link_setup_gnu_properties): Don't set
GNU_PROPERTY_X86_UINT32_VALID.
binutils/
PR ld/23900
* readelf.c (get_segment_type): Support PT_GNU_PROPERTY.
(decode_x86_isa): Don't check GNU_PROPERTY_X86_UINT32_VALID.
(decode_x86_feature_1): Likewise.
(decode_x86_feature_2): Likewise.
(print_gnu_property_note): Remove GNU_PROPERTY_X86_UINT32_VALID
check.
* testsuite/binutils-all/i386/empty.d: Updated.
* testsuite/binutils-all/x86-64/empty-x32.d: Likewise.
* testsuite/binutils-all/x86-64/empty.d: Likewise.
* testsuite/binutils-all/i386/pr21231b.s: Change
GNU_PROPERTY_X86_ISA_1_USED bits to 0x7fffffff.
* testsuite/binutils-all/x86-64/pr21231b.s: Likewise.
gas/
PR ld/23900
* config/tc-i386.c (x86_cleanup): Don't set
GNU_PROPERTY_X86_UINT32_VALID.
* testsuite/gas/i386/property-1.s: Change
GNU_PROPERTY_X86_ISA_1_USED bits to 0.
include/
PR ld/23900
* elf/common.h (PT_GNU_PROPERTY): New.
(GNU_PROPERTY_X86_UINT32_VALID): Removed.
ld/
PR ld/23900
* testsuite/ld-elf/elf.exp: Run PR ld/23900 test.
* testsuite/ld-elf/pr23900-1-32.rd: New file.
* testsuite/ld-elf/pr23900-1-64.rd: Likewise.
* testsuite/ld-elf/pr23900-1.d: Likewise.
* testsuite/ld-elf/pr23900-1.s: Likewise.
* testsuite/ld-elf/pr23900-2.s: Likewise.
* testsuite/ld-elf/pr23900-2a.d: Likewise.
* testsuite/ld-elf/pr23900-2b.d: Likewise.
* testsuite/ld-i386/ibt-plt-1.d: Adjusted.
* testsuite/ld-i386/ibt-plt-2c.d: Likewise.
* testsuite/ld-i386/ibt-plt-2d.d: Likewise.
* testsuite/ld-i386/ibt-plt-3d.d: Likewise.
* testsuite/ld-x86-64/ibt-plt-1-x32.d: Likewise.
* testsuite/ld-x86-64/ibt-plt-1.d: Likewise.
* testsuite/ld-x86-64/ibt-plt-2c-x32.d: Likewise.
* testsuite/ld-x86-64/ibt-plt-2c.d: Likewise.
* testsuite/ld-x86-64/ibt-plt-2d-x32.d: Likewise.
* testsuite/ld-x86-64/ibt-plt-2c.d: Likewise.
* testsuite/ld-x86-64/ibt-plt-3c-x32.d: Likewise.
* testsuite/ld-x86-64/ibt-plt-3c.d: Likewise.
* testsuite/ld-x86-64/ibt-plt-3d-x32.d: Likewise.
* testsuite/ld-x86-64/ibt-plt-3d.d: Likewise.
* testsuite/ld-i386/pr23372c.d: Expect <None>
for GNU_PROPERTY_X86_ISA_1_USED.
* testsuite/ld-x86-64/pr23372c-x32.d: Likewise.
* testsuite/ld-x86-64/pr23372c.d: Likewise.
* testsuite/ld-x86-64/pr23372d-x32.d: Likewise.
* testsuite/ld-x86-64/pr23372d.d: Likewise.
* testsuite/ld-x86-64/property-x86-5a.s: Change
GNU_PROPERTY_X86_ISA_1_USED bits to 0.
* testsuite/ld-x86-64/property-x86-5b.s: Likewise.
PR 88409
include * demangle.h (DEMANGLE_RECURSION_LIMIT): Increase to 2048.
binutils* NEWS: Note that recursion limit has increased to 2048.
* doc/binutils.texi: Likewise.
This patch addresses the multitude of bug reports about resource exhaustion
in libiberty's name demangling code. It adds a limit to the amount of
recursion that is allowed, before an error is triggered. It also adds a
new demangling option to disable this limit. (The limit is enabled by
default).
PR 87681
PR 87675
PR 87636
PR 87335
libiberty * cp-demangle.h (struct d_info): Add recursion_limit field.
* cp-demangle.c (d_function_type): If the recursion limit is
enabled and reached, return with a failure result.
(d_demangle_callback): If the recursion limit is enabled, check
for a mangled string that is so long that there is not enough
stack space for the local arrays.
* cplus-dem.c (struct work): Add recursion_level field.
(demangle_nested_args): If the recursion limit is enabled and
reached, return with a failure result.
include * demangle.h (DMGL_RECURSE_LIMIT): Define.
(DEMANGLE_RECURSION_LIMIT): Prototype.
binutuils * addr2line.c (demangle_flags): New static variable.
(long_options): Add --recurse-limit and --no-recurse-limit.
(translate_address): Pass demangle_flags to bfd_demangle.
(main): Handle --recurse-limit and --no-recurse-limit options.
* cxxfilt.c (flags): Add DMGL_RECURSE_LIMIT.
(long_options): Add --recurse-limit and --no-recurse-limit.
(main): Handle new options.
* dlltool.c (gen_def_file): Include DMGL_RECURSE_LIMIT in flags
passed to cplus_demangle.
* nm.c (demangle_flags): New static variable.
(long_options): Add --recurse-limit and --no-recurse-limit.
(main): Handle new options.
* objdump.c (demangle_flags): New static variable.
(usage): Add --recurse-limit and --no-recurse-limit.
(long_options): Likewise.
(objdump_print_symname): Pass demangle_flags to bfd_demangle.
(disassemble_section): Likewise.
(dump_dymbols): Likewise.
(main): Handle new options.
* prdbg.c (demangle_flags): New static variable.
(tg_variable): Pass demangle_flags to demangler.
(tg_start_function): Likewise.
* stabs.c (demangle_flags): New static variable.
(stab_demangle_template): Pass demangle_flags to demangler.
(stab_demangle_v3_argtypes): Likewise.
(stab_demangle_v3_arg): Likewise.
* doc/binutuls.texi: Document new command line options.
* NEWS: Mention the new feature.
* testsuite/config/default.exp (CXXFILT): Define if not already
defined.
(CXXFILTFLAGS): Likewise.
* testsuite/binutils-all/cxxfilt.exp: New file. Runs a few
simple tests of the cxxfilt program.
This patch started off just adding the warnings in tc-ppc.c about
incorrect usage of @l, @h and @ha in instructions that don't have
16-bit D-form fields. That unfortunately showed up three warnings in
ld/testsuite/ld-powerpc/vle-multiseg.s on instructions like
e_li r3, IV_table@l+0x00
which was being assembled to
8: 70 60 00 00 e_li r3,0
a: R_PPC_ADDR16_LO IV_table
The ADDR16_LO reloc is of course completely bogus on e_li, which has
a split 20-bit signed integer field in bits 0x1f7fff, the low 11 bit
in 0x7ff, the next 5 bits in 0x1f0000, and the high 4 bits in 0x7800.
Applying an ADDR16_LO reloc to the instruction potentially changes
the e_li instruction to e_add2i., e_add2is, e_cmp16i, e_mull2i,
e_cmpl16i, e_cmph16i, e_cmphl16i, e_or2i, e_and2i., e_or2is, e_lis,
e_and2is, or some invalid encodings.
Now there is a relocation that suits e_li, R_PPC_VLE_ADDR20, which was
added 2017-09-05 but I can't see code in gas to generate the
relocation. In any case, VLE_ADDR20 probably doesn't have the correct
semantics for @l since ideally you'd want an @l to pair with @h or @ha
to generate a 32-bit constant. Thus @l should only produce a 16-bit
value, I think. So we need some more relocations to handle e_li it
seems, or as I do in this patch, modify the behaviour of existing
relocations when applied to e_li instructions.
include/
* opcode/ppc.h (E_OPCODE_MASK, E_LI_MASK, E_LI_INSN): Define.
bfd/
* elf32-ppc.c (ppc_elf_howto_raw <R_PPC_VLE_ADDR20>): Correct
mask and shift value.
(ppc_elf_vle_split16): Use E_OPCODE_MASK. Handle e_li
specially.
gas/
* config/tc-ppc.c (md_assemble): Adjust relocs for VLE before
TLS tweaks. Handle e_li. Warn on unexpected operand field
for lo16/hi16/ha16 relocs.
The RISC-V assembler generates fake labels with the name '.L0 ' as
part of the debug information (see
gas/config/tc-riscv.h:FAKE_LABEL_NAME).
The problem is that currently, when disassembling an object file, the
output looks like this (this is an example from the GDB testsuite, but
is pretty representative of anything with debug information):
000000000000001e <main>:
1e: 7179 addi sp,sp,-48
20: f406 sd ra,40(sp)
22: f022 sd s0,32(sp)
24: 1800 addi s0,sp,48
0000000000000026 <.L0 >:
26: 87aa mv a5,a0
28: feb43023 sd a1,-32(s0)
2c: fcc43c23 sd a2,-40(s0)
30: fef42623 sw a5,-20(s0)
0000000000000034 <.L0 >:
34: fec42783 lw a5,-20(s0)
38: 0007871b sext.w a4,a5
3c: 678d lui a5,0x3
3e: 03978793 addi a5,a5,57 # 3039 <.LASF30+0x2a9d>
42: 02f71463 bne a4,a5,6a <.L0 >
0000000000000046 <.L0 >:
46: 000007b7 lui a5,0x0
4a: 0007b783 ld a5,0(a5) # 0 <need_malloc>
4e: 6f9c ld a5,24(a5)
0000000000000050 <.L0 >:
50: 86be mv a3,a5
52: 466d li a2,27
54: 4585 li a1,1
56: 000007b7 lui a5,0x0
5a: 00078513 mv a0,a5
5e: 00000097 auipc ra,0x0
62: 000080e7 jalr ra # 5e <.L0 +0xe>
0000000000000066 <.L0 >:
66: 4785 li a5,1
68: a869 j 102 <.L0 >
000000000000006a <.L0 >:
6a: 000007b7 lui a5,0x0
6e: 00078513 mv a0,a5
72: 00000097 auipc ra,0x0
76: 000080e7 jalr ra # 72 <.L0 +0x8>
The frequent repeated '.L0 ' labels are pointless, as they are
non-unique there's no way to match a use of '.L0 ' to its appearence
in the output, so we'd be better off just not printing it at all.
That's what this patch does by defining a 'symbol_is_valid' method for
RISC-V. With this commit, the same disassembly now looks like this:
000000000000001e <main>:
1e: 7179 addi sp,sp,-48
20: f406 sd ra,40(sp)
22: f022 sd s0,32(sp)
24: 1800 addi s0,sp,48
26: 87aa mv a5,a0
28: feb43023 sd a1,-32(s0)
2c: fcc43c23 sd a2,-40(s0)
30: fef42623 sw a5,-20(s0)
34: fec42783 lw a5,-20(s0)
38: 0007871b sext.w a4,a5
3c: 678d lui a5,0x3
3e: 03978793 addi a5,a5,57 # 3039 <.LASF30+0x2a9d>
42: 02f71463 bne a4,a5,6a <.L4>
46: 000007b7 lui a5,0x0
4a: 0007b783 ld a5,0(a5) # 0 <need_malloc>
4e: 6f9c ld a5,24(a5)
50: 86be mv a3,a5
52: 466d li a2,27
54: 4585 li a1,1
56: 000007b7 lui a5,0x0
5a: 00078513 mv a0,a5
5e: 00000097 auipc ra,0x0
62: 000080e7 jalr ra # 5e <main+0x40>
66: 4785 li a5,1
68: a869 j 102 <.L5>
000000000000006a <.L4>:
6a: 000007b7 lui a5,0x0
6e: 00078513 mv a0,a5
72: 00000097 auipc ra,0x0
76: 000080e7 jalr ra # 72 <.L4+0x8>
In order to share the fake label between the assembler and the
libopcodes library, I've added some new defines RISCV_FAKE_LABEL_NAME
and RISCV_FAKE_LABEL_CHAR in include/opcode/riscv.h. I could have
just moved FAKE_LABEL_NAME to the include file, however, I thnk this
would be confusing, someone working on the assembler would likely not
expect to find FAKE_LABEL_NAME defined outside of the assembler source
tree. By introducing the RISCV_FAKE_LABEL_* defines I can leave the
assembler standard FAKE_LABEL_ defines in the assembler source, but
still share the RISCV_FAKE_LABEL_* with libopcodes.
gas/ChangeLog:
* config/tc-riscv.h (FAKE_LABEL_NAME): Define as
RISCV_FAKE_LABEL_NAME.
(FAKE_LABEL_CHAR): Define as RISCV_FAKE_LABEL_CHAR.
include/ChangeLog:
* dis-asm.h (riscv_symbol_is_valid): Declare.
* opcode/riscv.h (RISCV_FAKE_LABEL_NAME): Define.
(RISCV_FAKE_LABEL_CHAR): Define.
opcodes/ChangeLog:
* disassembler.c (disassemble_init_for_target): Add RISC-V
initialisation.
* riscv-dis.c (riscv_symbol_is_valid): New function.
This patch is part of the patch series to add support for ARMv8.5-A
Memory Tagging Extensions which is an optional extension to
ARMv8.5-A and is enabled using the +memtag command line option.
This patch add support to the Bulk Allocation Tag instructions from
MTE. These are the following instructions added in this patch:
- LDGV <Xt>, [<Xn|SP>]!
- STGV <Xt>, [<Xn|SP>]!
This needed a new kind of operand for the new addressing [<Xn|SP>]!
since this has no offset and only takes a pre-indexed version.
Hence AARCH64_OPND_ADDR_SIMPLE_2 and ldtdgv_indexed are introduced.
(AARCH64_OPND_ADDR_SIMPLE fulfilled the no offset criteria but does
not allow writeback). We also needed new encoding and decoding
functions to be able to do the same.
where
<Xt> : Is the 64-bit destination GPR.
<Xn|SP> : Is the 64-bit first source GPR or Stack pointer.
*** include/ChangeLog ***
2018-11-12 Sudakshina Das <sudi.das@arm.com>
* opcode/aarch64.h (aarch64_opnd): Add AARCH64_OPND_ADDR_SIMPLE_2.
(aarch64_insn_class): Add ldstgv_indexed.
*** opcodes/ChangeLog ***
2018-11-12 Sudakshina Das <sudi.das@arm.com>
* aarch64-asm.c (aarch64_ins_addr_simple_2): New.
* aarch64-asm.h (ins_addr_simple_2): Declare the above.
* aarch64-dis.c (aarch64_ext_addr_simple_2): New.
* aarch64-dis.h (ext_addr_simple_2): Declare the above.
* aarch64-opc.c (operand_general_constraint_met_p): Add case for
AARCH64_OPND_ADDR_SIMPLE_2 and ldstgv_indexed.
(aarch64_print_operand): Add case for AARCH64_OPND_ADDR_SIMPLE_2.
* aarch64-tbl.h (aarch64_opcode_table): Add stgv and ldgv.
(AARCH64_OPERANDS): Define ADDR_SIMPLE_2.
* aarch64-asm-2.c: Regenerated.
* aarch64-dis-2.c: Regenerated.
* aarch64-opc-2.c: Regenerated.
*** gas/ChangeLog ***
2018-11-12 Sudakshina Das <sudi.das@arm.com>
* config/tc-aarch64.c (parse_operands): Add switch case for
AARCH64_OPND_ADDR_SIMPLE_2 and allow [base]! for it.
(warn_unpredictable_ldst): Exempt ldstgv_indexed for ldgv.
* testsuite/gas/aarch64/armv8_5-a-memtag.s: Add tests for ldgv and stgv.
* testsuite/gas/aarch64/armv8_5-a-memtag.d: Likewise.
* testsuite/gas/aarch64/illegal-memtag.s: Likewise.
* testsuite/gas/aarch64/illegal-memtag.l: Likewise.
This patch is part of the patch series to add support for ARMv8.5-A
Memory Tagging Extensions which is an optional extension to
ARMv8.5-A and is enabled using the +memtag command line option.
This patch add support to the Tag setting instructions from
MTE which consists of the following instructions:
- STG [<Xn|SP>, #<simm>]
- STG [<Xn|SP>, #<simm>]!
- STG [<Xn|SP>], #<simm>
- STZG [<Xn|SP>, #<simm>]
- STZG [<Xn|SP>, #<simm>]!
- STZG [<Xn|SP>], #<simm>
- ST2G [<Xn|SP>, #<simm>]
- ST2G [<Xn|SP>, #<simm>]!
- ST2G [<Xn|SP>], #<simm>
- STZ2G [<Xn|SP>, #<simm>]
- STZ2G [<Xn|SP>, #<simm>]!
- STZ2G [<Xn|SP>], #<simm>
- STGP <Xt>, <Xt2>, [<Xn|SP>, #<imm>]
- STGP <Xt>, <Xt2>, [<Xn|SP>, #<imm>]!
- STGP <Xt>, <Xt2>, [<Xn|SP>], #<imm>
where
<Xn|SP> : Is the 64-bit GPR or Stack pointer.
<simm> : Is the optional signed immediate offset, a multiple of 16
in the range -4096 to 4080, defaulting to 0.
*** include/ChangeLog ***
2018-11-12 Sudakshina Das <sudi.das@arm.com>
* opcode/aarch64.h (aarch64_opnd): Add AARCH64_OPND_ADDR_SIMM11
and AARCH64_OPND_ADDR_SIMM13.
(aarch64_opnd_qualifier): Add new AARCH64_OPND_QLF_imm_tag.
*** opcodes/ChangeLog ***
2018-11-12 Sudakshina Das <sudi.das@arm.com>
* aarch64-opc.c (aarch64_opnd_qualifiers): Add new data
for AARCH64_OPND_QLF_imm_tag.
(operand_general_constraint_met_p): Add case for
AARCH64_OPND_ADDR_SIMM11 and AARCH64_OPND_ADDR_SIMM13.
(aarch64_print_operand): Likewise.
* aarch64-tbl.h (QL_LDST_AT, QL_STGP): New.
(aarch64_opcode_table): Add stg, stzg, st2g, stz2g and stgp
for both offset and pre/post indexed versions.
(AARCH64_OPERANDS): Define ADDR_SIMM11 and ADDR_SIMM13.
* aarch64-asm-2.c: Regenerated.
* aarch64-dis-2.c: Regenerated.
* aarch64-opc-2.c: Regenerated.
*** gas/ChangeLog ***
2018-11-12 Sudakshina Das <sudi.das@arm.com>
* config/tc-aarch64.c (parse_operands): Add switch case for
AARCH64_OPND_ADDR_SIMM11 and AARCH64_OPND_ADDR_SIMM13.
(fix_insn): Likewise.
(warn_unpredictable_ldst): Exempt STGP.
* testsuite/gas/aarch64/armv8_5-a-memtag.s: Add tests for stg, st2g,
stzg, stz2g and stgp.
* testsuite/gas/aarch64/armv8_5-a-memtag.d: Likewise.
* testsuite/gas/aarch64/illegal-memtag.s: Likewise.
* testsuite/gas/aarch64/illegal-memtag.l: Likewise.
This patch is part of the patch series to add support for ARMv8.5-A
Memory Tagging Extensions which is an optional extension to
ARMv8.5-A and is enabled using the +memtag command line option.
This patch add support to the Tag generation instructions from
MTE. These are the following instructions added in this patch:
- IRG <Xd|SP>, <Xn|SP>{, Xm}
- ADDG <Xd|SP>, <Xn|SP>, #<uimm1>. #<uimm2>
- SUBG <Xd|SP>, <Xn|SP>, #<uimm1>. #<uimm2>
- GMI <Xd>, <Xn|SP>, <Xm>
where
<Xd|SP> : Is the 64-bit destination GPR or Stack pointer.
<Xn|SP> : Is the 64-bit source GPR or Stack pointer.
<uimm6> : Is the unsigned immediate, a multiple of 16
in the range 0 to 1008.
<uimm4> : Is the unsigned immediate, in the range 0 to 15.
*** include/ChangeLog ***
2018-11-12 Sudakshina Das <sudi.das@arm.com>
* opcode/aarch64.h (aarch64_opnd): Add
AARCH64_OPND_UIMM4_ADDG and AARCH64_OPND_UIMM10 as new enums.
*** opcodes/ChangeLog ***
2018-11-12 Sudakshina Das <sudi.das@arm.com>
* aarch64-opc.h (aarch64_field_kind): New FLD_imm4_3.
(OPD_F_SHIFT_BY_4, operand_need_shift_by_four): New.
* aarch64-opc.c (fields): Add entry for imm4_3.
(operand_general_constraint_met_p): Add cases for
AARCH64_OPND_UIMM4_ADDG and AARCH64_OPND_UIMM10.
(aarch64_print_operand): Likewise.
* aarch64-tbl.h (QL_ADDG): New.
(aarch64_opcode_table): Add addg, subg, irg and gmi.
(AARCH64_OPERANDS): Define UIMM4_ADDG and UIMM10.
* aarch64-asm.c (aarch64_ins_imm): Add case for
operand_need_shift_by_four.
* aarch64-asm-2.c: Regenerated.
* aarch64-dis-2.c: Regenerated.
* aarch64-opc-2.c: Regenerated.
*** gas/ChangeLog ***
2018-11-12 Sudakshina Das <sudi.das@arm.com>
* config/tc-aarch64.c (parse_operands): Add switch case for
AARCH64_OPND_UIMM4_ADDG and AARCH64_OPND_UIMM10.
* testsuite/gas/aarch64/armv8_5-a-memtag.s: New.
* testsuite/gas/aarch64/armv8_5-a-memtag.d: Likewise.
* testsuite/gas/aarch64/illegal-memtag.s: Likewise.
* testsuite/gas/aarch64/illegal-memtag.l: Likewise.
* testsuite/gas/aarch64/illegal-memtag.d: Likewise.
This patch is part of the patch series to add support for ARMv8.5-A
Memory Tagging Extensions. Memory Tagging Extension is an optional extension to
ARMv8.5-A and is enabled using the +memtag command line option.
This patch adds the new command line option and the new feature macros.
*** include/ChangeLog ***
2018-11-12 Sudakshina Das <sudi.das@arm.com>
* opcode/aarch64.h (AARCH64_FEATURE_MEMTAG): New.
*** opcodes/ChangeLog ***
2018-11-12 Sudakshina Das <sudi.das@arm.com>
* aarch64-tbl.h (aarch64_feature_memtag): New.
(MEMTAG, MEMTAG_INSN): New.
*** gas/ChangeLog ***
2018-11-12 Sudakshina Das <sudi.das@arm.com>
* config/tc-aarch64.c (aarch64_features): Add "memtag"
as a new option.
* doc/c-aarch64.texi: Document the same.
bfd * mach-o.h: Add new enums for BFD_MACH_O_PLATFORM_MACOS,
BFD_MACH_O_PLATFORM_IOS, BFD_MACH_O_PLATFORM_TVOS,
BFD_MACH_O_PLATFORM_WATCHOS, BFD_MACH_O_PLATFORM_BRIDGEOS,
BFD_MACH_O_TOOL_CLANG, BFD_MACH_O_TOOL_SWIFT, BFD_MACH_O_TOOL_LD.
(struct bfd_mach_o_note_command): New.
(struct bfd_mach_o_build_version_tool): New.
(struct bfd_mach_o_build_version_command): New.
(bfd_mach_o_read_version_min): Don't split version into
a few fields. Rename reserved to sdk.
* mach-o.c (bfd_mach_o_read_version_min): Don't split version into a
few fields. Rename reserved to sdk.
(bfd_mach_o_read_command): Handle LC_VERSION_MIN_TVOS, LC_NOTE,
LC_BUILD_VERSION.
(bfd_mach_o_read_note): New.
(bfd_mach_o_read_build_version): New.
PR 23728
binutils* od-macho.c (printf_version): New.
(dump_load_command): Use it to print version. Print sdk version. Print
version info for watchOS and tvOS. Print LC_NOTE, LC_BUILD_VERSION.
(dump_buld_version): New.
(bfd_mach_o_platform_name): New
(bfd_mach_o_tool_name): New
* mach-o/external.h (mach_o_nversion_min_command_external): Rename
reserved to sdk.
(mach_o_note_command_external): New.
(mach_o_build_version_command_external): New.
* mach-o/loader.h (BFD_MACH_O_LC_VERSION_MIN_TVOS): Define.
(BFD_MACH_O_LC_NOTE): Define.
This patch addresses the following
1) Adding ARMv8.5-A in select_arm_features.
2) Updating the feature macro so that the new ARM_EXT2_* features for
Armv8.5-A are moved to ARM_AEXT2_V8_5A.
*** opcodes/ChangeLog ***
2018-11-06 Sudakshina Das <sudi.das@arm.com>
* arm-dis.c (select_arm_features): Update bfd_mach_arm_8
with Armv8.5-A. Remove reduntant ARM_EXT2_FP16_FML.
*** include/ChangeLog ***
2018-11-06 Sudakshina Das <sudi.das@arm.com>
* opcode/arm.h (ARM_ARCH_V8_5A): Move ARM_EXT2_PREDRES and
ARM_EXT2_SB to ...
(ARM_AEXT2_V8_5A): Here.
Third party tools produce 32 bit relocs at index 6 with strange properties.
This change moves the existing 32 bit reloc (R_S12Z_EXT32) to index 7
and introduces a new one (R_S12Z_CW32) at index 6 to try to support code
generated by these tools.
* bfd/elf32-s12z.c (elf_s12z_howto_table) [R_S12Z_CW32]: New member.
* binutils/readelf.c (is_32bit_abs_reloc): Reloc type 7 is also 32 bit.
* include/elf/s12z.h (elf_s12z_reloc_tpe) [RELOC_NUMBER (R_S12Z_CW32)]: New enum.
This patch is part of the patch series to add support for ARMv8.5-A
extensions.
(https://developer.arm.com/products/architecture/cpu-architecture/a-profile/exploration-tools)
The encodings can be found in the System Register XML.
This patch adds support for the mitigation for Spectre Variant 4 by
adding the PSTATE bit SSBS which are accessible using MSR and MRS
instructions. Although this is a mandatory addition to the ARMv8.5-A,
it is permitted to be added to any version of the ARMv8 architecture.
This is enabled using the command line option of +ssbs for older
versions.
*** include/ChangeLog ***
2018-10-09 Sudakshina Das <sudi.das@arm.com>
* opcode/aarch64.h (AARCH64_FEATURE_SSBS): New.
(AARCH64_ARCH_V8_5): Add AARCH64_FEATURE_SSBS by default.
*** opcodes/ChangeLog ***
2018-10-09 Sudakshina Das <sudi.das@arm.com>
* aarch64-opc.c (operand_general_constraint_met_p): Add
SSBS in the check for one-bit immediate.
(aarch64_sys_regs): New entry for SSBS.
(aarch64_sys_reg_supported_p): New check for above.
(aarch64_pstatefields): New entry for SSBS.
(aarch64_pstatefield_supported_p): New check for above.
*** gas/ChangeLog ***
2018-10-09 Sudakshina Das <sudi.das@arm.com>
* config/tc-aarch64.c (aarch64_features): Add new "ssbs".
* doc/c-aarch64.texi: Document the same.
* testsuite/gas/aarch64/ssbs-illegal1.d: New test.
* testsuite/gas/aarch64/ssbs-illegal1.l: New test.
* testsuite/gas/aarch64/ssbs-illegal2.d: New test.
* testsuite/gas/aarch64/ssbs-illegal2.l: New test.
* testsuite/gas/aarch64/ssbs.s: New test.
* testsuite/gas/aarch64/ssbs1.d: Test with +ssbs
* testsuite/gas/aarch64/ssbs2.d: Test with armv8.5-a.
This patch is part of the patch series to add support for ARMv8.5-A
extensions.
(https://developer.arm.com/products/architecture/cpu-architecture/a-profile/exploration-tools)
The encodings can be found in the System Register XML.
This patch adds the new system registers SCXTNUM_ELx and ID_PFR2_EL1.
*** include/ChangeLog ***
2018-10-09 Sudakshina Das <sudi.das@arm.com>
* opcode/aarch64.h (AARCH64_FEATURE_SCXTNUM): New.
(AARCH64_FEATURE_ID_PFR2): New.
(AARCH64_ARCH_V8_5): Add both by default.
*** opcodes/ChangeLog ***
2018-10-09 Sudakshina Das <sudi.das@arm.com>
* aarch64-opc.c (aarch64_sys_regs): New entries for
scxtnum_el[0,1,2,3,12] and id_pfr2_el1.
(aarch64_sys_reg_supported_p): New checks for above.
*** gas/ChangeLog ***
2018-10-09 Sudakshina Das <sudi.das@arm.com>
* testsuite/gas/aarch64/sysreg-4.s: Test registers
scxtnum_el[0,1,2,3,12] and id_pfr2_el1.
* testsuite/gas/aarch64/sysreg-4.d: Likewise.
* testsuite/gas/aarch64/illegal-sysreg-4.l: Likewise.
This patch is part of the patch series to add support for ARMv8.5-A
extensions.
(https://developer.arm.com/products/architecture/cpu-architecture/a-profile/docs/ddi0596/a/a64-base-instructions-alphabetic-order/bti-branch-target-identification)
The Branch Target Identification instructions (BTI) are allocated to
existing HINT space, using HINT numbers 32, 34, 36, 38, such that
bits[7:6] of the instruction identify the compatibility of the BTI
instruction to different branches.
BTI {<targets>}
where <targets> one of the following, specifying which type of
indirection is allowed:
j : Can be a target of any BR Xn isntruction.
c : Can be a target of any BLR Xn and BR {X16|X17}.
jc: Can be a target of any free branch.
A BTI instruction without any <targets> is the strictest of all and
can not be a target of nay free branch.
*** include/ChangeLog ***
2018-10-09 Sudakshina Das <sudi.das@arm.com>
* opcode/aarch64.h (AARCH64_FEATURE_BTI): New.
(AARCH64_ARCH_V8_5): Add AARCH64_FEATURE_BTI by default.
(aarch64_opnd): Add AARCH64_OPND_BTI_TARGET.
(HINT_OPD_CSYNC, HINT_OPD_C, HINT_OPD_J): New macros to
define HINT #imm values.
(HINT_OPD_JC, HINT_OPD_NULL): Likewise.
*** opcodes/ChangeLog ***
2018-10-09 Sudakshina Das <sudi.das@arm.com>
* aarch64-opc.h (HINT_OPD_NOPRINT, HINT_ENCODE): New.
(HINT_FLAG, HINT_VALUE): New macros to encode NO_PRINT flag
with the hint immediate.
* aarch64-opc.c (aarch64_hint_options): New entries for
c, j, jc and default (with HINT_OPD_F_NOPRINT flag) for BTI.
(aarch64_print_operand): Add case for AARCH64_OPND_BTI_TARGET
while checking for HINT_OPD_F_NOPRINT flag.
* aarch64-dis.c (aarch64_ext_hint): Use new HINT_VALUE to
extract value.
* aarch64-tbl.h (aarch64_feature_bti, BTI, BTI_INSN): New.
(aarch64_opcode_table): Add entry for BTI.
(AARCH64_OPERANDS): Add new description for BTI targets.
* aarch64-asm-2.c: Regenerate.
* aarch64-dis-2.c: Regenerate.
* aarch64-opc-2.c: Regenerate.
*** gas/ChangeLog ***
2018-10-09 Sudakshina Das <sudi.das@arm.com>
* config/tc-aarch64.c (parse_bti_operand): New.
(process_omitted_operand): Add case for AARCH64_OPND_BTI_TARGET.
(parse_operands): Likewise.
* testsuite/gas/aarch64/system.d: Update for BTI.
* testsuite/gas/aarch64/bti.s: New.
* testsuite/gas/aarch64/bti.d: New.
* testsuite/gas/aarch64/illegal-bti.d: New.
* testsuite/gas/aarch64/illegal-bti.l: New.
This patch is part of the patch series to add support for ARMv8.5-A
extensions.
(https://developer.arm.com/products/architecture/cpu-architecture/a-profile/exploration-tools)
The encodings can be found in the System Register XML.
This patch adds the following:
MSR Xn, RNDR
MSR Xn, RNDRRS
These are optional instructions in ARMv8.5-A and hence the new
+rng is added.
*** include/ChangeLog ***
2018-10-09 Sudakshina Das <sudi.das@arm.com>
* opcode/aarch64.h (AARCH64_FEATURE_RNG): New.
*** opcodes/ChangeLog ***
2018-10-09 Sudakshina Das <sudi.das@arm.com>
* aarch64-opc.c (aarch64_sys_regs): New entries for
rndr and rndrrs.
(aarch64_sys_reg_supported_p): New check for above.
*** gas/ChangeLog ***
2018-10-09 Sudakshina Das <sudi.das@arm.com>
* config/tc-aarch64.c (aarch64_features): New "rng" option.
* doc/c-aarch64.texi: Document the same.
* testsuite/gas/aarch64/sysreg-4.s: Test both instructions.
* testsuite/gas/aarch64/sysreg-4.d: Likewise.
* testsuite/gas/aarch64/illegal-sysreg-4.l: Likewise.
This patch is part of the patch series to add support for ARMv8.5-A
extensions.
(https://developer.arm.com/products/architecture/cpu-architecture/a-profile/docs/ddi0596/a/a64-base-instructions-alphabetic-order/dc-data-cache-operation-an-alias-of-sys)
This patch adds the DC CVADP instruction. Since this has a separate
identification mechanism a new feature bit is added.
*** include/ChangeLog ***
2018-10-09 Sudakshina Das <sudi.das@arm.com>
* opcode/aarch64.h (AARCH64_FEATURE_CVADP): New.
*** opcodes/ChangeLog ***
2018-10-09 Sudakshina Das <sudi.das@arm.com>
* aarch64-opc.c (aarch64_sys_regs_dc): New entry for cvadp.
(aarch64_sys_ins_reg_supported_p): New check for above.
*** gas/ChangeLog ***
2018-10-09 Sudakshina Das <sudi.das@arm.com>
* testsuite/gas/aarch64/sysreg-4.s: Test instruction.
* testsuite/gas/aarch64/sysreg-4.d: Likewise.
* testsuite/gas/aarch64/illegal-sysreg-4.l: Likewise.
This patch is part of the patch series to add support for ARMv8.5-A
extensions.
(https://developer.arm.com/products/architecture/cpu-architecture/a-profile/docs/ddi0596/a/a64-base-instructions-alphabetic-order)
This patch adds the prediction restriction instructions (that is, cfp,
dvp, cpp). These instructions are retrospectively made optional for
all versions of the architecture from ARMv8.0 to ARMv8.4 and is
mandatory from ARMv8.5. Hence adding a new +predres which can be used
by the older architectures.
*** include/ChangeLog ***
2018-10-09 Sudakshina Das <sudi.das@arm.com>
* opcode/aarch64.h (AARCH64_FEATURE_PREDRES): New.
(AARCH64_ARCH_V8_5): Add AARCH64_FEATURE_PREDRES by default.
(aarch64_opnd): Add AARCH64_OPND_SYSREG_SR.
(aarch64_sys_regs_sr): Declare new table.
*** opcodes/ChangeLog ***
2018-10-09 Sudakshina Das <sudi.das@arm.com>
* aarch64-dis.c (aarch64_ext_sysins_op): Add case for
AARCH64_OPND_SYSREG_SR.
* aarch64-opc.c (aarch64_print_operand): Likewise.
(aarch64_sys_regs_sr): Define table.
(aarch64_sys_ins_reg_supported_p): Check for RCTX with
AARCH64_FEATURE_PREDRES.
* aarch64-tbl.h (aarch64_feature_predres): New.
(PREDRES, PREDRES_INSN): New.
(aarch64_opcode_table): Add entries for cfp, dvp and cpp.
(AARCH64_OPERANDS): Add new description for SYSREG_SR.
* aarch64-asm-2.c: Regenerate.
* aarch64-dis-2.c: Regenerate.
* aarch64-opc-2.c: Regenerate.
*** gas/ChangeLog ***
2018-10-09 Sudakshina Das <sudi.das@arm.com>
* config/tc-aarch64.c (aarch64_sys_regs_sr_hsh): New.
(parse_operands): Add entry for AARCH64_OPND_SYSREG_SR.
(md_begin): Allocate and initialize aarch64_sys_regs_sr_hsh
with aarch64_sys_regs_sr.
(aarch64_features): Add new "predres" option for older
architectures.
* doc/c-aarch64.texi: Document the same.
* testsuite/gas/aarch64/sysreg-4.s: New.
* testsuite/gas/aarch64/sysreg-4.d: New.
* testsuite/gas/aarch64/illegal-sysreg-4.d: New.
* testsuite/gas/aarch64/illegal-sysreg-4.l: New.
* testsuite/gas/aarch64/predres.s: New.
* testsuite/gas/aarch64/predres.d: New.
This patch is part of the patch series to add support for ARMv8.5-A
extensions.
(https://developer.arm.com/products/architecture/cpu-architecture/a-profile/docs/ddi0596/a/a64-base-instructions-alphabetic-order)
This instruction is retrospectively made optional for all versions of
the architecture from ARMv8.0 to ARMv8.4 and is mandatory from
ARMv8.5. Hence a new command line option of "+sb" is added for older
architectures.
*** include/ChangeLog ***
2018-10-09 Sudakshina Das <sudi.das@arm.com>
* opcode/aarch64.h (AARCH64_FEATURE_SB): New.
(AARCH64_ARCH_V8_5): Add AARCH64_FEATURE_SB by default.
*** opcodes/ChangeLog ***
2018-10-09 Sudakshina Das <sudi.das@arm.com>
* aarch64-tbl.h (aarch64_feature_sb): New.
(SB, SB_INSN): New.
(aarch64_opcode_table): Add entry for sb.
* aarch64-asm-2.c: Regenerate.
* aarch64-dis-2.c: Regenerate.
* aarch64-opc-2.c: Regenerate.
*** gas/ChangeLog ***
2018-10-09 Sudakshina Das <sudi.das@arm.com>
* config/tc-aarch64.c (aarch64_features): Add new "sb" option
for older architectures.
* doc/c-aarch64.texi: Document the same.
* testsuite/gas/aarch64/sb.s: New.
* testsuite/gas/aarch64/sb.d: New.
This patch is part of the patch series to add support for ARMv8.5-A
extensions.
(https://developer.arm.com/products/architecture/cpu-architecture/a-profile/docs/ddi0596/a/a64-base-instructions-alphabetic-order)
This patch adds the data processing instructions that are new to
ARMv8.5-A.
1) There are 2 instructions: xaflag, axflag, that are added to
manipulate the states of the flag and are used to convert between the
Arm representation and the fcmp representation.
2) The other instructions are rounding instructions which have 8
versions based on whether the floating-point number is a
Single-Precision or Double-Precision number, whether the target
integer is a 32-bit or 64-bit integer and whether the rounding mode is
the ambient rounding mode or to zero. Each of these instruction is
available in both Scalar and Vector forms.
Since both 1) and 2) have separate identification mechanism and it is
permissible that a ARMv8.4 compliant implementation may include any
arbitrary subset of the ARMv8.5 features unless otherwise specified,
new feature bits are added.
*** include/ChangeLog ***
2018-10-09 Sudakshina Das <sudi.das@arm.com>
* opcode/aarch64.h (AARCH64_FEATURE_FLAGMANIP): New.
(AARCH64_FEATURE_FRINTTS): New.
(AARCH64_ARCH_V8_5): Add both by default.
*** opcodes/ChangeLog ***
2018-10-09 Sudakshina Das <sudi.das@arm.com>
* aarch64-tbl.h (aarch64_feature_flagmanip): New.
(aarch64_feature_frintts): New.
(FLAGMANIP, FRINTTS): New.
(aarch64_opcode_table): Add entries for xaflag, axflag
and frint[32,64][x,z] instructions.
* aarch64-asm-2.c: Regenerate.
* aarch64-dis-2.c: Regenerate.
* aarch64-opc-2.c: Regenerate.
*** gas/ChangeLog ***
2018-10-09 Sudakshina Das <sudi.das@arm.com>
* testsuite/gas/aarch64/armv8_5-a-dp.s: New.
* testsuite/gas/aarch64/armv8_5-a-dp.d: New.
This patch is part of the patch series to add support for ARMv8.5-A
extensions.
(https://developer.arm.com/products/architecture/cpu-architecture/a-profile/exploration-tools)
This is the first of the patch series and adds -march=armv8.5-a and
other internal feature marcos needed for it.
2018-10-09 Sudakshina Das <sudi.das@arm.com>
* config/tc-aarch64.c (aarch64_archs): New entry for armv8.5-a.
* doc/c-aarch64.texi: Add documentation for the same.
*** include/ChnageLog ***
2018-10-09 Sudakshina Das <sudi.das@arm.com>
* opcode/aarch64.h (AARCH64_FEATURE_V8_5): New.
(AARCH64_ARCH_V8_5): New.
*** opcodes/ChangeLog ***
2018-10-09 Sudakshina Das <sudi.das@arm.com>
* aarch64-tbl.h (aarch64_feature_set aarch64_feature_v8_5): New.
(ARMV8_5, V8_5_INSN): New.
This patch, along with previous patches in the series, supports
putting the ELF file header and program headers in a PT_LOAD without
sections.
Logic governing whether headers a loaded has changed a little: The
primary reason to include headers is now the presence of
SIZEOF_HEADERS in a linker script. However, to support scripts that
may have reserved space for headers by hand, we continue to add
headers whenever the first section address is past the end of headers
modulo page size.
include/
* bfdlink.h (struct bfd_link_info): Add load_phdrs field.
bfd/
* elf-nacl.c (nacl_modify_segment_map): Cope with header PT_LOAD
lacking sections.
* elf.c (_bfd_elf_map_sections_to_segments): Assume file and
program headers are required when info->load_phdrs. Reorganize
code handling program headers. Generate a mapping without
sections just for file and program headers when -z separate-code
would indicate they should be on a different page to the first
section.
ld/
* ldexp.c (fold_name <SIZEOF_HEADERS>): Set link_info.load_phdrs.
* testsuite/ld-elf/loadaddr1.d: Pass -z noseparate-code.
* testsuite/ld-elf/loadaddr2.d: Likewise.
* testsuite/ld-i386/vxworks2.sd: Adjust expected output.
* testsuite/ld-powerpc/vxworks2.sd: Likewise.
* testsuite/ld-elf/overlay.d: Remove spu xfail.
* testsuite/ld-spu/ovl.lnk: Don't use SIZEOF_HEADERS.
* testsuite/ld-tic6x/dsbt-be.ld: Likewise.
* testsuite/ld-tic6x/dsbt-inrange.ld: Likewise.
* testsuite/ld-tic6x/dsbt-overflow.ld: Likewise.
* testsuite/ld-tic6x/dsbt.ld: Likewise.
This patch is part of the patch series to add support for ARMv8.5-A
extensions.
(https://developer.arm.com/products/architecture/cpu-architecture/a-profile/exploration-tools)
This patch adds the Execution and Data Prediction Restriction
instructions (that is, cfprctx, dvprxtc, cpprctx). These are all
aliases to MCR and are disassembled as such.
This instruction is retrospectively made optional for all versions of
the architecture from ARMv8.0 to ARMv8.4 and is mandatory from
ARMv8.5. Hence adding a new +predres for older versions of the
architecture.
*** include/ChangeLog ***
2018-10-05 Sudakshina Das <sudi.das@arm.com>
* opcode/arm.h (ARM_EXT2_PREDRES): New.
(ARM_ARCH_V8_5A): Add ARM_EXT2_PREDRES by default.
*** gas/ChangeLog ***
2018-10-05 Sudakshina Das <sudi.das@arm.com>
* config/tc-arm.c (arm_ext_predres): New.
(insns): Add new cfprctx, dvprctx and cpprctx instructions.
(arm_extensions): Add "predres".
* doc/c-arm.texi: Document the above.
* testsuite/gas/arm/predres-bad.d: New test.
* testsuite/gas/arm/predres-bad.l: New test.
* testsuite/gas/arm/predres.s: New test.
* testsuite/gas/arm/predres1.d: New test.
* testsuite/gas/arm/predres2.d: New test.
This patch is part of the patch series to add support for ARMv8.5-A
extensions.
(https://developer.arm.com/products/architecture/cpu-architecture/a-profile/exploration-tools)
This patch adds the instruction SB. This instruction is
retrospectively made optional for all versions of the architecture
from ARMv8.0 to ARMv8.4 and is mandatory from ARMv8.5. Hence adding a
new "+sb" for older archtectures.
*** include/ChangeLog ***
2018-10-05 Sudakshina Das <sudi.das@arm.com>
* opcode/arm.h (ARM_EXT2_SB): New.
(ARM_ARCH_V8_5A): Add ARM_EXT2_SB by default.
*** opcodes/ChangeLog ***
2018-10-05 Sudakshina Das <sudi.das@arm.com>
* arm-dis.c (arm_opcodes): Add sb.
(thumb32_opcodes): Likewise.
*** gas/ChangeLog ***
2018-10-05 Sudakshina Das <sudi.das@arm.com>
* config/tc-arm.c (arm_ext_sb): New.
(insns): Add new sb instruction.
(arm_extensions): Add "sb".
* doc/c-arm.texi: Document the above.
* testsuite/gas/arm/sb-bad.d: New test.
* testsuite/gas/arm/sb-bad.l: New test.
* testsuite/gas/arm/sb-thumb1.d: New test.
* testsuite/gas/arm/sb-thumb2.d: New test.
* testsuite/gas/arm/sb.s: New test.
* testsuite/gas/arm/sb1.d: New test.
* testsuite/gas/arm/sb2.d: New test.
This patch is part of the patch series to add support for ARMv8.5-A
extensions.
(https://developer.arm.com/products/architecture/cpu-architecture/a-profile/exploration-tools)
This is the first of the patch series and adds -march=armv8.5-a and
other internal feature marcos needed for it.
*** gas/ChangeLog ***
2018-10-05 Sudakshina Das <sudi.das@arm.com>
* config/tc-arm.c (arm_archs): New entry for armv8.5-a.
(cpu_arch_ver): Likewise.
* doc/c-arm.texi: Add documentation for the same.
* testsuite/gas/arm/attr-march-armv8_5-a.d: New.
*** include/ChnageLog ***
2018-10-05 Sudakshina Das <sudi.das@arm.com>
* opcode/arm.h (ARM_EXT2_V8_5A): New.
(ARM_AEXT2_V8_5A, ARM_ARCH_V8_5A): New.
This patch adds the new instruction and relocation as per proposal:
https://openrisc.io/proposals/ladrp
This is to be added to the spec in an upcoming revision. The new instruction
l.adrp loads the page offset of the current instruction offset by
a 21-bit immediate shifted left 13-bits. This is meant to be used with
a 13-bit lower bit page offset. This allows us to free up the got
register r16.
l.adrp r3, foo
l.ori r4, r3, po(foo)
l.lbz r5, po(foo)(r3)
l.sb po(foo)(r3), r6
The relocations we add are:
- BFD_RELOC_OR1K_PLTA26 For PLT jump relocation with PLT entry
asm: plta() implemented using l.ardp, meaning
no need for r16 (the GOT reg)
- BFD_RELOC_OR1K_GOT_PG21 Upper 21-bit Page offset got address
asm: got()
- BFD_RELOC_OR1K_TLS_GD_PG21 Upper 21-bit Page offset with TLS General
asm: tlsgd() Dynamic calculation
- BFD_RELOC_OR1K_TLS_LDM_PG21 Upper 21-bit Page offset with TLS local
asm: tlsldm() dynamic calculation
- BFD_RELOC_OR1K_TLS_IE_PG21 Upper 21-bit Page offset with TLS Initial
asm: gottp() Executable calculation
- BFD_RELOC_OR1K_PCREL_PG21 Default relocation for disp21 (l.adrp
instructions)
- BFD_RELOC_OR1K_LO13 low 13-bit page offset relocation
asm: po() i.e. mem loads, addi etc
- BFD_RELOC_OR1K_SLO13 low 13-bit page offset relocation
asm: po() i.e. mem stores, with split immediate
- BFD_RELOC_OR1K_GOT_LO13, low 13-bit page offset with GOT calcs
asm: gotpo()
- BFD_RELOC_OR1K_TLS_GD_LO13 Lower 13-bit offset with TLS GD calcs
asm: tlsgdpo()
- BFD_RELOC_OR1K_TLS_LDM_LO13 Lower 13-bit offset with TLS LD calcs
asm: tlsldmpo()
- BFD_RELOC_OR1K_TLS_IE_LO13 Lower 13-bit offset with TLS IE calcs
asm: gottppo()
bfd/ChangeLog:
yyyy-mm-dd Richard Henderson <rth@twiddle.net>
* bfd-in2.h: Regenerated.
* elf32-or1k.c: (or1k_elf_howto_table): Fix formatting for
R_OR1K_PLT26, Add R_OR1K_PCREL_PG21, R_OR1K_GOT_PG21,
R_OR1K_TLS_GD_PG21, R_OR1K_TLS_LDM_PG21, R_OR1K_TLS_IE_PG21,
R_OR1K_LO13, R_OR1K_GOT_LO13, R_OR1K_TLS_GD_LO13, R_OR1K_TLS_LDM_LO13,
R_OR1K_TLS_IE_LO13, R_OR1K_SLO13, R_OR1K_PLTA26.
(or1k_reloc_map): Add BFD_RELOC_OR1K_PCREL_PG21,
BFD_RELOC_OR1K_GOT_PG21, BFD_RELOC_OR1K_TLS_GD_PG21,
BFD_RELOC_OR1K_TLS_LDM_PG21, BFD_RELOC_OR1K_TLS_IE_PG21,
BFD_RELOC_OR1K_LO13, BFD_RELOC_OR1K_GOT_LO13,
BFD_RELOC_OR1K_TLS_GD_LO13, BFD_RELOC_OR1K_TLS_GD_LO13,
BFD_RELOC_OR1K_TLS_LDM_LO13, BFD_RELOC_OR1K_TLS_IE_LO13,
BFD_RELOC_OR1K_SLO13, BFD_RELOC_OR1K_PLTA26.
(elf_or1k_link_hash_table): Add field saw_plta.
(or1k_final_link_relocate): Add value calculations for new relocations.
(or1k_elf_relocate_section): Add section relocations for new
relocations.
(or1k_write_plt_entry): New function.
(or1k_elf_finish_dynamic_sections): Add support for PLTA relocations
using new l.adrp instruction. Cleanup PLT relocation code generation.
* libbfd.h: Regenerated.
* reloc.c: Add BFD_RELOC_OR1K_PCREL_PG21, BFD_RELOC_OR1K_LO13,
BFD_RELOC_OR1K_SLO13, BFD_RELOC_OR1K_GOT_PG21, BFD_RELOC_OR1K_GOT_LO13,
BFD_RELOC_OR1K_PLTA26, BFD_RELOC_OR1K_TLS_GD_PG21,
BFD_RELOC_OR1K_TLS_GD_LO13, BFD_RELOC_OR1K_TLS_LDM_PG21,
BFD_RELOC_OR1K_TLS_LDM_LO13, BFD_RELOC_OR1K_TLS_IE_PG21,
BFD_RELOC_OR1K_TLS_IE_LO13.
cpu/ChangeLog:
yyyy-mm-dd Richard Henderson <rth@twiddle.net>
* or1k.opc (parse_disp26): Add support for plta() relocations.
(parse_disp21): New function.
(or1k_rclass): New enum.
(or1k_rtype): New enum.
(or1k_imm16_relocs): Define new PO and SPO relocation mappings.
(parse_reloc): Add new po(), gotpo() and gottppo() for LO13 relocations.
(parse_imm16): Add support for the new 21bit and 13bit relocations.
* or1korbis.cpu (f-disp26): Don't assume SI.
(f-disp21): New pc-relative 21-bit 13 shifted to right.
(insn-opcode): Add ADRP.
(l-adrp): New instruction.
gas/ChangeLog:
yyyy-mm-dd Richard Henderson <rth@twiddle.net>
* config/tc-or1k.c (or1k_apply_fix): Add BFD_RELOC_OR1K_TLS_GD_PG21,
BFD_RELOC_OR1K_TLS_GD_LO13, BFD_RELOC_OR1K_TLS_LDM_PG21,
BFD_RELOC_OR1K_TLS_LDM_LO13, BFD_RELOC_OR1K_TLS_IE_PG21,
BFD_RELOC_OR1K_TLS_IE_LO13.
* testsuite/gas/or1k/allinsn.s: Add test for l.adrp.
* testsuite/gas/or1k/allinsn.d: Add test results for new
instructions.
* testsuite/gas/or1k/reloc-1.s: Add tests to generate
R_OR1K_PLTA26, R_OR1K_GOT_PG21, R_OR1K_TLS_GD_PG21, R_OR1K_TLS_LDM_PG21,
R_OR1K_TLS_IE_PG21, R_OR1K_LO13, R_OR1K_GOT_LO13, R_OR1K_TLS_GD_LO13,
R_OR1K_TLD_LDM_LO13, R_OR1K_TLS_IE_LO13, R_OR1K_LO13, R_OR1K_SLO13
relocations.
* testsuite/gas/or1k/reloc-1.d: Add relocation results for
tests.
* testsuite/gas/or1k/reloc-2.s: Add negative tests for store to
gotpo().
* testsuite/gas/or1k/reloc-2.l: Add expected error test results.
ld/ChangeLog:
yyyy-mm-dd Richard Henderson <rth@twiddle.net>
* testsuite/ld-or1k/or1k.exp: Add test cases for plt generation.
* testsuite/ld-or1k/plt1.dd: New file.
* testsuite/ld-or1k/plt1.s: New file.
* testsuite/ld-or1k/plt1.x.dd: New file.
* testsuite/ld-or1k/plta1.dd: New file.
* testsuite/ld-or1k/plta1.s: New file.
* testsuite/ld-or1k/pltlib.s: New file.
include/ChangeLog:
yyyy-mm-dd Richard Henderson <rth@twiddle.net>
* elf/or1k.h (elf_or1k_reloc_type): Add R_OR1K_PCREL_PG21,
R_OR1K_GOT_PG21, R_OR1K_TLS_GD_PG21, R_OR1K_TLS_LDM_PG21,
R_OR1K_TLS_IE_PG21, R_OR1K_LO13, R_OR1K_GOT_LO13,
R_OR1K_TLS_GD_LO13, R_OR1K_TLS_LDM_LO13, R_OR1K_TLS_IE_LO13,
R_OR1K_SLO13, R_OR1K_PLTA26.
opcodes/ChangeLog:
yyyy-mm-dd Richard Henderson <rth@twiddle.net>
* or1k-asm.c: Regenerated.
* or1k-desc.c: Regenerated.
* or1k-desc.h: Regenerated.
* or1k-dis.c: Regenerated.
* or1k-ibld.c: Regenerated.
* or1k-opc.c: Regenerated.
* or1k-opc.h: Regenerated.
* or1k-opinst.c: Regenerated.
This patch adds the following target relocations:
- BFD_RELOC_HI16_S High 16-bit relocation, for used with signed
asm: ha() lower.
- BFD_RELOC_HI16_S_GOTOFF High 16-bit GOT offset relocation for local
asm: gotoffha() symbols, for use with signed lower.
- BFD_RELOC_OR1K_TLS_IE_AHI16 High 16-bit TLS relocation with initial
asm: gottpoffha() executable calculation, for use with signed
lower.
- BFD_RELOC_OR1K_TLS_LE_AHI16 High 16-bit TLS relocation for local executable
asm: tpoffha() variables, for use with signed lower.
- BFD_RELOC_OR1K_SLO16 Split lower 16-bit relocation, used with
asm: lo() OpenRISC store instructions.
- BFD_RELOC_OR1K_GOTOFF_SLO16 Split lower 16-bit GOT offset relocation for
asm: gotofflo() local symbols, used with OpenRISC store
instructions.
- BFD_RELOC_OR1K_TLS_LE_SLO16 Split lower 16-bit relocation for TLS local
asm: tpofflo() executable variables, used with OpenRISC store
instructions.
bfd/ChangeLog:
yyyy-mm-dd Richard Henderson <rth@twiddle.net>
Stafford Horne <shorne@gmail.com>
* bfd-in2.h: Regenerated.
* elf32-or1k.c (N_ONES): New macro.
(or1k_elf_howto_table): Fix R_OR1K_PLT26 to complain on overflow.
Add definitions for R_OR1K_TLS_TPOFF, R_OR1K_TLS_DTPOFF,
R_OR1K_TLS_DTPMOD, R_OR1K_AHI16, R_OR1K_GOTOFF_AHI16,
R_OR1K_TLS_IE_AHI16, R_OR1K_TLS_LE_AHI16, R_OR1K_SLO16,
R_OR1K_GOTOFF_SLO16, R_OR1K_TLS_LE_SLO16.
(or1k_reloc_map): Add entries for BFD_RELOC_HI16_S,
BFD_RELOC_LO16_GOTOFF, BFD_RELOC_HI16_GOTOFF, BFD_RELOC_HI16_S_GOTOFF,
BFD_RELOC_OR1K_TLS_IE_AHI16, BFD_RELOC_OR1K_TLS_LE_AHI16,
BFD_RELOC_OR1K_SLO16, BFD_RELOC_OR1K_GOTOFF_SLO16,
BFD_RELOC_OR1K_TLS_LE_SLO16.
(or1k_reloc_type_lookup): Change search loop to start ad index 0 and
also check results before returning.
(or1k_reloc_name_lookup): Simplify loop to use R_OR1K_max as index
limit.
(or1k_final_link_relocate): New function.
(or1k_elf_relocate_section): Add support for new AHI and SLO
relocations. Use or1k_final_link_relocate instead of generic
_bfd_final_link_relocate.
(or1k_elf_check_relocs): Add support for new AHI and SLO relocations.
* reloc.c: Add new enums for BFD_RELOC_OR1K_SLO16,
BFD_RELOC_OR1K_GOTOFF_SLO16, BFD_RELOC_OR1K_TLS_IE_AHI16,
BFD_RELOC_OR1K_TLS_IE_AHI16, BFD_RELOC_OR1K_TLS_LE_AHI16,
BFD_RELOC_OR1K_TLS_LE_SLO16. Remove unused BFD_RELOC_OR1K_GOTOFF_HI16
and BFD_RELOC_OR1K_GOTOFF_LO16.
* libbfd.h: Regenerated.
cpu/ChangeLog:
yyyy-mm-dd Richard Henderson <rth@twiddle.net>
* or1k.opc: Add RTYPE_ enum.
(INVALID_STORE_RELOC): New string.
(or1k_imm16_relocs): New array array.
(parse_reloc): New static function that just does the parsing.
(parse_imm16): New static function for generic parsing.
(parse_simm16): Change to just call parse_imm16.
(parse_simm16_split): New function.
(parse_uimm16): Change to call parse_imm16.
(parse_uimm16_split): New function.
* or1korbis.cpu (simm16-split): Change to use new simm16_split.
(uimm16-split): Change to use new uimm16_split.
gas/ChangeLog:
yyyy-mm-dd Richard Henderson <rth@twiddle.net>
* testsuite/gas/or1k/allinsn.d (l_ha): Add result for ha() relocation.
* testsuite/gas/or1k/allinsn.s (l_ha): Add test for ha() relocations.
* testsuite/gas/or1k/allinsn.exp: Renamed to or1k.exp.
* testsuite/gas/or1k/or1k.exp: Add reloc-2 list test.
* testsuite/gas/or1k/reloc-1.d: New file.
* testsuite/gas/or1k/reloc-1.s: New file.
* testsuite/gas/or1k/reloc-2.l: New file.
* testsuite/gas/or1k/reloc-2.s: New file.
include/ChangeLog:
yyyy-mm-dd Richard Henderson <rth@twiddle.net>
* elf/or1k.h (elf_or1k_reloc_type): Add R_OR1K_AHI16,
R_OR1K_GOTOFF_AHI16, R_OR1K_TLS_IE_AHI16, R_OR1K_TLS_LE_AHI16,
R_OR1K_SLO16, R_OR1K_GOTOFF_SLO16, R_OR1K_TLS_LE_SLO16.
ld/ChangeLog:
yyyy-mm-dd Richard Henderson <rth@twiddle.net>
* testsuite/ld-or1k/offsets1.d: New file.
* testsuite/ld-or1k/offsets1.s: New file.
* testsuite/ld-or1k/or1k.exp: New file.
opcodes/ChangeLog:
yyyy-mm-dd Richard Henderson <rth@twiddle.net>
* or1k-asm.c: Regenerate.
This patch adds the verification rules for move prefix constraints.
The Arm SVE instruction MOVPRFX introduces[1] constraints on the instruction at
PC+4. Particularly the following constraints are handled by this patch
* MOVPRFX must be followed by an instruction.
* MOVPRFX can only be followed by non-layout altering directives.
* MOVPRFX destination register MUST be used as the destination register in the
instruction at PC+4, and is not allowed to be used in any other position other than
destructive input. This includes registers that architecturally overlap. e.g. x1
should be treated as z1.
* MOVPRFX must be followed by a restricted set of SVE instructions.
* The size of the destination register of MOVPRFX must be equal to that of
the operation at PC+4.
* The predicate register and operation of MOVPRFX must match that of the instruction
at PC+4
* The predicated instruction at PC+4 must use the merging predicate.
* Architectural aliases and pseudo-instructions need to be supported as well.
* MOVPRFX cannot be the last instruction in a sequence
Any failure to adhere to any of these constrains will emit an assembly warning
and a disassembly note.
[1] https://developer.arm.com/docs/ddi0584/latest/arm-architecture-reference-manual-supplement-the-scalable-vector-extension-sve-for-armv8-a
include/
* opcode/aarch64.h (aarch64_inst): Remove.
(enum err_type): Add ERR_VFI.
(aarch64_is_destructive_by_operands): New.
(init_insn_sequence): New.
(aarch64_decode_insn): Remove param name.
opcodes/
* aarch64-opc.c (init_insn_block): New.
(verify_constraints, aarch64_is_destructive_by_operands): New.
* aarch64-opc.h (verify_constraints): New.
gas/
* config/tc-aarch64.c (output_operand_error_report): Order warnings.
The current verifiers only take an instruction description and encoded value as
arguments. This was enough when the verifiers only needed to do simple checking
but it's insufficient for the purposes of validating instruction sequences.
This patch adds the required arguments and also a flag to allow a verifier to
distinguish between whether it's being run during encoding or decoding. It also
allows for errors and warnings to be returned by a verifier instead of a simple
pass/fail.
include/
* opcode/aarch64.h (struct aarch64_opcode): Expand verifiers to take
more arguments.
opcodes/
* aarch64-dis.c (aarch64_opcode_decode): Update verifier call.
* aarch64-opc.c (verify_ldpsw): Update arguments.
Previously the ERR_ values were defined as different constants, to make this a
bit more type safe and so they can be more easily re-used I'm changing them into
an actual enum and updating any usages.
include/
* opcode/aarch64.h (enum err_type): New.
(aarch64_decode_insn): Use it.
opcodes/
* aarch64-dis.c (ERR_OK, ERR_UND, ERR_UNP, ERR_NYI): Remove.
(aarch64_decode_insn, print_insn_aarch64_word): Use err_type.
This patch introduces aarch64_instr_sequence which is a structure similar to IT
blocks on Arm in order to track instructions that introduce a constraint or
dependency on instruction 1..N positions away from the instruction that opened
the block.
The struct is also wired through to the locations that require it.
gas/
* config/tc-aarch64.c (now_instr_sequence):
(*insn_sequence, now_instr_sequence): New.
(output_operand_error_record, do_encode): Add insn_sequence.
(md_assemble): Update insn_sequence.
(try_to_encode_as_unscaled_ldst, fix_mov_imm_insn, fix_insn):
Pass insn_sequence.
* config/tc-aarch64.h (struct aarch64_segment_info_type):
Add insn_sequence.
include/
* opcode/aarch64.h (struct aarch64_instr_sequence): New.
(aarch64_opcode_encode): Use it.
opcodes/
* aarch64-asm.c (aarch64_opcode_encode): Add insn_sequence.
* aarch64-dis.c (insn_sequence): New.
This patch series is to allow certain instructions such as the SVE MOVPRFX
instruction to apply a constraint/dependency on the instruction at PC+4.
This patch starts this off by marking which instructions impose the constraint
and which instructions must adhere to the constraint. This is done in a
generic way by extending the verifiers.
* The constraint F_SCAN indicates that an instruction opens a sequence and imposes
a constraint on an instructions following it. The length of the sequence depends
on the instruction itself and it handled in the verifier code.
* The C_SCAN_MOVPRFX flag is used to indicate which constrain the instruction is
checked against. An instruction with both F_SCAN and C_SCAN_MOVPRFX starts a
block for the C_SCAN_MOVPRFX instruction, and one with only C_SCAN_MOVPRFX must
adhere to a previous block constraint is applicable.
The SVE instructions in this list have been marked according to the SVE
specification[1].
[1] https://developer.arm.com/docs/ddi0584/latest/arm-architecture-reference-manual-supplement-the-scalable-vector-extension-sve-for-armv8-a
include/
* opcode/aarch64.h (struct aarch64_opcode): Add constraints,
extend flags field size.
(F_SCAN, C_SCAN_MOVPRFX, C_MAX_ELEM): New.
opcodes/
* aarch64-tbl.h (CORE_INSN, __FP_INSN, SIMD_INSN, CRYP_INSN, _CRC_INSN,
_LSE_INSN, _LOR_INSN, RDMA_INSN, FF16_INSN, SF16_INSN, V8_2_INSN,
_SVE_INSN, V8_3_INSN, CNUM_INSN, RCPC_INSN, SHA2_INSN, AES_INSN,
V8_4_INSN, SHA3_INSN, SM4_INSN, FP16_V8_2_INSN, DOT_INSN): Initialize
constraints.
(_SVE_INSNC): New.
(struct aarch64_opcode): (fjcvtzs, ldpsw, ldpsw, esb, psb): Initialize
constraints.
(movprfx): Change _SVE_INSN into _SVE_INSNC, add C_SCAN_MOVPRFX and
F_SCAN flags.
(msb, mul, neg, not, orr, rbit, revb, revh, revw, sabd, scvtf,
sdiv, sdivr, sdot, smax, smin, smulh, splice, sqadd, sqdecd, sqdech,
sqdecp, sqdecw, sqincd, sqinch, sqincp, sqincw, sqsub, sub, subr, sxtb,
sxth, sxtw, uabd, ucvtf, udiv, udivr, udot, umax, umin, umulh, uqadd,
uqdecd, uqdech, uqdecp, uqdecw, uqincd, uqinch, uqincp, uqincw, uqsub,
uxtb, uxth, uxtw, bic, eon, orn, mov, fmov): Change _SVE_INSN into _SVE_INSNC and add
C_SCAN_MOVPRFX and C_MAX_ELEM constraints.
The RISC-V memory model has been ratified, and it includes an additional
fence: "fence.tso". This pseudo instruction extends one of the
previously reserved full fence patterns to be less restrictive, and
therefor will execute correctly on all existing microarchitectures.
Thus there is no reason to allow this instruction to be disabled (or
unconverted to a full fence), so it's just unconditionally allowed.
I've added a test case for GAS to check that "fence.tso" correctly
assembles on rv32i-based targets. I checked to see that "fence.tso"
appears in "gas.log", but that's the only testing I've done.
gas/ChangeLog
2018-10-02 Palmer Dabbelt <palmer@sifive.com>
* testsuite/gas/riscv/fence-tso.d: New file.
* testsuite/gas/riscv/fence-tso.s: Likewise.
include/ChangeLog
2018-10-02 Palmer Dabbelt <palmer@sifive.com>
* opcode/riscv-opc.h (MATCH_FENCE_TSO): New define.
(MASK_FENCE_TSO): Likewise.
opcodes/ChangeLog
2018-10-02 Palmer Dabbelt <palmer@sifive.com>
* riscv-opc.c (riscv_opcodes) <fence.tso>: New opcode.
Inserted offset in final section in the GOT entry of type DTSOFF soon to be
relocated by the dynamic loader.
bfd/
2018-09-06 Cupertino Miranda <cmiranda@synopsys.com>
* arc-got.h (relocate_fix_got_relocs_for_got_info): Changed. Take TLS
section alignment in consideration for this relocation.
* elf32-arc.c (FINAL_SECTSTART): Added this formula macro.
(ARC_TLS_DTPOFF) Updated reloc to use new created macro instead.
We shouldn't include zero size sections at start of PT_NOTE segment,
similar to PT_DYNAMIC segment.
PR binutils/23694
* include/elf/internal.h (ELF_SECTION_IN_SEGMENT_1): Don't
include zero size sections at start of PT_NOTE segment.
We have not only removed all unsupported and obsolete code, but also supported lost of new features,
including better link-time relaxations and TLS implementations. Besides, the files generated by the
newly assembler and linker usually get higher performance and more optimized code size.
ld * emultempl/nds32elf.em (hyper_relax): New variable.
(nds32_elf_create_output_section_statements):
the parameters of bfd_elf32_nds32_set_target_option
(PARSE_AND_LIST_PROLOGUE, PARSE_AND_LIST_OPTIONS,
PARSE_AND_LIST_ARGS_CASES): Add new option --mhyper-relax.
* emultempl/nds32elf.em (nds32_elf_after_open): Updated.
* emultempl/nds32elf.em (tls_desc_trampoline): New variable.
* (nds32_elf_create_output_section_statements): Updated.
* (nds32_elf_after_parse): Disable relaxations when PIC is enable.
* (PARSE_AND_LIST_PROLOGUE, PARSE_AND_LIST_OPTIONS,
PARSE_AND_LIST_ARGS_CASES): Add new option --m[no-]tlsdesc-trampoline.
include * elf/nds32.h: Remove the unused target features.
* dis-asm.h (disassemble_init_nds32): Declared.
* elf/nds32.h (E_NDS32_NULL): Removed.
(E_NDS32_HAS_DSP_INST, E_NDS32_HAS_ZOL): New.
* opcode/nds32.h: Ident.
(N32_SUB6, INSN_LW): New macros.
(enum n32_opcodes): Updated.
* elf/nds32.h: Doc fixes.
* elf/nds32.h: Add R_NDS32_LSI.
* elf/nds32.h: Add new relocations for TLS.
gas * config/tc-nds32.c: Remove the unused target features.
(nds32_relax_relocs, md_pseudo_table, nds32_elf_record_fixup_exp,
nds32_set_elf_flags_by_insn, nds32_insert_relax_entry,
nds32_apply_fix): Likewise.
(nds32_no_ex9_begin): Removed.
* config/tc-nds32.c (add_mapping_symbol_for_align,
make_mapping_symbol, add_mapping_symbol): New functions.
* config/tc-nds32.h (enum mstate): New.
(nds32_segment_info_type): Likewise.
* configure.ac (--enable-dsp-ext, --enable-zol-ext): New options.
* config.in: Regenerated.
* configure: Regenerated.
* config/tc-nds32.c (nds32_dx_regs):
Set the value according to the configuration.
(nds32_perf_ext, nds32_perf_ext2, nds32_string_ext, nds32_audio_ext):
Likewise.
(nds32_dsp_ext): New variable. Set the value according to the
configuration.
(nds32_zol_ext): Likewise.
(asm_desc, nds32_pseudo_opcode_table): Make them static.
(nds32_set_elf_flags_by_insn): Updated.
(nds32_check_insn_available): Updated.
(nds32_str_tolower): New function.
* config/tc-nds32.c (relax_table): Updated.
(md_begin): Updated.
(md_assemble): Use XNEW macro to allocate space for `insn.info',
and then remember to free it.
(md_section_align): Cast (-1) to ValueT.
(nds32_get_align): Cast (~0U) to addressT.
(nds32_relax_branch_instructions): Updated.
(md_convert_frag): Add new local variable `final_r_type'.
(invalid_prev_frag): Add new bfd_boolean parameter `relax'.
All callers changed.
* config/tc-nds32.c (struct nds32_relocs_pattern): Add `insn' field.
(struct nds32_hint_map): Add `option_list' field.
(struct suffix_name, suffix_table): Remove the unused `pic' field.
(do_pseudo_b, do_pseudo_bal): Remove the suffix checking.
(do_pseudo_la_internal, do_pseudo_pushpopm): Indent.
(relax_hint_bias, relax_hint_id_current): New static variables.
(reset_bias, relax_hint_begin): New variables.
(nds_itoa): New function.
(CLEAN_REG, GET_OPCODE): New macros.
(struct relax_hint_id): New.
(nds32_relax_hint): For .relax_hint directive, we can use `begin'
and `end' to mark the relax pattern without giving exactly id number.
(nds32_elf_append_relax_relocs): Handle the case that the .relax_hint
directives are attached to pseudo instruction.
(nds32_elf_save_pseudo_pattern): Change the second parameter from
instruction's opcode to byte code.
(nds32_elf_build_relax_relation): Add new bfd_boolean parameter
`pseudo_hint'.
(nds32_lookup_pseudo_opcode): Fix the overflow issue.
(enum nds32_insn_type): Add N32_RELAX_ALU1 and N32_RELAX_16BIT.
(nds32_elf_record_fixup_exp, relax_ls_table, hint_map,
nds32_find_reloc_table, nds32_match_hint_insn, nds32_parse_name):
Updated.
* config/tc-nds32.h (MAX_RELAX_NUM): Extend it to 6.
(enum nds32_relax_hint_type): Merge NDS32_RELAX_HINT_LA and
NDS32_RELAX_HINT_LS into NDS32_RELAX_HINT_LALS. Add
NDS32_RELAX_HINT_LA_PLT, NDS32_RELAX_HINT_LA_GOT and
NDS32_RELAX_HINT_LA_GOTOFF.
* config/tc-nds32.h (relax_ls_table): Add floating load/store
to gp relax pattern.
(hint_map, nds32_find_reloc_table): Likewise.
* configure.ac: Define NDS32_LINUX_TOOLCHAIN.
* configure: Regenerated.
* config.in: Regenerated.
* config/tc-nds32.h (enum nds32_ramp): Updated.
(enum nds32_relax_hint_type): Likewise.
* config/tc-nds32.c: Include "errno.h" and "limits.h".
(relax_ls_table): Add TLS relax patterns.
(nds32_elf_append_relax_relocs): Attach BFD_RELOC_NDS32_GROUP on
each instructions of TLS patterns.
(nds32_elf_record_fixup_exp): Updated.
(nds32_apply_fix): Likewise.
(suffix_table): Add TLSDESC suffix.
binutils* testsuite/binutils-all/objcopy.exp: Set the unsupported reloc number
from 215 to 255 for NDS32.
bfd * elf32-nds32.c (nds32_elf_relax_loadstore):
Remove the unused target features.
(bfd_elf32_nds32_set_target_option): Remove the unused parameters.
(nds32_elf_relax_piclo12, nds32_elf_relax_letlslo12,
nds32_elf_relax_letlsadd, nds32_elf_relax_letlsls,
nds32_elf_relax_pltgot_suff, nds32_elf_relax_got_suff
nds32_elf_relax_gotoff_suff, calculate_plt_memory_address,
calculate_plt_offset, calculate_got_memory_address,
nds32_elf_check_dup_relocs): Removed.
All callers changed.
* elf32-nds32.h: Remove the unused macros and defines.
(elf_nds32_link_hash_table): Remove the unused variable.
(bfd_elf32_nds32_set_target_option): Update prototype.
(nds32_elf_ex9_init): Removed.
* elf32-nds32.c (nds32_convert_32_to_16): Updated.
* elf32-nds32.c (HOWTO2, HOWTO3): Define new HOWTO macros
to initialize array nds32_elf_howto_table in any order
without lots of EMPTY_HOWTO.
(nds32_reloc_map): Updated.
* reloc.c: Add BFD_RELOC_NDS32_LSI.
* bfd-in2.h: Regenerated.
* bfd/libbfd.h: Regenerated.
* elf32-nds32.c (nds32_elf_relax_howto_table): Add R_NDS32_LSI.
(nds32_reloc_map): Likewise.
(nds32_elf_relax_flsi): New function.
(nds32_elf_relax_section): Support floating load/store relaxation.
* elf32-nds32.c (NDS32_GUARD_SEC_P, elf32_nds32_local_gp_offset):
New macro.
(struct elf_nds32_link_hash_entry): New `offset_to_gp' field.
(struct elf_nds32_obj_tdata): New `offset_to_gp' and `hdr_size' fields.
(elf32_nds32_allocate_local_sym_info, nds32_elf_relax_guard,
nds32_elf_is_target_special_symbol, nds32_elf_maybe_function_sym):
New functions.
(nds32_info_to_howto_rel): Add BFD_ASSERT.
(bfd_elf32_bfd_reloc_type_table_lookup, nds32_elf_link_hash_newfunc,
nds32_elf_link_hash_table_create, nds32_elf_relocate_section,
nds32_elf_relax_loadstore, nds32_elf_relax_lo12, nds32_relax_adjust_label,
bfd_elf32_nds32_set_target_option, nds32_fag_mark_relax): Updated.
(nds32_elf_final_sda_base): Improve it to find the better gp value.
(insert_nds32_elf_blank): Must consider `len' when inserting blanks.
* elf32-nds32.h (bfd_elf32_nds32_set_target_option): Update prototype.
(struct elf_nds32_link_hash_table): Add new variable `hyper_relax'.
* elf32-nds32.c (elf32_nds32_allocate_dynrelocs): New function.
(create_got_section): Likewise.
(allocate_dynrelocs, nds32_elf_size_dynamic_sections,
nds32_elf_relocate_section, nds32_elf_finish_dynamic_symbol): Updated.
(nds32_elf_check_relocs): Fix the issue that the shared library may
has TEXTREL entry in the dynamic section.
(nds32_elf_create_dynamic_sections): Enable to call readonly_dynrelocs
since the TEXTREL issue is fixed in the nds32_elf_check_relocs.
(nds32_elf_finish_dynamic_sections): Update and add DT_RELASZ
dynamic entry.
(calculate_offset): Remove the unused parameter `pic_ext_target' and
related codes.
All callers changed.
(elf_backend_dtrel_excludes_plt): Disable it temporarily since it
will cause some errors for our test cases.
* elf32-nds32.c (nds32_elf_merge_private_bfd_data): Allow to link the
generic object.
* reloc.c: Add TLS relocations.
* libbfd.h: Regenerated.
* bfd-in2.h: Regenerated.
* elf32-nds32.h (struct section_id_list_t): New.
(elf32_nds32_lookup_section_id, elf32_nds32_check_relax_group,
elf32_nds32_unify_relax_group, nds32_elf_unify_tls_model):
New prototypes.
(elf32_nds32_compute_jump_table_size, elf32_nds32_local_tlsdesc_gotent):
New macro.
(nds32_insertion_sort, bfd_elf32_nds32_set_target_option,
elf_nds32_link_hash_table): Updated.
* elf32-nds32.c (enum elf_nds32_tls_type): New.
(struct elf32_nds32_relax_group_t, struct relax_group_list_t): New.
(elf32_nds32_add_dynreloc, patch_tls_desc_to_ie, get_tls_type,
fls, ones32, list_insert, list_insert_sibling, dump_chain,
elf32_nds32_check_relax_group, elf32_nds32_lookup_section_id,
elf32_nds32_unify_relax_group, nds32_elf_unify_tls_model): New functions.
(elf_nds32_obj_tdata): Add new fields.
(elf32_nds32_relax_group_ptr, nds32_elf_local_tlsdesc_gotent): New macros.
(nds32_elf_howto_table): Add TLS relocations.
(nds32_reloc_map): Likewise.
(nds32_elf_copy_indirect_symbol, nds32_elf_size_dynamic_sections,
nds32_elf_finish_dynamic_symbol, elf32_nds32_allocate_local_sym_info,
nds32_elf_relocate_section, bfd_elf32_nds32_set_target_option,
nds32_elf_check_relocs, allocate_dynrelocs): Updated.
(nds32_elf_relax_section): Call nds32_elf_unify_tls_model.
(dtpoff_base): Rename it to `gottpof' and then update it.
opcodes * nds32-asm.c (operand_fields): Remove the unused fields.
(nds32_opcodes): Remove the unused instructions.
* nds32-dis.c (nds32_ex9_info): Removed.
(nds32_parse_opcode): Updated.
(print_insn_nds32): Likewise.
* nds32-asm.c (config.h, stdlib.h, string.h): New includes.
(LEX_SET_FIELD, LEX_GET_FIELD): Update defines.
(nds32_asm_init, build_operand_hash_table, build_keyword_hash_table,
build_opcode_hash_table): New functions.
(nds32_keyword_table, nds32_keyword_count_table, nds32_field_table,
nds32_opcode_table): New.
(hw_ktabs): Declare it to a pointer rather than an array.
(build_hash_table): Removed.
* nds32-asm.h (enum): Add SYN_INPUT, SYN_OUTPUT, SYN_LOPT,
SYN_ROPT and upadte HW_GPR and HW_INT.
* nds32-dis.c (keywords): Remove const.
(match_field): New function.
(nds32_parse_opcode): Updated.
* disassemble.c (disassemble_init_for_target):
Add disassemble_init_nds32.
* nds32-dis.c (eum map_type): New.
(nds32_private_data): Likewise.
(get_mapping_symbol_type, is_mapping_symbol, nds32_symbol_is_valid,
nds32_add_opcode_hash_table, disassemble_init_nds32): New functions.
(print_insn_nds32): Updated.
* nds32-asm.c (parse_aext_reg): Add new parameter.
(parse_re, parse_re2, parse_aext_reg): Only reduced registers
are allowed to use.
All callers changed.
* nds32-asm.c (keyword_usr, keyword_sr): Updated.
(operand_fields): Add new fields.
(nds32_opcodes): Add new instructions.
(keyword_aridxi_mx): New keyword.
* nds32-asm.h (enum): Add NASM_ATTR_DSP_ISAEXT, HW_AEXT_ARIDXI_MX
and NASM_ATTR_ZOL.
(ALU2_1, ALU2_2, ALU2_3): New macros.
* nds32-dis.c (nds32_filter_unknown_insn): Updated.
Currently, three tests FAIL on Solaris 11.4+ (amd64-pc-solaris2.11 and
sparcv9-sun-solaris2.11):
info auxv
[...]
2009 AT_SUN_HWCAP Machine-dependent CPU capability hints 0x3f5ff7
2023 ??? 0x0
0 AT_NULL End of vector 0x0
(gdb) WARNING: Unrecognized tag value: 2023 ??? 0x0
FAIL: gdb.base/auxv.exp: info auxv on live process
info auxv
4294969310 ??? 0x7fffbfffe410
9225589753816 ??? 0x7fffbfffe45c
[...]
WARNING: Unrecognized tag value: 4294969310 ??? 0x7fffbfffe410
WARNING: Unrecognized tag value: 9225589753816 ??? 0x7fffbfffe45c
WARNING: Unrecognized tag value: 140733193388037 ??? 0x6
[...]
2009 AT_SUN_HWCAP Machine-dependent CPU capability hints 0x3f5ff7
2023 ??? 0x0
0 AT_NULL End of vector 0x0
(gdb) WARNING: Unrecognized tag value: 2023 ??? 0x0
UNRESOLVED: gdb.base/auxv.exp: info auxv on native core dump
info auxv
[...]
2009 AT_SUN_HWCAP Machine-dependent CPU capability hints 0x3f5ff7
2023 ??? 0x0
0 AT_NULL End of vector 0x0
(gdb) WARNING: Unrecognized tag value: 2023 ??? 0x0
FAIL: gdb.base/auxv.exp: info auxv on gcore-created dump
The following patch fixes this by introducing the missing AT_SUN_*
values from Solaris 11.4+ <sys/auxv.h>. This lets the live and
gcore-created dump tests PASS.
I don't know yet what's the reason for those weird 'Unrecognized tag
value' warnings with native core dumps is; elfdump -n certainly doesn't
show them. However, native core dumps still need quite some work
(mostly in bfd) in this and other areas.
Tested on amd64-pc-solaris2.11.
gdb:
* auxv.c (default_print_auxv_entry): Reflect AT_SUN_CAP_HW1
renaming.
Handle AT_SUN_EMULATOR, AT_SUN_BRANDNAME, AT_SUN_BRAND_AUX1,
AT_SUN_BRAND_AUX2, AT_SUN_BRAND_AUX3, AT_SUN_CAP_HW2.
include:
* elf/common.h (AT_SUN_HWCAP): Rename to ...
(AT_SUN_CAP_HW1): ... this. Retain old name for backward
compatibility.
(AT_SUN_EMULATOR, AT_SUN_BRANDNAME, AT_SUN_BRAND_AUX1)
(AT_SUN_BRAND_AUX2, AT_SUN_BRAND_AUX3, AT_SUN_CAP_HW2): Define.
commit 3322c5d9a1 ("Remove unneeded explicit .o targets") broke the
build with clang, because -Wno-format-nonliteral was in fact needed.
This patch fixes the problem by introducing
DIAGNOSTIC_IGNORE_FORMAT_NONLITERAL and using it in printcmd.c. This
seems preferable to reverting the patch because now the warning
suppression is more targeted.
gdb/ChangeLog
2018-09-05 Simon Marchi <simon.marchi@ericsson.com>
* printcmd.c (printf_c_string): Use
DIAGNOSTIC_IGNORE_FORMAT_NONLITERAL.
(printf_wide_c_string, printf_pointer, ui_printf): Likewise.
include/ChangeLog
2018-09-05 Simon Marchi <simon.marchi@ericsson.com>
* diagnostics.h (DIAGNOSTIC_IGNORE_FORMAT_NONLITERAL): New macro.
2018-08-29 Kito Cheng <kito@andestech.com>
gas/
* config/tc-riscv.c (riscv_subset_supports): New argument:
xlen_required.
(riscv_multi_subset_supports): New function, able to check more
than one extension.
(riscv_ip): Use riscv_multi_subset_supports instead of
riscv_subset_supports.
(riscv_set_arch): Update call-site for riscv_subset_supports.
(riscv_after_parse_args): Likewise.
include/
*opcode/riscv.h (MAX_SUBSET_NUM): New.
(riscv_opcode): Add xlen_requirement field and change type of
subset.
opcodes/
* riscv-dis.c (riscv_disassemble_insn): Check XLEN by
riscv_opcode.xlen_requirement.
* riscv-opc.c (riscv_opcodes): Update for struct change.
Alan Modra
H.J. Lu
Nick Clifton
Andrew Burgess
Jim Wilson
Thomas Preud'homme
Sudakshina Das
Roman Bolshakov
John Baldwin
John Darrington
Stafford Horne
Richard Henderson
Tamar Christina
Palmer Dabbelt
Cupertino Miranda
Rainer Orth
Simon Marchi