For riscv64-linux target, first half of fix for
FAIL: gdb.base/gnu_vector.exp: call add_various_floatvecs
GCC gives vectors natural aligment based on total size, not element size,
bounded by the maximum supported type alignment.
gdb/
* riscv-tdep.c (BIGGEST_ALIGNMENT): New.
(riscv_type_alignment) <TYPE_CODE_ARRAY>: If TYPE_VECTOR, return min
of TYPE_LENGTH and BIGGEST_ALIGNMENT.
For riscv64-linux target, fixes
FAIL: gdb.base/gnu_vector.exp: call add_many_charvecs
Ensure that stack slots are always the same alignment as XLEN by rounding
up arg align to xlen.
gdb/
* riscv-tdep.c (riscv_call_arg_scalar_int): Use std::min when
setting len. New local align, set to max of arg align and xlen,
and pass to first riscv_assign_stack_location call.
The decoding of the CRC operation in alu instructions was using bits
from the instruction word directly, instead of srcA which would be
different if the swap bit was set.
Signed-off-by: Francois H. Theron <francois.theron@netronome.com>
Glibc commit:
commit a15529fda8d132621328c3fe32997a3d9c55aef4
Author: H.J. Lu <hjl.tools@gmail.com>
Date: Mon May 14 09:23:55 2018 -0700
i386: Replace PREINIT_FUNCTION@PLT with *%eax in call
Since we have loaded address of PREINIT_FUNCTION into %eax, we can
avoid extra branch to PLT slot.
changed __gmon_start__ relocations in crt1.o from
00000015 0000092b R_386_GOT32X 00000000 __gmon_start__
0000001e 00000904 R_386_PLT32 00000000 __gmon_start__
to
00000015 00000a2b R_386_GOT32X 00000000 __gmon_start__
As the result, .plt.sec section may be generated instead of .plt.got
section, depending on __gmon_start__ relocations.
* testsuite/ld-i386/plt-main-ibt.dd: Accept both .plt.got and
.plt.sec sections.
Add completer to various commands that accept skip numbers:
- skip enable
- skip disable
- skip delete
- info skip
These commands also accept ranges, the completer works for that but is
not very smart. It will suggest invalid ranges, for example when doing
"2-<TAB>" it will suggest "1", which would not result in a valid range.
Also, it will keep suggesting when doing "1-2-<TAB>", even though it's
an invalid syntax.
A future idea would be to make a re-usable and well-tested completer for
numbers and ranges. I think it could at least be re-used for breakpoint
and thread numbers (for example with the "enable breakpoints" command).
gdb/ChangeLog:
* skip.c (complete_skip_number): New function.
(_initialize_step_skip): Add completers to some skip commands.
gdb/testsuite/ChangeLog:
* gdb.base/skip.exp: Add standard_testfile. Add "skip delete"
completer tests.
This patch is part of the patch series to add support for ARMv8.5-A
Memory Tagging Extensions which is an optional extension to
ARMv8.5-A and is enabled using the +memtag command line option.
This patch adds all the data cache instructions that are part of this
extension:
- DC IGVAC, Xt
- DC IGSW, Xt
- DC CGSW, Xt
- DC CIGSW, Xt
- DC CGVAC, Xt
- DC CGVAP, Xt
- DC CGVADP, Xt
- DC CIGVAC, Xt
- DC GVA, Xt
- DC IGDVAC, Xt
- DC IGDSW, Xt
- DC CGDSW, Xt
- DC CIGDSW, Xt
- DC CGDVAC, Xt
- DC CGDVAP, Xt
- DC CGDVADP, Xt
- DC CIGDVAC, Xt
- DC GZVA, Xt
*** opcodes/ChangeLog ***
2018-11-12 Sudakshina Das <sudi.das@arm.com>
* aarch64-opc.c (aarch64_sys_regs_dc): New entries for
IGVAC, IGSW, CGSW, CIGSW, CGVAC, CGVAP, CGVADP, CIGVAC, GVA,
IGDVAC, IGDSW, CGDSW, CIGDSW, CGDVAC, CGDVAP, CGDVADP,
CIGDVAC and GZVA.
(aarch64_sys_ins_reg_supported_p): New check for above.
*** gas/ChangeLog ***
2018-11-12 Sudakshina Das <sudi.das@arm.com>
* testsuite/gas/aarch64/sysreg-4.s: Test IGVAC, IGSW,
CGSW, CIGSW, CGVAC, CGVAP, CGVADP, CIGVAC, GVA,
IGDVAC, IGDSW, CGDSW, CIGDSW, CGDVAC, CGDVAP, CGDVADP,
CIGDVAC and GZVA with DC.
* testsuite/gas/aarch64/sysreg-4.d: Likewise.
* testsuite/gas/aarch64/illegal-sysreg-4.l: Likewise.
This patch is part of the patch series to add support for ARMv8.5-A
Memory Tagging Extensions which is an optional extension to
ARMv8.5-A and is enabled using the +memtag command line option.
This patch adds all the system registers that are part of this
extension and are accessible via the MRS/MSR instructions:
- TCO
- TFSRE0_SL1
- TFSR_EL1
- TFSR_EL2
- TFSR_EL3
- TFSR_EL12
- RGSR_EL1
- GCR_EL1
TCO is also accessible with the MSR(immediate) instruction.
*** opcodes/ChangeLog ***
2018-11-12 Sudakshina Das <sudi.das@arm.com>
* aarch64-opc.c (aarch64_sys_regs): New entries for TCO,
TFSRE0_SL1, TFSR_EL1, TFSR_EL2, TFSR_EL3, TFSR_EL12,
RGSR_EL1 and GCR_EL1.
(aarch64_sys_reg_supported_p): New check for above.
(aarch64_pstatefields): New entry for TCO.
(aarch64_pstatefield_supported_p): New check for above.
*** gas/ChangeLog ***
2018-11-12 Sudakshina Das <sudi.das@arm.com>
* testsuite/gas/aarch64/sysreg-4.s: Test TCO, TFSRE0_SL1,
TFSR_EL1, TFSR_EL2, TFSR_EL3, TFSR_EL12, RGSR_EL1 and
GCR_EL1 MSR and MRS.
* testsuite/gas/aarch64/sysreg-4.d: Likewise.
* testsuite/gas/aarch64/illegal-sysreg-4.l: Likewise.
This patch is part of the patch series to add support for ARMv8.5-A
Memory Tagging Extensions which is an optional extension to
ARMv8.5-A and is enabled using the +memtag command line option.
This patch add support to the Bulk Allocation Tag instructions from
MTE. These are the following instructions added in this patch:
- LDGV <Xt>, [<Xn|SP>]!
- STGV <Xt>, [<Xn|SP>]!
This needed a new kind of operand for the new addressing [<Xn|SP>]!
since this has no offset and only takes a pre-indexed version.
Hence AARCH64_OPND_ADDR_SIMPLE_2 and ldtdgv_indexed are introduced.
(AARCH64_OPND_ADDR_SIMPLE fulfilled the no offset criteria but does
not allow writeback). We also needed new encoding and decoding
functions to be able to do the same.
where
<Xt> : Is the 64-bit destination GPR.
<Xn|SP> : Is the 64-bit first source GPR or Stack pointer.
*** include/ChangeLog ***
2018-11-12 Sudakshina Das <sudi.das@arm.com>
* opcode/aarch64.h (aarch64_opnd): Add AARCH64_OPND_ADDR_SIMPLE_2.
(aarch64_insn_class): Add ldstgv_indexed.
*** opcodes/ChangeLog ***
2018-11-12 Sudakshina Das <sudi.das@arm.com>
* aarch64-asm.c (aarch64_ins_addr_simple_2): New.
* aarch64-asm.h (ins_addr_simple_2): Declare the above.
* aarch64-dis.c (aarch64_ext_addr_simple_2): New.
* aarch64-dis.h (ext_addr_simple_2): Declare the above.
* aarch64-opc.c (operand_general_constraint_met_p): Add case for
AARCH64_OPND_ADDR_SIMPLE_2 and ldstgv_indexed.
(aarch64_print_operand): Add case for AARCH64_OPND_ADDR_SIMPLE_2.
* aarch64-tbl.h (aarch64_opcode_table): Add stgv and ldgv.
(AARCH64_OPERANDS): Define ADDR_SIMPLE_2.
* aarch64-asm-2.c: Regenerated.
* aarch64-dis-2.c: Regenerated.
* aarch64-opc-2.c: Regenerated.
*** gas/ChangeLog ***
2018-11-12 Sudakshina Das <sudi.das@arm.com>
* config/tc-aarch64.c (parse_operands): Add switch case for
AARCH64_OPND_ADDR_SIMPLE_2 and allow [base]! for it.
(warn_unpredictable_ldst): Exempt ldstgv_indexed for ldgv.
* testsuite/gas/aarch64/armv8_5-a-memtag.s: Add tests for ldgv and stgv.
* testsuite/gas/aarch64/armv8_5-a-memtag.d: Likewise.
* testsuite/gas/aarch64/illegal-memtag.s: Likewise.
* testsuite/gas/aarch64/illegal-memtag.l: Likewise.
This patch is part of the patch series to add support for ARMv8.5-A
Memory Tagging Extensions which is an optional extension to
ARMv8.5-A and is enabled using the +memtag command line option.
This patch add support to the Tag Getting instruction from Memory Tagging
Extension.
- LDG <Xt>, [<Xn|SP>, #<simm>]
where
<Xt> : Is the 64-bit destination GPR.
<Xn|SP> : Is the 64-bit first source GPR or Stack pointer.
<simm> : Is the optional signed immediate offset, a multiple of 16
in the range of -4096 and 4080, defaulting to 0.
*** opcodes/ChangeLog ***
2018-11-12 Sudakshina Das <sudi.das@arm.com>
* aarch64-tbl.h (QL_LDG): New.
(aarch64_opcode_table): Add ldg.
* aarch64-asm-2.c: Regenerated.
* aarch64-dis-2.c: Regenerated.
* aarch64-opc-2.c: Regenerated.
*** gas/ChangeLog ***
2018-11-12 Sudakshina Das <sudi.das@arm.com>
* testsuite/gas/aarch64/armv8_5-a-memtag.s: Add tests for ldg.
* testsuite/gas/aarch64/armv8_5-a-memtag.d: Likewise.
* testsuite/gas/aarch64/illegal-memtag.s: Likewise.
* testsuite/gas/aarch64/illegal-memtag.l: Likewise.
This patch is part of the patch series to add support for ARMv8.5-A
Memory Tagging Extensions which is an optional extension to
ARMv8.5-A and is enabled using the +memtag command line option.
This patch add support to the Tag setting instructions from
MTE which consists of the following instructions:
- STG [<Xn|SP>, #<simm>]
- STG [<Xn|SP>, #<simm>]!
- STG [<Xn|SP>], #<simm>
- STZG [<Xn|SP>, #<simm>]
- STZG [<Xn|SP>, #<simm>]!
- STZG [<Xn|SP>], #<simm>
- ST2G [<Xn|SP>, #<simm>]
- ST2G [<Xn|SP>, #<simm>]!
- ST2G [<Xn|SP>], #<simm>
- STZ2G [<Xn|SP>, #<simm>]
- STZ2G [<Xn|SP>, #<simm>]!
- STZ2G [<Xn|SP>], #<simm>
- STGP <Xt>, <Xt2>, [<Xn|SP>, #<imm>]
- STGP <Xt>, <Xt2>, [<Xn|SP>, #<imm>]!
- STGP <Xt>, <Xt2>, [<Xn|SP>], #<imm>
where
<Xn|SP> : Is the 64-bit GPR or Stack pointer.
<simm> : Is the optional signed immediate offset, a multiple of 16
in the range -4096 to 4080, defaulting to 0.
*** include/ChangeLog ***
2018-11-12 Sudakshina Das <sudi.das@arm.com>
* opcode/aarch64.h (aarch64_opnd): Add AARCH64_OPND_ADDR_SIMM11
and AARCH64_OPND_ADDR_SIMM13.
(aarch64_opnd_qualifier): Add new AARCH64_OPND_QLF_imm_tag.
*** opcodes/ChangeLog ***
2018-11-12 Sudakshina Das <sudi.das@arm.com>
* aarch64-opc.c (aarch64_opnd_qualifiers): Add new data
for AARCH64_OPND_QLF_imm_tag.
(operand_general_constraint_met_p): Add case for
AARCH64_OPND_ADDR_SIMM11 and AARCH64_OPND_ADDR_SIMM13.
(aarch64_print_operand): Likewise.
* aarch64-tbl.h (QL_LDST_AT, QL_STGP): New.
(aarch64_opcode_table): Add stg, stzg, st2g, stz2g and stgp
for both offset and pre/post indexed versions.
(AARCH64_OPERANDS): Define ADDR_SIMM11 and ADDR_SIMM13.
* aarch64-asm-2.c: Regenerated.
* aarch64-dis-2.c: Regenerated.
* aarch64-opc-2.c: Regenerated.
*** gas/ChangeLog ***
2018-11-12 Sudakshina Das <sudi.das@arm.com>
* config/tc-aarch64.c (parse_operands): Add switch case for
AARCH64_OPND_ADDR_SIMM11 and AARCH64_OPND_ADDR_SIMM13.
(fix_insn): Likewise.
(warn_unpredictable_ldst): Exempt STGP.
* testsuite/gas/aarch64/armv8_5-a-memtag.s: Add tests for stg, st2g,
stzg, stz2g and stgp.
* testsuite/gas/aarch64/armv8_5-a-memtag.d: Likewise.
* testsuite/gas/aarch64/illegal-memtag.s: Likewise.
* testsuite/gas/aarch64/illegal-memtag.l: Likewise.
This patch is part of the patch series to add support for ARMv8.5-A
Memory Tagging Extensions which is an optional extension to
ARMv8.5-A and is enabled using the +memtag command line option.
This patch add support to the Pointer Arithmetic instructions from
MTE. These are the following instructions added in this patch:
- SUBP <Xd>, <Xn|SP>, <Xm|SP>
- SUBPS <Xd>, <Xn|SP>, <Xm|SP>
- CMPP <Xn|SP>, <Xm|SP>
where CMPP is an alias to SUBPS XZR, <Xn|SP>, <Xm|SP>
where
<Xd> : Is the 64-bit destination GPR.
<Xn|SP> : Is the 64-bit first source GPR or Stack pointer.
<Xm|SP> : Is the 64-bit second source GPR or Stack pointer.
*** opcodes/ChangeLog ***
2018-11-12 Sudakshina Das <sudi.das@arm.com>
* aarch64-tbl.h (aarch64_opcode_table): Add subp, subps and cmpp.
* aarch64-asm-2.c: Regenerated.
* aarch64-dis-2.c: Regenerated.
* aarch64-opc-2.c: Regenerated.
*** gas/ChangeLog ***
2018-11-12 Sudakshina Das <sudi.das@arm.com>
* testsuite/gas/aarch64/armv8_5-a-memtag.s: Add tests for subp,
subps and cmpp.
* testsuite/gas/aarch64/armv8_5-a-memtag.d: Likewise.
* testsuite/gas/aarch64/illegal-memtag.s: Likewise.
* testsuite/gas/aarch64/illegal-memtag.l: Likewise.
This patch is part of the patch series to add support for ARMv8.5-A
Memory Tagging Extensions which is an optional extension to
ARMv8.5-A and is enabled using the +memtag command line option.
This patch add support to the Tag generation instructions from
MTE. These are the following instructions added in this patch:
- IRG <Xd|SP>, <Xn|SP>{, Xm}
- ADDG <Xd|SP>, <Xn|SP>, #<uimm1>. #<uimm2>
- SUBG <Xd|SP>, <Xn|SP>, #<uimm1>. #<uimm2>
- GMI <Xd>, <Xn|SP>, <Xm>
where
<Xd|SP> : Is the 64-bit destination GPR or Stack pointer.
<Xn|SP> : Is the 64-bit source GPR or Stack pointer.
<uimm6> : Is the unsigned immediate, a multiple of 16
in the range 0 to 1008.
<uimm4> : Is the unsigned immediate, in the range 0 to 15.
*** include/ChangeLog ***
2018-11-12 Sudakshina Das <sudi.das@arm.com>
* opcode/aarch64.h (aarch64_opnd): Add
AARCH64_OPND_UIMM4_ADDG and AARCH64_OPND_UIMM10 as new enums.
*** opcodes/ChangeLog ***
2018-11-12 Sudakshina Das <sudi.das@arm.com>
* aarch64-opc.h (aarch64_field_kind): New FLD_imm4_3.
(OPD_F_SHIFT_BY_4, operand_need_shift_by_four): New.
* aarch64-opc.c (fields): Add entry for imm4_3.
(operand_general_constraint_met_p): Add cases for
AARCH64_OPND_UIMM4_ADDG and AARCH64_OPND_UIMM10.
(aarch64_print_operand): Likewise.
* aarch64-tbl.h (QL_ADDG): New.
(aarch64_opcode_table): Add addg, subg, irg and gmi.
(AARCH64_OPERANDS): Define UIMM4_ADDG and UIMM10.
* aarch64-asm.c (aarch64_ins_imm): Add case for
operand_need_shift_by_four.
* aarch64-asm-2.c: Regenerated.
* aarch64-dis-2.c: Regenerated.
* aarch64-opc-2.c: Regenerated.
*** gas/ChangeLog ***
2018-11-12 Sudakshina Das <sudi.das@arm.com>
* config/tc-aarch64.c (parse_operands): Add switch case for
AARCH64_OPND_UIMM4_ADDG and AARCH64_OPND_UIMM10.
* testsuite/gas/aarch64/armv8_5-a-memtag.s: New.
* testsuite/gas/aarch64/armv8_5-a-memtag.d: Likewise.
* testsuite/gas/aarch64/illegal-memtag.s: Likewise.
* testsuite/gas/aarch64/illegal-memtag.l: Likewise.
* testsuite/gas/aarch64/illegal-memtag.d: Likewise.
This patch is part of the patch series to add support for ARMv8.5-A
Memory Tagging Extensions. Memory Tagging Extension is an optional extension to
ARMv8.5-A and is enabled using the +memtag command line option.
This patch adds the new command line option and the new feature macros.
*** include/ChangeLog ***
2018-11-12 Sudakshina Das <sudi.das@arm.com>
* opcode/aarch64.h (AARCH64_FEATURE_MEMTAG): New.
*** opcodes/ChangeLog ***
2018-11-12 Sudakshina Das <sudi.das@arm.com>
* aarch64-tbl.h (aarch64_feature_memtag): New.
(MEMTAG, MEMTAG_INSN): New.
*** gas/ChangeLog ***
2018-11-12 Sudakshina Das <sudi.das@arm.com>
* config/tc-aarch64.c (aarch64_features): Add "memtag"
as a new option.
* doc/c-aarch64.texi: Document the same.
This removes the VEC from remote_g_packet_data, replacing it with a
std::vector. This is a bit odd in that this object is never
destroyed, and is obstack-allocated. I believe a gdbarch is never
destroyed, so this seemed ok.
Tested by the buildbot.
gdb/ChangeLog
2018-11-09 Tom Tromey <tom@tromey.com>
* remote.c (remote_g_packet_guess_s): Remove typedef and DEF_VEC.
(struct remote_g_packet_data): Derive from allocate_on_obstack.
<guesses>: Now a std::vector.
(remote_g_packet_data_init, register_remote_g_packet_guess):
Update.
(remote_read_description_p): Update. Return bool.
(remote_target::read_description): Update.
(struct remote_g_packet_guess): Add constructor.
Use a ssize_t helper variable for the number of bytes to shrink the
msymbols obstack rather than relying on unsigned overflow to shrink
the size of the obstack.
gdb/ChangeLog:
* minsyms.c (minimal_symbol_reader::install): Fix unsigned
overflow.
As suggested in
https://sourceware.org/ml/gdb-patches/2018-10/msg00510.html, this
patch changes the documentation for the VSX tdesc feature to make it
clear that the altivec and FPU features are requirements.
gdb/doc/ChangeLog:
2018-11-09 Pedro Franco de Carvalho <pedromfc@linux.ibm.com>
* gdb.texinfo (PowerPC Features): Document the altivec and fpu
requirements for the org.gnu.gdb.power.vsx feature.
Added warning for static TLS reloc.
Fixed issue related to TLS and partial static linking of libraries:
This issue was detected when throwing exceptions in C++ while linking with
-static-libstdc++.
TLS relocation from the libstdc++ wasn't being patched as local now that it was
static linked with the executable.
Fix for TLS with static and pie. Problem introduced by earlier patch:
Fixes the following glibc tests:
- elf/tst-tls1-static
bfd/
xxxx-xx-xx Cupertino Miranda <cmiranda@synopsys.com>
* arc-got.h (arc_got_entry_type_for_reloc): Changed to
correct static TLS relocs.
* elf32-arc.c (elf_arc_check_relocs): Introduced warning to
TLS relocs which require -fPIC.
(arc_create_forced_local_got_entries_for_tls): Created.
Traverses list of GOT entries to be resolved statically
when needed.
(elf_arc_finish_dynamic_sections): Changed. Calls
arc_create_forced_local_got_entries_for_tls for each known
possibly GOT symbol.
* strings.c (print_strings): Check for multibyte encodings.
* binutils-all/strings-1.bin: New file. Test binary for string decoding.
* testsuite/binutils-all/strings.exp: New file. Test the strings program.
* testsuite/config/default.exp (STRINGS): Define if not provided
by the environment.
(STRINGSFLAGS): Likewise.
Fix a memory leak appearing when the local got entry list was constructed.
bfd/
xxxx-xx-xx Claudiu Zissulescu <claziss@synopsys.com>
* arc-got.h (arc_get_local_got_ents): Revamp it; use
elf_local_got_ents to store the local got list.
(get_got_entry_list_for_symbo): Restructure it.
* elf32-arc.c (elf_arc_relocate_section): Correct the call to
get_got_entry_list_for_symbol.
Consider a test-case with source files msym.c:
...
static int foo (void) { return 1; }
...
and msym_main.c:
...
static int foo (void) { return 2; }
int main (void) { return 0; }
..
compiled as c++ with minimal symbols:
...
$ g++ msym_main.c msym.c
...
With objdump -x we find the two foo symbols prefixed with their corresponding
files in the symbol table:
...
0000000000000000 l df *ABS* 0000000000000000 msym_main.c
00000000004004c7 l F .text 000000000000000b _ZL3foov
0000000000000000 l df *ABS* 0000000000000000 msym.c
00000000004004dd l F .text 000000000000000b _ZL3foov
...
However, when we use gdb to print info on foo, both foos are listed, but we
get one symbol mangled and one symbol demangled:
...
$ gdb ./a.out -batch -ex "info func foo"
All functions matching regular expression "foo":
Non-debugging symbols:
0x00000000004004c7 foo()
0x00000000004004dd _ZL3foov
...
During minimal symbol reading symbol_set_names is called for each symbol.
First, it's called with foo from msym.c, an entry is created in
per_bfd->demangled_names_hash and symbol_find_demangled_name is called, which
has the side effect of setting the language of the symbol to language_cplus.
Then, it's called with foo from msym_main.c. Since
per_bfd->demangled_names_hash already has an entry for that name,
symbol_find_demangled_name is not called, and the language of the symbol
remains language_auto.
Fix this by doing the symbol_find_demangled_name call unconditionally.
Build and reg-tested on x86_64-linux.
gdb/ChangeLog:
2018-11-09 Tom de Vries <tdevries@suse.de>
* symtab.c (symbol_set_names): Call symbol_find_demangled_name
unconditionally, to set the language of the symbol. Manage freeing
returned pointer using gdb::unique_xmalloc_ptr.
gdb/testsuite/ChangeLog:
2018-11-09 Tom de Vries <tdevries@suse.de>
* gdb.base/msym-lang.c: New test.
* gdb.base/msym-lang.exp: New file.
* gdb.base/msym-lang-main.c: New test.
Instructions having an optional argument following a memory address
operand were not handled correctly if the optional argument was not
specified.
gas/ChangeLog:
2018-11-09 Andreas Krebbel <krebbel@linux.ibm.com>
* config/tc-s390.c (skip_optargs_p): New function.
(md_gather_operands): Use skip_optargs_p.
* testsuite/gas/s390/s390.exp: Run the new test.
* testsuite/gas/s390/zarch-optargs.d: New test.
* testsuite/gas/s390/zarch-optargs.s: New test.
We support source like the following
.data
.quad x-.
.space 8
x:
where at the time the .quad line is assembled, x is unknown so a fixup
is emitted for later evaluation. This is supported for data even when
the target may not have relocations for the expression, for example,
32-bit powerpc targets lack a 64-bit reloc. As long as the fixup
resolves at assembly time, gas is happy.
The idea of this patch is to support fixups that resolve at assembly
time for instructions too, even when the target might lack the
necessary relocations (and thus no howto).
* config/tc-ppc.c (fixup_size): New function.
(md_assemble): Use it to derive size and pcrel directly
from fixup reloc type.
This changes require_record_target to say "<TAB>" rather than "<tab>".
I think capitalizing here is a bit more GNU-ish, based on Emacs usage
and one other case in gdb.
gdb/ChangeLog
2018-11-08 Tom Tromey <tom@tromey.com>
* record.c (require_record_target): Upper-case "<TAB>".
I noticed that "info pretty-printers" will indent the "objfile" line
like:
(top-gdb) info pretty-printer
global pretty-printers:
builtin
mpx_bound128
objfile /home/tromey/gdb/build/gdb/gdb pretty-printers:
type_lookup_function
I think the "objfile" line should be "out-dented", following the same
style as the "global" and "progspace" (not shown) lines.
This patch implements this.
gdb/ChangeLog
2018-11-08 Tom Tromey <tom@tromey.com>
* python/lib/gdb/command/pretty_printers.py
(InfoPrettyPrinter.invoke): Don't indent "objfile" heading.
I noticed that if you pass the name of an existing file (not a
directory) as the argument to --data-directory, gdb will crash:
$ ./gdb -nx --data-directory ./gdb
../../binutils-gdb/gdb/target.c:590:56: runtime error: member call on null pointer of type 'struct target_ops'
This was later reported as PR gdb/23838.
This happens because warning ends up calling
target_supports_terminal_ours, which calls current_top_target, which
returns nullptr this early.
This fixes the problem by handling this case specially in
target_supports_terminal_ours. I also changed
target_supports_terminal_ours to return bool.
gdb/ChangeLog
2018-11-08 Tom Tromey <tom@tromey.com>
PR gdb/23555:
PR gdb/23838:
* target.h (target_supports_terminal_ours): Return bool.
* target.c (target_supports_terminal_ours): Handle case where
current_top_target returns nullptr. Return bool.
gdb/testsuite/ChangeLog
2018-11-08 Tom Tromey <tom@tromey.com>
PR gdb/23555:
PR gdb/23838:
* gdb.base/warning.exp: New file.
Consider the gdb.ada/array_return.exp testcase, and in particular,
consider the following code...
type Small_Float_Vector is array (1 .. 2) of Float;
function Create_Small_Float_Vector return Small_Float_Vector is
begin
return (others => 4.25);
end Create_Small_Float_Vector;
... which declares a type which is an array with 2 floats in it
(floats are 4 bytes on AArch64), trying to get GDB to print
the return value from that function does not work:
(gdb) fin
Run till exit from #0 pck.create_small_float_vector () at /[...]/pck.adb:15
0x000000000000062c in p () at /[...]/p.adb:11
11 Vector := Create_Small_Float_Vector;
Value returned is $1 = (4.25, 0.0)
^^^
|||
We expected the value shown to be:
(gdb) fin
Run till exit from #0 pck.create_small_float_vector () at /[...]/pck.adb:15
0x000000000000062c in p () at /[...]/p.adb:11
11 Vector := Create_Small_Float_Vector;
Value returned is $1 = (4.25, 4.25)
Because the return type is an HFA, it is returned via the first two
SIMD registers. However, what happens is that the current implementation
fails to realize that this is an HFA, and therefore fetches the return
value from the wrong location. And the reason why it fails to realize
this is because it thinks that our array has 8 elements (HFAs have
a maximum of 4). Looking at aapcs_is_vfp_call_or_return_candidate_1,
where this is determined, we can easily see why (looks like a thinko):
| case TYPE_CODE_ARRAY:
| [...]
| struct type *target_type = TYPE_TARGET_TYPE (type);
| int count = aapcs_is_vfp_call_or_return_candidate_1
| (target_type, fundamental_type);
|
| if (count == -1)
| return count;
|
!! -> | count *= TYPE_LENGTH (type);
| return count;
Here, we first determine the count for one element of our array,
and so we should then be multiplying that count by the number
of elements in our array (2 in our case). But instead, we multiply it
by the total size (8). As a result, we do not classify the return
type as an HFA, and thus pick the wrong location for fetching
the return value.
gdb/ChangeLog:
* aarch64-tdep.c (aapcs_is_vfp_call_or_return_candidate_1):
return the correct count for potential HFAs.
Tested on aarch64-linux, fixes:
array_return.exp: value printed by finish of Create_Small_Float_Vector
The three AVX512 state components are entirely independent - one being
in its "init state" has no implication whatsoever on either of the other
two. Fully separate X86_XSTATE_ZMM_H and X86_XSTATE_ZMM handling, to
prevent upper halves of the upper 16 ZMM registers to display as if they
were zero (when they aren't) after e.g. VZEROALL/VZEROUPPER.
Update gdb.arch/riscv-reg-aliases.exp test to support targets without
floating point registers.
gdb/testsuite/ChangeLog:
* gdb.arch/riscv-reg-aliases.exp: Handle targets without floating
point hardware.
When we connect to a remote target one of the first things GDB does is
establish a frame id. If an error is thrown while building this frame
id then GDB will disconnect from the target.
This can mean that, if the user is attempting to connect to a target
that doesn't yet have a program loaded, or the program the user is
going to load onto the target doesn't match what is already loaded, or
the target is just in some undefined state, then the very first
request for a frame id can fail (for example, by trying to load from
an invalid memory address), and GDB will disconnect. It is then
impossible for the user to connect to the target and load a new
program at all.
An example of such a session might look like this:
Reading symbols from ./gdb/testsuite/outputs/gdb.arch/riscv-reg-aliases/riscv-reg-aliases...
(gdb) target remote :37191
Remote debugging using :37191
0x0000000000000100 in ?? ()
Cannot access memory at address 0x0
(gdb) load
You can't do that when your target is `exec'
(gdb) info frame
/path/to/gdb/gdb/thread.c:93: internal-error: thread_info* inferior_thread(): Assertion `tp' failed.
A problem internal to GDB has been detected,
further debugging may prove unreliable.
Quit this debugging session? (y or n)
The solution is to handle errors in riscv_frame_this_id, and leave the
this_id variable with its default value, which is the predefined
'outermost' frame.
With this fix in place, connecting to the same target now looks like
this:
(gdb) target remote :37191
Remote debugging using :37191
0x0000000000000100 in ?? ()
(gdb) info frame
Stack level 0, frame at 0x0:
pc = 0x100; saved pc = <not saved>
Outermost frame: outermost
Arglist at unknown address.
Locals at unknown address, Previous frame's sp in sp
gdb/ChangeLog:
* riscv-tdep.c (riscv_insn::decode): Update header comment.
(riscv_frame_this_id): Catch errors thrown while building the
frame cache, leave the frame id as the default, which is the outer
frame id.
The patch allows the gold testsuite to pass when using something like
the following configure line, which works for the rest of the binutils
testsuite. At least, it does if you don't configure your gcc with any
of the options that force a particular path to as or ld.
gccdir="/home/alan/build/gcc/prev-"
gccsrc="/home/alan/src/gcc.git"
gcctarg="x86_64-linux"
CC="${gccdir}gcc/xgcc -B${gccdir}gcc/" \
CXX="${gccdir}gcc/xg++ -B${gccdir}gcc/ -I${gccdir}$gcctarg/libstdc++-v3/include -I${gccdir}$gcctarg/libstdc++-v3/include/$gcctarg -I${gccsrc}/libstdc++-v3/libsupc++ -L${gccdir}$gcctarg/libstdc++-v3/src/.libs/" \
~/src/binutils-gdb/configure ...
gold's -Bgcctestdir/ option must come before the -B supplied by $CC
or $CXX, in order to pick up the linker we want to test. Also when
using a not-yet-installed gcc, it is necessary to provide a collect-ld
in gcctestdir/ as otherwise a collect-ld script in -B${gccdir}gcc/
will be used and the wrong linker tested.
Besides this, the patch fixes some bugs: The $COMPILE -D_FORTIFY_SOURCE
edit was wrong (but worked for usual values), and the $CXXLINK_S edit
unnecessarily but harmlessly used extra backslash quoting. See
posix shell documentation regarding quoting, or
www.gnu.org/software/bash/manual/bashref.html#Command-Substitution
Also, -Bgcctestdir/ in one place makes it less likely a new test will
be added that accidentally lacks the option.
* Makefile.am (gcctestdir1/ld): Use $@ and absolute paths.
(gcctestdir1/collect-ld): New.
(ld1_DEPENDENCIES): Add gcctestdir1/collect-ld.
(ld1_LDFLAGS): Remove -Bgcctestdir1/.
(editcc1, ld1_LINK): Define.
(gcctestdir2/ld, gcctestdir2/collect-ld, ld2_DEPENDENCIES),
(ld2_LDFLAGS, editcc2, ld2_LINK),
(ld1_r_DEPENDENCIES, ld1_r_LDFLAGS, ld1_r_LINK),
(gcctestdir2-r/ld, gcctestdir2-r/collect-ld, ld2_r_DEPENDENCIES),
(ld2_r_LDFLAGS, editcc2r, ld2_r_LINK),
(gcctestdir3/ld, gcctestdir3/collect-ld, ld3_DEPENDENCIES),
(ld3_LDFLAGS, editcc3, ld3_LINK),
(gcctestdir4/ld, gcctestdir4/collect-ld, ld4_DEPENDENCIES),
(ld4_LDFLAGS, editcc4, ld4_LINK): Similarly.
* Makefile.in: Regenerate.
* testsuite/Makefile.am (editcc): Define sed command to put
our -B option first. Remove other occurrences of -Bgcctestdir/
throughout file.
(editcc1): Define for -D_FORTIFY_SOURCE stripping.
(editcc2): Define for -static-libgcc/libstdc++ stripping.
(LINK1, CXXLINK1): Don't use CCLD or CXXLD.
(CCLD, CXXLD, COMPILE, LINK, CXXCOMPILE, CXXLINK, CXXLINK_S): Define
using editcc macros.
(gcctestdir/collect-ld): New rule, add as a dependency of..
(gcctestdir/ld): ..this. Use $@ and abs_top_buildir.
(gcctestdir/as): Use $@.
* testsuite/Makefile.in: Regenerate.
* testsuite/incremental_test.sh (actual): Match collect-ld too.
Jim Wilson
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