2012-10-23 19:02:30 +02:00
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/* Builtins' description for AArch64 SIMD architecture.
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2022-01-03 10:42:10 +01:00
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Copyright (C) 2011-2022 Free Software Foundation, Inc.
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2012-10-23 19:02:30 +02:00
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Contributed by ARM Ltd.
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This file is part of GCC.
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GCC is free software; you can redistribute it and/or modify it
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under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 3, or (at your option)
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any later version.
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GCC is distributed in the hope that it will be useful, but
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WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with GCC; see the file COPYING3. If not see
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<http://www.gnu.org/licenses/>. */
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2017-12-16 15:10:55 +01:00
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#define IN_TARGET_CODE 1
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2012-10-23 19:02:30 +02:00
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#include "config.h"
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#include "system.h"
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#include "coretypes.h"
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#include "tm.h"
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2015-07-08 02:53:03 +02:00
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#include "function.h"
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#include "basic-block.h"
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2015-10-16 21:47:09 +02:00
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#include "rtl.h"
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2015-07-08 02:53:03 +02:00
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#include "tree.h"
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#include "gimple.h"
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2021-09-02 09:08:22 +02:00
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#include "ssa.h"
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Move MEMMODEL_* from coretypes.h to memmodel.h
2016-10-13 Thomas Preud'homme <thomas.preudhomme@arm.com>
gcc/
* coretypes.h: Move MEMMODEL_* macros and enum memmodel definition
into ...
* memmodel.h: This file.
* alias.c, asan.c, auto-inc-dec.c, bb-reorder.c, bt-load.c,
caller-save.c, calls.c, ccmp.c, cfgbuild.c, cfgcleanup.c,
cfgexpand.c, cfgloopanal.c, cfgrtl.c, cilk-common.c, combine.c,
combine-stack-adj.c, common/config/aarch64/aarch64-common.c,
common/config/arm/arm-common.c, common/config/bfin/bfin-common.c,
common/config/c6x/c6x-common.c, common/config/i386/i386-common.c,
common/config/ia64/ia64-common.c, common/config/nvptx/nvptx-common.c,
compare-elim.c, config/aarch64/aarch64-builtins.c,
config/aarch64/aarch64-c.c, config/aarch64/cortex-a57-fma-steering.c,
config/arc/arc.c, config/arc/arc-c.c, config/arm/arm-builtins.c,
config/arm/arm-c.c, config/avr/avr.c, config/avr/avr-c.c,
config/avr/avr-log.c, config/bfin/bfin.c, config/c6x/c6x.c,
config/cr16/cr16.c, config/cris/cris.c, config/darwin-c.c,
config/darwin.c, config/epiphany/epiphany.c,
config/epiphany/mode-switch-use.c,
config/epiphany/resolve-sw-modes.c, config/fr30/fr30.c,
config/frv/frv.c, config/ft32/ft32.c, config/h8300/h8300.c,
config/i386/i386-c.c, config/i386/winnt.c, config/iq2000/iq2000.c,
config/lm32/lm32.c, config/m32c/m32c.c, config/m32r/m32r.c,
config/m68k/m68k.c, config/mcore/mcore.c,
config/microblaze/microblaze.c, config/mmix/mmix.c,
config/mn10300/mn10300.c, config/moxie/moxie.c,
config/msp430/msp430.c, config/nds32/nds32-cost.c,
config/nds32/nds32-intrinsic.c, config/nds32/nds32-md-auxiliary.c,
config/nds32/nds32-memory-manipulation.c,
config/nds32/nds32-predicates.c, config/nds32/nds32.c,
config/nios2/nios2.c, config/nvptx/nvptx.c, config/pa/pa.c,
config/pdp11/pdp11.c, config/rl78/rl78.c, config/rs6000/rs6000-c.c,
config/rx/rx.c, config/s390/s390-c.c, config/s390/s390.c,
config/sh/sh.c, config/sh/sh-c.c, config/sh/sh-mem.cc,
config/sh/sh_treg_combine.cc, config/sol2.c, config/spu/spu.c,
config/stormy16/stormy16.c, config/tilegx/tilegx.c,
config/tilepro/tilepro.c, config/v850/v850.c, config/vax/vax.c,
config/visium/visium.c, config/vms/vms-c.c, config/xtensa/xtensa.c,
coverage.c, cppbuiltin.c, cprop.c, cse.c, cselib.c, dbxout.c, dce.c,
df-core.c, df-problems.c, df-scan.c, dojump.c, dse.c, dwarf2asm.c,
dwarf2cfi.c, dwarf2out.c, emit-rtl.c, except.c, explow.c, expmed.c,
expr.c, final.c, fold-const.c, function.c, fwprop.c, gcse.c,
ggc-page.c, haifa-sched.c, hsa-brig.c, hsa-gen.c, hw-doloop.c,
ifcvt.c, init-regs.c, internal-fn.c, ira-build.c, ira-color.c,
ira-conflicts.c, ira-costs.c, ira-emit.c, ira-lives.c, ira.c, jump.c,
loop-doloop.c, loop-invariant.c, loop-iv.c, loop-unroll.c,
lower-subreg.c, lra.c, lra-assigns.c, lra-coalesce.c,
lra-constraints.c, lra-eliminations.c, lra-lives.c, lra-remat.c,
lra-spills.c, mode-switching.c, modulo-sched.c, omp-low.c, passes.c,
postreload-gcse.c, postreload.c, predict.c, print-rtl-function.c,
recog.c, ree.c, reg-stack.c, regcprop.c, reginfo.c, regrename.c,
reload.c, reload1.c, reorg.c, resource.c, rtl-chkp.c, rtl-tests.c,
rtlanal.c, rtlhooks.c, sched-deps.c, sched-rgn.c, sdbout.c,
sel-sched-ir.c, sel-sched.c, shrink-wrap.c, simplify-rtx.c,
stack-ptr-mod.c, stmt.c, stor-layout.c, target-globals.c,
targhooks.c, toplev.c, tree-nested.c, tree-outof-ssa.c,
tree-profile.c, tree-ssa-coalesce.c, tree-ssa-ifcombine.c,
tree-ssa-loop-ivopts.c, tree-ssa-loop.c, tree-ssa-reassoc.c,
tree-ssa-sccvn.c, tree-vect-data-refs.c, ubsan.c, valtrack.c,
var-tracking.c, varasm.c: Include memmodel.h.
* genattrtab.c (write_header): Include memmodel.h in generated file.
* genautomata.c (main): Likewise.
* gengtype.c (open_base_files): Likewise.
* genopinit.c (main): Likewise.
* genconditions.c (write_header): Include memmodel.h earlier in
generated file.
* genemit.c (main): Likewise.
* genoutput.c (output_prologue): Likewise.
* genpeep.c (main): Likewise.
* genpreds.c (write_insn_preds_c): Likewise.
* genrecog.c (write_header): Likewise.
* Makefile.in (PLUGIN_HEADERS): Include memmodel.h
gcc/ada/
* gcc-interface/utils2.c: Include memmodel.h.
gcc/c-family/
* c-cppbuiltin.c: Include memmodel.h.
* c-opts.c: Likewise.
* c-pragma.c: Likewise.
* c-warn.c: Likewise.
gcc/c/
* c-typeck.c: Include memmodel.h.
gcc/cp/
* decl2.c: Include memmodel.h.
* rtti.c: Likewise.
gcc/fortran/
* trans-intrinsic.c: Include memmodel.h.
gcc/go/
* go-backend.c: Include memmodel.h.
libgcc/
* libgcov-profiler.c: Replace MEMMODEL_* macros by their __ATOMIC_*
equivalent.
* config/tilepro/atomic.c: Likewise and stop casting model to
enum memmodel.
From-SVN: r241121
2016-10-13 16:17:52 +02:00
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#include "memmodel.h"
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2015-10-16 21:47:09 +02:00
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#include "tm_p.h"
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#include "expmed.h"
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#include "optabs.h"
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#include "recog.h"
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#include "diagnostic-core.h"
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genattrtab.c (write_header): Include hash-set.h...
2015-01-09 Michael Collison <michael.collison@linaro.org>
* genattrtab.c (write_header): Include hash-set.h, machmode.h,
vec.h, double-int.h, input.h, alias.h, symtab.h, options.h
fold-const.h, wide-int.h, and inchash.h when generating
insn-attrtab.c.
* genautomata.c (main) : Include hash-set.h, macInclude hash-set.h, machmode.h,
vec.h, double-int.h, input.h, alias.h, symtab.h, options.h
fold-const.h, wide-int.h, and inchash.h when generating
insn-automata.c.
* genemit.c (main): Include hash-set.h, machmode.h,
vec.h, double-int.h, input.h, alias.h, symtab.h, options.h
fold-const.h, wide-int.h, and inchash.h when generating
insn-emit.c.
* gengtype.c (open_base_files): Include hash-set.h, machmode.h,
vec.h, double-int.h, input.h, alias.h, symtab.h, options.h
fold-const.h, wide-int.h, and inchash.h when generating
gtype-desc.c.
* genopinit.c (main): Include hash-set.h, machmode.h,
vec.h, double-int.h, input.h, alias.h, symtab.h, options.h
fold-const.h, wide-int.h, and inchash.h when generating
insn-opinit.c.
* genoutput.c (output_prologue): Include hash-set.h, machmode.h,
vec.h, double-int.h, input.h, alias.h, symtab.h, options.h
fold-const.h, wide-int.h, and inchash.h when generating
insn-output.c.
* genpeep.c (main): Include hash-set.h, machmode.h,
vec.h, double-int.h, input.h, alias.h, symtab.h, options.h
fold-const.h, wide-int.h, and inchash.h when generating
insn-peep.c.
* genpreds.c (write_insn_preds_c): Include hash-set.h, machmode.h,
vec.h, double-int.h, input.h, alias.h, symtab.h, options.h
fold-const.h, wide-int.h, and inchash.h when generating
insn-preds.c.
* optc-save-gen-awk: Include hash-set.h, machmode.h,
vec.h, double-int.h, input.h, alias.h, symtab.h, options.h
fold-const.h, wide-int.h, and inchash.h when generating
options-save.c.
* opth-gen.awk: Change include guard from GCC_C_COMMON_H to GCC_C_COMMON_C
when generating options.h.
* ada/gcc-interface/cuintp.c: Include hash-set.h, machmode.h,
vec.h, double-int.h, input.h, alias.h, symtab.h,
fold-const.h, wide-int.h, and inchash.h due to
flattening of tree.h.
* ada/gcc-interface/decl.c: ditto.
* ada/gcc-interface/misc.c: ditto.
* ada/gcc-interface/targtyps.c: Include hash-set.h, machmode.h,
vec.h, double-int.h, input.h, alias.h, symtab.h, options.h,
fold-const.h, wide-int.h, and inchash.h due to
flattening of tree.h.
* ada/gcc-interface/trans.c: Include hash-set.h, machmode.h,
vec.h, double-int.h, input.h, alias.h, symtab.h, real.h,
fold-const.h, wide-int.h, inchash.h due to
flattening of tree.h.
* ada/gcc-interface/utils.c: Include hash-set.h, machmode.h,
vec.h, double-int.h, input.h, alias.h, symtab.h,
fold-const.h, wide-int.h, and inchash.h due to
flattening of tree.h.
* ada/gcc-interface/utils2.c: ditto.
* alias.c: Include hash-set.h, machmode.h,
vec.h, double-int.h, input.h, alias.h, symtab.h, options.h
fold-const.h, wide-int.h, and inchash.h due to
flattening of tree.h.
* asan.c: ditto.
* attribs.c: ditto.
* auto-inc-dec.c: ditto.
* auto-profile.c: ditto
* bb-reorder.c: ditto.
* bt-load.c: Include symtab.h due to flattening of tree.h.
* builtins.c: Include hash-set.h, machmode.h,
vec.h, double-int.h, input.h, alias.h, symtab.h, options.h
fold-const.h, wide-int.h, and inchash.h due to
flattening of tree.h.
* c/c-array-notation.c: ditto.
* c/c-aux-info.c: ditto.
* c/c-convert.c: ditto.
* c/c-decl.c: ditto.
* c/c-errors.c: ditto.
* c/c-lang.c: dittoxs.
* c/c-objc-common.c: ditto.
* c/c-parser.c: ditto.
* c/c-typeck.c: Include hash-set.h, machmode.h,
vec.h, double-int.h, input.h, alias.h, symtab.h, options.h
fold-const.h, wide-int.h, inchash.h, real.h and
fixed-value.h due to flattening of tree.h.
* calls.c: Include hash-set.h, machmode.h,
vec.h, double-int.h, input.h, alias.h, symtab.h, options.h
fold-const.h, wide-int.h, and inchash.h due to
flattening of tree.h.
* ccmp.c: ditto.
* c-family/array-notation-common.c: ditto.
* c-family/c-ada-spec.c: ditto.
* c-family/c-cilkplus.c: ditto.
* c-family/c-common.c: Include input.h due to flattening of tree.h.
Define macro GCC_C_COMMON_C.
* c-family/c-common.h: Flatten tree.h header files into c-common.h.
Remove include of tree-core.h.
* c-family/c-cppbuiltin.c: Include hash-set.h, machmode.h,
vec.h, double-int.h, input.h, alias.h, symtab.h, options.h
fold-const.h, wide-int.h, and inchash.h due to
flattening of tree.h.
* c-family/c-dump.c: ditto.
* c-family/c-format.c: Flatten tree.h header files into c-common.h.
* c-family/c-cppbuiltin.c: Include hash-set.h, machmode.h,
vec.h, double-int.h, input.h, alias.h, symtab.h, options.h
fold-const.h, wide-int.h, and inchash.h due to
flattening of tree.h.
* c-family/c-dump.c: Include hash-set.h, machmode.h,
vec.h, double-int.h, input.h, alias.h, symtab.h, options.h
fold-const.h, wide-int.h, and inchash.h due to
flattening of tree.h.
* c-family/c-format.c: Include hash-set.h, machmode.h,
vec.h, double-int.h, input.h, alias.h, symtab.h, options.h
fold-const.h, wide-int.h, inchash.h and real.h due to
flattening of tree.h.
* c-family/c-gimplify.c: Include hash-set.h, machmode.h,
vec.h, double-int.h, input.h, alias.h, symtab.h, options.h
fold-const.h, wide-int.h, and inchash.h due to
flattening of tree.h.
* c-family/cilk.c: ditto.
* c-family/c-lex.c: ditto.
* c-family/c-omp.c: ditto.
* c-family/c-opts.c: ditto.
* c-family/c-pch.c: ditto.
* c-family/c-ppoutput.c: ditto.
* c-family/c-pragma.c: ditto.
* c-family/c-pretty-print.c: ditto.
* c-family/c-semantics.c: ditto.
* c-family/c-ubsan.c: ditto.
* c-family/stub-objc.c: ditto.
* cfgbuild.c: ditto.
* cfg.c: ditto.
* cfgcleanup.c: ditto.
* cfgexpand.c: ditto.
* cfghooks.c: ditto.
* cfgloop.c: Include symtab.h, fold-const.h, and
inchash.h due to flattening of tree.h.
* cfgloopmanip.c: ditto.
* cfgrtl.c: Include hash-set.h, machmode.h,
vec.h, double-int.h, input.h, alias.h, symtab.h, options.h
fold-const.h, wide-int.h, and inchash.h due to
flattening of tree.h.
* cgraphbuild.c: ditto.
* cgraph.c: ditto.
* cgraphclones.c: ditto.
* cgraphunit.c: ditto.
* cilk-common.c: ditto.
* combine.c: ditto.
* combine-stack-adj.c: Include symbol.h due to flattening of tree.h.
* config/aarch64/aarch64-builtins.c: Include hash-set.h, machmode.h,
vec.h, double-int.h, input.h, alias.h, symtab.h, options.h
fold-const.h, wide-int.h, and inchash.h due to
flattening of tree.h.
* config/aarch64/aarch64.c: ditto.
* config/alpha/alpha.c: ditto.
* config/arc/arc.c: ditto.
* config/arm/aarch-common.c: ditto.
* config/arm/arm-builtins.c: ditto.
* config/arm/arm.c: ditto.
* config/arm/arm-c.c: ditto.
* config/avr/avr.c: ditto.
* config/avr/avr-c.c: ditto.
* config/avr/avr-log.c: ditto.
* config/bfin/bfin.c: ditto.
* config/c6x/c6x.c: ditto.
* config/cr16/cr16.c: ditto.
* config/cris/cris.c: ditto.
* config/darwin.c: ditto.
* config/darwin-c.c: ditto.
* config/default-c.c: ditto.
* config/epiphany/epiphany.c: ditto.
* config/fr30/fr30.c: ditto.
* config/frv/frv.c: ditto.
* config/glibc-c.c: ditto.
* config/h8300/h8300.c: ditto.
* config/i386/i386.c: ditto.
* config/i386/i386-c.c: ditto.
* config/i386/msformat.c: ditto.
* config/i386/winnt.c: ditto.
* config/i386/winnt-cxx.c: ditto.
* config/i386/winnt-stubs.c: ditto.
* config/ia64/ia64.c: ditto.
* config/ia64/ia64-c.c: ditto.
* config/iq2000/iq2000.c: ditto.
* config/lm32/lm32.c: Include symtab.h, fold-const.h,
wide-int.h, and inchash.h due to flattening of tree.h.
* config/m32c/m32c.c: Include hash-set.h, machmode.h,
vec.h, double-int.h, input.h, alias.h, symtab.h, options.h
fold-const.h, wide-int.h, and inchash.h due to
flattening of tree.h.
* config/m32c/m32c-pragma.c: ditto.
* config/m32c/m32cr.c: ditto.
* config/m68/m68k.c: ditto.
* config/mcore/mcore.c: ditto.
* config/mep/mep.c: ditto.
* config/mep/mep-pragma.c: ditto.
* config/microblaze/microblaze.c: ditto.
* config/microblaze/microblaze-c.c: ditto.
* config/mips/mips.c: ditto.
* config/mmix/mmix.c: Include symtab.h, fold-const.h,
wide-int.h, and inchash.h due to flattening of tree.h.
* config/mn10300/mn10300.c: Include hash-set.h, machmode.h,
vec.h, double-int.h, input.h, alias.h, symtab.h, options.h
fold-const.h, wide-int.h, and inchash.h due to
flattening of tree.h.
* config/moxie/moxie.c: ditto.
* config/msp430/msp430.c: ditto.
* config/msp430/msp430-c.c: ditto.
* config/nds32/nds32.c: ditto.
* config/nds32/nds32-cost.c: ditto.
* config/nds32/nds32-fp-as-gp.c: ditto.
* config/nds32/nds32-intrinsic.c: ditto.
* config/nds32/nds32-isr.c: ditto.
* config/nds32/nds32-md-auxillary.c: ditto.
* config/nds32/nds32-memory-manipulationx.c: ditto.
* config/nds32/nds32-pipelines-auxillary.c: ditto.
* config/nds32/nds32-predicates.c: ditto.
* config/nios2/nios2.c: ditto.
* config/nvptx/nvptx.c: ditto.
* config/pa/pa.c: ditto.
* config/pdp11/pdp11x.c: Include symtab.h, fold-const.h,
wide-int.h, and inchash.h due to flattening of tree.h.
* config/rl78/rl78.c: Include hash-set.h, machmode.h,
vec.h, double-int.h, input.h, alias.h, symtab.h, options.h
fold-const.h, wide-int.h, and inchash.h due to
flattening of tree.h.
* config/rl78/rl78-cx.c: ditto.
* config/rs6000/rs6000.c: ditto.
* config/rs6000/rs6000-c.c: ditto.
* config/rx/rx.c: ditto.
* config/s390/s390.c: ditto.
* config/sh/sh.c: ditto.
* config/sh/sc.c: ditto.
* config/sh/sh-mem.cc: ditto.
* config/sh/sh_treg_combine.cc: Include symtab.h, inchash.h and tree.h
due to flattening of tree.h.
Remove include of tree-core.h.
* config/sol2.c: Include hash-set.h, machmode.h,
vec.h, double-int.h, input.h, alias.h, symtab.h, options.h
fold-const.h, wide-int.h, and inchash.h due to
flattening of tree.h.
* config/sol2-c.c: ditto.
* config/sol2-cxx.c: ditto.
* config/sol2-stubs.c: ditto.
* config/sparc/sparc.c: ditto.
* config/sparc/sparc-cx.c: ditto.
* config/spu/spu.c: ditto.
* config/spu/spu-c.c: ditto
* config/storym16/stormy16.c: ditto.
* config/tilegx/tilegx.c: Include symtab.h, fold-const.h,
wide-int.h, and inchash.h due to flattening of tree.h.
* config/tilepro/gen-mul-tables.cc: Include symtab.h in generated file.
* config/tilegx/tilegx-c.c: Include hash-set.h, machmode.h,
vec.h, double-int.h, input.h, alias.h, symtab.h, options.h
fold-const.h, wide-int.h, and inchash.h due to
flattening of tree.h.
* config/tilepro/tilepro.c: Include symtab.h, fold-const.h,
wide-int.h, and inchash.h due to flattening of tree.h.
* config/tilepro/tilepro-c.c: Include hash-set.h, machmode.h,
vec.h, double-int.h, input.h, alias.h, symtab.h, options.h
fold-const.h, wide-int.h, and inchash.h due to
flattening of tree.h.
* config/v850/v850.c: ditto.
* config/v850/v850-c.c: ditto.
* config/vax/vax.c: ditto.
* config/vms/vms.c: ditto.
* config/vms/vms-c.c: ditto.
* config/vxworks.c: ditto.
* config/winnt-c.c: ditto.
* config/xtensa/xtensa.c: Include symtab.h, fold-const.h,
wide-int.h, and inchash.h due to flattening of tree.h.
* convert.c: Include hash-set.h, machmode.h, vec.h, double-int.h,
input.h, alias.h, symtab.h, options.h, fold-const.h,
wide-int.h, and inchash.h due to flattening of tree.h.
* coverage.c: ditto.
* cp/call.c: ditto.
* cp/class.c: ditto.
* cp/constexpr.c: ditto.
* cp/cp-array-notation.c: ditto.
* cp/cp-gimplify.c: ditto.
* cp/cp-lang.c: ditto.
* cp/cp-objcp-common.c: ditto.
* cp/cvt.c: ditto.
* cp/decl2.c: ditto.
* cp/decl.c: ditto.
* cp/dump.c: ditto.
* cp/error.c: ditto.
* cp/except.c: ditto.
* cp/expr.c: ditto.
* cp/friend.c: ditto.
* cp/init.c: ditto.
* cp/lambda.c: ditto.
* cp/lex.c: ditto.
* cp/mangle.c: ditto.
* cp/name-lookup.c: ditto.
* cp/optimize.c: ditto.
* cp/parser.c: ditto.
* cp/pt.c: ditto.
* cp/ptree.c: ditto.
* cp/repo.c: ditto.
* cp/rtti.c: ditto.
* cp/search.c: ditto.
* cp/semantics.c: ditto.
* cp/tree.c: ditto.
* cp/typeck2.c: ditto.
* cp/typeck.c: ditto.
* cppbuiltin.c: ditto.
* cprop.c: ditto.
* cse.c: Add include of symtab.h due to flattening of tree.h.
* cselib.c: Include hash-set.h, machmode.h, vec.h, double-int.h,
input.h, alias.h, symtab.h, options.h, fold-const.h,
wide-int.h, and inchash.h due to flattening of tree.h.
* data-streamer.c: ditto.
* data-streamer-in.c: ditto.
* data-streamer-out.c: ditto.
* dbxout.c: ditto.
* dce.c: ditto.
* ddg.c: Add include of symtab.h due to flattening of tree.h.
* debug.c: Include hash-set.h, machmode.h, vec.h, double-int.h,
input.h, alias.h, symtab.h, options.h, fold-const.h,
wide-int.h, and inchash.h due to flattening of tree.h.
* dfp.c: ditto.
* df-scan.c: ditto.
* dojump.c: Include hash-set.h, machmode.h, vec.h, double-int.h,
input.h, alias.h, symtab.h, options.h, fold-const.h,
wide-int.h, inchash.h and real.h due to flattening of tree.h.
* double-int.c: ditto.
* dse.c: ditto.
* dumpfile.c: ditto.
* dwarf2asm.c: Include hash-set.h, machmode.h, vec.h, double-int.h,
input.h, alias.h, symtab.h, fold-const.h,
wide-int.h, inchash.h and real.h due to flattening of tree.h.
* dwarf2cfi.c: ditto.
* dwarf2out.c: ditto.
* emit-rtl.c: ditto.
* except.c: ditto.
* explow.c: ditto.
* expmed.c: Include hash-set.h, machmode.h, vec.h, double-int.h,
input.h, alias.h, symtab.h, fold-const.h,
wide-int.h, and inchash.h due to flattening of tree.h.
* expr.c: ditto.
* final.c: ditto.
* fixed-value.c: Include hash-set.h, machmode.h, vec.h, double-int.h,
input.h, alias.h, symtab.h, fold-const.h,
wide-int.h, inchash.h and fixed-value.h due to flattening of tree.h.
* fold-const.c: Include hash-set.h, machmode.h, vec.h, double-int.h,
input.h, alias.h, symtab.h, fold-const.h,
wide-int.h, and inchash.h due to flattening of tree.h.
Relocate inline function convert_to_ptrofftype_loc from tree.h.
Relocate inline function fold_build_pointer_plus_loc from tree.h.
Relocate inline function fold_build_pointer_plus_hwi_loc from tree.h.
* fold-const.h: Relocate macro convert_to_ptrofftype from tree.h.
Relocate macro fold_build_pointer_plus to relocate from tree.h.h.
Relocate macro fold_build_pointer_plus_hwi from tree.h.
Add prototype for convert_to_ptrofftype_loc relocated from tree.h.
Add prototype for fold_build_pointer_plus_loc relocated from tree.h.
Add prototype for fold_build_pointer_plus_hwi_loc relocated from tree.h.
* fortran/convert.c: Include hash-set.h, machmode.h, vec.h, double-int.h,
input.h, alias.h, symtab.h, options.h, fold-const.h,
wide-int.h, and inchash.h due to flattening of tree.h.
* fortran/cpp.c: Include hash-set.h, machmode.h, vec.h, double-int.h,
input.h, alias.h, symtab.h, fold-const.h,
wide-int.h, and inchash.h due to flattening of tree.h.
* fortran/decl.c: ditto.
* fortran/f95.c: Include hash-set.h, machmode.h, vec.h, double-int.h,
input.h, alias.h, symtab.h, options.h, fold-const.h,
wide-int.h, and inchash.h due to flattening of tree.h.
* fortran/iresolve.c: ditto.
* fortran/match.c: Include hash-set.h, machmode.h, vec.h, double-int.h,
input.h, alias.h, symtab.h, fold-const.h,
wide-int.h, and inchash.h due to flattening of tree.h.
* fortran/module.c: Include hash-set.h, machmode.h, vec.h, double-int.h,
input.h, alias.h, symtab.h, options.h, fold-const.h,
wide-int.h, and inchash.h due to flattening of tree.h.
* fortran/options.c: ditto.
* fortran/target-memory.c: Include hash-set.h, vec.h,
double-int.h, input.h, alias.h, symtab.h, fold-const.h,
wide-int.h, and inchash.h due to flattening of tree.h.
* fortran/trans-array.c: Include hash-set.h, machmode.h, vec.h, double-int.h,
input.h, alias.h, symtab.h, options.h, fold-const.h,
wide-int.h, and inchash.h due to flattening of tree.h.
* fortran/trans.c: Include hash-set.h, machmode.h, vec.h, double-int.h,
input.h, alias.h, symtab.h, options.h, fold-const.h,
wide-int.h, and inchash.h due to flattening of tree.h.
* fortran/trans-common.c: Include hash-set.h, machmode.h, vec.h, double-int.h,
input.h, alias.h, symtab.h, fold-const.h,
wide-int.h, and inchash.h due to flattening of tree.h.
* fortran/trans-const.c: ditto.
* fortran/trans-decl.c: ditto.
* fortran/trans-expr.c: Include hash-set.h, machmode.h, vec.h, double-int.h,
input.h, alias.h, symtab.h, options.h, fold-const.h,
wide-int.h, and inchash.h due to flattening of tree.h.
* fortran/trans-intrinsic.c: Include hash-set.h, machmode.h, vec.h, double-int.h,
input.h, alias.h, symtab.h, fold-const.h,
wide-int.h, inchash.h and real.h due to flattening of tree.h.
* fortran/trans-io.c: Include hash-set.h, machmode.h, vec.h, double-int.h,
input.h, alias.h, symtab.h, options.h, fold-const.h,
wide-int.h, and inchash.h due to flattening of tree.h.
* fortran/trans-openmp.c: ditto.
* fortran/trans-stmt.c: ditto.
* fortran/trans-types.c: Include hash-set.h, machmode.h, vec.h, double-int.h,
input.h, alias.h, symtab.h, fold-const.h,
wide-int.h, inchash.h and real.h due to flattening of tree.h.
* function.c: Include hash-set.h, machmode.h, vec.h, double-int.h,
input.h, alias.h, symtab.h, fold-const.h,
wide-int.h, and inchash.h due to flattening of tree.h.
* gcc-plugin.h: Include statistics.h, double-int.h, real.h, fixed-value.h,
alias.h, flags.h, and symtab.h due to flattening of tree.h
* gcse.c: ditto.
* generic-match-head.c: Include hash-set.h, machmode.h, vec.h, double-int.h,
input.h, alias.h, symtab.h, options.h, fold-const.h,
wide-int.h, and inchash.h due to flattening of tree.h.
* ggc-page.c: Include hash-set.h, machmode.h, vec.h, double-int.h,
input.h, alias.h, symtab.h, fold-const.h,
wide-int.h, and inchash.h due to flattening of tree.h.
* gimple-builder.c: ditto.
* gimple.c: ditto.
* gimple-expr.c: ditto.
* gimple-fold.c: ditto.
* gimple-iterator.c: ditto.
* gimple-low.c: ditto.
* gimple-match-head.c: ditto.
* gimple-pretty-print.c: ditto.
* generic-ssa-isolate-paths.c: Include hash-set.h, machmode.h, vec.h, double-int.h,
input.h, alias.h, symtab.h, options.h, fold-const.h,
wide-int.h, and inchash.h due to flattening of tree.h.
* gimple-ssa-strength-reduction.c: ditto.
* gimple-streamer-in.c: ditto.
* gimple-streamer-out.c: ditto.
* gimple-walk.c: Include hash-set.h, machmode.h, vec.h, double-int.h,
input.h, alias.h, symtab.h, fold-const.h,
wide-int.h, and inchash.h due to flattening of tree.h.
* gimplify.c: Include hash-set.h, machmode.h, vec.h, double-int.h,
input.h, alias.h, symtab.h, options.h, fold-const.h,
wide-int.h, and inchash.h due to flattening of tree.h.
* gimplify-me.c: ditto.
* go/go-gcc.cc: ditto.
* go/go-lang.c: ditto.
* go/gdump.c: ditto.
* graphite-blocking.c: ditto.
* graphite.c: ditto.
* graphite-dependencies.c: ditto.
* graphite-interchange.c: ditto.
* graphite-isl-ast-to-gimple.c: ditto.
* graphite-optimize-isl.c: ditto.
* graphite-poly.c: ditto.
* graphite-scop-detection.c: ditto.
* graphite-sese-to-poly.c: ditto.
* hw-doloop.c: Include symtab.h due to flattening of tree.h.
* ifcvt.c: ditto.
* init-regs.c: Include hash-set.h, machmode.h, vec.h, double-int.h,
input.h, alias.h, symtab.h, fold-const.h,
wide-int.h, and inchash.h due to flattening of tree.h.
* internal-fc.c: Include hash-set.h, machmode.h, vec.h, double-int.h,
input.h, alias.h, symtab.h,options.h, fold-const.h,
wide-int.h, and inchash.h due to flattening of tree.h.
* ipa.c: ditto.
* ipa-chkp.c: ditto.
* ipa-comdats.c: Include hash-set.h, machmode.h, vec.h, double-int.h,
input.h, alias.h, symtab.h, fold-const.h,
wide-int.h, and inchash.h due to flattening of tree.h.
* ipa-cp.c: Include hash-set.h, machmode.h, vec.h, double-int.h,
input.h, alias.h, symtab.h,options.h, fold-const.h,
wide-int.h, and inchash.h due to flattening of tree.h.
* ipa-devirt.c: Include hash-set.h, machmode.h, vec.h, double-int.h,
input.h, alias.h, symtab.h, fold-const.h,
wide-int.h, and inchash.h due to flattening of tree.h.
* ipa-icf.c: Include hash-set.h, machmode.h, vec.h, double-int.h,
input.h, alias.h, symtab.h,options.h, fold-const.h,
wide-int.h, and inchash.h due to flattening of tree.h.
* ipa-icf-gimple.c: ditto.
* ipa-inline-analysis.c: Include hash-set.h, machmode.h, vec.h, double-int.h,
input.h, alias.h, symtab.h, fold-const.h,
wide-int.h, and inchash.h due to flattening of tree.h.
* ipa-inline.c: ditto.
* ipa-inline-transform.c: ditto.
* ipa-polymorhpic-call.c: ditto.
* ipa-profile.c: ditto.
* ipa-prop.c: Include hash-set.h, machmode.h, vec.h, double-int.h,
input.h, alias.h, symtab.h, options.h, fold-const.h,
wide-int.h, and inchash.h due to flattening of tree.h.
* ipa-pure-const.c: Include hash-set.h, machmode.h, vec.h, double-int.h,
input.h, alias.h, symtab.h, fold-const.h,
wide-int.h, and inchash.h due to flattening of tree.h.
* ipa-ref.c: Include hash-set.h, machmode.h, vec.h, double-int.h,
input.h, alias.h, symtab.h, options.h, fold-const.h,
wide-int.h, and inchash.h due to flattening of tree.h.
* ipa-reference.c: ditto.
* ipa-split.c: ditto.
* ipa-utils.c: ditto.
* ipa-visbility.c: Include hash-set.h, machmode.h, vec.h, double-int.h,
input.h, alias.h, symtab.h, fold-const.h,
wide-int.h, and inchash.h due to flattening of tree.h.
* ira.c: ditto.
* ira-color.c: Include hash-set.h due to flattening of tree.h.
* ira-costs.c: ditto.
* ira-emit.c: ditto.
* java/boehm.c: Include hash-set.h, machmode.h, vec.h, double-int.h,
input.h, alias.h, symtab.h, options.h, fold-const.h,
wide-int.h, and inchash.h due to flattening of tree.h.
* java/builtins.c: ditto.
* java/class.c: ditto.
* java/constants.c: Include hash-set.h, machmode.h, vec.h, double-int.h,
input.h, alias.h, symtab.h, options.h, fold-const.h,
wide-int.h, and inchash.h due to flattening of tree.h.
* java/decl.c: ditto.
* java/except.c: Include hash-set.h, machmode.h, vec.h, double-int.h,
input.h, alias.h, symtab.h, fold-const.h,
wide-int.h, and inchash.h due to flattening of tree.h.
* java/expr.c: Include hash-set.h, machmode.h, vec.h, double-int.h,
input.h, alias.h, symtab.h, fold-const.h,
wide-int.h,inchash.h and real.h due to flattening of tree.h.
* java/gimplify.c: Include hash-set.h, machmode.h, vec.h, double-int.h,
input.h, alias.h, symtab.h, options.h, fold-const.h,
wide-int.h, and inchash.h due to flattening of tree.h.
* java/jcf-dump.c: ditto.
* java/jcf-io.c: ditto.
* java/jcf-parse.c: ditto.
* java/jvgenmain.c: ditto.
* java/lang.c: Include hash-set.h, machmode.h, vec.h, double-int.h,
input.h, alias.h, symtab.h, fold-const.h,
wide-int.h, and inchash.h due to flattening of tree.h.
* java/mangle.c: Include hash-set.h, machmode.h, vec.h, double-int.h,
input.h, alias.h, symtab.h, options.h, fold-const.h,
wide-int.h, and inchash.h due to flattening of tree.h.
* java/mangle_name.c: ditto.
* java/resource.c: ditto.
* java/typeck.c: ditto.
* java/verify-glue.c: ditto.
* java/verify-impl.c: ditto.
* jump.c: Include symtab.h due to flattening of tree.h.
* langhooks.c: Include hash-set.h, machmode.h, vec.h, double-int.h,
input.h, alias.h, symtab.h, fold-const.h,
wide-int.h, and inchash.h due to flattening of tree.h.
* loop-doloop.c: Include symtab.h due to flattening of tree.h.
* loop-init.c: Include hash-set.h, machmode.h, vec.h, double-int.h,
input.h, alias.h, symtab.h, fold-const.h,
wide-int.h, and inchash.h due to flattening of tree.h.
* loop-invariant.c: Include symtab.h due to flattening of tree.h.
* loop-iv.c: ditto.
* loop-unroll.c: Include hash-set.h, machmode.h, vec.h, double-int.h,
input.h, alias.h, symtab.h, fold-const.h,
wide-int.h, and inchash.h due to flattening of tree.h.
* lower-subreg.c: ditto.
* lra-assigns.c: Include symtab.h due to flattening of tree.h.
* lra.c: Include symtab.h, fold-const.h, wide-int.h and inchash.h
due to flattening of tree.h.
* lra-coalesce.c: Include symtab.h due to flattening of tree.h.
* lra-constraints.c: ditto.
* lra-eliminations.c: ditto.
* lra-livesc: ditto.
* lra-remat.c: ditto.
* lra-spills.c: ditto.
* lto/lto.c: Include hash-set.h, machmode.h, vec.h, double-int.h,
input.h, alias.h, symtab.h, options, fold-const.h,
wide-int.h, and inchash.h due to flattening of tree.h.
* lto/lto-lang.c: Include hash-set.h, machmode.h, vec.h, double-int.h,
input.h, alias.h, symtab.h, fold-const.h,
wide-int.h, and inchash.h due to flattening of tree.h.
* lto/lto-object.c: Include hash-set.h, machmode.h, vec.h, double-int.h,
input.h, alias.h, symtab.h, options, fold-const.h,
wide-int.h, and inchash.h due to flattening of tree.h.
* lto/lto-partition.c: ditto.
* lto/lto-symtab.c: ditto.
* lto-cgraph.c: Include hash-set.h, machmode.h, vec.h, double-int.h,
input.h, alias.h, symtab.h, fold-const.h,
wide-int.h, and inchash.h due to flattening of tree.h.
* lto-compress.c: Include hash-set.h, machmode.h, vec.h, double-int.h,
input.h, alias.h, symtab.h, options, fold-const.h,
wide-int.h, and inchash.h due to flattening of tree.h.
* lto-opts.c: ditto.
* lto-section-in.c: Include hash-set.h, machmode.h, vec.h, double-int.h,
input.h, alias.h, symtab.h, fold-const.h,
wide-int.h, and inchash.h due to flattening of tree.h.
* lto-section-out.c: ditto.
* lto-streamer.c: ditto.
* lto-streamer-in.c: ditto.
* lto-streamer-out.c: ditto.
* modulo-sched.c: Include hash-set.h, machmode.h, vec.h, double-int.h,
input.h, alias.h, symtab.h, fold-const.h, wide-int.h, and
inchash.h due to flattening of tree.h.
* objc/objc-act.c: Include hash-set.h, machmode.h, vec.h, double-int.h,
input.h, alias.h, symtab.h, options, fold-const.h,
wide-int.h, and inchash.h due to flattening of tree.h.
* objc/objc-encoding.c: ditto.
* objc/objc-gnu-runtime-abi-01.c: ditto.
* objc/objc-lang.c: ditto.
* objc/objc-map.c: ditto.
* objc/objc-next-runtime-abi-01.c: ditto.
* objc/objc-next-runtime-abi-02.c: ditto.
* objc/objc-runtime-shared-support.c: ditto.
* objcp/objcp-decl.c: ditto.
* objcp/objcp-lang.c: ditto.
* omega.c: ditto.
* omega-low.c: Include hash-set.h, machmode.h, vec.h, double-int.h,
input.h, alias.h, symtab.h, fold-const.h, wide-int.h, and
inchash.h due to flattening of tree.h.
* optabs.c: ditto.
* opts-global.c: ditto.
* passes.c: ditto.
* plugin.c: Include hash-set.h, machmode.h, vec.h, double-int.h,
input.h, alias.h, symtab.h, options.h, fold-const.h, wide-int.h, and
inchash.h due to flattening of tree.h.
* postreload.c: Include symtab.h due to flattening of tree.h.
* postreload-gcse.c: Include hash-set.h, machmode.h, vec.h, double-int.h,
input.h, alias.h, symtab.h, fold-const.h, wide-int.h, and
inchash.h due to flattening of tree.h.
* predict.c: ditto.
* print-rtl.c: ditto.
* print-tree.c: ditto.
* profile.c: Include symtab.h, fold-const.h
and inchash.h due to flattening of tree.h.
* real.c: Include hash-set.h, machmode.h, vec.h, double-int.h,
input.h, alias.h, symtab.h, fold-const.h, wide-int.h, and
inchash.h due to flattening of tree.h.
* realmpfr.c: Include hash-set.h, machmode.h, vec.h, double-int.h,
input.h, alias.h, symtab.h, options.h, fold-const.h, wide-int.h, and
inchash.h due to flattening of tree.h.
* recog.c: Include hash-set.h, machmode.h, vec.h, double-int.h,
input.h, alias.h, symtab.h, fold-const.h, wide-int.h, and
inchash.h due to flattening of tree.h.
* ree.c: ditto.
* reginfo.c: ditto.
* reg-stack.c: ditto.
* reload1.c: Include symtab.h, fold-const.h, wide-int.h
and inchash.h due to flattening of tree.h.
* reload.c: Include symtab.h due to flattening of tree.h.
* reorg.c: ditto.
* rtlanal.c: Include symtab.h, fold-const.h, wide-int.h
and inchash.h due to flattening of tree.h.
* rtl-chkp.c: Include hash-set.h, machmode.h, vec.h, double-int.h,
input.h, alias.h, symtab.h, fold-const.h, wide-int.h, and
inchash.h due to flattening of tree.h.
* rtlhooks.c: Include symtab.h due to flattening of tree.h.
* sanopt.c: Include hash-set.h, machmode.h, vec.h, double-int.h,
input.h, alias.h, symtab.h, options.h, fold-const.h, wide-int.h, and
inchash.h due to flattening of tree.h.
* sched-deps.c: Include hash-set.h, machmode.h, vec.h, double-int.h,
input.h, alias.h, symtab.h, options.h, fold-const.h, wide-int.h, and
inchash.h due to flattening of tree.h.
* sched-vis.c: ditto.
* sdbout.c: ditto.
* sel-sched.c: Include symtab.h, fold-const.h, wide-int.h
and inchash.h due to flattening of tree.h.
* sel-sched-ir.c: ditto.
* sese.c: Include hash-set.h, machmode.h, vec.h, double-int.h,
input.h, alias.h, symtab.h, options.h, fold-const.h, wide-int.h, and
inchash.h due to flattening of tree.h.
* shrink-wrap.c: Include hash-set.h, machmode.h, vec.h, double-int.h,
input.h, alias.h, symtab.h, options.h, fold-const.h, wide-int.h, and
inchash.h due to flattening of tree.h.
* simplify-rtx.c: Include hash-set.h, machmode.h, vec.h, double-int.h,
input.h, alias.h, symtab.h, options.h, fold-const.h, wide-int.h, and
inchash.h due to flattening of tree.h.
* stack-ptr-mod.c: ditto.
* stmt.c: ditto.
* store-motion.c: ditto.
* store-layout.c: ditto.
* stringpool.c: ditto.
* symtab.c: ditto.
* target-globals.c: ditto.
* targhooks.c: ditto.
* toplev.c: ditto.
* tracer.c: ditto.
* trans-mem.c: Include hash-set.h, machmode.h, vec.h, double-int.h,
input.h, alias.h, symtab.h, options.h, fold-const.h, wide-int.h, and
inchash.h due to flattening of tree.h.
* tree-affine.c: ditto.
* tree-browser.c: ditto.
* tree.c: Include hash-set.h, machmode.h, vec.h, double-int.h,
input.h, alias.h, symtab.h, options.h, fold-const.h, wide-int.h, and
inchash.h due to flattening of tree.h.
* tree-call-cdce.c: Include symtab.h, alias.h, double-int.h,
fold-const.h, wide-int.h, inchash.h and real.h due to
flattening of tree.h.
* tree-cfg.c: Include hash-set.h, machmode.h, vec.h, double-int.h,
input.h, alias.h, symtab.h, fold-const.h, wide-int.h, and
inchash.h due to flattening of tree.h.
* tree-cfgcleanup.c: ditto.
* tree-chkp.c: Include hash-set.h, machmode.h, vec.h, double-int.h,
input.h, alias.h, symtab.h, options.h, fold-const.h, wide-int.h, and
inchash.h due to flattening of tree.h.
* tree-chkp-opt.c: ditto.
* tree-chrec.c: ditto.
* tree-chkp-opt.c: Include hash-set.h, machmode.h, vec.h, double-int.h,
input.h, alias.h, symtab.h, fold-const.h, wide-int.h, inchash.h and
real.h due to flattening of tree.h.
* tree-core.h: Flatten header file by removing all #include statements.
* tree-data-ref.c: Include hash-set.h, machmode.h, vec.h, double-int.h,
input.h, alias.h, symtab.h, options.h, fold-const.h, wide-int.h, and
inchash.h due to flattening of tree.h.
* tree-dfa.c: Include hash-set.h, machmode.h, vec.h, double-int.h,
input.h, alias.h, symtab.h, fold-const.h, wide-int.h, inchash.h and
real.h due to flattening of tree.h.
* tree-diagnostic.c: ditto.
* tree-dump.c: Include hash-set.h, machmode.h, vec.h, double-int.h,
input.h, alias.h, symtab.h, fold-const.h, wide-int.h, inchash.h, real.h and
fixed-value.h due to flattening of tree.h.
* tree-dfa.c: ditto.
* tree-eh.c: Include hash-set.h, machmode.h, vec.h, double-int.h,
input.h, alias.h, symtab.h, fold-const.h, wide-int.h, inchash.h and
real.h due to flattening of tree.h.
* tree-emutls.c: Include hash-set.h, machmode.h, vec.h, double-int.h,
input.h, alias.h, symtab.h, options.h, fold-const.h, wide-int.h, and
inchash.h due to flattening of tree.h.
* tree.h: Flatten header files by removing all includes except tree-core.h.
Remove inline function convert_to_ptrofftype_loc to relocate to fold-const.c.
Remove macro convert_to_ptrofftype to relocate to fold-const.h.
Remove inline function fold_build_pointer_plus_loc to relocate to fold-const.c.
Remove macro fold_build_pointer_plus to relocate to fold-const.h.
Remove inline function fold_build_pointer_plus_hwi_loc to relocate to fold-const.c.
Remove macro fold_build_pointer_plus_hwi to relocate to fold-const.h.
* tree-if-conv.c: Include hash-set.h, machmode.h, vec.h, double-int.h,
input.h, alias.h, symtab.h, fold-const.h, wide-int.h, inchash.h, real.h and
fixed-value.h due to flattening of tree.h.
* tree-inline.c: ditto.
* tree-into-ssa.c: ditto.
* tree-iterator.c: Include hash-set.h, machmode.h, vec.h, double-int.h,
input.h, alias.h, symtab.h, options.h, fold-const.h, wide-int.h, and
inchash.h due to flattening of tree.h.
* tree-loop-distribution.c: ditto.
* tree-nested.c: Include hash-set.h, machmode.h, vec.h, double-int.h,
input.h, alias.h, symtab.h, fold-const.h, wide-int.h and inchash.h
due to flattening of tree.h.
* tree-nrv.c: ditto.
* tree-object-size.c: ditto.
* tree-outof-ssa.c: ditto.
* tree-parloops.c: Include hash-set.h, machmode.h, vec.h, double-int.h,
input.h, alias.h, symtab.h, options.h, fold-const.h, wide-int.h, and
inchash.h due to flattening of tree.h.
* tree-phinodes.c: ditto.
* tree-predcom.c: Include hash-set.h, machmode.h, vec.h, double-int.h,
input.h, alias.h, symtab.h, fold-const.h, wide-int.h and inchash.h
due to flattening of tree.h.
* tree-pretty-print.c: ditto.
* tree-profile.c: double-int.h, input.h, alias.h, symtab.h,
fold-const.h, wide-int.h and inchash.h due to flattening of tree.h.
* tree-scalar-evolution.c: Include hash-set.h, machmode.h, vec.h,
double-int.h, input.h, alias.h, symtab.h, options.h, fold-const.h,
wide-int.h and inchash.h due to flattening of tree.h.
* tree-sra.c: Include vec.h, double-int.h,
input.h, alias.h, symtab.h, fold-const.h, wide-int.h, and
inchash.h due to flattening of tree.h.
* tree-ssa-alias.c: Include hash-set.h, machmode.h, vec.h, double-int.h,
input.h, alias.h, symtab.h, fold-const.h, wide-int.h and inchash.h
due to flattening of tree.h.
* tree-ssa.c: ditto.
* tree-ssa-ccp.c: Include hash-set.h, machmode.h, vec.h, double-int.h,
input.h, alias.h, symtab.h, fold-const.h, wide-int.h, inchash.h
and real.h due to flattening of tree.h.
* tree-ssa-coalesce.c: Include hash-set.h, machmode.h, vec.h, double-int.h,
input.h, alias.h, symtab.h, fold-const.h, wide-int.h and inchash.h
due to flattening of tree.h.
* tree-ssa-copy.c: ditto.
* tree-ssa-copyrename.c: ditto.
* tree-ssa-dce.c: ditto.
* tree-ssa-dom.c: Include hash-set.h, machmode.h, vec.h, double-int.h,
input.h, alias.h, symtab.h, fold-const.h, wide-int.h, inchash.h
and real.h due to flattening of tree.h.
* tree-ssa-dse.c: Include hash-set.h, machmode.h, vec.h, double-int.h,
input.h, alias.h, symtab.h, fold-const.h, wide-int.h and inchash.h
due to flattening of tree.h.
* tree-ssa-forwprop.c: ditto.
* tree-ssa-ifcombine.c: ditto.
* tree-ssa-live.c: ditto.
* tree-ssa-loop.c: ditto.
* tree-ssa-loop-ch.c: ditto.
* tree-ssa-loop-im.c: ditto.
* tree-ssa-loop-ivcanon.c: ditto.
* tree-ssa-loop-ivopts.c: ditto.
* tree-ssa-loop-manip.c: ditto.
* tree-ssa-loop-niter.c: ditto.
* tree-ssa-loop-prefetch.c: ditto.
* tree-ssa-loop-unswitch.c: ditto.
* tree-ssa-loop-math-opts.c: ditto.
* tree-ssanames.c: ditto.
* tree-ssa-operands.c: ditto.
* tree-ssa-phiopt.c: ditto.
* tree-ssa-phiprop.c: ditto.
* tree-ssa-pre.c: ditto.
* tree-ssa-propagate.c: ditto.
* tree-ssa-reassoc.c: ditto.
* tree-ssa-sccvn.c: ditto.
* tree-ssa-sink.c: ditto.
* tree-ssa-strlen.c: Include hash-set.h, machmode.h, vec.h,
double-int.h, input.h, alias.h, symtab.h, options.h, fold-const.h,
wide-int.h and inchash.h due to flattening of tree.h.
* tree-ssa-structalias.c: double-int.h, input.h, alias.h, symtab.h,
fold-const.h, wide-int.h and inchash.h due to flattening of tree.h.
* tree-ssa-tail-merge.c: Include hash-set.h, machmode.h, vec.h,
double-int.h, input.h, alias.h, symtab.h, fold-const.h,
wide-int.h and inchash.h due to flattening of tree.h.
* tree-ssa-ter.c: ditto.
* tree-ssa-threadedge.c: ditto.
* tree-ssa-threadupdate.c: Include hash-set.h, machmode.h, vec.h,
double-int.h, input.h, alias.h, symtab.h, options.h, fold-const.h,
wide-int.h and inchash.h due to flattening of tree.h.
* tree-ssa-uncprop.c: Include hash-set.h, machmode.h, vec.h,
double-int.h, input.h, alias.h, symtab.h, fold-const.h,
wide-int.h and inchash.h due to flattening of tree.h.
* tree-ssa-uninit.c: ditto.
* tree-stdarg.c: Include vec.h, double-int.h, input.h, alias.h,
symtab.h, fold-const.h, wide-int.h and inchash.h due to flattening
of tree.h.
* tree-streamer.c: Include vec.h, double-int.h, input.h, alias.h,
symtab.h, options.h, fold-const.h, wide-int.h and
inchash.h due to flattening of tree.h.
* tree-streamer-in.c: Include hash-set.h, machmode.h, vec.h,
double-int.h, input.h, alias.h, symtab.h, options.h, fold-const.h,
wide-int.h, inchash.h, real.h and fixed-value.h due to flattening
of tree.h.
* tree-streamer-out.c: dittoo.
* tree-switch-conversion.c: Include hash-set.h, machmode.h, vec.h, double-int.h,
input.h, alias.h, symtab.h, fold-const.h, wide-int.h and inchash.h
due to flattening of tree.h.
* tree-tailcall.c: ditto.
* tree-vect-data-refs.c: ditto.
* tree-vect-generic.c: Include hash-set.h, machmode.h, vec.h, double-int.h, input.h,
alias.h, symtab.h, options.h, fold-const.h, wide-int.h and inchash.h
due to flattening of tree.h.
* tree-vect-loop.c: Include hash-set.h, machmode.h, vec.h, double-int.h,
input.h, alias.h, symtab.h, fold-const.h, wide-int.h and inchash.h
due to flattening of tree.h.
* tree-vect-loop-manip.c: ditto.
* tree-vectorizer.c: ditto.
* tree-vect-patterns.c: ditto.
* tree-vect-slp.c: ditto.
* tree-vect-stmts.c: ditto.
* tree-vrp.c: ditto.
* tsan.c: Include hash-set.h, machmode.h, vec.h, double-int.h,
input.h, alias.h, symtab.h, options.h, fold-const.h, wide-int.h and inchash.h
due to flattening of tree.h.
* ubsan.c: ditto.
* value-prof.c.c: Include hash-set.h, machmode.h, vec.h, double-int.h,
input.h, alias.h, symtab.h, fold-const.h, wide-int.h and inchash.h
due to flattening of tree.h.
* varasm.c: ditto.
* varpool.c: ditto.
* var-tracking.c: ditto.
* vmsdbgout.c: ditto.
* vtable-verify.c: Include hash-set.h, machmode.h, vec.h, double-int.h,
input.h, alias.h, symtab.h, options.h, fold-const.h, wide-int.h and inchash.h
due to flattening of tree.h.
* wide-int.cc: Include hash-set.h, machmode.h, vec.h, double-int.h,
input.h, alias.h, symtab.h, fold-const.h, wide-int.h and inchash.h
due to flattening of tree.h.
* xcoffout.c: ditto.
* libcc1/plugin.cc: Include hash-set.h, machmode.h, vec.h, double-int.h,
input.h, alias.h, symtab.h, options.h, fold-const.h, wide-int.h and inchash.h
due to flattening of tree.h.
From-SVN: r219402
2015-01-09 21:18:42 +01:00
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#include "fold-const.h"
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2013-11-19 13:31:09 +01:00
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#include "stor-layout.h"
|
dojump.h: New header file.
2015-10-15 Prathamesh Kulkarni <prathamesh.kulkarni@linaro.org>
* dojump.h: New header file.
* explow.h: Likewise.
* expr.h: Remove includes.
Move expmed.c prototypes to expmed.h.
Move dojump.c prototypes to dojump.h.
Move alias.c prototypes to alias.h.
Move explow.c prototypes to explow.h.
Move calls.c prototypes to calls.h.
Move emit-rtl.c prototypes to emit-rtl.h.
Move varasm.c prototypes to varasm.h.
Move stmt.c prototypes to stmt.h.
(saved_pending_stack_adjust): Move to dojump.h.
(adjust_address): Move to explow.h.
(adjust_address_nv): Move to emit-rtl.h.
(adjust_bitfield_address): Likewise.
(adjust_bitfield_address_size): Likewise.
(adjust_bitfield_address_nv): Likewise.
(adjust_automodify_address_nv): Likewise.
* explow.c (expr_size): Move to expr.c.
(int_expr_size): Likewise.
(tree_expr_size): Likewise.
Include calls.h dojump.h emit-rtl.h explow.h expmed.h
fixed-value.h hashtab.h statistics.h stmt.h varasm.h.
* genemit.c (main): Generate includes statistics.h, real.h, fixed-value.h,
insn-config.h, expmed.h, dojump.h, explow.h, emit-rtl.h, stmt.h.
* genopinit.c (main): Generate includes hashtab.h, hard-reg-set.h, function.h,
statistics.h, real.h, fixed-value.h, expmed.h, dojump.h, explow.h, emit-rtl.h,
stmt.h.
* genoutput.c (main): Generate includes hashtab.h, statistics.h, real.h,
fixed-value.h, expmed.h, dojump.h, explow.h, emit-rtl.h, stmt.h.
* genemit.c (open_base_files): Generate includes flags.h, statistics.h, real.h,
fixed-value.h, tree.h, expmed.h, dojump.h, explow.h, calls.h, emit-rtl.h, varasm.h,
stmt.h.
* config/tilepro/gen-mul-tables.cc: Generate includes hashtab.h, hash-set.h, vec.h,
machmode.h, tm.h, hard-reg-set.h, input.h, function.h, rtl.h, flags.h, statistics.h,
double-int.h, real.h, fixed-value.h, alias.h, wide-int.h, inchash.h, tree.h,
insn-config.h, expmed.h, dojump.h, explow.h, calls.h, emit-rtl.h, varasm.h, stmt.h.
* config/tilegx/mul-tables.c: Include alias.h calls.h dojump.h
double-int.h emit-rtl.h explow.h expmed.h fixed-value.h flags.h
function.h hard-reg-set.h hash-set.h hashtab.h inchash.h input.h
insn-config.h machmode.h real.h rtl.h statistics.h stmt.h symtab.h
tm.h tree.h varasm.h vec.h wide-int.h.
* rtlhooks.c: Include alias.h calls.h dojump.h double-int.h emit-rtl.h
explow.h expmed.h fixed-value.h flags.h function.h hard-reg-set.h
hash-set.h hashtab.h inchash.h input.h insn-config.h machmode.h
real.h statistics.h stmt.h tree.h varasm.h vec.h wide-int.h.
* cfgloopanal.c: Include alias.h calls.h dojump.h double-int.h emit-rtl.h
explow.h expmed.h fixed-value.h flags.h inchash.h insn-config.h
real.h statistics.h stmt.h tree.h varasm.h wide-int.h.
* loop-iv.c: Likewise.
* lra-assigns.c: Include alias.h calls.h dojump.h double-int.h emit-rtl.h
explow.h expmed.h fixed-value.h flags.h inchash.h real.h
statistics.h stmt.h tree.h varasm.h wide-int.h.
* lra-constraints.c: Likewise.
* lra-eliminations.c: Likewise.
* lra-lives.c: Likewise.
* lra-remat.c: Likewise.
* bt-load.c: Include alias.h calls.h dojump.h double-int.h emit-rtl.h
explow.h expmed.h fixed-value.h inchash.h insn-config.h real.h
statistics.h stmt.h tree.h varasm.h wide-int.h.
* hw-doloop.c: Likewise.
* ira-color.c: Likewise.
* ira-emit.c: Likewise.
* loop-doloop.c: Likewise.
* loop-invariant.c: Likewise.
* reload.c: Include alias.h calls.h dojump.h double-int.h emit-rtl.h
explow.h expmed.h fixed-value.h inchash.h real.h rtl.h
statistics.h stmt.h tree.h varasm.h wide-int.h.
* caller-save.c: Include alias.h calls.h dojump.h double-int.h emit-rtl.h
explow.h expmed.h fixed-value.h inchash.h real.h statistics.h
stmt.h tree.h varasm.h wide-int.h.
* combine-stack-adj.c: Likewise.
* cse.c: Likewise.
* ddg.c: Likewise.
* ifcvt.c: Likewise.
* ira-costs.c: Likewise.
* jump.c: Likewise.
* lra-coalesce.c: Likewise.
* lra-spills.c: Likewise.
* profile.c: Include alias.h calls.h dojump.h double-int.h emit-rtl.h
explow.h expmed.h fixed-value.h insn-config.h real.h statistics.h
stmt.h varasm.h wide-int.h.
* lra.c: Include alias.h calls.h dojump.h double-int.h emit-rtl.h
explow.h expmed.h fixed-value.h real.h statistics.h stmt.h
varasm.h.
* config/sh/sh_treg_combine.cc: Include alias.h calls.h dojump.h
double-int.h explow.h expmed.h fixed-value.h flags.h real.h
statistics.h stmt.h varasm.h wide-int.h.
* reorg.c: Include alias.h calls.h dojump.h double-int.h explow.h
expmed.h fixed-value.h inchash.h real.h statistics.h stmt.h tree.h
varasm.h wide-int.h.
* reload1.c: Include alias.h calls.h dojump.h double-int.h explow.h
expmed.h fixed-value.h real.h rtl.h statistics.h stmt.h varasm.h.
* config/tilegx/tilegx.c: Include alias.h dojump.h double-int.h
emit-rtl.h explow.h expmed.h fixed-value.h flags.h real.h
statistics.h stmt.h.
* config/tilepro/tilepro.c: Likewise.
* config/mmix/mmix.c: Include alias.h dojump.h double-int.h emit-rtl.h
explow.h expmed.h fixed-value.h real.h statistics.h stmt.h.
* config/pdp11/pdp11.c: Likewise.
* config/xtensa/xtensa.c: Likewise.
* config/lm32/lm32.c: Include alias.h dojump.h double-int.h emit-rtl.h
explow.h expmed.h fixed-value.h real.h statistics.h stmt.h
varasm.h.
* tree-chkp.c: Include calls.h dojump.h emit-rtl.h explow.h expmed.h
fixed-value.h flags.h function.h hard-reg-set.h hashtab.h
insn-config.h real.h rtl.h statistics.h stmt.h tm.h.
* cilk-common.c: Include calls.h dojump.h emit-rtl.h explow.h expmed.h
fixed-value.h flags.h function.h hard-reg-set.h hashtab.h
insn-config.h real.h rtl.h statistics.h stmt.h tm.h varasm.h.
* rtl-chkp.c: Likewise.
* tree-chkp-opt.c: Likewise.
* config/arm/arm-builtins.c: Include calls.h dojump.h emit-rtl.h explow.h
expmed.h fixed-value.h flags.h function.h hard-reg-set.h hashtab.h
insn-config.h real.h statistics.h stmt.h varasm.h.
* ipa-icf.c: Include calls.h dojump.h emit-rtl.h explow.h expmed.h
fixed-value.h flags.h hashtab.h insn-config.h real.h rtl.h
statistics.h stmt.h.
* tree-vect-data-refs.c: Likewise.
* graphite-sese-to-poly.c: Include calls.h dojump.h emit-rtl.h explow.h
expmed.h fixed-value.h flags.h hashtab.h insn-config.h real.h
rtl.h statistics.h stmt.h varasm.h.
* internal-fn.c: Likewise.
* ipa-icf-gimple.c: Likewise.
* lto-section-out.c: Likewise.
* tree-data-ref.c: Likewise.
* tree-nested.c: Likewise.
* tree-outof-ssa.c: Likewise.
* tree-predcom.c: Likewise.
* tree-pretty-print.c: Likewise.
* tree-scalar-evolution.c: Likewise.
* tree-ssa-strlen.c: Likewise.
* tree-vect-loop.c: Likewise.
* tree-vect-patterns.c: Likewise.
* tree-vect-slp.c: Likewise.
* tree-vect-stmts.c: Likewise.
* tsan.c: Likewise.
* targhooks.c: Include calls.h dojump.h emit-rtl.h explow.h expmed.h
fixed-value.h flags.h hashtab.h insn-config.h real.h statistics.h
stmt.h.
* config/sh/sh-mem.cc: Include calls.h dojump.h emit-rtl.h explow.h
expmed.h fixed-value.h flags.h hashtab.h insn-config.h real.h
statistics.h stmt.h varasm.h.
* loop-unroll.c: Likewise.
* ubsan.c: Likewise.
* tree-ssa-loop-prefetch.c: Include calls.h dojump.h emit-rtl.h explow.h
expmed.h fixed-value.h flags.h hashtab.h real.h rtl.h statistics.h
stmt.h varasm.h.
* dse.c: Include calls.h dojump.h emit-rtl.h explow.h expmed.h
fixed-value.h function.h hashtab.h statistics.h stmt.h varasm.h.
* tree-switch-conversion.c: Include calls.h dojump.h emit-rtl.h explow.h
expmed.h fixed-value.h hashtab.h insn-config.h real.h rtl.h
statistics.h stmt.h.
* generic-match-head.c: Include calls.h dojump.h emit-rtl.h explow.h
expmed.h fixed-value.h hashtab.h insn-config.h real.h rtl.h
statistics.h stmt.h varasm.h.
* gimple-match-head.c: Likewise.
* lto-cgraph.c: Likewise.
* lto-section-in.c: Likewise.
* lto-streamer-in.c: Likewise.
* lto-streamer-out.c: Likewise.
* tree-affine.c: Likewise.
* tree-cfg.c: Likewise.
* tree-cfgcleanup.c: Likewise.
* tree-if-conv.c: Likewise.
* tree-into-ssa.c: Likewise.
* tree-ssa-alias.c: Likewise.
* tree-ssa-copyrename.c: Likewise.
* tree-ssa-dse.c: Likewise.
* tree-ssa-forwprop.c: Likewise.
* tree-ssa-live.c: Likewise.
* tree-ssa-math-opts.c: Likewise.
* tree-ssa-pre.c: Likewise.
* tree-ssa-sccvn.c: Likewise.
* tree-tailcall.c: Likewise.
* tree-vect-generic.c: Likewise.
* tree-sra.c: Include calls.h dojump.h emit-rtl.h explow.h expmed.h
fixed-value.h hashtab.h insn-config.h real.h rtl.h stmt.h varasm.h.
* stor-layout.c: Include calls.h dojump.h emit-rtl.h explow.h expmed.h
fixed-value.h hashtab.h insn-config.h real.h statistics.h stmt.h.
* varasm.c: Likewise.
* coverage.c: Include calls.h dojump.h emit-rtl.h explow.h expmed.h
fixed-value.h hashtab.h insn-config.h real.h statistics.h stmt.h
varasm.h.
* init-regs.c: Likewise.
* ira.c: Likewise.
* omp-low.c: Likewise.
* stack-ptr-mod.c: Likewise.
* tree-ssa-reassoc.c: Likewise.
* tree-complex.c: Include calls.h dojump.h emit-rtl.h explow.h expmed.h
fixed-value.h hashtab.h insn-config.h rtl.h statistics.h stmt.h
varasm.h.
* dwarf2cfi.c: Include calls.h dojump.h emit-rtl.h explow.h expmed.h
fixed-value.h hashtab.h insn-config.h statistics.h stmt.h varasm.h.
* shrink-wrap.c: Include calls.h dojump.h emit-rtl.h explow.h expmed.h
fixed-value.h hashtab.h real.h rtl.h statistics.h stmt.h.
* recog.c: Include calls.h dojump.h emit-rtl.h explow.h expmed.h
fixed-value.h hashtab.h real.h rtl.h statistics.h stmt.h varasm.h.
* tree-ssa-phiopt.c: Likewise.
* config/darwin.c: Include calls.h dojump.h emit-rtl.h explow.h expmed.h
fixed-value.h hashtab.h real.h statistics.h stmt.h.
* config/fr30/fr30.c: Likewise.
* config/frv/frv.c: Likewise.
* expr.c: Likewise.
* final.c: Likewise.
* optabs.c: Likewise.
* passes.c: Likewise.
* simplify-rtx.c: Likewise.
* stmt.c: Likewise.
* toplev.c: Likewise.
* var-tracking.c: Likewise.
* gcse.c: Include calls.h dojump.h emit-rtl.h explow.h expmed.h
fixed-value.h hashtab.h real.h statistics.h stmt.h varasm.h.
* lower-subreg.c: Likewise.
* postreload-gcse.c: Likewise.
* ree.c: Likewise.
* reginfo.c: Likewise.
* store-motion.c: Likewise.
* combine.c: Include calls.h dojump.h emit-rtl.h explow.h expmed.h
fixed-value.h hashtab.h real.h stmt.h varasm.h.
* emit-rtl.c: Include calls.h dojump.h emit-rtl.h explow.h expmed.h
fixed-value.h hashtab.h statistics.h stmt.h.
* dojump.c: Include calls.h dojump.h emit-rtl.h explow.h expmed.h
fixed-value.h hashtab.h statistics.h stmt.h varasm.h.
* except.c: Likewise.
* explow.c: Likewise.
* tree-dfa.c: Include calls.h dojump.h emit-rtl.h explow.h expmed.h
fixed-value.h insn-config.h real.h rtl.h statistics.h stmt.h
varasm.h.
* gimple-fold.c: Include calls.h dojump.h emit-rtl.h explow.h expmed.h
fixed-value.h insn-config.h real.h rtl.h statistics.h varasm.h.
* tree-ssa-structalias.c: Likewise.
* cfgexpand.c: Include calls.h dojump.h emit-rtl.h explow.h expmed.h
fixed-value.h insn-config.h real.h statistics.h.
* calls.c: Include calls.h dojump.h emit-rtl.h explow.h expmed.h
fixed-value.h insn-config.h real.h statistics.h stmt.h.
* bb-reorder.c: Include calls.h dojump.h emit-rtl.h explow.h expmed.h
fixed-value.h insn-config.h real.h statistics.h stmt.h varasm.h.
* cfgbuild.c: Likewise.
* function.c: Include calls.h dojump.h emit-rtl.h explow.h expmed.h
fixed-value.h real.h rtl.h statistics.h stmt.h.
* cfgrtl.c: Include calls.h dojump.h emit-rtl.h explow.h expmed.h
fixed-value.h real.h rtl.h statistics.h stmt.h varasm.h.
* dbxout.c: Include calls.h dojump.h emit-rtl.h explow.h expmed.h
fixed-value.h real.h statistics.h stmt.h.
* auto-inc-dec.c: Include calls.h dojump.h emit-rtl.h explow.h expmed.h
fixed-value.h real.h statistics.h stmt.h varasm.h.
* cprop.c: Likewise.
* modulo-sched.c: Likewise.
* postreload.c: Likewise.
* ccmp.c: Include calls.h dojump.h emit-rtl.h explow.h fixed-value.h
flags.h function.h hard-reg-set.h hashtab.h insn-config.h real.h
statistics.h stmt.h varasm.h.
* gimple-ssa-strength-reduction.c: Include calls.h dojump.h emit-rtl.h
explow.h fixed-value.h flags.h hashtab.h insn-config.h real.h
rtl.h statistics.h stmt.h varasm.h.
* tree-ssa-loop-ivopts.c: Include calls.h dojump.h emit-rtl.h explow.h
fixed-value.h flags.h hashtab.h real.h rtl.h statistics.h stmt.h
varasm.h.
* expmed.c: Include calls.h dojump.h emit-rtl.h explow.h fixed-value.h
function.h hard-reg-set.h hashtab.h real.h statistics.h stmt.h
varasm.h.
* target-globals.c: Include calls.h dojump.h emit-rtl.h explow.h
fixed-value.h function.h hashtab.h real.h statistics.h stmt.h
varasm.h.
* tree-ssa-address.c: Include calls.h dojump.h emit-rtl.h explow.h
fixed-value.h hashtab.h real.h statistics.h stmt.h varasm.h.
* cfgcleanup.c: Include calls.h dojump.h explow.h expmed.h fixed-value.h
function.h real.h statistics.h stmt.h varasm.h.
* alias.c: Include calls.h dojump.h explow.h expmed.h fixed-value.h
insn-config.h real.h statistics.h stmt.h.
* dwarf2out.c: Include calls.h dojump.h explow.h expmed.h fixed-value.h
statistics.h stmt.h.
* config/nvptx/nvptx.c: Include dojump.h emit-rtl.h explow.h expmed.h
fixed-value.h flags.h hard-reg-set.h insn-config.h real.h
statistics.h stmt.h varasm.h.
* gimplify.c: Include dojump.h emit-rtl.h explow.h expmed.h fixed-value.h
flags.h hashtab.h insn-config.h real.h rtl.h statistics.h.
* asan.c: Include dojump.h emit-rtl.h explow.h expmed.h fixed-value.h
flags.h hashtab.h insn-config.h real.h rtl.h statistics.h stmt.h.
* ipa-devirt.c: Include dojump.h emit-rtl.h explow.h expmed.h
fixed-value.h flags.h hashtab.h insn-config.h real.h rtl.h
statistics.h stmt.h varasm.h.
* ipa-polymorphic-call.c: Likewise.
* config/aarch64/aarch64.c: Include dojump.h emit-rtl.h explow.h expmed.h
fixed-value.h flags.h hashtab.h insn-config.h real.h statistics.h
stmt.h.
* config/c6x/c6x.c: Likewise.
* config/aarch64/aarch64-builtins.c: Include dojump.h emit-rtl.h explow.h
expmed.h fixed-value.h flags.h hashtab.h insn-config.h real.h
statistics.h stmt.h varasm.h.
* ipa-prop.c: Include dojump.h emit-rtl.h explow.h expmed.h fixed-value.h
hashtab.h insn-config.h real.h rtl.h statistics.h stmt.h varasm.h.
* ipa-split.c: Likewise.
* tree-eh.c: Likewise.
* tree-ssa-dce.c: Likewise.
* tree-ssa-loop-niter.c: Likewise.
* tree-vrp.c: Likewise.
* config/nds32/nds32-cost.c: Include dojump.h emit-rtl.h explow.h
expmed.h fixed-value.h hashtab.h insn-config.h real.h statistics.h
stmt.h.
* config/nds32/nds32-fp-as-gp.c: Likewise.
* config/nds32/nds32-intrinsic.c: Likewise.
* config/nds32/nds32-isr.c: Likewise.
* config/nds32/nds32-md-auxiliary.c: Likewise.
* config/nds32/nds32-memory-manipulation.c: Likewise.
* config/nds32/nds32-pipelines-auxiliary.c: Likewise.
* config/nds32/nds32-predicates.c: Likewise.
* config/nds32/nds32.c: Likewise.
* config/cris/cris.c: Include dojump.h emit-rtl.h explow.h expmed.h
fixed-value.h hashtab.h real.h statistics.h.
* config/alpha/alpha.c: Include dojump.h emit-rtl.h explow.h expmed.h
fixed-value.h hashtab.h real.h statistics.h stmt.h.
* config/arm/arm.c: Likewise.
* config/avr/avr.c: Likewise.
* config/bfin/bfin.c: Likewise.
* config/h8300/h8300.c: Likewise.
* config/i386/i386.c: Likewise.
* config/ia64/ia64.c: Likewise.
* config/iq2000/iq2000.c: Likewise.
* config/m32c/m32c.c: Likewise.
* config/m32r/m32r.c: Likewise.
* config/m68k/m68k.c: Likewise.
* config/mcore/mcore.c: Likewise.
* config/mep/mep.c: Likewise.
* config/mips/mips.c: Likewise.
* config/mn10300/mn10300.c: Likewise.
* config/moxie/moxie.c: Likewise.
* config/pa/pa.c: Likewise.
* config/rl78/rl78.c: Likewise.
* config/rx/rx.c: Likewise.
* config/s390/s390.c: Likewise.
* config/sh/sh.c: Likewise.
* config/sparc/sparc.c: Likewise.
* config/spu/spu.c: Likewise.
* config/stormy16/stormy16.c: Likewise.
* config/v850/v850.c: Likewise.
* config/vax/vax.c: Likewise.
* config/cr16/cr16.c: Include dojump.h emit-rtl.h explow.h expmed.h
fixed-value.h hashtab.h real.h statistics.h stmt.h varasm.h.
* config/msp430/msp430.c: Likewise.
* predict.c: Likewise.
* value-prof.c: Likewise.
* config/epiphany/epiphany.c: Include dojump.h emit-rtl.h explow.h
expmed.h fixed-value.h hashtab.h statistics.h stmt.h.
* config/microblaze/microblaze.c: Likewise.
* config/nios2/nios2.c: Likewise.
* config/rs6000/rs6000.c: Likewise.
* tree.c: Include dojump.h emit-rtl.h explow.h expmed.h fixed-value.h
insn-config.h real.h rtl.h statistics.h stmt.h.
* cgraph.c: Include dojump.h emit-rtl.h explow.h expmed.h fixed-value.h
insn-config.h real.h statistics.h stmt.h.
* fold-const.c: Include dojump.h emit-rtl.h explow.h expmed.h
fixed-value.h insn-config.h real.h statistics.h stmt.h varasm.h.
* tree-inline.c: Include dojump.h emit-rtl.h explow.h expmed.h
fixed-value.h real.h rtl.h statistics.h stmt.h varasm.h.
* builtins.c: Include dojump.h emit-rtl.h explow.h expmed.h fixed-value.h
real.h statistics.h stmt.h.
* config/arc/arc.c: Include dojump.h emit-rtl.h explow.h expmed.h
fixed-value.h statistics.h stmt.h.
* config/visium/visium.c: Include dojump.h emit-rtl.h explow.h expmed.h
stmt.h.
java/
* builtins.c: Include calls.h dojump.h emit-rtl.h explow.h expmed.h
fixed-value.h function.h hard-reg-set.h hashtab.h insn-config.h
real.h statistics.h stmt.h varasm.h.
From-SVN: r219655
2015-01-15 14:28:42 +01:00
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#include "explow.h"
|
2012-10-23 19:02:30 +02:00
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|
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#include "expr.h"
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|
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#include "langhooks.h"
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gimple-walk.h: New File.
* gimple-walk.h: New File. Relocate prototypes from gimple.h.
(struct walk_stmt_info): Relocate here from gimple.h.
* gimple-iterator.h: New File. Relocate prototypes from gimple.h.
(struct gimple_stmt_iterator_d): Relocate here from gimple.h.
(gsi_start_1, gsi_none, gsi_start_bb, gsi_last_1, gsi_last_bb,
gsi_end_p, gsi_one_before_end_p, gsi_next, gsi_prev, gsi_stmt,
gsi_after_labels, gsi_next_nondebug, gsi_prev_nondebug,
gsi_start_nondebug_bb, gsi_start_nondebug_after_labels_bb,
gsi_last_nondebug_bb, gsi_bb, gsi_seq): Relocate here from gimple.h.
* gimple.h (struct gimple_stmt_iterator_d): Move to gimple-iterator.h.
(gsi_start_1, gsi_none, gsi_start_bb, gsi_last_1, gsi_last_bb,
gsi_end_p, gsi_one_before_end_p, gsi_next, gsi_prev, gsi_stmt,
gsi_after_labels, gsi_next_nondebug, gsi_prev_nondebug,
gsi_start_nondebug_bb, gsi_start_nondebug_after_labels_bb,
gsi_last_nondebug_bb, gsi_bb, gsi_seq): Move to gimple-iterator.h.
(struct walk_stmt_info): Move to gimple-walk.h.
(gimple_seq_set_location): Move to gimple.c
* gimple-walk.c: New File.
(walk_gimple_seq_mod, walk_gimple_seq, walk_gimple_asm, walk_gimple_op,
walk_gimple_stmt, get_base_loadstore, walk_stmt_load_store_addr_ops,
walk_stmt_load_store_ops): Relocate here from gimple.c.
* gimple-iterator.c: Include gimple-iterator.h.
* gimple.c (walk_gimple_seq_mod, walk_gimple_seq, walk_gimple_asm,
walk_gimple_op, walk_gimple_stmt, get_base_loadstore,
walk_stmt_load_store_addr_ops, walk_stmt_load_store_ops): Move to
gimple-walk.c.
(gimple_seq_set_location): Relocate from gimple.h.
* tree-phinodes.h (set_phi_nodes): Move to tree-phinodes.c.
* tree-phinodes.c (set_phi_nodes): Relocate from tree-phinodes.h.
* gengtype.c (open_base_files): Add gimple-iterator.h to include list.
* Makefile.in (OBJS): Add gimple-walk.o
* asan.c: Update Include list as required for gimple-iterator.h and
gimple-walk.h.
* cfgexpand.c: Likewise.
* cfgloop.c: Likewise.
* cfgloopmanip.c: Likewise.
* cgraph.c: Likewise.
* cgraphbuild.c: Likewise.
* cgraphunit.c: Likewise.
* gimple-fold.c: Likewise.
* gimple-low.c: Likewise.
* gimple-pretty-print.c: Likewise.
* gimple-ssa-isolate-paths.c: Likewise.
* gimple-ssa-strength-reduction.c: Likewise.
* gimple-streamer-in.c: Likewise.
* gimple-streamer-out.c: Likewise.
* gimplify.c: Likewise.
* graphite-blocking.c: Likewise.
* graphite-clast-to-gimple.c: Likewise.
* graphite-dependences.c: Likewise.
* graphite-interchange.c: Likewise.
* graphite-optimize-isl.c: Likewise.
* graphite-poly.c: Likewise.
* graphite-scop-detection.c: Likewise.
* graphite-sese-to-poly.c: Likewise.
* graphite.c: Likewise.
* ipa-inline-analysis.c: Likewise.
* ipa-profile.c: Likewise.
* ipa-prop.c: Likewise.
* ipa-pure-const.c: Likewise.
* ipa-split.c: Likewise.
* lto-streamer-in.c: Likewise.
* lto-streamer-out.c: Likewise.
* omp-low.c: Likewise.
* predict.c: Likewise.
* profile.c: Likewise.
* sese.c: Likewise.
* tracer.c: Likewise.
* trans-mem.c: Likewise.
* tree-call-cdce.c: Likewise.
* tree-cfg.c: Likewise.
* tree-cfgcleanup.c: Likewise.
* tree-complex.c: Likewise.
* tree-data-ref.c: Likewise.
* tree-dfa.c: Likewise.
* tree-eh.c: Likewise.
* tree-emutls.c: Likewise.
* tree-if-conv.c: Likewise.
* tree-inline.c: Likewise.
* tree-into-ssa.c: Likewise.
* tree-loop-distribution.c: Likewise.
* tree-nested.c: Likewise.
* tree-nrv.c: Likewise.
* tree-object-size.c: Likewise.
* tree-outof-ssa.c: Likewise.
* tree-parloops.c: Likewise.
* tree-predcom.c: Likewise.
* tree-profile.c: Likewise.
* tree-scalar-evolution.c: Likewise.
* tree-sra.c: Likewise.
* tree-ssa-ccp.c: Likewise.
* tree-ssa-coalesce.c: Likewise.
* tree-ssa-copy.c: Likewise.
* tree-ssa-copyrename.c: Likewise.
* tree-ssa-dce.c: Likewise.
* tree-ssa-dom.c: Likewise.
* tree-ssa-dse.c: Likewise.
* tree-ssa-forwprop.c: Likewise.
* tree-ssa-ifcombine.c: Likewise.
* tree-ssa-live.c: Likewise.
* tree-ssa-loop-ch.c: Likewise.
* tree-ssa-loop-im.c: Likewise.
* tree-ssa-loop-ivcanon.c: Likewise.
* tree-ssa-loop-ivopts.c: Likewise.
* tree-ssa-loop-manip.c: Likewise.
* tree-ssa-loop-niter.c: Likewise.
* tree-ssa-loop-prefetch.c: Likewise.
* tree-ssa-loop.c: Likewise.
* tree-ssa-math-opts.c: Likewise.
* tree-ssa-phiopt.c: Likewise.
* tree-ssa-phiprop.c: Likewise.
* tree-ssa-pre.c: Likewise.
* tree-ssa-propagate.c: Likewise.
* tree-ssa-reassoc.c: Likewise.
* tree-ssa-sink.c: Likewise.
* tree-ssa-strlen.c: Likewise.
* tree-ssa-structalias.c: Likewise.
* tree-ssa-tail-merge.c: Likewise.
* tree-ssa-ter.c: Likewise.
* tree-ssa-threadedge.c: Likewise.
* tree-ssa-threadupdate.c: Likewise.
* tree-ssa-uncprop.c: Likewise.
* tree-ssa-uninit.c: Likewise.
* tree-ssa.c: Likewise.
* tree-stdarg.c: Likewise.
* tree-switch-conversion.c: Likewise.
* tree-tailcall.c: Likewise.
* tree-vect-data-refs.c: Likewise.
* tree-vect-generic.c: Likewise.
* tree-vect-loop-manip.c: Likewise.
* tree-vect-loop.c: Likewise.
* tree-vect-patterns.c: Likewise.
* tree-vect-slp.c: Likewise.
* tree-vect-stmts.c: Likewise.
* tree-vectorizer.c: Likewise.
* tree-vrp.c: Likewise.
* tree.c: Likewise.
* tsan.c: Likewise.
* value-prof.c: Likewise.
* vtable-verify.c: Likewise.
* config/aarch64/aarch64-builtins.c: Include gimple-iterator.h.
* config/rs6000/rs6000.c: Include gimple-iterator.h and gimple-walk.h.
* testsuite/g++.dg/plugin/selfassign.c: Include gimple-iterator.h.
* testsuite/gcc.dg/plugin/selfassign.c: Likewise.
From-SVN: r204763
2013-11-14 00:54:17 +01:00
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#include "gimple-iterator.h"
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2015-11-17 19:55:13 +01:00
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#include "case-cfn-macros.h"
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aarch64-builtins.c (enum aarch64_type_qualifiers): Add qualifier_lane_pair_index.
gcc/ChangeLog:
2019-01-10 Tamar Christina <tamar.christina@arm.com>
* config/aarch64/aarch64-builtins.c (enum aarch64_type_qualifiers): Add qualifier_lane_pair_index.
(emit-rtl.h): Include.
(TYPES_QUADOP_LANE_PAIR): New.
(aarch64_simd_expand_args): Use it.
(aarch64_simd_expand_builtin): Likewise.
(AARCH64_SIMD_FCMLA_LANEQ_BUILTINS, aarch64_fcmla_laneq_builtin_datum): New.
(FCMLA_LANEQ_BUILTIN, AARCH64_SIMD_FCMLA_LANEQ_BUILTIN_BASE,
AARCH64_SIMD_FCMLA_LANEQ_BUILTINS, aarch64_fcmla_lane_builtin_data,
aarch64_init_fcmla_laneq_builtins, aarch64_expand_fcmla_builtin): New.
(aarch64_init_builtins): Add aarch64_init_fcmla_laneq_builtins.
(aarch64_expand_buildin): Add AARCH64_SIMD_BUILTIN_FCMLA_LANEQ0_V2SF,
AARCH64_SIMD_BUILTIN_FCMLA_LANEQ90_V2SF, AARCH64_SIMD_BUILTIN_FCMLA_LANEQ180_V2SF,
AARCH64_SIMD_BUILTIN_FCMLA_LANEQ2700_V2SF, AARCH64_SIMD_BUILTIN_FCMLA_LANEQ0_V4HF,
AARCH64_SIMD_BUILTIN_FCMLA_LANEQ90_V4HF, AARCH64_SIMD_BUILTIN_FCMLA_LANEQ180_V4HF,
AARCH64_SIMD_BUILTIN_FCMLA_LANEQ270_V4HF.
* config/aarch64/iterators.md (FCMLA_maybe_lane): New.
* config/aarch64/aarch64-c.c (aarch64_update_cpp_builtins): Add __ARM_FEATURE_COMPLEX.
* config/aarch64/aarch64-simd-builtins.def (fcadd90, fcadd270, fcmla0, fcmla90,
fcmla180, fcmla270, fcmla_lane0, fcmla_lane90, fcmla_lane180, fcmla_lane270,
fcmla_laneq0, fcmla_laneq90, fcmla_laneq180, fcmla_laneq270,
fcmlaq_lane0, fcmlaq_lane90, fcmlaq_lane180, fcmlaq_lane270): New.
* config/aarch64/aarch64-simd.md (aarch64_fcmla_lane<rot><mode>,
aarch64_fcmla_laneq<rot>v4hf, aarch64_fcmlaq_lane<rot><mode>,aarch64_fcadd<rot><mode>,
aarch64_fcmla<rot><mode>): New.
* config/aarch64/arm_neon.h:
(vcadd_rot90_f16): New.
(vcaddq_rot90_f16): New.
(vcadd_rot270_f16): New.
(vcaddq_rot270_f16): New.
(vcmla_f16): New.
(vcmlaq_f16): New.
(vcmla_lane_f16): New.
(vcmla_laneq_f16): New.
(vcmlaq_lane_f16): New.
(vcmlaq_rot90_lane_f16): New.
(vcmla_rot90_laneq_f16): New.
(vcmla_rot90_lane_f16): New.
(vcmlaq_rot90_f16): New.
(vcmla_rot90_f16): New.
(vcmlaq_laneq_f16): New.
(vcmla_rot180_laneq_f16): New.
(vcmla_rot180_lane_f16): New.
(vcmlaq_rot180_f16): New.
(vcmla_rot180_f16): New.
(vcmlaq_rot90_laneq_f16): New.
(vcmlaq_rot270_laneq_f16): New.
(vcmlaq_rot270_lane_f16): New.
(vcmla_rot270_laneq_f16): New.
(vcmlaq_rot270_f16): New.
(vcmla_rot270_f16): New.
(vcmlaq_rot180_laneq_f16): New.
(vcmlaq_rot180_lane_f16): New.
(vcmla_rot270_lane_f16): New.
(vcadd_rot90_f32): New.
(vcaddq_rot90_f32): New.
(vcaddq_rot90_f64): New.
(vcadd_rot270_f32): New.
(vcaddq_rot270_f32): New.
(vcaddq_rot270_f64): New.
(vcmla_f32): New.
(vcmlaq_f32): New.
(vcmlaq_f64): New.
(vcmla_lane_f32): New.
(vcmla_laneq_f32): New.
(vcmlaq_lane_f32): New.
(vcmlaq_laneq_f32): New.
(vcmla_rot90_f32): New.
(vcmlaq_rot90_f32): New.
(vcmlaq_rot90_f64): New.
(vcmla_rot90_lane_f32): New.
(vcmla_rot90_laneq_f32): New.
(vcmlaq_rot90_lane_f32): New.
(vcmlaq_rot90_laneq_f32): New.
(vcmla_rot180_f32): New.
(vcmlaq_rot180_f32): New.
(vcmlaq_rot180_f64): New.
(vcmla_rot180_lane_f32): New.
(vcmla_rot180_laneq_f32): New.
(vcmlaq_rot180_lane_f32): New.
(vcmlaq_rot180_laneq_f32): New.
(vcmla_rot270_f32): New.
(vcmlaq_rot270_f32): New.
(vcmlaq_rot270_f64): New.
(vcmla_rot270_lane_f32): New.
(vcmla_rot270_laneq_f32): New.
(vcmlaq_rot270_lane_f32): New.
(vcmlaq_rot270_laneq_f32): New.
* config/aarch64/aarch64.h (TARGET_COMPLEX): New.
* config/aarch64/iterators.md (UNSPEC_FCADD90, UNSPEC_FCADD270,
UNSPEC_FCMLA, UNSPEC_FCMLA90, UNSPEC_FCMLA180, UNSPEC_FCMLA270): New.
(FCADD, FCMLA): New.
(rot): New.
* config/arm/types.md (neon_fcadd, neon_fcmla): New.
gcc/testsuite/ChangeLog:
2019-01-10 Tamar Christina <tamar.christina@arm.com>
* gcc.target/aarch64/advsimd-intrinsics/vector-complex.c: New test.
* gcc.target/aarch64/advsimd-intrinsics/vector-complex_f16.c: New test.
From-SVN: r267795
2019-01-10 04:30:59 +01:00
|
|
|
#include "emit-rtl.h"
|
aarch64: Treat GNU and Advanced SIMD vectors as distinct [PR92789, PR95726]
PR95726 is about template look-up for things like:
foo<float vecf __attribute__((vector_size(16)))>
foo<float32x4_t>
The immediate cause of the problem is that the hash function usually
returns different hashes for these types, yet the equality function
thinks they are equal. This then raises the question of how the types
are supposed to be treated.
I think the answer is that the GNU vector type should be treated as
distinct from float32x4_t, not least because the two types mangle
differently. However, each type should implicitly convert to the other.
This would mean that, as far as the PR is concerned, the hashing
function is right to (sometimes) treat the types differently and
the equality function is wrong to treat them as the same.
The most obvious way to enforce the type difference is to use a
target-specific type attribute. That on its own is enough to fix
the PR. The difficulty is deciding whether the knock-on effects
are acceptable.
One obvious effect is that GCC then rejects:
typedef float vecf __attribute__((vector_size(16)));
vecf x;
float32x4_t &z = x;
on the basis that the types are no longer reference-compatible.
I think that's again the correct behaviour, and consistent with
current Clang.
A trickier question is whether:
vecf x;
float32x4_t y;
… c ? x : y …
should be valid, and if so, what its type should be [PR92789].
As explained in the comment in the testcase, GCC and Clang both
accepted this, but GCC chose the “then” type while Clang chose
the “else” type. This can lead to different mangling for (probably
artificial) corner cases, as seen for “sel1” and “sel2” in the
testcase.
Adding the attribute makes GCC reject the conditional expression
as ambiguous. I think that too is the correct behaviour, for the
reasons described in the testcase. However, it does seem to have
the potential to break existing code.
It looks like aarch64_comp_type_attributes is missing cases for
the SVE attributes, but I'll handle that in a separate patch.
2020-06-30 Richard Sandiford <richard.sandiford@arm.com>
gcc/
PR target/92789
PR target/95726
* config/aarch64/aarch64.c (aarch64_attribute_table): Add
"Advanced SIMD type".
(aarch64_comp_type_attributes): Check that the "Advanced SIMD type"
attributes are equal.
* config/aarch64/aarch64-builtins.c: Include stringpool.h and
attribs.h.
(aarch64_mangle_builtin_vector_type): Use the mangling recorded
in the "Advanced SIMD type" attribute.
(aarch64_init_simd_builtin_types): Add an "Advanced SIMD type"
attribute to each Advanced SIMD type, using the mangled type
as the attribute's single argument.
gcc/testsuite/
PR target/92789
PR target/95726
* g++.target/aarch64/pr95726.C: New test.
2020-06-30 22:40:30 +02:00
|
|
|
#include "stringpool.h"
|
|
|
|
#include "attribs.h"
|
2021-10-20 14:19:10 +02:00
|
|
|
#include "gimple-fold.h"
|
2012-10-23 19:02:30 +02:00
|
|
|
|
[1/77] Add an E_ prefix to mode names
Later patches will add wrapper types for specific classes
of mode. E.g. SImode will be a scalar_int_mode, SFmode will be a
scalar_float_mode, etc. This patch prepares for that change by adding
an E_ prefix to the mode enum values. It also adds #defines that map
the unprefixed names to the prefixed names; e.g:
#define QImode E_QImode
Later patches will change this to use things like scalar_int_mode
where appropriate.
The patch continues to use enum values to initialise static data.
This isn't necessary for correctness, but it cuts down on the amount
of load-time initialisation and shouldn't have any downsides.
The patch also changes things like:
cmp_mode == DImode ? DFmode : DImode
to:
cmp_mode == DImode ? E_DFmode : E_DImode
This is because DImode and DFmode will eventually be different
classes, so the original ?: wouldn't be well-formed.
2017-08-30 Richard Sandiford <richard.sandiford@linaro.org>
Alan Hayward <alan.hayward@arm.com>
David Sherwood <david.sherwood@arm.com>
gcc/
* genmodes.c (mode_size_inline): Add an E_ prefix to mode names.
(mode_nunits_inline): Likewise.
(mode_inner_inline): Likewise.
(mode_unit_size_inline): Likewise.
(mode_unit_precision_inline): Likewise.
(emit_insn_modes_h): Likewise. Also emit a #define of the
unprefixed name.
(emit_mode_wider): Add an E_ prefix to mode names.
(emit_mode_complex): Likewise.
(emit_mode_inner): Likewise.
(emit_mode_adjustments): Likewise.
(emit_mode_int_n): Likewise.
* config/aarch64/aarch64-builtins.c (v8qi_UP, v4hi_UP, v4hf_UP)
(v2si_UP, v2sf_UP, v1df_UP, di_UP, df_UP, v16qi_UP, v8hi_UP, v8hf_UP)
(v4si_UP, v4sf_UP, v2di_UP, v2df_UP, ti_UP, oi_UP, ci_UP, xi_UP)
(si_UP, sf_UP, hi_UP, hf_UP, qi_UP): Likewise.
(CRC32_BUILTIN, ENTRY): Likewise.
* config/aarch64/aarch64.c (aarch64_push_regs): Likewise.
(aarch64_pop_regs): Likewise.
(aarch64_process_components): Likewise.
* config/alpha/alpha.c (alpha_emit_conditional_move): Likewise.
* config/arm/arm-builtins.c (v8qi_UP, v4hi_UP, v4hf_UP, v2si_UP)
(v2sf_UP, di_UP, v16qi_UP, v8hi_UP, v8hf_UP, v4si_UP, v4sf_UP)
(v2di_UP, ti_UP, ei_UP, oi_UP, hf_UP, si_UP, void_UP): Likewise.
* config/arm/arm.c (arm_init_libfuncs): Likewise.
* config/i386/i386-builtin-types.awk (ix86_builtin_type_vect_mode):
Likewise.
* config/i386/i386-builtin.def (pcmpestr): Likewise.
(pcmpistr): Likewise.
* config/microblaze/microblaze.c (double_memory_operand): Likewise.
* config/mmix/mmix.c (mmix_output_condition): Likewise.
* config/powerpcspe/powerpcspe.c (rs6000_init_hard_regno_mode_ok):
Likewise.
* config/rl78/rl78.c (mduc_regs): Likewise.
* config/rs6000/rs6000.c (rs6000_init_hard_regno_mode_ok): Likewise.
(htm_expand_builtin): Likewise.
* config/sh/sh.h (REGISTER_NATURAL_MODE): Likewise.
* config/sparc/sparc.c (emit_save_or_restore_regs): Likewise.
* config/xtensa/xtensa.c (print_operand): Likewise.
* expmed.h (NUM_MODE_PARTIAL_INT): Likewise.
(NUM_MODE_VECTOR_INT): Likewise.
* genoutput.c (null_operand): Likewise.
(output_operand_data): Likewise.
* genrecog.c (print_parameter_value): Likewise.
* lra.c (debug_operand_data): Likewise.
Co-Authored-By: Alan Hayward <alan.hayward@arm.com>
Co-Authored-By: David Sherwood <david.sherwood@arm.com>
From-SVN: r251452
2017-08-30 13:08:14 +02:00
|
|
|
#define v8qi_UP E_V8QImode
|
2021-12-14 15:03:38 +01:00
|
|
|
#define v8di_UP E_V8DImode
|
[1/77] Add an E_ prefix to mode names
Later patches will add wrapper types for specific classes
of mode. E.g. SImode will be a scalar_int_mode, SFmode will be a
scalar_float_mode, etc. This patch prepares for that change by adding
an E_ prefix to the mode enum values. It also adds #defines that map
the unprefixed names to the prefixed names; e.g:
#define QImode E_QImode
Later patches will change this to use things like scalar_int_mode
where appropriate.
The patch continues to use enum values to initialise static data.
This isn't necessary for correctness, but it cuts down on the amount
of load-time initialisation and shouldn't have any downsides.
The patch also changes things like:
cmp_mode == DImode ? DFmode : DImode
to:
cmp_mode == DImode ? E_DFmode : E_DImode
This is because DImode and DFmode will eventually be different
classes, so the original ?: wouldn't be well-formed.
2017-08-30 Richard Sandiford <richard.sandiford@linaro.org>
Alan Hayward <alan.hayward@arm.com>
David Sherwood <david.sherwood@arm.com>
gcc/
* genmodes.c (mode_size_inline): Add an E_ prefix to mode names.
(mode_nunits_inline): Likewise.
(mode_inner_inline): Likewise.
(mode_unit_size_inline): Likewise.
(mode_unit_precision_inline): Likewise.
(emit_insn_modes_h): Likewise. Also emit a #define of the
unprefixed name.
(emit_mode_wider): Add an E_ prefix to mode names.
(emit_mode_complex): Likewise.
(emit_mode_inner): Likewise.
(emit_mode_adjustments): Likewise.
(emit_mode_int_n): Likewise.
* config/aarch64/aarch64-builtins.c (v8qi_UP, v4hi_UP, v4hf_UP)
(v2si_UP, v2sf_UP, v1df_UP, di_UP, df_UP, v16qi_UP, v8hi_UP, v8hf_UP)
(v4si_UP, v4sf_UP, v2di_UP, v2df_UP, ti_UP, oi_UP, ci_UP, xi_UP)
(si_UP, sf_UP, hi_UP, hf_UP, qi_UP): Likewise.
(CRC32_BUILTIN, ENTRY): Likewise.
* config/aarch64/aarch64.c (aarch64_push_regs): Likewise.
(aarch64_pop_regs): Likewise.
(aarch64_process_components): Likewise.
* config/alpha/alpha.c (alpha_emit_conditional_move): Likewise.
* config/arm/arm-builtins.c (v8qi_UP, v4hi_UP, v4hf_UP, v2si_UP)
(v2sf_UP, di_UP, v16qi_UP, v8hi_UP, v8hf_UP, v4si_UP, v4sf_UP)
(v2di_UP, ti_UP, ei_UP, oi_UP, hf_UP, si_UP, void_UP): Likewise.
* config/arm/arm.c (arm_init_libfuncs): Likewise.
* config/i386/i386-builtin-types.awk (ix86_builtin_type_vect_mode):
Likewise.
* config/i386/i386-builtin.def (pcmpestr): Likewise.
(pcmpistr): Likewise.
* config/microblaze/microblaze.c (double_memory_operand): Likewise.
* config/mmix/mmix.c (mmix_output_condition): Likewise.
* config/powerpcspe/powerpcspe.c (rs6000_init_hard_regno_mode_ok):
Likewise.
* config/rl78/rl78.c (mduc_regs): Likewise.
* config/rs6000/rs6000.c (rs6000_init_hard_regno_mode_ok): Likewise.
(htm_expand_builtin): Likewise.
* config/sh/sh.h (REGISTER_NATURAL_MODE): Likewise.
* config/sparc/sparc.c (emit_save_or_restore_regs): Likewise.
* config/xtensa/xtensa.c (print_operand): Likewise.
* expmed.h (NUM_MODE_PARTIAL_INT): Likewise.
(NUM_MODE_VECTOR_INT): Likewise.
* genoutput.c (null_operand): Likewise.
(output_operand_data): Likewise.
* genrecog.c (print_parameter_value): Likewise.
* lra.c (debug_operand_data): Likewise.
Co-Authored-By: Alan Hayward <alan.hayward@arm.com>
Co-Authored-By: David Sherwood <david.sherwood@arm.com>
From-SVN: r251452
2017-08-30 13:08:14 +02:00
|
|
|
#define v4hi_UP E_V4HImode
|
|
|
|
#define v4hf_UP E_V4HFmode
|
|
|
|
#define v2si_UP E_V2SImode
|
|
|
|
#define v2sf_UP E_V2SFmode
|
|
|
|
#define v1df_UP E_V1DFmode
|
|
|
|
#define di_UP E_DImode
|
|
|
|
#define df_UP E_DFmode
|
|
|
|
#define v16qi_UP E_V16QImode
|
|
|
|
#define v8hi_UP E_V8HImode
|
|
|
|
#define v8hf_UP E_V8HFmode
|
|
|
|
#define v4si_UP E_V4SImode
|
|
|
|
#define v4sf_UP E_V4SFmode
|
|
|
|
#define v2di_UP E_V2DImode
|
|
|
|
#define v2df_UP E_V2DFmode
|
|
|
|
#define ti_UP E_TImode
|
|
|
|
#define oi_UP E_OImode
|
|
|
|
#define ci_UP E_CImode
|
|
|
|
#define xi_UP E_XImode
|
|
|
|
#define si_UP E_SImode
|
|
|
|
#define sf_UP E_SFmode
|
|
|
|
#define hi_UP E_HImode
|
|
|
|
#define hf_UP E_HFmode
|
|
|
|
#define qi_UP E_QImode
|
2020-01-10 20:23:41 +01:00
|
|
|
#define bf_UP E_BFmode
|
|
|
|
#define v4bf_UP E_V4BFmode
|
|
|
|
#define v8bf_UP E_V8BFmode
|
2021-08-09 16:26:48 +02:00
|
|
|
#define v2x8qi_UP E_V2x8QImode
|
|
|
|
#define v2x4hi_UP E_V2x4HImode
|
|
|
|
#define v2x4hf_UP E_V2x4HFmode
|
|
|
|
#define v2x4bf_UP E_V2x4BFmode
|
|
|
|
#define v2x2si_UP E_V2x2SImode
|
|
|
|
#define v2x2sf_UP E_V2x2SFmode
|
|
|
|
#define v2x1di_UP E_V2x1DImode
|
|
|
|
#define v2x1df_UP E_V2x1DFmode
|
|
|
|
#define v2x16qi_UP E_V2x16QImode
|
|
|
|
#define v2x8hi_UP E_V2x8HImode
|
|
|
|
#define v2x8hf_UP E_V2x8HFmode
|
|
|
|
#define v2x8bf_UP E_V2x8BFmode
|
|
|
|
#define v2x4si_UP E_V2x4SImode
|
|
|
|
#define v2x4sf_UP E_V2x4SFmode
|
|
|
|
#define v2x2di_UP E_V2x2DImode
|
|
|
|
#define v2x2df_UP E_V2x2DFmode
|
|
|
|
#define v3x8qi_UP E_V3x8QImode
|
|
|
|
#define v3x4hi_UP E_V3x4HImode
|
|
|
|
#define v3x4hf_UP E_V3x4HFmode
|
|
|
|
#define v3x4bf_UP E_V3x4BFmode
|
|
|
|
#define v3x2si_UP E_V3x2SImode
|
|
|
|
#define v3x2sf_UP E_V3x2SFmode
|
|
|
|
#define v3x1di_UP E_V3x1DImode
|
|
|
|
#define v3x1df_UP E_V3x1DFmode
|
|
|
|
#define v3x16qi_UP E_V3x16QImode
|
|
|
|
#define v3x8hi_UP E_V3x8HImode
|
|
|
|
#define v3x8hf_UP E_V3x8HFmode
|
|
|
|
#define v3x8bf_UP E_V3x8BFmode
|
|
|
|
#define v3x4si_UP E_V3x4SImode
|
|
|
|
#define v3x4sf_UP E_V3x4SFmode
|
|
|
|
#define v3x2di_UP E_V3x2DImode
|
|
|
|
#define v3x2df_UP E_V3x2DFmode
|
|
|
|
#define v4x8qi_UP E_V4x8QImode
|
|
|
|
#define v4x4hi_UP E_V4x4HImode
|
|
|
|
#define v4x4hf_UP E_V4x4HFmode
|
|
|
|
#define v4x4bf_UP E_V4x4BFmode
|
|
|
|
#define v4x2si_UP E_V4x2SImode
|
|
|
|
#define v4x2sf_UP E_V4x2SFmode
|
|
|
|
#define v4x1di_UP E_V4x1DImode
|
|
|
|
#define v4x1df_UP E_V4x1DFmode
|
|
|
|
#define v4x16qi_UP E_V4x16QImode
|
|
|
|
#define v4x8hi_UP E_V4x8HImode
|
|
|
|
#define v4x8hf_UP E_V4x8HFmode
|
|
|
|
#define v4x8bf_UP E_V4x8BFmode
|
|
|
|
#define v4x4si_UP E_V4x4SImode
|
|
|
|
#define v4x4sf_UP E_V4x4SFmode
|
|
|
|
#define v4x2di_UP E_V4x2DImode
|
|
|
|
#define v4x2df_UP E_V4x2DFmode
|
2012-10-23 19:02:30 +02:00
|
|
|
#define UP(X) X##_UP
|
|
|
|
|
2013-11-20 10:19:25 +01:00
|
|
|
#define SIMD_MAX_BUILTIN_ARGS 5
|
|
|
|
|
|
|
|
enum aarch64_type_qualifiers
|
2012-10-23 19:02:30 +02:00
|
|
|
{
|
2013-11-20 10:19:25 +01:00
|
|
|
/* T foo. */
|
|
|
|
qualifier_none = 0x0,
|
|
|
|
/* unsigned T foo. */
|
|
|
|
qualifier_unsigned = 0x1, /* 1 << 0 */
|
|
|
|
/* const T foo. */
|
|
|
|
qualifier_const = 0x2, /* 1 << 1 */
|
|
|
|
/* T *foo. */
|
|
|
|
qualifier_pointer = 0x4, /* 1 << 2 */
|
|
|
|
/* Used when expanding arguments if an operand could
|
|
|
|
be an immediate. */
|
|
|
|
qualifier_immediate = 0x8, /* 1 << 3 */
|
|
|
|
qualifier_maybe_immediate = 0x10, /* 1 << 4 */
|
|
|
|
/* void foo (...). */
|
|
|
|
qualifier_void = 0x20, /* 1 << 5 */
|
|
|
|
/* Some patterns may have internal operands, this qualifier is an
|
|
|
|
instruction to the initialisation code to skip this operand. */
|
|
|
|
qualifier_internal = 0x40, /* 1 << 6 */
|
|
|
|
/* Some builtins should use the T_*mode* encoded in a simd_builtin_datum
|
|
|
|
rather than using the type of the operand. */
|
|
|
|
qualifier_map_mode = 0x80, /* 1 << 7 */
|
|
|
|
/* qualifier_pointer | qualifier_map_mode */
|
|
|
|
qualifier_pointer_map_mode = 0x84,
|
2014-09-05 12:37:00 +02:00
|
|
|
/* qualifier_const | qualifier_pointer | qualifier_map_mode */
|
2013-11-26 11:00:49 +01:00
|
|
|
qualifier_const_pointer_map_mode = 0x86,
|
|
|
|
/* Polynomial types. */
|
Add bounds checking to vqdm*_lane intrinsics via a qualifier that also flips endianness
gcc/:
* config/aarch64/aarch64.c (aarch64_simd_lane_bounds): Display indices.
* config/aarch64/aarch64-builtins.c (enum aarch64_type_qualifiers): Add
qualifier_lane_index.
(aarch64_types_ternop_lane_qualifiers, TYPES_TERNOP_LANE): Rename to...
(aarch64_types_quadop_lane_qualifiers, TYPES_QUADOP_LANE): ...these.
(aarch64_types_ternop_lane_qualifiers, TYPES_TERNOP_LANE): New.
(aarch64_types_getlane_qualifiers): Rename to...
(aarch64_types_binop_imm_qualifiers): ...this.
(TYPES_SHIFTIMM): Follow renaming.
(TYPES_GETLANE): Rename to...
(TYPE_GETREG): ...this.
(aarch64_types_setlane_qualifiers): Rename to...
(aarch64_type_ternop_imm_qualifiers): ...this.
(TYPES_SHIFTINSERT, TYPES_SHIFTACC): Follow renaming.
(TYPES_SETLANE): Follow renaming above, and rename self to...
(TYPE_SETREG): ...this.
(enum builtin_simd_arg): Add SIMD_ARG_LANE_INDEX.
(aarch64_simd_expand_args): Add range check and endianness-flip.
(aarch64_simd_expand_builtin): Add mapping for qualifier_lane_index.
* config/aarch64/aarch64-simd.md
(aarch64_sq<r>dmulh_lane<mode>_internal *2): Rename to...
(aarch64_sq<r>dmulh_lane<mode>): ...this, and remove lane bounds check.
(aarch64_sqdmulh_lane<mode> *2, aarch64_sqrdmulh_lane<mode> *2): Delete.
(aarch64_sq<r>dmulh_laneq<mode>_internal): Rename to...
(aarch64_sq<r>dmulh_lane<mode>): ...this.
(aarch64_sqdml<SBINQOPS:as>l_lane<mode>_internal *2): Rename to...
(aarch64_sqdml<SBINQOPS:as>l_lane<mode>): ...this.
(aarch64_sqdml<SBINQOPS:as>l_laneq<mode>_internal *2): Rename to...
(aarch64_sqdml<SBINQOPS:as>l_laneq<mode>): ...this.
(aarch64_sqdmull_lane<mode>_internal *2): Rename to...
(aarch64_sqdmull_lane<mode>): ...this.
(aarch64_sqdmull_laneq<mode>_internal *2): Rename to...
(aarch64_sqdmull_laneq<mode>): ...this.
(aarch64_sqdmulh_laneq<mode>, aarch64_sqrdmulh_laneq<mode>,
(aarch64_sqdmlal_lane<mode>, aarch64_sqdmlal_laneq<mode>,
aarch64_sqdmlsl_lane<mode>, aarch64_sqdmlsl_laneq<mode>,
aarch64_sqdmull_lane<mode>, aarch64_sqdmull_laneq<mode>): Delete.
(aarch64_sqdmlal2_lane<mode>, aarch64_sqdmlal2_laneq<mode>,
aarch64_sqdmlsl2_lane<mode>, aarch64_sqdmlsl2_laneq<mode>,
aarch64_sqdmull2_lane<mode>, aarch64_sqdmull2_laneq<mode>): Remove
bounds check and lane flip.
* config/aarch64/aarch64-simd-builtins.def (be_checked_get_lane,
get_dregoi, get_dregci, getdregxi, get_qregoi,get_qregci, get_qregxi,
set_qregoi, set_qregci, set_qregxi): Change qualifiers to GETREG.
(sqdmlal_lane, sqdmlsl_lane, sqdmlal_laneq, sqdmlsl_laneq,
sqdmlal2_lane, sqdmlsl2_lane, sqdmlal2_laneq, sqdmlsl2_laneq): Follow
renaming of TERNOP_LANE to QUADOP_LANE.
(sqdmull_lane, sqdmull_laneq, sqdmull2_lane, sqdmull2_laneq,
sqdmulh_lane, sqdmulh_laneq, sqrdmulh_lane, sqrdmulh_laneq): Set
qualifiers to TERNOP_LANE.
gcc/testsuite/:
* gcc.target/aarch64/simd/vqdmlal_high_lane_s16_indices_1.c: New test.
* gcc.target/aarch64/simd/vqdmlal_high_lane_s32_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqdmlal_high_laneq_s16_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqdmlal_high_laneq_s32_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqdmlal_lane_s16_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqdmlal_lane_s32_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqdmlal_laneq_s16_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqdmlal_laneq_s32_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqdmlalh_lane_s16_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqdmlals_lane_s32_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqdmlsl_high_lane_s16_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqdmlsl_high_lane_s32_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqdmlsl_high_laneq_s16_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqdmlsl_high_laneq_s32_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqdmlsl_lane_s16_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqdmlsl_lane_s32_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqdmlsl_laneq_s16_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqdmlsl_laneq_s32_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqdmlslh_lane_s16_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqdmlsls_lane_s32_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqdmulh_lane_s16_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqdmulh_lane_s32_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqdmulh_laneq_s16_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqdmulh_laneq_s32_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqdmulhh_lane_s16_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqdmulhq_lane_s16_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqdmulhq_lane_s32_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqdmulhq_laneq_s16_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqdmulhq_laneq_s32_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqdmulhs_lane_s32_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqdmull_high_lane_s16_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqdmull_high_lane_s32_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqdmull_high_laneq_s16_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqdmull_high_laneq_s32_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqdmull_lane_s16_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqdmull_lane_s32_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqdmull_laneq_s16_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqdmull_laneq_s32_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqdmullh_lane_s16_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqdmulls_lane_s32_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqrdmulh_lane_s16_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqrdmulh_lane_s32_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqrdmulh_laneq_s16_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqrdmulh_laneq_s32_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqrdmulhh_lane_s16_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqrdmulhq_lane_s16_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqrdmulhq_lane_s32_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqrdmulhq_laneq_s16_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqrdmulhq_laneq_s32_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqrdmulhs_lane_s32_indices_1.c: Likewise.
From-SVN: r217440
2014-11-12 19:51:53 +01:00
|
|
|
qualifier_poly = 0x100,
|
|
|
|
/* Lane indices - must be in range, and flipped for bigendian. */
|
2015-07-22 12:44:16 +02:00
|
|
|
qualifier_lane_index = 0x200,
|
|
|
|
/* Lane indices for single lane structure loads and stores. */
|
aarch64-builtins.c (enum aarch64_type_qualifiers): Add qualifier_lane_pair_index.
gcc/ChangeLog:
2019-01-10 Tamar Christina <tamar.christina@arm.com>
* config/aarch64/aarch64-builtins.c (enum aarch64_type_qualifiers): Add qualifier_lane_pair_index.
(emit-rtl.h): Include.
(TYPES_QUADOP_LANE_PAIR): New.
(aarch64_simd_expand_args): Use it.
(aarch64_simd_expand_builtin): Likewise.
(AARCH64_SIMD_FCMLA_LANEQ_BUILTINS, aarch64_fcmla_laneq_builtin_datum): New.
(FCMLA_LANEQ_BUILTIN, AARCH64_SIMD_FCMLA_LANEQ_BUILTIN_BASE,
AARCH64_SIMD_FCMLA_LANEQ_BUILTINS, aarch64_fcmla_lane_builtin_data,
aarch64_init_fcmla_laneq_builtins, aarch64_expand_fcmla_builtin): New.
(aarch64_init_builtins): Add aarch64_init_fcmla_laneq_builtins.
(aarch64_expand_buildin): Add AARCH64_SIMD_BUILTIN_FCMLA_LANEQ0_V2SF,
AARCH64_SIMD_BUILTIN_FCMLA_LANEQ90_V2SF, AARCH64_SIMD_BUILTIN_FCMLA_LANEQ180_V2SF,
AARCH64_SIMD_BUILTIN_FCMLA_LANEQ2700_V2SF, AARCH64_SIMD_BUILTIN_FCMLA_LANEQ0_V4HF,
AARCH64_SIMD_BUILTIN_FCMLA_LANEQ90_V4HF, AARCH64_SIMD_BUILTIN_FCMLA_LANEQ180_V4HF,
AARCH64_SIMD_BUILTIN_FCMLA_LANEQ270_V4HF.
* config/aarch64/iterators.md (FCMLA_maybe_lane): New.
* config/aarch64/aarch64-c.c (aarch64_update_cpp_builtins): Add __ARM_FEATURE_COMPLEX.
* config/aarch64/aarch64-simd-builtins.def (fcadd90, fcadd270, fcmla0, fcmla90,
fcmla180, fcmla270, fcmla_lane0, fcmla_lane90, fcmla_lane180, fcmla_lane270,
fcmla_laneq0, fcmla_laneq90, fcmla_laneq180, fcmla_laneq270,
fcmlaq_lane0, fcmlaq_lane90, fcmlaq_lane180, fcmlaq_lane270): New.
* config/aarch64/aarch64-simd.md (aarch64_fcmla_lane<rot><mode>,
aarch64_fcmla_laneq<rot>v4hf, aarch64_fcmlaq_lane<rot><mode>,aarch64_fcadd<rot><mode>,
aarch64_fcmla<rot><mode>): New.
* config/aarch64/arm_neon.h:
(vcadd_rot90_f16): New.
(vcaddq_rot90_f16): New.
(vcadd_rot270_f16): New.
(vcaddq_rot270_f16): New.
(vcmla_f16): New.
(vcmlaq_f16): New.
(vcmla_lane_f16): New.
(vcmla_laneq_f16): New.
(vcmlaq_lane_f16): New.
(vcmlaq_rot90_lane_f16): New.
(vcmla_rot90_laneq_f16): New.
(vcmla_rot90_lane_f16): New.
(vcmlaq_rot90_f16): New.
(vcmla_rot90_f16): New.
(vcmlaq_laneq_f16): New.
(vcmla_rot180_laneq_f16): New.
(vcmla_rot180_lane_f16): New.
(vcmlaq_rot180_f16): New.
(vcmla_rot180_f16): New.
(vcmlaq_rot90_laneq_f16): New.
(vcmlaq_rot270_laneq_f16): New.
(vcmlaq_rot270_lane_f16): New.
(vcmla_rot270_laneq_f16): New.
(vcmlaq_rot270_f16): New.
(vcmla_rot270_f16): New.
(vcmlaq_rot180_laneq_f16): New.
(vcmlaq_rot180_lane_f16): New.
(vcmla_rot270_lane_f16): New.
(vcadd_rot90_f32): New.
(vcaddq_rot90_f32): New.
(vcaddq_rot90_f64): New.
(vcadd_rot270_f32): New.
(vcaddq_rot270_f32): New.
(vcaddq_rot270_f64): New.
(vcmla_f32): New.
(vcmlaq_f32): New.
(vcmlaq_f64): New.
(vcmla_lane_f32): New.
(vcmla_laneq_f32): New.
(vcmlaq_lane_f32): New.
(vcmlaq_laneq_f32): New.
(vcmla_rot90_f32): New.
(vcmlaq_rot90_f32): New.
(vcmlaq_rot90_f64): New.
(vcmla_rot90_lane_f32): New.
(vcmla_rot90_laneq_f32): New.
(vcmlaq_rot90_lane_f32): New.
(vcmlaq_rot90_laneq_f32): New.
(vcmla_rot180_f32): New.
(vcmlaq_rot180_f32): New.
(vcmlaq_rot180_f64): New.
(vcmla_rot180_lane_f32): New.
(vcmla_rot180_laneq_f32): New.
(vcmlaq_rot180_lane_f32): New.
(vcmlaq_rot180_laneq_f32): New.
(vcmla_rot270_f32): New.
(vcmlaq_rot270_f32): New.
(vcmlaq_rot270_f64): New.
(vcmla_rot270_lane_f32): New.
(vcmla_rot270_laneq_f32): New.
(vcmlaq_rot270_lane_f32): New.
(vcmlaq_rot270_laneq_f32): New.
* config/aarch64/aarch64.h (TARGET_COMPLEX): New.
* config/aarch64/iterators.md (UNSPEC_FCADD90, UNSPEC_FCADD270,
UNSPEC_FCMLA, UNSPEC_FCMLA90, UNSPEC_FCMLA180, UNSPEC_FCMLA270): New.
(FCADD, FCMLA): New.
(rot): New.
* config/arm/types.md (neon_fcadd, neon_fcmla): New.
gcc/testsuite/ChangeLog:
2019-01-10 Tamar Christina <tamar.christina@arm.com>
* gcc.target/aarch64/advsimd-intrinsics/vector-complex.c: New test.
* gcc.target/aarch64/advsimd-intrinsics/vector-complex_f16.c: New test.
From-SVN: r267795
2019-01-10 04:30:59 +01:00
|
|
|
qualifier_struct_load_store_lane_index = 0x400,
|
|
|
|
/* Lane indices selected in pairs. - must be in range, and flipped for
|
|
|
|
bigendian. */
|
|
|
|
qualifier_lane_pair_index = 0x800,
|
2020-01-16 15:20:48 +01:00
|
|
|
/* Lane indices selected in quadtuplets. - must be in range, and flipped for
|
|
|
|
bigendian. */
|
|
|
|
qualifier_lane_quadtup_index = 0x1000,
|
2013-11-20 10:19:25 +01:00
|
|
|
};
|
2012-10-23 19:02:30 +02:00
|
|
|
|
2020-07-17 11:00:37 +02:00
|
|
|
/* Flags that describe what a function might do. */
|
|
|
|
const unsigned int FLAG_NONE = 0U;
|
|
|
|
const unsigned int FLAG_READ_FPCR = 1U << 0;
|
|
|
|
const unsigned int FLAG_RAISE_FP_EXCEPTIONS = 1U << 1;
|
|
|
|
const unsigned int FLAG_READ_MEMORY = 1U << 2;
|
|
|
|
const unsigned int FLAG_PREFETCH_MEMORY = 1U << 3;
|
|
|
|
const unsigned int FLAG_WRITE_MEMORY = 1U << 4;
|
|
|
|
|
2020-08-04 18:25:29 +02:00
|
|
|
/* Not all FP intrinsics raise FP exceptions or read FPCR register,
|
|
|
|
use this flag to suppress it. */
|
|
|
|
const unsigned int FLAG_AUTO_FP = 1U << 5;
|
|
|
|
|
2020-07-17 11:00:37 +02:00
|
|
|
const unsigned int FLAG_FP = FLAG_READ_FPCR | FLAG_RAISE_FP_EXCEPTIONS;
|
|
|
|
const unsigned int FLAG_ALL = FLAG_READ_FPCR | FLAG_RAISE_FP_EXCEPTIONS
|
|
|
|
| FLAG_READ_MEMORY | FLAG_PREFETCH_MEMORY | FLAG_WRITE_MEMORY;
|
2020-10-26 14:02:18 +01:00
|
|
|
const unsigned int FLAG_STORE = FLAG_WRITE_MEMORY | FLAG_AUTO_FP;
|
aarch64: Add and use FLAG_LOAD in builtins
We already have a STORE flag that we use for builtins. This patch introduces a LOAD set
that uses AUTO_FP and FLAG_READ_MEMORY. This allows for more aggressive optimisation of the load
intrinsics.
Turns out we have a great many testcases that do:
float16x4x2_t
f_vld2_lane_f16 (float16_t * p, float16x4x2_t v)
{
float16x4x2_t res;
/* { dg-error "lane 4 out of range 0 - 3" "" { target *-*-* } 0 } */
res = vld2_lane_f16 (p, v, 4);
/* { dg-error "lane -1 out of range 0 - 3" "" { target *-*-* } 0 } */
res = vld2_lane_f16 (p, v, -1);
return res;
}
but since the first res is unused it now gets eliminated early on before we get to give an error
message. Ideally we'd like to warn for both.
This patch takes the conservative approach and doesn't convert the load-lane builtins to LOAD ;
that's something we can improve later.
gcc/ChangeLog:
* config/aarch64/aarch64-builtins.c (FLAG_LOAD): Define.
* config/aarch64/aarch64-simd-builtins.def (ld1x2, ld2, ld3, ld4, ld2r,
ld3r, ld4r, ld1, ld1x3, ld1x4): Use LOAD flags.
2021-02-01 23:51:11 +01:00
|
|
|
const unsigned int FLAG_LOAD = FLAG_READ_MEMORY | FLAG_AUTO_FP;
|
2020-07-17 11:00:37 +02:00
|
|
|
|
2012-10-23 19:02:30 +02:00
|
|
|
typedef struct
|
|
|
|
{
|
|
|
|
const char *name;
|
decl.c, [...]: Remove redundant enum from machine_mode.
gcc/ada/
* gcc-interface/decl.c, gcc-interface/gigi.h, gcc-interface/misc.c,
gcc-interface/trans.c, gcc-interface/utils.c, gcc-interface/utils2.c:
Remove redundant enum from machine_mode.
gcc/c-family/
* c-common.c, c-common.h, c-cppbuiltin.c, c-lex.c: Remove redundant
enum from machine_mode.
gcc/c/
* c-decl.c, c-tree.h, c-typeck.c: Remove redundant enum from
machine_mode.
gcc/cp/
* constexpr.c: Remove redundant enum from machine_mode.
gcc/fortran/
* trans-types.c, trans-types.h: Remove redundant enum from
machine_mode.
gcc/go/
* go-lang.c: Remove redundant enum from machine_mode.
gcc/java/
* builtins.c, java-tree.h, typeck.c: Remove redundant enum from
machine_mode.
gcc/lto/
* lto-lang.c: Remove redundant enum from machine_mode.
gcc/
* addresses.h, alias.c, asan.c, auto-inc-dec.c, bt-load.c, builtins.c,
builtins.h, caller-save.c, calls.c, calls.h, cfgexpand.c, cfgloop.h,
cfgrtl.c, combine.c, compare-elim.c, config/aarch64/aarch64-builtins.c,
config/aarch64/aarch64-protos.h, config/aarch64/aarch64-simd.md,
config/aarch64/aarch64.c, config/aarch64/aarch64.h,
config/aarch64/aarch64.md, config/alpha/alpha-protos.h,
config/alpha/alpha.c, config/arc/arc-protos.h, config/arc/arc.c,
config/arc/arc.h, config/arc/predicates.md,
config/arm/aarch-common-protos.h, config/arm/aarch-common.c,
config/arm/arm-protos.h, config/arm/arm.c, config/arm/arm.h,
config/arm/arm.md, config/arm/neon.md, config/arm/thumb2.md,
config/avr/avr-log.c, config/avr/avr-protos.h, config/avr/avr.c,
config/avr/avr.md, config/bfin/bfin-protos.h, config/bfin/bfin.c,
config/c6x/c6x-protos.h, config/c6x/c6x.c, config/c6x/c6x.md,
config/cr16/cr16-protos.h, config/cr16/cr16.c,
config/cris/cris-protos.h, config/cris/cris.c, config/cris/cris.md,
config/darwin-protos.h, config/darwin.c,
config/epiphany/epiphany-protos.h, config/epiphany/epiphany.c,
config/epiphany/epiphany.md, config/fr30/fr30.c,
config/frv/frv-protos.h, config/frv/frv.c, config/frv/predicates.md,
config/h8300/h8300-protos.h, config/h8300/h8300.c,
config/i386/i386-builtin-types.awk, config/i386/i386-protos.h,
config/i386/i386.c, config/i386/i386.md, config/i386/predicates.md,
config/i386/sse.md, config/i386/sync.md, config/ia64/ia64-protos.h,
config/ia64/ia64.c, config/iq2000/iq2000-protos.h,
config/iq2000/iq2000.c, config/iq2000/iq2000.md,
config/lm32/lm32-protos.h, config/lm32/lm32.c,
config/m32c/m32c-protos.h, config/m32c/m32c.c,
config/m32r/m32r-protos.h, config/m32r/m32r.c,
config/m68k/m68k-protos.h, config/m68k/m68k.c,
config/mcore/mcore-protos.h, config/mcore/mcore.c,
config/mcore/mcore.md, config/mep/mep-protos.h, config/mep/mep.c,
config/microblaze/microblaze-protos.h, config/microblaze/microblaze.c,
config/mips/mips-protos.h, config/mips/mips.c,
config/mmix/mmix-protos.h, config/mmix/mmix.c,
config/mn10300/mn10300-protos.h, config/mn10300/mn10300.c,
config/moxie/moxie.c, config/msp430/msp430-protos.h,
config/msp430/msp430.c, config/nds32/nds32-cost.c,
config/nds32/nds32-intrinsic.c, config/nds32/nds32-md-auxiliary.c,
config/nds32/nds32-protos.h, config/nds32/nds32.c,
config/nios2/nios2-protos.h, config/nios2/nios2.c,
config/pa/pa-protos.h, config/pa/pa.c, config/pdp11/pdp11-protos.h,
config/pdp11/pdp11.c, config/rl78/rl78-protos.h, config/rl78/rl78.c,
config/rs6000/altivec.md, config/rs6000/rs6000-c.c,
config/rs6000/rs6000-protos.h, config/rs6000/rs6000.c,
config/rs6000/rs6000.h, config/rx/rx-protos.h, config/rx/rx.c,
config/s390/predicates.md, config/s390/s390-protos.h,
config/s390/s390.c, config/s390/s390.h, config/s390/s390.md,
config/sh/predicates.md, config/sh/sh-protos.h, config/sh/sh.c,
config/sh/sh.md, config/sparc/predicates.md,
config/sparc/sparc-protos.h, config/sparc/sparc.c,
config/sparc/sparc.md, config/spu/spu-protos.h, config/spu/spu.c,
config/stormy16/stormy16-protos.h, config/stormy16/stormy16.c,
config/tilegx/tilegx-protos.h, config/tilegx/tilegx.c,
config/tilegx/tilegx.md, config/tilepro/tilepro-protos.h,
config/tilepro/tilepro.c, config/v850/v850-protos.h,
config/v850/v850.c, config/v850/v850.md, config/vax/vax-protos.h,
config/vax/vax.c, config/vms/vms-c.c, config/xtensa/xtensa-protos.h,
config/xtensa/xtensa.c, coverage.c, cprop.c, cse.c, cselib.c, cselib.h,
dbxout.c, ddg.c, df-problems.c, dfp.c, dfp.h, doc/md.texi,
doc/rtl.texi, doc/tm.texi, doc/tm.texi.in, dojump.c, dse.c,
dwarf2cfi.c, dwarf2out.c, dwarf2out.h, emit-rtl.c, emit-rtl.h,
except.c, explow.c, expmed.c, expmed.h, expr.c, expr.h, final.c,
fixed-value.c, fixed-value.h, fold-const.c, function.c, function.h,
fwprop.c, gcse.c, gengenrtl.c, genmodes.c, genopinit.c, genoutput.c,
genpreds.c, genrecog.c, gensupport.c, gimple-ssa-strength-reduction.c,
graphite-clast-to-gimple.c, haifa-sched.c, hooks.c, hooks.h, ifcvt.c,
internal-fn.c, ira-build.c, ira-color.c, ira-conflicts.c, ira-costs.c,
ira-emit.c, ira-int.h, ira-lives.c, ira.c, ira.h, jump.c, langhooks.h,
libfuncs.h, lists.c, loop-doloop.c, loop-invariant.c, loop-iv.c,
loop-unroll.c, lower-subreg.c, lower-subreg.h, lra-assigns.c,
lra-constraints.c, lra-eliminations.c, lra-int.h, lra-lives.c,
lra-spills.c, lra.c, lra.h, machmode.h, omp-low.c, optabs.c, optabs.h,
output.h, postreload.c, print-tree.c, read-rtl.c, real.c, real.h,
recog.c, recog.h, ree.c, reg-stack.c, regcprop.c, reginfo.c,
regrename.c, regs.h, reload.c, reload.h, reload1.c, rtl.c, rtl.h,
rtlanal.c, rtlhash.c, rtlhooks-def.h, rtlhooks.c, sched-deps.c,
sel-sched-dump.c, sel-sched-ir.c, sel-sched-ir.h, sel-sched.c,
simplify-rtx.c, stmt.c, stor-layout.c, stor-layout.h, target.def,
targhooks.c, targhooks.h, tree-affine.c, tree-call-cdce.c,
tree-complex.c, tree-data-ref.c, tree-dfa.c, tree-if-conv.c,
tree-inline.c, tree-outof-ssa.c, tree-scalar-evolution.c,
tree-ssa-address.c, tree-ssa-ccp.c, tree-ssa-loop-ivopts.c,
tree-ssa-loop-ivopts.h, tree-ssa-loop-manip.c,
tree-ssa-loop-prefetch.c, tree-ssa-math-opts.c, tree-ssa-reassoc.c,
tree-ssa-sccvn.c, tree-streamer-in.c, tree-switch-conversion.c,
tree-vect-data-refs.c, tree-vect-generic.c, tree-vect-loop.c,
tree-vect-patterns.c, tree-vect-slp.c, tree-vect-stmts.c,
tree-vrp.c, tree.c, tree.h, tsan.c, ubsan.c, valtrack.c,
var-tracking.c, varasm.c: Remove redundant enum from
machine_mode.
gcc/
* gengtype.c (main): Treat machine_mode as a scalar typedef.
* genmodes.c (emit_insn_modes_h): Hide inline functions if
USED_FOR_TARGET.
From-SVN: r216834
2014-10-29 13:02:45 +01:00
|
|
|
machine_mode mode;
|
2012-11-20 13:10:37 +01:00
|
|
|
const enum insn_code code;
|
|
|
|
unsigned int fcode;
|
2013-11-20 10:19:25 +01:00
|
|
|
enum aarch64_type_qualifiers *qualifiers;
|
2020-07-17 11:00:37 +02:00
|
|
|
unsigned int flags;
|
2012-10-23 19:02:30 +02:00
|
|
|
} aarch64_simd_builtin_datum;
|
|
|
|
|
2013-11-20 10:19:25 +01:00
|
|
|
static enum aarch64_type_qualifiers
|
|
|
|
aarch64_types_unop_qualifiers[SIMD_MAX_BUILTIN_ARGS]
|
2014-12-09 20:19:54 +01:00
|
|
|
= { qualifier_none, qualifier_none };
|
2013-11-20 10:19:25 +01:00
|
|
|
#define TYPES_UNOP (aarch64_types_unop_qualifiers)
|
Implement support for AArch64 Crypto AES.
gcc/
* config/aarch64/aarch64-simd-builtins.def: Update builtins table.
* config/aarch64/aarch64-builtins.c (aarch64_types_binopu_qualifiers,
TYPES_BINOPU): New.
* config/aarch64/aarch64-simd.md (aarch64_crypto_aes<aes_op>v16qi,
aarch64_crypto_aes<aesmc_op>v16qi): New.
* config/aarch64/arm_neon.h (vaeseq_u8, vaesdq_u8, vaesmcq_u8,
vaesimcq_u8): New.
* config/aarch64/iterators.md (UNSPEC_AESE, UNSPEC_AESD, UNSPEC_AESMC,
UNSPEC_AESIMC): New.
(CRYPTO_AES, CRYPTO_AESMC): New int iterators.
(aes_op, aesmc_op): New int attributes.
testsuite/
* gcc.target/aarch64/aes_1.c: New.
From-SVN: r206117
2013-12-19 15:51:28 +01:00
|
|
|
static enum aarch64_type_qualifiers
|
|
|
|
aarch64_types_unopu_qualifiers[SIMD_MAX_BUILTIN_ARGS]
|
|
|
|
= { qualifier_unsigned, qualifier_unsigned };
|
|
|
|
#define TYPES_UNOPU (aarch64_types_unopu_qualifiers)
|
2013-11-20 10:19:25 +01:00
|
|
|
static enum aarch64_type_qualifiers
|
2016-01-15 18:50:01 +01:00
|
|
|
aarch64_types_unopus_qualifiers[SIMD_MAX_BUILTIN_ARGS]
|
|
|
|
= { qualifier_unsigned, qualifier_none };
|
|
|
|
#define TYPES_UNOPUS (aarch64_types_unopus_qualifiers)
|
|
|
|
static enum aarch64_type_qualifiers
|
2013-11-20 10:19:25 +01:00
|
|
|
aarch64_types_binop_qualifiers[SIMD_MAX_BUILTIN_ARGS]
|
|
|
|
= { qualifier_none, qualifier_none, qualifier_maybe_immediate };
|
|
|
|
#define TYPES_BINOP (aarch64_types_binop_qualifiers)
|
|
|
|
static enum aarch64_type_qualifiers
|
Implement support for AArch64 Crypto AES.
gcc/
* config/aarch64/aarch64-simd-builtins.def: Update builtins table.
* config/aarch64/aarch64-builtins.c (aarch64_types_binopu_qualifiers,
TYPES_BINOPU): New.
* config/aarch64/aarch64-simd.md (aarch64_crypto_aes<aes_op>v16qi,
aarch64_crypto_aes<aesmc_op>v16qi): New.
* config/aarch64/arm_neon.h (vaeseq_u8, vaesdq_u8, vaesmcq_u8,
vaesimcq_u8): New.
* config/aarch64/iterators.md (UNSPEC_AESE, UNSPEC_AESD, UNSPEC_AESMC,
UNSPEC_AESIMC): New.
(CRYPTO_AES, CRYPTO_AESMC): New int iterators.
(aes_op, aesmc_op): New int attributes.
testsuite/
* gcc.target/aarch64/aes_1.c: New.
From-SVN: r206117
2013-12-19 15:51:28 +01:00
|
|
|
aarch64_types_binopu_qualifiers[SIMD_MAX_BUILTIN_ARGS]
|
|
|
|
= { qualifier_unsigned, qualifier_unsigned, qualifier_unsigned };
|
|
|
|
#define TYPES_BINOPU (aarch64_types_binopu_qualifiers)
|
2013-12-19 16:04:19 +01:00
|
|
|
static enum aarch64_type_qualifiers
|
[PATCH AArch64 1/2] Correct signedness of builtins, remove casts from arm_neon.h
* gcc/config/aarch64/aarch64-builtins.c
(aarch64_types_binop_uus_qualifiers,
aarch64_types_shift_to_unsigned_qualifiers,
aarch64_types_unsigned_shiftacc_qualifiers): Define.
* gcc/config/aarch64/aarch64-simd-builtins.def (uqshl, uqrshl, uqadd,
uqsub, usqadd, usra_n, ursra_n, uqshrn_n, uqrshrn_n, usri_n, usli_n,
sqshlu_n, uqshl_n): Update qualifiers.
* gcc/config/aarch64/arm_neon.h (vqadd_u8, vqadd_u16, vqadd_u32,
vqadd_u64, vqaddq_u8, vqaddq_u16, vqaddq_u32, vqaddq_u64, vqsub_u8,
vqsub_u16, vqsub_u32, vqsub_u64, vqsubq_u8, vqsubq_u16, vqsubq_u32,
vqsubq_u64, vqaddb_u8, vqaddh_u16, vqadds_u32, vqaddd_u64, vqrshl_u8,
vqrshl_u16, vqrshl_u32, vqrshl_u64, vqrshlq_u8, vqrshlq_u16,
vqrshlq_u32, vqrshlq_u64, vqrshlb_u8, vqrshlh_u16, vqrshls_u32,
vqrshld_u64, vqrshrn_n_u16, vqrshrn_n_u32, vqrshrn_n_u64,
vqrshrnh_n_u16, vqrshrns_n_u32, vqrshrnd_n_u64, vqshl_u8, vqshl_u16,
vqshl_u32, vqshl_u64, vqshlq_u8, vqshlq_u16, vqshlq_u32, vqshlq_u64,
vqshlb_u8, vqshlh_u16, vqshls_u32, vqshld_u64, vqshl_n_u8, vqshl_n_u16,
vqshl_n_u32, vqshl_n_u64, vqshlq_n_u8, vqshlq_n_u16, vqshlq_n_u32,
vqshlq_n_u64, vqshlb_n_u8, vqshlh_n_u16, vqshls_n_u32, vqshld_n_u64,
vqshlu_n_s8, vqshlu_n_s16, vqshlu_n_s32, vqshlu_n_s64, vqshluq_n_s8,
vqshluq_n_s16, vqshluq_n_s32, vqshluq_n_s64, vqshlub_n_s8,
vqshluh_n_s16, vqshlus_n_s32, vqshlud_n_s64, vqshrn_n_u16,
vqshrn_n_u32, vqshrn_n_u64, vqshrnh_n_u16, vqshrns_n_u32,
vqshrnd_n_u64, vqsubb_u8, vqsubh_u16, vqsubs_u32, vqsubd_u64,
vrsra_n_u8, vrsra_n_u16, vrsra_n_u32, vrsra_n_u64, vrsraq_n_u8,
vrsraq_n_u16, vrsraq_n_u32, vrsraq_n_u64, vrsrad_n_u64, vsli_n_u8,
vsli_n_u16, vsli_n_u32,vsli_n_u64, vsliq_n_u8, vsliq_n_u16,
vsliq_n_u32, vsliq_n_u64, vslid_n_u64, vsqadd_u8, vsqadd_u16,
vsqadd_u32, vsqadd_u64, vsqaddq_u8, vsqaddq_u16, vsqaddq_u32,
vsqaddq_u64, vsqaddb_u8, vsqaddh_u16, vsqadds_u32, vsqaddd_u64,
vsra_n_u8, vsra_n_u16, vsra_n_u32, vsra_n_u64, vsraq_n_u8,
vsraq_n_u16, vsraq_n_u32, vsraq_n_u64, vsrad_n_u64, vsri_n_u8,
vsri_n_u16, vsri_n_u32, vsri_n_u64, vsriq_n_u8, vsriq_n_u16,
vsriq_n_u32, vsriq_n_u64, vsrid_n_u64): Remove casts.
From-SVN: r211185
2014-06-03 16:57:22 +02:00
|
|
|
aarch64_types_binop_uus_qualifiers[SIMD_MAX_BUILTIN_ARGS]
|
|
|
|
= { qualifier_unsigned, qualifier_unsigned, qualifier_none };
|
|
|
|
#define TYPES_BINOP_UUS (aarch64_types_binop_uus_qualifiers)
|
|
|
|
static enum aarch64_type_qualifiers
|
[PATCH AArch64 2/2] Correct signedness of builtins, remove casts from arm_neon.h
* gcc/config/aarch64/aarch64-builtins.c
(aarch64_types_binop_ssu_qualifiers): New static data.
(TYPES_BINOP_SSU): Define.
* gcc/config/aarch64/aarch64-simd-builtins.def (suqadd, ushl, urshl,
urshr_n, ushll_n): Use appropriate unsigned qualifiers.
* gcc/config/aarch64/arm_neon.h (vrshl_u8, vrshl_u16, vrshl_u32,
vrshl_u64, vrshlq_u8, vrshlq_u16, vrshlq_u32, vrshlq_u64, vrshld_u64,
vrshr_n_u8, vrshr_n_u16, vrshr_n_u32, vrshr_n_u64, vrshrq_n_u8,
vrshrq_n_u16, vrshrq_n_u32, vrshrq_n_u64, vrshrd_n_u64, vshll_n_u8,
vshll_n_u16, vshll_n_u32, vuqadd_s8, vuqadd_s16, vuqadd_s32,
vuqadd_s64, vuqaddq_s8, vuqaddq_s16, vuqaddq_s32, vuqaddq_s64,
vuqaddb_s8, vuqaddh_s16, vuqadds_s32, vuqaddd_s64): Add signedness
suffix to builtin function name, remove cast.
(vshl_s8, vshl_s16, vshl_s32, vshl_s64, vshl_u8, vshl_u16, vshl_u32,
vshl_u64, vshlq_s8, vshlq_s16, vshlq_s32, vshlq_s64, vshlq_u8,
vshlq_u16, vshlq_u32, vshlq_u64, vshld_s64, vshld_u64): Remove cast.
From-SVN: r211186
2014-06-03 17:06:01 +02:00
|
|
|
aarch64_types_binop_ssu_qualifiers[SIMD_MAX_BUILTIN_ARGS]
|
|
|
|
= { qualifier_none, qualifier_none, qualifier_unsigned };
|
|
|
|
#define TYPES_BINOP_SSU (aarch64_types_binop_ssu_qualifiers)
|
|
|
|
static enum aarch64_type_qualifiers
|
[AArch64][2/10] ARMv8.2-A FP16 one operand vector intrinsics
gcc/
* config/aarch64/aarch64-builtins.c (TYPES_BINOP_USS): New.
* config/aarch64/aarch64-simd-builtins.def: Register new builtins.
* config/aarch64/aarch64-simd.md (aarch64_rsqrte<mode>): Extend to HF modes.
(neg<mode>2): Likewise.
(abs<mode>2): Likewise.
(<frint_pattern><mode>2): Likewise.
(l<fcvt_pattern><su_optab><VDQF:mode><fcvt_target>2): Likewise.
(<optab><VDQF:mode><fcvt_target>2): Likewise.
(<fix_trunc_optab><VDQF:mode><fcvt_target>2): Likewise.
(ftrunc<VDQF:mode>2): Likewise.
(<optab><fcvt_target><VDQF:mode>2): Likewise.
(sqrt<mode>2): Likewise.
(*sqrt<mode>2): Likewise.
(aarch64_frecpe<mode>): Likewise.
(aarch64_cm<optab><mode>): Likewise.
* config/aarch64/aarch64.c (aarch64_emit_approx_sqrt): Return
false for V4HF and V8HF.
* config/aarch64/iterators.md (VHSDF, VHSDF_DF, VHSDF_SDF): New.
(VDQF_COND, fcvt_target, FCVT_TARGET, hcon): Extend mode attribute to HF modes.
(stype): New.
* config/aarch64/arm_neon.h (vdup_n_f16): New.
(vdupq_n_f16): Likewise.
(vld1_dup_f16): Use vdup_n_f16.
(vld1q_dup_f16): Use vdupq_n_f16.
(vabs_f16): New.
(vabsq_f16, vceqz_f16, vceqzq_f16, vcgez_f16, vcgezq_f16, vcgtz_f16,
vcgtzq_f16, vclez_f16, vclezq_f16, vcltz_f16, vcltzq_f16, vcvt_f16_s16,
vcvtq_f16_s16, vcvt_f16_u16, vcvtq_f16_u16, vcvt_s16_f16, vcvtq_s16_f16,
vcvt_u16_f16, vcvtq_u16_f16, vcvta_s16_f16, vcvtaq_s16_f16,
vcvta_u16_f16, vcvtaq_u16_f16, vcvtm_s16_f16, vcvtmq_s16_f16,
vcvtm_u16_f16, vcvtmq_u16_f16, vcvtn_s16_f16, vcvtnq_s16_f16,
vcvtn_u16_f16, vcvtnq_u16_f16, vcvtp_s16_f16, vcvtpq_s16_f16,
vcvtp_u16_f16, vcvtpq_u16_f16, vneg_f16, vnegq_f16, vrecpe_f16,
vrecpeq_f16, vrnd_f16, vrndq_f16, vrnda_f16, vrndaq_f16, vrndi_f16,
vrndiq_f16, vrndm_f16, vrndmq_f16, vrndn_f16, vrndnq_f16, vrndp_f16,
vrndpq_f16, vrndx_f16, vrndxq_f16, vrsqrte_f16, vrsqrteq_f16, vsqrt_f16,
vsqrtq_f16): Likewise.
From-SVN: r238716
2016-07-25 16:20:37 +02:00
|
|
|
aarch64_types_binop_uss_qualifiers[SIMD_MAX_BUILTIN_ARGS]
|
|
|
|
= { qualifier_unsigned, qualifier_none, qualifier_none };
|
|
|
|
#define TYPES_BINOP_USS (aarch64_types_binop_uss_qualifiers)
|
|
|
|
static enum aarch64_type_qualifiers
|
2013-12-19 16:04:19 +01:00
|
|
|
aarch64_types_binopp_qualifiers[SIMD_MAX_BUILTIN_ARGS]
|
|
|
|
= { qualifier_poly, qualifier_poly, qualifier_poly };
|
|
|
|
#define TYPES_BINOPP (aarch64_types_binopp_qualifiers)
|
2021-09-23 15:27:22 +02:00
|
|
|
static enum aarch64_type_qualifiers
|
|
|
|
aarch64_types_binop_ppu_qualifiers[SIMD_MAX_BUILTIN_ARGS]
|
|
|
|
= { qualifier_poly, qualifier_poly, qualifier_unsigned };
|
|
|
|
#define TYPES_BINOP_PPU (aarch64_types_binop_ppu_qualifiers)
|
2013-12-19 16:04:19 +01:00
|
|
|
|
Implement support for AArch64 Crypto AES.
gcc/
* config/aarch64/aarch64-simd-builtins.def: Update builtins table.
* config/aarch64/aarch64-builtins.c (aarch64_types_binopu_qualifiers,
TYPES_BINOPU): New.
* config/aarch64/aarch64-simd.md (aarch64_crypto_aes<aes_op>v16qi,
aarch64_crypto_aes<aesmc_op>v16qi): New.
* config/aarch64/arm_neon.h (vaeseq_u8, vaesdq_u8, vaesmcq_u8,
vaesimcq_u8): New.
* config/aarch64/iterators.md (UNSPEC_AESE, UNSPEC_AESD, UNSPEC_AESMC,
UNSPEC_AESIMC): New.
(CRYPTO_AES, CRYPTO_AESMC): New int iterators.
(aes_op, aesmc_op): New int attributes.
testsuite/
* gcc.target/aarch64/aes_1.c: New.
From-SVN: r206117
2013-12-19 15:51:28 +01:00
|
|
|
static enum aarch64_type_qualifiers
|
2013-11-20 10:19:25 +01:00
|
|
|
aarch64_types_ternop_qualifiers[SIMD_MAX_BUILTIN_ARGS]
|
|
|
|
= { qualifier_none, qualifier_none, qualifier_none, qualifier_none };
|
|
|
|
#define TYPES_TERNOP (aarch64_types_ternop_qualifiers)
|
Implement support for AArch64 Crypto SHA1.
gcc/
* config/aarch64/aarch64-simd-builtins.def: Update builtins table.
* config/aarch64/aarch64-builtins.c (aarch64_types_ternopu_qualifiers,
TYPES_TERNOPU): New.
* config/aarch64/aarch64-simd.md (aarch64_crypto_sha1hsi,
aarch64_crypto_sha1su1v4si, aarch64_crypto_sha1<sha1_op>v4si,
aarch64_crypto_sha1su0v4si): New.
* config/aarch64/arm_neon.h (vsha1cq_u32, sha1mq_u32, vsha1pq_u32,
vsha1h_u32, vsha1su0q_u32, vsha1su1q_u32): New.
* config/aarch64/iterators.md (UNSPEC_SHA1<CPMH>, UNSPEC_SHA1SU<01>):
New.
(CRYPTO_SHA1): New int iterator.
(sha1_op): New int attribute.
testsuite/
* gcc.target/aarch64/sha1_1.c: New.
From-SVN: r206118
2013-12-19 15:55:47 +01:00
|
|
|
static enum aarch64_type_qualifiers
|
Add bounds checking to vqdm*_lane intrinsics via a qualifier that also flips endianness
gcc/:
* config/aarch64/aarch64.c (aarch64_simd_lane_bounds): Display indices.
* config/aarch64/aarch64-builtins.c (enum aarch64_type_qualifiers): Add
qualifier_lane_index.
(aarch64_types_ternop_lane_qualifiers, TYPES_TERNOP_LANE): Rename to...
(aarch64_types_quadop_lane_qualifiers, TYPES_QUADOP_LANE): ...these.
(aarch64_types_ternop_lane_qualifiers, TYPES_TERNOP_LANE): New.
(aarch64_types_getlane_qualifiers): Rename to...
(aarch64_types_binop_imm_qualifiers): ...this.
(TYPES_SHIFTIMM): Follow renaming.
(TYPES_GETLANE): Rename to...
(TYPE_GETREG): ...this.
(aarch64_types_setlane_qualifiers): Rename to...
(aarch64_type_ternop_imm_qualifiers): ...this.
(TYPES_SHIFTINSERT, TYPES_SHIFTACC): Follow renaming.
(TYPES_SETLANE): Follow renaming above, and rename self to...
(TYPE_SETREG): ...this.
(enum builtin_simd_arg): Add SIMD_ARG_LANE_INDEX.
(aarch64_simd_expand_args): Add range check and endianness-flip.
(aarch64_simd_expand_builtin): Add mapping for qualifier_lane_index.
* config/aarch64/aarch64-simd.md
(aarch64_sq<r>dmulh_lane<mode>_internal *2): Rename to...
(aarch64_sq<r>dmulh_lane<mode>): ...this, and remove lane bounds check.
(aarch64_sqdmulh_lane<mode> *2, aarch64_sqrdmulh_lane<mode> *2): Delete.
(aarch64_sq<r>dmulh_laneq<mode>_internal): Rename to...
(aarch64_sq<r>dmulh_lane<mode>): ...this.
(aarch64_sqdml<SBINQOPS:as>l_lane<mode>_internal *2): Rename to...
(aarch64_sqdml<SBINQOPS:as>l_lane<mode>): ...this.
(aarch64_sqdml<SBINQOPS:as>l_laneq<mode>_internal *2): Rename to...
(aarch64_sqdml<SBINQOPS:as>l_laneq<mode>): ...this.
(aarch64_sqdmull_lane<mode>_internal *2): Rename to...
(aarch64_sqdmull_lane<mode>): ...this.
(aarch64_sqdmull_laneq<mode>_internal *2): Rename to...
(aarch64_sqdmull_laneq<mode>): ...this.
(aarch64_sqdmulh_laneq<mode>, aarch64_sqrdmulh_laneq<mode>,
(aarch64_sqdmlal_lane<mode>, aarch64_sqdmlal_laneq<mode>,
aarch64_sqdmlsl_lane<mode>, aarch64_sqdmlsl_laneq<mode>,
aarch64_sqdmull_lane<mode>, aarch64_sqdmull_laneq<mode>): Delete.
(aarch64_sqdmlal2_lane<mode>, aarch64_sqdmlal2_laneq<mode>,
aarch64_sqdmlsl2_lane<mode>, aarch64_sqdmlsl2_laneq<mode>,
aarch64_sqdmull2_lane<mode>, aarch64_sqdmull2_laneq<mode>): Remove
bounds check and lane flip.
* config/aarch64/aarch64-simd-builtins.def (be_checked_get_lane,
get_dregoi, get_dregci, getdregxi, get_qregoi,get_qregci, get_qregxi,
set_qregoi, set_qregci, set_qregxi): Change qualifiers to GETREG.
(sqdmlal_lane, sqdmlsl_lane, sqdmlal_laneq, sqdmlsl_laneq,
sqdmlal2_lane, sqdmlsl2_lane, sqdmlal2_laneq, sqdmlsl2_laneq): Follow
renaming of TERNOP_LANE to QUADOP_LANE.
(sqdmull_lane, sqdmull_laneq, sqdmull2_lane, sqdmull2_laneq,
sqdmulh_lane, sqdmulh_laneq, sqrdmulh_lane, sqrdmulh_laneq): Set
qualifiers to TERNOP_LANE.
gcc/testsuite/:
* gcc.target/aarch64/simd/vqdmlal_high_lane_s16_indices_1.c: New test.
* gcc.target/aarch64/simd/vqdmlal_high_lane_s32_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqdmlal_high_laneq_s16_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqdmlal_high_laneq_s32_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqdmlal_lane_s16_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqdmlal_lane_s32_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqdmlal_laneq_s16_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqdmlal_laneq_s32_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqdmlalh_lane_s16_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqdmlals_lane_s32_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqdmlsl_high_lane_s16_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqdmlsl_high_lane_s32_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqdmlsl_high_laneq_s16_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqdmlsl_high_laneq_s32_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqdmlsl_lane_s16_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqdmlsl_lane_s32_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqdmlsl_laneq_s16_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqdmlsl_laneq_s32_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqdmlslh_lane_s16_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqdmlsls_lane_s32_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqdmulh_lane_s16_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqdmulh_lane_s32_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqdmulh_laneq_s16_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqdmulh_laneq_s32_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqdmulhh_lane_s16_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqdmulhq_lane_s16_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqdmulhq_lane_s32_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqdmulhq_laneq_s16_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqdmulhq_laneq_s32_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqdmulhs_lane_s32_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqdmull_high_lane_s16_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqdmull_high_lane_s32_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqdmull_high_laneq_s16_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqdmull_high_laneq_s32_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqdmull_lane_s16_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqdmull_lane_s32_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqdmull_laneq_s16_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqdmull_laneq_s32_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqdmullh_lane_s16_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqdmulls_lane_s32_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqrdmulh_lane_s16_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqrdmulh_lane_s32_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqrdmulh_laneq_s16_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqrdmulh_laneq_s32_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqrdmulhh_lane_s16_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqrdmulhq_lane_s16_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqrdmulhq_lane_s32_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqrdmulhq_laneq_s16_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqrdmulhq_laneq_s32_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqrdmulhs_lane_s32_indices_1.c: Likewise.
From-SVN: r217440
2014-11-12 19:51:53 +01:00
|
|
|
aarch64_types_ternop_lane_qualifiers[SIMD_MAX_BUILTIN_ARGS]
|
|
|
|
= { qualifier_none, qualifier_none, qualifier_none, qualifier_lane_index };
|
|
|
|
#define TYPES_TERNOP_LANE (aarch64_types_ternop_lane_qualifiers)
|
|
|
|
static enum aarch64_type_qualifiers
|
Implement support for AArch64 Crypto SHA1.
gcc/
* config/aarch64/aarch64-simd-builtins.def: Update builtins table.
* config/aarch64/aarch64-builtins.c (aarch64_types_ternopu_qualifiers,
TYPES_TERNOPU): New.
* config/aarch64/aarch64-simd.md (aarch64_crypto_sha1hsi,
aarch64_crypto_sha1su1v4si, aarch64_crypto_sha1<sha1_op>v4si,
aarch64_crypto_sha1su0v4si): New.
* config/aarch64/arm_neon.h (vsha1cq_u32, sha1mq_u32, vsha1pq_u32,
vsha1h_u32, vsha1su0q_u32, vsha1su1q_u32): New.
* config/aarch64/iterators.md (UNSPEC_SHA1<CPMH>, UNSPEC_SHA1SU<01>):
New.
(CRYPTO_SHA1): New int iterator.
(sha1_op): New int attribute.
testsuite/
* gcc.target/aarch64/sha1_1.c: New.
From-SVN: r206118
2013-12-19 15:55:47 +01:00
|
|
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aarch64_types_ternopu_qualifiers[SIMD_MAX_BUILTIN_ARGS]
|
|
|
|
= { qualifier_unsigned, qualifier_unsigned,
|
|
|
|
qualifier_unsigned, qualifier_unsigned };
|
|
|
|
#define TYPES_TERNOPU (aarch64_types_ternopu_qualifiers)
|
2018-01-11 07:04:17 +01:00
|
|
|
static enum aarch64_type_qualifiers
|
2020-03-06 19:29:02 +01:00
|
|
|
aarch64_types_ternopu_lane_qualifiers[SIMD_MAX_BUILTIN_ARGS]
|
|
|
|
= { qualifier_unsigned, qualifier_unsigned,
|
|
|
|
qualifier_unsigned, qualifier_lane_index };
|
|
|
|
#define TYPES_TERNOPU_LANE (aarch64_types_ternopu_lane_qualifiers)
|
|
|
|
static enum aarch64_type_qualifiers
|
2018-01-11 07:04:17 +01:00
|
|
|
aarch64_types_ternopu_imm_qualifiers[SIMD_MAX_BUILTIN_ARGS]
|
|
|
|
= { qualifier_unsigned, qualifier_unsigned,
|
|
|
|
qualifier_unsigned, qualifier_immediate };
|
|
|
|
#define TYPES_TERNOPUI (aarch64_types_ternopu_imm_qualifiers)
|
2020-01-16 15:20:48 +01:00
|
|
|
static enum aarch64_type_qualifiers
|
2021-09-23 15:27:22 +02:00
|
|
|
aarch64_types_ternop_sssu_qualifiers[SIMD_MAX_BUILTIN_ARGS]
|
|
|
|
= { qualifier_none, qualifier_none, qualifier_none, qualifier_unsigned };
|
|
|
|
#define TYPES_TERNOP_SSSU (aarch64_types_ternop_sssu_qualifiers)
|
|
|
|
static enum aarch64_type_qualifiers
|
2020-01-16 15:20:48 +01:00
|
|
|
aarch64_types_ternop_ssus_qualifiers[SIMD_MAX_BUILTIN_ARGS]
|
|
|
|
= { qualifier_none, qualifier_none, qualifier_unsigned, qualifier_none };
|
|
|
|
#define TYPES_TERNOP_SSUS (aarch64_types_ternop_ssus_qualifiers)
|
2021-07-26 11:22:23 +02:00
|
|
|
static enum aarch64_type_qualifiers
|
|
|
|
aarch64_types_ternop_suss_qualifiers[SIMD_MAX_BUILTIN_ARGS]
|
|
|
|
= { qualifier_none, qualifier_unsigned, qualifier_none, qualifier_none };
|
|
|
|
#define TYPES_TERNOP_SUSS (aarch64_types_ternop_suss_qualifiers)
|
2021-09-23 15:27:22 +02:00
|
|
|
static enum aarch64_type_qualifiers
|
|
|
|
aarch64_types_binop_pppu_qualifiers[SIMD_MAX_BUILTIN_ARGS]
|
|
|
|
= { qualifier_poly, qualifier_poly, qualifier_poly, qualifier_unsigned };
|
|
|
|
#define TYPES_TERNOP_PPPU (aarch64_types_binop_pppu_qualifiers)
|
2018-01-11 07:04:17 +01:00
|
|
|
|
aarch64-builtins.c (enum aarch64_type_qualifiers): Add qualifier_lane_pair_index.
gcc/ChangeLog:
2019-01-10 Tamar Christina <tamar.christina@arm.com>
* config/aarch64/aarch64-builtins.c (enum aarch64_type_qualifiers): Add qualifier_lane_pair_index.
(emit-rtl.h): Include.
(TYPES_QUADOP_LANE_PAIR): New.
(aarch64_simd_expand_args): Use it.
(aarch64_simd_expand_builtin): Likewise.
(AARCH64_SIMD_FCMLA_LANEQ_BUILTINS, aarch64_fcmla_laneq_builtin_datum): New.
(FCMLA_LANEQ_BUILTIN, AARCH64_SIMD_FCMLA_LANEQ_BUILTIN_BASE,
AARCH64_SIMD_FCMLA_LANEQ_BUILTINS, aarch64_fcmla_lane_builtin_data,
aarch64_init_fcmla_laneq_builtins, aarch64_expand_fcmla_builtin): New.
(aarch64_init_builtins): Add aarch64_init_fcmla_laneq_builtins.
(aarch64_expand_buildin): Add AARCH64_SIMD_BUILTIN_FCMLA_LANEQ0_V2SF,
AARCH64_SIMD_BUILTIN_FCMLA_LANEQ90_V2SF, AARCH64_SIMD_BUILTIN_FCMLA_LANEQ180_V2SF,
AARCH64_SIMD_BUILTIN_FCMLA_LANEQ2700_V2SF, AARCH64_SIMD_BUILTIN_FCMLA_LANEQ0_V4HF,
AARCH64_SIMD_BUILTIN_FCMLA_LANEQ90_V4HF, AARCH64_SIMD_BUILTIN_FCMLA_LANEQ180_V4HF,
AARCH64_SIMD_BUILTIN_FCMLA_LANEQ270_V4HF.
* config/aarch64/iterators.md (FCMLA_maybe_lane): New.
* config/aarch64/aarch64-c.c (aarch64_update_cpp_builtins): Add __ARM_FEATURE_COMPLEX.
* config/aarch64/aarch64-simd-builtins.def (fcadd90, fcadd270, fcmla0, fcmla90,
fcmla180, fcmla270, fcmla_lane0, fcmla_lane90, fcmla_lane180, fcmla_lane270,
fcmla_laneq0, fcmla_laneq90, fcmla_laneq180, fcmla_laneq270,
fcmlaq_lane0, fcmlaq_lane90, fcmlaq_lane180, fcmlaq_lane270): New.
* config/aarch64/aarch64-simd.md (aarch64_fcmla_lane<rot><mode>,
aarch64_fcmla_laneq<rot>v4hf, aarch64_fcmlaq_lane<rot><mode>,aarch64_fcadd<rot><mode>,
aarch64_fcmla<rot><mode>): New.
* config/aarch64/arm_neon.h:
(vcadd_rot90_f16): New.
(vcaddq_rot90_f16): New.
(vcadd_rot270_f16): New.
(vcaddq_rot270_f16): New.
(vcmla_f16): New.
(vcmlaq_f16): New.
(vcmla_lane_f16): New.
(vcmla_laneq_f16): New.
(vcmlaq_lane_f16): New.
(vcmlaq_rot90_lane_f16): New.
(vcmla_rot90_laneq_f16): New.
(vcmla_rot90_lane_f16): New.
(vcmlaq_rot90_f16): New.
(vcmla_rot90_f16): New.
(vcmlaq_laneq_f16): New.
(vcmla_rot180_laneq_f16): New.
(vcmla_rot180_lane_f16): New.
(vcmlaq_rot180_f16): New.
(vcmla_rot180_f16): New.
(vcmlaq_rot90_laneq_f16): New.
(vcmlaq_rot270_laneq_f16): New.
(vcmlaq_rot270_lane_f16): New.
(vcmla_rot270_laneq_f16): New.
(vcmlaq_rot270_f16): New.
(vcmla_rot270_f16): New.
(vcmlaq_rot180_laneq_f16): New.
(vcmlaq_rot180_lane_f16): New.
(vcmla_rot270_lane_f16): New.
(vcadd_rot90_f32): New.
(vcaddq_rot90_f32): New.
(vcaddq_rot90_f64): New.
(vcadd_rot270_f32): New.
(vcaddq_rot270_f32): New.
(vcaddq_rot270_f64): New.
(vcmla_f32): New.
(vcmlaq_f32): New.
(vcmlaq_f64): New.
(vcmla_lane_f32): New.
(vcmla_laneq_f32): New.
(vcmlaq_lane_f32): New.
(vcmlaq_laneq_f32): New.
(vcmla_rot90_f32): New.
(vcmlaq_rot90_f32): New.
(vcmlaq_rot90_f64): New.
(vcmla_rot90_lane_f32): New.
(vcmla_rot90_laneq_f32): New.
(vcmlaq_rot90_lane_f32): New.
(vcmlaq_rot90_laneq_f32): New.
(vcmla_rot180_f32): New.
(vcmlaq_rot180_f32): New.
(vcmlaq_rot180_f64): New.
(vcmla_rot180_lane_f32): New.
(vcmla_rot180_laneq_f32): New.
(vcmlaq_rot180_lane_f32): New.
(vcmlaq_rot180_laneq_f32): New.
(vcmla_rot270_f32): New.
(vcmlaq_rot270_f32): New.
(vcmlaq_rot270_f64): New.
(vcmla_rot270_lane_f32): New.
(vcmla_rot270_laneq_f32): New.
(vcmlaq_rot270_lane_f32): New.
(vcmlaq_rot270_laneq_f32): New.
* config/aarch64/aarch64.h (TARGET_COMPLEX): New.
* config/aarch64/iterators.md (UNSPEC_FCADD90, UNSPEC_FCADD270,
UNSPEC_FCMLA, UNSPEC_FCMLA90, UNSPEC_FCMLA180, UNSPEC_FCMLA270): New.
(FCADD, FCMLA): New.
(rot): New.
* config/arm/types.md (neon_fcadd, neon_fcmla): New.
gcc/testsuite/ChangeLog:
2019-01-10 Tamar Christina <tamar.christina@arm.com>
* gcc.target/aarch64/advsimd-intrinsics/vector-complex.c: New test.
* gcc.target/aarch64/advsimd-intrinsics/vector-complex_f16.c: New test.
From-SVN: r267795
2019-01-10 04:30:59 +01:00
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|
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static enum aarch64_type_qualifiers
|
|
|
|
aarch64_types_quadop_lane_pair_qualifiers[SIMD_MAX_BUILTIN_ARGS]
|
|
|
|
= { qualifier_none, qualifier_none, qualifier_none,
|
|
|
|
qualifier_none, qualifier_lane_pair_index };
|
|
|
|
#define TYPES_QUADOP_LANE_PAIR (aarch64_types_quadop_lane_pair_qualifiers)
|
2013-11-20 10:19:25 +01:00
|
|
|
static enum aarch64_type_qualifiers
|
Add bounds checking to vqdm*_lane intrinsics via a qualifier that also flips endianness
gcc/:
* config/aarch64/aarch64.c (aarch64_simd_lane_bounds): Display indices.
* config/aarch64/aarch64-builtins.c (enum aarch64_type_qualifiers): Add
qualifier_lane_index.
(aarch64_types_ternop_lane_qualifiers, TYPES_TERNOP_LANE): Rename to...
(aarch64_types_quadop_lane_qualifiers, TYPES_QUADOP_LANE): ...these.
(aarch64_types_ternop_lane_qualifiers, TYPES_TERNOP_LANE): New.
(aarch64_types_getlane_qualifiers): Rename to...
(aarch64_types_binop_imm_qualifiers): ...this.
(TYPES_SHIFTIMM): Follow renaming.
(TYPES_GETLANE): Rename to...
(TYPE_GETREG): ...this.
(aarch64_types_setlane_qualifiers): Rename to...
(aarch64_type_ternop_imm_qualifiers): ...this.
(TYPES_SHIFTINSERT, TYPES_SHIFTACC): Follow renaming.
(TYPES_SETLANE): Follow renaming above, and rename self to...
(TYPE_SETREG): ...this.
(enum builtin_simd_arg): Add SIMD_ARG_LANE_INDEX.
(aarch64_simd_expand_args): Add range check and endianness-flip.
(aarch64_simd_expand_builtin): Add mapping for qualifier_lane_index.
* config/aarch64/aarch64-simd.md
(aarch64_sq<r>dmulh_lane<mode>_internal *2): Rename to...
(aarch64_sq<r>dmulh_lane<mode>): ...this, and remove lane bounds check.
(aarch64_sqdmulh_lane<mode> *2, aarch64_sqrdmulh_lane<mode> *2): Delete.
(aarch64_sq<r>dmulh_laneq<mode>_internal): Rename to...
(aarch64_sq<r>dmulh_lane<mode>): ...this.
(aarch64_sqdml<SBINQOPS:as>l_lane<mode>_internal *2): Rename to...
(aarch64_sqdml<SBINQOPS:as>l_lane<mode>): ...this.
(aarch64_sqdml<SBINQOPS:as>l_laneq<mode>_internal *2): Rename to...
(aarch64_sqdml<SBINQOPS:as>l_laneq<mode>): ...this.
(aarch64_sqdmull_lane<mode>_internal *2): Rename to...
(aarch64_sqdmull_lane<mode>): ...this.
(aarch64_sqdmull_laneq<mode>_internal *2): Rename to...
(aarch64_sqdmull_laneq<mode>): ...this.
(aarch64_sqdmulh_laneq<mode>, aarch64_sqrdmulh_laneq<mode>,
(aarch64_sqdmlal_lane<mode>, aarch64_sqdmlal_laneq<mode>,
aarch64_sqdmlsl_lane<mode>, aarch64_sqdmlsl_laneq<mode>,
aarch64_sqdmull_lane<mode>, aarch64_sqdmull_laneq<mode>): Delete.
(aarch64_sqdmlal2_lane<mode>, aarch64_sqdmlal2_laneq<mode>,
aarch64_sqdmlsl2_lane<mode>, aarch64_sqdmlsl2_laneq<mode>,
aarch64_sqdmull2_lane<mode>, aarch64_sqdmull2_laneq<mode>): Remove
bounds check and lane flip.
* config/aarch64/aarch64-simd-builtins.def (be_checked_get_lane,
get_dregoi, get_dregci, getdregxi, get_qregoi,get_qregci, get_qregxi,
set_qregoi, set_qregci, set_qregxi): Change qualifiers to GETREG.
(sqdmlal_lane, sqdmlsl_lane, sqdmlal_laneq, sqdmlsl_laneq,
sqdmlal2_lane, sqdmlsl2_lane, sqdmlal2_laneq, sqdmlsl2_laneq): Follow
renaming of TERNOP_LANE to QUADOP_LANE.
(sqdmull_lane, sqdmull_laneq, sqdmull2_lane, sqdmull2_laneq,
sqdmulh_lane, sqdmulh_laneq, sqrdmulh_lane, sqrdmulh_laneq): Set
qualifiers to TERNOP_LANE.
gcc/testsuite/:
* gcc.target/aarch64/simd/vqdmlal_high_lane_s16_indices_1.c: New test.
* gcc.target/aarch64/simd/vqdmlal_high_lane_s32_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqdmlal_high_laneq_s16_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqdmlal_high_laneq_s32_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqdmlal_lane_s16_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqdmlal_lane_s32_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqdmlal_laneq_s16_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqdmlal_laneq_s32_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqdmlalh_lane_s16_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqdmlals_lane_s32_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqdmlsl_high_lane_s16_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqdmlsl_high_lane_s32_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqdmlsl_high_laneq_s16_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqdmlsl_high_laneq_s32_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqdmlsl_lane_s16_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqdmlsl_lane_s32_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqdmlsl_laneq_s16_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqdmlsl_laneq_s32_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqdmlslh_lane_s16_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqdmlsls_lane_s32_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqdmulh_lane_s16_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqdmulh_lane_s32_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqdmulh_laneq_s16_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqdmulh_laneq_s32_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqdmulhh_lane_s16_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqdmulhq_lane_s16_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqdmulhq_lane_s32_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqdmulhq_laneq_s16_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqdmulhq_laneq_s32_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqdmulhs_lane_s32_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqdmull_high_lane_s16_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqdmull_high_lane_s32_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqdmull_high_laneq_s16_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqdmull_high_laneq_s32_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqdmull_lane_s16_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqdmull_lane_s32_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqdmull_laneq_s16_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqdmull_laneq_s32_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqdmullh_lane_s16_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqdmulls_lane_s32_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqrdmulh_lane_s16_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqrdmulh_lane_s32_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqrdmulh_laneq_s16_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqrdmulh_laneq_s32_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqrdmulhh_lane_s16_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqrdmulhq_lane_s16_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqrdmulhq_lane_s32_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqrdmulhq_laneq_s16_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqrdmulhq_laneq_s32_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqrdmulhs_lane_s32_indices_1.c: Likewise.
From-SVN: r217440
2014-11-12 19:51:53 +01:00
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aarch64_types_quadop_lane_qualifiers[SIMD_MAX_BUILTIN_ARGS]
|
2013-11-20 10:19:25 +01:00
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|
|
= { qualifier_none, qualifier_none, qualifier_none,
|
Add bounds checking to vqdm*_lane intrinsics via a qualifier that also flips endianness
gcc/:
* config/aarch64/aarch64.c (aarch64_simd_lane_bounds): Display indices.
* config/aarch64/aarch64-builtins.c (enum aarch64_type_qualifiers): Add
qualifier_lane_index.
(aarch64_types_ternop_lane_qualifiers, TYPES_TERNOP_LANE): Rename to...
(aarch64_types_quadop_lane_qualifiers, TYPES_QUADOP_LANE): ...these.
(aarch64_types_ternop_lane_qualifiers, TYPES_TERNOP_LANE): New.
(aarch64_types_getlane_qualifiers): Rename to...
(aarch64_types_binop_imm_qualifiers): ...this.
(TYPES_SHIFTIMM): Follow renaming.
(TYPES_GETLANE): Rename to...
(TYPE_GETREG): ...this.
(aarch64_types_setlane_qualifiers): Rename to...
(aarch64_type_ternop_imm_qualifiers): ...this.
(TYPES_SHIFTINSERT, TYPES_SHIFTACC): Follow renaming.
(TYPES_SETLANE): Follow renaming above, and rename self to...
(TYPE_SETREG): ...this.
(enum builtin_simd_arg): Add SIMD_ARG_LANE_INDEX.
(aarch64_simd_expand_args): Add range check and endianness-flip.
(aarch64_simd_expand_builtin): Add mapping for qualifier_lane_index.
* config/aarch64/aarch64-simd.md
(aarch64_sq<r>dmulh_lane<mode>_internal *2): Rename to...
(aarch64_sq<r>dmulh_lane<mode>): ...this, and remove lane bounds check.
(aarch64_sqdmulh_lane<mode> *2, aarch64_sqrdmulh_lane<mode> *2): Delete.
(aarch64_sq<r>dmulh_laneq<mode>_internal): Rename to...
(aarch64_sq<r>dmulh_lane<mode>): ...this.
(aarch64_sqdml<SBINQOPS:as>l_lane<mode>_internal *2): Rename to...
(aarch64_sqdml<SBINQOPS:as>l_lane<mode>): ...this.
(aarch64_sqdml<SBINQOPS:as>l_laneq<mode>_internal *2): Rename to...
(aarch64_sqdml<SBINQOPS:as>l_laneq<mode>): ...this.
(aarch64_sqdmull_lane<mode>_internal *2): Rename to...
(aarch64_sqdmull_lane<mode>): ...this.
(aarch64_sqdmull_laneq<mode>_internal *2): Rename to...
(aarch64_sqdmull_laneq<mode>): ...this.
(aarch64_sqdmulh_laneq<mode>, aarch64_sqrdmulh_laneq<mode>,
(aarch64_sqdmlal_lane<mode>, aarch64_sqdmlal_laneq<mode>,
aarch64_sqdmlsl_lane<mode>, aarch64_sqdmlsl_laneq<mode>,
aarch64_sqdmull_lane<mode>, aarch64_sqdmull_laneq<mode>): Delete.
(aarch64_sqdmlal2_lane<mode>, aarch64_sqdmlal2_laneq<mode>,
aarch64_sqdmlsl2_lane<mode>, aarch64_sqdmlsl2_laneq<mode>,
aarch64_sqdmull2_lane<mode>, aarch64_sqdmull2_laneq<mode>): Remove
bounds check and lane flip.
* config/aarch64/aarch64-simd-builtins.def (be_checked_get_lane,
get_dregoi, get_dregci, getdregxi, get_qregoi,get_qregci, get_qregxi,
set_qregoi, set_qregci, set_qregxi): Change qualifiers to GETREG.
(sqdmlal_lane, sqdmlsl_lane, sqdmlal_laneq, sqdmlsl_laneq,
sqdmlal2_lane, sqdmlsl2_lane, sqdmlal2_laneq, sqdmlsl2_laneq): Follow
renaming of TERNOP_LANE to QUADOP_LANE.
(sqdmull_lane, sqdmull_laneq, sqdmull2_lane, sqdmull2_laneq,
sqdmulh_lane, sqdmulh_laneq, sqrdmulh_lane, sqrdmulh_laneq): Set
qualifiers to TERNOP_LANE.
gcc/testsuite/:
* gcc.target/aarch64/simd/vqdmlal_high_lane_s16_indices_1.c: New test.
* gcc.target/aarch64/simd/vqdmlal_high_lane_s32_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqdmlal_high_laneq_s16_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqdmlal_high_laneq_s32_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqdmlal_lane_s16_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqdmlal_lane_s32_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqdmlal_laneq_s16_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqdmlal_laneq_s32_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqdmlalh_lane_s16_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqdmlals_lane_s32_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqdmlsl_high_lane_s16_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqdmlsl_high_lane_s32_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqdmlsl_high_laneq_s16_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqdmlsl_high_laneq_s32_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqdmlsl_lane_s16_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqdmlsl_lane_s32_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqdmlsl_laneq_s16_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqdmlsl_laneq_s32_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqdmlslh_lane_s16_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqdmlsls_lane_s32_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqdmulh_lane_s16_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqdmulh_lane_s32_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqdmulh_laneq_s16_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqdmulh_laneq_s32_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqdmulhh_lane_s16_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqdmulhq_lane_s16_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqdmulhq_lane_s32_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqdmulhq_laneq_s16_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqdmulhq_laneq_s32_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqdmulhs_lane_s32_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqdmull_high_lane_s16_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqdmull_high_lane_s32_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqdmull_high_laneq_s16_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqdmull_high_laneq_s32_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqdmull_lane_s16_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqdmull_lane_s32_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqdmull_laneq_s16_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqdmull_laneq_s32_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqdmullh_lane_s16_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqdmulls_lane_s32_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqrdmulh_lane_s16_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqrdmulh_lane_s32_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqrdmulh_laneq_s16_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqrdmulh_laneq_s32_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqrdmulhh_lane_s16_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqrdmulhq_lane_s16_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqrdmulhq_lane_s32_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqrdmulhq_laneq_s16_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqrdmulhq_laneq_s32_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqrdmulhs_lane_s32_indices_1.c: Likewise.
From-SVN: r217440
2014-11-12 19:51:53 +01:00
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qualifier_none, qualifier_lane_index };
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#define TYPES_QUADOP_LANE (aarch64_types_quadop_lane_qualifiers)
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2017-10-16 11:56:41 +02:00
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static enum aarch64_type_qualifiers
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aarch64_types_quadopu_lane_qualifiers[SIMD_MAX_BUILTIN_ARGS]
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= { qualifier_unsigned, qualifier_unsigned, qualifier_unsigned,
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qualifier_unsigned, qualifier_lane_index };
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#define TYPES_QUADOPU_LANE (aarch64_types_quadopu_lane_qualifiers)
|
2013-11-20 10:19:25 +01:00
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2020-01-16 15:20:48 +01:00
|
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static enum aarch64_type_qualifiers
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aarch64_types_quadopssus_lane_quadtup_qualifiers[SIMD_MAX_BUILTIN_ARGS]
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= { qualifier_none, qualifier_none, qualifier_unsigned,
|
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qualifier_none, qualifier_lane_quadtup_index };
|
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#define TYPES_QUADOPSSUS_LANE_QUADTUP \
|
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(aarch64_types_quadopssus_lane_quadtup_qualifiers)
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static enum aarch64_type_qualifiers
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|
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aarch64_types_quadopsssu_lane_quadtup_qualifiers[SIMD_MAX_BUILTIN_ARGS]
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|
= { qualifier_none, qualifier_none, qualifier_none,
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|
|
qualifier_unsigned, qualifier_lane_quadtup_index };
|
|
|
|
#define TYPES_QUADOPSSSU_LANE_QUADTUP \
|
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|
(aarch64_types_quadopsssu_lane_quadtup_qualifiers)
|
|
|
|
|
2018-01-11 07:04:17 +01:00
|
|
|
static enum aarch64_type_qualifiers
|
|
|
|
aarch64_types_quadopu_imm_qualifiers[SIMD_MAX_BUILTIN_ARGS]
|
|
|
|
= { qualifier_unsigned, qualifier_unsigned, qualifier_unsigned,
|
|
|
|
qualifier_unsigned, qualifier_immediate };
|
|
|
|
#define TYPES_QUADOPUI (aarch64_types_quadopu_imm_qualifiers)
|
|
|
|
|
2013-11-20 10:19:25 +01:00
|
|
|
static enum aarch64_type_qualifiers
|
Add bounds checking to vqdm*_lane intrinsics via a qualifier that also flips endianness
gcc/:
* config/aarch64/aarch64.c (aarch64_simd_lane_bounds): Display indices.
* config/aarch64/aarch64-builtins.c (enum aarch64_type_qualifiers): Add
qualifier_lane_index.
(aarch64_types_ternop_lane_qualifiers, TYPES_TERNOP_LANE): Rename to...
(aarch64_types_quadop_lane_qualifiers, TYPES_QUADOP_LANE): ...these.
(aarch64_types_ternop_lane_qualifiers, TYPES_TERNOP_LANE): New.
(aarch64_types_getlane_qualifiers): Rename to...
(aarch64_types_binop_imm_qualifiers): ...this.
(TYPES_SHIFTIMM): Follow renaming.
(TYPES_GETLANE): Rename to...
(TYPE_GETREG): ...this.
(aarch64_types_setlane_qualifiers): Rename to...
(aarch64_type_ternop_imm_qualifiers): ...this.
(TYPES_SHIFTINSERT, TYPES_SHIFTACC): Follow renaming.
(TYPES_SETLANE): Follow renaming above, and rename self to...
(TYPE_SETREG): ...this.
(enum builtin_simd_arg): Add SIMD_ARG_LANE_INDEX.
(aarch64_simd_expand_args): Add range check and endianness-flip.
(aarch64_simd_expand_builtin): Add mapping for qualifier_lane_index.
* config/aarch64/aarch64-simd.md
(aarch64_sq<r>dmulh_lane<mode>_internal *2): Rename to...
(aarch64_sq<r>dmulh_lane<mode>): ...this, and remove lane bounds check.
(aarch64_sqdmulh_lane<mode> *2, aarch64_sqrdmulh_lane<mode> *2): Delete.
(aarch64_sq<r>dmulh_laneq<mode>_internal): Rename to...
(aarch64_sq<r>dmulh_lane<mode>): ...this.
(aarch64_sqdml<SBINQOPS:as>l_lane<mode>_internal *2): Rename to...
(aarch64_sqdml<SBINQOPS:as>l_lane<mode>): ...this.
(aarch64_sqdml<SBINQOPS:as>l_laneq<mode>_internal *2): Rename to...
(aarch64_sqdml<SBINQOPS:as>l_laneq<mode>): ...this.
(aarch64_sqdmull_lane<mode>_internal *2): Rename to...
(aarch64_sqdmull_lane<mode>): ...this.
(aarch64_sqdmull_laneq<mode>_internal *2): Rename to...
(aarch64_sqdmull_laneq<mode>): ...this.
(aarch64_sqdmulh_laneq<mode>, aarch64_sqrdmulh_laneq<mode>,
(aarch64_sqdmlal_lane<mode>, aarch64_sqdmlal_laneq<mode>,
aarch64_sqdmlsl_lane<mode>, aarch64_sqdmlsl_laneq<mode>,
aarch64_sqdmull_lane<mode>, aarch64_sqdmull_laneq<mode>): Delete.
(aarch64_sqdmlal2_lane<mode>, aarch64_sqdmlal2_laneq<mode>,
aarch64_sqdmlsl2_lane<mode>, aarch64_sqdmlsl2_laneq<mode>,
aarch64_sqdmull2_lane<mode>, aarch64_sqdmull2_laneq<mode>): Remove
bounds check and lane flip.
* config/aarch64/aarch64-simd-builtins.def (be_checked_get_lane,
get_dregoi, get_dregci, getdregxi, get_qregoi,get_qregci, get_qregxi,
set_qregoi, set_qregci, set_qregxi): Change qualifiers to GETREG.
(sqdmlal_lane, sqdmlsl_lane, sqdmlal_laneq, sqdmlsl_laneq,
sqdmlal2_lane, sqdmlsl2_lane, sqdmlal2_laneq, sqdmlsl2_laneq): Follow
renaming of TERNOP_LANE to QUADOP_LANE.
(sqdmull_lane, sqdmull_laneq, sqdmull2_lane, sqdmull2_laneq,
sqdmulh_lane, sqdmulh_laneq, sqrdmulh_lane, sqrdmulh_laneq): Set
qualifiers to TERNOP_LANE.
gcc/testsuite/:
* gcc.target/aarch64/simd/vqdmlal_high_lane_s16_indices_1.c: New test.
* gcc.target/aarch64/simd/vqdmlal_high_lane_s32_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqdmlal_high_laneq_s16_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqdmlal_high_laneq_s32_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqdmlal_lane_s16_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqdmlal_lane_s32_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqdmlal_laneq_s16_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqdmlal_laneq_s32_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqdmlalh_lane_s16_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqdmlals_lane_s32_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqdmlsl_high_lane_s16_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqdmlsl_high_lane_s32_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqdmlsl_high_laneq_s16_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqdmlsl_high_laneq_s32_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqdmlsl_lane_s16_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqdmlsl_lane_s32_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqdmlsl_laneq_s16_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqdmlsl_laneq_s32_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqdmlslh_lane_s16_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqdmlsls_lane_s32_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqdmulh_lane_s16_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqdmulh_lane_s32_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqdmulh_laneq_s16_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqdmulh_laneq_s32_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqdmulhh_lane_s16_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqdmulhq_lane_s16_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqdmulhq_lane_s32_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqdmulhq_laneq_s16_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqdmulhq_laneq_s32_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqdmulhs_lane_s32_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqdmull_high_lane_s16_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqdmull_high_lane_s32_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqdmull_high_laneq_s16_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqdmull_high_laneq_s32_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqdmull_lane_s16_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqdmull_lane_s32_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqdmull_laneq_s16_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqdmull_laneq_s32_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqdmullh_lane_s16_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqdmulls_lane_s32_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqrdmulh_lane_s16_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqrdmulh_lane_s32_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqrdmulh_laneq_s16_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqrdmulh_laneq_s32_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqrdmulhh_lane_s16_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqrdmulhq_lane_s16_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqrdmulhq_lane_s32_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqrdmulhq_laneq_s16_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqrdmulhq_laneq_s32_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqrdmulhs_lane_s32_indices_1.c: Likewise.
From-SVN: r217440
2014-11-12 19:51:53 +01:00
|
|
|
aarch64_types_binop_imm_qualifiers[SIMD_MAX_BUILTIN_ARGS]
|
2013-11-20 10:19:25 +01:00
|
|
|
= { qualifier_none, qualifier_none, qualifier_immediate };
|
Add bounds checking to vqdm*_lane intrinsics via a qualifier that also flips endianness
gcc/:
* config/aarch64/aarch64.c (aarch64_simd_lane_bounds): Display indices.
* config/aarch64/aarch64-builtins.c (enum aarch64_type_qualifiers): Add
qualifier_lane_index.
(aarch64_types_ternop_lane_qualifiers, TYPES_TERNOP_LANE): Rename to...
(aarch64_types_quadop_lane_qualifiers, TYPES_QUADOP_LANE): ...these.
(aarch64_types_ternop_lane_qualifiers, TYPES_TERNOP_LANE): New.
(aarch64_types_getlane_qualifiers): Rename to...
(aarch64_types_binop_imm_qualifiers): ...this.
(TYPES_SHIFTIMM): Follow renaming.
(TYPES_GETLANE): Rename to...
(TYPE_GETREG): ...this.
(aarch64_types_setlane_qualifiers): Rename to...
(aarch64_type_ternop_imm_qualifiers): ...this.
(TYPES_SHIFTINSERT, TYPES_SHIFTACC): Follow renaming.
(TYPES_SETLANE): Follow renaming above, and rename self to...
(TYPE_SETREG): ...this.
(enum builtin_simd_arg): Add SIMD_ARG_LANE_INDEX.
(aarch64_simd_expand_args): Add range check and endianness-flip.
(aarch64_simd_expand_builtin): Add mapping for qualifier_lane_index.
* config/aarch64/aarch64-simd.md
(aarch64_sq<r>dmulh_lane<mode>_internal *2): Rename to...
(aarch64_sq<r>dmulh_lane<mode>): ...this, and remove lane bounds check.
(aarch64_sqdmulh_lane<mode> *2, aarch64_sqrdmulh_lane<mode> *2): Delete.
(aarch64_sq<r>dmulh_laneq<mode>_internal): Rename to...
(aarch64_sq<r>dmulh_lane<mode>): ...this.
(aarch64_sqdml<SBINQOPS:as>l_lane<mode>_internal *2): Rename to...
(aarch64_sqdml<SBINQOPS:as>l_lane<mode>): ...this.
(aarch64_sqdml<SBINQOPS:as>l_laneq<mode>_internal *2): Rename to...
(aarch64_sqdml<SBINQOPS:as>l_laneq<mode>): ...this.
(aarch64_sqdmull_lane<mode>_internal *2): Rename to...
(aarch64_sqdmull_lane<mode>): ...this.
(aarch64_sqdmull_laneq<mode>_internal *2): Rename to...
(aarch64_sqdmull_laneq<mode>): ...this.
(aarch64_sqdmulh_laneq<mode>, aarch64_sqrdmulh_laneq<mode>,
(aarch64_sqdmlal_lane<mode>, aarch64_sqdmlal_laneq<mode>,
aarch64_sqdmlsl_lane<mode>, aarch64_sqdmlsl_laneq<mode>,
aarch64_sqdmull_lane<mode>, aarch64_sqdmull_laneq<mode>): Delete.
(aarch64_sqdmlal2_lane<mode>, aarch64_sqdmlal2_laneq<mode>,
aarch64_sqdmlsl2_lane<mode>, aarch64_sqdmlsl2_laneq<mode>,
aarch64_sqdmull2_lane<mode>, aarch64_sqdmull2_laneq<mode>): Remove
bounds check and lane flip.
* config/aarch64/aarch64-simd-builtins.def (be_checked_get_lane,
get_dregoi, get_dregci, getdregxi, get_qregoi,get_qregci, get_qregxi,
set_qregoi, set_qregci, set_qregxi): Change qualifiers to GETREG.
(sqdmlal_lane, sqdmlsl_lane, sqdmlal_laneq, sqdmlsl_laneq,
sqdmlal2_lane, sqdmlsl2_lane, sqdmlal2_laneq, sqdmlsl2_laneq): Follow
renaming of TERNOP_LANE to QUADOP_LANE.
(sqdmull_lane, sqdmull_laneq, sqdmull2_lane, sqdmull2_laneq,
sqdmulh_lane, sqdmulh_laneq, sqrdmulh_lane, sqrdmulh_laneq): Set
qualifiers to TERNOP_LANE.
gcc/testsuite/:
* gcc.target/aarch64/simd/vqdmlal_high_lane_s16_indices_1.c: New test.
* gcc.target/aarch64/simd/vqdmlal_high_lane_s32_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqdmlal_high_laneq_s16_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqdmlal_high_laneq_s32_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqdmlal_lane_s16_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqdmlal_lane_s32_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqdmlal_laneq_s16_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqdmlal_laneq_s32_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqdmlalh_lane_s16_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqdmlals_lane_s32_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqdmlsl_high_lane_s16_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqdmlsl_high_lane_s32_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqdmlsl_high_laneq_s16_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqdmlsl_high_laneq_s32_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqdmlsl_lane_s16_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqdmlsl_lane_s32_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqdmlsl_laneq_s16_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqdmlsl_laneq_s32_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqdmlslh_lane_s16_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqdmlsls_lane_s32_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqdmulh_lane_s16_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqdmulh_lane_s32_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqdmulh_laneq_s16_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqdmulh_laneq_s32_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqdmulhh_lane_s16_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqdmulhq_lane_s16_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqdmulhq_lane_s32_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqdmulhq_laneq_s16_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqdmulhq_laneq_s32_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqdmulhs_lane_s32_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqdmull_high_lane_s16_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqdmull_high_lane_s32_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqdmull_high_laneq_s16_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqdmull_high_laneq_s32_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqdmull_lane_s16_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqdmull_lane_s32_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqdmull_laneq_s16_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqdmull_laneq_s32_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqdmullh_lane_s16_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqdmulls_lane_s32_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqrdmulh_lane_s16_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqrdmulh_lane_s32_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqrdmulh_laneq_s16_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqrdmulh_laneq_s32_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqrdmulhh_lane_s16_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqrdmulhq_lane_s16_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqrdmulhq_lane_s32_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqrdmulhq_laneq_s16_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqrdmulhq_laneq_s32_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqrdmulhs_lane_s32_indices_1.c: Likewise.
From-SVN: r217440
2014-11-12 19:51:53 +01:00
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#define TYPES_GETREG (aarch64_types_binop_imm_qualifiers)
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#define TYPES_SHIFTIMM (aarch64_types_binop_imm_qualifiers)
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2013-11-20 10:19:25 +01:00
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static enum aarch64_type_qualifiers
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[PATCH AArch64 1/2] Correct signedness of builtins, remove casts from arm_neon.h
* gcc/config/aarch64/aarch64-builtins.c
(aarch64_types_binop_uus_qualifiers,
aarch64_types_shift_to_unsigned_qualifiers,
aarch64_types_unsigned_shiftacc_qualifiers): Define.
* gcc/config/aarch64/aarch64-simd-builtins.def (uqshl, uqrshl, uqadd,
uqsub, usqadd, usra_n, ursra_n, uqshrn_n, uqrshrn_n, usri_n, usli_n,
sqshlu_n, uqshl_n): Update qualifiers.
* gcc/config/aarch64/arm_neon.h (vqadd_u8, vqadd_u16, vqadd_u32,
vqadd_u64, vqaddq_u8, vqaddq_u16, vqaddq_u32, vqaddq_u64, vqsub_u8,
vqsub_u16, vqsub_u32, vqsub_u64, vqsubq_u8, vqsubq_u16, vqsubq_u32,
vqsubq_u64, vqaddb_u8, vqaddh_u16, vqadds_u32, vqaddd_u64, vqrshl_u8,
vqrshl_u16, vqrshl_u32, vqrshl_u64, vqrshlq_u8, vqrshlq_u16,
vqrshlq_u32, vqrshlq_u64, vqrshlb_u8, vqrshlh_u16, vqrshls_u32,
vqrshld_u64, vqrshrn_n_u16, vqrshrn_n_u32, vqrshrn_n_u64,
vqrshrnh_n_u16, vqrshrns_n_u32, vqrshrnd_n_u64, vqshl_u8, vqshl_u16,
vqshl_u32, vqshl_u64, vqshlq_u8, vqshlq_u16, vqshlq_u32, vqshlq_u64,
vqshlb_u8, vqshlh_u16, vqshls_u32, vqshld_u64, vqshl_n_u8, vqshl_n_u16,
vqshl_n_u32, vqshl_n_u64, vqshlq_n_u8, vqshlq_n_u16, vqshlq_n_u32,
vqshlq_n_u64, vqshlb_n_u8, vqshlh_n_u16, vqshls_n_u32, vqshld_n_u64,
vqshlu_n_s8, vqshlu_n_s16, vqshlu_n_s32, vqshlu_n_s64, vqshluq_n_s8,
vqshluq_n_s16, vqshluq_n_s32, vqshluq_n_s64, vqshlub_n_s8,
vqshluh_n_s16, vqshlus_n_s32, vqshlud_n_s64, vqshrn_n_u16,
vqshrn_n_u32, vqshrn_n_u64, vqshrnh_n_u16, vqshrns_n_u32,
vqshrnd_n_u64, vqsubb_u8, vqsubh_u16, vqsubs_u32, vqsubd_u64,
vrsra_n_u8, vrsra_n_u16, vrsra_n_u32, vrsra_n_u64, vrsraq_n_u8,
vrsraq_n_u16, vrsraq_n_u32, vrsraq_n_u64, vrsrad_n_u64, vsli_n_u8,
vsli_n_u16, vsli_n_u32,vsli_n_u64, vsliq_n_u8, vsliq_n_u16,
vsliq_n_u32, vsliq_n_u64, vslid_n_u64, vsqadd_u8, vsqadd_u16,
vsqadd_u32, vsqadd_u64, vsqaddq_u8, vsqaddq_u16, vsqaddq_u32,
vsqaddq_u64, vsqaddb_u8, vsqaddh_u16, vsqadds_u32, vsqaddd_u64,
vsra_n_u8, vsra_n_u16, vsra_n_u32, vsra_n_u64, vsraq_n_u8,
vsraq_n_u16, vsraq_n_u32, vsraq_n_u64, vsrad_n_u64, vsri_n_u8,
vsri_n_u16, vsri_n_u32, vsri_n_u64, vsriq_n_u8, vsriq_n_u16,
vsriq_n_u32, vsriq_n_u64, vsrid_n_u64): Remove casts.
From-SVN: r211185
2014-06-03 16:57:22 +02:00
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aarch64_types_shift_to_unsigned_qualifiers[SIMD_MAX_BUILTIN_ARGS]
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= { qualifier_unsigned, qualifier_none, qualifier_immediate };
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#define TYPES_SHIFTIMM_USS (aarch64_types_shift_to_unsigned_qualifiers)
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static enum aarch64_type_qualifiers
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2016-06-20 15:40:07 +02:00
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aarch64_types_fcvt_from_unsigned_qualifiers[SIMD_MAX_BUILTIN_ARGS]
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= { qualifier_none, qualifier_unsigned, qualifier_immediate };
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#define TYPES_FCVTIMM_SUS (aarch64_types_fcvt_from_unsigned_qualifiers)
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static enum aarch64_type_qualifiers
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2014-03-24 13:05:38 +01:00
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aarch64_types_unsigned_shift_qualifiers[SIMD_MAX_BUILTIN_ARGS]
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= { qualifier_unsigned, qualifier_unsigned, qualifier_immediate };
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#define TYPES_USHIFTIMM (aarch64_types_unsigned_shift_qualifiers)
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2020-11-06 18:53:03 +01:00
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#define TYPES_USHIFT2IMM (aarch64_types_ternopu_imm_qualifiers)
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static enum aarch64_type_qualifiers
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aarch64_types_shift2_to_unsigned_qualifiers[SIMD_MAX_BUILTIN_ARGS]
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= { qualifier_unsigned, qualifier_unsigned, qualifier_none, qualifier_immediate };
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#define TYPES_SHIFT2IMM_UUSS (aarch64_types_shift2_to_unsigned_qualifiers)
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[PATCH AArch64 1/2] Correct signedness of builtins, remove casts from arm_neon.h
* gcc/config/aarch64/aarch64-builtins.c
(aarch64_types_binop_uus_qualifiers,
aarch64_types_shift_to_unsigned_qualifiers,
aarch64_types_unsigned_shiftacc_qualifiers): Define.
* gcc/config/aarch64/aarch64-simd-builtins.def (uqshl, uqrshl, uqadd,
uqsub, usqadd, usra_n, ursra_n, uqshrn_n, uqrshrn_n, usri_n, usli_n,
sqshlu_n, uqshl_n): Update qualifiers.
* gcc/config/aarch64/arm_neon.h (vqadd_u8, vqadd_u16, vqadd_u32,
vqadd_u64, vqaddq_u8, vqaddq_u16, vqaddq_u32, vqaddq_u64, vqsub_u8,
vqsub_u16, vqsub_u32, vqsub_u64, vqsubq_u8, vqsubq_u16, vqsubq_u32,
vqsubq_u64, vqaddb_u8, vqaddh_u16, vqadds_u32, vqaddd_u64, vqrshl_u8,
vqrshl_u16, vqrshl_u32, vqrshl_u64, vqrshlq_u8, vqrshlq_u16,
vqrshlq_u32, vqrshlq_u64, vqrshlb_u8, vqrshlh_u16, vqrshls_u32,
vqrshld_u64, vqrshrn_n_u16, vqrshrn_n_u32, vqrshrn_n_u64,
vqrshrnh_n_u16, vqrshrns_n_u32, vqrshrnd_n_u64, vqshl_u8, vqshl_u16,
vqshl_u32, vqshl_u64, vqshlq_u8, vqshlq_u16, vqshlq_u32, vqshlq_u64,
vqshlb_u8, vqshlh_u16, vqshls_u32, vqshld_u64, vqshl_n_u8, vqshl_n_u16,
vqshl_n_u32, vqshl_n_u64, vqshlq_n_u8, vqshlq_n_u16, vqshlq_n_u32,
vqshlq_n_u64, vqshlb_n_u8, vqshlh_n_u16, vqshls_n_u32, vqshld_n_u64,
vqshlu_n_s8, vqshlu_n_s16, vqshlu_n_s32, vqshlu_n_s64, vqshluq_n_s8,
vqshluq_n_s16, vqshluq_n_s32, vqshluq_n_s64, vqshlub_n_s8,
vqshluh_n_s16, vqshlus_n_s32, vqshlud_n_s64, vqshrn_n_u16,
vqshrn_n_u32, vqshrn_n_u64, vqshrnh_n_u16, vqshrns_n_u32,
vqshrnd_n_u64, vqsubb_u8, vqsubh_u16, vqsubs_u32, vqsubd_u64,
vrsra_n_u8, vrsra_n_u16, vrsra_n_u32, vrsra_n_u64, vrsraq_n_u8,
vrsraq_n_u16, vrsraq_n_u32, vrsraq_n_u64, vrsrad_n_u64, vsli_n_u8,
vsli_n_u16, vsli_n_u32,vsli_n_u64, vsliq_n_u8, vsliq_n_u16,
vsliq_n_u32, vsliq_n_u64, vslid_n_u64, vsqadd_u8, vsqadd_u16,
vsqadd_u32, vsqadd_u64, vsqaddq_u8, vsqaddq_u16, vsqaddq_u32,
vsqaddq_u64, vsqaddb_u8, vsqaddh_u16, vsqadds_u32, vsqaddd_u64,
vsra_n_u8, vsra_n_u16, vsra_n_u32, vsra_n_u64, vsraq_n_u8,
vsraq_n_u16, vsraq_n_u32, vsraq_n_u64, vsrad_n_u64, vsri_n_u8,
vsri_n_u16, vsri_n_u32, vsri_n_u64, vsriq_n_u8, vsriq_n_u16,
vsriq_n_u32, vsriq_n_u64, vsrid_n_u64): Remove casts.
From-SVN: r211185
2014-06-03 16:57:22 +02:00
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aarch64-builtins.c (TYPES_SETREGP): Added poly type.
2016-11-28 Tamar Christina <tamar.christina@arm.com>
* config/aarch64/aarch64-builtins.c (TYPES_SETREGP): Added poly type.
(TYPES_GETREGP): Likewise.
(TYPES_SHIFTINSERTP): Likewise.
(TYPES_COMBINEP): Likewise.
(TYPES_STORE1P): Likewise.
* config/aarch64/aarch64-simd-builtins.def
(combine): Added poly generator.
(get_dregoi): Likewise.
(get_dregci): Likewise.
(get_dregxi): Likewise.
(ssli_n): Likewise.
(ld1): Likewise.
(st1): Likewise.
* config/aarch64/arm_neon.h
(poly64x1x2_t, poly64x1x3_t): New.
(poly64x1x4_t, poly64x2x2_t): Likewise.
(poly64x2x3_t, poly64x2x4_t): Likewise.
(poly64x1_t): Likewise.
(vcreate_p64, vcombine_p64): Likewise.
(vdup_n_p64, vdupq_n_p64): Likewise.
(vld2_p64, vld2q_p64): Likewise.
(vld3_p64, vld3q_p64): Likewise.
(vld4_p64, vld4q_p64): Likewise.
(vld2_dup_p64, vld3_dup_p64): Likewise.
(vld4_dup_p64, vsli_n_p64): Likewise.
(vsliq_n_p64, vst1_p64): Likewise.
(vst1q_p64, vst2_p64): Likewise.
(vst3_p64, vst4_p64): Likewise.
(__aarch64_vdup_lane_p64, __aarch64_vdup_laneq_p64): Likewise.
(__aarch64_vdupq_lane_p64, __aarch64_vdupq_laneq_p64): Likewise.
(vget_lane_p64, vgetq_lane_p64): Likewise.
(vreinterpret_p8_p64, vreinterpretq_p8_p64): Likewise.
(vreinterpret_p16_p64, vreinterpretq_p16_p64): Likewise.
(vreinterpret_p64_f16, vreinterpret_p64_f64): Likewise.
(vreinterpret_p64_s8, vreinterpret_p64_s16): Likewise.
(vreinterpret_p64_s32, vreinterpret_p64_s64): Likewise.
(vreinterpret_p64_f32, vreinterpret_p64_u8): Likewise.
(vreinterpret_p64_u16, vreinterpret_p64_u32): Likewise.
(vreinterpret_p64_u64, vreinterpret_p64_p8): Likewise.
(vreinterpretq_p64_f64, vreinterpretq_p64_s8): Likewise.
(vreinterpretq_p64_s16, vreinterpretq_p64_s32): Likewise.
(vreinterpretq_p64_s64, vreinterpretq_p64_f16): Likewise.
(vreinterpretq_p64_f32, vreinterpretq_p64_u8): Likewise.
(vreinterpretq_p64_u16, vreinterpretq_p64_u32): Likewise.
(vreinterpretq_p64_u64, vreinterpretq_p64_p8): Likewise.
(vreinterpret_f16_p64, vreinterpretq_f16_p64): Likewise.
(vreinterpret_f32_p64, vreinterpretq_f32_p64): Likewise.
(vreinterpret_f64_p64, vreinterpretq_f64_p64): Likewise.
(vreinterpret_s64_p64, vreinterpretq_s64_p64): Likewise.
(vreinterpret_u64_p64, vreinterpretq_u64_p64): Likewise.
(vreinterpret_s8_p64, vreinterpretq_s8_p64): Likewise.
(vreinterpret_s16_p64, vreinterpret_s32_p64): Likewise.
(vreinterpretq_s32_p64, vreinterpret_u8_p64): Likewise.
(vreinterpret_u16_p64, vreinterpretq_u16_p64): Likewise.
(vreinterpret_u32_p64, vreinterpretq_u32_p64): Likewise.
(vset_lane_p64, vsetq_lane_p64): Likewise.
(vget_low_p64, vget_high_p64): Likewise.
(vcombine_p64, vst2_lane_p64): Likewise.
(vst3_lane_p64, vst4_lane_p64): Likewise.
(vst2q_lane_p64, vst3q_lane_p64): Likewise.
(vst4q_lane_p64, vget_lane_p64): Likewise.
(vget_laneq_p64, vset_lane_p64): Likewise.
(vset_laneq_p64, vcopy_lane_p64): Likewise.
(vcopy_laneq_p64, vdup_n_p64): Likewise.
(vdupq_n_p64, vdup_lane_p64): Likewise.
(vdup_laneq_p64, vld1_p64): Likewise.
(vld1q_p64, vld1_dup_p64): Likewise.
(vld1q_dup_p64, vld1q_dup_p64): Likewise.
(vmov_n_p64, vmovq_n_p64): Likewise.
(vst3q_p64, vst4q_p64): Likewise.
(vld1_lane_p64, vld1q_lane_p64): Likewise.
(vst1_lane_p64, vst1q_lane_p64): Likewise.
(vcopy_laneq_p64, vcopyq_laneq_p64): Likewise.
(vdupq_laneq_p64): Likewise.
From-SVN: r242915
2016-11-28 13:41:03 +01:00
|
|
|
static enum aarch64_type_qualifiers
|
|
|
|
aarch64_types_ternop_s_imm_qualifiers[SIMD_MAX_BUILTIN_ARGS]
|
|
|
|
= { qualifier_none, qualifier_none, qualifier_none, qualifier_immediate};
|
|
|
|
#define TYPES_SETREG (aarch64_types_ternop_s_imm_qualifiers)
|
|
|
|
#define TYPES_SHIFTINSERT (aarch64_types_ternop_s_imm_qualifiers)
|
|
|
|
#define TYPES_SHIFTACC (aarch64_types_ternop_s_imm_qualifiers)
|
2020-11-06 18:53:03 +01:00
|
|
|
#define TYPES_SHIFT2IMM (aarch64_types_ternop_s_imm_qualifiers)
|
aarch64-builtins.c (TYPES_SETREGP): Added poly type.
2016-11-28 Tamar Christina <tamar.christina@arm.com>
* config/aarch64/aarch64-builtins.c (TYPES_SETREGP): Added poly type.
(TYPES_GETREGP): Likewise.
(TYPES_SHIFTINSERTP): Likewise.
(TYPES_COMBINEP): Likewise.
(TYPES_STORE1P): Likewise.
* config/aarch64/aarch64-simd-builtins.def
(combine): Added poly generator.
(get_dregoi): Likewise.
(get_dregci): Likewise.
(get_dregxi): Likewise.
(ssli_n): Likewise.
(ld1): Likewise.
(st1): Likewise.
* config/aarch64/arm_neon.h
(poly64x1x2_t, poly64x1x3_t): New.
(poly64x1x4_t, poly64x2x2_t): Likewise.
(poly64x2x3_t, poly64x2x4_t): Likewise.
(poly64x1_t): Likewise.
(vcreate_p64, vcombine_p64): Likewise.
(vdup_n_p64, vdupq_n_p64): Likewise.
(vld2_p64, vld2q_p64): Likewise.
(vld3_p64, vld3q_p64): Likewise.
(vld4_p64, vld4q_p64): Likewise.
(vld2_dup_p64, vld3_dup_p64): Likewise.
(vld4_dup_p64, vsli_n_p64): Likewise.
(vsliq_n_p64, vst1_p64): Likewise.
(vst1q_p64, vst2_p64): Likewise.
(vst3_p64, vst4_p64): Likewise.
(__aarch64_vdup_lane_p64, __aarch64_vdup_laneq_p64): Likewise.
(__aarch64_vdupq_lane_p64, __aarch64_vdupq_laneq_p64): Likewise.
(vget_lane_p64, vgetq_lane_p64): Likewise.
(vreinterpret_p8_p64, vreinterpretq_p8_p64): Likewise.
(vreinterpret_p16_p64, vreinterpretq_p16_p64): Likewise.
(vreinterpret_p64_f16, vreinterpret_p64_f64): Likewise.
(vreinterpret_p64_s8, vreinterpret_p64_s16): Likewise.
(vreinterpret_p64_s32, vreinterpret_p64_s64): Likewise.
(vreinterpret_p64_f32, vreinterpret_p64_u8): Likewise.
(vreinterpret_p64_u16, vreinterpret_p64_u32): Likewise.
(vreinterpret_p64_u64, vreinterpret_p64_p8): Likewise.
(vreinterpretq_p64_f64, vreinterpretq_p64_s8): Likewise.
(vreinterpretq_p64_s16, vreinterpretq_p64_s32): Likewise.
(vreinterpretq_p64_s64, vreinterpretq_p64_f16): Likewise.
(vreinterpretq_p64_f32, vreinterpretq_p64_u8): Likewise.
(vreinterpretq_p64_u16, vreinterpretq_p64_u32): Likewise.
(vreinterpretq_p64_u64, vreinterpretq_p64_p8): Likewise.
(vreinterpret_f16_p64, vreinterpretq_f16_p64): Likewise.
(vreinterpret_f32_p64, vreinterpretq_f32_p64): Likewise.
(vreinterpret_f64_p64, vreinterpretq_f64_p64): Likewise.
(vreinterpret_s64_p64, vreinterpretq_s64_p64): Likewise.
(vreinterpret_u64_p64, vreinterpretq_u64_p64): Likewise.
(vreinterpret_s8_p64, vreinterpretq_s8_p64): Likewise.
(vreinterpret_s16_p64, vreinterpret_s32_p64): Likewise.
(vreinterpretq_s32_p64, vreinterpret_u8_p64): Likewise.
(vreinterpret_u16_p64, vreinterpretq_u16_p64): Likewise.
(vreinterpret_u32_p64, vreinterpretq_u32_p64): Likewise.
(vset_lane_p64, vsetq_lane_p64): Likewise.
(vget_low_p64, vget_high_p64): Likewise.
(vcombine_p64, vst2_lane_p64): Likewise.
(vst3_lane_p64, vst4_lane_p64): Likewise.
(vst2q_lane_p64, vst3q_lane_p64): Likewise.
(vst4q_lane_p64, vget_lane_p64): Likewise.
(vget_laneq_p64, vset_lane_p64): Likewise.
(vset_laneq_p64, vcopy_lane_p64): Likewise.
(vcopy_laneq_p64, vdup_n_p64): Likewise.
(vdupq_n_p64, vdup_lane_p64): Likewise.
(vdup_laneq_p64, vld1_p64): Likewise.
(vld1q_p64, vld1_dup_p64): Likewise.
(vld1q_dup_p64, vld1q_dup_p64): Likewise.
(vmov_n_p64, vmovq_n_p64): Likewise.
(vst3q_p64, vst4q_p64): Likewise.
(vld1_lane_p64, vld1q_lane_p64): Likewise.
(vst1_lane_p64, vst1q_lane_p64): Likewise.
(vcopy_laneq_p64, vcopyq_laneq_p64): Likewise.
(vdupq_laneq_p64): Likewise.
From-SVN: r242915
2016-11-28 13:41:03 +01:00
|
|
|
|
|
|
|
static enum aarch64_type_qualifiers
|
|
|
|
aarch64_types_ternop_p_imm_qualifiers[SIMD_MAX_BUILTIN_ARGS]
|
|
|
|
= { qualifier_poly, qualifier_poly, qualifier_poly, qualifier_immediate};
|
|
|
|
#define TYPES_SHIFTINSERTP (aarch64_types_ternop_p_imm_qualifiers)
|
2013-11-20 10:19:25 +01:00
|
|
|
|
[PATCH AArch64 1/2] Correct signedness of builtins, remove casts from arm_neon.h
* gcc/config/aarch64/aarch64-builtins.c
(aarch64_types_binop_uus_qualifiers,
aarch64_types_shift_to_unsigned_qualifiers,
aarch64_types_unsigned_shiftacc_qualifiers): Define.
* gcc/config/aarch64/aarch64-simd-builtins.def (uqshl, uqrshl, uqadd,
uqsub, usqadd, usra_n, ursra_n, uqshrn_n, uqrshrn_n, usri_n, usli_n,
sqshlu_n, uqshl_n): Update qualifiers.
* gcc/config/aarch64/arm_neon.h (vqadd_u8, vqadd_u16, vqadd_u32,
vqadd_u64, vqaddq_u8, vqaddq_u16, vqaddq_u32, vqaddq_u64, vqsub_u8,
vqsub_u16, vqsub_u32, vqsub_u64, vqsubq_u8, vqsubq_u16, vqsubq_u32,
vqsubq_u64, vqaddb_u8, vqaddh_u16, vqadds_u32, vqaddd_u64, vqrshl_u8,
vqrshl_u16, vqrshl_u32, vqrshl_u64, vqrshlq_u8, vqrshlq_u16,
vqrshlq_u32, vqrshlq_u64, vqrshlb_u8, vqrshlh_u16, vqrshls_u32,
vqrshld_u64, vqrshrn_n_u16, vqrshrn_n_u32, vqrshrn_n_u64,
vqrshrnh_n_u16, vqrshrns_n_u32, vqrshrnd_n_u64, vqshl_u8, vqshl_u16,
vqshl_u32, vqshl_u64, vqshlq_u8, vqshlq_u16, vqshlq_u32, vqshlq_u64,
vqshlb_u8, vqshlh_u16, vqshls_u32, vqshld_u64, vqshl_n_u8, vqshl_n_u16,
vqshl_n_u32, vqshl_n_u64, vqshlq_n_u8, vqshlq_n_u16, vqshlq_n_u32,
vqshlq_n_u64, vqshlb_n_u8, vqshlh_n_u16, vqshls_n_u32, vqshld_n_u64,
vqshlu_n_s8, vqshlu_n_s16, vqshlu_n_s32, vqshlu_n_s64, vqshluq_n_s8,
vqshluq_n_s16, vqshluq_n_s32, vqshluq_n_s64, vqshlub_n_s8,
vqshluh_n_s16, vqshlus_n_s32, vqshlud_n_s64, vqshrn_n_u16,
vqshrn_n_u32, vqshrn_n_u64, vqshrnh_n_u16, vqshrns_n_u32,
vqshrnd_n_u64, vqsubb_u8, vqsubh_u16, vqsubs_u32, vqsubd_u64,
vrsra_n_u8, vrsra_n_u16, vrsra_n_u32, vrsra_n_u64, vrsraq_n_u8,
vrsraq_n_u16, vrsraq_n_u32, vrsraq_n_u64, vrsrad_n_u64, vsli_n_u8,
vsli_n_u16, vsli_n_u32,vsli_n_u64, vsliq_n_u8, vsliq_n_u16,
vsliq_n_u32, vsliq_n_u64, vslid_n_u64, vsqadd_u8, vsqadd_u16,
vsqadd_u32, vsqadd_u64, vsqaddq_u8, vsqaddq_u16, vsqaddq_u32,
vsqaddq_u64, vsqaddb_u8, vsqaddh_u16, vsqadds_u32, vsqaddd_u64,
vsra_n_u8, vsra_n_u16, vsra_n_u32, vsra_n_u64, vsraq_n_u8,
vsraq_n_u16, vsraq_n_u32, vsraq_n_u64, vsrad_n_u64, vsri_n_u8,
vsri_n_u16, vsri_n_u32, vsri_n_u64, vsriq_n_u8, vsriq_n_u16,
vsriq_n_u32, vsriq_n_u64, vsrid_n_u64): Remove casts.
From-SVN: r211185
2014-06-03 16:57:22 +02:00
|
|
|
static enum aarch64_type_qualifiers
|
|
|
|
aarch64_types_unsigned_shiftacc_qualifiers[SIMD_MAX_BUILTIN_ARGS]
|
|
|
|
= { qualifier_unsigned, qualifier_unsigned, qualifier_unsigned,
|
|
|
|
qualifier_immediate };
|
|
|
|
#define TYPES_USHIFTACC (aarch64_types_unsigned_shiftacc_qualifiers)
|
|
|
|
|
2013-11-20 10:19:25 +01:00
|
|
|
static enum aarch64_type_qualifiers
|
|
|
|
aarch64_types_load1_qualifiers[SIMD_MAX_BUILTIN_ARGS]
|
|
|
|
= { qualifier_none, qualifier_const_pointer_map_mode };
|
|
|
|
#define TYPES_LOAD1 (aarch64_types_load1_qualifiers)
|
|
|
|
#define TYPES_LOADSTRUCT (aarch64_types_load1_qualifiers)
|
2021-08-09 16:26:48 +02:00
|
|
|
static enum aarch64_type_qualifiers
|
|
|
|
aarch64_types_load1_u_qualifiers[SIMD_MAX_BUILTIN_ARGS]
|
|
|
|
= { qualifier_unsigned, qualifier_const_pointer_map_mode };
|
2021-11-10 11:49:19 +01:00
|
|
|
#define TYPES_LOAD1_U (aarch64_types_load1_u_qualifiers)
|
2021-08-09 16:26:48 +02:00
|
|
|
#define TYPES_LOADSTRUCT_U (aarch64_types_load1_u_qualifiers)
|
|
|
|
static enum aarch64_type_qualifiers
|
|
|
|
aarch64_types_load1_p_qualifiers[SIMD_MAX_BUILTIN_ARGS]
|
|
|
|
= { qualifier_poly, qualifier_const_pointer_map_mode };
|
2021-11-10 11:49:19 +01:00
|
|
|
#define TYPES_LOAD1_P (aarch64_types_load1_p_qualifiers)
|
2021-08-09 16:26:48 +02:00
|
|
|
#define TYPES_LOADSTRUCT_P (aarch64_types_load1_p_qualifiers)
|
|
|
|
|
2014-10-24 16:58:51 +02:00
|
|
|
static enum aarch64_type_qualifiers
|
|
|
|
aarch64_types_loadstruct_lane_qualifiers[SIMD_MAX_BUILTIN_ARGS]
|
|
|
|
= { qualifier_none, qualifier_const_pointer_map_mode,
|
2015-07-22 12:44:16 +02:00
|
|
|
qualifier_none, qualifier_struct_load_store_lane_index };
|
2014-10-24 16:58:51 +02:00
|
|
|
#define TYPES_LOADSTRUCT_LANE (aarch64_types_loadstruct_lane_qualifiers)
|
2021-08-09 16:26:48 +02:00
|
|
|
static enum aarch64_type_qualifiers
|
|
|
|
aarch64_types_loadstruct_lane_u_qualifiers[SIMD_MAX_BUILTIN_ARGS]
|
|
|
|
= { qualifier_unsigned, qualifier_const_pointer_map_mode,
|
|
|
|
qualifier_unsigned, qualifier_struct_load_store_lane_index };
|
|
|
|
#define TYPES_LOADSTRUCT_LANE_U (aarch64_types_loadstruct_lane_u_qualifiers)
|
|
|
|
static enum aarch64_type_qualifiers
|
|
|
|
aarch64_types_loadstruct_lane_p_qualifiers[SIMD_MAX_BUILTIN_ARGS]
|
|
|
|
= { qualifier_poly, qualifier_const_pointer_map_mode,
|
|
|
|
qualifier_poly, qualifier_struct_load_store_lane_index };
|
|
|
|
#define TYPES_LOADSTRUCT_LANE_P (aarch64_types_loadstruct_lane_p_qualifiers)
|
2013-11-20 10:19:25 +01:00
|
|
|
|
2013-11-26 11:03:14 +01:00
|
|
|
static enum aarch64_type_qualifiers
|
|
|
|
aarch64_types_bsl_p_qualifiers[SIMD_MAX_BUILTIN_ARGS]
|
|
|
|
= { qualifier_poly, qualifier_unsigned,
|
|
|
|
qualifier_poly, qualifier_poly };
|
|
|
|
#define TYPES_BSL_P (aarch64_types_bsl_p_qualifiers)
|
|
|
|
static enum aarch64_type_qualifiers
|
|
|
|
aarch64_types_bsl_s_qualifiers[SIMD_MAX_BUILTIN_ARGS]
|
|
|
|
= { qualifier_none, qualifier_unsigned,
|
|
|
|
qualifier_none, qualifier_none };
|
|
|
|
#define TYPES_BSL_S (aarch64_types_bsl_s_qualifiers)
|
|
|
|
static enum aarch64_type_qualifiers
|
|
|
|
aarch64_types_bsl_u_qualifiers[SIMD_MAX_BUILTIN_ARGS]
|
|
|
|
= { qualifier_unsigned, qualifier_unsigned,
|
|
|
|
qualifier_unsigned, qualifier_unsigned };
|
|
|
|
#define TYPES_BSL_U (aarch64_types_bsl_u_qualifiers)
|
|
|
|
|
2013-11-20 10:19:25 +01:00
|
|
|
/* The first argument (return type) of a store should be void type,
|
|
|
|
which we represent with qualifier_void. Their first operand will be
|
|
|
|
a DImode pointer to the location to store to, so we must use
|
|
|
|
qualifier_map_mode | qualifier_pointer to build a pointer to the
|
|
|
|
element type of the vector. */
|
|
|
|
static enum aarch64_type_qualifiers
|
|
|
|
aarch64_types_store1_qualifiers[SIMD_MAX_BUILTIN_ARGS]
|
|
|
|
= { qualifier_void, qualifier_pointer_map_mode, qualifier_none };
|
|
|
|
#define TYPES_STORE1 (aarch64_types_store1_qualifiers)
|
|
|
|
#define TYPES_STORESTRUCT (aarch64_types_store1_qualifiers)
|
2021-08-09 16:26:48 +02:00
|
|
|
static enum aarch64_type_qualifiers
|
|
|
|
aarch64_types_store1_u_qualifiers[SIMD_MAX_BUILTIN_ARGS]
|
|
|
|
= { qualifier_void, qualifier_pointer_map_mode, qualifier_unsigned };
|
2021-11-10 11:49:19 +01:00
|
|
|
#define TYPES_STORE1_U (aarch64_types_store1_u_qualifiers)
|
2021-08-09 16:26:48 +02:00
|
|
|
#define TYPES_STORESTRUCT_U (aarch64_types_store1_u_qualifiers)
|
|
|
|
static enum aarch64_type_qualifiers
|
|
|
|
aarch64_types_store1_p_qualifiers[SIMD_MAX_BUILTIN_ARGS]
|
|
|
|
= { qualifier_void, qualifier_pointer_map_mode, qualifier_poly };
|
2021-11-10 11:49:19 +01:00
|
|
|
#define TYPES_STORE1_P (aarch64_types_store1_p_qualifiers)
|
2021-08-09 16:26:48 +02:00
|
|
|
#define TYPES_STORESTRUCT_P (aarch64_types_store1_p_qualifiers)
|
|
|
|
|
2014-04-28 23:05:51 +02:00
|
|
|
static enum aarch64_type_qualifiers
|
|
|
|
aarch64_types_storestruct_lane_qualifiers[SIMD_MAX_BUILTIN_ARGS]
|
|
|
|
= { qualifier_void, qualifier_pointer_map_mode,
|
2015-07-22 12:44:16 +02:00
|
|
|
qualifier_none, qualifier_struct_load_store_lane_index };
|
2014-04-28 23:05:51 +02:00
|
|
|
#define TYPES_STORESTRUCT_LANE (aarch64_types_storestruct_lane_qualifiers)
|
2021-08-09 16:26:48 +02:00
|
|
|
static enum aarch64_type_qualifiers
|
|
|
|
aarch64_types_storestruct_lane_u_qualifiers[SIMD_MAX_BUILTIN_ARGS]
|
|
|
|
= { qualifier_void, qualifier_pointer_map_mode,
|
|
|
|
qualifier_unsigned, qualifier_struct_load_store_lane_index };
|
|
|
|
#define TYPES_STORESTRUCT_LANE_U (aarch64_types_storestruct_lane_u_qualifiers)
|
|
|
|
static enum aarch64_type_qualifiers
|
|
|
|
aarch64_types_storestruct_lane_p_qualifiers[SIMD_MAX_BUILTIN_ARGS]
|
|
|
|
= { qualifier_void, qualifier_pointer_map_mode,
|
|
|
|
qualifier_poly, qualifier_struct_load_store_lane_index };
|
|
|
|
#define TYPES_STORESTRUCT_LANE_P (aarch64_types_storestruct_lane_p_qualifiers)
|
2013-11-20 10:19:25 +01:00
|
|
|
|
2013-04-22 14:46:38 +02:00
|
|
|
#define CF0(N, X) CODE_FOR_aarch64_##N##X
|
|
|
|
#define CF1(N, X) CODE_FOR_##N##X##1
|
|
|
|
#define CF2(N, X) CODE_FOR_##N##X##2
|
|
|
|
#define CF3(N, X) CODE_FOR_##N##X##3
|
|
|
|
#define CF4(N, X) CODE_FOR_##N##X##4
|
|
|
|
#define CF10(N, X) CODE_FOR_##N##X
|
|
|
|
|
2020-07-17 11:00:37 +02:00
|
|
|
#define VAR1(T, N, MAP, FLAG, A) \
|
|
|
|
{#N #A, UP (A), CF##MAP (N, A), 0, TYPES_##T, FLAG_##FLAG},
|
|
|
|
#define VAR2(T, N, MAP, FLAG, A, B) \
|
|
|
|
VAR1 (T, N, MAP, FLAG, A) \
|
|
|
|
VAR1 (T, N, MAP, FLAG, B)
|
|
|
|
#define VAR3(T, N, MAP, FLAG, A, B, C) \
|
|
|
|
VAR2 (T, N, MAP, FLAG, A, B) \
|
|
|
|
VAR1 (T, N, MAP, FLAG, C)
|
|
|
|
#define VAR4(T, N, MAP, FLAG, A, B, C, D) \
|
|
|
|
VAR3 (T, N, MAP, FLAG, A, B, C) \
|
|
|
|
VAR1 (T, N, MAP, FLAG, D)
|
|
|
|
#define VAR5(T, N, MAP, FLAG, A, B, C, D, E) \
|
|
|
|
VAR4 (T, N, MAP, FLAG, A, B, C, D) \
|
|
|
|
VAR1 (T, N, MAP, FLAG, E)
|
|
|
|
#define VAR6(T, N, MAP, FLAG, A, B, C, D, E, F) \
|
|
|
|
VAR5 (T, N, MAP, FLAG, A, B, C, D, E) \
|
|
|
|
VAR1 (T, N, MAP, FLAG, F)
|
|
|
|
#define VAR7(T, N, MAP, FLAG, A, B, C, D, E, F, G) \
|
|
|
|
VAR6 (T, N, MAP, FLAG, A, B, C, D, E, F) \
|
|
|
|
VAR1 (T, N, MAP, FLAG, G)
|
|
|
|
#define VAR8(T, N, MAP, FLAG, A, B, C, D, E, F, G, H) \
|
|
|
|
VAR7 (T, N, MAP, FLAG, A, B, C, D, E, F, G) \
|
|
|
|
VAR1 (T, N, MAP, FLAG, H)
|
|
|
|
#define VAR9(T, N, MAP, FLAG, A, B, C, D, E, F, G, H, I) \
|
|
|
|
VAR8 (T, N, MAP, FLAG, A, B, C, D, E, F, G, H) \
|
|
|
|
VAR1 (T, N, MAP, FLAG, I)
|
|
|
|
#define VAR10(T, N, MAP, FLAG, A, B, C, D, E, F, G, H, I, J) \
|
|
|
|
VAR9 (T, N, MAP, FLAG, A, B, C, D, E, F, G, H, I) \
|
|
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|
VAR1 (T, N, MAP, FLAG, J)
|
|
|
|
#define VAR11(T, N, MAP, FLAG, A, B, C, D, E, F, G, H, I, J, K) \
|
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VAR10 (T, N, MAP, FLAG, A, B, C, D, E, F, G, H, I, J) \
|
|
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VAR1 (T, N, MAP, FLAG, K)
|
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|
|
#define VAR12(T, N, MAP, FLAG, A, B, C, D, E, F, G, H, I, J, K, L) \
|
|
|
|
VAR11 (T, N, MAP, FLAG, A, B, C, D, E, F, G, H, I, J, K) \
|
|
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|
VAR1 (T, N, MAP, FLAG, L)
|
|
|
|
#define VAR13(T, N, MAP, FLAG, A, B, C, D, E, F, G, H, I, J, K, L, M) \
|
|
|
|
VAR12 (T, N, MAP, FLAG, A, B, C, D, E, F, G, H, I, J, K, L) \
|
|
|
|
VAR1 (T, N, MAP, FLAG, M)
|
|
|
|
#define VAR14(T, X, MAP, FLAG, A, B, C, D, E, F, G, H, I, J, K, L, M, N) \
|
|
|
|
VAR13 (T, X, MAP, FLAG, A, B, C, D, E, F, G, H, I, J, K, L, M) \
|
|
|
|
VAR1 (T, X, MAP, FLAG, N)
|
|
|
|
#define VAR15(T, X, MAP, FLAG, A, B, C, D, E, F, G, H, I, J, K, L, M, N, O) \
|
|
|
|
VAR14 (T, X, MAP, FLAG, A, B, C, D, E, F, G, H, I, J, K, L, M, N) \
|
|
|
|
VAR1 (T, X, MAP, FLAG, O)
|
|
|
|
#define VAR16(T, X, MAP, FLAG, A, B, C, D, E, F, G, H, I, J, K, L, M, N, O, P) \
|
|
|
|
VAR15 (T, X, MAP, FLAG, A, B, C, D, E, F, G, H, I, J, K, L, M, N, O) \
|
|
|
|
VAR1 (T, X, MAP, FLAG, P)
|
2012-11-20 13:10:37 +01:00
|
|
|
|
2014-09-22 18:24:57 +02:00
|
|
|
#include "aarch64-builtin-iterators.h"
|
2012-10-23 19:02:30 +02:00
|
|
|
|
|
|
|
static aarch64_simd_builtin_datum aarch64_simd_builtin_data[] = {
|
2012-11-20 13:10:37 +01:00
|
|
|
#include "aarch64-simd-builtins.def"
|
|
|
|
};
|
|
|
|
|
2014-06-11 11:17:18 +02:00
|
|
|
/* There's only 8 CRC32 builtins. Probably not worth their own .def file. */
|
|
|
|
#define AARCH64_CRC32_BUILTINS \
|
|
|
|
CRC32_BUILTIN (crc32b, QI) \
|
|
|
|
CRC32_BUILTIN (crc32h, HI) \
|
|
|
|
CRC32_BUILTIN (crc32w, SI) \
|
|
|
|
CRC32_BUILTIN (crc32x, DI) \
|
|
|
|
CRC32_BUILTIN (crc32cb, QI) \
|
|
|
|
CRC32_BUILTIN (crc32ch, HI) \
|
|
|
|
CRC32_BUILTIN (crc32cw, SI) \
|
|
|
|
CRC32_BUILTIN (crc32cx, DI)
|
|
|
|
|
aarch64-builtins.c (enum aarch64_type_qualifiers): Add qualifier_lane_pair_index.
gcc/ChangeLog:
2019-01-10 Tamar Christina <tamar.christina@arm.com>
* config/aarch64/aarch64-builtins.c (enum aarch64_type_qualifiers): Add qualifier_lane_pair_index.
(emit-rtl.h): Include.
(TYPES_QUADOP_LANE_PAIR): New.
(aarch64_simd_expand_args): Use it.
(aarch64_simd_expand_builtin): Likewise.
(AARCH64_SIMD_FCMLA_LANEQ_BUILTINS, aarch64_fcmla_laneq_builtin_datum): New.
(FCMLA_LANEQ_BUILTIN, AARCH64_SIMD_FCMLA_LANEQ_BUILTIN_BASE,
AARCH64_SIMD_FCMLA_LANEQ_BUILTINS, aarch64_fcmla_lane_builtin_data,
aarch64_init_fcmla_laneq_builtins, aarch64_expand_fcmla_builtin): New.
(aarch64_init_builtins): Add aarch64_init_fcmla_laneq_builtins.
(aarch64_expand_buildin): Add AARCH64_SIMD_BUILTIN_FCMLA_LANEQ0_V2SF,
AARCH64_SIMD_BUILTIN_FCMLA_LANEQ90_V2SF, AARCH64_SIMD_BUILTIN_FCMLA_LANEQ180_V2SF,
AARCH64_SIMD_BUILTIN_FCMLA_LANEQ2700_V2SF, AARCH64_SIMD_BUILTIN_FCMLA_LANEQ0_V4HF,
AARCH64_SIMD_BUILTIN_FCMLA_LANEQ90_V4HF, AARCH64_SIMD_BUILTIN_FCMLA_LANEQ180_V4HF,
AARCH64_SIMD_BUILTIN_FCMLA_LANEQ270_V4HF.
* config/aarch64/iterators.md (FCMLA_maybe_lane): New.
* config/aarch64/aarch64-c.c (aarch64_update_cpp_builtins): Add __ARM_FEATURE_COMPLEX.
* config/aarch64/aarch64-simd-builtins.def (fcadd90, fcadd270, fcmla0, fcmla90,
fcmla180, fcmla270, fcmla_lane0, fcmla_lane90, fcmla_lane180, fcmla_lane270,
fcmla_laneq0, fcmla_laneq90, fcmla_laneq180, fcmla_laneq270,
fcmlaq_lane0, fcmlaq_lane90, fcmlaq_lane180, fcmlaq_lane270): New.
* config/aarch64/aarch64-simd.md (aarch64_fcmla_lane<rot><mode>,
aarch64_fcmla_laneq<rot>v4hf, aarch64_fcmlaq_lane<rot><mode>,aarch64_fcadd<rot><mode>,
aarch64_fcmla<rot><mode>): New.
* config/aarch64/arm_neon.h:
(vcadd_rot90_f16): New.
(vcaddq_rot90_f16): New.
(vcadd_rot270_f16): New.
(vcaddq_rot270_f16): New.
(vcmla_f16): New.
(vcmlaq_f16): New.
(vcmla_lane_f16): New.
(vcmla_laneq_f16): New.
(vcmlaq_lane_f16): New.
(vcmlaq_rot90_lane_f16): New.
(vcmla_rot90_laneq_f16): New.
(vcmla_rot90_lane_f16): New.
(vcmlaq_rot90_f16): New.
(vcmla_rot90_f16): New.
(vcmlaq_laneq_f16): New.
(vcmla_rot180_laneq_f16): New.
(vcmla_rot180_lane_f16): New.
(vcmlaq_rot180_f16): New.
(vcmla_rot180_f16): New.
(vcmlaq_rot90_laneq_f16): New.
(vcmlaq_rot270_laneq_f16): New.
(vcmlaq_rot270_lane_f16): New.
(vcmla_rot270_laneq_f16): New.
(vcmlaq_rot270_f16): New.
(vcmla_rot270_f16): New.
(vcmlaq_rot180_laneq_f16): New.
(vcmlaq_rot180_lane_f16): New.
(vcmla_rot270_lane_f16): New.
(vcadd_rot90_f32): New.
(vcaddq_rot90_f32): New.
(vcaddq_rot90_f64): New.
(vcadd_rot270_f32): New.
(vcaddq_rot270_f32): New.
(vcaddq_rot270_f64): New.
(vcmla_f32): New.
(vcmlaq_f32): New.
(vcmlaq_f64): New.
(vcmla_lane_f32): New.
(vcmla_laneq_f32): New.
(vcmlaq_lane_f32): New.
(vcmlaq_laneq_f32): New.
(vcmla_rot90_f32): New.
(vcmlaq_rot90_f32): New.
(vcmlaq_rot90_f64): New.
(vcmla_rot90_lane_f32): New.
(vcmla_rot90_laneq_f32): New.
(vcmlaq_rot90_lane_f32): New.
(vcmlaq_rot90_laneq_f32): New.
(vcmla_rot180_f32): New.
(vcmlaq_rot180_f32): New.
(vcmlaq_rot180_f64): New.
(vcmla_rot180_lane_f32): New.
(vcmla_rot180_laneq_f32): New.
(vcmlaq_rot180_lane_f32): New.
(vcmlaq_rot180_laneq_f32): New.
(vcmla_rot270_f32): New.
(vcmlaq_rot270_f32): New.
(vcmlaq_rot270_f64): New.
(vcmla_rot270_lane_f32): New.
(vcmla_rot270_laneq_f32): New.
(vcmlaq_rot270_lane_f32): New.
(vcmlaq_rot270_laneq_f32): New.
* config/aarch64/aarch64.h (TARGET_COMPLEX): New.
* config/aarch64/iterators.md (UNSPEC_FCADD90, UNSPEC_FCADD270,
UNSPEC_FCMLA, UNSPEC_FCMLA90, UNSPEC_FCMLA180, UNSPEC_FCMLA270): New.
(FCADD, FCMLA): New.
(rot): New.
* config/arm/types.md (neon_fcadd, neon_fcmla): New.
gcc/testsuite/ChangeLog:
2019-01-10 Tamar Christina <tamar.christina@arm.com>
* gcc.target/aarch64/advsimd-intrinsics/vector-complex.c: New test.
* gcc.target/aarch64/advsimd-intrinsics/vector-complex_f16.c: New test.
From-SVN: r267795
2019-01-10 04:30:59 +01:00
|
|
|
/* The next 8 FCMLA instrinsics require some special handling compared the
|
|
|
|
normal simd intrinsics. */
|
|
|
|
#define AARCH64_SIMD_FCMLA_LANEQ_BUILTINS \
|
|
|
|
FCMLA_LANEQ_BUILTIN (0, v2sf, fcmla, V2SF, false) \
|
|
|
|
FCMLA_LANEQ_BUILTIN (90, v2sf, fcmla, V2SF, false) \
|
|
|
|
FCMLA_LANEQ_BUILTIN (180, v2sf, fcmla, V2SF, false) \
|
|
|
|
FCMLA_LANEQ_BUILTIN (270, v2sf, fcmla, V2SF, false) \
|
|
|
|
FCMLA_LANEQ_BUILTIN (0, v4hf, fcmla_laneq, V4HF, true) \
|
|
|
|
FCMLA_LANEQ_BUILTIN (90, v4hf, fcmla_laneq, V4HF, true) \
|
|
|
|
FCMLA_LANEQ_BUILTIN (180, v4hf, fcmla_laneq, V4HF, true) \
|
|
|
|
FCMLA_LANEQ_BUILTIN (270, v4hf, fcmla_laneq, V4HF, true) \
|
|
|
|
|
2014-06-11 11:17:18 +02:00
|
|
|
typedef struct
|
|
|
|
{
|
|
|
|
const char *name;
|
decl.c, [...]: Remove redundant enum from machine_mode.
gcc/ada/
* gcc-interface/decl.c, gcc-interface/gigi.h, gcc-interface/misc.c,
gcc-interface/trans.c, gcc-interface/utils.c, gcc-interface/utils2.c:
Remove redundant enum from machine_mode.
gcc/c-family/
* c-common.c, c-common.h, c-cppbuiltin.c, c-lex.c: Remove redundant
enum from machine_mode.
gcc/c/
* c-decl.c, c-tree.h, c-typeck.c: Remove redundant enum from
machine_mode.
gcc/cp/
* constexpr.c: Remove redundant enum from machine_mode.
gcc/fortran/
* trans-types.c, trans-types.h: Remove redundant enum from
machine_mode.
gcc/go/
* go-lang.c: Remove redundant enum from machine_mode.
gcc/java/
* builtins.c, java-tree.h, typeck.c: Remove redundant enum from
machine_mode.
gcc/lto/
* lto-lang.c: Remove redundant enum from machine_mode.
gcc/
* addresses.h, alias.c, asan.c, auto-inc-dec.c, bt-load.c, builtins.c,
builtins.h, caller-save.c, calls.c, calls.h, cfgexpand.c, cfgloop.h,
cfgrtl.c, combine.c, compare-elim.c, config/aarch64/aarch64-builtins.c,
config/aarch64/aarch64-protos.h, config/aarch64/aarch64-simd.md,
config/aarch64/aarch64.c, config/aarch64/aarch64.h,
config/aarch64/aarch64.md, config/alpha/alpha-protos.h,
config/alpha/alpha.c, config/arc/arc-protos.h, config/arc/arc.c,
config/arc/arc.h, config/arc/predicates.md,
config/arm/aarch-common-protos.h, config/arm/aarch-common.c,
config/arm/arm-protos.h, config/arm/arm.c, config/arm/arm.h,
config/arm/arm.md, config/arm/neon.md, config/arm/thumb2.md,
config/avr/avr-log.c, config/avr/avr-protos.h, config/avr/avr.c,
config/avr/avr.md, config/bfin/bfin-protos.h, config/bfin/bfin.c,
config/c6x/c6x-protos.h, config/c6x/c6x.c, config/c6x/c6x.md,
config/cr16/cr16-protos.h, config/cr16/cr16.c,
config/cris/cris-protos.h, config/cris/cris.c, config/cris/cris.md,
config/darwin-protos.h, config/darwin.c,
config/epiphany/epiphany-protos.h, config/epiphany/epiphany.c,
config/epiphany/epiphany.md, config/fr30/fr30.c,
config/frv/frv-protos.h, config/frv/frv.c, config/frv/predicates.md,
config/h8300/h8300-protos.h, config/h8300/h8300.c,
config/i386/i386-builtin-types.awk, config/i386/i386-protos.h,
config/i386/i386.c, config/i386/i386.md, config/i386/predicates.md,
config/i386/sse.md, config/i386/sync.md, config/ia64/ia64-protos.h,
config/ia64/ia64.c, config/iq2000/iq2000-protos.h,
config/iq2000/iq2000.c, config/iq2000/iq2000.md,
config/lm32/lm32-protos.h, config/lm32/lm32.c,
config/m32c/m32c-protos.h, config/m32c/m32c.c,
config/m32r/m32r-protos.h, config/m32r/m32r.c,
config/m68k/m68k-protos.h, config/m68k/m68k.c,
config/mcore/mcore-protos.h, config/mcore/mcore.c,
config/mcore/mcore.md, config/mep/mep-protos.h, config/mep/mep.c,
config/microblaze/microblaze-protos.h, config/microblaze/microblaze.c,
config/mips/mips-protos.h, config/mips/mips.c,
config/mmix/mmix-protos.h, config/mmix/mmix.c,
config/mn10300/mn10300-protos.h, config/mn10300/mn10300.c,
config/moxie/moxie.c, config/msp430/msp430-protos.h,
config/msp430/msp430.c, config/nds32/nds32-cost.c,
config/nds32/nds32-intrinsic.c, config/nds32/nds32-md-auxiliary.c,
config/nds32/nds32-protos.h, config/nds32/nds32.c,
config/nios2/nios2-protos.h, config/nios2/nios2.c,
config/pa/pa-protos.h, config/pa/pa.c, config/pdp11/pdp11-protos.h,
config/pdp11/pdp11.c, config/rl78/rl78-protos.h, config/rl78/rl78.c,
config/rs6000/altivec.md, config/rs6000/rs6000-c.c,
config/rs6000/rs6000-protos.h, config/rs6000/rs6000.c,
config/rs6000/rs6000.h, config/rx/rx-protos.h, config/rx/rx.c,
config/s390/predicates.md, config/s390/s390-protos.h,
config/s390/s390.c, config/s390/s390.h, config/s390/s390.md,
config/sh/predicates.md, config/sh/sh-protos.h, config/sh/sh.c,
config/sh/sh.md, config/sparc/predicates.md,
config/sparc/sparc-protos.h, config/sparc/sparc.c,
config/sparc/sparc.md, config/spu/spu-protos.h, config/spu/spu.c,
config/stormy16/stormy16-protos.h, config/stormy16/stormy16.c,
config/tilegx/tilegx-protos.h, config/tilegx/tilegx.c,
config/tilegx/tilegx.md, config/tilepro/tilepro-protos.h,
config/tilepro/tilepro.c, config/v850/v850-protos.h,
config/v850/v850.c, config/v850/v850.md, config/vax/vax-protos.h,
config/vax/vax.c, config/vms/vms-c.c, config/xtensa/xtensa-protos.h,
config/xtensa/xtensa.c, coverage.c, cprop.c, cse.c, cselib.c, cselib.h,
dbxout.c, ddg.c, df-problems.c, dfp.c, dfp.h, doc/md.texi,
doc/rtl.texi, doc/tm.texi, doc/tm.texi.in, dojump.c, dse.c,
dwarf2cfi.c, dwarf2out.c, dwarf2out.h, emit-rtl.c, emit-rtl.h,
except.c, explow.c, expmed.c, expmed.h, expr.c, expr.h, final.c,
fixed-value.c, fixed-value.h, fold-const.c, function.c, function.h,
fwprop.c, gcse.c, gengenrtl.c, genmodes.c, genopinit.c, genoutput.c,
genpreds.c, genrecog.c, gensupport.c, gimple-ssa-strength-reduction.c,
graphite-clast-to-gimple.c, haifa-sched.c, hooks.c, hooks.h, ifcvt.c,
internal-fn.c, ira-build.c, ira-color.c, ira-conflicts.c, ira-costs.c,
ira-emit.c, ira-int.h, ira-lives.c, ira.c, ira.h, jump.c, langhooks.h,
libfuncs.h, lists.c, loop-doloop.c, loop-invariant.c, loop-iv.c,
loop-unroll.c, lower-subreg.c, lower-subreg.h, lra-assigns.c,
lra-constraints.c, lra-eliminations.c, lra-int.h, lra-lives.c,
lra-spills.c, lra.c, lra.h, machmode.h, omp-low.c, optabs.c, optabs.h,
output.h, postreload.c, print-tree.c, read-rtl.c, real.c, real.h,
recog.c, recog.h, ree.c, reg-stack.c, regcprop.c, reginfo.c,
regrename.c, regs.h, reload.c, reload.h, reload1.c, rtl.c, rtl.h,
rtlanal.c, rtlhash.c, rtlhooks-def.h, rtlhooks.c, sched-deps.c,
sel-sched-dump.c, sel-sched-ir.c, sel-sched-ir.h, sel-sched.c,
simplify-rtx.c, stmt.c, stor-layout.c, stor-layout.h, target.def,
targhooks.c, targhooks.h, tree-affine.c, tree-call-cdce.c,
tree-complex.c, tree-data-ref.c, tree-dfa.c, tree-if-conv.c,
tree-inline.c, tree-outof-ssa.c, tree-scalar-evolution.c,
tree-ssa-address.c, tree-ssa-ccp.c, tree-ssa-loop-ivopts.c,
tree-ssa-loop-ivopts.h, tree-ssa-loop-manip.c,
tree-ssa-loop-prefetch.c, tree-ssa-math-opts.c, tree-ssa-reassoc.c,
tree-ssa-sccvn.c, tree-streamer-in.c, tree-switch-conversion.c,
tree-vect-data-refs.c, tree-vect-generic.c, tree-vect-loop.c,
tree-vect-patterns.c, tree-vect-slp.c, tree-vect-stmts.c,
tree-vrp.c, tree.c, tree.h, tsan.c, ubsan.c, valtrack.c,
var-tracking.c, varasm.c: Remove redundant enum from
machine_mode.
gcc/
* gengtype.c (main): Treat machine_mode as a scalar typedef.
* genmodes.c (emit_insn_modes_h): Hide inline functions if
USED_FOR_TARGET.
From-SVN: r216834
2014-10-29 13:02:45 +01:00
|
|
|
machine_mode mode;
|
2014-06-11 11:17:18 +02:00
|
|
|
const enum insn_code icode;
|
|
|
|
unsigned int fcode;
|
|
|
|
} aarch64_crc_builtin_datum;
|
|
|
|
|
aarch64-builtins.c (enum aarch64_type_qualifiers): Add qualifier_lane_pair_index.
gcc/ChangeLog:
2019-01-10 Tamar Christina <tamar.christina@arm.com>
* config/aarch64/aarch64-builtins.c (enum aarch64_type_qualifiers): Add qualifier_lane_pair_index.
(emit-rtl.h): Include.
(TYPES_QUADOP_LANE_PAIR): New.
(aarch64_simd_expand_args): Use it.
(aarch64_simd_expand_builtin): Likewise.
(AARCH64_SIMD_FCMLA_LANEQ_BUILTINS, aarch64_fcmla_laneq_builtin_datum): New.
(FCMLA_LANEQ_BUILTIN, AARCH64_SIMD_FCMLA_LANEQ_BUILTIN_BASE,
AARCH64_SIMD_FCMLA_LANEQ_BUILTINS, aarch64_fcmla_lane_builtin_data,
aarch64_init_fcmla_laneq_builtins, aarch64_expand_fcmla_builtin): New.
(aarch64_init_builtins): Add aarch64_init_fcmla_laneq_builtins.
(aarch64_expand_buildin): Add AARCH64_SIMD_BUILTIN_FCMLA_LANEQ0_V2SF,
AARCH64_SIMD_BUILTIN_FCMLA_LANEQ90_V2SF, AARCH64_SIMD_BUILTIN_FCMLA_LANEQ180_V2SF,
AARCH64_SIMD_BUILTIN_FCMLA_LANEQ2700_V2SF, AARCH64_SIMD_BUILTIN_FCMLA_LANEQ0_V4HF,
AARCH64_SIMD_BUILTIN_FCMLA_LANEQ90_V4HF, AARCH64_SIMD_BUILTIN_FCMLA_LANEQ180_V4HF,
AARCH64_SIMD_BUILTIN_FCMLA_LANEQ270_V4HF.
* config/aarch64/iterators.md (FCMLA_maybe_lane): New.
* config/aarch64/aarch64-c.c (aarch64_update_cpp_builtins): Add __ARM_FEATURE_COMPLEX.
* config/aarch64/aarch64-simd-builtins.def (fcadd90, fcadd270, fcmla0, fcmla90,
fcmla180, fcmla270, fcmla_lane0, fcmla_lane90, fcmla_lane180, fcmla_lane270,
fcmla_laneq0, fcmla_laneq90, fcmla_laneq180, fcmla_laneq270,
fcmlaq_lane0, fcmlaq_lane90, fcmlaq_lane180, fcmlaq_lane270): New.
* config/aarch64/aarch64-simd.md (aarch64_fcmla_lane<rot><mode>,
aarch64_fcmla_laneq<rot>v4hf, aarch64_fcmlaq_lane<rot><mode>,aarch64_fcadd<rot><mode>,
aarch64_fcmla<rot><mode>): New.
* config/aarch64/arm_neon.h:
(vcadd_rot90_f16): New.
(vcaddq_rot90_f16): New.
(vcadd_rot270_f16): New.
(vcaddq_rot270_f16): New.
(vcmla_f16): New.
(vcmlaq_f16): New.
(vcmla_lane_f16): New.
(vcmla_laneq_f16): New.
(vcmlaq_lane_f16): New.
(vcmlaq_rot90_lane_f16): New.
(vcmla_rot90_laneq_f16): New.
(vcmla_rot90_lane_f16): New.
(vcmlaq_rot90_f16): New.
(vcmla_rot90_f16): New.
(vcmlaq_laneq_f16): New.
(vcmla_rot180_laneq_f16): New.
(vcmla_rot180_lane_f16): New.
(vcmlaq_rot180_f16): New.
(vcmla_rot180_f16): New.
(vcmlaq_rot90_laneq_f16): New.
(vcmlaq_rot270_laneq_f16): New.
(vcmlaq_rot270_lane_f16): New.
(vcmla_rot270_laneq_f16): New.
(vcmlaq_rot270_f16): New.
(vcmla_rot270_f16): New.
(vcmlaq_rot180_laneq_f16): New.
(vcmlaq_rot180_lane_f16): New.
(vcmla_rot270_lane_f16): New.
(vcadd_rot90_f32): New.
(vcaddq_rot90_f32): New.
(vcaddq_rot90_f64): New.
(vcadd_rot270_f32): New.
(vcaddq_rot270_f32): New.
(vcaddq_rot270_f64): New.
(vcmla_f32): New.
(vcmlaq_f32): New.
(vcmlaq_f64): New.
(vcmla_lane_f32): New.
(vcmla_laneq_f32): New.
(vcmlaq_lane_f32): New.
(vcmlaq_laneq_f32): New.
(vcmla_rot90_f32): New.
(vcmlaq_rot90_f32): New.
(vcmlaq_rot90_f64): New.
(vcmla_rot90_lane_f32): New.
(vcmla_rot90_laneq_f32): New.
(vcmlaq_rot90_lane_f32): New.
(vcmlaq_rot90_laneq_f32): New.
(vcmla_rot180_f32): New.
(vcmlaq_rot180_f32): New.
(vcmlaq_rot180_f64): New.
(vcmla_rot180_lane_f32): New.
(vcmla_rot180_laneq_f32): New.
(vcmlaq_rot180_lane_f32): New.
(vcmlaq_rot180_laneq_f32): New.
(vcmla_rot270_f32): New.
(vcmlaq_rot270_f32): New.
(vcmlaq_rot270_f64): New.
(vcmla_rot270_lane_f32): New.
(vcmla_rot270_laneq_f32): New.
(vcmlaq_rot270_lane_f32): New.
(vcmlaq_rot270_laneq_f32): New.
* config/aarch64/aarch64.h (TARGET_COMPLEX): New.
* config/aarch64/iterators.md (UNSPEC_FCADD90, UNSPEC_FCADD270,
UNSPEC_FCMLA, UNSPEC_FCMLA90, UNSPEC_FCMLA180, UNSPEC_FCMLA270): New.
(FCADD, FCMLA): New.
(rot): New.
* config/arm/types.md (neon_fcadd, neon_fcmla): New.
gcc/testsuite/ChangeLog:
2019-01-10 Tamar Christina <tamar.christina@arm.com>
* gcc.target/aarch64/advsimd-intrinsics/vector-complex.c: New test.
* gcc.target/aarch64/advsimd-intrinsics/vector-complex_f16.c: New test.
From-SVN: r267795
2019-01-10 04:30:59 +01:00
|
|
|
/* Hold information about how to expand the FCMLA_LANEQ builtins. */
|
|
|
|
typedef struct
|
|
|
|
{
|
|
|
|
const char *name;
|
|
|
|
machine_mode mode;
|
|
|
|
const enum insn_code icode;
|
|
|
|
unsigned int fcode;
|
|
|
|
bool lane;
|
|
|
|
} aarch64_fcmla_laneq_builtin_datum;
|
|
|
|
|
2014-06-11 11:17:18 +02:00
|
|
|
#define CRC32_BUILTIN(N, M) \
|
|
|
|
AARCH64_BUILTIN_##N,
|
|
|
|
|
aarch64-builtins.c (enum aarch64_type_qualifiers): Add qualifier_lane_pair_index.
gcc/ChangeLog:
2019-01-10 Tamar Christina <tamar.christina@arm.com>
* config/aarch64/aarch64-builtins.c (enum aarch64_type_qualifiers): Add qualifier_lane_pair_index.
(emit-rtl.h): Include.
(TYPES_QUADOP_LANE_PAIR): New.
(aarch64_simd_expand_args): Use it.
(aarch64_simd_expand_builtin): Likewise.
(AARCH64_SIMD_FCMLA_LANEQ_BUILTINS, aarch64_fcmla_laneq_builtin_datum): New.
(FCMLA_LANEQ_BUILTIN, AARCH64_SIMD_FCMLA_LANEQ_BUILTIN_BASE,
AARCH64_SIMD_FCMLA_LANEQ_BUILTINS, aarch64_fcmla_lane_builtin_data,
aarch64_init_fcmla_laneq_builtins, aarch64_expand_fcmla_builtin): New.
(aarch64_init_builtins): Add aarch64_init_fcmla_laneq_builtins.
(aarch64_expand_buildin): Add AARCH64_SIMD_BUILTIN_FCMLA_LANEQ0_V2SF,
AARCH64_SIMD_BUILTIN_FCMLA_LANEQ90_V2SF, AARCH64_SIMD_BUILTIN_FCMLA_LANEQ180_V2SF,
AARCH64_SIMD_BUILTIN_FCMLA_LANEQ2700_V2SF, AARCH64_SIMD_BUILTIN_FCMLA_LANEQ0_V4HF,
AARCH64_SIMD_BUILTIN_FCMLA_LANEQ90_V4HF, AARCH64_SIMD_BUILTIN_FCMLA_LANEQ180_V4HF,
AARCH64_SIMD_BUILTIN_FCMLA_LANEQ270_V4HF.
* config/aarch64/iterators.md (FCMLA_maybe_lane): New.
* config/aarch64/aarch64-c.c (aarch64_update_cpp_builtins): Add __ARM_FEATURE_COMPLEX.
* config/aarch64/aarch64-simd-builtins.def (fcadd90, fcadd270, fcmla0, fcmla90,
fcmla180, fcmla270, fcmla_lane0, fcmla_lane90, fcmla_lane180, fcmla_lane270,
fcmla_laneq0, fcmla_laneq90, fcmla_laneq180, fcmla_laneq270,
fcmlaq_lane0, fcmlaq_lane90, fcmlaq_lane180, fcmlaq_lane270): New.
* config/aarch64/aarch64-simd.md (aarch64_fcmla_lane<rot><mode>,
aarch64_fcmla_laneq<rot>v4hf, aarch64_fcmlaq_lane<rot><mode>,aarch64_fcadd<rot><mode>,
aarch64_fcmla<rot><mode>): New.
* config/aarch64/arm_neon.h:
(vcadd_rot90_f16): New.
(vcaddq_rot90_f16): New.
(vcadd_rot270_f16): New.
(vcaddq_rot270_f16): New.
(vcmla_f16): New.
(vcmlaq_f16): New.
(vcmla_lane_f16): New.
(vcmla_laneq_f16): New.
(vcmlaq_lane_f16): New.
(vcmlaq_rot90_lane_f16): New.
(vcmla_rot90_laneq_f16): New.
(vcmla_rot90_lane_f16): New.
(vcmlaq_rot90_f16): New.
(vcmla_rot90_f16): New.
(vcmlaq_laneq_f16): New.
(vcmla_rot180_laneq_f16): New.
(vcmla_rot180_lane_f16): New.
(vcmlaq_rot180_f16): New.
(vcmla_rot180_f16): New.
(vcmlaq_rot90_laneq_f16): New.
(vcmlaq_rot270_laneq_f16): New.
(vcmlaq_rot270_lane_f16): New.
(vcmla_rot270_laneq_f16): New.
(vcmlaq_rot270_f16): New.
(vcmla_rot270_f16): New.
(vcmlaq_rot180_laneq_f16): New.
(vcmlaq_rot180_lane_f16): New.
(vcmla_rot270_lane_f16): New.
(vcadd_rot90_f32): New.
(vcaddq_rot90_f32): New.
(vcaddq_rot90_f64): New.
(vcadd_rot270_f32): New.
(vcaddq_rot270_f32): New.
(vcaddq_rot270_f64): New.
(vcmla_f32): New.
(vcmlaq_f32): New.
(vcmlaq_f64): New.
(vcmla_lane_f32): New.
(vcmla_laneq_f32): New.
(vcmlaq_lane_f32): New.
(vcmlaq_laneq_f32): New.
(vcmla_rot90_f32): New.
(vcmlaq_rot90_f32): New.
(vcmlaq_rot90_f64): New.
(vcmla_rot90_lane_f32): New.
(vcmla_rot90_laneq_f32): New.
(vcmlaq_rot90_lane_f32): New.
(vcmlaq_rot90_laneq_f32): New.
(vcmla_rot180_f32): New.
(vcmlaq_rot180_f32): New.
(vcmlaq_rot180_f64): New.
(vcmla_rot180_lane_f32): New.
(vcmla_rot180_laneq_f32): New.
(vcmlaq_rot180_lane_f32): New.
(vcmlaq_rot180_laneq_f32): New.
(vcmla_rot270_f32): New.
(vcmlaq_rot270_f32): New.
(vcmlaq_rot270_f64): New.
(vcmla_rot270_lane_f32): New.
(vcmla_rot270_laneq_f32): New.
(vcmlaq_rot270_lane_f32): New.
(vcmlaq_rot270_laneq_f32): New.
* config/aarch64/aarch64.h (TARGET_COMPLEX): New.
* config/aarch64/iterators.md (UNSPEC_FCADD90, UNSPEC_FCADD270,
UNSPEC_FCMLA, UNSPEC_FCMLA90, UNSPEC_FCMLA180, UNSPEC_FCMLA270): New.
(FCADD, FCMLA): New.
(rot): New.
* config/arm/types.md (neon_fcadd, neon_fcmla): New.
gcc/testsuite/ChangeLog:
2019-01-10 Tamar Christina <tamar.christina@arm.com>
* gcc.target/aarch64/advsimd-intrinsics/vector-complex.c: New test.
* gcc.target/aarch64/advsimd-intrinsics/vector-complex_f16.c: New test.
From-SVN: r267795
2019-01-10 04:30:59 +01:00
|
|
|
#define FCMLA_LANEQ_BUILTIN(I, N, X, M, T) \
|
|
|
|
AARCH64_SIMD_BUILTIN_FCMLA_LANEQ##I##_##M,
|
|
|
|
|
2012-11-20 13:10:37 +01:00
|
|
|
#undef VAR1
|
2020-07-17 11:00:37 +02:00
|
|
|
#define VAR1(T, N, MAP, FLAG, A) \
|
2013-11-26 10:59:10 +01:00
|
|
|
AARCH64_SIMD_BUILTIN_##T##_##N##A,
|
2012-11-20 13:10:37 +01:00
|
|
|
|
|
|
|
enum aarch64_builtins
|
|
|
|
{
|
|
|
|
AARCH64_BUILTIN_MIN,
|
2014-05-23 00:05:08 +02:00
|
|
|
|
|
|
|
AARCH64_BUILTIN_GET_FPCR,
|
|
|
|
AARCH64_BUILTIN_SET_FPCR,
|
|
|
|
AARCH64_BUILTIN_GET_FPSR,
|
|
|
|
AARCH64_BUILTIN_SET_FPSR,
|
|
|
|
|
2020-05-28 09:49:42 +02:00
|
|
|
AARCH64_BUILTIN_GET_FPCR64,
|
|
|
|
AARCH64_BUILTIN_SET_FPCR64,
|
|
|
|
AARCH64_BUILTIN_GET_FPSR64,
|
|
|
|
AARCH64_BUILTIN_SET_FPSR64,
|
|
|
|
|
2015-11-06 18:10:17 +01:00
|
|
|
AARCH64_BUILTIN_RSQRT_DF,
|
|
|
|
AARCH64_BUILTIN_RSQRT_SF,
|
|
|
|
AARCH64_BUILTIN_RSQRT_V2DF,
|
|
|
|
AARCH64_BUILTIN_RSQRT_V2SF,
|
|
|
|
AARCH64_BUILTIN_RSQRT_V4SF,
|
2012-11-20 13:10:37 +01:00
|
|
|
AARCH64_SIMD_BUILTIN_BASE,
|
[AArch64] Fix ICE on non-constant indices to __builtin_aarch64_im_lane_boundsi
gcc/:
* config/aarch64/aarch64-builtins.c (aarch64_types_binopv_qualifiers,
TYPES_BINOPV): Delete.
(enum aarch64_builtins): Add AARCH64_BUILTIN_SIMD_LANE_CHECK and
AARCH64_SIMD_PATTERN_START.
(aarch64_init_simd_builtins): Register
__builtin_aarch64_im_lane_boundsi; use AARCH64_SIMD_PATTERN_START.
(aarch64_simd_expand_builtin): Handle AARCH64_BUILTIN_LANE_CHECK; use
AARCH64_SIMD_PATTERN_START.
* config/aarch64/aarch64-simd.md (aarch64_im_lane_boundsi): Delete.
* config/aarch64/aarch64-simd-builtins.def (im_lane_bound): Delete.
* config/aarch64/arm_neon.h (__AARCH64_LANE_CHECK): New.
(__aarch64_vget_lane_f64, __aarch64_vget_lane_s64,
__aarch64_vget_lane_u64, __aarch64_vset_lane_any, vdupd_lane_f64,
vdupd_lane_s64, vdupd_lane_u64, vext_f32, vext_f64, vext_p8, vext_p16,
vext_s8, vext_s16, vext_s32, vext_s64, vext_u8, vext_u16, vext_u32,
vext_u64, vextq_f32, vextq_f64, vextq_p8, vextq_p16, vextq_s8,
vextq_s16, vextq_s32, vextq_s64, vextq_u8, vextq_u16, vextq_u32,
vextq_u64, vmulq_lane_f64): Use __AARCH64_LANE_CHECK.
gcc/testsuite/:
* gcc.target/aarch64/simd/vset_lane_s16_const_1.c: New test.
From-SVN: r218532
2014-12-09 20:52:22 +01:00
|
|
|
AARCH64_SIMD_BUILTIN_LANE_CHECK,
|
2012-11-20 13:10:37 +01:00
|
|
|
#include "aarch64-simd-builtins.def"
|
[AArch64] Fix ICE on non-constant indices to __builtin_aarch64_im_lane_boundsi
gcc/:
* config/aarch64/aarch64-builtins.c (aarch64_types_binopv_qualifiers,
TYPES_BINOPV): Delete.
(enum aarch64_builtins): Add AARCH64_BUILTIN_SIMD_LANE_CHECK and
AARCH64_SIMD_PATTERN_START.
(aarch64_init_simd_builtins): Register
__builtin_aarch64_im_lane_boundsi; use AARCH64_SIMD_PATTERN_START.
(aarch64_simd_expand_builtin): Handle AARCH64_BUILTIN_LANE_CHECK; use
AARCH64_SIMD_PATTERN_START.
* config/aarch64/aarch64-simd.md (aarch64_im_lane_boundsi): Delete.
* config/aarch64/aarch64-simd-builtins.def (im_lane_bound): Delete.
* config/aarch64/arm_neon.h (__AARCH64_LANE_CHECK): New.
(__aarch64_vget_lane_f64, __aarch64_vget_lane_s64,
__aarch64_vget_lane_u64, __aarch64_vset_lane_any, vdupd_lane_f64,
vdupd_lane_s64, vdupd_lane_u64, vext_f32, vext_f64, vext_p8, vext_p16,
vext_s8, vext_s16, vext_s32, vext_s64, vext_u8, vext_u16, vext_u32,
vext_u64, vextq_f32, vextq_f64, vextq_p8, vextq_p16, vextq_s8,
vextq_s16, vextq_s32, vextq_s64, vextq_u8, vextq_u16, vextq_u32,
vextq_u64, vmulq_lane_f64): Use __AARCH64_LANE_CHECK.
gcc/testsuite/:
* gcc.target/aarch64/simd/vset_lane_s16_const_1.c: New test.
From-SVN: r218532
2014-12-09 20:52:22 +01:00
|
|
|
/* The first enum element which is based on an insn_data pattern. */
|
|
|
|
AARCH64_SIMD_PATTERN_START = AARCH64_SIMD_BUILTIN_LANE_CHECK + 1,
|
|
|
|
AARCH64_SIMD_BUILTIN_MAX = AARCH64_SIMD_PATTERN_START
|
|
|
|
+ ARRAY_SIZE (aarch64_simd_builtin_data) - 1,
|
2014-06-11 11:17:18 +02:00
|
|
|
AARCH64_CRC32_BUILTIN_BASE,
|
|
|
|
AARCH64_CRC32_BUILTINS
|
|
|
|
AARCH64_CRC32_BUILTIN_MAX,
|
2017-01-20 01:10:11 +01:00
|
|
|
/* ARMv8.3-A Pointer Authentication Builtins. */
|
|
|
|
AARCH64_PAUTH_BUILTIN_AUTIA1716,
|
|
|
|
AARCH64_PAUTH_BUILTIN_PACIA1716,
|
[PATCH 3/3][GCC][AARCH64] Add support for pointer authentication B key
gcc/
2019-05-29 Sam Tebbs <sam.tebbs@arm.com>
* config/aarch64/aarch64-builtins.c (aarch64_builtins): Add
AARCH64_PAUTH_BUILTIN_AUTIB1716 and AARCH64_PAUTH_BUILTIN_PACIB1716.
* config/aarch64/aarch64-builtins.c (aarch64_init_pauth_hint_builtins):
Add autib1716 and pacib1716 initialisation.
* config/aarch64/aarch64-builtins.c (aarch64_expand_builtin): Add checks
for autib1716 and pacib1716.
* config/aarch64/aarch64-protos.h (aarch64_key_type,
aarch64_post_cfi_startproc): Define.
* config/aarch64/aarch64-protos.h (aarch64_ra_sign_key): Define extern.
* config/aarch64/aarch64.c (aarch64_handle_standard_branch_protection,
aarch64_handle_pac_ret_protection): Set default sign key to A.
* config/aarch64/aarch64.c (aarch64_expand_epilogue,
aarch64_expand_prologue): Add check for b-key.
* config/aarch64/aarch64.c (aarch64_ra_sign_key,
aarch64_post_cfi_startproc, aarch64_handle_pac_ret_b_key): Define.
* config/aarch64/aarch64.h (TARGET_ASM_POST_CFI_STARTPROC): Define.
* config/aarch64/aarch64.c (aarch64_pac_ret_subtypes): Add "b-key".
* config/aarch64/aarch64.md (unspec): Add UNSPEC_AUTIA1716,
UNSPEC_AUTIB1716, UNSPEC_AUTIASP, UNSPEC_AUTIBSP, UNSPEC_PACIA1716,
UNSPEC_PACIB1716, UNSPEC_PACIASP, UNSPEC_PACIBSP.
* config/aarch64/aarch64.md (do_return): Add check for b-key.
* config/aarch64/aarch64.md (<pauth_mnem_prefix>sp): Replace
pauth_hint_num_a with pauth_hint_num.
* config/aarch64/aarch64.md (<pauth_mnem_prefix>1716): Replace
pauth_hint_num_a with pauth_hint_num.
* config/aarch64/aarch64.opt (msign-return-address=): Deprecate.
* config/aarch64/iterators.md (PAUTH_LR_SP): Add UNSPEC_AUTIASP,
UNSPEC_AUTIBSP, UNSPEC_PACIASP, UNSPEC_PACIBSP.
* config/aarch64/iterators.md (PAUTH_17_16): Add UNSPEC_AUTIA1716,
UNSPEC_AUTIB1716, UNSPEC_PACIA1716, UNSPEC_PACIB1716.
* config/aarch64/iterators.md (pauth_mnem_prefix): Add UNSPEC_AUTIA1716,
UNSPEC_AUTIB1716, UNSPEC_PACIA1716, UNSPEC_PACIB1716, UNSPEC_AUTIASP,
UNSPEC_AUTIBSP, UNSPEC_PACIASP, UNSPEC_PACIBSP.
* config/aarch64/iterators.md (pauth_hint_num_a): Replace
UNSPEC_PACI1716 and UNSPEC_AUTI1716 with UNSPEC_PACIA1716 and
UNSPEC_AUTIA1716 respectively.
* config/aarch64/iterators.md (pauth_hint_num_a): Rename to pauth_hint_num
and add UNSPEC_PACIBSP, UNSPEC_AUTIBSP, UNSPEC_PACIB1716, UNSPEC_AUTIB1716.
* doc/invoke.texi (-mbranch-protection): Add b-key type.
* config/aarch64/aarch64-bti-insert.c (aarch64_pac_insn_p): Rename
UNSPEC_PACISP to UNSPEC_PACIASP and UNSPEC_PACIBSP.
gcc/testsuite
2019-05-29 Sam Tebbs <sam.tebbs@arm.com>
* gcc.target/aarch64/return_address_sign_b_1.c: New file.
* gcc.target/aarch64/return_address_sign_b_2.c: New file.
* gcc.target/aarch64/return_address_sign_b_3.c: New file.
* gcc.target/aarch64/return_address_sign_b_exception.c: New file.
* gcc.target/aarch64/return_address_sign_ab_exception.c: New file.
* gcc.target/aarch64/return_address_sign_builtin.c: New file
libgcc/
2019-05-29 Sam Tebbs <sam.tebbs@arm.com>
* config/aarch64/aarch64-unwind.h (aarch64_cie_signed_with_b_key): New
function.
* config/aarch64/aarch64-unwind.h (aarch64_post_extract_frame_addr,
aarch64_post_frob_eh_handler_addr): Add check for b-key.
* config/aarch64/aarch64-unwind-h (aarch64_post_extract_frame_addr,
aarch64_post_frob_eh_handler_addr, aarch64_post_frob_update_context):
Rename RA_A_SIGNED_BIT to RA_SIGNED_BIT.
* unwind-dw2-fde.c (get_cie_encoding): Add check for 'B' in augmentation
string.
* unwind-dw2.c (extract_cie_info): Add check for 'B' in augmentation
string.
(RA_A_SIGNED_BIT): Rename to RA_SIGNED_BIT.
From-SVN: r271735
2019-05-29 11:22:17 +02:00
|
|
|
AARCH64_PAUTH_BUILTIN_AUTIB1716,
|
|
|
|
AARCH64_PAUTH_BUILTIN_PACIB1716,
|
2017-01-20 01:10:11 +01:00
|
|
|
AARCH64_PAUTH_BUILTIN_XPACLRI,
|
aarch64-builtins.c (enum aarch64_type_qualifiers): Add qualifier_lane_pair_index.
gcc/ChangeLog:
2019-01-10 Tamar Christina <tamar.christina@arm.com>
* config/aarch64/aarch64-builtins.c (enum aarch64_type_qualifiers): Add qualifier_lane_pair_index.
(emit-rtl.h): Include.
(TYPES_QUADOP_LANE_PAIR): New.
(aarch64_simd_expand_args): Use it.
(aarch64_simd_expand_builtin): Likewise.
(AARCH64_SIMD_FCMLA_LANEQ_BUILTINS, aarch64_fcmla_laneq_builtin_datum): New.
(FCMLA_LANEQ_BUILTIN, AARCH64_SIMD_FCMLA_LANEQ_BUILTIN_BASE,
AARCH64_SIMD_FCMLA_LANEQ_BUILTINS, aarch64_fcmla_lane_builtin_data,
aarch64_init_fcmla_laneq_builtins, aarch64_expand_fcmla_builtin): New.
(aarch64_init_builtins): Add aarch64_init_fcmla_laneq_builtins.
(aarch64_expand_buildin): Add AARCH64_SIMD_BUILTIN_FCMLA_LANEQ0_V2SF,
AARCH64_SIMD_BUILTIN_FCMLA_LANEQ90_V2SF, AARCH64_SIMD_BUILTIN_FCMLA_LANEQ180_V2SF,
AARCH64_SIMD_BUILTIN_FCMLA_LANEQ2700_V2SF, AARCH64_SIMD_BUILTIN_FCMLA_LANEQ0_V4HF,
AARCH64_SIMD_BUILTIN_FCMLA_LANEQ90_V4HF, AARCH64_SIMD_BUILTIN_FCMLA_LANEQ180_V4HF,
AARCH64_SIMD_BUILTIN_FCMLA_LANEQ270_V4HF.
* config/aarch64/iterators.md (FCMLA_maybe_lane): New.
* config/aarch64/aarch64-c.c (aarch64_update_cpp_builtins): Add __ARM_FEATURE_COMPLEX.
* config/aarch64/aarch64-simd-builtins.def (fcadd90, fcadd270, fcmla0, fcmla90,
fcmla180, fcmla270, fcmla_lane0, fcmla_lane90, fcmla_lane180, fcmla_lane270,
fcmla_laneq0, fcmla_laneq90, fcmla_laneq180, fcmla_laneq270,
fcmlaq_lane0, fcmlaq_lane90, fcmlaq_lane180, fcmlaq_lane270): New.
* config/aarch64/aarch64-simd.md (aarch64_fcmla_lane<rot><mode>,
aarch64_fcmla_laneq<rot>v4hf, aarch64_fcmlaq_lane<rot><mode>,aarch64_fcadd<rot><mode>,
aarch64_fcmla<rot><mode>): New.
* config/aarch64/arm_neon.h:
(vcadd_rot90_f16): New.
(vcaddq_rot90_f16): New.
(vcadd_rot270_f16): New.
(vcaddq_rot270_f16): New.
(vcmla_f16): New.
(vcmlaq_f16): New.
(vcmla_lane_f16): New.
(vcmla_laneq_f16): New.
(vcmlaq_lane_f16): New.
(vcmlaq_rot90_lane_f16): New.
(vcmla_rot90_laneq_f16): New.
(vcmla_rot90_lane_f16): New.
(vcmlaq_rot90_f16): New.
(vcmla_rot90_f16): New.
(vcmlaq_laneq_f16): New.
(vcmla_rot180_laneq_f16): New.
(vcmla_rot180_lane_f16): New.
(vcmlaq_rot180_f16): New.
(vcmla_rot180_f16): New.
(vcmlaq_rot90_laneq_f16): New.
(vcmlaq_rot270_laneq_f16): New.
(vcmlaq_rot270_lane_f16): New.
(vcmla_rot270_laneq_f16): New.
(vcmlaq_rot270_f16): New.
(vcmla_rot270_f16): New.
(vcmlaq_rot180_laneq_f16): New.
(vcmlaq_rot180_lane_f16): New.
(vcmla_rot270_lane_f16): New.
(vcadd_rot90_f32): New.
(vcaddq_rot90_f32): New.
(vcaddq_rot90_f64): New.
(vcadd_rot270_f32): New.
(vcaddq_rot270_f32): New.
(vcaddq_rot270_f64): New.
(vcmla_f32): New.
(vcmlaq_f32): New.
(vcmlaq_f64): New.
(vcmla_lane_f32): New.
(vcmla_laneq_f32): New.
(vcmlaq_lane_f32): New.
(vcmlaq_laneq_f32): New.
(vcmla_rot90_f32): New.
(vcmlaq_rot90_f32): New.
(vcmlaq_rot90_f64): New.
(vcmla_rot90_lane_f32): New.
(vcmla_rot90_laneq_f32): New.
(vcmlaq_rot90_lane_f32): New.
(vcmlaq_rot90_laneq_f32): New.
(vcmla_rot180_f32): New.
(vcmlaq_rot180_f32): New.
(vcmlaq_rot180_f64): New.
(vcmla_rot180_lane_f32): New.
(vcmla_rot180_laneq_f32): New.
(vcmlaq_rot180_lane_f32): New.
(vcmlaq_rot180_laneq_f32): New.
(vcmla_rot270_f32): New.
(vcmlaq_rot270_f32): New.
(vcmlaq_rot270_f64): New.
(vcmla_rot270_lane_f32): New.
(vcmla_rot270_laneq_f32): New.
(vcmlaq_rot270_lane_f32): New.
(vcmlaq_rot270_laneq_f32): New.
* config/aarch64/aarch64.h (TARGET_COMPLEX): New.
* config/aarch64/iterators.md (UNSPEC_FCADD90, UNSPEC_FCADD270,
UNSPEC_FCMLA, UNSPEC_FCMLA90, UNSPEC_FCMLA180, UNSPEC_FCMLA270): New.
(FCADD, FCMLA): New.
(rot): New.
* config/arm/types.md (neon_fcadd, neon_fcmla): New.
gcc/testsuite/ChangeLog:
2019-01-10 Tamar Christina <tamar.christina@arm.com>
* gcc.target/aarch64/advsimd-intrinsics/vector-complex.c: New test.
* gcc.target/aarch64/advsimd-intrinsics/vector-complex_f16.c: New test.
From-SVN: r267795
2019-01-10 04:30:59 +01:00
|
|
|
/* Special cased Armv8.3-A Complex FMA by Lane quad Builtins. */
|
|
|
|
AARCH64_SIMD_FCMLA_LANEQ_BUILTIN_BASE,
|
|
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AARCH64_SIMD_FCMLA_LANEQ_BUILTINS
|
2019-09-03 10:40:30 +02:00
|
|
|
/* Builtin for Arm8.3-a Javascript conversion instruction. */
|
|
|
|
AARCH64_JSCVT,
|
[GCC, AArch64] Enable Transactional Memory Extension
This patch enables the new Transactional Memory Extension announced recently
as part of Arm's new architecture technologies.
We introduce a new optional extension "tme" to enable this. The following
instructions are part of the extension:
* tstart <Xt>
* ttest <Xt>
* tcommit
* tcancel #<imm>
We have also added ACLE intrinsics for the instructions.
*** gcc/ChangeLog ***
2019-07-31 Sudakshina Das <sudi.das@arm.com>
* config/aarch64/aarch64-builtins.c (enum aarch64_builtins): Add
AARCH64_TME_BUILTIN_TSTART, AARCH64_TME_BUILTIN_TCOMMIT,
AARCH64_TME_BUILTIN_TTEST and AARCH64_TME_BUILTIN_TCANCEL.
(aarch64_init_tme_builtins): New.
(aarch64_init_builtins): Call aarch64_init_tme_builtins.
(aarch64_expand_builtin_tme): New.
(aarch64_expand_builtin): Handle TME builtins.
* config/aarch64/aarch64-c.c (aarch64_update_cpp_builtins): Define
__ARM_FEATURE_TME when enabled.
* config/aarch64/aarch64-option-extensions.def: Add "tme".
* config/aarch64/aarch64.h (AARCH64_FL_TME, AARCH64_ISA_TME): New.
(TARGET_TME): New.
* config/aarch64/aarch64.md (define_c_enum "unspec"): Add UNSPEC_TTEST.
(define_c_enum "unspecv"): Add UNSPECV_TSTART, UNSPECV_TCOMMIT and
UNSPECV_TCANCEL.
(tstart, ttest, tcommit, tcancel): New instructions.
* config/aarch64/arm_acle.h (__tstart, __tcommit): New.
(__tcancel, __ttest): New.
(_TMFAILURE_REASON, _TMFAILURE_RTRY, _TMFAILURE_CNCL): New macro.
(_TMFAILURE_MEM, _TMFAILURE_IMP, _TMFAILURE_ERR): Likewise.
(_TMFAILURE_SIZE, _TMFAILURE_NEST, _TMFAILURE_DBG): Likewise.
(_TMFAILURE_INT, _TMFAILURE_TRIVIAL): Likewise.
* config/arm/types.md: Add new tme type attr.
* doc/invoke.texi: Document "tme".
*** gcc/testsuite/ChangeLog ***
2019-07-31 Sudakshina Das <sudi.das@arm.com>
* gcc.target/aarch64/acle/tme.c: New test.
* gcc.target/aarch64/pragma_cpp_predefs_2.c: New test.
From-SVN: r273926
2019-07-31 11:19:53 +02:00
|
|
|
/* TME builtins. */
|
|
|
|
AARCH64_TME_BUILTIN_TSTART,
|
|
|
|
AARCH64_TME_BUILTIN_TCOMMIT,
|
|
|
|
AARCH64_TME_BUILTIN_TTEST,
|
|
|
|
AARCH64_TME_BUILTIN_TCANCEL,
|
2019-10-21 12:52:05 +02:00
|
|
|
/* Armv8.5-a RNG instruction builtins. */
|
|
|
|
AARCH64_BUILTIN_RNG_RNDR,
|
|
|
|
AARCH64_BUILTIN_RNG_RNDRRS,
|
[AArch64] Implement Armv8.5-A memory tagging (MTE) intrinsics
2019-11-19 Dennis Zhang <dennis.zhang@arm.com>
* config/aarch64/aarch64-builtins.c (enum aarch64_builtins): Add
AARCH64_MEMTAG_BUILTIN_START, AARCH64_MEMTAG_BUILTIN_IRG,
AARCH64_MEMTAG_BUILTIN_GMI, AARCH64_MEMTAG_BUILTIN_SUBP,
AARCH64_MEMTAG_BUILTIN_INC_TAG, AARCH64_MEMTAG_BUILTIN_SET_TAG,
AARCH64_MEMTAG_BUILTIN_GET_TAG, and AARCH64_MEMTAG_BUILTIN_END.
(aarch64_init_memtag_builtins): New.
(AARCH64_INIT_MEMTAG_BUILTINS_DECL): New macro.
(aarch64_general_init_builtins): Call aarch64_init_memtag_builtins.
(aarch64_expand_builtin_memtag): New.
(aarch64_general_expand_builtin): Call aarch64_expand_builtin_memtag.
(AARCH64_BUILTIN_SUBCODE): New macro.
(aarch64_resolve_overloaded_memtag): New.
(aarch64_resolve_overloaded_builtin_general): New. Call
aarch64_resolve_overloaded_memtag to handle overloaded MTE builtins.
* config/aarch64/aarch64-c.c (aarch64_update_cpp_builtins): Define
__ARM_FEATURE_MEMORY_TAGGING when enabled.
(aarch64_resolve_overloaded_builtin): Call
aarch64_resolve_overloaded_builtin_general.
* config/aarch64/aarch64-protos.h
(aarch64_resolve_overloaded_builtin_general): New declaration.
* config/aarch64/aarch64.h (AARCH64_ISA_MEMTAG): New macro.
(TARGET_MEMTAG): Likewise.
* config/aarch64/aarch64.md (UNSPEC_GEN_TAG): New unspec.
(UNSPEC_GEN_TAG_RND, and UNSPEC_TAG_SPACE): Likewise.
(irg, gmi, subp, addg, ldg, stg): New instructions.
* config/aarch64/arm_acle.h (__arm_mte_create_random_tag): New macro.
(__arm_mte_exclude_tag, __arm_mte_ptrdiff): Likewise.
(__arm_mte_increment_tag, __arm_mte_set_tag): Likewise.
(__arm_mte_get_tag): Likewise.
* config/aarch64/predicates.md (aarch64_memtag_tag_offset): New.
(aarch64_granule16_uimm6, aarch64_granule16_simm9): New.
* config/arm/types.md (memtag): New.
* doc/invoke.texi (-memtag): Update description.
2019-11-19 Dennis Zhang <dennis.zhang@arm.com>
* gcc.target/aarch64/acle/memtag_1.c: New test.
* gcc.target/aarch64/acle/memtag_2.c: New test.
* gcc.target/aarch64/acle/memtag_3.c: New test.
From-SVN: r278444
2019-11-19 14:43:39 +01:00
|
|
|
/* MEMTAG builtins. */
|
|
|
|
AARCH64_MEMTAG_BUILTIN_START,
|
|
|
|
AARCH64_MEMTAG_BUILTIN_IRG,
|
|
|
|
AARCH64_MEMTAG_BUILTIN_GMI,
|
|
|
|
AARCH64_MEMTAG_BUILTIN_SUBP,
|
|
|
|
AARCH64_MEMTAG_BUILTIN_INC_TAG,
|
|
|
|
AARCH64_MEMTAG_BUILTIN_SET_TAG,
|
|
|
|
AARCH64_MEMTAG_BUILTIN_GET_TAG,
|
|
|
|
AARCH64_MEMTAG_BUILTIN_END,
|
2021-12-14 15:03:38 +01:00
|
|
|
/* LS64 builtins. */
|
|
|
|
AARCH64_LS64_BUILTIN_LD64B,
|
|
|
|
AARCH64_LS64_BUILTIN_ST64B,
|
|
|
|
AARCH64_LS64_BUILTIN_ST64BV,
|
|
|
|
AARCH64_LS64_BUILTIN_ST64BV0,
|
2012-11-20 13:10:37 +01:00
|
|
|
AARCH64_BUILTIN_MAX
|
2012-10-23 19:02:30 +02:00
|
|
|
};
|
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|
2014-06-11 11:17:18 +02:00
|
|
|
#undef CRC32_BUILTIN
|
|
|
|
#define CRC32_BUILTIN(N, M) \
|
[1/77] Add an E_ prefix to mode names
Later patches will add wrapper types for specific classes
of mode. E.g. SImode will be a scalar_int_mode, SFmode will be a
scalar_float_mode, etc. This patch prepares for that change by adding
an E_ prefix to the mode enum values. It also adds #defines that map
the unprefixed names to the prefixed names; e.g:
#define QImode E_QImode
Later patches will change this to use things like scalar_int_mode
where appropriate.
The patch continues to use enum values to initialise static data.
This isn't necessary for correctness, but it cuts down on the amount
of load-time initialisation and shouldn't have any downsides.
The patch also changes things like:
cmp_mode == DImode ? DFmode : DImode
to:
cmp_mode == DImode ? E_DFmode : E_DImode
This is because DImode and DFmode will eventually be different
classes, so the original ?: wouldn't be well-formed.
2017-08-30 Richard Sandiford <richard.sandiford@linaro.org>
Alan Hayward <alan.hayward@arm.com>
David Sherwood <david.sherwood@arm.com>
gcc/
* genmodes.c (mode_size_inline): Add an E_ prefix to mode names.
(mode_nunits_inline): Likewise.
(mode_inner_inline): Likewise.
(mode_unit_size_inline): Likewise.
(mode_unit_precision_inline): Likewise.
(emit_insn_modes_h): Likewise. Also emit a #define of the
unprefixed name.
(emit_mode_wider): Add an E_ prefix to mode names.
(emit_mode_complex): Likewise.
(emit_mode_inner): Likewise.
(emit_mode_adjustments): Likewise.
(emit_mode_int_n): Likewise.
* config/aarch64/aarch64-builtins.c (v8qi_UP, v4hi_UP, v4hf_UP)
(v2si_UP, v2sf_UP, v1df_UP, di_UP, df_UP, v16qi_UP, v8hi_UP, v8hf_UP)
(v4si_UP, v4sf_UP, v2di_UP, v2df_UP, ti_UP, oi_UP, ci_UP, xi_UP)
(si_UP, sf_UP, hi_UP, hf_UP, qi_UP): Likewise.
(CRC32_BUILTIN, ENTRY): Likewise.
* config/aarch64/aarch64.c (aarch64_push_regs): Likewise.
(aarch64_pop_regs): Likewise.
(aarch64_process_components): Likewise.
* config/alpha/alpha.c (alpha_emit_conditional_move): Likewise.
* config/arm/arm-builtins.c (v8qi_UP, v4hi_UP, v4hf_UP, v2si_UP)
(v2sf_UP, di_UP, v16qi_UP, v8hi_UP, v8hf_UP, v4si_UP, v4sf_UP)
(v2di_UP, ti_UP, ei_UP, oi_UP, hf_UP, si_UP, void_UP): Likewise.
* config/arm/arm.c (arm_init_libfuncs): Likewise.
* config/i386/i386-builtin-types.awk (ix86_builtin_type_vect_mode):
Likewise.
* config/i386/i386-builtin.def (pcmpestr): Likewise.
(pcmpistr): Likewise.
* config/microblaze/microblaze.c (double_memory_operand): Likewise.
* config/mmix/mmix.c (mmix_output_condition): Likewise.
* config/powerpcspe/powerpcspe.c (rs6000_init_hard_regno_mode_ok):
Likewise.
* config/rl78/rl78.c (mduc_regs): Likewise.
* config/rs6000/rs6000.c (rs6000_init_hard_regno_mode_ok): Likewise.
(htm_expand_builtin): Likewise.
* config/sh/sh.h (REGISTER_NATURAL_MODE): Likewise.
* config/sparc/sparc.c (emit_save_or_restore_regs): Likewise.
* config/xtensa/xtensa.c (print_operand): Likewise.
* expmed.h (NUM_MODE_PARTIAL_INT): Likewise.
(NUM_MODE_VECTOR_INT): Likewise.
* genoutput.c (null_operand): Likewise.
(output_operand_data): Likewise.
* genrecog.c (print_parameter_value): Likewise.
* lra.c (debug_operand_data): Likewise.
Co-Authored-By: Alan Hayward <alan.hayward@arm.com>
Co-Authored-By: David Sherwood <david.sherwood@arm.com>
From-SVN: r251452
2017-08-30 13:08:14 +02:00
|
|
|
{"__builtin_aarch64_"#N, E_##M##mode, CODE_FOR_aarch64_##N, AARCH64_BUILTIN_##N},
|
2014-06-11 11:17:18 +02:00
|
|
|
|
|
|
|
static aarch64_crc_builtin_datum aarch64_crc_builtin_data[] = {
|
|
|
|
AARCH64_CRC32_BUILTINS
|
|
|
|
};
|
|
|
|
|
aarch64-builtins.c (enum aarch64_type_qualifiers): Add qualifier_lane_pair_index.
gcc/ChangeLog:
2019-01-10 Tamar Christina <tamar.christina@arm.com>
* config/aarch64/aarch64-builtins.c (enum aarch64_type_qualifiers): Add qualifier_lane_pair_index.
(emit-rtl.h): Include.
(TYPES_QUADOP_LANE_PAIR): New.
(aarch64_simd_expand_args): Use it.
(aarch64_simd_expand_builtin): Likewise.
(AARCH64_SIMD_FCMLA_LANEQ_BUILTINS, aarch64_fcmla_laneq_builtin_datum): New.
(FCMLA_LANEQ_BUILTIN, AARCH64_SIMD_FCMLA_LANEQ_BUILTIN_BASE,
AARCH64_SIMD_FCMLA_LANEQ_BUILTINS, aarch64_fcmla_lane_builtin_data,
aarch64_init_fcmla_laneq_builtins, aarch64_expand_fcmla_builtin): New.
(aarch64_init_builtins): Add aarch64_init_fcmla_laneq_builtins.
(aarch64_expand_buildin): Add AARCH64_SIMD_BUILTIN_FCMLA_LANEQ0_V2SF,
AARCH64_SIMD_BUILTIN_FCMLA_LANEQ90_V2SF, AARCH64_SIMD_BUILTIN_FCMLA_LANEQ180_V2SF,
AARCH64_SIMD_BUILTIN_FCMLA_LANEQ2700_V2SF, AARCH64_SIMD_BUILTIN_FCMLA_LANEQ0_V4HF,
AARCH64_SIMD_BUILTIN_FCMLA_LANEQ90_V4HF, AARCH64_SIMD_BUILTIN_FCMLA_LANEQ180_V4HF,
AARCH64_SIMD_BUILTIN_FCMLA_LANEQ270_V4HF.
* config/aarch64/iterators.md (FCMLA_maybe_lane): New.
* config/aarch64/aarch64-c.c (aarch64_update_cpp_builtins): Add __ARM_FEATURE_COMPLEX.
* config/aarch64/aarch64-simd-builtins.def (fcadd90, fcadd270, fcmla0, fcmla90,
fcmla180, fcmla270, fcmla_lane0, fcmla_lane90, fcmla_lane180, fcmla_lane270,
fcmla_laneq0, fcmla_laneq90, fcmla_laneq180, fcmla_laneq270,
fcmlaq_lane0, fcmlaq_lane90, fcmlaq_lane180, fcmlaq_lane270): New.
* config/aarch64/aarch64-simd.md (aarch64_fcmla_lane<rot><mode>,
aarch64_fcmla_laneq<rot>v4hf, aarch64_fcmlaq_lane<rot><mode>,aarch64_fcadd<rot><mode>,
aarch64_fcmla<rot><mode>): New.
* config/aarch64/arm_neon.h:
(vcadd_rot90_f16): New.
(vcaddq_rot90_f16): New.
(vcadd_rot270_f16): New.
(vcaddq_rot270_f16): New.
(vcmla_f16): New.
(vcmlaq_f16): New.
(vcmla_lane_f16): New.
(vcmla_laneq_f16): New.
(vcmlaq_lane_f16): New.
(vcmlaq_rot90_lane_f16): New.
(vcmla_rot90_laneq_f16): New.
(vcmla_rot90_lane_f16): New.
(vcmlaq_rot90_f16): New.
(vcmla_rot90_f16): New.
(vcmlaq_laneq_f16): New.
(vcmla_rot180_laneq_f16): New.
(vcmla_rot180_lane_f16): New.
(vcmlaq_rot180_f16): New.
(vcmla_rot180_f16): New.
(vcmlaq_rot90_laneq_f16): New.
(vcmlaq_rot270_laneq_f16): New.
(vcmlaq_rot270_lane_f16): New.
(vcmla_rot270_laneq_f16): New.
(vcmlaq_rot270_f16): New.
(vcmla_rot270_f16): New.
(vcmlaq_rot180_laneq_f16): New.
(vcmlaq_rot180_lane_f16): New.
(vcmla_rot270_lane_f16): New.
(vcadd_rot90_f32): New.
(vcaddq_rot90_f32): New.
(vcaddq_rot90_f64): New.
(vcadd_rot270_f32): New.
(vcaddq_rot270_f32): New.
(vcaddq_rot270_f64): New.
(vcmla_f32): New.
(vcmlaq_f32): New.
(vcmlaq_f64): New.
(vcmla_lane_f32): New.
(vcmla_laneq_f32): New.
(vcmlaq_lane_f32): New.
(vcmlaq_laneq_f32): New.
(vcmla_rot90_f32): New.
(vcmlaq_rot90_f32): New.
(vcmlaq_rot90_f64): New.
(vcmla_rot90_lane_f32): New.
(vcmla_rot90_laneq_f32): New.
(vcmlaq_rot90_lane_f32): New.
(vcmlaq_rot90_laneq_f32): New.
(vcmla_rot180_f32): New.
(vcmlaq_rot180_f32): New.
(vcmlaq_rot180_f64): New.
(vcmla_rot180_lane_f32): New.
(vcmla_rot180_laneq_f32): New.
(vcmlaq_rot180_lane_f32): New.
(vcmlaq_rot180_laneq_f32): New.
(vcmla_rot270_f32): New.
(vcmlaq_rot270_f32): New.
(vcmlaq_rot270_f64): New.
(vcmla_rot270_lane_f32): New.
(vcmla_rot270_laneq_f32): New.
(vcmlaq_rot270_lane_f32): New.
(vcmlaq_rot270_laneq_f32): New.
* config/aarch64/aarch64.h (TARGET_COMPLEX): New.
* config/aarch64/iterators.md (UNSPEC_FCADD90, UNSPEC_FCADD270,
UNSPEC_FCMLA, UNSPEC_FCMLA90, UNSPEC_FCMLA180, UNSPEC_FCMLA270): New.
(FCADD, FCMLA): New.
(rot): New.
* config/arm/types.md (neon_fcadd, neon_fcmla): New.
gcc/testsuite/ChangeLog:
2019-01-10 Tamar Christina <tamar.christina@arm.com>
* gcc.target/aarch64/advsimd-intrinsics/vector-complex.c: New test.
* gcc.target/aarch64/advsimd-intrinsics/vector-complex_f16.c: New test.
From-SVN: r267795
2019-01-10 04:30:59 +01:00
|
|
|
|
|
|
|
#undef FCMLA_LANEQ_BUILTIN
|
|
|
|
#define FCMLA_LANEQ_BUILTIN(I, N, X, M, T) \
|
|
|
|
{"__builtin_aarch64_fcmla_laneq"#I#N, E_##M##mode, CODE_FOR_aarch64_##X##I##N, \
|
|
|
|
AARCH64_SIMD_BUILTIN_FCMLA_LANEQ##I##_##M, T},
|
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|
|
|
|
|
/* This structure contains how to manage the mapping form the builtin to the
|
|
|
|
instruction to generate in the backend and how to invoke the instruction. */
|
2019-02-07 12:05:22 +01:00
|
|
|
static aarch64_fcmla_laneq_builtin_datum aarch64_fcmla_lane_builtin_data[] = {
|
aarch64-builtins.c (enum aarch64_type_qualifiers): Add qualifier_lane_pair_index.
gcc/ChangeLog:
2019-01-10 Tamar Christina <tamar.christina@arm.com>
* config/aarch64/aarch64-builtins.c (enum aarch64_type_qualifiers): Add qualifier_lane_pair_index.
(emit-rtl.h): Include.
(TYPES_QUADOP_LANE_PAIR): New.
(aarch64_simd_expand_args): Use it.
(aarch64_simd_expand_builtin): Likewise.
(AARCH64_SIMD_FCMLA_LANEQ_BUILTINS, aarch64_fcmla_laneq_builtin_datum): New.
(FCMLA_LANEQ_BUILTIN, AARCH64_SIMD_FCMLA_LANEQ_BUILTIN_BASE,
AARCH64_SIMD_FCMLA_LANEQ_BUILTINS, aarch64_fcmla_lane_builtin_data,
aarch64_init_fcmla_laneq_builtins, aarch64_expand_fcmla_builtin): New.
(aarch64_init_builtins): Add aarch64_init_fcmla_laneq_builtins.
(aarch64_expand_buildin): Add AARCH64_SIMD_BUILTIN_FCMLA_LANEQ0_V2SF,
AARCH64_SIMD_BUILTIN_FCMLA_LANEQ90_V2SF, AARCH64_SIMD_BUILTIN_FCMLA_LANEQ180_V2SF,
AARCH64_SIMD_BUILTIN_FCMLA_LANEQ2700_V2SF, AARCH64_SIMD_BUILTIN_FCMLA_LANEQ0_V4HF,
AARCH64_SIMD_BUILTIN_FCMLA_LANEQ90_V4HF, AARCH64_SIMD_BUILTIN_FCMLA_LANEQ180_V4HF,
AARCH64_SIMD_BUILTIN_FCMLA_LANEQ270_V4HF.
* config/aarch64/iterators.md (FCMLA_maybe_lane): New.
* config/aarch64/aarch64-c.c (aarch64_update_cpp_builtins): Add __ARM_FEATURE_COMPLEX.
* config/aarch64/aarch64-simd-builtins.def (fcadd90, fcadd270, fcmla0, fcmla90,
fcmla180, fcmla270, fcmla_lane0, fcmla_lane90, fcmla_lane180, fcmla_lane270,
fcmla_laneq0, fcmla_laneq90, fcmla_laneq180, fcmla_laneq270,
fcmlaq_lane0, fcmlaq_lane90, fcmlaq_lane180, fcmlaq_lane270): New.
* config/aarch64/aarch64-simd.md (aarch64_fcmla_lane<rot><mode>,
aarch64_fcmla_laneq<rot>v4hf, aarch64_fcmlaq_lane<rot><mode>,aarch64_fcadd<rot><mode>,
aarch64_fcmla<rot><mode>): New.
* config/aarch64/arm_neon.h:
(vcadd_rot90_f16): New.
(vcaddq_rot90_f16): New.
(vcadd_rot270_f16): New.
(vcaddq_rot270_f16): New.
(vcmla_f16): New.
(vcmlaq_f16): New.
(vcmla_lane_f16): New.
(vcmla_laneq_f16): New.
(vcmlaq_lane_f16): New.
(vcmlaq_rot90_lane_f16): New.
(vcmla_rot90_laneq_f16): New.
(vcmla_rot90_lane_f16): New.
(vcmlaq_rot90_f16): New.
(vcmla_rot90_f16): New.
(vcmlaq_laneq_f16): New.
(vcmla_rot180_laneq_f16): New.
(vcmla_rot180_lane_f16): New.
(vcmlaq_rot180_f16): New.
(vcmla_rot180_f16): New.
(vcmlaq_rot90_laneq_f16): New.
(vcmlaq_rot270_laneq_f16): New.
(vcmlaq_rot270_lane_f16): New.
(vcmla_rot270_laneq_f16): New.
(vcmlaq_rot270_f16): New.
(vcmla_rot270_f16): New.
(vcmlaq_rot180_laneq_f16): New.
(vcmlaq_rot180_lane_f16): New.
(vcmla_rot270_lane_f16): New.
(vcadd_rot90_f32): New.
(vcaddq_rot90_f32): New.
(vcaddq_rot90_f64): New.
(vcadd_rot270_f32): New.
(vcaddq_rot270_f32): New.
(vcaddq_rot270_f64): New.
(vcmla_f32): New.
(vcmlaq_f32): New.
(vcmlaq_f64): New.
(vcmla_lane_f32): New.
(vcmla_laneq_f32): New.
(vcmlaq_lane_f32): New.
(vcmlaq_laneq_f32): New.
(vcmla_rot90_f32): New.
(vcmlaq_rot90_f32): New.
(vcmlaq_rot90_f64): New.
(vcmla_rot90_lane_f32): New.
(vcmla_rot90_laneq_f32): New.
(vcmlaq_rot90_lane_f32): New.
(vcmlaq_rot90_laneq_f32): New.
(vcmla_rot180_f32): New.
(vcmlaq_rot180_f32): New.
(vcmlaq_rot180_f64): New.
(vcmla_rot180_lane_f32): New.
(vcmla_rot180_laneq_f32): New.
(vcmlaq_rot180_lane_f32): New.
(vcmlaq_rot180_laneq_f32): New.
(vcmla_rot270_f32): New.
(vcmlaq_rot270_f32): New.
(vcmlaq_rot270_f64): New.
(vcmla_rot270_lane_f32): New.
(vcmla_rot270_laneq_f32): New.
(vcmlaq_rot270_lane_f32): New.
(vcmlaq_rot270_laneq_f32): New.
* config/aarch64/aarch64.h (TARGET_COMPLEX): New.
* config/aarch64/iterators.md (UNSPEC_FCADD90, UNSPEC_FCADD270,
UNSPEC_FCMLA, UNSPEC_FCMLA90, UNSPEC_FCMLA180, UNSPEC_FCMLA270): New.
(FCADD, FCMLA): New.
(rot): New.
* config/arm/types.md (neon_fcadd, neon_fcmla): New.
gcc/testsuite/ChangeLog:
2019-01-10 Tamar Christina <tamar.christina@arm.com>
* gcc.target/aarch64/advsimd-intrinsics/vector-complex.c: New test.
* gcc.target/aarch64/advsimd-intrinsics/vector-complex_f16.c: New test.
From-SVN: r267795
2019-01-10 04:30:59 +01:00
|
|
|
AARCH64_SIMD_FCMLA_LANEQ_BUILTINS
|
|
|
|
};
|
|
|
|
|
2014-06-11 11:17:18 +02:00
|
|
|
#undef CRC32_BUILTIN
|
|
|
|
|
2012-11-26 18:48:13 +01:00
|
|
|
static GTY(()) tree aarch64_builtin_decls[AARCH64_BUILTIN_MAX];
|
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|
|
2012-10-23 19:02:30 +02:00
|
|
|
#define NUM_DREG_TYPES 6
|
|
|
|
#define NUM_QREG_TYPES 6
|
|
|
|
|
[AArch64] Restructure arm_neon.h vector types.
2014-11-05 Tejas Belagod <tejas.belagod@arm.com>
* config/aarch64/aarch64-builtins.c
(aarch64_build_scalar_type): Remove.
(aarch64_scalar_builtin_types, aarch64_simd_type,
aarch64_simd_type, aarch64_mangle_builtin_scalar_type,
aarch64_mangle_builtin_vector_type,
aarch64_mangle_builtin_type, aarch64_simd_builtin_std_type,
aarch64_lookup_simd_builtin_type, aarch64_simd_builtin_type,
aarch64_init_simd_builtin_types,
aarch64_init_simd_builtin_scalar_types): New.
(aarch64_init_simd_builtins): Refactor.
(aarch64_init_crc32_builtins): Fixup with qualifier.
* config/aarch64/aarch64-protos.h
(aarch64_mangle_builtin_type): Export.
* config/aarch64/aarch64-simd-builtin-types.def: New.
* config/aarch64/aarch64.c (aarch64_simd_mangle_map): Remove.
(aarch64_mangle_type): Refactor.
* config/aarch64/arm_neon.h: Declare vector types based on
internal types.
* config/aarch64/t-aarch64: Update dependency.
From-SVN: r217114
2014-11-05 09:26:54 +01:00
|
|
|
/* Internal scalar builtin types. These types are used to support
|
|
|
|
neon intrinsic builtins. They are _not_ user-visible types. Therefore
|
|
|
|
the mangling for these types are implementation defined. */
|
|
|
|
const char *aarch64_scalar_builtin_types[] = {
|
|
|
|
"__builtin_aarch64_simd_qi",
|
|
|
|
"__builtin_aarch64_simd_hi",
|
|
|
|
"__builtin_aarch64_simd_si",
|
[AArch64] vld{2,3,4}{,_lane,_dup}, vcombine, vcreate
gcc/:
* config/aarch64/aarch64.c (aarch64_split_simd_combine): Add V4HFmode.
* config/aarch64/aarch64-builtins.c (VAR13, VAR14): New.
(aarch64_scalar_builtin_types, aarch64_init_simd_builtin_scalar_types):
Add __builtin_aarch64_simd_hf.
* config/aarch64/arm_neon.h (float16x4x2_t, float16x8x2_t,
float16x4x3_t, float16x8x3_t, float16x4x4_t, float16x8x4_t,
vcombine_f16, vst2_lane_f16, vst2q_lane_f16, vst3_lane_f16,
vst3q_lane_f16, vst4_lane_f16, vst4q_lane_f16, vld2_f16, vld2q_f16,
vld3_f16, vld3q_f16, vld4_f16, vld4q_f16, vld2_dup_f16, vld2q_dup_f16,
vld3_dup_f16, vld3q_dup_f16, vld4_dup_f16, vld4q_dup_f16,
vld2_lane_f16, vld2q_lane_f16, vld3_lane_f16, vld3q_lane_f16,
vld4_lane_f16, vld4q_lane_f16, vst2_f16, vst2q_f16, vst3_f16,
vst3q_f16, vst4_f16, vst4q_f16, vcreate_f16): New.
* config/aarch64/iterators.md (VALLDIF, Vtype, Vetype, Vbtype,
V_cmp_result, v_cmp_result): Add cases for V4HF and V8HF.
(VDC, Vdbl): Add V4HF.
gcc/testsuite/:
* gcc.target/aarch64/vldN_1.c: Add float16x4_t and float16x8_t cases.
* gcc.target/aarch64/vldN_dup_1.c: Likewise.
* gcc.target/aarch64/vldN_lane_1.c: Likewise.
(main): update orig_data to avoid float16 NaN on bigendian.
From-SVN: r227543
2015-09-08 21:03:53 +02:00
|
|
|
"__builtin_aarch64_simd_hf",
|
[AArch64] Restructure arm_neon.h vector types.
2014-11-05 Tejas Belagod <tejas.belagod@arm.com>
* config/aarch64/aarch64-builtins.c
(aarch64_build_scalar_type): Remove.
(aarch64_scalar_builtin_types, aarch64_simd_type,
aarch64_simd_type, aarch64_mangle_builtin_scalar_type,
aarch64_mangle_builtin_vector_type,
aarch64_mangle_builtin_type, aarch64_simd_builtin_std_type,
aarch64_lookup_simd_builtin_type, aarch64_simd_builtin_type,
aarch64_init_simd_builtin_types,
aarch64_init_simd_builtin_scalar_types): New.
(aarch64_init_simd_builtins): Refactor.
(aarch64_init_crc32_builtins): Fixup with qualifier.
* config/aarch64/aarch64-protos.h
(aarch64_mangle_builtin_type): Export.
* config/aarch64/aarch64-simd-builtin-types.def: New.
* config/aarch64/aarch64.c (aarch64_simd_mangle_map): Remove.
(aarch64_mangle_type): Refactor.
* config/aarch64/arm_neon.h: Declare vector types based on
internal types.
* config/aarch64/t-aarch64: Update dependency.
From-SVN: r217114
2014-11-05 09:26:54 +01:00
|
|
|
"__builtin_aarch64_simd_sf",
|
|
|
|
"__builtin_aarch64_simd_di",
|
|
|
|
"__builtin_aarch64_simd_df",
|
|
|
|
"__builtin_aarch64_simd_poly8",
|
|
|
|
"__builtin_aarch64_simd_poly16",
|
|
|
|
"__builtin_aarch64_simd_poly64",
|
|
|
|
"__builtin_aarch64_simd_poly128",
|
|
|
|
"__builtin_aarch64_simd_ti",
|
|
|
|
"__builtin_aarch64_simd_uqi",
|
|
|
|
"__builtin_aarch64_simd_uhi",
|
|
|
|
"__builtin_aarch64_simd_usi",
|
|
|
|
"__builtin_aarch64_simd_udi",
|
|
|
|
"__builtin_aarch64_simd_ei",
|
|
|
|
"__builtin_aarch64_simd_oi",
|
|
|
|
"__builtin_aarch64_simd_ci",
|
|
|
|
"__builtin_aarch64_simd_xi",
|
aarch64: Add bfloat16 vldn/vstn intrinsics
This patch adds the load/store bfloat16 intrinsics to the AArch64 back-end.
ACLE documents are at https://developer.arm.com/docs/101028/latest
ISA documents are at https://developer.arm.com/docs/ddi0596/latest
2020-02-25 Mihail Ionescu <mihail.ionescu@arm.com>
gcc/
* config/aarch64/aarch64-builtins.c (aarch64_scalar_builtin_types):
Add simd_bf.
(aarch64_init_simd_builtin_scalar_types): Register simd_bf.
(VAR15, VAR16): New.
* config/aarch64/iterators.md (VALLDIF): Enable for V4BF and V8BF.
(VD): Enable for V4BF.
(VDC): Likewise.
(VQ): Enable for V8BF.
(VQ2): Likewise.
(VQ_NO2E): Likewise.
(VDBL, Vdbl): Add V4BF.
(V_INT_EQUIV, v_int_equiv): Add V4BF and V8BF.
* config/aarch64/arm_neon.h (bfloat16x4x2_t): New typedef.
(bfloat16x8x2_t): Likewise.
(bfloat16x4x3_t): Likewise.
(bfloat16x8x3_t): Likewise.
(bfloat16x4x4_t): Likewise.
(bfloat16x8x4_t): Likewise.
(vcombine_bf16): New.
(vld1_bf16, vld1_bf16_x2): New.
(vld1_bf16_x3, vld1_bf16_x4): New.
(vld1q_bf16, vld1q_bf16_x2): New.
(vld1q_bf16_x3, vld1q_bf16_x4): New.
(vld1_lane_bf16): New.
(vld1q_lane_bf16): New.
(vld1_dup_bf16): New.
(vld1q_dup_bf16): New.
(vld2_bf16): New.
(vld2q_bf16): New.
(vld2_dup_bf16): New.
(vld2q_dup_bf16): New.
(vld3_bf16): New.
(vld3q_bf16): New.
(vld3_dup_bf16): New.
(vld3q_dup_bf16): New.
(vld4_bf16): New.
(vld4q_bf16): New.
(vld4_dup_bf16): New.
(vld4q_dup_bf16): New.
(vst1_bf16, vst1_bf16_x2): New.
(vst1_bf16_x3, vst1_bf16_x4): New.
(vst1q_bf16, vst1q_bf16_x2): New.
(vst1q_bf16_x3, vst1q_bf16_x4): New.
(vst1_lane_bf16): New.
(vst1q_lane_bf16): New.
(vst2_bf16): New.
(vst2q_bf16): New.
(vst3_bf16): New.
(vst3q_bf16): New.
(vst4_bf16): New.
(vst4q_bf16): New.
gcc/testsuite/
* gcc.target/aarch64/advsimd-intrinsics/bf16_vstn.c: New test.
* gcc.target/aarch64/advsimd-intrinsics/bf16_vldn.c: New test.
2020-02-18 15:29:47 +01:00
|
|
|
"__builtin_aarch64_simd_bf",
|
[AArch64] Restructure arm_neon.h vector types.
2014-11-05 Tejas Belagod <tejas.belagod@arm.com>
* config/aarch64/aarch64-builtins.c
(aarch64_build_scalar_type): Remove.
(aarch64_scalar_builtin_types, aarch64_simd_type,
aarch64_simd_type, aarch64_mangle_builtin_scalar_type,
aarch64_mangle_builtin_vector_type,
aarch64_mangle_builtin_type, aarch64_simd_builtin_std_type,
aarch64_lookup_simd_builtin_type, aarch64_simd_builtin_type,
aarch64_init_simd_builtin_types,
aarch64_init_simd_builtin_scalar_types): New.
(aarch64_init_simd_builtins): Refactor.
(aarch64_init_crc32_builtins): Fixup with qualifier.
* config/aarch64/aarch64-protos.h
(aarch64_mangle_builtin_type): Export.
* config/aarch64/aarch64-simd-builtin-types.def: New.
* config/aarch64/aarch64.c (aarch64_simd_mangle_map): Remove.
(aarch64_mangle_type): Refactor.
* config/aarch64/arm_neon.h: Declare vector types based on
internal types.
* config/aarch64/t-aarch64: Update dependency.
From-SVN: r217114
2014-11-05 09:26:54 +01:00
|
|
|
NULL
|
|
|
|
};
|
2013-11-20 10:19:25 +01:00
|
|
|
|
[AArch64] Restructure arm_neon.h vector types.
2014-11-05 Tejas Belagod <tejas.belagod@arm.com>
* config/aarch64/aarch64-builtins.c
(aarch64_build_scalar_type): Remove.
(aarch64_scalar_builtin_types, aarch64_simd_type,
aarch64_simd_type, aarch64_mangle_builtin_scalar_type,
aarch64_mangle_builtin_vector_type,
aarch64_mangle_builtin_type, aarch64_simd_builtin_std_type,
aarch64_lookup_simd_builtin_type, aarch64_simd_builtin_type,
aarch64_init_simd_builtin_types,
aarch64_init_simd_builtin_scalar_types): New.
(aarch64_init_simd_builtins): Refactor.
(aarch64_init_crc32_builtins): Fixup with qualifier.
* config/aarch64/aarch64-protos.h
(aarch64_mangle_builtin_type): Export.
* config/aarch64/aarch64-simd-builtin-types.def: New.
* config/aarch64/aarch64.c (aarch64_simd_mangle_map): Remove.
(aarch64_mangle_type): Refactor.
* config/aarch64/arm_neon.h: Declare vector types based on
internal types.
* config/aarch64/t-aarch64: Update dependency.
From-SVN: r217114
2014-11-05 09:26:54 +01:00
|
|
|
#define ENTRY(E, M, Q, G) E,
|
|
|
|
enum aarch64_simd_type
|
|
|
|
{
|
|
|
|
#include "aarch64-simd-builtin-types.def"
|
|
|
|
ARM_NEON_H_TYPES_LAST
|
|
|
|
};
|
|
|
|
#undef ENTRY
|
2013-11-20 10:19:25 +01:00
|
|
|
|
2021-09-03 04:12:29 +02:00
|
|
|
struct GTY(()) aarch64_simd_type_info
|
2013-11-20 10:19:25 +01:00
|
|
|
{
|
[AArch64] Restructure arm_neon.h vector types.
2014-11-05 Tejas Belagod <tejas.belagod@arm.com>
* config/aarch64/aarch64-builtins.c
(aarch64_build_scalar_type): Remove.
(aarch64_scalar_builtin_types, aarch64_simd_type,
aarch64_simd_type, aarch64_mangle_builtin_scalar_type,
aarch64_mangle_builtin_vector_type,
aarch64_mangle_builtin_type, aarch64_simd_builtin_std_type,
aarch64_lookup_simd_builtin_type, aarch64_simd_builtin_type,
aarch64_init_simd_builtin_types,
aarch64_init_simd_builtin_scalar_types): New.
(aarch64_init_simd_builtins): Refactor.
(aarch64_init_crc32_builtins): Fixup with qualifier.
* config/aarch64/aarch64-protos.h
(aarch64_mangle_builtin_type): Export.
* config/aarch64/aarch64-simd-builtin-types.def: New.
* config/aarch64/aarch64.c (aarch64_simd_mangle_map): Remove.
(aarch64_mangle_type): Refactor.
* config/aarch64/arm_neon.h: Declare vector types based on
internal types.
* config/aarch64/t-aarch64: Update dependency.
From-SVN: r217114
2014-11-05 09:26:54 +01:00
|
|
|
enum aarch64_simd_type type;
|
|
|
|
|
|
|
|
/* Internal type name. */
|
|
|
|
const char *name;
|
|
|
|
|
|
|
|
/* Internal type name(mangled). The mangled names conform to the
|
|
|
|
AAPCS64 (see "Procedure Call Standard for the ARM 64-bit Architecture",
|
|
|
|
Appendix A). To qualify for emission with the mangled names defined in
|
|
|
|
that document, a vector type must not only be of the correct mode but also
|
|
|
|
be of the correct internal AdvSIMD vector type (e.g. __Int8x8_t); these
|
|
|
|
types are registered by aarch64_init_simd_builtin_types (). In other
|
|
|
|
words, vector types defined in other ways e.g. via vector_size attribute
|
|
|
|
will get default mangled names. */
|
|
|
|
const char *mangle;
|
|
|
|
|
|
|
|
/* Internal type. */
|
|
|
|
tree itype;
|
|
|
|
|
|
|
|
/* Element type. */
|
2013-11-20 10:19:25 +01:00
|
|
|
tree eltype;
|
|
|
|
|
[AArch64] Restructure arm_neon.h vector types.
2014-11-05 Tejas Belagod <tejas.belagod@arm.com>
* config/aarch64/aarch64-builtins.c
(aarch64_build_scalar_type): Remove.
(aarch64_scalar_builtin_types, aarch64_simd_type,
aarch64_simd_type, aarch64_mangle_builtin_scalar_type,
aarch64_mangle_builtin_vector_type,
aarch64_mangle_builtin_type, aarch64_simd_builtin_std_type,
aarch64_lookup_simd_builtin_type, aarch64_simd_builtin_type,
aarch64_init_simd_builtin_types,
aarch64_init_simd_builtin_scalar_types): New.
(aarch64_init_simd_builtins): Refactor.
(aarch64_init_crc32_builtins): Fixup with qualifier.
* config/aarch64/aarch64-protos.h
(aarch64_mangle_builtin_type): Export.
* config/aarch64/aarch64-simd-builtin-types.def: New.
* config/aarch64/aarch64.c (aarch64_simd_mangle_map): Remove.
(aarch64_mangle_type): Refactor.
* config/aarch64/arm_neon.h: Declare vector types based on
internal types.
* config/aarch64/t-aarch64: Update dependency.
From-SVN: r217114
2014-11-05 09:26:54 +01:00
|
|
|
/* Machine mode the internal type maps to. */
|
|
|
|
enum machine_mode mode;
|
2013-11-20 10:19:25 +01:00
|
|
|
|
[AArch64] Restructure arm_neon.h vector types.
2014-11-05 Tejas Belagod <tejas.belagod@arm.com>
* config/aarch64/aarch64-builtins.c
(aarch64_build_scalar_type): Remove.
(aarch64_scalar_builtin_types, aarch64_simd_type,
aarch64_simd_type, aarch64_mangle_builtin_scalar_type,
aarch64_mangle_builtin_vector_type,
aarch64_mangle_builtin_type, aarch64_simd_builtin_std_type,
aarch64_lookup_simd_builtin_type, aarch64_simd_builtin_type,
aarch64_init_simd_builtin_types,
aarch64_init_simd_builtin_scalar_types): New.
(aarch64_init_simd_builtins): Refactor.
(aarch64_init_crc32_builtins): Fixup with qualifier.
* config/aarch64/aarch64-protos.h
(aarch64_mangle_builtin_type): Export.
* config/aarch64/aarch64-simd-builtin-types.def: New.
* config/aarch64/aarch64.c (aarch64_simd_mangle_map): Remove.
(aarch64_mangle_type): Refactor.
* config/aarch64/arm_neon.h: Declare vector types based on
internal types.
* config/aarch64/t-aarch64: Update dependency.
From-SVN: r217114
2014-11-05 09:26:54 +01:00
|
|
|
/* Qualifiers. */
|
|
|
|
enum aarch64_type_qualifiers q;
|
|
|
|
};
|
|
|
|
|
|
|
|
#define ENTRY(E, M, Q, G) \
|
[1/77] Add an E_ prefix to mode names
Later patches will add wrapper types for specific classes
of mode. E.g. SImode will be a scalar_int_mode, SFmode will be a
scalar_float_mode, etc. This patch prepares for that change by adding
an E_ prefix to the mode enum values. It also adds #defines that map
the unprefixed names to the prefixed names; e.g:
#define QImode E_QImode
Later patches will change this to use things like scalar_int_mode
where appropriate.
The patch continues to use enum values to initialise static data.
This isn't necessary for correctness, but it cuts down on the amount
of load-time initialisation and shouldn't have any downsides.
The patch also changes things like:
cmp_mode == DImode ? DFmode : DImode
to:
cmp_mode == DImode ? E_DFmode : E_DImode
This is because DImode and DFmode will eventually be different
classes, so the original ?: wouldn't be well-formed.
2017-08-30 Richard Sandiford <richard.sandiford@linaro.org>
Alan Hayward <alan.hayward@arm.com>
David Sherwood <david.sherwood@arm.com>
gcc/
* genmodes.c (mode_size_inline): Add an E_ prefix to mode names.
(mode_nunits_inline): Likewise.
(mode_inner_inline): Likewise.
(mode_unit_size_inline): Likewise.
(mode_unit_precision_inline): Likewise.
(emit_insn_modes_h): Likewise. Also emit a #define of the
unprefixed name.
(emit_mode_wider): Add an E_ prefix to mode names.
(emit_mode_complex): Likewise.
(emit_mode_inner): Likewise.
(emit_mode_adjustments): Likewise.
(emit_mode_int_n): Likewise.
* config/aarch64/aarch64-builtins.c (v8qi_UP, v4hi_UP, v4hf_UP)
(v2si_UP, v2sf_UP, v1df_UP, di_UP, df_UP, v16qi_UP, v8hi_UP, v8hf_UP)
(v4si_UP, v4sf_UP, v2di_UP, v2df_UP, ti_UP, oi_UP, ci_UP, xi_UP)
(si_UP, sf_UP, hi_UP, hf_UP, qi_UP): Likewise.
(CRC32_BUILTIN, ENTRY): Likewise.
* config/aarch64/aarch64.c (aarch64_push_regs): Likewise.
(aarch64_pop_regs): Likewise.
(aarch64_process_components): Likewise.
* config/alpha/alpha.c (alpha_emit_conditional_move): Likewise.
* config/arm/arm-builtins.c (v8qi_UP, v4hi_UP, v4hf_UP, v2si_UP)
(v2sf_UP, di_UP, v16qi_UP, v8hi_UP, v8hf_UP, v4si_UP, v4sf_UP)
(v2di_UP, ti_UP, ei_UP, oi_UP, hf_UP, si_UP, void_UP): Likewise.
* config/arm/arm.c (arm_init_libfuncs): Likewise.
* config/i386/i386-builtin-types.awk (ix86_builtin_type_vect_mode):
Likewise.
* config/i386/i386-builtin.def (pcmpestr): Likewise.
(pcmpistr): Likewise.
* config/microblaze/microblaze.c (double_memory_operand): Likewise.
* config/mmix/mmix.c (mmix_output_condition): Likewise.
* config/powerpcspe/powerpcspe.c (rs6000_init_hard_regno_mode_ok):
Likewise.
* config/rl78/rl78.c (mduc_regs): Likewise.
* config/rs6000/rs6000.c (rs6000_init_hard_regno_mode_ok): Likewise.
(htm_expand_builtin): Likewise.
* config/sh/sh.h (REGISTER_NATURAL_MODE): Likewise.
* config/sparc/sparc.c (emit_save_or_restore_regs): Likewise.
* config/xtensa/xtensa.c (print_operand): Likewise.
* expmed.h (NUM_MODE_PARTIAL_INT): Likewise.
(NUM_MODE_VECTOR_INT): Likewise.
* genoutput.c (null_operand): Likewise.
(output_operand_data): Likewise.
* genrecog.c (print_parameter_value): Likewise.
* lra.c (debug_operand_data): Likewise.
Co-Authored-By: Alan Hayward <alan.hayward@arm.com>
Co-Authored-By: David Sherwood <david.sherwood@arm.com>
From-SVN: r251452
2017-08-30 13:08:14 +02:00
|
|
|
{E, "__" #E, #G "__" #E, NULL_TREE, NULL_TREE, E_##M##mode, qualifier_##Q},
|
2021-09-03 04:12:29 +02:00
|
|
|
static GTY(()) struct aarch64_simd_type_info aarch64_simd_types [] = {
|
[AArch64] Restructure arm_neon.h vector types.
2014-11-05 Tejas Belagod <tejas.belagod@arm.com>
* config/aarch64/aarch64-builtins.c
(aarch64_build_scalar_type): Remove.
(aarch64_scalar_builtin_types, aarch64_simd_type,
aarch64_simd_type, aarch64_mangle_builtin_scalar_type,
aarch64_mangle_builtin_vector_type,
aarch64_mangle_builtin_type, aarch64_simd_builtin_std_type,
aarch64_lookup_simd_builtin_type, aarch64_simd_builtin_type,
aarch64_init_simd_builtin_types,
aarch64_init_simd_builtin_scalar_types): New.
(aarch64_init_simd_builtins): Refactor.
(aarch64_init_crc32_builtins): Fixup with qualifier.
* config/aarch64/aarch64-protos.h
(aarch64_mangle_builtin_type): Export.
* config/aarch64/aarch64-simd-builtin-types.def: New.
* config/aarch64/aarch64.c (aarch64_simd_mangle_map): Remove.
(aarch64_mangle_type): Refactor.
* config/aarch64/arm_neon.h: Declare vector types based on
internal types.
* config/aarch64/t-aarch64: Update dependency.
From-SVN: r217114
2014-11-05 09:26:54 +01:00
|
|
|
#include "aarch64-simd-builtin-types.def"
|
|
|
|
};
|
|
|
|
#undef ENTRY
|
|
|
|
|
2022-04-05 18:31:35 +02:00
|
|
|
static machine_mode aarch64_simd_tuple_modes[ARM_NEON_H_TYPES_LAST][3];
|
2021-08-09 16:26:48 +02:00
|
|
|
static GTY(()) tree aarch64_simd_tuple_types[ARM_NEON_H_TYPES_LAST][3];
|
|
|
|
|
2021-09-03 04:12:29 +02:00
|
|
|
static GTY(()) tree aarch64_simd_intOI_type_node = NULL_TREE;
|
|
|
|
static GTY(()) tree aarch64_simd_intCI_type_node = NULL_TREE;
|
|
|
|
static GTY(()) tree aarch64_simd_intXI_type_node = NULL_TREE;
|
[AArch64] Restructure arm_neon.h vector types.
2014-11-05 Tejas Belagod <tejas.belagod@arm.com>
* config/aarch64/aarch64-builtins.c
(aarch64_build_scalar_type): Remove.
(aarch64_scalar_builtin_types, aarch64_simd_type,
aarch64_simd_type, aarch64_mangle_builtin_scalar_type,
aarch64_mangle_builtin_vector_type,
aarch64_mangle_builtin_type, aarch64_simd_builtin_std_type,
aarch64_lookup_simd_builtin_type, aarch64_simd_builtin_type,
aarch64_init_simd_builtin_types,
aarch64_init_simd_builtin_scalar_types): New.
(aarch64_init_simd_builtins): Refactor.
(aarch64_init_crc32_builtins): Fixup with qualifier.
* config/aarch64/aarch64-protos.h
(aarch64_mangle_builtin_type): Export.
* config/aarch64/aarch64-simd-builtin-types.def: New.
* config/aarch64/aarch64.c (aarch64_simd_mangle_map): Remove.
(aarch64_mangle_type): Refactor.
* config/aarch64/arm_neon.h: Declare vector types based on
internal types.
* config/aarch64/t-aarch64: Update dependency.
From-SVN: r217114
2014-11-05 09:26:54 +01:00
|
|
|
|
2016-08-05 18:08:24 +02:00
|
|
|
/* The user-visible __fp16 type, and a pointer to that type. Used
|
|
|
|
across the back-end. */
|
|
|
|
tree aarch64_fp16_type_node = NULL_TREE;
|
|
|
|
tree aarch64_fp16_ptr_type_node = NULL_TREE;
|
|
|
|
|
2020-01-10 20:23:41 +01:00
|
|
|
/* Back-end node type for brain float (bfloat) types. */
|
|
|
|
tree aarch64_bf16_type_node = NULL_TREE;
|
|
|
|
tree aarch64_bf16_ptr_type_node = NULL_TREE;
|
|
|
|
|
[AArch64] Split built-in function codes into major and minor codes
It was easier to add the SVE ACLE support without enumerating every
function at build time. This in turn meant that it was easier if the
SVE builtins occupied a distinct numberspace from the existing AArch64
ones, which *are* enumerated at build time. This patch therefore
divides the built-in functions codes into "major" and "minor" codes.
At present the major code is just "general", but the SVE patch will add
"SVE" as well.
Also, it was convenient to put the SVE ACLE support in its own file,
so the patch makes aarch64.c provide the frontline target hooks directly,
forwarding to the other files for the real work.
The reason for organising the files this way is that aarch64.c needs
to define the target hook macros whatever happens, and having aarch64.c
macros forward to aarch64-builtins.c functions and aarch64-bulitins.c
functions forward to the SVE file seemed a bit indirect. Doing things
the way the patch does them puts aarch64-builtins.c and the SVE code on
more of an equal footing.
The aarch64_(general_)gimple_fold_builtin change is mostly just
reindentation.
2019-09-27 Richard Sandiford <richard.sandiford@arm.com>
gcc/
* config/aarch64/aarch64-protos.h (aarch64_builtin_class): New enum.
(AARCH64_BUILTIN_SHIFT, AARCH64_BUILTIN_CLASS): New constants.
(aarch64_gimple_fold_builtin, aarch64_mangle_builtin_type)
(aarch64_fold_builtin, aarch64_init_builtins, aarch64_expand_builtin):
(aarch64_builtin_decl, aarch64_builtin_rsqrt): Delete.
(aarch64_general_mangle_builtin_type, aarch64_general_init_builtins):
(aarch64_general_fold_builtin, aarch64_general_gimple_fold_builtin):
(aarch64_general_expand_builtin, aarch64_general_builtin_decl):
(aarch64_general_builtin_rsqrt): Declare.
* config/aarch64/aarch64-builtins.c (aarch64_general_add_builtin):
New function.
(aarch64_mangle_builtin_type): Rename to...
(aarch64_general_mangle_builtin_type): ...this.
(aarch64_init_fcmla_laneq_builtins, aarch64_init_simd_builtins)
(aarch64_init_crc32_builtins, aarch64_init_builtin_rsqrt)
(aarch64_init_pauth_hint_builtins, aarch64_init_tme_builtins): Use
aarch64_general_add_builtin instead of add_builtin_function.
(aarch64_init_builtins): Rename to...
(aarch64_general_init_builtins): ...this. Use
aarch64_general_add_builtin instead of add_builtin_function.
(aarch64_builtin_decl): Rename to...
(aarch64_general_builtin_decl): ...this and remove the unused
arguments.
(aarch64_expand_builtin): Rename to...
(aarch64_general_expand_builtin): ...this and remove the unused
arguments.
(aarch64_builtin_rsqrt): Rename to...
(aarch64_general_builtin_rsqrt): ...this.
(aarch64_fold_builtin): Rename to...
(aarch64_general_fold_builtin): ...this. Take the function subcode
and return type as arguments. Remove the "ignored" argument.
(aarch64_gimple_fold_builtin): Rename to...
(aarch64_general_gimple_fold_builtin): ...this. Take the function
subcode and gcall as arguments, and return the new function call.
* config/aarch64/aarch64.c (aarch64_init_builtins)
(aarch64_fold_builtin, aarch64_gimple_fold_builtin)
(aarch64_expand_builtin, aarch64_builtin_decl): New functions.
(aarch64_builtin_reciprocal): Call aarch64_general_builtin_rsqrt
instead of aarch64_builtin_rsqrt.
(aarch64_mangle_type): Call aarch64_general_mangle_builtin_type
instead of aarch64_mangle_builtin_type.
From-SVN: r276177
2019-09-27 10:47:21 +02:00
|
|
|
/* Wrapper around add_builtin_function. NAME is the name of the built-in
|
2020-07-31 10:52:25 +02:00
|
|
|
function, TYPE is the function type, CODE is the function subcode
|
|
|
|
(relative to AARCH64_BUILTIN_GENERAL), and ATTRS is the function
|
|
|
|
attributes. */
|
[AArch64] Split built-in function codes into major and minor codes
It was easier to add the SVE ACLE support without enumerating every
function at build time. This in turn meant that it was easier if the
SVE builtins occupied a distinct numberspace from the existing AArch64
ones, which *are* enumerated at build time. This patch therefore
divides the built-in functions codes into "major" and "minor" codes.
At present the major code is just "general", but the SVE patch will add
"SVE" as well.
Also, it was convenient to put the SVE ACLE support in its own file,
so the patch makes aarch64.c provide the frontline target hooks directly,
forwarding to the other files for the real work.
The reason for organising the files this way is that aarch64.c needs
to define the target hook macros whatever happens, and having aarch64.c
macros forward to aarch64-builtins.c functions and aarch64-bulitins.c
functions forward to the SVE file seemed a bit indirect. Doing things
the way the patch does them puts aarch64-builtins.c and the SVE code on
more of an equal footing.
The aarch64_(general_)gimple_fold_builtin change is mostly just
reindentation.
2019-09-27 Richard Sandiford <richard.sandiford@arm.com>
gcc/
* config/aarch64/aarch64-protos.h (aarch64_builtin_class): New enum.
(AARCH64_BUILTIN_SHIFT, AARCH64_BUILTIN_CLASS): New constants.
(aarch64_gimple_fold_builtin, aarch64_mangle_builtin_type)
(aarch64_fold_builtin, aarch64_init_builtins, aarch64_expand_builtin):
(aarch64_builtin_decl, aarch64_builtin_rsqrt): Delete.
(aarch64_general_mangle_builtin_type, aarch64_general_init_builtins):
(aarch64_general_fold_builtin, aarch64_general_gimple_fold_builtin):
(aarch64_general_expand_builtin, aarch64_general_builtin_decl):
(aarch64_general_builtin_rsqrt): Declare.
* config/aarch64/aarch64-builtins.c (aarch64_general_add_builtin):
New function.
(aarch64_mangle_builtin_type): Rename to...
(aarch64_general_mangle_builtin_type): ...this.
(aarch64_init_fcmla_laneq_builtins, aarch64_init_simd_builtins)
(aarch64_init_crc32_builtins, aarch64_init_builtin_rsqrt)
(aarch64_init_pauth_hint_builtins, aarch64_init_tme_builtins): Use
aarch64_general_add_builtin instead of add_builtin_function.
(aarch64_init_builtins): Rename to...
(aarch64_general_init_builtins): ...this. Use
aarch64_general_add_builtin instead of add_builtin_function.
(aarch64_builtin_decl): Rename to...
(aarch64_general_builtin_decl): ...this and remove the unused
arguments.
(aarch64_expand_builtin): Rename to...
(aarch64_general_expand_builtin): ...this and remove the unused
arguments.
(aarch64_builtin_rsqrt): Rename to...
(aarch64_general_builtin_rsqrt): ...this.
(aarch64_fold_builtin): Rename to...
(aarch64_general_fold_builtin): ...this. Take the function subcode
and return type as arguments. Remove the "ignored" argument.
(aarch64_gimple_fold_builtin): Rename to...
(aarch64_general_gimple_fold_builtin): ...this. Take the function
subcode and gcall as arguments, and return the new function call.
* config/aarch64/aarch64.c (aarch64_init_builtins)
(aarch64_fold_builtin, aarch64_gimple_fold_builtin)
(aarch64_expand_builtin, aarch64_builtin_decl): New functions.
(aarch64_builtin_reciprocal): Call aarch64_general_builtin_rsqrt
instead of aarch64_builtin_rsqrt.
(aarch64_mangle_type): Call aarch64_general_mangle_builtin_type
instead of aarch64_mangle_builtin_type.
From-SVN: r276177
2019-09-27 10:47:21 +02:00
|
|
|
static tree
|
2020-07-31 10:52:25 +02:00
|
|
|
aarch64_general_add_builtin (const char *name, tree type, unsigned int code,
|
|
|
|
tree attrs = NULL_TREE)
|
[AArch64] Split built-in function codes into major and minor codes
It was easier to add the SVE ACLE support without enumerating every
function at build time. This in turn meant that it was easier if the
SVE builtins occupied a distinct numberspace from the existing AArch64
ones, which *are* enumerated at build time. This patch therefore
divides the built-in functions codes into "major" and "minor" codes.
At present the major code is just "general", but the SVE patch will add
"SVE" as well.
Also, it was convenient to put the SVE ACLE support in its own file,
so the patch makes aarch64.c provide the frontline target hooks directly,
forwarding to the other files for the real work.
The reason for organising the files this way is that aarch64.c needs
to define the target hook macros whatever happens, and having aarch64.c
macros forward to aarch64-builtins.c functions and aarch64-bulitins.c
functions forward to the SVE file seemed a bit indirect. Doing things
the way the patch does them puts aarch64-builtins.c and the SVE code on
more of an equal footing.
The aarch64_(general_)gimple_fold_builtin change is mostly just
reindentation.
2019-09-27 Richard Sandiford <richard.sandiford@arm.com>
gcc/
* config/aarch64/aarch64-protos.h (aarch64_builtin_class): New enum.
(AARCH64_BUILTIN_SHIFT, AARCH64_BUILTIN_CLASS): New constants.
(aarch64_gimple_fold_builtin, aarch64_mangle_builtin_type)
(aarch64_fold_builtin, aarch64_init_builtins, aarch64_expand_builtin):
(aarch64_builtin_decl, aarch64_builtin_rsqrt): Delete.
(aarch64_general_mangle_builtin_type, aarch64_general_init_builtins):
(aarch64_general_fold_builtin, aarch64_general_gimple_fold_builtin):
(aarch64_general_expand_builtin, aarch64_general_builtin_decl):
(aarch64_general_builtin_rsqrt): Declare.
* config/aarch64/aarch64-builtins.c (aarch64_general_add_builtin):
New function.
(aarch64_mangle_builtin_type): Rename to...
(aarch64_general_mangle_builtin_type): ...this.
(aarch64_init_fcmla_laneq_builtins, aarch64_init_simd_builtins)
(aarch64_init_crc32_builtins, aarch64_init_builtin_rsqrt)
(aarch64_init_pauth_hint_builtins, aarch64_init_tme_builtins): Use
aarch64_general_add_builtin instead of add_builtin_function.
(aarch64_init_builtins): Rename to...
(aarch64_general_init_builtins): ...this. Use
aarch64_general_add_builtin instead of add_builtin_function.
(aarch64_builtin_decl): Rename to...
(aarch64_general_builtin_decl): ...this and remove the unused
arguments.
(aarch64_expand_builtin): Rename to...
(aarch64_general_expand_builtin): ...this and remove the unused
arguments.
(aarch64_builtin_rsqrt): Rename to...
(aarch64_general_builtin_rsqrt): ...this.
(aarch64_fold_builtin): Rename to...
(aarch64_general_fold_builtin): ...this. Take the function subcode
and return type as arguments. Remove the "ignored" argument.
(aarch64_gimple_fold_builtin): Rename to...
(aarch64_general_gimple_fold_builtin): ...this. Take the function
subcode and gcall as arguments, and return the new function call.
* config/aarch64/aarch64.c (aarch64_init_builtins)
(aarch64_fold_builtin, aarch64_gimple_fold_builtin)
(aarch64_expand_builtin, aarch64_builtin_decl): New functions.
(aarch64_builtin_reciprocal): Call aarch64_general_builtin_rsqrt
instead of aarch64_builtin_rsqrt.
(aarch64_mangle_type): Call aarch64_general_mangle_builtin_type
instead of aarch64_mangle_builtin_type.
From-SVN: r276177
2019-09-27 10:47:21 +02:00
|
|
|
{
|
|
|
|
code = (code << AARCH64_BUILTIN_SHIFT) | AARCH64_BUILTIN_GENERAL;
|
|
|
|
return add_builtin_function (name, type, code, BUILT_IN_MD,
|
2020-07-31 10:52:25 +02:00
|
|
|
NULL, attrs);
|
[AArch64] Split built-in function codes into major and minor codes
It was easier to add the SVE ACLE support without enumerating every
function at build time. This in turn meant that it was easier if the
SVE builtins occupied a distinct numberspace from the existing AArch64
ones, which *are* enumerated at build time. This patch therefore
divides the built-in functions codes into "major" and "minor" codes.
At present the major code is just "general", but the SVE patch will add
"SVE" as well.
Also, it was convenient to put the SVE ACLE support in its own file,
so the patch makes aarch64.c provide the frontline target hooks directly,
forwarding to the other files for the real work.
The reason for organising the files this way is that aarch64.c needs
to define the target hook macros whatever happens, and having aarch64.c
macros forward to aarch64-builtins.c functions and aarch64-bulitins.c
functions forward to the SVE file seemed a bit indirect. Doing things
the way the patch does them puts aarch64-builtins.c and the SVE code on
more of an equal footing.
The aarch64_(general_)gimple_fold_builtin change is mostly just
reindentation.
2019-09-27 Richard Sandiford <richard.sandiford@arm.com>
gcc/
* config/aarch64/aarch64-protos.h (aarch64_builtin_class): New enum.
(AARCH64_BUILTIN_SHIFT, AARCH64_BUILTIN_CLASS): New constants.
(aarch64_gimple_fold_builtin, aarch64_mangle_builtin_type)
(aarch64_fold_builtin, aarch64_init_builtins, aarch64_expand_builtin):
(aarch64_builtin_decl, aarch64_builtin_rsqrt): Delete.
(aarch64_general_mangle_builtin_type, aarch64_general_init_builtins):
(aarch64_general_fold_builtin, aarch64_general_gimple_fold_builtin):
(aarch64_general_expand_builtin, aarch64_general_builtin_decl):
(aarch64_general_builtin_rsqrt): Declare.
* config/aarch64/aarch64-builtins.c (aarch64_general_add_builtin):
New function.
(aarch64_mangle_builtin_type): Rename to...
(aarch64_general_mangle_builtin_type): ...this.
(aarch64_init_fcmla_laneq_builtins, aarch64_init_simd_builtins)
(aarch64_init_crc32_builtins, aarch64_init_builtin_rsqrt)
(aarch64_init_pauth_hint_builtins, aarch64_init_tme_builtins): Use
aarch64_general_add_builtin instead of add_builtin_function.
(aarch64_init_builtins): Rename to...
(aarch64_general_init_builtins): ...this. Use
aarch64_general_add_builtin instead of add_builtin_function.
(aarch64_builtin_decl): Rename to...
(aarch64_general_builtin_decl): ...this and remove the unused
arguments.
(aarch64_expand_builtin): Rename to...
(aarch64_general_expand_builtin): ...this and remove the unused
arguments.
(aarch64_builtin_rsqrt): Rename to...
(aarch64_general_builtin_rsqrt): ...this.
(aarch64_fold_builtin): Rename to...
(aarch64_general_fold_builtin): ...this. Take the function subcode
and return type as arguments. Remove the "ignored" argument.
(aarch64_gimple_fold_builtin): Rename to...
(aarch64_general_gimple_fold_builtin): ...this. Take the function
subcode and gcall as arguments, and return the new function call.
* config/aarch64/aarch64.c (aarch64_init_builtins)
(aarch64_fold_builtin, aarch64_gimple_fold_builtin)
(aarch64_expand_builtin, aarch64_builtin_decl): New functions.
(aarch64_builtin_reciprocal): Call aarch64_general_builtin_rsqrt
instead of aarch64_builtin_rsqrt.
(aarch64_mangle_type): Call aarch64_general_mangle_builtin_type
instead of aarch64_mangle_builtin_type.
From-SVN: r276177
2019-09-27 10:47:21 +02:00
|
|
|
}
|
|
|
|
|
[AArch64] Restructure arm_neon.h vector types.
2014-11-05 Tejas Belagod <tejas.belagod@arm.com>
* config/aarch64/aarch64-builtins.c
(aarch64_build_scalar_type): Remove.
(aarch64_scalar_builtin_types, aarch64_simd_type,
aarch64_simd_type, aarch64_mangle_builtin_scalar_type,
aarch64_mangle_builtin_vector_type,
aarch64_mangle_builtin_type, aarch64_simd_builtin_std_type,
aarch64_lookup_simd_builtin_type, aarch64_simd_builtin_type,
aarch64_init_simd_builtin_types,
aarch64_init_simd_builtin_scalar_types): New.
(aarch64_init_simd_builtins): Refactor.
(aarch64_init_crc32_builtins): Fixup with qualifier.
* config/aarch64/aarch64-protos.h
(aarch64_mangle_builtin_type): Export.
* config/aarch64/aarch64-simd-builtin-types.def: New.
* config/aarch64/aarch64.c (aarch64_simd_mangle_map): Remove.
(aarch64_mangle_type): Refactor.
* config/aarch64/arm_neon.h: Declare vector types based on
internal types.
* config/aarch64/t-aarch64: Update dependency.
From-SVN: r217114
2014-11-05 09:26:54 +01:00
|
|
|
static const char *
|
|
|
|
aarch64_mangle_builtin_scalar_type (const_tree type)
|
|
|
|
{
|
|
|
|
int i = 0;
|
|
|
|
|
|
|
|
while (aarch64_scalar_builtin_types[i] != NULL)
|
2013-11-20 10:19:25 +01:00
|
|
|
{
|
[AArch64] Restructure arm_neon.h vector types.
2014-11-05 Tejas Belagod <tejas.belagod@arm.com>
* config/aarch64/aarch64-builtins.c
(aarch64_build_scalar_type): Remove.
(aarch64_scalar_builtin_types, aarch64_simd_type,
aarch64_simd_type, aarch64_mangle_builtin_scalar_type,
aarch64_mangle_builtin_vector_type,
aarch64_mangle_builtin_type, aarch64_simd_builtin_std_type,
aarch64_lookup_simd_builtin_type, aarch64_simd_builtin_type,
aarch64_init_simd_builtin_types,
aarch64_init_simd_builtin_scalar_types): New.
(aarch64_init_simd_builtins): Refactor.
(aarch64_init_crc32_builtins): Fixup with qualifier.
* config/aarch64/aarch64-protos.h
(aarch64_mangle_builtin_type): Export.
* config/aarch64/aarch64-simd-builtin-types.def: New.
* config/aarch64/aarch64.c (aarch64_simd_mangle_map): Remove.
(aarch64_mangle_type): Refactor.
* config/aarch64/arm_neon.h: Declare vector types based on
internal types.
* config/aarch64/t-aarch64: Update dependency.
From-SVN: r217114
2014-11-05 09:26:54 +01:00
|
|
|
const char *name = aarch64_scalar_builtin_types[i];
|
|
|
|
|
|
|
|
if (TREE_CODE (TYPE_NAME (type)) == TYPE_DECL
|
|
|
|
&& DECL_NAME (TYPE_NAME (type))
|
|
|
|
&& !strcmp (IDENTIFIER_POINTER (DECL_NAME (TYPE_NAME (type))), name))
|
|
|
|
return aarch64_scalar_builtin_types[i];
|
|
|
|
i++;
|
|
|
|
}
|
|
|
|
return NULL;
|
2013-11-20 10:19:25 +01:00
|
|
|
}
|
|
|
|
|
[AArch64] Restructure arm_neon.h vector types.
2014-11-05 Tejas Belagod <tejas.belagod@arm.com>
* config/aarch64/aarch64-builtins.c
(aarch64_build_scalar_type): Remove.
(aarch64_scalar_builtin_types, aarch64_simd_type,
aarch64_simd_type, aarch64_mangle_builtin_scalar_type,
aarch64_mangle_builtin_vector_type,
aarch64_mangle_builtin_type, aarch64_simd_builtin_std_type,
aarch64_lookup_simd_builtin_type, aarch64_simd_builtin_type,
aarch64_init_simd_builtin_types,
aarch64_init_simd_builtin_scalar_types): New.
(aarch64_init_simd_builtins): Refactor.
(aarch64_init_crc32_builtins): Fixup with qualifier.
* config/aarch64/aarch64-protos.h
(aarch64_mangle_builtin_type): Export.
* config/aarch64/aarch64-simd-builtin-types.def: New.
* config/aarch64/aarch64.c (aarch64_simd_mangle_map): Remove.
(aarch64_mangle_type): Refactor.
* config/aarch64/arm_neon.h: Declare vector types based on
internal types.
* config/aarch64/t-aarch64: Update dependency.
From-SVN: r217114
2014-11-05 09:26:54 +01:00
|
|
|
static const char *
|
|
|
|
aarch64_mangle_builtin_vector_type (const_tree type)
|
2013-11-20 10:19:25 +01:00
|
|
|
{
|
aarch64: Treat GNU and Advanced SIMD vectors as distinct [PR92789, PR95726]
PR95726 is about template look-up for things like:
foo<float vecf __attribute__((vector_size(16)))>
foo<float32x4_t>
The immediate cause of the problem is that the hash function usually
returns different hashes for these types, yet the equality function
thinks they are equal. This then raises the question of how the types
are supposed to be treated.
I think the answer is that the GNU vector type should be treated as
distinct from float32x4_t, not least because the two types mangle
differently. However, each type should implicitly convert to the other.
This would mean that, as far as the PR is concerned, the hashing
function is right to (sometimes) treat the types differently and
the equality function is wrong to treat them as the same.
The most obvious way to enforce the type difference is to use a
target-specific type attribute. That on its own is enough to fix
the PR. The difficulty is deciding whether the knock-on effects
are acceptable.
One obvious effect is that GCC then rejects:
typedef float vecf __attribute__((vector_size(16)));
vecf x;
float32x4_t &z = x;
on the basis that the types are no longer reference-compatible.
I think that's again the correct behaviour, and consistent with
current Clang.
A trickier question is whether:
vecf x;
float32x4_t y;
… c ? x : y …
should be valid, and if so, what its type should be [PR92789].
As explained in the comment in the testcase, GCC and Clang both
accepted this, but GCC chose the “then” type while Clang chose
the “else” type. This can lead to different mangling for (probably
artificial) corner cases, as seen for “sel1” and “sel2” in the
testcase.
Adding the attribute makes GCC reject the conditional expression
as ambiguous. I think that too is the correct behaviour, for the
reasons described in the testcase. However, it does seem to have
the potential to break existing code.
It looks like aarch64_comp_type_attributes is missing cases for
the SVE attributes, but I'll handle that in a separate patch.
2020-06-30 Richard Sandiford <richard.sandiford@arm.com>
gcc/
PR target/92789
PR target/95726
* config/aarch64/aarch64.c (aarch64_attribute_table): Add
"Advanced SIMD type".
(aarch64_comp_type_attributes): Check that the "Advanced SIMD type"
attributes are equal.
* config/aarch64/aarch64-builtins.c: Include stringpool.h and
attribs.h.
(aarch64_mangle_builtin_vector_type): Use the mangling recorded
in the "Advanced SIMD type" attribute.
(aarch64_init_simd_builtin_types): Add an "Advanced SIMD type"
attribute to each Advanced SIMD type, using the mangled type
as the attribute's single argument.
gcc/testsuite/
PR target/92789
PR target/95726
* g++.target/aarch64/pr95726.C: New test.
2020-06-30 22:40:30 +02:00
|
|
|
tree attrs = TYPE_ATTRIBUTES (type);
|
|
|
|
if (tree attr = lookup_attribute ("Advanced SIMD type", attrs))
|
|
|
|
{
|
|
|
|
tree mangled_name = TREE_VALUE (TREE_VALUE (attr));
|
|
|
|
return IDENTIFIER_POINTER (mangled_name);
|
|
|
|
}
|
[AArch64] Restructure arm_neon.h vector types.
2014-11-05 Tejas Belagod <tejas.belagod@arm.com>
* config/aarch64/aarch64-builtins.c
(aarch64_build_scalar_type): Remove.
(aarch64_scalar_builtin_types, aarch64_simd_type,
aarch64_simd_type, aarch64_mangle_builtin_scalar_type,
aarch64_mangle_builtin_vector_type,
aarch64_mangle_builtin_type, aarch64_simd_builtin_std_type,
aarch64_lookup_simd_builtin_type, aarch64_simd_builtin_type,
aarch64_init_simd_builtin_types,
aarch64_init_simd_builtin_scalar_types): New.
(aarch64_init_simd_builtins): Refactor.
(aarch64_init_crc32_builtins): Fixup with qualifier.
* config/aarch64/aarch64-protos.h
(aarch64_mangle_builtin_type): Export.
* config/aarch64/aarch64-simd-builtin-types.def: New.
* config/aarch64/aarch64.c (aarch64_simd_mangle_map): Remove.
(aarch64_mangle_type): Refactor.
* config/aarch64/arm_neon.h: Declare vector types based on
internal types.
* config/aarch64/t-aarch64: Update dependency.
From-SVN: r217114
2014-11-05 09:26:54 +01:00
|
|
|
|
|
|
|
return NULL;
|
2013-11-26 11:00:49 +01:00
|
|
|
}
|
|
|
|
|
[AArch64] Restructure arm_neon.h vector types.
2014-11-05 Tejas Belagod <tejas.belagod@arm.com>
* config/aarch64/aarch64-builtins.c
(aarch64_build_scalar_type): Remove.
(aarch64_scalar_builtin_types, aarch64_simd_type,
aarch64_simd_type, aarch64_mangle_builtin_scalar_type,
aarch64_mangle_builtin_vector_type,
aarch64_mangle_builtin_type, aarch64_simd_builtin_std_type,
aarch64_lookup_simd_builtin_type, aarch64_simd_builtin_type,
aarch64_init_simd_builtin_types,
aarch64_init_simd_builtin_scalar_types): New.
(aarch64_init_simd_builtins): Refactor.
(aarch64_init_crc32_builtins): Fixup with qualifier.
* config/aarch64/aarch64-protos.h
(aarch64_mangle_builtin_type): Export.
* config/aarch64/aarch64-simd-builtin-types.def: New.
* config/aarch64/aarch64.c (aarch64_simd_mangle_map): Remove.
(aarch64_mangle_type): Refactor.
* config/aarch64/arm_neon.h: Declare vector types based on
internal types.
* config/aarch64/t-aarch64: Update dependency.
From-SVN: r217114
2014-11-05 09:26:54 +01:00
|
|
|
const char *
|
[AArch64] Split built-in function codes into major and minor codes
It was easier to add the SVE ACLE support without enumerating every
function at build time. This in turn meant that it was easier if the
SVE builtins occupied a distinct numberspace from the existing AArch64
ones, which *are* enumerated at build time. This patch therefore
divides the built-in functions codes into "major" and "minor" codes.
At present the major code is just "general", but the SVE patch will add
"SVE" as well.
Also, it was convenient to put the SVE ACLE support in its own file,
so the patch makes aarch64.c provide the frontline target hooks directly,
forwarding to the other files for the real work.
The reason for organising the files this way is that aarch64.c needs
to define the target hook macros whatever happens, and having aarch64.c
macros forward to aarch64-builtins.c functions and aarch64-bulitins.c
functions forward to the SVE file seemed a bit indirect. Doing things
the way the patch does them puts aarch64-builtins.c and the SVE code on
more of an equal footing.
The aarch64_(general_)gimple_fold_builtin change is mostly just
reindentation.
2019-09-27 Richard Sandiford <richard.sandiford@arm.com>
gcc/
* config/aarch64/aarch64-protos.h (aarch64_builtin_class): New enum.
(AARCH64_BUILTIN_SHIFT, AARCH64_BUILTIN_CLASS): New constants.
(aarch64_gimple_fold_builtin, aarch64_mangle_builtin_type)
(aarch64_fold_builtin, aarch64_init_builtins, aarch64_expand_builtin):
(aarch64_builtin_decl, aarch64_builtin_rsqrt): Delete.
(aarch64_general_mangle_builtin_type, aarch64_general_init_builtins):
(aarch64_general_fold_builtin, aarch64_general_gimple_fold_builtin):
(aarch64_general_expand_builtin, aarch64_general_builtin_decl):
(aarch64_general_builtin_rsqrt): Declare.
* config/aarch64/aarch64-builtins.c (aarch64_general_add_builtin):
New function.
(aarch64_mangle_builtin_type): Rename to...
(aarch64_general_mangle_builtin_type): ...this.
(aarch64_init_fcmla_laneq_builtins, aarch64_init_simd_builtins)
(aarch64_init_crc32_builtins, aarch64_init_builtin_rsqrt)
(aarch64_init_pauth_hint_builtins, aarch64_init_tme_builtins): Use
aarch64_general_add_builtin instead of add_builtin_function.
(aarch64_init_builtins): Rename to...
(aarch64_general_init_builtins): ...this. Use
aarch64_general_add_builtin instead of add_builtin_function.
(aarch64_builtin_decl): Rename to...
(aarch64_general_builtin_decl): ...this and remove the unused
arguments.
(aarch64_expand_builtin): Rename to...
(aarch64_general_expand_builtin): ...this and remove the unused
arguments.
(aarch64_builtin_rsqrt): Rename to...
(aarch64_general_builtin_rsqrt): ...this.
(aarch64_fold_builtin): Rename to...
(aarch64_general_fold_builtin): ...this. Take the function subcode
and return type as arguments. Remove the "ignored" argument.
(aarch64_gimple_fold_builtin): Rename to...
(aarch64_general_gimple_fold_builtin): ...this. Take the function
subcode and gcall as arguments, and return the new function call.
* config/aarch64/aarch64.c (aarch64_init_builtins)
(aarch64_fold_builtin, aarch64_gimple_fold_builtin)
(aarch64_expand_builtin, aarch64_builtin_decl): New functions.
(aarch64_builtin_reciprocal): Call aarch64_general_builtin_rsqrt
instead of aarch64_builtin_rsqrt.
(aarch64_mangle_type): Call aarch64_general_mangle_builtin_type
instead of aarch64_mangle_builtin_type.
From-SVN: r276177
2019-09-27 10:47:21 +02:00
|
|
|
aarch64_general_mangle_builtin_type (const_tree type)
|
2013-11-26 11:00:49 +01:00
|
|
|
{
|
[AArch64] Restructure arm_neon.h vector types.
2014-11-05 Tejas Belagod <tejas.belagod@arm.com>
* config/aarch64/aarch64-builtins.c
(aarch64_build_scalar_type): Remove.
(aarch64_scalar_builtin_types, aarch64_simd_type,
aarch64_simd_type, aarch64_mangle_builtin_scalar_type,
aarch64_mangle_builtin_vector_type,
aarch64_mangle_builtin_type, aarch64_simd_builtin_std_type,
aarch64_lookup_simd_builtin_type, aarch64_simd_builtin_type,
aarch64_init_simd_builtin_types,
aarch64_init_simd_builtin_scalar_types): New.
(aarch64_init_simd_builtins): Refactor.
(aarch64_init_crc32_builtins): Fixup with qualifier.
* config/aarch64/aarch64-protos.h
(aarch64_mangle_builtin_type): Export.
* config/aarch64/aarch64-simd-builtin-types.def: New.
* config/aarch64/aarch64.c (aarch64_simd_mangle_map): Remove.
(aarch64_mangle_type): Refactor.
* config/aarch64/arm_neon.h: Declare vector types based on
internal types.
* config/aarch64/t-aarch64: Update dependency.
From-SVN: r217114
2014-11-05 09:26:54 +01:00
|
|
|
const char *mangle;
|
|
|
|
/* Walk through all the AArch64 builtins types tables to filter out the
|
|
|
|
incoming type. */
|
|
|
|
if ((mangle = aarch64_mangle_builtin_vector_type (type))
|
|
|
|
|| (mangle = aarch64_mangle_builtin_scalar_type (type)))
|
|
|
|
return mangle;
|
|
|
|
|
|
|
|
return NULL;
|
2013-11-26 11:00:49 +01:00
|
|
|
}
|
|
|
|
|
[AArch64] Restructure arm_neon.h vector types.
2014-11-05 Tejas Belagod <tejas.belagod@arm.com>
* config/aarch64/aarch64-builtins.c
(aarch64_build_scalar_type): Remove.
(aarch64_scalar_builtin_types, aarch64_simd_type,
aarch64_simd_type, aarch64_mangle_builtin_scalar_type,
aarch64_mangle_builtin_vector_type,
aarch64_mangle_builtin_type, aarch64_simd_builtin_std_type,
aarch64_lookup_simd_builtin_type, aarch64_simd_builtin_type,
aarch64_init_simd_builtin_types,
aarch64_init_simd_builtin_scalar_types): New.
(aarch64_init_simd_builtins): Refactor.
(aarch64_init_crc32_builtins): Fixup with qualifier.
* config/aarch64/aarch64-protos.h
(aarch64_mangle_builtin_type): Export.
* config/aarch64/aarch64-simd-builtin-types.def: New.
* config/aarch64/aarch64.c (aarch64_simd_mangle_map): Remove.
(aarch64_mangle_type): Refactor.
* config/aarch64/arm_neon.h: Declare vector types based on
internal types.
* config/aarch64/t-aarch64: Update dependency.
From-SVN: r217114
2014-11-05 09:26:54 +01:00
|
|
|
static tree
|
2017-07-05 17:29:27 +02:00
|
|
|
aarch64_simd_builtin_std_type (machine_mode mode,
|
[AArch64] Restructure arm_neon.h vector types.
2014-11-05 Tejas Belagod <tejas.belagod@arm.com>
* config/aarch64/aarch64-builtins.c
(aarch64_build_scalar_type): Remove.
(aarch64_scalar_builtin_types, aarch64_simd_type,
aarch64_simd_type, aarch64_mangle_builtin_scalar_type,
aarch64_mangle_builtin_vector_type,
aarch64_mangle_builtin_type, aarch64_simd_builtin_std_type,
aarch64_lookup_simd_builtin_type, aarch64_simd_builtin_type,
aarch64_init_simd_builtin_types,
aarch64_init_simd_builtin_scalar_types): New.
(aarch64_init_simd_builtins): Refactor.
(aarch64_init_crc32_builtins): Fixup with qualifier.
* config/aarch64/aarch64-protos.h
(aarch64_mangle_builtin_type): Export.
* config/aarch64/aarch64-simd-builtin-types.def: New.
* config/aarch64/aarch64.c (aarch64_simd_mangle_map): Remove.
(aarch64_mangle_type): Refactor.
* config/aarch64/arm_neon.h: Declare vector types based on
internal types.
* config/aarch64/t-aarch64: Update dependency.
From-SVN: r217114
2014-11-05 09:26:54 +01:00
|
|
|
enum aarch64_type_qualifiers q)
|
2013-11-26 11:00:49 +01:00
|
|
|
{
|
[AArch64] Restructure arm_neon.h vector types.
2014-11-05 Tejas Belagod <tejas.belagod@arm.com>
* config/aarch64/aarch64-builtins.c
(aarch64_build_scalar_type): Remove.
(aarch64_scalar_builtin_types, aarch64_simd_type,
aarch64_simd_type, aarch64_mangle_builtin_scalar_type,
aarch64_mangle_builtin_vector_type,
aarch64_mangle_builtin_type, aarch64_simd_builtin_std_type,
aarch64_lookup_simd_builtin_type, aarch64_simd_builtin_type,
aarch64_init_simd_builtin_types,
aarch64_init_simd_builtin_scalar_types): New.
(aarch64_init_simd_builtins): Refactor.
(aarch64_init_crc32_builtins): Fixup with qualifier.
* config/aarch64/aarch64-protos.h
(aarch64_mangle_builtin_type): Export.
* config/aarch64/aarch64-simd-builtin-types.def: New.
* config/aarch64/aarch64.c (aarch64_simd_mangle_map): Remove.
(aarch64_mangle_type): Refactor.
* config/aarch64/arm_neon.h: Declare vector types based on
internal types.
* config/aarch64/t-aarch64: Update dependency.
From-SVN: r217114
2014-11-05 09:26:54 +01:00
|
|
|
#define QUAL_TYPE(M) \
|
|
|
|
((q == qualifier_none) ? int##M##_type_node : unsigned_int##M##_type_node);
|
|
|
|
switch (mode)
|
|
|
|
{
|
2017-08-30 13:08:28 +02:00
|
|
|
case E_QImode:
|
[AArch64] Restructure arm_neon.h vector types.
2014-11-05 Tejas Belagod <tejas.belagod@arm.com>
* config/aarch64/aarch64-builtins.c
(aarch64_build_scalar_type): Remove.
(aarch64_scalar_builtin_types, aarch64_simd_type,
aarch64_simd_type, aarch64_mangle_builtin_scalar_type,
aarch64_mangle_builtin_vector_type,
aarch64_mangle_builtin_type, aarch64_simd_builtin_std_type,
aarch64_lookup_simd_builtin_type, aarch64_simd_builtin_type,
aarch64_init_simd_builtin_types,
aarch64_init_simd_builtin_scalar_types): New.
(aarch64_init_simd_builtins): Refactor.
(aarch64_init_crc32_builtins): Fixup with qualifier.
* config/aarch64/aarch64-protos.h
(aarch64_mangle_builtin_type): Export.
* config/aarch64/aarch64-simd-builtin-types.def: New.
* config/aarch64/aarch64.c (aarch64_simd_mangle_map): Remove.
(aarch64_mangle_type): Refactor.
* config/aarch64/arm_neon.h: Declare vector types based on
internal types.
* config/aarch64/t-aarch64: Update dependency.
From-SVN: r217114
2014-11-05 09:26:54 +01:00
|
|
|
return QUAL_TYPE (QI);
|
2017-08-30 13:08:28 +02:00
|
|
|
case E_HImode:
|
[AArch64] Restructure arm_neon.h vector types.
2014-11-05 Tejas Belagod <tejas.belagod@arm.com>
* config/aarch64/aarch64-builtins.c
(aarch64_build_scalar_type): Remove.
(aarch64_scalar_builtin_types, aarch64_simd_type,
aarch64_simd_type, aarch64_mangle_builtin_scalar_type,
aarch64_mangle_builtin_vector_type,
aarch64_mangle_builtin_type, aarch64_simd_builtin_std_type,
aarch64_lookup_simd_builtin_type, aarch64_simd_builtin_type,
aarch64_init_simd_builtin_types,
aarch64_init_simd_builtin_scalar_types): New.
(aarch64_init_simd_builtins): Refactor.
(aarch64_init_crc32_builtins): Fixup with qualifier.
* config/aarch64/aarch64-protos.h
(aarch64_mangle_builtin_type): Export.
* config/aarch64/aarch64-simd-builtin-types.def: New.
* config/aarch64/aarch64.c (aarch64_simd_mangle_map): Remove.
(aarch64_mangle_type): Refactor.
* config/aarch64/arm_neon.h: Declare vector types based on
internal types.
* config/aarch64/t-aarch64: Update dependency.
From-SVN: r217114
2014-11-05 09:26:54 +01:00
|
|
|
return QUAL_TYPE (HI);
|
2017-08-30 13:08:28 +02:00
|
|
|
case E_SImode:
|
[AArch64] Restructure arm_neon.h vector types.
2014-11-05 Tejas Belagod <tejas.belagod@arm.com>
* config/aarch64/aarch64-builtins.c
(aarch64_build_scalar_type): Remove.
(aarch64_scalar_builtin_types, aarch64_simd_type,
aarch64_simd_type, aarch64_mangle_builtin_scalar_type,
aarch64_mangle_builtin_vector_type,
aarch64_mangle_builtin_type, aarch64_simd_builtin_std_type,
aarch64_lookup_simd_builtin_type, aarch64_simd_builtin_type,
aarch64_init_simd_builtin_types,
aarch64_init_simd_builtin_scalar_types): New.
(aarch64_init_simd_builtins): Refactor.
(aarch64_init_crc32_builtins): Fixup with qualifier.
* config/aarch64/aarch64-protos.h
(aarch64_mangle_builtin_type): Export.
* config/aarch64/aarch64-simd-builtin-types.def: New.
* config/aarch64/aarch64.c (aarch64_simd_mangle_map): Remove.
(aarch64_mangle_type): Refactor.
* config/aarch64/arm_neon.h: Declare vector types based on
internal types.
* config/aarch64/t-aarch64: Update dependency.
From-SVN: r217114
2014-11-05 09:26:54 +01:00
|
|
|
return QUAL_TYPE (SI);
|
2017-08-30 13:08:28 +02:00
|
|
|
case E_DImode:
|
[AArch64] Restructure arm_neon.h vector types.
2014-11-05 Tejas Belagod <tejas.belagod@arm.com>
* config/aarch64/aarch64-builtins.c
(aarch64_build_scalar_type): Remove.
(aarch64_scalar_builtin_types, aarch64_simd_type,
aarch64_simd_type, aarch64_mangle_builtin_scalar_type,
aarch64_mangle_builtin_vector_type,
aarch64_mangle_builtin_type, aarch64_simd_builtin_std_type,
aarch64_lookup_simd_builtin_type, aarch64_simd_builtin_type,
aarch64_init_simd_builtin_types,
aarch64_init_simd_builtin_scalar_types): New.
(aarch64_init_simd_builtins): Refactor.
(aarch64_init_crc32_builtins): Fixup with qualifier.
* config/aarch64/aarch64-protos.h
(aarch64_mangle_builtin_type): Export.
* config/aarch64/aarch64-simd-builtin-types.def: New.
* config/aarch64/aarch64.c (aarch64_simd_mangle_map): Remove.
(aarch64_mangle_type): Refactor.
* config/aarch64/arm_neon.h: Declare vector types based on
internal types.
* config/aarch64/t-aarch64: Update dependency.
From-SVN: r217114
2014-11-05 09:26:54 +01:00
|
|
|
return QUAL_TYPE (DI);
|
2017-08-30 13:08:28 +02:00
|
|
|
case E_TImode:
|
[AArch64] Restructure arm_neon.h vector types.
2014-11-05 Tejas Belagod <tejas.belagod@arm.com>
* config/aarch64/aarch64-builtins.c
(aarch64_build_scalar_type): Remove.
(aarch64_scalar_builtin_types, aarch64_simd_type,
aarch64_simd_type, aarch64_mangle_builtin_scalar_type,
aarch64_mangle_builtin_vector_type,
aarch64_mangle_builtin_type, aarch64_simd_builtin_std_type,
aarch64_lookup_simd_builtin_type, aarch64_simd_builtin_type,
aarch64_init_simd_builtin_types,
aarch64_init_simd_builtin_scalar_types): New.
(aarch64_init_simd_builtins): Refactor.
(aarch64_init_crc32_builtins): Fixup with qualifier.
* config/aarch64/aarch64-protos.h
(aarch64_mangle_builtin_type): Export.
* config/aarch64/aarch64-simd-builtin-types.def: New.
* config/aarch64/aarch64.c (aarch64_simd_mangle_map): Remove.
(aarch64_mangle_type): Refactor.
* config/aarch64/arm_neon.h: Declare vector types based on
internal types.
* config/aarch64/t-aarch64: Update dependency.
From-SVN: r217114
2014-11-05 09:26:54 +01:00
|
|
|
return QUAL_TYPE (TI);
|
2017-08-30 13:08:28 +02:00
|
|
|
case E_OImode:
|
[AArch64] Restructure arm_neon.h vector types.
2014-11-05 Tejas Belagod <tejas.belagod@arm.com>
* config/aarch64/aarch64-builtins.c
(aarch64_build_scalar_type): Remove.
(aarch64_scalar_builtin_types, aarch64_simd_type,
aarch64_simd_type, aarch64_mangle_builtin_scalar_type,
aarch64_mangle_builtin_vector_type,
aarch64_mangle_builtin_type, aarch64_simd_builtin_std_type,
aarch64_lookup_simd_builtin_type, aarch64_simd_builtin_type,
aarch64_init_simd_builtin_types,
aarch64_init_simd_builtin_scalar_types): New.
(aarch64_init_simd_builtins): Refactor.
(aarch64_init_crc32_builtins): Fixup with qualifier.
* config/aarch64/aarch64-protos.h
(aarch64_mangle_builtin_type): Export.
* config/aarch64/aarch64-simd-builtin-types.def: New.
* config/aarch64/aarch64.c (aarch64_simd_mangle_map): Remove.
(aarch64_mangle_type): Refactor.
* config/aarch64/arm_neon.h: Declare vector types based on
internal types.
* config/aarch64/t-aarch64: Update dependency.
From-SVN: r217114
2014-11-05 09:26:54 +01:00
|
|
|
return aarch64_simd_intOI_type_node;
|
2017-08-30 13:08:28 +02:00
|
|
|
case E_CImode:
|
[AArch64] Restructure arm_neon.h vector types.
2014-11-05 Tejas Belagod <tejas.belagod@arm.com>
* config/aarch64/aarch64-builtins.c
(aarch64_build_scalar_type): Remove.
(aarch64_scalar_builtin_types, aarch64_simd_type,
aarch64_simd_type, aarch64_mangle_builtin_scalar_type,
aarch64_mangle_builtin_vector_type,
aarch64_mangle_builtin_type, aarch64_simd_builtin_std_type,
aarch64_lookup_simd_builtin_type, aarch64_simd_builtin_type,
aarch64_init_simd_builtin_types,
aarch64_init_simd_builtin_scalar_types): New.
(aarch64_init_simd_builtins): Refactor.
(aarch64_init_crc32_builtins): Fixup with qualifier.
* config/aarch64/aarch64-protos.h
(aarch64_mangle_builtin_type): Export.
* config/aarch64/aarch64-simd-builtin-types.def: New.
* config/aarch64/aarch64.c (aarch64_simd_mangle_map): Remove.
(aarch64_mangle_type): Refactor.
* config/aarch64/arm_neon.h: Declare vector types based on
internal types.
* config/aarch64/t-aarch64: Update dependency.
From-SVN: r217114
2014-11-05 09:26:54 +01:00
|
|
|
return aarch64_simd_intCI_type_node;
|
2017-08-30 13:08:28 +02:00
|
|
|
case E_XImode:
|
[AArch64] Restructure arm_neon.h vector types.
2014-11-05 Tejas Belagod <tejas.belagod@arm.com>
* config/aarch64/aarch64-builtins.c
(aarch64_build_scalar_type): Remove.
(aarch64_scalar_builtin_types, aarch64_simd_type,
aarch64_simd_type, aarch64_mangle_builtin_scalar_type,
aarch64_mangle_builtin_vector_type,
aarch64_mangle_builtin_type, aarch64_simd_builtin_std_type,
aarch64_lookup_simd_builtin_type, aarch64_simd_builtin_type,
aarch64_init_simd_builtin_types,
aarch64_init_simd_builtin_scalar_types): New.
(aarch64_init_simd_builtins): Refactor.
(aarch64_init_crc32_builtins): Fixup with qualifier.
* config/aarch64/aarch64-protos.h
(aarch64_mangle_builtin_type): Export.
* config/aarch64/aarch64-simd-builtin-types.def: New.
* config/aarch64/aarch64.c (aarch64_simd_mangle_map): Remove.
(aarch64_mangle_type): Refactor.
* config/aarch64/arm_neon.h: Declare vector types based on
internal types.
* config/aarch64/t-aarch64: Update dependency.
From-SVN: r217114
2014-11-05 09:26:54 +01:00
|
|
|
return aarch64_simd_intXI_type_node;
|
2017-08-30 13:08:28 +02:00
|
|
|
case E_HFmode:
|
[AArch64] Add support for float16x{4,8}_t vectors/builtins
gcc/:
* config/aarch64/aarch64.c (aarch64_vector_mode_supported_p): Support
V4HFmode and V8HFmode.
(aarch64_split_simd_move): Add case for V8HFmode.
* config/aarch64/aarch64-builtins.c (v4hf_UP, v8hf_UP): Define.
(aarch64_simd_builtin_std_type): Handle HFmode.
(aarch64_init_simd_builtin_types): Include Float16x4_t and Float16x8_t.
* config/aarch64/aarch64-simd.md (mov<mode>, aarch64_get_lane<mode>,
aarch64_ld1<VALL:mode>, aarch64_st1<VALL:mode): Use VALL_F16 iterator.
(aarch64_be_ld1<mode>, aarch64_be_st1<mode>): Use VALLDI_F16 iterator.
* config/aarch64/aarch64-simd-builtin-types.def: Add Float16x4_t,
Float16x8_t.
* config/aarch64/aarch64-simd-builtins.def (ld1, st1): Use VALL_F16.
* config/aarch64/arm_neon.h (float16x4_t, float16x8_t, float16_t):
New typedefs.
(vget_lane_f16, vgetq_lane_f16, vset_lane_f16, vsetq_lane_f16,
vld1_f16, vld1q_f16, vst1_f16, vst1q_f16, vst1_lane_f16,
vst1q_lane_f16): New.
* config/aarch64/iterators.md (VD, VQ, VQ_NO2E): Add vectors of HFmode.
(VALLDI_F16, VALL_F16): New.
(Vmtype, VEL, VCONQ, VHALF, V_TWO_ELEM, V_THREE_ELEM, V_FOUR_ELEM, q):
Add cases for V4HF and V8HF.
(VDBL, VRL2, VRL3, VRL4): Add V4HF case.
gcc/testsuite/:
* g++.dg/abi/mangle-neon-aarch64.C: Add cases for float16x4_t and
float16x8_t.
* gcc.target/aarch64/vset_lane_1.c: Likewise.
* gcc.target/aarch64/vld1-vst1_1.c: Likewise.
* gcc.target/aarch64/vld1_lane.c: Likewise.
From-SVN: r227542
2015-09-08 20:57:31 +02:00
|
|
|
return aarch64_fp16_type_node;
|
2017-08-30 13:08:28 +02:00
|
|
|
case E_SFmode:
|
[AArch64] Restructure arm_neon.h vector types.
2014-11-05 Tejas Belagod <tejas.belagod@arm.com>
* config/aarch64/aarch64-builtins.c
(aarch64_build_scalar_type): Remove.
(aarch64_scalar_builtin_types, aarch64_simd_type,
aarch64_simd_type, aarch64_mangle_builtin_scalar_type,
aarch64_mangle_builtin_vector_type,
aarch64_mangle_builtin_type, aarch64_simd_builtin_std_type,
aarch64_lookup_simd_builtin_type, aarch64_simd_builtin_type,
aarch64_init_simd_builtin_types,
aarch64_init_simd_builtin_scalar_types): New.
(aarch64_init_simd_builtins): Refactor.
(aarch64_init_crc32_builtins): Fixup with qualifier.
* config/aarch64/aarch64-protos.h
(aarch64_mangle_builtin_type): Export.
* config/aarch64/aarch64-simd-builtin-types.def: New.
* config/aarch64/aarch64.c (aarch64_simd_mangle_map): Remove.
(aarch64_mangle_type): Refactor.
* config/aarch64/arm_neon.h: Declare vector types based on
internal types.
* config/aarch64/t-aarch64: Update dependency.
From-SVN: r217114
2014-11-05 09:26:54 +01:00
|
|
|
return float_type_node;
|
2017-08-30 13:08:28 +02:00
|
|
|
case E_DFmode:
|
[AArch64] Restructure arm_neon.h vector types.
2014-11-05 Tejas Belagod <tejas.belagod@arm.com>
* config/aarch64/aarch64-builtins.c
(aarch64_build_scalar_type): Remove.
(aarch64_scalar_builtin_types, aarch64_simd_type,
aarch64_simd_type, aarch64_mangle_builtin_scalar_type,
aarch64_mangle_builtin_vector_type,
aarch64_mangle_builtin_type, aarch64_simd_builtin_std_type,
aarch64_lookup_simd_builtin_type, aarch64_simd_builtin_type,
aarch64_init_simd_builtin_types,
aarch64_init_simd_builtin_scalar_types): New.
(aarch64_init_simd_builtins): Refactor.
(aarch64_init_crc32_builtins): Fixup with qualifier.
* config/aarch64/aarch64-protos.h
(aarch64_mangle_builtin_type): Export.
* config/aarch64/aarch64-simd-builtin-types.def: New.
* config/aarch64/aarch64.c (aarch64_simd_mangle_map): Remove.
(aarch64_mangle_type): Refactor.
* config/aarch64/arm_neon.h: Declare vector types based on
internal types.
* config/aarch64/t-aarch64: Update dependency.
From-SVN: r217114
2014-11-05 09:26:54 +01:00
|
|
|
return double_type_node;
|
2020-01-10 20:23:41 +01:00
|
|
|
case E_BFmode:
|
|
|
|
return aarch64_bf16_type_node;
|
[AArch64] Restructure arm_neon.h vector types.
2014-11-05 Tejas Belagod <tejas.belagod@arm.com>
* config/aarch64/aarch64-builtins.c
(aarch64_build_scalar_type): Remove.
(aarch64_scalar_builtin_types, aarch64_simd_type,
aarch64_simd_type, aarch64_mangle_builtin_scalar_type,
aarch64_mangle_builtin_vector_type,
aarch64_mangle_builtin_type, aarch64_simd_builtin_std_type,
aarch64_lookup_simd_builtin_type, aarch64_simd_builtin_type,
aarch64_init_simd_builtin_types,
aarch64_init_simd_builtin_scalar_types): New.
(aarch64_init_simd_builtins): Refactor.
(aarch64_init_crc32_builtins): Fixup with qualifier.
* config/aarch64/aarch64-protos.h
(aarch64_mangle_builtin_type): Export.
* config/aarch64/aarch64-simd-builtin-types.def: New.
* config/aarch64/aarch64.c (aarch64_simd_mangle_map): Remove.
(aarch64_mangle_type): Refactor.
* config/aarch64/arm_neon.h: Declare vector types based on
internal types.
* config/aarch64/t-aarch64: Update dependency.
From-SVN: r217114
2014-11-05 09:26:54 +01:00
|
|
|
default:
|
|
|
|
gcc_unreachable ();
|
|
|
|
}
|
|
|
|
#undef QUAL_TYPE
|
2013-11-26 11:00:49 +01:00
|
|
|
}
|
|
|
|
|
[AArch64] Restructure arm_neon.h vector types.
2014-11-05 Tejas Belagod <tejas.belagod@arm.com>
* config/aarch64/aarch64-builtins.c
(aarch64_build_scalar_type): Remove.
(aarch64_scalar_builtin_types, aarch64_simd_type,
aarch64_simd_type, aarch64_mangle_builtin_scalar_type,
aarch64_mangle_builtin_vector_type,
aarch64_mangle_builtin_type, aarch64_simd_builtin_std_type,
aarch64_lookup_simd_builtin_type, aarch64_simd_builtin_type,
aarch64_init_simd_builtin_types,
aarch64_init_simd_builtin_scalar_types): New.
(aarch64_init_simd_builtins): Refactor.
(aarch64_init_crc32_builtins): Fixup with qualifier.
* config/aarch64/aarch64-protos.h
(aarch64_mangle_builtin_type): Export.
* config/aarch64/aarch64-simd-builtin-types.def: New.
* config/aarch64/aarch64.c (aarch64_simd_mangle_map): Remove.
(aarch64_mangle_type): Refactor.
* config/aarch64/arm_neon.h: Declare vector types based on
internal types.
* config/aarch64/t-aarch64: Update dependency.
From-SVN: r217114
2014-11-05 09:26:54 +01:00
|
|
|
static tree
|
2017-07-05 17:29:27 +02:00
|
|
|
aarch64_lookup_simd_builtin_type (machine_mode mode,
|
[AArch64] Restructure arm_neon.h vector types.
2014-11-05 Tejas Belagod <tejas.belagod@arm.com>
* config/aarch64/aarch64-builtins.c
(aarch64_build_scalar_type): Remove.
(aarch64_scalar_builtin_types, aarch64_simd_type,
aarch64_simd_type, aarch64_mangle_builtin_scalar_type,
aarch64_mangle_builtin_vector_type,
aarch64_mangle_builtin_type, aarch64_simd_builtin_std_type,
aarch64_lookup_simd_builtin_type, aarch64_simd_builtin_type,
aarch64_init_simd_builtin_types,
aarch64_init_simd_builtin_scalar_types): New.
(aarch64_init_simd_builtins): Refactor.
(aarch64_init_crc32_builtins): Fixup with qualifier.
* config/aarch64/aarch64-protos.h
(aarch64_mangle_builtin_type): Export.
* config/aarch64/aarch64-simd-builtin-types.def: New.
* config/aarch64/aarch64.c (aarch64_simd_mangle_map): Remove.
(aarch64_mangle_type): Refactor.
* config/aarch64/arm_neon.h: Declare vector types based on
internal types.
* config/aarch64/t-aarch64: Update dependency.
From-SVN: r217114
2014-11-05 09:26:54 +01:00
|
|
|
enum aarch64_type_qualifiers q)
|
2013-11-26 11:00:49 +01:00
|
|
|
{
|
[AArch64] Restructure arm_neon.h vector types.
2014-11-05 Tejas Belagod <tejas.belagod@arm.com>
* config/aarch64/aarch64-builtins.c
(aarch64_build_scalar_type): Remove.
(aarch64_scalar_builtin_types, aarch64_simd_type,
aarch64_simd_type, aarch64_mangle_builtin_scalar_type,
aarch64_mangle_builtin_vector_type,
aarch64_mangle_builtin_type, aarch64_simd_builtin_std_type,
aarch64_lookup_simd_builtin_type, aarch64_simd_builtin_type,
aarch64_init_simd_builtin_types,
aarch64_init_simd_builtin_scalar_types): New.
(aarch64_init_simd_builtins): Refactor.
(aarch64_init_crc32_builtins): Fixup with qualifier.
* config/aarch64/aarch64-protos.h
(aarch64_mangle_builtin_type): Export.
* config/aarch64/aarch64-simd-builtin-types.def: New.
* config/aarch64/aarch64.c (aarch64_simd_mangle_map): Remove.
(aarch64_mangle_type): Refactor.
* config/aarch64/arm_neon.h: Declare vector types based on
internal types.
* config/aarch64/t-aarch64: Update dependency.
From-SVN: r217114
2014-11-05 09:26:54 +01:00
|
|
|
int i;
|
|
|
|
int nelts = sizeof (aarch64_simd_types) / sizeof (aarch64_simd_types[0]);
|
|
|
|
|
|
|
|
/* Non-poly scalar modes map to standard types not in the table. */
|
|
|
|
if (q != qualifier_poly && !VECTOR_MODE_P (mode))
|
|
|
|
return aarch64_simd_builtin_std_type (mode, q);
|
|
|
|
|
|
|
|
for (i = 0; i < nelts; i++)
|
2021-08-09 16:26:48 +02:00
|
|
|
{
|
|
|
|
if (aarch64_simd_types[i].mode == mode
|
|
|
|
&& aarch64_simd_types[i].q == q)
|
|
|
|
return aarch64_simd_types[i].itype;
|
|
|
|
if (aarch64_simd_tuple_types[i][0] != NULL_TREE)
|
|
|
|
for (int j = 0; j < 3; j++)
|
2022-04-05 18:31:35 +02:00
|
|
|
if (aarch64_simd_tuple_modes[i][j] == mode
|
2021-08-09 16:26:48 +02:00
|
|
|
&& aarch64_simd_types[i].q == q)
|
|
|
|
return aarch64_simd_tuple_types[i][j];
|
|
|
|
}
|
[AArch64] Restructure arm_neon.h vector types.
2014-11-05 Tejas Belagod <tejas.belagod@arm.com>
* config/aarch64/aarch64-builtins.c
(aarch64_build_scalar_type): Remove.
(aarch64_scalar_builtin_types, aarch64_simd_type,
aarch64_simd_type, aarch64_mangle_builtin_scalar_type,
aarch64_mangle_builtin_vector_type,
aarch64_mangle_builtin_type, aarch64_simd_builtin_std_type,
aarch64_lookup_simd_builtin_type, aarch64_simd_builtin_type,
aarch64_init_simd_builtin_types,
aarch64_init_simd_builtin_scalar_types): New.
(aarch64_init_simd_builtins): Refactor.
(aarch64_init_crc32_builtins): Fixup with qualifier.
* config/aarch64/aarch64-protos.h
(aarch64_mangle_builtin_type): Export.
* config/aarch64/aarch64-simd-builtin-types.def: New.
* config/aarch64/aarch64.c (aarch64_simd_mangle_map): Remove.
(aarch64_mangle_type): Refactor.
* config/aarch64/arm_neon.h: Declare vector types based on
internal types.
* config/aarch64/t-aarch64: Update dependency.
From-SVN: r217114
2014-11-05 09:26:54 +01:00
|
|
|
|
|
|
|
return NULL_TREE;
|
2013-11-20 10:19:25 +01:00
|
|
|
}
|
|
|
|
|
[AArch64] Restructure arm_neon.h vector types.
2014-11-05 Tejas Belagod <tejas.belagod@arm.com>
* config/aarch64/aarch64-builtins.c
(aarch64_build_scalar_type): Remove.
(aarch64_scalar_builtin_types, aarch64_simd_type,
aarch64_simd_type, aarch64_mangle_builtin_scalar_type,
aarch64_mangle_builtin_vector_type,
aarch64_mangle_builtin_type, aarch64_simd_builtin_std_type,
aarch64_lookup_simd_builtin_type, aarch64_simd_builtin_type,
aarch64_init_simd_builtin_types,
aarch64_init_simd_builtin_scalar_types): New.
(aarch64_init_simd_builtins): Refactor.
(aarch64_init_crc32_builtins): Fixup with qualifier.
* config/aarch64/aarch64-protos.h
(aarch64_mangle_builtin_type): Export.
* config/aarch64/aarch64-simd-builtin-types.def: New.
* config/aarch64/aarch64.c (aarch64_simd_mangle_map): Remove.
(aarch64_mangle_type): Refactor.
* config/aarch64/arm_neon.h: Declare vector types based on
internal types.
* config/aarch64/t-aarch64: Update dependency.
From-SVN: r217114
2014-11-05 09:26:54 +01:00
|
|
|
static tree
|
2017-07-05 17:29:27 +02:00
|
|
|
aarch64_simd_builtin_type (machine_mode mode,
|
[AArch64] Restructure arm_neon.h vector types.
2014-11-05 Tejas Belagod <tejas.belagod@arm.com>
* config/aarch64/aarch64-builtins.c
(aarch64_build_scalar_type): Remove.
(aarch64_scalar_builtin_types, aarch64_simd_type,
aarch64_simd_type, aarch64_mangle_builtin_scalar_type,
aarch64_mangle_builtin_vector_type,
aarch64_mangle_builtin_type, aarch64_simd_builtin_std_type,
aarch64_lookup_simd_builtin_type, aarch64_simd_builtin_type,
aarch64_init_simd_builtin_types,
aarch64_init_simd_builtin_scalar_types): New.
(aarch64_init_simd_builtins): Refactor.
(aarch64_init_crc32_builtins): Fixup with qualifier.
* config/aarch64/aarch64-protos.h
(aarch64_mangle_builtin_type): Export.
* config/aarch64/aarch64-simd-builtin-types.def: New.
* config/aarch64/aarch64.c (aarch64_simd_mangle_map): Remove.
(aarch64_mangle_type): Refactor.
* config/aarch64/arm_neon.h: Declare vector types based on
internal types.
* config/aarch64/t-aarch64: Update dependency.
From-SVN: r217114
2014-11-05 09:26:54 +01:00
|
|
|
bool unsigned_p, bool poly_p)
|
|
|
|
{
|
|
|
|
if (poly_p)
|
|
|
|
return aarch64_lookup_simd_builtin_type (mode, qualifier_poly);
|
|
|
|
else if (unsigned_p)
|
|
|
|
return aarch64_lookup_simd_builtin_type (mode, qualifier_unsigned);
|
|
|
|
else
|
|
|
|
return aarch64_lookup_simd_builtin_type (mode, qualifier_none);
|
|
|
|
}
|
|
|
|
|
2013-02-28 18:19:33 +01:00
|
|
|
static void
|
[AArch64] Restructure arm_neon.h vector types.
2014-11-05 Tejas Belagod <tejas.belagod@arm.com>
* config/aarch64/aarch64-builtins.c
(aarch64_build_scalar_type): Remove.
(aarch64_scalar_builtin_types, aarch64_simd_type,
aarch64_simd_type, aarch64_mangle_builtin_scalar_type,
aarch64_mangle_builtin_vector_type,
aarch64_mangle_builtin_type, aarch64_simd_builtin_std_type,
aarch64_lookup_simd_builtin_type, aarch64_simd_builtin_type,
aarch64_init_simd_builtin_types,
aarch64_init_simd_builtin_scalar_types): New.
(aarch64_init_simd_builtins): Refactor.
(aarch64_init_crc32_builtins): Fixup with qualifier.
* config/aarch64/aarch64-protos.h
(aarch64_mangle_builtin_type): Export.
* config/aarch64/aarch64-simd-builtin-types.def: New.
* config/aarch64/aarch64.c (aarch64_simd_mangle_map): Remove.
(aarch64_mangle_type): Refactor.
* config/aarch64/arm_neon.h: Declare vector types based on
internal types.
* config/aarch64/t-aarch64: Update dependency.
From-SVN: r217114
2014-11-05 09:26:54 +01:00
|
|
|
aarch64_init_simd_builtin_types (void)
|
2012-10-23 19:02:30 +02:00
|
|
|
{
|
[AArch64] Restructure arm_neon.h vector types.
2014-11-05 Tejas Belagod <tejas.belagod@arm.com>
* config/aarch64/aarch64-builtins.c
(aarch64_build_scalar_type): Remove.
(aarch64_scalar_builtin_types, aarch64_simd_type,
aarch64_simd_type, aarch64_mangle_builtin_scalar_type,
aarch64_mangle_builtin_vector_type,
aarch64_mangle_builtin_type, aarch64_simd_builtin_std_type,
aarch64_lookup_simd_builtin_type, aarch64_simd_builtin_type,
aarch64_init_simd_builtin_types,
aarch64_init_simd_builtin_scalar_types): New.
(aarch64_init_simd_builtins): Refactor.
(aarch64_init_crc32_builtins): Fixup with qualifier.
* config/aarch64/aarch64-protos.h
(aarch64_mangle_builtin_type): Export.
* config/aarch64/aarch64-simd-builtin-types.def: New.
* config/aarch64/aarch64.c (aarch64_simd_mangle_map): Remove.
(aarch64_mangle_type): Refactor.
* config/aarch64/arm_neon.h: Declare vector types based on
internal types.
* config/aarch64/t-aarch64: Update dependency.
From-SVN: r217114
2014-11-05 09:26:54 +01:00
|
|
|
int i;
|
|
|
|
int nelts = sizeof (aarch64_simd_types) / sizeof (aarch64_simd_types[0]);
|
|
|
|
tree tdecl;
|
|
|
|
|
|
|
|
/* Init all the element types built by the front-end. */
|
|
|
|
aarch64_simd_types[Int8x8_t].eltype = intQI_type_node;
|
|
|
|
aarch64_simd_types[Int8x16_t].eltype = intQI_type_node;
|
|
|
|
aarch64_simd_types[Int16x4_t].eltype = intHI_type_node;
|
|
|
|
aarch64_simd_types[Int16x8_t].eltype = intHI_type_node;
|
|
|
|
aarch64_simd_types[Int32x2_t].eltype = intSI_type_node;
|
|
|
|
aarch64_simd_types[Int32x4_t].eltype = intSI_type_node;
|
|
|
|
aarch64_simd_types[Int64x1_t].eltype = intDI_type_node;
|
|
|
|
aarch64_simd_types[Int64x2_t].eltype = intDI_type_node;
|
|
|
|
aarch64_simd_types[Uint8x8_t].eltype = unsigned_intQI_type_node;
|
|
|
|
aarch64_simd_types[Uint8x16_t].eltype = unsigned_intQI_type_node;
|
|
|
|
aarch64_simd_types[Uint16x4_t].eltype = unsigned_intHI_type_node;
|
|
|
|
aarch64_simd_types[Uint16x8_t].eltype = unsigned_intHI_type_node;
|
|
|
|
aarch64_simd_types[Uint32x2_t].eltype = unsigned_intSI_type_node;
|
|
|
|
aarch64_simd_types[Uint32x4_t].eltype = unsigned_intSI_type_node;
|
|
|
|
aarch64_simd_types[Uint64x1_t].eltype = unsigned_intDI_type_node;
|
|
|
|
aarch64_simd_types[Uint64x2_t].eltype = unsigned_intDI_type_node;
|
|
|
|
|
|
|
|
/* Poly types are a world of their own. */
|
|
|
|
aarch64_simd_types[Poly8_t].eltype = aarch64_simd_types[Poly8_t].itype =
|
|
|
|
build_distinct_type_copy (unsigned_intQI_type_node);
|
2018-08-15 17:25:46 +02:00
|
|
|
/* Prevent front-ends from transforming Poly8_t arrays into string
|
|
|
|
literals. */
|
|
|
|
TYPE_STRING_FLAG (aarch64_simd_types[Poly8_t].eltype) = false;
|
|
|
|
|
[AArch64] Restructure arm_neon.h vector types.
2014-11-05 Tejas Belagod <tejas.belagod@arm.com>
* config/aarch64/aarch64-builtins.c
(aarch64_build_scalar_type): Remove.
(aarch64_scalar_builtin_types, aarch64_simd_type,
aarch64_simd_type, aarch64_mangle_builtin_scalar_type,
aarch64_mangle_builtin_vector_type,
aarch64_mangle_builtin_type, aarch64_simd_builtin_std_type,
aarch64_lookup_simd_builtin_type, aarch64_simd_builtin_type,
aarch64_init_simd_builtin_types,
aarch64_init_simd_builtin_scalar_types): New.
(aarch64_init_simd_builtins): Refactor.
(aarch64_init_crc32_builtins): Fixup with qualifier.
* config/aarch64/aarch64-protos.h
(aarch64_mangle_builtin_type): Export.
* config/aarch64/aarch64-simd-builtin-types.def: New.
* config/aarch64/aarch64.c (aarch64_simd_mangle_map): Remove.
(aarch64_mangle_type): Refactor.
* config/aarch64/arm_neon.h: Declare vector types based on
internal types.
* config/aarch64/t-aarch64: Update dependency.
From-SVN: r217114
2014-11-05 09:26:54 +01:00
|
|
|
aarch64_simd_types[Poly16_t].eltype = aarch64_simd_types[Poly16_t].itype =
|
|
|
|
build_distinct_type_copy (unsigned_intHI_type_node);
|
|
|
|
aarch64_simd_types[Poly64_t].eltype = aarch64_simd_types[Poly64_t].itype =
|
|
|
|
build_distinct_type_copy (unsigned_intDI_type_node);
|
|
|
|
aarch64_simd_types[Poly128_t].eltype = aarch64_simd_types[Poly128_t].itype =
|
|
|
|
build_distinct_type_copy (unsigned_intTI_type_node);
|
|
|
|
/* Init poly vector element types with scalar poly types. */
|
|
|
|
aarch64_simd_types[Poly8x8_t].eltype = aarch64_simd_types[Poly8_t].itype;
|
|
|
|
aarch64_simd_types[Poly8x16_t].eltype = aarch64_simd_types[Poly8_t].itype;
|
|
|
|
aarch64_simd_types[Poly16x4_t].eltype = aarch64_simd_types[Poly16_t].itype;
|
|
|
|
aarch64_simd_types[Poly16x8_t].eltype = aarch64_simd_types[Poly16_t].itype;
|
|
|
|
aarch64_simd_types[Poly64x1_t].eltype = aarch64_simd_types[Poly64_t].itype;
|
|
|
|
aarch64_simd_types[Poly64x2_t].eltype = aarch64_simd_types[Poly64_t].itype;
|
|
|
|
|
|
|
|
/* Continue with standard types. */
|
[AArch64] Add support for float16x{4,8}_t vectors/builtins
gcc/:
* config/aarch64/aarch64.c (aarch64_vector_mode_supported_p): Support
V4HFmode and V8HFmode.
(aarch64_split_simd_move): Add case for V8HFmode.
* config/aarch64/aarch64-builtins.c (v4hf_UP, v8hf_UP): Define.
(aarch64_simd_builtin_std_type): Handle HFmode.
(aarch64_init_simd_builtin_types): Include Float16x4_t and Float16x8_t.
* config/aarch64/aarch64-simd.md (mov<mode>, aarch64_get_lane<mode>,
aarch64_ld1<VALL:mode>, aarch64_st1<VALL:mode): Use VALL_F16 iterator.
(aarch64_be_ld1<mode>, aarch64_be_st1<mode>): Use VALLDI_F16 iterator.
* config/aarch64/aarch64-simd-builtin-types.def: Add Float16x4_t,
Float16x8_t.
* config/aarch64/aarch64-simd-builtins.def (ld1, st1): Use VALL_F16.
* config/aarch64/arm_neon.h (float16x4_t, float16x8_t, float16_t):
New typedefs.
(vget_lane_f16, vgetq_lane_f16, vset_lane_f16, vsetq_lane_f16,
vld1_f16, vld1q_f16, vst1_f16, vst1q_f16, vst1_lane_f16,
vst1q_lane_f16): New.
* config/aarch64/iterators.md (VD, VQ, VQ_NO2E): Add vectors of HFmode.
(VALLDI_F16, VALL_F16): New.
(Vmtype, VEL, VCONQ, VHALF, V_TWO_ELEM, V_THREE_ELEM, V_FOUR_ELEM, q):
Add cases for V4HF and V8HF.
(VDBL, VRL2, VRL3, VRL4): Add V4HF case.
gcc/testsuite/:
* g++.dg/abi/mangle-neon-aarch64.C: Add cases for float16x4_t and
float16x8_t.
* gcc.target/aarch64/vset_lane_1.c: Likewise.
* gcc.target/aarch64/vld1-vst1_1.c: Likewise.
* gcc.target/aarch64/vld1_lane.c: Likewise.
From-SVN: r227542
2015-09-08 20:57:31 +02:00
|
|
|
aarch64_simd_types[Float16x4_t].eltype = aarch64_fp16_type_node;
|
|
|
|
aarch64_simd_types[Float16x8_t].eltype = aarch64_fp16_type_node;
|
[AArch64] Restructure arm_neon.h vector types.
2014-11-05 Tejas Belagod <tejas.belagod@arm.com>
* config/aarch64/aarch64-builtins.c
(aarch64_build_scalar_type): Remove.
(aarch64_scalar_builtin_types, aarch64_simd_type,
aarch64_simd_type, aarch64_mangle_builtin_scalar_type,
aarch64_mangle_builtin_vector_type,
aarch64_mangle_builtin_type, aarch64_simd_builtin_std_type,
aarch64_lookup_simd_builtin_type, aarch64_simd_builtin_type,
aarch64_init_simd_builtin_types,
aarch64_init_simd_builtin_scalar_types): New.
(aarch64_init_simd_builtins): Refactor.
(aarch64_init_crc32_builtins): Fixup with qualifier.
* config/aarch64/aarch64-protos.h
(aarch64_mangle_builtin_type): Export.
* config/aarch64/aarch64-simd-builtin-types.def: New.
* config/aarch64/aarch64.c (aarch64_simd_mangle_map): Remove.
(aarch64_mangle_type): Refactor.
* config/aarch64/arm_neon.h: Declare vector types based on
internal types.
* config/aarch64/t-aarch64: Update dependency.
From-SVN: r217114
2014-11-05 09:26:54 +01:00
|
|
|
aarch64_simd_types[Float32x2_t].eltype = float_type_node;
|
|
|
|
aarch64_simd_types[Float32x4_t].eltype = float_type_node;
|
|
|
|
aarch64_simd_types[Float64x1_t].eltype = double_type_node;
|
|
|
|
aarch64_simd_types[Float64x2_t].eltype = double_type_node;
|
|
|
|
|
2020-01-10 20:23:41 +01:00
|
|
|
/* Init Bfloat vector types with underlying __bf16 type. */
|
|
|
|
aarch64_simd_types[Bfloat16x4_t].eltype = aarch64_bf16_type_node;
|
|
|
|
aarch64_simd_types[Bfloat16x8_t].eltype = aarch64_bf16_type_node;
|
|
|
|
|
[AArch64] Restructure arm_neon.h vector types.
2014-11-05 Tejas Belagod <tejas.belagod@arm.com>
* config/aarch64/aarch64-builtins.c
(aarch64_build_scalar_type): Remove.
(aarch64_scalar_builtin_types, aarch64_simd_type,
aarch64_simd_type, aarch64_mangle_builtin_scalar_type,
aarch64_mangle_builtin_vector_type,
aarch64_mangle_builtin_type, aarch64_simd_builtin_std_type,
aarch64_lookup_simd_builtin_type, aarch64_simd_builtin_type,
aarch64_init_simd_builtin_types,
aarch64_init_simd_builtin_scalar_types): New.
(aarch64_init_simd_builtins): Refactor.
(aarch64_init_crc32_builtins): Fixup with qualifier.
* config/aarch64/aarch64-protos.h
(aarch64_mangle_builtin_type): Export.
* config/aarch64/aarch64-simd-builtin-types.def: New.
* config/aarch64/aarch64.c (aarch64_simd_mangle_map): Remove.
(aarch64_mangle_type): Refactor.
* config/aarch64/arm_neon.h: Declare vector types based on
internal types.
* config/aarch64/t-aarch64: Update dependency.
From-SVN: r217114
2014-11-05 09:26:54 +01:00
|
|
|
for (i = 0; i < nelts; i++)
|
|
|
|
{
|
|
|
|
tree eltype = aarch64_simd_types[i].eltype;
|
2017-07-05 17:29:27 +02:00
|
|
|
machine_mode mode = aarch64_simd_types[i].mode;
|
[AArch64] Restructure arm_neon.h vector types.
2014-11-05 Tejas Belagod <tejas.belagod@arm.com>
* config/aarch64/aarch64-builtins.c
(aarch64_build_scalar_type): Remove.
(aarch64_scalar_builtin_types, aarch64_simd_type,
aarch64_simd_type, aarch64_mangle_builtin_scalar_type,
aarch64_mangle_builtin_vector_type,
aarch64_mangle_builtin_type, aarch64_simd_builtin_std_type,
aarch64_lookup_simd_builtin_type, aarch64_simd_builtin_type,
aarch64_init_simd_builtin_types,
aarch64_init_simd_builtin_scalar_types): New.
(aarch64_init_simd_builtins): Refactor.
(aarch64_init_crc32_builtins): Fixup with qualifier.
* config/aarch64/aarch64-protos.h
(aarch64_mangle_builtin_type): Export.
* config/aarch64/aarch64-simd-builtin-types.def: New.
* config/aarch64/aarch64.c (aarch64_simd_mangle_map): Remove.
(aarch64_mangle_type): Refactor.
* config/aarch64/arm_neon.h: Declare vector types based on
internal types.
* config/aarch64/t-aarch64: Update dependency.
From-SVN: r217114
2014-11-05 09:26:54 +01:00
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if (aarch64_simd_types[i].itype == NULL)
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2016-01-26 11:04:46 +01:00
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{
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aarch64: Treat GNU and Advanced SIMD vectors as distinct [PR92789, PR95726]
PR95726 is about template look-up for things like:
foo<float vecf __attribute__((vector_size(16)))>
foo<float32x4_t>
The immediate cause of the problem is that the hash function usually
returns different hashes for these types, yet the equality function
thinks they are equal. This then raises the question of how the types
are supposed to be treated.
I think the answer is that the GNU vector type should be treated as
distinct from float32x4_t, not least because the two types mangle
differently. However, each type should implicitly convert to the other.
This would mean that, as far as the PR is concerned, the hashing
function is right to (sometimes) treat the types differently and
the equality function is wrong to treat them as the same.
The most obvious way to enforce the type difference is to use a
target-specific type attribute. That on its own is enough to fix
the PR. The difficulty is deciding whether the knock-on effects
are acceptable.
One obvious effect is that GCC then rejects:
typedef float vecf __attribute__((vector_size(16)));
vecf x;
float32x4_t &z = x;
on the basis that the types are no longer reference-compatible.
I think that's again the correct behaviour, and consistent with
current Clang.
A trickier question is whether:
vecf x;
float32x4_t y;
… c ? x : y …
should be valid, and if so, what its type should be [PR92789].
As explained in the comment in the testcase, GCC and Clang both
accepted this, but GCC chose the “then” type while Clang chose
the “else” type. This can lead to different mangling for (probably
artificial) corner cases, as seen for “sel1” and “sel2” in the
testcase.
Adding the attribute makes GCC reject the conditional expression
as ambiguous. I think that too is the correct behaviour, for the
reasons described in the testcase. However, it does seem to have
the potential to break existing code.
It looks like aarch64_comp_type_attributes is missing cases for
the SVE attributes, but I'll handle that in a separate patch.
2020-06-30 Richard Sandiford <richard.sandiford@arm.com>
gcc/
PR target/92789
PR target/95726
* config/aarch64/aarch64.c (aarch64_attribute_table): Add
"Advanced SIMD type".
(aarch64_comp_type_attributes): Check that the "Advanced SIMD type"
attributes are equal.
* config/aarch64/aarch64-builtins.c: Include stringpool.h and
attribs.h.
(aarch64_mangle_builtin_vector_type): Use the mangling recorded
in the "Advanced SIMD type" attribute.
(aarch64_init_simd_builtin_types): Add an "Advanced SIMD type"
attribute to each Advanced SIMD type, using the mangled type
as the attribute's single argument.
gcc/testsuite/
PR target/92789
PR target/95726
* g++.target/aarch64/pr95726.C: New test.
2020-06-30 22:40:30 +02:00
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tree type = build_vector_type (eltype, GET_MODE_NUNITS (mode));
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type = build_distinct_type_copy (type);
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SET_TYPE_STRUCTURAL_EQUALITY (type);
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tree mangled_name = get_identifier (aarch64_simd_types[i].mangle);
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tree value = tree_cons (NULL_TREE, mangled_name, NULL_TREE);
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TYPE_ATTRIBUTES (type)
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= tree_cons (get_identifier ("Advanced SIMD type"), value,
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TYPE_ATTRIBUTES (type));
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aarch64_simd_types[i].itype = type;
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2016-01-26 11:04:46 +01:00
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}
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[AArch64] Restructure arm_neon.h vector types.
2014-11-05 Tejas Belagod <tejas.belagod@arm.com>
* config/aarch64/aarch64-builtins.c
(aarch64_build_scalar_type): Remove.
(aarch64_scalar_builtin_types, aarch64_simd_type,
aarch64_simd_type, aarch64_mangle_builtin_scalar_type,
aarch64_mangle_builtin_vector_type,
aarch64_mangle_builtin_type, aarch64_simd_builtin_std_type,
aarch64_lookup_simd_builtin_type, aarch64_simd_builtin_type,
aarch64_init_simd_builtin_types,
aarch64_init_simd_builtin_scalar_types): New.
(aarch64_init_simd_builtins): Refactor.
(aarch64_init_crc32_builtins): Fixup with qualifier.
* config/aarch64/aarch64-protos.h
(aarch64_mangle_builtin_type): Export.
* config/aarch64/aarch64-simd-builtin-types.def: New.
* config/aarch64/aarch64.c (aarch64_simd_mangle_map): Remove.
(aarch64_mangle_type): Refactor.
* config/aarch64/arm_neon.h: Declare vector types based on
internal types.
* config/aarch64/t-aarch64: Update dependency.
From-SVN: r217114
2014-11-05 09:26:54 +01:00
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tdecl = add_builtin_type (aarch64_simd_types[i].name,
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aarch64_simd_types[i].itype);
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TYPE_NAME (aarch64_simd_types[i].itype) = tdecl;
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}
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2012-10-23 19:02:30 +02:00
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[AArch64] Restructure arm_neon.h vector types.
2014-11-05 Tejas Belagod <tejas.belagod@arm.com>
* config/aarch64/aarch64-builtins.c
(aarch64_build_scalar_type): Remove.
(aarch64_scalar_builtin_types, aarch64_simd_type,
aarch64_simd_type, aarch64_mangle_builtin_scalar_type,
aarch64_mangle_builtin_vector_type,
aarch64_mangle_builtin_type, aarch64_simd_builtin_std_type,
aarch64_lookup_simd_builtin_type, aarch64_simd_builtin_type,
aarch64_init_simd_builtin_types,
aarch64_init_simd_builtin_scalar_types): New.
(aarch64_init_simd_builtins): Refactor.
(aarch64_init_crc32_builtins): Fixup with qualifier.
* config/aarch64/aarch64-protos.h
(aarch64_mangle_builtin_type): Export.
* config/aarch64/aarch64-simd-builtin-types.def: New.
* config/aarch64/aarch64.c (aarch64_simd_mangle_map): Remove.
(aarch64_mangle_type): Refactor.
* config/aarch64/arm_neon.h: Declare vector types based on
internal types.
* config/aarch64/t-aarch64: Update dependency.
From-SVN: r217114
2014-11-05 09:26:54 +01:00
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#define AARCH64_BUILD_SIGNED_TYPE(mode) \
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make_signed_type (GET_MODE_PRECISION (mode));
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aarch64_simd_intOI_type_node = AARCH64_BUILD_SIGNED_TYPE (OImode);
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aarch64_simd_intCI_type_node = AARCH64_BUILD_SIGNED_TYPE (CImode);
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aarch64_simd_intXI_type_node = AARCH64_BUILD_SIGNED_TYPE (XImode);
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#undef AARCH64_BUILD_SIGNED_TYPE
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tdecl = add_builtin_type
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("__builtin_aarch64_simd_oi" , aarch64_simd_intOI_type_node);
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TYPE_NAME (aarch64_simd_intOI_type_node) = tdecl;
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tdecl = add_builtin_type
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("__builtin_aarch64_simd_ci" , aarch64_simd_intCI_type_node);
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TYPE_NAME (aarch64_simd_intCI_type_node) = tdecl;
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tdecl = add_builtin_type
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("__builtin_aarch64_simd_xi" , aarch64_simd_intXI_type_node);
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TYPE_NAME (aarch64_simd_intXI_type_node) = tdecl;
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}
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static void
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aarch64_init_simd_builtin_scalar_types (void)
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{
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/* Define typedefs for all the standard scalar types. */
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(*lang_hooks.types.register_builtin_type) (intQI_type_node,
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2012-10-23 19:02:30 +02:00
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"__builtin_aarch64_simd_qi");
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[AArch64] Restructure arm_neon.h vector types.
2014-11-05 Tejas Belagod <tejas.belagod@arm.com>
* config/aarch64/aarch64-builtins.c
(aarch64_build_scalar_type): Remove.
(aarch64_scalar_builtin_types, aarch64_simd_type,
aarch64_simd_type, aarch64_mangle_builtin_scalar_type,
aarch64_mangle_builtin_vector_type,
aarch64_mangle_builtin_type, aarch64_simd_builtin_std_type,
aarch64_lookup_simd_builtin_type, aarch64_simd_builtin_type,
aarch64_init_simd_builtin_types,
aarch64_init_simd_builtin_scalar_types): New.
(aarch64_init_simd_builtins): Refactor.
(aarch64_init_crc32_builtins): Fixup with qualifier.
* config/aarch64/aarch64-protos.h
(aarch64_mangle_builtin_type): Export.
* config/aarch64/aarch64-simd-builtin-types.def: New.
* config/aarch64/aarch64.c (aarch64_simd_mangle_map): Remove.
(aarch64_mangle_type): Refactor.
* config/aarch64/arm_neon.h: Declare vector types based on
internal types.
* config/aarch64/t-aarch64: Update dependency.
From-SVN: r217114
2014-11-05 09:26:54 +01:00
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(*lang_hooks.types.register_builtin_type) (intHI_type_node,
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2012-10-23 19:02:30 +02:00
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"__builtin_aarch64_simd_hi");
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[AArch64] vld{2,3,4}{,_lane,_dup}, vcombine, vcreate
gcc/:
* config/aarch64/aarch64.c (aarch64_split_simd_combine): Add V4HFmode.
* config/aarch64/aarch64-builtins.c (VAR13, VAR14): New.
(aarch64_scalar_builtin_types, aarch64_init_simd_builtin_scalar_types):
Add __builtin_aarch64_simd_hf.
* config/aarch64/arm_neon.h (float16x4x2_t, float16x8x2_t,
float16x4x3_t, float16x8x3_t, float16x4x4_t, float16x8x4_t,
vcombine_f16, vst2_lane_f16, vst2q_lane_f16, vst3_lane_f16,
vst3q_lane_f16, vst4_lane_f16, vst4q_lane_f16, vld2_f16, vld2q_f16,
vld3_f16, vld3q_f16, vld4_f16, vld4q_f16, vld2_dup_f16, vld2q_dup_f16,
vld3_dup_f16, vld3q_dup_f16, vld4_dup_f16, vld4q_dup_f16,
vld2_lane_f16, vld2q_lane_f16, vld3_lane_f16, vld3q_lane_f16,
vld4_lane_f16, vld4q_lane_f16, vst2_f16, vst2q_f16, vst3_f16,
vst3q_f16, vst4_f16, vst4q_f16, vcreate_f16): New.
* config/aarch64/iterators.md (VALLDIF, Vtype, Vetype, Vbtype,
V_cmp_result, v_cmp_result): Add cases for V4HF and V8HF.
(VDC, Vdbl): Add V4HF.
gcc/testsuite/:
* gcc.target/aarch64/vldN_1.c: Add float16x4_t and float16x8_t cases.
* gcc.target/aarch64/vldN_dup_1.c: Likewise.
* gcc.target/aarch64/vldN_lane_1.c: Likewise.
(main): update orig_data to avoid float16 NaN on bigendian.
From-SVN: r227543
2015-09-08 21:03:53 +02:00
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(*lang_hooks.types.register_builtin_type) (aarch64_fp16_type_node,
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"__builtin_aarch64_simd_hf");
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[AArch64] Restructure arm_neon.h vector types.
2014-11-05 Tejas Belagod <tejas.belagod@arm.com>
* config/aarch64/aarch64-builtins.c
(aarch64_build_scalar_type): Remove.
(aarch64_scalar_builtin_types, aarch64_simd_type,
aarch64_simd_type, aarch64_mangle_builtin_scalar_type,
aarch64_mangle_builtin_vector_type,
aarch64_mangle_builtin_type, aarch64_simd_builtin_std_type,
aarch64_lookup_simd_builtin_type, aarch64_simd_builtin_type,
aarch64_init_simd_builtin_types,
aarch64_init_simd_builtin_scalar_types): New.
(aarch64_init_simd_builtins): Refactor.
(aarch64_init_crc32_builtins): Fixup with qualifier.
* config/aarch64/aarch64-protos.h
(aarch64_mangle_builtin_type): Export.
* config/aarch64/aarch64-simd-builtin-types.def: New.
* config/aarch64/aarch64.c (aarch64_simd_mangle_map): Remove.
(aarch64_mangle_type): Refactor.
* config/aarch64/arm_neon.h: Declare vector types based on
internal types.
* config/aarch64/t-aarch64: Update dependency.
From-SVN: r217114
2014-11-05 09:26:54 +01:00
|
|
|
(*lang_hooks.types.register_builtin_type) (intSI_type_node,
|
2012-10-23 19:02:30 +02:00
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|
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"__builtin_aarch64_simd_si");
|
[AArch64] Restructure arm_neon.h vector types.
2014-11-05 Tejas Belagod <tejas.belagod@arm.com>
* config/aarch64/aarch64-builtins.c
(aarch64_build_scalar_type): Remove.
(aarch64_scalar_builtin_types, aarch64_simd_type,
aarch64_simd_type, aarch64_mangle_builtin_scalar_type,
aarch64_mangle_builtin_vector_type,
aarch64_mangle_builtin_type, aarch64_simd_builtin_std_type,
aarch64_lookup_simd_builtin_type, aarch64_simd_builtin_type,
aarch64_init_simd_builtin_types,
aarch64_init_simd_builtin_scalar_types): New.
(aarch64_init_simd_builtins): Refactor.
(aarch64_init_crc32_builtins): Fixup with qualifier.
* config/aarch64/aarch64-protos.h
(aarch64_mangle_builtin_type): Export.
* config/aarch64/aarch64-simd-builtin-types.def: New.
* config/aarch64/aarch64.c (aarch64_simd_mangle_map): Remove.
(aarch64_mangle_type): Refactor.
* config/aarch64/arm_neon.h: Declare vector types based on
internal types.
* config/aarch64/t-aarch64: Update dependency.
From-SVN: r217114
2014-11-05 09:26:54 +01:00
|
|
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(*lang_hooks.types.register_builtin_type) (float_type_node,
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2012-10-23 19:02:30 +02:00
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|
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"__builtin_aarch64_simd_sf");
|
[AArch64] Restructure arm_neon.h vector types.
2014-11-05 Tejas Belagod <tejas.belagod@arm.com>
* config/aarch64/aarch64-builtins.c
(aarch64_build_scalar_type): Remove.
(aarch64_scalar_builtin_types, aarch64_simd_type,
aarch64_simd_type, aarch64_mangle_builtin_scalar_type,
aarch64_mangle_builtin_vector_type,
aarch64_mangle_builtin_type, aarch64_simd_builtin_std_type,
aarch64_lookup_simd_builtin_type, aarch64_simd_builtin_type,
aarch64_init_simd_builtin_types,
aarch64_init_simd_builtin_scalar_types): New.
(aarch64_init_simd_builtins): Refactor.
(aarch64_init_crc32_builtins): Fixup with qualifier.
* config/aarch64/aarch64-protos.h
(aarch64_mangle_builtin_type): Export.
* config/aarch64/aarch64-simd-builtin-types.def: New.
* config/aarch64/aarch64.c (aarch64_simd_mangle_map): Remove.
(aarch64_mangle_type): Refactor.
* config/aarch64/arm_neon.h: Declare vector types based on
internal types.
* config/aarch64/t-aarch64: Update dependency.
From-SVN: r217114
2014-11-05 09:26:54 +01:00
|
|
|
(*lang_hooks.types.register_builtin_type) (intDI_type_node,
|
2012-10-23 19:02:30 +02:00
|
|
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"__builtin_aarch64_simd_di");
|
[AArch64] Restructure arm_neon.h vector types.
2014-11-05 Tejas Belagod <tejas.belagod@arm.com>
* config/aarch64/aarch64-builtins.c
(aarch64_build_scalar_type): Remove.
(aarch64_scalar_builtin_types, aarch64_simd_type,
aarch64_simd_type, aarch64_mangle_builtin_scalar_type,
aarch64_mangle_builtin_vector_type,
aarch64_mangle_builtin_type, aarch64_simd_builtin_std_type,
aarch64_lookup_simd_builtin_type, aarch64_simd_builtin_type,
aarch64_init_simd_builtin_types,
aarch64_init_simd_builtin_scalar_types): New.
(aarch64_init_simd_builtins): Refactor.
(aarch64_init_crc32_builtins): Fixup with qualifier.
* config/aarch64/aarch64-protos.h
(aarch64_mangle_builtin_type): Export.
* config/aarch64/aarch64-simd-builtin-types.def: New.
* config/aarch64/aarch64.c (aarch64_simd_mangle_map): Remove.
(aarch64_mangle_type): Refactor.
* config/aarch64/arm_neon.h: Declare vector types based on
internal types.
* config/aarch64/t-aarch64: Update dependency.
From-SVN: r217114
2014-11-05 09:26:54 +01:00
|
|
|
(*lang_hooks.types.register_builtin_type) (double_type_node,
|
2012-10-23 19:02:30 +02:00
|
|
|
"__builtin_aarch64_simd_df");
|
[AArch64] Restructure arm_neon.h vector types.
2014-11-05 Tejas Belagod <tejas.belagod@arm.com>
* config/aarch64/aarch64-builtins.c
(aarch64_build_scalar_type): Remove.
(aarch64_scalar_builtin_types, aarch64_simd_type,
aarch64_simd_type, aarch64_mangle_builtin_scalar_type,
aarch64_mangle_builtin_vector_type,
aarch64_mangle_builtin_type, aarch64_simd_builtin_std_type,
aarch64_lookup_simd_builtin_type, aarch64_simd_builtin_type,
aarch64_init_simd_builtin_types,
aarch64_init_simd_builtin_scalar_types): New.
(aarch64_init_simd_builtins): Refactor.
(aarch64_init_crc32_builtins): Fixup with qualifier.
* config/aarch64/aarch64-protos.h
(aarch64_mangle_builtin_type): Export.
* config/aarch64/aarch64-simd-builtin-types.def: New.
* config/aarch64/aarch64.c (aarch64_simd_mangle_map): Remove.
(aarch64_mangle_type): Refactor.
* config/aarch64/arm_neon.h: Declare vector types based on
internal types.
* config/aarch64/t-aarch64: Update dependency.
From-SVN: r217114
2014-11-05 09:26:54 +01:00
|
|
|
(*lang_hooks.types.register_builtin_type) (unsigned_intQI_type_node,
|
2012-10-23 19:02:30 +02:00
|
|
|
"__builtin_aarch64_simd_poly8");
|
[AArch64] Restructure arm_neon.h vector types.
2014-11-05 Tejas Belagod <tejas.belagod@arm.com>
* config/aarch64/aarch64-builtins.c
(aarch64_build_scalar_type): Remove.
(aarch64_scalar_builtin_types, aarch64_simd_type,
aarch64_simd_type, aarch64_mangle_builtin_scalar_type,
aarch64_mangle_builtin_vector_type,
aarch64_mangle_builtin_type, aarch64_simd_builtin_std_type,
aarch64_lookup_simd_builtin_type, aarch64_simd_builtin_type,
aarch64_init_simd_builtin_types,
aarch64_init_simd_builtin_scalar_types): New.
(aarch64_init_simd_builtins): Refactor.
(aarch64_init_crc32_builtins): Fixup with qualifier.
* config/aarch64/aarch64-protos.h
(aarch64_mangle_builtin_type): Export.
* config/aarch64/aarch64-simd-builtin-types.def: New.
* config/aarch64/aarch64.c (aarch64_simd_mangle_map): Remove.
(aarch64_mangle_type): Refactor.
* config/aarch64/arm_neon.h: Declare vector types based on
internal types.
* config/aarch64/t-aarch64: Update dependency.
From-SVN: r217114
2014-11-05 09:26:54 +01:00
|
|
|
(*lang_hooks.types.register_builtin_type) (unsigned_intHI_type_node,
|
2012-10-23 19:02:30 +02:00
|
|
|
"__builtin_aarch64_simd_poly16");
|
[AArch64] Restructure arm_neon.h vector types.
2014-11-05 Tejas Belagod <tejas.belagod@arm.com>
* config/aarch64/aarch64-builtins.c
(aarch64_build_scalar_type): Remove.
(aarch64_scalar_builtin_types, aarch64_simd_type,
aarch64_simd_type, aarch64_mangle_builtin_scalar_type,
aarch64_mangle_builtin_vector_type,
aarch64_mangle_builtin_type, aarch64_simd_builtin_std_type,
aarch64_lookup_simd_builtin_type, aarch64_simd_builtin_type,
aarch64_init_simd_builtin_types,
aarch64_init_simd_builtin_scalar_types): New.
(aarch64_init_simd_builtins): Refactor.
(aarch64_init_crc32_builtins): Fixup with qualifier.
* config/aarch64/aarch64-protos.h
(aarch64_mangle_builtin_type): Export.
* config/aarch64/aarch64-simd-builtin-types.def: New.
* config/aarch64/aarch64.c (aarch64_simd_mangle_map): Remove.
(aarch64_mangle_type): Refactor.
* config/aarch64/arm_neon.h: Declare vector types based on
internal types.
* config/aarch64/t-aarch64: Update dependency.
From-SVN: r217114
2014-11-05 09:26:54 +01:00
|
|
|
(*lang_hooks.types.register_builtin_type) (unsigned_intDI_type_node,
|
2013-12-19 16:04:19 +01:00
|
|
|
"__builtin_aarch64_simd_poly64");
|
[AArch64] Restructure arm_neon.h vector types.
2014-11-05 Tejas Belagod <tejas.belagod@arm.com>
* config/aarch64/aarch64-builtins.c
(aarch64_build_scalar_type): Remove.
(aarch64_scalar_builtin_types, aarch64_simd_type,
aarch64_simd_type, aarch64_mangle_builtin_scalar_type,
aarch64_mangle_builtin_vector_type,
aarch64_mangle_builtin_type, aarch64_simd_builtin_std_type,
aarch64_lookup_simd_builtin_type, aarch64_simd_builtin_type,
aarch64_init_simd_builtin_types,
aarch64_init_simd_builtin_scalar_types): New.
(aarch64_init_simd_builtins): Refactor.
(aarch64_init_crc32_builtins): Fixup with qualifier.
* config/aarch64/aarch64-protos.h
(aarch64_mangle_builtin_type): Export.
* config/aarch64/aarch64-simd-builtin-types.def: New.
* config/aarch64/aarch64.c (aarch64_simd_mangle_map): Remove.
(aarch64_mangle_type): Refactor.
* config/aarch64/arm_neon.h: Declare vector types based on
internal types.
* config/aarch64/t-aarch64: Update dependency.
From-SVN: r217114
2014-11-05 09:26:54 +01:00
|
|
|
(*lang_hooks.types.register_builtin_type) (unsigned_intTI_type_node,
|
2013-12-19 16:04:19 +01:00
|
|
|
"__builtin_aarch64_simd_poly128");
|
[AArch64] Restructure arm_neon.h vector types.
2014-11-05 Tejas Belagod <tejas.belagod@arm.com>
* config/aarch64/aarch64-builtins.c
(aarch64_build_scalar_type): Remove.
(aarch64_scalar_builtin_types, aarch64_simd_type,
aarch64_simd_type, aarch64_mangle_builtin_scalar_type,
aarch64_mangle_builtin_vector_type,
aarch64_mangle_builtin_type, aarch64_simd_builtin_std_type,
aarch64_lookup_simd_builtin_type, aarch64_simd_builtin_type,
aarch64_init_simd_builtin_types,
aarch64_init_simd_builtin_scalar_types): New.
(aarch64_init_simd_builtins): Refactor.
(aarch64_init_crc32_builtins): Fixup with qualifier.
* config/aarch64/aarch64-protos.h
(aarch64_mangle_builtin_type): Export.
* config/aarch64/aarch64-simd-builtin-types.def: New.
* config/aarch64/aarch64.c (aarch64_simd_mangle_map): Remove.
(aarch64_mangle_type): Refactor.
* config/aarch64/arm_neon.h: Declare vector types based on
internal types.
* config/aarch64/t-aarch64: Update dependency.
From-SVN: r217114
2014-11-05 09:26:54 +01:00
|
|
|
(*lang_hooks.types.register_builtin_type) (intTI_type_node,
|
2012-10-23 19:02:30 +02:00
|
|
|
"__builtin_aarch64_simd_ti");
|
aarch64: Add bfloat16 vldn/vstn intrinsics
This patch adds the load/store bfloat16 intrinsics to the AArch64 back-end.
ACLE documents are at https://developer.arm.com/docs/101028/latest
ISA documents are at https://developer.arm.com/docs/ddi0596/latest
2020-02-25 Mihail Ionescu <mihail.ionescu@arm.com>
gcc/
* config/aarch64/aarch64-builtins.c (aarch64_scalar_builtin_types):
Add simd_bf.
(aarch64_init_simd_builtin_scalar_types): Register simd_bf.
(VAR15, VAR16): New.
* config/aarch64/iterators.md (VALLDIF): Enable for V4BF and V8BF.
(VD): Enable for V4BF.
(VDC): Likewise.
(VQ): Enable for V8BF.
(VQ2): Likewise.
(VQ_NO2E): Likewise.
(VDBL, Vdbl): Add V4BF.
(V_INT_EQUIV, v_int_equiv): Add V4BF and V8BF.
* config/aarch64/arm_neon.h (bfloat16x4x2_t): New typedef.
(bfloat16x8x2_t): Likewise.
(bfloat16x4x3_t): Likewise.
(bfloat16x8x3_t): Likewise.
(bfloat16x4x4_t): Likewise.
(bfloat16x8x4_t): Likewise.
(vcombine_bf16): New.
(vld1_bf16, vld1_bf16_x2): New.
(vld1_bf16_x3, vld1_bf16_x4): New.
(vld1q_bf16, vld1q_bf16_x2): New.
(vld1q_bf16_x3, vld1q_bf16_x4): New.
(vld1_lane_bf16): New.
(vld1q_lane_bf16): New.
(vld1_dup_bf16): New.
(vld1q_dup_bf16): New.
(vld2_bf16): New.
(vld2q_bf16): New.
(vld2_dup_bf16): New.
(vld2q_dup_bf16): New.
(vld3_bf16): New.
(vld3q_bf16): New.
(vld3_dup_bf16): New.
(vld3q_dup_bf16): New.
(vld4_bf16): New.
(vld4q_bf16): New.
(vld4_dup_bf16): New.
(vld4q_dup_bf16): New.
(vst1_bf16, vst1_bf16_x2): New.
(vst1_bf16_x3, vst1_bf16_x4): New.
(vst1q_bf16, vst1q_bf16_x2): New.
(vst1q_bf16_x3, vst1q_bf16_x4): New.
(vst1_lane_bf16): New.
(vst1q_lane_bf16): New.
(vst2_bf16): New.
(vst2q_bf16): New.
(vst3_bf16): New.
(vst3q_bf16): New.
(vst4_bf16): New.
(vst4q_bf16): New.
gcc/testsuite/
* gcc.target/aarch64/advsimd-intrinsics/bf16_vstn.c: New test.
* gcc.target/aarch64/advsimd-intrinsics/bf16_vldn.c: New test.
2020-02-18 15:29:47 +01:00
|
|
|
(*lang_hooks.types.register_builtin_type) (aarch64_bf16_type_node,
|
|
|
|
"__builtin_aarch64_simd_bf");
|
2013-11-20 10:19:25 +01:00
|
|
|
/* Unsigned integer types for various mode sizes. */
|
[AArch64] Restructure arm_neon.h vector types.
2014-11-05 Tejas Belagod <tejas.belagod@arm.com>
* config/aarch64/aarch64-builtins.c
(aarch64_build_scalar_type): Remove.
(aarch64_scalar_builtin_types, aarch64_simd_type,
aarch64_simd_type, aarch64_mangle_builtin_scalar_type,
aarch64_mangle_builtin_vector_type,
aarch64_mangle_builtin_type, aarch64_simd_builtin_std_type,
aarch64_lookup_simd_builtin_type, aarch64_simd_builtin_type,
aarch64_init_simd_builtin_types,
aarch64_init_simd_builtin_scalar_types): New.
(aarch64_init_simd_builtins): Refactor.
(aarch64_init_crc32_builtins): Fixup with qualifier.
* config/aarch64/aarch64-protos.h
(aarch64_mangle_builtin_type): Export.
* config/aarch64/aarch64-simd-builtin-types.def: New.
* config/aarch64/aarch64.c (aarch64_simd_mangle_map): Remove.
(aarch64_mangle_type): Refactor.
* config/aarch64/arm_neon.h: Declare vector types based on
internal types.
* config/aarch64/t-aarch64: Update dependency.
From-SVN: r217114
2014-11-05 09:26:54 +01:00
|
|
|
(*lang_hooks.types.register_builtin_type) (unsigned_intQI_type_node,
|
2013-11-20 10:19:25 +01:00
|
|
|
"__builtin_aarch64_simd_uqi");
|
[AArch64] Restructure arm_neon.h vector types.
2014-11-05 Tejas Belagod <tejas.belagod@arm.com>
* config/aarch64/aarch64-builtins.c
(aarch64_build_scalar_type): Remove.
(aarch64_scalar_builtin_types, aarch64_simd_type,
aarch64_simd_type, aarch64_mangle_builtin_scalar_type,
aarch64_mangle_builtin_vector_type,
aarch64_mangle_builtin_type, aarch64_simd_builtin_std_type,
aarch64_lookup_simd_builtin_type, aarch64_simd_builtin_type,
aarch64_init_simd_builtin_types,
aarch64_init_simd_builtin_scalar_types): New.
(aarch64_init_simd_builtins): Refactor.
(aarch64_init_crc32_builtins): Fixup with qualifier.
* config/aarch64/aarch64-protos.h
(aarch64_mangle_builtin_type): Export.
* config/aarch64/aarch64-simd-builtin-types.def: New.
* config/aarch64/aarch64.c (aarch64_simd_mangle_map): Remove.
(aarch64_mangle_type): Refactor.
* config/aarch64/arm_neon.h: Declare vector types based on
internal types.
* config/aarch64/t-aarch64: Update dependency.
From-SVN: r217114
2014-11-05 09:26:54 +01:00
|
|
|
(*lang_hooks.types.register_builtin_type) (unsigned_intHI_type_node,
|
2013-11-20 10:19:25 +01:00
|
|
|
"__builtin_aarch64_simd_uhi");
|
[AArch64] Restructure arm_neon.h vector types.
2014-11-05 Tejas Belagod <tejas.belagod@arm.com>
* config/aarch64/aarch64-builtins.c
(aarch64_build_scalar_type): Remove.
(aarch64_scalar_builtin_types, aarch64_simd_type,
aarch64_simd_type, aarch64_mangle_builtin_scalar_type,
aarch64_mangle_builtin_vector_type,
aarch64_mangle_builtin_type, aarch64_simd_builtin_std_type,
aarch64_lookup_simd_builtin_type, aarch64_simd_builtin_type,
aarch64_init_simd_builtin_types,
aarch64_init_simd_builtin_scalar_types): New.
(aarch64_init_simd_builtins): Refactor.
(aarch64_init_crc32_builtins): Fixup with qualifier.
* config/aarch64/aarch64-protos.h
(aarch64_mangle_builtin_type): Export.
* config/aarch64/aarch64-simd-builtin-types.def: New.
* config/aarch64/aarch64.c (aarch64_simd_mangle_map): Remove.
(aarch64_mangle_type): Refactor.
* config/aarch64/arm_neon.h: Declare vector types based on
internal types.
* config/aarch64/t-aarch64: Update dependency.
From-SVN: r217114
2014-11-05 09:26:54 +01:00
|
|
|
(*lang_hooks.types.register_builtin_type) (unsigned_intSI_type_node,
|
2013-11-20 10:19:25 +01:00
|
|
|
"__builtin_aarch64_simd_usi");
|
[AArch64] Restructure arm_neon.h vector types.
2014-11-05 Tejas Belagod <tejas.belagod@arm.com>
* config/aarch64/aarch64-builtins.c
(aarch64_build_scalar_type): Remove.
(aarch64_scalar_builtin_types, aarch64_simd_type,
aarch64_simd_type, aarch64_mangle_builtin_scalar_type,
aarch64_mangle_builtin_vector_type,
aarch64_mangle_builtin_type, aarch64_simd_builtin_std_type,
aarch64_lookup_simd_builtin_type, aarch64_simd_builtin_type,
aarch64_init_simd_builtin_types,
aarch64_init_simd_builtin_scalar_types): New.
(aarch64_init_simd_builtins): Refactor.
(aarch64_init_crc32_builtins): Fixup with qualifier.
* config/aarch64/aarch64-protos.h
(aarch64_mangle_builtin_type): Export.
* config/aarch64/aarch64-simd-builtin-types.def: New.
* config/aarch64/aarch64.c (aarch64_simd_mangle_map): Remove.
(aarch64_mangle_type): Refactor.
* config/aarch64/arm_neon.h: Declare vector types based on
internal types.
* config/aarch64/t-aarch64: Update dependency.
From-SVN: r217114
2014-11-05 09:26:54 +01:00
|
|
|
(*lang_hooks.types.register_builtin_type) (unsigned_intDI_type_node,
|
2013-11-20 10:19:25 +01:00
|
|
|
"__builtin_aarch64_simd_udi");
|
[AArch64] Restructure arm_neon.h vector types.
2014-11-05 Tejas Belagod <tejas.belagod@arm.com>
* config/aarch64/aarch64-builtins.c
(aarch64_build_scalar_type): Remove.
(aarch64_scalar_builtin_types, aarch64_simd_type,
aarch64_simd_type, aarch64_mangle_builtin_scalar_type,
aarch64_mangle_builtin_vector_type,
aarch64_mangle_builtin_type, aarch64_simd_builtin_std_type,
aarch64_lookup_simd_builtin_type, aarch64_simd_builtin_type,
aarch64_init_simd_builtin_types,
aarch64_init_simd_builtin_scalar_types): New.
(aarch64_init_simd_builtins): Refactor.
(aarch64_init_crc32_builtins): Fixup with qualifier.
* config/aarch64/aarch64-protos.h
(aarch64_mangle_builtin_type): Export.
* config/aarch64/aarch64-simd-builtin-types.def: New.
* config/aarch64/aarch64.c (aarch64_simd_mangle_map): Remove.
(aarch64_mangle_type): Refactor.
* config/aarch64/arm_neon.h: Declare vector types based on
internal types.
* config/aarch64/t-aarch64: Update dependency.
From-SVN: r217114
2014-11-05 09:26:54 +01:00
|
|
|
}
|
|
|
|
|
2021-05-21 15:46:00 +02:00
|
|
|
/* Return a set of FLAG_* flags derived from FLAGS
|
|
|
|
that describe what a function with result MODE could do,
|
2020-07-31 10:52:25 +02:00
|
|
|
taking the command-line flags into account. */
|
|
|
|
static unsigned int
|
2021-05-21 15:46:00 +02:00
|
|
|
aarch64_call_properties (unsigned int flags, machine_mode mode)
|
2020-07-31 10:52:25 +02:00
|
|
|
{
|
2021-05-21 15:46:00 +02:00
|
|
|
if (!(flags & FLAG_AUTO_FP) && FLOAT_MODE_P (mode))
|
2020-08-04 18:25:29 +02:00
|
|
|
flags |= FLAG_FP;
|
2020-07-31 10:52:25 +02:00
|
|
|
|
|
|
|
/* -fno-trapping-math means that we can assume any FP exceptions
|
|
|
|
are not user-visible. */
|
|
|
|
if (!flag_trapping_math)
|
|
|
|
flags &= ~FLAG_RAISE_FP_EXCEPTIONS;
|
|
|
|
|
|
|
|
return flags;
|
|
|
|
}
|
|
|
|
|
2021-05-21 15:46:00 +02:00
|
|
|
/* Return true if calls to a function with flags F and mode MODE
|
|
|
|
could modify some form of global state. */
|
2020-07-31 10:52:25 +02:00
|
|
|
static bool
|
2021-05-21 15:46:00 +02:00
|
|
|
aarch64_modifies_global_state_p (unsigned int f, machine_mode mode)
|
2020-07-31 10:52:25 +02:00
|
|
|
{
|
2021-05-21 15:46:00 +02:00
|
|
|
unsigned int flags = aarch64_call_properties (f, mode);
|
2020-07-31 10:52:25 +02:00
|
|
|
|
|
|
|
if (flags & FLAG_RAISE_FP_EXCEPTIONS)
|
|
|
|
return true;
|
|
|
|
|
|
|
|
if (flags & FLAG_PREFETCH_MEMORY)
|
|
|
|
return true;
|
|
|
|
|
|
|
|
return flags & FLAG_WRITE_MEMORY;
|
|
|
|
}
|
|
|
|
|
2021-05-21 15:46:00 +02:00
|
|
|
/* Return true if calls to a function with flags F and mode MODE
|
|
|
|
could read some form of global state. */
|
2020-07-31 10:52:25 +02:00
|
|
|
static bool
|
2021-05-21 15:46:00 +02:00
|
|
|
aarch64_reads_global_state_p (unsigned int f, machine_mode mode)
|
2020-07-31 10:52:25 +02:00
|
|
|
{
|
2021-05-21 15:46:00 +02:00
|
|
|
unsigned int flags = aarch64_call_properties (f, mode);
|
2020-07-31 10:52:25 +02:00
|
|
|
|
|
|
|
if (flags & FLAG_READ_FPCR)
|
|
|
|
return true;
|
|
|
|
|
|
|
|
return flags & FLAG_READ_MEMORY;
|
|
|
|
}
|
|
|
|
|
2021-05-21 15:46:00 +02:00
|
|
|
/* Return true if calls to a function with flags F and mode MODE
|
|
|
|
could raise a signal. */
|
2020-07-31 10:52:25 +02:00
|
|
|
static bool
|
2021-05-21 15:46:00 +02:00
|
|
|
aarch64_could_trap_p (unsigned int f, machine_mode mode)
|
2020-07-31 10:52:25 +02:00
|
|
|
{
|
2021-05-21 15:46:00 +02:00
|
|
|
unsigned int flags = aarch64_call_properties (f, mode);
|
2020-07-31 10:52:25 +02:00
|
|
|
|
|
|
|
if (flags & FLAG_RAISE_FP_EXCEPTIONS)
|
|
|
|
return true;
|
|
|
|
|
|
|
|
if (flags & (FLAG_READ_MEMORY | FLAG_WRITE_MEMORY))
|
|
|
|
return true;
|
|
|
|
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Add attribute NAME to ATTRS. */
|
|
|
|
static tree
|
|
|
|
aarch64_add_attribute (const char *name, tree attrs)
|
|
|
|
{
|
|
|
|
return tree_cons (get_identifier (name), NULL_TREE, attrs);
|
|
|
|
}
|
|
|
|
|
2021-05-21 15:46:00 +02:00
|
|
|
/* Return the appropriate attributes for a function that has
|
|
|
|
flags F and mode MODE. */
|
2020-07-31 10:52:25 +02:00
|
|
|
static tree
|
2021-05-21 15:46:00 +02:00
|
|
|
aarch64_get_attributes (unsigned int f, machine_mode mode)
|
2020-07-31 10:52:25 +02:00
|
|
|
{
|
|
|
|
tree attrs = NULL_TREE;
|
|
|
|
|
2021-05-21 15:46:00 +02:00
|
|
|
if (!aarch64_modifies_global_state_p (f, mode))
|
2020-07-31 10:52:25 +02:00
|
|
|
{
|
2021-05-21 15:46:00 +02:00
|
|
|
if (aarch64_reads_global_state_p (f, mode))
|
2020-07-31 10:52:25 +02:00
|
|
|
attrs = aarch64_add_attribute ("pure", attrs);
|
|
|
|
else
|
|
|
|
attrs = aarch64_add_attribute ("const", attrs);
|
|
|
|
}
|
|
|
|
|
2021-05-21 15:46:00 +02:00
|
|
|
if (!flag_non_call_exceptions || !aarch64_could_trap_p (f, mode))
|
2020-07-31 10:52:25 +02:00
|
|
|
attrs = aarch64_add_attribute ("nothrow", attrs);
|
|
|
|
|
|
|
|
return aarch64_add_attribute ("leaf", attrs);
|
|
|
|
}
|
|
|
|
|
2015-08-04 12:39:42 +02:00
|
|
|
static bool aarch64_simd_builtins_initialized_p = false;
|
|
|
|
|
aarch64-builtins.c (enum aarch64_type_qualifiers): Add qualifier_lane_pair_index.
gcc/ChangeLog:
2019-01-10 Tamar Christina <tamar.christina@arm.com>
* config/aarch64/aarch64-builtins.c (enum aarch64_type_qualifiers): Add qualifier_lane_pair_index.
(emit-rtl.h): Include.
(TYPES_QUADOP_LANE_PAIR): New.
(aarch64_simd_expand_args): Use it.
(aarch64_simd_expand_builtin): Likewise.
(AARCH64_SIMD_FCMLA_LANEQ_BUILTINS, aarch64_fcmla_laneq_builtin_datum): New.
(FCMLA_LANEQ_BUILTIN, AARCH64_SIMD_FCMLA_LANEQ_BUILTIN_BASE,
AARCH64_SIMD_FCMLA_LANEQ_BUILTINS, aarch64_fcmla_lane_builtin_data,
aarch64_init_fcmla_laneq_builtins, aarch64_expand_fcmla_builtin): New.
(aarch64_init_builtins): Add aarch64_init_fcmla_laneq_builtins.
(aarch64_expand_buildin): Add AARCH64_SIMD_BUILTIN_FCMLA_LANEQ0_V2SF,
AARCH64_SIMD_BUILTIN_FCMLA_LANEQ90_V2SF, AARCH64_SIMD_BUILTIN_FCMLA_LANEQ180_V2SF,
AARCH64_SIMD_BUILTIN_FCMLA_LANEQ2700_V2SF, AARCH64_SIMD_BUILTIN_FCMLA_LANEQ0_V4HF,
AARCH64_SIMD_BUILTIN_FCMLA_LANEQ90_V4HF, AARCH64_SIMD_BUILTIN_FCMLA_LANEQ180_V4HF,
AARCH64_SIMD_BUILTIN_FCMLA_LANEQ270_V4HF.
* config/aarch64/iterators.md (FCMLA_maybe_lane): New.
* config/aarch64/aarch64-c.c (aarch64_update_cpp_builtins): Add __ARM_FEATURE_COMPLEX.
* config/aarch64/aarch64-simd-builtins.def (fcadd90, fcadd270, fcmla0, fcmla90,
fcmla180, fcmla270, fcmla_lane0, fcmla_lane90, fcmla_lane180, fcmla_lane270,
fcmla_laneq0, fcmla_laneq90, fcmla_laneq180, fcmla_laneq270,
fcmlaq_lane0, fcmlaq_lane90, fcmlaq_lane180, fcmlaq_lane270): New.
* config/aarch64/aarch64-simd.md (aarch64_fcmla_lane<rot><mode>,
aarch64_fcmla_laneq<rot>v4hf, aarch64_fcmlaq_lane<rot><mode>,aarch64_fcadd<rot><mode>,
aarch64_fcmla<rot><mode>): New.
* config/aarch64/arm_neon.h:
(vcadd_rot90_f16): New.
(vcaddq_rot90_f16): New.
(vcadd_rot270_f16): New.
(vcaddq_rot270_f16): New.
(vcmla_f16): New.
(vcmlaq_f16): New.
(vcmla_lane_f16): New.
(vcmla_laneq_f16): New.
(vcmlaq_lane_f16): New.
(vcmlaq_rot90_lane_f16): New.
(vcmla_rot90_laneq_f16): New.
(vcmla_rot90_lane_f16): New.
(vcmlaq_rot90_f16): New.
(vcmla_rot90_f16): New.
(vcmlaq_laneq_f16): New.
(vcmla_rot180_laneq_f16): New.
(vcmla_rot180_lane_f16): New.
(vcmlaq_rot180_f16): New.
(vcmla_rot180_f16): New.
(vcmlaq_rot90_laneq_f16): New.
(vcmlaq_rot270_laneq_f16): New.
(vcmlaq_rot270_lane_f16): New.
(vcmla_rot270_laneq_f16): New.
(vcmlaq_rot270_f16): New.
(vcmla_rot270_f16): New.
(vcmlaq_rot180_laneq_f16): New.
(vcmlaq_rot180_lane_f16): New.
(vcmla_rot270_lane_f16): New.
(vcadd_rot90_f32): New.
(vcaddq_rot90_f32): New.
(vcaddq_rot90_f64): New.
(vcadd_rot270_f32): New.
(vcaddq_rot270_f32): New.
(vcaddq_rot270_f64): New.
(vcmla_f32): New.
(vcmlaq_f32): New.
(vcmlaq_f64): New.
(vcmla_lane_f32): New.
(vcmla_laneq_f32): New.
(vcmlaq_lane_f32): New.
(vcmlaq_laneq_f32): New.
(vcmla_rot90_f32): New.
(vcmlaq_rot90_f32): New.
(vcmlaq_rot90_f64): New.
(vcmla_rot90_lane_f32): New.
(vcmla_rot90_laneq_f32): New.
(vcmlaq_rot90_lane_f32): New.
(vcmlaq_rot90_laneq_f32): New.
(vcmla_rot180_f32): New.
(vcmlaq_rot180_f32): New.
(vcmlaq_rot180_f64): New.
(vcmla_rot180_lane_f32): New.
(vcmla_rot180_laneq_f32): New.
(vcmlaq_rot180_lane_f32): New.
(vcmlaq_rot180_laneq_f32): New.
(vcmla_rot270_f32): New.
(vcmlaq_rot270_f32): New.
(vcmlaq_rot270_f64): New.
(vcmla_rot270_lane_f32): New.
(vcmla_rot270_laneq_f32): New.
(vcmlaq_rot270_lane_f32): New.
(vcmlaq_rot270_laneq_f32): New.
* config/aarch64/aarch64.h (TARGET_COMPLEX): New.
* config/aarch64/iterators.md (UNSPEC_FCADD90, UNSPEC_FCADD270,
UNSPEC_FCMLA, UNSPEC_FCMLA90, UNSPEC_FCMLA180, UNSPEC_FCMLA270): New.
(FCADD, FCMLA): New.
(rot): New.
* config/arm/types.md (neon_fcadd, neon_fcmla): New.
gcc/testsuite/ChangeLog:
2019-01-10 Tamar Christina <tamar.christina@arm.com>
* gcc.target/aarch64/advsimd-intrinsics/vector-complex.c: New test.
* gcc.target/aarch64/advsimd-intrinsics/vector-complex_f16.c: New test.
From-SVN: r267795
2019-01-10 04:30:59 +01:00
|
|
|
/* Due to the architecture not providing lane variant of the lane instructions
|
|
|
|
for fcmla we can't use the standard simd builtin expansion code, but we
|
|
|
|
still want the majority of the validation that would normally be done. */
|
|
|
|
|
|
|
|
void
|
|
|
|
aarch64_init_fcmla_laneq_builtins (void)
|
|
|
|
{
|
|
|
|
unsigned int i = 0;
|
|
|
|
|
|
|
|
for (i = 0; i < ARRAY_SIZE (aarch64_fcmla_lane_builtin_data); ++i)
|
|
|
|
{
|
|
|
|
aarch64_fcmla_laneq_builtin_datum* d
|
|
|
|
= &aarch64_fcmla_lane_builtin_data[i];
|
|
|
|
tree argtype = aarch64_lookup_simd_builtin_type (d->mode, qualifier_none);
|
|
|
|
machine_mode quadmode = GET_MODE_2XWIDER_MODE (d->mode).require ();
|
|
|
|
tree quadtype
|
|
|
|
= aarch64_lookup_simd_builtin_type (quadmode, qualifier_none);
|
|
|
|
tree lanetype
|
|
|
|
= aarch64_simd_builtin_std_type (SImode, qualifier_lane_pair_index);
|
|
|
|
tree ftype = build_function_type_list (argtype, argtype, argtype,
|
|
|
|
quadtype, lanetype, NULL_TREE);
|
2021-05-21 15:46:00 +02:00
|
|
|
tree attrs = aarch64_get_attributes (FLAG_FP, d->mode);
|
|
|
|
tree fndecl
|
|
|
|
= aarch64_general_add_builtin (d->name, ftype, d->fcode, attrs);
|
aarch64-builtins.c (enum aarch64_type_qualifiers): Add qualifier_lane_pair_index.
gcc/ChangeLog:
2019-01-10 Tamar Christina <tamar.christina@arm.com>
* config/aarch64/aarch64-builtins.c (enum aarch64_type_qualifiers): Add qualifier_lane_pair_index.
(emit-rtl.h): Include.
(TYPES_QUADOP_LANE_PAIR): New.
(aarch64_simd_expand_args): Use it.
(aarch64_simd_expand_builtin): Likewise.
(AARCH64_SIMD_FCMLA_LANEQ_BUILTINS, aarch64_fcmla_laneq_builtin_datum): New.
(FCMLA_LANEQ_BUILTIN, AARCH64_SIMD_FCMLA_LANEQ_BUILTIN_BASE,
AARCH64_SIMD_FCMLA_LANEQ_BUILTINS, aarch64_fcmla_lane_builtin_data,
aarch64_init_fcmla_laneq_builtins, aarch64_expand_fcmla_builtin): New.
(aarch64_init_builtins): Add aarch64_init_fcmla_laneq_builtins.
(aarch64_expand_buildin): Add AARCH64_SIMD_BUILTIN_FCMLA_LANEQ0_V2SF,
AARCH64_SIMD_BUILTIN_FCMLA_LANEQ90_V2SF, AARCH64_SIMD_BUILTIN_FCMLA_LANEQ180_V2SF,
AARCH64_SIMD_BUILTIN_FCMLA_LANEQ2700_V2SF, AARCH64_SIMD_BUILTIN_FCMLA_LANEQ0_V4HF,
AARCH64_SIMD_BUILTIN_FCMLA_LANEQ90_V4HF, AARCH64_SIMD_BUILTIN_FCMLA_LANEQ180_V4HF,
AARCH64_SIMD_BUILTIN_FCMLA_LANEQ270_V4HF.
* config/aarch64/iterators.md (FCMLA_maybe_lane): New.
* config/aarch64/aarch64-c.c (aarch64_update_cpp_builtins): Add __ARM_FEATURE_COMPLEX.
* config/aarch64/aarch64-simd-builtins.def (fcadd90, fcadd270, fcmla0, fcmla90,
fcmla180, fcmla270, fcmla_lane0, fcmla_lane90, fcmla_lane180, fcmla_lane270,
fcmla_laneq0, fcmla_laneq90, fcmla_laneq180, fcmla_laneq270,
fcmlaq_lane0, fcmlaq_lane90, fcmlaq_lane180, fcmlaq_lane270): New.
* config/aarch64/aarch64-simd.md (aarch64_fcmla_lane<rot><mode>,
aarch64_fcmla_laneq<rot>v4hf, aarch64_fcmlaq_lane<rot><mode>,aarch64_fcadd<rot><mode>,
aarch64_fcmla<rot><mode>): New.
* config/aarch64/arm_neon.h:
(vcadd_rot90_f16): New.
(vcaddq_rot90_f16): New.
(vcadd_rot270_f16): New.
(vcaddq_rot270_f16): New.
(vcmla_f16): New.
(vcmlaq_f16): New.
(vcmla_lane_f16): New.
(vcmla_laneq_f16): New.
(vcmlaq_lane_f16): New.
(vcmlaq_rot90_lane_f16): New.
(vcmla_rot90_laneq_f16): New.
(vcmla_rot90_lane_f16): New.
(vcmlaq_rot90_f16): New.
(vcmla_rot90_f16): New.
(vcmlaq_laneq_f16): New.
(vcmla_rot180_laneq_f16): New.
(vcmla_rot180_lane_f16): New.
(vcmlaq_rot180_f16): New.
(vcmla_rot180_f16): New.
(vcmlaq_rot90_laneq_f16): New.
(vcmlaq_rot270_laneq_f16): New.
(vcmlaq_rot270_lane_f16): New.
(vcmla_rot270_laneq_f16): New.
(vcmlaq_rot270_f16): New.
(vcmla_rot270_f16): New.
(vcmlaq_rot180_laneq_f16): New.
(vcmlaq_rot180_lane_f16): New.
(vcmla_rot270_lane_f16): New.
(vcadd_rot90_f32): New.
(vcaddq_rot90_f32): New.
(vcaddq_rot90_f64): New.
(vcadd_rot270_f32): New.
(vcaddq_rot270_f32): New.
(vcaddq_rot270_f64): New.
(vcmla_f32): New.
(vcmlaq_f32): New.
(vcmlaq_f64): New.
(vcmla_lane_f32): New.
(vcmla_laneq_f32): New.
(vcmlaq_lane_f32): New.
(vcmlaq_laneq_f32): New.
(vcmla_rot90_f32): New.
(vcmlaq_rot90_f32): New.
(vcmlaq_rot90_f64): New.
(vcmla_rot90_lane_f32): New.
(vcmla_rot90_laneq_f32): New.
(vcmlaq_rot90_lane_f32): New.
(vcmlaq_rot90_laneq_f32): New.
(vcmla_rot180_f32): New.
(vcmlaq_rot180_f32): New.
(vcmlaq_rot180_f64): New.
(vcmla_rot180_lane_f32): New.
(vcmla_rot180_laneq_f32): New.
(vcmlaq_rot180_lane_f32): New.
(vcmlaq_rot180_laneq_f32): New.
(vcmla_rot270_f32): New.
(vcmlaq_rot270_f32): New.
(vcmlaq_rot270_f64): New.
(vcmla_rot270_lane_f32): New.
(vcmla_rot270_laneq_f32): New.
(vcmlaq_rot270_lane_f32): New.
(vcmlaq_rot270_laneq_f32): New.
* config/aarch64/aarch64.h (TARGET_COMPLEX): New.
* config/aarch64/iterators.md (UNSPEC_FCADD90, UNSPEC_FCADD270,
UNSPEC_FCMLA, UNSPEC_FCMLA90, UNSPEC_FCMLA180, UNSPEC_FCMLA270): New.
(FCADD, FCMLA): New.
(rot): New.
* config/arm/types.md (neon_fcadd, neon_fcmla): New.
gcc/testsuite/ChangeLog:
2019-01-10 Tamar Christina <tamar.christina@arm.com>
* gcc.target/aarch64/advsimd-intrinsics/vector-complex.c: New test.
* gcc.target/aarch64/advsimd-intrinsics/vector-complex_f16.c: New test.
From-SVN: r267795
2019-01-10 04:30:59 +01:00
|
|
|
|
|
|
|
aarch64_builtin_decls[d->fcode] = fndecl;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2015-08-04 12:39:42 +02:00
|
|
|
void
|
2021-09-10 17:48:02 +02:00
|
|
|
aarch64_init_simd_builtin_functions (bool called_from_pragma)
|
[AArch64] Restructure arm_neon.h vector types.
2014-11-05 Tejas Belagod <tejas.belagod@arm.com>
* config/aarch64/aarch64-builtins.c
(aarch64_build_scalar_type): Remove.
(aarch64_scalar_builtin_types, aarch64_simd_type,
aarch64_simd_type, aarch64_mangle_builtin_scalar_type,
aarch64_mangle_builtin_vector_type,
aarch64_mangle_builtin_type, aarch64_simd_builtin_std_type,
aarch64_lookup_simd_builtin_type, aarch64_simd_builtin_type,
aarch64_init_simd_builtin_types,
aarch64_init_simd_builtin_scalar_types): New.
(aarch64_init_simd_builtins): Refactor.
(aarch64_init_crc32_builtins): Fixup with qualifier.
* config/aarch64/aarch64-protos.h
(aarch64_mangle_builtin_type): Export.
* config/aarch64/aarch64-simd-builtin-types.def: New.
* config/aarch64/aarch64.c (aarch64_simd_mangle_map): Remove.
(aarch64_mangle_type): Refactor.
* config/aarch64/arm_neon.h: Declare vector types based on
internal types.
* config/aarch64/t-aarch64: Update dependency.
From-SVN: r217114
2014-11-05 09:26:54 +01:00
|
|
|
{
|
[AArch64] Fix ICE on non-constant indices to __builtin_aarch64_im_lane_boundsi
gcc/:
* config/aarch64/aarch64-builtins.c (aarch64_types_binopv_qualifiers,
TYPES_BINOPV): Delete.
(enum aarch64_builtins): Add AARCH64_BUILTIN_SIMD_LANE_CHECK and
AARCH64_SIMD_PATTERN_START.
(aarch64_init_simd_builtins): Register
__builtin_aarch64_im_lane_boundsi; use AARCH64_SIMD_PATTERN_START.
(aarch64_simd_expand_builtin): Handle AARCH64_BUILTIN_LANE_CHECK; use
AARCH64_SIMD_PATTERN_START.
* config/aarch64/aarch64-simd.md (aarch64_im_lane_boundsi): Delete.
* config/aarch64/aarch64-simd-builtins.def (im_lane_bound): Delete.
* config/aarch64/arm_neon.h (__AARCH64_LANE_CHECK): New.
(__aarch64_vget_lane_f64, __aarch64_vget_lane_s64,
__aarch64_vget_lane_u64, __aarch64_vset_lane_any, vdupd_lane_f64,
vdupd_lane_s64, vdupd_lane_u64, vext_f32, vext_f64, vext_p8, vext_p16,
vext_s8, vext_s16, vext_s32, vext_s64, vext_u8, vext_u16, vext_u32,
vext_u64, vextq_f32, vextq_f64, vextq_p8, vextq_p16, vextq_s8,
vextq_s16, vextq_s32, vextq_s64, vextq_u8, vextq_u16, vextq_u32,
vextq_u64, vmulq_lane_f64): Use __AARCH64_LANE_CHECK.
gcc/testsuite/:
* gcc.target/aarch64/simd/vset_lane_s16_const_1.c: New test.
From-SVN: r218532
2014-12-09 20:52:22 +01:00
|
|
|
unsigned int i, fcode = AARCH64_SIMD_PATTERN_START;
|
[AArch64] Restructure arm_neon.h vector types.
2014-11-05 Tejas Belagod <tejas.belagod@arm.com>
* config/aarch64/aarch64-builtins.c
(aarch64_build_scalar_type): Remove.
(aarch64_scalar_builtin_types, aarch64_simd_type,
aarch64_simd_type, aarch64_mangle_builtin_scalar_type,
aarch64_mangle_builtin_vector_type,
aarch64_mangle_builtin_type, aarch64_simd_builtin_std_type,
aarch64_lookup_simd_builtin_type, aarch64_simd_builtin_type,
aarch64_init_simd_builtin_types,
aarch64_init_simd_builtin_scalar_types): New.
(aarch64_init_simd_builtins): Refactor.
(aarch64_init_crc32_builtins): Fixup with qualifier.
* config/aarch64/aarch64-protos.h
(aarch64_mangle_builtin_type): Export.
* config/aarch64/aarch64-simd-builtin-types.def: New.
* config/aarch64/aarch64.c (aarch64_simd_mangle_map): Remove.
(aarch64_mangle_type): Refactor.
* config/aarch64/arm_neon.h: Declare vector types based on
internal types.
* config/aarch64/t-aarch64: Update dependency.
From-SVN: r217114
2014-11-05 09:26:54 +01:00
|
|
|
|
2021-09-10 17:48:02 +02:00
|
|
|
if (!called_from_pragma)
|
|
|
|
{
|
|
|
|
tree lane_check_fpr = build_function_type_list (void_type_node,
|
|
|
|
size_type_node,
|
|
|
|
size_type_node,
|
|
|
|
intSI_type_node,
|
|
|
|
NULL);
|
|
|
|
aarch64_builtin_decls[AARCH64_SIMD_BUILTIN_LANE_CHECK]
|
|
|
|
= aarch64_general_add_builtin ("__builtin_aarch64_im_lane_boundsi",
|
|
|
|
lane_check_fpr,
|
|
|
|
AARCH64_SIMD_BUILTIN_LANE_CHECK);
|
|
|
|
}
|
[AArch64] Fix ICE on non-constant indices to __builtin_aarch64_im_lane_boundsi
gcc/:
* config/aarch64/aarch64-builtins.c (aarch64_types_binopv_qualifiers,
TYPES_BINOPV): Delete.
(enum aarch64_builtins): Add AARCH64_BUILTIN_SIMD_LANE_CHECK and
AARCH64_SIMD_PATTERN_START.
(aarch64_init_simd_builtins): Register
__builtin_aarch64_im_lane_boundsi; use AARCH64_SIMD_PATTERN_START.
(aarch64_simd_expand_builtin): Handle AARCH64_BUILTIN_LANE_CHECK; use
AARCH64_SIMD_PATTERN_START.
* config/aarch64/aarch64-simd.md (aarch64_im_lane_boundsi): Delete.
* config/aarch64/aarch64-simd-builtins.def (im_lane_bound): Delete.
* config/aarch64/arm_neon.h (__AARCH64_LANE_CHECK): New.
(__aarch64_vget_lane_f64, __aarch64_vget_lane_s64,
__aarch64_vget_lane_u64, __aarch64_vset_lane_any, vdupd_lane_f64,
vdupd_lane_s64, vdupd_lane_u64, vext_f32, vext_f64, vext_p8, vext_p16,
vext_s8, vext_s16, vext_s32, vext_s64, vext_u8, vext_u16, vext_u32,
vext_u64, vextq_f32, vextq_f64, vextq_p8, vextq_p16, vextq_s8,
vextq_s16, vextq_s32, vextq_s64, vextq_u8, vextq_u16, vextq_u32,
vextq_u64, vmulq_lane_f64): Use __AARCH64_LANE_CHECK.
gcc/testsuite/:
* gcc.target/aarch64/simd/vset_lane_s16_const_1.c: New test.
From-SVN: r218532
2014-12-09 20:52:22 +01:00
|
|
|
|
2012-11-20 13:10:37 +01:00
|
|
|
for (i = 0; i < ARRAY_SIZE (aarch64_simd_builtin_data); i++, fcode++)
|
2012-10-23 19:02:30 +02:00
|
|
|
{
|
2013-11-20 10:19:25 +01:00
|
|
|
bool print_type_signature_p = false;
|
2017-08-31 12:54:38 +02:00
|
|
|
char type_signature[SIMD_MAX_BUILTIN_ARGS + 1] = { 0 };
|
2012-10-23 19:02:30 +02:00
|
|
|
aarch64_simd_builtin_datum *d = &aarch64_simd_builtin_data[i];
|
2012-11-20 13:10:37 +01:00
|
|
|
char namebuf[60];
|
|
|
|
tree ftype = NULL;
|
2012-11-26 18:48:13 +01:00
|
|
|
tree fndecl = NULL;
|
2012-11-20 13:10:37 +01:00
|
|
|
|
|
|
|
d->fcode = fcode;
|
2012-10-23 19:02:30 +02:00
|
|
|
|
2013-11-20 10:19:25 +01:00
|
|
|
/* We must track two variables here. op_num is
|
|
|
|
the operand number as in the RTL pattern. This is
|
|
|
|
required to access the mode (e.g. V4SF mode) of the
|
|
|
|
argument, from which the base type can be derived.
|
|
|
|
arg_num is an index in to the qualifiers data, which
|
|
|
|
gives qualifiers to the type (e.g. const unsigned).
|
|
|
|
The reason these two variables may differ by one is the
|
|
|
|
void return type. While all return types take the 0th entry
|
|
|
|
in the qualifiers array, there is no operand for them in the
|
|
|
|
RTL pattern. */
|
|
|
|
int op_num = insn_data[d->code].n_operands - 1;
|
|
|
|
int arg_num = d->qualifiers[0] & qualifier_void
|
|
|
|
? op_num + 1
|
|
|
|
: op_num;
|
|
|
|
tree return_type = void_type_node, args = void_list_node;
|
|
|
|
tree eltype;
|
|
|
|
|
2021-09-10 17:48:02 +02:00
|
|
|
int struct_mode_args = 0;
|
|
|
|
for (int j = op_num; j >= 0; j--)
|
|
|
|
{
|
|
|
|
machine_mode op_mode = insn_data[d->code].operand[j].mode;
|
|
|
|
if (aarch64_advsimd_struct_mode_p (op_mode))
|
|
|
|
struct_mode_args++;
|
|
|
|
}
|
|
|
|
|
|
|
|
if ((called_from_pragma && struct_mode_args == 0)
|
|
|
|
|| (!called_from_pragma && struct_mode_args > 0))
|
|
|
|
continue;
|
|
|
|
|
2013-11-20 10:19:25 +01:00
|
|
|
/* Build a function type directly from the insn_data for this
|
|
|
|
builtin. The build_function_type () function takes care of
|
|
|
|
removing duplicates for us. */
|
|
|
|
for (; op_num >= 0; arg_num--, op_num--)
|
2012-10-23 19:02:30 +02:00
|
|
|
{
|
decl.c, [...]: Remove redundant enum from machine_mode.
gcc/ada/
* gcc-interface/decl.c, gcc-interface/gigi.h, gcc-interface/misc.c,
gcc-interface/trans.c, gcc-interface/utils.c, gcc-interface/utils2.c:
Remove redundant enum from machine_mode.
gcc/c-family/
* c-common.c, c-common.h, c-cppbuiltin.c, c-lex.c: Remove redundant
enum from machine_mode.
gcc/c/
* c-decl.c, c-tree.h, c-typeck.c: Remove redundant enum from
machine_mode.
gcc/cp/
* constexpr.c: Remove redundant enum from machine_mode.
gcc/fortran/
* trans-types.c, trans-types.h: Remove redundant enum from
machine_mode.
gcc/go/
* go-lang.c: Remove redundant enum from machine_mode.
gcc/java/
* builtins.c, java-tree.h, typeck.c: Remove redundant enum from
machine_mode.
gcc/lto/
* lto-lang.c: Remove redundant enum from machine_mode.
gcc/
* addresses.h, alias.c, asan.c, auto-inc-dec.c, bt-load.c, builtins.c,
builtins.h, caller-save.c, calls.c, calls.h, cfgexpand.c, cfgloop.h,
cfgrtl.c, combine.c, compare-elim.c, config/aarch64/aarch64-builtins.c,
config/aarch64/aarch64-protos.h, config/aarch64/aarch64-simd.md,
config/aarch64/aarch64.c, config/aarch64/aarch64.h,
config/aarch64/aarch64.md, config/alpha/alpha-protos.h,
config/alpha/alpha.c, config/arc/arc-protos.h, config/arc/arc.c,
config/arc/arc.h, config/arc/predicates.md,
config/arm/aarch-common-protos.h, config/arm/aarch-common.c,
config/arm/arm-protos.h, config/arm/arm.c, config/arm/arm.h,
config/arm/arm.md, config/arm/neon.md, config/arm/thumb2.md,
config/avr/avr-log.c, config/avr/avr-protos.h, config/avr/avr.c,
config/avr/avr.md, config/bfin/bfin-protos.h, config/bfin/bfin.c,
config/c6x/c6x-protos.h, config/c6x/c6x.c, config/c6x/c6x.md,
config/cr16/cr16-protos.h, config/cr16/cr16.c,
config/cris/cris-protos.h, config/cris/cris.c, config/cris/cris.md,
config/darwin-protos.h, config/darwin.c,
config/epiphany/epiphany-protos.h, config/epiphany/epiphany.c,
config/epiphany/epiphany.md, config/fr30/fr30.c,
config/frv/frv-protos.h, config/frv/frv.c, config/frv/predicates.md,
config/h8300/h8300-protos.h, config/h8300/h8300.c,
config/i386/i386-builtin-types.awk, config/i386/i386-protos.h,
config/i386/i386.c, config/i386/i386.md, config/i386/predicates.md,
config/i386/sse.md, config/i386/sync.md, config/ia64/ia64-protos.h,
config/ia64/ia64.c, config/iq2000/iq2000-protos.h,
config/iq2000/iq2000.c, config/iq2000/iq2000.md,
config/lm32/lm32-protos.h, config/lm32/lm32.c,
config/m32c/m32c-protos.h, config/m32c/m32c.c,
config/m32r/m32r-protos.h, config/m32r/m32r.c,
config/m68k/m68k-protos.h, config/m68k/m68k.c,
config/mcore/mcore-protos.h, config/mcore/mcore.c,
config/mcore/mcore.md, config/mep/mep-protos.h, config/mep/mep.c,
config/microblaze/microblaze-protos.h, config/microblaze/microblaze.c,
config/mips/mips-protos.h, config/mips/mips.c,
config/mmix/mmix-protos.h, config/mmix/mmix.c,
config/mn10300/mn10300-protos.h, config/mn10300/mn10300.c,
config/moxie/moxie.c, config/msp430/msp430-protos.h,
config/msp430/msp430.c, config/nds32/nds32-cost.c,
config/nds32/nds32-intrinsic.c, config/nds32/nds32-md-auxiliary.c,
config/nds32/nds32-protos.h, config/nds32/nds32.c,
config/nios2/nios2-protos.h, config/nios2/nios2.c,
config/pa/pa-protos.h, config/pa/pa.c, config/pdp11/pdp11-protos.h,
config/pdp11/pdp11.c, config/rl78/rl78-protos.h, config/rl78/rl78.c,
config/rs6000/altivec.md, config/rs6000/rs6000-c.c,
config/rs6000/rs6000-protos.h, config/rs6000/rs6000.c,
config/rs6000/rs6000.h, config/rx/rx-protos.h, config/rx/rx.c,
config/s390/predicates.md, config/s390/s390-protos.h,
config/s390/s390.c, config/s390/s390.h, config/s390/s390.md,
config/sh/predicates.md, config/sh/sh-protos.h, config/sh/sh.c,
config/sh/sh.md, config/sparc/predicates.md,
config/sparc/sparc-protos.h, config/sparc/sparc.c,
config/sparc/sparc.md, config/spu/spu-protos.h, config/spu/spu.c,
config/stormy16/stormy16-protos.h, config/stormy16/stormy16.c,
config/tilegx/tilegx-protos.h, config/tilegx/tilegx.c,
config/tilegx/tilegx.md, config/tilepro/tilepro-protos.h,
config/tilepro/tilepro.c, config/v850/v850-protos.h,
config/v850/v850.c, config/v850/v850.md, config/vax/vax-protos.h,
config/vax/vax.c, config/vms/vms-c.c, config/xtensa/xtensa-protos.h,
config/xtensa/xtensa.c, coverage.c, cprop.c, cse.c, cselib.c, cselib.h,
dbxout.c, ddg.c, df-problems.c, dfp.c, dfp.h, doc/md.texi,
doc/rtl.texi, doc/tm.texi, doc/tm.texi.in, dojump.c, dse.c,
dwarf2cfi.c, dwarf2out.c, dwarf2out.h, emit-rtl.c, emit-rtl.h,
except.c, explow.c, expmed.c, expmed.h, expr.c, expr.h, final.c,
fixed-value.c, fixed-value.h, fold-const.c, function.c, function.h,
fwprop.c, gcse.c, gengenrtl.c, genmodes.c, genopinit.c, genoutput.c,
genpreds.c, genrecog.c, gensupport.c, gimple-ssa-strength-reduction.c,
graphite-clast-to-gimple.c, haifa-sched.c, hooks.c, hooks.h, ifcvt.c,
internal-fn.c, ira-build.c, ira-color.c, ira-conflicts.c, ira-costs.c,
ira-emit.c, ira-int.h, ira-lives.c, ira.c, ira.h, jump.c, langhooks.h,
libfuncs.h, lists.c, loop-doloop.c, loop-invariant.c, loop-iv.c,
loop-unroll.c, lower-subreg.c, lower-subreg.h, lra-assigns.c,
lra-constraints.c, lra-eliminations.c, lra-int.h, lra-lives.c,
lra-spills.c, lra.c, lra.h, machmode.h, omp-low.c, optabs.c, optabs.h,
output.h, postreload.c, print-tree.c, read-rtl.c, real.c, real.h,
recog.c, recog.h, ree.c, reg-stack.c, regcprop.c, reginfo.c,
regrename.c, regs.h, reload.c, reload.h, reload1.c, rtl.c, rtl.h,
rtlanal.c, rtlhash.c, rtlhooks-def.h, rtlhooks.c, sched-deps.c,
sel-sched-dump.c, sel-sched-ir.c, sel-sched-ir.h, sel-sched.c,
simplify-rtx.c, stmt.c, stor-layout.c, stor-layout.h, target.def,
targhooks.c, targhooks.h, tree-affine.c, tree-call-cdce.c,
tree-complex.c, tree-data-ref.c, tree-dfa.c, tree-if-conv.c,
tree-inline.c, tree-outof-ssa.c, tree-scalar-evolution.c,
tree-ssa-address.c, tree-ssa-ccp.c, tree-ssa-loop-ivopts.c,
tree-ssa-loop-ivopts.h, tree-ssa-loop-manip.c,
tree-ssa-loop-prefetch.c, tree-ssa-math-opts.c, tree-ssa-reassoc.c,
tree-ssa-sccvn.c, tree-streamer-in.c, tree-switch-conversion.c,
tree-vect-data-refs.c, tree-vect-generic.c, tree-vect-loop.c,
tree-vect-patterns.c, tree-vect-slp.c, tree-vect-stmts.c,
tree-vrp.c, tree.c, tree.h, tsan.c, ubsan.c, valtrack.c,
var-tracking.c, varasm.c: Remove redundant enum from
machine_mode.
gcc/
* gengtype.c (main): Treat machine_mode as a scalar typedef.
* genmodes.c (emit_insn_modes_h): Hide inline functions if
USED_FOR_TARGET.
From-SVN: r216834
2014-10-29 13:02:45 +01:00
|
|
|
machine_mode op_mode = insn_data[d->code].operand[op_num].mode;
|
2013-11-20 10:19:25 +01:00
|
|
|
enum aarch64_type_qualifiers qualifiers = d->qualifiers[arg_num];
|
2012-10-23 19:02:30 +02:00
|
|
|
|
2013-11-20 10:19:25 +01:00
|
|
|
if (qualifiers & qualifier_unsigned)
|
|
|
|
{
|
2016-09-13 18:32:23 +02:00
|
|
|
type_signature[op_num] = 'u';
|
2013-11-20 10:19:25 +01:00
|
|
|
print_type_signature_p = true;
|
|
|
|
}
|
2013-11-26 11:00:49 +01:00
|
|
|
else if (qualifiers & qualifier_poly)
|
|
|
|
{
|
2016-09-13 18:32:23 +02:00
|
|
|
type_signature[op_num] = 'p';
|
2013-11-26 11:00:49 +01:00
|
|
|
print_type_signature_p = true;
|
|
|
|
}
|
2013-11-20 10:19:25 +01:00
|
|
|
else
|
2016-09-13 18:32:23 +02:00
|
|
|
type_signature[op_num] = 's';
|
2013-11-20 10:19:25 +01:00
|
|
|
|
|
|
|
/* Skip an internal operand for vget_{low, high}. */
|
|
|
|
if (qualifiers & qualifier_internal)
|
|
|
|
continue;
|
|
|
|
|
|
|
|
/* Some builtins have different user-facing types
|
|
|
|
for certain arguments, encoded in d->mode. */
|
|
|
|
if (qualifiers & qualifier_map_mode)
|
2014-08-05 11:49:05 +02:00
|
|
|
op_mode = d->mode;
|
2013-11-20 10:19:25 +01:00
|
|
|
|
|
|
|
/* For pointers, we want a pointer to the basic type
|
|
|
|
of the vector. */
|
|
|
|
if (qualifiers & qualifier_pointer && VECTOR_MODE_P (op_mode))
|
|
|
|
op_mode = GET_MODE_INNER (op_mode);
|
|
|
|
|
[AArch64] Restructure arm_neon.h vector types.
2014-11-05 Tejas Belagod <tejas.belagod@arm.com>
* config/aarch64/aarch64-builtins.c
(aarch64_build_scalar_type): Remove.
(aarch64_scalar_builtin_types, aarch64_simd_type,
aarch64_simd_type, aarch64_mangle_builtin_scalar_type,
aarch64_mangle_builtin_vector_type,
aarch64_mangle_builtin_type, aarch64_simd_builtin_std_type,
aarch64_lookup_simd_builtin_type, aarch64_simd_builtin_type,
aarch64_init_simd_builtin_types,
aarch64_init_simd_builtin_scalar_types): New.
(aarch64_init_simd_builtins): Refactor.
(aarch64_init_crc32_builtins): Fixup with qualifier.
* config/aarch64/aarch64-protos.h
(aarch64_mangle_builtin_type): Export.
* config/aarch64/aarch64-simd-builtin-types.def: New.
* config/aarch64/aarch64.c (aarch64_simd_mangle_map): Remove.
(aarch64_mangle_type): Refactor.
* config/aarch64/arm_neon.h: Declare vector types based on
internal types.
* config/aarch64/t-aarch64: Update dependency.
From-SVN: r217114
2014-11-05 09:26:54 +01:00
|
|
|
eltype = aarch64_simd_builtin_type
|
|
|
|
(op_mode,
|
|
|
|
(qualifiers & qualifier_unsigned) != 0,
|
|
|
|
(qualifiers & qualifier_poly) != 0);
|
|
|
|
gcc_assert (eltype != NULL);
|
2013-11-20 10:19:25 +01:00
|
|
|
|
|
|
|
/* Add qualifiers. */
|
|
|
|
if (qualifiers & qualifier_const)
|
|
|
|
eltype = build_qualified_type (eltype, TYPE_QUAL_CONST);
|
|
|
|
|
|
|
|
if (qualifiers & qualifier_pointer)
|
|
|
|
eltype = build_pointer_type (eltype);
|
|
|
|
|
|
|
|
/* If we have reached arg_num == 0, we are at a non-void
|
|
|
|
return type. Otherwise, we are still processing
|
|
|
|
arguments. */
|
|
|
|
if (arg_num == 0)
|
|
|
|
return_type = eltype;
|
|
|
|
else
|
|
|
|
args = tree_cons (NULL_TREE, eltype, args);
|
|
|
|
}
|
2012-11-20 13:10:37 +01:00
|
|
|
|
2013-11-20 10:19:25 +01:00
|
|
|
ftype = build_function_type (return_type, args);
|
2012-10-23 19:02:30 +02:00
|
|
|
|
2012-11-20 13:10:37 +01:00
|
|
|
gcc_assert (ftype != NULL);
|
2012-10-23 19:02:30 +02:00
|
|
|
|
2013-11-20 10:19:25 +01:00
|
|
|
if (print_type_signature_p)
|
2014-08-05 11:49:05 +02:00
|
|
|
snprintf (namebuf, sizeof (namebuf), "__builtin_aarch64_%s_%s",
|
|
|
|
d->name, type_signature);
|
2013-11-20 10:19:25 +01:00
|
|
|
else
|
2014-08-05 11:49:05 +02:00
|
|
|
snprintf (namebuf, sizeof (namebuf), "__builtin_aarch64_%s",
|
|
|
|
d->name);
|
2012-10-23 19:02:30 +02:00
|
|
|
|
2021-05-21 15:46:00 +02:00
|
|
|
tree attrs = aarch64_get_attributes (d->flags, d->mode);
|
2020-07-31 10:52:25 +02:00
|
|
|
|
2021-08-09 16:26:48 +02:00
|
|
|
if (called_from_pragma)
|
|
|
|
{
|
|
|
|
unsigned int raw_code
|
|
|
|
= (fcode << AARCH64_BUILTIN_SHIFT) | AARCH64_BUILTIN_GENERAL;
|
|
|
|
fndecl = simulate_builtin_function_decl (input_location, namebuf,
|
|
|
|
ftype, raw_code, NULL,
|
|
|
|
attrs);
|
|
|
|
}
|
|
|
|
else
|
|
|
|
fndecl = aarch64_general_add_builtin (namebuf, ftype, fcode, attrs);
|
|
|
|
|
2012-11-26 18:48:13 +01:00
|
|
|
aarch64_builtin_decls[fcode] = fndecl;
|
2012-10-23 19:02:30 +02:00
|
|
|
}
|
2021-09-10 17:48:02 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
/* Register the tuple type that contains NUM_VECTORS of the AdvSIMD type
|
|
|
|
indexed by TYPE_INDEX. */
|
|
|
|
static void
|
|
|
|
register_tuple_type (unsigned int num_vectors, unsigned int type_index)
|
|
|
|
{
|
|
|
|
aarch64_simd_type_info *type = &aarch64_simd_types[type_index];
|
|
|
|
|
|
|
|
/* Synthesize the name of the user-visible vector tuple type. */
|
|
|
|
const char *vector_type_name = type->name;
|
|
|
|
char tuple_type_name[sizeof ("bfloat16x4x2_t")];
|
|
|
|
snprintf (tuple_type_name, sizeof (tuple_type_name), "%.*sx%d_t",
|
|
|
|
(int) strlen (vector_type_name) - 4, vector_type_name + 2,
|
|
|
|
num_vectors);
|
|
|
|
tuple_type_name[0] = TOLOWER (tuple_type_name[0]);
|
|
|
|
|
|
|
|
tree vector_type = type->itype;
|
|
|
|
tree array_type = build_array_type_nelts (vector_type, num_vectors);
|
2021-08-09 16:26:48 +02:00
|
|
|
if (type->mode == DImode)
|
|
|
|
{
|
|
|
|
if (num_vectors == 2)
|
|
|
|
SET_TYPE_MODE (array_type, V2x1DImode);
|
|
|
|
else if (num_vectors == 3)
|
|
|
|
SET_TYPE_MODE (array_type, V3x1DImode);
|
|
|
|
else if (num_vectors == 4)
|
|
|
|
SET_TYPE_MODE (array_type, V4x1DImode);
|
|
|
|
}
|
|
|
|
|
2021-09-10 17:48:02 +02:00
|
|
|
unsigned int alignment
|
2022-04-05 18:31:35 +02:00
|
|
|
= known_eq (GET_MODE_SIZE (type->mode), 16) ? 128 : 64;
|
|
|
|
machine_mode tuple_mode = TYPE_MODE_RAW (array_type);
|
|
|
|
gcc_assert (VECTOR_MODE_P (tuple_mode)
|
|
|
|
&& TYPE_MODE (array_type) == tuple_mode
|
2021-09-10 17:48:02 +02:00
|
|
|
&& TYPE_ALIGN (array_type) == alignment);
|
|
|
|
|
|
|
|
tree field = build_decl (input_location, FIELD_DECL,
|
|
|
|
get_identifier ("val"), array_type);
|
|
|
|
|
|
|
|
tree t = lang_hooks.types.simulate_record_decl (input_location,
|
|
|
|
tuple_type_name,
|
|
|
|
make_array_slice (&field,
|
|
|
|
1));
|
|
|
|
gcc_assert (TYPE_MODE_RAW (t) == TYPE_MODE (t)
|
2022-04-05 18:31:35 +02:00
|
|
|
&& (flag_pack_struct
|
|
|
|
|| maximum_field_alignment
|
|
|
|
|| (TYPE_MODE_RAW (t) == tuple_mode
|
|
|
|
&& TYPE_ALIGN (t) == alignment)));
|
|
|
|
|
|
|
|
aarch64_simd_tuple_modes[type_index][num_vectors - 2] = tuple_mode;
|
|
|
|
aarch64_simd_tuple_types[type_index][num_vectors - 2] = t;
|
2021-09-10 17:48:02 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
static bool
|
|
|
|
aarch64_scalar_builtin_type_p (aarch64_simd_type t)
|
|
|
|
{
|
|
|
|
return (t == Poly8_t || t == Poly16_t || t == Poly64_t || t == Poly128_t);
|
|
|
|
}
|
|
|
|
|
2022-04-05 18:31:35 +02:00
|
|
|
/* Enable AARCH64_FL_* flags EXTRA_FLAGS on top of the base Advanced SIMD
|
|
|
|
set. */
|
|
|
|
aarch64_simd_switcher::aarch64_simd_switcher (unsigned int extra_flags)
|
|
|
|
: m_old_isa_flags (aarch64_isa_flags),
|
|
|
|
m_old_general_regs_only (TARGET_GENERAL_REGS_ONLY)
|
|
|
|
{
|
|
|
|
/* Changing the ISA flags should be enough here. We shouldn't need to
|
|
|
|
pay the compile-time cost of a full target switch. */
|
|
|
|
aarch64_isa_flags = AARCH64_FL_FP | AARCH64_FL_SIMD | extra_flags;
|
|
|
|
global_options.x_target_flags &= ~MASK_GENERAL_REGS_ONLY;
|
|
|
|
}
|
|
|
|
|
|
|
|
aarch64_simd_switcher::~aarch64_simd_switcher ()
|
|
|
|
{
|
|
|
|
if (m_old_general_regs_only)
|
|
|
|
global_options.x_target_flags |= MASK_GENERAL_REGS_ONLY;
|
|
|
|
aarch64_isa_flags = m_old_isa_flags;
|
|
|
|
}
|
|
|
|
|
2021-09-10 17:48:02 +02:00
|
|
|
/* Implement #pragma GCC aarch64 "arm_neon.h". */
|
|
|
|
void
|
|
|
|
handle_arm_neon_h (void)
|
|
|
|
{
|
2022-04-05 18:31:35 +02:00
|
|
|
aarch64_simd_switcher simd;
|
|
|
|
|
2021-09-10 17:48:02 +02:00
|
|
|
/* Register the AdvSIMD vector tuple types. */
|
|
|
|
for (unsigned int i = 0; i < ARM_NEON_H_TYPES_LAST; i++)
|
|
|
|
for (unsigned int count = 2; count <= 4; ++count)
|
|
|
|
if (!aarch64_scalar_builtin_type_p (aarch64_simd_types[i].type))
|
|
|
|
register_tuple_type (count, i);
|
|
|
|
|
|
|
|
aarch64_init_simd_builtin_functions (true);
|
|
|
|
}
|
|
|
|
|
|
|
|
void
|
|
|
|
aarch64_init_simd_builtins (void)
|
|
|
|
{
|
|
|
|
if (aarch64_simd_builtins_initialized_p)
|
|
|
|
return;
|
|
|
|
|
|
|
|
aarch64_simd_builtins_initialized_p = true;
|
|
|
|
|
|
|
|
aarch64_init_simd_builtin_types ();
|
|
|
|
|
|
|
|
/* Strong-typing hasn't been implemented for all AdvSIMD builtin intrinsics.
|
|
|
|
Therefore we need to preserve the old __builtin scalar types. It can be
|
|
|
|
removed once all the intrinsics become strongly typed using the qualifier
|
|
|
|
system. */
|
|
|
|
aarch64_init_simd_builtin_scalar_types ();
|
|
|
|
|
|
|
|
aarch64_init_simd_builtin_functions (false);
|
|
|
|
if (in_lto_p)
|
|
|
|
handle_arm_neon_h ();
|
2019-01-10 23:28:00 +01:00
|
|
|
|
2021-09-10 17:48:02 +02:00
|
|
|
/* Initialize the remaining fcmla_laneq intrinsics. */
|
|
|
|
aarch64_init_fcmla_laneq_builtins ();
|
2012-10-23 19:02:30 +02:00
|
|
|
}
|
|
|
|
|
2014-06-11 11:17:18 +02:00
|
|
|
static void
|
|
|
|
aarch64_init_crc32_builtins ()
|
|
|
|
{
|
[AArch64] Restructure arm_neon.h vector types.
2014-11-05 Tejas Belagod <tejas.belagod@arm.com>
* config/aarch64/aarch64-builtins.c
(aarch64_build_scalar_type): Remove.
(aarch64_scalar_builtin_types, aarch64_simd_type,
aarch64_simd_type, aarch64_mangle_builtin_scalar_type,
aarch64_mangle_builtin_vector_type,
aarch64_mangle_builtin_type, aarch64_simd_builtin_std_type,
aarch64_lookup_simd_builtin_type, aarch64_simd_builtin_type,
aarch64_init_simd_builtin_types,
aarch64_init_simd_builtin_scalar_types): New.
(aarch64_init_simd_builtins): Refactor.
(aarch64_init_crc32_builtins): Fixup with qualifier.
* config/aarch64/aarch64-protos.h
(aarch64_mangle_builtin_type): Export.
* config/aarch64/aarch64-simd-builtin-types.def: New.
* config/aarch64/aarch64.c (aarch64_simd_mangle_map): Remove.
(aarch64_mangle_type): Refactor.
* config/aarch64/arm_neon.h: Declare vector types based on
internal types.
* config/aarch64/t-aarch64: Update dependency.
From-SVN: r217114
2014-11-05 09:26:54 +01:00
|
|
|
tree usi_type = aarch64_simd_builtin_std_type (SImode, qualifier_unsigned);
|
2014-06-11 11:17:18 +02:00
|
|
|
unsigned int i = 0;
|
|
|
|
|
|
|
|
for (i = 0; i < ARRAY_SIZE (aarch64_crc_builtin_data); ++i)
|
|
|
|
{
|
|
|
|
aarch64_crc_builtin_datum* d = &aarch64_crc_builtin_data[i];
|
[AArch64] Restructure arm_neon.h vector types.
2014-11-05 Tejas Belagod <tejas.belagod@arm.com>
* config/aarch64/aarch64-builtins.c
(aarch64_build_scalar_type): Remove.
(aarch64_scalar_builtin_types, aarch64_simd_type,
aarch64_simd_type, aarch64_mangle_builtin_scalar_type,
aarch64_mangle_builtin_vector_type,
aarch64_mangle_builtin_type, aarch64_simd_builtin_std_type,
aarch64_lookup_simd_builtin_type, aarch64_simd_builtin_type,
aarch64_init_simd_builtin_types,
aarch64_init_simd_builtin_scalar_types): New.
(aarch64_init_simd_builtins): Refactor.
(aarch64_init_crc32_builtins): Fixup with qualifier.
* config/aarch64/aarch64-protos.h
(aarch64_mangle_builtin_type): Export.
* config/aarch64/aarch64-simd-builtin-types.def: New.
* config/aarch64/aarch64.c (aarch64_simd_mangle_map): Remove.
(aarch64_mangle_type): Refactor.
* config/aarch64/arm_neon.h: Declare vector types based on
internal types.
* config/aarch64/t-aarch64: Update dependency.
From-SVN: r217114
2014-11-05 09:26:54 +01:00
|
|
|
tree argtype = aarch64_simd_builtin_std_type (d->mode,
|
|
|
|
qualifier_unsigned);
|
2014-06-11 11:17:18 +02:00
|
|
|
tree ftype = build_function_type_list (usi_type, usi_type, argtype, NULL_TREE);
|
2021-05-21 15:46:00 +02:00
|
|
|
tree attrs = aarch64_get_attributes (FLAG_NONE, d->mode);
|
|
|
|
tree fndecl
|
|
|
|
= aarch64_general_add_builtin (d->name, ftype, d->fcode, attrs);
|
2014-06-11 11:17:18 +02:00
|
|
|
|
|
|
|
aarch64_builtin_decls[d->fcode] = fndecl;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2015-11-06 18:10:17 +01:00
|
|
|
/* Add builtins for reciprocal square root. */
|
|
|
|
|
|
|
|
void
|
|
|
|
aarch64_init_builtin_rsqrt (void)
|
|
|
|
{
|
|
|
|
tree fndecl = NULL;
|
|
|
|
tree ftype = NULL;
|
|
|
|
|
|
|
|
tree V2SF_type_node = build_vector_type (float_type_node, 2);
|
|
|
|
tree V2DF_type_node = build_vector_type (double_type_node, 2);
|
|
|
|
tree V4SF_type_node = build_vector_type (float_type_node, 4);
|
|
|
|
|
|
|
|
struct builtin_decls_data
|
|
|
|
{
|
|
|
|
tree type_node;
|
|
|
|
const char *builtin_name;
|
|
|
|
int function_code;
|
|
|
|
};
|
|
|
|
|
|
|
|
builtin_decls_data bdda[] =
|
|
|
|
{
|
|
|
|
{ double_type_node, "__builtin_aarch64_rsqrt_df", AARCH64_BUILTIN_RSQRT_DF },
|
|
|
|
{ float_type_node, "__builtin_aarch64_rsqrt_sf", AARCH64_BUILTIN_RSQRT_SF },
|
|
|
|
{ V2DF_type_node, "__builtin_aarch64_rsqrt_v2df", AARCH64_BUILTIN_RSQRT_V2DF },
|
|
|
|
{ V2SF_type_node, "__builtin_aarch64_rsqrt_v2sf", AARCH64_BUILTIN_RSQRT_V2SF },
|
|
|
|
{ V4SF_type_node, "__builtin_aarch64_rsqrt_v4sf", AARCH64_BUILTIN_RSQRT_V4SF }
|
|
|
|
};
|
|
|
|
|
|
|
|
builtin_decls_data *bdd = bdda;
|
|
|
|
builtin_decls_data *bdd_end = bdd + (sizeof (bdda) / sizeof (builtin_decls_data));
|
|
|
|
|
|
|
|
for (; bdd < bdd_end; bdd++)
|
|
|
|
{
|
|
|
|
ftype = build_function_type_list (bdd->type_node, bdd->type_node, NULL_TREE);
|
2021-05-21 15:46:00 +02:00
|
|
|
tree attrs = aarch64_get_attributes (FLAG_FP, TYPE_MODE (bdd->type_node));
|
[AArch64] Split built-in function codes into major and minor codes
It was easier to add the SVE ACLE support without enumerating every
function at build time. This in turn meant that it was easier if the
SVE builtins occupied a distinct numberspace from the existing AArch64
ones, which *are* enumerated at build time. This patch therefore
divides the built-in functions codes into "major" and "minor" codes.
At present the major code is just "general", but the SVE patch will add
"SVE" as well.
Also, it was convenient to put the SVE ACLE support in its own file,
so the patch makes aarch64.c provide the frontline target hooks directly,
forwarding to the other files for the real work.
The reason for organising the files this way is that aarch64.c needs
to define the target hook macros whatever happens, and having aarch64.c
macros forward to aarch64-builtins.c functions and aarch64-bulitins.c
functions forward to the SVE file seemed a bit indirect. Doing things
the way the patch does them puts aarch64-builtins.c and the SVE code on
more of an equal footing.
The aarch64_(general_)gimple_fold_builtin change is mostly just
reindentation.
2019-09-27 Richard Sandiford <richard.sandiford@arm.com>
gcc/
* config/aarch64/aarch64-protos.h (aarch64_builtin_class): New enum.
(AARCH64_BUILTIN_SHIFT, AARCH64_BUILTIN_CLASS): New constants.
(aarch64_gimple_fold_builtin, aarch64_mangle_builtin_type)
(aarch64_fold_builtin, aarch64_init_builtins, aarch64_expand_builtin):
(aarch64_builtin_decl, aarch64_builtin_rsqrt): Delete.
(aarch64_general_mangle_builtin_type, aarch64_general_init_builtins):
(aarch64_general_fold_builtin, aarch64_general_gimple_fold_builtin):
(aarch64_general_expand_builtin, aarch64_general_builtin_decl):
(aarch64_general_builtin_rsqrt): Declare.
* config/aarch64/aarch64-builtins.c (aarch64_general_add_builtin):
New function.
(aarch64_mangle_builtin_type): Rename to...
(aarch64_general_mangle_builtin_type): ...this.
(aarch64_init_fcmla_laneq_builtins, aarch64_init_simd_builtins)
(aarch64_init_crc32_builtins, aarch64_init_builtin_rsqrt)
(aarch64_init_pauth_hint_builtins, aarch64_init_tme_builtins): Use
aarch64_general_add_builtin instead of add_builtin_function.
(aarch64_init_builtins): Rename to...
(aarch64_general_init_builtins): ...this. Use
aarch64_general_add_builtin instead of add_builtin_function.
(aarch64_builtin_decl): Rename to...
(aarch64_general_builtin_decl): ...this and remove the unused
arguments.
(aarch64_expand_builtin): Rename to...
(aarch64_general_expand_builtin): ...this and remove the unused
arguments.
(aarch64_builtin_rsqrt): Rename to...
(aarch64_general_builtin_rsqrt): ...this.
(aarch64_fold_builtin): Rename to...
(aarch64_general_fold_builtin): ...this. Take the function subcode
and return type as arguments. Remove the "ignored" argument.
(aarch64_gimple_fold_builtin): Rename to...
(aarch64_general_gimple_fold_builtin): ...this. Take the function
subcode and gcall as arguments, and return the new function call.
* config/aarch64/aarch64.c (aarch64_init_builtins)
(aarch64_fold_builtin, aarch64_gimple_fold_builtin)
(aarch64_expand_builtin, aarch64_builtin_decl): New functions.
(aarch64_builtin_reciprocal): Call aarch64_general_builtin_rsqrt
instead of aarch64_builtin_rsqrt.
(aarch64_mangle_type): Call aarch64_general_mangle_builtin_type
instead of aarch64_mangle_builtin_type.
From-SVN: r276177
2019-09-27 10:47:21 +02:00
|
|
|
fndecl = aarch64_general_add_builtin (bdd->builtin_name,
|
2021-05-21 15:46:00 +02:00
|
|
|
ftype, bdd->function_code, attrs);
|
2015-11-06 18:10:17 +01:00
|
|
|
aarch64_builtin_decls[bdd->function_code] = fndecl;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2016-08-05 18:08:24 +02:00
|
|
|
/* Initialize the backend types that support the user-visible __fp16
|
|
|
|
type, also initialize a pointer to that type, to be used when
|
|
|
|
forming HFAs. */
|
|
|
|
|
|
|
|
static void
|
|
|
|
aarch64_init_fp16_types (void)
|
|
|
|
{
|
|
|
|
aarch64_fp16_type_node = make_node (REAL_TYPE);
|
|
|
|
TYPE_PRECISION (aarch64_fp16_type_node) = 16;
|
|
|
|
layout_type (aarch64_fp16_type_node);
|
|
|
|
|
|
|
|
(*lang_hooks.types.register_builtin_type) (aarch64_fp16_type_node, "__fp16");
|
|
|
|
aarch64_fp16_ptr_type_node = build_pointer_type (aarch64_fp16_type_node);
|
|
|
|
}
|
|
|
|
|
2020-01-10 20:23:41 +01:00
|
|
|
/* Initialize the backend REAL_TYPE type supporting bfloat types. */
|
|
|
|
static void
|
|
|
|
aarch64_init_bf16_types (void)
|
|
|
|
{
|
|
|
|
aarch64_bf16_type_node = make_node (REAL_TYPE);
|
|
|
|
TYPE_PRECISION (aarch64_bf16_type_node) = 16;
|
|
|
|
SET_TYPE_MODE (aarch64_bf16_type_node, BFmode);
|
|
|
|
layout_type (aarch64_bf16_type_node);
|
|
|
|
|
|
|
|
lang_hooks.types.register_builtin_type (aarch64_bf16_type_node, "__bf16");
|
|
|
|
aarch64_bf16_ptr_type_node = build_pointer_type (aarch64_bf16_type_node);
|
|
|
|
}
|
|
|
|
|
2017-01-20 01:10:11 +01:00
|
|
|
/* Pointer authentication builtins that will become NOP on legacy platform.
|
|
|
|
Currently, these builtins are for internal use only (libgcc EH unwinder). */
|
|
|
|
|
|
|
|
void
|
|
|
|
aarch64_init_pauth_hint_builtins (void)
|
|
|
|
{
|
|
|
|
/* Pointer Authentication builtins. */
|
|
|
|
tree ftype_pointer_auth
|
|
|
|
= build_function_type_list (ptr_type_node, ptr_type_node,
|
|
|
|
unsigned_intDI_type_node, NULL_TREE);
|
|
|
|
tree ftype_pointer_strip
|
|
|
|
= build_function_type_list (ptr_type_node, ptr_type_node, NULL_TREE);
|
|
|
|
|
|
|
|
aarch64_builtin_decls[AARCH64_PAUTH_BUILTIN_AUTIA1716]
|
[AArch64] Split built-in function codes into major and minor codes
It was easier to add the SVE ACLE support without enumerating every
function at build time. This in turn meant that it was easier if the
SVE builtins occupied a distinct numberspace from the existing AArch64
ones, which *are* enumerated at build time. This patch therefore
divides the built-in functions codes into "major" and "minor" codes.
At present the major code is just "general", but the SVE patch will add
"SVE" as well.
Also, it was convenient to put the SVE ACLE support in its own file,
so the patch makes aarch64.c provide the frontline target hooks directly,
forwarding to the other files for the real work.
The reason for organising the files this way is that aarch64.c needs
to define the target hook macros whatever happens, and having aarch64.c
macros forward to aarch64-builtins.c functions and aarch64-bulitins.c
functions forward to the SVE file seemed a bit indirect. Doing things
the way the patch does them puts aarch64-builtins.c and the SVE code on
more of an equal footing.
The aarch64_(general_)gimple_fold_builtin change is mostly just
reindentation.
2019-09-27 Richard Sandiford <richard.sandiford@arm.com>
gcc/
* config/aarch64/aarch64-protos.h (aarch64_builtin_class): New enum.
(AARCH64_BUILTIN_SHIFT, AARCH64_BUILTIN_CLASS): New constants.
(aarch64_gimple_fold_builtin, aarch64_mangle_builtin_type)
(aarch64_fold_builtin, aarch64_init_builtins, aarch64_expand_builtin):
(aarch64_builtin_decl, aarch64_builtin_rsqrt): Delete.
(aarch64_general_mangle_builtin_type, aarch64_general_init_builtins):
(aarch64_general_fold_builtin, aarch64_general_gimple_fold_builtin):
(aarch64_general_expand_builtin, aarch64_general_builtin_decl):
(aarch64_general_builtin_rsqrt): Declare.
* config/aarch64/aarch64-builtins.c (aarch64_general_add_builtin):
New function.
(aarch64_mangle_builtin_type): Rename to...
(aarch64_general_mangle_builtin_type): ...this.
(aarch64_init_fcmla_laneq_builtins, aarch64_init_simd_builtins)
(aarch64_init_crc32_builtins, aarch64_init_builtin_rsqrt)
(aarch64_init_pauth_hint_builtins, aarch64_init_tme_builtins): Use
aarch64_general_add_builtin instead of add_builtin_function.
(aarch64_init_builtins): Rename to...
(aarch64_general_init_builtins): ...this. Use
aarch64_general_add_builtin instead of add_builtin_function.
(aarch64_builtin_decl): Rename to...
(aarch64_general_builtin_decl): ...this and remove the unused
arguments.
(aarch64_expand_builtin): Rename to...
(aarch64_general_expand_builtin): ...this and remove the unused
arguments.
(aarch64_builtin_rsqrt): Rename to...
(aarch64_general_builtin_rsqrt): ...this.
(aarch64_fold_builtin): Rename to...
(aarch64_general_fold_builtin): ...this. Take the function subcode
and return type as arguments. Remove the "ignored" argument.
(aarch64_gimple_fold_builtin): Rename to...
(aarch64_general_gimple_fold_builtin): ...this. Take the function
subcode and gcall as arguments, and return the new function call.
* config/aarch64/aarch64.c (aarch64_init_builtins)
(aarch64_fold_builtin, aarch64_gimple_fold_builtin)
(aarch64_expand_builtin, aarch64_builtin_decl): New functions.
(aarch64_builtin_reciprocal): Call aarch64_general_builtin_rsqrt
instead of aarch64_builtin_rsqrt.
(aarch64_mangle_type): Call aarch64_general_mangle_builtin_type
instead of aarch64_mangle_builtin_type.
From-SVN: r276177
2019-09-27 10:47:21 +02:00
|
|
|
= aarch64_general_add_builtin ("__builtin_aarch64_autia1716",
|
|
|
|
ftype_pointer_auth,
|
|
|
|
AARCH64_PAUTH_BUILTIN_AUTIA1716);
|
2017-01-20 01:10:11 +01:00
|
|
|
aarch64_builtin_decls[AARCH64_PAUTH_BUILTIN_PACIA1716]
|
[AArch64] Split built-in function codes into major and minor codes
It was easier to add the SVE ACLE support without enumerating every
function at build time. This in turn meant that it was easier if the
SVE builtins occupied a distinct numberspace from the existing AArch64
ones, which *are* enumerated at build time. This patch therefore
divides the built-in functions codes into "major" and "minor" codes.
At present the major code is just "general", but the SVE patch will add
"SVE" as well.
Also, it was convenient to put the SVE ACLE support in its own file,
so the patch makes aarch64.c provide the frontline target hooks directly,
forwarding to the other files for the real work.
The reason for organising the files this way is that aarch64.c needs
to define the target hook macros whatever happens, and having aarch64.c
macros forward to aarch64-builtins.c functions and aarch64-bulitins.c
functions forward to the SVE file seemed a bit indirect. Doing things
the way the patch does them puts aarch64-builtins.c and the SVE code on
more of an equal footing.
The aarch64_(general_)gimple_fold_builtin change is mostly just
reindentation.
2019-09-27 Richard Sandiford <richard.sandiford@arm.com>
gcc/
* config/aarch64/aarch64-protos.h (aarch64_builtin_class): New enum.
(AARCH64_BUILTIN_SHIFT, AARCH64_BUILTIN_CLASS): New constants.
(aarch64_gimple_fold_builtin, aarch64_mangle_builtin_type)
(aarch64_fold_builtin, aarch64_init_builtins, aarch64_expand_builtin):
(aarch64_builtin_decl, aarch64_builtin_rsqrt): Delete.
(aarch64_general_mangle_builtin_type, aarch64_general_init_builtins):
(aarch64_general_fold_builtin, aarch64_general_gimple_fold_builtin):
(aarch64_general_expand_builtin, aarch64_general_builtin_decl):
(aarch64_general_builtin_rsqrt): Declare.
* config/aarch64/aarch64-builtins.c (aarch64_general_add_builtin):
New function.
(aarch64_mangle_builtin_type): Rename to...
(aarch64_general_mangle_builtin_type): ...this.
(aarch64_init_fcmla_laneq_builtins, aarch64_init_simd_builtins)
(aarch64_init_crc32_builtins, aarch64_init_builtin_rsqrt)
(aarch64_init_pauth_hint_builtins, aarch64_init_tme_builtins): Use
aarch64_general_add_builtin instead of add_builtin_function.
(aarch64_init_builtins): Rename to...
(aarch64_general_init_builtins): ...this. Use
aarch64_general_add_builtin instead of add_builtin_function.
(aarch64_builtin_decl): Rename to...
(aarch64_general_builtin_decl): ...this and remove the unused
arguments.
(aarch64_expand_builtin): Rename to...
(aarch64_general_expand_builtin): ...this and remove the unused
arguments.
(aarch64_builtin_rsqrt): Rename to...
(aarch64_general_builtin_rsqrt): ...this.
(aarch64_fold_builtin): Rename to...
(aarch64_general_fold_builtin): ...this. Take the function subcode
and return type as arguments. Remove the "ignored" argument.
(aarch64_gimple_fold_builtin): Rename to...
(aarch64_general_gimple_fold_builtin): ...this. Take the function
subcode and gcall as arguments, and return the new function call.
* config/aarch64/aarch64.c (aarch64_init_builtins)
(aarch64_fold_builtin, aarch64_gimple_fold_builtin)
(aarch64_expand_builtin, aarch64_builtin_decl): New functions.
(aarch64_builtin_reciprocal): Call aarch64_general_builtin_rsqrt
instead of aarch64_builtin_rsqrt.
(aarch64_mangle_type): Call aarch64_general_mangle_builtin_type
instead of aarch64_mangle_builtin_type.
From-SVN: r276177
2019-09-27 10:47:21 +02:00
|
|
|
= aarch64_general_add_builtin ("__builtin_aarch64_pacia1716",
|
|
|
|
ftype_pointer_auth,
|
|
|
|
AARCH64_PAUTH_BUILTIN_PACIA1716);
|
[PATCH 3/3][GCC][AARCH64] Add support for pointer authentication B key
gcc/
2019-05-29 Sam Tebbs <sam.tebbs@arm.com>
* config/aarch64/aarch64-builtins.c (aarch64_builtins): Add
AARCH64_PAUTH_BUILTIN_AUTIB1716 and AARCH64_PAUTH_BUILTIN_PACIB1716.
* config/aarch64/aarch64-builtins.c (aarch64_init_pauth_hint_builtins):
Add autib1716 and pacib1716 initialisation.
* config/aarch64/aarch64-builtins.c (aarch64_expand_builtin): Add checks
for autib1716 and pacib1716.
* config/aarch64/aarch64-protos.h (aarch64_key_type,
aarch64_post_cfi_startproc): Define.
* config/aarch64/aarch64-protos.h (aarch64_ra_sign_key): Define extern.
* config/aarch64/aarch64.c (aarch64_handle_standard_branch_protection,
aarch64_handle_pac_ret_protection): Set default sign key to A.
* config/aarch64/aarch64.c (aarch64_expand_epilogue,
aarch64_expand_prologue): Add check for b-key.
* config/aarch64/aarch64.c (aarch64_ra_sign_key,
aarch64_post_cfi_startproc, aarch64_handle_pac_ret_b_key): Define.
* config/aarch64/aarch64.h (TARGET_ASM_POST_CFI_STARTPROC): Define.
* config/aarch64/aarch64.c (aarch64_pac_ret_subtypes): Add "b-key".
* config/aarch64/aarch64.md (unspec): Add UNSPEC_AUTIA1716,
UNSPEC_AUTIB1716, UNSPEC_AUTIASP, UNSPEC_AUTIBSP, UNSPEC_PACIA1716,
UNSPEC_PACIB1716, UNSPEC_PACIASP, UNSPEC_PACIBSP.
* config/aarch64/aarch64.md (do_return): Add check for b-key.
* config/aarch64/aarch64.md (<pauth_mnem_prefix>sp): Replace
pauth_hint_num_a with pauth_hint_num.
* config/aarch64/aarch64.md (<pauth_mnem_prefix>1716): Replace
pauth_hint_num_a with pauth_hint_num.
* config/aarch64/aarch64.opt (msign-return-address=): Deprecate.
* config/aarch64/iterators.md (PAUTH_LR_SP): Add UNSPEC_AUTIASP,
UNSPEC_AUTIBSP, UNSPEC_PACIASP, UNSPEC_PACIBSP.
* config/aarch64/iterators.md (PAUTH_17_16): Add UNSPEC_AUTIA1716,
UNSPEC_AUTIB1716, UNSPEC_PACIA1716, UNSPEC_PACIB1716.
* config/aarch64/iterators.md (pauth_mnem_prefix): Add UNSPEC_AUTIA1716,
UNSPEC_AUTIB1716, UNSPEC_PACIA1716, UNSPEC_PACIB1716, UNSPEC_AUTIASP,
UNSPEC_AUTIBSP, UNSPEC_PACIASP, UNSPEC_PACIBSP.
* config/aarch64/iterators.md (pauth_hint_num_a): Replace
UNSPEC_PACI1716 and UNSPEC_AUTI1716 with UNSPEC_PACIA1716 and
UNSPEC_AUTIA1716 respectively.
* config/aarch64/iterators.md (pauth_hint_num_a): Rename to pauth_hint_num
and add UNSPEC_PACIBSP, UNSPEC_AUTIBSP, UNSPEC_PACIB1716, UNSPEC_AUTIB1716.
* doc/invoke.texi (-mbranch-protection): Add b-key type.
* config/aarch64/aarch64-bti-insert.c (aarch64_pac_insn_p): Rename
UNSPEC_PACISP to UNSPEC_PACIASP and UNSPEC_PACIBSP.
gcc/testsuite
2019-05-29 Sam Tebbs <sam.tebbs@arm.com>
* gcc.target/aarch64/return_address_sign_b_1.c: New file.
* gcc.target/aarch64/return_address_sign_b_2.c: New file.
* gcc.target/aarch64/return_address_sign_b_3.c: New file.
* gcc.target/aarch64/return_address_sign_b_exception.c: New file.
* gcc.target/aarch64/return_address_sign_ab_exception.c: New file.
* gcc.target/aarch64/return_address_sign_builtin.c: New file
libgcc/
2019-05-29 Sam Tebbs <sam.tebbs@arm.com>
* config/aarch64/aarch64-unwind.h (aarch64_cie_signed_with_b_key): New
function.
* config/aarch64/aarch64-unwind.h (aarch64_post_extract_frame_addr,
aarch64_post_frob_eh_handler_addr): Add check for b-key.
* config/aarch64/aarch64-unwind-h (aarch64_post_extract_frame_addr,
aarch64_post_frob_eh_handler_addr, aarch64_post_frob_update_context):
Rename RA_A_SIGNED_BIT to RA_SIGNED_BIT.
* unwind-dw2-fde.c (get_cie_encoding): Add check for 'B' in augmentation
string.
* unwind-dw2.c (extract_cie_info): Add check for 'B' in augmentation
string.
(RA_A_SIGNED_BIT): Rename to RA_SIGNED_BIT.
From-SVN: r271735
2019-05-29 11:22:17 +02:00
|
|
|
aarch64_builtin_decls[AARCH64_PAUTH_BUILTIN_AUTIB1716]
|
[AArch64] Split built-in function codes into major and minor codes
It was easier to add the SVE ACLE support without enumerating every
function at build time. This in turn meant that it was easier if the
SVE builtins occupied a distinct numberspace from the existing AArch64
ones, which *are* enumerated at build time. This patch therefore
divides the built-in functions codes into "major" and "minor" codes.
At present the major code is just "general", but the SVE patch will add
"SVE" as well.
Also, it was convenient to put the SVE ACLE support in its own file,
so the patch makes aarch64.c provide the frontline target hooks directly,
forwarding to the other files for the real work.
The reason for organising the files this way is that aarch64.c needs
to define the target hook macros whatever happens, and having aarch64.c
macros forward to aarch64-builtins.c functions and aarch64-bulitins.c
functions forward to the SVE file seemed a bit indirect. Doing things
the way the patch does them puts aarch64-builtins.c and the SVE code on
more of an equal footing.
The aarch64_(general_)gimple_fold_builtin change is mostly just
reindentation.
2019-09-27 Richard Sandiford <richard.sandiford@arm.com>
gcc/
* config/aarch64/aarch64-protos.h (aarch64_builtin_class): New enum.
(AARCH64_BUILTIN_SHIFT, AARCH64_BUILTIN_CLASS): New constants.
(aarch64_gimple_fold_builtin, aarch64_mangle_builtin_type)
(aarch64_fold_builtin, aarch64_init_builtins, aarch64_expand_builtin):
(aarch64_builtin_decl, aarch64_builtin_rsqrt): Delete.
(aarch64_general_mangle_builtin_type, aarch64_general_init_builtins):
(aarch64_general_fold_builtin, aarch64_general_gimple_fold_builtin):
(aarch64_general_expand_builtin, aarch64_general_builtin_decl):
(aarch64_general_builtin_rsqrt): Declare.
* config/aarch64/aarch64-builtins.c (aarch64_general_add_builtin):
New function.
(aarch64_mangle_builtin_type): Rename to...
(aarch64_general_mangle_builtin_type): ...this.
(aarch64_init_fcmla_laneq_builtins, aarch64_init_simd_builtins)
(aarch64_init_crc32_builtins, aarch64_init_builtin_rsqrt)
(aarch64_init_pauth_hint_builtins, aarch64_init_tme_builtins): Use
aarch64_general_add_builtin instead of add_builtin_function.
(aarch64_init_builtins): Rename to...
(aarch64_general_init_builtins): ...this. Use
aarch64_general_add_builtin instead of add_builtin_function.
(aarch64_builtin_decl): Rename to...
(aarch64_general_builtin_decl): ...this and remove the unused
arguments.
(aarch64_expand_builtin): Rename to...
(aarch64_general_expand_builtin): ...this and remove the unused
arguments.
(aarch64_builtin_rsqrt): Rename to...
(aarch64_general_builtin_rsqrt): ...this.
(aarch64_fold_builtin): Rename to...
(aarch64_general_fold_builtin): ...this. Take the function subcode
and return type as arguments. Remove the "ignored" argument.
(aarch64_gimple_fold_builtin): Rename to...
(aarch64_general_gimple_fold_builtin): ...this. Take the function
subcode and gcall as arguments, and return the new function call.
* config/aarch64/aarch64.c (aarch64_init_builtins)
(aarch64_fold_builtin, aarch64_gimple_fold_builtin)
(aarch64_expand_builtin, aarch64_builtin_decl): New functions.
(aarch64_builtin_reciprocal): Call aarch64_general_builtin_rsqrt
instead of aarch64_builtin_rsqrt.
(aarch64_mangle_type): Call aarch64_general_mangle_builtin_type
instead of aarch64_mangle_builtin_type.
From-SVN: r276177
2019-09-27 10:47:21 +02:00
|
|
|
= aarch64_general_add_builtin ("__builtin_aarch64_autib1716",
|
|
|
|
ftype_pointer_auth,
|
|
|
|
AARCH64_PAUTH_BUILTIN_AUTIB1716);
|
[PATCH 3/3][GCC][AARCH64] Add support for pointer authentication B key
gcc/
2019-05-29 Sam Tebbs <sam.tebbs@arm.com>
* config/aarch64/aarch64-builtins.c (aarch64_builtins): Add
AARCH64_PAUTH_BUILTIN_AUTIB1716 and AARCH64_PAUTH_BUILTIN_PACIB1716.
* config/aarch64/aarch64-builtins.c (aarch64_init_pauth_hint_builtins):
Add autib1716 and pacib1716 initialisation.
* config/aarch64/aarch64-builtins.c (aarch64_expand_builtin): Add checks
for autib1716 and pacib1716.
* config/aarch64/aarch64-protos.h (aarch64_key_type,
aarch64_post_cfi_startproc): Define.
* config/aarch64/aarch64-protos.h (aarch64_ra_sign_key): Define extern.
* config/aarch64/aarch64.c (aarch64_handle_standard_branch_protection,
aarch64_handle_pac_ret_protection): Set default sign key to A.
* config/aarch64/aarch64.c (aarch64_expand_epilogue,
aarch64_expand_prologue): Add check for b-key.
* config/aarch64/aarch64.c (aarch64_ra_sign_key,
aarch64_post_cfi_startproc, aarch64_handle_pac_ret_b_key): Define.
* config/aarch64/aarch64.h (TARGET_ASM_POST_CFI_STARTPROC): Define.
* config/aarch64/aarch64.c (aarch64_pac_ret_subtypes): Add "b-key".
* config/aarch64/aarch64.md (unspec): Add UNSPEC_AUTIA1716,
UNSPEC_AUTIB1716, UNSPEC_AUTIASP, UNSPEC_AUTIBSP, UNSPEC_PACIA1716,
UNSPEC_PACIB1716, UNSPEC_PACIASP, UNSPEC_PACIBSP.
* config/aarch64/aarch64.md (do_return): Add check for b-key.
* config/aarch64/aarch64.md (<pauth_mnem_prefix>sp): Replace
pauth_hint_num_a with pauth_hint_num.
* config/aarch64/aarch64.md (<pauth_mnem_prefix>1716): Replace
pauth_hint_num_a with pauth_hint_num.
* config/aarch64/aarch64.opt (msign-return-address=): Deprecate.
* config/aarch64/iterators.md (PAUTH_LR_SP): Add UNSPEC_AUTIASP,
UNSPEC_AUTIBSP, UNSPEC_PACIASP, UNSPEC_PACIBSP.
* config/aarch64/iterators.md (PAUTH_17_16): Add UNSPEC_AUTIA1716,
UNSPEC_AUTIB1716, UNSPEC_PACIA1716, UNSPEC_PACIB1716.
* config/aarch64/iterators.md (pauth_mnem_prefix): Add UNSPEC_AUTIA1716,
UNSPEC_AUTIB1716, UNSPEC_PACIA1716, UNSPEC_PACIB1716, UNSPEC_AUTIASP,
UNSPEC_AUTIBSP, UNSPEC_PACIASP, UNSPEC_PACIBSP.
* config/aarch64/iterators.md (pauth_hint_num_a): Replace
UNSPEC_PACI1716 and UNSPEC_AUTI1716 with UNSPEC_PACIA1716 and
UNSPEC_AUTIA1716 respectively.
* config/aarch64/iterators.md (pauth_hint_num_a): Rename to pauth_hint_num
and add UNSPEC_PACIBSP, UNSPEC_AUTIBSP, UNSPEC_PACIB1716, UNSPEC_AUTIB1716.
* doc/invoke.texi (-mbranch-protection): Add b-key type.
* config/aarch64/aarch64-bti-insert.c (aarch64_pac_insn_p): Rename
UNSPEC_PACISP to UNSPEC_PACIASP and UNSPEC_PACIBSP.
gcc/testsuite
2019-05-29 Sam Tebbs <sam.tebbs@arm.com>
* gcc.target/aarch64/return_address_sign_b_1.c: New file.
* gcc.target/aarch64/return_address_sign_b_2.c: New file.
* gcc.target/aarch64/return_address_sign_b_3.c: New file.
* gcc.target/aarch64/return_address_sign_b_exception.c: New file.
* gcc.target/aarch64/return_address_sign_ab_exception.c: New file.
* gcc.target/aarch64/return_address_sign_builtin.c: New file
libgcc/
2019-05-29 Sam Tebbs <sam.tebbs@arm.com>
* config/aarch64/aarch64-unwind.h (aarch64_cie_signed_with_b_key): New
function.
* config/aarch64/aarch64-unwind.h (aarch64_post_extract_frame_addr,
aarch64_post_frob_eh_handler_addr): Add check for b-key.
* config/aarch64/aarch64-unwind-h (aarch64_post_extract_frame_addr,
aarch64_post_frob_eh_handler_addr, aarch64_post_frob_update_context):
Rename RA_A_SIGNED_BIT to RA_SIGNED_BIT.
* unwind-dw2-fde.c (get_cie_encoding): Add check for 'B' in augmentation
string.
* unwind-dw2.c (extract_cie_info): Add check for 'B' in augmentation
string.
(RA_A_SIGNED_BIT): Rename to RA_SIGNED_BIT.
From-SVN: r271735
2019-05-29 11:22:17 +02:00
|
|
|
aarch64_builtin_decls[AARCH64_PAUTH_BUILTIN_PACIB1716]
|
[AArch64] Split built-in function codes into major and minor codes
It was easier to add the SVE ACLE support without enumerating every
function at build time. This in turn meant that it was easier if the
SVE builtins occupied a distinct numberspace from the existing AArch64
ones, which *are* enumerated at build time. This patch therefore
divides the built-in functions codes into "major" and "minor" codes.
At present the major code is just "general", but the SVE patch will add
"SVE" as well.
Also, it was convenient to put the SVE ACLE support in its own file,
so the patch makes aarch64.c provide the frontline target hooks directly,
forwarding to the other files for the real work.
The reason for organising the files this way is that aarch64.c needs
to define the target hook macros whatever happens, and having aarch64.c
macros forward to aarch64-builtins.c functions and aarch64-bulitins.c
functions forward to the SVE file seemed a bit indirect. Doing things
the way the patch does them puts aarch64-builtins.c and the SVE code on
more of an equal footing.
The aarch64_(general_)gimple_fold_builtin change is mostly just
reindentation.
2019-09-27 Richard Sandiford <richard.sandiford@arm.com>
gcc/
* config/aarch64/aarch64-protos.h (aarch64_builtin_class): New enum.
(AARCH64_BUILTIN_SHIFT, AARCH64_BUILTIN_CLASS): New constants.
(aarch64_gimple_fold_builtin, aarch64_mangle_builtin_type)
(aarch64_fold_builtin, aarch64_init_builtins, aarch64_expand_builtin):
(aarch64_builtin_decl, aarch64_builtin_rsqrt): Delete.
(aarch64_general_mangle_builtin_type, aarch64_general_init_builtins):
(aarch64_general_fold_builtin, aarch64_general_gimple_fold_builtin):
(aarch64_general_expand_builtin, aarch64_general_builtin_decl):
(aarch64_general_builtin_rsqrt): Declare.
* config/aarch64/aarch64-builtins.c (aarch64_general_add_builtin):
New function.
(aarch64_mangle_builtin_type): Rename to...
(aarch64_general_mangle_builtin_type): ...this.
(aarch64_init_fcmla_laneq_builtins, aarch64_init_simd_builtins)
(aarch64_init_crc32_builtins, aarch64_init_builtin_rsqrt)
(aarch64_init_pauth_hint_builtins, aarch64_init_tme_builtins): Use
aarch64_general_add_builtin instead of add_builtin_function.
(aarch64_init_builtins): Rename to...
(aarch64_general_init_builtins): ...this. Use
aarch64_general_add_builtin instead of add_builtin_function.
(aarch64_builtin_decl): Rename to...
(aarch64_general_builtin_decl): ...this and remove the unused
arguments.
(aarch64_expand_builtin): Rename to...
(aarch64_general_expand_builtin): ...this and remove the unused
arguments.
(aarch64_builtin_rsqrt): Rename to...
(aarch64_general_builtin_rsqrt): ...this.
(aarch64_fold_builtin): Rename to...
(aarch64_general_fold_builtin): ...this. Take the function subcode
and return type as arguments. Remove the "ignored" argument.
(aarch64_gimple_fold_builtin): Rename to...
(aarch64_general_gimple_fold_builtin): ...this. Take the function
subcode and gcall as arguments, and return the new function call.
* config/aarch64/aarch64.c (aarch64_init_builtins)
(aarch64_fold_builtin, aarch64_gimple_fold_builtin)
(aarch64_expand_builtin, aarch64_builtin_decl): New functions.
(aarch64_builtin_reciprocal): Call aarch64_general_builtin_rsqrt
instead of aarch64_builtin_rsqrt.
(aarch64_mangle_type): Call aarch64_general_mangle_builtin_type
instead of aarch64_mangle_builtin_type.
From-SVN: r276177
2019-09-27 10:47:21 +02:00
|
|
|
= aarch64_general_add_builtin ("__builtin_aarch64_pacib1716",
|
|
|
|
ftype_pointer_auth,
|
|
|
|
AARCH64_PAUTH_BUILTIN_PACIB1716);
|
2017-01-20 01:10:11 +01:00
|
|
|
aarch64_builtin_decls[AARCH64_PAUTH_BUILTIN_XPACLRI]
|
[AArch64] Split built-in function codes into major and minor codes
It was easier to add the SVE ACLE support without enumerating every
function at build time. This in turn meant that it was easier if the
SVE builtins occupied a distinct numberspace from the existing AArch64
ones, which *are* enumerated at build time. This patch therefore
divides the built-in functions codes into "major" and "minor" codes.
At present the major code is just "general", but the SVE patch will add
"SVE" as well.
Also, it was convenient to put the SVE ACLE support in its own file,
so the patch makes aarch64.c provide the frontline target hooks directly,
forwarding to the other files for the real work.
The reason for organising the files this way is that aarch64.c needs
to define the target hook macros whatever happens, and having aarch64.c
macros forward to aarch64-builtins.c functions and aarch64-bulitins.c
functions forward to the SVE file seemed a bit indirect. Doing things
the way the patch does them puts aarch64-builtins.c and the SVE code on
more of an equal footing.
The aarch64_(general_)gimple_fold_builtin change is mostly just
reindentation.
2019-09-27 Richard Sandiford <richard.sandiford@arm.com>
gcc/
* config/aarch64/aarch64-protos.h (aarch64_builtin_class): New enum.
(AARCH64_BUILTIN_SHIFT, AARCH64_BUILTIN_CLASS): New constants.
(aarch64_gimple_fold_builtin, aarch64_mangle_builtin_type)
(aarch64_fold_builtin, aarch64_init_builtins, aarch64_expand_builtin):
(aarch64_builtin_decl, aarch64_builtin_rsqrt): Delete.
(aarch64_general_mangle_builtin_type, aarch64_general_init_builtins):
(aarch64_general_fold_builtin, aarch64_general_gimple_fold_builtin):
(aarch64_general_expand_builtin, aarch64_general_builtin_decl):
(aarch64_general_builtin_rsqrt): Declare.
* config/aarch64/aarch64-builtins.c (aarch64_general_add_builtin):
New function.
(aarch64_mangle_builtin_type): Rename to...
(aarch64_general_mangle_builtin_type): ...this.
(aarch64_init_fcmla_laneq_builtins, aarch64_init_simd_builtins)
(aarch64_init_crc32_builtins, aarch64_init_builtin_rsqrt)
(aarch64_init_pauth_hint_builtins, aarch64_init_tme_builtins): Use
aarch64_general_add_builtin instead of add_builtin_function.
(aarch64_init_builtins): Rename to...
(aarch64_general_init_builtins): ...this. Use
aarch64_general_add_builtin instead of add_builtin_function.
(aarch64_builtin_decl): Rename to...
(aarch64_general_builtin_decl): ...this and remove the unused
arguments.
(aarch64_expand_builtin): Rename to...
(aarch64_general_expand_builtin): ...this and remove the unused
arguments.
(aarch64_builtin_rsqrt): Rename to...
(aarch64_general_builtin_rsqrt): ...this.
(aarch64_fold_builtin): Rename to...
(aarch64_general_fold_builtin): ...this. Take the function subcode
and return type as arguments. Remove the "ignored" argument.
(aarch64_gimple_fold_builtin): Rename to...
(aarch64_general_gimple_fold_builtin): ...this. Take the function
subcode and gcall as arguments, and return the new function call.
* config/aarch64/aarch64.c (aarch64_init_builtins)
(aarch64_fold_builtin, aarch64_gimple_fold_builtin)
(aarch64_expand_builtin, aarch64_builtin_decl): New functions.
(aarch64_builtin_reciprocal): Call aarch64_general_builtin_rsqrt
instead of aarch64_builtin_rsqrt.
(aarch64_mangle_type): Call aarch64_general_mangle_builtin_type
instead of aarch64_mangle_builtin_type.
From-SVN: r276177
2019-09-27 10:47:21 +02:00
|
|
|
= aarch64_general_add_builtin ("__builtin_aarch64_xpaclri",
|
|
|
|
ftype_pointer_strip,
|
|
|
|
AARCH64_PAUTH_BUILTIN_XPACLRI);
|
2017-01-20 01:10:11 +01:00
|
|
|
}
|
|
|
|
|
[GCC, AArch64] Enable Transactional Memory Extension
This patch enables the new Transactional Memory Extension announced recently
as part of Arm's new architecture technologies.
We introduce a new optional extension "tme" to enable this. The following
instructions are part of the extension:
* tstart <Xt>
* ttest <Xt>
* tcommit
* tcancel #<imm>
We have also added ACLE intrinsics for the instructions.
*** gcc/ChangeLog ***
2019-07-31 Sudakshina Das <sudi.das@arm.com>
* config/aarch64/aarch64-builtins.c (enum aarch64_builtins): Add
AARCH64_TME_BUILTIN_TSTART, AARCH64_TME_BUILTIN_TCOMMIT,
AARCH64_TME_BUILTIN_TTEST and AARCH64_TME_BUILTIN_TCANCEL.
(aarch64_init_tme_builtins): New.
(aarch64_init_builtins): Call aarch64_init_tme_builtins.
(aarch64_expand_builtin_tme): New.
(aarch64_expand_builtin): Handle TME builtins.
* config/aarch64/aarch64-c.c (aarch64_update_cpp_builtins): Define
__ARM_FEATURE_TME when enabled.
* config/aarch64/aarch64-option-extensions.def: Add "tme".
* config/aarch64/aarch64.h (AARCH64_FL_TME, AARCH64_ISA_TME): New.
(TARGET_TME): New.
* config/aarch64/aarch64.md (define_c_enum "unspec"): Add UNSPEC_TTEST.
(define_c_enum "unspecv"): Add UNSPECV_TSTART, UNSPECV_TCOMMIT and
UNSPECV_TCANCEL.
(tstart, ttest, tcommit, tcancel): New instructions.
* config/aarch64/arm_acle.h (__tstart, __tcommit): New.
(__tcancel, __ttest): New.
(_TMFAILURE_REASON, _TMFAILURE_RTRY, _TMFAILURE_CNCL): New macro.
(_TMFAILURE_MEM, _TMFAILURE_IMP, _TMFAILURE_ERR): Likewise.
(_TMFAILURE_SIZE, _TMFAILURE_NEST, _TMFAILURE_DBG): Likewise.
(_TMFAILURE_INT, _TMFAILURE_TRIVIAL): Likewise.
* config/arm/types.md: Add new tme type attr.
* doc/invoke.texi: Document "tme".
*** gcc/testsuite/ChangeLog ***
2019-07-31 Sudakshina Das <sudi.das@arm.com>
* gcc.target/aarch64/acle/tme.c: New test.
* gcc.target/aarch64/pragma_cpp_predefs_2.c: New test.
From-SVN: r273926
2019-07-31 11:19:53 +02:00
|
|
|
/* Initialize the transactional memory extension (TME) builtins. */
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|
static void
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|
aarch64_init_tme_builtins (void)
|
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|
{
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tree ftype_uint64_void
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|
|
|
= build_function_type_list (uint64_type_node, NULL);
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|
|
|
tree ftype_void_void
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|
|
|
= build_function_type_list (void_type_node, NULL);
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|
tree ftype_void_uint64
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|
|
= build_function_type_list (void_type_node, uint64_type_node, NULL);
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|
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aarch64_builtin_decls[AARCH64_TME_BUILTIN_TSTART]
|
[AArch64] Split built-in function codes into major and minor codes
It was easier to add the SVE ACLE support without enumerating every
function at build time. This in turn meant that it was easier if the
SVE builtins occupied a distinct numberspace from the existing AArch64
ones, which *are* enumerated at build time. This patch therefore
divides the built-in functions codes into "major" and "minor" codes.
At present the major code is just "general", but the SVE patch will add
"SVE" as well.
Also, it was convenient to put the SVE ACLE support in its own file,
so the patch makes aarch64.c provide the frontline target hooks directly,
forwarding to the other files for the real work.
The reason for organising the files this way is that aarch64.c needs
to define the target hook macros whatever happens, and having aarch64.c
macros forward to aarch64-builtins.c functions and aarch64-bulitins.c
functions forward to the SVE file seemed a bit indirect. Doing things
the way the patch does them puts aarch64-builtins.c and the SVE code on
more of an equal footing.
The aarch64_(general_)gimple_fold_builtin change is mostly just
reindentation.
2019-09-27 Richard Sandiford <richard.sandiford@arm.com>
gcc/
* config/aarch64/aarch64-protos.h (aarch64_builtin_class): New enum.
(AARCH64_BUILTIN_SHIFT, AARCH64_BUILTIN_CLASS): New constants.
(aarch64_gimple_fold_builtin, aarch64_mangle_builtin_type)
(aarch64_fold_builtin, aarch64_init_builtins, aarch64_expand_builtin):
(aarch64_builtin_decl, aarch64_builtin_rsqrt): Delete.
(aarch64_general_mangle_builtin_type, aarch64_general_init_builtins):
(aarch64_general_fold_builtin, aarch64_general_gimple_fold_builtin):
(aarch64_general_expand_builtin, aarch64_general_builtin_decl):
(aarch64_general_builtin_rsqrt): Declare.
* config/aarch64/aarch64-builtins.c (aarch64_general_add_builtin):
New function.
(aarch64_mangle_builtin_type): Rename to...
(aarch64_general_mangle_builtin_type): ...this.
(aarch64_init_fcmla_laneq_builtins, aarch64_init_simd_builtins)
(aarch64_init_crc32_builtins, aarch64_init_builtin_rsqrt)
(aarch64_init_pauth_hint_builtins, aarch64_init_tme_builtins): Use
aarch64_general_add_builtin instead of add_builtin_function.
(aarch64_init_builtins): Rename to...
(aarch64_general_init_builtins): ...this. Use
aarch64_general_add_builtin instead of add_builtin_function.
(aarch64_builtin_decl): Rename to...
(aarch64_general_builtin_decl): ...this and remove the unused
arguments.
(aarch64_expand_builtin): Rename to...
(aarch64_general_expand_builtin): ...this and remove the unused
arguments.
(aarch64_builtin_rsqrt): Rename to...
(aarch64_general_builtin_rsqrt): ...this.
(aarch64_fold_builtin): Rename to...
(aarch64_general_fold_builtin): ...this. Take the function subcode
and return type as arguments. Remove the "ignored" argument.
(aarch64_gimple_fold_builtin): Rename to...
(aarch64_general_gimple_fold_builtin): ...this. Take the function
subcode and gcall as arguments, and return the new function call.
* config/aarch64/aarch64.c (aarch64_init_builtins)
(aarch64_fold_builtin, aarch64_gimple_fold_builtin)
(aarch64_expand_builtin, aarch64_builtin_decl): New functions.
(aarch64_builtin_reciprocal): Call aarch64_general_builtin_rsqrt
instead of aarch64_builtin_rsqrt.
(aarch64_mangle_type): Call aarch64_general_mangle_builtin_type
instead of aarch64_mangle_builtin_type.
From-SVN: r276177
2019-09-27 10:47:21 +02:00
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|
|
= aarch64_general_add_builtin ("__builtin_aarch64_tstart",
|
|
|
|
ftype_uint64_void,
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|
|
|
AARCH64_TME_BUILTIN_TSTART);
|
[GCC, AArch64] Enable Transactional Memory Extension
This patch enables the new Transactional Memory Extension announced recently
as part of Arm's new architecture technologies.
We introduce a new optional extension "tme" to enable this. The following
instructions are part of the extension:
* tstart <Xt>
* ttest <Xt>
* tcommit
* tcancel #<imm>
We have also added ACLE intrinsics for the instructions.
*** gcc/ChangeLog ***
2019-07-31 Sudakshina Das <sudi.das@arm.com>
* config/aarch64/aarch64-builtins.c (enum aarch64_builtins): Add
AARCH64_TME_BUILTIN_TSTART, AARCH64_TME_BUILTIN_TCOMMIT,
AARCH64_TME_BUILTIN_TTEST and AARCH64_TME_BUILTIN_TCANCEL.
(aarch64_init_tme_builtins): New.
(aarch64_init_builtins): Call aarch64_init_tme_builtins.
(aarch64_expand_builtin_tme): New.
(aarch64_expand_builtin): Handle TME builtins.
* config/aarch64/aarch64-c.c (aarch64_update_cpp_builtins): Define
__ARM_FEATURE_TME when enabled.
* config/aarch64/aarch64-option-extensions.def: Add "tme".
* config/aarch64/aarch64.h (AARCH64_FL_TME, AARCH64_ISA_TME): New.
(TARGET_TME): New.
* config/aarch64/aarch64.md (define_c_enum "unspec"): Add UNSPEC_TTEST.
(define_c_enum "unspecv"): Add UNSPECV_TSTART, UNSPECV_TCOMMIT and
UNSPECV_TCANCEL.
(tstart, ttest, tcommit, tcancel): New instructions.
* config/aarch64/arm_acle.h (__tstart, __tcommit): New.
(__tcancel, __ttest): New.
(_TMFAILURE_REASON, _TMFAILURE_RTRY, _TMFAILURE_CNCL): New macro.
(_TMFAILURE_MEM, _TMFAILURE_IMP, _TMFAILURE_ERR): Likewise.
(_TMFAILURE_SIZE, _TMFAILURE_NEST, _TMFAILURE_DBG): Likewise.
(_TMFAILURE_INT, _TMFAILURE_TRIVIAL): Likewise.
* config/arm/types.md: Add new tme type attr.
* doc/invoke.texi: Document "tme".
*** gcc/testsuite/ChangeLog ***
2019-07-31 Sudakshina Das <sudi.das@arm.com>
* gcc.target/aarch64/acle/tme.c: New test.
* gcc.target/aarch64/pragma_cpp_predefs_2.c: New test.
From-SVN: r273926
2019-07-31 11:19:53 +02:00
|
|
|
aarch64_builtin_decls[AARCH64_TME_BUILTIN_TTEST]
|
[AArch64] Split built-in function codes into major and minor codes
It was easier to add the SVE ACLE support without enumerating every
function at build time. This in turn meant that it was easier if the
SVE builtins occupied a distinct numberspace from the existing AArch64
ones, which *are* enumerated at build time. This patch therefore
divides the built-in functions codes into "major" and "minor" codes.
At present the major code is just "general", but the SVE patch will add
"SVE" as well.
Also, it was convenient to put the SVE ACLE support in its own file,
so the patch makes aarch64.c provide the frontline target hooks directly,
forwarding to the other files for the real work.
The reason for organising the files this way is that aarch64.c needs
to define the target hook macros whatever happens, and having aarch64.c
macros forward to aarch64-builtins.c functions and aarch64-bulitins.c
functions forward to the SVE file seemed a bit indirect. Doing things
the way the patch does them puts aarch64-builtins.c and the SVE code on
more of an equal footing.
The aarch64_(general_)gimple_fold_builtin change is mostly just
reindentation.
2019-09-27 Richard Sandiford <richard.sandiford@arm.com>
gcc/
* config/aarch64/aarch64-protos.h (aarch64_builtin_class): New enum.
(AARCH64_BUILTIN_SHIFT, AARCH64_BUILTIN_CLASS): New constants.
(aarch64_gimple_fold_builtin, aarch64_mangle_builtin_type)
(aarch64_fold_builtin, aarch64_init_builtins, aarch64_expand_builtin):
(aarch64_builtin_decl, aarch64_builtin_rsqrt): Delete.
(aarch64_general_mangle_builtin_type, aarch64_general_init_builtins):
(aarch64_general_fold_builtin, aarch64_general_gimple_fold_builtin):
(aarch64_general_expand_builtin, aarch64_general_builtin_decl):
(aarch64_general_builtin_rsqrt): Declare.
* config/aarch64/aarch64-builtins.c (aarch64_general_add_builtin):
New function.
(aarch64_mangle_builtin_type): Rename to...
(aarch64_general_mangle_builtin_type): ...this.
(aarch64_init_fcmla_laneq_builtins, aarch64_init_simd_builtins)
(aarch64_init_crc32_builtins, aarch64_init_builtin_rsqrt)
(aarch64_init_pauth_hint_builtins, aarch64_init_tme_builtins): Use
aarch64_general_add_builtin instead of add_builtin_function.
(aarch64_init_builtins): Rename to...
(aarch64_general_init_builtins): ...this. Use
aarch64_general_add_builtin instead of add_builtin_function.
(aarch64_builtin_decl): Rename to...
(aarch64_general_builtin_decl): ...this and remove the unused
arguments.
(aarch64_expand_builtin): Rename to...
(aarch64_general_expand_builtin): ...this and remove the unused
arguments.
(aarch64_builtin_rsqrt): Rename to...
(aarch64_general_builtin_rsqrt): ...this.
(aarch64_fold_builtin): Rename to...
(aarch64_general_fold_builtin): ...this. Take the function subcode
and return type as arguments. Remove the "ignored" argument.
(aarch64_gimple_fold_builtin): Rename to...
(aarch64_general_gimple_fold_builtin): ...this. Take the function
subcode and gcall as arguments, and return the new function call.
* config/aarch64/aarch64.c (aarch64_init_builtins)
(aarch64_fold_builtin, aarch64_gimple_fold_builtin)
(aarch64_expand_builtin, aarch64_builtin_decl): New functions.
(aarch64_builtin_reciprocal): Call aarch64_general_builtin_rsqrt
instead of aarch64_builtin_rsqrt.
(aarch64_mangle_type): Call aarch64_general_mangle_builtin_type
instead of aarch64_mangle_builtin_type.
From-SVN: r276177
2019-09-27 10:47:21 +02:00
|
|
|
= aarch64_general_add_builtin ("__builtin_aarch64_ttest",
|
|
|
|
ftype_uint64_void,
|
|
|
|
AARCH64_TME_BUILTIN_TTEST);
|
[GCC, AArch64] Enable Transactional Memory Extension
This patch enables the new Transactional Memory Extension announced recently
as part of Arm's new architecture technologies.
We introduce a new optional extension "tme" to enable this. The following
instructions are part of the extension:
* tstart <Xt>
* ttest <Xt>
* tcommit
* tcancel #<imm>
We have also added ACLE intrinsics for the instructions.
*** gcc/ChangeLog ***
2019-07-31 Sudakshina Das <sudi.das@arm.com>
* config/aarch64/aarch64-builtins.c (enum aarch64_builtins): Add
AARCH64_TME_BUILTIN_TSTART, AARCH64_TME_BUILTIN_TCOMMIT,
AARCH64_TME_BUILTIN_TTEST and AARCH64_TME_BUILTIN_TCANCEL.
(aarch64_init_tme_builtins): New.
(aarch64_init_builtins): Call aarch64_init_tme_builtins.
(aarch64_expand_builtin_tme): New.
(aarch64_expand_builtin): Handle TME builtins.
* config/aarch64/aarch64-c.c (aarch64_update_cpp_builtins): Define
__ARM_FEATURE_TME when enabled.
* config/aarch64/aarch64-option-extensions.def: Add "tme".
* config/aarch64/aarch64.h (AARCH64_FL_TME, AARCH64_ISA_TME): New.
(TARGET_TME): New.
* config/aarch64/aarch64.md (define_c_enum "unspec"): Add UNSPEC_TTEST.
(define_c_enum "unspecv"): Add UNSPECV_TSTART, UNSPECV_TCOMMIT and
UNSPECV_TCANCEL.
(tstart, ttest, tcommit, tcancel): New instructions.
* config/aarch64/arm_acle.h (__tstart, __tcommit): New.
(__tcancel, __ttest): New.
(_TMFAILURE_REASON, _TMFAILURE_RTRY, _TMFAILURE_CNCL): New macro.
(_TMFAILURE_MEM, _TMFAILURE_IMP, _TMFAILURE_ERR): Likewise.
(_TMFAILURE_SIZE, _TMFAILURE_NEST, _TMFAILURE_DBG): Likewise.
(_TMFAILURE_INT, _TMFAILURE_TRIVIAL): Likewise.
* config/arm/types.md: Add new tme type attr.
* doc/invoke.texi: Document "tme".
*** gcc/testsuite/ChangeLog ***
2019-07-31 Sudakshina Das <sudi.das@arm.com>
* gcc.target/aarch64/acle/tme.c: New test.
* gcc.target/aarch64/pragma_cpp_predefs_2.c: New test.
From-SVN: r273926
2019-07-31 11:19:53 +02:00
|
|
|
aarch64_builtin_decls[AARCH64_TME_BUILTIN_TCOMMIT]
|
[AArch64] Split built-in function codes into major and minor codes
It was easier to add the SVE ACLE support without enumerating every
function at build time. This in turn meant that it was easier if the
SVE builtins occupied a distinct numberspace from the existing AArch64
ones, which *are* enumerated at build time. This patch therefore
divides the built-in functions codes into "major" and "minor" codes.
At present the major code is just "general", but the SVE patch will add
"SVE" as well.
Also, it was convenient to put the SVE ACLE support in its own file,
so the patch makes aarch64.c provide the frontline target hooks directly,
forwarding to the other files for the real work.
The reason for organising the files this way is that aarch64.c needs
to define the target hook macros whatever happens, and having aarch64.c
macros forward to aarch64-builtins.c functions and aarch64-bulitins.c
functions forward to the SVE file seemed a bit indirect. Doing things
the way the patch does them puts aarch64-builtins.c and the SVE code on
more of an equal footing.
The aarch64_(general_)gimple_fold_builtin change is mostly just
reindentation.
2019-09-27 Richard Sandiford <richard.sandiford@arm.com>
gcc/
* config/aarch64/aarch64-protos.h (aarch64_builtin_class): New enum.
(AARCH64_BUILTIN_SHIFT, AARCH64_BUILTIN_CLASS): New constants.
(aarch64_gimple_fold_builtin, aarch64_mangle_builtin_type)
(aarch64_fold_builtin, aarch64_init_builtins, aarch64_expand_builtin):
(aarch64_builtin_decl, aarch64_builtin_rsqrt): Delete.
(aarch64_general_mangle_builtin_type, aarch64_general_init_builtins):
(aarch64_general_fold_builtin, aarch64_general_gimple_fold_builtin):
(aarch64_general_expand_builtin, aarch64_general_builtin_decl):
(aarch64_general_builtin_rsqrt): Declare.
* config/aarch64/aarch64-builtins.c (aarch64_general_add_builtin):
New function.
(aarch64_mangle_builtin_type): Rename to...
(aarch64_general_mangle_builtin_type): ...this.
(aarch64_init_fcmla_laneq_builtins, aarch64_init_simd_builtins)
(aarch64_init_crc32_builtins, aarch64_init_builtin_rsqrt)
(aarch64_init_pauth_hint_builtins, aarch64_init_tme_builtins): Use
aarch64_general_add_builtin instead of add_builtin_function.
(aarch64_init_builtins): Rename to...
(aarch64_general_init_builtins): ...this. Use
aarch64_general_add_builtin instead of add_builtin_function.
(aarch64_builtin_decl): Rename to...
(aarch64_general_builtin_decl): ...this and remove the unused
arguments.
(aarch64_expand_builtin): Rename to...
(aarch64_general_expand_builtin): ...this and remove the unused
arguments.
(aarch64_builtin_rsqrt): Rename to...
(aarch64_general_builtin_rsqrt): ...this.
(aarch64_fold_builtin): Rename to...
(aarch64_general_fold_builtin): ...this. Take the function subcode
and return type as arguments. Remove the "ignored" argument.
(aarch64_gimple_fold_builtin): Rename to...
(aarch64_general_gimple_fold_builtin): ...this. Take the function
subcode and gcall as arguments, and return the new function call.
* config/aarch64/aarch64.c (aarch64_init_builtins)
(aarch64_fold_builtin, aarch64_gimple_fold_builtin)
(aarch64_expand_builtin, aarch64_builtin_decl): New functions.
(aarch64_builtin_reciprocal): Call aarch64_general_builtin_rsqrt
instead of aarch64_builtin_rsqrt.
(aarch64_mangle_type): Call aarch64_general_mangle_builtin_type
instead of aarch64_mangle_builtin_type.
From-SVN: r276177
2019-09-27 10:47:21 +02:00
|
|
|
= aarch64_general_add_builtin ("__builtin_aarch64_tcommit",
|
|
|
|
ftype_void_void,
|
|
|
|
AARCH64_TME_BUILTIN_TCOMMIT);
|
[GCC, AArch64] Enable Transactional Memory Extension
This patch enables the new Transactional Memory Extension announced recently
as part of Arm's new architecture technologies.
We introduce a new optional extension "tme" to enable this. The following
instructions are part of the extension:
* tstart <Xt>
* ttest <Xt>
* tcommit
* tcancel #<imm>
We have also added ACLE intrinsics for the instructions.
*** gcc/ChangeLog ***
2019-07-31 Sudakshina Das <sudi.das@arm.com>
* config/aarch64/aarch64-builtins.c (enum aarch64_builtins): Add
AARCH64_TME_BUILTIN_TSTART, AARCH64_TME_BUILTIN_TCOMMIT,
AARCH64_TME_BUILTIN_TTEST and AARCH64_TME_BUILTIN_TCANCEL.
(aarch64_init_tme_builtins): New.
(aarch64_init_builtins): Call aarch64_init_tme_builtins.
(aarch64_expand_builtin_tme): New.
(aarch64_expand_builtin): Handle TME builtins.
* config/aarch64/aarch64-c.c (aarch64_update_cpp_builtins): Define
__ARM_FEATURE_TME when enabled.
* config/aarch64/aarch64-option-extensions.def: Add "tme".
* config/aarch64/aarch64.h (AARCH64_FL_TME, AARCH64_ISA_TME): New.
(TARGET_TME): New.
* config/aarch64/aarch64.md (define_c_enum "unspec"): Add UNSPEC_TTEST.
(define_c_enum "unspecv"): Add UNSPECV_TSTART, UNSPECV_TCOMMIT and
UNSPECV_TCANCEL.
(tstart, ttest, tcommit, tcancel): New instructions.
* config/aarch64/arm_acle.h (__tstart, __tcommit): New.
(__tcancel, __ttest): New.
(_TMFAILURE_REASON, _TMFAILURE_RTRY, _TMFAILURE_CNCL): New macro.
(_TMFAILURE_MEM, _TMFAILURE_IMP, _TMFAILURE_ERR): Likewise.
(_TMFAILURE_SIZE, _TMFAILURE_NEST, _TMFAILURE_DBG): Likewise.
(_TMFAILURE_INT, _TMFAILURE_TRIVIAL): Likewise.
* config/arm/types.md: Add new tme type attr.
* doc/invoke.texi: Document "tme".
*** gcc/testsuite/ChangeLog ***
2019-07-31 Sudakshina Das <sudi.das@arm.com>
* gcc.target/aarch64/acle/tme.c: New test.
* gcc.target/aarch64/pragma_cpp_predefs_2.c: New test.
From-SVN: r273926
2019-07-31 11:19:53 +02:00
|
|
|
aarch64_builtin_decls[AARCH64_TME_BUILTIN_TCANCEL]
|
[AArch64] Split built-in function codes into major and minor codes
It was easier to add the SVE ACLE support without enumerating every
function at build time. This in turn meant that it was easier if the
SVE builtins occupied a distinct numberspace from the existing AArch64
ones, which *are* enumerated at build time. This patch therefore
divides the built-in functions codes into "major" and "minor" codes.
At present the major code is just "general", but the SVE patch will add
"SVE" as well.
Also, it was convenient to put the SVE ACLE support in its own file,
so the patch makes aarch64.c provide the frontline target hooks directly,
forwarding to the other files for the real work.
The reason for organising the files this way is that aarch64.c needs
to define the target hook macros whatever happens, and having aarch64.c
macros forward to aarch64-builtins.c functions and aarch64-bulitins.c
functions forward to the SVE file seemed a bit indirect. Doing things
the way the patch does them puts aarch64-builtins.c and the SVE code on
more of an equal footing.
The aarch64_(general_)gimple_fold_builtin change is mostly just
reindentation.
2019-09-27 Richard Sandiford <richard.sandiford@arm.com>
gcc/
* config/aarch64/aarch64-protos.h (aarch64_builtin_class): New enum.
(AARCH64_BUILTIN_SHIFT, AARCH64_BUILTIN_CLASS): New constants.
(aarch64_gimple_fold_builtin, aarch64_mangle_builtin_type)
(aarch64_fold_builtin, aarch64_init_builtins, aarch64_expand_builtin):
(aarch64_builtin_decl, aarch64_builtin_rsqrt): Delete.
(aarch64_general_mangle_builtin_type, aarch64_general_init_builtins):
(aarch64_general_fold_builtin, aarch64_general_gimple_fold_builtin):
(aarch64_general_expand_builtin, aarch64_general_builtin_decl):
(aarch64_general_builtin_rsqrt): Declare.
* config/aarch64/aarch64-builtins.c (aarch64_general_add_builtin):
New function.
(aarch64_mangle_builtin_type): Rename to...
(aarch64_general_mangle_builtin_type): ...this.
(aarch64_init_fcmla_laneq_builtins, aarch64_init_simd_builtins)
(aarch64_init_crc32_builtins, aarch64_init_builtin_rsqrt)
(aarch64_init_pauth_hint_builtins, aarch64_init_tme_builtins): Use
aarch64_general_add_builtin instead of add_builtin_function.
(aarch64_init_builtins): Rename to...
(aarch64_general_init_builtins): ...this. Use
aarch64_general_add_builtin instead of add_builtin_function.
(aarch64_builtin_decl): Rename to...
(aarch64_general_builtin_decl): ...this and remove the unused
arguments.
(aarch64_expand_builtin): Rename to...
(aarch64_general_expand_builtin): ...this and remove the unused
arguments.
(aarch64_builtin_rsqrt): Rename to...
(aarch64_general_builtin_rsqrt): ...this.
(aarch64_fold_builtin): Rename to...
(aarch64_general_fold_builtin): ...this. Take the function subcode
and return type as arguments. Remove the "ignored" argument.
(aarch64_gimple_fold_builtin): Rename to...
(aarch64_general_gimple_fold_builtin): ...this. Take the function
subcode and gcall as arguments, and return the new function call.
* config/aarch64/aarch64.c (aarch64_init_builtins)
(aarch64_fold_builtin, aarch64_gimple_fold_builtin)
(aarch64_expand_builtin, aarch64_builtin_decl): New functions.
(aarch64_builtin_reciprocal): Call aarch64_general_builtin_rsqrt
instead of aarch64_builtin_rsqrt.
(aarch64_mangle_type): Call aarch64_general_mangle_builtin_type
instead of aarch64_mangle_builtin_type.
From-SVN: r276177
2019-09-27 10:47:21 +02:00
|
|
|
= aarch64_general_add_builtin ("__builtin_aarch64_tcancel",
|
|
|
|
ftype_void_uint64,
|
|
|
|
AARCH64_TME_BUILTIN_TCANCEL);
|
[GCC, AArch64] Enable Transactional Memory Extension
This patch enables the new Transactional Memory Extension announced recently
as part of Arm's new architecture technologies.
We introduce a new optional extension "tme" to enable this. The following
instructions are part of the extension:
* tstart <Xt>
* ttest <Xt>
* tcommit
* tcancel #<imm>
We have also added ACLE intrinsics for the instructions.
*** gcc/ChangeLog ***
2019-07-31 Sudakshina Das <sudi.das@arm.com>
* config/aarch64/aarch64-builtins.c (enum aarch64_builtins): Add
AARCH64_TME_BUILTIN_TSTART, AARCH64_TME_BUILTIN_TCOMMIT,
AARCH64_TME_BUILTIN_TTEST and AARCH64_TME_BUILTIN_TCANCEL.
(aarch64_init_tme_builtins): New.
(aarch64_init_builtins): Call aarch64_init_tme_builtins.
(aarch64_expand_builtin_tme): New.
(aarch64_expand_builtin): Handle TME builtins.
* config/aarch64/aarch64-c.c (aarch64_update_cpp_builtins): Define
__ARM_FEATURE_TME when enabled.
* config/aarch64/aarch64-option-extensions.def: Add "tme".
* config/aarch64/aarch64.h (AARCH64_FL_TME, AARCH64_ISA_TME): New.
(TARGET_TME): New.
* config/aarch64/aarch64.md (define_c_enum "unspec"): Add UNSPEC_TTEST.
(define_c_enum "unspecv"): Add UNSPECV_TSTART, UNSPECV_TCOMMIT and
UNSPECV_TCANCEL.
(tstart, ttest, tcommit, tcancel): New instructions.
* config/aarch64/arm_acle.h (__tstart, __tcommit): New.
(__tcancel, __ttest): New.
(_TMFAILURE_REASON, _TMFAILURE_RTRY, _TMFAILURE_CNCL): New macro.
(_TMFAILURE_MEM, _TMFAILURE_IMP, _TMFAILURE_ERR): Likewise.
(_TMFAILURE_SIZE, _TMFAILURE_NEST, _TMFAILURE_DBG): Likewise.
(_TMFAILURE_INT, _TMFAILURE_TRIVIAL): Likewise.
* config/arm/types.md: Add new tme type attr.
* doc/invoke.texi: Document "tme".
*** gcc/testsuite/ChangeLog ***
2019-07-31 Sudakshina Das <sudi.das@arm.com>
* gcc.target/aarch64/acle/tme.c: New test.
* gcc.target/aarch64/pragma_cpp_predefs_2.c: New test.
From-SVN: r273926
2019-07-31 11:19:53 +02:00
|
|
|
}
|
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|
|
|
2019-10-21 12:52:05 +02:00
|
|
|
/* Add builtins for Random Number instructions. */
|
|
|
|
|
|
|
|
static void
|
|
|
|
aarch64_init_rng_builtins (void)
|
|
|
|
{
|
|
|
|
tree unsigned_ptr_type = build_pointer_type (unsigned_intDI_type_node);
|
|
|
|
tree ftype
|
|
|
|
= build_function_type_list (integer_type_node, unsigned_ptr_type, NULL);
|
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|
|
aarch64_builtin_decls[AARCH64_BUILTIN_RNG_RNDR]
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|
|
|
= aarch64_general_add_builtin ("__builtin_aarch64_rndr", ftype,
|
|
|
|
AARCH64_BUILTIN_RNG_RNDR);
|
|
|
|
aarch64_builtin_decls[AARCH64_BUILTIN_RNG_RNDRRS]
|
|
|
|
= aarch64_general_add_builtin ("__builtin_aarch64_rndrrs", ftype,
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|
|
AARCH64_BUILTIN_RNG_RNDRRS);
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|
|
|
}
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|
[AArch64] Implement Armv8.5-A memory tagging (MTE) intrinsics
2019-11-19 Dennis Zhang <dennis.zhang@arm.com>
* config/aarch64/aarch64-builtins.c (enum aarch64_builtins): Add
AARCH64_MEMTAG_BUILTIN_START, AARCH64_MEMTAG_BUILTIN_IRG,
AARCH64_MEMTAG_BUILTIN_GMI, AARCH64_MEMTAG_BUILTIN_SUBP,
AARCH64_MEMTAG_BUILTIN_INC_TAG, AARCH64_MEMTAG_BUILTIN_SET_TAG,
AARCH64_MEMTAG_BUILTIN_GET_TAG, and AARCH64_MEMTAG_BUILTIN_END.
(aarch64_init_memtag_builtins): New.
(AARCH64_INIT_MEMTAG_BUILTINS_DECL): New macro.
(aarch64_general_init_builtins): Call aarch64_init_memtag_builtins.
(aarch64_expand_builtin_memtag): New.
(aarch64_general_expand_builtin): Call aarch64_expand_builtin_memtag.
(AARCH64_BUILTIN_SUBCODE): New macro.
(aarch64_resolve_overloaded_memtag): New.
(aarch64_resolve_overloaded_builtin_general): New. Call
aarch64_resolve_overloaded_memtag to handle overloaded MTE builtins.
* config/aarch64/aarch64-c.c (aarch64_update_cpp_builtins): Define
__ARM_FEATURE_MEMORY_TAGGING when enabled.
(aarch64_resolve_overloaded_builtin): Call
aarch64_resolve_overloaded_builtin_general.
* config/aarch64/aarch64-protos.h
(aarch64_resolve_overloaded_builtin_general): New declaration.
* config/aarch64/aarch64.h (AARCH64_ISA_MEMTAG): New macro.
(TARGET_MEMTAG): Likewise.
* config/aarch64/aarch64.md (UNSPEC_GEN_TAG): New unspec.
(UNSPEC_GEN_TAG_RND, and UNSPEC_TAG_SPACE): Likewise.
(irg, gmi, subp, addg, ldg, stg): New instructions.
* config/aarch64/arm_acle.h (__arm_mte_create_random_tag): New macro.
(__arm_mte_exclude_tag, __arm_mte_ptrdiff): Likewise.
(__arm_mte_increment_tag, __arm_mte_set_tag): Likewise.
(__arm_mte_get_tag): Likewise.
* config/aarch64/predicates.md (aarch64_memtag_tag_offset): New.
(aarch64_granule16_uimm6, aarch64_granule16_simm9): New.
* config/arm/types.md (memtag): New.
* doc/invoke.texi (-memtag): Update description.
2019-11-19 Dennis Zhang <dennis.zhang@arm.com>
* gcc.target/aarch64/acle/memtag_1.c: New test.
* gcc.target/aarch64/acle/memtag_2.c: New test.
* gcc.target/aarch64/acle/memtag_3.c: New test.
From-SVN: r278444
2019-11-19 14:43:39 +01:00
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|
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/* Initialize the memory tagging extension (MTE) builtins. */
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|
|
struct
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|
|
|
{
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|
|
tree ftype;
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|
|
enum insn_code icode;
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|
} aarch64_memtag_builtin_data[AARCH64_MEMTAG_BUILTIN_END -
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|
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AARCH64_MEMTAG_BUILTIN_START - 1];
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|
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static void
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|
|
aarch64_init_memtag_builtins (void)
|
|
|
|
{
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|
|
|
tree fntype = NULL;
|
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|
|
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|
|
|
#define AARCH64_INIT_MEMTAG_BUILTINS_DECL(F, N, I, T) \
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aarch64_builtin_decls[AARCH64_MEMTAG_BUILTIN_##F] \
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= aarch64_general_add_builtin ("__builtin_aarch64_memtag_"#N, \
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T, AARCH64_MEMTAG_BUILTIN_##F); \
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aarch64_memtag_builtin_data[AARCH64_MEMTAG_BUILTIN_##F - \
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AARCH64_MEMTAG_BUILTIN_START - 1] = \
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|
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{T, CODE_FOR_##I};
|
|
|
|
|
|
|
|
fntype = build_function_type_list (ptr_type_node, ptr_type_node,
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|
|
|
uint64_type_node, NULL);
|
|
|
|
AARCH64_INIT_MEMTAG_BUILTINS_DECL (IRG, irg, irg, fntype);
|
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|
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|
|
|
|
fntype = build_function_type_list (uint64_type_node, ptr_type_node,
|
|
|
|
uint64_type_node, NULL);
|
|
|
|
AARCH64_INIT_MEMTAG_BUILTINS_DECL (GMI, gmi, gmi, fntype);
|
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|
|
|
|
|
|
fntype = build_function_type_list (ptrdiff_type_node, ptr_type_node,
|
|
|
|
ptr_type_node, NULL);
|
|
|
|
AARCH64_INIT_MEMTAG_BUILTINS_DECL (SUBP, subp, subp, fntype);
|
|
|
|
|
|
|
|
fntype = build_function_type_list (ptr_type_node, ptr_type_node,
|
|
|
|
unsigned_type_node, NULL);
|
|
|
|
AARCH64_INIT_MEMTAG_BUILTINS_DECL (INC_TAG, inc_tag, addg, fntype);
|
|
|
|
|
|
|
|
fntype = build_function_type_list (void_type_node, ptr_type_node, NULL);
|
|
|
|
AARCH64_INIT_MEMTAG_BUILTINS_DECL (SET_TAG, set_tag, stg, fntype);
|
|
|
|
|
|
|
|
fntype = build_function_type_list (ptr_type_node, ptr_type_node, NULL);
|
|
|
|
AARCH64_INIT_MEMTAG_BUILTINS_DECL (GET_TAG, get_tag, ldg, fntype);
|
|
|
|
|
|
|
|
#undef AARCH64_INIT_MEMTAG_BUILTINS_DECL
|
|
|
|
}
|
2019-10-21 12:52:05 +02:00
|
|
|
|
2021-12-14 15:03:38 +01:00
|
|
|
/* Add builtins for Load/store 64 Byte instructions. */
|
|
|
|
|
|
|
|
typedef struct
|
|
|
|
{
|
|
|
|
const char *name;
|
|
|
|
unsigned int code;
|
|
|
|
tree type;
|
|
|
|
} ls64_builtins_data;
|
|
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|
|
|
|
|
static GTY(()) tree ls64_arm_data_t = NULL_TREE;
|
|
|
|
|
|
|
|
static void
|
|
|
|
aarch64_init_ls64_builtins_types (void)
|
|
|
|
{
|
|
|
|
/* Synthesize:
|
|
|
|
|
|
|
|
typedef struct {
|
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|
|
uint64_t val[8];
|
|
|
|
} __arm_data512_t; */
|
|
|
|
const char *tuple_type_name = "__arm_data512_t";
|
|
|
|
tree node_type = get_typenode_from_name (UINT64_TYPE);
|
|
|
|
tree array_type = build_array_type_nelts (node_type, 8);
|
|
|
|
SET_TYPE_MODE (array_type, V8DImode);
|
|
|
|
|
|
|
|
gcc_assert (TYPE_MODE_RAW (array_type) == TYPE_MODE (array_type));
|
|
|
|
gcc_assert (TYPE_ALIGN (array_type) == 64);
|
|
|
|
|
|
|
|
tree field = build_decl (input_location, FIELD_DECL,
|
|
|
|
get_identifier ("val"), array_type);
|
|
|
|
|
|
|
|
ls64_arm_data_t = lang_hooks.types.simulate_record_decl (input_location,
|
|
|
|
tuple_type_name,
|
|
|
|
make_array_slice (&field, 1));
|
|
|
|
|
|
|
|
gcc_assert (TYPE_MODE (ls64_arm_data_t) == V8DImode);
|
|
|
|
gcc_assert (TYPE_MODE_RAW (ls64_arm_data_t) == TYPE_MODE (ls64_arm_data_t));
|
|
|
|
gcc_assert (TYPE_ALIGN (ls64_arm_data_t) == 64);
|
|
|
|
}
|
|
|
|
|
|
|
|
static void
|
|
|
|
aarch64_init_ls64_builtins (void)
|
|
|
|
{
|
|
|
|
aarch64_init_ls64_builtins_types ();
|
|
|
|
|
|
|
|
ls64_builtins_data data[4] = {
|
|
|
|
{"__builtin_aarch64_ld64b", AARCH64_LS64_BUILTIN_LD64B,
|
|
|
|
build_function_type_list (ls64_arm_data_t,
|
|
|
|
const_ptr_type_node, NULL_TREE)},
|
|
|
|
{"__builtin_aarch64_st64b", AARCH64_LS64_BUILTIN_ST64B,
|
|
|
|
build_function_type_list (void_type_node, ptr_type_node,
|
|
|
|
ls64_arm_data_t, NULL_TREE)},
|
|
|
|
{"__builtin_aarch64_st64bv", AARCH64_LS64_BUILTIN_ST64BV,
|
|
|
|
build_function_type_list (uint64_type_node, ptr_type_node,
|
|
|
|
ls64_arm_data_t, NULL_TREE)},
|
|
|
|
{"__builtin_aarch64_st64bv0", AARCH64_LS64_BUILTIN_ST64BV0,
|
|
|
|
build_function_type_list (uint64_type_node, ptr_type_node,
|
|
|
|
ls64_arm_data_t, NULL_TREE)},
|
|
|
|
};
|
|
|
|
|
|
|
|
for (size_t i = 0; i < ARRAY_SIZE (data); ++i)
|
|
|
|
aarch64_builtin_decls[data[i].code]
|
|
|
|
= aarch64_general_add_builtin (data[i].name, data[i].type, data[i].code);
|
|
|
|
}
|
|
|
|
|
2022-04-07 17:48:05 +02:00
|
|
|
/* Implement #pragma GCC aarch64 "arm_acle.h". */
|
|
|
|
void
|
|
|
|
handle_arm_acle_h (void)
|
|
|
|
{
|
|
|
|
if (TARGET_LS64)
|
|
|
|
aarch64_init_ls64_builtins ();
|
|
|
|
}
|
|
|
|
|
2020-05-28 09:49:42 +02:00
|
|
|
/* Initialize fpsr fpcr getters and setters. */
|
2019-10-21 12:52:05 +02:00
|
|
|
|
2020-05-28 09:49:42 +02:00
|
|
|
static void
|
|
|
|
aarch64_init_fpsr_fpcr_builtins (void)
|
2012-10-23 19:02:30 +02:00
|
|
|
{
|
2020-05-28 09:49:42 +02:00
|
|
|
tree ftype_set
|
2014-05-23 00:05:08 +02:00
|
|
|
= build_function_type_list (void_type_node, unsigned_type_node, NULL);
|
2020-05-28 09:49:42 +02:00
|
|
|
tree ftype_get
|
2014-05-23 00:05:08 +02:00
|
|
|
= build_function_type_list (unsigned_type_node, NULL);
|
|
|
|
|
|
|
|
aarch64_builtin_decls[AARCH64_BUILTIN_GET_FPCR]
|
[AArch64] Split built-in function codes into major and minor codes
It was easier to add the SVE ACLE support without enumerating every
function at build time. This in turn meant that it was easier if the
SVE builtins occupied a distinct numberspace from the existing AArch64
ones, which *are* enumerated at build time. This patch therefore
divides the built-in functions codes into "major" and "minor" codes.
At present the major code is just "general", but the SVE patch will add
"SVE" as well.
Also, it was convenient to put the SVE ACLE support in its own file,
so the patch makes aarch64.c provide the frontline target hooks directly,
forwarding to the other files for the real work.
The reason for organising the files this way is that aarch64.c needs
to define the target hook macros whatever happens, and having aarch64.c
macros forward to aarch64-builtins.c functions and aarch64-bulitins.c
functions forward to the SVE file seemed a bit indirect. Doing things
the way the patch does them puts aarch64-builtins.c and the SVE code on
more of an equal footing.
The aarch64_(general_)gimple_fold_builtin change is mostly just
reindentation.
2019-09-27 Richard Sandiford <richard.sandiford@arm.com>
gcc/
* config/aarch64/aarch64-protos.h (aarch64_builtin_class): New enum.
(AARCH64_BUILTIN_SHIFT, AARCH64_BUILTIN_CLASS): New constants.
(aarch64_gimple_fold_builtin, aarch64_mangle_builtin_type)
(aarch64_fold_builtin, aarch64_init_builtins, aarch64_expand_builtin):
(aarch64_builtin_decl, aarch64_builtin_rsqrt): Delete.
(aarch64_general_mangle_builtin_type, aarch64_general_init_builtins):
(aarch64_general_fold_builtin, aarch64_general_gimple_fold_builtin):
(aarch64_general_expand_builtin, aarch64_general_builtin_decl):
(aarch64_general_builtin_rsqrt): Declare.
* config/aarch64/aarch64-builtins.c (aarch64_general_add_builtin):
New function.
(aarch64_mangle_builtin_type): Rename to...
(aarch64_general_mangle_builtin_type): ...this.
(aarch64_init_fcmla_laneq_builtins, aarch64_init_simd_builtins)
(aarch64_init_crc32_builtins, aarch64_init_builtin_rsqrt)
(aarch64_init_pauth_hint_builtins, aarch64_init_tme_builtins): Use
aarch64_general_add_builtin instead of add_builtin_function.
(aarch64_init_builtins): Rename to...
(aarch64_general_init_builtins): ...this. Use
aarch64_general_add_builtin instead of add_builtin_function.
(aarch64_builtin_decl): Rename to...
(aarch64_general_builtin_decl): ...this and remove the unused
arguments.
(aarch64_expand_builtin): Rename to...
(aarch64_general_expand_builtin): ...this and remove the unused
arguments.
(aarch64_builtin_rsqrt): Rename to...
(aarch64_general_builtin_rsqrt): ...this.
(aarch64_fold_builtin): Rename to...
(aarch64_general_fold_builtin): ...this. Take the function subcode
and return type as arguments. Remove the "ignored" argument.
(aarch64_gimple_fold_builtin): Rename to...
(aarch64_general_gimple_fold_builtin): ...this. Take the function
subcode and gcall as arguments, and return the new function call.
* config/aarch64/aarch64.c (aarch64_init_builtins)
(aarch64_fold_builtin, aarch64_gimple_fold_builtin)
(aarch64_expand_builtin, aarch64_builtin_decl): New functions.
(aarch64_builtin_reciprocal): Call aarch64_general_builtin_rsqrt
instead of aarch64_builtin_rsqrt.
(aarch64_mangle_type): Call aarch64_general_mangle_builtin_type
instead of aarch64_mangle_builtin_type.
From-SVN: r276177
2019-09-27 10:47:21 +02:00
|
|
|
= aarch64_general_add_builtin ("__builtin_aarch64_get_fpcr",
|
2020-05-28 09:49:42 +02:00
|
|
|
ftype_get,
|
[AArch64] Split built-in function codes into major and minor codes
It was easier to add the SVE ACLE support without enumerating every
function at build time. This in turn meant that it was easier if the
SVE builtins occupied a distinct numberspace from the existing AArch64
ones, which *are* enumerated at build time. This patch therefore
divides the built-in functions codes into "major" and "minor" codes.
At present the major code is just "general", but the SVE patch will add
"SVE" as well.
Also, it was convenient to put the SVE ACLE support in its own file,
so the patch makes aarch64.c provide the frontline target hooks directly,
forwarding to the other files for the real work.
The reason for organising the files this way is that aarch64.c needs
to define the target hook macros whatever happens, and having aarch64.c
macros forward to aarch64-builtins.c functions and aarch64-bulitins.c
functions forward to the SVE file seemed a bit indirect. Doing things
the way the patch does them puts aarch64-builtins.c and the SVE code on
more of an equal footing.
The aarch64_(general_)gimple_fold_builtin change is mostly just
reindentation.
2019-09-27 Richard Sandiford <richard.sandiford@arm.com>
gcc/
* config/aarch64/aarch64-protos.h (aarch64_builtin_class): New enum.
(AARCH64_BUILTIN_SHIFT, AARCH64_BUILTIN_CLASS): New constants.
(aarch64_gimple_fold_builtin, aarch64_mangle_builtin_type)
(aarch64_fold_builtin, aarch64_init_builtins, aarch64_expand_builtin):
(aarch64_builtin_decl, aarch64_builtin_rsqrt): Delete.
(aarch64_general_mangle_builtin_type, aarch64_general_init_builtins):
(aarch64_general_fold_builtin, aarch64_general_gimple_fold_builtin):
(aarch64_general_expand_builtin, aarch64_general_builtin_decl):
(aarch64_general_builtin_rsqrt): Declare.
* config/aarch64/aarch64-builtins.c (aarch64_general_add_builtin):
New function.
(aarch64_mangle_builtin_type): Rename to...
(aarch64_general_mangle_builtin_type): ...this.
(aarch64_init_fcmla_laneq_builtins, aarch64_init_simd_builtins)
(aarch64_init_crc32_builtins, aarch64_init_builtin_rsqrt)
(aarch64_init_pauth_hint_builtins, aarch64_init_tme_builtins): Use
aarch64_general_add_builtin instead of add_builtin_function.
(aarch64_init_builtins): Rename to...
(aarch64_general_init_builtins): ...this. Use
aarch64_general_add_builtin instead of add_builtin_function.
(aarch64_builtin_decl): Rename to...
(aarch64_general_builtin_decl): ...this and remove the unused
arguments.
(aarch64_expand_builtin): Rename to...
(aarch64_general_expand_builtin): ...this and remove the unused
arguments.
(aarch64_builtin_rsqrt): Rename to...
(aarch64_general_builtin_rsqrt): ...this.
(aarch64_fold_builtin): Rename to...
(aarch64_general_fold_builtin): ...this. Take the function subcode
and return type as arguments. Remove the "ignored" argument.
(aarch64_gimple_fold_builtin): Rename to...
(aarch64_general_gimple_fold_builtin): ...this. Take the function
subcode and gcall as arguments, and return the new function call.
* config/aarch64/aarch64.c (aarch64_init_builtins)
(aarch64_fold_builtin, aarch64_gimple_fold_builtin)
(aarch64_expand_builtin, aarch64_builtin_decl): New functions.
(aarch64_builtin_reciprocal): Call aarch64_general_builtin_rsqrt
instead of aarch64_builtin_rsqrt.
(aarch64_mangle_type): Call aarch64_general_mangle_builtin_type
instead of aarch64_mangle_builtin_type.
From-SVN: r276177
2019-09-27 10:47:21 +02:00
|
|
|
AARCH64_BUILTIN_GET_FPCR);
|
2014-05-23 00:05:08 +02:00
|
|
|
aarch64_builtin_decls[AARCH64_BUILTIN_SET_FPCR]
|
[AArch64] Split built-in function codes into major and minor codes
It was easier to add the SVE ACLE support without enumerating every
function at build time. This in turn meant that it was easier if the
SVE builtins occupied a distinct numberspace from the existing AArch64
ones, which *are* enumerated at build time. This patch therefore
divides the built-in functions codes into "major" and "minor" codes.
At present the major code is just "general", but the SVE patch will add
"SVE" as well.
Also, it was convenient to put the SVE ACLE support in its own file,
so the patch makes aarch64.c provide the frontline target hooks directly,
forwarding to the other files for the real work.
The reason for organising the files this way is that aarch64.c needs
to define the target hook macros whatever happens, and having aarch64.c
macros forward to aarch64-builtins.c functions and aarch64-bulitins.c
functions forward to the SVE file seemed a bit indirect. Doing things
the way the patch does them puts aarch64-builtins.c and the SVE code on
more of an equal footing.
The aarch64_(general_)gimple_fold_builtin change is mostly just
reindentation.
2019-09-27 Richard Sandiford <richard.sandiford@arm.com>
gcc/
* config/aarch64/aarch64-protos.h (aarch64_builtin_class): New enum.
(AARCH64_BUILTIN_SHIFT, AARCH64_BUILTIN_CLASS): New constants.
(aarch64_gimple_fold_builtin, aarch64_mangle_builtin_type)
(aarch64_fold_builtin, aarch64_init_builtins, aarch64_expand_builtin):
(aarch64_builtin_decl, aarch64_builtin_rsqrt): Delete.
(aarch64_general_mangle_builtin_type, aarch64_general_init_builtins):
(aarch64_general_fold_builtin, aarch64_general_gimple_fold_builtin):
(aarch64_general_expand_builtin, aarch64_general_builtin_decl):
(aarch64_general_builtin_rsqrt): Declare.
* config/aarch64/aarch64-builtins.c (aarch64_general_add_builtin):
New function.
(aarch64_mangle_builtin_type): Rename to...
(aarch64_general_mangle_builtin_type): ...this.
(aarch64_init_fcmla_laneq_builtins, aarch64_init_simd_builtins)
(aarch64_init_crc32_builtins, aarch64_init_builtin_rsqrt)
(aarch64_init_pauth_hint_builtins, aarch64_init_tme_builtins): Use
aarch64_general_add_builtin instead of add_builtin_function.
(aarch64_init_builtins): Rename to...
(aarch64_general_init_builtins): ...this. Use
aarch64_general_add_builtin instead of add_builtin_function.
(aarch64_builtin_decl): Rename to...
(aarch64_general_builtin_decl): ...this and remove the unused
arguments.
(aarch64_expand_builtin): Rename to...
(aarch64_general_expand_builtin): ...this and remove the unused
arguments.
(aarch64_builtin_rsqrt): Rename to...
(aarch64_general_builtin_rsqrt): ...this.
(aarch64_fold_builtin): Rename to...
(aarch64_general_fold_builtin): ...this. Take the function subcode
and return type as arguments. Remove the "ignored" argument.
(aarch64_gimple_fold_builtin): Rename to...
(aarch64_general_gimple_fold_builtin): ...this. Take the function
subcode and gcall as arguments, and return the new function call.
* config/aarch64/aarch64.c (aarch64_init_builtins)
(aarch64_fold_builtin, aarch64_gimple_fold_builtin)
(aarch64_expand_builtin, aarch64_builtin_decl): New functions.
(aarch64_builtin_reciprocal): Call aarch64_general_builtin_rsqrt
instead of aarch64_builtin_rsqrt.
(aarch64_mangle_type): Call aarch64_general_mangle_builtin_type
instead of aarch64_mangle_builtin_type.
From-SVN: r276177
2019-09-27 10:47:21 +02:00
|
|
|
= aarch64_general_add_builtin ("__builtin_aarch64_set_fpcr",
|
2020-05-28 09:49:42 +02:00
|
|
|
ftype_set,
|
[AArch64] Split built-in function codes into major and minor codes
It was easier to add the SVE ACLE support without enumerating every
function at build time. This in turn meant that it was easier if the
SVE builtins occupied a distinct numberspace from the existing AArch64
ones, which *are* enumerated at build time. This patch therefore
divides the built-in functions codes into "major" and "minor" codes.
At present the major code is just "general", but the SVE patch will add
"SVE" as well.
Also, it was convenient to put the SVE ACLE support in its own file,
so the patch makes aarch64.c provide the frontline target hooks directly,
forwarding to the other files for the real work.
The reason for organising the files this way is that aarch64.c needs
to define the target hook macros whatever happens, and having aarch64.c
macros forward to aarch64-builtins.c functions and aarch64-bulitins.c
functions forward to the SVE file seemed a bit indirect. Doing things
the way the patch does them puts aarch64-builtins.c and the SVE code on
more of an equal footing.
The aarch64_(general_)gimple_fold_builtin change is mostly just
reindentation.
2019-09-27 Richard Sandiford <richard.sandiford@arm.com>
gcc/
* config/aarch64/aarch64-protos.h (aarch64_builtin_class): New enum.
(AARCH64_BUILTIN_SHIFT, AARCH64_BUILTIN_CLASS): New constants.
(aarch64_gimple_fold_builtin, aarch64_mangle_builtin_type)
(aarch64_fold_builtin, aarch64_init_builtins, aarch64_expand_builtin):
(aarch64_builtin_decl, aarch64_builtin_rsqrt): Delete.
(aarch64_general_mangle_builtin_type, aarch64_general_init_builtins):
(aarch64_general_fold_builtin, aarch64_general_gimple_fold_builtin):
(aarch64_general_expand_builtin, aarch64_general_builtin_decl):
(aarch64_general_builtin_rsqrt): Declare.
* config/aarch64/aarch64-builtins.c (aarch64_general_add_builtin):
New function.
(aarch64_mangle_builtin_type): Rename to...
(aarch64_general_mangle_builtin_type): ...this.
(aarch64_init_fcmla_laneq_builtins, aarch64_init_simd_builtins)
(aarch64_init_crc32_builtins, aarch64_init_builtin_rsqrt)
(aarch64_init_pauth_hint_builtins, aarch64_init_tme_builtins): Use
aarch64_general_add_builtin instead of add_builtin_function.
(aarch64_init_builtins): Rename to...
(aarch64_general_init_builtins): ...this. Use
aarch64_general_add_builtin instead of add_builtin_function.
(aarch64_builtin_decl): Rename to...
(aarch64_general_builtin_decl): ...this and remove the unused
arguments.
(aarch64_expand_builtin): Rename to...
(aarch64_general_expand_builtin): ...this and remove the unused
arguments.
(aarch64_builtin_rsqrt): Rename to...
(aarch64_general_builtin_rsqrt): ...this.
(aarch64_fold_builtin): Rename to...
(aarch64_general_fold_builtin): ...this. Take the function subcode
and return type as arguments. Remove the "ignored" argument.
(aarch64_gimple_fold_builtin): Rename to...
(aarch64_general_gimple_fold_builtin): ...this. Take the function
subcode and gcall as arguments, and return the new function call.
* config/aarch64/aarch64.c (aarch64_init_builtins)
(aarch64_fold_builtin, aarch64_gimple_fold_builtin)
(aarch64_expand_builtin, aarch64_builtin_decl): New functions.
(aarch64_builtin_reciprocal): Call aarch64_general_builtin_rsqrt
instead of aarch64_builtin_rsqrt.
(aarch64_mangle_type): Call aarch64_general_mangle_builtin_type
instead of aarch64_mangle_builtin_type.
From-SVN: r276177
2019-09-27 10:47:21 +02:00
|
|
|
AARCH64_BUILTIN_SET_FPCR);
|
2014-05-23 00:05:08 +02:00
|
|
|
aarch64_builtin_decls[AARCH64_BUILTIN_GET_FPSR]
|
[AArch64] Split built-in function codes into major and minor codes
It was easier to add the SVE ACLE support without enumerating every
function at build time. This in turn meant that it was easier if the
SVE builtins occupied a distinct numberspace from the existing AArch64
ones, which *are* enumerated at build time. This patch therefore
divides the built-in functions codes into "major" and "minor" codes.
At present the major code is just "general", but the SVE patch will add
"SVE" as well.
Also, it was convenient to put the SVE ACLE support in its own file,
so the patch makes aarch64.c provide the frontline target hooks directly,
forwarding to the other files for the real work.
The reason for organising the files this way is that aarch64.c needs
to define the target hook macros whatever happens, and having aarch64.c
macros forward to aarch64-builtins.c functions and aarch64-bulitins.c
functions forward to the SVE file seemed a bit indirect. Doing things
the way the patch does them puts aarch64-builtins.c and the SVE code on
more of an equal footing.
The aarch64_(general_)gimple_fold_builtin change is mostly just
reindentation.
2019-09-27 Richard Sandiford <richard.sandiford@arm.com>
gcc/
* config/aarch64/aarch64-protos.h (aarch64_builtin_class): New enum.
(AARCH64_BUILTIN_SHIFT, AARCH64_BUILTIN_CLASS): New constants.
(aarch64_gimple_fold_builtin, aarch64_mangle_builtin_type)
(aarch64_fold_builtin, aarch64_init_builtins, aarch64_expand_builtin):
(aarch64_builtin_decl, aarch64_builtin_rsqrt): Delete.
(aarch64_general_mangle_builtin_type, aarch64_general_init_builtins):
(aarch64_general_fold_builtin, aarch64_general_gimple_fold_builtin):
(aarch64_general_expand_builtin, aarch64_general_builtin_decl):
(aarch64_general_builtin_rsqrt): Declare.
* config/aarch64/aarch64-builtins.c (aarch64_general_add_builtin):
New function.
(aarch64_mangle_builtin_type): Rename to...
(aarch64_general_mangle_builtin_type): ...this.
(aarch64_init_fcmla_laneq_builtins, aarch64_init_simd_builtins)
(aarch64_init_crc32_builtins, aarch64_init_builtin_rsqrt)
(aarch64_init_pauth_hint_builtins, aarch64_init_tme_builtins): Use
aarch64_general_add_builtin instead of add_builtin_function.
(aarch64_init_builtins): Rename to...
(aarch64_general_init_builtins): ...this. Use
aarch64_general_add_builtin instead of add_builtin_function.
(aarch64_builtin_decl): Rename to...
(aarch64_general_builtin_decl): ...this and remove the unused
arguments.
(aarch64_expand_builtin): Rename to...
(aarch64_general_expand_builtin): ...this and remove the unused
arguments.
(aarch64_builtin_rsqrt): Rename to...
(aarch64_general_builtin_rsqrt): ...this.
(aarch64_fold_builtin): Rename to...
(aarch64_general_fold_builtin): ...this. Take the function subcode
and return type as arguments. Remove the "ignored" argument.
(aarch64_gimple_fold_builtin): Rename to...
(aarch64_general_gimple_fold_builtin): ...this. Take the function
subcode and gcall as arguments, and return the new function call.
* config/aarch64/aarch64.c (aarch64_init_builtins)
(aarch64_fold_builtin, aarch64_gimple_fold_builtin)
(aarch64_expand_builtin, aarch64_builtin_decl): New functions.
(aarch64_builtin_reciprocal): Call aarch64_general_builtin_rsqrt
instead of aarch64_builtin_rsqrt.
(aarch64_mangle_type): Call aarch64_general_mangle_builtin_type
instead of aarch64_mangle_builtin_type.
From-SVN: r276177
2019-09-27 10:47:21 +02:00
|
|
|
= aarch64_general_add_builtin ("__builtin_aarch64_get_fpsr",
|
2020-05-28 09:49:42 +02:00
|
|
|
ftype_get,
|
[AArch64] Split built-in function codes into major and minor codes
It was easier to add the SVE ACLE support without enumerating every
function at build time. This in turn meant that it was easier if the
SVE builtins occupied a distinct numberspace from the existing AArch64
ones, which *are* enumerated at build time. This patch therefore
divides the built-in functions codes into "major" and "minor" codes.
At present the major code is just "general", but the SVE patch will add
"SVE" as well.
Also, it was convenient to put the SVE ACLE support in its own file,
so the patch makes aarch64.c provide the frontline target hooks directly,
forwarding to the other files for the real work.
The reason for organising the files this way is that aarch64.c needs
to define the target hook macros whatever happens, and having aarch64.c
macros forward to aarch64-builtins.c functions and aarch64-bulitins.c
functions forward to the SVE file seemed a bit indirect. Doing things
the way the patch does them puts aarch64-builtins.c and the SVE code on
more of an equal footing.
The aarch64_(general_)gimple_fold_builtin change is mostly just
reindentation.
2019-09-27 Richard Sandiford <richard.sandiford@arm.com>
gcc/
* config/aarch64/aarch64-protos.h (aarch64_builtin_class): New enum.
(AARCH64_BUILTIN_SHIFT, AARCH64_BUILTIN_CLASS): New constants.
(aarch64_gimple_fold_builtin, aarch64_mangle_builtin_type)
(aarch64_fold_builtin, aarch64_init_builtins, aarch64_expand_builtin):
(aarch64_builtin_decl, aarch64_builtin_rsqrt): Delete.
(aarch64_general_mangle_builtin_type, aarch64_general_init_builtins):
(aarch64_general_fold_builtin, aarch64_general_gimple_fold_builtin):
(aarch64_general_expand_builtin, aarch64_general_builtin_decl):
(aarch64_general_builtin_rsqrt): Declare.
* config/aarch64/aarch64-builtins.c (aarch64_general_add_builtin):
New function.
(aarch64_mangle_builtin_type): Rename to...
(aarch64_general_mangle_builtin_type): ...this.
(aarch64_init_fcmla_laneq_builtins, aarch64_init_simd_builtins)
(aarch64_init_crc32_builtins, aarch64_init_builtin_rsqrt)
(aarch64_init_pauth_hint_builtins, aarch64_init_tme_builtins): Use
aarch64_general_add_builtin instead of add_builtin_function.
(aarch64_init_builtins): Rename to...
(aarch64_general_init_builtins): ...this. Use
aarch64_general_add_builtin instead of add_builtin_function.
(aarch64_builtin_decl): Rename to...
(aarch64_general_builtin_decl): ...this and remove the unused
arguments.
(aarch64_expand_builtin): Rename to...
(aarch64_general_expand_builtin): ...this and remove the unused
arguments.
(aarch64_builtin_rsqrt): Rename to...
(aarch64_general_builtin_rsqrt): ...this.
(aarch64_fold_builtin): Rename to...
(aarch64_general_fold_builtin): ...this. Take the function subcode
and return type as arguments. Remove the "ignored" argument.
(aarch64_gimple_fold_builtin): Rename to...
(aarch64_general_gimple_fold_builtin): ...this. Take the function
subcode and gcall as arguments, and return the new function call.
* config/aarch64/aarch64.c (aarch64_init_builtins)
(aarch64_fold_builtin, aarch64_gimple_fold_builtin)
(aarch64_expand_builtin, aarch64_builtin_decl): New functions.
(aarch64_builtin_reciprocal): Call aarch64_general_builtin_rsqrt
instead of aarch64_builtin_rsqrt.
(aarch64_mangle_type): Call aarch64_general_mangle_builtin_type
instead of aarch64_mangle_builtin_type.
From-SVN: r276177
2019-09-27 10:47:21 +02:00
|
|
|
AARCH64_BUILTIN_GET_FPSR);
|
2014-05-23 00:05:08 +02:00
|
|
|
aarch64_builtin_decls[AARCH64_BUILTIN_SET_FPSR]
|
[AArch64] Split built-in function codes into major and minor codes
It was easier to add the SVE ACLE support without enumerating every
function at build time. This in turn meant that it was easier if the
SVE builtins occupied a distinct numberspace from the existing AArch64
ones, which *are* enumerated at build time. This patch therefore
divides the built-in functions codes into "major" and "minor" codes.
At present the major code is just "general", but the SVE patch will add
"SVE" as well.
Also, it was convenient to put the SVE ACLE support in its own file,
so the patch makes aarch64.c provide the frontline target hooks directly,
forwarding to the other files for the real work.
The reason for organising the files this way is that aarch64.c needs
to define the target hook macros whatever happens, and having aarch64.c
macros forward to aarch64-builtins.c functions and aarch64-bulitins.c
functions forward to the SVE file seemed a bit indirect. Doing things
the way the patch does them puts aarch64-builtins.c and the SVE code on
more of an equal footing.
The aarch64_(general_)gimple_fold_builtin change is mostly just
reindentation.
2019-09-27 Richard Sandiford <richard.sandiford@arm.com>
gcc/
* config/aarch64/aarch64-protos.h (aarch64_builtin_class): New enum.
(AARCH64_BUILTIN_SHIFT, AARCH64_BUILTIN_CLASS): New constants.
(aarch64_gimple_fold_builtin, aarch64_mangle_builtin_type)
(aarch64_fold_builtin, aarch64_init_builtins, aarch64_expand_builtin):
(aarch64_builtin_decl, aarch64_builtin_rsqrt): Delete.
(aarch64_general_mangle_builtin_type, aarch64_general_init_builtins):
(aarch64_general_fold_builtin, aarch64_general_gimple_fold_builtin):
(aarch64_general_expand_builtin, aarch64_general_builtin_decl):
(aarch64_general_builtin_rsqrt): Declare.
* config/aarch64/aarch64-builtins.c (aarch64_general_add_builtin):
New function.
(aarch64_mangle_builtin_type): Rename to...
(aarch64_general_mangle_builtin_type): ...this.
(aarch64_init_fcmla_laneq_builtins, aarch64_init_simd_builtins)
(aarch64_init_crc32_builtins, aarch64_init_builtin_rsqrt)
(aarch64_init_pauth_hint_builtins, aarch64_init_tme_builtins): Use
aarch64_general_add_builtin instead of add_builtin_function.
(aarch64_init_builtins): Rename to...
(aarch64_general_init_builtins): ...this. Use
aarch64_general_add_builtin instead of add_builtin_function.
(aarch64_builtin_decl): Rename to...
(aarch64_general_builtin_decl): ...this and remove the unused
arguments.
(aarch64_expand_builtin): Rename to...
(aarch64_general_expand_builtin): ...this and remove the unused
arguments.
(aarch64_builtin_rsqrt): Rename to...
(aarch64_general_builtin_rsqrt): ...this.
(aarch64_fold_builtin): Rename to...
(aarch64_general_fold_builtin): ...this. Take the function subcode
and return type as arguments. Remove the "ignored" argument.
(aarch64_gimple_fold_builtin): Rename to...
(aarch64_general_gimple_fold_builtin): ...this. Take the function
subcode and gcall as arguments, and return the new function call.
* config/aarch64/aarch64.c (aarch64_init_builtins)
(aarch64_fold_builtin, aarch64_gimple_fold_builtin)
(aarch64_expand_builtin, aarch64_builtin_decl): New functions.
(aarch64_builtin_reciprocal): Call aarch64_general_builtin_rsqrt
instead of aarch64_builtin_rsqrt.
(aarch64_mangle_type): Call aarch64_general_mangle_builtin_type
instead of aarch64_mangle_builtin_type.
From-SVN: r276177
2019-09-27 10:47:21 +02:00
|
|
|
= aarch64_general_add_builtin ("__builtin_aarch64_set_fpsr",
|
2020-05-28 09:49:42 +02:00
|
|
|
ftype_set,
|
[AArch64] Split built-in function codes into major and minor codes
It was easier to add the SVE ACLE support without enumerating every
function at build time. This in turn meant that it was easier if the
SVE builtins occupied a distinct numberspace from the existing AArch64
ones, which *are* enumerated at build time. This patch therefore
divides the built-in functions codes into "major" and "minor" codes.
At present the major code is just "general", but the SVE patch will add
"SVE" as well.
Also, it was convenient to put the SVE ACLE support in its own file,
so the patch makes aarch64.c provide the frontline target hooks directly,
forwarding to the other files for the real work.
The reason for organising the files this way is that aarch64.c needs
to define the target hook macros whatever happens, and having aarch64.c
macros forward to aarch64-builtins.c functions and aarch64-bulitins.c
functions forward to the SVE file seemed a bit indirect. Doing things
the way the patch does them puts aarch64-builtins.c and the SVE code on
more of an equal footing.
The aarch64_(general_)gimple_fold_builtin change is mostly just
reindentation.
2019-09-27 Richard Sandiford <richard.sandiford@arm.com>
gcc/
* config/aarch64/aarch64-protos.h (aarch64_builtin_class): New enum.
(AARCH64_BUILTIN_SHIFT, AARCH64_BUILTIN_CLASS): New constants.
(aarch64_gimple_fold_builtin, aarch64_mangle_builtin_type)
(aarch64_fold_builtin, aarch64_init_builtins, aarch64_expand_builtin):
(aarch64_builtin_decl, aarch64_builtin_rsqrt): Delete.
(aarch64_general_mangle_builtin_type, aarch64_general_init_builtins):
(aarch64_general_fold_builtin, aarch64_general_gimple_fold_builtin):
(aarch64_general_expand_builtin, aarch64_general_builtin_decl):
(aarch64_general_builtin_rsqrt): Declare.
* config/aarch64/aarch64-builtins.c (aarch64_general_add_builtin):
New function.
(aarch64_mangle_builtin_type): Rename to...
(aarch64_general_mangle_builtin_type): ...this.
(aarch64_init_fcmla_laneq_builtins, aarch64_init_simd_builtins)
(aarch64_init_crc32_builtins, aarch64_init_builtin_rsqrt)
(aarch64_init_pauth_hint_builtins, aarch64_init_tme_builtins): Use
aarch64_general_add_builtin instead of add_builtin_function.
(aarch64_init_builtins): Rename to...
(aarch64_general_init_builtins): ...this. Use
aarch64_general_add_builtin instead of add_builtin_function.
(aarch64_builtin_decl): Rename to...
(aarch64_general_builtin_decl): ...this and remove the unused
arguments.
(aarch64_expand_builtin): Rename to...
(aarch64_general_expand_builtin): ...this and remove the unused
arguments.
(aarch64_builtin_rsqrt): Rename to...
(aarch64_general_builtin_rsqrt): ...this.
(aarch64_fold_builtin): Rename to...
(aarch64_general_fold_builtin): ...this. Take the function subcode
and return type as arguments. Remove the "ignored" argument.
(aarch64_gimple_fold_builtin): Rename to...
(aarch64_general_gimple_fold_builtin): ...this. Take the function
subcode and gcall as arguments, and return the new function call.
* config/aarch64/aarch64.c (aarch64_init_builtins)
(aarch64_fold_builtin, aarch64_gimple_fold_builtin)
(aarch64_expand_builtin, aarch64_builtin_decl): New functions.
(aarch64_builtin_reciprocal): Call aarch64_general_builtin_rsqrt
instead of aarch64_builtin_rsqrt.
(aarch64_mangle_type): Call aarch64_general_mangle_builtin_type
instead of aarch64_mangle_builtin_type.
From-SVN: r276177
2019-09-27 10:47:21 +02:00
|
|
|
AARCH64_BUILTIN_SET_FPSR);
|
2014-05-23 00:05:08 +02:00
|
|
|
|
2020-05-28 09:49:42 +02:00
|
|
|
ftype_set
|
|
|
|
= build_function_type_list (void_type_node, long_long_unsigned_type_node,
|
|
|
|
NULL);
|
|
|
|
ftype_get
|
|
|
|
= build_function_type_list (long_long_unsigned_type_node, NULL);
|
|
|
|
|
|
|
|
aarch64_builtin_decls[AARCH64_BUILTIN_GET_FPCR64]
|
|
|
|
= aarch64_general_add_builtin ("__builtin_aarch64_get_fpcr64",
|
|
|
|
ftype_get,
|
|
|
|
AARCH64_BUILTIN_GET_FPCR64);
|
|
|
|
aarch64_builtin_decls[AARCH64_BUILTIN_SET_FPCR64]
|
|
|
|
= aarch64_general_add_builtin ("__builtin_aarch64_set_fpcr64",
|
|
|
|
ftype_set,
|
|
|
|
AARCH64_BUILTIN_SET_FPCR64);
|
|
|
|
aarch64_builtin_decls[AARCH64_BUILTIN_GET_FPSR64]
|
|
|
|
= aarch64_general_add_builtin ("__builtin_aarch64_get_fpsr64",
|
|
|
|
ftype_get,
|
|
|
|
AARCH64_BUILTIN_GET_FPSR64);
|
|
|
|
aarch64_builtin_decls[AARCH64_BUILTIN_SET_FPSR64]
|
|
|
|
= aarch64_general_add_builtin ("__builtin_aarch64_set_fpsr64",
|
|
|
|
ftype_set,
|
|
|
|
AARCH64_BUILTIN_SET_FPSR64);
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Initialize all builtins in the AARCH64_BUILTIN_GENERAL group. */
|
|
|
|
|
|
|
|
void
|
|
|
|
aarch64_general_init_builtins (void)
|
|
|
|
{
|
|
|
|
aarch64_init_fpsr_fpcr_builtins ();
|
|
|
|
|
2016-08-05 18:08:24 +02:00
|
|
|
aarch64_init_fp16_types ();
|
2015-07-29 14:27:05 +02:00
|
|
|
|
2020-01-10 20:23:41 +01:00
|
|
|
aarch64_init_bf16_types ();
|
|
|
|
|
2022-04-05 18:31:35 +02:00
|
|
|
{
|
|
|
|
aarch64_simd_switcher simd;
|
2019-01-10 23:28:00 +01:00
|
|
|
aarch64_init_simd_builtins ();
|
2022-04-05 18:31:35 +02:00
|
|
|
}
|
2015-08-04 12:39:42 +02:00
|
|
|
|
|
|
|
aarch64_init_crc32_builtins ();
|
2015-11-06 18:10:17 +01:00
|
|
|
aarch64_init_builtin_rsqrt ();
|
2019-10-21 12:52:05 +02:00
|
|
|
aarch64_init_rng_builtins ();
|
2017-01-20 01:10:11 +01:00
|
|
|
|
2019-09-03 10:40:30 +02:00
|
|
|
tree ftype_jcvt
|
|
|
|
= build_function_type_list (intSI_type_node, double_type_node, NULL);
|
|
|
|
aarch64_builtin_decls[AARCH64_JSCVT]
|
[AArch64] Split built-in function codes into major and minor codes
It was easier to add the SVE ACLE support without enumerating every
function at build time. This in turn meant that it was easier if the
SVE builtins occupied a distinct numberspace from the existing AArch64
ones, which *are* enumerated at build time. This patch therefore
divides the built-in functions codes into "major" and "minor" codes.
At present the major code is just "general", but the SVE patch will add
"SVE" as well.
Also, it was convenient to put the SVE ACLE support in its own file,
so the patch makes aarch64.c provide the frontline target hooks directly,
forwarding to the other files for the real work.
The reason for organising the files this way is that aarch64.c needs
to define the target hook macros whatever happens, and having aarch64.c
macros forward to aarch64-builtins.c functions and aarch64-bulitins.c
functions forward to the SVE file seemed a bit indirect. Doing things
the way the patch does them puts aarch64-builtins.c and the SVE code on
more of an equal footing.
The aarch64_(general_)gimple_fold_builtin change is mostly just
reindentation.
2019-09-27 Richard Sandiford <richard.sandiford@arm.com>
gcc/
* config/aarch64/aarch64-protos.h (aarch64_builtin_class): New enum.
(AARCH64_BUILTIN_SHIFT, AARCH64_BUILTIN_CLASS): New constants.
(aarch64_gimple_fold_builtin, aarch64_mangle_builtin_type)
(aarch64_fold_builtin, aarch64_init_builtins, aarch64_expand_builtin):
(aarch64_builtin_decl, aarch64_builtin_rsqrt): Delete.
(aarch64_general_mangle_builtin_type, aarch64_general_init_builtins):
(aarch64_general_fold_builtin, aarch64_general_gimple_fold_builtin):
(aarch64_general_expand_builtin, aarch64_general_builtin_decl):
(aarch64_general_builtin_rsqrt): Declare.
* config/aarch64/aarch64-builtins.c (aarch64_general_add_builtin):
New function.
(aarch64_mangle_builtin_type): Rename to...
(aarch64_general_mangle_builtin_type): ...this.
(aarch64_init_fcmla_laneq_builtins, aarch64_init_simd_builtins)
(aarch64_init_crc32_builtins, aarch64_init_builtin_rsqrt)
(aarch64_init_pauth_hint_builtins, aarch64_init_tme_builtins): Use
aarch64_general_add_builtin instead of add_builtin_function.
(aarch64_init_builtins): Rename to...
(aarch64_general_init_builtins): ...this. Use
aarch64_general_add_builtin instead of add_builtin_function.
(aarch64_builtin_decl): Rename to...
(aarch64_general_builtin_decl): ...this and remove the unused
arguments.
(aarch64_expand_builtin): Rename to...
(aarch64_general_expand_builtin): ...this and remove the unused
arguments.
(aarch64_builtin_rsqrt): Rename to...
(aarch64_general_builtin_rsqrt): ...this.
(aarch64_fold_builtin): Rename to...
(aarch64_general_fold_builtin): ...this. Take the function subcode
and return type as arguments. Remove the "ignored" argument.
(aarch64_gimple_fold_builtin): Rename to...
(aarch64_general_gimple_fold_builtin): ...this. Take the function
subcode and gcall as arguments, and return the new function call.
* config/aarch64/aarch64.c (aarch64_init_builtins)
(aarch64_fold_builtin, aarch64_gimple_fold_builtin)
(aarch64_expand_builtin, aarch64_builtin_decl): New functions.
(aarch64_builtin_reciprocal): Call aarch64_general_builtin_rsqrt
instead of aarch64_builtin_rsqrt.
(aarch64_mangle_type): Call aarch64_general_mangle_builtin_type
instead of aarch64_mangle_builtin_type.
From-SVN: r276177
2019-09-27 10:47:21 +02:00
|
|
|
= aarch64_general_add_builtin ("__builtin_aarch64_jcvtzs", ftype_jcvt,
|
|
|
|
AARCH64_JSCVT);
|
2019-09-03 10:40:30 +02:00
|
|
|
|
2017-01-20 22:03:41 +01:00
|
|
|
/* Initialize pointer authentication builtins which are backed by instructions
|
|
|
|
in NOP encoding space.
|
|
|
|
|
|
|
|
NOTE: these builtins are supposed to be used by libgcc unwinder only, as
|
|
|
|
there is no support on return address signing under ILP32, we don't
|
|
|
|
register them. */
|
|
|
|
if (!TARGET_ILP32)
|
|
|
|
aarch64_init_pauth_hint_builtins ();
|
[GCC, AArch64] Enable Transactional Memory Extension
This patch enables the new Transactional Memory Extension announced recently
as part of Arm's new architecture technologies.
We introduce a new optional extension "tme" to enable this. The following
instructions are part of the extension:
* tstart <Xt>
* ttest <Xt>
* tcommit
* tcancel #<imm>
We have also added ACLE intrinsics for the instructions.
*** gcc/ChangeLog ***
2019-07-31 Sudakshina Das <sudi.das@arm.com>
* config/aarch64/aarch64-builtins.c (enum aarch64_builtins): Add
AARCH64_TME_BUILTIN_TSTART, AARCH64_TME_BUILTIN_TCOMMIT,
AARCH64_TME_BUILTIN_TTEST and AARCH64_TME_BUILTIN_TCANCEL.
(aarch64_init_tme_builtins): New.
(aarch64_init_builtins): Call aarch64_init_tme_builtins.
(aarch64_expand_builtin_tme): New.
(aarch64_expand_builtin): Handle TME builtins.
* config/aarch64/aarch64-c.c (aarch64_update_cpp_builtins): Define
__ARM_FEATURE_TME when enabled.
* config/aarch64/aarch64-option-extensions.def: Add "tme".
* config/aarch64/aarch64.h (AARCH64_FL_TME, AARCH64_ISA_TME): New.
(TARGET_TME): New.
* config/aarch64/aarch64.md (define_c_enum "unspec"): Add UNSPEC_TTEST.
(define_c_enum "unspecv"): Add UNSPECV_TSTART, UNSPECV_TCOMMIT and
UNSPECV_TCANCEL.
(tstart, ttest, tcommit, tcancel): New instructions.
* config/aarch64/arm_acle.h (__tstart, __tcommit): New.
(__tcancel, __ttest): New.
(_TMFAILURE_REASON, _TMFAILURE_RTRY, _TMFAILURE_CNCL): New macro.
(_TMFAILURE_MEM, _TMFAILURE_IMP, _TMFAILURE_ERR): Likewise.
(_TMFAILURE_SIZE, _TMFAILURE_NEST, _TMFAILURE_DBG): Likewise.
(_TMFAILURE_INT, _TMFAILURE_TRIVIAL): Likewise.
* config/arm/types.md: Add new tme type attr.
* doc/invoke.texi: Document "tme".
*** gcc/testsuite/ChangeLog ***
2019-07-31 Sudakshina Das <sudi.das@arm.com>
* gcc.target/aarch64/acle/tme.c: New test.
* gcc.target/aarch64/pragma_cpp_predefs_2.c: New test.
From-SVN: r273926
2019-07-31 11:19:53 +02:00
|
|
|
|
|
|
|
if (TARGET_TME)
|
|
|
|
aarch64_init_tme_builtins ();
|
[AArch64] Implement Armv8.5-A memory tagging (MTE) intrinsics
2019-11-19 Dennis Zhang <dennis.zhang@arm.com>
* config/aarch64/aarch64-builtins.c (enum aarch64_builtins): Add
AARCH64_MEMTAG_BUILTIN_START, AARCH64_MEMTAG_BUILTIN_IRG,
AARCH64_MEMTAG_BUILTIN_GMI, AARCH64_MEMTAG_BUILTIN_SUBP,
AARCH64_MEMTAG_BUILTIN_INC_TAG, AARCH64_MEMTAG_BUILTIN_SET_TAG,
AARCH64_MEMTAG_BUILTIN_GET_TAG, and AARCH64_MEMTAG_BUILTIN_END.
(aarch64_init_memtag_builtins): New.
(AARCH64_INIT_MEMTAG_BUILTINS_DECL): New macro.
(aarch64_general_init_builtins): Call aarch64_init_memtag_builtins.
(aarch64_expand_builtin_memtag): New.
(aarch64_general_expand_builtin): Call aarch64_expand_builtin_memtag.
(AARCH64_BUILTIN_SUBCODE): New macro.
(aarch64_resolve_overloaded_memtag): New.
(aarch64_resolve_overloaded_builtin_general): New. Call
aarch64_resolve_overloaded_memtag to handle overloaded MTE builtins.
* config/aarch64/aarch64-c.c (aarch64_update_cpp_builtins): Define
__ARM_FEATURE_MEMORY_TAGGING when enabled.
(aarch64_resolve_overloaded_builtin): Call
aarch64_resolve_overloaded_builtin_general.
* config/aarch64/aarch64-protos.h
(aarch64_resolve_overloaded_builtin_general): New declaration.
* config/aarch64/aarch64.h (AARCH64_ISA_MEMTAG): New macro.
(TARGET_MEMTAG): Likewise.
* config/aarch64/aarch64.md (UNSPEC_GEN_TAG): New unspec.
(UNSPEC_GEN_TAG_RND, and UNSPEC_TAG_SPACE): Likewise.
(irg, gmi, subp, addg, ldg, stg): New instructions.
* config/aarch64/arm_acle.h (__arm_mte_create_random_tag): New macro.
(__arm_mte_exclude_tag, __arm_mte_ptrdiff): Likewise.
(__arm_mte_increment_tag, __arm_mte_set_tag): Likewise.
(__arm_mte_get_tag): Likewise.
* config/aarch64/predicates.md (aarch64_memtag_tag_offset): New.
(aarch64_granule16_uimm6, aarch64_granule16_simm9): New.
* config/arm/types.md (memtag): New.
* doc/invoke.texi (-memtag): Update description.
2019-11-19 Dennis Zhang <dennis.zhang@arm.com>
* gcc.target/aarch64/acle/memtag_1.c: New test.
* gcc.target/aarch64/acle/memtag_2.c: New test.
* gcc.target/aarch64/acle/memtag_3.c: New test.
From-SVN: r278444
2019-11-19 14:43:39 +01:00
|
|
|
|
|
|
|
if (TARGET_MEMTAG)
|
|
|
|
aarch64_init_memtag_builtins ();
|
2012-10-23 19:02:30 +02:00
|
|
|
}
|
|
|
|
|
[AArch64] Split built-in function codes into major and minor codes
It was easier to add the SVE ACLE support without enumerating every
function at build time. This in turn meant that it was easier if the
SVE builtins occupied a distinct numberspace from the existing AArch64
ones, which *are* enumerated at build time. This patch therefore
divides the built-in functions codes into "major" and "minor" codes.
At present the major code is just "general", but the SVE patch will add
"SVE" as well.
Also, it was convenient to put the SVE ACLE support in its own file,
so the patch makes aarch64.c provide the frontline target hooks directly,
forwarding to the other files for the real work.
The reason for organising the files this way is that aarch64.c needs
to define the target hook macros whatever happens, and having aarch64.c
macros forward to aarch64-builtins.c functions and aarch64-bulitins.c
functions forward to the SVE file seemed a bit indirect. Doing things
the way the patch does them puts aarch64-builtins.c and the SVE code on
more of an equal footing.
The aarch64_(general_)gimple_fold_builtin change is mostly just
reindentation.
2019-09-27 Richard Sandiford <richard.sandiford@arm.com>
gcc/
* config/aarch64/aarch64-protos.h (aarch64_builtin_class): New enum.
(AARCH64_BUILTIN_SHIFT, AARCH64_BUILTIN_CLASS): New constants.
(aarch64_gimple_fold_builtin, aarch64_mangle_builtin_type)
(aarch64_fold_builtin, aarch64_init_builtins, aarch64_expand_builtin):
(aarch64_builtin_decl, aarch64_builtin_rsqrt): Delete.
(aarch64_general_mangle_builtin_type, aarch64_general_init_builtins):
(aarch64_general_fold_builtin, aarch64_general_gimple_fold_builtin):
(aarch64_general_expand_builtin, aarch64_general_builtin_decl):
(aarch64_general_builtin_rsqrt): Declare.
* config/aarch64/aarch64-builtins.c (aarch64_general_add_builtin):
New function.
(aarch64_mangle_builtin_type): Rename to...
(aarch64_general_mangle_builtin_type): ...this.
(aarch64_init_fcmla_laneq_builtins, aarch64_init_simd_builtins)
(aarch64_init_crc32_builtins, aarch64_init_builtin_rsqrt)
(aarch64_init_pauth_hint_builtins, aarch64_init_tme_builtins): Use
aarch64_general_add_builtin instead of add_builtin_function.
(aarch64_init_builtins): Rename to...
(aarch64_general_init_builtins): ...this. Use
aarch64_general_add_builtin instead of add_builtin_function.
(aarch64_builtin_decl): Rename to...
(aarch64_general_builtin_decl): ...this and remove the unused
arguments.
(aarch64_expand_builtin): Rename to...
(aarch64_general_expand_builtin): ...this and remove the unused
arguments.
(aarch64_builtin_rsqrt): Rename to...
(aarch64_general_builtin_rsqrt): ...this.
(aarch64_fold_builtin): Rename to...
(aarch64_general_fold_builtin): ...this. Take the function subcode
and return type as arguments. Remove the "ignored" argument.
(aarch64_gimple_fold_builtin): Rename to...
(aarch64_general_gimple_fold_builtin): ...this. Take the function
subcode and gcall as arguments, and return the new function call.
* config/aarch64/aarch64.c (aarch64_init_builtins)
(aarch64_fold_builtin, aarch64_gimple_fold_builtin)
(aarch64_expand_builtin, aarch64_builtin_decl): New functions.
(aarch64_builtin_reciprocal): Call aarch64_general_builtin_rsqrt
instead of aarch64_builtin_rsqrt.
(aarch64_mangle_type): Call aarch64_general_mangle_builtin_type
instead of aarch64_mangle_builtin_type.
From-SVN: r276177
2019-09-27 10:47:21 +02:00
|
|
|
/* Implement TARGET_BUILTIN_DECL for the AARCH64_BUILTIN_GENERAL group. */
|
2012-11-26 18:48:13 +01:00
|
|
|
tree
|
[AArch64] Split built-in function codes into major and minor codes
It was easier to add the SVE ACLE support without enumerating every
function at build time. This in turn meant that it was easier if the
SVE builtins occupied a distinct numberspace from the existing AArch64
ones, which *are* enumerated at build time. This patch therefore
divides the built-in functions codes into "major" and "minor" codes.
At present the major code is just "general", but the SVE patch will add
"SVE" as well.
Also, it was convenient to put the SVE ACLE support in its own file,
so the patch makes aarch64.c provide the frontline target hooks directly,
forwarding to the other files for the real work.
The reason for organising the files this way is that aarch64.c needs
to define the target hook macros whatever happens, and having aarch64.c
macros forward to aarch64-builtins.c functions and aarch64-bulitins.c
functions forward to the SVE file seemed a bit indirect. Doing things
the way the patch does them puts aarch64-builtins.c and the SVE code on
more of an equal footing.
The aarch64_(general_)gimple_fold_builtin change is mostly just
reindentation.
2019-09-27 Richard Sandiford <richard.sandiford@arm.com>
gcc/
* config/aarch64/aarch64-protos.h (aarch64_builtin_class): New enum.
(AARCH64_BUILTIN_SHIFT, AARCH64_BUILTIN_CLASS): New constants.
(aarch64_gimple_fold_builtin, aarch64_mangle_builtin_type)
(aarch64_fold_builtin, aarch64_init_builtins, aarch64_expand_builtin):
(aarch64_builtin_decl, aarch64_builtin_rsqrt): Delete.
(aarch64_general_mangle_builtin_type, aarch64_general_init_builtins):
(aarch64_general_fold_builtin, aarch64_general_gimple_fold_builtin):
(aarch64_general_expand_builtin, aarch64_general_builtin_decl):
(aarch64_general_builtin_rsqrt): Declare.
* config/aarch64/aarch64-builtins.c (aarch64_general_add_builtin):
New function.
(aarch64_mangle_builtin_type): Rename to...
(aarch64_general_mangle_builtin_type): ...this.
(aarch64_init_fcmla_laneq_builtins, aarch64_init_simd_builtins)
(aarch64_init_crc32_builtins, aarch64_init_builtin_rsqrt)
(aarch64_init_pauth_hint_builtins, aarch64_init_tme_builtins): Use
aarch64_general_add_builtin instead of add_builtin_function.
(aarch64_init_builtins): Rename to...
(aarch64_general_init_builtins): ...this. Use
aarch64_general_add_builtin instead of add_builtin_function.
(aarch64_builtin_decl): Rename to...
(aarch64_general_builtin_decl): ...this and remove the unused
arguments.
(aarch64_expand_builtin): Rename to...
(aarch64_general_expand_builtin): ...this and remove the unused
arguments.
(aarch64_builtin_rsqrt): Rename to...
(aarch64_general_builtin_rsqrt): ...this.
(aarch64_fold_builtin): Rename to...
(aarch64_general_fold_builtin): ...this. Take the function subcode
and return type as arguments. Remove the "ignored" argument.
(aarch64_gimple_fold_builtin): Rename to...
(aarch64_general_gimple_fold_builtin): ...this. Take the function
subcode and gcall as arguments, and return the new function call.
* config/aarch64/aarch64.c (aarch64_init_builtins)
(aarch64_fold_builtin, aarch64_gimple_fold_builtin)
(aarch64_expand_builtin, aarch64_builtin_decl): New functions.
(aarch64_builtin_reciprocal): Call aarch64_general_builtin_rsqrt
instead of aarch64_builtin_rsqrt.
(aarch64_mangle_type): Call aarch64_general_mangle_builtin_type
instead of aarch64_mangle_builtin_type.
From-SVN: r276177
2019-09-27 10:47:21 +02:00
|
|
|
aarch64_general_builtin_decl (unsigned code, bool)
|
2012-11-26 18:48:13 +01:00
|
|
|
{
|
|
|
|
if (code >= AARCH64_BUILTIN_MAX)
|
|
|
|
return error_mark_node;
|
|
|
|
|
|
|
|
return aarch64_builtin_decls[code];
|
|
|
|
}
|
|
|
|
|
2012-10-23 19:02:30 +02:00
|
|
|
typedef enum
|
|
|
|
{
|
|
|
|
SIMD_ARG_COPY_TO_REG,
|
|
|
|
SIMD_ARG_CONSTANT,
|
Add bounds checking to vqdm*_lane intrinsics via a qualifier that also flips endianness
gcc/:
* config/aarch64/aarch64.c (aarch64_simd_lane_bounds): Display indices.
* config/aarch64/aarch64-builtins.c (enum aarch64_type_qualifiers): Add
qualifier_lane_index.
(aarch64_types_ternop_lane_qualifiers, TYPES_TERNOP_LANE): Rename to...
(aarch64_types_quadop_lane_qualifiers, TYPES_QUADOP_LANE): ...these.
(aarch64_types_ternop_lane_qualifiers, TYPES_TERNOP_LANE): New.
(aarch64_types_getlane_qualifiers): Rename to...
(aarch64_types_binop_imm_qualifiers): ...this.
(TYPES_SHIFTIMM): Follow renaming.
(TYPES_GETLANE): Rename to...
(TYPE_GETREG): ...this.
(aarch64_types_setlane_qualifiers): Rename to...
(aarch64_type_ternop_imm_qualifiers): ...this.
(TYPES_SHIFTINSERT, TYPES_SHIFTACC): Follow renaming.
(TYPES_SETLANE): Follow renaming above, and rename self to...
(TYPE_SETREG): ...this.
(enum builtin_simd_arg): Add SIMD_ARG_LANE_INDEX.
(aarch64_simd_expand_args): Add range check and endianness-flip.
(aarch64_simd_expand_builtin): Add mapping for qualifier_lane_index.
* config/aarch64/aarch64-simd.md
(aarch64_sq<r>dmulh_lane<mode>_internal *2): Rename to...
(aarch64_sq<r>dmulh_lane<mode>): ...this, and remove lane bounds check.
(aarch64_sqdmulh_lane<mode> *2, aarch64_sqrdmulh_lane<mode> *2): Delete.
(aarch64_sq<r>dmulh_laneq<mode>_internal): Rename to...
(aarch64_sq<r>dmulh_lane<mode>): ...this.
(aarch64_sqdml<SBINQOPS:as>l_lane<mode>_internal *2): Rename to...
(aarch64_sqdml<SBINQOPS:as>l_lane<mode>): ...this.
(aarch64_sqdml<SBINQOPS:as>l_laneq<mode>_internal *2): Rename to...
(aarch64_sqdml<SBINQOPS:as>l_laneq<mode>): ...this.
(aarch64_sqdmull_lane<mode>_internal *2): Rename to...
(aarch64_sqdmull_lane<mode>): ...this.
(aarch64_sqdmull_laneq<mode>_internal *2): Rename to...
(aarch64_sqdmull_laneq<mode>): ...this.
(aarch64_sqdmulh_laneq<mode>, aarch64_sqrdmulh_laneq<mode>,
(aarch64_sqdmlal_lane<mode>, aarch64_sqdmlal_laneq<mode>,
aarch64_sqdmlsl_lane<mode>, aarch64_sqdmlsl_laneq<mode>,
aarch64_sqdmull_lane<mode>, aarch64_sqdmull_laneq<mode>): Delete.
(aarch64_sqdmlal2_lane<mode>, aarch64_sqdmlal2_laneq<mode>,
aarch64_sqdmlsl2_lane<mode>, aarch64_sqdmlsl2_laneq<mode>,
aarch64_sqdmull2_lane<mode>, aarch64_sqdmull2_laneq<mode>): Remove
bounds check and lane flip.
* config/aarch64/aarch64-simd-builtins.def (be_checked_get_lane,
get_dregoi, get_dregci, getdregxi, get_qregoi,get_qregci, get_qregxi,
set_qregoi, set_qregci, set_qregxi): Change qualifiers to GETREG.
(sqdmlal_lane, sqdmlsl_lane, sqdmlal_laneq, sqdmlsl_laneq,
sqdmlal2_lane, sqdmlsl2_lane, sqdmlal2_laneq, sqdmlsl2_laneq): Follow
renaming of TERNOP_LANE to QUADOP_LANE.
(sqdmull_lane, sqdmull_laneq, sqdmull2_lane, sqdmull2_laneq,
sqdmulh_lane, sqdmulh_laneq, sqrdmulh_lane, sqrdmulh_laneq): Set
qualifiers to TERNOP_LANE.
gcc/testsuite/:
* gcc.target/aarch64/simd/vqdmlal_high_lane_s16_indices_1.c: New test.
* gcc.target/aarch64/simd/vqdmlal_high_lane_s32_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqdmlal_high_laneq_s16_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqdmlal_high_laneq_s32_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqdmlal_lane_s16_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqdmlal_lane_s32_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqdmlal_laneq_s16_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqdmlal_laneq_s32_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqdmlalh_lane_s16_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqdmlals_lane_s32_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqdmlsl_high_lane_s16_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqdmlsl_high_lane_s32_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqdmlsl_high_laneq_s16_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqdmlsl_high_laneq_s32_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqdmlsl_lane_s16_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqdmlsl_lane_s32_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqdmlsl_laneq_s16_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqdmlsl_laneq_s32_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqdmlslh_lane_s16_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqdmlsls_lane_s32_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqdmulh_lane_s16_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqdmulh_lane_s32_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqdmulh_laneq_s16_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqdmulh_laneq_s32_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqdmulhh_lane_s16_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqdmulhq_lane_s16_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqdmulhq_lane_s32_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqdmulhq_laneq_s16_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqdmulhq_laneq_s32_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqdmulhs_lane_s32_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqdmull_high_lane_s16_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqdmull_high_lane_s32_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqdmull_high_laneq_s16_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqdmull_high_laneq_s32_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqdmull_lane_s16_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqdmull_lane_s32_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqdmull_laneq_s16_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqdmull_laneq_s32_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqdmullh_lane_s16_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqdmulls_lane_s32_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqrdmulh_lane_s16_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqrdmulh_lane_s32_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqrdmulh_laneq_s16_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqrdmulh_laneq_s32_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqrdmulhh_lane_s16_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqrdmulhq_lane_s16_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqrdmulhq_lane_s32_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqrdmulhq_laneq_s16_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqrdmulhq_laneq_s32_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqrdmulhs_lane_s32_indices_1.c: Likewise.
From-SVN: r217440
2014-11-12 19:51:53 +01:00
|
|
|
SIMD_ARG_LANE_INDEX,
|
2015-07-22 12:44:16 +02:00
|
|
|
SIMD_ARG_STRUCT_LOAD_STORE_LANE_INDEX,
|
aarch64-builtins.c (enum aarch64_type_qualifiers): Add qualifier_lane_pair_index.
gcc/ChangeLog:
2019-01-10 Tamar Christina <tamar.christina@arm.com>
* config/aarch64/aarch64-builtins.c (enum aarch64_type_qualifiers): Add qualifier_lane_pair_index.
(emit-rtl.h): Include.
(TYPES_QUADOP_LANE_PAIR): New.
(aarch64_simd_expand_args): Use it.
(aarch64_simd_expand_builtin): Likewise.
(AARCH64_SIMD_FCMLA_LANEQ_BUILTINS, aarch64_fcmla_laneq_builtin_datum): New.
(FCMLA_LANEQ_BUILTIN, AARCH64_SIMD_FCMLA_LANEQ_BUILTIN_BASE,
AARCH64_SIMD_FCMLA_LANEQ_BUILTINS, aarch64_fcmla_lane_builtin_data,
aarch64_init_fcmla_laneq_builtins, aarch64_expand_fcmla_builtin): New.
(aarch64_init_builtins): Add aarch64_init_fcmla_laneq_builtins.
(aarch64_expand_buildin): Add AARCH64_SIMD_BUILTIN_FCMLA_LANEQ0_V2SF,
AARCH64_SIMD_BUILTIN_FCMLA_LANEQ90_V2SF, AARCH64_SIMD_BUILTIN_FCMLA_LANEQ180_V2SF,
AARCH64_SIMD_BUILTIN_FCMLA_LANEQ2700_V2SF, AARCH64_SIMD_BUILTIN_FCMLA_LANEQ0_V4HF,
AARCH64_SIMD_BUILTIN_FCMLA_LANEQ90_V4HF, AARCH64_SIMD_BUILTIN_FCMLA_LANEQ180_V4HF,
AARCH64_SIMD_BUILTIN_FCMLA_LANEQ270_V4HF.
* config/aarch64/iterators.md (FCMLA_maybe_lane): New.
* config/aarch64/aarch64-c.c (aarch64_update_cpp_builtins): Add __ARM_FEATURE_COMPLEX.
* config/aarch64/aarch64-simd-builtins.def (fcadd90, fcadd270, fcmla0, fcmla90,
fcmla180, fcmla270, fcmla_lane0, fcmla_lane90, fcmla_lane180, fcmla_lane270,
fcmla_laneq0, fcmla_laneq90, fcmla_laneq180, fcmla_laneq270,
fcmlaq_lane0, fcmlaq_lane90, fcmlaq_lane180, fcmlaq_lane270): New.
* config/aarch64/aarch64-simd.md (aarch64_fcmla_lane<rot><mode>,
aarch64_fcmla_laneq<rot>v4hf, aarch64_fcmlaq_lane<rot><mode>,aarch64_fcadd<rot><mode>,
aarch64_fcmla<rot><mode>): New.
* config/aarch64/arm_neon.h:
(vcadd_rot90_f16): New.
(vcaddq_rot90_f16): New.
(vcadd_rot270_f16): New.
(vcaddq_rot270_f16): New.
(vcmla_f16): New.
(vcmlaq_f16): New.
(vcmla_lane_f16): New.
(vcmla_laneq_f16): New.
(vcmlaq_lane_f16): New.
(vcmlaq_rot90_lane_f16): New.
(vcmla_rot90_laneq_f16): New.
(vcmla_rot90_lane_f16): New.
(vcmlaq_rot90_f16): New.
(vcmla_rot90_f16): New.
(vcmlaq_laneq_f16): New.
(vcmla_rot180_laneq_f16): New.
(vcmla_rot180_lane_f16): New.
(vcmlaq_rot180_f16): New.
(vcmla_rot180_f16): New.
(vcmlaq_rot90_laneq_f16): New.
(vcmlaq_rot270_laneq_f16): New.
(vcmlaq_rot270_lane_f16): New.
(vcmla_rot270_laneq_f16): New.
(vcmlaq_rot270_f16): New.
(vcmla_rot270_f16): New.
(vcmlaq_rot180_laneq_f16): New.
(vcmlaq_rot180_lane_f16): New.
(vcmla_rot270_lane_f16): New.
(vcadd_rot90_f32): New.
(vcaddq_rot90_f32): New.
(vcaddq_rot90_f64): New.
(vcadd_rot270_f32): New.
(vcaddq_rot270_f32): New.
(vcaddq_rot270_f64): New.
(vcmla_f32): New.
(vcmlaq_f32): New.
(vcmlaq_f64): New.
(vcmla_lane_f32): New.
(vcmla_laneq_f32): New.
(vcmlaq_lane_f32): New.
(vcmlaq_laneq_f32): New.
(vcmla_rot90_f32): New.
(vcmlaq_rot90_f32): New.
(vcmlaq_rot90_f64): New.
(vcmla_rot90_lane_f32): New.
(vcmla_rot90_laneq_f32): New.
(vcmlaq_rot90_lane_f32): New.
(vcmlaq_rot90_laneq_f32): New.
(vcmla_rot180_f32): New.
(vcmlaq_rot180_f32): New.
(vcmlaq_rot180_f64): New.
(vcmla_rot180_lane_f32): New.
(vcmla_rot180_laneq_f32): New.
(vcmlaq_rot180_lane_f32): New.
(vcmlaq_rot180_laneq_f32): New.
(vcmla_rot270_f32): New.
(vcmlaq_rot270_f32): New.
(vcmlaq_rot270_f64): New.
(vcmla_rot270_lane_f32): New.
(vcmla_rot270_laneq_f32): New.
(vcmlaq_rot270_lane_f32): New.
(vcmlaq_rot270_laneq_f32): New.
* config/aarch64/aarch64.h (TARGET_COMPLEX): New.
* config/aarch64/iterators.md (UNSPEC_FCADD90, UNSPEC_FCADD270,
UNSPEC_FCMLA, UNSPEC_FCMLA90, UNSPEC_FCMLA180, UNSPEC_FCMLA270): New.
(FCADD, FCMLA): New.
(rot): New.
* config/arm/types.md (neon_fcadd, neon_fcmla): New.
gcc/testsuite/ChangeLog:
2019-01-10 Tamar Christina <tamar.christina@arm.com>
* gcc.target/aarch64/advsimd-intrinsics/vector-complex.c: New test.
* gcc.target/aarch64/advsimd-intrinsics/vector-complex_f16.c: New test.
From-SVN: r267795
2019-01-10 04:30:59 +01:00
|
|
|
SIMD_ARG_LANE_PAIR_INDEX,
|
2020-01-16 15:20:48 +01:00
|
|
|
SIMD_ARG_LANE_QUADTUP_INDEX,
|
2012-10-23 19:02:30 +02:00
|
|
|
SIMD_ARG_STOP
|
|
|
|
} builtin_simd_arg;
|
|
|
|
|
2015-08-04 12:39:42 +02:00
|
|
|
|
2012-10-23 19:02:30 +02:00
|
|
|
static rtx
|
|
|
|
aarch64_simd_expand_args (rtx target, int icode, int have_retval,
|
2015-07-22 12:44:16 +02:00
|
|
|
tree exp, builtin_simd_arg *args,
|
2017-07-05 17:29:27 +02:00
|
|
|
machine_mode builtin_mode)
|
2012-10-23 19:02:30 +02:00
|
|
|
{
|
|
|
|
rtx pat;
|
2014-11-24 16:15:20 +01:00
|
|
|
rtx op[SIMD_MAX_BUILTIN_ARGS + 1]; /* First element for result operand. */
|
|
|
|
int opc = 0;
|
|
|
|
|
|
|
|
if (have_retval)
|
|
|
|
{
|
|
|
|
machine_mode tmode = insn_data[icode].operand[0].mode;
|
|
|
|
if (!target
|
2012-10-23 19:02:30 +02:00
|
|
|
|| GET_MODE (target) != tmode
|
2014-11-24 16:15:20 +01:00
|
|
|
|| !(*insn_data[icode].operand[0].predicate) (target, tmode))
|
|
|
|
target = gen_reg_rtx (tmode);
|
|
|
|
op[opc++] = target;
|
|
|
|
}
|
2012-10-23 19:02:30 +02:00
|
|
|
|
|
|
|
for (;;)
|
|
|
|
{
|
2014-11-24 16:15:20 +01:00
|
|
|
builtin_simd_arg thisarg = args[opc - have_retval];
|
2012-10-23 19:02:30 +02:00
|
|
|
|
|
|
|
if (thisarg == SIMD_ARG_STOP)
|
|
|
|
break;
|
|
|
|
else
|
|
|
|
{
|
2014-11-24 16:15:20 +01:00
|
|
|
tree arg = CALL_EXPR_ARG (exp, opc - have_retval);
|
2017-07-05 17:29:27 +02:00
|
|
|
machine_mode mode = insn_data[icode].operand[opc].mode;
|
2014-11-24 16:15:20 +01:00
|
|
|
op[opc] = expand_normal (arg);
|
2012-10-23 19:02:30 +02:00
|
|
|
|
|
|
|
switch (thisarg)
|
|
|
|
{
|
|
|
|
case SIMD_ARG_COPY_TO_REG:
|
2014-11-24 16:15:20 +01:00
|
|
|
if (POINTER_TYPE_P (TREE_TYPE (arg)))
|
|
|
|
op[opc] = convert_memory_address (Pmode, op[opc]);
|
|
|
|
/*gcc_assert (GET_MODE (op[opc]) == mode); */
|
|
|
|
if (!(*insn_data[icode].operand[opc].predicate)
|
|
|
|
(op[opc], mode))
|
|
|
|
op[opc] = copy_to_mode_reg (mode, op[opc]);
|
2012-10-23 19:02:30 +02:00
|
|
|
break;
|
|
|
|
|
2015-07-22 12:44:16 +02:00
|
|
|
case SIMD_ARG_STRUCT_LOAD_STORE_LANE_INDEX:
|
|
|
|
gcc_assert (opc > 1);
|
|
|
|
if (CONST_INT_P (op[opc]))
|
|
|
|
{
|
[AArch64] Set NUM_POLY_INT_COEFFS to 2
This patch switches the AArch64 port to use 2 poly_int coefficients
and updates code as necessary to keep it compiling.
One potentially-significant change is to
aarch64_hard_regno_caller_save_mode. The old implementation
was written in a pretty conservative way: it changed the default
behaviour for single-register values, but used the default handling
for multi-register values.
I don't think that's necessary, since the interesting cases for this
macro are usually the single-register ones. Multi-register modes take
up the whole of the constituent registers and the move patterns for all
multi-register modes should be equally good.
Using the original mode for multi-register cases stops us from using
SVE modes to spill multi-register NEON values. This was caught by
gcc.c-torture/execute/pr47538.c.
Also, aarch64_shift_truncation_mask used GET_MODE_BITSIZE - 1.
GET_MODE_UNIT_BITSIZE - 1 is equivalent for the cases that it handles
(which are all scalars), and I think it's more obvious, since if we ever
do use this for elementwise shifts of vector modes, the mask will depend
on the number of bits in each element rather than the number of bits in
the whole vector.
2018-01-11 Richard Sandiford <richard.sandiford@linaro.org>
Alan Hayward <alan.hayward@arm.com>
David Sherwood <david.sherwood@arm.com>
gcc/
* config/aarch64/aarch64-modes.def (NUM_POLY_INT_COEFFS): Set to 2.
* config/aarch64/aarch64-protos.h (aarch64_initial_elimination_offset):
Return a poly_int64 rather than a HOST_WIDE_INT.
(aarch64_offset_7bit_signed_scaled_p): Take the offset as a poly_int64
rather than a HOST_WIDE_INT.
* config/aarch64/aarch64.h (aarch64_frame): Protect with
HAVE_POLY_INT_H rather than HOST_WIDE_INT. Change locals_offset,
hard_fp_offset, frame_size, initial_adjust, callee_offset and
final_offset from HOST_WIDE_INT to poly_int64.
* config/aarch64/aarch64-builtins.c (aarch64_simd_expand_args): Use
to_constant when getting the number of units in an Advanced SIMD
mode.
(aarch64_builtin_vectorized_function): Check for a constant number
of units.
* config/aarch64/aarch64-simd.md (mov<mode>): Handle polynomial
GET_MODE_SIZE.
(aarch64_ld<VSTRUCT:nregs>_lane<VALLDIF:mode>): Use the nunits
attribute instead of GET_MODE_NUNITS.
* config/aarch64/aarch64.c (aarch64_hard_regno_nregs)
(aarch64_class_max_nregs): Use the constant_lowest_bound of the
GET_MODE_SIZE for fixed-size registers.
(aarch64_const_vec_all_same_in_range_p): Use const_vec_duplicate_p.
(aarch64_hard_regno_call_part_clobbered, aarch64_classify_index)
(aarch64_mode_valid_for_sched_fusion_p, aarch64_classify_address)
(aarch64_legitimize_address_displacement, aarch64_secondary_reload)
(aarch64_print_operand, aarch64_print_address_internal)
(aarch64_address_cost, aarch64_rtx_costs, aarch64_register_move_cost)
(aarch64_short_vector_p, aapcs_vfp_sub_candidate)
(aarch64_simd_attr_length_rglist, aarch64_operands_ok_for_ldpstp):
Handle polynomial GET_MODE_SIZE.
(aarch64_hard_regno_caller_save_mode): Likewise. Return modes
wider than SImode without modification.
(tls_symbolic_operand_type): Use strip_offset instead of split_const.
(aarch64_pass_by_reference, aarch64_layout_arg, aarch64_pad_reg_upward)
(aarch64_gimplify_va_arg_expr): Assert that we don't yet handle
passing and returning SVE modes.
(aarch64_function_value, aarch64_layout_arg): Use gen_int_mode
rather than GEN_INT.
(aarch64_emit_probe_stack_range): Take the size as a poly_int64
rather than a HOST_WIDE_INT, but call sorry if it isn't constant.
(aarch64_allocate_and_probe_stack_space): Likewise.
(aarch64_layout_frame): Cope with polynomial offsets.
(aarch64_save_callee_saves, aarch64_restore_callee_saves): Take the
start_offset as a poly_int64 rather than a HOST_WIDE_INT. Track
polynomial offsets.
(offset_9bit_signed_unscaled_p, offset_12bit_unsigned_scaled_p)
(aarch64_offset_7bit_signed_scaled_p): Take the offset as a
poly_int64 rather than a HOST_WIDE_INT.
(aarch64_get_separate_components, aarch64_process_components)
(aarch64_expand_prologue, aarch64_expand_epilogue)
(aarch64_use_return_insn_p): Handle polynomial frame offsets.
(aarch64_anchor_offset): New function, split out from...
(aarch64_legitimize_address): ...here.
(aarch64_builtin_vectorization_cost): Handle polynomial
TYPE_VECTOR_SUBPARTS.
(aarch64_simd_check_vect_par_cnst_half): Handle polynomial
GET_MODE_NUNITS.
(aarch64_simd_make_constant, aarch64_expand_vector_init): Get the
number of elements from the PARALLEL rather than the mode.
(aarch64_shift_truncation_mask): Use GET_MODE_UNIT_BITSIZE
rather than GET_MODE_BITSIZE.
(aarch64_evpc_trn, aarch64_evpc_uzp, aarch64_evpc_ext)
(aarch64_evpc_rev, aarch64_evpc_dup, aarch64_evpc_zip)
(aarch64_expand_vec_perm_const_1): Handle polynomial
d->perm.length () and d->perm elements.
(aarch64_evpc_tbl): Likewise. Use nelt rather than GET_MODE_NUNITS.
Apply to_constant to d->perm elements.
(aarch64_simd_valid_immediate, aarch64_vec_fpconst_pow_of_2): Handle
polynomial CONST_VECTOR_NUNITS.
(aarch64_move_pointer): Take amount as a poly_int64 rather
than an int.
(aarch64_progress_pointer): Avoid temporary variable.
* config/aarch64/aarch64.md (aarch64_<crc_variant>): Use
the mode attribute instead of GET_MODE.
Co-Authored-By: Alan Hayward <alan.hayward@arm.com>
Co-Authored-By: David Sherwood <david.sherwood@arm.com>
From-SVN: r256533
2018-01-11 14:17:02 +01:00
|
|
|
unsigned int nunits
|
|
|
|
= GET_MODE_NUNITS (builtin_mode).to_constant ();
|
|
|
|
aarch64_simd_lane_bounds (op[opc], 0, nunits, exp);
|
2015-07-22 12:44:16 +02:00
|
|
|
/* Keep to GCC-vector-extension lane indices in the RTL. */
|
[AArch64] Add an endian_lane_rtx helper routine
Later patches turn the number of vector units into a poly_int.
We deliberately don't support applying GEN_INT to those (except
in target code that doesn't distinguish between poly_ints and normal
constants); gen_int_mode needs to be used instead.
This patch therefore replaces instances of:
GEN_INT (ENDIAN_LANE_N (builtin_mode, INTVAL (op[opc])))
with uses of a new endian_lane_rtx function.
2017-11-06 Richard Sandiford <richard.sandiford@linaro.org>
Alan Hayward <alan.hayward@arm.com>
David Sherwood <david.sherwood@arm.com>
gcc/
* config/aarch64/aarch64-protos.h (aarch64_endian_lane_rtx): Declare.
* config/aarch64/aarch64.c (aarch64_endian_lane_rtx): New function.
* config/aarch64/aarch64.h (ENDIAN_LANE_N): Take the number
of units rather than the mode.
* config/aarch64/iterators.md (nunits): New mode attribute.
* config/aarch64/aarch64-builtins.c (aarch64_simd_expand_args):
Use aarch64_endian_lane_rtx instead of GEN_INT (ENDIAN_LANE_N ...).
* config/aarch64/aarch64-simd.md (aarch64_dup_lane<mode>)
(aarch64_dup_lane_<vswap_width_name><mode>, *aarch64_mul3_elt<mode>)
(*aarch64_mul3_elt_<vswap_width_name><mode>): Likewise.
(*aarch64_mul3_elt_to_64v2df, *aarch64_mla_elt<mode>): Likewise.
(*aarch64_mla_elt_<vswap_width_name><mode>, *aarch64_mls_elt<mode>)
(*aarch64_mls_elt_<vswap_width_name><mode>, *aarch64_fma4_elt<mode>)
(*aarch64_fma4_elt_<vswap_width_name><mode>):: Likewise.
(*aarch64_fma4_elt_to_64v2df, *aarch64_fnma4_elt<mode>): Likewise.
(*aarch64_fnma4_elt_<vswap_width_name><mode>): Likewise.
(*aarch64_fnma4_elt_to_64v2df, reduc_plus_scal_<mode>): Likewise.
(reduc_plus_scal_v4sf, reduc_<maxmin_uns>_scal_<mode>): Likewise.
(reduc_<maxmin_uns>_scal_<mode>): Likewise.
(*aarch64_get_lane_extend<GPI:mode><VDQQH:mode>): Likewise.
(*aarch64_get_lane_zero_extendsi<mode>): Likewise.
(aarch64_get_lane<mode>, *aarch64_mulx_elt_<vswap_width_name><mode>)
(*aarch64_mulx_elt<mode>, *aarch64_vgetfmulx<mode>): Likewise.
(aarch64_sq<r>dmulh_lane<mode>, aarch64_sq<r>dmulh_laneq<mode>)
(aarch64_sqrdml<SQRDMLH_AS:rdma_as>h_lane<mode>): Likewise.
(aarch64_sqrdml<SQRDMLH_AS:rdma_as>h_laneq<mode>): Likewise.
(aarch64_sqdml<SBINQOPS:as>l_lane<mode>): Likewise.
(aarch64_sqdml<SBINQOPS:as>l_laneq<mode>): Likewise.
(aarch64_sqdml<SBINQOPS:as>l2_lane<mode>_internal): Likewise.
(aarch64_sqdml<SBINQOPS:as>l2_laneq<mode>_internal): Likewise.
(aarch64_sqdmull_lane<mode>, aarch64_sqdmull_laneq<mode>): Likewise.
(aarch64_sqdmull2_lane<mode>_internal): Likewise.
(aarch64_sqdmull2_laneq<mode>_internal): Likewise.
(aarch64_vec_load_lanesoi_lane<mode>): Likewise.
(aarch64_vec_store_lanesoi_lane<mode>): Likewise.
(aarch64_vec_load_lanesci_lane<mode>): Likewise.
(aarch64_vec_store_lanesci_lane<mode>): Likewise.
(aarch64_vec_load_lanesxi_lane<mode>): Likewise.
(aarch64_vec_store_lanesxi_lane<mode>): Likewise.
(aarch64_simd_vec_set<mode>): Update use of ENDIAN_LANE_N.
(aarch64_simd_vec_setv2di): Likewise.
Reviewed-by: James Greenhalgh <james.greenhalgh@arm.com>
Co-Authored-By: Alan Hayward <alan.hayward@arm.com>
Co-Authored-By: David Sherwood <david.sherwood@arm.com>
From-SVN: r254466
2017-11-06 21:02:10 +01:00
|
|
|
op[opc] = aarch64_endian_lane_rtx (builtin_mode,
|
|
|
|
INTVAL (op[opc]));
|
2015-07-22 12:44:16 +02:00
|
|
|
}
|
|
|
|
goto constant_arg;
|
|
|
|
|
Add bounds checking to vqdm*_lane intrinsics via a qualifier that also flips endianness
gcc/:
* config/aarch64/aarch64.c (aarch64_simd_lane_bounds): Display indices.
* config/aarch64/aarch64-builtins.c (enum aarch64_type_qualifiers): Add
qualifier_lane_index.
(aarch64_types_ternop_lane_qualifiers, TYPES_TERNOP_LANE): Rename to...
(aarch64_types_quadop_lane_qualifiers, TYPES_QUADOP_LANE): ...these.
(aarch64_types_ternop_lane_qualifiers, TYPES_TERNOP_LANE): New.
(aarch64_types_getlane_qualifiers): Rename to...
(aarch64_types_binop_imm_qualifiers): ...this.
(TYPES_SHIFTIMM): Follow renaming.
(TYPES_GETLANE): Rename to...
(TYPE_GETREG): ...this.
(aarch64_types_setlane_qualifiers): Rename to...
(aarch64_type_ternop_imm_qualifiers): ...this.
(TYPES_SHIFTINSERT, TYPES_SHIFTACC): Follow renaming.
(TYPES_SETLANE): Follow renaming above, and rename self to...
(TYPE_SETREG): ...this.
(enum builtin_simd_arg): Add SIMD_ARG_LANE_INDEX.
(aarch64_simd_expand_args): Add range check and endianness-flip.
(aarch64_simd_expand_builtin): Add mapping for qualifier_lane_index.
* config/aarch64/aarch64-simd.md
(aarch64_sq<r>dmulh_lane<mode>_internal *2): Rename to...
(aarch64_sq<r>dmulh_lane<mode>): ...this, and remove lane bounds check.
(aarch64_sqdmulh_lane<mode> *2, aarch64_sqrdmulh_lane<mode> *2): Delete.
(aarch64_sq<r>dmulh_laneq<mode>_internal): Rename to...
(aarch64_sq<r>dmulh_lane<mode>): ...this.
(aarch64_sqdml<SBINQOPS:as>l_lane<mode>_internal *2): Rename to...
(aarch64_sqdml<SBINQOPS:as>l_lane<mode>): ...this.
(aarch64_sqdml<SBINQOPS:as>l_laneq<mode>_internal *2): Rename to...
(aarch64_sqdml<SBINQOPS:as>l_laneq<mode>): ...this.
(aarch64_sqdmull_lane<mode>_internal *2): Rename to...
(aarch64_sqdmull_lane<mode>): ...this.
(aarch64_sqdmull_laneq<mode>_internal *2): Rename to...
(aarch64_sqdmull_laneq<mode>): ...this.
(aarch64_sqdmulh_laneq<mode>, aarch64_sqrdmulh_laneq<mode>,
(aarch64_sqdmlal_lane<mode>, aarch64_sqdmlal_laneq<mode>,
aarch64_sqdmlsl_lane<mode>, aarch64_sqdmlsl_laneq<mode>,
aarch64_sqdmull_lane<mode>, aarch64_sqdmull_laneq<mode>): Delete.
(aarch64_sqdmlal2_lane<mode>, aarch64_sqdmlal2_laneq<mode>,
aarch64_sqdmlsl2_lane<mode>, aarch64_sqdmlsl2_laneq<mode>,
aarch64_sqdmull2_lane<mode>, aarch64_sqdmull2_laneq<mode>): Remove
bounds check and lane flip.
* config/aarch64/aarch64-simd-builtins.def (be_checked_get_lane,
get_dregoi, get_dregci, getdregxi, get_qregoi,get_qregci, get_qregxi,
set_qregoi, set_qregci, set_qregxi): Change qualifiers to GETREG.
(sqdmlal_lane, sqdmlsl_lane, sqdmlal_laneq, sqdmlsl_laneq,
sqdmlal2_lane, sqdmlsl2_lane, sqdmlal2_laneq, sqdmlsl2_laneq): Follow
renaming of TERNOP_LANE to QUADOP_LANE.
(sqdmull_lane, sqdmull_laneq, sqdmull2_lane, sqdmull2_laneq,
sqdmulh_lane, sqdmulh_laneq, sqrdmulh_lane, sqrdmulh_laneq): Set
qualifiers to TERNOP_LANE.
gcc/testsuite/:
* gcc.target/aarch64/simd/vqdmlal_high_lane_s16_indices_1.c: New test.
* gcc.target/aarch64/simd/vqdmlal_high_lane_s32_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqdmlal_high_laneq_s16_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqdmlal_high_laneq_s32_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqdmlal_lane_s16_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqdmlal_lane_s32_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqdmlal_laneq_s16_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqdmlal_laneq_s32_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqdmlalh_lane_s16_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqdmlals_lane_s32_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqdmlsl_high_lane_s16_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqdmlsl_high_lane_s32_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqdmlsl_high_laneq_s16_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqdmlsl_high_laneq_s32_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqdmlsl_lane_s16_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqdmlsl_lane_s32_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqdmlsl_laneq_s16_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqdmlsl_laneq_s32_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqdmlslh_lane_s16_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqdmlsls_lane_s32_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqdmulh_lane_s16_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqdmulh_lane_s32_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqdmulh_laneq_s16_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqdmulh_laneq_s32_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqdmulhh_lane_s16_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqdmulhq_lane_s16_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqdmulhq_lane_s32_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqdmulhq_laneq_s16_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqdmulhq_laneq_s32_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqdmulhs_lane_s32_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqdmull_high_lane_s16_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqdmull_high_lane_s32_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqdmull_high_laneq_s16_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqdmull_high_laneq_s32_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqdmull_lane_s16_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqdmull_lane_s32_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqdmull_laneq_s16_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqdmull_laneq_s32_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqdmullh_lane_s16_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqdmulls_lane_s32_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqrdmulh_lane_s16_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqrdmulh_lane_s32_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqrdmulh_laneq_s16_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqrdmulh_laneq_s32_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqrdmulhh_lane_s16_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqrdmulhq_lane_s16_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqrdmulhq_lane_s32_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqrdmulhq_laneq_s16_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqrdmulhq_laneq_s32_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqrdmulhs_lane_s32_indices_1.c: Likewise.
From-SVN: r217440
2014-11-12 19:51:53 +01:00
|
|
|
case SIMD_ARG_LANE_INDEX:
|
|
|
|
/* Must be a previous operand into which this is an index. */
|
2014-11-24 16:15:20 +01:00
|
|
|
gcc_assert (opc > 0);
|
|
|
|
if (CONST_INT_P (op[opc]))
|
Add bounds checking to vqdm*_lane intrinsics via a qualifier that also flips endianness
gcc/:
* config/aarch64/aarch64.c (aarch64_simd_lane_bounds): Display indices.
* config/aarch64/aarch64-builtins.c (enum aarch64_type_qualifiers): Add
qualifier_lane_index.
(aarch64_types_ternop_lane_qualifiers, TYPES_TERNOP_LANE): Rename to...
(aarch64_types_quadop_lane_qualifiers, TYPES_QUADOP_LANE): ...these.
(aarch64_types_ternop_lane_qualifiers, TYPES_TERNOP_LANE): New.
(aarch64_types_getlane_qualifiers): Rename to...
(aarch64_types_binop_imm_qualifiers): ...this.
(TYPES_SHIFTIMM): Follow renaming.
(TYPES_GETLANE): Rename to...
(TYPE_GETREG): ...this.
(aarch64_types_setlane_qualifiers): Rename to...
(aarch64_type_ternop_imm_qualifiers): ...this.
(TYPES_SHIFTINSERT, TYPES_SHIFTACC): Follow renaming.
(TYPES_SETLANE): Follow renaming above, and rename self to...
(TYPE_SETREG): ...this.
(enum builtin_simd_arg): Add SIMD_ARG_LANE_INDEX.
(aarch64_simd_expand_args): Add range check and endianness-flip.
(aarch64_simd_expand_builtin): Add mapping for qualifier_lane_index.
* config/aarch64/aarch64-simd.md
(aarch64_sq<r>dmulh_lane<mode>_internal *2): Rename to...
(aarch64_sq<r>dmulh_lane<mode>): ...this, and remove lane bounds check.
(aarch64_sqdmulh_lane<mode> *2, aarch64_sqrdmulh_lane<mode> *2): Delete.
(aarch64_sq<r>dmulh_laneq<mode>_internal): Rename to...
(aarch64_sq<r>dmulh_lane<mode>): ...this.
(aarch64_sqdml<SBINQOPS:as>l_lane<mode>_internal *2): Rename to...
(aarch64_sqdml<SBINQOPS:as>l_lane<mode>): ...this.
(aarch64_sqdml<SBINQOPS:as>l_laneq<mode>_internal *2): Rename to...
(aarch64_sqdml<SBINQOPS:as>l_laneq<mode>): ...this.
(aarch64_sqdmull_lane<mode>_internal *2): Rename to...
(aarch64_sqdmull_lane<mode>): ...this.
(aarch64_sqdmull_laneq<mode>_internal *2): Rename to...
(aarch64_sqdmull_laneq<mode>): ...this.
(aarch64_sqdmulh_laneq<mode>, aarch64_sqrdmulh_laneq<mode>,
(aarch64_sqdmlal_lane<mode>, aarch64_sqdmlal_laneq<mode>,
aarch64_sqdmlsl_lane<mode>, aarch64_sqdmlsl_laneq<mode>,
aarch64_sqdmull_lane<mode>, aarch64_sqdmull_laneq<mode>): Delete.
(aarch64_sqdmlal2_lane<mode>, aarch64_sqdmlal2_laneq<mode>,
aarch64_sqdmlsl2_lane<mode>, aarch64_sqdmlsl2_laneq<mode>,
aarch64_sqdmull2_lane<mode>, aarch64_sqdmull2_laneq<mode>): Remove
bounds check and lane flip.
* config/aarch64/aarch64-simd-builtins.def (be_checked_get_lane,
get_dregoi, get_dregci, getdregxi, get_qregoi,get_qregci, get_qregxi,
set_qregoi, set_qregci, set_qregxi): Change qualifiers to GETREG.
(sqdmlal_lane, sqdmlsl_lane, sqdmlal_laneq, sqdmlsl_laneq,
sqdmlal2_lane, sqdmlsl2_lane, sqdmlal2_laneq, sqdmlsl2_laneq): Follow
renaming of TERNOP_LANE to QUADOP_LANE.
(sqdmull_lane, sqdmull_laneq, sqdmull2_lane, sqdmull2_laneq,
sqdmulh_lane, sqdmulh_laneq, sqrdmulh_lane, sqrdmulh_laneq): Set
qualifiers to TERNOP_LANE.
gcc/testsuite/:
* gcc.target/aarch64/simd/vqdmlal_high_lane_s16_indices_1.c: New test.
* gcc.target/aarch64/simd/vqdmlal_high_lane_s32_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqdmlal_high_laneq_s16_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqdmlal_high_laneq_s32_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqdmlal_lane_s16_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqdmlal_lane_s32_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqdmlal_laneq_s16_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqdmlal_laneq_s32_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqdmlalh_lane_s16_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqdmlals_lane_s32_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqdmlsl_high_lane_s16_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqdmlsl_high_lane_s32_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqdmlsl_high_laneq_s16_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqdmlsl_high_laneq_s32_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqdmlsl_lane_s16_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqdmlsl_lane_s32_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqdmlsl_laneq_s16_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqdmlsl_laneq_s32_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqdmlslh_lane_s16_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqdmlsls_lane_s32_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqdmulh_lane_s16_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqdmulh_lane_s32_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqdmulh_laneq_s16_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqdmulh_laneq_s32_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqdmulhh_lane_s16_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqdmulhq_lane_s16_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqdmulhq_lane_s32_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqdmulhq_laneq_s16_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqdmulhq_laneq_s32_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqdmulhs_lane_s32_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqdmull_high_lane_s16_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqdmull_high_lane_s32_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqdmull_high_laneq_s16_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqdmull_high_laneq_s32_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqdmull_lane_s16_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqdmull_lane_s32_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqdmull_laneq_s16_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqdmull_laneq_s32_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqdmullh_lane_s16_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqdmulls_lane_s32_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqrdmulh_lane_s16_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqrdmulh_lane_s32_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqrdmulh_laneq_s16_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqrdmulh_laneq_s32_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqrdmulhh_lane_s16_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqrdmulhq_lane_s16_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqrdmulhq_lane_s32_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqrdmulhq_laneq_s16_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqrdmulhq_laneq_s32_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqrdmulhs_lane_s32_indices_1.c: Likewise.
From-SVN: r217440
2014-11-12 19:51:53 +01:00
|
|
|
{
|
2014-11-24 16:15:20 +01:00
|
|
|
machine_mode vmode = insn_data[icode].operand[opc - 1].mode;
|
[AArch64] Set NUM_POLY_INT_COEFFS to 2
This patch switches the AArch64 port to use 2 poly_int coefficients
and updates code as necessary to keep it compiling.
One potentially-significant change is to
aarch64_hard_regno_caller_save_mode. The old implementation
was written in a pretty conservative way: it changed the default
behaviour for single-register values, but used the default handling
for multi-register values.
I don't think that's necessary, since the interesting cases for this
macro are usually the single-register ones. Multi-register modes take
up the whole of the constituent registers and the move patterns for all
multi-register modes should be equally good.
Using the original mode for multi-register cases stops us from using
SVE modes to spill multi-register NEON values. This was caught by
gcc.c-torture/execute/pr47538.c.
Also, aarch64_shift_truncation_mask used GET_MODE_BITSIZE - 1.
GET_MODE_UNIT_BITSIZE - 1 is equivalent for the cases that it handles
(which are all scalars), and I think it's more obvious, since if we ever
do use this for elementwise shifts of vector modes, the mask will depend
on the number of bits in each element rather than the number of bits in
the whole vector.
2018-01-11 Richard Sandiford <richard.sandiford@linaro.org>
Alan Hayward <alan.hayward@arm.com>
David Sherwood <david.sherwood@arm.com>
gcc/
* config/aarch64/aarch64-modes.def (NUM_POLY_INT_COEFFS): Set to 2.
* config/aarch64/aarch64-protos.h (aarch64_initial_elimination_offset):
Return a poly_int64 rather than a HOST_WIDE_INT.
(aarch64_offset_7bit_signed_scaled_p): Take the offset as a poly_int64
rather than a HOST_WIDE_INT.
* config/aarch64/aarch64.h (aarch64_frame): Protect with
HAVE_POLY_INT_H rather than HOST_WIDE_INT. Change locals_offset,
hard_fp_offset, frame_size, initial_adjust, callee_offset and
final_offset from HOST_WIDE_INT to poly_int64.
* config/aarch64/aarch64-builtins.c (aarch64_simd_expand_args): Use
to_constant when getting the number of units in an Advanced SIMD
mode.
(aarch64_builtin_vectorized_function): Check for a constant number
of units.
* config/aarch64/aarch64-simd.md (mov<mode>): Handle polynomial
GET_MODE_SIZE.
(aarch64_ld<VSTRUCT:nregs>_lane<VALLDIF:mode>): Use the nunits
attribute instead of GET_MODE_NUNITS.
* config/aarch64/aarch64.c (aarch64_hard_regno_nregs)
(aarch64_class_max_nregs): Use the constant_lowest_bound of the
GET_MODE_SIZE for fixed-size registers.
(aarch64_const_vec_all_same_in_range_p): Use const_vec_duplicate_p.
(aarch64_hard_regno_call_part_clobbered, aarch64_classify_index)
(aarch64_mode_valid_for_sched_fusion_p, aarch64_classify_address)
(aarch64_legitimize_address_displacement, aarch64_secondary_reload)
(aarch64_print_operand, aarch64_print_address_internal)
(aarch64_address_cost, aarch64_rtx_costs, aarch64_register_move_cost)
(aarch64_short_vector_p, aapcs_vfp_sub_candidate)
(aarch64_simd_attr_length_rglist, aarch64_operands_ok_for_ldpstp):
Handle polynomial GET_MODE_SIZE.
(aarch64_hard_regno_caller_save_mode): Likewise. Return modes
wider than SImode without modification.
(tls_symbolic_operand_type): Use strip_offset instead of split_const.
(aarch64_pass_by_reference, aarch64_layout_arg, aarch64_pad_reg_upward)
(aarch64_gimplify_va_arg_expr): Assert that we don't yet handle
passing and returning SVE modes.
(aarch64_function_value, aarch64_layout_arg): Use gen_int_mode
rather than GEN_INT.
(aarch64_emit_probe_stack_range): Take the size as a poly_int64
rather than a HOST_WIDE_INT, but call sorry if it isn't constant.
(aarch64_allocate_and_probe_stack_space): Likewise.
(aarch64_layout_frame): Cope with polynomial offsets.
(aarch64_save_callee_saves, aarch64_restore_callee_saves): Take the
start_offset as a poly_int64 rather than a HOST_WIDE_INT. Track
polynomial offsets.
(offset_9bit_signed_unscaled_p, offset_12bit_unsigned_scaled_p)
(aarch64_offset_7bit_signed_scaled_p): Take the offset as a
poly_int64 rather than a HOST_WIDE_INT.
(aarch64_get_separate_components, aarch64_process_components)
(aarch64_expand_prologue, aarch64_expand_epilogue)
(aarch64_use_return_insn_p): Handle polynomial frame offsets.
(aarch64_anchor_offset): New function, split out from...
(aarch64_legitimize_address): ...here.
(aarch64_builtin_vectorization_cost): Handle polynomial
TYPE_VECTOR_SUBPARTS.
(aarch64_simd_check_vect_par_cnst_half): Handle polynomial
GET_MODE_NUNITS.
(aarch64_simd_make_constant, aarch64_expand_vector_init): Get the
number of elements from the PARALLEL rather than the mode.
(aarch64_shift_truncation_mask): Use GET_MODE_UNIT_BITSIZE
rather than GET_MODE_BITSIZE.
(aarch64_evpc_trn, aarch64_evpc_uzp, aarch64_evpc_ext)
(aarch64_evpc_rev, aarch64_evpc_dup, aarch64_evpc_zip)
(aarch64_expand_vec_perm_const_1): Handle polynomial
d->perm.length () and d->perm elements.
(aarch64_evpc_tbl): Likewise. Use nelt rather than GET_MODE_NUNITS.
Apply to_constant to d->perm elements.
(aarch64_simd_valid_immediate, aarch64_vec_fpconst_pow_of_2): Handle
polynomial CONST_VECTOR_NUNITS.
(aarch64_move_pointer): Take amount as a poly_int64 rather
than an int.
(aarch64_progress_pointer): Avoid temporary variable.
* config/aarch64/aarch64.md (aarch64_<crc_variant>): Use
the mode attribute instead of GET_MODE.
Co-Authored-By: Alan Hayward <alan.hayward@arm.com>
Co-Authored-By: David Sherwood <david.sherwood@arm.com>
From-SVN: r256533
2018-01-11 14:17:02 +01:00
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|
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unsigned int nunits
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= GET_MODE_NUNITS (vmode).to_constant ();
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aarch64_simd_lane_bounds (op[opc], 0, nunits, exp);
|
Add bounds checking to vqdm*_lane intrinsics via a qualifier that also flips endianness
gcc/:
* config/aarch64/aarch64.c (aarch64_simd_lane_bounds): Display indices.
* config/aarch64/aarch64-builtins.c (enum aarch64_type_qualifiers): Add
qualifier_lane_index.
(aarch64_types_ternop_lane_qualifiers, TYPES_TERNOP_LANE): Rename to...
(aarch64_types_quadop_lane_qualifiers, TYPES_QUADOP_LANE): ...these.
(aarch64_types_ternop_lane_qualifiers, TYPES_TERNOP_LANE): New.
(aarch64_types_getlane_qualifiers): Rename to...
(aarch64_types_binop_imm_qualifiers): ...this.
(TYPES_SHIFTIMM): Follow renaming.
(TYPES_GETLANE): Rename to...
(TYPE_GETREG): ...this.
(aarch64_types_setlane_qualifiers): Rename to...
(aarch64_type_ternop_imm_qualifiers): ...this.
(TYPES_SHIFTINSERT, TYPES_SHIFTACC): Follow renaming.
(TYPES_SETLANE): Follow renaming above, and rename self to...
(TYPE_SETREG): ...this.
(enum builtin_simd_arg): Add SIMD_ARG_LANE_INDEX.
(aarch64_simd_expand_args): Add range check and endianness-flip.
(aarch64_simd_expand_builtin): Add mapping for qualifier_lane_index.
* config/aarch64/aarch64-simd.md
(aarch64_sq<r>dmulh_lane<mode>_internal *2): Rename to...
(aarch64_sq<r>dmulh_lane<mode>): ...this, and remove lane bounds check.
(aarch64_sqdmulh_lane<mode> *2, aarch64_sqrdmulh_lane<mode> *2): Delete.
(aarch64_sq<r>dmulh_laneq<mode>_internal): Rename to...
(aarch64_sq<r>dmulh_lane<mode>): ...this.
(aarch64_sqdml<SBINQOPS:as>l_lane<mode>_internal *2): Rename to...
(aarch64_sqdml<SBINQOPS:as>l_lane<mode>): ...this.
(aarch64_sqdml<SBINQOPS:as>l_laneq<mode>_internal *2): Rename to...
(aarch64_sqdml<SBINQOPS:as>l_laneq<mode>): ...this.
(aarch64_sqdmull_lane<mode>_internal *2): Rename to...
(aarch64_sqdmull_lane<mode>): ...this.
(aarch64_sqdmull_laneq<mode>_internal *2): Rename to...
(aarch64_sqdmull_laneq<mode>): ...this.
(aarch64_sqdmulh_laneq<mode>, aarch64_sqrdmulh_laneq<mode>,
(aarch64_sqdmlal_lane<mode>, aarch64_sqdmlal_laneq<mode>,
aarch64_sqdmlsl_lane<mode>, aarch64_sqdmlsl_laneq<mode>,
aarch64_sqdmull_lane<mode>, aarch64_sqdmull_laneq<mode>): Delete.
(aarch64_sqdmlal2_lane<mode>, aarch64_sqdmlal2_laneq<mode>,
aarch64_sqdmlsl2_lane<mode>, aarch64_sqdmlsl2_laneq<mode>,
aarch64_sqdmull2_lane<mode>, aarch64_sqdmull2_laneq<mode>): Remove
bounds check and lane flip.
* config/aarch64/aarch64-simd-builtins.def (be_checked_get_lane,
get_dregoi, get_dregci, getdregxi, get_qregoi,get_qregci, get_qregxi,
set_qregoi, set_qregci, set_qregxi): Change qualifiers to GETREG.
(sqdmlal_lane, sqdmlsl_lane, sqdmlal_laneq, sqdmlsl_laneq,
sqdmlal2_lane, sqdmlsl2_lane, sqdmlal2_laneq, sqdmlsl2_laneq): Follow
renaming of TERNOP_LANE to QUADOP_LANE.
(sqdmull_lane, sqdmull_laneq, sqdmull2_lane, sqdmull2_laneq,
sqdmulh_lane, sqdmulh_laneq, sqrdmulh_lane, sqrdmulh_laneq): Set
qualifiers to TERNOP_LANE.
gcc/testsuite/:
* gcc.target/aarch64/simd/vqdmlal_high_lane_s16_indices_1.c: New test.
* gcc.target/aarch64/simd/vqdmlal_high_lane_s32_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqdmlal_high_laneq_s16_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqdmlal_high_laneq_s32_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqdmlal_lane_s16_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqdmlal_lane_s32_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqdmlal_laneq_s16_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqdmlal_laneq_s32_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqdmlalh_lane_s16_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqdmlals_lane_s32_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqdmlsl_high_lane_s16_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqdmlsl_high_lane_s32_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqdmlsl_high_laneq_s16_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqdmlsl_high_laneq_s32_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqdmlsl_lane_s16_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqdmlsl_lane_s32_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqdmlsl_laneq_s16_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqdmlsl_laneq_s32_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqdmlslh_lane_s16_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqdmlsls_lane_s32_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqdmulh_lane_s16_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqdmulh_lane_s32_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqdmulh_laneq_s16_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqdmulh_laneq_s32_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqdmulhh_lane_s16_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqdmulhq_lane_s16_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqdmulhq_lane_s32_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqdmulhq_laneq_s16_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqdmulhq_laneq_s32_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqdmulhs_lane_s32_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqdmull_high_lane_s16_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqdmull_high_lane_s32_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqdmull_high_laneq_s16_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqdmull_high_laneq_s32_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqdmull_lane_s16_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqdmull_lane_s32_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqdmull_laneq_s16_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqdmull_laneq_s32_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqdmullh_lane_s16_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqdmulls_lane_s32_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqrdmulh_lane_s16_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqrdmulh_lane_s32_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqrdmulh_laneq_s16_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqrdmulh_laneq_s32_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqrdmulhh_lane_s16_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqrdmulhq_lane_s16_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqrdmulhq_lane_s32_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqrdmulhq_laneq_s16_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqrdmulhq_laneq_s32_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqrdmulhs_lane_s32_indices_1.c: Likewise.
From-SVN: r217440
2014-11-12 19:51:53 +01:00
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/* Keep to GCC-vector-extension lane indices in the RTL. */
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[AArch64] Add an endian_lane_rtx helper routine
Later patches turn the number of vector units into a poly_int.
We deliberately don't support applying GEN_INT to those (except
in target code that doesn't distinguish between poly_ints and normal
constants); gen_int_mode needs to be used instead.
This patch therefore replaces instances of:
GEN_INT (ENDIAN_LANE_N (builtin_mode, INTVAL (op[opc])))
with uses of a new endian_lane_rtx function.
2017-11-06 Richard Sandiford <richard.sandiford@linaro.org>
Alan Hayward <alan.hayward@arm.com>
David Sherwood <david.sherwood@arm.com>
gcc/
* config/aarch64/aarch64-protos.h (aarch64_endian_lane_rtx): Declare.
* config/aarch64/aarch64.c (aarch64_endian_lane_rtx): New function.
* config/aarch64/aarch64.h (ENDIAN_LANE_N): Take the number
of units rather than the mode.
* config/aarch64/iterators.md (nunits): New mode attribute.
* config/aarch64/aarch64-builtins.c (aarch64_simd_expand_args):
Use aarch64_endian_lane_rtx instead of GEN_INT (ENDIAN_LANE_N ...).
* config/aarch64/aarch64-simd.md (aarch64_dup_lane<mode>)
(aarch64_dup_lane_<vswap_width_name><mode>, *aarch64_mul3_elt<mode>)
(*aarch64_mul3_elt_<vswap_width_name><mode>): Likewise.
(*aarch64_mul3_elt_to_64v2df, *aarch64_mla_elt<mode>): Likewise.
(*aarch64_mla_elt_<vswap_width_name><mode>, *aarch64_mls_elt<mode>)
(*aarch64_mls_elt_<vswap_width_name><mode>, *aarch64_fma4_elt<mode>)
(*aarch64_fma4_elt_<vswap_width_name><mode>):: Likewise.
(*aarch64_fma4_elt_to_64v2df, *aarch64_fnma4_elt<mode>): Likewise.
(*aarch64_fnma4_elt_<vswap_width_name><mode>): Likewise.
(*aarch64_fnma4_elt_to_64v2df, reduc_plus_scal_<mode>): Likewise.
(reduc_plus_scal_v4sf, reduc_<maxmin_uns>_scal_<mode>): Likewise.
(reduc_<maxmin_uns>_scal_<mode>): Likewise.
(*aarch64_get_lane_extend<GPI:mode><VDQQH:mode>): Likewise.
(*aarch64_get_lane_zero_extendsi<mode>): Likewise.
(aarch64_get_lane<mode>, *aarch64_mulx_elt_<vswap_width_name><mode>)
(*aarch64_mulx_elt<mode>, *aarch64_vgetfmulx<mode>): Likewise.
(aarch64_sq<r>dmulh_lane<mode>, aarch64_sq<r>dmulh_laneq<mode>)
(aarch64_sqrdml<SQRDMLH_AS:rdma_as>h_lane<mode>): Likewise.
(aarch64_sqrdml<SQRDMLH_AS:rdma_as>h_laneq<mode>): Likewise.
(aarch64_sqdml<SBINQOPS:as>l_lane<mode>): Likewise.
(aarch64_sqdml<SBINQOPS:as>l_laneq<mode>): Likewise.
(aarch64_sqdml<SBINQOPS:as>l2_lane<mode>_internal): Likewise.
(aarch64_sqdml<SBINQOPS:as>l2_laneq<mode>_internal): Likewise.
(aarch64_sqdmull_lane<mode>, aarch64_sqdmull_laneq<mode>): Likewise.
(aarch64_sqdmull2_lane<mode>_internal): Likewise.
(aarch64_sqdmull2_laneq<mode>_internal): Likewise.
(aarch64_vec_load_lanesoi_lane<mode>): Likewise.
(aarch64_vec_store_lanesoi_lane<mode>): Likewise.
(aarch64_vec_load_lanesci_lane<mode>): Likewise.
(aarch64_vec_store_lanesci_lane<mode>): Likewise.
(aarch64_vec_load_lanesxi_lane<mode>): Likewise.
(aarch64_vec_store_lanesxi_lane<mode>): Likewise.
(aarch64_simd_vec_set<mode>): Update use of ENDIAN_LANE_N.
(aarch64_simd_vec_setv2di): Likewise.
Reviewed-by: James Greenhalgh <james.greenhalgh@arm.com>
Co-Authored-By: Alan Hayward <alan.hayward@arm.com>
Co-Authored-By: David Sherwood <david.sherwood@arm.com>
From-SVN: r254466
2017-11-06 21:02:10 +01:00
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op[opc] = aarch64_endian_lane_rtx (vmode, INTVAL (op[opc]));
|
Add bounds checking to vqdm*_lane intrinsics via a qualifier that also flips endianness
gcc/:
* config/aarch64/aarch64.c (aarch64_simd_lane_bounds): Display indices.
* config/aarch64/aarch64-builtins.c (enum aarch64_type_qualifiers): Add
qualifier_lane_index.
(aarch64_types_ternop_lane_qualifiers, TYPES_TERNOP_LANE): Rename to...
(aarch64_types_quadop_lane_qualifiers, TYPES_QUADOP_LANE): ...these.
(aarch64_types_ternop_lane_qualifiers, TYPES_TERNOP_LANE): New.
(aarch64_types_getlane_qualifiers): Rename to...
(aarch64_types_binop_imm_qualifiers): ...this.
(TYPES_SHIFTIMM): Follow renaming.
(TYPES_GETLANE): Rename to...
(TYPE_GETREG): ...this.
(aarch64_types_setlane_qualifiers): Rename to...
(aarch64_type_ternop_imm_qualifiers): ...this.
(TYPES_SHIFTINSERT, TYPES_SHIFTACC): Follow renaming.
(TYPES_SETLANE): Follow renaming above, and rename self to...
(TYPE_SETREG): ...this.
(enum builtin_simd_arg): Add SIMD_ARG_LANE_INDEX.
(aarch64_simd_expand_args): Add range check and endianness-flip.
(aarch64_simd_expand_builtin): Add mapping for qualifier_lane_index.
* config/aarch64/aarch64-simd.md
(aarch64_sq<r>dmulh_lane<mode>_internal *2): Rename to...
(aarch64_sq<r>dmulh_lane<mode>): ...this, and remove lane bounds check.
(aarch64_sqdmulh_lane<mode> *2, aarch64_sqrdmulh_lane<mode> *2): Delete.
(aarch64_sq<r>dmulh_laneq<mode>_internal): Rename to...
(aarch64_sq<r>dmulh_lane<mode>): ...this.
(aarch64_sqdml<SBINQOPS:as>l_lane<mode>_internal *2): Rename to...
(aarch64_sqdml<SBINQOPS:as>l_lane<mode>): ...this.
(aarch64_sqdml<SBINQOPS:as>l_laneq<mode>_internal *2): Rename to...
(aarch64_sqdml<SBINQOPS:as>l_laneq<mode>): ...this.
(aarch64_sqdmull_lane<mode>_internal *2): Rename to...
(aarch64_sqdmull_lane<mode>): ...this.
(aarch64_sqdmull_laneq<mode>_internal *2): Rename to...
(aarch64_sqdmull_laneq<mode>): ...this.
(aarch64_sqdmulh_laneq<mode>, aarch64_sqrdmulh_laneq<mode>,
(aarch64_sqdmlal_lane<mode>, aarch64_sqdmlal_laneq<mode>,
aarch64_sqdmlsl_lane<mode>, aarch64_sqdmlsl_laneq<mode>,
aarch64_sqdmull_lane<mode>, aarch64_sqdmull_laneq<mode>): Delete.
(aarch64_sqdmlal2_lane<mode>, aarch64_sqdmlal2_laneq<mode>,
aarch64_sqdmlsl2_lane<mode>, aarch64_sqdmlsl2_laneq<mode>,
aarch64_sqdmull2_lane<mode>, aarch64_sqdmull2_laneq<mode>): Remove
bounds check and lane flip.
* config/aarch64/aarch64-simd-builtins.def (be_checked_get_lane,
get_dregoi, get_dregci, getdregxi, get_qregoi,get_qregci, get_qregxi,
set_qregoi, set_qregci, set_qregxi): Change qualifiers to GETREG.
(sqdmlal_lane, sqdmlsl_lane, sqdmlal_laneq, sqdmlsl_laneq,
sqdmlal2_lane, sqdmlsl2_lane, sqdmlal2_laneq, sqdmlsl2_laneq): Follow
renaming of TERNOP_LANE to QUADOP_LANE.
(sqdmull_lane, sqdmull_laneq, sqdmull2_lane, sqdmull2_laneq,
sqdmulh_lane, sqdmulh_laneq, sqrdmulh_lane, sqrdmulh_laneq): Set
qualifiers to TERNOP_LANE.
gcc/testsuite/:
* gcc.target/aarch64/simd/vqdmlal_high_lane_s16_indices_1.c: New test.
* gcc.target/aarch64/simd/vqdmlal_high_lane_s32_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqdmlal_high_laneq_s16_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqdmlal_high_laneq_s32_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqdmlal_lane_s16_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqdmlal_lane_s32_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqdmlal_laneq_s16_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqdmlal_laneq_s32_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqdmlalh_lane_s16_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqdmlals_lane_s32_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqdmlsl_high_lane_s16_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqdmlsl_high_lane_s32_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqdmlsl_high_laneq_s16_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqdmlsl_high_laneq_s32_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqdmlsl_lane_s16_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqdmlsl_lane_s32_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqdmlsl_laneq_s16_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqdmlsl_laneq_s32_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqdmlslh_lane_s16_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqdmlsls_lane_s32_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqdmulh_lane_s16_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqdmulh_lane_s32_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqdmulh_laneq_s16_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqdmulh_laneq_s32_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqdmulhh_lane_s16_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqdmulhq_lane_s16_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqdmulhq_lane_s32_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqdmulhq_laneq_s16_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqdmulhq_laneq_s32_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqdmulhs_lane_s32_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqdmull_high_lane_s16_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqdmull_high_lane_s32_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqdmull_high_laneq_s16_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqdmull_high_laneq_s32_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqdmull_lane_s16_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqdmull_lane_s32_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqdmull_laneq_s16_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqdmull_laneq_s32_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqdmullh_lane_s16_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqdmulls_lane_s32_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqrdmulh_lane_s16_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqrdmulh_lane_s32_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqrdmulh_laneq_s16_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqrdmulh_laneq_s32_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqrdmulhh_lane_s16_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqrdmulhq_lane_s16_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqrdmulhq_lane_s32_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqrdmulhq_laneq_s16_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqrdmulhq_laneq_s32_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqrdmulhs_lane_s32_indices_1.c: Likewise.
From-SVN: r217440
2014-11-12 19:51:53 +01:00
|
|
|
}
|
aarch64-builtins.c (enum aarch64_type_qualifiers): Add qualifier_lane_pair_index.
gcc/ChangeLog:
2019-01-10 Tamar Christina <tamar.christina@arm.com>
* config/aarch64/aarch64-builtins.c (enum aarch64_type_qualifiers): Add qualifier_lane_pair_index.
(emit-rtl.h): Include.
(TYPES_QUADOP_LANE_PAIR): New.
(aarch64_simd_expand_args): Use it.
(aarch64_simd_expand_builtin): Likewise.
(AARCH64_SIMD_FCMLA_LANEQ_BUILTINS, aarch64_fcmla_laneq_builtin_datum): New.
(FCMLA_LANEQ_BUILTIN, AARCH64_SIMD_FCMLA_LANEQ_BUILTIN_BASE,
AARCH64_SIMD_FCMLA_LANEQ_BUILTINS, aarch64_fcmla_lane_builtin_data,
aarch64_init_fcmla_laneq_builtins, aarch64_expand_fcmla_builtin): New.
(aarch64_init_builtins): Add aarch64_init_fcmla_laneq_builtins.
(aarch64_expand_buildin): Add AARCH64_SIMD_BUILTIN_FCMLA_LANEQ0_V2SF,
AARCH64_SIMD_BUILTIN_FCMLA_LANEQ90_V2SF, AARCH64_SIMD_BUILTIN_FCMLA_LANEQ180_V2SF,
AARCH64_SIMD_BUILTIN_FCMLA_LANEQ2700_V2SF, AARCH64_SIMD_BUILTIN_FCMLA_LANEQ0_V4HF,
AARCH64_SIMD_BUILTIN_FCMLA_LANEQ90_V4HF, AARCH64_SIMD_BUILTIN_FCMLA_LANEQ180_V4HF,
AARCH64_SIMD_BUILTIN_FCMLA_LANEQ270_V4HF.
* config/aarch64/iterators.md (FCMLA_maybe_lane): New.
* config/aarch64/aarch64-c.c (aarch64_update_cpp_builtins): Add __ARM_FEATURE_COMPLEX.
* config/aarch64/aarch64-simd-builtins.def (fcadd90, fcadd270, fcmla0, fcmla90,
fcmla180, fcmla270, fcmla_lane0, fcmla_lane90, fcmla_lane180, fcmla_lane270,
fcmla_laneq0, fcmla_laneq90, fcmla_laneq180, fcmla_laneq270,
fcmlaq_lane0, fcmlaq_lane90, fcmlaq_lane180, fcmlaq_lane270): New.
* config/aarch64/aarch64-simd.md (aarch64_fcmla_lane<rot><mode>,
aarch64_fcmla_laneq<rot>v4hf, aarch64_fcmlaq_lane<rot><mode>,aarch64_fcadd<rot><mode>,
aarch64_fcmla<rot><mode>): New.
* config/aarch64/arm_neon.h:
(vcadd_rot90_f16): New.
(vcaddq_rot90_f16): New.
(vcadd_rot270_f16): New.
(vcaddq_rot270_f16): New.
(vcmla_f16): New.
(vcmlaq_f16): New.
(vcmla_lane_f16): New.
(vcmla_laneq_f16): New.
(vcmlaq_lane_f16): New.
(vcmlaq_rot90_lane_f16): New.
(vcmla_rot90_laneq_f16): New.
(vcmla_rot90_lane_f16): New.
(vcmlaq_rot90_f16): New.
(vcmla_rot90_f16): New.
(vcmlaq_laneq_f16): New.
(vcmla_rot180_laneq_f16): New.
(vcmla_rot180_lane_f16): New.
(vcmlaq_rot180_f16): New.
(vcmla_rot180_f16): New.
(vcmlaq_rot90_laneq_f16): New.
(vcmlaq_rot270_laneq_f16): New.
(vcmlaq_rot270_lane_f16): New.
(vcmla_rot270_laneq_f16): New.
(vcmlaq_rot270_f16): New.
(vcmla_rot270_f16): New.
(vcmlaq_rot180_laneq_f16): New.
(vcmlaq_rot180_lane_f16): New.
(vcmla_rot270_lane_f16): New.
(vcadd_rot90_f32): New.
(vcaddq_rot90_f32): New.
(vcaddq_rot90_f64): New.
(vcadd_rot270_f32): New.
(vcaddq_rot270_f32): New.
(vcaddq_rot270_f64): New.
(vcmla_f32): New.
(vcmlaq_f32): New.
(vcmlaq_f64): New.
(vcmla_lane_f32): New.
(vcmla_laneq_f32): New.
(vcmlaq_lane_f32): New.
(vcmlaq_laneq_f32): New.
(vcmla_rot90_f32): New.
(vcmlaq_rot90_f32): New.
(vcmlaq_rot90_f64): New.
(vcmla_rot90_lane_f32): New.
(vcmla_rot90_laneq_f32): New.
(vcmlaq_rot90_lane_f32): New.
(vcmlaq_rot90_laneq_f32): New.
(vcmla_rot180_f32): New.
(vcmlaq_rot180_f32): New.
(vcmlaq_rot180_f64): New.
(vcmla_rot180_lane_f32): New.
(vcmla_rot180_laneq_f32): New.
(vcmlaq_rot180_lane_f32): New.
(vcmlaq_rot180_laneq_f32): New.
(vcmla_rot270_f32): New.
(vcmlaq_rot270_f32): New.
(vcmlaq_rot270_f64): New.
(vcmla_rot270_lane_f32): New.
(vcmla_rot270_laneq_f32): New.
(vcmlaq_rot270_lane_f32): New.
(vcmlaq_rot270_laneq_f32): New.
* config/aarch64/aarch64.h (TARGET_COMPLEX): New.
* config/aarch64/iterators.md (UNSPEC_FCADD90, UNSPEC_FCADD270,
UNSPEC_FCMLA, UNSPEC_FCMLA90, UNSPEC_FCMLA180, UNSPEC_FCMLA270): New.
(FCADD, FCMLA): New.
(rot): New.
* config/arm/types.md (neon_fcadd, neon_fcmla): New.
gcc/testsuite/ChangeLog:
2019-01-10 Tamar Christina <tamar.christina@arm.com>
* gcc.target/aarch64/advsimd-intrinsics/vector-complex.c: New test.
* gcc.target/aarch64/advsimd-intrinsics/vector-complex_f16.c: New test.
From-SVN: r267795
2019-01-10 04:30:59 +01:00
|
|
|
/* If the lane index isn't a constant then error out. */
|
|
|
|
goto constant_arg;
|
|
|
|
|
|
|
|
case SIMD_ARG_LANE_PAIR_INDEX:
|
|
|
|
/* Must be a previous operand into which this is an index and
|
|
|
|
index is restricted to nunits / 2. */
|
|
|
|
gcc_assert (opc > 0);
|
|
|
|
if (CONST_INT_P (op[opc]))
|
|
|
|
{
|
|
|
|
machine_mode vmode = insn_data[icode].operand[opc - 1].mode;
|
|
|
|
unsigned int nunits
|
|
|
|
= GET_MODE_NUNITS (vmode).to_constant ();
|
|
|
|
aarch64_simd_lane_bounds (op[opc], 0, nunits / 2, exp);
|
|
|
|
/* Keep to GCC-vector-extension lane indices in the RTL. */
|
2019-01-16 19:29:00 +01:00
|
|
|
int lane = INTVAL (op[opc]);
|
|
|
|
op[opc] = gen_int_mode (ENDIAN_LANE_N (nunits / 2, lane),
|
|
|
|
SImode);
|
aarch64-builtins.c (enum aarch64_type_qualifiers): Add qualifier_lane_pair_index.
gcc/ChangeLog:
2019-01-10 Tamar Christina <tamar.christina@arm.com>
* config/aarch64/aarch64-builtins.c (enum aarch64_type_qualifiers): Add qualifier_lane_pair_index.
(emit-rtl.h): Include.
(TYPES_QUADOP_LANE_PAIR): New.
(aarch64_simd_expand_args): Use it.
(aarch64_simd_expand_builtin): Likewise.
(AARCH64_SIMD_FCMLA_LANEQ_BUILTINS, aarch64_fcmla_laneq_builtin_datum): New.
(FCMLA_LANEQ_BUILTIN, AARCH64_SIMD_FCMLA_LANEQ_BUILTIN_BASE,
AARCH64_SIMD_FCMLA_LANEQ_BUILTINS, aarch64_fcmla_lane_builtin_data,
aarch64_init_fcmla_laneq_builtins, aarch64_expand_fcmla_builtin): New.
(aarch64_init_builtins): Add aarch64_init_fcmla_laneq_builtins.
(aarch64_expand_buildin): Add AARCH64_SIMD_BUILTIN_FCMLA_LANEQ0_V2SF,
AARCH64_SIMD_BUILTIN_FCMLA_LANEQ90_V2SF, AARCH64_SIMD_BUILTIN_FCMLA_LANEQ180_V2SF,
AARCH64_SIMD_BUILTIN_FCMLA_LANEQ2700_V2SF, AARCH64_SIMD_BUILTIN_FCMLA_LANEQ0_V4HF,
AARCH64_SIMD_BUILTIN_FCMLA_LANEQ90_V4HF, AARCH64_SIMD_BUILTIN_FCMLA_LANEQ180_V4HF,
AARCH64_SIMD_BUILTIN_FCMLA_LANEQ270_V4HF.
* config/aarch64/iterators.md (FCMLA_maybe_lane): New.
* config/aarch64/aarch64-c.c (aarch64_update_cpp_builtins): Add __ARM_FEATURE_COMPLEX.
* config/aarch64/aarch64-simd-builtins.def (fcadd90, fcadd270, fcmla0, fcmla90,
fcmla180, fcmla270, fcmla_lane0, fcmla_lane90, fcmla_lane180, fcmla_lane270,
fcmla_laneq0, fcmla_laneq90, fcmla_laneq180, fcmla_laneq270,
fcmlaq_lane0, fcmlaq_lane90, fcmlaq_lane180, fcmlaq_lane270): New.
* config/aarch64/aarch64-simd.md (aarch64_fcmla_lane<rot><mode>,
aarch64_fcmla_laneq<rot>v4hf, aarch64_fcmlaq_lane<rot><mode>,aarch64_fcadd<rot><mode>,
aarch64_fcmla<rot><mode>): New.
* config/aarch64/arm_neon.h:
(vcadd_rot90_f16): New.
(vcaddq_rot90_f16): New.
(vcadd_rot270_f16): New.
(vcaddq_rot270_f16): New.
(vcmla_f16): New.
(vcmlaq_f16): New.
(vcmla_lane_f16): New.
(vcmla_laneq_f16): New.
(vcmlaq_lane_f16): New.
(vcmlaq_rot90_lane_f16): New.
(vcmla_rot90_laneq_f16): New.
(vcmla_rot90_lane_f16): New.
(vcmlaq_rot90_f16): New.
(vcmla_rot90_f16): New.
(vcmlaq_laneq_f16): New.
(vcmla_rot180_laneq_f16): New.
(vcmla_rot180_lane_f16): New.
(vcmlaq_rot180_f16): New.
(vcmla_rot180_f16): New.
(vcmlaq_rot90_laneq_f16): New.
(vcmlaq_rot270_laneq_f16): New.
(vcmlaq_rot270_lane_f16): New.
(vcmla_rot270_laneq_f16): New.
(vcmlaq_rot270_f16): New.
(vcmla_rot270_f16): New.
(vcmlaq_rot180_laneq_f16): New.
(vcmlaq_rot180_lane_f16): New.
(vcmla_rot270_lane_f16): New.
(vcadd_rot90_f32): New.
(vcaddq_rot90_f32): New.
(vcaddq_rot90_f64): New.
(vcadd_rot270_f32): New.
(vcaddq_rot270_f32): New.
(vcaddq_rot270_f64): New.
(vcmla_f32): New.
(vcmlaq_f32): New.
(vcmlaq_f64): New.
(vcmla_lane_f32): New.
(vcmla_laneq_f32): New.
(vcmlaq_lane_f32): New.
(vcmlaq_laneq_f32): New.
(vcmla_rot90_f32): New.
(vcmlaq_rot90_f32): New.
(vcmlaq_rot90_f64): New.
(vcmla_rot90_lane_f32): New.
(vcmla_rot90_laneq_f32): New.
(vcmlaq_rot90_lane_f32): New.
(vcmlaq_rot90_laneq_f32): New.
(vcmla_rot180_f32): New.
(vcmlaq_rot180_f32): New.
(vcmlaq_rot180_f64): New.
(vcmla_rot180_lane_f32): New.
(vcmla_rot180_laneq_f32): New.
(vcmlaq_rot180_lane_f32): New.
(vcmlaq_rot180_laneq_f32): New.
(vcmla_rot270_f32): New.
(vcmlaq_rot270_f32): New.
(vcmlaq_rot270_f64): New.
(vcmla_rot270_lane_f32): New.
(vcmla_rot270_laneq_f32): New.
(vcmlaq_rot270_lane_f32): New.
(vcmlaq_rot270_laneq_f32): New.
* config/aarch64/aarch64.h (TARGET_COMPLEX): New.
* config/aarch64/iterators.md (UNSPEC_FCADD90, UNSPEC_FCADD270,
UNSPEC_FCMLA, UNSPEC_FCMLA90, UNSPEC_FCMLA180, UNSPEC_FCMLA270): New.
(FCADD, FCMLA): New.
(rot): New.
* config/arm/types.md (neon_fcadd, neon_fcmla): New.
gcc/testsuite/ChangeLog:
2019-01-10 Tamar Christina <tamar.christina@arm.com>
* gcc.target/aarch64/advsimd-intrinsics/vector-complex.c: New test.
* gcc.target/aarch64/advsimd-intrinsics/vector-complex_f16.c: New test.
From-SVN: r267795
2019-01-10 04:30:59 +01:00
|
|
|
}
|
2020-01-16 15:20:48 +01:00
|
|
|
/* If the lane index isn't a constant then error out. */
|
|
|
|
goto constant_arg;
|
|
|
|
case SIMD_ARG_LANE_QUADTUP_INDEX:
|
|
|
|
/* Must be a previous operand into which this is an index and
|
|
|
|
index is restricted to nunits / 4. */
|
|
|
|
gcc_assert (opc > 0);
|
|
|
|
if (CONST_INT_P (op[opc]))
|
|
|
|
{
|
|
|
|
machine_mode vmode = insn_data[icode].operand[opc - 1].mode;
|
|
|
|
unsigned int nunits
|
|
|
|
= GET_MODE_NUNITS (vmode).to_constant ();
|
|
|
|
aarch64_simd_lane_bounds (op[opc], 0, nunits / 4, exp);
|
|
|
|
/* Keep to GCC-vector-extension lane indices in the RTL. */
|
|
|
|
int lane = INTVAL (op[opc]);
|
|
|
|
op[opc] = gen_int_mode (ENDIAN_LANE_N (nunits / 4, lane),
|
|
|
|
SImode);
|
|
|
|
}
|
|
|
|
/* If the lane index isn't a constant then error out. */
|
|
|
|
goto constant_arg;
|
2012-10-23 19:02:30 +02:00
|
|
|
case SIMD_ARG_CONSTANT:
|
2015-07-22 12:44:16 +02:00
|
|
|
constant_arg:
|
2014-11-24 16:15:20 +01:00
|
|
|
if (!(*insn_data[icode].operand[opc].predicate)
|
|
|
|
(op[opc], mode))
|
2014-09-09 12:15:46 +02:00
|
|
|
{
|
2021-07-06 21:45:54 +02:00
|
|
|
error_at (EXPR_LOCATION (exp),
|
|
|
|
"argument %d must be a constant immediate",
|
|
|
|
opc + 1 - have_retval);
|
2014-09-09 12:15:46 +02:00
|
|
|
return const0_rtx;
|
|
|
|
}
|
2012-10-23 19:02:30 +02:00
|
|
|
break;
|
|
|
|
|
|
|
|
case SIMD_ARG_STOP:
|
|
|
|
gcc_unreachable ();
|
|
|
|
}
|
|
|
|
|
2014-11-24 16:15:20 +01:00
|
|
|
opc++;
|
2012-10-23 19:02:30 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2014-11-24 16:15:20 +01:00
|
|
|
switch (opc)
|
|
|
|
{
|
|
|
|
case 1:
|
|
|
|
pat = GEN_FCN (icode) (op[0]);
|
|
|
|
break;
|
2012-10-23 19:02:30 +02:00
|
|
|
|
2014-11-24 16:15:20 +01:00
|
|
|
case 2:
|
|
|
|
pat = GEN_FCN (icode) (op[0], op[1]);
|
|
|
|
break;
|
2012-10-23 19:02:30 +02:00
|
|
|
|
2014-11-24 16:15:20 +01:00
|
|
|
case 3:
|
|
|
|
pat = GEN_FCN (icode) (op[0], op[1], op[2]);
|
|
|
|
break;
|
2012-10-23 19:02:30 +02:00
|
|
|
|
2014-11-24 16:15:20 +01:00
|
|
|
case 4:
|
|
|
|
pat = GEN_FCN (icode) (op[0], op[1], op[2], op[3]);
|
|
|
|
break;
|
2012-10-23 19:02:30 +02:00
|
|
|
|
2014-11-24 16:15:20 +01:00
|
|
|
case 5:
|
|
|
|
pat = GEN_FCN (icode) (op[0], op[1], op[2], op[3], op[4]);
|
|
|
|
break;
|
2012-10-23 19:02:30 +02:00
|
|
|
|
2014-11-24 16:15:20 +01:00
|
|
|
case 6:
|
|
|
|
pat = GEN_FCN (icode) (op[0], op[1], op[2], op[3], op[4], op[5]);
|
|
|
|
break;
|
2012-10-23 19:02:30 +02:00
|
|
|
|
2014-11-24 16:15:20 +01:00
|
|
|
default:
|
|
|
|
gcc_unreachable ();
|
|
|
|
}
|
2012-10-23 19:02:30 +02:00
|
|
|
|
|
|
|
if (!pat)
|
2014-09-09 12:15:46 +02:00
|
|
|
return NULL_RTX;
|
2012-10-23 19:02:30 +02:00
|
|
|
|
|
|
|
emit_insn (pat);
|
|
|
|
|
|
|
|
return target;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Expand an AArch64 AdvSIMD builtin(intrinsic). */
|
|
|
|
rtx
|
|
|
|
aarch64_simd_expand_builtin (int fcode, tree exp, rtx target)
|
|
|
|
{
|
[AArch64] Fix ICE on non-constant indices to __builtin_aarch64_im_lane_boundsi
gcc/:
* config/aarch64/aarch64-builtins.c (aarch64_types_binopv_qualifiers,
TYPES_BINOPV): Delete.
(enum aarch64_builtins): Add AARCH64_BUILTIN_SIMD_LANE_CHECK and
AARCH64_SIMD_PATTERN_START.
(aarch64_init_simd_builtins): Register
__builtin_aarch64_im_lane_boundsi; use AARCH64_SIMD_PATTERN_START.
(aarch64_simd_expand_builtin): Handle AARCH64_BUILTIN_LANE_CHECK; use
AARCH64_SIMD_PATTERN_START.
* config/aarch64/aarch64-simd.md (aarch64_im_lane_boundsi): Delete.
* config/aarch64/aarch64-simd-builtins.def (im_lane_bound): Delete.
* config/aarch64/arm_neon.h (__AARCH64_LANE_CHECK): New.
(__aarch64_vget_lane_f64, __aarch64_vget_lane_s64,
__aarch64_vget_lane_u64, __aarch64_vset_lane_any, vdupd_lane_f64,
vdupd_lane_s64, vdupd_lane_u64, vext_f32, vext_f64, vext_p8, vext_p16,
vext_s8, vext_s16, vext_s32, vext_s64, vext_u8, vext_u16, vext_u32,
vext_u64, vextq_f32, vextq_f64, vextq_p8, vextq_p16, vextq_s8,
vextq_s16, vextq_s32, vextq_s64, vextq_u8, vextq_u16, vextq_u32,
vextq_u64, vmulq_lane_f64): Use __AARCH64_LANE_CHECK.
gcc/testsuite/:
* gcc.target/aarch64/simd/vset_lane_s16_const_1.c: New test.
From-SVN: r218532
2014-12-09 20:52:22 +01:00
|
|
|
if (fcode == AARCH64_SIMD_BUILTIN_LANE_CHECK)
|
|
|
|
{
|
2015-02-11 11:18:45 +01:00
|
|
|
rtx totalsize = expand_normal (CALL_EXPR_ARG (exp, 0));
|
|
|
|
rtx elementsize = expand_normal (CALL_EXPR_ARG (exp, 1));
|
|
|
|
if (CONST_INT_P (totalsize) && CONST_INT_P (elementsize)
|
|
|
|
&& UINTVAL (elementsize) != 0
|
|
|
|
&& UINTVAL (totalsize) != 0)
|
|
|
|
{
|
|
|
|
rtx lane_idx = expand_normal (CALL_EXPR_ARG (exp, 2));
|
|
|
|
if (CONST_INT_P (lane_idx))
|
|
|
|
aarch64_simd_lane_bounds (lane_idx, 0,
|
|
|
|
UINTVAL (totalsize)
|
|
|
|
/ UINTVAL (elementsize),
|
|
|
|
exp);
|
|
|
|
else
|
2021-07-06 21:45:54 +02:00
|
|
|
error_at (EXPR_LOCATION (exp),
|
|
|
|
"lane index must be a constant immediate");
|
2015-02-11 11:18:45 +01:00
|
|
|
}
|
[AArch64] Fix ICE on non-constant indices to __builtin_aarch64_im_lane_boundsi
gcc/:
* config/aarch64/aarch64-builtins.c (aarch64_types_binopv_qualifiers,
TYPES_BINOPV): Delete.
(enum aarch64_builtins): Add AARCH64_BUILTIN_SIMD_LANE_CHECK and
AARCH64_SIMD_PATTERN_START.
(aarch64_init_simd_builtins): Register
__builtin_aarch64_im_lane_boundsi; use AARCH64_SIMD_PATTERN_START.
(aarch64_simd_expand_builtin): Handle AARCH64_BUILTIN_LANE_CHECK; use
AARCH64_SIMD_PATTERN_START.
* config/aarch64/aarch64-simd.md (aarch64_im_lane_boundsi): Delete.
* config/aarch64/aarch64-simd-builtins.def (im_lane_bound): Delete.
* config/aarch64/arm_neon.h (__AARCH64_LANE_CHECK): New.
(__aarch64_vget_lane_f64, __aarch64_vget_lane_s64,
__aarch64_vget_lane_u64, __aarch64_vset_lane_any, vdupd_lane_f64,
vdupd_lane_s64, vdupd_lane_u64, vext_f32, vext_f64, vext_p8, vext_p16,
vext_s8, vext_s16, vext_s32, vext_s64, vext_u8, vext_u16, vext_u32,
vext_u64, vextq_f32, vextq_f64, vextq_p8, vextq_p16, vextq_s8,
vextq_s16, vextq_s32, vextq_s64, vextq_u8, vextq_u16, vextq_u32,
vextq_u64, vmulq_lane_f64): Use __AARCH64_LANE_CHECK.
gcc/testsuite/:
* gcc.target/aarch64/simd/vset_lane_s16_const_1.c: New test.
From-SVN: r218532
2014-12-09 20:52:22 +01:00
|
|
|
else
|
2021-07-06 21:45:54 +02:00
|
|
|
error_at (EXPR_LOCATION (exp),
|
2022-01-18 16:31:55 +01:00
|
|
|
"total size and element size must be a nonzero "
|
2021-07-06 21:45:54 +02:00
|
|
|
"constant immediate");
|
[AArch64] Fix ICE on non-constant indices to __builtin_aarch64_im_lane_boundsi
gcc/:
* config/aarch64/aarch64-builtins.c (aarch64_types_binopv_qualifiers,
TYPES_BINOPV): Delete.
(enum aarch64_builtins): Add AARCH64_BUILTIN_SIMD_LANE_CHECK and
AARCH64_SIMD_PATTERN_START.
(aarch64_init_simd_builtins): Register
__builtin_aarch64_im_lane_boundsi; use AARCH64_SIMD_PATTERN_START.
(aarch64_simd_expand_builtin): Handle AARCH64_BUILTIN_LANE_CHECK; use
AARCH64_SIMD_PATTERN_START.
* config/aarch64/aarch64-simd.md (aarch64_im_lane_boundsi): Delete.
* config/aarch64/aarch64-simd-builtins.def (im_lane_bound): Delete.
* config/aarch64/arm_neon.h (__AARCH64_LANE_CHECK): New.
(__aarch64_vget_lane_f64, __aarch64_vget_lane_s64,
__aarch64_vget_lane_u64, __aarch64_vset_lane_any, vdupd_lane_f64,
vdupd_lane_s64, vdupd_lane_u64, vext_f32, vext_f64, vext_p8, vext_p16,
vext_s8, vext_s16, vext_s32, vext_s64, vext_u8, vext_u16, vext_u32,
vext_u64, vextq_f32, vextq_f64, vextq_p8, vextq_p16, vextq_s8,
vextq_s16, vextq_s32, vextq_s64, vextq_u8, vextq_u16, vextq_u32,
vextq_u64, vmulq_lane_f64): Use __AARCH64_LANE_CHECK.
gcc/testsuite/:
* gcc.target/aarch64/simd/vset_lane_s16_const_1.c: New test.
From-SVN: r218532
2014-12-09 20:52:22 +01:00
|
|
|
/* Don't generate any RTL. */
|
|
|
|
return const0_rtx;
|
|
|
|
}
|
2012-11-20 13:10:37 +01:00
|
|
|
aarch64_simd_builtin_datum *d =
|
[AArch64] Fix ICE on non-constant indices to __builtin_aarch64_im_lane_boundsi
gcc/:
* config/aarch64/aarch64-builtins.c (aarch64_types_binopv_qualifiers,
TYPES_BINOPV): Delete.
(enum aarch64_builtins): Add AARCH64_BUILTIN_SIMD_LANE_CHECK and
AARCH64_SIMD_PATTERN_START.
(aarch64_init_simd_builtins): Register
__builtin_aarch64_im_lane_boundsi; use AARCH64_SIMD_PATTERN_START.
(aarch64_simd_expand_builtin): Handle AARCH64_BUILTIN_LANE_CHECK; use
AARCH64_SIMD_PATTERN_START.
* config/aarch64/aarch64-simd.md (aarch64_im_lane_boundsi): Delete.
* config/aarch64/aarch64-simd-builtins.def (im_lane_bound): Delete.
* config/aarch64/arm_neon.h (__AARCH64_LANE_CHECK): New.
(__aarch64_vget_lane_f64, __aarch64_vget_lane_s64,
__aarch64_vget_lane_u64, __aarch64_vset_lane_any, vdupd_lane_f64,
vdupd_lane_s64, vdupd_lane_u64, vext_f32, vext_f64, vext_p8, vext_p16,
vext_s8, vext_s16, vext_s32, vext_s64, vext_u8, vext_u16, vext_u32,
vext_u64, vextq_f32, vextq_f64, vextq_p8, vextq_p16, vextq_s8,
vextq_s16, vextq_s32, vextq_s64, vextq_u8, vextq_u16, vextq_u32,
vextq_u64, vmulq_lane_f64): Use __AARCH64_LANE_CHECK.
gcc/testsuite/:
* gcc.target/aarch64/simd/vset_lane_s16_const_1.c: New test.
From-SVN: r218532
2014-12-09 20:52:22 +01:00
|
|
|
&aarch64_simd_builtin_data[fcode - AARCH64_SIMD_PATTERN_START];
|
2012-11-20 13:10:37 +01:00
|
|
|
enum insn_code icode = d->code;
|
2015-04-01 13:18:03 +02:00
|
|
|
builtin_simd_arg args[SIMD_MAX_BUILTIN_ARGS + 1];
|
2013-11-20 10:19:25 +01:00
|
|
|
int num_args = insn_data[d->code].n_operands;
|
|
|
|
int is_void = 0;
|
|
|
|
int k;
|
2012-10-23 19:02:30 +02:00
|
|
|
|
2013-11-20 10:19:25 +01:00
|
|
|
is_void = !!(d->qualifiers[0] & qualifier_void);
|
2012-10-23 19:02:30 +02:00
|
|
|
|
2013-11-20 10:19:25 +01:00
|
|
|
num_args += is_void;
|
|
|
|
|
|
|
|
for (k = 1; k < num_args; k++)
|
|
|
|
{
|
|
|
|
/* We have four arrays of data, each indexed in a different fashion.
|
|
|
|
qualifiers - element 0 always describes the function return type.
|
|
|
|
operands - element 0 is either the operand for return value (if
|
|
|
|
the function has a non-void return type) or the operand for the
|
|
|
|
first argument.
|
|
|
|
expr_args - element 0 always holds the first argument.
|
|
|
|
args - element 0 is always used for the return type. */
|
|
|
|
int qualifiers_k = k;
|
|
|
|
int operands_k = k - is_void;
|
|
|
|
int expr_args_k = k - 1;
|
|
|
|
|
Add bounds checking to vqdm*_lane intrinsics via a qualifier that also flips endianness
gcc/:
* config/aarch64/aarch64.c (aarch64_simd_lane_bounds): Display indices.
* config/aarch64/aarch64-builtins.c (enum aarch64_type_qualifiers): Add
qualifier_lane_index.
(aarch64_types_ternop_lane_qualifiers, TYPES_TERNOP_LANE): Rename to...
(aarch64_types_quadop_lane_qualifiers, TYPES_QUADOP_LANE): ...these.
(aarch64_types_ternop_lane_qualifiers, TYPES_TERNOP_LANE): New.
(aarch64_types_getlane_qualifiers): Rename to...
(aarch64_types_binop_imm_qualifiers): ...this.
(TYPES_SHIFTIMM): Follow renaming.
(TYPES_GETLANE): Rename to...
(TYPE_GETREG): ...this.
(aarch64_types_setlane_qualifiers): Rename to...
(aarch64_type_ternop_imm_qualifiers): ...this.
(TYPES_SHIFTINSERT, TYPES_SHIFTACC): Follow renaming.
(TYPES_SETLANE): Follow renaming above, and rename self to...
(TYPE_SETREG): ...this.
(enum builtin_simd_arg): Add SIMD_ARG_LANE_INDEX.
(aarch64_simd_expand_args): Add range check and endianness-flip.
(aarch64_simd_expand_builtin): Add mapping for qualifier_lane_index.
* config/aarch64/aarch64-simd.md
(aarch64_sq<r>dmulh_lane<mode>_internal *2): Rename to...
(aarch64_sq<r>dmulh_lane<mode>): ...this, and remove lane bounds check.
(aarch64_sqdmulh_lane<mode> *2, aarch64_sqrdmulh_lane<mode> *2): Delete.
(aarch64_sq<r>dmulh_laneq<mode>_internal): Rename to...
(aarch64_sq<r>dmulh_lane<mode>): ...this.
(aarch64_sqdml<SBINQOPS:as>l_lane<mode>_internal *2): Rename to...
(aarch64_sqdml<SBINQOPS:as>l_lane<mode>): ...this.
(aarch64_sqdml<SBINQOPS:as>l_laneq<mode>_internal *2): Rename to...
(aarch64_sqdml<SBINQOPS:as>l_laneq<mode>): ...this.
(aarch64_sqdmull_lane<mode>_internal *2): Rename to...
(aarch64_sqdmull_lane<mode>): ...this.
(aarch64_sqdmull_laneq<mode>_internal *2): Rename to...
(aarch64_sqdmull_laneq<mode>): ...this.
(aarch64_sqdmulh_laneq<mode>, aarch64_sqrdmulh_laneq<mode>,
(aarch64_sqdmlal_lane<mode>, aarch64_sqdmlal_laneq<mode>,
aarch64_sqdmlsl_lane<mode>, aarch64_sqdmlsl_laneq<mode>,
aarch64_sqdmull_lane<mode>, aarch64_sqdmull_laneq<mode>): Delete.
(aarch64_sqdmlal2_lane<mode>, aarch64_sqdmlal2_laneq<mode>,
aarch64_sqdmlsl2_lane<mode>, aarch64_sqdmlsl2_laneq<mode>,
aarch64_sqdmull2_lane<mode>, aarch64_sqdmull2_laneq<mode>): Remove
bounds check and lane flip.
* config/aarch64/aarch64-simd-builtins.def (be_checked_get_lane,
get_dregoi, get_dregci, getdregxi, get_qregoi,get_qregci, get_qregxi,
set_qregoi, set_qregci, set_qregxi): Change qualifiers to GETREG.
(sqdmlal_lane, sqdmlsl_lane, sqdmlal_laneq, sqdmlsl_laneq,
sqdmlal2_lane, sqdmlsl2_lane, sqdmlal2_laneq, sqdmlsl2_laneq): Follow
renaming of TERNOP_LANE to QUADOP_LANE.
(sqdmull_lane, sqdmull_laneq, sqdmull2_lane, sqdmull2_laneq,
sqdmulh_lane, sqdmulh_laneq, sqrdmulh_lane, sqrdmulh_laneq): Set
qualifiers to TERNOP_LANE.
gcc/testsuite/:
* gcc.target/aarch64/simd/vqdmlal_high_lane_s16_indices_1.c: New test.
* gcc.target/aarch64/simd/vqdmlal_high_lane_s32_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqdmlal_high_laneq_s16_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqdmlal_high_laneq_s32_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqdmlal_lane_s16_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqdmlal_lane_s32_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqdmlal_laneq_s16_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqdmlal_laneq_s32_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqdmlalh_lane_s16_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqdmlals_lane_s32_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqdmlsl_high_lane_s16_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqdmlsl_high_lane_s32_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqdmlsl_high_laneq_s16_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqdmlsl_high_laneq_s32_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqdmlsl_lane_s16_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqdmlsl_lane_s32_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqdmlsl_laneq_s16_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqdmlsl_laneq_s32_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqdmlslh_lane_s16_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqdmlsls_lane_s32_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqdmulh_lane_s16_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqdmulh_lane_s32_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqdmulh_laneq_s16_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqdmulh_laneq_s32_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqdmulhh_lane_s16_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqdmulhq_lane_s16_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqdmulhq_lane_s32_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqdmulhq_laneq_s16_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqdmulhq_laneq_s32_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqdmulhs_lane_s32_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqdmull_high_lane_s16_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqdmull_high_lane_s32_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqdmull_high_laneq_s16_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqdmull_high_laneq_s32_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqdmull_lane_s16_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqdmull_lane_s32_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqdmull_laneq_s16_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqdmull_laneq_s32_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqdmullh_lane_s16_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqdmulls_lane_s32_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqrdmulh_lane_s16_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqrdmulh_lane_s32_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqrdmulh_laneq_s16_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqrdmulh_laneq_s32_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqrdmulhh_lane_s16_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqrdmulhq_lane_s16_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqrdmulhq_lane_s32_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqrdmulhq_laneq_s16_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqrdmulhq_laneq_s32_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqrdmulhs_lane_s32_indices_1.c: Likewise.
From-SVN: r217440
2014-11-12 19:51:53 +01:00
|
|
|
if (d->qualifiers[qualifiers_k] & qualifier_lane_index)
|
|
|
|
args[k] = SIMD_ARG_LANE_INDEX;
|
aarch64-builtins.c (enum aarch64_type_qualifiers): Add qualifier_lane_pair_index.
gcc/ChangeLog:
2019-01-10 Tamar Christina <tamar.christina@arm.com>
* config/aarch64/aarch64-builtins.c (enum aarch64_type_qualifiers): Add qualifier_lane_pair_index.
(emit-rtl.h): Include.
(TYPES_QUADOP_LANE_PAIR): New.
(aarch64_simd_expand_args): Use it.
(aarch64_simd_expand_builtin): Likewise.
(AARCH64_SIMD_FCMLA_LANEQ_BUILTINS, aarch64_fcmla_laneq_builtin_datum): New.
(FCMLA_LANEQ_BUILTIN, AARCH64_SIMD_FCMLA_LANEQ_BUILTIN_BASE,
AARCH64_SIMD_FCMLA_LANEQ_BUILTINS, aarch64_fcmla_lane_builtin_data,
aarch64_init_fcmla_laneq_builtins, aarch64_expand_fcmla_builtin): New.
(aarch64_init_builtins): Add aarch64_init_fcmla_laneq_builtins.
(aarch64_expand_buildin): Add AARCH64_SIMD_BUILTIN_FCMLA_LANEQ0_V2SF,
AARCH64_SIMD_BUILTIN_FCMLA_LANEQ90_V2SF, AARCH64_SIMD_BUILTIN_FCMLA_LANEQ180_V2SF,
AARCH64_SIMD_BUILTIN_FCMLA_LANEQ2700_V2SF, AARCH64_SIMD_BUILTIN_FCMLA_LANEQ0_V4HF,
AARCH64_SIMD_BUILTIN_FCMLA_LANEQ90_V4HF, AARCH64_SIMD_BUILTIN_FCMLA_LANEQ180_V4HF,
AARCH64_SIMD_BUILTIN_FCMLA_LANEQ270_V4HF.
* config/aarch64/iterators.md (FCMLA_maybe_lane): New.
* config/aarch64/aarch64-c.c (aarch64_update_cpp_builtins): Add __ARM_FEATURE_COMPLEX.
* config/aarch64/aarch64-simd-builtins.def (fcadd90, fcadd270, fcmla0, fcmla90,
fcmla180, fcmla270, fcmla_lane0, fcmla_lane90, fcmla_lane180, fcmla_lane270,
fcmla_laneq0, fcmla_laneq90, fcmla_laneq180, fcmla_laneq270,
fcmlaq_lane0, fcmlaq_lane90, fcmlaq_lane180, fcmlaq_lane270): New.
* config/aarch64/aarch64-simd.md (aarch64_fcmla_lane<rot><mode>,
aarch64_fcmla_laneq<rot>v4hf, aarch64_fcmlaq_lane<rot><mode>,aarch64_fcadd<rot><mode>,
aarch64_fcmla<rot><mode>): New.
* config/aarch64/arm_neon.h:
(vcadd_rot90_f16): New.
(vcaddq_rot90_f16): New.
(vcadd_rot270_f16): New.
(vcaddq_rot270_f16): New.
(vcmla_f16): New.
(vcmlaq_f16): New.
(vcmla_lane_f16): New.
(vcmla_laneq_f16): New.
(vcmlaq_lane_f16): New.
(vcmlaq_rot90_lane_f16): New.
(vcmla_rot90_laneq_f16): New.
(vcmla_rot90_lane_f16): New.
(vcmlaq_rot90_f16): New.
(vcmla_rot90_f16): New.
(vcmlaq_laneq_f16): New.
(vcmla_rot180_laneq_f16): New.
(vcmla_rot180_lane_f16): New.
(vcmlaq_rot180_f16): New.
(vcmla_rot180_f16): New.
(vcmlaq_rot90_laneq_f16): New.
(vcmlaq_rot270_laneq_f16): New.
(vcmlaq_rot270_lane_f16): New.
(vcmla_rot270_laneq_f16): New.
(vcmlaq_rot270_f16): New.
(vcmla_rot270_f16): New.
(vcmlaq_rot180_laneq_f16): New.
(vcmlaq_rot180_lane_f16): New.
(vcmla_rot270_lane_f16): New.
(vcadd_rot90_f32): New.
(vcaddq_rot90_f32): New.
(vcaddq_rot90_f64): New.
(vcadd_rot270_f32): New.
(vcaddq_rot270_f32): New.
(vcaddq_rot270_f64): New.
(vcmla_f32): New.
(vcmlaq_f32): New.
(vcmlaq_f64): New.
(vcmla_lane_f32): New.
(vcmla_laneq_f32): New.
(vcmlaq_lane_f32): New.
(vcmlaq_laneq_f32): New.
(vcmla_rot90_f32): New.
(vcmlaq_rot90_f32): New.
(vcmlaq_rot90_f64): New.
(vcmla_rot90_lane_f32): New.
(vcmla_rot90_laneq_f32): New.
(vcmlaq_rot90_lane_f32): New.
(vcmlaq_rot90_laneq_f32): New.
(vcmla_rot180_f32): New.
(vcmlaq_rot180_f32): New.
(vcmlaq_rot180_f64): New.
(vcmla_rot180_lane_f32): New.
(vcmla_rot180_laneq_f32): New.
(vcmlaq_rot180_lane_f32): New.
(vcmlaq_rot180_laneq_f32): New.
(vcmla_rot270_f32): New.
(vcmlaq_rot270_f32): New.
(vcmlaq_rot270_f64): New.
(vcmla_rot270_lane_f32): New.
(vcmla_rot270_laneq_f32): New.
(vcmlaq_rot270_lane_f32): New.
(vcmlaq_rot270_laneq_f32): New.
* config/aarch64/aarch64.h (TARGET_COMPLEX): New.
* config/aarch64/iterators.md (UNSPEC_FCADD90, UNSPEC_FCADD270,
UNSPEC_FCMLA, UNSPEC_FCMLA90, UNSPEC_FCMLA180, UNSPEC_FCMLA270): New.
(FCADD, FCMLA): New.
(rot): New.
* config/arm/types.md (neon_fcadd, neon_fcmla): New.
gcc/testsuite/ChangeLog:
2019-01-10 Tamar Christina <tamar.christina@arm.com>
* gcc.target/aarch64/advsimd-intrinsics/vector-complex.c: New test.
* gcc.target/aarch64/advsimd-intrinsics/vector-complex_f16.c: New test.
From-SVN: r267795
2019-01-10 04:30:59 +01:00
|
|
|
else if (d->qualifiers[qualifiers_k] & qualifier_lane_pair_index)
|
|
|
|
args[k] = SIMD_ARG_LANE_PAIR_INDEX;
|
2020-01-16 15:20:48 +01:00
|
|
|
else if (d->qualifiers[qualifiers_k] & qualifier_lane_quadtup_index)
|
|
|
|
args[k] = SIMD_ARG_LANE_QUADTUP_INDEX;
|
2015-07-22 12:44:16 +02:00
|
|
|
else if (d->qualifiers[qualifiers_k] & qualifier_struct_load_store_lane_index)
|
|
|
|
args[k] = SIMD_ARG_STRUCT_LOAD_STORE_LANE_INDEX;
|
Add bounds checking to vqdm*_lane intrinsics via a qualifier that also flips endianness
gcc/:
* config/aarch64/aarch64.c (aarch64_simd_lane_bounds): Display indices.
* config/aarch64/aarch64-builtins.c (enum aarch64_type_qualifiers): Add
qualifier_lane_index.
(aarch64_types_ternop_lane_qualifiers, TYPES_TERNOP_LANE): Rename to...
(aarch64_types_quadop_lane_qualifiers, TYPES_QUADOP_LANE): ...these.
(aarch64_types_ternop_lane_qualifiers, TYPES_TERNOP_LANE): New.
(aarch64_types_getlane_qualifiers): Rename to...
(aarch64_types_binop_imm_qualifiers): ...this.
(TYPES_SHIFTIMM): Follow renaming.
(TYPES_GETLANE): Rename to...
(TYPE_GETREG): ...this.
(aarch64_types_setlane_qualifiers): Rename to...
(aarch64_type_ternop_imm_qualifiers): ...this.
(TYPES_SHIFTINSERT, TYPES_SHIFTACC): Follow renaming.
(TYPES_SETLANE): Follow renaming above, and rename self to...
(TYPE_SETREG): ...this.
(enum builtin_simd_arg): Add SIMD_ARG_LANE_INDEX.
(aarch64_simd_expand_args): Add range check and endianness-flip.
(aarch64_simd_expand_builtin): Add mapping for qualifier_lane_index.
* config/aarch64/aarch64-simd.md
(aarch64_sq<r>dmulh_lane<mode>_internal *2): Rename to...
(aarch64_sq<r>dmulh_lane<mode>): ...this, and remove lane bounds check.
(aarch64_sqdmulh_lane<mode> *2, aarch64_sqrdmulh_lane<mode> *2): Delete.
(aarch64_sq<r>dmulh_laneq<mode>_internal): Rename to...
(aarch64_sq<r>dmulh_lane<mode>): ...this.
(aarch64_sqdml<SBINQOPS:as>l_lane<mode>_internal *2): Rename to...
(aarch64_sqdml<SBINQOPS:as>l_lane<mode>): ...this.
(aarch64_sqdml<SBINQOPS:as>l_laneq<mode>_internal *2): Rename to...
(aarch64_sqdml<SBINQOPS:as>l_laneq<mode>): ...this.
(aarch64_sqdmull_lane<mode>_internal *2): Rename to...
(aarch64_sqdmull_lane<mode>): ...this.
(aarch64_sqdmull_laneq<mode>_internal *2): Rename to...
(aarch64_sqdmull_laneq<mode>): ...this.
(aarch64_sqdmulh_laneq<mode>, aarch64_sqrdmulh_laneq<mode>,
(aarch64_sqdmlal_lane<mode>, aarch64_sqdmlal_laneq<mode>,
aarch64_sqdmlsl_lane<mode>, aarch64_sqdmlsl_laneq<mode>,
aarch64_sqdmull_lane<mode>, aarch64_sqdmull_laneq<mode>): Delete.
(aarch64_sqdmlal2_lane<mode>, aarch64_sqdmlal2_laneq<mode>,
aarch64_sqdmlsl2_lane<mode>, aarch64_sqdmlsl2_laneq<mode>,
aarch64_sqdmull2_lane<mode>, aarch64_sqdmull2_laneq<mode>): Remove
bounds check and lane flip.
* config/aarch64/aarch64-simd-builtins.def (be_checked_get_lane,
get_dregoi, get_dregci, getdregxi, get_qregoi,get_qregci, get_qregxi,
set_qregoi, set_qregci, set_qregxi): Change qualifiers to GETREG.
(sqdmlal_lane, sqdmlsl_lane, sqdmlal_laneq, sqdmlsl_laneq,
sqdmlal2_lane, sqdmlsl2_lane, sqdmlal2_laneq, sqdmlsl2_laneq): Follow
renaming of TERNOP_LANE to QUADOP_LANE.
(sqdmull_lane, sqdmull_laneq, sqdmull2_lane, sqdmull2_laneq,
sqdmulh_lane, sqdmulh_laneq, sqrdmulh_lane, sqrdmulh_laneq): Set
qualifiers to TERNOP_LANE.
gcc/testsuite/:
* gcc.target/aarch64/simd/vqdmlal_high_lane_s16_indices_1.c: New test.
* gcc.target/aarch64/simd/vqdmlal_high_lane_s32_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqdmlal_high_laneq_s16_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqdmlal_high_laneq_s32_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqdmlal_lane_s16_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqdmlal_lane_s32_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqdmlal_laneq_s16_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqdmlal_laneq_s32_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqdmlalh_lane_s16_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqdmlals_lane_s32_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqdmlsl_high_lane_s16_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqdmlsl_high_lane_s32_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqdmlsl_high_laneq_s16_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqdmlsl_high_laneq_s32_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqdmlsl_lane_s16_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqdmlsl_lane_s32_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqdmlsl_laneq_s16_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqdmlsl_laneq_s32_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqdmlslh_lane_s16_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqdmlsls_lane_s32_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqdmulh_lane_s16_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqdmulh_lane_s32_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqdmulh_laneq_s16_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqdmulh_laneq_s32_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqdmulhh_lane_s16_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqdmulhq_lane_s16_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqdmulhq_lane_s32_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqdmulhq_laneq_s16_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqdmulhq_laneq_s32_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqdmulhs_lane_s32_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqdmull_high_lane_s16_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqdmull_high_lane_s32_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqdmull_high_laneq_s16_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqdmull_high_laneq_s32_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqdmull_lane_s16_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqdmull_lane_s32_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqdmull_laneq_s16_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqdmull_laneq_s32_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqdmullh_lane_s16_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqdmulls_lane_s32_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqrdmulh_lane_s16_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqrdmulh_lane_s32_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqrdmulh_laneq_s16_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqrdmulh_laneq_s32_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqrdmulhh_lane_s16_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqrdmulhq_lane_s16_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqrdmulhq_lane_s32_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqrdmulhq_laneq_s16_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqrdmulhq_laneq_s32_indices_1.c: Likewise.
* gcc.target/aarch64/simd/vqrdmulhs_lane_s32_indices_1.c: Likewise.
From-SVN: r217440
2014-11-12 19:51:53 +01:00
|
|
|
else if (d->qualifiers[qualifiers_k] & qualifier_immediate)
|
2013-11-20 10:19:25 +01:00
|
|
|
args[k] = SIMD_ARG_CONSTANT;
|
|
|
|
else if (d->qualifiers[qualifiers_k] & qualifier_maybe_immediate)
|
|
|
|
{
|
|
|
|
rtx arg
|
|
|
|
= expand_normal (CALL_EXPR_ARG (exp,
|
|
|
|
(expr_args_k)));
|
|
|
|
/* Handle constants only if the predicate allows it. */
|
|
|
|
bool op_const_int_p =
|
|
|
|
(CONST_INT_P (arg)
|
|
|
|
&& (*insn_data[icode].operand[operands_k].predicate)
|
|
|
|
(arg, insn_data[icode].operand[operands_k].mode));
|
|
|
|
args[k] = op_const_int_p ? SIMD_ARG_CONSTANT : SIMD_ARG_COPY_TO_REG;
|
|
|
|
}
|
|
|
|
else
|
|
|
|
args[k] = SIMD_ARG_COPY_TO_REG;
|
2012-10-23 19:02:30 +02:00
|
|
|
|
|
|
|
}
|
2013-11-20 10:19:25 +01:00
|
|
|
args[k] = SIMD_ARG_STOP;
|
|
|
|
|
|
|
|
/* The interface to aarch64_simd_expand_args expects a 0 if
|
|
|
|
the function is void, and a 1 if it is not. */
|
|
|
|
return aarch64_simd_expand_args
|
2015-07-22 12:44:16 +02:00
|
|
|
(target, icode, !is_void, exp, &args[1], d->mode);
|
2012-10-23 19:02:30 +02:00
|
|
|
}
|
2012-11-20 13:10:37 +01:00
|
|
|
|
2014-06-11 11:17:18 +02:00
|
|
|
rtx
|
|
|
|
aarch64_crc32_expand_builtin (int fcode, tree exp, rtx target)
|
|
|
|
{
|
|
|
|
rtx pat;
|
|
|
|
aarch64_crc_builtin_datum *d
|
|
|
|
= &aarch64_crc_builtin_data[fcode - (AARCH64_CRC32_BUILTIN_BASE + 1)];
|
|
|
|
enum insn_code icode = d->icode;
|
|
|
|
tree arg0 = CALL_EXPR_ARG (exp, 0);
|
|
|
|
tree arg1 = CALL_EXPR_ARG (exp, 1);
|
|
|
|
rtx op0 = expand_normal (arg0);
|
|
|
|
rtx op1 = expand_normal (arg1);
|
decl.c, [...]: Remove redundant enum from machine_mode.
gcc/ada/
* gcc-interface/decl.c, gcc-interface/gigi.h, gcc-interface/misc.c,
gcc-interface/trans.c, gcc-interface/utils.c, gcc-interface/utils2.c:
Remove redundant enum from machine_mode.
gcc/c-family/
* c-common.c, c-common.h, c-cppbuiltin.c, c-lex.c: Remove redundant
enum from machine_mode.
gcc/c/
* c-decl.c, c-tree.h, c-typeck.c: Remove redundant enum from
machine_mode.
gcc/cp/
* constexpr.c: Remove redundant enum from machine_mode.
gcc/fortran/
* trans-types.c, trans-types.h: Remove redundant enum from
machine_mode.
gcc/go/
* go-lang.c: Remove redundant enum from machine_mode.
gcc/java/
* builtins.c, java-tree.h, typeck.c: Remove redundant enum from
machine_mode.
gcc/lto/
* lto-lang.c: Remove redundant enum from machine_mode.
gcc/
* addresses.h, alias.c, asan.c, auto-inc-dec.c, bt-load.c, builtins.c,
builtins.h, caller-save.c, calls.c, calls.h, cfgexpand.c, cfgloop.h,
cfgrtl.c, combine.c, compare-elim.c, config/aarch64/aarch64-builtins.c,
config/aarch64/aarch64-protos.h, config/aarch64/aarch64-simd.md,
config/aarch64/aarch64.c, config/aarch64/aarch64.h,
config/aarch64/aarch64.md, config/alpha/alpha-protos.h,
config/alpha/alpha.c, config/arc/arc-protos.h, config/arc/arc.c,
config/arc/arc.h, config/arc/predicates.md,
config/arm/aarch-common-protos.h, config/arm/aarch-common.c,
config/arm/arm-protos.h, config/arm/arm.c, config/arm/arm.h,
config/arm/arm.md, config/arm/neon.md, config/arm/thumb2.md,
config/avr/avr-log.c, config/avr/avr-protos.h, config/avr/avr.c,
config/avr/avr.md, config/bfin/bfin-protos.h, config/bfin/bfin.c,
config/c6x/c6x-protos.h, config/c6x/c6x.c, config/c6x/c6x.md,
config/cr16/cr16-protos.h, config/cr16/cr16.c,
config/cris/cris-protos.h, config/cris/cris.c, config/cris/cris.md,
config/darwin-protos.h, config/darwin.c,
config/epiphany/epiphany-protos.h, config/epiphany/epiphany.c,
config/epiphany/epiphany.md, config/fr30/fr30.c,
config/frv/frv-protos.h, config/frv/frv.c, config/frv/predicates.md,
config/h8300/h8300-protos.h, config/h8300/h8300.c,
config/i386/i386-builtin-types.awk, config/i386/i386-protos.h,
config/i386/i386.c, config/i386/i386.md, config/i386/predicates.md,
config/i386/sse.md, config/i386/sync.md, config/ia64/ia64-protos.h,
config/ia64/ia64.c, config/iq2000/iq2000-protos.h,
config/iq2000/iq2000.c, config/iq2000/iq2000.md,
config/lm32/lm32-protos.h, config/lm32/lm32.c,
config/m32c/m32c-protos.h, config/m32c/m32c.c,
config/m32r/m32r-protos.h, config/m32r/m32r.c,
config/m68k/m68k-protos.h, config/m68k/m68k.c,
config/mcore/mcore-protos.h, config/mcore/mcore.c,
config/mcore/mcore.md, config/mep/mep-protos.h, config/mep/mep.c,
config/microblaze/microblaze-protos.h, config/microblaze/microblaze.c,
config/mips/mips-protos.h, config/mips/mips.c,
config/mmix/mmix-protos.h, config/mmix/mmix.c,
config/mn10300/mn10300-protos.h, config/mn10300/mn10300.c,
config/moxie/moxie.c, config/msp430/msp430-protos.h,
config/msp430/msp430.c, config/nds32/nds32-cost.c,
config/nds32/nds32-intrinsic.c, config/nds32/nds32-md-auxiliary.c,
config/nds32/nds32-protos.h, config/nds32/nds32.c,
config/nios2/nios2-protos.h, config/nios2/nios2.c,
config/pa/pa-protos.h, config/pa/pa.c, config/pdp11/pdp11-protos.h,
config/pdp11/pdp11.c, config/rl78/rl78-protos.h, config/rl78/rl78.c,
config/rs6000/altivec.md, config/rs6000/rs6000-c.c,
config/rs6000/rs6000-protos.h, config/rs6000/rs6000.c,
config/rs6000/rs6000.h, config/rx/rx-protos.h, config/rx/rx.c,
config/s390/predicates.md, config/s390/s390-protos.h,
config/s390/s390.c, config/s390/s390.h, config/s390/s390.md,
config/sh/predicates.md, config/sh/sh-protos.h, config/sh/sh.c,
config/sh/sh.md, config/sparc/predicates.md,
config/sparc/sparc-protos.h, config/sparc/sparc.c,
config/sparc/sparc.md, config/spu/spu-protos.h, config/spu/spu.c,
config/stormy16/stormy16-protos.h, config/stormy16/stormy16.c,
config/tilegx/tilegx-protos.h, config/tilegx/tilegx.c,
config/tilegx/tilegx.md, config/tilepro/tilepro-protos.h,
config/tilepro/tilepro.c, config/v850/v850-protos.h,
config/v850/v850.c, config/v850/v850.md, config/vax/vax-protos.h,
config/vax/vax.c, config/vms/vms-c.c, config/xtensa/xtensa-protos.h,
config/xtensa/xtensa.c, coverage.c, cprop.c, cse.c, cselib.c, cselib.h,
dbxout.c, ddg.c, df-problems.c, dfp.c, dfp.h, doc/md.texi,
doc/rtl.texi, doc/tm.texi, doc/tm.texi.in, dojump.c, dse.c,
dwarf2cfi.c, dwarf2out.c, dwarf2out.h, emit-rtl.c, emit-rtl.h,
except.c, explow.c, expmed.c, expmed.h, expr.c, expr.h, final.c,
fixed-value.c, fixed-value.h, fold-const.c, function.c, function.h,
fwprop.c, gcse.c, gengenrtl.c, genmodes.c, genopinit.c, genoutput.c,
genpreds.c, genrecog.c, gensupport.c, gimple-ssa-strength-reduction.c,
graphite-clast-to-gimple.c, haifa-sched.c, hooks.c, hooks.h, ifcvt.c,
internal-fn.c, ira-build.c, ira-color.c, ira-conflicts.c, ira-costs.c,
ira-emit.c, ira-int.h, ira-lives.c, ira.c, ira.h, jump.c, langhooks.h,
libfuncs.h, lists.c, loop-doloop.c, loop-invariant.c, loop-iv.c,
loop-unroll.c, lower-subreg.c, lower-subreg.h, lra-assigns.c,
lra-constraints.c, lra-eliminations.c, lra-int.h, lra-lives.c,
lra-spills.c, lra.c, lra.h, machmode.h, omp-low.c, optabs.c, optabs.h,
output.h, postreload.c, print-tree.c, read-rtl.c, real.c, real.h,
recog.c, recog.h, ree.c, reg-stack.c, regcprop.c, reginfo.c,
regrename.c, regs.h, reload.c, reload.h, reload1.c, rtl.c, rtl.h,
rtlanal.c, rtlhash.c, rtlhooks-def.h, rtlhooks.c, sched-deps.c,
sel-sched-dump.c, sel-sched-ir.c, sel-sched-ir.h, sel-sched.c,
simplify-rtx.c, stmt.c, stor-layout.c, stor-layout.h, target.def,
targhooks.c, targhooks.h, tree-affine.c, tree-call-cdce.c,
tree-complex.c, tree-data-ref.c, tree-dfa.c, tree-if-conv.c,
tree-inline.c, tree-outof-ssa.c, tree-scalar-evolution.c,
tree-ssa-address.c, tree-ssa-ccp.c, tree-ssa-loop-ivopts.c,
tree-ssa-loop-ivopts.h, tree-ssa-loop-manip.c,
tree-ssa-loop-prefetch.c, tree-ssa-math-opts.c, tree-ssa-reassoc.c,
tree-ssa-sccvn.c, tree-streamer-in.c, tree-switch-conversion.c,
tree-vect-data-refs.c, tree-vect-generic.c, tree-vect-loop.c,
tree-vect-patterns.c, tree-vect-slp.c, tree-vect-stmts.c,
tree-vrp.c, tree.c, tree.h, tsan.c, ubsan.c, valtrack.c,
var-tracking.c, varasm.c: Remove redundant enum from
machine_mode.
gcc/
* gengtype.c (main): Treat machine_mode as a scalar typedef.
* genmodes.c (emit_insn_modes_h): Hide inline functions if
USED_FOR_TARGET.
From-SVN: r216834
2014-10-29 13:02:45 +01:00
|
|
|
machine_mode tmode = insn_data[icode].operand[0].mode;
|
|
|
|
machine_mode mode0 = insn_data[icode].operand[1].mode;
|
|
|
|
machine_mode mode1 = insn_data[icode].operand[2].mode;
|
2014-06-11 11:17:18 +02:00
|
|
|
|
|
|
|
if (! target
|
|
|
|
|| GET_MODE (target) != tmode
|
|
|
|
|| ! (*insn_data[icode].operand[0].predicate) (target, tmode))
|
|
|
|
target = gen_reg_rtx (tmode);
|
|
|
|
|
|
|
|
gcc_assert ((GET_MODE (op0) == mode0 || GET_MODE (op0) == VOIDmode)
|
|
|
|
&& (GET_MODE (op1) == mode1 || GET_MODE (op1) == VOIDmode));
|
|
|
|
|
|
|
|
if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
|
|
|
|
op0 = copy_to_mode_reg (mode0, op0);
|
|
|
|
if (! (*insn_data[icode].operand[2].predicate) (op1, mode1))
|
|
|
|
op1 = copy_to_mode_reg (mode1, op1);
|
|
|
|
|
|
|
|
pat = GEN_FCN (icode) (target, op0, op1);
|
2014-09-09 12:15:46 +02:00
|
|
|
if (!pat)
|
|
|
|
return NULL_RTX;
|
|
|
|
|
2014-06-11 11:17:18 +02:00
|
|
|
emit_insn (pat);
|
|
|
|
return target;
|
|
|
|
}
|
|
|
|
|
2015-11-06 18:10:17 +01:00
|
|
|
/* Function to expand reciprocal square root builtins. */
|
|
|
|
|
|
|
|
static rtx
|
|
|
|
aarch64_expand_builtin_rsqrt (int fcode, tree exp, rtx target)
|
|
|
|
{
|
|
|
|
tree arg0 = CALL_EXPR_ARG (exp, 0);
|
|
|
|
rtx op0 = expand_normal (arg0);
|
|
|
|
|
|
|
|
rtx (*gen) (rtx, rtx);
|
|
|
|
|
|
|
|
switch (fcode)
|
|
|
|
{
|
|
|
|
case AARCH64_BUILTIN_RSQRT_DF:
|
Add an rsqrt_optab and IFN_RSQRT internal function
All current uses of builtin_reciprocal convert 1.0/sqrt into rsqrt.
This patch adds an rsqrt optab and associated internal function for
that instead. We can then pick up the vector forms of rsqrt automatically,
fixing an AArch64 regression from my internal_fn patches.
With that change, builtin_reciprocal only needs to handle target-specific
built-in functions. I've restricted the hook to those since, if we need
a reciprocal of another standard function later, I think there should be
a strong preference for adding a new optab and internal function for it,
rather than hiding the code in a backend.
Three targets implement builtin_reciprocal: aarch64, i386 and rs6000.
i386 and rs6000 already used the obvious rsqrt<mode>2 pattern names
for the instructions, so they pick up the new code automatically.
aarch64 needs a slight rename.
mn10300 is unusual in that its native operation is rsqrt, and
sqrt is approximated as 1.0/rsqrt. The port also uses rsqrt<mode>2
for the rsqrt pattern, so after the patch we now pick it up as a native
operation.
Two other ports define rsqrt patterns: sh and v850. AFAICT these
patterns aren't currently used, but I think the patch does what the
authors of the patterns would have expected. There's obviously some
risk of fallout though.
Tested on x86_64-linux-gnu, aarch64-linux-gnu, arm-linux-gnueabihf
(as a target without the hooks) and powerpc64-linux-gnu.
gcc/
* internal-fn.def (RSQRT): New function.
* optabs.def (rsqrt_optab): New optab.
* doc/md.texi (rsqrtM2): Document.
* target.def (builtin_reciprocal): Replace gcall argument with
a function decl. Restrict hook to machine functions.
* doc/tm.texi: Regenerate.
* targhooks.h (default_builtin_reciprocal): Update prototype.
* targhooks.c (default_builtin_reciprocal): Likewise.
* tree-ssa-math-opts.c: Include internal-fn.h.
(internal_fn_reciprocal): New function.
(pass_cse_reciprocals::execute): Call it, and build a call to an
internal function on success. Only call targetm.builtin_reciprocal
for machine functions.
* config/aarch64/aarch64-protos.h (aarch64_builtin_rsqrt): Remove
second argument.
* config/aarch64/aarch64-builtins.c (aarch64_expand_builtin_rsqrt):
Rename aarch64_rsqrt_<mode>2 to rsqrt<mode>2.
(aarch64_builtin_rsqrt): Remove md_fn argument and only handle
machine functions.
* config/aarch64/aarch64.c (use_rsqrt_p): New function.
(aarch64_builtin_reciprocal): Replace gcall argument with a
function decl. Use use_rsqrt_p. Remove optimize_size check.
Only handle machine functions. Update call to aarch64_builtin_rsqrt.
(aarch64_optab_supported_p): New function.
(TARGET_OPTAB_SUPPORTED_P): Define.
* config/aarch64/aarch64-simd.md (aarch64_rsqrt_<mode>2): Rename to...
(rsqrt<mode>2): ...this.
* config/i386/i386.c (use_rsqrt_p): New function.
(ix86_builtin_reciprocal): Replace gcall argument with a
function decl. Use use_rsqrt_p. Remove optimize_insn_for_size_p
check. Only handle machine functions.
(ix86_optab_supported_p): Handle rsqrt_optab.
* config/rs6000/rs6000.c (TARGET_OPTAB_SUPPORTED_P): Define.
(rs6000_builtin_reciprocal): Replace gcall argument with a
function decl. Remove optimize_insn_for_size_p check.
Only handle machine functions.
(rs6000_optab_supported_p): New function.
From-SVN: r231229
2015-12-03 15:31:55 +01:00
|
|
|
gen = gen_rsqrtdf2;
|
2015-11-06 18:10:17 +01:00
|
|
|
break;
|
|
|
|
case AARCH64_BUILTIN_RSQRT_SF:
|
Add an rsqrt_optab and IFN_RSQRT internal function
All current uses of builtin_reciprocal convert 1.0/sqrt into rsqrt.
This patch adds an rsqrt optab and associated internal function for
that instead. We can then pick up the vector forms of rsqrt automatically,
fixing an AArch64 regression from my internal_fn patches.
With that change, builtin_reciprocal only needs to handle target-specific
built-in functions. I've restricted the hook to those since, if we need
a reciprocal of another standard function later, I think there should be
a strong preference for adding a new optab and internal function for it,
rather than hiding the code in a backend.
Three targets implement builtin_reciprocal: aarch64, i386 and rs6000.
i386 and rs6000 already used the obvious rsqrt<mode>2 pattern names
for the instructions, so they pick up the new code automatically.
aarch64 needs a slight rename.
mn10300 is unusual in that its native operation is rsqrt, and
sqrt is approximated as 1.0/rsqrt. The port also uses rsqrt<mode>2
for the rsqrt pattern, so after the patch we now pick it up as a native
operation.
Two other ports define rsqrt patterns: sh and v850. AFAICT these
patterns aren't currently used, but I think the patch does what the
authors of the patterns would have expected. There's obviously some
risk of fallout though.
Tested on x86_64-linux-gnu, aarch64-linux-gnu, arm-linux-gnueabihf
(as a target without the hooks) and powerpc64-linux-gnu.
gcc/
* internal-fn.def (RSQRT): New function.
* optabs.def (rsqrt_optab): New optab.
* doc/md.texi (rsqrtM2): Document.
* target.def (builtin_reciprocal): Replace gcall argument with
a function decl. Restrict hook to machine functions.
* doc/tm.texi: Regenerate.
* targhooks.h (default_builtin_reciprocal): Update prototype.
* targhooks.c (default_builtin_reciprocal): Likewise.
* tree-ssa-math-opts.c: Include internal-fn.h.
(internal_fn_reciprocal): New function.
(pass_cse_reciprocals::execute): Call it, and build a call to an
internal function on success. Only call targetm.builtin_reciprocal
for machine functions.
* config/aarch64/aarch64-protos.h (aarch64_builtin_rsqrt): Remove
second argument.
* config/aarch64/aarch64-builtins.c (aarch64_expand_builtin_rsqrt):
Rename aarch64_rsqrt_<mode>2 to rsqrt<mode>2.
(aarch64_builtin_rsqrt): Remove md_fn argument and only handle
machine functions.
* config/aarch64/aarch64.c (use_rsqrt_p): New function.
(aarch64_builtin_reciprocal): Replace gcall argument with a
function decl. Use use_rsqrt_p. Remove optimize_size check.
Only handle machine functions. Update call to aarch64_builtin_rsqrt.
(aarch64_optab_supported_p): New function.
(TARGET_OPTAB_SUPPORTED_P): Define.
* config/aarch64/aarch64-simd.md (aarch64_rsqrt_<mode>2): Rename to...
(rsqrt<mode>2): ...this.
* config/i386/i386.c (use_rsqrt_p): New function.
(ix86_builtin_reciprocal): Replace gcall argument with a
function decl. Use use_rsqrt_p. Remove optimize_insn_for_size_p
check. Only handle machine functions.
(ix86_optab_supported_p): Handle rsqrt_optab.
* config/rs6000/rs6000.c (TARGET_OPTAB_SUPPORTED_P): Define.
(rs6000_builtin_reciprocal): Replace gcall argument with a
function decl. Remove optimize_insn_for_size_p check.
Only handle machine functions.
(rs6000_optab_supported_p): New function.
From-SVN: r231229
2015-12-03 15:31:55 +01:00
|
|
|
gen = gen_rsqrtsf2;
|
2015-11-06 18:10:17 +01:00
|
|
|
break;
|
|
|
|
case AARCH64_BUILTIN_RSQRT_V2DF:
|
Add an rsqrt_optab and IFN_RSQRT internal function
All current uses of builtin_reciprocal convert 1.0/sqrt into rsqrt.
This patch adds an rsqrt optab and associated internal function for
that instead. We can then pick up the vector forms of rsqrt automatically,
fixing an AArch64 regression from my internal_fn patches.
With that change, builtin_reciprocal only needs to handle target-specific
built-in functions. I've restricted the hook to those since, if we need
a reciprocal of another standard function later, I think there should be
a strong preference for adding a new optab and internal function for it,
rather than hiding the code in a backend.
Three targets implement builtin_reciprocal: aarch64, i386 and rs6000.
i386 and rs6000 already used the obvious rsqrt<mode>2 pattern names
for the instructions, so they pick up the new code automatically.
aarch64 needs a slight rename.
mn10300 is unusual in that its native operation is rsqrt, and
sqrt is approximated as 1.0/rsqrt. The port also uses rsqrt<mode>2
for the rsqrt pattern, so after the patch we now pick it up as a native
operation.
Two other ports define rsqrt patterns: sh and v850. AFAICT these
patterns aren't currently used, but I think the patch does what the
authors of the patterns would have expected. There's obviously some
risk of fallout though.
Tested on x86_64-linux-gnu, aarch64-linux-gnu, arm-linux-gnueabihf
(as a target without the hooks) and powerpc64-linux-gnu.
gcc/
* internal-fn.def (RSQRT): New function.
* optabs.def (rsqrt_optab): New optab.
* doc/md.texi (rsqrtM2): Document.
* target.def (builtin_reciprocal): Replace gcall argument with
a function decl. Restrict hook to machine functions.
* doc/tm.texi: Regenerate.
* targhooks.h (default_builtin_reciprocal): Update prototype.
* targhooks.c (default_builtin_reciprocal): Likewise.
* tree-ssa-math-opts.c: Include internal-fn.h.
(internal_fn_reciprocal): New function.
(pass_cse_reciprocals::execute): Call it, and build a call to an
internal function on success. Only call targetm.builtin_reciprocal
for machine functions.
* config/aarch64/aarch64-protos.h (aarch64_builtin_rsqrt): Remove
second argument.
* config/aarch64/aarch64-builtins.c (aarch64_expand_builtin_rsqrt):
Rename aarch64_rsqrt_<mode>2 to rsqrt<mode>2.
(aarch64_builtin_rsqrt): Remove md_fn argument and only handle
machine functions.
* config/aarch64/aarch64.c (use_rsqrt_p): New function.
(aarch64_builtin_reciprocal): Replace gcall argument with a
function decl. Use use_rsqrt_p. Remove optimize_size check.
Only handle machine functions. Update call to aarch64_builtin_rsqrt.
(aarch64_optab_supported_p): New function.
(TARGET_OPTAB_SUPPORTED_P): Define.
* config/aarch64/aarch64-simd.md (aarch64_rsqrt_<mode>2): Rename to...
(rsqrt<mode>2): ...this.
* config/i386/i386.c (use_rsqrt_p): New function.
(ix86_builtin_reciprocal): Replace gcall argument with a
function decl. Use use_rsqrt_p. Remove optimize_insn_for_size_p
check. Only handle machine functions.
(ix86_optab_supported_p): Handle rsqrt_optab.
* config/rs6000/rs6000.c (TARGET_OPTAB_SUPPORTED_P): Define.
(rs6000_builtin_reciprocal): Replace gcall argument with a
function decl. Remove optimize_insn_for_size_p check.
Only handle machine functions.
(rs6000_optab_supported_p): New function.
From-SVN: r231229
2015-12-03 15:31:55 +01:00
|
|
|
gen = gen_rsqrtv2df2;
|
2015-11-06 18:10:17 +01:00
|
|
|
break;
|
|
|
|
case AARCH64_BUILTIN_RSQRT_V2SF:
|
Add an rsqrt_optab and IFN_RSQRT internal function
All current uses of builtin_reciprocal convert 1.0/sqrt into rsqrt.
This patch adds an rsqrt optab and associated internal function for
that instead. We can then pick up the vector forms of rsqrt automatically,
fixing an AArch64 regression from my internal_fn patches.
With that change, builtin_reciprocal only needs to handle target-specific
built-in functions. I've restricted the hook to those since, if we need
a reciprocal of another standard function later, I think there should be
a strong preference for adding a new optab and internal function for it,
rather than hiding the code in a backend.
Three targets implement builtin_reciprocal: aarch64, i386 and rs6000.
i386 and rs6000 already used the obvious rsqrt<mode>2 pattern names
for the instructions, so they pick up the new code automatically.
aarch64 needs a slight rename.
mn10300 is unusual in that its native operation is rsqrt, and
sqrt is approximated as 1.0/rsqrt. The port also uses rsqrt<mode>2
for the rsqrt pattern, so after the patch we now pick it up as a native
operation.
Two other ports define rsqrt patterns: sh and v850. AFAICT these
patterns aren't currently used, but I think the patch does what the
authors of the patterns would have expected. There's obviously some
risk of fallout though.
Tested on x86_64-linux-gnu, aarch64-linux-gnu, arm-linux-gnueabihf
(as a target without the hooks) and powerpc64-linux-gnu.
gcc/
* internal-fn.def (RSQRT): New function.
* optabs.def (rsqrt_optab): New optab.
* doc/md.texi (rsqrtM2): Document.
* target.def (builtin_reciprocal): Replace gcall argument with
a function decl. Restrict hook to machine functions.
* doc/tm.texi: Regenerate.
* targhooks.h (default_builtin_reciprocal): Update prototype.
* targhooks.c (default_builtin_reciprocal): Likewise.
* tree-ssa-math-opts.c: Include internal-fn.h.
(internal_fn_reciprocal): New function.
(pass_cse_reciprocals::execute): Call it, and build a call to an
internal function on success. Only call targetm.builtin_reciprocal
for machine functions.
* config/aarch64/aarch64-protos.h (aarch64_builtin_rsqrt): Remove
second argument.
* config/aarch64/aarch64-builtins.c (aarch64_expand_builtin_rsqrt):
Rename aarch64_rsqrt_<mode>2 to rsqrt<mode>2.
(aarch64_builtin_rsqrt): Remove md_fn argument and only handle
machine functions.
* config/aarch64/aarch64.c (use_rsqrt_p): New function.
(aarch64_builtin_reciprocal): Replace gcall argument with a
function decl. Use use_rsqrt_p. Remove optimize_size check.
Only handle machine functions. Update call to aarch64_builtin_rsqrt.
(aarch64_optab_supported_p): New function.
(TARGET_OPTAB_SUPPORTED_P): Define.
* config/aarch64/aarch64-simd.md (aarch64_rsqrt_<mode>2): Rename to...
(rsqrt<mode>2): ...this.
* config/i386/i386.c (use_rsqrt_p): New function.
(ix86_builtin_reciprocal): Replace gcall argument with a
function decl. Use use_rsqrt_p. Remove optimize_insn_for_size_p
check. Only handle machine functions.
(ix86_optab_supported_p): Handle rsqrt_optab.
* config/rs6000/rs6000.c (TARGET_OPTAB_SUPPORTED_P): Define.
(rs6000_builtin_reciprocal): Replace gcall argument with a
function decl. Remove optimize_insn_for_size_p check.
Only handle machine functions.
(rs6000_optab_supported_p): New function.
From-SVN: r231229
2015-12-03 15:31:55 +01:00
|
|
|
gen = gen_rsqrtv2sf2;
|
2015-11-06 18:10:17 +01:00
|
|
|
break;
|
|
|
|
case AARCH64_BUILTIN_RSQRT_V4SF:
|
Add an rsqrt_optab and IFN_RSQRT internal function
All current uses of builtin_reciprocal convert 1.0/sqrt into rsqrt.
This patch adds an rsqrt optab and associated internal function for
that instead. We can then pick up the vector forms of rsqrt automatically,
fixing an AArch64 regression from my internal_fn patches.
With that change, builtin_reciprocal only needs to handle target-specific
built-in functions. I've restricted the hook to those since, if we need
a reciprocal of another standard function later, I think there should be
a strong preference for adding a new optab and internal function for it,
rather than hiding the code in a backend.
Three targets implement builtin_reciprocal: aarch64, i386 and rs6000.
i386 and rs6000 already used the obvious rsqrt<mode>2 pattern names
for the instructions, so they pick up the new code automatically.
aarch64 needs a slight rename.
mn10300 is unusual in that its native operation is rsqrt, and
sqrt is approximated as 1.0/rsqrt. The port also uses rsqrt<mode>2
for the rsqrt pattern, so after the patch we now pick it up as a native
operation.
Two other ports define rsqrt patterns: sh and v850. AFAICT these
patterns aren't currently used, but I think the patch does what the
authors of the patterns would have expected. There's obviously some
risk of fallout though.
Tested on x86_64-linux-gnu, aarch64-linux-gnu, arm-linux-gnueabihf
(as a target without the hooks) and powerpc64-linux-gnu.
gcc/
* internal-fn.def (RSQRT): New function.
* optabs.def (rsqrt_optab): New optab.
* doc/md.texi (rsqrtM2): Document.
* target.def (builtin_reciprocal): Replace gcall argument with
a function decl. Restrict hook to machine functions.
* doc/tm.texi: Regenerate.
* targhooks.h (default_builtin_reciprocal): Update prototype.
* targhooks.c (default_builtin_reciprocal): Likewise.
* tree-ssa-math-opts.c: Include internal-fn.h.
(internal_fn_reciprocal): New function.
(pass_cse_reciprocals::execute): Call it, and build a call to an
internal function on success. Only call targetm.builtin_reciprocal
for machine functions.
* config/aarch64/aarch64-protos.h (aarch64_builtin_rsqrt): Remove
second argument.
* config/aarch64/aarch64-builtins.c (aarch64_expand_builtin_rsqrt):
Rename aarch64_rsqrt_<mode>2 to rsqrt<mode>2.
(aarch64_builtin_rsqrt): Remove md_fn argument and only handle
machine functions.
* config/aarch64/aarch64.c (use_rsqrt_p): New function.
(aarch64_builtin_reciprocal): Replace gcall argument with a
function decl. Use use_rsqrt_p. Remove optimize_size check.
Only handle machine functions. Update call to aarch64_builtin_rsqrt.
(aarch64_optab_supported_p): New function.
(TARGET_OPTAB_SUPPORTED_P): Define.
* config/aarch64/aarch64-simd.md (aarch64_rsqrt_<mode>2): Rename to...
(rsqrt<mode>2): ...this.
* config/i386/i386.c (use_rsqrt_p): New function.
(ix86_builtin_reciprocal): Replace gcall argument with a
function decl. Use use_rsqrt_p. Remove optimize_insn_for_size_p
check. Only handle machine functions.
(ix86_optab_supported_p): Handle rsqrt_optab.
* config/rs6000/rs6000.c (TARGET_OPTAB_SUPPORTED_P): Define.
(rs6000_builtin_reciprocal): Replace gcall argument with a
function decl. Remove optimize_insn_for_size_p check.
Only handle machine functions.
(rs6000_optab_supported_p): New function.
From-SVN: r231229
2015-12-03 15:31:55 +01:00
|
|
|
gen = gen_rsqrtv4sf2;
|
2015-11-06 18:10:17 +01:00
|
|
|
break;
|
|
|
|
default: gcc_unreachable ();
|
|
|
|
}
|
|
|
|
|
|
|
|
if (!target)
|
|
|
|
target = gen_reg_rtx (GET_MODE (op0));
|
|
|
|
|
|
|
|
emit_insn (gen (target, op0));
|
|
|
|
|
|
|
|
return target;
|
|
|
|
}
|
|
|
|
|
aarch64-builtins.c (enum aarch64_type_qualifiers): Add qualifier_lane_pair_index.
gcc/ChangeLog:
2019-01-10 Tamar Christina <tamar.christina@arm.com>
* config/aarch64/aarch64-builtins.c (enum aarch64_type_qualifiers): Add qualifier_lane_pair_index.
(emit-rtl.h): Include.
(TYPES_QUADOP_LANE_PAIR): New.
(aarch64_simd_expand_args): Use it.
(aarch64_simd_expand_builtin): Likewise.
(AARCH64_SIMD_FCMLA_LANEQ_BUILTINS, aarch64_fcmla_laneq_builtin_datum): New.
(FCMLA_LANEQ_BUILTIN, AARCH64_SIMD_FCMLA_LANEQ_BUILTIN_BASE,
AARCH64_SIMD_FCMLA_LANEQ_BUILTINS, aarch64_fcmla_lane_builtin_data,
aarch64_init_fcmla_laneq_builtins, aarch64_expand_fcmla_builtin): New.
(aarch64_init_builtins): Add aarch64_init_fcmla_laneq_builtins.
(aarch64_expand_buildin): Add AARCH64_SIMD_BUILTIN_FCMLA_LANEQ0_V2SF,
AARCH64_SIMD_BUILTIN_FCMLA_LANEQ90_V2SF, AARCH64_SIMD_BUILTIN_FCMLA_LANEQ180_V2SF,
AARCH64_SIMD_BUILTIN_FCMLA_LANEQ2700_V2SF, AARCH64_SIMD_BUILTIN_FCMLA_LANEQ0_V4HF,
AARCH64_SIMD_BUILTIN_FCMLA_LANEQ90_V4HF, AARCH64_SIMD_BUILTIN_FCMLA_LANEQ180_V4HF,
AARCH64_SIMD_BUILTIN_FCMLA_LANEQ270_V4HF.
* config/aarch64/iterators.md (FCMLA_maybe_lane): New.
* config/aarch64/aarch64-c.c (aarch64_update_cpp_builtins): Add __ARM_FEATURE_COMPLEX.
* config/aarch64/aarch64-simd-builtins.def (fcadd90, fcadd270, fcmla0, fcmla90,
fcmla180, fcmla270, fcmla_lane0, fcmla_lane90, fcmla_lane180, fcmla_lane270,
fcmla_laneq0, fcmla_laneq90, fcmla_laneq180, fcmla_laneq270,
fcmlaq_lane0, fcmlaq_lane90, fcmlaq_lane180, fcmlaq_lane270): New.
* config/aarch64/aarch64-simd.md (aarch64_fcmla_lane<rot><mode>,
aarch64_fcmla_laneq<rot>v4hf, aarch64_fcmlaq_lane<rot><mode>,aarch64_fcadd<rot><mode>,
aarch64_fcmla<rot><mode>): New.
* config/aarch64/arm_neon.h:
(vcadd_rot90_f16): New.
(vcaddq_rot90_f16): New.
(vcadd_rot270_f16): New.
(vcaddq_rot270_f16): New.
(vcmla_f16): New.
(vcmlaq_f16): New.
(vcmla_lane_f16): New.
(vcmla_laneq_f16): New.
(vcmlaq_lane_f16): New.
(vcmlaq_rot90_lane_f16): New.
(vcmla_rot90_laneq_f16): New.
(vcmla_rot90_lane_f16): New.
(vcmlaq_rot90_f16): New.
(vcmla_rot90_f16): New.
(vcmlaq_laneq_f16): New.
(vcmla_rot180_laneq_f16): New.
(vcmla_rot180_lane_f16): New.
(vcmlaq_rot180_f16): New.
(vcmla_rot180_f16): New.
(vcmlaq_rot90_laneq_f16): New.
(vcmlaq_rot270_laneq_f16): New.
(vcmlaq_rot270_lane_f16): New.
(vcmla_rot270_laneq_f16): New.
(vcmlaq_rot270_f16): New.
(vcmla_rot270_f16): New.
(vcmlaq_rot180_laneq_f16): New.
(vcmlaq_rot180_lane_f16): New.
(vcmla_rot270_lane_f16): New.
(vcadd_rot90_f32): New.
(vcaddq_rot90_f32): New.
(vcaddq_rot90_f64): New.
(vcadd_rot270_f32): New.
(vcaddq_rot270_f32): New.
(vcaddq_rot270_f64): New.
(vcmla_f32): New.
(vcmlaq_f32): New.
(vcmlaq_f64): New.
(vcmla_lane_f32): New.
(vcmla_laneq_f32): New.
(vcmlaq_lane_f32): New.
(vcmlaq_laneq_f32): New.
(vcmla_rot90_f32): New.
(vcmlaq_rot90_f32): New.
(vcmlaq_rot90_f64): New.
(vcmla_rot90_lane_f32): New.
(vcmla_rot90_laneq_f32): New.
(vcmlaq_rot90_lane_f32): New.
(vcmlaq_rot90_laneq_f32): New.
(vcmla_rot180_f32): New.
(vcmlaq_rot180_f32): New.
(vcmlaq_rot180_f64): New.
(vcmla_rot180_lane_f32): New.
(vcmla_rot180_laneq_f32): New.
(vcmlaq_rot180_lane_f32): New.
(vcmlaq_rot180_laneq_f32): New.
(vcmla_rot270_f32): New.
(vcmlaq_rot270_f32): New.
(vcmlaq_rot270_f64): New.
(vcmla_rot270_lane_f32): New.
(vcmla_rot270_laneq_f32): New.
(vcmlaq_rot270_lane_f32): New.
(vcmlaq_rot270_laneq_f32): New.
* config/aarch64/aarch64.h (TARGET_COMPLEX): New.
* config/aarch64/iterators.md (UNSPEC_FCADD90, UNSPEC_FCADD270,
UNSPEC_FCMLA, UNSPEC_FCMLA90, UNSPEC_FCMLA180, UNSPEC_FCMLA270): New.
(FCADD, FCMLA): New.
(rot): New.
* config/arm/types.md (neon_fcadd, neon_fcmla): New.
gcc/testsuite/ChangeLog:
2019-01-10 Tamar Christina <tamar.christina@arm.com>
* gcc.target/aarch64/advsimd-intrinsics/vector-complex.c: New test.
* gcc.target/aarch64/advsimd-intrinsics/vector-complex_f16.c: New test.
From-SVN: r267795
2019-01-10 04:30:59 +01:00
|
|
|
/* Expand a FCMLA lane expression EXP with code FCODE and
|
|
|
|
result going to TARGET if that is convenient. */
|
|
|
|
|
|
|
|
rtx
|
|
|
|
aarch64_expand_fcmla_builtin (tree exp, rtx target, int fcode)
|
|
|
|
{
|
|
|
|
int bcode = fcode - AARCH64_SIMD_FCMLA_LANEQ_BUILTIN_BASE - 1;
|
|
|
|
aarch64_fcmla_laneq_builtin_datum* d
|
|
|
|
= &aarch64_fcmla_lane_builtin_data[bcode];
|
|
|
|
machine_mode quadmode = GET_MODE_2XWIDER_MODE (d->mode).require ();
|
|
|
|
rtx op0 = force_reg (d->mode, expand_normal (CALL_EXPR_ARG (exp, 0)));
|
|
|
|
rtx op1 = force_reg (d->mode, expand_normal (CALL_EXPR_ARG (exp, 1)));
|
|
|
|
rtx op2 = force_reg (quadmode, expand_normal (CALL_EXPR_ARG (exp, 2)));
|
|
|
|
tree tmp = CALL_EXPR_ARG (exp, 3);
|
|
|
|
rtx lane_idx = expand_expr (tmp, NULL_RTX, VOIDmode, EXPAND_INITIALIZER);
|
|
|
|
|
|
|
|
/* Validate that the lane index is a constant. */
|
|
|
|
if (!CONST_INT_P (lane_idx))
|
|
|
|
{
|
2021-07-06 21:45:54 +02:00
|
|
|
error_at (EXPR_LOCATION (exp),
|
|
|
|
"argument %d must be a constant immediate", 4);
|
aarch64-builtins.c (enum aarch64_type_qualifiers): Add qualifier_lane_pair_index.
gcc/ChangeLog:
2019-01-10 Tamar Christina <tamar.christina@arm.com>
* config/aarch64/aarch64-builtins.c (enum aarch64_type_qualifiers): Add qualifier_lane_pair_index.
(emit-rtl.h): Include.
(TYPES_QUADOP_LANE_PAIR): New.
(aarch64_simd_expand_args): Use it.
(aarch64_simd_expand_builtin): Likewise.
(AARCH64_SIMD_FCMLA_LANEQ_BUILTINS, aarch64_fcmla_laneq_builtin_datum): New.
(FCMLA_LANEQ_BUILTIN, AARCH64_SIMD_FCMLA_LANEQ_BUILTIN_BASE,
AARCH64_SIMD_FCMLA_LANEQ_BUILTINS, aarch64_fcmla_lane_builtin_data,
aarch64_init_fcmla_laneq_builtins, aarch64_expand_fcmla_builtin): New.
(aarch64_init_builtins): Add aarch64_init_fcmla_laneq_builtins.
(aarch64_expand_buildin): Add AARCH64_SIMD_BUILTIN_FCMLA_LANEQ0_V2SF,
AARCH64_SIMD_BUILTIN_FCMLA_LANEQ90_V2SF, AARCH64_SIMD_BUILTIN_FCMLA_LANEQ180_V2SF,
AARCH64_SIMD_BUILTIN_FCMLA_LANEQ2700_V2SF, AARCH64_SIMD_BUILTIN_FCMLA_LANEQ0_V4HF,
AARCH64_SIMD_BUILTIN_FCMLA_LANEQ90_V4HF, AARCH64_SIMD_BUILTIN_FCMLA_LANEQ180_V4HF,
AARCH64_SIMD_BUILTIN_FCMLA_LANEQ270_V4HF.
* config/aarch64/iterators.md (FCMLA_maybe_lane): New.
* config/aarch64/aarch64-c.c (aarch64_update_cpp_builtins): Add __ARM_FEATURE_COMPLEX.
* config/aarch64/aarch64-simd-builtins.def (fcadd90, fcadd270, fcmla0, fcmla90,
fcmla180, fcmla270, fcmla_lane0, fcmla_lane90, fcmla_lane180, fcmla_lane270,
fcmla_laneq0, fcmla_laneq90, fcmla_laneq180, fcmla_laneq270,
fcmlaq_lane0, fcmlaq_lane90, fcmlaq_lane180, fcmlaq_lane270): New.
* config/aarch64/aarch64-simd.md (aarch64_fcmla_lane<rot><mode>,
aarch64_fcmla_laneq<rot>v4hf, aarch64_fcmlaq_lane<rot><mode>,aarch64_fcadd<rot><mode>,
aarch64_fcmla<rot><mode>): New.
* config/aarch64/arm_neon.h:
(vcadd_rot90_f16): New.
(vcaddq_rot90_f16): New.
(vcadd_rot270_f16): New.
(vcaddq_rot270_f16): New.
(vcmla_f16): New.
(vcmlaq_f16): New.
(vcmla_lane_f16): New.
(vcmla_laneq_f16): New.
(vcmlaq_lane_f16): New.
(vcmlaq_rot90_lane_f16): New.
(vcmla_rot90_laneq_f16): New.
(vcmla_rot90_lane_f16): New.
(vcmlaq_rot90_f16): New.
(vcmla_rot90_f16): New.
(vcmlaq_laneq_f16): New.
(vcmla_rot180_laneq_f16): New.
(vcmla_rot180_lane_f16): New.
(vcmlaq_rot180_f16): New.
(vcmla_rot180_f16): New.
(vcmlaq_rot90_laneq_f16): New.
(vcmlaq_rot270_laneq_f16): New.
(vcmlaq_rot270_lane_f16): New.
(vcmla_rot270_laneq_f16): New.
(vcmlaq_rot270_f16): New.
(vcmla_rot270_f16): New.
(vcmlaq_rot180_laneq_f16): New.
(vcmlaq_rot180_lane_f16): New.
(vcmla_rot270_lane_f16): New.
(vcadd_rot90_f32): New.
(vcaddq_rot90_f32): New.
(vcaddq_rot90_f64): New.
(vcadd_rot270_f32): New.
(vcaddq_rot270_f32): New.
(vcaddq_rot270_f64): New.
(vcmla_f32): New.
(vcmlaq_f32): New.
(vcmlaq_f64): New.
(vcmla_lane_f32): New.
(vcmla_laneq_f32): New.
(vcmlaq_lane_f32): New.
(vcmlaq_laneq_f32): New.
(vcmla_rot90_f32): New.
(vcmlaq_rot90_f32): New.
(vcmlaq_rot90_f64): New.
(vcmla_rot90_lane_f32): New.
(vcmla_rot90_laneq_f32): New.
(vcmlaq_rot90_lane_f32): New.
(vcmlaq_rot90_laneq_f32): New.
(vcmla_rot180_f32): New.
(vcmlaq_rot180_f32): New.
(vcmlaq_rot180_f64): New.
(vcmla_rot180_lane_f32): New.
(vcmla_rot180_laneq_f32): New.
(vcmlaq_rot180_lane_f32): New.
(vcmlaq_rot180_laneq_f32): New.
(vcmla_rot270_f32): New.
(vcmlaq_rot270_f32): New.
(vcmlaq_rot270_f64): New.
(vcmla_rot270_lane_f32): New.
(vcmla_rot270_laneq_f32): New.
(vcmlaq_rot270_lane_f32): New.
(vcmlaq_rot270_laneq_f32): New.
* config/aarch64/aarch64.h (TARGET_COMPLEX): New.
* config/aarch64/iterators.md (UNSPEC_FCADD90, UNSPEC_FCADD270,
UNSPEC_FCMLA, UNSPEC_FCMLA90, UNSPEC_FCMLA180, UNSPEC_FCMLA270): New.
(FCADD, FCMLA): New.
(rot): New.
* config/arm/types.md (neon_fcadd, neon_fcmla): New.
gcc/testsuite/ChangeLog:
2019-01-10 Tamar Christina <tamar.christina@arm.com>
* gcc.target/aarch64/advsimd-intrinsics/vector-complex.c: New test.
* gcc.target/aarch64/advsimd-intrinsics/vector-complex_f16.c: New test.
From-SVN: r267795
2019-01-10 04:30:59 +01:00
|
|
|
return const0_rtx;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Validate that the index is within the expected range. */
|
|
|
|
int nunits = GET_MODE_NUNITS (quadmode).to_constant ();
|
|
|
|
aarch64_simd_lane_bounds (lane_idx, 0, nunits / 2, exp);
|
|
|
|
|
|
|
|
/* Generate the correct register and mode. */
|
|
|
|
int lane = INTVAL (lane_idx);
|
|
|
|
|
|
|
|
if (lane < nunits / 4)
|
2019-01-16 19:29:00 +01:00
|
|
|
op2 = simplify_gen_subreg (d->mode, op2, quadmode,
|
|
|
|
subreg_lowpart_offset (d->mode, quadmode));
|
aarch64-builtins.c (enum aarch64_type_qualifiers): Add qualifier_lane_pair_index.
gcc/ChangeLog:
2019-01-10 Tamar Christina <tamar.christina@arm.com>
* config/aarch64/aarch64-builtins.c (enum aarch64_type_qualifiers): Add qualifier_lane_pair_index.
(emit-rtl.h): Include.
(TYPES_QUADOP_LANE_PAIR): New.
(aarch64_simd_expand_args): Use it.
(aarch64_simd_expand_builtin): Likewise.
(AARCH64_SIMD_FCMLA_LANEQ_BUILTINS, aarch64_fcmla_laneq_builtin_datum): New.
(FCMLA_LANEQ_BUILTIN, AARCH64_SIMD_FCMLA_LANEQ_BUILTIN_BASE,
AARCH64_SIMD_FCMLA_LANEQ_BUILTINS, aarch64_fcmla_lane_builtin_data,
aarch64_init_fcmla_laneq_builtins, aarch64_expand_fcmla_builtin): New.
(aarch64_init_builtins): Add aarch64_init_fcmla_laneq_builtins.
(aarch64_expand_buildin): Add AARCH64_SIMD_BUILTIN_FCMLA_LANEQ0_V2SF,
AARCH64_SIMD_BUILTIN_FCMLA_LANEQ90_V2SF, AARCH64_SIMD_BUILTIN_FCMLA_LANEQ180_V2SF,
AARCH64_SIMD_BUILTIN_FCMLA_LANEQ2700_V2SF, AARCH64_SIMD_BUILTIN_FCMLA_LANEQ0_V4HF,
AARCH64_SIMD_BUILTIN_FCMLA_LANEQ90_V4HF, AARCH64_SIMD_BUILTIN_FCMLA_LANEQ180_V4HF,
AARCH64_SIMD_BUILTIN_FCMLA_LANEQ270_V4HF.
* config/aarch64/iterators.md (FCMLA_maybe_lane): New.
* config/aarch64/aarch64-c.c (aarch64_update_cpp_builtins): Add __ARM_FEATURE_COMPLEX.
* config/aarch64/aarch64-simd-builtins.def (fcadd90, fcadd270, fcmla0, fcmla90,
fcmla180, fcmla270, fcmla_lane0, fcmla_lane90, fcmla_lane180, fcmla_lane270,
fcmla_laneq0, fcmla_laneq90, fcmla_laneq180, fcmla_laneq270,
fcmlaq_lane0, fcmlaq_lane90, fcmlaq_lane180, fcmlaq_lane270): New.
* config/aarch64/aarch64-simd.md (aarch64_fcmla_lane<rot><mode>,
aarch64_fcmla_laneq<rot>v4hf, aarch64_fcmlaq_lane<rot><mode>,aarch64_fcadd<rot><mode>,
aarch64_fcmla<rot><mode>): New.
* config/aarch64/arm_neon.h:
(vcadd_rot90_f16): New.
(vcaddq_rot90_f16): New.
(vcadd_rot270_f16): New.
(vcaddq_rot270_f16): New.
(vcmla_f16): New.
(vcmlaq_f16): New.
(vcmla_lane_f16): New.
(vcmla_laneq_f16): New.
(vcmlaq_lane_f16): New.
(vcmlaq_rot90_lane_f16): New.
(vcmla_rot90_laneq_f16): New.
(vcmla_rot90_lane_f16): New.
(vcmlaq_rot90_f16): New.
(vcmla_rot90_f16): New.
(vcmlaq_laneq_f16): New.
(vcmla_rot180_laneq_f16): New.
(vcmla_rot180_lane_f16): New.
(vcmlaq_rot180_f16): New.
(vcmla_rot180_f16): New.
(vcmlaq_rot90_laneq_f16): New.
(vcmlaq_rot270_laneq_f16): New.
(vcmlaq_rot270_lane_f16): New.
(vcmla_rot270_laneq_f16): New.
(vcmlaq_rot270_f16): New.
(vcmla_rot270_f16): New.
(vcmlaq_rot180_laneq_f16): New.
(vcmlaq_rot180_lane_f16): New.
(vcmla_rot270_lane_f16): New.
(vcadd_rot90_f32): New.
(vcaddq_rot90_f32): New.
(vcaddq_rot90_f64): New.
(vcadd_rot270_f32): New.
(vcaddq_rot270_f32): New.
(vcaddq_rot270_f64): New.
(vcmla_f32): New.
(vcmlaq_f32): New.
(vcmlaq_f64): New.
(vcmla_lane_f32): New.
(vcmla_laneq_f32): New.
(vcmlaq_lane_f32): New.
(vcmlaq_laneq_f32): New.
(vcmla_rot90_f32): New.
(vcmlaq_rot90_f32): New.
(vcmlaq_rot90_f64): New.
(vcmla_rot90_lane_f32): New.
(vcmla_rot90_laneq_f32): New.
(vcmlaq_rot90_lane_f32): New.
(vcmlaq_rot90_laneq_f32): New.
(vcmla_rot180_f32): New.
(vcmlaq_rot180_f32): New.
(vcmlaq_rot180_f64): New.
(vcmla_rot180_lane_f32): New.
(vcmla_rot180_laneq_f32): New.
(vcmlaq_rot180_lane_f32): New.
(vcmlaq_rot180_laneq_f32): New.
(vcmla_rot270_f32): New.
(vcmlaq_rot270_f32): New.
(vcmlaq_rot270_f64): New.
(vcmla_rot270_lane_f32): New.
(vcmla_rot270_laneq_f32): New.
(vcmlaq_rot270_lane_f32): New.
(vcmlaq_rot270_laneq_f32): New.
* config/aarch64/aarch64.h (TARGET_COMPLEX): New.
* config/aarch64/iterators.md (UNSPEC_FCADD90, UNSPEC_FCADD270,
UNSPEC_FCMLA, UNSPEC_FCMLA90, UNSPEC_FCMLA180, UNSPEC_FCMLA270): New.
(FCADD, FCMLA): New.
(rot): New.
* config/arm/types.md (neon_fcadd, neon_fcmla): New.
gcc/testsuite/ChangeLog:
2019-01-10 Tamar Christina <tamar.christina@arm.com>
* gcc.target/aarch64/advsimd-intrinsics/vector-complex.c: New test.
* gcc.target/aarch64/advsimd-intrinsics/vector-complex_f16.c: New test.
From-SVN: r267795
2019-01-10 04:30:59 +01:00
|
|
|
else
|
|
|
|
{
|
|
|
|
/* Select the upper 64 bits, either a V2SF or V4HF, this however
|
|
|
|
is quite messy, as the operation required even though simple
|
|
|
|
doesn't have a simple RTL pattern, and seems it's quite hard to
|
|
|
|
define using a single RTL pattern. The target generic version
|
|
|
|
gen_highpart_mode generates code that isn't optimal. */
|
|
|
|
rtx temp1 = gen_reg_rtx (d->mode);
|
|
|
|
rtx temp2 = gen_reg_rtx (DImode);
|
2019-01-16 19:29:00 +01:00
|
|
|
temp1 = simplify_gen_subreg (d->mode, op2, quadmode,
|
|
|
|
subreg_lowpart_offset (d->mode, quadmode));
|
aarch64-builtins.c (enum aarch64_type_qualifiers): Add qualifier_lane_pair_index.
gcc/ChangeLog:
2019-01-10 Tamar Christina <tamar.christina@arm.com>
* config/aarch64/aarch64-builtins.c (enum aarch64_type_qualifiers): Add qualifier_lane_pair_index.
(emit-rtl.h): Include.
(TYPES_QUADOP_LANE_PAIR): New.
(aarch64_simd_expand_args): Use it.
(aarch64_simd_expand_builtin): Likewise.
(AARCH64_SIMD_FCMLA_LANEQ_BUILTINS, aarch64_fcmla_laneq_builtin_datum): New.
(FCMLA_LANEQ_BUILTIN, AARCH64_SIMD_FCMLA_LANEQ_BUILTIN_BASE,
AARCH64_SIMD_FCMLA_LANEQ_BUILTINS, aarch64_fcmla_lane_builtin_data,
aarch64_init_fcmla_laneq_builtins, aarch64_expand_fcmla_builtin): New.
(aarch64_init_builtins): Add aarch64_init_fcmla_laneq_builtins.
(aarch64_expand_buildin): Add AARCH64_SIMD_BUILTIN_FCMLA_LANEQ0_V2SF,
AARCH64_SIMD_BUILTIN_FCMLA_LANEQ90_V2SF, AARCH64_SIMD_BUILTIN_FCMLA_LANEQ180_V2SF,
AARCH64_SIMD_BUILTIN_FCMLA_LANEQ2700_V2SF, AARCH64_SIMD_BUILTIN_FCMLA_LANEQ0_V4HF,
AARCH64_SIMD_BUILTIN_FCMLA_LANEQ90_V4HF, AARCH64_SIMD_BUILTIN_FCMLA_LANEQ180_V4HF,
AARCH64_SIMD_BUILTIN_FCMLA_LANEQ270_V4HF.
* config/aarch64/iterators.md (FCMLA_maybe_lane): New.
* config/aarch64/aarch64-c.c (aarch64_update_cpp_builtins): Add __ARM_FEATURE_COMPLEX.
* config/aarch64/aarch64-simd-builtins.def (fcadd90, fcadd270, fcmla0, fcmla90,
fcmla180, fcmla270, fcmla_lane0, fcmla_lane90, fcmla_lane180, fcmla_lane270,
fcmla_laneq0, fcmla_laneq90, fcmla_laneq180, fcmla_laneq270,
fcmlaq_lane0, fcmlaq_lane90, fcmlaq_lane180, fcmlaq_lane270): New.
* config/aarch64/aarch64-simd.md (aarch64_fcmla_lane<rot><mode>,
aarch64_fcmla_laneq<rot>v4hf, aarch64_fcmlaq_lane<rot><mode>,aarch64_fcadd<rot><mode>,
aarch64_fcmla<rot><mode>): New.
* config/aarch64/arm_neon.h:
(vcadd_rot90_f16): New.
(vcaddq_rot90_f16): New.
(vcadd_rot270_f16): New.
(vcaddq_rot270_f16): New.
(vcmla_f16): New.
(vcmlaq_f16): New.
(vcmla_lane_f16): New.
(vcmla_laneq_f16): New.
(vcmlaq_lane_f16): New.
(vcmlaq_rot90_lane_f16): New.
(vcmla_rot90_laneq_f16): New.
(vcmla_rot90_lane_f16): New.
(vcmlaq_rot90_f16): New.
(vcmla_rot90_f16): New.
(vcmlaq_laneq_f16): New.
(vcmla_rot180_laneq_f16): New.
(vcmla_rot180_lane_f16): New.
(vcmlaq_rot180_f16): New.
(vcmla_rot180_f16): New.
(vcmlaq_rot90_laneq_f16): New.
(vcmlaq_rot270_laneq_f16): New.
(vcmlaq_rot270_lane_f16): New.
(vcmla_rot270_laneq_f16): New.
(vcmlaq_rot270_f16): New.
(vcmla_rot270_f16): New.
(vcmlaq_rot180_laneq_f16): New.
(vcmlaq_rot180_lane_f16): New.
(vcmla_rot270_lane_f16): New.
(vcadd_rot90_f32): New.
(vcaddq_rot90_f32): New.
(vcaddq_rot90_f64): New.
(vcadd_rot270_f32): New.
(vcaddq_rot270_f32): New.
(vcaddq_rot270_f64): New.
(vcmla_f32): New.
(vcmlaq_f32): New.
(vcmlaq_f64): New.
(vcmla_lane_f32): New.
(vcmla_laneq_f32): New.
(vcmlaq_lane_f32): New.
(vcmlaq_laneq_f32): New.
(vcmla_rot90_f32): New.
(vcmlaq_rot90_f32): New.
(vcmlaq_rot90_f64): New.
(vcmla_rot90_lane_f32): New.
(vcmla_rot90_laneq_f32): New.
(vcmlaq_rot90_lane_f32): New.
(vcmlaq_rot90_laneq_f32): New.
(vcmla_rot180_f32): New.
(vcmlaq_rot180_f32): New.
(vcmlaq_rot180_f64): New.
(vcmla_rot180_lane_f32): New.
(vcmla_rot180_laneq_f32): New.
(vcmlaq_rot180_lane_f32): New.
(vcmlaq_rot180_laneq_f32): New.
(vcmla_rot270_f32): New.
(vcmlaq_rot270_f32): New.
(vcmlaq_rot270_f64): New.
(vcmla_rot270_lane_f32): New.
(vcmla_rot270_laneq_f32): New.
(vcmlaq_rot270_lane_f32): New.
(vcmlaq_rot270_laneq_f32): New.
* config/aarch64/aarch64.h (TARGET_COMPLEX): New.
* config/aarch64/iterators.md (UNSPEC_FCADD90, UNSPEC_FCADD270,
UNSPEC_FCMLA, UNSPEC_FCMLA90, UNSPEC_FCMLA180, UNSPEC_FCMLA270): New.
(FCADD, FCMLA): New.
(rot): New.
* config/arm/types.md (neon_fcadd, neon_fcmla): New.
gcc/testsuite/ChangeLog:
2019-01-10 Tamar Christina <tamar.christina@arm.com>
* gcc.target/aarch64/advsimd-intrinsics/vector-complex.c: New test.
* gcc.target/aarch64/advsimd-intrinsics/vector-complex_f16.c: New test.
From-SVN: r267795
2019-01-10 04:30:59 +01:00
|
|
|
temp1 = simplify_gen_subreg (V2DImode, temp1, d->mode, 0);
|
2019-01-16 19:29:00 +01:00
|
|
|
if (BYTES_BIG_ENDIAN)
|
|
|
|
emit_insn (gen_aarch64_get_lanev2di (temp2, temp1, const0_rtx));
|
|
|
|
else
|
|
|
|
emit_insn (gen_aarch64_get_lanev2di (temp2, temp1, const1_rtx));
|
aarch64-builtins.c (enum aarch64_type_qualifiers): Add qualifier_lane_pair_index.
gcc/ChangeLog:
2019-01-10 Tamar Christina <tamar.christina@arm.com>
* config/aarch64/aarch64-builtins.c (enum aarch64_type_qualifiers): Add qualifier_lane_pair_index.
(emit-rtl.h): Include.
(TYPES_QUADOP_LANE_PAIR): New.
(aarch64_simd_expand_args): Use it.
(aarch64_simd_expand_builtin): Likewise.
(AARCH64_SIMD_FCMLA_LANEQ_BUILTINS, aarch64_fcmla_laneq_builtin_datum): New.
(FCMLA_LANEQ_BUILTIN, AARCH64_SIMD_FCMLA_LANEQ_BUILTIN_BASE,
AARCH64_SIMD_FCMLA_LANEQ_BUILTINS, aarch64_fcmla_lane_builtin_data,
aarch64_init_fcmla_laneq_builtins, aarch64_expand_fcmla_builtin): New.
(aarch64_init_builtins): Add aarch64_init_fcmla_laneq_builtins.
(aarch64_expand_buildin): Add AARCH64_SIMD_BUILTIN_FCMLA_LANEQ0_V2SF,
AARCH64_SIMD_BUILTIN_FCMLA_LANEQ90_V2SF, AARCH64_SIMD_BUILTIN_FCMLA_LANEQ180_V2SF,
AARCH64_SIMD_BUILTIN_FCMLA_LANEQ2700_V2SF, AARCH64_SIMD_BUILTIN_FCMLA_LANEQ0_V4HF,
AARCH64_SIMD_BUILTIN_FCMLA_LANEQ90_V4HF, AARCH64_SIMD_BUILTIN_FCMLA_LANEQ180_V4HF,
AARCH64_SIMD_BUILTIN_FCMLA_LANEQ270_V4HF.
* config/aarch64/iterators.md (FCMLA_maybe_lane): New.
* config/aarch64/aarch64-c.c (aarch64_update_cpp_builtins): Add __ARM_FEATURE_COMPLEX.
* config/aarch64/aarch64-simd-builtins.def (fcadd90, fcadd270, fcmla0, fcmla90,
fcmla180, fcmla270, fcmla_lane0, fcmla_lane90, fcmla_lane180, fcmla_lane270,
fcmla_laneq0, fcmla_laneq90, fcmla_laneq180, fcmla_laneq270,
fcmlaq_lane0, fcmlaq_lane90, fcmlaq_lane180, fcmlaq_lane270): New.
* config/aarch64/aarch64-simd.md (aarch64_fcmla_lane<rot><mode>,
aarch64_fcmla_laneq<rot>v4hf, aarch64_fcmlaq_lane<rot><mode>,aarch64_fcadd<rot><mode>,
aarch64_fcmla<rot><mode>): New.
* config/aarch64/arm_neon.h:
(vcadd_rot90_f16): New.
(vcaddq_rot90_f16): New.
(vcadd_rot270_f16): New.
(vcaddq_rot270_f16): New.
(vcmla_f16): New.
(vcmlaq_f16): New.
(vcmla_lane_f16): New.
(vcmla_laneq_f16): New.
(vcmlaq_lane_f16): New.
(vcmlaq_rot90_lane_f16): New.
(vcmla_rot90_laneq_f16): New.
(vcmla_rot90_lane_f16): New.
(vcmlaq_rot90_f16): New.
(vcmla_rot90_f16): New.
(vcmlaq_laneq_f16): New.
(vcmla_rot180_laneq_f16): New.
(vcmla_rot180_lane_f16): New.
(vcmlaq_rot180_f16): New.
(vcmla_rot180_f16): New.
(vcmlaq_rot90_laneq_f16): New.
(vcmlaq_rot270_laneq_f16): New.
(vcmlaq_rot270_lane_f16): New.
(vcmla_rot270_laneq_f16): New.
(vcmlaq_rot270_f16): New.
(vcmla_rot270_f16): New.
(vcmlaq_rot180_laneq_f16): New.
(vcmlaq_rot180_lane_f16): New.
(vcmla_rot270_lane_f16): New.
(vcadd_rot90_f32): New.
(vcaddq_rot90_f32): New.
(vcaddq_rot90_f64): New.
(vcadd_rot270_f32): New.
(vcaddq_rot270_f32): New.
(vcaddq_rot270_f64): New.
(vcmla_f32): New.
(vcmlaq_f32): New.
(vcmlaq_f64): New.
(vcmla_lane_f32): New.
(vcmla_laneq_f32): New.
(vcmlaq_lane_f32): New.
(vcmlaq_laneq_f32): New.
(vcmla_rot90_f32): New.
(vcmlaq_rot90_f32): New.
(vcmlaq_rot90_f64): New.
(vcmla_rot90_lane_f32): New.
(vcmla_rot90_laneq_f32): New.
(vcmlaq_rot90_lane_f32): New.
(vcmlaq_rot90_laneq_f32): New.
(vcmla_rot180_f32): New.
(vcmlaq_rot180_f32): New.
(vcmlaq_rot180_f64): New.
(vcmla_rot180_lane_f32): New.
(vcmla_rot180_laneq_f32): New.
(vcmlaq_rot180_lane_f32): New.
(vcmlaq_rot180_laneq_f32): New.
(vcmla_rot270_f32): New.
(vcmlaq_rot270_f32): New.
(vcmlaq_rot270_f64): New.
(vcmla_rot270_lane_f32): New.
(vcmla_rot270_laneq_f32): New.
(vcmlaq_rot270_lane_f32): New.
(vcmlaq_rot270_laneq_f32): New.
* config/aarch64/aarch64.h (TARGET_COMPLEX): New.
* config/aarch64/iterators.md (UNSPEC_FCADD90, UNSPEC_FCADD270,
UNSPEC_FCMLA, UNSPEC_FCMLA90, UNSPEC_FCMLA180, UNSPEC_FCMLA270): New.
(FCADD, FCMLA): New.
(rot): New.
* config/arm/types.md (neon_fcadd, neon_fcmla): New.
gcc/testsuite/ChangeLog:
2019-01-10 Tamar Christina <tamar.christina@arm.com>
* gcc.target/aarch64/advsimd-intrinsics/vector-complex.c: New test.
* gcc.target/aarch64/advsimd-intrinsics/vector-complex_f16.c: New test.
From-SVN: r267795
2019-01-10 04:30:59 +01:00
|
|
|
op2 = simplify_gen_subreg (d->mode, temp2, GET_MODE (temp2), 0);
|
|
|
|
|
|
|
|
/* And recalculate the index. */
|
|
|
|
lane -= nunits / 4;
|
|
|
|
}
|
|
|
|
|
2019-01-16 19:29:00 +01:00
|
|
|
/* Keep to GCC-vector-extension lane indices in the RTL, only nunits / 4
|
|
|
|
(max nunits in range check) are valid. Which means only 0-1, so we
|
|
|
|
only need to know the order in a V2mode. */
|
|
|
|
lane_idx = aarch64_endian_lane_rtx (V2DImode, lane);
|
|
|
|
|
2020-11-06 17:17:32 +01:00
|
|
|
if (!target
|
|
|
|
|| !REG_P (target)
|
|
|
|
|| GET_MODE (target) != d->mode)
|
aarch64-builtins.c (enum aarch64_type_qualifiers): Add qualifier_lane_pair_index.
gcc/ChangeLog:
2019-01-10 Tamar Christina <tamar.christina@arm.com>
* config/aarch64/aarch64-builtins.c (enum aarch64_type_qualifiers): Add qualifier_lane_pair_index.
(emit-rtl.h): Include.
(TYPES_QUADOP_LANE_PAIR): New.
(aarch64_simd_expand_args): Use it.
(aarch64_simd_expand_builtin): Likewise.
(AARCH64_SIMD_FCMLA_LANEQ_BUILTINS, aarch64_fcmla_laneq_builtin_datum): New.
(FCMLA_LANEQ_BUILTIN, AARCH64_SIMD_FCMLA_LANEQ_BUILTIN_BASE,
AARCH64_SIMD_FCMLA_LANEQ_BUILTINS, aarch64_fcmla_lane_builtin_data,
aarch64_init_fcmla_laneq_builtins, aarch64_expand_fcmla_builtin): New.
(aarch64_init_builtins): Add aarch64_init_fcmla_laneq_builtins.
(aarch64_expand_buildin): Add AARCH64_SIMD_BUILTIN_FCMLA_LANEQ0_V2SF,
AARCH64_SIMD_BUILTIN_FCMLA_LANEQ90_V2SF, AARCH64_SIMD_BUILTIN_FCMLA_LANEQ180_V2SF,
AARCH64_SIMD_BUILTIN_FCMLA_LANEQ2700_V2SF, AARCH64_SIMD_BUILTIN_FCMLA_LANEQ0_V4HF,
AARCH64_SIMD_BUILTIN_FCMLA_LANEQ90_V4HF, AARCH64_SIMD_BUILTIN_FCMLA_LANEQ180_V4HF,
AARCH64_SIMD_BUILTIN_FCMLA_LANEQ270_V4HF.
* config/aarch64/iterators.md (FCMLA_maybe_lane): New.
* config/aarch64/aarch64-c.c (aarch64_update_cpp_builtins): Add __ARM_FEATURE_COMPLEX.
* config/aarch64/aarch64-simd-builtins.def (fcadd90, fcadd270, fcmla0, fcmla90,
fcmla180, fcmla270, fcmla_lane0, fcmla_lane90, fcmla_lane180, fcmla_lane270,
fcmla_laneq0, fcmla_laneq90, fcmla_laneq180, fcmla_laneq270,
fcmlaq_lane0, fcmlaq_lane90, fcmlaq_lane180, fcmlaq_lane270): New.
* config/aarch64/aarch64-simd.md (aarch64_fcmla_lane<rot><mode>,
aarch64_fcmla_laneq<rot>v4hf, aarch64_fcmlaq_lane<rot><mode>,aarch64_fcadd<rot><mode>,
aarch64_fcmla<rot><mode>): New.
* config/aarch64/arm_neon.h:
(vcadd_rot90_f16): New.
(vcaddq_rot90_f16): New.
(vcadd_rot270_f16): New.
(vcaddq_rot270_f16): New.
(vcmla_f16): New.
(vcmlaq_f16): New.
(vcmla_lane_f16): New.
(vcmla_laneq_f16): New.
(vcmlaq_lane_f16): New.
(vcmlaq_rot90_lane_f16): New.
(vcmla_rot90_laneq_f16): New.
(vcmla_rot90_lane_f16): New.
(vcmlaq_rot90_f16): New.
(vcmla_rot90_f16): New.
(vcmlaq_laneq_f16): New.
(vcmla_rot180_laneq_f16): New.
(vcmla_rot180_lane_f16): New.
(vcmlaq_rot180_f16): New.
(vcmla_rot180_f16): New.
(vcmlaq_rot90_laneq_f16): New.
(vcmlaq_rot270_laneq_f16): New.
(vcmlaq_rot270_lane_f16): New.
(vcmla_rot270_laneq_f16): New.
(vcmlaq_rot270_f16): New.
(vcmla_rot270_f16): New.
(vcmlaq_rot180_laneq_f16): New.
(vcmlaq_rot180_lane_f16): New.
(vcmla_rot270_lane_f16): New.
(vcadd_rot90_f32): New.
(vcaddq_rot90_f32): New.
(vcaddq_rot90_f64): New.
(vcadd_rot270_f32): New.
(vcaddq_rot270_f32): New.
(vcaddq_rot270_f64): New.
(vcmla_f32): New.
(vcmlaq_f32): New.
(vcmlaq_f64): New.
(vcmla_lane_f32): New.
(vcmla_laneq_f32): New.
(vcmlaq_lane_f32): New.
(vcmlaq_laneq_f32): New.
(vcmla_rot90_f32): New.
(vcmlaq_rot90_f32): New.
(vcmlaq_rot90_f64): New.
(vcmla_rot90_lane_f32): New.
(vcmla_rot90_laneq_f32): New.
(vcmlaq_rot90_lane_f32): New.
(vcmlaq_rot90_laneq_f32): New.
(vcmla_rot180_f32): New.
(vcmlaq_rot180_f32): New.
(vcmlaq_rot180_f64): New.
(vcmla_rot180_lane_f32): New.
(vcmla_rot180_laneq_f32): New.
(vcmlaq_rot180_lane_f32): New.
(vcmlaq_rot180_laneq_f32): New.
(vcmla_rot270_f32): New.
(vcmlaq_rot270_f32): New.
(vcmlaq_rot270_f64): New.
(vcmla_rot270_lane_f32): New.
(vcmla_rot270_laneq_f32): New.
(vcmlaq_rot270_lane_f32): New.
(vcmlaq_rot270_laneq_f32): New.
* config/aarch64/aarch64.h (TARGET_COMPLEX): New.
* config/aarch64/iterators.md (UNSPEC_FCADD90, UNSPEC_FCADD270,
UNSPEC_FCMLA, UNSPEC_FCMLA90, UNSPEC_FCMLA180, UNSPEC_FCMLA270): New.
(FCADD, FCMLA): New.
(rot): New.
* config/arm/types.md (neon_fcadd, neon_fcmla): New.
gcc/testsuite/ChangeLog:
2019-01-10 Tamar Christina <tamar.christina@arm.com>
* gcc.target/aarch64/advsimd-intrinsics/vector-complex.c: New test.
* gcc.target/aarch64/advsimd-intrinsics/vector-complex_f16.c: New test.
From-SVN: r267795
2019-01-10 04:30:59 +01:00
|
|
|
target = gen_reg_rtx (d->mode);
|
|
|
|
|
|
|
|
rtx pat = NULL_RTX;
|
|
|
|
|
|
|
|
if (d->lane)
|
2019-01-16 19:29:00 +01:00
|
|
|
pat = GEN_FCN (d->icode) (target, op0, op1, op2, lane_idx);
|
aarch64-builtins.c (enum aarch64_type_qualifiers): Add qualifier_lane_pair_index.
gcc/ChangeLog:
2019-01-10 Tamar Christina <tamar.christina@arm.com>
* config/aarch64/aarch64-builtins.c (enum aarch64_type_qualifiers): Add qualifier_lane_pair_index.
(emit-rtl.h): Include.
(TYPES_QUADOP_LANE_PAIR): New.
(aarch64_simd_expand_args): Use it.
(aarch64_simd_expand_builtin): Likewise.
(AARCH64_SIMD_FCMLA_LANEQ_BUILTINS, aarch64_fcmla_laneq_builtin_datum): New.
(FCMLA_LANEQ_BUILTIN, AARCH64_SIMD_FCMLA_LANEQ_BUILTIN_BASE,
AARCH64_SIMD_FCMLA_LANEQ_BUILTINS, aarch64_fcmla_lane_builtin_data,
aarch64_init_fcmla_laneq_builtins, aarch64_expand_fcmla_builtin): New.
(aarch64_init_builtins): Add aarch64_init_fcmla_laneq_builtins.
(aarch64_expand_buildin): Add AARCH64_SIMD_BUILTIN_FCMLA_LANEQ0_V2SF,
AARCH64_SIMD_BUILTIN_FCMLA_LANEQ90_V2SF, AARCH64_SIMD_BUILTIN_FCMLA_LANEQ180_V2SF,
AARCH64_SIMD_BUILTIN_FCMLA_LANEQ2700_V2SF, AARCH64_SIMD_BUILTIN_FCMLA_LANEQ0_V4HF,
AARCH64_SIMD_BUILTIN_FCMLA_LANEQ90_V4HF, AARCH64_SIMD_BUILTIN_FCMLA_LANEQ180_V4HF,
AARCH64_SIMD_BUILTIN_FCMLA_LANEQ270_V4HF.
* config/aarch64/iterators.md (FCMLA_maybe_lane): New.
* config/aarch64/aarch64-c.c (aarch64_update_cpp_builtins): Add __ARM_FEATURE_COMPLEX.
* config/aarch64/aarch64-simd-builtins.def (fcadd90, fcadd270, fcmla0, fcmla90,
fcmla180, fcmla270, fcmla_lane0, fcmla_lane90, fcmla_lane180, fcmla_lane270,
fcmla_laneq0, fcmla_laneq90, fcmla_laneq180, fcmla_laneq270,
fcmlaq_lane0, fcmlaq_lane90, fcmlaq_lane180, fcmlaq_lane270): New.
* config/aarch64/aarch64-simd.md (aarch64_fcmla_lane<rot><mode>,
aarch64_fcmla_laneq<rot>v4hf, aarch64_fcmlaq_lane<rot><mode>,aarch64_fcadd<rot><mode>,
aarch64_fcmla<rot><mode>): New.
* config/aarch64/arm_neon.h:
(vcadd_rot90_f16): New.
(vcaddq_rot90_f16): New.
(vcadd_rot270_f16): New.
(vcaddq_rot270_f16): New.
(vcmla_f16): New.
(vcmlaq_f16): New.
(vcmla_lane_f16): New.
(vcmla_laneq_f16): New.
(vcmlaq_lane_f16): New.
(vcmlaq_rot90_lane_f16): New.
(vcmla_rot90_laneq_f16): New.
(vcmla_rot90_lane_f16): New.
(vcmlaq_rot90_f16): New.
(vcmla_rot90_f16): New.
(vcmlaq_laneq_f16): New.
(vcmla_rot180_laneq_f16): New.
(vcmla_rot180_lane_f16): New.
(vcmlaq_rot180_f16): New.
(vcmla_rot180_f16): New.
(vcmlaq_rot90_laneq_f16): New.
(vcmlaq_rot270_laneq_f16): New.
(vcmlaq_rot270_lane_f16): New.
(vcmla_rot270_laneq_f16): New.
(vcmlaq_rot270_f16): New.
(vcmla_rot270_f16): New.
(vcmlaq_rot180_laneq_f16): New.
(vcmlaq_rot180_lane_f16): New.
(vcmla_rot270_lane_f16): New.
(vcadd_rot90_f32): New.
(vcaddq_rot90_f32): New.
(vcaddq_rot90_f64): New.
(vcadd_rot270_f32): New.
(vcaddq_rot270_f32): New.
(vcaddq_rot270_f64): New.
(vcmla_f32): New.
(vcmlaq_f32): New.
(vcmlaq_f64): New.
(vcmla_lane_f32): New.
(vcmla_laneq_f32): New.
(vcmlaq_lane_f32): New.
(vcmlaq_laneq_f32): New.
(vcmla_rot90_f32): New.
(vcmlaq_rot90_f32): New.
(vcmlaq_rot90_f64): New.
(vcmla_rot90_lane_f32): New.
(vcmla_rot90_laneq_f32): New.
(vcmlaq_rot90_lane_f32): New.
(vcmlaq_rot90_laneq_f32): New.
(vcmla_rot180_f32): New.
(vcmlaq_rot180_f32): New.
(vcmlaq_rot180_f64): New.
(vcmla_rot180_lane_f32): New.
(vcmla_rot180_laneq_f32): New.
(vcmlaq_rot180_lane_f32): New.
(vcmlaq_rot180_laneq_f32): New.
(vcmla_rot270_f32): New.
(vcmlaq_rot270_f32): New.
(vcmlaq_rot270_f64): New.
(vcmla_rot270_lane_f32): New.
(vcmla_rot270_laneq_f32): New.
(vcmlaq_rot270_lane_f32): New.
(vcmlaq_rot270_laneq_f32): New.
* config/aarch64/aarch64.h (TARGET_COMPLEX): New.
* config/aarch64/iterators.md (UNSPEC_FCADD90, UNSPEC_FCADD270,
UNSPEC_FCMLA, UNSPEC_FCMLA90, UNSPEC_FCMLA180, UNSPEC_FCMLA270): New.
(FCADD, FCMLA): New.
(rot): New.
* config/arm/types.md (neon_fcadd, neon_fcmla): New.
gcc/testsuite/ChangeLog:
2019-01-10 Tamar Christina <tamar.christina@arm.com>
* gcc.target/aarch64/advsimd-intrinsics/vector-complex.c: New test.
* gcc.target/aarch64/advsimd-intrinsics/vector-complex_f16.c: New test.
From-SVN: r267795
2019-01-10 04:30:59 +01:00
|
|
|
else
|
|
|
|
pat = GEN_FCN (d->icode) (target, op0, op1, op2);
|
|
|
|
|
|
|
|
if (!pat)
|
|
|
|
return NULL_RTX;
|
|
|
|
|
|
|
|
emit_insn (pat);
|
|
|
|
return target;
|
|
|
|
}
|
|
|
|
|
[GCC, AArch64] Enable Transactional Memory Extension
This patch enables the new Transactional Memory Extension announced recently
as part of Arm's new architecture technologies.
We introduce a new optional extension "tme" to enable this. The following
instructions are part of the extension:
* tstart <Xt>
* ttest <Xt>
* tcommit
* tcancel #<imm>
We have also added ACLE intrinsics for the instructions.
*** gcc/ChangeLog ***
2019-07-31 Sudakshina Das <sudi.das@arm.com>
* config/aarch64/aarch64-builtins.c (enum aarch64_builtins): Add
AARCH64_TME_BUILTIN_TSTART, AARCH64_TME_BUILTIN_TCOMMIT,
AARCH64_TME_BUILTIN_TTEST and AARCH64_TME_BUILTIN_TCANCEL.
(aarch64_init_tme_builtins): New.
(aarch64_init_builtins): Call aarch64_init_tme_builtins.
(aarch64_expand_builtin_tme): New.
(aarch64_expand_builtin): Handle TME builtins.
* config/aarch64/aarch64-c.c (aarch64_update_cpp_builtins): Define
__ARM_FEATURE_TME when enabled.
* config/aarch64/aarch64-option-extensions.def: Add "tme".
* config/aarch64/aarch64.h (AARCH64_FL_TME, AARCH64_ISA_TME): New.
(TARGET_TME): New.
* config/aarch64/aarch64.md (define_c_enum "unspec"): Add UNSPEC_TTEST.
(define_c_enum "unspecv"): Add UNSPECV_TSTART, UNSPECV_TCOMMIT and
UNSPECV_TCANCEL.
(tstart, ttest, tcommit, tcancel): New instructions.
* config/aarch64/arm_acle.h (__tstart, __tcommit): New.
(__tcancel, __ttest): New.
(_TMFAILURE_REASON, _TMFAILURE_RTRY, _TMFAILURE_CNCL): New macro.
(_TMFAILURE_MEM, _TMFAILURE_IMP, _TMFAILURE_ERR): Likewise.
(_TMFAILURE_SIZE, _TMFAILURE_NEST, _TMFAILURE_DBG): Likewise.
(_TMFAILURE_INT, _TMFAILURE_TRIVIAL): Likewise.
* config/arm/types.md: Add new tme type attr.
* doc/invoke.texi: Document "tme".
*** gcc/testsuite/ChangeLog ***
2019-07-31 Sudakshina Das <sudi.das@arm.com>
* gcc.target/aarch64/acle/tme.c: New test.
* gcc.target/aarch64/pragma_cpp_predefs_2.c: New test.
From-SVN: r273926
2019-07-31 11:19:53 +02:00
|
|
|
/* Function to expand an expression EXP which calls one of the Transactional
|
|
|
|
Memory Extension (TME) builtins FCODE with the result going to TARGET. */
|
|
|
|
static rtx
|
|
|
|
aarch64_expand_builtin_tme (int fcode, tree exp, rtx target)
|
|
|
|
{
|
|
|
|
switch (fcode)
|
|
|
|
{
|
|
|
|
case AARCH64_TME_BUILTIN_TSTART:
|
|
|
|
target = gen_reg_rtx (DImode);
|
|
|
|
emit_insn (GEN_FCN (CODE_FOR_tstart) (target));
|
|
|
|
break;
|
|
|
|
|
|
|
|
case AARCH64_TME_BUILTIN_TTEST:
|
|
|
|
target = gen_reg_rtx (DImode);
|
|
|
|
emit_insn (GEN_FCN (CODE_FOR_ttest) (target));
|
|
|
|
break;
|
|
|
|
|
|
|
|
case AARCH64_TME_BUILTIN_TCOMMIT:
|
|
|
|
emit_insn (GEN_FCN (CODE_FOR_tcommit) ());
|
|
|
|
break;
|
|
|
|
|
|
|
|
case AARCH64_TME_BUILTIN_TCANCEL:
|
|
|
|
{
|
|
|
|
tree arg0 = CALL_EXPR_ARG (exp, 0);
|
|
|
|
rtx op0 = expand_normal (arg0);
|
|
|
|
if (CONST_INT_P (op0) && UINTVAL (op0) <= 65536)
|
|
|
|
emit_insn (GEN_FCN (CODE_FOR_tcancel) (op0));
|
|
|
|
else
|
|
|
|
{
|
2021-07-06 21:45:54 +02:00
|
|
|
error_at (EXPR_LOCATION (exp),
|
|
|
|
"argument must be a 16-bit constant immediate");
|
[GCC, AArch64] Enable Transactional Memory Extension
This patch enables the new Transactional Memory Extension announced recently
as part of Arm's new architecture technologies.
We introduce a new optional extension "tme" to enable this. The following
instructions are part of the extension:
* tstart <Xt>
* ttest <Xt>
* tcommit
* tcancel #<imm>
We have also added ACLE intrinsics for the instructions.
*** gcc/ChangeLog ***
2019-07-31 Sudakshina Das <sudi.das@arm.com>
* config/aarch64/aarch64-builtins.c (enum aarch64_builtins): Add
AARCH64_TME_BUILTIN_TSTART, AARCH64_TME_BUILTIN_TCOMMIT,
AARCH64_TME_BUILTIN_TTEST and AARCH64_TME_BUILTIN_TCANCEL.
(aarch64_init_tme_builtins): New.
(aarch64_init_builtins): Call aarch64_init_tme_builtins.
(aarch64_expand_builtin_tme): New.
(aarch64_expand_builtin): Handle TME builtins.
* config/aarch64/aarch64-c.c (aarch64_update_cpp_builtins): Define
__ARM_FEATURE_TME when enabled.
* config/aarch64/aarch64-option-extensions.def: Add "tme".
* config/aarch64/aarch64.h (AARCH64_FL_TME, AARCH64_ISA_TME): New.
(TARGET_TME): New.
* config/aarch64/aarch64.md (define_c_enum "unspec"): Add UNSPEC_TTEST.
(define_c_enum "unspecv"): Add UNSPECV_TSTART, UNSPECV_TCOMMIT and
UNSPECV_TCANCEL.
(tstart, ttest, tcommit, tcancel): New instructions.
* config/aarch64/arm_acle.h (__tstart, __tcommit): New.
(__tcancel, __ttest): New.
(_TMFAILURE_REASON, _TMFAILURE_RTRY, _TMFAILURE_CNCL): New macro.
(_TMFAILURE_MEM, _TMFAILURE_IMP, _TMFAILURE_ERR): Likewise.
(_TMFAILURE_SIZE, _TMFAILURE_NEST, _TMFAILURE_DBG): Likewise.
(_TMFAILURE_INT, _TMFAILURE_TRIVIAL): Likewise.
* config/arm/types.md: Add new tme type attr.
* doc/invoke.texi: Document "tme".
*** gcc/testsuite/ChangeLog ***
2019-07-31 Sudakshina Das <sudi.das@arm.com>
* gcc.target/aarch64/acle/tme.c: New test.
* gcc.target/aarch64/pragma_cpp_predefs_2.c: New test.
From-SVN: r273926
2019-07-31 11:19:53 +02:00
|
|
|
return const0_rtx;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
break;
|
|
|
|
|
|
|
|
default :
|
|
|
|
gcc_unreachable ();
|
|
|
|
}
|
|
|
|
return target;
|
|
|
|
}
|
|
|
|
|
2021-12-14 15:03:38 +01:00
|
|
|
/* Function to expand an expression EXP which calls one of the Load/Store
|
|
|
|
64 Byte extension (LS64) builtins FCODE with the result going to TARGET. */
|
|
|
|
static rtx
|
|
|
|
aarch64_expand_builtin_ls64 (int fcode, tree exp, rtx target)
|
|
|
|
{
|
|
|
|
expand_operand ops[3];
|
|
|
|
|
|
|
|
switch (fcode)
|
|
|
|
{
|
|
|
|
case AARCH64_LS64_BUILTIN_LD64B:
|
|
|
|
{
|
|
|
|
rtx op0 = expand_normal (CALL_EXPR_ARG (exp, 0));
|
|
|
|
create_output_operand (&ops[0], target, V8DImode);
|
|
|
|
create_input_operand (&ops[1], op0, DImode);
|
|
|
|
expand_insn (CODE_FOR_ld64b, 2, ops);
|
|
|
|
return ops[0].value;
|
|
|
|
}
|
|
|
|
case AARCH64_LS64_BUILTIN_ST64B:
|
|
|
|
{
|
|
|
|
rtx op0 = expand_normal (CALL_EXPR_ARG (exp, 0));
|
|
|
|
rtx op1 = expand_normal (CALL_EXPR_ARG (exp, 1));
|
|
|
|
create_output_operand (&ops[0], op0, DImode);
|
|
|
|
create_input_operand (&ops[1], op1, V8DImode);
|
|
|
|
expand_insn (CODE_FOR_st64b, 2, ops);
|
|
|
|
return const0_rtx;
|
|
|
|
}
|
|
|
|
case AARCH64_LS64_BUILTIN_ST64BV:
|
|
|
|
{
|
|
|
|
rtx op0 = expand_normal (CALL_EXPR_ARG (exp, 0));
|
|
|
|
rtx op1 = expand_normal (CALL_EXPR_ARG (exp, 1));
|
|
|
|
create_output_operand (&ops[0], target, DImode);
|
|
|
|
create_input_operand (&ops[1], op0, DImode);
|
|
|
|
create_input_operand (&ops[2], op1, V8DImode);
|
|
|
|
expand_insn (CODE_FOR_st64bv, 3, ops);
|
|
|
|
return ops[0].value;
|
|
|
|
}
|
|
|
|
case AARCH64_LS64_BUILTIN_ST64BV0:
|
|
|
|
{
|
|
|
|
rtx op0 = expand_normal (CALL_EXPR_ARG (exp, 0));
|
|
|
|
rtx op1 = expand_normal (CALL_EXPR_ARG (exp, 1));
|
|
|
|
create_output_operand (&ops[0], target, DImode);
|
|
|
|
create_input_operand (&ops[1], op0, DImode);
|
|
|
|
create_input_operand (&ops[2], op1, V8DImode);
|
|
|
|
expand_insn (CODE_FOR_st64bv0, 3, ops);
|
|
|
|
return ops[0].value;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
gcc_unreachable ();
|
|
|
|
}
|
|
|
|
|
2019-10-21 12:52:05 +02:00
|
|
|
/* Expand a random number builtin EXP with code FCODE, putting the result
|
|
|
|
int TARGET. If IGNORE is true the return value is ignored. */
|
|
|
|
|
|
|
|
rtx
|
|
|
|
aarch64_expand_rng_builtin (tree exp, rtx target, int fcode, int ignore)
|
|
|
|
{
|
|
|
|
rtx pat;
|
|
|
|
enum insn_code icode;
|
|
|
|
if (fcode == AARCH64_BUILTIN_RNG_RNDR)
|
|
|
|
icode = CODE_FOR_aarch64_rndr;
|
|
|
|
else if (fcode == AARCH64_BUILTIN_RNG_RNDRRS)
|
|
|
|
icode = CODE_FOR_aarch64_rndrrs;
|
|
|
|
else
|
|
|
|
gcc_unreachable ();
|
|
|
|
|
|
|
|
rtx rand = gen_reg_rtx (DImode);
|
|
|
|
pat = GEN_FCN (icode) (rand);
|
|
|
|
if (!pat)
|
|
|
|
return NULL_RTX;
|
|
|
|
|
|
|
|
tree arg0 = CALL_EXPR_ARG (exp, 0);
|
|
|
|
rtx res_addr = expand_normal (arg0);
|
|
|
|
res_addr = convert_memory_address (Pmode, res_addr);
|
|
|
|
rtx res_mem = gen_rtx_MEM (DImode, res_addr);
|
|
|
|
emit_insn (pat);
|
|
|
|
emit_move_insn (res_mem, rand);
|
|
|
|
/* If the status result is unused don't generate the CSET code. */
|
|
|
|
if (ignore)
|
|
|
|
return target;
|
|
|
|
|
|
|
|
rtx cc_reg = gen_rtx_REG (CC_Zmode, CC_REGNUM);
|
2021-03-17 19:21:05 +01:00
|
|
|
rtx cmp_rtx = gen_rtx_fmt_ee (EQ, SImode, cc_reg, const0_rtx);
|
2019-10-21 12:52:05 +02:00
|
|
|
emit_insn (gen_aarch64_cstoresi (target, cmp_rtx, cc_reg));
|
|
|
|
return target;
|
|
|
|
}
|
|
|
|
|
[AArch64] Implement Armv8.5-A memory tagging (MTE) intrinsics
2019-11-19 Dennis Zhang <dennis.zhang@arm.com>
* config/aarch64/aarch64-builtins.c (enum aarch64_builtins): Add
AARCH64_MEMTAG_BUILTIN_START, AARCH64_MEMTAG_BUILTIN_IRG,
AARCH64_MEMTAG_BUILTIN_GMI, AARCH64_MEMTAG_BUILTIN_SUBP,
AARCH64_MEMTAG_BUILTIN_INC_TAG, AARCH64_MEMTAG_BUILTIN_SET_TAG,
AARCH64_MEMTAG_BUILTIN_GET_TAG, and AARCH64_MEMTAG_BUILTIN_END.
(aarch64_init_memtag_builtins): New.
(AARCH64_INIT_MEMTAG_BUILTINS_DECL): New macro.
(aarch64_general_init_builtins): Call aarch64_init_memtag_builtins.
(aarch64_expand_builtin_memtag): New.
(aarch64_general_expand_builtin): Call aarch64_expand_builtin_memtag.
(AARCH64_BUILTIN_SUBCODE): New macro.
(aarch64_resolve_overloaded_memtag): New.
(aarch64_resolve_overloaded_builtin_general): New. Call
aarch64_resolve_overloaded_memtag to handle overloaded MTE builtins.
* config/aarch64/aarch64-c.c (aarch64_update_cpp_builtins): Define
__ARM_FEATURE_MEMORY_TAGGING when enabled.
(aarch64_resolve_overloaded_builtin): Call
aarch64_resolve_overloaded_builtin_general.
* config/aarch64/aarch64-protos.h
(aarch64_resolve_overloaded_builtin_general): New declaration.
* config/aarch64/aarch64.h (AARCH64_ISA_MEMTAG): New macro.
(TARGET_MEMTAG): Likewise.
* config/aarch64/aarch64.md (UNSPEC_GEN_TAG): New unspec.
(UNSPEC_GEN_TAG_RND, and UNSPEC_TAG_SPACE): Likewise.
(irg, gmi, subp, addg, ldg, stg): New instructions.
* config/aarch64/arm_acle.h (__arm_mte_create_random_tag): New macro.
(__arm_mte_exclude_tag, __arm_mte_ptrdiff): Likewise.
(__arm_mte_increment_tag, __arm_mte_set_tag): Likewise.
(__arm_mte_get_tag): Likewise.
* config/aarch64/predicates.md (aarch64_memtag_tag_offset): New.
(aarch64_granule16_uimm6, aarch64_granule16_simm9): New.
* config/arm/types.md (memtag): New.
* doc/invoke.texi (-memtag): Update description.
2019-11-19 Dennis Zhang <dennis.zhang@arm.com>
* gcc.target/aarch64/acle/memtag_1.c: New test.
* gcc.target/aarch64/acle/memtag_2.c: New test.
* gcc.target/aarch64/acle/memtag_3.c: New test.
From-SVN: r278444
2019-11-19 14:43:39 +01:00
|
|
|
/* Expand an expression EXP that calls a MEMTAG built-in FCODE
|
|
|
|
with result going to TARGET. */
|
|
|
|
static rtx
|
|
|
|
aarch64_expand_builtin_memtag (int fcode, tree exp, rtx target)
|
|
|
|
{
|
|
|
|
if (TARGET_ILP32)
|
|
|
|
{
|
|
|
|
error ("Memory Tagging Extension does not support %<-mabi=ilp32%>");
|
|
|
|
return const0_rtx;
|
|
|
|
}
|
|
|
|
|
|
|
|
rtx pat = NULL;
|
|
|
|
enum insn_code icode = aarch64_memtag_builtin_data[fcode -
|
|
|
|
AARCH64_MEMTAG_BUILTIN_START - 1].icode;
|
|
|
|
|
|
|
|
rtx op0 = expand_normal (CALL_EXPR_ARG (exp, 0));
|
|
|
|
machine_mode mode0 = GET_MODE (op0);
|
|
|
|
op0 = force_reg (mode0 == VOIDmode ? DImode : mode0, op0);
|
|
|
|
op0 = convert_to_mode (DImode, op0, true);
|
|
|
|
|
|
|
|
switch (fcode)
|
|
|
|
{
|
|
|
|
case AARCH64_MEMTAG_BUILTIN_IRG:
|
|
|
|
case AARCH64_MEMTAG_BUILTIN_GMI:
|
|
|
|
case AARCH64_MEMTAG_BUILTIN_SUBP:
|
|
|
|
case AARCH64_MEMTAG_BUILTIN_INC_TAG:
|
|
|
|
{
|
|
|
|
if (! target
|
|
|
|
|| GET_MODE (target) != DImode
|
|
|
|
|| ! (*insn_data[icode].operand[0].predicate) (target, DImode))
|
|
|
|
target = gen_reg_rtx (DImode);
|
|
|
|
|
|
|
|
if (fcode == AARCH64_MEMTAG_BUILTIN_INC_TAG)
|
|
|
|
{
|
|
|
|
rtx op1 = expand_normal (CALL_EXPR_ARG (exp, 1));
|
|
|
|
|
|
|
|
if ((*insn_data[icode].operand[3].predicate) (op1, QImode))
|
|
|
|
{
|
|
|
|
pat = GEN_FCN (icode) (target, op0, const0_rtx, op1);
|
|
|
|
break;
|
|
|
|
}
|
2021-07-06 21:45:54 +02:00
|
|
|
error_at (EXPR_LOCATION (exp),
|
|
|
|
"argument %d must be a constant immediate "
|
|
|
|
"in range [0,15]", 2);
|
[AArch64] Implement Armv8.5-A memory tagging (MTE) intrinsics
2019-11-19 Dennis Zhang <dennis.zhang@arm.com>
* config/aarch64/aarch64-builtins.c (enum aarch64_builtins): Add
AARCH64_MEMTAG_BUILTIN_START, AARCH64_MEMTAG_BUILTIN_IRG,
AARCH64_MEMTAG_BUILTIN_GMI, AARCH64_MEMTAG_BUILTIN_SUBP,
AARCH64_MEMTAG_BUILTIN_INC_TAG, AARCH64_MEMTAG_BUILTIN_SET_TAG,
AARCH64_MEMTAG_BUILTIN_GET_TAG, and AARCH64_MEMTAG_BUILTIN_END.
(aarch64_init_memtag_builtins): New.
(AARCH64_INIT_MEMTAG_BUILTINS_DECL): New macro.
(aarch64_general_init_builtins): Call aarch64_init_memtag_builtins.
(aarch64_expand_builtin_memtag): New.
(aarch64_general_expand_builtin): Call aarch64_expand_builtin_memtag.
(AARCH64_BUILTIN_SUBCODE): New macro.
(aarch64_resolve_overloaded_memtag): New.
(aarch64_resolve_overloaded_builtin_general): New. Call
aarch64_resolve_overloaded_memtag to handle overloaded MTE builtins.
* config/aarch64/aarch64-c.c (aarch64_update_cpp_builtins): Define
__ARM_FEATURE_MEMORY_TAGGING when enabled.
(aarch64_resolve_overloaded_builtin): Call
aarch64_resolve_overloaded_builtin_general.
* config/aarch64/aarch64-protos.h
(aarch64_resolve_overloaded_builtin_general): New declaration.
* config/aarch64/aarch64.h (AARCH64_ISA_MEMTAG): New macro.
(TARGET_MEMTAG): Likewise.
* config/aarch64/aarch64.md (UNSPEC_GEN_TAG): New unspec.
(UNSPEC_GEN_TAG_RND, and UNSPEC_TAG_SPACE): Likewise.
(irg, gmi, subp, addg, ldg, stg): New instructions.
* config/aarch64/arm_acle.h (__arm_mte_create_random_tag): New macro.
(__arm_mte_exclude_tag, __arm_mte_ptrdiff): Likewise.
(__arm_mte_increment_tag, __arm_mte_set_tag): Likewise.
(__arm_mte_get_tag): Likewise.
* config/aarch64/predicates.md (aarch64_memtag_tag_offset): New.
(aarch64_granule16_uimm6, aarch64_granule16_simm9): New.
* config/arm/types.md (memtag): New.
* doc/invoke.texi (-memtag): Update description.
2019-11-19 Dennis Zhang <dennis.zhang@arm.com>
* gcc.target/aarch64/acle/memtag_1.c: New test.
* gcc.target/aarch64/acle/memtag_2.c: New test.
* gcc.target/aarch64/acle/memtag_3.c: New test.
From-SVN: r278444
2019-11-19 14:43:39 +01:00
|
|
|
return const0_rtx;
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
rtx op1 = expand_normal (CALL_EXPR_ARG (exp, 1));
|
|
|
|
machine_mode mode1 = GET_MODE (op1);
|
|
|
|
op1 = force_reg (mode1 == VOIDmode ? DImode : mode1, op1);
|
|
|
|
op1 = convert_to_mode (DImode, op1, true);
|
|
|
|
pat = GEN_FCN (icode) (target, op0, op1);
|
|
|
|
}
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
case AARCH64_MEMTAG_BUILTIN_GET_TAG:
|
|
|
|
target = op0;
|
|
|
|
pat = GEN_FCN (icode) (target, op0, const0_rtx);
|
|
|
|
break;
|
|
|
|
case AARCH64_MEMTAG_BUILTIN_SET_TAG:
|
|
|
|
pat = GEN_FCN (icode) (op0, op0, const0_rtx);
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
gcc_unreachable();
|
|
|
|
}
|
|
|
|
|
|
|
|
if (!pat)
|
|
|
|
return NULL_RTX;
|
|
|
|
|
|
|
|
emit_insn (pat);
|
|
|
|
return target;
|
|
|
|
}
|
|
|
|
|
2020-09-14 15:47:24 +02:00
|
|
|
/* Expand an expression EXP as fpsr or fpcr setter (depending on
|
2020-05-28 09:49:42 +02:00
|
|
|
UNSPEC) using MODE. */
|
|
|
|
static void
|
|
|
|
aarch64_expand_fpsr_fpcr_setter (int unspec, machine_mode mode, tree exp)
|
|
|
|
{
|
|
|
|
tree arg = CALL_EXPR_ARG (exp, 0);
|
|
|
|
rtx op = force_reg (mode, expand_normal (arg));
|
|
|
|
emit_insn (gen_aarch64_set (unspec, mode, op));
|
|
|
|
}
|
|
|
|
|
2020-09-14 15:47:24 +02:00
|
|
|
/* Expand a fpsr or fpcr getter (depending on UNSPEC) using MODE.
|
|
|
|
Return the target. */
|
|
|
|
static rtx
|
|
|
|
aarch64_expand_fpsr_fpcr_getter (enum insn_code icode, machine_mode mode,
|
|
|
|
rtx target)
|
|
|
|
{
|
|
|
|
expand_operand op;
|
|
|
|
create_output_operand (&op, target, mode);
|
|
|
|
expand_insn (icode, 1, &op);
|
|
|
|
return op.value;
|
|
|
|
}
|
|
|
|
|
[AArch64] Split built-in function codes into major and minor codes
It was easier to add the SVE ACLE support without enumerating every
function at build time. This in turn meant that it was easier if the
SVE builtins occupied a distinct numberspace from the existing AArch64
ones, which *are* enumerated at build time. This patch therefore
divides the built-in functions codes into "major" and "minor" codes.
At present the major code is just "general", but the SVE patch will add
"SVE" as well.
Also, it was convenient to put the SVE ACLE support in its own file,
so the patch makes aarch64.c provide the frontline target hooks directly,
forwarding to the other files for the real work.
The reason for organising the files this way is that aarch64.c needs
to define the target hook macros whatever happens, and having aarch64.c
macros forward to aarch64-builtins.c functions and aarch64-bulitins.c
functions forward to the SVE file seemed a bit indirect. Doing things
the way the patch does them puts aarch64-builtins.c and the SVE code on
more of an equal footing.
The aarch64_(general_)gimple_fold_builtin change is mostly just
reindentation.
2019-09-27 Richard Sandiford <richard.sandiford@arm.com>
gcc/
* config/aarch64/aarch64-protos.h (aarch64_builtin_class): New enum.
(AARCH64_BUILTIN_SHIFT, AARCH64_BUILTIN_CLASS): New constants.
(aarch64_gimple_fold_builtin, aarch64_mangle_builtin_type)
(aarch64_fold_builtin, aarch64_init_builtins, aarch64_expand_builtin):
(aarch64_builtin_decl, aarch64_builtin_rsqrt): Delete.
(aarch64_general_mangle_builtin_type, aarch64_general_init_builtins):
(aarch64_general_fold_builtin, aarch64_general_gimple_fold_builtin):
(aarch64_general_expand_builtin, aarch64_general_builtin_decl):
(aarch64_general_builtin_rsqrt): Declare.
* config/aarch64/aarch64-builtins.c (aarch64_general_add_builtin):
New function.
(aarch64_mangle_builtin_type): Rename to...
(aarch64_general_mangle_builtin_type): ...this.
(aarch64_init_fcmla_laneq_builtins, aarch64_init_simd_builtins)
(aarch64_init_crc32_builtins, aarch64_init_builtin_rsqrt)
(aarch64_init_pauth_hint_builtins, aarch64_init_tme_builtins): Use
aarch64_general_add_builtin instead of add_builtin_function.
(aarch64_init_builtins): Rename to...
(aarch64_general_init_builtins): ...this. Use
aarch64_general_add_builtin instead of add_builtin_function.
(aarch64_builtin_decl): Rename to...
(aarch64_general_builtin_decl): ...this and remove the unused
arguments.
(aarch64_expand_builtin): Rename to...
(aarch64_general_expand_builtin): ...this and remove the unused
arguments.
(aarch64_builtin_rsqrt): Rename to...
(aarch64_general_builtin_rsqrt): ...this.
(aarch64_fold_builtin): Rename to...
(aarch64_general_fold_builtin): ...this. Take the function subcode
and return type as arguments. Remove the "ignored" argument.
(aarch64_gimple_fold_builtin): Rename to...
(aarch64_general_gimple_fold_builtin): ...this. Take the function
subcode and gcall as arguments, and return the new function call.
* config/aarch64/aarch64.c (aarch64_init_builtins)
(aarch64_fold_builtin, aarch64_gimple_fold_builtin)
(aarch64_expand_builtin, aarch64_builtin_decl): New functions.
(aarch64_builtin_reciprocal): Call aarch64_general_builtin_rsqrt
instead of aarch64_builtin_rsqrt.
(aarch64_mangle_type): Call aarch64_general_mangle_builtin_type
instead of aarch64_mangle_builtin_type.
From-SVN: r276177
2019-09-27 10:47:21 +02:00
|
|
|
/* Expand an expression EXP that calls built-in function FCODE,
|
2019-10-21 12:52:05 +02:00
|
|
|
with result going to TARGET if that's convenient. IGNORE is true
|
|
|
|
if the result of the builtin is ignored. */
|
2012-11-20 13:10:37 +01:00
|
|
|
rtx
|
2019-10-21 12:52:05 +02:00
|
|
|
aarch64_general_expand_builtin (unsigned int fcode, tree exp, rtx target,
|
|
|
|
int ignore)
|
2012-11-20 13:10:37 +01:00
|
|
|
{
|
2014-05-23 00:05:08 +02:00
|
|
|
int icode;
|
2020-05-28 09:49:42 +02:00
|
|
|
rtx op0;
|
2014-05-23 00:05:08 +02:00
|
|
|
tree arg0;
|
|
|
|
|
|
|
|
switch (fcode)
|
|
|
|
{
|
|
|
|
case AARCH64_BUILTIN_GET_FPCR:
|
2020-09-14 15:47:24 +02:00
|
|
|
return aarch64_expand_fpsr_fpcr_getter (CODE_FOR_aarch64_get_fpcrsi,
|
|
|
|
SImode, target);
|
2014-05-23 00:05:08 +02:00
|
|
|
case AARCH64_BUILTIN_SET_FPCR:
|
2020-05-28 09:49:42 +02:00
|
|
|
aarch64_expand_fpsr_fpcr_setter (UNSPECV_SET_FPCR, SImode, exp);
|
|
|
|
return target;
|
2014-05-23 00:05:08 +02:00
|
|
|
case AARCH64_BUILTIN_GET_FPSR:
|
2020-09-14 15:47:24 +02:00
|
|
|
return aarch64_expand_fpsr_fpcr_getter (CODE_FOR_aarch64_get_fpsrsi,
|
|
|
|
SImode, target);
|
2014-05-23 00:05:08 +02:00
|
|
|
case AARCH64_BUILTIN_SET_FPSR:
|
2020-05-28 09:49:42 +02:00
|
|
|
aarch64_expand_fpsr_fpcr_setter (UNSPECV_SET_FPSR, SImode, exp);
|
|
|
|
return target;
|
|
|
|
case AARCH64_BUILTIN_GET_FPCR64:
|
2020-09-14 15:47:24 +02:00
|
|
|
return aarch64_expand_fpsr_fpcr_getter (CODE_FOR_aarch64_get_fpcrdi,
|
|
|
|
DImode, target);
|
2020-05-28 09:49:42 +02:00
|
|
|
case AARCH64_BUILTIN_SET_FPCR64:
|
|
|
|
aarch64_expand_fpsr_fpcr_setter (UNSPECV_SET_FPCR, DImode, exp);
|
|
|
|
return target;
|
|
|
|
case AARCH64_BUILTIN_GET_FPSR64:
|
2020-09-14 15:47:24 +02:00
|
|
|
return aarch64_expand_fpsr_fpcr_getter (CODE_FOR_aarch64_get_fpsrdi,
|
|
|
|
DImode, target);
|
2020-05-28 09:49:42 +02:00
|
|
|
case AARCH64_BUILTIN_SET_FPSR64:
|
|
|
|
aarch64_expand_fpsr_fpcr_setter (UNSPECV_SET_FPSR, DImode, exp);
|
2014-05-23 00:05:08 +02:00
|
|
|
return target;
|
2017-01-20 01:10:11 +01:00
|
|
|
case AARCH64_PAUTH_BUILTIN_AUTIA1716:
|
|
|
|
case AARCH64_PAUTH_BUILTIN_PACIA1716:
|
[PATCH 3/3][GCC][AARCH64] Add support for pointer authentication B key
gcc/
2019-05-29 Sam Tebbs <sam.tebbs@arm.com>
* config/aarch64/aarch64-builtins.c (aarch64_builtins): Add
AARCH64_PAUTH_BUILTIN_AUTIB1716 and AARCH64_PAUTH_BUILTIN_PACIB1716.
* config/aarch64/aarch64-builtins.c (aarch64_init_pauth_hint_builtins):
Add autib1716 and pacib1716 initialisation.
* config/aarch64/aarch64-builtins.c (aarch64_expand_builtin): Add checks
for autib1716 and pacib1716.
* config/aarch64/aarch64-protos.h (aarch64_key_type,
aarch64_post_cfi_startproc): Define.
* config/aarch64/aarch64-protos.h (aarch64_ra_sign_key): Define extern.
* config/aarch64/aarch64.c (aarch64_handle_standard_branch_protection,
aarch64_handle_pac_ret_protection): Set default sign key to A.
* config/aarch64/aarch64.c (aarch64_expand_epilogue,
aarch64_expand_prologue): Add check for b-key.
* config/aarch64/aarch64.c (aarch64_ra_sign_key,
aarch64_post_cfi_startproc, aarch64_handle_pac_ret_b_key): Define.
* config/aarch64/aarch64.h (TARGET_ASM_POST_CFI_STARTPROC): Define.
* config/aarch64/aarch64.c (aarch64_pac_ret_subtypes): Add "b-key".
* config/aarch64/aarch64.md (unspec): Add UNSPEC_AUTIA1716,
UNSPEC_AUTIB1716, UNSPEC_AUTIASP, UNSPEC_AUTIBSP, UNSPEC_PACIA1716,
UNSPEC_PACIB1716, UNSPEC_PACIASP, UNSPEC_PACIBSP.
* config/aarch64/aarch64.md (do_return): Add check for b-key.
* config/aarch64/aarch64.md (<pauth_mnem_prefix>sp): Replace
pauth_hint_num_a with pauth_hint_num.
* config/aarch64/aarch64.md (<pauth_mnem_prefix>1716): Replace
pauth_hint_num_a with pauth_hint_num.
* config/aarch64/aarch64.opt (msign-return-address=): Deprecate.
* config/aarch64/iterators.md (PAUTH_LR_SP): Add UNSPEC_AUTIASP,
UNSPEC_AUTIBSP, UNSPEC_PACIASP, UNSPEC_PACIBSP.
* config/aarch64/iterators.md (PAUTH_17_16): Add UNSPEC_AUTIA1716,
UNSPEC_AUTIB1716, UNSPEC_PACIA1716, UNSPEC_PACIB1716.
* config/aarch64/iterators.md (pauth_mnem_prefix): Add UNSPEC_AUTIA1716,
UNSPEC_AUTIB1716, UNSPEC_PACIA1716, UNSPEC_PACIB1716, UNSPEC_AUTIASP,
UNSPEC_AUTIBSP, UNSPEC_PACIASP, UNSPEC_PACIBSP.
* config/aarch64/iterators.md (pauth_hint_num_a): Replace
UNSPEC_PACI1716 and UNSPEC_AUTI1716 with UNSPEC_PACIA1716 and
UNSPEC_AUTIA1716 respectively.
* config/aarch64/iterators.md (pauth_hint_num_a): Rename to pauth_hint_num
and add UNSPEC_PACIBSP, UNSPEC_AUTIBSP, UNSPEC_PACIB1716, UNSPEC_AUTIB1716.
* doc/invoke.texi (-mbranch-protection): Add b-key type.
* config/aarch64/aarch64-bti-insert.c (aarch64_pac_insn_p): Rename
UNSPEC_PACISP to UNSPEC_PACIASP and UNSPEC_PACIBSP.
gcc/testsuite
2019-05-29 Sam Tebbs <sam.tebbs@arm.com>
* gcc.target/aarch64/return_address_sign_b_1.c: New file.
* gcc.target/aarch64/return_address_sign_b_2.c: New file.
* gcc.target/aarch64/return_address_sign_b_3.c: New file.
* gcc.target/aarch64/return_address_sign_b_exception.c: New file.
* gcc.target/aarch64/return_address_sign_ab_exception.c: New file.
* gcc.target/aarch64/return_address_sign_builtin.c: New file
libgcc/
2019-05-29 Sam Tebbs <sam.tebbs@arm.com>
* config/aarch64/aarch64-unwind.h (aarch64_cie_signed_with_b_key): New
function.
* config/aarch64/aarch64-unwind.h (aarch64_post_extract_frame_addr,
aarch64_post_frob_eh_handler_addr): Add check for b-key.
* config/aarch64/aarch64-unwind-h (aarch64_post_extract_frame_addr,
aarch64_post_frob_eh_handler_addr, aarch64_post_frob_update_context):
Rename RA_A_SIGNED_BIT to RA_SIGNED_BIT.
* unwind-dw2-fde.c (get_cie_encoding): Add check for 'B' in augmentation
string.
* unwind-dw2.c (extract_cie_info): Add check for 'B' in augmentation
string.
(RA_A_SIGNED_BIT): Rename to RA_SIGNED_BIT.
From-SVN: r271735
2019-05-29 11:22:17 +02:00
|
|
|
case AARCH64_PAUTH_BUILTIN_AUTIB1716:
|
|
|
|
case AARCH64_PAUTH_BUILTIN_PACIB1716:
|
2017-01-20 01:10:11 +01:00
|
|
|
case AARCH64_PAUTH_BUILTIN_XPACLRI:
|
|
|
|
arg0 = CALL_EXPR_ARG (exp, 0);
|
|
|
|
op0 = force_reg (Pmode, expand_normal (arg0));
|
|
|
|
|
|
|
|
if (fcode == AARCH64_PAUTH_BUILTIN_XPACLRI)
|
|
|
|
{
|
|
|
|
rtx lr = gen_rtx_REG (Pmode, R30_REGNUM);
|
|
|
|
icode = CODE_FOR_xpaclri;
|
|
|
|
emit_move_insn (lr, op0);
|
|
|
|
emit_insn (GEN_FCN (icode) ());
|
2020-09-21 14:52:45 +02:00
|
|
|
return lr;
|
2017-01-20 01:10:11 +01:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
tree arg1 = CALL_EXPR_ARG (exp, 1);
|
|
|
|
rtx op1 = force_reg (Pmode, expand_normal (arg1));
|
[PATCH 3/3][GCC][AARCH64] Add support for pointer authentication B key
gcc/
2019-05-29 Sam Tebbs <sam.tebbs@arm.com>
* config/aarch64/aarch64-builtins.c (aarch64_builtins): Add
AARCH64_PAUTH_BUILTIN_AUTIB1716 and AARCH64_PAUTH_BUILTIN_PACIB1716.
* config/aarch64/aarch64-builtins.c (aarch64_init_pauth_hint_builtins):
Add autib1716 and pacib1716 initialisation.
* config/aarch64/aarch64-builtins.c (aarch64_expand_builtin): Add checks
for autib1716 and pacib1716.
* config/aarch64/aarch64-protos.h (aarch64_key_type,
aarch64_post_cfi_startproc): Define.
* config/aarch64/aarch64-protos.h (aarch64_ra_sign_key): Define extern.
* config/aarch64/aarch64.c (aarch64_handle_standard_branch_protection,
aarch64_handle_pac_ret_protection): Set default sign key to A.
* config/aarch64/aarch64.c (aarch64_expand_epilogue,
aarch64_expand_prologue): Add check for b-key.
* config/aarch64/aarch64.c (aarch64_ra_sign_key,
aarch64_post_cfi_startproc, aarch64_handle_pac_ret_b_key): Define.
* config/aarch64/aarch64.h (TARGET_ASM_POST_CFI_STARTPROC): Define.
* config/aarch64/aarch64.c (aarch64_pac_ret_subtypes): Add "b-key".
* config/aarch64/aarch64.md (unspec): Add UNSPEC_AUTIA1716,
UNSPEC_AUTIB1716, UNSPEC_AUTIASP, UNSPEC_AUTIBSP, UNSPEC_PACIA1716,
UNSPEC_PACIB1716, UNSPEC_PACIASP, UNSPEC_PACIBSP.
* config/aarch64/aarch64.md (do_return): Add check for b-key.
* config/aarch64/aarch64.md (<pauth_mnem_prefix>sp): Replace
pauth_hint_num_a with pauth_hint_num.
* config/aarch64/aarch64.md (<pauth_mnem_prefix>1716): Replace
pauth_hint_num_a with pauth_hint_num.
* config/aarch64/aarch64.opt (msign-return-address=): Deprecate.
* config/aarch64/iterators.md (PAUTH_LR_SP): Add UNSPEC_AUTIASP,
UNSPEC_AUTIBSP, UNSPEC_PACIASP, UNSPEC_PACIBSP.
* config/aarch64/iterators.md (PAUTH_17_16): Add UNSPEC_AUTIA1716,
UNSPEC_AUTIB1716, UNSPEC_PACIA1716, UNSPEC_PACIB1716.
* config/aarch64/iterators.md (pauth_mnem_prefix): Add UNSPEC_AUTIA1716,
UNSPEC_AUTIB1716, UNSPEC_PACIA1716, UNSPEC_PACIB1716, UNSPEC_AUTIASP,
UNSPEC_AUTIBSP, UNSPEC_PACIASP, UNSPEC_PACIBSP.
* config/aarch64/iterators.md (pauth_hint_num_a): Replace
UNSPEC_PACI1716 and UNSPEC_AUTI1716 with UNSPEC_PACIA1716 and
UNSPEC_AUTIA1716 respectively.
* config/aarch64/iterators.md (pauth_hint_num_a): Rename to pauth_hint_num
and add UNSPEC_PACIBSP, UNSPEC_AUTIBSP, UNSPEC_PACIB1716, UNSPEC_AUTIB1716.
* doc/invoke.texi (-mbranch-protection): Add b-key type.
* config/aarch64/aarch64-bti-insert.c (aarch64_pac_insn_p): Rename
UNSPEC_PACISP to UNSPEC_PACIASP and UNSPEC_PACIBSP.
gcc/testsuite
2019-05-29 Sam Tebbs <sam.tebbs@arm.com>
* gcc.target/aarch64/return_address_sign_b_1.c: New file.
* gcc.target/aarch64/return_address_sign_b_2.c: New file.
* gcc.target/aarch64/return_address_sign_b_3.c: New file.
* gcc.target/aarch64/return_address_sign_b_exception.c: New file.
* gcc.target/aarch64/return_address_sign_ab_exception.c: New file.
* gcc.target/aarch64/return_address_sign_builtin.c: New file
libgcc/
2019-05-29 Sam Tebbs <sam.tebbs@arm.com>
* config/aarch64/aarch64-unwind.h (aarch64_cie_signed_with_b_key): New
function.
* config/aarch64/aarch64-unwind.h (aarch64_post_extract_frame_addr,
aarch64_post_frob_eh_handler_addr): Add check for b-key.
* config/aarch64/aarch64-unwind-h (aarch64_post_extract_frame_addr,
aarch64_post_frob_eh_handler_addr, aarch64_post_frob_update_context):
Rename RA_A_SIGNED_BIT to RA_SIGNED_BIT.
* unwind-dw2-fde.c (get_cie_encoding): Add check for 'B' in augmentation
string.
* unwind-dw2.c (extract_cie_info): Add check for 'B' in augmentation
string.
(RA_A_SIGNED_BIT): Rename to RA_SIGNED_BIT.
From-SVN: r271735
2019-05-29 11:22:17 +02:00
|
|
|
switch (fcode)
|
|
|
|
{
|
|
|
|
case AARCH64_PAUTH_BUILTIN_AUTIA1716:
|
|
|
|
icode = CODE_FOR_autia1716;
|
|
|
|
break;
|
|
|
|
case AARCH64_PAUTH_BUILTIN_AUTIB1716:
|
|
|
|
icode = CODE_FOR_autib1716;
|
|
|
|
break;
|
|
|
|
case AARCH64_PAUTH_BUILTIN_PACIA1716:
|
|
|
|
icode = CODE_FOR_pacia1716;
|
|
|
|
break;
|
|
|
|
case AARCH64_PAUTH_BUILTIN_PACIB1716:
|
|
|
|
icode = CODE_FOR_pacib1716;
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
icode = 0;
|
|
|
|
gcc_unreachable ();
|
|
|
|
}
|
2017-01-20 01:10:11 +01:00
|
|
|
|
|
|
|
rtx x16_reg = gen_rtx_REG (Pmode, R16_REGNUM);
|
|
|
|
rtx x17_reg = gen_rtx_REG (Pmode, R17_REGNUM);
|
|
|
|
emit_move_insn (x17_reg, op0);
|
|
|
|
emit_move_insn (x16_reg, op1);
|
|
|
|
emit_insn (GEN_FCN (icode) ());
|
2020-09-21 14:52:45 +02:00
|
|
|
return x17_reg;
|
2017-01-20 01:10:11 +01:00
|
|
|
}
|
|
|
|
|
2019-09-03 10:40:30 +02:00
|
|
|
case AARCH64_JSCVT:
|
2020-09-17 18:17:52 +02:00
|
|
|
{
|
|
|
|
expand_operand ops[2];
|
|
|
|
create_output_operand (&ops[0], target, SImode);
|
|
|
|
op0 = expand_normal (CALL_EXPR_ARG (exp, 0));
|
|
|
|
create_input_operand (&ops[1], op0, DFmode);
|
|
|
|
expand_insn (CODE_FOR_aarch64_fjcvtzs, 2, ops);
|
|
|
|
return ops[0].value;
|
|
|
|
}
|
2019-09-03 10:40:30 +02:00
|
|
|
|
aarch64-builtins.c (enum aarch64_type_qualifiers): Add qualifier_lane_pair_index.
gcc/ChangeLog:
2019-01-10 Tamar Christina <tamar.christina@arm.com>
* config/aarch64/aarch64-builtins.c (enum aarch64_type_qualifiers): Add qualifier_lane_pair_index.
(emit-rtl.h): Include.
(TYPES_QUADOP_LANE_PAIR): New.
(aarch64_simd_expand_args): Use it.
(aarch64_simd_expand_builtin): Likewise.
(AARCH64_SIMD_FCMLA_LANEQ_BUILTINS, aarch64_fcmla_laneq_builtin_datum): New.
(FCMLA_LANEQ_BUILTIN, AARCH64_SIMD_FCMLA_LANEQ_BUILTIN_BASE,
AARCH64_SIMD_FCMLA_LANEQ_BUILTINS, aarch64_fcmla_lane_builtin_data,
aarch64_init_fcmla_laneq_builtins, aarch64_expand_fcmla_builtin): New.
(aarch64_init_builtins): Add aarch64_init_fcmla_laneq_builtins.
(aarch64_expand_buildin): Add AARCH64_SIMD_BUILTIN_FCMLA_LANEQ0_V2SF,
AARCH64_SIMD_BUILTIN_FCMLA_LANEQ90_V2SF, AARCH64_SIMD_BUILTIN_FCMLA_LANEQ180_V2SF,
AARCH64_SIMD_BUILTIN_FCMLA_LANEQ2700_V2SF, AARCH64_SIMD_BUILTIN_FCMLA_LANEQ0_V4HF,
AARCH64_SIMD_BUILTIN_FCMLA_LANEQ90_V4HF, AARCH64_SIMD_BUILTIN_FCMLA_LANEQ180_V4HF,
AARCH64_SIMD_BUILTIN_FCMLA_LANEQ270_V4HF.
* config/aarch64/iterators.md (FCMLA_maybe_lane): New.
* config/aarch64/aarch64-c.c (aarch64_update_cpp_builtins): Add __ARM_FEATURE_COMPLEX.
* config/aarch64/aarch64-simd-builtins.def (fcadd90, fcadd270, fcmla0, fcmla90,
fcmla180, fcmla270, fcmla_lane0, fcmla_lane90, fcmla_lane180, fcmla_lane270,
fcmla_laneq0, fcmla_laneq90, fcmla_laneq180, fcmla_laneq270,
fcmlaq_lane0, fcmlaq_lane90, fcmlaq_lane180, fcmlaq_lane270): New.
* config/aarch64/aarch64-simd.md (aarch64_fcmla_lane<rot><mode>,
aarch64_fcmla_laneq<rot>v4hf, aarch64_fcmlaq_lane<rot><mode>,aarch64_fcadd<rot><mode>,
aarch64_fcmla<rot><mode>): New.
* config/aarch64/arm_neon.h:
(vcadd_rot90_f16): New.
(vcaddq_rot90_f16): New.
(vcadd_rot270_f16): New.
(vcaddq_rot270_f16): New.
(vcmla_f16): New.
(vcmlaq_f16): New.
(vcmla_lane_f16): New.
(vcmla_laneq_f16): New.
(vcmlaq_lane_f16): New.
(vcmlaq_rot90_lane_f16): New.
(vcmla_rot90_laneq_f16): New.
(vcmla_rot90_lane_f16): New.
(vcmlaq_rot90_f16): New.
(vcmla_rot90_f16): New.
(vcmlaq_laneq_f16): New.
(vcmla_rot180_laneq_f16): New.
(vcmla_rot180_lane_f16): New.
(vcmlaq_rot180_f16): New.
(vcmla_rot180_f16): New.
(vcmlaq_rot90_laneq_f16): New.
(vcmlaq_rot270_laneq_f16): New.
(vcmlaq_rot270_lane_f16): New.
(vcmla_rot270_laneq_f16): New.
(vcmlaq_rot270_f16): New.
(vcmla_rot270_f16): New.
(vcmlaq_rot180_laneq_f16): New.
(vcmlaq_rot180_lane_f16): New.
(vcmla_rot270_lane_f16): New.
(vcadd_rot90_f32): New.
(vcaddq_rot90_f32): New.
(vcaddq_rot90_f64): New.
(vcadd_rot270_f32): New.
(vcaddq_rot270_f32): New.
(vcaddq_rot270_f64): New.
(vcmla_f32): New.
(vcmlaq_f32): New.
(vcmlaq_f64): New.
(vcmla_lane_f32): New.
(vcmla_laneq_f32): New.
(vcmlaq_lane_f32): New.
(vcmlaq_laneq_f32): New.
(vcmla_rot90_f32): New.
(vcmlaq_rot90_f32): New.
(vcmlaq_rot90_f64): New.
(vcmla_rot90_lane_f32): New.
(vcmla_rot90_laneq_f32): New.
(vcmlaq_rot90_lane_f32): New.
(vcmlaq_rot90_laneq_f32): New.
(vcmla_rot180_f32): New.
(vcmlaq_rot180_f32): New.
(vcmlaq_rot180_f64): New.
(vcmla_rot180_lane_f32): New.
(vcmla_rot180_laneq_f32): New.
(vcmlaq_rot180_lane_f32): New.
(vcmlaq_rot180_laneq_f32): New.
(vcmla_rot270_f32): New.
(vcmlaq_rot270_f32): New.
(vcmlaq_rot270_f64): New.
(vcmla_rot270_lane_f32): New.
(vcmla_rot270_laneq_f32): New.
(vcmlaq_rot270_lane_f32): New.
(vcmlaq_rot270_laneq_f32): New.
* config/aarch64/aarch64.h (TARGET_COMPLEX): New.
* config/aarch64/iterators.md (UNSPEC_FCADD90, UNSPEC_FCADD270,
UNSPEC_FCMLA, UNSPEC_FCMLA90, UNSPEC_FCMLA180, UNSPEC_FCMLA270): New.
(FCADD, FCMLA): New.
(rot): New.
* config/arm/types.md (neon_fcadd, neon_fcmla): New.
gcc/testsuite/ChangeLog:
2019-01-10 Tamar Christina <tamar.christina@arm.com>
* gcc.target/aarch64/advsimd-intrinsics/vector-complex.c: New test.
* gcc.target/aarch64/advsimd-intrinsics/vector-complex_f16.c: New test.
From-SVN: r267795
2019-01-10 04:30:59 +01:00
|
|
|
case AARCH64_SIMD_BUILTIN_FCMLA_LANEQ0_V2SF:
|
|
|
|
case AARCH64_SIMD_BUILTIN_FCMLA_LANEQ90_V2SF:
|
|
|
|
case AARCH64_SIMD_BUILTIN_FCMLA_LANEQ180_V2SF:
|
|
|
|
case AARCH64_SIMD_BUILTIN_FCMLA_LANEQ270_V2SF:
|
|
|
|
case AARCH64_SIMD_BUILTIN_FCMLA_LANEQ0_V4HF:
|
|
|
|
case AARCH64_SIMD_BUILTIN_FCMLA_LANEQ90_V4HF:
|
|
|
|
case AARCH64_SIMD_BUILTIN_FCMLA_LANEQ180_V4HF:
|
|
|
|
case AARCH64_SIMD_BUILTIN_FCMLA_LANEQ270_V4HF:
|
|
|
|
return aarch64_expand_fcmla_builtin (exp, target, fcode);
|
2019-10-21 12:52:05 +02:00
|
|
|
case AARCH64_BUILTIN_RNG_RNDR:
|
|
|
|
case AARCH64_BUILTIN_RNG_RNDRRS:
|
|
|
|
return aarch64_expand_rng_builtin (exp, target, fcode, ignore);
|
2014-05-23 00:05:08 +02:00
|
|
|
}
|
2012-11-20 13:10:37 +01:00
|
|
|
|
2014-06-11 11:17:18 +02:00
|
|
|
if (fcode >= AARCH64_SIMD_BUILTIN_BASE && fcode <= AARCH64_SIMD_BUILTIN_MAX)
|
2012-11-20 13:10:37 +01:00
|
|
|
return aarch64_simd_expand_builtin (fcode, exp, target);
|
2014-06-11 11:17:18 +02:00
|
|
|
else if (fcode >= AARCH64_CRC32_BUILTIN_BASE && fcode <= AARCH64_CRC32_BUILTIN_MAX)
|
|
|
|
return aarch64_crc32_expand_builtin (fcode, exp, target);
|
2012-11-20 13:10:37 +01:00
|
|
|
|
2015-11-06 18:10:17 +01:00
|
|
|
if (fcode == AARCH64_BUILTIN_RSQRT_DF
|
|
|
|
|| fcode == AARCH64_BUILTIN_RSQRT_SF
|
|
|
|
|| fcode == AARCH64_BUILTIN_RSQRT_V2DF
|
|
|
|
|| fcode == AARCH64_BUILTIN_RSQRT_V2SF
|
|
|
|
|| fcode == AARCH64_BUILTIN_RSQRT_V4SF)
|
|
|
|
return aarch64_expand_builtin_rsqrt (fcode, exp, target);
|
|
|
|
|
[GCC, AArch64] Enable Transactional Memory Extension
This patch enables the new Transactional Memory Extension announced recently
as part of Arm's new architecture technologies.
We introduce a new optional extension "tme" to enable this. The following
instructions are part of the extension:
* tstart <Xt>
* ttest <Xt>
* tcommit
* tcancel #<imm>
We have also added ACLE intrinsics for the instructions.
*** gcc/ChangeLog ***
2019-07-31 Sudakshina Das <sudi.das@arm.com>
* config/aarch64/aarch64-builtins.c (enum aarch64_builtins): Add
AARCH64_TME_BUILTIN_TSTART, AARCH64_TME_BUILTIN_TCOMMIT,
AARCH64_TME_BUILTIN_TTEST and AARCH64_TME_BUILTIN_TCANCEL.
(aarch64_init_tme_builtins): New.
(aarch64_init_builtins): Call aarch64_init_tme_builtins.
(aarch64_expand_builtin_tme): New.
(aarch64_expand_builtin): Handle TME builtins.
* config/aarch64/aarch64-c.c (aarch64_update_cpp_builtins): Define
__ARM_FEATURE_TME when enabled.
* config/aarch64/aarch64-option-extensions.def: Add "tme".
* config/aarch64/aarch64.h (AARCH64_FL_TME, AARCH64_ISA_TME): New.
(TARGET_TME): New.
* config/aarch64/aarch64.md (define_c_enum "unspec"): Add UNSPEC_TTEST.
(define_c_enum "unspecv"): Add UNSPECV_TSTART, UNSPECV_TCOMMIT and
UNSPECV_TCANCEL.
(tstart, ttest, tcommit, tcancel): New instructions.
* config/aarch64/arm_acle.h (__tstart, __tcommit): New.
(__tcancel, __ttest): New.
(_TMFAILURE_REASON, _TMFAILURE_RTRY, _TMFAILURE_CNCL): New macro.
(_TMFAILURE_MEM, _TMFAILURE_IMP, _TMFAILURE_ERR): Likewise.
(_TMFAILURE_SIZE, _TMFAILURE_NEST, _TMFAILURE_DBG): Likewise.
(_TMFAILURE_INT, _TMFAILURE_TRIVIAL): Likewise.
* config/arm/types.md: Add new tme type attr.
* doc/invoke.texi: Document "tme".
*** gcc/testsuite/ChangeLog ***
2019-07-31 Sudakshina Das <sudi.das@arm.com>
* gcc.target/aarch64/acle/tme.c: New test.
* gcc.target/aarch64/pragma_cpp_predefs_2.c: New test.
From-SVN: r273926
2019-07-31 11:19:53 +02:00
|
|
|
if (fcode == AARCH64_TME_BUILTIN_TSTART
|
|
|
|
|| fcode == AARCH64_TME_BUILTIN_TCOMMIT
|
|
|
|
|| fcode == AARCH64_TME_BUILTIN_TTEST
|
|
|
|
|| fcode == AARCH64_TME_BUILTIN_TCANCEL)
|
|
|
|
return aarch64_expand_builtin_tme (fcode, exp, target);
|
|
|
|
|
2021-12-14 15:03:38 +01:00
|
|
|
if (fcode == AARCH64_LS64_BUILTIN_LD64B
|
|
|
|
|| fcode == AARCH64_LS64_BUILTIN_ST64B
|
|
|
|
|| fcode == AARCH64_LS64_BUILTIN_ST64BV
|
|
|
|
|| fcode == AARCH64_LS64_BUILTIN_ST64BV0)
|
|
|
|
return aarch64_expand_builtin_ls64 (fcode, exp, target);
|
|
|
|
|
[AArch64] Implement Armv8.5-A memory tagging (MTE) intrinsics
2019-11-19 Dennis Zhang <dennis.zhang@arm.com>
* config/aarch64/aarch64-builtins.c (enum aarch64_builtins): Add
AARCH64_MEMTAG_BUILTIN_START, AARCH64_MEMTAG_BUILTIN_IRG,
AARCH64_MEMTAG_BUILTIN_GMI, AARCH64_MEMTAG_BUILTIN_SUBP,
AARCH64_MEMTAG_BUILTIN_INC_TAG, AARCH64_MEMTAG_BUILTIN_SET_TAG,
AARCH64_MEMTAG_BUILTIN_GET_TAG, and AARCH64_MEMTAG_BUILTIN_END.
(aarch64_init_memtag_builtins): New.
(AARCH64_INIT_MEMTAG_BUILTINS_DECL): New macro.
(aarch64_general_init_builtins): Call aarch64_init_memtag_builtins.
(aarch64_expand_builtin_memtag): New.
(aarch64_general_expand_builtin): Call aarch64_expand_builtin_memtag.
(AARCH64_BUILTIN_SUBCODE): New macro.
(aarch64_resolve_overloaded_memtag): New.
(aarch64_resolve_overloaded_builtin_general): New. Call
aarch64_resolve_overloaded_memtag to handle overloaded MTE builtins.
* config/aarch64/aarch64-c.c (aarch64_update_cpp_builtins): Define
__ARM_FEATURE_MEMORY_TAGGING when enabled.
(aarch64_resolve_overloaded_builtin): Call
aarch64_resolve_overloaded_builtin_general.
* config/aarch64/aarch64-protos.h
(aarch64_resolve_overloaded_builtin_general): New declaration.
* config/aarch64/aarch64.h (AARCH64_ISA_MEMTAG): New macro.
(TARGET_MEMTAG): Likewise.
* config/aarch64/aarch64.md (UNSPEC_GEN_TAG): New unspec.
(UNSPEC_GEN_TAG_RND, and UNSPEC_TAG_SPACE): Likewise.
(irg, gmi, subp, addg, ldg, stg): New instructions.
* config/aarch64/arm_acle.h (__arm_mte_create_random_tag): New macro.
(__arm_mte_exclude_tag, __arm_mte_ptrdiff): Likewise.
(__arm_mte_increment_tag, __arm_mte_set_tag): Likewise.
(__arm_mte_get_tag): Likewise.
* config/aarch64/predicates.md (aarch64_memtag_tag_offset): New.
(aarch64_granule16_uimm6, aarch64_granule16_simm9): New.
* config/arm/types.md (memtag): New.
* doc/invoke.texi (-memtag): Update description.
2019-11-19 Dennis Zhang <dennis.zhang@arm.com>
* gcc.target/aarch64/acle/memtag_1.c: New test.
* gcc.target/aarch64/acle/memtag_2.c: New test.
* gcc.target/aarch64/acle/memtag_3.c: New test.
From-SVN: r278444
2019-11-19 14:43:39 +01:00
|
|
|
if (fcode >= AARCH64_MEMTAG_BUILTIN_START
|
|
|
|
&& fcode <= AARCH64_MEMTAG_BUILTIN_END)
|
|
|
|
return aarch64_expand_builtin_memtag (fcode, exp, target);
|
|
|
|
|
2014-09-09 12:15:46 +02:00
|
|
|
gcc_unreachable ();
|
2012-11-20 13:10:37 +01:00
|
|
|
}
|
[AARCH64] Add support for vectorizable standard math patterns.
gcc/
* config/aarch64/aarch64-builtins.c
(aarch64_builtin_vectorized_function): New.
* config/aarch64/aarch64-protos.h
(aarch64_builtin_vectorized_function): Declare.
* config/aarch64/aarch64-simd-builtins.def (frintz, frintp): Add.
(frintm, frinti, frintx, frinta, fcvtzs, fcvtzu): Likewise.
(fcvtas, fcvtau, fcvtps, fcvtpu, fcvtms, fcvtmu): Likewise.
* config/aarch64/aarch64-simd.md
(aarch64_frint_<frint_suffix><mode>): New.
(<frint_pattern><mode>2): Likewise.
(aarch64_fcvt<frint_suffix><su><mode>): Likewise.
(l<fcvt_pattern><su_optab><fcvt_target><VDQF:mode>2): Likewise.
* config/aarch64/aarch64.c (TARGET_VECTORIZE_BUILTINS): Define.
(TARGET_VECTORIZE_BUILTIN_VECTORIZED_FUNCTION): Likewise.
* config/aarch64/aarch64.md
(btrunc<mode>2, ceil<mode>2, floor<mode>2)
(round<mode>2, rint<mode>2, nearbyint<mode>2): Consolidate as...
(<frint_pattern><mode>2): ...this.
(lceil<su_optab><mode><mode>2, lfloor<su_optab><mode><mode>2)
(lround<su_optab><mode><mode>2)
(lrint<su_optab><mode><mode>2): Consolidate as...
(l<fcvt_pattern><su_optab><GPF:mode><GPI:mode>2): ... this.
* config/aarch64/iterators.md (fcvt_target): New.
(FCVT_TARGET): Likewise.
(FRINT): Likewise.
(FCVT): Likewise.
(frint_pattern): Likewise.
(frint_suffix): Likewise.
(fcvt_pattern): Likewise.
gcc/testsuite/
* gcc.dg/vect/vect-rounding-btrunc.c: New test.
* gcc.dg/vect/vect-rounding-btruncf.c: Likewise.
* gcc.dg/vect/vect-rounding-ceil.c: Likewise.
* gcc.dg/vect/vect-rounding-ceilf.c: Likewise.
* gcc.dg/vect/vect-rounding-floor.c: Likewise.
* gcc.dg/vect/vect-rounding-floorf.c: Likewise.
* gcc.dg/vect/vect-rounding-lceil.c: Likewise.
* gcc.dg/vect/vect-rounding-lfloor.c: Likewise.
* gcc.dg/vect/vect-rounding-nearbyint.c: Likewise.
* gcc.dg/vect/vect-rounding-nearbyintf.c: Likewise.
* gcc.dg/vect/vect-rounding-round.c: Likewise.
* gcc.dg/vect/vect-rounding-roundf.c: Likewise.
* target-supports.exp
(check_effective_target_vect_call_btrunc): New.
(check_effective_target_vect_call_btruncf): Likewise.
(check_effective_target_vect_call_ceil): Likewise.
(check_effective_target_vect_call_ceilf): Likewise.
(check_effective_target_vect_call_floor): Likewise.
(check_effective_target_vect_call_floorf): Likewise.
(check_effective_target_vect_call_lceil): Likewise.
(check_effective_target_vect_call_lfloor): Likewise.
(check_effective_target_vect_call_nearbyint): Likewise.
(check_effective_target_vect_call_nearbyintf): Likewise.
(check_effective_target_vect_call_round): Likewise.
(check_effective_target_vect_call_roundf): Likewise.
From-SVN: r194197
2012-12-05 11:34:31 +01:00
|
|
|
|
|
|
|
tree
|
2015-11-17 19:55:13 +01:00
|
|
|
aarch64_builtin_vectorized_function (unsigned int fn, tree type_out,
|
|
|
|
tree type_in)
|
[AARCH64] Add support for vectorizable standard math patterns.
gcc/
* config/aarch64/aarch64-builtins.c
(aarch64_builtin_vectorized_function): New.
* config/aarch64/aarch64-protos.h
(aarch64_builtin_vectorized_function): Declare.
* config/aarch64/aarch64-simd-builtins.def (frintz, frintp): Add.
(frintm, frinti, frintx, frinta, fcvtzs, fcvtzu): Likewise.
(fcvtas, fcvtau, fcvtps, fcvtpu, fcvtms, fcvtmu): Likewise.
* config/aarch64/aarch64-simd.md
(aarch64_frint_<frint_suffix><mode>): New.
(<frint_pattern><mode>2): Likewise.
(aarch64_fcvt<frint_suffix><su><mode>): Likewise.
(l<fcvt_pattern><su_optab><fcvt_target><VDQF:mode>2): Likewise.
* config/aarch64/aarch64.c (TARGET_VECTORIZE_BUILTINS): Define.
(TARGET_VECTORIZE_BUILTIN_VECTORIZED_FUNCTION): Likewise.
* config/aarch64/aarch64.md
(btrunc<mode>2, ceil<mode>2, floor<mode>2)
(round<mode>2, rint<mode>2, nearbyint<mode>2): Consolidate as...
(<frint_pattern><mode>2): ...this.
(lceil<su_optab><mode><mode>2, lfloor<su_optab><mode><mode>2)
(lround<su_optab><mode><mode>2)
(lrint<su_optab><mode><mode>2): Consolidate as...
(l<fcvt_pattern><su_optab><GPF:mode><GPI:mode>2): ... this.
* config/aarch64/iterators.md (fcvt_target): New.
(FCVT_TARGET): Likewise.
(FRINT): Likewise.
(FCVT): Likewise.
(frint_pattern): Likewise.
(frint_suffix): Likewise.
(fcvt_pattern): Likewise.
gcc/testsuite/
* gcc.dg/vect/vect-rounding-btrunc.c: New test.
* gcc.dg/vect/vect-rounding-btruncf.c: Likewise.
* gcc.dg/vect/vect-rounding-ceil.c: Likewise.
* gcc.dg/vect/vect-rounding-ceilf.c: Likewise.
* gcc.dg/vect/vect-rounding-floor.c: Likewise.
* gcc.dg/vect/vect-rounding-floorf.c: Likewise.
* gcc.dg/vect/vect-rounding-lceil.c: Likewise.
* gcc.dg/vect/vect-rounding-lfloor.c: Likewise.
* gcc.dg/vect/vect-rounding-nearbyint.c: Likewise.
* gcc.dg/vect/vect-rounding-nearbyintf.c: Likewise.
* gcc.dg/vect/vect-rounding-round.c: Likewise.
* gcc.dg/vect/vect-rounding-roundf.c: Likewise.
* target-supports.exp
(check_effective_target_vect_call_btrunc): New.
(check_effective_target_vect_call_btruncf): Likewise.
(check_effective_target_vect_call_ceil): Likewise.
(check_effective_target_vect_call_ceilf): Likewise.
(check_effective_target_vect_call_floor): Likewise.
(check_effective_target_vect_call_floorf): Likewise.
(check_effective_target_vect_call_lceil): Likewise.
(check_effective_target_vect_call_lfloor): Likewise.
(check_effective_target_vect_call_nearbyint): Likewise.
(check_effective_target_vect_call_nearbyintf): Likewise.
(check_effective_target_vect_call_round): Likewise.
(check_effective_target_vect_call_roundf): Likewise.
From-SVN: r194197
2012-12-05 11:34:31 +01:00
|
|
|
{
|
decl.c, [...]: Remove redundant enum from machine_mode.
gcc/ada/
* gcc-interface/decl.c, gcc-interface/gigi.h, gcc-interface/misc.c,
gcc-interface/trans.c, gcc-interface/utils.c, gcc-interface/utils2.c:
Remove redundant enum from machine_mode.
gcc/c-family/
* c-common.c, c-common.h, c-cppbuiltin.c, c-lex.c: Remove redundant
enum from machine_mode.
gcc/c/
* c-decl.c, c-tree.h, c-typeck.c: Remove redundant enum from
machine_mode.
gcc/cp/
* constexpr.c: Remove redundant enum from machine_mode.
gcc/fortran/
* trans-types.c, trans-types.h: Remove redundant enum from
machine_mode.
gcc/go/
* go-lang.c: Remove redundant enum from machine_mode.
gcc/java/
* builtins.c, java-tree.h, typeck.c: Remove redundant enum from
machine_mode.
gcc/lto/
* lto-lang.c: Remove redundant enum from machine_mode.
gcc/
* addresses.h, alias.c, asan.c, auto-inc-dec.c, bt-load.c, builtins.c,
builtins.h, caller-save.c, calls.c, calls.h, cfgexpand.c, cfgloop.h,
cfgrtl.c, combine.c, compare-elim.c, config/aarch64/aarch64-builtins.c,
config/aarch64/aarch64-protos.h, config/aarch64/aarch64-simd.md,
config/aarch64/aarch64.c, config/aarch64/aarch64.h,
config/aarch64/aarch64.md, config/alpha/alpha-protos.h,
config/alpha/alpha.c, config/arc/arc-protos.h, config/arc/arc.c,
config/arc/arc.h, config/arc/predicates.md,
config/arm/aarch-common-protos.h, config/arm/aarch-common.c,
config/arm/arm-protos.h, config/arm/arm.c, config/arm/arm.h,
config/arm/arm.md, config/arm/neon.md, config/arm/thumb2.md,
config/avr/avr-log.c, config/avr/avr-protos.h, config/avr/avr.c,
config/avr/avr.md, config/bfin/bfin-protos.h, config/bfin/bfin.c,
config/c6x/c6x-protos.h, config/c6x/c6x.c, config/c6x/c6x.md,
config/cr16/cr16-protos.h, config/cr16/cr16.c,
config/cris/cris-protos.h, config/cris/cris.c, config/cris/cris.md,
config/darwin-protos.h, config/darwin.c,
config/epiphany/epiphany-protos.h, config/epiphany/epiphany.c,
config/epiphany/epiphany.md, config/fr30/fr30.c,
config/frv/frv-protos.h, config/frv/frv.c, config/frv/predicates.md,
config/h8300/h8300-protos.h, config/h8300/h8300.c,
config/i386/i386-builtin-types.awk, config/i386/i386-protos.h,
config/i386/i386.c, config/i386/i386.md, config/i386/predicates.md,
config/i386/sse.md, config/i386/sync.md, config/ia64/ia64-protos.h,
config/ia64/ia64.c, config/iq2000/iq2000-protos.h,
config/iq2000/iq2000.c, config/iq2000/iq2000.md,
config/lm32/lm32-protos.h, config/lm32/lm32.c,
config/m32c/m32c-protos.h, config/m32c/m32c.c,
config/m32r/m32r-protos.h, config/m32r/m32r.c,
config/m68k/m68k-protos.h, config/m68k/m68k.c,
config/mcore/mcore-protos.h, config/mcore/mcore.c,
config/mcore/mcore.md, config/mep/mep-protos.h, config/mep/mep.c,
config/microblaze/microblaze-protos.h, config/microblaze/microblaze.c,
config/mips/mips-protos.h, config/mips/mips.c,
config/mmix/mmix-protos.h, config/mmix/mmix.c,
config/mn10300/mn10300-protos.h, config/mn10300/mn10300.c,
config/moxie/moxie.c, config/msp430/msp430-protos.h,
config/msp430/msp430.c, config/nds32/nds32-cost.c,
config/nds32/nds32-intrinsic.c, config/nds32/nds32-md-auxiliary.c,
config/nds32/nds32-protos.h, config/nds32/nds32.c,
config/nios2/nios2-protos.h, config/nios2/nios2.c,
config/pa/pa-protos.h, config/pa/pa.c, config/pdp11/pdp11-protos.h,
config/pdp11/pdp11.c, config/rl78/rl78-protos.h, config/rl78/rl78.c,
config/rs6000/altivec.md, config/rs6000/rs6000-c.c,
config/rs6000/rs6000-protos.h, config/rs6000/rs6000.c,
config/rs6000/rs6000.h, config/rx/rx-protos.h, config/rx/rx.c,
config/s390/predicates.md, config/s390/s390-protos.h,
config/s390/s390.c, config/s390/s390.h, config/s390/s390.md,
config/sh/predicates.md, config/sh/sh-protos.h, config/sh/sh.c,
config/sh/sh.md, config/sparc/predicates.md,
config/sparc/sparc-protos.h, config/sparc/sparc.c,
config/sparc/sparc.md, config/spu/spu-protos.h, config/spu/spu.c,
config/stormy16/stormy16-protos.h, config/stormy16/stormy16.c,
config/tilegx/tilegx-protos.h, config/tilegx/tilegx.c,
config/tilegx/tilegx.md, config/tilepro/tilepro-protos.h,
config/tilepro/tilepro.c, config/v850/v850-protos.h,
config/v850/v850.c, config/v850/v850.md, config/vax/vax-protos.h,
config/vax/vax.c, config/vms/vms-c.c, config/xtensa/xtensa-protos.h,
config/xtensa/xtensa.c, coverage.c, cprop.c, cse.c, cselib.c, cselib.h,
dbxout.c, ddg.c, df-problems.c, dfp.c, dfp.h, doc/md.texi,
doc/rtl.texi, doc/tm.texi, doc/tm.texi.in, dojump.c, dse.c,
dwarf2cfi.c, dwarf2out.c, dwarf2out.h, emit-rtl.c, emit-rtl.h,
except.c, explow.c, expmed.c, expmed.h, expr.c, expr.h, final.c,
fixed-value.c, fixed-value.h, fold-const.c, function.c, function.h,
fwprop.c, gcse.c, gengenrtl.c, genmodes.c, genopinit.c, genoutput.c,
genpreds.c, genrecog.c, gensupport.c, gimple-ssa-strength-reduction.c,
graphite-clast-to-gimple.c, haifa-sched.c, hooks.c, hooks.h, ifcvt.c,
internal-fn.c, ira-build.c, ira-color.c, ira-conflicts.c, ira-costs.c,
ira-emit.c, ira-int.h, ira-lives.c, ira.c, ira.h, jump.c, langhooks.h,
libfuncs.h, lists.c, loop-doloop.c, loop-invariant.c, loop-iv.c,
loop-unroll.c, lower-subreg.c, lower-subreg.h, lra-assigns.c,
lra-constraints.c, lra-eliminations.c, lra-int.h, lra-lives.c,
lra-spills.c, lra.c, lra.h, machmode.h, omp-low.c, optabs.c, optabs.h,
output.h, postreload.c, print-tree.c, read-rtl.c, real.c, real.h,
recog.c, recog.h, ree.c, reg-stack.c, regcprop.c, reginfo.c,
regrename.c, regs.h, reload.c, reload.h, reload1.c, rtl.c, rtl.h,
rtlanal.c, rtlhash.c, rtlhooks-def.h, rtlhooks.c, sched-deps.c,
sel-sched-dump.c, sel-sched-ir.c, sel-sched-ir.h, sel-sched.c,
simplify-rtx.c, stmt.c, stor-layout.c, stor-layout.h, target.def,
targhooks.c, targhooks.h, tree-affine.c, tree-call-cdce.c,
tree-complex.c, tree-data-ref.c, tree-dfa.c, tree-if-conv.c,
tree-inline.c, tree-outof-ssa.c, tree-scalar-evolution.c,
tree-ssa-address.c, tree-ssa-ccp.c, tree-ssa-loop-ivopts.c,
tree-ssa-loop-ivopts.h, tree-ssa-loop-manip.c,
tree-ssa-loop-prefetch.c, tree-ssa-math-opts.c, tree-ssa-reassoc.c,
tree-ssa-sccvn.c, tree-streamer-in.c, tree-switch-conversion.c,
tree-vect-data-refs.c, tree-vect-generic.c, tree-vect-loop.c,
tree-vect-patterns.c, tree-vect-slp.c, tree-vect-stmts.c,
tree-vrp.c, tree.c, tree.h, tsan.c, ubsan.c, valtrack.c,
var-tracking.c, varasm.c: Remove redundant enum from
machine_mode.
gcc/
* gengtype.c (main): Treat machine_mode as a scalar typedef.
* genmodes.c (emit_insn_modes_h): Hide inline functions if
USED_FOR_TARGET.
From-SVN: r216834
2014-10-29 13:02:45 +01:00
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machine_mode in_mode, out_mode;
|
[AARCH64] Add support for vectorizable standard math patterns.
gcc/
* config/aarch64/aarch64-builtins.c
(aarch64_builtin_vectorized_function): New.
* config/aarch64/aarch64-protos.h
(aarch64_builtin_vectorized_function): Declare.
* config/aarch64/aarch64-simd-builtins.def (frintz, frintp): Add.
(frintm, frinti, frintx, frinta, fcvtzs, fcvtzu): Likewise.
(fcvtas, fcvtau, fcvtps, fcvtpu, fcvtms, fcvtmu): Likewise.
* config/aarch64/aarch64-simd.md
(aarch64_frint_<frint_suffix><mode>): New.
(<frint_pattern><mode>2): Likewise.
(aarch64_fcvt<frint_suffix><su><mode>): Likewise.
(l<fcvt_pattern><su_optab><fcvt_target><VDQF:mode>2): Likewise.
* config/aarch64/aarch64.c (TARGET_VECTORIZE_BUILTINS): Define.
(TARGET_VECTORIZE_BUILTIN_VECTORIZED_FUNCTION): Likewise.
* config/aarch64/aarch64.md
(btrunc<mode>2, ceil<mode>2, floor<mode>2)
(round<mode>2, rint<mode>2, nearbyint<mode>2): Consolidate as...
(<frint_pattern><mode>2): ...this.
(lceil<su_optab><mode><mode>2, lfloor<su_optab><mode><mode>2)
(lround<su_optab><mode><mode>2)
(lrint<su_optab><mode><mode>2): Consolidate as...
(l<fcvt_pattern><su_optab><GPF:mode><GPI:mode>2): ... this.
* config/aarch64/iterators.md (fcvt_target): New.
(FCVT_TARGET): Likewise.
(FRINT): Likewise.
(FCVT): Likewise.
(frint_pattern): Likewise.
(frint_suffix): Likewise.
(fcvt_pattern): Likewise.
gcc/testsuite/
* gcc.dg/vect/vect-rounding-btrunc.c: New test.
* gcc.dg/vect/vect-rounding-btruncf.c: Likewise.
* gcc.dg/vect/vect-rounding-ceil.c: Likewise.
* gcc.dg/vect/vect-rounding-ceilf.c: Likewise.
* gcc.dg/vect/vect-rounding-floor.c: Likewise.
* gcc.dg/vect/vect-rounding-floorf.c: Likewise.
* gcc.dg/vect/vect-rounding-lceil.c: Likewise.
* gcc.dg/vect/vect-rounding-lfloor.c: Likewise.
* gcc.dg/vect/vect-rounding-nearbyint.c: Likewise.
* gcc.dg/vect/vect-rounding-nearbyintf.c: Likewise.
* gcc.dg/vect/vect-rounding-round.c: Likewise.
* gcc.dg/vect/vect-rounding-roundf.c: Likewise.
* target-supports.exp
(check_effective_target_vect_call_btrunc): New.
(check_effective_target_vect_call_btruncf): Likewise.
(check_effective_target_vect_call_ceil): Likewise.
(check_effective_target_vect_call_ceilf): Likewise.
(check_effective_target_vect_call_floor): Likewise.
(check_effective_target_vect_call_floorf): Likewise.
(check_effective_target_vect_call_lceil): Likewise.
(check_effective_target_vect_call_lfloor): Likewise.
(check_effective_target_vect_call_nearbyint): Likewise.
(check_effective_target_vect_call_nearbyintf): Likewise.
(check_effective_target_vect_call_round): Likewise.
(check_effective_target_vect_call_roundf): Likewise.
From-SVN: r194197
2012-12-05 11:34:31 +01:00
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if (TREE_CODE (type_out) != VECTOR_TYPE
|
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|| TREE_CODE (type_in) != VECTOR_TYPE)
|
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return NULL_TREE;
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2020-01-10 16:05:40 +01:00
|
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out_mode = TYPE_MODE (type_out);
|
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in_mode = TYPE_MODE (type_in);
|
[AARCH64] Add support for vectorizable standard math patterns.
gcc/
* config/aarch64/aarch64-builtins.c
(aarch64_builtin_vectorized_function): New.
* config/aarch64/aarch64-protos.h
(aarch64_builtin_vectorized_function): Declare.
* config/aarch64/aarch64-simd-builtins.def (frintz, frintp): Add.
(frintm, frinti, frintx, frinta, fcvtzs, fcvtzu): Likewise.
(fcvtas, fcvtau, fcvtps, fcvtpu, fcvtms, fcvtmu): Likewise.
* config/aarch64/aarch64-simd.md
(aarch64_frint_<frint_suffix><mode>): New.
(<frint_pattern><mode>2): Likewise.
(aarch64_fcvt<frint_suffix><su><mode>): Likewise.
(l<fcvt_pattern><su_optab><fcvt_target><VDQF:mode>2): Likewise.
* config/aarch64/aarch64.c (TARGET_VECTORIZE_BUILTINS): Define.
(TARGET_VECTORIZE_BUILTIN_VECTORIZED_FUNCTION): Likewise.
* config/aarch64/aarch64.md
(btrunc<mode>2, ceil<mode>2, floor<mode>2)
(round<mode>2, rint<mode>2, nearbyint<mode>2): Consolidate as...
(<frint_pattern><mode>2): ...this.
(lceil<su_optab><mode><mode>2, lfloor<su_optab><mode><mode>2)
(lround<su_optab><mode><mode>2)
(lrint<su_optab><mode><mode>2): Consolidate as...
(l<fcvt_pattern><su_optab><GPF:mode><GPI:mode>2): ... this.
* config/aarch64/iterators.md (fcvt_target): New.
(FCVT_TARGET): Likewise.
(FRINT): Likewise.
(FCVT): Likewise.
(frint_pattern): Likewise.
(frint_suffix): Likewise.
(fcvt_pattern): Likewise.
gcc/testsuite/
* gcc.dg/vect/vect-rounding-btrunc.c: New test.
* gcc.dg/vect/vect-rounding-btruncf.c: Likewise.
* gcc.dg/vect/vect-rounding-ceil.c: Likewise.
* gcc.dg/vect/vect-rounding-ceilf.c: Likewise.
* gcc.dg/vect/vect-rounding-floor.c: Likewise.
* gcc.dg/vect/vect-rounding-floorf.c: Likewise.
* gcc.dg/vect/vect-rounding-lceil.c: Likewise.
* gcc.dg/vect/vect-rounding-lfloor.c: Likewise.
* gcc.dg/vect/vect-rounding-nearbyint.c: Likewise.
* gcc.dg/vect/vect-rounding-nearbyintf.c: Likewise.
* gcc.dg/vect/vect-rounding-round.c: Likewise.
* gcc.dg/vect/vect-rounding-roundf.c: Likewise.
* target-supports.exp
(check_effective_target_vect_call_btrunc): New.
(check_effective_target_vect_call_btruncf): Likewise.
(check_effective_target_vect_call_ceil): Likewise.
(check_effective_target_vect_call_ceilf): Likewise.
(check_effective_target_vect_call_floor): Likewise.
(check_effective_target_vect_call_floorf): Likewise.
(check_effective_target_vect_call_lceil): Likewise.
(check_effective_target_vect_call_lfloor): Likewise.
(check_effective_target_vect_call_nearbyint): Likewise.
(check_effective_target_vect_call_nearbyintf): Likewise.
(check_effective_target_vect_call_round): Likewise.
(check_effective_target_vect_call_roundf): Likewise.
From-SVN: r194197
2012-12-05 11:34:31 +01:00
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#undef AARCH64_CHECK_BUILTIN_MODE
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#define AARCH64_CHECK_BUILTIN_MODE(C, N) 1
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#define AARCH64_FIND_FRINT_VARIANT(N) \
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(AARCH64_CHECK_BUILTIN_MODE (2, D) \
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2013-11-26 10:59:10 +01:00
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? aarch64_builtin_decls[AARCH64_SIMD_BUILTIN_UNOP_##N##v2df] \
|
[AARCH64] Add support for vectorizable standard math patterns.
gcc/
* config/aarch64/aarch64-builtins.c
(aarch64_builtin_vectorized_function): New.
* config/aarch64/aarch64-protos.h
(aarch64_builtin_vectorized_function): Declare.
* config/aarch64/aarch64-simd-builtins.def (frintz, frintp): Add.
(frintm, frinti, frintx, frinta, fcvtzs, fcvtzu): Likewise.
(fcvtas, fcvtau, fcvtps, fcvtpu, fcvtms, fcvtmu): Likewise.
* config/aarch64/aarch64-simd.md
(aarch64_frint_<frint_suffix><mode>): New.
(<frint_pattern><mode>2): Likewise.
(aarch64_fcvt<frint_suffix><su><mode>): Likewise.
(l<fcvt_pattern><su_optab><fcvt_target><VDQF:mode>2): Likewise.
* config/aarch64/aarch64.c (TARGET_VECTORIZE_BUILTINS): Define.
(TARGET_VECTORIZE_BUILTIN_VECTORIZED_FUNCTION): Likewise.
* config/aarch64/aarch64.md
(btrunc<mode>2, ceil<mode>2, floor<mode>2)
(round<mode>2, rint<mode>2, nearbyint<mode>2): Consolidate as...
(<frint_pattern><mode>2): ...this.
(lceil<su_optab><mode><mode>2, lfloor<su_optab><mode><mode>2)
(lround<su_optab><mode><mode>2)
(lrint<su_optab><mode><mode>2): Consolidate as...
(l<fcvt_pattern><su_optab><GPF:mode><GPI:mode>2): ... this.
* config/aarch64/iterators.md (fcvt_target): New.
(FCVT_TARGET): Likewise.
(FRINT): Likewise.
(FCVT): Likewise.
(frint_pattern): Likewise.
(frint_suffix): Likewise.
(fcvt_pattern): Likewise.
gcc/testsuite/
* gcc.dg/vect/vect-rounding-btrunc.c: New test.
* gcc.dg/vect/vect-rounding-btruncf.c: Likewise.
* gcc.dg/vect/vect-rounding-ceil.c: Likewise.
* gcc.dg/vect/vect-rounding-ceilf.c: Likewise.
* gcc.dg/vect/vect-rounding-floor.c: Likewise.
* gcc.dg/vect/vect-rounding-floorf.c: Likewise.
* gcc.dg/vect/vect-rounding-lceil.c: Likewise.
* gcc.dg/vect/vect-rounding-lfloor.c: Likewise.
* gcc.dg/vect/vect-rounding-nearbyint.c: Likewise.
* gcc.dg/vect/vect-rounding-nearbyintf.c: Likewise.
* gcc.dg/vect/vect-rounding-round.c: Likewise.
* gcc.dg/vect/vect-rounding-roundf.c: Likewise.
* target-supports.exp
(check_effective_target_vect_call_btrunc): New.
(check_effective_target_vect_call_btruncf): Likewise.
(check_effective_target_vect_call_ceil): Likewise.
(check_effective_target_vect_call_ceilf): Likewise.
(check_effective_target_vect_call_floor): Likewise.
(check_effective_target_vect_call_floorf): Likewise.
(check_effective_target_vect_call_lceil): Likewise.
(check_effective_target_vect_call_lfloor): Likewise.
(check_effective_target_vect_call_nearbyint): Likewise.
(check_effective_target_vect_call_nearbyintf): Likewise.
(check_effective_target_vect_call_round): Likewise.
(check_effective_target_vect_call_roundf): Likewise.
From-SVN: r194197
2012-12-05 11:34:31 +01:00
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: (AARCH64_CHECK_BUILTIN_MODE (4, S) \
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2013-11-26 10:59:10 +01:00
|
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? aarch64_builtin_decls[AARCH64_SIMD_BUILTIN_UNOP_##N##v4sf] \
|
[AARCH64] Add support for vectorizable standard math patterns.
gcc/
* config/aarch64/aarch64-builtins.c
(aarch64_builtin_vectorized_function): New.
* config/aarch64/aarch64-protos.h
(aarch64_builtin_vectorized_function): Declare.
* config/aarch64/aarch64-simd-builtins.def (frintz, frintp): Add.
(frintm, frinti, frintx, frinta, fcvtzs, fcvtzu): Likewise.
(fcvtas, fcvtau, fcvtps, fcvtpu, fcvtms, fcvtmu): Likewise.
* config/aarch64/aarch64-simd.md
(aarch64_frint_<frint_suffix><mode>): New.
(<frint_pattern><mode>2): Likewise.
(aarch64_fcvt<frint_suffix><su><mode>): Likewise.
(l<fcvt_pattern><su_optab><fcvt_target><VDQF:mode>2): Likewise.
* config/aarch64/aarch64.c (TARGET_VECTORIZE_BUILTINS): Define.
(TARGET_VECTORIZE_BUILTIN_VECTORIZED_FUNCTION): Likewise.
* config/aarch64/aarch64.md
(btrunc<mode>2, ceil<mode>2, floor<mode>2)
(round<mode>2, rint<mode>2, nearbyint<mode>2): Consolidate as...
(<frint_pattern><mode>2): ...this.
(lceil<su_optab><mode><mode>2, lfloor<su_optab><mode><mode>2)
(lround<su_optab><mode><mode>2)
(lrint<su_optab><mode><mode>2): Consolidate as...
(l<fcvt_pattern><su_optab><GPF:mode><GPI:mode>2): ... this.
* config/aarch64/iterators.md (fcvt_target): New.
(FCVT_TARGET): Likewise.
(FRINT): Likewise.
(FCVT): Likewise.
(frint_pattern): Likewise.
(frint_suffix): Likewise.
(fcvt_pattern): Likewise.
gcc/testsuite/
* gcc.dg/vect/vect-rounding-btrunc.c: New test.
* gcc.dg/vect/vect-rounding-btruncf.c: Likewise.
* gcc.dg/vect/vect-rounding-ceil.c: Likewise.
* gcc.dg/vect/vect-rounding-ceilf.c: Likewise.
* gcc.dg/vect/vect-rounding-floor.c: Likewise.
* gcc.dg/vect/vect-rounding-floorf.c: Likewise.
* gcc.dg/vect/vect-rounding-lceil.c: Likewise.
* gcc.dg/vect/vect-rounding-lfloor.c: Likewise.
* gcc.dg/vect/vect-rounding-nearbyint.c: Likewise.
* gcc.dg/vect/vect-rounding-nearbyintf.c: Likewise.
* gcc.dg/vect/vect-rounding-round.c: Likewise.
* gcc.dg/vect/vect-rounding-roundf.c: Likewise.
* target-supports.exp
(check_effective_target_vect_call_btrunc): New.
(check_effective_target_vect_call_btruncf): Likewise.
(check_effective_target_vect_call_ceil): Likewise.
(check_effective_target_vect_call_ceilf): Likewise.
(check_effective_target_vect_call_floor): Likewise.
(check_effective_target_vect_call_floorf): Likewise.
(check_effective_target_vect_call_lceil): Likewise.
(check_effective_target_vect_call_lfloor): Likewise.
(check_effective_target_vect_call_nearbyint): Likewise.
(check_effective_target_vect_call_nearbyintf): Likewise.
(check_effective_target_vect_call_round): Likewise.
(check_effective_target_vect_call_roundf): Likewise.
From-SVN: r194197
2012-12-05 11:34:31 +01:00
|
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: (AARCH64_CHECK_BUILTIN_MODE (2, S) \
|
2013-11-26 10:59:10 +01:00
|
|
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? aarch64_builtin_decls[AARCH64_SIMD_BUILTIN_UNOP_##N##v2sf] \
|
[AARCH64] Add support for vectorizable standard math patterns.
gcc/
* config/aarch64/aarch64-builtins.c
(aarch64_builtin_vectorized_function): New.
* config/aarch64/aarch64-protos.h
(aarch64_builtin_vectorized_function): Declare.
* config/aarch64/aarch64-simd-builtins.def (frintz, frintp): Add.
(frintm, frinti, frintx, frinta, fcvtzs, fcvtzu): Likewise.
(fcvtas, fcvtau, fcvtps, fcvtpu, fcvtms, fcvtmu): Likewise.
* config/aarch64/aarch64-simd.md
(aarch64_frint_<frint_suffix><mode>): New.
(<frint_pattern><mode>2): Likewise.
(aarch64_fcvt<frint_suffix><su><mode>): Likewise.
(l<fcvt_pattern><su_optab><fcvt_target><VDQF:mode>2): Likewise.
* config/aarch64/aarch64.c (TARGET_VECTORIZE_BUILTINS): Define.
(TARGET_VECTORIZE_BUILTIN_VECTORIZED_FUNCTION): Likewise.
* config/aarch64/aarch64.md
(btrunc<mode>2, ceil<mode>2, floor<mode>2)
(round<mode>2, rint<mode>2, nearbyint<mode>2): Consolidate as...
(<frint_pattern><mode>2): ...this.
(lceil<su_optab><mode><mode>2, lfloor<su_optab><mode><mode>2)
(lround<su_optab><mode><mode>2)
(lrint<su_optab><mode><mode>2): Consolidate as...
(l<fcvt_pattern><su_optab><GPF:mode><GPI:mode>2): ... this.
* config/aarch64/iterators.md (fcvt_target): New.
(FCVT_TARGET): Likewise.
(FRINT): Likewise.
(FCVT): Likewise.
(frint_pattern): Likewise.
(frint_suffix): Likewise.
(fcvt_pattern): Likewise.
gcc/testsuite/
* gcc.dg/vect/vect-rounding-btrunc.c: New test.
* gcc.dg/vect/vect-rounding-btruncf.c: Likewise.
* gcc.dg/vect/vect-rounding-ceil.c: Likewise.
* gcc.dg/vect/vect-rounding-ceilf.c: Likewise.
* gcc.dg/vect/vect-rounding-floor.c: Likewise.
* gcc.dg/vect/vect-rounding-floorf.c: Likewise.
* gcc.dg/vect/vect-rounding-lceil.c: Likewise.
* gcc.dg/vect/vect-rounding-lfloor.c: Likewise.
* gcc.dg/vect/vect-rounding-nearbyint.c: Likewise.
* gcc.dg/vect/vect-rounding-nearbyintf.c: Likewise.
* gcc.dg/vect/vect-rounding-round.c: Likewise.
* gcc.dg/vect/vect-rounding-roundf.c: Likewise.
* target-supports.exp
(check_effective_target_vect_call_btrunc): New.
(check_effective_target_vect_call_btruncf): Likewise.
(check_effective_target_vect_call_ceil): Likewise.
(check_effective_target_vect_call_ceilf): Likewise.
(check_effective_target_vect_call_floor): Likewise.
(check_effective_target_vect_call_floorf): Likewise.
(check_effective_target_vect_call_lceil): Likewise.
(check_effective_target_vect_call_lfloor): Likewise.
(check_effective_target_vect_call_nearbyint): Likewise.
(check_effective_target_vect_call_nearbyintf): Likewise.
(check_effective_target_vect_call_round): Likewise.
(check_effective_target_vect_call_roundf): Likewise.
From-SVN: r194197
2012-12-05 11:34:31 +01:00
|
|
|
: NULL_TREE)))
|
2015-11-17 19:55:13 +01:00
|
|
|
switch (fn)
|
[AARCH64] Add support for vectorizable standard math patterns.
gcc/
* config/aarch64/aarch64-builtins.c
(aarch64_builtin_vectorized_function): New.
* config/aarch64/aarch64-protos.h
(aarch64_builtin_vectorized_function): Declare.
* config/aarch64/aarch64-simd-builtins.def (frintz, frintp): Add.
(frintm, frinti, frintx, frinta, fcvtzs, fcvtzu): Likewise.
(fcvtas, fcvtau, fcvtps, fcvtpu, fcvtms, fcvtmu): Likewise.
* config/aarch64/aarch64-simd.md
(aarch64_frint_<frint_suffix><mode>): New.
(<frint_pattern><mode>2): Likewise.
(aarch64_fcvt<frint_suffix><su><mode>): Likewise.
(l<fcvt_pattern><su_optab><fcvt_target><VDQF:mode>2): Likewise.
* config/aarch64/aarch64.c (TARGET_VECTORIZE_BUILTINS): Define.
(TARGET_VECTORIZE_BUILTIN_VECTORIZED_FUNCTION): Likewise.
* config/aarch64/aarch64.md
(btrunc<mode>2, ceil<mode>2, floor<mode>2)
(round<mode>2, rint<mode>2, nearbyint<mode>2): Consolidate as...
(<frint_pattern><mode>2): ...this.
(lceil<su_optab><mode><mode>2, lfloor<su_optab><mode><mode>2)
(lround<su_optab><mode><mode>2)
(lrint<su_optab><mode><mode>2): Consolidate as...
(l<fcvt_pattern><su_optab><GPF:mode><GPI:mode>2): ... this.
* config/aarch64/iterators.md (fcvt_target): New.
(FCVT_TARGET): Likewise.
(FRINT): Likewise.
(FCVT): Likewise.
(frint_pattern): Likewise.
(frint_suffix): Likewise.
(fcvt_pattern): Likewise.
gcc/testsuite/
* gcc.dg/vect/vect-rounding-btrunc.c: New test.
* gcc.dg/vect/vect-rounding-btruncf.c: Likewise.
* gcc.dg/vect/vect-rounding-ceil.c: Likewise.
* gcc.dg/vect/vect-rounding-ceilf.c: Likewise.
* gcc.dg/vect/vect-rounding-floor.c: Likewise.
* gcc.dg/vect/vect-rounding-floorf.c: Likewise.
* gcc.dg/vect/vect-rounding-lceil.c: Likewise.
* gcc.dg/vect/vect-rounding-lfloor.c: Likewise.
* gcc.dg/vect/vect-rounding-nearbyint.c: Likewise.
* gcc.dg/vect/vect-rounding-nearbyintf.c: Likewise.
* gcc.dg/vect/vect-rounding-round.c: Likewise.
* gcc.dg/vect/vect-rounding-roundf.c: Likewise.
* target-supports.exp
(check_effective_target_vect_call_btrunc): New.
(check_effective_target_vect_call_btruncf): Likewise.
(check_effective_target_vect_call_ceil): Likewise.
(check_effective_target_vect_call_ceilf): Likewise.
(check_effective_target_vect_call_floor): Likewise.
(check_effective_target_vect_call_floorf): Likewise.
(check_effective_target_vect_call_lceil): Likewise.
(check_effective_target_vect_call_lfloor): Likewise.
(check_effective_target_vect_call_nearbyint): Likewise.
(check_effective_target_vect_call_nearbyintf): Likewise.
(check_effective_target_vect_call_round): Likewise.
(check_effective_target_vect_call_roundf): Likewise.
From-SVN: r194197
2012-12-05 11:34:31 +01:00
|
|
|
{
|
|
|
|
#undef AARCH64_CHECK_BUILTIN_MODE
|
|
|
|
#define AARCH64_CHECK_BUILTIN_MODE(C, N) \
|
2020-01-10 16:05:40 +01:00
|
|
|
(out_mode == V##C##N##Fmode && in_mode == V##C##N##Fmode)
|
2015-11-17 19:55:13 +01:00
|
|
|
CASE_CFN_FLOOR:
|
|
|
|
return AARCH64_FIND_FRINT_VARIANT (floor);
|
|
|
|
CASE_CFN_CEIL:
|
|
|
|
return AARCH64_FIND_FRINT_VARIANT (ceil);
|
|
|
|
CASE_CFN_TRUNC:
|
|
|
|
return AARCH64_FIND_FRINT_VARIANT (btrunc);
|
|
|
|
CASE_CFN_ROUND:
|
|
|
|
return AARCH64_FIND_FRINT_VARIANT (round);
|
|
|
|
CASE_CFN_NEARBYINT:
|
|
|
|
return AARCH64_FIND_FRINT_VARIANT (nearbyint);
|
|
|
|
CASE_CFN_SQRT:
|
|
|
|
return AARCH64_FIND_FRINT_VARIANT (sqrt);
|
[AARCH64] Add support for vectorizable standard math patterns.
gcc/
* config/aarch64/aarch64-builtins.c
(aarch64_builtin_vectorized_function): New.
* config/aarch64/aarch64-protos.h
(aarch64_builtin_vectorized_function): Declare.
* config/aarch64/aarch64-simd-builtins.def (frintz, frintp): Add.
(frintm, frinti, frintx, frinta, fcvtzs, fcvtzu): Likewise.
(fcvtas, fcvtau, fcvtps, fcvtpu, fcvtms, fcvtmu): Likewise.
* config/aarch64/aarch64-simd.md
(aarch64_frint_<frint_suffix><mode>): New.
(<frint_pattern><mode>2): Likewise.
(aarch64_fcvt<frint_suffix><su><mode>): Likewise.
(l<fcvt_pattern><su_optab><fcvt_target><VDQF:mode>2): Likewise.
* config/aarch64/aarch64.c (TARGET_VECTORIZE_BUILTINS): Define.
(TARGET_VECTORIZE_BUILTIN_VECTORIZED_FUNCTION): Likewise.
* config/aarch64/aarch64.md
(btrunc<mode>2, ceil<mode>2, floor<mode>2)
(round<mode>2, rint<mode>2, nearbyint<mode>2): Consolidate as...
(<frint_pattern><mode>2): ...this.
(lceil<su_optab><mode><mode>2, lfloor<su_optab><mode><mode>2)
(lround<su_optab><mode><mode>2)
(lrint<su_optab><mode><mode>2): Consolidate as...
(l<fcvt_pattern><su_optab><GPF:mode><GPI:mode>2): ... this.
* config/aarch64/iterators.md (fcvt_target): New.
(FCVT_TARGET): Likewise.
(FRINT): Likewise.
(FCVT): Likewise.
(frint_pattern): Likewise.
(frint_suffix): Likewise.
(fcvt_pattern): Likewise.
gcc/testsuite/
* gcc.dg/vect/vect-rounding-btrunc.c: New test.
* gcc.dg/vect/vect-rounding-btruncf.c: Likewise.
* gcc.dg/vect/vect-rounding-ceil.c: Likewise.
* gcc.dg/vect/vect-rounding-ceilf.c: Likewise.
* gcc.dg/vect/vect-rounding-floor.c: Likewise.
* gcc.dg/vect/vect-rounding-floorf.c: Likewise.
* gcc.dg/vect/vect-rounding-lceil.c: Likewise.
* gcc.dg/vect/vect-rounding-lfloor.c: Likewise.
* gcc.dg/vect/vect-rounding-nearbyint.c: Likewise.
* gcc.dg/vect/vect-rounding-nearbyintf.c: Likewise.
* gcc.dg/vect/vect-rounding-round.c: Likewise.
* gcc.dg/vect/vect-rounding-roundf.c: Likewise.
* target-supports.exp
(check_effective_target_vect_call_btrunc): New.
(check_effective_target_vect_call_btruncf): Likewise.
(check_effective_target_vect_call_ceil): Likewise.
(check_effective_target_vect_call_ceilf): Likewise.
(check_effective_target_vect_call_floor): Likewise.
(check_effective_target_vect_call_floorf): Likewise.
(check_effective_target_vect_call_lceil): Likewise.
(check_effective_target_vect_call_lfloor): Likewise.
(check_effective_target_vect_call_nearbyint): Likewise.
(check_effective_target_vect_call_nearbyintf): Likewise.
(check_effective_target_vect_call_round): Likewise.
(check_effective_target_vect_call_roundf): Likewise.
From-SVN: r194197
2012-12-05 11:34:31 +01:00
|
|
|
#undef AARCH64_CHECK_BUILTIN_MODE
|
2013-05-23 15:36:41 +02:00
|
|
|
#define AARCH64_CHECK_BUILTIN_MODE(C, N) \
|
2020-01-10 16:05:40 +01:00
|
|
|
(out_mode == V##C##SImode && in_mode == V##C##N##Imode)
|
2015-11-17 19:55:13 +01:00
|
|
|
CASE_CFN_CLZ:
|
|
|
|
{
|
|
|
|
if (AARCH64_CHECK_BUILTIN_MODE (4, S))
|
|
|
|
return aarch64_builtin_decls[AARCH64_SIMD_BUILTIN_UNOP_clzv4si];
|
|
|
|
return NULL_TREE;
|
|
|
|
}
|
|
|
|
CASE_CFN_CTZ:
|
|
|
|
{
|
|
|
|
if (AARCH64_CHECK_BUILTIN_MODE (2, S))
|
|
|
|
return aarch64_builtin_decls[AARCH64_SIMD_BUILTIN_UNOP_ctzv2si];
|
|
|
|
else if (AARCH64_CHECK_BUILTIN_MODE (4, S))
|
|
|
|
return aarch64_builtin_decls[AARCH64_SIMD_BUILTIN_UNOP_ctzv4si];
|
|
|
|
return NULL_TREE;
|
|
|
|
}
|
2013-05-23 15:36:41 +02:00
|
|
|
#undef AARCH64_CHECK_BUILTIN_MODE
|
[AARCH64] Add support for vectorizable standard math patterns.
gcc/
* config/aarch64/aarch64-builtins.c
(aarch64_builtin_vectorized_function): New.
* config/aarch64/aarch64-protos.h
(aarch64_builtin_vectorized_function): Declare.
* config/aarch64/aarch64-simd-builtins.def (frintz, frintp): Add.
(frintm, frinti, frintx, frinta, fcvtzs, fcvtzu): Likewise.
(fcvtas, fcvtau, fcvtps, fcvtpu, fcvtms, fcvtmu): Likewise.
* config/aarch64/aarch64-simd.md
(aarch64_frint_<frint_suffix><mode>): New.
(<frint_pattern><mode>2): Likewise.
(aarch64_fcvt<frint_suffix><su><mode>): Likewise.
(l<fcvt_pattern><su_optab><fcvt_target><VDQF:mode>2): Likewise.
* config/aarch64/aarch64.c (TARGET_VECTORIZE_BUILTINS): Define.
(TARGET_VECTORIZE_BUILTIN_VECTORIZED_FUNCTION): Likewise.
* config/aarch64/aarch64.md
(btrunc<mode>2, ceil<mode>2, floor<mode>2)
(round<mode>2, rint<mode>2, nearbyint<mode>2): Consolidate as...
(<frint_pattern><mode>2): ...this.
(lceil<su_optab><mode><mode>2, lfloor<su_optab><mode><mode>2)
(lround<su_optab><mode><mode>2)
(lrint<su_optab><mode><mode>2): Consolidate as...
(l<fcvt_pattern><su_optab><GPF:mode><GPI:mode>2): ... this.
* config/aarch64/iterators.md (fcvt_target): New.
(FCVT_TARGET): Likewise.
(FRINT): Likewise.
(FCVT): Likewise.
(frint_pattern): Likewise.
(frint_suffix): Likewise.
(fcvt_pattern): Likewise.
gcc/testsuite/
* gcc.dg/vect/vect-rounding-btrunc.c: New test.
* gcc.dg/vect/vect-rounding-btruncf.c: Likewise.
* gcc.dg/vect/vect-rounding-ceil.c: Likewise.
* gcc.dg/vect/vect-rounding-ceilf.c: Likewise.
* gcc.dg/vect/vect-rounding-floor.c: Likewise.
* gcc.dg/vect/vect-rounding-floorf.c: Likewise.
* gcc.dg/vect/vect-rounding-lceil.c: Likewise.
* gcc.dg/vect/vect-rounding-lfloor.c: Likewise.
* gcc.dg/vect/vect-rounding-nearbyint.c: Likewise.
* gcc.dg/vect/vect-rounding-nearbyintf.c: Likewise.
* gcc.dg/vect/vect-rounding-round.c: Likewise.
* gcc.dg/vect/vect-rounding-roundf.c: Likewise.
* target-supports.exp
(check_effective_target_vect_call_btrunc): New.
(check_effective_target_vect_call_btruncf): Likewise.
(check_effective_target_vect_call_ceil): Likewise.
(check_effective_target_vect_call_ceilf): Likewise.
(check_effective_target_vect_call_floor): Likewise.
(check_effective_target_vect_call_floorf): Likewise.
(check_effective_target_vect_call_lceil): Likewise.
(check_effective_target_vect_call_lfloor): Likewise.
(check_effective_target_vect_call_nearbyint): Likewise.
(check_effective_target_vect_call_nearbyintf): Likewise.
(check_effective_target_vect_call_round): Likewise.
(check_effective_target_vect_call_roundf): Likewise.
From-SVN: r194197
2012-12-05 11:34:31 +01:00
|
|
|
#define AARCH64_CHECK_BUILTIN_MODE(C, N) \
|
2020-01-10 16:05:40 +01:00
|
|
|
(out_mode == V##C##N##Imode && in_mode == V##C##N##Fmode)
|
2015-11-17 19:55:13 +01:00
|
|
|
CASE_CFN_IFLOOR:
|
|
|
|
CASE_CFN_LFLOOR:
|
|
|
|
CASE_CFN_LLFLOOR:
|
|
|
|
{
|
|
|
|
enum aarch64_builtins builtin;
|
|
|
|
if (AARCH64_CHECK_BUILTIN_MODE (2, D))
|
|
|
|
builtin = AARCH64_SIMD_BUILTIN_UNOP_lfloorv2dfv2di;
|
|
|
|
else if (AARCH64_CHECK_BUILTIN_MODE (4, S))
|
|
|
|
builtin = AARCH64_SIMD_BUILTIN_UNOP_lfloorv4sfv4si;
|
|
|
|
else if (AARCH64_CHECK_BUILTIN_MODE (2, S))
|
|
|
|
builtin = AARCH64_SIMD_BUILTIN_UNOP_lfloorv2sfv2si;
|
|
|
|
else
|
|
|
|
return NULL_TREE;
|
|
|
|
|
|
|
|
return aarch64_builtin_decls[builtin];
|
|
|
|
}
|
|
|
|
CASE_CFN_ICEIL:
|
|
|
|
CASE_CFN_LCEIL:
|
|
|
|
CASE_CFN_LLCEIL:
|
|
|
|
{
|
|
|
|
enum aarch64_builtins builtin;
|
|
|
|
if (AARCH64_CHECK_BUILTIN_MODE (2, D))
|
|
|
|
builtin = AARCH64_SIMD_BUILTIN_UNOP_lceilv2dfv2di;
|
|
|
|
else if (AARCH64_CHECK_BUILTIN_MODE (4, S))
|
|
|
|
builtin = AARCH64_SIMD_BUILTIN_UNOP_lceilv4sfv4si;
|
|
|
|
else if (AARCH64_CHECK_BUILTIN_MODE (2, S))
|
|
|
|
builtin = AARCH64_SIMD_BUILTIN_UNOP_lceilv2sfv2si;
|
|
|
|
else
|
|
|
|
return NULL_TREE;
|
|
|
|
|
|
|
|
return aarch64_builtin_decls[builtin];
|
|
|
|
}
|
|
|
|
CASE_CFN_IROUND:
|
|
|
|
CASE_CFN_LROUND:
|
|
|
|
CASE_CFN_LLROUND:
|
|
|
|
{
|
|
|
|
enum aarch64_builtins builtin;
|
|
|
|
if (AARCH64_CHECK_BUILTIN_MODE (2, D))
|
|
|
|
builtin = AARCH64_SIMD_BUILTIN_UNOP_lroundv2dfv2di;
|
|
|
|
else if (AARCH64_CHECK_BUILTIN_MODE (4, S))
|
|
|
|
builtin = AARCH64_SIMD_BUILTIN_UNOP_lroundv4sfv4si;
|
|
|
|
else if (AARCH64_CHECK_BUILTIN_MODE (2, S))
|
|
|
|
builtin = AARCH64_SIMD_BUILTIN_UNOP_lroundv2sfv2si;
|
|
|
|
else
|
|
|
|
return NULL_TREE;
|
|
|
|
|
|
|
|
return aarch64_builtin_decls[builtin];
|
|
|
|
}
|
|
|
|
default:
|
|
|
|
return NULL_TREE;
|
[AARCH64] Add support for vectorizable standard math patterns.
gcc/
* config/aarch64/aarch64-builtins.c
(aarch64_builtin_vectorized_function): New.
* config/aarch64/aarch64-protos.h
(aarch64_builtin_vectorized_function): Declare.
* config/aarch64/aarch64-simd-builtins.def (frintz, frintp): Add.
(frintm, frinti, frintx, frinta, fcvtzs, fcvtzu): Likewise.
(fcvtas, fcvtau, fcvtps, fcvtpu, fcvtms, fcvtmu): Likewise.
* config/aarch64/aarch64-simd.md
(aarch64_frint_<frint_suffix><mode>): New.
(<frint_pattern><mode>2): Likewise.
(aarch64_fcvt<frint_suffix><su><mode>): Likewise.
(l<fcvt_pattern><su_optab><fcvt_target><VDQF:mode>2): Likewise.
* config/aarch64/aarch64.c (TARGET_VECTORIZE_BUILTINS): Define.
(TARGET_VECTORIZE_BUILTIN_VECTORIZED_FUNCTION): Likewise.
* config/aarch64/aarch64.md
(btrunc<mode>2, ceil<mode>2, floor<mode>2)
(round<mode>2, rint<mode>2, nearbyint<mode>2): Consolidate as...
(<frint_pattern><mode>2): ...this.
(lceil<su_optab><mode><mode>2, lfloor<su_optab><mode><mode>2)
(lround<su_optab><mode><mode>2)
(lrint<su_optab><mode><mode>2): Consolidate as...
(l<fcvt_pattern><su_optab><GPF:mode><GPI:mode>2): ... this.
* config/aarch64/iterators.md (fcvt_target): New.
(FCVT_TARGET): Likewise.
(FRINT): Likewise.
(FCVT): Likewise.
(frint_pattern): Likewise.
(frint_suffix): Likewise.
(fcvt_pattern): Likewise.
gcc/testsuite/
* gcc.dg/vect/vect-rounding-btrunc.c: New test.
* gcc.dg/vect/vect-rounding-btruncf.c: Likewise.
* gcc.dg/vect/vect-rounding-ceil.c: Likewise.
* gcc.dg/vect/vect-rounding-ceilf.c: Likewise.
* gcc.dg/vect/vect-rounding-floor.c: Likewise.
* gcc.dg/vect/vect-rounding-floorf.c: Likewise.
* gcc.dg/vect/vect-rounding-lceil.c: Likewise.
* gcc.dg/vect/vect-rounding-lfloor.c: Likewise.
* gcc.dg/vect/vect-rounding-nearbyint.c: Likewise.
* gcc.dg/vect/vect-rounding-nearbyintf.c: Likewise.
* gcc.dg/vect/vect-rounding-round.c: Likewise.
* gcc.dg/vect/vect-rounding-roundf.c: Likewise.
* target-supports.exp
(check_effective_target_vect_call_btrunc): New.
(check_effective_target_vect_call_btruncf): Likewise.
(check_effective_target_vect_call_ceil): Likewise.
(check_effective_target_vect_call_ceilf): Likewise.
(check_effective_target_vect_call_floor): Likewise.
(check_effective_target_vect_call_floorf): Likewise.
(check_effective_target_vect_call_lceil): Likewise.
(check_effective_target_vect_call_lfloor): Likewise.
(check_effective_target_vect_call_nearbyint): Likewise.
(check_effective_target_vect_call_nearbyintf): Likewise.
(check_effective_target_vect_call_round): Likewise.
(check_effective_target_vect_call_roundf): Likewise.
From-SVN: r194197
2012-12-05 11:34:31 +01:00
|
|
|
}
|
|
|
|
|
|
|
|
return NULL_TREE;
|
|
|
|
}
|
2013-04-25 14:44:25 +02:00
|
|
|
|
2015-11-06 18:10:17 +01:00
|
|
|
/* Return builtin for reciprocal square root. */
|
|
|
|
|
|
|
|
tree
|
[AArch64] Split built-in function codes into major and minor codes
It was easier to add the SVE ACLE support without enumerating every
function at build time. This in turn meant that it was easier if the
SVE builtins occupied a distinct numberspace from the existing AArch64
ones, which *are* enumerated at build time. This patch therefore
divides the built-in functions codes into "major" and "minor" codes.
At present the major code is just "general", but the SVE patch will add
"SVE" as well.
Also, it was convenient to put the SVE ACLE support in its own file,
so the patch makes aarch64.c provide the frontline target hooks directly,
forwarding to the other files for the real work.
The reason for organising the files this way is that aarch64.c needs
to define the target hook macros whatever happens, and having aarch64.c
macros forward to aarch64-builtins.c functions and aarch64-bulitins.c
functions forward to the SVE file seemed a bit indirect. Doing things
the way the patch does them puts aarch64-builtins.c and the SVE code on
more of an equal footing.
The aarch64_(general_)gimple_fold_builtin change is mostly just
reindentation.
2019-09-27 Richard Sandiford <richard.sandiford@arm.com>
gcc/
* config/aarch64/aarch64-protos.h (aarch64_builtin_class): New enum.
(AARCH64_BUILTIN_SHIFT, AARCH64_BUILTIN_CLASS): New constants.
(aarch64_gimple_fold_builtin, aarch64_mangle_builtin_type)
(aarch64_fold_builtin, aarch64_init_builtins, aarch64_expand_builtin):
(aarch64_builtin_decl, aarch64_builtin_rsqrt): Delete.
(aarch64_general_mangle_builtin_type, aarch64_general_init_builtins):
(aarch64_general_fold_builtin, aarch64_general_gimple_fold_builtin):
(aarch64_general_expand_builtin, aarch64_general_builtin_decl):
(aarch64_general_builtin_rsqrt): Declare.
* config/aarch64/aarch64-builtins.c (aarch64_general_add_builtin):
New function.
(aarch64_mangle_builtin_type): Rename to...
(aarch64_general_mangle_builtin_type): ...this.
(aarch64_init_fcmla_laneq_builtins, aarch64_init_simd_builtins)
(aarch64_init_crc32_builtins, aarch64_init_builtin_rsqrt)
(aarch64_init_pauth_hint_builtins, aarch64_init_tme_builtins): Use
aarch64_general_add_builtin instead of add_builtin_function.
(aarch64_init_builtins): Rename to...
(aarch64_general_init_builtins): ...this. Use
aarch64_general_add_builtin instead of add_builtin_function.
(aarch64_builtin_decl): Rename to...
(aarch64_general_builtin_decl): ...this and remove the unused
arguments.
(aarch64_expand_builtin): Rename to...
(aarch64_general_expand_builtin): ...this and remove the unused
arguments.
(aarch64_builtin_rsqrt): Rename to...
(aarch64_general_builtin_rsqrt): ...this.
(aarch64_fold_builtin): Rename to...
(aarch64_general_fold_builtin): ...this. Take the function subcode
and return type as arguments. Remove the "ignored" argument.
(aarch64_gimple_fold_builtin): Rename to...
(aarch64_general_gimple_fold_builtin): ...this. Take the function
subcode and gcall as arguments, and return the new function call.
* config/aarch64/aarch64.c (aarch64_init_builtins)
(aarch64_fold_builtin, aarch64_gimple_fold_builtin)
(aarch64_expand_builtin, aarch64_builtin_decl): New functions.
(aarch64_builtin_reciprocal): Call aarch64_general_builtin_rsqrt
instead of aarch64_builtin_rsqrt.
(aarch64_mangle_type): Call aarch64_general_mangle_builtin_type
instead of aarch64_mangle_builtin_type.
From-SVN: r276177
2019-09-27 10:47:21 +02:00
|
|
|
aarch64_general_builtin_rsqrt (unsigned int fn)
|
2015-11-06 18:10:17 +01:00
|
|
|
{
|
Add an rsqrt_optab and IFN_RSQRT internal function
All current uses of builtin_reciprocal convert 1.0/sqrt into rsqrt.
This patch adds an rsqrt optab and associated internal function for
that instead. We can then pick up the vector forms of rsqrt automatically,
fixing an AArch64 regression from my internal_fn patches.
With that change, builtin_reciprocal only needs to handle target-specific
built-in functions. I've restricted the hook to those since, if we need
a reciprocal of another standard function later, I think there should be
a strong preference for adding a new optab and internal function for it,
rather than hiding the code in a backend.
Three targets implement builtin_reciprocal: aarch64, i386 and rs6000.
i386 and rs6000 already used the obvious rsqrt<mode>2 pattern names
for the instructions, so they pick up the new code automatically.
aarch64 needs a slight rename.
mn10300 is unusual in that its native operation is rsqrt, and
sqrt is approximated as 1.0/rsqrt. The port also uses rsqrt<mode>2
for the rsqrt pattern, so after the patch we now pick it up as a native
operation.
Two other ports define rsqrt patterns: sh and v850. AFAICT these
patterns aren't currently used, but I think the patch does what the
authors of the patterns would have expected. There's obviously some
risk of fallout though.
Tested on x86_64-linux-gnu, aarch64-linux-gnu, arm-linux-gnueabihf
(as a target without the hooks) and powerpc64-linux-gnu.
gcc/
* internal-fn.def (RSQRT): New function.
* optabs.def (rsqrt_optab): New optab.
* doc/md.texi (rsqrtM2): Document.
* target.def (builtin_reciprocal): Replace gcall argument with
a function decl. Restrict hook to machine functions.
* doc/tm.texi: Regenerate.
* targhooks.h (default_builtin_reciprocal): Update prototype.
* targhooks.c (default_builtin_reciprocal): Likewise.
* tree-ssa-math-opts.c: Include internal-fn.h.
(internal_fn_reciprocal): New function.
(pass_cse_reciprocals::execute): Call it, and build a call to an
internal function on success. Only call targetm.builtin_reciprocal
for machine functions.
* config/aarch64/aarch64-protos.h (aarch64_builtin_rsqrt): Remove
second argument.
* config/aarch64/aarch64-builtins.c (aarch64_expand_builtin_rsqrt):
Rename aarch64_rsqrt_<mode>2 to rsqrt<mode>2.
(aarch64_builtin_rsqrt): Remove md_fn argument and only handle
machine functions.
* config/aarch64/aarch64.c (use_rsqrt_p): New function.
(aarch64_builtin_reciprocal): Replace gcall argument with a
function decl. Use use_rsqrt_p. Remove optimize_size check.
Only handle machine functions. Update call to aarch64_builtin_rsqrt.
(aarch64_optab_supported_p): New function.
(TARGET_OPTAB_SUPPORTED_P): Define.
* config/aarch64/aarch64-simd.md (aarch64_rsqrt_<mode>2): Rename to...
(rsqrt<mode>2): ...this.
* config/i386/i386.c (use_rsqrt_p): New function.
(ix86_builtin_reciprocal): Replace gcall argument with a
function decl. Use use_rsqrt_p. Remove optimize_insn_for_size_p
check. Only handle machine functions.
(ix86_optab_supported_p): Handle rsqrt_optab.
* config/rs6000/rs6000.c (TARGET_OPTAB_SUPPORTED_P): Define.
(rs6000_builtin_reciprocal): Replace gcall argument with a
function decl. Remove optimize_insn_for_size_p check.
Only handle machine functions.
(rs6000_optab_supported_p): New function.
From-SVN: r231229
2015-12-03 15:31:55 +01:00
|
|
|
if (fn == AARCH64_SIMD_BUILTIN_UNOP_sqrtv2df)
|
|
|
|
return aarch64_builtin_decls[AARCH64_BUILTIN_RSQRT_V2DF];
|
|
|
|
if (fn == AARCH64_SIMD_BUILTIN_UNOP_sqrtv2sf)
|
|
|
|
return aarch64_builtin_decls[AARCH64_BUILTIN_RSQRT_V2SF];
|
|
|
|
if (fn == AARCH64_SIMD_BUILTIN_UNOP_sqrtv4sf)
|
|
|
|
return aarch64_builtin_decls[AARCH64_BUILTIN_RSQRT_V4SF];
|
2015-11-06 18:10:17 +01:00
|
|
|
return NULL_TREE;
|
|
|
|
}
|
|
|
|
|
2021-09-02 09:08:22 +02:00
|
|
|
/* Return true if the lane check can be removed as there is no
|
|
|
|
error going to be emitted. */
|
|
|
|
static bool
|
|
|
|
aarch64_fold_builtin_lane_check (tree arg0, tree arg1, tree arg2)
|
|
|
|
{
|
|
|
|
if (TREE_CODE (arg0) != INTEGER_CST)
|
|
|
|
return false;
|
|
|
|
if (TREE_CODE (arg1) != INTEGER_CST)
|
|
|
|
return false;
|
|
|
|
if (TREE_CODE (arg2) != INTEGER_CST)
|
|
|
|
return false;
|
|
|
|
|
|
|
|
auto totalsize = wi::to_widest (arg0);
|
|
|
|
auto elementsize = wi::to_widest (arg1);
|
|
|
|
if (totalsize == 0 || elementsize == 0)
|
|
|
|
return false;
|
|
|
|
auto lane = wi::to_widest (arg2);
|
|
|
|
auto high = wi::udiv_trunc (totalsize, elementsize);
|
|
|
|
return wi::ltu_p (lane, high);
|
|
|
|
}
|
|
|
|
|
2013-04-25 14:44:25 +02:00
|
|
|
#undef VAR1
|
2020-07-17 11:00:37 +02:00
|
|
|
#define VAR1(T, N, MAP, FLAG, A) \
|
2013-11-26 10:59:10 +01:00
|
|
|
case AARCH64_SIMD_BUILTIN_##T##_##N##A:
|
2013-04-25 14:44:25 +02:00
|
|
|
|
[AArch64] Split built-in function codes into major and minor codes
It was easier to add the SVE ACLE support without enumerating every
function at build time. This in turn meant that it was easier if the
SVE builtins occupied a distinct numberspace from the existing AArch64
ones, which *are* enumerated at build time. This patch therefore
divides the built-in functions codes into "major" and "minor" codes.
At present the major code is just "general", but the SVE patch will add
"SVE" as well.
Also, it was convenient to put the SVE ACLE support in its own file,
so the patch makes aarch64.c provide the frontline target hooks directly,
forwarding to the other files for the real work.
The reason for organising the files this way is that aarch64.c needs
to define the target hook macros whatever happens, and having aarch64.c
macros forward to aarch64-builtins.c functions and aarch64-bulitins.c
functions forward to the SVE file seemed a bit indirect. Doing things
the way the patch does them puts aarch64-builtins.c and the SVE code on
more of an equal footing.
The aarch64_(general_)gimple_fold_builtin change is mostly just
reindentation.
2019-09-27 Richard Sandiford <richard.sandiford@arm.com>
gcc/
* config/aarch64/aarch64-protos.h (aarch64_builtin_class): New enum.
(AARCH64_BUILTIN_SHIFT, AARCH64_BUILTIN_CLASS): New constants.
(aarch64_gimple_fold_builtin, aarch64_mangle_builtin_type)
(aarch64_fold_builtin, aarch64_init_builtins, aarch64_expand_builtin):
(aarch64_builtin_decl, aarch64_builtin_rsqrt): Delete.
(aarch64_general_mangle_builtin_type, aarch64_general_init_builtins):
(aarch64_general_fold_builtin, aarch64_general_gimple_fold_builtin):
(aarch64_general_expand_builtin, aarch64_general_builtin_decl):
(aarch64_general_builtin_rsqrt): Declare.
* config/aarch64/aarch64-builtins.c (aarch64_general_add_builtin):
New function.
(aarch64_mangle_builtin_type): Rename to...
(aarch64_general_mangle_builtin_type): ...this.
(aarch64_init_fcmla_laneq_builtins, aarch64_init_simd_builtins)
(aarch64_init_crc32_builtins, aarch64_init_builtin_rsqrt)
(aarch64_init_pauth_hint_builtins, aarch64_init_tme_builtins): Use
aarch64_general_add_builtin instead of add_builtin_function.
(aarch64_init_builtins): Rename to...
(aarch64_general_init_builtins): ...this. Use
aarch64_general_add_builtin instead of add_builtin_function.
(aarch64_builtin_decl): Rename to...
(aarch64_general_builtin_decl): ...this and remove the unused
arguments.
(aarch64_expand_builtin): Rename to...
(aarch64_general_expand_builtin): ...this and remove the unused
arguments.
(aarch64_builtin_rsqrt): Rename to...
(aarch64_general_builtin_rsqrt): ...this.
(aarch64_fold_builtin): Rename to...
(aarch64_general_fold_builtin): ...this. Take the function subcode
and return type as arguments. Remove the "ignored" argument.
(aarch64_gimple_fold_builtin): Rename to...
(aarch64_general_gimple_fold_builtin): ...this. Take the function
subcode and gcall as arguments, and return the new function call.
* config/aarch64/aarch64.c (aarch64_init_builtins)
(aarch64_fold_builtin, aarch64_gimple_fold_builtin)
(aarch64_expand_builtin, aarch64_builtin_decl): New functions.
(aarch64_builtin_reciprocal): Call aarch64_general_builtin_rsqrt
instead of aarch64_builtin_rsqrt.
(aarch64_mangle_type): Call aarch64_general_mangle_builtin_type
instead of aarch64_mangle_builtin_type.
From-SVN: r276177
2019-09-27 10:47:21 +02:00
|
|
|
/* Try to fold a call to the built-in function with subcode FCODE. The
|
|
|
|
function is passed the N_ARGS arguments in ARGS and it returns a value
|
|
|
|
of type TYPE. Return the new expression on success and NULL_TREE on
|
|
|
|
failure. */
|
2013-04-25 14:47:18 +02:00
|
|
|
tree
|
[AArch64] Split built-in function codes into major and minor codes
It was easier to add the SVE ACLE support without enumerating every
function at build time. This in turn meant that it was easier if the
SVE builtins occupied a distinct numberspace from the existing AArch64
ones, which *are* enumerated at build time. This patch therefore
divides the built-in functions codes into "major" and "minor" codes.
At present the major code is just "general", but the SVE patch will add
"SVE" as well.
Also, it was convenient to put the SVE ACLE support in its own file,
so the patch makes aarch64.c provide the frontline target hooks directly,
forwarding to the other files for the real work.
The reason for organising the files this way is that aarch64.c needs
to define the target hook macros whatever happens, and having aarch64.c
macros forward to aarch64-builtins.c functions and aarch64-bulitins.c
functions forward to the SVE file seemed a bit indirect. Doing things
the way the patch does them puts aarch64-builtins.c and the SVE code on
more of an equal footing.
The aarch64_(general_)gimple_fold_builtin change is mostly just
reindentation.
2019-09-27 Richard Sandiford <richard.sandiford@arm.com>
gcc/
* config/aarch64/aarch64-protos.h (aarch64_builtin_class): New enum.
(AARCH64_BUILTIN_SHIFT, AARCH64_BUILTIN_CLASS): New constants.
(aarch64_gimple_fold_builtin, aarch64_mangle_builtin_type)
(aarch64_fold_builtin, aarch64_init_builtins, aarch64_expand_builtin):
(aarch64_builtin_decl, aarch64_builtin_rsqrt): Delete.
(aarch64_general_mangle_builtin_type, aarch64_general_init_builtins):
(aarch64_general_fold_builtin, aarch64_general_gimple_fold_builtin):
(aarch64_general_expand_builtin, aarch64_general_builtin_decl):
(aarch64_general_builtin_rsqrt): Declare.
* config/aarch64/aarch64-builtins.c (aarch64_general_add_builtin):
New function.
(aarch64_mangle_builtin_type): Rename to...
(aarch64_general_mangle_builtin_type): ...this.
(aarch64_init_fcmla_laneq_builtins, aarch64_init_simd_builtins)
(aarch64_init_crc32_builtins, aarch64_init_builtin_rsqrt)
(aarch64_init_pauth_hint_builtins, aarch64_init_tme_builtins): Use
aarch64_general_add_builtin instead of add_builtin_function.
(aarch64_init_builtins): Rename to...
(aarch64_general_init_builtins): ...this. Use
aarch64_general_add_builtin instead of add_builtin_function.
(aarch64_builtin_decl): Rename to...
(aarch64_general_builtin_decl): ...this and remove the unused
arguments.
(aarch64_expand_builtin): Rename to...
(aarch64_general_expand_builtin): ...this and remove the unused
arguments.
(aarch64_builtin_rsqrt): Rename to...
(aarch64_general_builtin_rsqrt): ...this.
(aarch64_fold_builtin): Rename to...
(aarch64_general_fold_builtin): ...this. Take the function subcode
and return type as arguments. Remove the "ignored" argument.
(aarch64_gimple_fold_builtin): Rename to...
(aarch64_general_gimple_fold_builtin): ...this. Take the function
subcode and gcall as arguments, and return the new function call.
* config/aarch64/aarch64.c (aarch64_init_builtins)
(aarch64_fold_builtin, aarch64_gimple_fold_builtin)
(aarch64_expand_builtin, aarch64_builtin_decl): New functions.
(aarch64_builtin_reciprocal): Call aarch64_general_builtin_rsqrt
instead of aarch64_builtin_rsqrt.
(aarch64_mangle_type): Call aarch64_general_mangle_builtin_type
instead of aarch64_mangle_builtin_type.
From-SVN: r276177
2019-09-27 10:47:21 +02:00
|
|
|
aarch64_general_fold_builtin (unsigned int fcode, tree type,
|
|
|
|
unsigned int n_args ATTRIBUTE_UNUSED, tree *args)
|
2013-04-25 14:47:18 +02:00
|
|
|
{
|
|
|
|
switch (fcode)
|
|
|
|
{
|
2020-07-17 11:00:37 +02:00
|
|
|
BUILTIN_VDQF (UNOP, abs, 2, ALL)
|
2013-04-25 14:47:18 +02:00
|
|
|
return fold_build1 (ABS_EXPR, type, args[0]);
|
2020-07-17 11:00:37 +02:00
|
|
|
VAR1 (UNOP, floatv2si, 2, ALL, v2sf)
|
|
|
|
VAR1 (UNOP, floatv4si, 2, ALL, v4sf)
|
|
|
|
VAR1 (UNOP, floatv2di, 2, ALL, v2df)
|
2013-04-29 12:54:32 +02:00
|
|
|
return fold_build1 (FLOAT_EXPR, type, args[0]);
|
2021-09-02 09:08:22 +02:00
|
|
|
case AARCH64_SIMD_BUILTIN_LANE_CHECK:
|
|
|
|
gcc_assert (n_args == 3);
|
|
|
|
if (aarch64_fold_builtin_lane_check (args[0], args[1], args[2]))
|
|
|
|
return void_node;
|
|
|
|
break;
|
2013-04-25 14:47:18 +02:00
|
|
|
default:
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
|
|
|
return NULL_TREE;
|
|
|
|
}
|
|
|
|
|
2021-10-20 14:19:10 +02:00
|
|
|
enum aarch64_simd_type
|
|
|
|
get_mem_type_for_load_store (unsigned int fcode)
|
|
|
|
{
|
|
|
|
switch (fcode)
|
|
|
|
{
|
2021-11-10 11:49:19 +01:00
|
|
|
VAR1 (LOAD1, ld1, 0, LOAD, v8qi)
|
|
|
|
VAR1 (STORE1, st1, 0, STORE, v8qi)
|
2021-10-20 14:19:10 +02:00
|
|
|
return Int8x8_t;
|
2021-11-10 11:49:19 +01:00
|
|
|
VAR1 (LOAD1, ld1, 0, LOAD, v16qi)
|
|
|
|
VAR1 (STORE1, st1, 0, STORE, v16qi)
|
2021-10-20 14:19:10 +02:00
|
|
|
return Int8x16_t;
|
2021-11-10 11:49:19 +01:00
|
|
|
VAR1 (LOAD1, ld1, 0, LOAD, v4hi)
|
|
|
|
VAR1 (STORE1, st1, 0, STORE, v4hi)
|
2021-10-20 14:19:10 +02:00
|
|
|
return Int16x4_t;
|
2021-11-10 11:49:19 +01:00
|
|
|
VAR1 (LOAD1, ld1, 0, LOAD, v8hi)
|
|
|
|
VAR1 (STORE1, st1, 0, STORE, v8hi)
|
2021-10-20 14:19:10 +02:00
|
|
|
return Int16x8_t;
|
2021-11-10 11:49:19 +01:00
|
|
|
VAR1 (LOAD1, ld1, 0, LOAD, v2si)
|
|
|
|
VAR1 (STORE1, st1, 0, STORE, v2si)
|
2021-10-20 14:19:10 +02:00
|
|
|
return Int32x2_t;
|
2021-11-10 11:49:19 +01:00
|
|
|
VAR1 (LOAD1, ld1, 0, LOAD, v4si)
|
|
|
|
VAR1 (STORE1, st1, 0, STORE, v4si)
|
2021-10-20 14:19:10 +02:00
|
|
|
return Int32x4_t;
|
2021-11-10 11:49:19 +01:00
|
|
|
VAR1 (LOAD1, ld1, 0, LOAD, v2di)
|
|
|
|
VAR1 (STORE1, st1, 0, STORE, v2di)
|
2021-10-20 14:19:10 +02:00
|
|
|
return Int64x2_t;
|
2021-11-10 11:49:19 +01:00
|
|
|
VAR1 (LOAD1_U, ld1, 0, LOAD, v8qi)
|
|
|
|
VAR1 (STORE1_U, st1, 0, STORE, v8qi)
|
|
|
|
return Uint8x8_t;
|
|
|
|
VAR1 (LOAD1_U, ld1, 0, LOAD, v16qi)
|
|
|
|
VAR1 (STORE1_U, st1, 0, STORE, v16qi)
|
|
|
|
return Uint8x16_t;
|
|
|
|
VAR1 (LOAD1_U, ld1, 0, LOAD, v4hi)
|
|
|
|
VAR1 (STORE1_U, st1, 0, STORE, v4hi)
|
|
|
|
return Uint16x4_t;
|
|
|
|
VAR1 (LOAD1_U, ld1, 0, LOAD, v8hi)
|
|
|
|
VAR1 (STORE1_U, st1, 0, STORE, v8hi)
|
|
|
|
return Uint16x8_t;
|
|
|
|
VAR1 (LOAD1_U, ld1, 0, LOAD, v2si)
|
|
|
|
VAR1 (STORE1_U, st1, 0, STORE, v2si)
|
|
|
|
return Uint32x2_t;
|
|
|
|
VAR1 (LOAD1_U, ld1, 0, LOAD, v4si)
|
|
|
|
VAR1 (STORE1_U, st1, 0, STORE, v4si)
|
|
|
|
return Uint32x4_t;
|
|
|
|
VAR1 (LOAD1_U, ld1, 0, LOAD, v2di)
|
|
|
|
VAR1 (STORE1_U, st1, 0, STORE, v2di)
|
|
|
|
return Uint64x2_t;
|
|
|
|
VAR1 (LOAD1_P, ld1, 0, LOAD, v8qi)
|
|
|
|
VAR1 (STORE1_P, st1, 0, STORE, v8qi)
|
|
|
|
return Poly8x8_t;
|
|
|
|
VAR1 (LOAD1_P, ld1, 0, LOAD, v16qi)
|
|
|
|
VAR1 (STORE1_P, st1, 0, STORE, v16qi)
|
|
|
|
return Poly8x16_t;
|
|
|
|
VAR1 (LOAD1_P, ld1, 0, LOAD, v4hi)
|
|
|
|
VAR1 (STORE1_P, st1, 0, STORE, v4hi)
|
|
|
|
return Poly16x4_t;
|
|
|
|
VAR1 (LOAD1_P, ld1, 0, LOAD, v8hi)
|
|
|
|
VAR1 (STORE1_P, st1, 0, STORE, v8hi)
|
|
|
|
return Poly16x8_t;
|
|
|
|
VAR1 (LOAD1_P, ld1, 0, LOAD, v2di)
|
|
|
|
VAR1 (STORE1_P, st1, 0, STORE, v2di)
|
|
|
|
return Poly64x2_t;
|
|
|
|
VAR1 (LOAD1, ld1, 0, LOAD, v4hf)
|
|
|
|
VAR1 (STORE1, st1, 0, STORE, v4hf)
|
2021-10-20 14:19:10 +02:00
|
|
|
return Float16x4_t;
|
2021-11-10 11:49:19 +01:00
|
|
|
VAR1 (LOAD1, ld1, 0, LOAD, v8hf)
|
|
|
|
VAR1 (STORE1, st1, 0, STORE, v8hf)
|
2021-10-20 14:19:10 +02:00
|
|
|
return Float16x8_t;
|
2021-11-10 11:49:19 +01:00
|
|
|
VAR1 (LOAD1, ld1, 0, LOAD, v4bf)
|
|
|
|
VAR1 (STORE1, st1, 0, STORE, v4bf)
|
2021-10-20 14:19:10 +02:00
|
|
|
return Bfloat16x4_t;
|
2021-11-10 11:49:19 +01:00
|
|
|
VAR1 (LOAD1, ld1, 0, LOAD, v8bf)
|
|
|
|
VAR1 (STORE1, st1, 0, STORE, v8bf)
|
2021-10-20 14:19:10 +02:00
|
|
|
return Bfloat16x8_t;
|
2021-11-10 11:49:19 +01:00
|
|
|
VAR1 (LOAD1, ld1, 0, LOAD, v2sf)
|
|
|
|
VAR1 (STORE1, st1, 0, STORE, v2sf)
|
2021-10-20 14:19:10 +02:00
|
|
|
return Float32x2_t;
|
2021-11-10 11:49:19 +01:00
|
|
|
VAR1 (LOAD1, ld1, 0, LOAD, v4sf)
|
|
|
|
VAR1 (STORE1, st1, 0, STORE, v4sf)
|
2021-10-20 14:19:10 +02:00
|
|
|
return Float32x4_t;
|
2021-11-10 11:49:19 +01:00
|
|
|
VAR1 (LOAD1, ld1, 0, LOAD, v2df)
|
|
|
|
VAR1 (STORE1, st1, 0, STORE, v2df)
|
2021-10-20 14:19:10 +02:00
|
|
|
return Float64x2_t;
|
|
|
|
default:
|
|
|
|
gcc_unreachable ();
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
[AArch64] Split built-in function codes into major and minor codes
It was easier to add the SVE ACLE support without enumerating every
function at build time. This in turn meant that it was easier if the
SVE builtins occupied a distinct numberspace from the existing AArch64
ones, which *are* enumerated at build time. This patch therefore
divides the built-in functions codes into "major" and "minor" codes.
At present the major code is just "general", but the SVE patch will add
"SVE" as well.
Also, it was convenient to put the SVE ACLE support in its own file,
so the patch makes aarch64.c provide the frontline target hooks directly,
forwarding to the other files for the real work.
The reason for organising the files this way is that aarch64.c needs
to define the target hook macros whatever happens, and having aarch64.c
macros forward to aarch64-builtins.c functions and aarch64-bulitins.c
functions forward to the SVE file seemed a bit indirect. Doing things
the way the patch does them puts aarch64-builtins.c and the SVE code on
more of an equal footing.
The aarch64_(general_)gimple_fold_builtin change is mostly just
reindentation.
2019-09-27 Richard Sandiford <richard.sandiford@arm.com>
gcc/
* config/aarch64/aarch64-protos.h (aarch64_builtin_class): New enum.
(AARCH64_BUILTIN_SHIFT, AARCH64_BUILTIN_CLASS): New constants.
(aarch64_gimple_fold_builtin, aarch64_mangle_builtin_type)
(aarch64_fold_builtin, aarch64_init_builtins, aarch64_expand_builtin):
(aarch64_builtin_decl, aarch64_builtin_rsqrt): Delete.
(aarch64_general_mangle_builtin_type, aarch64_general_init_builtins):
(aarch64_general_fold_builtin, aarch64_general_gimple_fold_builtin):
(aarch64_general_expand_builtin, aarch64_general_builtin_decl):
(aarch64_general_builtin_rsqrt): Declare.
* config/aarch64/aarch64-builtins.c (aarch64_general_add_builtin):
New function.
(aarch64_mangle_builtin_type): Rename to...
(aarch64_general_mangle_builtin_type): ...this.
(aarch64_init_fcmla_laneq_builtins, aarch64_init_simd_builtins)
(aarch64_init_crc32_builtins, aarch64_init_builtin_rsqrt)
(aarch64_init_pauth_hint_builtins, aarch64_init_tme_builtins): Use
aarch64_general_add_builtin instead of add_builtin_function.
(aarch64_init_builtins): Rename to...
(aarch64_general_init_builtins): ...this. Use
aarch64_general_add_builtin instead of add_builtin_function.
(aarch64_builtin_decl): Rename to...
(aarch64_general_builtin_decl): ...this and remove the unused
arguments.
(aarch64_expand_builtin): Rename to...
(aarch64_general_expand_builtin): ...this and remove the unused
arguments.
(aarch64_builtin_rsqrt): Rename to...
(aarch64_general_builtin_rsqrt): ...this.
(aarch64_fold_builtin): Rename to...
(aarch64_general_fold_builtin): ...this. Take the function subcode
and return type as arguments. Remove the "ignored" argument.
(aarch64_gimple_fold_builtin): Rename to...
(aarch64_general_gimple_fold_builtin): ...this. Take the function
subcode and gcall as arguments, and return the new function call.
* config/aarch64/aarch64.c (aarch64_init_builtins)
(aarch64_fold_builtin, aarch64_gimple_fold_builtin)
(aarch64_expand_builtin, aarch64_builtin_decl): New functions.
(aarch64_builtin_reciprocal): Call aarch64_general_builtin_rsqrt
instead of aarch64_builtin_rsqrt.
(aarch64_mangle_type): Call aarch64_general_mangle_builtin_type
instead of aarch64_mangle_builtin_type.
From-SVN: r276177
2019-09-27 10:47:21 +02:00
|
|
|
/* Try to fold STMT, given that it's a call to the built-in function with
|
|
|
|
subcode FCODE. Return the new statement on success and null on
|
|
|
|
failure. */
|
|
|
|
gimple *
|
2021-10-20 14:19:10 +02:00
|
|
|
aarch64_general_gimple_fold_builtin (unsigned int fcode, gcall *stmt,
|
2021-11-10 13:58:10 +01:00
|
|
|
gimple_stmt_iterator *gsi ATTRIBUTE_UNUSED)
|
2013-04-25 14:44:25 +02:00
|
|
|
{
|
2015-09-20 02:52:59 +02:00
|
|
|
gimple *new_stmt = NULL;
|
[AArch64] Split built-in function codes into major and minor codes
It was easier to add the SVE ACLE support without enumerating every
function at build time. This in turn meant that it was easier if the
SVE builtins occupied a distinct numberspace from the existing AArch64
ones, which *are* enumerated at build time. This patch therefore
divides the built-in functions codes into "major" and "minor" codes.
At present the major code is just "general", but the SVE patch will add
"SVE" as well.
Also, it was convenient to put the SVE ACLE support in its own file,
so the patch makes aarch64.c provide the frontline target hooks directly,
forwarding to the other files for the real work.
The reason for organising the files this way is that aarch64.c needs
to define the target hook macros whatever happens, and having aarch64.c
macros forward to aarch64-builtins.c functions and aarch64-bulitins.c
functions forward to the SVE file seemed a bit indirect. Doing things
the way the patch does them puts aarch64-builtins.c and the SVE code on
more of an equal footing.
The aarch64_(general_)gimple_fold_builtin change is mostly just
reindentation.
2019-09-27 Richard Sandiford <richard.sandiford@arm.com>
gcc/
* config/aarch64/aarch64-protos.h (aarch64_builtin_class): New enum.
(AARCH64_BUILTIN_SHIFT, AARCH64_BUILTIN_CLASS): New constants.
(aarch64_gimple_fold_builtin, aarch64_mangle_builtin_type)
(aarch64_fold_builtin, aarch64_init_builtins, aarch64_expand_builtin):
(aarch64_builtin_decl, aarch64_builtin_rsqrt): Delete.
(aarch64_general_mangle_builtin_type, aarch64_general_init_builtins):
(aarch64_general_fold_builtin, aarch64_general_gimple_fold_builtin):
(aarch64_general_expand_builtin, aarch64_general_builtin_decl):
(aarch64_general_builtin_rsqrt): Declare.
* config/aarch64/aarch64-builtins.c (aarch64_general_add_builtin):
New function.
(aarch64_mangle_builtin_type): Rename to...
(aarch64_general_mangle_builtin_type): ...this.
(aarch64_init_fcmla_laneq_builtins, aarch64_init_simd_builtins)
(aarch64_init_crc32_builtins, aarch64_init_builtin_rsqrt)
(aarch64_init_pauth_hint_builtins, aarch64_init_tme_builtins): Use
aarch64_general_add_builtin instead of add_builtin_function.
(aarch64_init_builtins): Rename to...
(aarch64_general_init_builtins): ...this. Use
aarch64_general_add_builtin instead of add_builtin_function.
(aarch64_builtin_decl): Rename to...
(aarch64_general_builtin_decl): ...this and remove the unused
arguments.
(aarch64_expand_builtin): Rename to...
(aarch64_general_expand_builtin): ...this and remove the unused
arguments.
(aarch64_builtin_rsqrt): Rename to...
(aarch64_general_builtin_rsqrt): ...this.
(aarch64_fold_builtin): Rename to...
(aarch64_general_fold_builtin): ...this. Take the function subcode
and return type as arguments. Remove the "ignored" argument.
(aarch64_gimple_fold_builtin): Rename to...
(aarch64_general_gimple_fold_builtin): ...this. Take the function
subcode and gcall as arguments, and return the new function call.
* config/aarch64/aarch64.c (aarch64_init_builtins)
(aarch64_fold_builtin, aarch64_gimple_fold_builtin)
(aarch64_expand_builtin, aarch64_builtin_decl): New functions.
(aarch64_builtin_reciprocal): Call aarch64_general_builtin_rsqrt
instead of aarch64_builtin_rsqrt.
(aarch64_mangle_type): Call aarch64_general_mangle_builtin_type
instead of aarch64_mangle_builtin_type.
From-SVN: r276177
2019-09-27 10:47:21 +02:00
|
|
|
unsigned nargs = gimple_call_num_args (stmt);
|
|
|
|
tree *args = (nargs > 0
|
|
|
|
? gimple_call_arg_ptr (stmt, 0)
|
|
|
|
: &error_mark_node);
|
|
|
|
|
|
|
|
/* We use gimple's IFN_REDUC_(PLUS|MIN|MAX)s for float, signed int
|
|
|
|
and unsigned int; it will distinguish according to the types of
|
|
|
|
the arguments to the __builtin. */
|
|
|
|
switch (fcode)
|
2013-04-25 14:44:25 +02:00
|
|
|
{
|
2020-07-17 11:00:37 +02:00
|
|
|
BUILTIN_VALL (UNOP, reduc_plus_scal_, 10, ALL)
|
[AArch64] Split built-in function codes into major and minor codes
It was easier to add the SVE ACLE support without enumerating every
function at build time. This in turn meant that it was easier if the
SVE builtins occupied a distinct numberspace from the existing AArch64
ones, which *are* enumerated at build time. This patch therefore
divides the built-in functions codes into "major" and "minor" codes.
At present the major code is just "general", but the SVE patch will add
"SVE" as well.
Also, it was convenient to put the SVE ACLE support in its own file,
so the patch makes aarch64.c provide the frontline target hooks directly,
forwarding to the other files for the real work.
The reason for organising the files this way is that aarch64.c needs
to define the target hook macros whatever happens, and having aarch64.c
macros forward to aarch64-builtins.c functions and aarch64-bulitins.c
functions forward to the SVE file seemed a bit indirect. Doing things
the way the patch does them puts aarch64-builtins.c and the SVE code on
more of an equal footing.
The aarch64_(general_)gimple_fold_builtin change is mostly just
reindentation.
2019-09-27 Richard Sandiford <richard.sandiford@arm.com>
gcc/
* config/aarch64/aarch64-protos.h (aarch64_builtin_class): New enum.
(AARCH64_BUILTIN_SHIFT, AARCH64_BUILTIN_CLASS): New constants.
(aarch64_gimple_fold_builtin, aarch64_mangle_builtin_type)
(aarch64_fold_builtin, aarch64_init_builtins, aarch64_expand_builtin):
(aarch64_builtin_decl, aarch64_builtin_rsqrt): Delete.
(aarch64_general_mangle_builtin_type, aarch64_general_init_builtins):
(aarch64_general_fold_builtin, aarch64_general_gimple_fold_builtin):
(aarch64_general_expand_builtin, aarch64_general_builtin_decl):
(aarch64_general_builtin_rsqrt): Declare.
* config/aarch64/aarch64-builtins.c (aarch64_general_add_builtin):
New function.
(aarch64_mangle_builtin_type): Rename to...
(aarch64_general_mangle_builtin_type): ...this.
(aarch64_init_fcmla_laneq_builtins, aarch64_init_simd_builtins)
(aarch64_init_crc32_builtins, aarch64_init_builtin_rsqrt)
(aarch64_init_pauth_hint_builtins, aarch64_init_tme_builtins): Use
aarch64_general_add_builtin instead of add_builtin_function.
(aarch64_init_builtins): Rename to...
(aarch64_general_init_builtins): ...this. Use
aarch64_general_add_builtin instead of add_builtin_function.
(aarch64_builtin_decl): Rename to...
(aarch64_general_builtin_decl): ...this and remove the unused
arguments.
(aarch64_expand_builtin): Rename to...
(aarch64_general_expand_builtin): ...this and remove the unused
arguments.
(aarch64_builtin_rsqrt): Rename to...
(aarch64_general_builtin_rsqrt): ...this.
(aarch64_fold_builtin): Rename to...
(aarch64_general_fold_builtin): ...this. Take the function subcode
and return type as arguments. Remove the "ignored" argument.
(aarch64_gimple_fold_builtin): Rename to...
(aarch64_general_gimple_fold_builtin): ...this. Take the function
subcode and gcall as arguments, and return the new function call.
* config/aarch64/aarch64.c (aarch64_init_builtins)
(aarch64_fold_builtin, aarch64_gimple_fold_builtin)
(aarch64_expand_builtin, aarch64_builtin_decl): New functions.
(aarch64_builtin_reciprocal): Call aarch64_general_builtin_rsqrt
instead of aarch64_builtin_rsqrt.
(aarch64_mangle_type): Call aarch64_general_mangle_builtin_type
instead of aarch64_mangle_builtin_type.
From-SVN: r276177
2019-09-27 10:47:21 +02:00
|
|
|
new_stmt = gimple_build_call_internal (IFN_REDUC_PLUS,
|
|
|
|
1, args[0]);
|
|
|
|
gimple_call_set_lhs (new_stmt, gimple_call_lhs (stmt));
|
|
|
|
break;
|
2021-10-20 14:19:10 +02:00
|
|
|
|
2022-01-10 08:39:31 +01:00
|
|
|
/* Lower sqrt builtins to gimple/internal function sqrt. */
|
|
|
|
BUILTIN_VHSDF_DF (UNOP, sqrt, 2, FP)
|
|
|
|
new_stmt = gimple_build_call_internal (IFN_SQRT,
|
|
|
|
1, args[0]);
|
|
|
|
gimple_call_set_lhs (new_stmt, gimple_call_lhs (stmt));
|
|
|
|
break;
|
|
|
|
|
2021-10-20 14:19:10 +02:00
|
|
|
/*lower store and load neon builtins to gimple. */
|
|
|
|
BUILTIN_VALL_F16 (LOAD1, ld1, 0, LOAD)
|
2021-11-10 11:49:19 +01:00
|
|
|
BUILTIN_VDQ_I (LOAD1_U, ld1, 0, LOAD)
|
|
|
|
BUILTIN_VALLP_NO_DI (LOAD1_P, ld1, 0, LOAD)
|
2021-10-20 14:19:10 +02:00
|
|
|
if (!BYTES_BIG_ENDIAN)
|
|
|
|
{
|
|
|
|
enum aarch64_simd_type mem_type
|
|
|
|
= get_mem_type_for_load_store(fcode);
|
|
|
|
aarch64_simd_type_info simd_type
|
|
|
|
= aarch64_simd_types[mem_type];
|
2021-11-10 10:52:49 +01:00
|
|
|
tree elt_ptr_type = build_pointer_type_for_mode (simd_type.eltype,
|
|
|
|
VOIDmode, true);
|
2021-10-20 14:19:10 +02:00
|
|
|
tree zero = build_zero_cst (elt_ptr_type);
|
2021-11-10 10:52:49 +01:00
|
|
|
/* Use element type alignment. */
|
|
|
|
tree access_type
|
|
|
|
= build_aligned_type (simd_type.itype,
|
|
|
|
TYPE_ALIGN (simd_type.eltype));
|
2021-10-20 14:19:10 +02:00
|
|
|
new_stmt
|
|
|
|
= gimple_build_assign (gimple_get_lhs (stmt),
|
|
|
|
fold_build2 (MEM_REF,
|
2021-11-10 10:52:49 +01:00
|
|
|
access_type,
|
|
|
|
args[0], zero));
|
2021-10-20 14:19:10 +02:00
|
|
|
}
|
|
|
|
break;
|
|
|
|
|
|
|
|
BUILTIN_VALL_F16 (STORE1, st1, 0, STORE)
|
2021-11-10 11:49:19 +01:00
|
|
|
BUILTIN_VDQ_I (STORE1_U, st1, 0, STORE)
|
|
|
|
BUILTIN_VALLP_NO_DI (STORE1_P, st1, 0, STORE)
|
2021-10-20 14:19:10 +02:00
|
|
|
if (!BYTES_BIG_ENDIAN)
|
|
|
|
{
|
|
|
|
enum aarch64_simd_type mem_type
|
|
|
|
= get_mem_type_for_load_store(fcode);
|
|
|
|
aarch64_simd_type_info simd_type
|
|
|
|
= aarch64_simd_types[mem_type];
|
2021-11-10 10:52:49 +01:00
|
|
|
tree elt_ptr_type = build_pointer_type_for_mode (simd_type.eltype,
|
|
|
|
VOIDmode, true);
|
2021-10-20 14:19:10 +02:00
|
|
|
tree zero = build_zero_cst (elt_ptr_type);
|
2021-11-10 10:52:49 +01:00
|
|
|
/* Use element type alignment. */
|
|
|
|
tree access_type
|
|
|
|
= build_aligned_type (simd_type.itype,
|
|
|
|
TYPE_ALIGN (simd_type.eltype));
|
2021-10-20 14:19:10 +02:00
|
|
|
new_stmt
|
2021-11-10 10:52:49 +01:00
|
|
|
= gimple_build_assign (fold_build2 (MEM_REF, access_type,
|
|
|
|
args[0], zero),
|
|
|
|
args[1]);
|
2021-10-20 14:19:10 +02:00
|
|
|
}
|
|
|
|
break;
|
|
|
|
|
2020-07-17 11:00:37 +02:00
|
|
|
BUILTIN_VDQIF (UNOP, reduc_smax_scal_, 10, ALL)
|
|
|
|
BUILTIN_VDQ_BHSI (UNOPU, reduc_umax_scal_, 10, ALL)
|
[AArch64] Split built-in function codes into major and minor codes
It was easier to add the SVE ACLE support without enumerating every
function at build time. This in turn meant that it was easier if the
SVE builtins occupied a distinct numberspace from the existing AArch64
ones, which *are* enumerated at build time. This patch therefore
divides the built-in functions codes into "major" and "minor" codes.
At present the major code is just "general", but the SVE patch will add
"SVE" as well.
Also, it was convenient to put the SVE ACLE support in its own file,
so the patch makes aarch64.c provide the frontline target hooks directly,
forwarding to the other files for the real work.
The reason for organising the files this way is that aarch64.c needs
to define the target hook macros whatever happens, and having aarch64.c
macros forward to aarch64-builtins.c functions and aarch64-bulitins.c
functions forward to the SVE file seemed a bit indirect. Doing things
the way the patch does them puts aarch64-builtins.c and the SVE code on
more of an equal footing.
The aarch64_(general_)gimple_fold_builtin change is mostly just
reindentation.
2019-09-27 Richard Sandiford <richard.sandiford@arm.com>
gcc/
* config/aarch64/aarch64-protos.h (aarch64_builtin_class): New enum.
(AARCH64_BUILTIN_SHIFT, AARCH64_BUILTIN_CLASS): New constants.
(aarch64_gimple_fold_builtin, aarch64_mangle_builtin_type)
(aarch64_fold_builtin, aarch64_init_builtins, aarch64_expand_builtin):
(aarch64_builtin_decl, aarch64_builtin_rsqrt): Delete.
(aarch64_general_mangle_builtin_type, aarch64_general_init_builtins):
(aarch64_general_fold_builtin, aarch64_general_gimple_fold_builtin):
(aarch64_general_expand_builtin, aarch64_general_builtin_decl):
(aarch64_general_builtin_rsqrt): Declare.
* config/aarch64/aarch64-builtins.c (aarch64_general_add_builtin):
New function.
(aarch64_mangle_builtin_type): Rename to...
(aarch64_general_mangle_builtin_type): ...this.
(aarch64_init_fcmla_laneq_builtins, aarch64_init_simd_builtins)
(aarch64_init_crc32_builtins, aarch64_init_builtin_rsqrt)
(aarch64_init_pauth_hint_builtins, aarch64_init_tme_builtins): Use
aarch64_general_add_builtin instead of add_builtin_function.
(aarch64_init_builtins): Rename to...
(aarch64_general_init_builtins): ...this. Use
aarch64_general_add_builtin instead of add_builtin_function.
(aarch64_builtin_decl): Rename to...
(aarch64_general_builtin_decl): ...this and remove the unused
arguments.
(aarch64_expand_builtin): Rename to...
(aarch64_general_expand_builtin): ...this and remove the unused
arguments.
(aarch64_builtin_rsqrt): Rename to...
(aarch64_general_builtin_rsqrt): ...this.
(aarch64_fold_builtin): Rename to...
(aarch64_general_fold_builtin): ...this. Take the function subcode
and return type as arguments. Remove the "ignored" argument.
(aarch64_gimple_fold_builtin): Rename to...
(aarch64_general_gimple_fold_builtin): ...this. Take the function
subcode and gcall as arguments, and return the new function call.
* config/aarch64/aarch64.c (aarch64_init_builtins)
(aarch64_fold_builtin, aarch64_gimple_fold_builtin)
(aarch64_expand_builtin, aarch64_builtin_decl): New functions.
(aarch64_builtin_reciprocal): Call aarch64_general_builtin_rsqrt
instead of aarch64_builtin_rsqrt.
(aarch64_mangle_type): Call aarch64_general_mangle_builtin_type
instead of aarch64_mangle_builtin_type.
From-SVN: r276177
2019-09-27 10:47:21 +02:00
|
|
|
new_stmt = gimple_build_call_internal (IFN_REDUC_MAX,
|
|
|
|
1, args[0]);
|
|
|
|
gimple_call_set_lhs (new_stmt, gimple_call_lhs (stmt));
|
|
|
|
break;
|
2020-07-17 11:00:37 +02:00
|
|
|
BUILTIN_VDQIF (UNOP, reduc_smin_scal_, 10, ALL)
|
|
|
|
BUILTIN_VDQ_BHSI (UNOPU, reduc_umin_scal_, 10, ALL)
|
[AArch64] Split built-in function codes into major and minor codes
It was easier to add the SVE ACLE support without enumerating every
function at build time. This in turn meant that it was easier if the
SVE builtins occupied a distinct numberspace from the existing AArch64
ones, which *are* enumerated at build time. This patch therefore
divides the built-in functions codes into "major" and "minor" codes.
At present the major code is just "general", but the SVE patch will add
"SVE" as well.
Also, it was convenient to put the SVE ACLE support in its own file,
so the patch makes aarch64.c provide the frontline target hooks directly,
forwarding to the other files for the real work.
The reason for organising the files this way is that aarch64.c needs
to define the target hook macros whatever happens, and having aarch64.c
macros forward to aarch64-builtins.c functions and aarch64-bulitins.c
functions forward to the SVE file seemed a bit indirect. Doing things
the way the patch does them puts aarch64-builtins.c and the SVE code on
more of an equal footing.
The aarch64_(general_)gimple_fold_builtin change is mostly just
reindentation.
2019-09-27 Richard Sandiford <richard.sandiford@arm.com>
gcc/
* config/aarch64/aarch64-protos.h (aarch64_builtin_class): New enum.
(AARCH64_BUILTIN_SHIFT, AARCH64_BUILTIN_CLASS): New constants.
(aarch64_gimple_fold_builtin, aarch64_mangle_builtin_type)
(aarch64_fold_builtin, aarch64_init_builtins, aarch64_expand_builtin):
(aarch64_builtin_decl, aarch64_builtin_rsqrt): Delete.
(aarch64_general_mangle_builtin_type, aarch64_general_init_builtins):
(aarch64_general_fold_builtin, aarch64_general_gimple_fold_builtin):
(aarch64_general_expand_builtin, aarch64_general_builtin_decl):
(aarch64_general_builtin_rsqrt): Declare.
* config/aarch64/aarch64-builtins.c (aarch64_general_add_builtin):
New function.
(aarch64_mangle_builtin_type): Rename to...
(aarch64_general_mangle_builtin_type): ...this.
(aarch64_init_fcmla_laneq_builtins, aarch64_init_simd_builtins)
(aarch64_init_crc32_builtins, aarch64_init_builtin_rsqrt)
(aarch64_init_pauth_hint_builtins, aarch64_init_tme_builtins): Use
aarch64_general_add_builtin instead of add_builtin_function.
(aarch64_init_builtins): Rename to...
(aarch64_general_init_builtins): ...this. Use
aarch64_general_add_builtin instead of add_builtin_function.
(aarch64_builtin_decl): Rename to...
(aarch64_general_builtin_decl): ...this and remove the unused
arguments.
(aarch64_expand_builtin): Rename to...
(aarch64_general_expand_builtin): ...this and remove the unused
arguments.
(aarch64_builtin_rsqrt): Rename to...
(aarch64_general_builtin_rsqrt): ...this.
(aarch64_fold_builtin): Rename to...
(aarch64_general_fold_builtin): ...this. Take the function subcode
and return type as arguments. Remove the "ignored" argument.
(aarch64_gimple_fold_builtin): Rename to...
(aarch64_general_gimple_fold_builtin): ...this. Take the function
subcode and gcall as arguments, and return the new function call.
* config/aarch64/aarch64.c (aarch64_init_builtins)
(aarch64_fold_builtin, aarch64_gimple_fold_builtin)
(aarch64_expand_builtin, aarch64_builtin_decl): New functions.
(aarch64_builtin_reciprocal): Call aarch64_general_builtin_rsqrt
instead of aarch64_builtin_rsqrt.
(aarch64_mangle_type): Call aarch64_general_mangle_builtin_type
instead of aarch64_mangle_builtin_type.
From-SVN: r276177
2019-09-27 10:47:21 +02:00
|
|
|
new_stmt = gimple_build_call_internal (IFN_REDUC_MIN,
|
|
|
|
1, args[0]);
|
|
|
|
gimple_call_set_lhs (new_stmt, gimple_call_lhs (stmt));
|
|
|
|
break;
|
AArch64: Lower intrinsics shift to GIMPLE when possible.
This lowers shifts to GIMPLE when the C interpretations of the shift operations
matches that of AArch64.
In C shifting right by BITSIZE is undefined, but the behavior is defined in
AArch64. Additionally negative shifts lefts are undefined for the register
variant of the instruction (SSHL, USHL) as being right shifts.
Since we have a right shift by immediate I rewrite those cases into right shifts
So:
int64x1_t foo3 (int64x1_t a)
{
return vshl_s64 (a, vdup_n_s64(-6));
}
produces:
foo3:
sshr d0, d0, 6
ret
instead of:
foo3:
mov x0, -6
fmov d1, x0
sshl d0, d0, d1
ret
This behavior isn't specifically mentioned for a left shift by immediate, but I
believe that only the case because we do have a right shift by immediate but not
a right shift by register. As such I do the same for left shift by immediate.
gcc/ChangeLog:
* config/aarch64/aarch64-builtins.c
(aarch64_general_gimple_fold_builtin): Add ashl, sshl, ushl, ashr,
ashr_simd, lshr, lshr_simd.
* config/aarch64/aarch64-simd-builtins.def (lshr): Use USHIFTIMM.
* config/aarch64/arm_neon.h (vshr_n_u8, vshr_n_u16, vshr_n_u32,
vshrq_n_u8, vshrq_n_u16, vshrq_n_u32, vshrq_n_u64): Fix type hack.
gcc/testsuite/ChangeLog:
* gcc.target/aarch64/advsimd-intrinsics/vshl-opt-1.c: New test.
* gcc.target/aarch64/advsimd-intrinsics/vshl-opt-2.c: New test.
* gcc.target/aarch64/advsimd-intrinsics/vshl-opt-3.c: New test.
* gcc.target/aarch64/advsimd-intrinsics/vshl-opt-4.c: New test.
* gcc.target/aarch64/advsimd-intrinsics/vshl-opt-5.c: New test.
* gcc.target/aarch64/advsimd-intrinsics/vshl-opt-6.c: New test.
* gcc.target/aarch64/advsimd-intrinsics/vshl-opt-7.c: New test.
* gcc.target/aarch64/advsimd-intrinsics/vshl-opt-8.c: New test.
* gcc.target/aarch64/signbit-2.c: New test.
2021-11-04 18:36:08 +01:00
|
|
|
BUILTIN_VSDQ_I_DI (BINOP, ashl, 3, NONE)
|
|
|
|
if (TREE_CODE (args[1]) == INTEGER_CST
|
|
|
|
&& wi::ltu_p (wi::to_wide (args[1]), element_precision (args[0])))
|
|
|
|
new_stmt = gimple_build_assign (gimple_call_lhs (stmt),
|
|
|
|
LSHIFT_EXPR, args[0], args[1]);
|
|
|
|
break;
|
|
|
|
BUILTIN_VSDQ_I_DI (BINOP, sshl, 0, NONE)
|
|
|
|
BUILTIN_VSDQ_I_DI (BINOP_UUS, ushl, 0, NONE)
|
|
|
|
{
|
|
|
|
tree cst = args[1];
|
|
|
|
tree ctype = TREE_TYPE (cst);
|
|
|
|
/* Left shifts can be both scalar or vector, e.g. uint64x1_t is
|
|
|
|
treated as a scalar type not a vector one. */
|
|
|
|
if ((cst = uniform_integer_cst_p (cst)) != NULL_TREE)
|
|
|
|
{
|
|
|
|
wide_int wcst = wi::to_wide (cst);
|
|
|
|
tree unit_ty = TREE_TYPE (cst);
|
|
|
|
|
|
|
|
wide_int abs_cst = wi::abs (wcst);
|
|
|
|
if (wi::geu_p (abs_cst, element_precision (args[0])))
|
|
|
|
break;
|
|
|
|
|
|
|
|
if (wi::neg_p (wcst, TYPE_SIGN (ctype)))
|
|
|
|
{
|
|
|
|
tree final_cst;
|
|
|
|
final_cst = wide_int_to_tree (unit_ty, abs_cst);
|
|
|
|
if (TREE_CODE (cst) != INTEGER_CST)
|
|
|
|
final_cst = build_uniform_cst (ctype, final_cst);
|
|
|
|
|
|
|
|
new_stmt = gimple_build_assign (gimple_call_lhs (stmt),
|
|
|
|
RSHIFT_EXPR, args[0],
|
|
|
|
final_cst);
|
|
|
|
}
|
|
|
|
else
|
|
|
|
new_stmt = gimple_build_assign (gimple_call_lhs (stmt),
|
|
|
|
LSHIFT_EXPR, args[0], args[1]);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
break;
|
|
|
|
BUILTIN_VDQ_I (SHIFTIMM, ashr, 3, NONE)
|
|
|
|
VAR1 (SHIFTIMM, ashr_simd, 0, NONE, di)
|
|
|
|
BUILTIN_VDQ_I (USHIFTIMM, lshr, 3, NONE)
|
|
|
|
VAR1 (USHIFTIMM, lshr_simd, 0, NONE, di)
|
|
|
|
if (TREE_CODE (args[1]) == INTEGER_CST
|
|
|
|
&& wi::ltu_p (wi::to_wide (args[1]), element_precision (args[0])))
|
|
|
|
new_stmt = gimple_build_assign (gimple_call_lhs (stmt),
|
|
|
|
RSHIFT_EXPR, args[0], args[1]);
|
|
|
|
break;
|
2020-07-17 11:00:37 +02:00
|
|
|
BUILTIN_GPF (BINOP, fmulx, 0, ALL)
|
2013-04-25 14:44:25 +02:00
|
|
|
{
|
[AArch64] Split built-in function codes into major and minor codes
It was easier to add the SVE ACLE support without enumerating every
function at build time. This in turn meant that it was easier if the
SVE builtins occupied a distinct numberspace from the existing AArch64
ones, which *are* enumerated at build time. This patch therefore
divides the built-in functions codes into "major" and "minor" codes.
At present the major code is just "general", but the SVE patch will add
"SVE" as well.
Also, it was convenient to put the SVE ACLE support in its own file,
so the patch makes aarch64.c provide the frontline target hooks directly,
forwarding to the other files for the real work.
The reason for organising the files this way is that aarch64.c needs
to define the target hook macros whatever happens, and having aarch64.c
macros forward to aarch64-builtins.c functions and aarch64-bulitins.c
functions forward to the SVE file seemed a bit indirect. Doing things
the way the patch does them puts aarch64-builtins.c and the SVE code on
more of an equal footing.
The aarch64_(general_)gimple_fold_builtin change is mostly just
reindentation.
2019-09-27 Richard Sandiford <richard.sandiford@arm.com>
gcc/
* config/aarch64/aarch64-protos.h (aarch64_builtin_class): New enum.
(AARCH64_BUILTIN_SHIFT, AARCH64_BUILTIN_CLASS): New constants.
(aarch64_gimple_fold_builtin, aarch64_mangle_builtin_type)
(aarch64_fold_builtin, aarch64_init_builtins, aarch64_expand_builtin):
(aarch64_builtin_decl, aarch64_builtin_rsqrt): Delete.
(aarch64_general_mangle_builtin_type, aarch64_general_init_builtins):
(aarch64_general_fold_builtin, aarch64_general_gimple_fold_builtin):
(aarch64_general_expand_builtin, aarch64_general_builtin_decl):
(aarch64_general_builtin_rsqrt): Declare.
* config/aarch64/aarch64-builtins.c (aarch64_general_add_builtin):
New function.
(aarch64_mangle_builtin_type): Rename to...
(aarch64_general_mangle_builtin_type): ...this.
(aarch64_init_fcmla_laneq_builtins, aarch64_init_simd_builtins)
(aarch64_init_crc32_builtins, aarch64_init_builtin_rsqrt)
(aarch64_init_pauth_hint_builtins, aarch64_init_tme_builtins): Use
aarch64_general_add_builtin instead of add_builtin_function.
(aarch64_init_builtins): Rename to...
(aarch64_general_init_builtins): ...this. Use
aarch64_general_add_builtin instead of add_builtin_function.
(aarch64_builtin_decl): Rename to...
(aarch64_general_builtin_decl): ...this and remove the unused
arguments.
(aarch64_expand_builtin): Rename to...
(aarch64_general_expand_builtin): ...this and remove the unused
arguments.
(aarch64_builtin_rsqrt): Rename to...
(aarch64_general_builtin_rsqrt): ...this.
(aarch64_fold_builtin): Rename to...
(aarch64_general_fold_builtin): ...this. Take the function subcode
and return type as arguments. Remove the "ignored" argument.
(aarch64_gimple_fold_builtin): Rename to...
(aarch64_general_gimple_fold_builtin): ...this. Take the function
subcode and gcall as arguments, and return the new function call.
* config/aarch64/aarch64.c (aarch64_init_builtins)
(aarch64_fold_builtin, aarch64_gimple_fold_builtin)
(aarch64_expand_builtin, aarch64_builtin_decl): New functions.
(aarch64_builtin_reciprocal): Call aarch64_general_builtin_rsqrt
instead of aarch64_builtin_rsqrt.
(aarch64_mangle_type): Call aarch64_general_mangle_builtin_type
instead of aarch64_mangle_builtin_type.
From-SVN: r276177
2019-09-27 10:47:21 +02:00
|
|
|
gcc_assert (nargs == 2);
|
|
|
|
bool a0_cst_p = TREE_CODE (args[0]) == REAL_CST;
|
|
|
|
bool a1_cst_p = TREE_CODE (args[1]) == REAL_CST;
|
|
|
|
if (a0_cst_p || a1_cst_p)
|
2013-04-25 14:44:25 +02:00
|
|
|
{
|
[AArch64] Split built-in function codes into major and minor codes
It was easier to add the SVE ACLE support without enumerating every
function at build time. This in turn meant that it was easier if the
SVE builtins occupied a distinct numberspace from the existing AArch64
ones, which *are* enumerated at build time. This patch therefore
divides the built-in functions codes into "major" and "minor" codes.
At present the major code is just "general", but the SVE patch will add
"SVE" as well.
Also, it was convenient to put the SVE ACLE support in its own file,
so the patch makes aarch64.c provide the frontline target hooks directly,
forwarding to the other files for the real work.
The reason for organising the files this way is that aarch64.c needs
to define the target hook macros whatever happens, and having aarch64.c
macros forward to aarch64-builtins.c functions and aarch64-bulitins.c
functions forward to the SVE file seemed a bit indirect. Doing things
the way the patch does them puts aarch64-builtins.c and the SVE code on
more of an equal footing.
The aarch64_(general_)gimple_fold_builtin change is mostly just
reindentation.
2019-09-27 Richard Sandiford <richard.sandiford@arm.com>
gcc/
* config/aarch64/aarch64-protos.h (aarch64_builtin_class): New enum.
(AARCH64_BUILTIN_SHIFT, AARCH64_BUILTIN_CLASS): New constants.
(aarch64_gimple_fold_builtin, aarch64_mangle_builtin_type)
(aarch64_fold_builtin, aarch64_init_builtins, aarch64_expand_builtin):
(aarch64_builtin_decl, aarch64_builtin_rsqrt): Delete.
(aarch64_general_mangle_builtin_type, aarch64_general_init_builtins):
(aarch64_general_fold_builtin, aarch64_general_gimple_fold_builtin):
(aarch64_general_expand_builtin, aarch64_general_builtin_decl):
(aarch64_general_builtin_rsqrt): Declare.
* config/aarch64/aarch64-builtins.c (aarch64_general_add_builtin):
New function.
(aarch64_mangle_builtin_type): Rename to...
(aarch64_general_mangle_builtin_type): ...this.
(aarch64_init_fcmla_laneq_builtins, aarch64_init_simd_builtins)
(aarch64_init_crc32_builtins, aarch64_init_builtin_rsqrt)
(aarch64_init_pauth_hint_builtins, aarch64_init_tme_builtins): Use
aarch64_general_add_builtin instead of add_builtin_function.
(aarch64_init_builtins): Rename to...
(aarch64_general_init_builtins): ...this. Use
aarch64_general_add_builtin instead of add_builtin_function.
(aarch64_builtin_decl): Rename to...
(aarch64_general_builtin_decl): ...this and remove the unused
arguments.
(aarch64_expand_builtin): Rename to...
(aarch64_general_expand_builtin): ...this and remove the unused
arguments.
(aarch64_builtin_rsqrt): Rename to...
(aarch64_general_builtin_rsqrt): ...this.
(aarch64_fold_builtin): Rename to...
(aarch64_general_fold_builtin): ...this. Take the function subcode
and return type as arguments. Remove the "ignored" argument.
(aarch64_gimple_fold_builtin): Rename to...
(aarch64_general_gimple_fold_builtin): ...this. Take the function
subcode and gcall as arguments, and return the new function call.
* config/aarch64/aarch64.c (aarch64_init_builtins)
(aarch64_fold_builtin, aarch64_gimple_fold_builtin)
(aarch64_expand_builtin, aarch64_builtin_decl): New functions.
(aarch64_builtin_reciprocal): Call aarch64_general_builtin_rsqrt
instead of aarch64_builtin_rsqrt.
(aarch64_mangle_type): Call aarch64_general_mangle_builtin_type
instead of aarch64_mangle_builtin_type.
From-SVN: r276177
2019-09-27 10:47:21 +02:00
|
|
|
if (a0_cst_p && a1_cst_p)
|
2015-11-23 15:23:20 +01:00
|
|
|
{
|
[AArch64] Split built-in function codes into major and minor codes
It was easier to add the SVE ACLE support without enumerating every
function at build time. This in turn meant that it was easier if the
SVE builtins occupied a distinct numberspace from the existing AArch64
ones, which *are* enumerated at build time. This patch therefore
divides the built-in functions codes into "major" and "minor" codes.
At present the major code is just "general", but the SVE patch will add
"SVE" as well.
Also, it was convenient to put the SVE ACLE support in its own file,
so the patch makes aarch64.c provide the frontline target hooks directly,
forwarding to the other files for the real work.
The reason for organising the files this way is that aarch64.c needs
to define the target hook macros whatever happens, and having aarch64.c
macros forward to aarch64-builtins.c functions and aarch64-bulitins.c
functions forward to the SVE file seemed a bit indirect. Doing things
the way the patch does them puts aarch64-builtins.c and the SVE code on
more of an equal footing.
The aarch64_(general_)gimple_fold_builtin change is mostly just
reindentation.
2019-09-27 Richard Sandiford <richard.sandiford@arm.com>
gcc/
* config/aarch64/aarch64-protos.h (aarch64_builtin_class): New enum.
(AARCH64_BUILTIN_SHIFT, AARCH64_BUILTIN_CLASS): New constants.
(aarch64_gimple_fold_builtin, aarch64_mangle_builtin_type)
(aarch64_fold_builtin, aarch64_init_builtins, aarch64_expand_builtin):
(aarch64_builtin_decl, aarch64_builtin_rsqrt): Delete.
(aarch64_general_mangle_builtin_type, aarch64_general_init_builtins):
(aarch64_general_fold_builtin, aarch64_general_gimple_fold_builtin):
(aarch64_general_expand_builtin, aarch64_general_builtin_decl):
(aarch64_general_builtin_rsqrt): Declare.
* config/aarch64/aarch64-builtins.c (aarch64_general_add_builtin):
New function.
(aarch64_mangle_builtin_type): Rename to...
(aarch64_general_mangle_builtin_type): ...this.
(aarch64_init_fcmla_laneq_builtins, aarch64_init_simd_builtins)
(aarch64_init_crc32_builtins, aarch64_init_builtin_rsqrt)
(aarch64_init_pauth_hint_builtins, aarch64_init_tme_builtins): Use
aarch64_general_add_builtin instead of add_builtin_function.
(aarch64_init_builtins): Rename to...
(aarch64_general_init_builtins): ...this. Use
aarch64_general_add_builtin instead of add_builtin_function.
(aarch64_builtin_decl): Rename to...
(aarch64_general_builtin_decl): ...this and remove the unused
arguments.
(aarch64_expand_builtin): Rename to...
(aarch64_general_expand_builtin): ...this and remove the unused
arguments.
(aarch64_builtin_rsqrt): Rename to...
(aarch64_general_builtin_rsqrt): ...this.
(aarch64_fold_builtin): Rename to...
(aarch64_general_fold_builtin): ...this. Take the function subcode
and return type as arguments. Remove the "ignored" argument.
(aarch64_gimple_fold_builtin): Rename to...
(aarch64_general_gimple_fold_builtin): ...this. Take the function
subcode and gcall as arguments, and return the new function call.
* config/aarch64/aarch64.c (aarch64_init_builtins)
(aarch64_fold_builtin, aarch64_gimple_fold_builtin)
(aarch64_expand_builtin, aarch64_builtin_decl): New functions.
(aarch64_builtin_reciprocal): Call aarch64_general_builtin_rsqrt
instead of aarch64_builtin_rsqrt.
(aarch64_mangle_type): Call aarch64_general_mangle_builtin_type
instead of aarch64_mangle_builtin_type.
From-SVN: r276177
2019-09-27 10:47:21 +02:00
|
|
|
tree t0 = TREE_TYPE (args[0]);
|
|
|
|
real_value a0 = (TREE_REAL_CST (args[0]));
|
|
|
|
real_value a1 = (TREE_REAL_CST (args[1]));
|
|
|
|
if (real_equal (&a1, &dconst0))
|
|
|
|
std::swap (a0, a1);
|
|
|
|
/* According to real_equal (), +0 equals -0. */
|
|
|
|
if (real_equal (&a0, &dconst0) && real_isinf (&a1))
|
2015-11-23 15:23:20 +01:00
|
|
|
{
|
[AArch64] Split built-in function codes into major and minor codes
It was easier to add the SVE ACLE support without enumerating every
function at build time. This in turn meant that it was easier if the
SVE builtins occupied a distinct numberspace from the existing AArch64
ones, which *are* enumerated at build time. This patch therefore
divides the built-in functions codes into "major" and "minor" codes.
At present the major code is just "general", but the SVE patch will add
"SVE" as well.
Also, it was convenient to put the SVE ACLE support in its own file,
so the patch makes aarch64.c provide the frontline target hooks directly,
forwarding to the other files for the real work.
The reason for organising the files this way is that aarch64.c needs
to define the target hook macros whatever happens, and having aarch64.c
macros forward to aarch64-builtins.c functions and aarch64-bulitins.c
functions forward to the SVE file seemed a bit indirect. Doing things
the way the patch does them puts aarch64-builtins.c and the SVE code on
more of an equal footing.
The aarch64_(general_)gimple_fold_builtin change is mostly just
reindentation.
2019-09-27 Richard Sandiford <richard.sandiford@arm.com>
gcc/
* config/aarch64/aarch64-protos.h (aarch64_builtin_class): New enum.
(AARCH64_BUILTIN_SHIFT, AARCH64_BUILTIN_CLASS): New constants.
(aarch64_gimple_fold_builtin, aarch64_mangle_builtin_type)
(aarch64_fold_builtin, aarch64_init_builtins, aarch64_expand_builtin):
(aarch64_builtin_decl, aarch64_builtin_rsqrt): Delete.
(aarch64_general_mangle_builtin_type, aarch64_general_init_builtins):
(aarch64_general_fold_builtin, aarch64_general_gimple_fold_builtin):
(aarch64_general_expand_builtin, aarch64_general_builtin_decl):
(aarch64_general_builtin_rsqrt): Declare.
* config/aarch64/aarch64-builtins.c (aarch64_general_add_builtin):
New function.
(aarch64_mangle_builtin_type): Rename to...
(aarch64_general_mangle_builtin_type): ...this.
(aarch64_init_fcmla_laneq_builtins, aarch64_init_simd_builtins)
(aarch64_init_crc32_builtins, aarch64_init_builtin_rsqrt)
(aarch64_init_pauth_hint_builtins, aarch64_init_tme_builtins): Use
aarch64_general_add_builtin instead of add_builtin_function.
(aarch64_init_builtins): Rename to...
(aarch64_general_init_builtins): ...this. Use
aarch64_general_add_builtin instead of add_builtin_function.
(aarch64_builtin_decl): Rename to...
(aarch64_general_builtin_decl): ...this and remove the unused
arguments.
(aarch64_expand_builtin): Rename to...
(aarch64_general_expand_builtin): ...this and remove the unused
arguments.
(aarch64_builtin_rsqrt): Rename to...
(aarch64_general_builtin_rsqrt): ...this.
(aarch64_fold_builtin): Rename to...
(aarch64_general_fold_builtin): ...this. Take the function subcode
and return type as arguments. Remove the "ignored" argument.
(aarch64_gimple_fold_builtin): Rename to...
(aarch64_general_gimple_fold_builtin): ...this. Take the function
subcode and gcall as arguments, and return the new function call.
* config/aarch64/aarch64.c (aarch64_init_builtins)
(aarch64_fold_builtin, aarch64_gimple_fold_builtin)
(aarch64_expand_builtin, aarch64_builtin_decl): New functions.
(aarch64_builtin_reciprocal): Call aarch64_general_builtin_rsqrt
instead of aarch64_builtin_rsqrt.
(aarch64_mangle_type): Call aarch64_general_mangle_builtin_type
instead of aarch64_mangle_builtin_type.
From-SVN: r276177
2019-09-27 10:47:21 +02:00
|
|
|
real_value res = dconst2;
|
|
|
|
res.sign = a0.sign ^ a1.sign;
|
|
|
|
new_stmt = gimple_build_assign (gimple_call_lhs (stmt),
|
|
|
|
REAL_CST,
|
|
|
|
build_real (t0, res));
|
2015-11-23 15:23:20 +01:00
|
|
|
}
|
[AArch64] Split built-in function codes into major and minor codes
It was easier to add the SVE ACLE support without enumerating every
function at build time. This in turn meant that it was easier if the
SVE builtins occupied a distinct numberspace from the existing AArch64
ones, which *are* enumerated at build time. This patch therefore
divides the built-in functions codes into "major" and "minor" codes.
At present the major code is just "general", but the SVE patch will add
"SVE" as well.
Also, it was convenient to put the SVE ACLE support in its own file,
so the patch makes aarch64.c provide the frontline target hooks directly,
forwarding to the other files for the real work.
The reason for organising the files this way is that aarch64.c needs
to define the target hook macros whatever happens, and having aarch64.c
macros forward to aarch64-builtins.c functions and aarch64-bulitins.c
functions forward to the SVE file seemed a bit indirect. Doing things
the way the patch does them puts aarch64-builtins.c and the SVE code on
more of an equal footing.
The aarch64_(general_)gimple_fold_builtin change is mostly just
reindentation.
2019-09-27 Richard Sandiford <richard.sandiford@arm.com>
gcc/
* config/aarch64/aarch64-protos.h (aarch64_builtin_class): New enum.
(AARCH64_BUILTIN_SHIFT, AARCH64_BUILTIN_CLASS): New constants.
(aarch64_gimple_fold_builtin, aarch64_mangle_builtin_type)
(aarch64_fold_builtin, aarch64_init_builtins, aarch64_expand_builtin):
(aarch64_builtin_decl, aarch64_builtin_rsqrt): Delete.
(aarch64_general_mangle_builtin_type, aarch64_general_init_builtins):
(aarch64_general_fold_builtin, aarch64_general_gimple_fold_builtin):
(aarch64_general_expand_builtin, aarch64_general_builtin_decl):
(aarch64_general_builtin_rsqrt): Declare.
* config/aarch64/aarch64-builtins.c (aarch64_general_add_builtin):
New function.
(aarch64_mangle_builtin_type): Rename to...
(aarch64_general_mangle_builtin_type): ...this.
(aarch64_init_fcmla_laneq_builtins, aarch64_init_simd_builtins)
(aarch64_init_crc32_builtins, aarch64_init_builtin_rsqrt)
(aarch64_init_pauth_hint_builtins, aarch64_init_tme_builtins): Use
aarch64_general_add_builtin instead of add_builtin_function.
(aarch64_init_builtins): Rename to...
(aarch64_general_init_builtins): ...this. Use
aarch64_general_add_builtin instead of add_builtin_function.
(aarch64_builtin_decl): Rename to...
(aarch64_general_builtin_decl): ...this and remove the unused
arguments.
(aarch64_expand_builtin): Rename to...
(aarch64_general_expand_builtin): ...this and remove the unused
arguments.
(aarch64_builtin_rsqrt): Rename to...
(aarch64_general_builtin_rsqrt): ...this.
(aarch64_fold_builtin): Rename to...
(aarch64_general_fold_builtin): ...this. Take the function subcode
and return type as arguments. Remove the "ignored" argument.
(aarch64_gimple_fold_builtin): Rename to...
(aarch64_general_gimple_fold_builtin): ...this. Take the function
subcode and gcall as arguments, and return the new function call.
* config/aarch64/aarch64.c (aarch64_init_builtins)
(aarch64_fold_builtin, aarch64_gimple_fold_builtin)
(aarch64_expand_builtin, aarch64_builtin_decl): New functions.
(aarch64_builtin_reciprocal): Call aarch64_general_builtin_rsqrt
instead of aarch64_builtin_rsqrt.
(aarch64_mangle_type): Call aarch64_general_mangle_builtin_type
instead of aarch64_mangle_builtin_type.
From-SVN: r276177
2019-09-27 10:47:21 +02:00
|
|
|
else
|
|
|
|
new_stmt = gimple_build_assign (gimple_call_lhs (stmt),
|
|
|
|
MULT_EXPR,
|
|
|
|
args[0], args[1]);
|
2015-11-23 15:23:20 +01:00
|
|
|
}
|
[AArch64] Split built-in function codes into major and minor codes
It was easier to add the SVE ACLE support without enumerating every
function at build time. This in turn meant that it was easier if the
SVE builtins occupied a distinct numberspace from the existing AArch64
ones, which *are* enumerated at build time. This patch therefore
divides the built-in functions codes into "major" and "minor" codes.
At present the major code is just "general", but the SVE patch will add
"SVE" as well.
Also, it was convenient to put the SVE ACLE support in its own file,
so the patch makes aarch64.c provide the frontline target hooks directly,
forwarding to the other files for the real work.
The reason for organising the files this way is that aarch64.c needs
to define the target hook macros whatever happens, and having aarch64.c
macros forward to aarch64-builtins.c functions and aarch64-bulitins.c
functions forward to the SVE file seemed a bit indirect. Doing things
the way the patch does them puts aarch64-builtins.c and the SVE code on
more of an equal footing.
The aarch64_(general_)gimple_fold_builtin change is mostly just
reindentation.
2019-09-27 Richard Sandiford <richard.sandiford@arm.com>
gcc/
* config/aarch64/aarch64-protos.h (aarch64_builtin_class): New enum.
(AARCH64_BUILTIN_SHIFT, AARCH64_BUILTIN_CLASS): New constants.
(aarch64_gimple_fold_builtin, aarch64_mangle_builtin_type)
(aarch64_fold_builtin, aarch64_init_builtins, aarch64_expand_builtin):
(aarch64_builtin_decl, aarch64_builtin_rsqrt): Delete.
(aarch64_general_mangle_builtin_type, aarch64_general_init_builtins):
(aarch64_general_fold_builtin, aarch64_general_gimple_fold_builtin):
(aarch64_general_expand_builtin, aarch64_general_builtin_decl):
(aarch64_general_builtin_rsqrt): Declare.
* config/aarch64/aarch64-builtins.c (aarch64_general_add_builtin):
New function.
(aarch64_mangle_builtin_type): Rename to...
(aarch64_general_mangle_builtin_type): ...this.
(aarch64_init_fcmla_laneq_builtins, aarch64_init_simd_builtins)
(aarch64_init_crc32_builtins, aarch64_init_builtin_rsqrt)
(aarch64_init_pauth_hint_builtins, aarch64_init_tme_builtins): Use
aarch64_general_add_builtin instead of add_builtin_function.
(aarch64_init_builtins): Rename to...
(aarch64_general_init_builtins): ...this. Use
aarch64_general_add_builtin instead of add_builtin_function.
(aarch64_builtin_decl): Rename to...
(aarch64_general_builtin_decl): ...this and remove the unused
arguments.
(aarch64_expand_builtin): Rename to...
(aarch64_general_expand_builtin): ...this and remove the unused
arguments.
(aarch64_builtin_rsqrt): Rename to...
(aarch64_general_builtin_rsqrt): ...this.
(aarch64_fold_builtin): Rename to...
(aarch64_general_fold_builtin): ...this. Take the function subcode
and return type as arguments. Remove the "ignored" argument.
(aarch64_gimple_fold_builtin): Rename to...
(aarch64_general_gimple_fold_builtin): ...this. Take the function
subcode and gcall as arguments, and return the new function call.
* config/aarch64/aarch64.c (aarch64_init_builtins)
(aarch64_fold_builtin, aarch64_gimple_fold_builtin)
(aarch64_expand_builtin, aarch64_builtin_decl): New functions.
(aarch64_builtin_reciprocal): Call aarch64_general_builtin_rsqrt
instead of aarch64_builtin_rsqrt.
(aarch64_mangle_type): Call aarch64_general_mangle_builtin_type
instead of aarch64_mangle_builtin_type.
From-SVN: r276177
2019-09-27 10:47:21 +02:00
|
|
|
else /* a0_cst_p ^ a1_cst_p. */
|
|
|
|
{
|
|
|
|
real_value const_part = a0_cst_p
|
|
|
|
? TREE_REAL_CST (args[0]) : TREE_REAL_CST (args[1]);
|
|
|
|
if (!real_equal (&const_part, &dconst0)
|
|
|
|
&& !real_isinf (&const_part))
|
|
|
|
new_stmt = gimple_build_assign (gimple_call_lhs (stmt),
|
|
|
|
MULT_EXPR, args[0],
|
|
|
|
args[1]);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
if (new_stmt)
|
|
|
|
{
|
|
|
|
gimple_set_vuse (new_stmt, gimple_vuse (stmt));
|
|
|
|
gimple_set_vdef (new_stmt, gimple_vdef (stmt));
|
2013-04-25 14:44:25 +02:00
|
|
|
}
|
[AArch64] Split built-in function codes into major and minor codes
It was easier to add the SVE ACLE support without enumerating every
function at build time. This in turn meant that it was easier if the
SVE builtins occupied a distinct numberspace from the existing AArch64
ones, which *are* enumerated at build time. This patch therefore
divides the built-in functions codes into "major" and "minor" codes.
At present the major code is just "general", but the SVE patch will add
"SVE" as well.
Also, it was convenient to put the SVE ACLE support in its own file,
so the patch makes aarch64.c provide the frontline target hooks directly,
forwarding to the other files for the real work.
The reason for organising the files this way is that aarch64.c needs
to define the target hook macros whatever happens, and having aarch64.c
macros forward to aarch64-builtins.c functions and aarch64-bulitins.c
functions forward to the SVE file seemed a bit indirect. Doing things
the way the patch does them puts aarch64-builtins.c and the SVE code on
more of an equal footing.
The aarch64_(general_)gimple_fold_builtin change is mostly just
reindentation.
2019-09-27 Richard Sandiford <richard.sandiford@arm.com>
gcc/
* config/aarch64/aarch64-protos.h (aarch64_builtin_class): New enum.
(AARCH64_BUILTIN_SHIFT, AARCH64_BUILTIN_CLASS): New constants.
(aarch64_gimple_fold_builtin, aarch64_mangle_builtin_type)
(aarch64_fold_builtin, aarch64_init_builtins, aarch64_expand_builtin):
(aarch64_builtin_decl, aarch64_builtin_rsqrt): Delete.
(aarch64_general_mangle_builtin_type, aarch64_general_init_builtins):
(aarch64_general_fold_builtin, aarch64_general_gimple_fold_builtin):
(aarch64_general_expand_builtin, aarch64_general_builtin_decl):
(aarch64_general_builtin_rsqrt): Declare.
* config/aarch64/aarch64-builtins.c (aarch64_general_add_builtin):
New function.
(aarch64_mangle_builtin_type): Rename to...
(aarch64_general_mangle_builtin_type): ...this.
(aarch64_init_fcmla_laneq_builtins, aarch64_init_simd_builtins)
(aarch64_init_crc32_builtins, aarch64_init_builtin_rsqrt)
(aarch64_init_pauth_hint_builtins, aarch64_init_tme_builtins): Use
aarch64_general_add_builtin instead of add_builtin_function.
(aarch64_init_builtins): Rename to...
(aarch64_general_init_builtins): ...this. Use
aarch64_general_add_builtin instead of add_builtin_function.
(aarch64_builtin_decl): Rename to...
(aarch64_general_builtin_decl): ...this and remove the unused
arguments.
(aarch64_expand_builtin): Rename to...
(aarch64_general_expand_builtin): ...this and remove the unused
arguments.
(aarch64_builtin_rsqrt): Rename to...
(aarch64_general_builtin_rsqrt): ...this.
(aarch64_fold_builtin): Rename to...
(aarch64_general_fold_builtin): ...this. Take the function subcode
and return type as arguments. Remove the "ignored" argument.
(aarch64_gimple_fold_builtin): Rename to...
(aarch64_general_gimple_fold_builtin): ...this. Take the function
subcode and gcall as arguments, and return the new function call.
* config/aarch64/aarch64.c (aarch64_init_builtins)
(aarch64_fold_builtin, aarch64_gimple_fold_builtin)
(aarch64_expand_builtin, aarch64_builtin_decl): New functions.
(aarch64_builtin_reciprocal): Call aarch64_general_builtin_rsqrt
instead of aarch64_builtin_rsqrt.
(aarch64_mangle_type): Call aarch64_general_mangle_builtin_type
instead of aarch64_mangle_builtin_type.
From-SVN: r276177
2019-09-27 10:47:21 +02:00
|
|
|
break;
|
2013-04-25 14:44:25 +02:00
|
|
|
}
|
2021-09-02 09:08:22 +02:00
|
|
|
case AARCH64_SIMD_BUILTIN_LANE_CHECK:
|
|
|
|
if (aarch64_fold_builtin_lane_check (args[0], args[1], args[2]))
|
|
|
|
{
|
|
|
|
unlink_stmt_vdef (stmt);
|
|
|
|
release_defs (stmt);
|
|
|
|
new_stmt = gimple_build_nop ();
|
|
|
|
}
|
|
|
|
break;
|
[AArch64] Split built-in function codes into major and minor codes
It was easier to add the SVE ACLE support without enumerating every
function at build time. This in turn meant that it was easier if the
SVE builtins occupied a distinct numberspace from the existing AArch64
ones, which *are* enumerated at build time. This patch therefore
divides the built-in functions codes into "major" and "minor" codes.
At present the major code is just "general", but the SVE patch will add
"SVE" as well.
Also, it was convenient to put the SVE ACLE support in its own file,
so the patch makes aarch64.c provide the frontline target hooks directly,
forwarding to the other files for the real work.
The reason for organising the files this way is that aarch64.c needs
to define the target hook macros whatever happens, and having aarch64.c
macros forward to aarch64-builtins.c functions and aarch64-bulitins.c
functions forward to the SVE file seemed a bit indirect. Doing things
the way the patch does them puts aarch64-builtins.c and the SVE code on
more of an equal footing.
The aarch64_(general_)gimple_fold_builtin change is mostly just
reindentation.
2019-09-27 Richard Sandiford <richard.sandiford@arm.com>
gcc/
* config/aarch64/aarch64-protos.h (aarch64_builtin_class): New enum.
(AARCH64_BUILTIN_SHIFT, AARCH64_BUILTIN_CLASS): New constants.
(aarch64_gimple_fold_builtin, aarch64_mangle_builtin_type)
(aarch64_fold_builtin, aarch64_init_builtins, aarch64_expand_builtin):
(aarch64_builtin_decl, aarch64_builtin_rsqrt): Delete.
(aarch64_general_mangle_builtin_type, aarch64_general_init_builtins):
(aarch64_general_fold_builtin, aarch64_general_gimple_fold_builtin):
(aarch64_general_expand_builtin, aarch64_general_builtin_decl):
(aarch64_general_builtin_rsqrt): Declare.
* config/aarch64/aarch64-builtins.c (aarch64_general_add_builtin):
New function.
(aarch64_mangle_builtin_type): Rename to...
(aarch64_general_mangle_builtin_type): ...this.
(aarch64_init_fcmla_laneq_builtins, aarch64_init_simd_builtins)
(aarch64_init_crc32_builtins, aarch64_init_builtin_rsqrt)
(aarch64_init_pauth_hint_builtins, aarch64_init_tme_builtins): Use
aarch64_general_add_builtin instead of add_builtin_function.
(aarch64_init_builtins): Rename to...
(aarch64_general_init_builtins): ...this. Use
aarch64_general_add_builtin instead of add_builtin_function.
(aarch64_builtin_decl): Rename to...
(aarch64_general_builtin_decl): ...this and remove the unused
arguments.
(aarch64_expand_builtin): Rename to...
(aarch64_general_expand_builtin): ...this and remove the unused
arguments.
(aarch64_builtin_rsqrt): Rename to...
(aarch64_general_builtin_rsqrt): ...this.
(aarch64_fold_builtin): Rename to...
(aarch64_general_fold_builtin): ...this. Take the function subcode
and return type as arguments. Remove the "ignored" argument.
(aarch64_gimple_fold_builtin): Rename to...
(aarch64_general_gimple_fold_builtin): ...this. Take the function
subcode and gcall as arguments, and return the new function call.
* config/aarch64/aarch64.c (aarch64_init_builtins)
(aarch64_fold_builtin, aarch64_gimple_fold_builtin)
(aarch64_expand_builtin, aarch64_builtin_decl): New functions.
(aarch64_builtin_reciprocal): Call aarch64_general_builtin_rsqrt
instead of aarch64_builtin_rsqrt.
(aarch64_mangle_type): Call aarch64_general_mangle_builtin_type
instead of aarch64_mangle_builtin_type.
From-SVN: r276177
2019-09-27 10:47:21 +02:00
|
|
|
default:
|
|
|
|
break;
|
2013-04-25 14:44:25 +02:00
|
|
|
}
|
[AArch64] Split built-in function codes into major and minor codes
It was easier to add the SVE ACLE support without enumerating every
function at build time. This in turn meant that it was easier if the
SVE builtins occupied a distinct numberspace from the existing AArch64
ones, which *are* enumerated at build time. This patch therefore
divides the built-in functions codes into "major" and "minor" codes.
At present the major code is just "general", but the SVE patch will add
"SVE" as well.
Also, it was convenient to put the SVE ACLE support in its own file,
so the patch makes aarch64.c provide the frontline target hooks directly,
forwarding to the other files for the real work.
The reason for organising the files this way is that aarch64.c needs
to define the target hook macros whatever happens, and having aarch64.c
macros forward to aarch64-builtins.c functions and aarch64-bulitins.c
functions forward to the SVE file seemed a bit indirect. Doing things
the way the patch does them puts aarch64-builtins.c and the SVE code on
more of an equal footing.
The aarch64_(general_)gimple_fold_builtin change is mostly just
reindentation.
2019-09-27 Richard Sandiford <richard.sandiford@arm.com>
gcc/
* config/aarch64/aarch64-protos.h (aarch64_builtin_class): New enum.
(AARCH64_BUILTIN_SHIFT, AARCH64_BUILTIN_CLASS): New constants.
(aarch64_gimple_fold_builtin, aarch64_mangle_builtin_type)
(aarch64_fold_builtin, aarch64_init_builtins, aarch64_expand_builtin):
(aarch64_builtin_decl, aarch64_builtin_rsqrt): Delete.
(aarch64_general_mangle_builtin_type, aarch64_general_init_builtins):
(aarch64_general_fold_builtin, aarch64_general_gimple_fold_builtin):
(aarch64_general_expand_builtin, aarch64_general_builtin_decl):
(aarch64_general_builtin_rsqrt): Declare.
* config/aarch64/aarch64-builtins.c (aarch64_general_add_builtin):
New function.
(aarch64_mangle_builtin_type): Rename to...
(aarch64_general_mangle_builtin_type): ...this.
(aarch64_init_fcmla_laneq_builtins, aarch64_init_simd_builtins)
(aarch64_init_crc32_builtins, aarch64_init_builtin_rsqrt)
(aarch64_init_pauth_hint_builtins, aarch64_init_tme_builtins): Use
aarch64_general_add_builtin instead of add_builtin_function.
(aarch64_init_builtins): Rename to...
(aarch64_general_init_builtins): ...this. Use
aarch64_general_add_builtin instead of add_builtin_function.
(aarch64_builtin_decl): Rename to...
(aarch64_general_builtin_decl): ...this and remove the unused
arguments.
(aarch64_expand_builtin): Rename to...
(aarch64_general_expand_builtin): ...this and remove the unused
arguments.
(aarch64_builtin_rsqrt): Rename to...
(aarch64_general_builtin_rsqrt): ...this.
(aarch64_fold_builtin): Rename to...
(aarch64_general_fold_builtin): ...this. Take the function subcode
and return type as arguments. Remove the "ignored" argument.
(aarch64_gimple_fold_builtin): Rename to...
(aarch64_general_gimple_fold_builtin): ...this. Take the function
subcode and gcall as arguments, and return the new function call.
* config/aarch64/aarch64.c (aarch64_init_builtins)
(aarch64_fold_builtin, aarch64_gimple_fold_builtin)
(aarch64_expand_builtin, aarch64_builtin_decl): New functions.
(aarch64_builtin_reciprocal): Call aarch64_general_builtin_rsqrt
instead of aarch64_builtin_rsqrt.
(aarch64_mangle_type): Call aarch64_general_mangle_builtin_type
instead of aarch64_mangle_builtin_type.
From-SVN: r276177
2019-09-27 10:47:21 +02:00
|
|
|
return new_stmt;
|
2013-04-25 14:44:25 +02:00
|
|
|
}
|
|
|
|
|
2014-05-23 00:05:08 +02:00
|
|
|
void
|
|
|
|
aarch64_atomic_assign_expand_fenv (tree *hold, tree *clear, tree *update)
|
|
|
|
{
|
|
|
|
const unsigned AARCH64_FE_INVALID = 1;
|
|
|
|
const unsigned AARCH64_FE_DIVBYZERO = 2;
|
|
|
|
const unsigned AARCH64_FE_OVERFLOW = 4;
|
|
|
|
const unsigned AARCH64_FE_UNDERFLOW = 8;
|
|
|
|
const unsigned AARCH64_FE_INEXACT = 16;
|
|
|
|
const unsigned HOST_WIDE_INT AARCH64_FE_ALL_EXCEPT = (AARCH64_FE_INVALID
|
|
|
|
| AARCH64_FE_DIVBYZERO
|
|
|
|
| AARCH64_FE_OVERFLOW
|
|
|
|
| AARCH64_FE_UNDERFLOW
|
|
|
|
| AARCH64_FE_INEXACT);
|
|
|
|
const unsigned HOST_WIDE_INT AARCH64_FE_EXCEPT_SHIFT = 8;
|
|
|
|
tree fenv_cr, fenv_sr, get_fpcr, set_fpcr, mask_cr, mask_sr;
|
|
|
|
tree ld_fenv_cr, ld_fenv_sr, masked_fenv_cr, masked_fenv_sr, hold_fnclex_cr;
|
|
|
|
tree hold_fnclex_sr, new_fenv_var, reload_fenv, restore_fnenv, get_fpsr, set_fpsr;
|
|
|
|
tree update_call, atomic_feraiseexcept, hold_fnclex, masked_fenv, ld_fenv;
|
|
|
|
|
|
|
|
/* Generate the equivalence of :
|
|
|
|
unsigned int fenv_cr;
|
|
|
|
fenv_cr = __builtin_aarch64_get_fpcr ();
|
|
|
|
|
|
|
|
unsigned int fenv_sr;
|
|
|
|
fenv_sr = __builtin_aarch64_get_fpsr ();
|
|
|
|
|
|
|
|
Now set all exceptions to non-stop
|
|
|
|
unsigned int mask_cr
|
|
|
|
= ~(AARCH64_FE_ALL_EXCEPT << AARCH64_FE_EXCEPT_SHIFT);
|
|
|
|
unsigned int masked_cr;
|
|
|
|
masked_cr = fenv_cr & mask_cr;
|
|
|
|
|
|
|
|
And clear all exception flags
|
|
|
|
unsigned int maske_sr = ~AARCH64_FE_ALL_EXCEPT;
|
|
|
|
unsigned int masked_cr;
|
|
|
|
masked_sr = fenv_sr & mask_sr;
|
|
|
|
|
|
|
|
__builtin_aarch64_set_cr (masked_cr);
|
|
|
|
__builtin_aarch64_set_sr (masked_sr); */
|
|
|
|
|
2015-10-06 17:09:43 +02:00
|
|
|
fenv_cr = create_tmp_var_raw (unsigned_type_node);
|
|
|
|
fenv_sr = create_tmp_var_raw (unsigned_type_node);
|
2014-05-23 00:05:08 +02:00
|
|
|
|
|
|
|
get_fpcr = aarch64_builtin_decls[AARCH64_BUILTIN_GET_FPCR];
|
|
|
|
set_fpcr = aarch64_builtin_decls[AARCH64_BUILTIN_SET_FPCR];
|
|
|
|
get_fpsr = aarch64_builtin_decls[AARCH64_BUILTIN_GET_FPSR];
|
|
|
|
set_fpsr = aarch64_builtin_decls[AARCH64_BUILTIN_SET_FPSR];
|
|
|
|
|
|
|
|
mask_cr = build_int_cst (unsigned_type_node,
|
|
|
|
~(AARCH64_FE_ALL_EXCEPT << AARCH64_FE_EXCEPT_SHIFT));
|
|
|
|
mask_sr = build_int_cst (unsigned_type_node,
|
|
|
|
~(AARCH64_FE_ALL_EXCEPT));
|
|
|
|
|
2020-04-29 10:23:11 +02:00
|
|
|
ld_fenv_cr = build4 (TARGET_EXPR, unsigned_type_node,
|
|
|
|
fenv_cr, build_call_expr (get_fpcr, 0),
|
|
|
|
NULL_TREE, NULL_TREE);
|
|
|
|
ld_fenv_sr = build4 (TARGET_EXPR, unsigned_type_node,
|
|
|
|
fenv_sr, build_call_expr (get_fpsr, 0),
|
|
|
|
NULL_TREE, NULL_TREE);
|
2014-05-23 00:05:08 +02:00
|
|
|
|
|
|
|
masked_fenv_cr = build2 (BIT_AND_EXPR, unsigned_type_node, fenv_cr, mask_cr);
|
|
|
|
masked_fenv_sr = build2 (BIT_AND_EXPR, unsigned_type_node, fenv_sr, mask_sr);
|
|
|
|
|
|
|
|
hold_fnclex_cr = build_call_expr (set_fpcr, 1, masked_fenv_cr);
|
|
|
|
hold_fnclex_sr = build_call_expr (set_fpsr, 1, masked_fenv_sr);
|
|
|
|
|
|
|
|
hold_fnclex = build2 (COMPOUND_EXPR, void_type_node, hold_fnclex_cr,
|
|
|
|
hold_fnclex_sr);
|
|
|
|
masked_fenv = build2 (COMPOUND_EXPR, void_type_node, masked_fenv_cr,
|
|
|
|
masked_fenv_sr);
|
|
|
|
ld_fenv = build2 (COMPOUND_EXPR, void_type_node, ld_fenv_cr, ld_fenv_sr);
|
|
|
|
|
|
|
|
*hold = build2 (COMPOUND_EXPR, void_type_node,
|
|
|
|
build2 (COMPOUND_EXPR, void_type_node, masked_fenv, ld_fenv),
|
|
|
|
hold_fnclex);
|
|
|
|
|
|
|
|
/* Store the value of masked_fenv to clear the exceptions:
|
|
|
|
__builtin_aarch64_set_fpsr (masked_fenv_sr); */
|
|
|
|
|
|
|
|
*clear = build_call_expr (set_fpsr, 1, masked_fenv_sr);
|
|
|
|
|
|
|
|
/* Generate the equivalent of :
|
|
|
|
unsigned int new_fenv_var;
|
|
|
|
new_fenv_var = __builtin_aarch64_get_fpsr ();
|
|
|
|
|
|
|
|
__builtin_aarch64_set_fpsr (fenv_sr);
|
|
|
|
|
|
|
|
__atomic_feraiseexcept (new_fenv_var); */
|
|
|
|
|
2015-10-06 17:09:43 +02:00
|
|
|
new_fenv_var = create_tmp_var_raw (unsigned_type_node);
|
2020-04-29 10:23:11 +02:00
|
|
|
reload_fenv = build4 (TARGET_EXPR, unsigned_type_node,
|
|
|
|
new_fenv_var, build_call_expr (get_fpsr, 0),
|
|
|
|
NULL_TREE, NULL_TREE);
|
2014-05-23 00:05:08 +02:00
|
|
|
restore_fnenv = build_call_expr (set_fpsr, 1, fenv_sr);
|
|
|
|
atomic_feraiseexcept = builtin_decl_implicit (BUILT_IN_ATOMIC_FERAISEEXCEPT);
|
|
|
|
update_call = build_call_expr (atomic_feraiseexcept, 1,
|
|
|
|
fold_convert (integer_type_node, new_fenv_var));
|
|
|
|
*update = build2 (COMPOUND_EXPR, void_type_node,
|
|
|
|
build2 (COMPOUND_EXPR, void_type_node,
|
|
|
|
reload_fenv, restore_fnenv), update_call);
|
|
|
|
}
|
|
|
|
|
[AArch64] Implement Armv8.5-A memory tagging (MTE) intrinsics
2019-11-19 Dennis Zhang <dennis.zhang@arm.com>
* config/aarch64/aarch64-builtins.c (enum aarch64_builtins): Add
AARCH64_MEMTAG_BUILTIN_START, AARCH64_MEMTAG_BUILTIN_IRG,
AARCH64_MEMTAG_BUILTIN_GMI, AARCH64_MEMTAG_BUILTIN_SUBP,
AARCH64_MEMTAG_BUILTIN_INC_TAG, AARCH64_MEMTAG_BUILTIN_SET_TAG,
AARCH64_MEMTAG_BUILTIN_GET_TAG, and AARCH64_MEMTAG_BUILTIN_END.
(aarch64_init_memtag_builtins): New.
(AARCH64_INIT_MEMTAG_BUILTINS_DECL): New macro.
(aarch64_general_init_builtins): Call aarch64_init_memtag_builtins.
(aarch64_expand_builtin_memtag): New.
(aarch64_general_expand_builtin): Call aarch64_expand_builtin_memtag.
(AARCH64_BUILTIN_SUBCODE): New macro.
(aarch64_resolve_overloaded_memtag): New.
(aarch64_resolve_overloaded_builtin_general): New. Call
aarch64_resolve_overloaded_memtag to handle overloaded MTE builtins.
* config/aarch64/aarch64-c.c (aarch64_update_cpp_builtins): Define
__ARM_FEATURE_MEMORY_TAGGING when enabled.
(aarch64_resolve_overloaded_builtin): Call
aarch64_resolve_overloaded_builtin_general.
* config/aarch64/aarch64-protos.h
(aarch64_resolve_overloaded_builtin_general): New declaration.
* config/aarch64/aarch64.h (AARCH64_ISA_MEMTAG): New macro.
(TARGET_MEMTAG): Likewise.
* config/aarch64/aarch64.md (UNSPEC_GEN_TAG): New unspec.
(UNSPEC_GEN_TAG_RND, and UNSPEC_TAG_SPACE): Likewise.
(irg, gmi, subp, addg, ldg, stg): New instructions.
* config/aarch64/arm_acle.h (__arm_mte_create_random_tag): New macro.
(__arm_mte_exclude_tag, __arm_mte_ptrdiff): Likewise.
(__arm_mte_increment_tag, __arm_mte_set_tag): Likewise.
(__arm_mte_get_tag): Likewise.
* config/aarch64/predicates.md (aarch64_memtag_tag_offset): New.
(aarch64_granule16_uimm6, aarch64_granule16_simm9): New.
* config/arm/types.md (memtag): New.
* doc/invoke.texi (-memtag): Update description.
2019-11-19 Dennis Zhang <dennis.zhang@arm.com>
* gcc.target/aarch64/acle/memtag_1.c: New test.
* gcc.target/aarch64/acle/memtag_2.c: New test.
* gcc.target/aarch64/acle/memtag_3.c: New test.
From-SVN: r278444
2019-11-19 14:43:39 +01:00
|
|
|
/* Resolve overloaded MEMTAG build-in functions. */
|
|
|
|
#define AARCH64_BUILTIN_SUBCODE(F) \
|
|
|
|
(DECL_MD_FUNCTION_CODE (F) >> AARCH64_BUILTIN_SHIFT)
|
|
|
|
|
|
|
|
static tree
|
|
|
|
aarch64_resolve_overloaded_memtag (location_t loc,
|
|
|
|
tree fndecl, void *pass_params)
|
|
|
|
{
|
|
|
|
vec<tree, va_gc> *params = static_cast<vec<tree, va_gc> *> (pass_params);
|
|
|
|
unsigned param_num = params ? params->length() : 0;
|
|
|
|
unsigned int fcode = AARCH64_BUILTIN_SUBCODE (fndecl);
|
|
|
|
tree inittype = aarch64_memtag_builtin_data[
|
|
|
|
fcode - AARCH64_MEMTAG_BUILTIN_START - 1].ftype;
|
|
|
|
unsigned arg_num = list_length (TYPE_ARG_TYPES (inittype)) - 1;
|
|
|
|
|
|
|
|
if (param_num != arg_num)
|
|
|
|
{
|
|
|
|
TREE_TYPE (fndecl) = inittype;
|
|
|
|
return NULL_TREE;
|
|
|
|
}
|
|
|
|
tree retype = NULL;
|
|
|
|
|
|
|
|
if (fcode == AARCH64_MEMTAG_BUILTIN_SUBP)
|
|
|
|
{
|
|
|
|
tree t0 = TREE_TYPE ((*params)[0]);
|
|
|
|
tree t1 = TREE_TYPE ((*params)[1]);
|
|
|
|
|
|
|
|
if (t0 == error_mark_node || TREE_CODE (t0) != POINTER_TYPE)
|
|
|
|
t0 = ptr_type_node;
|
|
|
|
if (t1 == error_mark_node || TREE_CODE (t1) != POINTER_TYPE)
|
|
|
|
t1 = ptr_type_node;
|
|
|
|
|
|
|
|
if (TYPE_MODE (t0) != DImode)
|
|
|
|
warning_at (loc, 1, "expected 64-bit address but argument 1 is %d-bit",
|
|
|
|
(int)tree_to_shwi (DECL_SIZE ((*params)[0])));
|
|
|
|
|
|
|
|
if (TYPE_MODE (t1) != DImode)
|
|
|
|
warning_at (loc, 1, "expected 64-bit address but argument 2 is %d-bit",
|
|
|
|
(int)tree_to_shwi (DECL_SIZE ((*params)[1])));
|
|
|
|
|
|
|
|
retype = build_function_type_list (ptrdiff_type_node, t0, t1, NULL);
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
tree t0 = TREE_TYPE ((*params)[0]);
|
|
|
|
|
|
|
|
if (t0 == error_mark_node || TREE_CODE (t0) != POINTER_TYPE)
|
|
|
|
{
|
|
|
|
TREE_TYPE (fndecl) = inittype;
|
|
|
|
return NULL_TREE;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (TYPE_MODE (t0) != DImode)
|
|
|
|
warning_at (loc, 1, "expected 64-bit address but argument 1 is %d-bit",
|
|
|
|
(int)tree_to_shwi (DECL_SIZE ((*params)[0])));
|
|
|
|
|
|
|
|
switch (fcode)
|
|
|
|
{
|
|
|
|
case AARCH64_MEMTAG_BUILTIN_IRG:
|
|
|
|
retype = build_function_type_list (t0, t0, uint64_type_node, NULL);
|
|
|
|
break;
|
|
|
|
case AARCH64_MEMTAG_BUILTIN_GMI:
|
|
|
|
retype = build_function_type_list (uint64_type_node, t0,
|
|
|
|
uint64_type_node, NULL);
|
|
|
|
break;
|
|
|
|
case AARCH64_MEMTAG_BUILTIN_INC_TAG:
|
|
|
|
retype = build_function_type_list (t0, t0, unsigned_type_node, NULL);
|
|
|
|
break;
|
|
|
|
case AARCH64_MEMTAG_BUILTIN_SET_TAG:
|
|
|
|
retype = build_function_type_list (void_type_node, t0, NULL);
|
|
|
|
break;
|
|
|
|
case AARCH64_MEMTAG_BUILTIN_GET_TAG:
|
|
|
|
retype = build_function_type_list (t0, t0, NULL);
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
return NULL_TREE;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
if (!retype || retype == error_mark_node)
|
|
|
|
TREE_TYPE (fndecl) = inittype;
|
|
|
|
else
|
|
|
|
TREE_TYPE (fndecl) = retype;
|
|
|
|
|
|
|
|
return NULL_TREE;
|
|
|
|
}
|
|
|
|
|
2022-01-14 16:57:02 +01:00
|
|
|
/* Called at aarch64_resolve_overloaded_builtin in aarch64-c.cc. */
|
[AArch64] Implement Armv8.5-A memory tagging (MTE) intrinsics
2019-11-19 Dennis Zhang <dennis.zhang@arm.com>
* config/aarch64/aarch64-builtins.c (enum aarch64_builtins): Add
AARCH64_MEMTAG_BUILTIN_START, AARCH64_MEMTAG_BUILTIN_IRG,
AARCH64_MEMTAG_BUILTIN_GMI, AARCH64_MEMTAG_BUILTIN_SUBP,
AARCH64_MEMTAG_BUILTIN_INC_TAG, AARCH64_MEMTAG_BUILTIN_SET_TAG,
AARCH64_MEMTAG_BUILTIN_GET_TAG, and AARCH64_MEMTAG_BUILTIN_END.
(aarch64_init_memtag_builtins): New.
(AARCH64_INIT_MEMTAG_BUILTINS_DECL): New macro.
(aarch64_general_init_builtins): Call aarch64_init_memtag_builtins.
(aarch64_expand_builtin_memtag): New.
(aarch64_general_expand_builtin): Call aarch64_expand_builtin_memtag.
(AARCH64_BUILTIN_SUBCODE): New macro.
(aarch64_resolve_overloaded_memtag): New.
(aarch64_resolve_overloaded_builtin_general): New. Call
aarch64_resolve_overloaded_memtag to handle overloaded MTE builtins.
* config/aarch64/aarch64-c.c (aarch64_update_cpp_builtins): Define
__ARM_FEATURE_MEMORY_TAGGING when enabled.
(aarch64_resolve_overloaded_builtin): Call
aarch64_resolve_overloaded_builtin_general.
* config/aarch64/aarch64-protos.h
(aarch64_resolve_overloaded_builtin_general): New declaration.
* config/aarch64/aarch64.h (AARCH64_ISA_MEMTAG): New macro.
(TARGET_MEMTAG): Likewise.
* config/aarch64/aarch64.md (UNSPEC_GEN_TAG): New unspec.
(UNSPEC_GEN_TAG_RND, and UNSPEC_TAG_SPACE): Likewise.
(irg, gmi, subp, addg, ldg, stg): New instructions.
* config/aarch64/arm_acle.h (__arm_mte_create_random_tag): New macro.
(__arm_mte_exclude_tag, __arm_mte_ptrdiff): Likewise.
(__arm_mte_increment_tag, __arm_mte_set_tag): Likewise.
(__arm_mte_get_tag): Likewise.
* config/aarch64/predicates.md (aarch64_memtag_tag_offset): New.
(aarch64_granule16_uimm6, aarch64_granule16_simm9): New.
* config/arm/types.md (memtag): New.
* doc/invoke.texi (-memtag): Update description.
2019-11-19 Dennis Zhang <dennis.zhang@arm.com>
* gcc.target/aarch64/acle/memtag_1.c: New test.
* gcc.target/aarch64/acle/memtag_2.c: New test.
* gcc.target/aarch64/acle/memtag_3.c: New test.
From-SVN: r278444
2019-11-19 14:43:39 +01:00
|
|
|
tree
|
|
|
|
aarch64_resolve_overloaded_builtin_general (location_t loc, tree function,
|
|
|
|
void *pass_params)
|
|
|
|
{
|
|
|
|
unsigned int fcode = AARCH64_BUILTIN_SUBCODE (function);
|
|
|
|
|
|
|
|
if (fcode >= AARCH64_MEMTAG_BUILTIN_START
|
|
|
|
&& fcode <= AARCH64_MEMTAG_BUILTIN_END)
|
|
|
|
return aarch64_resolve_overloaded_memtag(loc, function, pass_params);
|
|
|
|
|
|
|
|
return NULL_TREE;
|
|
|
|
}
|
2014-05-23 00:05:08 +02:00
|
|
|
|
[AARCH64] Add support for vectorizable standard math patterns.
gcc/
* config/aarch64/aarch64-builtins.c
(aarch64_builtin_vectorized_function): New.
* config/aarch64/aarch64-protos.h
(aarch64_builtin_vectorized_function): Declare.
* config/aarch64/aarch64-simd-builtins.def (frintz, frintp): Add.
(frintm, frinti, frintx, frinta, fcvtzs, fcvtzu): Likewise.
(fcvtas, fcvtau, fcvtps, fcvtpu, fcvtms, fcvtmu): Likewise.
* config/aarch64/aarch64-simd.md
(aarch64_frint_<frint_suffix><mode>): New.
(<frint_pattern><mode>2): Likewise.
(aarch64_fcvt<frint_suffix><su><mode>): Likewise.
(l<fcvt_pattern><su_optab><fcvt_target><VDQF:mode>2): Likewise.
* config/aarch64/aarch64.c (TARGET_VECTORIZE_BUILTINS): Define.
(TARGET_VECTORIZE_BUILTIN_VECTORIZED_FUNCTION): Likewise.
* config/aarch64/aarch64.md
(btrunc<mode>2, ceil<mode>2, floor<mode>2)
(round<mode>2, rint<mode>2, nearbyint<mode>2): Consolidate as...
(<frint_pattern><mode>2): ...this.
(lceil<su_optab><mode><mode>2, lfloor<su_optab><mode><mode>2)
(lround<su_optab><mode><mode>2)
(lrint<su_optab><mode><mode>2): Consolidate as...
(l<fcvt_pattern><su_optab><GPF:mode><GPI:mode>2): ... this.
* config/aarch64/iterators.md (fcvt_target): New.
(FCVT_TARGET): Likewise.
(FRINT): Likewise.
(FCVT): Likewise.
(frint_pattern): Likewise.
(frint_suffix): Likewise.
(fcvt_pattern): Likewise.
gcc/testsuite/
* gcc.dg/vect/vect-rounding-btrunc.c: New test.
* gcc.dg/vect/vect-rounding-btruncf.c: Likewise.
* gcc.dg/vect/vect-rounding-ceil.c: Likewise.
* gcc.dg/vect/vect-rounding-ceilf.c: Likewise.
* gcc.dg/vect/vect-rounding-floor.c: Likewise.
* gcc.dg/vect/vect-rounding-floorf.c: Likewise.
* gcc.dg/vect/vect-rounding-lceil.c: Likewise.
* gcc.dg/vect/vect-rounding-lfloor.c: Likewise.
* gcc.dg/vect/vect-rounding-nearbyint.c: Likewise.
* gcc.dg/vect/vect-rounding-nearbyintf.c: Likewise.
* gcc.dg/vect/vect-rounding-round.c: Likewise.
* gcc.dg/vect/vect-rounding-roundf.c: Likewise.
* target-supports.exp
(check_effective_target_vect_call_btrunc): New.
(check_effective_target_vect_call_btruncf): Likewise.
(check_effective_target_vect_call_ceil): Likewise.
(check_effective_target_vect_call_ceilf): Likewise.
(check_effective_target_vect_call_floor): Likewise.
(check_effective_target_vect_call_floorf): Likewise.
(check_effective_target_vect_call_lceil): Likewise.
(check_effective_target_vect_call_lfloor): Likewise.
(check_effective_target_vect_call_nearbyint): Likewise.
(check_effective_target_vect_call_nearbyintf): Likewise.
(check_effective_target_vect_call_round): Likewise.
(check_effective_target_vect_call_roundf): Likewise.
From-SVN: r194197
2012-12-05 11:34:31 +01:00
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#undef AARCH64_CHECK_BUILTIN_MODE
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#undef AARCH64_FIND_FRINT_VARIANT
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2013-04-22 14:46:38 +02:00
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#undef CF0
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#undef CF1
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#undef CF2
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#undef CF3
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#undef CF4
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#undef CF10
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#undef VAR1
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#undef VAR2
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#undef VAR3
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#undef VAR4
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#undef VAR5
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#undef VAR6
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#undef VAR7
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#undef VAR8
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#undef VAR9
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#undef VAR10
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#undef VAR11
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2014-11-12 00:40:03 +01:00
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#include "gt-aarch64-builtins.h"
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