110d61da1d
[AArch64] Removed unused VRL2/3/4 iterator values
...
* config/aarch64/iterators.md (VRL2, VRL3, VRL4): Remove values for
128-bit vector modes.
From-SVN: r226408
2015-07-30 16:04:08 +00:00
c2ec330c9a
[AArch64] Add basic FP16 support
...
gcc/:
* config/aarch64/aarch64-builtins.c (aarch64_fp16_type_node): New.
(aarch64_init_builtins): Make aarch64_fp16_type_node, use for __fp16.
* config/aarch64/aarch64-modes.def: Add HFmode.
* config/aarch64/aarch64.h (TARGET_CPU_CPP_BUILTINS): Define
__ARM_FP16_FORMAT_IEEE and __ARM_FP16_ARGS. Set bit 1 of __ARM_FP.
* config/aarch64/aarch64.c (aarch64_init_libfuncs,
aarch64_promoted_type): New.
(aarch64_float_const_representable_p): Disable HFmode.
(aarch64_mangle_type): Mangle half-precision floats to "Dh".
(TARGET_PROMOTED_TYPE): Define to aarch64_promoted_type.
(TARGET_INIT_LIBFUNCS): Define to aarch64_init_libfuncs.
* config/aarch64/aarch64.md (mov<mode>): Include HFmode using GPF_F16.
(movhf_aarch64, extendhfsf2, extendhfdf2, truncsfhf2, truncdfhf2): New.
* config/aarch64/iterators.md (GPF_F16): New.
gcc/testsuite/:
* gcc.target/aarch64/f16_movs_1.c: New test.
From-SVN: r226346
2015-07-29 12:27:05 +00:00
1b1e81f847
[AArch64][2/2] Implement -fpic for -mcmodel=small
...
2015-06-26 Jiong Wang <jiong.wang@arm.com>
gcc/
* config/aarch64/aarch64-protos.h (aarch64_symbol_type): New type
SYMBOL_SMALL_GOT_28K.
* config/aarch64/aarch64.md: (ldr_got_small_<mode>): Support new GOT
relocation modifiers.
(unspec): New enum "UNSPEC_GOTMALLPIC28K.
(ldr_got_small_28k_<mode>): New.
(ldr_got_small_28k_sidi): New.
* config/aarch64/iterators.md (got_modifier): New mode iterator.
* config/aarch64/aarch64-otps.h (aarch64_code_model): New model.
* config/aarch64/aarch64.c (aarch64_load_symref_appropriately): Support
SYMBOL_SMALL_GOT_28K.
(aarch64_rtx_costs): Add costs for new instruction sequences.
(initialize_aarch64_code_model): Initialize new model.
(aarch64_classify_symbol): Recognize new model and new symbol classification.
(aarch64_asm_preferred_eh_data_format): Support new model.
(aarch64_load_symref_appropriately): Generate new instruction
sequences for -fpic.
(TARGET_USE_PSEUDO_PIC_REG): New definition.
(aarch64_use_pseudo_pic_reg): New function.
gcc/testsuite/
* gcc.target/aarch64/pic-small.c: New testcase.
From-SVN: r225017
2015-06-26 14:00:56 +00:00
9c004c58b3
[PATCH][AARCH64]Define vec_shr as an unspec, use shl for big-endian.
...
gcc/
2015-04-30 Renlin Li <renlin.li@arm.com>
* config/aarch64/aarch64-simd.md (vec_shr): Defined as an unspec.
* config/aarch64/iterators.md (unspec): Add UNSPEC_VEC_SHR.
gcc/testsuite/
2015-04-30 Renlin Li <renlin.li@arm.com>
Alan Lawrence <alan.lawrence@arm.com>
* gcc.target/aarch64/vect-reduc-or_1.c: New.
From-SVN: r222635
2015-04-30 15:52:24 +00:00
285398d2db
[Patch AArch64] Make integer vabs intrinsics UNSPECs
...
gcc/
* config/aarch64/aarch64-simd.md (aarch64_abs<mode>): New.
* config/aarch64/aarch64-simd-builtins.def (abs): Split by
integer and floating point variants.
* config/aarch64/iterators.md (unspec): Add UNSPEC_ABS.
gcc/testsuite/
* gcc.target/aarch64/abs_2.c: New.
From-SVN: r220202
2015-01-28 10:08:57 +00:00
096e8448ca
[AArch64] Improve bit-test-branch pattern to avoid unnecessary register clobber
...
2015-01-27 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
Jiong Wang <jiong.wang@arm.com>
gcc/
* config/aarch64/aarch64.md (tb<optab><mode>1): Clobber CC reg instead of
scratch reg.
(cb<optab><mode>1): Likewise.
* config/aarch64/iterators.md (bcond): New define_code_attr.
gcc/testsuite/
* gcc.dg/long_branch.c: New testcase.
From-SVN: r220170
2015-01-27 15:20:14 +00:00
668046d175
gcc/
...
2015-01-21 David Sherwood <david.sherwood@arm.com>
Tejas Belagod <Tejas.Belagod@arm.com>
* config/aarch64/aarch64-protos.h (aarch64_simd_attr_length_rglist)
(aarch64_reverse_mask): New decls.
* config/aarch64/iterators.md (UNSPEC_REV_REGLIST): New enum.
(insn_count): New mode_attr.
* config/aarch64/aarch64-simd.md (vec_store_lanesoi, vec_store_lanesci)
(vec_store_lanesxi, vec_load_lanesoi, vec_load_lanesci)
(vec_load_lanesxi): Made ABI compliant for Big Endian targets.
(aarch64_rev_reglist, aarch64_simd_ld2, aarch64_simd_ld3)
(aarch64_simd_ld4, aarch64_simd_st2, aarch64_simd_st3)
(aarch64_simd_st4): New patterns.
* config/aarch64/aarch64.c (aarch64_simd_attr_length_rglist)
(aarch64_reverse_mask): New functions.
Co-Authored-By: Tejas Belagod <tejas.belagod@arm.com>
From-SVN: r219959
2015-01-21 17:53:44 +00:00
5624e564d2
Update copyright years.
...
From-SVN: r219188
2015-01-05 13:33:28 +01:00
84be603271
[AArch64 3/3] Fix XOR_one_cmpl pattern; add SIMD-reg variants for BIC,ORN,EON
...
gcc/:
* config/aarch64/aarch64.c (<LOGICAL:optab>_one_cmpl<mode>3):
Reparameterize to...
(<NLOGICAL:optab>_one_cmpl<mode>3): with extra SIMD-register variant.
(xor_one_cmpl<mode>3): New define_insn_and_split.
* config/aarch64/iterators.md (NLOGICAL): New define_code_iterator.
gcc/testsuite/:
* gcc.target/aarch64/eon_1.c: New test.
From-SVN: r218961
2014-12-19 17:59:23 +00:00
fe82d1f27e
[AArch64 2/3] Add SIMD-reg variants of logical operators and/ior/xor/not
...
* config/aarch64/aarch64.md (<optab><mode>3, one_cmpl<mode>2):
Add SIMD-register variant.
* config/aarch64/iterators.md (Vbtype): Add value for SI.
From-SVN: r218960
2014-12-19 17:48:15 +00:00
58a3bd25ba
arm_neon.h (vrecpe_u32, [...]): Rewrite using builtin functions.
...
* config/aarch64/arm_neon.h (vrecpe_u32, vrecpeq_u32): Rewrite using
builtin functions.
(vfma_f32, vfmaq_f32, vfmaq_f64, vfma_n_f32, vfmaq_n_f32, vfmaq_n_f64,
vfms_f32, vfmsq_f32, vfmsq_f64): Likewise.
(vhsub_s8, vhsub_u8, vhsub_s16, vhsub_u16, vhsub_s32, vhsub_u32,
vhsubq_s8, vhsubq_u8, vhsubq_s16, vhsubq_u16, vhsubq_s32, vhsubq_u32,
vsubhn_s16, vsubhn_u16, vsubhn_s32, vsubhn_u32, vsubhn_s64, vsubhn_u66,
vrsubhn_s16, vrsubhn_u16, vrsubhn_s32, vrsubhn_u32, vrsubhn_s64,
vrsubhn_u64, vsubhn_high_s16, vsubhn_high_u16, vsubhn_high_s32,
vsubhn_high_u32, vsubhn_high_s64, vsubhn_high_u64, vrsubhn_high_s16,
vrsubhn_high_u16, vrsubhn_high_s32, vrsubhn_high_u32, vrsubhn_high_s64,
vrsubhn_high_u64): Likewise.
* config/aarch64/iterators.md (VDQ_SI): New mode iterator.
* config/aarch64/aarch64.md (define_c_enum "unspec"): Add UNSPEC_URECPE.
* config/aarch64/aarch64-simd.md (aarch64_urecpe<mode>): New pattern.
* config/aarch64/aarch64-simd-builtins.def (shsub, uhsub, subhn, rsubhn,
subhn2, rsubhn2, urecpe): New builtins.
Co-Authored-By: Haijian Zhang <z.zhanghaijian@huawei.com>
Co-Authored-By: Jiji Jiang <jiangjiji@huawei.com>
Co-Authored-By: Pengfei Sui <suipengfei@huawei.com>
From-SVN: r218484
2014-12-08 14:19:44 +00:00
a844a69583
[AArch64] Remove/merge redundant iterators
...
* config/aarch64/aarch64-simd.md (aarch64_simd_dup<mode>, orn<mode>3,
bic<mode>3, add<mode>3, sub<mode>3, neg<mode>2, abs<mode>2, and<mode>3,
ior<mode>3, xor<mode>3, one_cmpl<mode>2,
aarch64_simd_lshr<mode> ,arch64_simd_ashr<mode>,
aarch64_simd_imm_shl<mode>, aarch64_simd_reg_sshl<mode>,
aarch64_simd_reg_shl<mode>_unsigned, aarch64_simd_reg_shr<mode>_signed,
ashl<mode>3, lshr<mode>3, ashr<mode>3, vashl<mode>3,
reduc_plus_scal_<mode>, aarch64_vcond_internal<mode><mode>,
vcondu<mode><mode>, aarch64_cm<optab><mode>, aarch64_cmtst<mode>):
Change VDQ to VDQ_I.
(mul<mode>3): Change VDQM to VDQ_BHSI.
(aarch64_simd_vec_set<mode>,vashr<mode>3, vlshr<mode>3, vec_set<mode>,
aarch64_mla<mode>, aarch64_mls<mode>, <su><maxmin><mode>3,
aarch64_<sur>h<addsub><mode>): Change VQ_S to VDQ_BHSI.
(*aarch64_<su>mlal<mode>, *aarch64_<su>mlsl<mode>,
aarch64_<ANY_EXTEND:su><ADDSUB:optab>l<mode>,
aarch64_<ANY_EXTEND:su><ADDSUB:optab>w<mode>, aarch64_<sur>shll_n<mode>):
Change VDW to VD_BHSI.
(*aarch64_combinez<mode>, *aarch64_combinez_be<mode>):
Change VDIC to VD_BHSI.
* config/aarch64/aarch64-simd-builtins.def (saddl, uaddl, ssubl, usubl,
saddw, uaddw, ssubw, usubw, shadd, uhadd, srhadd, urhadd, sshll_n,
ushll_n): Change BUILTIN_VDW to BUILTIN_VD_BHSI.
* config/aarch64/iterators.md (SDQ_I, VDQ, VQ_S, VSDQ_I_BHSI, VDQM, VDW,
VDIC, VDQQHS): Remove.
(Vwtype): Update comment (changing VDW to VD_BHSI).
From-SVN: r218310
2014-12-03 12:12:07 +00:00
5e32e83b6e
[AArch64] Add vector pattern for __builtin_ctz
...
gcc/
* config/aarch64/iterators.md (VS): New mode iterator.
(vsi2qi): New mode attribute.
(VSI2QI): Likewise.
* config/aarch64/aarch64-simd-builtins.def: New entry for ctz.
* config/aarch64/aarch64-simd.md (ctz<mode>2): New pattern for ctz.
* config/aarch64/aarch64-builtins.c
(aarch64_builtin_vectorized_function): Support BUILT_IN_CTZ.
gcc/testsuite/
* gcc.target/aarch64/vect_ctz_1.c: New testcase.
From-SVN: r217938
2014-11-21 16:56:21 +00:00
544009d369
aarch64-builtins.c (TYPES_CREATE): Remove.
...
gcc/:
* config/aarch64/aarch64-builtins.c (TYPES_CREATE): Remove.
* config/aarch64/aarch64-simd-builtins.def (create): Remove.
* config/aarch64/aarch64-simd.md (aarch64_create<mode>): Remove.
* config/aarch64/arm_neon.h (vcreate_f64, vreinterpret_f64_s64,
vreinterpret_f64_u64): Replace __builtin_aarch64_createv1df with C casts.
* config/aarch64/iterators.md (VD1): Remove.
gcc/testsuite/:
* gcc.target/aarch64/simd/vfma_f64.c: Add asm volatile memory.
* gcc.target/aarch64/simd/vfms_f64.c: Likewise.
From-SVN: r217662
2014-11-17 18:07:45 +00:00
95d47b10be
[AArch64] Fix predicate and constraint mismatch in logical atomic operations
...
2014-11-04 Michael Collison <michael.collison@linaro.org>
* config/aarch64/iterators.md (lconst_atomic): New mode attribute
to support constraints for CONST_INT in atomic operations.
* config/aarch64/atomics.md
(atomic_<atomic_optab><mode>): Use lconst_atomic constraint.
(atomic_nand<mode>): Likewise.
(atomic_fetch_<atomic_optab><mode>): Likewise.
(atomic_fetch_nand<mode>): Likewise.
(atomic_<atomic_optab>_fetch<mode>): Likewise.
(atomic_nand_fetch<mode>): Likewise.
From-SVN: r217076
2014-11-04 12:23:10 +01:00
f5156c3ead
[AArch64] Use new reduc_plus_scal optabs, inc. for __builtins
...
* config/aarch64/aarch64-simd-builtins.def
(reduc_splus_<mode>/VDQF, reduc_uplus_<mode>/VDQF, reduc_splus_v4sf):
Remove.
(reduc_plus_scal_<mode>, reduc_plus_scal_v4sf): New.
* config/aarch64/aarch64-simd.md (reduc_<sur>plus_mode): Remove.
(reduc_splus_<mode>, reduc_uplus_<mode>, reduc_plus_scal_<mode>): New.
(reduc_<sur>plus_mode): Change SUADDV -> UNSPEC_ADDV, rename to...
(aarch64_reduc_plus_internal<mode>): ...this.
(reduc_<sur>plus_v2si): Change SUADDV -> UNSPEC_ADDV, rename to...
(aarch64_reduc_plus_internalv2si): ...this.
(reduc_splus_<mode>/V2F): Rename to...
(aarch64_reduc_plus_internal<mode>): ...this.
* config/aarch64/iterators.md
(UNSPEC_SADDV, UNSPEC_UADDV, SUADDV): Remove.
(UNSPEC_ADDV): New.
(sur): Remove elements for UNSPEC_SADDV and UNSPEC_UADDV.
* config/aarch64/arm_neon.h (vaddv_s8, vaddv_s16, vaddv_s32, vaddv_u8,
vaddv_u16, vaddv_u32, vaddvq_s8, vaddvq_s16, vaddvq_s32, vaddvq_s64,
vaddvq_u8, vaddvq_u16, vaddvq_u32, vaddvq_u64, vaddv_f32, vaddvq_f32,
vaddvq_f64): Change __builtin_aarch64_reduc_[us]plus_... to
__builtin_aarch64_reduc_plus_scal, remove vget_lane wrapper.
From-SVN: r216738
2014-10-27 15:20:18 +00:00
cb23a30cc4
[AArch64] Tighten predicates on SIMD shift intrinsics
...
gcc/
* config/aarch64/aarch64-protos.h (aarch64_simd_const_bounds): Delete.
* config/aarch64/aarch64-simd.md (aarch64_<sur>q<r>shl<mode>): Use
new predicates.
(aarch64_<sur>shll2_n<mode>): Likewise.
(aarch64_<sur>shr_n<mode>): Likewise.
(aarch64_<sur>sra_n<mode>: Likewise.
(aarch64_<sur>s<lr>i_n<mode>): Likewise.
(aarch64_<sur>qshl<u>_n<mode>): Likewise.
* config/aarch64/aarch64.c (aarch64_simd_const_bounds): Delete.
* config/aarch64/iterators.md (ve_mode): New.
(offsetlr): Remap to infix text for use in new predicates.
* config/aarch64/predicates.md (aarch64_simd_shift_imm_qi): New.
(aarch64_simd_shift_imm_hi): Likewise.
(aarch64_simd_shift_imm_si): Likewise.
(aarch64_simd_shift_imm_di): Likewise.
(aarch64_simd_shift_imm_offset_qi): Likewise.
(aarch64_simd_shift_imm_offset_hi): Likewise.
(aarch64_simd_shift_imm_offset_si): Likewise.
(aarch64_simd_shift_imm_offset_di): Likewise.
(aarch64_simd_shift_imm_bitsize_qi): Likewise.
(aarch64_simd_shift_imm_bitsize_hi): Likewise.
(aarch64_simd_shift_imm_bitsize_si): Likewise.
(aarch64_simd_shift_imm_bitsize_di): Likewise.
gcc/testsuite/
* gcc.target/aarch64/simd/vqshlb_1.c: New.
From-SVN: r215612
2014-09-25 16:54:38 +00:00
f421c516aa
[AArch64] Auto-generate the "BUILTIN_" macros for aarch64-builtins.c
...
gcc/
* config/aarch64/geniterators.sh: New.
* config/aarch64/iterators.md (VDQF_DF): New.
* config/aarch64/t-aarch64: Generate aarch64-builtin-iterators.h.
* config/aarch64/aarch64-builtins.c (BUILTIN_*) Remove.
From-SVN: r215471
2014-09-22 16:24:57 +00:00
bc138f7bee
[AArch64] Simplify vreinterpret for float64x1_t using casts.
...
* config/aarch64/aarch64-builtins.c (aarch64_types_unop_su_qualifiers,
TYPES_REINTERP_SU, aarch64_types_unop_sp_qualifiers, TYPE_REINTERP_SP,
aarch64_types_unop_us_qualifiers, TYPES_REINTERP_US,
aarch64_types_unop_ps_qualifiers, TYPES_REINTERP_PS, BUILTIN_VD):
Delete.
(aarch64_fold_builtin): Remove all reinterpret cases.
* config/aarch64/aarch64-protos.h (aarch64_simd_reinterpret): Delete.
* config/aarch64/aarch64-simd-builtins.def (reinterpret*) : Delete.
* config/aarch64/aarch64-simd.md (aarch64_reinterpretv8qi<mode>,
aarch64_reinterpretv4hi<mode>, aarch64_reinterpretv2si<mode>,
aarch64_reinterpretv2sf<mode>, aarch64_reinterpretdi<mode>,
aarch64_reinterpretv1df<mode>, aarch64_reinterpretv16qi<mode>,
aarch64_reinterpretv8hi<mode>, aarch64_reinterpretv4si<mode>,
aarch64_reinterpretv4sf<mode>, aarch64_reinterpretv2di<mode>,
aarch64_reinterpretv2df<mode>): Delete.
* config/aarch64/aarch64.c (aarch64_simd_reinterpret): Delete.
* config/aarch64/arm_neon.h (vreinterpret_p8_f64,
vreinterpret_p16_f64, vreinterpret_f32_f64, vreinterpret_f64_f32,
vreinterpret_f64_p8, vreinterpret_f64_p16, vreinterpret_f64_s8,
vreinterpret_f64_s16, vreinterpret_f64_s32, vreinterpret_f64_u8,
vreinterpret_f64_u16, vreinterpret_f64_u32, vreinterpret_s64_f64,
vreinterpret_u64_f64, vreinterpret_s8_f64, vreinterpret_s16_f64,
vreinterpret_s32_f64, vreinterpret_u8_f64, vreinterpret_u16_f64,
vreinterpret_u32_f64): Use cast.
* config/aarch64/iterators.md (VD_RE): Delete.
From-SVN: r215180
2014-09-11 16:16:24 +00:00
5143726943
re PR target/62040 (internal compiler error: in simplify_const_unary_operation, at simplify-rtx.c:1555)
...
PR target/62040
* config/aarch64/iterators.md (VQ_NO2E, VQ_2E): New iterators.
* config/aarch64/aarch64-simd.md (move_lo_quad_internal_<mode>): Split
it into two patterns.
(move_lo_quad_internal_be_<mode>): Likewise.
* gcc.target/aarch64/pr62040.c: New test.
From-SVN: r214905
2014-09-04 16:06:13 +00:00
c6a29a091a
PR/60825 Make float64x1_t in arm_neon.h a proper vector type
...
gcc/ChangeLog:
PR target/60825
* config/aarch64/aarch64.c (aarch64_simd_mangle_map): Add entry for
V1DFmode.
* config/aarch64/aarch64-builtins.c (aarch64_simd_builtin_type_mode):
add V1DFmode
(BUILTIN_VD1): New.
(BUILTIN_VD_RE): Remove.
(aarch64_init_simd_builtins): Add V1DF to modes/modenames.
(aarch64_fold_builtin): Update reinterpret patterns, df becomes v1df.
* config/aarch64/aarch64-simd-builtins.def (create): Make a v1df
variant but not df.
(vreinterpretv1df*, vreinterpret*v1df): New.
(vreinterpretdf*, vreinterpret*df): Remove.
* config/aarch64/aarch64-simd.md (aarch64_create, aarch64_reinterpret*):
Generate V1DFmode pattern not DFmode.
* config/aarch64/iterators.md (VD_RE): Include V1DF, remove DF.
(VD1): New.
* config/aarch64/arm_neon.h (float64x1_t): typedef with gcc extensions.
(vcreate_f64): Remove cast, use v1df builtin.
(vcombine_f64): Remove cast, get elements with gcc vector extensions.
(vget_low_f64, vabs_f64, vceq_f64, vceqz_f64, vcge_f64, vgfez_f64,
vcgt_f64, vcgtz_f64, vcle_f64, vclez_f64, vclt_f64, vcltz_f64,
vdup_n_f64, vdupq_lane_f64, vld1_f64, vld2_f64, vld3_f64, vld4_f64,
vmov_n_f64, vst1_f64): Use gcc vector extensions.
(vget_lane_f64, vdupd_lane_f64, vmulq_lane_f64, ): Use gcc extensions,
add range check using __builtin_aarch64_im_lane_boundsi.
(vfma_lane_f64, vfmad_lane_f64, vfma_laneq_f64, vfmaq_lane_f64,
vfms_lane_f64, vfmsd_lane_f64, vfms_laneq_f64, vfmsq_lane_f64): Fix
type signature, use gcc vector extensions.
(vreinterpret_p8_f64, vreinterpret_p16_f64, vreinterpret_f32_f64,
vreinterpret_f64_f32, vreinterpret_f64_p8, vreinterpret_f64_p16,
vreinterpret_f64_s8, vreinterpret_f64_s16, vreinterpret_f64_s32,
vreinterpret_f64_s64, vreinterpret_f64_u8, vreinterpret_f64_u16,
vreinterpret_f64_u32, vreinterpret_f64_u64, vreinterpret_s8_f64,
vreinterpret_s16_f64, vreinterpret_s32_f64, vreinterpret_s64_f64,
vreinterpret_u8_f64, vreinterpret_u16_f64, vreinterpret_u32_f64,
vreinterpret_u64_f64): Use v1df builtin not df.
gcc/testsuite/ChangeLog:
* g++.dg/abi/mangle-neon-aarch64.C: Also test mangling of float64x1_t.
* gcc.target/aarch64/aapcs/test_64x1_1.c: New test.
* gcc.target/aarch64/aapcs/func-ret-64x1_1.c: New test.
* gcc.target/aarch64/simd/ext_f64_1.c (main): Compare vector elements.
* gcc.target/aarch64/vadd_f64.c: Rewrite with macro to use vector types.
* gcc.target/aarch64/vsub_f64.c: Likewise.
* gcc.target/aarch64/vdiv_f.c (INDEX*, RUN_TEST): Remove indexing scheme
as now the same for all variants.
* gcc.target/aarch64/vrnd_f64_1.c (compare_f64): Return float64_t not
float64x1_t.
From-SVN: r211892
2014-06-23 12:46:52 +00:00
278821f265
[AArch64] Fix some saturating math NEON intrinsics types.
...
[gcc/]
* config/aarch64/iterators.md (VCOND): Handle SI and HI modes.
Update comments.
(VCONQ): Make comment more helpful.
(VCON): Delete.
* config/aarch64/aarch64-simd.md
(aarch64_sqdmulh_lane<mode>):
Use VCOND for operands 2. Update lane checking and flipping logic.
(aarch64_sqrdmulh_lane<mode>): Likewise.
(aarch64_sq<r>dmulh_lane<mode>_internal): Likewise.
(aarch64_sqdmull2<mode>): Remove VCON, use VQ_HSI mode iterator.
(aarch64_sqdml<SBINQOPS:as>l_lane<mode>_internal, VD_HSI): Change mode
attribute of operand 3 to VCOND.
(aarch64_sqdml<SBINQOPS:as>l_lane<mode>_internal, SD_HSI): Likewise.
(aarch64_sqdml<SBINQOPS:as>l2_lane<mode>_internal): Likewise.
(aarch64_sqdmull_lane<mode>_internal, VD_HSI): Likewise.
(aarch64_sqdmull_lane<mode>_internal, SD_HSI): Likewise.
(aarch64_sqdmull2_lane<mode>_internal): Likewise.
(aarch64_sqdml<SBINQOPS:as>l_laneq<mode>_internal, VD_HSI: New
define_insn.
(aarch64_sqdml<SBINQOPS:as>l_laneq<mode>_internal, SD_HSI): Likewise.
(aarch64_sqdml<SBINQOPS:as>l2_laneq<mode>_internal): Likewise.
(aarch64_sqdmull_laneq<mode>_internal, VD_HSI): Likewise.
(aarch64_sqdmull_laneq<mode>_internal, SD_HSI): Likewise.
(aarch64_sqdmull2_laneq<mode>_internal): Likewise.
(aarch64_sqdmlal_lane<mode>): Change mode attribute of penultimate
operand to VCOND. Update lane flipping and bounds checking logic.
(aarch64_sqdmlal2_lane<mode>): Likewise.
(aarch64_sqdmlsl_lane<mode>): Likewise.
(aarch64_sqdmull_lane<mode>): Likewise.
(aarch64_sqdmull2_lane<mode>): Likewise.
(aarch64_sqdmlal_laneq<mode>):
Replace VCON usage with VCONQ.
Emit aarch64_sqdmlal_laneq<mode>_internal insn.
(aarch64_sqdmlal2_laneq<mode>): Emit
aarch64_sqdmlal2_laneq<mode>_internal insn.
Replace VCON with VCONQ.
(aarch64_sqdmlsl2_lane<mode>): Replace VCON with VCONQ.
(aarch64_sqdmlsl2_laneq<mode>): Likewise.
(aarch64_sqdmull_laneq<mode>): Emit
aarch64_sqdmull_laneq<mode>_internal insn.
Replace VCON with VCONQ.
(aarch64_sqdmull2_laneq<mode>): Emit
aarch64_sqdmull2_laneq<mode>_internal insn.
(aarch64_sqdmlsl_laneq<mode>): Replace VCON usage with VCONQ.
* config/aarch64/arm_neon.h (vqdmlal_high_lane_s16): Change type
of 3rd argument to int16x4_t.
(vqdmlalh_lane_s16): Likewise.
(vqdmlslh_lane_s16): Likewise.
(vqdmull_high_lane_s16): Likewise.
(vqdmullh_lane_s16): Change type of 2nd argument to int16x4_t.
(vqdmlal_lane_s16): Don't create temporary int16x8_t value.
(vqdmlsl_lane_s16): Likewise.
(vqdmull_lane_s16): Don't create temporary int16x8_t value.
(vqdmlal_high_lane_s32): Change type 3rd argument to int32x2_t.
(vqdmlals_lane_s32): Likewise.
(vqdmlsls_lane_s32): Likewise.
(vqdmull_high_lane_s32): Change type 2nd argument to int32x2_t.
(vqdmulls_lane_s32): Likewise.
(vqdmlal_lane_s32): Don't create temporary int32x4_t value.
(vqdmlsl_lane_s32): Likewise.
(vqdmull_lane_s32): Don't create temporary int32x4_t value.
(vqdmulhh_lane_s16): Change type of second argument to int16x4_t.
(vqrdmulhh_lane_s16): Likewise.
(vqdmlsl_high_lane_s16): Likewise.
(vqdmulhs_lane_s32): Change type of second argument to int32x2_t.
(vqdmlsl_high_lane_s32): Likewise.
(vqrdmulhs_lane_s32): Likewise.
[gcc/testsuite]
* gcc.target/aarch64/simd/vqdmulhh_lane_s16.c: New test.
* gcc.target/aarch64/simd/vqdmulhs_lane_s32.c: Likewise.
* gcc.target/aarch64/simd/vqrdmulhh_lane_s16.c: Likewise.
* gcc.target/aarch64/simd/vqrdmulhs_lane_s32.c: Likewise.
* gcc.target/aarch64/simd/vqdmlal_high_lane_s16.c: New test.
* gcc.target/aarch64/simd/vqdmlal_high_lane_s32.c: Likewise.
* gcc.target/aarch64/simd/vqdmlal_high_laneq_s16.c: Likewise.
* gcc.target/aarch64/simd/vqdmlal_high_laneq_s32.c: Likewise.
* gcc.target/aarch64/simd/vqdmlal_lane_s16.c: Likewise.
* gcc.target/aarch64/simd/vqdmlal_lane_s32.c: Likewise.
* gcc.target/aarch64/simd/vqdmlal_laneq_s16.c: Likewise.
* gcc.target/aarch64/simd/vqdmlal_laneq_s32.c: Likewise.
* gcc.target/aarch64/simd/vqdmlalh_lane_s16.c: Likewise.
* gcc.target/aarch64/simd/vqdmlals_lane_s32.c: Likewise.
* gcc.target/aarch64/simd/vqdmlsl_high_lane_s16.c: Likewise.
* gcc.target/aarch64/simd/vqdmlsl_high_lane_s32.c: Likewise.
* gcc.target/aarch64/simd/vqdmlsl_high_laneq_s16.c: Likewise.
* gcc.target/aarch64/simd/vqdmlsl_high_laneq_s32.c: Likewise.
* gcc.target/aarch64/simd/vqdmlsl_lane_s16.c: Likewise.
* gcc.target/aarch64/simd/vqdmlsl_lane_s32.c: Likewise.
* gcc.target/aarch64/simd/vqdmlsl_laneq_s32.c: Likewise.
* gcc.target/aarch64/simd/vqdmlslh_lane_s16.c: Likewise.
* gcc.target/aarch64/simd/vqdmlsls_lane_s32.c: Likewise.
* gcc.target/aarch64/simd/vqdmulh_laneq_s16.c: Likewise.
* gcc.target/aarch64/simd/vqdmulh_laneq_s32.c: Likewise.
* gcc.target/aarch64/simd/vqdmulhq_laneq_s16.c: Likewise.
* gcc.target/aarch64/simd/vqdmulhq_laneq_s32.c: Likewise.
* gcc.target/aarch64/simd/vqdmull_high_lane_s16.c: Likewise.
* gcc.target/aarch64/simd/vqdmull_high_lane_s32.c: Likewise.
* gcc.target/aarch64/simd/vqdmull_high_laneq_s16.c: Likewise.
* gcc.target/aarch64/simd/vqdmull_high_laneq_s32.c: Likewise.
* gcc.target/aarch64/simd/vqdmull_lane_s16.c: Likewise.
* gcc.target/aarch64/simd/vqdmull_lane_s32.c: Likewise.
* gcc.target/aarch64/simd/vqdmull_laneq_s16.c: Likewise.
* gcc.target/aarch64/simd/vqdmull_laneq_s32.c: Likewise.
* gcc.target/aarch64/simd/vqdmullh_lane_s16.c: Likewise.
* gcc.target/aarch64/simd/vqdmulls_lane_s32.c: Likewise.
* gcc.target/aarch64/simd/vqrdmulh_laneq_s16.c: Likewise.
* gcc.target/aarch64/simd/vqrdmulh_laneq_s32.c: Likewise.
* gcc.target/aarch64/simd/vqrdmulhq_laneq_s16.c: Likewise.
* gcc.target/aarch64/simd/vqrdmulhq_laneq_s32.c: Likewise.
* gcc.target/aarch64/vector_intrinsics.c: Simplify arm_neon.h include.
(test_vqdmlal_high_lane_s16): Fix parameter type.
(test_vqdmlal_high_lane_s32): Likewise.
(test_vqdmull_high_lane_s16): Likewise.
(test_vqdmull_high_lane_s32): Likewise.
(test_vqdmlsl_high_lane_s32): Likewise.
(test_vqdmlsl_high_lane_s16): Likewise.
* gcc.target/aarch64/scalar_intrinsics.c (test_vqdmlalh_lane_s16):
Fix argument type.
(test_vqdmlals_lane_s32): Likewise.
(test_vqdmlslh_lane_s16): Likewise.
(test_vqdmlsls_lane_s32): Likewise.
(test_vqdmulhh_lane_s16): Likewise.
(test_vqdmulhs_lane_s32): Likewise.
(test_vqdmullh_lane_s16): Likewise.
(test_vqdmulls_lane_s32): Likewise.
(test_vqrdmulhh_lane_s16): Likewise.
(test_vqrdmulhs_lane_s32): Likewise.
From-SVN: r211842
2014-06-20 08:51:34 +00:00
5d357f260c
[AArch64] Implement CRC32 ACLE intrinsics.
...
* config.gcc (aarch64*-*-*): Add arm_acle.h to extra headers.
* Makefile.in (TEXI_GCC_FILES): Add aarch64-acle-intrinsics.texi to
dependencies.
* config/aarch64/aarch64-builtins.c (AARCH64_CRC32_BUILTINS): Define.
(aarch64_crc_builtin_datum): New struct.
(aarch64_crc_builtin_data): New.
(aarch64_init_crc32_builtins): New function.
(aarch64_init_builtins): Initialise CRC32 builtins when appropriate.
(aarch64_crc32_expand_builtin): New.
(aarch64_expand_builtin): Add CRC32 builtin expansion case.
* config/aarch64/aarch64.h (TARGET_CPU_CPP_BUILTINS): Define
__ARM_FEATURE_CRC32 when appropriate.
(TARGET_CRC32): Define.
* config/aarch64/aarch64.md (UNSPEC_CRC32B, UNSPEC_CRC32H,
UNSPEC_CRC32W, UNSPEC_CRC32X, UNSPEC_CRC32CB, UNSPEC_CRC32CH,
UNSPEC_CRC32CW, UNSPEC_CRC32CX): New unspec values.
(aarch64_<crc_variant>): New pattern.
* config/aarch64/arm_acle.h: New file.
* config/aarch64/iterators.md (CRC): New int iterator.
(crc_variant, crc_mode): New int attributes.
* doc/aarch64-acle-intrinsics.texi: New file.
* doc/extend.texi (aarch64): Document aarch64 ACLE intrinsics.
Include aarch64-acle-intrinsics.texi.
From-SVN: r211440
2014-06-11 09:17:18 +00:00
923fcec3d8
Recognize shuffle patterns for REV instructions on AArch64, rewrite intrinsics.
...
* config/aarch64/aarch64-simd.md (aarch64_rev<REVERSE:rev-op><mode>):
New pattern.
* config/aarch64/aarch64.c (aarch64_evpc_rev): New function.
(aarch64_expand_vec_perm_const_1): Add call to aarch64_evpc_rev.
* config/aarch64/iterators.md (REVERSE): New iterator.
(UNSPEC_REV64, UNSPEC_REV32, UNSPEC_REV16): New enum elements.
(rev_op): New int_attribute.
* config/aarch64/arm_neon.h (vrev16_p8, vrev16_s8, vrev16_u8,
vrev16q_p8, vrev16q_s8, vrev16q_u8, vrev32_p8, vrev32_p16, vrev32_s8,
vrev32_s16, vrev32_u8, vrev32_u16, vrev32q_p8, vrev32q_p16, vrev32q_s8,
vrev32q_s16, vrev32q_u8, vrev32q_u16, vrev64_f32, vrev64_p8,
vrev64_p16, vrev64_s8, vrev64_s16, vrev64_s32, vrev64_u8, vrev64_u16,
vrev64_u32, vrev64q_f32, vrev64q_p8, vrev64q_p16, vrev64q_s8,
vrev64q_s16, vrev64q_s32, vrev64q_u8, vrev64q_u16, vrev64q_u32):
Replace temporary __asm__ with __builtin_shuffle.
From-SVN: r211174
2014-06-03 11:28:55 +00:00
ae0533da54
Detect EXT patterns to vec_perm_const, use for EXT intrinsics
...
* config/aarch64/aarch64-builtins.c (aarch64_types_binopv_qualifiers,
TYPES_BINOPV): New static data.
* config/aarch64/aarch64-simd-builtins.def (im_lane_bound): New builtin.
* config/aarch64/aarch64-simd.md (aarch64_ext, aarch64_im_lane_boundsi):
New patterns.
* config/aarch64/aarch64.c (aarch64_expand_vec_perm_const_1): Match
patterns for EXT.
(aarch64_evpc_ext): New function.
* config/aarch64/iterators.md (UNSPEC_EXT): New enum element.
* config/aarch64/arm_neon.h (vext_f32, vext_f64, vext_p8, vext_p16,
vext_s8, vext_s16, vext_s32, vext_s64, vext_u8, vext_u16, vext_u32,
vext_u64, vextq_f32, vextq_f64, vextq_p8, vextq_p16, vextq_s8,
vextq_s16, vextq_s32, vextq_s64, vextq_u8, vextq_u16, vextq_u32,
vextq_u64): Replace __asm with __builtin_shuffle and im_lane_boundsi.
From-SVN: r211058
2014-05-29 16:57:42 +00:00
ba081b77be
[AArch64] Improve vst4_lane intrinsics
...
gcc/
* config/aarch64/aarch64-builtins.c
(aarch64_types_storestruct_lane_qualifiers): New.
(TYPES_STORESTRUCT_LANE): Likewise.
* config/aarch64/aarch64-simd-builtins.def (st2_lane): New.
(st3_lane): Likewise.
(st4_lane): Likewise.
* config/aarch64/aarch64-simd.md (vec_store_lanesoi_lane<mode>): New.
(vec_store_lanesci_lane<mode>): Likewise.
(vec_store_lanesxi_lane<mode>): Likewise.
(aarch64_st2_lane<VQ:mode>): Likewise.
(aarch64_st3_lane<VQ:mode>): Likewise.
(aarch64_st4_lane<VQ:mode>): Likewise.
* config/aarch64/aarch64.md (unspec): Add UNSPEC_ST{2,3,4}_LANE.
* config/aarch64/arm_neon.h
(__ST2_LANE_FUNC): Rewrite using builtins, update use points to
use new macro arguments.
(__ST3_LANE_FUNC): Likewise.
(__ST4_LANE_FUNC): Likewise.
* config/aarch64/iterators.md (V_TWO_ELEM): New.
(V_THREE_ELEM): Likewise.
(V_FOUR_ELEM): Likewise.
From-SVN: r209880
2014-04-28 21:05:51 +00:00
c7f28cd58e
[AArch64] Vectorise bswap[16,32,64]
...
* config/aarch64/aarch64-builtins.c
(aarch64_builtin_vectorized_function): Handle BUILT_IN_BSWAP16,
BUILT_IN_BSWAP32, BUILT_IN_BSWAP64.
* config/aarch64/aarch64-simd.md (bswap<mode>): New pattern.
* config/aarch64/aarch64-simd-builtins.def: Define vector bswap
builtins.
* config/aarch64/iterator.md (VDQHSD): New mode iterator.
(Vrevsuff): New mode attribute.
* lib/target-supports.exp (check_effective_target_vect_bswap): New.
* gcc.dg/vect/vect-bswap16: New test.
* gcc.dg/vect/vect-bswap32: Likewise.
* gcc.dg/vect/vect-bswap64: Likewise.
From-SVN: r209736
2014-04-24 08:05:07 +00:00
0d35c5c270
aarch64.md (float<GPI:mode><GPF:mode>2): Remove.
...
gcc/ChangeLog:
2014-04-22 Vidya Praveen <vidyapraveen@arm.com>
* aarch64.md (float<GPI:mode><GPF:mode>2): Remove.
(floatuns<GPI:mode><GPF:mode>2): Remove.
(<optab><fcvt_target><GPF:mode>2): New pattern for equal width float
and floatuns conversions.
(<optab><fcvt_iesize><GPF:mode>2): New pattern for inequal width float
and floatuns conversions.
* iterators.md (fcvt_target, FCVT_TARGET): Support SF and DF modes.
(w1,w2): New mode attributes for inequal width conversions.
gcc/testsuite/ChangeLog:
2014-04-22 Vidya Praveen <vidyapraveen@arm.com>
* gcc.target/aarch64/vect_cvtf_1.c: New.
From-SVN: r209620
2014-04-22 12:34:52 +01:00
23a5b65a92
Update copyright years in gcc/
...
From-SVN: r206289
2014-01-02 22:23:26 +00:00
7baa225d39
Implement support for AArch64 Crypto PMULL.64.
...
gcc/
* config/aarch64/aarch64-builtins.c (aarch64_init_simd_builtins):
Define builtin types for poly64_t poly128_t.
(TYPES_BINOPP, aarch64_types_binopp_qualifiers): New.
* aarch64/aarch64-simd-builtins.def: Update builtins table.
* config/aarch64/aarch64-simd.md (aarch64_crypto_pmulldi,
aarch64_crypto_pmullv2di): New.
* config/aarch64/aarch64.c (aarch64_simd_mangle_map): Update table for
poly64x2_t mangler.
* config/aarch64/arm_neon.h (poly64x2_t, poly64_t, poly128_t): Define.
(vmull_p64, vmull_high_p64): New.
* config/aarch64/iterators.md (UNSPEC_PMULL<2>): New.
testsuite/
* gcc.target/aarch64/pmull_1.c: New.
From-SVN: r206120
2013-12-19 15:04:19 +00:00
b9cb0a44c1
Implement support for AArch64 Crypto SHA256.
...
gcc/
* config/aarch64/aarch64-simd-builtins.def: Update builtins table.
* config/aarch64/aarch64-simd.md (aarch64_crypto_sha256h<sha256_op>v4si,
aarch64_crypto_sha256su0v4si, aarch64_crypto_sha256su1v4si): New.
* config/aarch64/arm_neon.h (vsha256hq_u32, vsha256h2q_u32,
vsha256su0q_u32, vsha256su1q_u32): New.
* config/aarch64/iterators.md (UNSPEC_SHA256H<2>, UNSPEC_SHA256SU<01>):
New.
(CRYPTO_SHA256): New int iterator.
(sha256_op): New int attribute.
testsuite/
* gcc.target/aarch64/sha256_1.c: New.
From-SVN: r206119
2013-12-19 15:00:53 +00:00
3044268251
Implement support for AArch64 Crypto SHA1.
...
gcc/
* config/aarch64/aarch64-simd-builtins.def: Update builtins table.
* config/aarch64/aarch64-builtins.c (aarch64_types_ternopu_qualifiers,
TYPES_TERNOPU): New.
* config/aarch64/aarch64-simd.md (aarch64_crypto_sha1hsi,
aarch64_crypto_sha1su1v4si, aarch64_crypto_sha1<sha1_op>v4si,
aarch64_crypto_sha1su0v4si): New.
* config/aarch64/arm_neon.h (vsha1cq_u32, sha1mq_u32, vsha1pq_u32,
vsha1h_u32, vsha1su0q_u32, vsha1su1q_u32): New.
* config/aarch64/iterators.md (UNSPEC_SHA1<CPMH>, UNSPEC_SHA1SU<01>):
New.
(CRYPTO_SHA1): New int iterator.
(sha1_op): New int attribute.
testsuite/
* gcc.target/aarch64/sha1_1.c: New.
From-SVN: r206118
2013-12-19 14:55:47 +00:00
5a7a4e8064
Implement support for AArch64 Crypto AES.
...
gcc/
* config/aarch64/aarch64-simd-builtins.def: Update builtins table.
* config/aarch64/aarch64-builtins.c (aarch64_types_binopu_qualifiers,
TYPES_BINOPU): New.
* config/aarch64/aarch64-simd.md (aarch64_crypto_aes<aes_op>v16qi,
aarch64_crypto_aes<aesmc_op>v16qi): New.
* config/aarch64/arm_neon.h (vaeseq_u8, vaesdq_u8, vaesmcq_u8,
vaesimcq_u8): New.
* config/aarch64/iterators.md (UNSPEC_AESE, UNSPEC_AESD, UNSPEC_AESMC,
UNSPEC_AESIMC): New.
(CRYPTO_AES, CRYPTO_AESMC): New int iterators.
(aes_op, aesmc_op): New int attributes.
testsuite/
* gcc.target/aarch64/aes_1.c: New.
From-SVN: r206117
2013-12-19 14:51:28 +00:00
46e778c4f5
[AArch64] [3/4 Fix vtbx1]Implement bsl intrinsics using builtins
...
gcc/
* config/aarch64/aarch64-builtins.c
(aarch64_types_bsl_p_qualifiers): New.
(aarch64_types_bsl_s_qualifiers): Likewise.
(aarch64_types_bsl_u_qualifiers): Likewise.
(TYPES_BSL_P): Likewise.
(TYPES_BSL_S): Likewise.
(TYPES_BSL_U): Likewise.
(BUILTIN_VALLDIF): Likewise.
(BUILTIN_VDQQH): Likewise.
* config/aarch64/aarch64-simd-builtins.def (simd_bsl): New.
* config/aarch64/aarch64-simd.md
(aarch64_simd_bsl<mode>_internal): Handle more modes.
(aarch64_simd_bsl<mode>): Likewise.
* config/aarch64/arm_neon.h
(vbsl<q>_<fpsu><8,16,32,64): Implement using builtins.
* config/aarch64/iterators.md (VALLDIF): New.
(Vbtype): Handle more modes.
From-SVN: r205385
2013-11-26 10:03:14 +00:00
928353177b
aarch64-simd.md (vec_pack_trunc_<mode>, [...]): Swap for big-endian.
...
2013-11-22 Tejas Belagod <tejas.belagod@arm.com>
gcc/
* config/aarch64/aarch64-simd.md (vec_pack_trunc_<mode>,
vec_pack_trunc_v2df, vec_pack_trunc_df): Swap for big-endian.
(reduc_<sur>plus_<mode>): Factorize V2DI into this.
(reduc_<sur>plus_<mode>): Change this to reduc_splus_<mode> for floats
and also change to float UNSPEC.
(reduc_maxmin_uns>_<mode>): Remove V2DI.
* config/aarch64/arm_neon.h (vaddv<q>_<suf><8,16,32,64>,
vmaxv<q>_<suf><8,16,32,64>, vminv<q>_<suf><8,16,32,64>): Fix up scalar
result access for big-endian.
(__LANE0): New macro used to fix up lane access of 'across-lanes'
intrinsics for big-endian.
* config/aarch64/iterators.md (VDQV): Add V2DI.
(VDQV_S): New.
(vp): New mode attribute.
From-SVN: r205269
2013-11-22 15:34:36 +00:00
0f686aa981
[AArch64] [Neon types 4/10] Add type attributes to all simd insns
...
gcc/
* config/aarch64/iterators.md (Vetype): Add SF and DF modes.
(fp): New.
* config/aarch64/aarch64-simd.md (neon_type): Remove.
* config/aarch64/aarch64-simd.md: Add "type" attribute to all
patterns.
From-SVN: r203614
2013-10-15 15:30:00 +00:00
a9e66678ca
[AArch64] [Neon types 2/10] Update Current type attributes to new Neon Types.
...
gcc/
* config/aarch64/aarch64.md (movtf_aarch64): Update type attribute.
(load_pair): Update type attribute.
(store_pair): Update type attribute.
* config/aarch64/iterators.md (q): New.
From-SVN: r203612
2013-10-15 15:26:15 +00:00
828e70c1d7
[AArch64] Improve arm_neon.h vml<as>_lane handling.
...
gcc/
* config/aarch64/aarch64-simd-builtins.def (fma): New.
* config/aarch64/aarch64-simd.md
(aarch64_mla_elt<mode>): New.
(aarch64_mla_elt_<vswap_width_name><mode>): Likewise.
(aarch64_mls_elt<mode>): Likewise.
(aarch64_mls_elt_<vswap_width_name><mode>): Likewise.
(aarch64_fma4_elt<mode>): Likewise.
(aarch64_fma4_elt_<vswap_width_name><mode>): Likewise.
(aarch64_fma4_elt_to_128v2df): Likewise.
(aarch64_fma4_elt_to_64df): Likewise.
(fnma<mode>4): Likewise.
(aarch64_fnma4_elt<mode>): Likewise.
(aarch64_fnma4_elt_<vswap_width_name><mode>): Likewise.
(aarch64_fnma4_elt_to_128v2df): Likewise.
(aarch64_fnma4_elt_to_64df): Likewise.
* config/aarch64/iterators.md (VDQSF): New.
* config/aarch64/arm_neon.h
(vfm<as><sdq>_lane<q>_f<32, 64>): Convert to C implementation.
(vml<sa><q>_lane<q>_<fsu><16, 32, 64>): Likewise.
gcc/testsuite/
* gcc.target/aarch64/fmla-intrinsic.c: New.
* gcc.target/aarch64/mla-intrinsic.c: Likewise.
* gcc.target/aarch64/fmls-intrinsic.c: Likewise.
* gcc.target/aarch64/mls-intrinsic.c: Likewise.
From-SVN: r202625
2013-09-16 09:53:11 +00:00
779aea46cc
[AArch64] Implement vmul<q>_lane<q>_<fsu><16,32,64> intrinsics in C
...
gcc/
* config/aarch64/aarch64-simd.md (aarch64_mul3_elt<mode>): New.
(aarch64_mul3_elt_<vswap_width_name><mode>): Likewise.
(aarch64_mul3_elt_to_128df): Likewise.
(aarch64_mul3_elt_to_64v2df): Likewise.
* config/aarch64/iterators.md (VEL): Also handle DFmode.
(VMUL): New.
(VMUL_CHANGE_NLANES) Likewise.
(h_con): Likewise.
(f): Likewise.
* config/aarch64/arm_neon.h
(vmul<q>_lane<q>_<suf><16,32,64>): Convert to C implementation.
gcc/testsuite/
* gcc.target/aarch64/mul_intrinsic_1.c: New.
* gcc.target/aarch64/fmul_intrinsic_1.c: Likewise.
From-SVN: r202624
2013-09-16 09:50:21 +00:00
91bd4114a7
[AArch64] Rewrite the vdup_lane intrinsics in C
...
gcc/
* config/aarch64/aarch64-simd-builtins.def
(dup_lane_scalar): Remove.
* config/aarch64/aarch64-simd.md
(aarch64_simd_dup): Add 'w->w' alternative.
(aarch64_dup_lane<mode>): Allow for VALL.
(aarch64_dup_lane_scalar<mode>): Remove.
(aarch64_dup_lane_<vswap_width_name><mode>): New.
(aarch64_get_lane_signed<mode>): Add w->w altenative.
(aarch64_get_lane_unsigned<mode>): Likewise.
(aarch64_get_lane<mode>): Likewise.
* config/aarch64/aarch64.c (aarch64_evpc_dup): New.
(aarch64_expand_vec_perm_const_1): Use aarch64_evpc_dup.
* config/aarch64/iterators.md (VSWAP_WIDTH): New.
(VCON): Change container of V2SF.
(vswap_width_name): Likewise.
* config/aarch64/arm_neon.h
(__aarch64_vdup_lane_any): New.
(__aarch64_vdup<q>_lane<q>_<fpsu><8,16,32,64>): Likewise.
(vdup<q>_n_<psuf><8,16,32,64>): Convert to C implementation.
(vdup<q>_lane<q>_<fpsu><8,16,32,64>): Likewise.
gcc/testsuite/
* gcc.target/aarch64/scalar_intrinsics.c
(vdup<bhsd>_lane<su><8,16,32,64>): Force values to SIMD registers.
From-SVN: r202180
2013-09-02 16:22:10 +00:00
66adb8eb44
[AArch64] Fixup the vget_lane RTL patterns and intrinsics
...
gcc/
* config/aarch64/aarch64-simd-builtins.def (get_lane_signed): Remove.
(get_lane_unsigned): Likewise.
(dup_lane_scalar): Likewise.
(get_lane): enable for VALL.
* config/aarch64/aarch64-simd.md
(aarch64_dup_lane_scalar<mode>): Remove.
(aarch64_get_lane_signed<mode>): Likewise.
(aarch64_get_lane_unsigned<mode>): Likewise.
(aarch64_get_lane_extend<GPI:mode><VDQQH:mode>): New.
(aarch64_get_lane_zero_extendsi<mode>): Likewise.
(aarch64_get_lane<mode>): Enable for all vector modes.
(aarch64_get_lanedi): Remove misleading constraints.
* config/aarch64/arm_neon.h
(__aarch64_vget_lane_any): Define.
(__aarch64_vget<q>_lane_<fpsu><8,16,32,64>): Likewise.
(vget<q>_lane_<fpsu><8,16,32,64>): Use __aarch64_vget_lane macros.
(vdup<bhsd>_lane_<su><8,16,32,64>): Likewise.
* config/aarch64/iterators.md (VDQQH): New.
(VDQQHS): Likewise.
(vwcore): Likewise.
gcc/testsuite/
* gcc.target/aarch64/scalar_intrinsics.c: Update expected
output of vdup intrinsics.
From-SVN: r201624
2013-08-09 09:28:51 +00:00
89fdc743cc
AArch64 support for NEG in vector registers for DI and SI mode (part 2)
...
From-SVN: r201263
2013-07-26 10:54:59 +00:00
28514ddab4
[AArch64, ILP32] 2/6 More backend changes and support for small absolute and
...
small PIC addressing models
gcc/
* config/aarch64/aarch64.c (POINTER_BYTES): New define.
(aarch64_load_symref_appropriately): In the case of
SYMBOL_SMALL_ABSOLUTE, use the mode of 'dest' instead of Pmode
to generate new rtx; likewise to the case of SYMBOL_SMALL_GOT.
(aarch64_expand_mov_immediate): In the case of SYMBOL_FORCE_TO_MEM,
change to pass 'ptr_mode' to force_const_mem and zero-extend 'mem'
if 'mode' doesn't equal to 'ptr_mode'.
(aarch64_output_mi_thunk): Add an assertion on the alignment of
'vcall_offset'; change to call aarch64_emit_move differently depending
on whether 'Pmode' equals to 'ptr_mode' or not; use 'POINTER_BYTES'
to calculate the upper bound of 'vcall_offset'.
(aarch64_cannot_force_const_mem): Change to also return true if
mode != ptr_mode.
(aarch64_legitimize_reload_address): In the case of large
displacements, add new local variable 'xmode' and an assertion
based on it; change to use 'xmode' to generate the new rtx and
reload.
(aarch64_asm_trampoline_template): Change to generate the template
differently depending on TARGET_ILP32 or not; change to use
'POINTER_BYTES' in the argument passed to assemble_aligned_integer.
(aarch64_trampoline_size): Removed.
(aarch64_trampoline_init): Add new local constant 'tramp_code_sz'
and replace immediate literals with it. Change to use 'ptr_mode'
instead of 'DImode' and call convert_memory_address if the mode
of 'fnaddr' doesn't equal to 'ptr_mode'.
(aarch64_elf_asm_constructor): Change to use assemble_aligned_integer
to output symbol.
(aarch64_elf_asm_destructor): Likewise.
* config/aarch64/aarch64.h (TRAMPOLINE_SIZE): Change to be dependent
on TARGET_ILP32 instead of aarch64_trampoline_size.
* config/aarch64/aarch64.md (movsi_aarch64): Add new alternatives
of 'mov' between WSP and W registers as well as 'adr' and 'adrp'.
(loadwb_pair<GPI:mode>_<PTR:mode>): Rename to ...
(loadwb_pair<GPI:mode>_<P:mode>): ... this. Replace PTR with P.
(storewb_pair<GPI:mode>_<PTR:mode>): Likewise; rename to ...
(storewb_pair<GPI:mode>_<P:mode>): ... this.
(add_losym): Change to 'define_expand' and call gen_add_losym_<mode>
depending on the value of 'mode'.
(add_losym_<mode>): New.
(ldr_got_small_<mode>): New, based on ldr_got_small.
(ldr_got_small): Remove.
(ldr_got_small_sidi): New.
* config/aarch64/iterators.md (P): New.
(PTR): Change to 'ptr_mode' in the condition.
From-SVN: r201165
2013-07-23 12:20:05 +00:00
8b033a8a92
aarch64-simd.md (aarch64_combine<mode>): convert to split.
...
* config/aarch64/aarch64-simd.md (aarch64_combine<mode>): convert to split.
(aarch64_simd_combine<mode>): New instruction expansion.
* config/aarch64/aarch64-protos.h (aarch64_split_simd_combine): New
function prototype.
* config/aarch64/aarch64.c (aarch64_split_combine): New function.
* config/aarch64/iterators.md (Vdbl): Add entry for DF.
From-SVN: r200020
2013-06-12 15:34:06 +00:00
fc21784dec
[AArch64] Fix vcond where comparison and result have different types.
...
gcc/
* config/aarch64/aarch64-simd.md
(aarch64_vcond_internal<mode>): Rename to...
(aarch64_vcond_internal<mode><mode>): ...This, for integer modes.
(aarch64_vcond_internal<VDQF_COND:mode><VDQF:mode>): ...This for
float modes. Clarify all iterator modes.
(vcond<mode><mode>): Use new name for vcond expanders.
(vcond<v_cmp_result><mode>): Likewise.
(vcondu<mode><mode>: Likewise.
* config/aarch64/iterators.md (VDQF_COND): New.
gcc/testsuite/
* gcc.target/aarch64/vect-fcm.x: Add cases testing
FLOAT cmp FLOAT ? INT : INT.
* gcc.target/aarch64/vect-fcm-eq-d.c: Define IMODE.
* gcc.target/aarch64/vect-fcm-eq-f.c: Likewise.
* gcc.target/aarch64/vect-fcm-ge-d.c: Likewise.
* gcc.target/aarch64/vect-fcm-ge-f.c: Likewise.
* gcc.target/aarch64/vect-fcm-gt-d.c: Likewise.
* gcc.target/aarch64/vect-fcm-gt-f.c: Likewise.
From-SVN: r198890
2013-05-14 14:56:13 +00:00
36054fabf5
[AArch64] Refactor reduc_<su>plus patterns.
...
gcc/
* config/aarch64/aarch64-builtins.c
(aarch64_gimple_fold_builtin.c): Fold more modes for reduc_splus_.
* config/aarch64/aarch64-simd-builtins.def
(reduc_splus_): Add new modes.
(reduc_uplus_): New.
* config/aarch64/aarch64-simd.md (aarch64_addvv4sf): Remove.
(reduc_uplus_v4sf): Likewise.
(reduc_splus_v4sf): Likewise.
(aarch64_addv<mode>): Likewise.
(reduc_uplus_<mode>): Likewise.
(reduc_splus_<mode>): Likewise.
(aarch64_addvv2di): Likewise.
(reduc_uplus_v2di): Likewise.
(reduc_splus_v2di): Likewise.
(aarch64_addvv2si): Likewise.
(reduc_uplus_v2si): Likewise.
(reduc_splus_v2si): Likewise.
(reduc_<sur>plus_<mode>): New.
(reduc_<sur>plus_v2di): Likewise.
(reduc_<sur>plus_v2si): Likewise.
(reduc_<sur>plus_v4sf): Likewise.
(aarch64_addpv4sf): Likewise.
* config/aarch64/arm_neon.h
(vaddv<q>_<s,u,f><8, 16, 32, 64): Rewrite using builtins.
* config/aarch64/iterators.md (unspec): Remove UNSPEC_ADDV,
add UNSPEC_SADDV, UNSPEC_UADDV.
(SUADDV): New.
(sur): Add UNSPEC_SADDV, UNSPEC_UADDV.
gcc/testsuite/
* gcc.target/aarch64/vect-vaddv.c: New.
From-SVN: r198500
2013-05-01 15:37:52 +00:00
998eaf975b
[AArch64] Refactor vector max and min RTL and builtins.
...
gcc/
* config/aarch64/aarch64-simd-builtins.def
(reduc_smax_): New.
(reduc_smin_): Likewise.
(reduc_umax_): Likewise.
(reduc_umin_): Likewise.
(reduc_smax_nan_): Likewise.
(reduc_smin_nan_): Likewise.
(fmax): Remove.
(fmin): Likewise.
(smax): Update for V2SF, V4SF and V2DF modes.
(smin): Likewise.
(smax_nan): New.
(smin_nan): Likewise.
* config/aarch64/aarch64-simd.md (<maxmin><mode>3): Rename to...
(<su><maxmin><mode>3): ...This, refactor.
(s<maxmin><mode>3): New.
(<maxmin_uns><mode>3): Likewise.
(reduc_<maxmin_uns>_<mode>): Refactor.
(reduc_<maxmin_uns>_v4sf): Likewise.
(reduc_<maxmin_uns>_v2si): Likewise.
(aarch64_<fmaxmin><mode>: Remove.
* config/aarch64/arm_neon.h (vmax<q>_f<32,64>): Rewrite to use
new builtin names.
(vmin<q>_f<32,64>): Likewise.
* config/iterators.md (unspec): Add UNSPEC_FMAXNMV, UNSPEC_FMINNMV.
(FMAXMIN): New.
(su): Add mappings for smax, smin, umax, umin.
(maxmin): New.
(FMAXMINV): Add UNSPEC_FMAXNMV, UNSPEC_FMINNMV.
(FMAXMIN): Rename as...
(FMAXMIN_UNS): ...This.
(maxminv): Remove.
(fmaxminv): Likewise.
(fmaxmin): Likewise.
(maxmin_uns): New.
(maxmin_uns_op): Likewise.
From-SVN: r198497
2013-05-01 15:16:14 +00:00
75dd5aceb2
[AArch64] Add combiner patterns for FAC instructions
...
gcc/
* config/aarch64/aarch64-simd.md (*aarch64_fac<optab><mode>): New.
* config/aarch64/iterators.md (FAC_COMPARISONS): New.
From-SVN: r198494
2013-05-01 10:46:00 +00:00
889b941239
[AArch64] Improve description of <F>CM instructions in RTL
...
gcc/
* config/aarch64/aarch64-simd-builtins.def (cmhs): Rename to...
(cmgeu): ...This.
(cmhi): Rename to...
(cmgtu): ...This.
* config/aarch64/aarch64-simd.md
(simd_mode): Add SF.
(aarch64_vcond_internal): Use new names for unsigned comparison insns.
(aarch64_cm<optab><mode>): Rewrite to not use UNSPECs.
* config/aarch64/aarch64.md (*cstore<mode>_neg): Rename to...
(cstore<mode>_neg): ...This.
* config/aarch64/iterators.md
(VALLF): new.
(unspec): Remove UNSPEC_CM<EQ, LE, LT, GE, GT, HS, HI, TST>.
(COMPARISONS): New.
(UCOMPARISONS): Likewise.
(optab): Add missing comparisons.
(n_optab): New.
(cmp_1): Likewise.
(cmp_2): Likewise.
(CMP): Likewise.
(cmp): Remove.
(VCMP_S): Likewise.
(VCMP_U): Likewise.
(V_cmp_result): Add DF, SF modes.
(v_cmp_result): Likewise.
(v): Likewise.
(vmtype): Likewise.
* config/aarch64/predicates.md (aarch64_reg_or_fp_zero): New.
From-SVN: r198490
2013-05-01 10:33:57 +00:00
384be29f47
[AArch64] Add vector fix, fixuns, fix_trunc, fixuns_trunc standard patterns
...
gcc/
* config/aarch64/aarch64-simd.md
(<optab><VDQF:mode><fcvt_target>2): New, maps to fix, fixuns.
(<fix_trunc_optab><VDQF:mode><fcvt_target>2): New, maps to
fix_trunc, fixuns_trunc.
(ftrunc<VDQF:mode>2): New.
* config/aarch64/iterators.md (optab): Add fix, fixuns.
(fix_trunc_optab): New.
From-SVN: r198403
2013-04-29 11:04:56 +00:00
Alan Lawrence
Jiong Wang
Renlin Li
James Greenhalgh
Jiong Wang
David Sherwood
Jakub Jelinek
Felix Yang
Michael Collison
Guozhi Wei
Kyrylo Tkachov
Vidya Praveen
Richard Sandiford
Tejas Belagod
Ian Bolton
Yufeng Zhang
Sofiane Naci