Commit Graph

671 Commits

Author SHA1 Message Date
Andrew Stubbs
91d7b7fe84 GCN libgcc.
This patch contains the GCN port of libgcc.

2019-01-17  Andrew Stubbs  <ams@codesourcery.com>
	    Kwok Cheung Yeung  <kcy@codesourcery.com>
	    Julian Brown  <julian@codesourcery.com>
	    Tom de Vries  <tom@codesourcery.com>

	libgcc/
	* config.host: Recognize amdgcn*-*-amdhsa.
	* config/gcn/crt0.c: New file.
	* config/gcn/lib2-divmod-hi.c: New file.
	* config/gcn/lib2-divmod.c: New file.
	* config/gcn/lib2-gcn.h: New file.
	* config/gcn/sfp-machine.h: New file.
	* config/gcn/t-amdgcn: New file.


Co-Authored-By: Julian Brown <julian@codesourcery.com>
Co-Authored-By: Kwok Cheung Yeung <kcy@codesourcery.com>
Co-Authored-By: Tom de Vries <tom@codesourcery.com>

From-SVN: r268021
2019-01-17 12:29:13 +00:00
Sandra Loosemore
6791469314 PR other/16615 [1/5]
2019-01-09  Sandra Loosemore  <sandra@codesourcery.com>

	PR other/16615 [1/5]

	contrib/
	* mklog: Mechanically replace "can not" with "cannot".

	gcc/
	* Makefile.in: Mechanically replace "can not" with "cannot".
	* alias.c: Likewise.
	* builtins.c: Likewise.
	* calls.c: Likewise.
	* cgraph.c: Likewise.
	* cgraph.h: Likewise.
	* cgraphclones.c: Likewise.
	* cgraphunit.c: Likewise.
	* combine-stack-adj.c: Likewise.
	* combine.c: Likewise.
	* common/config/i386/i386-common.c: Likewise.
	* config/aarch64/aarch64.c: Likewise.
	* config/alpha/sync.md: Likewise.
	* config/arc/arc.c: Likewise.
	* config/arc/predicates.md: Likewise.
	* config/arm/arm-c.c: Likewise.
	* config/arm/arm.c: Likewise.
	* config/arm/arm.h: Likewise.
	* config/arm/arm.md: Likewise.
	* config/arm/cortex-r4f.md: Likewise.
	* config/csky/csky.c: Likewise.
	* config/csky/csky.h: Likewise.
	* config/darwin-f.c: Likewise.
	* config/epiphany/epiphany.md: Likewise.
	* config/i386/i386.c: Likewise.
	* config/i386/sol2.h: Likewise.
	* config/m68k/m68k.c: Likewise.
	* config/mcore/mcore.h: Likewise.
	* config/microblaze/microblaze.md: Likewise.
	* config/mips/20kc.md: Likewise.
	* config/mips/sb1.md: Likewise.
	* config/nds32/nds32.c: Likewise.
	* config/nds32/predicates.md: Likewise.
	* config/pa/pa.c: Likewise.
	* config/rs6000/e300c2c3.md: Likewise.
	* config/rs6000/rs6000.c: Likewise.
	* config/s390/s390.h: Likewise.
	* config/sh/sh.c: Likewise.
	* config/sh/sh.md: Likewise.
	* config/spu/vmx2spu.h: Likewise.
	* cprop.c: Likewise.
	* dbxout.c: Likewise.
	* df-scan.c: Likewise.
	* doc/cfg.texi: Likewise.
	* doc/extend.texi: Likewise.
	* doc/fragments.texi: Likewise.
	* doc/gty.texi: Likewise.
	* doc/invoke.texi: Likewise.
	* doc/lto.texi: Likewise.
	* doc/md.texi: Likewise.
	* doc/objc.texi: Likewise.
	* doc/rtl.texi: Likewise.
	* doc/tm.texi: Likewise.
	* dse.c: Likewise.
	* emit-rtl.c: Likewise.
	* emit-rtl.h: Likewise.
	* except.c: Likewise.
	* expmed.c: Likewise.
	* expr.c: Likewise.
	* fold-const.c: Likewise.
	* genautomata.c: Likewise.
	* gimple-fold.c: Likewise.
	* hard-reg-set.h: Likewise.
	* ifcvt.c: Likewise.
	* ipa-comdats.c: Likewise.
	* ipa-cp.c: Likewise.
	* ipa-devirt.c: Likewise.
	* ipa-fnsummary.c: Likewise.
	* ipa-icf.c: Likewise.
	* ipa-inline-transform.c: Likewise.
	* ipa-inline.c: Likewise.
	* ipa-polymorphic-call.c: Likewise.
	* ipa-profile.c: Likewise.
	* ipa-prop.c: Likewise.
	* ipa-pure-const.c: Likewise.
	* ipa-reference.c: Likewise.
	* ipa-split.c: Likewise.
	* ipa-visibility.c: Likewise.
	* ipa.c: Likewise.
	* ira-build.c: Likewise.
	* ira-color.c: Likewise.
	* ira-conflicts.c: Likewise.
	* ira-costs.c: Likewise.
	* ira-int.h: Likewise.
	* ira-lives.c: Likewise.
	* ira.c: Likewise.
	* ira.h: Likewise.
	* loop-invariant.c: Likewise.
	* loop-unroll.c: Likewise.
	* lower-subreg.c: Likewise.
	* lra-assigns.c: Likewise.
	* lra-constraints.c: Likewise.
	* lra-eliminations.c: Likewise.
	* lra-lives.c: Likewise.
	* lra-remat.c: Likewise.
	* lra-spills.c: Likewise.
	* lra.c: Likewise.
	* lto-cgraph.c: Likewise.
	* lto-streamer-out.c: Likewise.
	* postreload-gcse.c: Likewise.
	* predict.c: Likewise.
	* profile-count.h: Likewise.
	* profile.c: Likewise.
	* recog.c: Likewise.
	* ree.c: Likewise.
	* reload.c: Likewise.
	* reload1.c: Likewise.
	* reorg.c: Likewise.
	* resource.c: Likewise.
	* rtl.def: Likewise.
	* rtl.h: Likewise.
	* rtlanal.c: Likewise.
	* sched-deps.c: Likewise.
	* sched-ebb.c: Likewise.
	* sched-rgn.c: Likewise.
	* sel-sched-ir.c: Likewise.
	* sel-sched.c: Likewise.
	* shrink-wrap.c: Likewise.
	* simplify-rtx.c: Likewise.
	* symtab.c: Likewise.
	* target.def: Likewise.
	* toplev.c: Likewise.
	* tree-call-cdce.c: Likewise.
	* tree-cfg.c: Likewise.
	* tree-complex.c: Likewise.
	* tree-core.h: Likewise.
	* tree-eh.c: Likewise.
	* tree-inline.c: Likewise.
	* tree-loop-distribution.c: Likewise.
	* tree-nrv.c: Likewise.
	* tree-profile.c: Likewise.
	* tree-sra.c: Likewise.
	* tree-ssa-alias.c: Likewise.
	* tree-ssa-dce.c: Likewise.
	* tree-ssa-dom.c: Likewise.
	* tree-ssa-forwprop.c: Likewise.
	* tree-ssa-loop-im.c: Likewise.
	* tree-ssa-loop-ivcanon.c: Likewise.
	* tree-ssa-loop-ivopts.c: Likewise.
	* tree-ssa-loop-niter.c: Likewise.
	* tree-ssa-phionlycprop.c: Likewise.
	* tree-ssa-phiopt.c: Likewise.
	* tree-ssa-propagate.c: Likewise.
	* tree-ssa-threadedge.c: Likewise.
	* tree-ssa-threadupdate.c: Likewise.
	* tree-ssa-uninit.c: Likewise.
	* tree-ssanames.c: Likewise.
	* tree-streamer-out.c: Likewise.
	* tree.c: Likewise.
	* tree.h: Likewise.
	* vr-values.c: Likewise.

	gcc/ada/
	* exp_ch9.adb: Mechanically replace "can not" with "cannot".
	* libgnat/s-regpat.ads: Likewise.
	* par-ch4.adb: Likewise.
	* set_targ.adb: Likewise.
	* types.ads: Likewise.

	gcc/cp/
	* cp-tree.h: Mechanically replace "can not" with "cannot".
	* parser.c: Likewise.
	* pt.c: Likewise.

	gcc/fortran/
	* class.c: Mechanically replace "can not" with "cannot".
	* decl.c: Likewise.
	* expr.c: Likewise.
	* gfc-internals.texi: Likewise.
	* intrinsic.texi: Likewise.
	* invoke.texi: Likewise.
	* io.c: Likewise.
	* match.c: Likewise.
	* parse.c: Likewise.
	* primary.c: Likewise.
	* resolve.c: Likewise.
	* symbol.c: Likewise.
	* trans-array.c: Likewise.
	* trans-decl.c: Likewise.
	* trans-intrinsic.c: Likewise.
	* trans-stmt.c: Likewise.

	gcc/go/
	* go-backend.c: Mechanically replace "can not" with "cannot".
	* go-gcc.cc: Likewise.

	gcc/lto/
	* lto-partition.c: Mechanically replace "can not" with "cannot".
	* lto-symtab.c: Likewise.
	* lto.c: Likewise.

	gcc/objc/
	* objc-act.c: Mechanically replace "can not" with "cannot".

	libbacktrace/
	* backtrace.h: Mechanically replace "can not" with "cannot".

	libgcc/
	* config/c6x/libunwind.S: Mechanically replace "can not" with
	"cannot".
	* config/tilepro/atomic.h: Likewise.
	* config/vxlib-tls.c: Likewise.
	* generic-morestack-thread.c: Likewise.
	* generic-morestack.c: Likewise.
	* mkmap-symver.awk: Likewise.

	libgfortran/
	* caf/single.c: Mechanically replace "can not" with "cannot".
	* io/unit.c: Likewise.

	libobjc/
	* class.c: Mechanically replace "can not" with "cannot".
	* objc/runtime.h: Likewise.
	* sendmsg.c: Likewise.

	liboffloadmic/
	* include/coi/common/COIResult_common.h: Mechanically replace
	"can not" with "cannot".
	* include/coi/source/COIBuffer_source.h: Likewise.

	libstdc++-v3/
	* include/ext/bitmap_allocator.h: Mechanically replace "can not"
	with "cannot".

From-SVN: r267783
2019-01-09 16:37:45 -05:00
Jakub Jelinek
a554497024 Update copyright years.
From-SVN: r267494
2019-01-01 13:31:55 +01:00
Thomas Preud'homme
72e3a52923 [ARM] Optimize executable size when using softfloat fmul/dmul
Softfloat single precision and double precision floating-point
multiplication routines in libgcc share some code with the
floating-point division of their corresponding precision. As the code
is structured now, this leads to *all* division code being pulled in an
executable in softfloat mode even if only multiplication is
performed.

This patch create some new LIB1ASMFUNCS macros to also build files with
just the multiplication and shared code as weak symbols. By putting
these earlier in the static library, they can then be picked up when
only multiplication is used and they are overriden by the global
definition in the existing file containing both multiplication and
division code when division is needed.

The patch also removes changes made to the FUNC_START and ARM_FUNC_START
macros in r218124 since the intent was to put multiplication and
division code into their own section in a later patch to achieve the
same size optimization. That approach relied on specific section layout
to ensure multiplication and division were not too far from the shared
bit of code in order to the branches to be within range. Due to lack of
guarantee regarding section layout, in particular with all the
possibility of linker scripts, this approach was chosen instead. This
patch keeps the two testcases that were posted by Tony Wang on the mailing
list to implement this approach and adds a new one.

2018-12-19  Thomas Preud'homme  <thomas.preudhomme@linaro.org>

    libgcc/
    * /config/arm/lib1funcs.S (FUNC_START): Remove unused sp_section
    parameter and corresponding code.
    (ARM_FUNC_START): Likewise in both definitions.
    Also update footer comment about condition that need to match with
    gcc/config/arm/elf.h to also include libgcc/config/arm/t-arm.
    * config/arm/ieee754-df.S (muldf3): Also build it if L_arm_muldf3 is
    defined.  Weakly define it in this case.
    * config/arm/ieee754-sf.S (mulsf3): Likewise with L_arm_mulsf3.
    * config/arm/t-elf (LIB1ASMFUNCS): Build _arm_muldf3.o and
    _arm_mulsf3.o before muldiv versions if targeting Thumb-1 only. Add
    comment to keep condition in sync with the one in
    libgcc/config/arm/lib1funcs.S and gcc/config/arm/elf.h.

    gcc/
    * config/arm/elf.h: Update comment about condition that need to
    match with libgcc/config/arm/lib1funcs.S to also include
    libgcc/config/arm/t-arm.
    * doc/sourcebuild.texi (output-exists, output-exists-not): Rename
    subsubsection these directives are in to "Check for output files".
    Move scan-symbol to that section and add to it new scan-symbol-not
    directive.

2018-12-19  Tony Wang  <tony.wang@arm.com>
	    Thomas Preud'homme  <thomas.preudhomme@linaro.org>

    gcc/testsuite/
    * lib/lto.exp (lto-execute): Define output_file and testname_with_flags
    to same value as execname.
    (scan-symbol): Move and rename to ...
    * lib/gcc-dg.exp (scan-symbol-common): This.  Adapt into a
    helper function returning true or false if a symbol is present.
    (scan-symbol): New procedure.
    (scan-symbol-not): Likewise.
    * gcc.target/arm/size-optimization-ieee-1.c: New testcase.
    * gcc.target/arm/size-optimization-ieee-2.c: Likewise.
    * gcc.target/arm/size-optimization-ieee-3.c: Likewise.

From-SVN: r267282
2018-12-19 17:34:18 +00:00
Wei Xiao
5d54c79858 driver-i386.c (host_detect_local_cpu): Detect cascadelake.
gcc/ChangeLog
2018-12-18  Wei Xiao  <wei3.xiao@intel.com>

	* config/i386/driver-i386.c (host_detect_local_cpu): Detect cascadelake.
	* config/i386/i386.c (fold_builtin_cpu): Handle cascadelake.
	* doc/extend.texi: Add cascadelake.

gcc/testsuite/ChangeLog
2018-12-18  Wei Xiao  <wei3.xiao@intel.com>

	* g++.target/i386/mv16.C: Handle new march.
	* gcc.target/i386/builtin_target.c: Ditto.

libgcc/ChangeLog
2018-12-18  Wei Xiao  <wei3.xiao@intel.com>

	* config/i386/cpuinfo.c (get_intel_cpu): Handle cascadelake.
	* config/i386/cpuinfo.h: Add INTEL_COREI7_CASCADELAKE.

From-SVN: r267226
2018-12-18 03:41:44 +00:00
Rasmus Villemoes
5a2580b6ad libgcc: rs6000: tramp.S: fix placement of .cfi_endproc for __trampoline_setup
Currently, .cfi_endproc and FUNC_END(__trampoline_setup) are placed
inside the #else branch of an "#if defined (__VXWORKS__) ...", so
non-pic vxworks does not get proper CFI nor a .size directive for
__trampoline_setup. I assume there's no magic reason for that (which
would warrant a comment), so move them outside.

From-SVN: r267051
2018-12-12 10:12:36 +00:00
Alan Modra
1ea7ea181d [RS6000] libgcc cfi
There are a few places in libgcc assembly where we don't emit call
frame information for functions, potentially breaking unwinding from
asynchronous signal handlers.  This patch fixes them.  Although I
patch tramp.S there is no attempt made to provide CFI for the actual
trampoline on the stack.  Doing that would require generating CFI at
run time and both registering and deregistering it, which is probably
not worth doing since it would significantly slow down the call.

	* config/rs6000/morestack.S (__stack_split_initialize),
	(__morestack_get_guard, __morestack_set_guard),
	(__morestack_make_guard): Provide CFI covering these functions.
	* config/rs6000/tramp.S (__trampoline_setup): Likewise.

From-SVN: r266503
2018-11-27 12:29:56 +10:30
Xianmiao Qu
ff641ae112 linux-unwind.h (sc_pt_regs): Update for kernel.
2018-11-15  Xianmiao Qu  <xianmiao_qu@c-sky.com>

	libgcc/
	* config/csky/linux-unwind.h (sc_pt_regs): Update for kernel. 
	(sc_pt_regs_lr): Update for kernel.
	(sc_pt_regs_tls): Update for kernel.

From-SVN: r266200
2018-11-16 01:26:04 +00:00
Xianmiao Qu
2820937241 csky-linux-elf.h (LINUX_DYNAMIC_LINKER): Remove.
2018-11-15  Xianmiao Qu  <xianmiao_qu@c-sky.com>

	gcc/
	* config/csky/csky-linux-elf.h (LINUX_DYNAMIC_LINKER): Remove.
	(GLIBC_DYNAMIC_LINKER): Define.
	(LINUX_TARGET_LINK_SPEC): Update the dynamic linker's name.

	libgcc/
	* config/csky/linux-unwind.h: Fix coding style.

From-SVN: r266172
2018-11-15 06:01:09 +00:00
Xianmiao Qu
b2a71af6e2 linux-unwind.h (_sig_ucontext_t): Remove.
2018-11-13  Xianmiao Qu  <xianmiao_qu@c-sky.com>

	libgcc/
	* config/csky/linux-unwind.h (_sig_ucontext_t): Remove.
	(csky_fallback_frame_state): Modify the check of the 
	instructions to adapt to changes in the kernel

From-SVN: r266060
2018-11-13 09:12:36 +00:00
Stafford Horne
d929e137f8 or1k: libgcc: initial support for openrisc
libgcc/ChangeLog:

2018-11-09  Stafford Horne  <shorne@gmail.com>
	    Richard Henderson  <rth@twiddle.net>

	* config.host: Add OpenRISC support.
	* config/or1k/*: New.


Co-Authored-By: Richard Henderson <rth@twiddle.net>

From-SVN: r265961
2018-11-09 12:09:15 +00:00
Venkataramanan Kumar
2901f42f4b Enable support for next generation AMD Zen CPU, via -march=znver2.
gcc/ChangeLog:
	* common/config/i386/i386-common.c (processor_alias_table): Add znver2 entry.
	* config.gcc (i[34567]86-*-linux* | ...): Add znver2.
	(case ${target}): Add znver2.
	* config/i386/driver-i386.c: (host_detect_local_cpu): Let
	-march=native recognize znver2 processors.
	* config/i386/i386-c.c (ix86_target_macros_internal): Add znver2.
	* config/i386/i386.c (m_znver2): New definition.
	(m_ZNVER): New definition.
	(m_AMD_MULTIPLE): Includes m_znver2.
	(processor_cost_table): Add znver2 entry.
	(processor_target_table): Add znver2 entry.
	(get_builtin_code_for_version): Set priority for
	PROCESSOR_ZNVER2.
	(processor_model): Add M_AMDFAM17H_ZNVER2.
	(arch_names_table): Ditto.
	(ix86_reassociation_width): Include znver2. 
	* config/i386/i386.h (TARGET_znver2): New definition.
	(struct ix86_size_cost): Add TARGET_ZNVER2.
	(enum processor_type): Add PROCESSOR_ZNVER2.
	* config/i386/i386.md (define_attr "cpu"): Add znver2.
	* config/i386/x86-tune-costs.h: (processor_costs) Add znver2 costs.
	* config/i386/x86-tune-sched.c: (ix86_issue_rate): Add znver2.
	(ix86_adjust_cost): Add znver2.
	* config/i386/x86-tune.def:  Replace m_ZNVER1 by m_ZNVER
	* gcc/doc/extend.texi: Add details about znver2.
	* gcc/doc/invoke.texi: Add details about znver2.

libgcc/ChangeLog
	* config/i386/cpuinfo.c: (get_amd_cpu): Add znver2.
	* config/i386/cpuinfo.h(processor_subtypes): Ditto.

From-SVN: r265775
2018-11-04 11:17:54 +00:00
Paul Koning
4310ca662a t-pdp11 (LIB2ADD): Add divmod.c.
* config/pdp11/t-pdp11 (LIB2ADD): Add divmod.c.
	(HOST_LIBGCC2_CFLAGS): Change to optimize for size.

From-SVN: r265726
2018-11-01 14:36:52 -04:00
Claudiu Zissulescu
8180cde0fb [ARC] Remove non standard funcions calls.
Replace all custom "library" calls with compiler known patterns.

gcc/
xxxx-xx-xx  Claudiu Zissulescu  <claziss@synopsys.com>

	* config/arc/arc.md (mulsi3): Remove call to mulsi_600_lib.
	(mulsi3_600_lib): Remove pattern.
	(umulsi3_highpart_600_lib_le): Likewise.
	(umulsi3_highpart): Remove call to umulsi3_highpart_600_lib_le.
	(umulsidi3): Remove call to umulsidi3_600_lib.
	(umulsidi3_600_lib): Remove pattern.
	(peephole2): Remove peephole using the above deprecated patterns.

testsuite/
xxxx-xx-xx  Claudiu Zissulescu  <claziss@synopsys.com>

	* gcc.target/arc/mulsi3_highpart-2.c: Update test.

libgcc/
xxxx-xx-xx  Claudiu Zissulescu  <claziss@synopsys.com>

	* config/arc/lib1funcs.S (_muldi3): New function.
	* config/arc/t-arc (LIB1ASMFUNCS): Add _muldi3.

From-SVN: r265672
2018-10-31 12:27:07 +01:00
Rasmus Villemoes
be7b071e9e libgcc: properly destroy mutexes on VxWorks
Just as one needs run-time initialization of mutexes, one needs to
destroy them properly to allow the OS to release resources associated
with the semaphore.

From-SVN: r265616
2018-10-30 08:33:04 +00:00
Paul Koning
a9a2fddbf2 udivmodsi4.c (__udivmodsi4): Rename to conform to coding standard.
* udivmodsi4.c (__udivmodsi4): Rename to conform to coding
	standard.
	* divmod.c: Update references to __udivmodsi4.
	* udivmod.c: Ditto.
	* udivhi3.c: New file.
	* udivmodhi4.c: New file.
	* config/pdp11/t-pdp11 (LIB2ADD): Add the new files.

From-SVN: r265277
2018-10-18 14:01:15 -04:00
Olivier Hainque
87f918e380 tighten the toplevel guard on ibm-ldouble.c
2018-10-12  Olivier Hainque  <hainque@adacore.com>

        * config/rs6000/ibm-ldouble.c: Augment the toplevel guard with
        defined (__FLOAT128_TYPE__) || defined (__LONG_DOUBLE_128__).

From-SVN: r265135
2018-10-12 21:25:46 +00:00
Paul Koning
be86efa7cc * config/pdp11/t-pdp11: Remove -mfloat32 switch.
From-SVN: r264939
2018-10-08 12:49:48 -04:00
Uros Bizjak
0a76bba487 crtprec.c (set_precision): Use fnstcw instead of fstcw.
* config/i386/crtprec.c (set_precision): Use fnstcw instead of fstcw.

From-SVN: r264649
2018-09-26 17:25:15 +02:00
Olivier Hainque
5244089f15 Leverage cacheTextUpdate for __clear_cache on VxWorks
2018-09-21  Alexandre Oliva  <oliva@adacore.com>

libgcc/
	* config/vxcache.c: New file.  Provide __clear_cache, based on
	the cacheTextUpdate VxWorks service.
	* config/t-vxworks (LIB2ADD): Add vxcache.c.
	(LIB2FUNCS_EXCLUDE): Add _clear_cache.
	* config/t-vxwoks7: Likewise.
gcc/
	* config/vxworks.h (CLEAR_INSN_CACHE): #define to 1.

From-SVN: r264479
2018-09-21 13:09:51 +00:00
Monk Chiang
36ff254bf6 [NDS32] Sync glibc and kernel structure, all use _rt_sigframe.
libgcc/
	* config/nds32/linux-unwind.h (struct _rt_sigframe): Use struct
	ucontext_t type instead.
	(nds32_fallback_frame_state): Remove struct _sigframe statement.

From-SVN: r264461
2018-09-21 08:39:35 +00:00
Kito Cheng
229a033dac [NDS32] Add t-nds32-glibc file.
libgcc/
	* config/nds32/t-nds32-glibc: New file.

From-SVN: r264460
2018-09-21 08:11:40 +00:00
Rainer Orth
53c6feb2b2 Use v2 map syntax in libgcc-unwind.map if Solaris ld supports it
* configure.ac (solaris_ld_v2_maps): New test.
	* configure: Regenerate.
	* Makefile.in (solaris_ld_v2_maps): New variable.
	* config/t-slibgcc-sld (libgcc-unwind.map): Emit v2 mapfile syntax
	if supported.

From-SVN: r264382
2018-09-18 07:04:15 +00:00
Richard Earnshaw
ebdb6f2377 PR target/86951 arm - Handle speculation barriers on pre-armv7 CPUs
The AArch32 instruction sets prior to Armv7 do not define the ISB and
DSB instructions that are needed to form a speculation barrier.  While
I do not know of any instances of cores based on those instruction
sets being vulnerable to speculative side channel attacks it is
possible to run code built for those ISAs on more recent hardware
where they would become vulnerable.

This patch works around this by using a library call added to libgcc.
That code can then take any platform-specific actions necessary to
ensure safety.

For the moment I've only handled two cases: the library code being
built for armv7 or later anyway and running on Linux.

On Linux we can handle this by calling the kernel function that will
flush a small amount of cache.  Such a sequence ends with a ISB+DSB
sequence if running on an Armv7 or later CPU.

gcc:

	PR target/86951
	* config/arm/arm-protos.h (arm_emit_speculation_barrier): New
	prototype.
	* config/arm/arm.c (speculation_barrier_libfunc): New static
	variable.
	(arm_init_libfuncs): Initialize it.
	(arm_emit_speculation_barrier): New function.
	* config/arm/arm.md (speculation_barrier): Call
	arm_emit_speculation_barrier for architectures that do not have 
	DSB or ISB.
	(speculation_barrier_insn): Only match on Armv7 or later.

libgcc:

	PR target/86951
	* config/arm/lib1funcs.asm (speculation_barrier): New function.
	* config/arm/t-arm (LIB1ASMFUNCS): Add it to list of functions
	to build.

From-SVN: r263806
2018-08-23 09:47:34 +00:00
Iain Sandoe
a49c064e40 Move Darwin10 unwinder fix to a crt shim.
gcc/
	* config/darwin10.h (LINK_GCC_C_SEQUENCE_SPEC): Adjust to use the
	Darwin10-specific unwinder-shim.
	* config/darwin12.h (LINK_GCC_C_SEQUENCE_SPEC): Remove.
	* config/rs6000/darwin.h (DARWIN_CRT1_SPEC, DARWIN_DYLIB1_SPEC): 
	New to cater for Darwin10 Rosetta.

libgcc/
	* config/unwind-dw2-fde-darwin.c
	(_darwin10_Unwind_FindEnclosingFunction): move from here ...
	* config/darwin10-unwind-find-enc-func.c: … to here.
	* config/t-darwin: Build Darwin10 unwinder shim crt.
	* libgcc/config.host: Add the Darwin10 unwinder shim.

From-SVN: r263765
2018-08-22 11:58:43 +00:00
Jojo
4cd0bc3b69 C-SKY port: libgcc
2018-08-17  Jojo  <jijie_rong@c-sky.com>
	    Huibin Wang  <huibin_wang@c-sky.com>
	    Sandra Loosemore  <sandra@codesourcery.com>
	    Chung-Lin Tang  <cltang@codesourcery.com>

	C-SKY port: libgcc

	libgcc/
	* config.host: Add C-SKY support.
	* config/csky/*: New.

Co-Authored-By: Chung-Lin Tang <cltang@codesourcery.com>
Co-Authored-By: Huibin Wang <huibin_wang@c-sky.com>
Co-Authored-By: Sandra Loosemore <sandra@codesourcery.com>

From-SVN: r263631
2018-08-17 15:08:27 -04:00
Chung-Ju Wu
a493174524 [NDS32] Implement more C ISR extension.
gcc/
	* config.gcc (nds32*): Add nds32_isr.h and nds32_init.inc in
	extra_headers.
	* common/config/nds32/nds32-common.c (nds32_handle_option): Handle
	OPT_misr_secure_ case.
	* config/nds32/nds32-isr.c: Implementation of backward compatibility.
	* config/nds32/nds32-protos.h (nds32_isr_function_critical_p): New.
	* config/nds32/nds32.c (nds32_attribute_table): Add critical and
	secure attribute.
	* config/nds32/nds32.h (nds32_isr_nested_type): Add NDS32_CRITICAL.
	(nds32_isr_info): New field security_level.
	(TARGET_ISR_VECTOR_SIZE_4_BYTE): New macro.
	* config/nds32/nds32.md (return_internal): Consider critical attribute.
	* config/nds32/nds32.opt (misr-secure): New option.
	* config/nds32/nds32_init.inc: New file.
	* config/nds32/nds32_isr.h: New file.

libgcc/
	* config/nds32/t-nds32-isr: Rearrange object dependency.
	* config/nds32/initfini.c: Add dwarf2 unwinding support.
	* config/nds32/isr-library/adj_intr_lvl.inc: Consider new extensions
	and registers usage.
	* config/nds32/isr-library/excp_isr.S: Ditto.
	* config/nds32/isr-library/intr_isr.S: Ditto.
	* config/nds32/isr-library/reset.S: Ditto.
	* config/nds32/isr-library/restore_all.inc: Ditto.
	* config/nds32/isr-library/restore_mac_regs.inc: Ditto.
	* config/nds32/isr-library/restore_partial.inc: Ditto.
	* config/nds32/isr-library/restore_usr_regs.inc: Ditto.
	* config/nds32/isr-library/save_all.inc: Ditto.
	* config/nds32/isr-library/save_mac_regs.inc: Ditto.
	* config/nds32/isr-library/save_partial.inc: Ditto.
	* config/nds32/isr-library/save_usr_regs.inc: Ditto.
	* config/nds32/isr-library/vec_vid*.S: Consider 4-byte vector size.

From-SVN: r263493
2018-08-12 07:38:40 +00:00
John David Anglin
2b1969f635 pa.md (UNSPEC_MEMORY_BARRIER): New unspec enum.
gcc
	* config/pa/pa.md (UNSPEC_MEMORY_BARRIER): New unspec enum.
	Update comment for atomic instructions.
	(atomic_storeqi, atomic_storehi, atomic_storesi, atomic_storesf,
	atomic_loaddf, atomic_loaddf_1, atomic_storedf, atomic_storedf_1):
	Remove.
	(atomic_loaddi): Revise fence expansion to only emit fence prior to
	load for __ATOMIC_SEQ_CST model.
	(atomic_loaddi_1): Remove float register target.
	(atomic_storedi): Handle CONST_INT values.
	(atomic_storedi_1): Remove float register source.  Add special case
	for zero value.
	(memory_barrier): New expander and insn.

	libgcc
	* config/pa/linux-atomic.c: Update comment.
	(FETCH_AND_OP_2, OP_AND_FETCH_2, FETCH_AND_OP_WORD, OP_AND_FETCH_WORD,
	COMPARE_AND_SWAP_2, __sync_val_compare_and_swap_4,
	SYNC_LOCK_TEST_AND_SET_2, __sync_lock_test_and_set_4): Use
	__ATOMIC_RELAXED for atomic loads.
	(SYNC_LOCK_RELEASE_1): New define.  Use __sync_synchronize() and
	unordered store to release lock.
	(__sync_lock_release_8): Likewise.
	(SYNC_LOCK_RELEASE_2): Remove define.

From-SVN: r263488
2018-08-11 21:37:55 +00:00
Nicolas Pitre
89fff9cc2b arm - correctly handle denormal results during softfp subtraction
2018-08-02  Nicolas Pitre <nico@fluxnic.net>

	PR libgcc/86512
	* config/arm/ieee754-df.S (adddf3): Don't shortcut denormal handling
	when exponent goes negative. Update my email address.
	* config/arm/ieee754-sf.S (addsf3): Likewise.

From-SVN: r263267
2018-08-02 16:50:07 +00:00
Christophe Lyon
b74159752d [ARM] libgcc: Fix comment for code working on architectures >= 4.
2018-07-30  Christophe Lyon  <christophe.lyon@linaro.org>

	* config/arm/ieee754-df.S: Fix comment for code working on
	architectures >= 4.
	* config/arm/ieee754-sf.S: Likewise.

From-SVN: r263066
2018-07-30 14:51:42 +02:00
H.J. Lu
b72e71a39c i386: Remove _Unwind_Frames_Increment
CET kernel has been changed to place a restore token on shadow stack for
signal handler to enhance security.  It is usually transparent to user
programs since kernel will pop the restore token when signal handler
returns.  But when an exception is thrown from a signal handler, now
we need to remove _Unwind_Frames_Increment to pop the the restore token
from shadow stack.  Otherwise, we get

FAIL: g++.dg/torture/pr85334.C   -O0  execution test
FAIL: g++.dg/torture/pr85334.C   -O1  execution test
FAIL: g++.dg/torture/pr85334.C   -O2  execution test
FAIL: g++.dg/torture/pr85334.C   -O3 -g  execution test
FAIL: g++.dg/torture/pr85334.C   -Os  execution test
FAIL: g++.dg/torture/pr85334.C   -O2 -flto -fno-use-linker-plugin -flto-partition=none  execution test

	PR libgcc/85334
	* config/i386/shadow-stack-unwind.h (_Unwind_Frames_Increment):
	Removed.

From-SVN: r263030
2018-07-27 07:40:47 -07:00
Christophe Lyon
9b2e34ef6d [ARM] Use __ARM_ARCH and __ARM_FEATURE_LDREX instead of __ARM_ARCH__
2018-06-21  Christophe Lyon  <christophe.lyon@linaro.org>

	libatomic/
	* config/arm/arm-config.h (__ARM_ARCH__): Remove definitions, use
	__ARM_ARCH instead. Use __ARM_FEATURE_LDREX to define HAVE_STREX
	and HAVE_STREXBHD

	libgcc/
	* config/arm/lib1funcs.S (__ARM_ARCH__): Remove definitions, use
	__ARM_ARCH and __ARM_FEATURE_CLZ instead.
	(HAVE_ARM_CLZ): Remove definition, use __ARM_FEATURE_CLZ instead.
	* config/arm/ieee754-df.S: Use __ARM_FEATURE_CLZ instead of
	__ARM_ARCH__.
	* config/arm/ieee754-sf.S: Likewise.
	* config/arm/libunwind.S: Use __ARM_ARCH instead of __ARM_ARCH__.

From-SVN: r261841
2018-06-21 13:05:36 +02:00
Christophe Lyon
d1b0dd54ab [ARM] libgcc: Remove unsupported code for __ARM_ARCH__ < 4
2018-06-21  Christophe Lyon  <christophe.lyon@linaro.org>

	libgcc/
	* config/arm/ieee754-df.S: Remove code for __ARM_ARCH__ < 4, no
	longer supported.
	* config/arm/ieee754-sf.S: Likewise.

From-SVN: r261840
2018-06-21 13:01:05 +02:00
Michael Meissner
6a8886e45f re PR target/85358 (PowerPC: Using -mabi=ieeelongdouble -mcpu=power9 breaks __ibm128)
[gcc]
2018-06-18  Michael Meissner  <meissner@linux.ibm.com>

	PR target/85358
	* config/rs6000/rs6000-modes.def (toplevel): Rework the 128-bit
	floating point modes, so that IFmode is numerically greater than
	TFmode, which is greater than KFmode using FRACTIONAL_FLOAT_MODE
	to declare the ordering.  This prevents IFmode from being
	converted to TFmode when long double is IEEE 128-bit on an ISA 3.0
	machine.  Include rs6000-modes.h to share the fractional values
	between genmodes* and the rest of the compiler.
	(IFmode): Likewise.
	(KFmode): Likewise.
	(TFmode): Likewise.
	* config/rs6000/rs6000-modes.h: New file.
	* config/rs6000/rs6000.c (rs6000_debug_reg_global): Change the
	meaning of rs6000_long_double_size so that 126..128 selects an
	appropriate 128-bit floating point type.
	(rs6000_option_override_internal): Likewise.
	* config/rs6000/rs6000.h (toplevel): Include rs6000-modes.h.
	(TARGET_LONG_DOUBLE_128): Change the meaning of
	rs6000_long_double_size so that 126..128 selects an appropriate
	128-bit floating point type.
	(LONG_DOUBLE_TYPE_SIZE): Update comment.
	* config/rs6000/rs6000.md (trunciftf2): Correct the modes of the
	source and destination to match the standard usage.
	(truncifkf2): Likewise.
	(copysign<mode>3, IEEE iterator): Rework copysign of float128 on
	ISA 2.07 to use an explicit clobber, instead of passing in a
	temporary.
	(copysign<mode>3_soft): Likewise.

[libgcc]
2018-06-18  Michael Meissner  <meissner@linux.ibm.com>

	* config/rs6000/t-float128 (FP128_CFLAGS_SW): Compile float128
	support modules with -mno-gnu-attribute.
	* config/rs6000/t-float128-hw (FP128_CFLAGS_HW): Likewise.

From-SVN: r261712
2018-06-18 19:10:08 +00:00
Olivier Hainque
fb9970973a t-vxworks (LIBGCC_INCLUDES): Add -I$(MULTIBUILDTOP)../../gcc/include.
2018-06-07  Olivier Hainque  <hainque@adacore.com>

        * config/t-vxworks (LIBGCC_INCLUDES): Add
        -I$(MULTIBUILDTOP)../../gcc/include.
        * config/t-vxworks7: Likewise. Reformat a bit to match
        the t-vxworks layout.

From-SVN: r261273
2018-06-07 13:31:24 +00:00
Olga Makhotina
a548a5a1d6 config.gcc: Support "tremont".
2018-06-07  Olga Makhotina  <olga.makhotina@intel.com>

gcc/

        * config.gcc: Support "tremont".
        * config/i386/driver-i386.c (host_detect_local_cpu): Detect "tremont".
        * config/i386/i386-c.c (ix86_target_macros_internal): Handle
        PROCESSOR_TREMONT.
        * config/i386/i386.c (m_TREMONT): Define.
        (processor_target_table): Add "tremont".
        (PTA_TREMONT): Define.
        (ix86_lea_outperforms): Add TARGET_TREMONT.
        (get_builtin_code_for_version): Handle PROCESSOR_TREMONT.
        (fold_builtin_cpu): Add M_INTEL_TREMONT, replace M_INTEL_GOLDMONT
        and M_INTEL_GOLDMONT_PLUS.
        (fold_builtin_cpu): Add "tremont".
        (ix86_add_stmt_cost): Add TARGET_TREMONT.
        (ix86_option_override_internal): Add "tremont".
        * config/i386/i386.h (processor_costs): Define TARGET_TREMONT.
        (processor_type): Add PROCESSOR_TREMONT.
        * config/i386/x86-tune.def: Add m_TREMONT.
        * doc/invoke.texi: Add tremont as x86 -march=/-mtune= CPU type.

gcc/testsuite/

        * gcc.target/i386/funcspec-56.inc: Test arch=tremont.

libgcc/

        * config/i386/cpuinfo.h (processor_types): Add INTEL_TREMONT.

From-SVN: r261270
2018-06-07 13:07:05 +02:00
Chung-Ju Wu
cf3cd43d5a [NDS32] Support Linux target for nds32.
gcc/
	* config.gcc (nds32*): Use nds32-linux.opt and nds32-elf.opt.
	(nds32le-*-*, nds32be-*-*): Integrate checking process.
	(nds32*-*-*): Add glibc and uclibc conditions.
	* common/config/nds32/nds32-common.c (nds32_except_unwind_info): New.
	(TARGET_EXCEPT_UNWIND_INFO): Define.
	* config/nds32/elf.h: New file.
	* config/nds32/linux.h: New file.
	* config/nds32/nds32-elf.opt: New file.
	* config/nds32/nds32-linux.opt: New file.
	* config/nds32/nds32-fp-as-gp.c
	(pass_nds32_fp_as_gp::gate): Consider TARGET_LINUX_ABI.
	* config/nds32/nds32.c (nds32_conditional_register_usage): Consider
	TARGET_LINUX_ABI.
	(nds32_asm_file_end): Ditto.
	(nds32_print_operand): Ditto.
	(nds32_insert_attributes): Ditto.
	(nds32_init_libfuncs): New function.
	(TARGET_HAVE_TLS): Define.
	(TARGET_INIT_LIBFUNCS): Define.
	* config/nds32/nds32.h (TARGET_DEFAULT_RELAX): Apply different relax
	spec content.
	(TARGET_ELF): Apply different mcmodel setting.
	(LINK_SPEC, LIB_SPEC, STARTFILE_SPEC, ENDFILE_SPEC): The content has
	been migrated into elf.h and linux.h files.
	* config/nds32/nds32.md (add_pc): Consider TARGET_LINUX_ABI.
	* config/nds32/nds32.opt (mvh): Consider TARGET_LINUX_ABI.
	(mcmodel): The content has been migrated into nds32-elf.opt and
	nds32-linux.opt files.
	* config/nds32/t-elf: New file.
	* config/nds32/t-linux: New file.

libgcc/
	* config.host (nds32*-linux*): New.
	* config/nds32/linux-atomic.c: New file.
	* config/nds32/linux-unwind.h: New file.

Co-Authored-By: Kito Cheng <kito.cheng@gmail.com>
Co-Authored-By: Monk Chiang <sh.chiang04@gmail.com>

From-SVN: r261116
2018-06-02 14:22:12 +00:00
Uros Bizjak
8b8003ed54 re PR target/85591 (__builtin_cpu_is() is not detecting bdver2 with Model = 0x02)
PR target/85591
	* config/i386/cpuinfo.c (get_amd_cpu): Return
	AMDFAM15H_BDVER2 for AMDFAM15H model 0x2.

From-SVN: r261036
2018-05-31 21:45:54 +02:00
Kalamatee
54fd159056 lb1sf68.S (Laddsf$nf): Fix sign bit handling in path to Lf$finfty.
2018-05-23  Kalamatee  <kalamatee@gmail.com>

	* config/m68k/lb1sf68.S (Laddsf$nf): Fix sign bit handling in
	path to Lf$finfty.

From-SVN: r260626
2018-05-23 16:29:01 -06:00
Kito Cheng
09baee1ab1 RISC-V: Add RV32E support.
Kito Cheng <kito.cheng@gmail.com>
	Monk Chiang  <sh.chiang04@gmail.com>

	gcc/
	* common/config/riscv/riscv-common.c (riscv_parse_arch_string):
	Add support to parse rv32e*.  Clear MASK_RVE for rv32i and rv64i.
	* config.gcc (riscv*-*-*): Add support for rv32e* and ilp32e.
	* config/riscv/riscv-c.c (riscv_cpu_cpp_builtins): Define
	__riscv_32e when TARGET_RVE.  Handle ABI_ILP32E as soft-float ABI.
	* config/riscv/riscv-opts.h (riscv_abi_type): Add ABI_ILP32E.
	* config/riscv/riscv.c (riscv_compute_frame_info): When TARGET_RVE,
	compute save_libcall_adjustment properly.
	(riscv_option_override): Call error if TARGET_RVE and not ABI_ILP32E.
	(riscv_conditional_register_usage): Handle TARGET_RVE and ABI_ILP32E.
	* config/riscv/riscv.h (UNITS_PER_FP_ARG): Handle ABI_ILP32E.
	(STACK_BOUNDARY, ABI_STACK_BOUNDARY): Handle TARGET_RVE.
	(GP_REG_LAST, MAX_ARGS_IN_REGISTERS): Likewise.
	(ABI_SPEC): Handle mabi=ilp32e.
	* config/riscv/riscv.opt (abi_type): Add ABI_ILP32E.
	(RVE): Add RVE mask.
	* doc/invoke.texi (RISC-V options) <-mabi>: Add ilp32e info.
	<-march>: Add rv32e as an example.

	gcc/testsuite/
	* gcc.dg/stack-usage-1.c: Add support for rv32e.

	libgcc/
	* config/riscv/save-restore.S: Add support for rv32e.

Co-Authored-By: Jim Wilson <jimw@sifive.com>
Co-Authored-By: Monk Chiang <sh.chiang04@gmail.com>

From-SVN: r260384
2018-05-18 15:53:55 -07:00
Kyrylo Tkachov
c3f808d3f8 [arm][1/2] Remove support for deprecated -march=armv5 and armv5e
The -march=armv5 and armv5e options have been deprecated in GCC 7 [1].
This patch removes support for them.
It's mostly mechanical stuff. The functionality that was previously
gated on arm_arch5 is now gated on arm_arch5t and the functionality
that was gated on arm_arch5e is now gated on arm_arch5te.

A path in TARGET_OS_CPP_BUILTINS for VxWorks is now unreachable and
therefore is deleted.

References to armv5 and armv5e are deleted/updated throughout the
source tree and testsuite.

Bootstrapped and tested on arm-none-linux-gnueabihf.
Also built a cc1 for arm-wrs-vxworks as a sanity check.

        * config/arm/arm-cpus.in (armv5, armv5e): Delete features.
        (armv5t, armv5te): New features.
        (ARMv5, ARMv5e): Delete fgroups.
        (ARMv5t, ARMv5te): Adjust for above changes.
        (ARMv6m): Likewise.
        (armv5, armv5e): Delete arches.
        * config/arm/arm.md (*call_reg_armv5): Use arm_arch5t instead of
        arm_arch5.
        (*call_reg_arm): Likewise.
        (*call_value_reg_armv5): Likewise.
        (*call_value_reg_arm): Likewise.
        (*call_symbol): Likewise.
        (*call_value_symbol): Likewise.
        (*sibcall_insn): Likewise.
        (*sibcall_value_insn): Likewise.
        (clzsi2): Likewise.
        (prefetch): Likewise.
        (define_split and define_peephole2 dependent on arm_arch5):
        Likewise.
        * config/arm/arm.h (TARGET_LDRD): Use arm_arch5te instead of
        arm_arch5e.
        (TARGET_ARM_QBIT): Likewise.
        (TARGET_DSP_MULTIPLY): Likewise.
        (enum base_architecture): Delete BASE_ARCH_5, BASE_ARCH_5E.
        (arm_arch5, arm_arch5e): Delete.
        (arm_arch5t, arm_arch5te): Declare.
        * config/arm/arm.c (arm_arch5, arm_arch5e): Delete.
        (arm_arch5t): Declare.
        (arm_option_reconfigure_globals): Update for the above.
        (arm_options_perform_arch_sanity_checks): Update comment, replace
        use of arm_arch5 with arm_arch5t.
        (use_return_insn): Likewise.
        (arm_emit_call_insn): Likewise.
        (output_return_instruction): Likewise.
        (arm_final_prescan_insn): Likewise.
        (arm_coproc_builtin_available): Likewise.
        * config/arm/arm-c.c (arm_cpu_builtins): Replace arm_arch5 and
        arm_arch5e with arm_arch5t and arm_arch5te.
        * config/arm/arm-protos.h (arm_arch5, arm_arch5e): Delete.
        (arm_arch5t, arm_arch5te): Declare.
        * config/arm/arm-tables.opt: Regenerate.
        * config/arm/t-arm-elf: Remove references to armv5, armv5e.
        * config/arm/t-multilib: Likewise.
        * config/arm/thumb1.md (*call_reg_thumb1_v5): Check arm_arch5t
        instead of arm_arch5.
        (*call_reg_thumb1): Likewise.
        (*call_value_reg_thumb1_v5): Likewise.
        (*call_value_reg_thumb1): Likewise.
        * config/arm/vxworks.h (TARGET_OS_CPP_BUILTINS): Remove now
        unreachable path.
        * doc/invoke.texi (ARM Options): Remove references to armv5, armv5e.

        * gcc.target/arm/pr40887.c: Update comment.
        * lib/target-supports.exp: Don't generate effective target checks
        and related helpers for armv5.  Update comment.
        * gcc.target/arm/armv5_thumb_isa.c: Delete.
        * gcc.target/arm/di-longlong64-sync-withhelpers.c: Update effective
        target check and options.

        * config/arm/libunwind.S: Update comment relating to armv5.

From-SVN: r260362
2018-05-18 13:08:16 +00:00
Jerome Lambourg
fcf4f8311e arm_cmse.h (cmse_nsfptr_create, [...]): Remove #include <stdint.h>.
2018-05-17  Jerome Lambourg  <lambourg@adacore.com>

	gcc/
	* config/arm/arm_cmse.h (cmse_nsfptr_create, cmse_is_nsfptr): Remove
	#include <stdint.h>.  Replace intptr_t with __INTPTR_TYPE__.

	libgcc/
	* config/arm/cmse.c (cmse_check_address_range): Replace
	UINTPTR_MAX with __UINTPTR_MAX__ and uintptr_t with __UINTPTR_TYPE__.

From-SVN: r260330
2018-05-17 16:36:36 +00:00
Olga Makhotina
74b2bb19f3 config.gcc: Support "goldmont-plus".
2018-05-17  Olga Makhotina  <olga.makhotina@intel.com>

gcc/

	* config.gcc: Support "goldmont-plus".
	* config/i386/driver-i386.c (host_detect_local_cpu): Detect
	"goldmont-plus".
	* config/i386/i386-c.c (ix86_target_macros_internal): Handle
	PROCESSOR_GOLDMONT_PLUS.
	* config/i386/i386.c (m_GOLDMONT_PLUS): Define.
	(processor_target_table): Add "goldmont-plus".
	(PTA_GOLDMONT_PLUS): Define.
	(ix86_lea_outperforms): Add TARGET_GOLDMONT_PLUS.
	(get_builtin_code_for_version): Handle PROCESSOR_GOLDMONT_PLUS.
	(fold_builtin_cpu): Add M_INTEL_GOLDMONT_PLUS.
	(fold_builtin_cpu): Add "goldmont-plus".
	(ix86_add_stmt_cost): Add TARGET_GOLDMONT_PLUS.
	(ix86_option_override_internal): Add "goldmont-plus".
	* config/i386/i386.h (processor_costs): Define TARGET_GOLDMONT_PLUS.
	(processor_type): Add PROCESSOR_GOLDMONT_PLUS.
	* config/i386/x86-tune.def: Add m_GOLDMONT_PLUS.
	* doc/invoke.texi: Add goldmont-plus as x86 -march=/-mtune= CPU type.

libgcc/

	* config/i386/cpuinfo.h (processor_types): Add INTEL_GOLDMONT_PLUS.
	* config/i386/cpuinfo.c (get_intel_cpu): Detect Goldmont Plus.

gcc/testsuite/

	* gcc.target/i386/builtin_target.c: Test goldmont-plus.
	* gcc.target/i386/funcspec-56.inc: Test arch=goldmont-plus.

From-SVN: r260307
2018-05-17 10:13:23 +02:00
Olga Makhotina
50e461dfe3 config.gcc: Support "goldmont".
2018-05-08  Olga Makhotina  <olga.makhotina@intel.com>

gcc/

	* config.gcc: Support "goldmont".
	* config/i386/driver-i386.c (host_detect_local_cpu): Detect "goldmont".
	* config/i386/i386-c.c (ix86_target_macros_internal): Handle
	PROCESSOR_GOLDMONT.
	* config/i386/i386.c (m_GOLDMONT): Define.
	(processor_target_table): Add "goldmont".
	(PTA_GOLDMONT): Define.
	(ix86_lea_outperforms): Add TARGET_GOLDMONT.
	(get_builtin_code_for_version): Handle PROCESSOR_GOLDMONT.
	(fold_builtin_cpu): Add M_INTEL_GOLDMONT.
	(fold_builtin_cpu): Add "goldmont".
	(ix86_add_stmt_cost): Add TARGET_GOLDMONT.
	(ix86_option_override_internal): Add "goldmont".
	* config/i386/i386.h (processor_costs): Define TARGET_GOLDMONT.
	(processor_type): Add PROCESSOR_GOLDMONT.
	* config/i386/i386.md: Add CPU "glm".
	* config/i386/glm.md: New file.
	* config/i386/x86-tune.def: Add m_GOLDMONT.
	* doc/invoke.texi: Add goldmont as x86 -march=/-mtune= CPU type.

libgcc/
	* config/i386/cpuinfo.h (processor_types): Add INTEL_GOLDMONT.
	* config/i386/cpuinfo.c (get_intel_cpu): Detect Goldmont.

gcc/testsuite/

	* gcc.target/i386/builtin_target.c: Test goldmont.
	* gcc.target/i386/funcspec-56.inc: Tests for arch=goldmont and
	arch=silvermont.

From-SVN: r260042
2018-05-08 14:23:08 +02:00
Andreas Tobler
8f479d7a35 re PR libgcc/84292 (__sync_add_and_fetch returns the old value instead of the new value)
2018-04-27  Andreas Tobler  <andreast@gcc.gnu.org>
	    Maryse Levavasseur <maryse.levavasseur@stormshield.eu>

	PR libgcc/84292
	* config/arm/freebsd-atomic.c (SYNC_OP_AND_FETCH_N): Fix the
	op_and_fetch to return the right result.

Co-Authored-By: Maryse Levavasseur <maryse.levavasseur@stormshield.eu>

From-SVN: r259722
2018-04-27 21:14:05 +02:00
Alan Modra
ae0432915e PR85532, crtend.o built without --enable-initfini-array has bad .eh_frame
PR libgcc/85532
	* config/rs6000/t-crtstuff (CRTSTUFF_T_CFLAGS): Add
	-fno-asynchronous-unwind-tables.

From-SVN: r259702
2018-04-27 18:36:39 +09:30
Chung-Ju Wu
ba169b7424 [NDS32] Fix incorrect settings in sfp-machine.h and t-nds32-newlib for hard fp.
libgcc/
	* config/nds32/sfp-machine.h: Fix settings for NDS32_ABI_2FP_PLUS.
	* config/nds32/t-nds32-newlib (HOST_LIBGCC2_CFLAGS): Use -fwrapv.

From-SVN: r259645
2018-04-25 12:08:14 +00:00
H.J. Lu
ffc2fc06e3 x86: Update __CET__ check
__CET__ has been changed by revision 259522:

commit d59cfa9a4064339cf2bd2da828c4c133f13e57f0
Author: hjl <hjl@138bc75d-0d04-0410-961f-82ee72b054a4>
Date:   Fri Apr 20 13:30:13 2018 +0000

    Define __CET__ for -fcf-protection and remove -mibt

to

    (__CET__ & 1) != 0: -fcf-protection=branch or -fcf-protection=full
    (__CET__ & 2) != 0: -fcf-protection=return or -fcf-protection=full

We should check (__CET__ & 2) != 0 for shadow stack.

libgcc/

	* config/i386/linux-unwind.h: Add (__CET__ & 2) != 0 check
	when including "config/i386/shadow-stack-unwind.h".

libitm/

	* config/x86/sjlj.S (_ITM_beginTransaction): Add
	(__CET__ & 2) != 0 check for shadow stack.
	(GTM_longjmp): Likewise.

From-SVN: r259621
2018-04-24 15:15:51 -07:00
Michael Meissner
661eb8f9e5 re PR target/85456 (PowerPC: Using -mabi=ieeelongdouble calls wrong function for __builtin_powi.)
[libgcc]
2018-04-20  Michael Meissner  <meissner@linux.ibm.com>

	PR target/85456
	* config/rs6000/_powikf2.c: New file.  Add support for the
	__builtin_powil function when long double is IEEE 128-bit floating
	point.
	* config/rs6000/float128-ifunc.c (__powikf2_resolve): Add
	__powikf2 support.
	(__powikf2): Likewise.
	* config/rs6000/quad-float128.h (__powikf2_sw): Likewise.
	(__powikf2_hw): Likewise.
	(__powikf2): Likewise.
	* config/rs6000/t-float128 (fp128_ppc_funcs): Likewise.
	* config/rs6000/t-float128-hw (fp128_hw_func): Likewise.
	(_powikf2-hw.c): Likewise.

[gcc]
2018-04-20  Michael Meissner  <meissner@linux.ibm.com>

	PR target/85456
	* config/rs6000/rs6000.c (init_float128_ieee): Add support to call
	__powikf2 when long double is IEEE 128-bit.

[gcc/testsuite]
2018-04-20  Michael Meissner  <meissner@linux.ibm.com>

	PR target/85456
	* gcc.target/powerpc/pr85456.c: New test.

From-SVN: r259533
2018-04-20 21:27:08 +00:00
H.J. Lu
5707be3c7d libgcc/CET: Skip signal frames when unwinding shadow stack
When -fcf-protection -mcet is used, I got

FAIL: g++.dg/eh/sighandle.C

(gdb) bt
 #0  _Unwind_RaiseException (exc=exc@entry=0x416ed0)
    at /export/gnu/import/git/sources/gcc/libgcc/unwind.inc:140
 #1  0x00007ffff7d9936b in __cxxabiv1::__cxa_throw (obj=<optimized out>,
    tinfo=0x403dd0 <typeinfo for int@@CXXABI_1.3>, dest=0x0)
    at /export/gnu/import/git/sources/gcc/libstdc++-v3/libsupc++/eh_throw.cc:90
 #2  0x0000000000401255 in sighandler (signo=11, si=0x7fffffffd6f8,
    uc=0x7fffffffd5c0)
    at /export/gnu/import/git/sources/gcc/gcc/testsuite/g++.dg/eh/sighandle.C:9
 #3  <signal handler called> <<<< Signal frame which isn't on shadow stack
 #4  dosegv ()
    at /export/gnu/import/git/sources/gcc/gcc/testsuite/g++.dg/eh/sighandle.C:14
 #5  0x00000000004012e3 in main ()
    at /export/gnu/import/git/sources/gcc/gcc/testsuite/g++.dg/eh/sighandle.C:30
(gdb) p frames
$6 = 5
(gdb)

frame count should be 4, not 5.  This patch skips signal frames when
unwinding shadow stack.

gcc/testsuite/

	PR libgcc/85334
	* g++.dg/torture/pr85334.C: New test.

libgcc/

	PR libgcc/85334
	* unwind-generic.h (_Unwind_Frames_Increment): New.
	* config/i386/shadow-stack-unwind.h (_Unwind_Frames_Increment):
	Likewise.
	* unwind.inc (_Unwind_RaiseException_Phase2): Increment frame
	count with _Unwind_Frames_Increment.
	(_Unwind_ForcedUnwind_Phase2): Likewise.

From-SVN: r259502
2018-04-19 10:05:39 -07:00