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Support AMD64/Intel ISAs in assembler/disassembler AMD64 spec and Intel64 spec differ in direct unconditional branches in 64-bit mode. AMD64 supports direct unconditional branches with 16-bit offset via the data size prefix, which truncates RIP to 16 bits, while the data size prefix is ignored by Intel64. This patch adds -mamd64/-mintel64 option to x86-64 assembler and -Mamd64/-Mintel64 option to x86-64 disassembler. The most permissive ISA, which is AMD64, is the default. GDB can add an option, similar to (gdb) help set disassembly-flavor Set the disassembly flavor. The valid values are "att" and "intel", and the default value is "att". to select which ISA to disassemble. binutils/ PR binutis/18386 * doc/binutils.texi: Document -Mamd64 and -Mintel64. gas/ PR binutis/18386 * config/tc-i386.c (OPTION_MAMD64): New. (OPTION_MINTEL64): Likewise. (md_longopts): Add -mamd64 and -mintel64. (md_parse_option): Handle OPTION_MAMD64 and OPTION_MINTEL64. (md_show_usage): Add -mamd64 and -mintel64. * doc/c-i386.texi: Document -mamd64 and -mintel64. gas/testsuite/ PR binutis/18386 * gas/i386/i386.exp: Run x86-64-branch-2 and x86-64-branch-3. * gas/i386/x86-64-branch.d: Also pass -Mintel64 to objdump. * gas/i386/ilp32/x86-64-branch.d: Likewise. * gas/i386/x86-64-branch-2.d: New file. * gas/i386/x86-64-branch-2.s: Likewise. * gas/i386/x86-64-branch-3.l: Likewise. * gas/i386/x86-64-branch-3.s: Likewise. ld/testsuite/ PR binutis/18386 * ld-x86-64/tlsgdesc.dd: Also pass -Mintel64 to objdump. * ld-x86-64/tlspic.dd: Likewise. * ld-x86-64/x86-64.exp (x86_64tests): Also pass -Mintel64 to objdump for tlspic.dd and tlsgdesc.dd. opcodes/ PR binutis/18386 * i386-dis.c: Add comments for '@'. (x86_64_table): Use '@' on call/jmp for X86_64_E8/X86_64_E9. (enum x86_64_isa): New. (isa64): Likewise. (print_i386_disassembler_options): Add amd64 and intel64. (print_insn): Handle amd64 and intel64. (putop): Handle '@'. (OP_J): Don't ignore the operand size prefix for AMD64 in 64-bit. * i386-gen.c (cpu_flags): Add CpuAMD64 and CpuIntel64. * i386-opc.h (AMD64): New. (CpuIntel64): Likewise. (i386_cpu_flags): Add cpuamd64 and cpuintel64. * i386-opc.tbl: Add direct call/jmp with Disp16|Disp32 for AMD64. Mark direct call/jmp without Disp16|Disp32 as Intel64. * i386-init.h: Regenerated. * i386-tbl.h: Likewise.
2015-05-15 18:47:39 +02:00
2015-05-15 H.J. Lu <hongjiu.lu@intel.com>
PR binutis/18386
* config/tc-i386.c (OPTION_MAMD64): New.
(OPTION_MINTEL64): Likewise.
(md_longopts): Add -mamd64 and -mintel64.
(md_parse_option): Handle OPTION_MAMD64 and OPTION_MINTEL64.
(md_show_usage): Add -mamd64 and -mintel64.
* doc/c-i386.texi: Document -mamd64 and -mintel64.
Add -mshared option to x86 ELF assembler This patch adds -mshared option to x86 ELF assembler. By default, assembler will optimize out non-PLT relocations against defined non-weak global branch targets with default visibility. The -mshared option tells the assembler to generate code which may go into a shared library where all non-weak global branch targets with default visibility can be preempted. The resulting code is slightly bigger. This option only affects the handling of branch instructions. This Linux kernel patch is needed to create a working x86 Linux kernel if it hasn't been applied: diff --git a/arch/x86/kernel/head_64.S b/arch/x86/kernel/head_64.S index ae6588b..b91a00c 100644 --- a/arch/x86/kernel/head_64.S +++ b/arch/x86/kernel/head_64.S @@ -339,8 +339,8 @@ early_idt_handlers: i = i + 1 .endr -/* This is global to keep gas from relaxing the jumps */ -ENTRY(early_idt_handler) +/* This is weak to keep gas from relaxing the jumps */ +WEAK(early_idt_handler) cld cmpl $2,(%rsp) # X86_TRAP_NMI -- gas/ * config/tc-i386.c (shared): New. (OPTION_MSHARED): Likewise. (elf_symbol_resolved_in_segment_p): Add relocation argument. Check PLT relocations and shared. (md_estimate_size_before_relax): Pass fragP->fr_var to elf_symbol_resolved_in_segment_p. (md_longopts): Add -mshared. (md_show_usage): Likewise. (md_parse_option): Handle OPTION_MSHARED. * doc/c-i386.texi: Document -mshared. gas/testsuite/ * gas/i386/i386.exp: Don't run pcrel for ELF targets. Run pcrel-elf, relax-4 and x86-64-relax-3 for ELF targets. * gas/i386/pcrel-elf.d: New file. * gas/i386/relax-4.d: Likewise. * gas/i386/x86-64-relax-3.d: Likewise. * gas/i386/relax-3.d: Pass -mshared to assembler. Updated. * gas/i386/x86-64-relax-2.d: Likewise. * gas/i386/relax-3.s: Add test for PLT relocation.
2015-05-15 12:17:31 +02:00
2015-05-15 H.J. Lu <hongjiu.lu@intel.com>
* config/tc-i386.c (shared): New.
(OPTION_MSHARED): Likewise.
(elf_symbol_resolved_in_segment_p): Add relocation argument.
Check PLT relocations and shared.
(md_estimate_size_before_relax): Pass fragP->fr_var to
elf_symbol_resolved_in_segment_p.
(md_longopts): Add -mshared.
(md_show_usage): Likewise.
(md_parse_option): Handle OPTION_MSHARED.
* doc/c-i386.texi: Document -mshared.
Don't add the zlib header to SHF_COMPRESSED section In a SHF_COMPRESSED compressed section, the raw compressed data should begin immediately after the compression header. This patch removes the extra zlib header from the SHF_COMPRESSED section. bfd/ * bfd.c (bfd_update_compression_header): Also write the zlib header if the SHF_COMPRESSED bit cleared.. (bfd_check_compression_header): Return the uncompressed size. * compress.c (decompress_contents): Don't skip the zlib header. (bfd_compress_section_contents): Properly handle ELFCOMPRESS_ZLIB, which doesn't have the zlib header. (bfd_init_section_decompress_status): Likewise. (bfd_get_full_section_contents): Updated. (bfd_is_section_compressed): Likewise. (bfd_is_section_compressed_with_header): Return the uncompressed size. * elf.c (_bfd_elf_make_section_from_shdr): Updated. * bfd-in2.h: Regenerated. binutils/ * readelf.c (uncompress_section_contents): Add a parameter for uncompressed size. Don't check the zlib header. (load_specific_debug_section): Updated. binutils/testsuite/ * binutils-all/compress.exp: Replace "$OBJDUMP -s -j .debug_info" with "$OBJDUMP -W". * binutils-all/libdw2-compressedgabi.out: Updated. gas/ 2015-05-14 H.J. Lu <hongjiu.lu@intel.com> * write.c (compress_debug): Don't write the zlib header, which is handled by bfd_update_compression_header.
2015-05-15 00:58:51 +02:00
2015-05-14 H.J. Lu <hongjiu.lu@intel.com>
* write.c (compress_debug): Don't write the zlib header, which
is handled by bfd_update_compression_header.
xtensa: fix gas trampolines regression Extra condition 'abs (addr - trampaddr) < J_RANGE / 2' for trampoline selection results in regressions: when relaxable jump is little longer than J_RANGE so that single trampoline makes two new jumps, one longer than J_RANGE / 2 and one shorter, correct trampoline cannot be found. Drop that condition. 2015-05-13 Max Filippov <jcmvbkbc@gmail.com> gas/ * config/tc-xtensa.c (xtensa_relax_frag): Allow trampoline to be closer than J_RANGE / 2 to jump frag. gas/testsuite/ * gas/xtensa/trampoline.s: Add regression testcase.
2015-05-10 00:02:31 +02:00
2015-05-13 Max Filippov <jcmvbkbc@gmail.com>
* config/tc-xtensa.c (xtensa_relax_frag): Allow trampoline to be
closer than J_RANGE / 2 to jump frag.
Default e_machine to EM_IAMCU for i?86-*-elfiamcu This patch sets the default ELF output format of assembler and linker to EM_IAMCU when binutils is configured to i?86-*-elfiamcu target. gas/ * configure.tgt (arch): Set to iamcu for i386-*-elfiamcu target. * config/tc-i386.c (i386_mach): Support iamcu. (i386_target_format): Likewise. ld/ * configure.tgt: Support i[3-7]86-*-elfiamcu target. ld/testsuite/ * ld-i386/i386.exp (iamcu_tests): Run iamcu-4. * ld-i386/iamcu-4.d: New file.
2015-05-11 21:01:57 +02:00
2015-05-11 H.J. Lu <hongjiu.lu@intel.com>
* configure.tgt (arch): Set to iamcu for i386-*-elfiamcu target.
* config/tc-i386.c (i386_mach): Support iamcu.
(i386_target_format): Likewise.
Add Intel MCU support to gas -march=iamcu must be passed to i386 assembler to generate Intel MCU object file. gas/ * config/tc-i386.c (cpu_arch): Add iamcu. (i386_align_code): Handle PROCESSOR_IAMCU. (i386_arch): Likewise. (i386_mach): Likewise. (i386_target_format): Likewise. (valid_iamcu_cpu_flags): New function. (check_cpu_arch_compatible): Only allow Intel MCU instructions when targeting Intel MCU. (set_cpu_arch): Call valid_iamcu_cpu_flags to check if CPU flags are valid for Intel MCU. (md_parse_option): Likewise. * tc-i386.h (ELF_TARGET_IAMCU_FORMAT): New. (processor_type): Add PROCESSOR_IAMCU. * doc/c-i386.texi: Document iamcu. gas/testsuite/ * gas/i386/i386.exp: Run iamcu-1, iamcu-2, iamcu-3, iamcu-inval-1, iamcu-inval-2 and iamcu-inval-3. * gas/i386/iamcu-1.d: New file. * gas/i386/iamcu-1.s: Likewise. * gas/i386/iamcu-2.d: Likewise. * gas/i386/iamcu-2.s: Likewise. * gas/i386/iamcu-3.d: Likewise. * gas/i386/iamcu-3.s: Likewise. * gas/i386/iamcu-inval-1.l: Likewise. * gas/i386/iamcu-inval-1.s: Likewise. * gas/i386/iamcu-inval-2.l: Likewise. * gas/i386/iamcu-inval-2.s: Likewise. * gas/i386/iamcu-inval-3.l: Likewise. * gas/i386/iamcu-inval-3.s: Likewise.
2015-05-11 20:11:19 +02:00
2015-05-11 H.J. Lu <hongjiu.lu@intel.com>
* config/tc-i386.c (cpu_arch): Add iamcu.
(i386_align_code): Handle PROCESSOR_IAMCU.
(i386_arch): Likewise.
(i386_mach): Likewise.
(i386_target_format): Likewise.
(valid_iamcu_cpu_flags): New function.
(check_cpu_arch_compatible): Only allow Intel MCU instructions
when targeting Intel MCU.
(set_cpu_arch): Call valid_iamcu_cpu_flags to check if CPU flags
are valid for Intel MCU.
(md_parse_option): Likewise.
* tc-i386.h (ELF_TARGET_IAMCU_FORMAT): New.
(processor_type): Add PROCESSOR_IAMCU.
* doc/c-i386.texi: Document iamcu.
Change ARM symbol name verification code so that it only triggers when the form "name = val" is used. PR gas/18347 * config/tc-arm.h (TC_EQUAL_IN_INSN): Define. * config/tc-arm.c (arm_tc_equal_in_insn): New function. Move the symbol name checking code to here from... (md_undefined_symbo): ... here.
2015-05-08 18:28:26 +02:00
2015-05-08 Nick Clifton <nickc@redhat.com>
PR gas/18347
* config/tc-arm.h (TC_EQUAL_IN_INSN): Define.
* config/tc-arm.c (arm_tc_equal_in_insn): New function. Move
the symbol name checking code to here from...
(md_undefined_symbo): ... here.
Optimize branches to non-weak symbols with visibility Branches to global non-weak symbols defined in the same segment with non-default visibility can be optimized the same way as branches to local symbols. gas/ * config/tc-i386.c (elf_symbol_resolved_in_segment_p): New. (md_estimate_size_before_relax): Use it. gas/testsuite/ * gas/i386/i386.exp: Run relax-3 and x86-64-relax-2. * gas/i386/relax-3.d: New file. * gas/i386/relax-3.s: Likewise. * gas/i386/x86-64-relax-2.d: Likewise.
2015-05-07 18:13:39 +02:00
2015-05-07 H.J. Lu <hongjiu.lu@intel.com>
* config/tc-i386.c (elf_symbol_resolved_in_segment_p): New.
(md_estimate_size_before_relax): Use it.
gas: typo in comment fixed. gas/ChangeLog: 2015-05-06 Jose E. Marchesi <jose.marchesi@oracle.com> * config/tc-sparc.c: Typo in comment fixed.
2015-05-01 19:16:59 +02:00
2015-05-06 Jose E. Marchesi <jose.marchesi@oracle.com>
* config/tc-sparc.c: Typo in comment fixed.
gas: support for the sparc %ncc condition codes register. gas/ChangeLog: 2015-05-06 Jose E. Marchesi <jose.marchesi@oracle.com> * config/tc-sparc.c (sparc_ip): Support the %ncc "natural" condition codes * doc/c-sparc.texi (Sparc-Regs): Document %ncc. gas/testsuite/ChangeLog: 2015-05-06 Jose E. Marchesi <jose.marchesi@oracle.com> * gas/sparc/natural.s: New file. * gas/sparc/natural-32.s: Likewise. * gas/sparc/natural.d: Likewise. * gas/sparc/natural-32.d: Likewise. * gas/sparc/sparc.exp (sparc_elf_setup): Run the tests natural and natural-32.
2015-05-01 02:17:20 +02:00
2015-05-06 Jose E. Marchesi <jose.marchesi@oracle.com>
* config/tc-sparc.c (sparc_ip): Support the %ncc "natural"
condition codes
* doc/c-sparc.texi (Sparc-Regs): Document %ncc.
Update GAS documentation to note that dollar local labels are only supported on some targets. * doc/as.texinfo (Dollar Local Labels): Note that these are only supported on some targets.
2015-05-06 14:13:10 +02:00
2015-05-06 Nick Clifton <nickc@redhat.com>
* doc/as.texinfo (Dollar Local Labels): Note that these are only
supported on some targets.
[AArch64] Record instruction alignment for .inst directive 2015-05-06 Renlin Li <renlin.li@arm.com> gas/ * config/tc-aarch64.c (mapping_state): Recording alignment before exit. gas/testsuite/ * gas/aarch64/codealign_1.s: New. * gas/aarch64/codealign_1.d: New.
2015-05-06 13:18:19 +02:00
2015-05-06 Renlin Li <renlin.li@arm.com>
* config/tc-aarch64.c (mapping_state): Recording alignment before exit.
[AARCH64] Positively emit symbols for alignment 2015-05-05 Renlin Li <renlin.li@arm.com> gas/ * config/tc-aarch64.c (aarch64_init_frag): Always generate mapping symbols. gas/testsuite/ * gas/aarch64/mapping_5.d: New. * gas/aarch64/mapping_5.s: New. * gas/aarch64/mapping_6.d: New. * gas/aarch64/mapping_6.s: New.
2015-05-05 18:48:18 +02:00
2015-05-05 Renlin Li <renlin.li@arm.com>
* config/tc-aarch64.c (aarch64_init_frag): Always generate mapping
symbols.
Add support to the MSP430 linker for the automatic placement of code and data into either low or high memory regions. gas * config/tc-msp430.c (MAX_OP_LEN): Increase to 4096. (msp430_make_init_symbols): New function. (msp430_section): Call it. (msp430_frob_section): Likewise. ld * emulparams/msp430elf.sh (TEMPLATE_NAME): Change to msp430. * scripttempl/msp430.sc (.text): Add .lower.text and .either.text. (.data): Add .lower.data and .either.data. (.bss): Add .lower.bss and .either.bss. (.rodata): Add .lower.rodata and .either.rodata. * emultempl/msp430.em: New file. Implements a new orphan placement algorithm that divides sections between lower and upper memory regions. * Makefile.am (emsp430elf.c): Depend upon msp430.em. *emsp430X.c): Likewise. * Makefine.in: Regenerate.
2015-05-05 14:38:00 +02:00
2015-05-05 Nick Clifton <nickc@redhat.com>
* config/tc-msp430.c (MAX_OP_LEN): Increase to 4096.
(msp430_make_init_symbols): New function.
(msp430_section): Call it.
(msp430_frob_section): Likewise.
xtensa: optimize trampolines relaxation Currently every fixup in the current segment is checked when relaxing trampoline frag. This is very expensive. Make a searchable array of fixups pointing at potentially oversized jumps at the beginning of every relaxation pass and only check subset of this cache in the reach of single jump from the trampoline frag currently being relaxed. Original profile: % time self children called name ----------------------------------------- 370.16 593.38 12283048/12283048 relax_segment 98.4 370.16 593.38 12283048 xtensa_relax_frag 58.91 269.26 2691463834/2699602236 xtensa_insnbuf_from_chars 68.35 68.17 811266668/813338977 S_GET_VALUE 36.85 29.51 2684369246/2685538060 xtensa_opcode_decode 28.34 8.84 2684369246/2685538060 xtensa_format_get_slot 12.39 5.94 2691463834/2699775044 xtensa_format_decode 0.03 4.60 4101109/4101109 relax_frag_for_align 0.18 1.76 994617/994617 relax_frag_immed 0.07 0.09 24556277/24851220 new_logical_line 0.06 0.00 12283048/14067410 as_where 0.04 0.00 7094588/15460506 xtensa_format_num_slots 0.00 0.00 1/712477 xtensa_insnbuf_alloc ----------------------------------------- Same data, after optimization: % time self children called name ----------------------------------------- 0.51 7.47 12283048/12283048 relax_segment 58.0 0.51 7.47 12283048 xtensa_relax_frag 0.02 4.08 4101109/4101109 relax_frag_for_align 0.18 1.39 994617/994617 relax_frag_immed 0.01 0.98 555/555 xtensa_cache_relaxable_fixups 0.21 0.25 7094588/16693271 xtensa_insnbuf_from_chars 0.06 0.12 24556277/24851220 new_logical_line 0.06 0.00 7094588/15460506 xtensa_format_num_slots 0.02 0.04 7094588/16866079 xtensa_format_decode 0.05 0.00 12283048/14067410 as_where 0.00 0.00 1/712477 xtensa_insnbuf_alloc 0.00 0.00 93808/93808 xtensa_find_first_cached_fixup ----------------------------------------- 2015-05-02 Max Filippov <jcmvbkbc@gmail.com> gas/ * config/tc-xtensa.c (cached_fixupS, fixup_cacheS): New typedefs. (struct cached_fixup, struct fixup_cache): New structures. (fixup_order, xtensa_make_cached_fixup), (xtensa_realloc_fixup_cache, xtensa_cache_relaxable_fixups), (xtensa_find_first_cached_fixup, xtensa_delete_cached_fixup), (xtensa_add_cached_fixup): New functions. (xtensa_relax_frag): Cache fixups pointing at potentially oversized jumps at the beginning of every relaxation pass. Only check subset of this cache in the reach of single jump from the trampoline frag currently being relaxed.
2015-05-01 10:39:12 +02:00
2015-05-02 Max Filippov <jcmvbkbc@gmail.com>
* config/tc-xtensa.c (cached_fixupS, fixup_cacheS): New typedefs.
(struct cached_fixup, struct fixup_cache): New structures.
(fixup_order, xtensa_make_cached_fixup),
(xtensa_realloc_fixup_cache, xtensa_cache_relaxable_fixups),
(xtensa_find_first_cached_fixup, xtensa_delete_cached_fixup),
(xtensa_add_cached_fixup): New functions.
(xtensa_relax_frag): Cache fixups pointing at potentially
oversized jumps at the beginning of every relaxation pass. Only
check subset of this cache in the reach of single jump from the
trampoline frag currently being relaxed.
Fix typos in previous patch. * config/rl78-parse.y (MULU): Remove ISA_G14. (MULH, DIVHU, DIVWU, MACHI, MACH): Update error strings.
2015-05-01 21:08:07 +02:00
2015-05-01 Nick Clifton <nickc@redhat.com>
* config/rl78-parse.y (MULU): Remove ISA_G14.
(MULH, DIVHU, DIVWU, MACHI, MACH): Update error strings.
Remove i386_elf_emit_arch_note This x86 assembler patch: https://sourceware.org/ml/binutils/2001-11/msg00344.html generates a .note section for .arch directive so that GDB can tell which architecture an i386 binary belongs: https://sourceware.org/ml/binutils/2001-11/msg00271.html However, x86 assembly code can have any instructions. A .note section doesn't help. This patch removes it. gas/ * config/tc-i386.c (i386_elf_emit_arch_note): Removed. * config/tc-i386.h (md_end): Likewise. (i386_elf_emit_arch_note): Likewise. gas/testsuite/ * gas/i386/i386.exp: Run note. * gas/i386/note.d: New file. * gas/i386/note.s: Likewise.
2015-05-01 17:29:16 +02:00
2015-05-01 H.J. Lu <hongjiu.lu@intel.com>
* config/tc-i386.c (i386_elf_emit_arch_note): Removed.
* config/tc-i386.h (md_end): Likewise.
(i386_elf_emit_arch_note): Likewise.
Support ix86-*-elf* bfd/ * config.bfd: Support i[3-7]86-*-elf*. gas/ * configure.tgt: Support i386-*-elf*.
2015-05-01 14:02:30 +02:00
2015-05-01 H.J. Lu <hongjiu.lu@intel.com>
* configure.tgt: Support i386-*-elf*.
Make RL78 disassembler and simulator respect ISA for mul/div [gas] * config/rl78-defs.h (rl78_isa_g10): New. (rl78_isa_g13): New. (rl78_isa_g14): New. * config/rl78-parse.y (ISA_G10): New. (ISA_G13): New. (ISA_G14): New. (MULHU, MULH, MULU, DIVHU, DIVWU, MACHU, MACH): Use them. * config/tc-rl78.c (rl78_isa_g10): New. (rl78_isa_g13): New. (rl78_isa_g14): New. [gdb] * rl78-tdep.c (rl78_analyze_prologue): Pass RL78_ISA_DEFAULT to rl78_decode_opcode [include] * dis-asm.h (print_insn_rl78_g10): New. (print_insn_rl78_g13): New. (print_insn_rl78_g14): New. (rl78_get_disassembler): New. * opcode/rl78.h (RL78_Dis_Isa): New. (rl78_decode_opcode): Add ISA parameter. [opcodes] * disassemble.c (disassembler): Choose suitable disassembler based on E_ABI. * rl78-decode.opc (rl78_decode_opcode): Take ISA parameter. Use it to decode mul/div insns. * rl78-decode.c: Regenerate. * rl78-dis.c (print_insn_rl78): Rename to... (print_insn_rl78_common): ...this, take ISA parameter. (print_insn_rl78): New. (print_insn_rl78_g10): New. (print_insn_rl78_g13): New. (print_insn_rl78_g14): New. (rl78_get_disassembler): New. [sim] * rl78/cpu.c (g14_multiply): New. * rl78/cpu.h (g14_multiply): New. * rl78/load.c (rl78_load): Decode ISA completely. * rl78/main.c (main): Expand -M to include other ISAs. * rl78/rl78.c (decode_opcode): Decode based on ISA. * rl78/trace.c (rl78_disasm_fn): New. (sim_disasm_init): Reset it. (sim_disasm_one): Get correct disassembler for ISA.
2015-04-30 21:25:49 +02:00
2015-04-30 DJ Delorie <dj@redhat.com>
* config/rl78-defs.h (rl78_isa_g10): New.
(rl78_isa_g13): New.
(rl78_isa_g14): New.
* config/rl78-parse.y (ISA_G10): New.
(ISA_G13): New.
(ISA_G14): New.
(MULHU, MULH, MULU, DIVHU, DIVWU, MACHU, MACH): Use them.
* config/tc-rl78.c (rl78_isa_g10): New.
(rl78_isa_g13): New.
(rl78_isa_g14): New.
Use "else if" on cpu_arch_isa * config/tc-i386.c (i386_target_format): Use "else if" on cpu_arch_isa.
2015-04-30 17:36:17 +02:00
2015-04-30 H.J. Lu <hongjiu.lu@intel.com>
* config/tc-i386.c (i386_target_format): Use "else if" on
cpu_arch_isa.
Adds documentation of GAS's .zero directive. PR gas/18353 * doc/as.texinfo (Zero): Add documentation of the .zero pseudo-op.
2015-04-30 11:13:53 +02:00
2015-04-30 Nick Clifton <nickc@redhat.com>
GAS ARM: Warn if the user creates a symbol with the same name as an instruction. PR gas/18347 gas * config/tc-arm.c (md_undefined_symbol): Issue a warning message (if enabled) when the user creates a symbol with the same name as an ARM instruction. (flag_warn_syms): New static variable. (arm_opts): Add mwarn-syms and mno-warn-syms. * doc/c-arm.texi (ARM Options): Document the -m[no-]warn-syms options. tests * gas/arm/pr18347.s: New file: Test case. * gas/arm/pr18347.l: New file: Expected assembler output. * gas/arm/pr18347.d: New file: Test driver.
2015-04-30 12:17:55 +02:00
PR gas/18347
* config/tc-arm.c (md_undefined_symbol): Issue a warning message
(if enabled) when the user creates a symbol with the same name as
an ARM instruction.
(flag_warn_syms): New static variable.
(arm_opts): Add mwarn-syms and mno-warn-syms.
* doc/c-arm.texi (ARM Options): Document the -m[no-]warn-syms
options.
Adds documentation of GAS's .zero directive. PR gas/18353 * doc/as.texinfo (Zero): Add documentation of the .zero pseudo-op.
2015-04-30 11:13:53 +02:00
PR gas/18353
* doc/as.texinfo (Zero): Add documentation of the .zero pseudo-op.
Fix an internal error in GAS when assembling a bogus piece of source code. gas PR 18256 * config/tc-arm.c (encode_arm_cp_address): Issue an error message if the operand is neither a register nor a vector. tests * gas/arm/pr18256.s: New file: Test case. * gas/arm/pr18256.l: New file: Expected assembler output. * gas/arm/pr18256.d: New file: Test driver.
2015-04-29 18:09:05 +02:00
2015-04-29 Nick Clifton <nickc@redhat.com>
PR 18256
* config/tc-arm.c (encode_arm_cp_address): Issue an error message
if the operand is neither a register nor a vector.
Updates the description of GAS's .set directive, to note that for some targets a symbolic value can only be set once. * doc/as.texinfo (Set): Note that a symbol cannot be set multiple times if the expression is not constant and the target uses linker relaxation.
2015-04-29 12:10:45 +02:00
2015-04-29 Nick Clifton <nickc@redhat.com>
* doc/as.texinfo (Set): Note that a symbol cannot be set multiple
times if the expression is not constant and the target uses linker
relaxation.
[ARM]Positively emit symbols for alignment 2015-04-28 Renlin Li <renlin.li@arm.com> gas/ * config/tc-arm.c (arm_init_frag): Always emit mapping symbols. gas/testsuite/ * gas/arm/thumb2_vpool_be.d: Adjust the desired output. * gas/arm/vldconst_be.d: Ditto.
2015-04-28 18:10:26 +02:00
2015-04-28 Renlin Li <renlin.li@arm.com>
* config/tc-arm.c (arm_init_frag): Always emit mapping symbols.
Fix compile time warnings about a local variable being used before it is set. PR 18313 * cond.c (s_if): Stop compile time warning about stopc being used before it is set. (s_ifc): Likewise.
2015-04-28 12:22:57 +02:00
2015-04-28 Nick Clifton <nickc@redhat.com>
PR 18313
* cond.c (s_if): Stop compile time warning about stopc being used
before it is set.
(s_ifc): Likewise.
[AArch64] Don't try to align insn in non-executale section 2015-04-27 Renlin Li <renlin.li@arm.com> gas/ * config/tc-aarch64.c (s_aarch64_inst): Don't align code for non-text section. (md_assemble): Likewise, move the align code outside the loop.
2015-04-27 12:36:12 +02:00
2015-04-27 Renlin Li <renlin.li@arm.com>
* config/tc-aarch64.c (s_aarch64_inst): Don't align code for non-text
section.
(md_assemble): Likewise, move the align code outside the loop.
gas thunderx support gas/ * config/tc-aarch64.c (aarch64_cpus): Add CRC and CRYPTO features for thunderx.
2015-04-24 22:38:25 +02:00
2015-04-24 Jim Wilson <jim.wilson@linaro.org>
* config/tc-aarch64.c (aarch64_cpus): Add CRC and CRYPTO features
for thunderx.
2015-04-24 Richard Earnshaw <rearnsha@arm.com>
[ARM]: Don't tail-pad over-aligned functions to the alignment boundary. 2015-04/24 Richard Earnshaw <rearnsha@arm.com> gas/ * config/tc-arm.h (arm_min): New function. (SUB_SEGMENT_ALIGN): Define. gas/testsuite/ * gas/arm/align64.d: Delete trailing padding NOPs. ld/testsuite/ * ld-arm/armthumb-lib.d: Regenerate expected output. * ld-arm/armthumb-lib.d: Likewise. * ld-arm/armthumb-lib.sym: Likewise. * ld-arm/cortex-a8-fix-b-rel-arm.d: Likewise. * ld-arm/cortex-a8-fix-b-rel-thumb.d: Likewise. * ld-arm/cortex-a8-fix-b.d: Likewise. * ld-arm/cortex-a8-fix-bcc-rel-thumb.d: Likewise. * ld-arm/cortex-a8-fix-bcc.d: Likewise. * ld-arm/cortex-a8-fix-bl-rel-arm.d: Likewise. * ld-arm/cortex-a8-fix-bl-rel-plt.d: Likewise. * ld-arm/cortex-a8-fix-bl-rel-thumb.d: Likewise. * ld-arm/cortex-a8-fix-bl.d: Likewise. * ld-arm/cortex-a8-fix-blx-bcond.d: Likewise. * ld-arm/cortex-a8-fix-blx-rel-arm.d: Likewise. * ld-arm/cortex-a8-fix-blx-rel-thumb.d: Likewise. * ld-arm/cortex-a8-fix-blx.d: Likewise. * ld-arm/cortex-a8-fix-hdr.d: Likewise. * ld-arm/farcall-mixed-app-v5.d: Likewise. * ld-arm/farcall-mixed-app.d: Likewise. * ld-arm/farcall-mixed-lib-v4t.d: Likewise. * ld-arm/farcall-mixed-lib.d: Likewise. * ld-arm/mixed-app-v5.d: Likewise. * ld-arm/mixed-app.d: Likewise. * ld-arm/mixed-lib.d: Likewise.
2015-04-24 16:51:49 +02:00
* config/tc-arm.h (arm_min): New function.
(SUB_SEGMENT_ALIGN): Define.
Improve warning messages for la/dla gas/ * config/tc-mips.c (macro): State the recommended way of creating 32-bit or 64-bit addresses. gas/testsuite/ * gas/mips/dla-warn.l: New file. * gas/mips/dla-warn.s: New file. * gas/mips/la-warn.l: New file. * gas/mips/la-warn.s: New file. * gas/mips/mips.exp: Run new tests.
2015-04-23 21:09:13 +02:00
2015-04-23 Matthew Fortune <matthew.fortune@imgtec.com>
* config/tc-mips.c (macro): State the recommended way of creating
32-bit or 64-bit addresses.
x86: don't require operand size specification for AVX512 broadcasts Certain conversion operations as well as vfpclassp{d,s} are ambiguous when the input operand is in memory. That ambiguity, however, doesn't apply when using broadcasts (the destination operand size can be induced from the broadcast specifier). gas/ 2015-04-23 Jan Beulich <jbeulich@suse.com> * config/tc-i386.c (match_mem_size): Also allow no size specification when broadcasting. gas/testsuite/ 2015-04-23 Jan Beulich <jbeulich@suse.com> * gas/i386/avx512dq.s: Drop 'z' suffix from vfpclassp{d,s} in some AT&T and all Intel cases. * gas/i386/x86-64-avx512dq.s: Likewise. * gas/i386/avx512dq_vl.s: Drop 'x' and 'y' suffixes from vcvt{,u}qq2ps and vfpclassp{d,s} in some AT&T and all Intel cases. * gas/i386/x86-64-avx512dq_vl.s: Likewise. * gas/i386/avx512f_vl.s: Drop 'x' and 'y' suffixes from vcvt{,t}pd2{,u}dq and vcvtpd2ps in some AT&T and all Intel cases. * gas/i386/x86-64-avx512f_vl.s: Likewise.
2015-04-23 16:41:21 +02:00
2015-04-23 Jan Beulich <jbeulich@suse.com>
* config/tc-i386.c (match_mem_size): Also allow no size
specification when broadcasting.
Silence texinfo 5.1 warnings This patch silences texinfo 5.1 warnings by using @subsection and sorting entries in Machine Dependencies menu. * doc/as.texinfo (Bundle directives): Shorten menu entry and use @subsection. (CFI directives): Use @subsection. (SH-Dependent, SH64-Dependent): Moved after SCORE-Dependent. * doc/c-i386.texi (i386-Mnemonics): Use @subsection.
2015-04-20 17:05:13 +02:00
2015-04-20 H.J. Lu <hongjiu.lu@intel.com>
* doc/as.texinfo (Bundle directives): Shorten menu entry and
use @subsection.
(CFI directives): Use @subsection.
(SH-Dependent, SH64-Dependent): Moved after SCORE-Dependent.
* doc/c-i386.texi (i386-Mnemonics): Use @subsection.
Fix avr compiler warning declaration of "link" shadows a global declaration * config/tc-avr.c (create_record_for_frag): Rename link to prop_rec_link.
2015-04-17 13:25:54 +02:00
2015-04-17 Senthil Kumar Selvaraj <senthil_kumar.selvaraj@atmel.com>
* config/tc-avr.c (create_record_for_frag): Rename link to
prop_rec_link.
Mention --compress-debug-sections=[none|zlib|zlib-gnu|zlib-gabi] binutils/ * NEWS: Mention --compress-debug-sections=[none|zlib|zlib-gnu|zlib-gabi]. gas/ * NEWS: Mention --compress-debug-sections=[none|zlib|zlib-gnu|zlib-gabi]. ld/ * NEWS: Mention --compress-debug-sections=[none|zlib|zlib-gnu|zlib-gabi].
2015-04-15 14:25:58 +02:00
2015-04-15 H.J. Lu <hongjiu.lu@intel.com>
* NEWS: Mention
--compress-debug-sections=[none|zlib|zlib-gnu|zlib-gabi].
Add --compress-debug-sections=[none|zlib|zlib-gnu|zlib-gabi] This patch adds --compress-debug-sections=[none|zlib|zlib-gnu|zlib-gabi] to ld for ELF targets to support generating compressed DWARF debug sections. We always generate .zdebug_* section since section names have been finalized and they can't be changed easily when compression is being performed. bfd/ * bfd-in.h (compressed_debug_section_type): New. * compress.c (bfd_compress_section_contents): Add an argument for linker write compression and always generate .zdebug_* section when linking. (bfd_init_section_compress_status): Pass FALSE to bfd_compress_section_contents. (bfd_compress_section): New function. * elf.c (elf_fake_sections): For linking, set SEC_ELF_COMPRESS on DWARF debug sections if COMPRESS_DEBUG is set and rename section if COMPRESS_DEBUG_GABI_ZLIB isn't set. (assign_file_positions_for_non_load_sections): Set sh_offset to -1 if SEC_ELF_COMPRESS is set. (assign_file_positions_except_relocs): Likwise. (_bfd_elf_assign_file_positions_for_relocs): Renamed to ... (_bfd_elf_assign_file_positions_for_non_load): This. Change return time to bfd_boolean. Compress the section if SEC_ELF_COMPRESS is set. (_bfd_elf_write_object_contents): Updated. (_bfd_elf_set_section_contents): Write section contents to the buffer if SEC_ELF_COMPRESS is set. * merge.c: Include "elf-bfd.h". (sec_merge_emit): Add arguments for contents and offset. Write to contents with offset if contents isn't NULL. (_bfd_write_merged_section): Write section contents to the buffer if SEC_ELF_COMPRESS is set. Pass contents and output_offset to sec_merge_emit. * elflink.c (bfd_elf_final_link): Allocate the buffer for output section contents if SEC_ELF_COMPRESS is set. * section.c (SEC_ELF_COMPRESS): New. * bfd-in2.h: Regenerated. gas/ * as.h (compressed_debug_section_type): Removed. include/ * bfdlink.h (bfd_link_info): Add compress_debug. ld/ * ld.texinfo: Document --compress-debug-sections=. * ldmain.c (main): Set BFD_COMPRESS on output_bfd if COMPRESS_DEBUG is set. Set BFD_COMPRESS_GABI on output_bfd for COMPRESS_DEBUG_GABI_ZLIB. * lexsup.c (elf_static_list_options): Add --compress-debug-sections=. * emultempl/elf32.em (OPTION_COMPRESS_DEBUG): New. (xtra_long): Add "compress-debug-sections". (gld${EMULATION_NAME}_handle_option): Handle OPTION_COMPRESS_DEBUG. ld/testsuite/ * ld-elf/compress.exp (build_tests): Add tests for --compress-debug-sections=. (run_tests): Likewise. Add additonal tests for --compress-debug-sections=. * ld-elf/gabiend.rt: New file. * ld-elf/gabinormal.rt: Likewise. * ld-elf/gnubegin.rS: Likewise. * ld-elf/gnunormal.rS: Likewise. * ld-elf/zlibbegin.rS: Likewise. * ld-elf/zlibnormal.rS: Likewise.
2015-04-15 07:01:25 +02:00
2015-04-14 H.J. Lu <hongjiu.lu@intel.com>
* as.h (compressed_debug_section_type): Removed.
Adds support to the RL78 port for linker relaxation affecting .debug sections. gas * config/tc-rl78.h (TC_LINKRELAX_FIXUP): Define. (TC_FORCE_RELOCATION_SUB_SAME): Define. (DWARF2_USE_FIXED_ADVANCE_PC): Define. * gas/lns/lns.exp: Add RL78 to list of targets using DW_LNS_fixed_advance_pc. bfd * elf32-rl78.c (RL78_OP_REL): New macro. (rl78_elf_howto_table): Use it for complex relocs. (get_symbol_value): Handle the cases when the info or status arguments are NULL. (get_romstart): Cache the status returned by get_symbol_value. (get_ramstart): Likewise. (RL78_STACK_PUSH): Generate an error message if the stack overflows. (RL78_STACK_POP): Likewise for underflows. (rl78_compute_complex_reloc): New function. Contains the basic processing code for all RL78 complex relocs. (rl78_special_reloc): New function. Provides special reloc handling for complex relocs. (rl78_elf_relocate_section): Use rl78_compute_complex_reloc. (rl78_offset_for_reloc): Likewise. binutils* readelf.c (target_specific_reloc_handling): Add code to handle RL78 complex relocs.
2015-04-14 17:23:33 +02:00
2015-04-14 Nick Clifton <nickc@redhat.com>
* config/tc-rl78.h (TC_LINKRELAX_FIXUP): Define.
(TC_FORCE_RELOCATION_SUB_SAME): Define.
(DWARF2_USE_FIXED_ADVANCE_PC): Define.
Add documentation about the interation of the ARM assembler's -EB option and the linker's --be8 option. PR binutils/18198 * ld.texinfo (--be8): Add a note about the interaction of this option with the assembler's -EB option. * doc/c-arm.texi (ARM Options): Add a note about the interaction of the -EB option with the linker's --be8 option.
2015-04-10 09:26:07 +02:00
2015-04-10 Nick Clifton <nickc@redhat.com>
PR binutils/18198
* doc/c-arm.texi (ARM Options): Add a note about the interaction of
the -EB option with the linker's --be8 option.
doc/c-rx.texi: Fix markup typos in last change.
2015-04-09 21:09:02 +02:00
2015-04-09 Hans-Peter Nilsson <hp@axis.com>
* doc/c-rx.texi: Fix markup typos in last change.
Add support to the RX toolchain to restrict the use of string instructions. bfd * elf32-rx.c (describe_flags): Report the settings of the string insn using bits. (rx_elf_merge_private_bfd_data): Handle merging of the string insn using bits. bin * readelf.c (get_machine_flags): Report the setting of the string insn using bits. gas * config/tc-rx.c (enum options): Add OPTION_DISALLOW_STRING_INSNS. (md_longopts): Add -mno-allow-string-insns. (md_parse_option): Handle -mno-allow-string-insns. (md_show_usage): Mention -mno-allow-string-insns. (rx_note_string_insn_use): New function. Produces an error message if a string insn is used when it is not allowed. * config/rx-parse.y (SCMPU): Call rx_note_string_insn_use. (SMOVU, SMOVB, SMOVF, SUNTIL, SWHILE, RMPA): Likewise. * config/rx-defs.h (rx_note_string_insn_use): Prototype. * doc/c-rx.texi: Document -mno-allow-string-insns. elf * rx.h (E_FLAG_RX_SINSNS_SET): New bit in e_flags field. (E_FLAG_RX_SINSNS_YES): Likewise. (E_FLAG_RX_SINSNS_MASK): New define.
2015-04-09 13:48:37 +02:00
2015-04-09 Nick Clifton <nickc@redhat.com>
* config/tc-rx.c (enum options): Add OPTION_DISALLOW_STRING_INSNS.
(md_longopts): Add -mno-allow-string-insns.
(md_parse_option): Handle -mno-allow-string-insns.
(md_show_usage): Mention -mno-allow-string-insns.
(rx_note_string_insn_use): New function. Produces an error
message if a string insn is used when it is not allowed.
* config/rx-parse.y (SCMPU): Call rx_note_string_insn_use.
(SMOVU, SMOVB, SMOVF, SUNTIL, SWHILE, RMPA): Likewise.
* config/rx-defs.h (rx_note_string_insn_use): Prototype.
* doc/c-rx.texi: Document -mno-allow-string-insns.
Add SHF_COMPRESSED support to gas and objcopy This patch adds --compress-debug-sections={none|zlib|zlib-gnu|zlib-gabi} options to gas and objcopy for ELF files. They control how DWARF debug sections are compressed. --compress-debug-sections=none is equivalent to --nocompress-debug-sections. --compress-debug-sections=zlib and --compress-debug-sections=zlib-gnu are equivalent to --compress-debug-sections. --compress-debug-sections=zlib-gabi compresses DWARF debug sections with SHF_COMPRESSED from the ELF ABI. No linker changes are required to support SHF_COMPRESSED. bfd/ * archive.c (_bfd_get_elt_at_filepos): Also copy BFD_COMPRESS_GABI bit. * bfd.c (bfd::flags): Increase size to 18 bits. (BFD_COMPRESS_GABI): New. (BFD_FLAGS_SAVED): Add BFD_COMPRESS_GABI. (BFD_FLAGS_FOR_BFD_USE_MASK): Likewise. (bfd_update_compression_header): New fuction. (bfd_check_compression_header): Likewise. (bfd_get_compression_header_size): Likewise. (bfd_is_section_compressed_with_header): Likewise. * compress.c (MAX_COMPRESSION_HEADER_SIZE): New. (bfd_compress_section_contents): Return the uncompressed size if the full section contents is compressed successfully. Support converting from/to .zdebug* sections. (bfd_get_full_section_contents): Call bfd_get_compression_header_size to get compression header size. (bfd_is_section_compressed): Renamed to ... (bfd_is_section_compressed_with_header): This. Add a pointer argument to return compression header size. (bfd_is_section_compressed): Use it. (bfd_init_section_decompress_status): Call bfd_get_compression_header_size to get compression header size. Return FALSE if uncompressed section size is 0. * elf.c (_bfd_elf_make_section_from_shdr): Support converting from/to .zdebug* sections. * bfd-in2.h: Regenerated. binutils/ * objcopy.c (do_debug_sections): Add compress_zlib, compress_gnu_zlib and compress_gabi_zlib. (copy_options): Use optional_argument on compress-debug-sections. (copy_usage): Update --compress-debug-sections. (copy_file): Handle compress_zlib, compress_gnu_zlib and compress_gabi_zlib. (copy_main): Handle --compress-debug-sections={none|zlib|zlib-gnu|zlib-gabi}. * doc/binutils.texi: Document --compress-debug-sections={none|zlib|zlib-gnu|zlib-gabi}. binutils/testsuite/ * compress.exp: Add tests for --compress-debug-sections={none|zlib|zlib-gnu|zlib-gabi}. * binutils-all/dw2-3.rS: New file. * binutils-all/dw2-3.rt: Likewise. * binutils-all/libdw2-compressedgabi.out: Likewise. gas/ * as.c (show_usage): Update --compress-debug-sections. (std_longopts): Use optional_argument on compress-debug-sections. (parse_args): Handle --compress-debug-sections={none|zlib|zlib-gnu|zlib-gabi}. * as.h (compressed_debug_section_type): New. (flag_compress_debug): Change type to compressed_debug_section_type. --compress-debug-sections={none|zlib|zlib-gnu|zlib-gabi}. * write.c (compress_debug): Set BFD_COMPRESS_GABI for --compress-debug-sections=zlib-gabi. Call bfd_get_compression_header_size to get compression header size. Don't rename section name for --compress-debug-sections=zlib-gabi. * config/tc-i386.c (compressed_debug_section_type): Set to COMPRESS_DEBUG_ZLIB. * doc/as.texinfo: Document --compress-debug-sections={none|zlib|zlib-gnu|zlib-gabi}. gas/testsuite/ * gas/i386/dw2-compressed-1.d: New file. * gas/i386/dw2-compressed-2.d: Likewise. * gas/i386/dw2-compressed-3.d: Likewise. * gas/i386/x86-64-dw2-compressed-2.d: Likewise. * gas/i386/i386.exp: Run dw2-compressed-2, dw2-compressed-1, dw2-compressed-3 and x86-64-dw2-compressed-2. ld/testsuite/ * ld-elf/compress.exp: Add a test for --compress-debug-sections=zlib-gabi. (build_tests): Add 2 tests for --compress-debug-sections=zlib-gabi. (run_tests): Likewise. Verify linker output with zlib-gabi compressed debug input. * ld-elf/compressed1a.d: New file. * ld-elf/compressed1b.d: Likewise. * ld-elf/compressed1c.d: Likewise.
2015-04-08 16:53:54 +02:00
2015-04-08 H.J. Lu <hongjiu.lu@intel.com>
* as.c (show_usage): Update --compress-debug-sections.
(std_longopts): Use optional_argument on compress-debug-sections.
(parse_args): Handle
--compress-debug-sections={none|zlib|zlib-gnu|zlib-gabi}.
* as.h (compressed_debug_section_type): New.
(flag_compress_debug): Change type to compressed_debug_section_type.
--compress-debug-sections={none|zlib|zlib-gnu|zlib-gabi}.
* write.c (compress_debug): Set BFD_COMPRESS_GABI for
--compress-debug-sections=zlib-gabi. Call
bfd_get_compression_header_size to get compression header size.
Don't rename section name for --compress-debug-sections=zlib-gabi.
* config/tc-i386.c (compressed_debug_section_type): Set to
COMPRESS_DEBUG_ZLIB.
* doc/as.texinfo: Document
--compress-debug-sections={none|zlib|zlib-gnu|zlib-gabi}.
[AArch64] use subseg_text_p to check .text 2015-04-07 Renlin Li <renlin.li@arm.com> gas/ * config/tc-aarch64.c (mapping_state): Use subseg_text_p. (s_aarch64_inst): Likewise. (md_assemble): Likewise.
2015-04-07 19:10:33 +02:00
2015-04-07 Renlin Li <renlin.li@arm.com>
* config/tc-aarch64.c (mapping_state): Use subseg_text_p.
(s_aarch64_inst): Likewise.
(md_assemble): Likewise.
Use bfd_putb64/bfd_getb64 bfd/ * compress.c (get_uncompressed_size): Removed. (bfd_compress_section_contents): Use bfd_putb64 to write uncompressed section size. (bfd_init_section_decompress_status): Replace get_uncompressed_size with bfd_getb64. gas/ * write.c (compress_debug): Use bfd_putb64 to write uncompressed section size.
2015-04-06 18:01:43 +02:00
2015-04-06 H.J. Lu <hongjiu.lu@intel.com>
* write.c (compress_debug): Use bfd_putb64 to write uncompressed
section size.
Xfail the compressed debug sections There is no need to generate compressed debug section if compressed section size is the same as before compression. We should xfail the compressed debug section test if there are no compressed sections binutils/testsuite/ * binutils-all/compress.exp (compression_used): New. Xfail test if compression didn't make the section smaller. gas/ 2015-04-05 H.J. Lu <hongjiu.lu@intel.com> * write.c (compress_debug): Don't write the zlib header if compressed section size is the same as before compression.
2015-04-05 17:11:11 +02:00
2015-04-05 H.J. Lu <hongjiu.lu@intel.com>
* write.c (compress_debug): Don't write the zlib header if
compressed section size is the same as before compression.
Fixes a bug in the microblaze assembler where it would not complain about constants larger than 32-bits. PR gas/18189 * config/tc-microblaze.c (parse_imm): Use offsetT as the type for min and max parameters.
2015-04-02 17:10:06 +02:00
2015-04-02 Nick Clifton <nickc@redhat.com>
PR gas/18189
* config/tc-microblaze.c (parse_imm): Use offsetT as the type for
Second fix for microblaze gas port's ability to parse constants. PR gas/18189 * config/tc-microblaze.c (parse_imm): Use offsetT as the type for min and max parameters. Sign extend values before testing.
2015-04-02 18:13:12 +02:00
min and max parameters. Sign extend values before testing.
Fixes a bug in the microblaze assembler where it would not complain about constants larger than 32-bits. PR gas/18189 * config/tc-microblaze.c (parse_imm): Use offsetT as the type for min and max parameters.
2015-04-02 17:10:06 +02:00
[AArch64] Emit DATA_MAP in order within text section 2015-03-27 Renlin Li <renlin.li@arm.com> gas/ * config/tc-aarch64.c (mapping_state): Emit MAP_DATA within text section in order. (mapping_state_2): Don't emit MAP_DATA here. (s_aarch64_inst): Align frag during state transition. (md_assemble): Likewise.
2015-04-02 15:59:45 +02:00
2015-04-02 Renlin Li <renlin.li@arm.com>
* config/tc-aarch64.c (mapping_state): Emit MAP_DATA within text section in order.
(mapping_state_2): Don't emit MAP_DATA here.
(s_aarch64_inst): Align frag during state transition.
(md_assemble): Likewise.
Remove unused functions in tc-aarch64.c. * config/tc-aarch64.c (set_error_kind): Delete. (set_error_message): Delete.
2015-04-02 15:44:59 +02:00
2015-04-02 Ed Maste <emaste@freebsd.org>
* config/tc-aarch64.c (set_error_kind): Delete.
(set_error_message): Delete.
Regenerate configure in bfd/binutils/gas/gdb/gold bfd/ * configure: Regenerated. binutils/ * configure: Regenerated. gas/ * configure: Regenerated. gdb/ * Makefile.in (top_srcdir): New. * configure: Regenerated. gold/ * configure: Regenerated.
2015-04-02 14:41:50 +02:00
2015-04-02 H.J. Lu <hongjiu.lu@intel.com>
* configure: Regenerated.
[AArch64] Add support for the Samsung Exynos M1 processor 2015-03-26 Evandro Menezes <e.menezes@samsung.com> gas/ * config/tc-aarch64.c: Add support for Samsung Exynos M1. * doc/c-aarch64.texi (-mcpu=): Add "exynos-m1".
2015-03-26 21:18:08 +01:00
2015-04-01 Evandro Menezes <e.menezes@samsung.com>
* config/tc-aarch64.c: Add support for Samsung Exynos M1.
* doc/c-aarch64.texi (-mcpu=): Add "exynos-m1".
[ARM] Add support for the Samsung Exynos M1 processor 2015-03-26 Evandro Menezes <e.menezes@samsung.com> gas/ * config/tc-arm.c: Add support for Samsung Exynos M1. * doc/c-arm.texi (-mcpu=): Add "exynos-m1".
2015-03-26 21:51:14 +01:00
2015-04-01 Evandro Menezes <e.menezes@samsung.com>
* config/tc-arm.c: Add support for Samsung Exynos M1.
* doc/c-arm.texi (-mcpu=): Add "exynos-m1".
Regenerate configure in bfd/binutils/gas/gdb bfd/ 2015-04-01 H.J. Lu <hongjiu.lu@intel.com> * configure: Regenerated. binutils/ 2015-04-01 H.J. Lu <hongjiu.lu@intel.com> * configure: Regenerated. gas/ 2015-04-01 H.J. Lu <hongjiu.lu@intel.com> * configure: Regenerated. gdb/ 2015-04-01 H.J. Lu <hongjiu.lu@intel.com> * configure: Regenerated.
2015-04-01 13:55:48 +02:00
2015-04-01 H.J. Lu <hongjiu.lu@intel.com>
* configure: Regenerated.
Add support for Nuxi CloudABI on x86-64 bfd/ * config.bfd (targ_defvec): Set to x86_64_elf64_cloudabi_vec for x86_64-*-cloudabi*. * configure.ac: Handle x86_64_elf64_cloudabi_vec. * configure: Regenerated. * elf64-x86-64.c (TARGET_LITTLE_SYM): Support x86_64-*-cloudabi*. (TARGET_LITTLE_NAME): Likewise. (ELF_OSABI): Likewise. (elf64_bed): Likewise. * targets.c (x86_64_elf64_cloudabi_vec): New. (_bfd_target_vector): Add x86_64_elf64_cloudabi_vec. gas/ * configure.tgt (fmt): Set to elf for *-*-cloudabi*. ld/ * Makefile.am (ALL_64_EMULATION_SOURCES): Add eelf_x86_64_cloudabi.c. (eelf_x86_64_cloudabi.c): New. * configure.tgt (targ_emul): Set to elf_x86_64_cloudabi for x86_64-*-cloudabi*. * Makefile.in: Regenerated. * emulparams/elf_x86_64_cloudabi.sh: New file.
2015-03-31 11:33:45 +02:00
2015-03-31 Ed Schouten <ed@nuxi.nl>
* configure.tgt (fmt): Set to elf for *-*-cloudabi*.
Revert the AM_ZLIB change in gas * configure.ac: Revert the AM_ZLIB change. * Makefile.in: Regenerated. * aclocal.m4: Likewise. * configure: Likewise.
2015-03-31 14:55:18 +02:00
2015-03-31 H.J. Lu <hongjiu.lu@intel.com>
* configure.ac: Revert the AM_ZLIB change.
* Makefile.in: Regenerated.
* aclocal.m4: Likewise.
* configure: Likewise.
Add --with-system-zlib in gas This patch adds --with-system-zlib and remove --with-zlib in gas. gas/ * Makefile.am (ZLIBINC): New. (AM_CFLAGS): Add $(ZLIBINC). * as.c: (show_usage): Don't check HAVE_ZLIB_H. (parse_args): Likewise. * compress-debug.c: Don't check HAVE_ZLIB_H to include <zlib.h>. (compress_init): Don't check HAVE_ZLIB_H. (compress_data): Likewise. (compress_finish): Likewise. * configure.ac (AM_ZLIB): Removed. (zlibinc): New. AC_SUBST. Add --with-system-zlib. * Makefile.in: Regenerated. * config.in: Likewise. * configure: Likewise. * doc/Makefile.in: Likewise. gas/testsuite/ * gas/i386/dw2-compress-1.d: Expect .zdebug_info.
2015-03-31 12:55:56 +02:00
2015-03-31 H.J. Lu <hongjiu.lu@intel.com>
* Makefile.am (ZLIBINC): New.
(AM_CFLAGS): Add $(ZLIBINC).
* as.c: (show_usage): Don't check HAVE_ZLIB_H.
(parse_args): Likewise.
* compress-debug.c: Don't check HAVE_ZLIB_H to include <zlib.h>.
(compress_init): Don't check HAVE_ZLIB_H.
(compress_data): Likewise.
(compress_finish): Likewise.
* configure.ac (AM_ZLIB): Removed.
(zlibinc): New. AC_SUBST.
Add --with-system-zlib.
* Makefile.in: Regenerated.
* config.in: Likewise.
* configure: Likewise.
* doc/Makefile.in: Likewise.
Remove the unused cpu_flags_set * config/tc-i386.c (cpu_flags_set): Removed.
2015-03-27 17:29:05 +01:00
2015-03-27 H.J. Lu <hongjiu.lu@intel.com>
* config/tc-i386.c (cpu_flags_set): Removed.
[AARCH64]Fix "align directive causes MAP_DATA symbol to be lost" gas/ChangeLog: 2015-03-25 Renlin Li <renlin.li@arm.com> * config/tc-aarch64.c (mapping_state): Remove first MAP_DATA emitting code. (mapping_state_2): Emit first MAP_DATA symbol here.
2015-03-25 13:33:07 +01:00
2015-03-25 Renlin Li <renlin.li@arm.com>
* config/tc-aarch64.c (mapping_state): Remove first MAP_DATA emitting
code.
(mapping_state_2): Emit first MAP_DATA symbol here.
Don't write the zlib header if not used No need to write the zlib header if compression didn't make the section smaller. PR gas/18087 * write.c (compress_debug): Don't write the zlib header if compression didn't make the section smaller.
2015-03-25 03:06:22 +01:00
2015-03-24 H.J. Lu <hongjiu.lu@intel.com>
PR gas/18087
* write.c (compress_debug): Don't write the zlib header if
compression didn't make the section smaller.
Extend arm_feature_set struct to provide more bits gas/ChangeLog: 2015-03-24 Terry Guo <terry.guo@arm.com> * config/tc-arm.c (no_cpu_selected): Use new macro to compare features. (parse_psr): Likewise. (do_t_mrs): Likewise. (do_t_msr): Likewise. (static const arm_feature_set arm_ext_*): Defined with new macros. (static const arm_feature_set arm_cext_*): Likewise. (static const arm_feature_set fpu_fpa_ext_*): Likewise. (static const arm_feature_set fpu_vfp_ext_*): Likewise. (deprecated_coproc_regs): Likewise. (UL_BARRIER): Likewise. (barrier_opt_names): Likewise. (arm_cpus): Likewise. (arm_extensions): Likewise. include/opcode/ChangeLog: 2015-03-24 Terry Guo <terry.guo@arm.com> * arm.h (arm_feature_set): Extended to provide more available * bits. (ARM_ANY): Updated to follow above new definition. (ARM_CPU_HAS_FEATURE): Likewise. (ARM_CPU_IS_ANY): Likewise. (ARM_MERGE_FEATURE_SETS): Likewise. (ARM_CLEAR_FEATURE): Likewise. (ARM_FEATURE): Likewise. (ARM_FEATURE_COPY): New macro. (ARM_FEATURE_EQUAL): Likewise. (ARM_FEATURE_ZERO): Likewise. (ARM_FEATURE_CORE_EQUAL): Likewise. (ARM_FEATURE_LOW): Likewise. (ARM_FEATURE_CORE_LOW): Likewise. (ARM_FEATURE_CORE_COPROC): Likewise. opcodes/ChangeLog: 2015-03-24 Terry Guo <terry.guo@arm.com> * arm-dis.c (opcode32): Updated to use new arm feature struct. (opcode16): Likewise. (coprocessor_opcodes): Replace bit with feature struct. (neon_opcodes): Likewise. (arm_opcodes): Likewise. (thumb_opcodes): Likewise. (thumb32_opcodes): Likewise. (print_insn_coprocessor): Likewise. (print_insn_arm): Likewise. (select_arm_features): Follow new feature struct.
2015-03-24 07:08:08 +01:00
2015-03-24 Terry Guo <terry.guo@arm.com>
* config/tc-arm.c (no_cpu_selected): Use new macro to compare
features.
(parse_psr): Likewise.
(do_t_mrs): Likewise.
(do_t_msr): Likewise.
(static const arm_feature_set arm_ext_*): Defined with new macros.
(static const arm_feature_set arm_cext_*): Likewise.
(static const arm_feature_set fpu_fpa_ext_*): Likewise.
(static const arm_feature_set fpu_vfp_ext_*): Likewise.
(deprecated_coproc_regs): Likewise.
(UL_BARRIER): Likewise.
(barrier_opt_names): Likewise.
(arm_cpus): Likewise.
(arm_extensions): Likewise.
Limit multi-byte nop instructions to 10 bytes There is no performance advantage to use multi-byte nop instructions greater than 10 bytes. This patch limits multi-byte nop instructions to 10 bytes. Since there is only one way to encode multi-byte nop instructions now, it also removed redundant nop tests. gas/ * config/tc-i386.c (i386_align_code): Limit multi-byte nop instructions to 10 bytes. gas/testsuite/ * gas/i386/i386.exp: Don't run nops-1-bdver1, nops-1-bdver2, nops-1-bdver3, nops-1-bdver4, nops-1-znver1, nops-1-btver1 nops-1-btver2, x86-64-nops-1-nocona, x86-64-nops-1-bdver1, x86-64-nops-1-bdver2, x86-64-nops-1-bdver3, x86-64-nops-1-bdver4, x86-64-nops-1-znver1, x86-64-nops-1-btver1 nor x86-64-nops-1-btver2. * gas/i386/nops-1-core2.d: Updated. * gas/i386/nops-1-k8.d: Likewise. * gas/i386/nops-4a-i686.d: Likewise. * gas/i386/nops-5-i686.d: Likewise. * gas/i386/nops-5.d: Likewise. * gas/i386/nops-6.d: Likewise. * gas/i386/x86-64-nops-1-core2.d: Likewise. * gas/i386/x86-64-nops-1-g64.d: Likewise. * gas/i386/x86-64-nops-1-k8.d: Likewise. * gas/i386/x86-64-nops-1.d: Likewise. * gas/i386/x86-64-nops-2.d: Likewise. * gas/i386/x86-64-nops-3.d: Likewise. * gas/i386/x86-64-nops-4-core2.d: Likewise. * gas/i386/x86-64-nops-4-k8.d: Likewise. * gas/i386/x86-64-nops-4.d: Likewise. * gas/i386/x86-64-nops-5-k8.d: Likewise. * gas/i386/x86-64-nops-5.d: Likewise. * gas/i386/ilp32/x86-64-nops-1-core2.d: Likewise. * gas/i386/ilp32/x86-64-nops-1-k8.d: Likewise. * gas/i386/ilp32/x86-64-nops-1.d: Likewise. * gas/i386/ilp32/x86-64-nops-2.d: Likewise. * gas/i386/ilp32/x86-64-nops-3.d: Likewise. * gas/i386/ilp32/x86-64-nops-4-core2.d: Likewise. * gas/i386/ilp32/x86-64-nops-4-k8.d: Likewise. * gas/i386/ilp32/x86-64-nops-4.d: Likewise. * gas/i386/ilp32/x86-64-nops-5-k8.d: Likewise. * gas/i386/ilp32/x86-64-nops-5.d: Likewise. * gas/i386/nops-1-bdver1.d: Removed. * gas/i386/nops-1-bdver2.d: Likewise. * gas/i386/nops-1-bdver3.d: Likewise. * gas/i386/nops-1-bdver4.d: Likewise. * gas/i386/nops-1-btver1.d: Likewise. * gas/i386/nops-1-btver2.d: Likewise. * gas/i386/nops-1-znver1.d: Likewise. * gas/i386/x86-64-nops-1-bdver1.d: Likewise. * gas/i386/x86-64-nops-1-bdver2.d: Likewise. * gas/i386/x86-64-nops-1-bdver3.d: Likewise. * gas/i386/x86-64-nops-1-bdver4.d: Likewise. * gas/i386/x86-64-nops-1-btver1.d: Likewise. * gas/i386/x86-64-nops-1-btver2.d: Likewise. * gas/i386/x86-64-nops-1-nocona.d: Likewise. * gas/i386/x86-64-nops-1-znver1.d: Likewise. * gas/i386/ilp32/x86-64-nops-1-nocona.d: Likewise.
2015-03-20 12:39:04 +01:00
2015-03-20 H.J. Lu <hongjiu.lu@intel.com>
* config/tc-i386.c (i386_align_code): Limit multi-byte nop
instructions to 10 bytes.
Add support for G13 and G14 flag bits in RL78 ELF binaries. inc * rl78.h (E_FLAG_RL78_G10): Redefine. (E_FLAG_RL78_CPU_MASK, E_FLAG_RL78_ANY_CPU, E_FLAG_RL78_G13 E_FLAG_RL78_G14): New flags. bin * readelf.c (get_machine_flags): Decode RL78's G13 and G14 flags. gas * config/tc-rl78.c (enum options): Add G13 and G14. (md_longopts): Add -mg13 and -mg14. (md_parse_option): Handle -mg13 and -mg14. (md_show_usage): List -mg13 and -mg14. * doc/c-rl78.texi: Add description of -mg13 and -mg14 options. bfd * elf32-rl78.c (rl78_cpu_name): New function. Prints the name of the RL78 core based upon the flags. (rl78_elf_merge_private_bfd_data): Handle merging of G13 and G14 flags. (rl78_elf_print_private_bfd_data): Use rl78_cpu_name. (elf32_rl78_machine): Always return bfd_mach_rl78.
2015-03-19 16:37:43 +01:00
2015-03-19 Nick Clifton <nickc@redhat.com>
* config/tc-rl78.c (enum options): Add G13 and G14.
(md_longopts): Add -mg13 and -mg14.
(md_parse_option): Handle -mg13 and -mg14.
(md_show_usage): List -mg13 and -mg14.
* doc/c-rl78.texi: Add description of -mg13 and -mg14 options.
Fix debug section compression so that it is only performed if it would make the section smaller. PR binutils/18087 gas * doc/as.texinfo: Note that when gas compresses debug sections the compression is only performed if it makes the section smaller. * write.c (compress_debug): Do not compress a debug section if doing so would make it larger. tests * gas/i386/dw2-compress-1.d: Do not expect the .debug_abbrev or .debug_info sections to be compressed. binu * doc/binutils.texi: Note that when objcopy compresses debug sections the compression is only performed if it makes the section smaller. bfd * coffgen.c (make_a_section_from_file): Only prepend a z to a debug section's name if the section was actually compressed. * elf.c (_bfd_elf_make_section_from_shdr): Likewise. * compress.c (bfd_init_section_compress_status): Do not compress the section if doing so would make it bigger. In such cases leave the section alone and return COMPRESS_SECTION_NONE.
2015-03-18 16:47:13 +01:00
2015-03-18 Jon Turney <jon.turney@dronecode.org.uk>
Nick Clifton <nickc@redhat.com>
PR binutils/18087
* doc/as.texinfo: Note that when gas compresses debug sections the
compression is only performed if it makes the section smaller.
* write.c (compress_debug): Do not compress a debug section if
doing so would make it larger.
Add znver1 processor
2015-03-17 17:19:15 +01:00
2015-03-17 Ganesh Gopalasubramanian <Ganesh.Gopalasubramanian@amd.com>
* config/tc-i386.c (cpu_arch): Add PROCESSOR_ZNVER flags.
(i386_align_code): Add PROCESSOR_ZNVER cases.
* config/tc-i386.h (processor_type): Add PROCESSOR_ZNVER.
* doc/c-i386.texi: Add znver1 and clzero.
Removes a #if 1 ... #endif accidentally left in the source code. * dwarf2dbg.c (out_header): Remove spurious #if 1.
2015-03-16 12:17:52 +01:00
2015-03-16 Nick Clifton <nickc@redhat.com>
* dwarf2dbg.c (out_header): Remove spurious #if 1.
[AArch64] Don't warn on XZR/SP overlapping when it's in load/store 2015-03-13 Jiong Wang <jiong.wang@arm.com> gas/ * config/tc-aarch64.c (warn_unpredictable_ldst): Don't warn on reg number 31. gas/testsuite/ * gas/aarch64/diagnostic.s: New testcases. * gas/aarch64/diagnostic.l: New error match.
2015-03-13 13:02:23 +01:00
2015-03-13 Jiong Wang <jiong.wang@arm.com>
* config/tc-aarch64.c (warn_unpredictable_ldst): Don't warn on reg
number 31.
[AArch64] Don't tail-pads sections to the alignment 2015-03-13 Jiong Wang <jiong.wang@arm.com> gas/ * config/tc-aarch64.h (SUB_SEGMENT_ALIGN): Define to be zero. gas/testsuite/ * gas/aarch64/tail_padding.s: New testcase. * gas/aarch64/tail_padding.d: New expectation file.
2015-03-13 13:00:37 +01:00
2015-03-13 Jiong Wang <jiong.wang@arm.com>
* config/tc-aarch64.h (SUB_SEGMENT_ALIGN): Define to be zero.
Add i6400 entry to the MIPS CPU table. gas/ * config/tc-mips.c (mips_cpu_info_table): Add i6400 entry. * doc/c-mips.texi: Document i6400 -march option.
2015-03-12 17:27:46 +01:00
2015-03-12 Andrew Bennett <andrew.bennett@imgtec.com>
* config/tc-mips.c (mips_cpu_info_table): Add i6400 entry.
* doc/c-mips.texi: Document i6400 -march option.
Fixes a problem generating relocs for thumb function calls to local symbols defined in other sections. PR gas/17444 * config/tc-arm.h (MD_APPLY_SYM_VALUE): Pass the current segment to arm_apply_sym_value. Update prototype. * config/tc-arm.c (arm_apply_sym_value): Add segment argument. Do not apply the value if the symbol is in a different segment to the current segment.
2015-03-12 16:58:37 +01:00
2015-03-12 Nick Clifton <nickc@redhat.com>
PR gas/17444
* config/tc-arm.h (MD_APPLY_SYM_VALUE): Pass the current segment
to arm_apply_sym_value. Update prototype.
* config/tc-arm.c (arm_apply_sym_value): Add segment argument.
Do not apply the value if the symbol is in a different segment to
the current segment.
Fix powerpc gas abort on invalid instruction fixups * config/tc-ppc.c (md_assemble): Don't abort on 8 byte insn fixups. (md_apply_fix): Report an error on data-only fixups used with insns.
2015-03-11 08:23:50 +01:00
2015-03-11 Alan Modra <amodra@gmail.com>
* config/tc-ppc.c (md_assemble): Don't abort on 8 byte insn fixups.
(md_apply_fix): Report an error on data-only fixups used with insns.
S/390: Add check for length field operand gas/ 2015-03-10 Andreas Krebbel <krebbel@linux.vnet.ibm.com> * gas/config/tc-s390.c (md_gather_operands): Check for valid length field operands.
2015-03-10 12:41:57 +01:00
2015-03-10 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
* config/tc-s390.c (md_gather_operands): Check for valid
length field operands.
Fixes a bug in the ARM port of GAS when parsing inverted register lists. * config/tc-arm.c (parse_operands): Fix bug setting writeback values for '^' on OP_REGLSTs. (do_push_pop): Add new writeback constraint.
2015-03-10 12:47:46 +01:00
2015-03-10 Michael Perkins <perkinsmg75@yahoo.co.uk>
* config/tc-arm.c (parse_operands): Fix bug setting writeback
values for '^' on OP_REGLSTs.
(do_push_pop): Add new writeback constraint.
[ARM]Fix "align directive causes MAP_DATA symbol to be lost" gas/ 2015-03-10 Renlin Li <renlin.li@arm.com> * config/tc-arm.c (mapping_state): Remove first MAP_DATA emitting code. (mapping_state_2): Emit first MAP_DATA symbol here. gas/testsuite/ 2015-03-05 Renlin Li <renlin.li@arm.com> * gas/arm/dis-data.d: Adjust the desired output. * gas/arm/dis-data2.d: Ditto.
2015-03-10 12:34:50 +01:00
2015-03-10 Renlin Li <renlin.li@arm.com>
* config/tc-arm.c (mapping_state): Remove first MAP_DATA emitting code.
(mapping_state_2): Emit first MAP_DATA symbol here.
[AArch64] Set the minimum alignment on code segments gas/ 2015-03-10 Matthew Wahab <matthew.wahab@arm.com> * config/tc-aarch64.c (mapping_state): Set minimum alignment for code sections. gas/testsuite 2015-03-10 Matthew Wahab <matthew.wahab@arm.com> * gas/aarch64/codealign.d: Add test for code section alignment. * gas/aarch64/codealign.s: New file.
2015-03-10 12:20:57 +01:00
2015-03-10 Matthew Wahab <matthew.wahab@arm.com>
* config/tc-aarch64.c (mapping_state): Set minimum alignment for
code sections.
Fixes a bug building the ARM Linux kernel with a toolchain compiled with CPU_DEFAULT set. PR gas/17852 * config/tc-arm.c (md_begin): Ensure that selected_cpu is initialised when CPU_DEFAULT is defined.
2015-03-10 11:01:45 +01:00
2015-03-10 Nick Clifton <nickc@redhat.com>
PR gas/17852
* config/tc-arm.c (md_begin): Ensure that selected_cpu is
initialised when CPU_DEFAULT is defined.
Fixes a thinko in the implementation of the V850 -m8byte-align and -m4byte-align command line options. * config/tc-v850.c (md_parse_option): Fix code to set or clear EF_RH850_DATA_ALIGN8 bit in ELF header, based upon the use of the -m8byte-align and -m4byte-align command line options.
2015-03-05 14:04:33 +01:00
2015-03-05 Nick Clifton <nickc@redhat.com>
* config/tc-v850.c (md_parse_option): Fix code to set or clear
EF_RH850_DATA_ALIGN8 bit in ELF header, based upon the use of the
-m8byte-align and -m4byte-align command line options.
Allow MOVK for R_AARCH64_TLSLE_MOVW_TPREL_G{0,1}NC bfd/ PR gas/17843 * elfxx-aarch64.c (_bfd_aarch64_elf_put_addend): Expect R_AARCH64_TLSLE_MOVW_TPREL_G0_NC and R_AARCH64_TLSLE_MOVW_TPREL_G1_NC to be used with MOVK rather than MOVZ. gas/ PR gas/17843 * config/tc-aarch64.c (process_movw_reloc_info): Allow R_AARCH64_TLSLE_MOVW_TPREL_G0_NC and R_AARCH64_TLSLE_MOVW_TPREL_G1_NC for MOVK. gas/testsuite/ PR gas/17843 * gas/aarch64/tls.s, gas/aarch64/tls.d: Add test for R_AARCH64_TLSLE_MOVW_TPREL_G0/R_AARCH64_TLSLE_MOVW_TPREL_G1_NC sequence. ld/testsuite/ PR gas/17843 * ld-aarch64/tlsle.s, ld-aarch64/tlsle.d: New test. * ld-aarch64/aarch64-elf.exp: Run it.
2015-03-04 10:08:49 +01:00
2015-03-04 Richard Sandiford <richard.sandiford@arm.com>
PR gas/17843
* config/tc-aarch64.c (process_movw_reloc_info): Allow
R_AARCH64_TLSLE_MOVW_TPREL_G0_NC and R_AARCH64_TLSLE_MOVW_TPREL_G1_NC
for MOVK.
Pad only text sections at end by default gas/ * write.c (SUB_SEGMENT_ALIGN): Don't pad non-code sections at end to their alignment. gas/testsuite/ * gas/sparc/pcrel.d: Update for changed padding in data sections. * gas/sparc/pcrel64.d: Likewise. ld/testsuite/ * ld-sparc/gotop32.rd: Update for changed padding in data sections. * ld-sparc/gotop32.td: Likewise. * ld-sparc/gotop64.rd: Likewise. * ld-sparc/gotop64.td: Likewise. * ld-tilegx/external.s: Align .data. * ld-tilepro/external.s: Likewise.
2015-02-25 00:06:36 +01:00
2015-02-28 Alan Modra <amodra@gmail.com>
* write.c (SUB_SEGMENT_ALIGN): Don't pad non-code sections at
end to their alignment.
[AArch64] Add support for :tlsdesc: and TLSDESC_ADR_PREL21
2015-02-18 16:36:40 +01:00
2015-02-19 Marcus Shawcroft <marcus.shawcroft@arm.com>
* config/tc-aarch64.c (reloc_table_entry): Generate
BFD_RELOC_AARCH64_TLSDESC_ADR_PREL21.
(md_apply_fix, aarch64_force_relocation): Handle
BFD_RELOC_AARCH64_TLSGD_ADR_PREL21.
Add ADR :tlsgd: directive and TLSGD_ADR_PREL21 support.
2015-02-13 08:13:57 +01:00
2015-02-19 Marcus Shawcroft <marcus.shawcroft@arm.com>
* config/tc-aarch64.c (reloc_table_entry): Generate
BFD_RELOC_AARCH64_TLSGD_ADR_PREL21.
(md_apply_fix, aarch64_force_relocation): Handle
BFD_RELOC_AARCH64_TLSGD_ADR_PREL21.
Adding support for TLSIE_LD_GOTTREL_PREL19.
2015-02-13 10:57:11 +01:00
2015-02-19 Marcus Shawcroft <marcus.shawcroft@arm.com>
* config/tc-aarch64.c (reloc_table_entry): Generate
BFD_RELOC_AARCH64_TLSIE_LD_GOTTPREL_PREL19.
(md_apply_fix, aarch64_force_relocation): Handle
BFD_RELOC_AARCH64_TLSIE_LD_GOTTPREL_PREL19.
Adding ld_literal_type. Extend the address modifier parsing to distinguish between the modifers used in LDR literal and LDR register offset address modes. The current parser incorrectly accepts the :got: modifier on a register offset instruction resulting in silent corruption of the output binary.
2015-02-18 19:10:27 +01:00
2015-02-26 Marcus Shawcroft <marcus.shawcroft@arm.com>
* config/tc-aarch64.c (reloc_table_entry): Add ld_literal_type.
(reloc_table): Likewise.
(parse_address_main): Use ld_literal_type.
Adding adr_type and prevent adr :got: The current implementation of the :got: assembler modifier does not distinguish the ADR and ADRP instruction. The :got: modifier does not make sense on and ADR instruction and should be error'd rather than the current behavior of applying an inappropriate relocation to the output and scrambling the underlying instruction silently.
2015-02-05 17:57:09 +01:00
2015-02-26 Marcus Shawcroft <marcus.shawcroft@arm.com>
* config/tc-aarch64.c (reloc_table_entry): Add adr_type.
(reloc_table): Likewise.
(parse_address_main): Use adr_type.
Remove dead code.
2015-02-13 07:02:52 +01:00
2015-02-26 Marcus Shawcroft <marcus.shawcroft@arm.com>
* config/tc-aarch64.c (aarch64_arch_any, aarch64_arch_node): Remove.
avr/gas: Write out data to track .org/.align usage. Adds support to the assembler to write out data for tracking the use of .org and .align directives. This data is collected within the assembler and written out to a section ".avr.prop" (if there's anything to write out). This patch does not add any tests. The next patch in this series will add a better mechanism for visualising the contents of .avr.prop which will make writing tests much easier. This patch also does not make any use of this collected data, that will also come along in a later patch; the intended consumer is the linker, during linker relaxation this information will be used to ensure that the .org and .align directives are honoured. bfd/ChangeLog: * elf32-avr.h (AVR_PROPERTY_RECORD_SECTION_NAME): Define. (AVR_PROPERTY_RECORDS_VERSION): Define. (AVR_PROPERTY_SECTION_HEADER_SIZE): Define. (struct avr_property_record): New structure. gas/ChangeLog: * config/tc-avr.c: Add elf32-avr.h include. (struct avr_property_record_link): New structure. (avr_output_property_section_header): New function. (avr_record_size): New function. (avr_output_property_record): New function. (avr_create_property_section): New function. (avr_handle_align): New function. (exclude_section_from_property_tables): New function. (create_record_for_frag): New function. (append_records_for_section): New function. (avr_create_and_fill_property_section): New function. (avr_post_relax_hook): New function. * config/tc-avr.h (md_post_relax_hook): Define. (avr_post_relax_hook): Declare. (HANDLE_ALIGN): Define. (avr_handle_align): Declare. (strut avr_frag_data): New structure. (TC_FRAG_TYPE): Define.
2015-01-08 21:55:10 +01:00
2015-02-25 Andrew Burgess <andrew.burgess@embecosm.com>
* config/tc-avr.c: Add elf32-avr.h include.
(struct avr_property_record_link): New structure.
(avr_output_property_section_header): New function.
(avr_record_size): New function.
(avr_output_property_record): New function.
(avr_create_property_section): New function.
(avr_handle_align): New function.
(exclude_section_from_property_tables): New function.
(create_record_for_frag): New function.
(append_records_for_section): New function.
(avr_create_and_fill_property_section): New function.
(avr_post_relax_hook): New function.
* config/tc-avr.h (md_post_relax_hook): Define.
(avr_post_relax_hook): Declare.
(HANDLE_ALIGN): Define.
(avr_handle_align): Declare.
(strut avr_frag_data): New structure.
(TC_FRAG_TYPE): Define.
[gas][ARM] Document supported ARMv8 cores. 2015-02-25 Matthew Wahab <matthew.wahab@arm.com> * doc/c-arm.texi (-mcpu=): Add cortex-a53, cortex-a57 and cortex-a72.
2015-02-25 14:40:08 +01:00
2015-02-25 Matthew Wahab <matthew.wahab@arm.com>
* doc/c-arm.texi (-mcpu=): Add cortex-a53, cortex-a57 and
cortex-a72.
Adds support for generating notes in V850 binaries. bfd * elf32-v850.c (v850_set_note): New function. Creates a Renesas style note entry. (v850_elf_make_note_section): New function. Creates a note section. (v850_elf_create_sections): New function. Create a note section if one is not already present. (v850_elf_set_note): New function. Adds a note to a bfd. (v850_elf_copy_private_bfd_data): New function. Copies V850 notes. (v850_elf_merge_notes): New function. Merges V850 notes. (print_v850_note): New function. Displays a V850 note. (v850_elf_print_notes): New function. Displays all notes attached to a bfd. (v850_elf_merge_private_bfd_data): Call v850_elf_merge_notes. (v850_elf_print_private_bfd_data): Call v850_elf_print_notes. (v850_elf_fake_sections): Set the type of the V850 note section. * bfd-in.h (v850_elf_create_sections): Add prototype. (v850_elf_set_note): Add prototype. * bfd-in2.h: Regenerate. binutils* readelf.c (get_machine_flags): Remove deprecated V850 machine flags. (get_v850_section_type_name): New function. Handles V850 special sections. (get_section_type_name): Add support for V850. (get_v850_elf_note_type): New function. Returns the name of a V850 note. (print_v850_note): New function. Prints a V850 note. (process_v850_notes): New function. Prints V850 notes. (process_note_sections): Add support for V850. binutils/testsute * binutils-all/objcopy.exp: Skip the strip-10 test for the V850. gas * config/tc-v850.c (soft_float): New variable. (v850_data_8): New variable. (md_show_usage): Add -msoft-float/-mhard-float. (md_parse_option): Likewise. (md_begin): Set the default value of soft_float. (v850_md_end): New function. Creates a note section. * config/tc-v850.h (md_end): Define. * doc/c-v850.texi: Document -msoft-float/-mhard-float. gas/testsuite * gas/elf/elf.exp: Add special version of the section2 test for the V850. * gas/elf/section2.e-v850: New file. include/elf * v850.h (EF_RH850_SIMD): Delete deprecated flag. (EF_RH850_CACHE): Likewise. (EF_RH850_MMU): Likewise. (EF_RH850_DATA_ALIGN8): Likewise. (SHT_RENESAS_IOP): Fix typo in name. (SHT_RENESAS_INFO): Define. (V850_NOTE_SECNAME): Define. (SIZEOF_V850_NOTE): Define. (V850_NOTE_NAME): Define. (enum v850_notes): New enum. (NUM_V850_NOTES): Define. ld/ChangeLog 2015-02-24 Nick Clifton <nickc@redhat.com> * Makefile.am (ev850.c): Add dependency upon $(srcdir)/emultempl/v850elf.em. (ev850_rh850.c): Likewise. * Makefile.in: Regenerate. * emultempl/v850elf.em: New file. * emulparams/v850.sh (EXTRA_EM_FILE): Define. * emulparams/v850_rh850.sh (EXTRA_EM_FILE): Define. * scripttempl/v850.sc: Add .note.renesas section. * scripttempl/v850_rh850.sc: Likewise. ld/testsuite * ld-elf/extract-symbol-1sec.d: Expect to fail on the V850.
2015-02-24 18:54:09 +01:00
2015-02-24 Nick Clifton <nickc@redhat.com>
* config/tc-v850.c (soft_float): New variable.
(v850_data_8): New variable.
(md_show_usage): Add -msoft-float/-mhard-float.
(md_parse_option): Likewise.
(md_begin): Set the default value of soft_float.
(v850_md_end): New function. Creates a note section.
* config/tc-v850.h (md_end): Define.
* doc/c-v850.texi: Document -msoft-float/-mhard-float.
Add support for the h8300-linux target. ld * Makefile.am: (ALL_EMULATION_SOURCES): Add new emulations. * Makefile.in: Regenerate. * configure.tgt: Add h8300-*-linux * emulparams/h8300elf_linux.sh: Add new emulation. * emulparams/h8300helf_linux.sh: Likewise. * emulparams/h8300self_linux.sh: Likewise. * emulparams/h8300sxelf_linux.sh: Likewise. bfd * config.bfd: Add h8300-*-linux. * configure.ac: Add h8300_elf32_linux_vec. * configure: Regenerate. * elf32-h8300.c: Likewise. * targets.c(_bfd_target_vector): Likewise. gas * config/tc-h8300.c (line_separater_chars): Add a version for h8300-linux that includes a separator. (default_mach): New variable. (md_main): Use it. (md_longopts): Add '--march' option. (md_parse_option): Parse the new option. * config/tc-h8300.h (TARGET_FORMAT): Add elf32-h8300-linux. * configure.tgt: Add h8300-*-linux * doc/c-h8300.texi: Document --march.
2015-02-23 18:04:53 +01:00
2015-02-23 Yoshinori Sato <ysato@users.sourceforge.jp>
* config/tc-h8300.c (line_separater_chars): Add a version for
h8300-linux that includes a separator.
(default_mach): New variable.
(md_main): Use it.
(md_longopts): Add '--march' option.
(md_parse_option): Parse the new option.
* config/tc-h8300.h (TARGET_FORMAT): Add elf32-h8300-linux.
* configure.tgt: Add h8300-*-linux
* doc/c-h8300.texi: Document --march.
Fixes the generation of dwarf line debug information for the msp430, even in the presence of function sections and linker garbage collection. PR 17940 * dwarf2dbg.c (out_header): When generating dwarf sections use real symbols not temps for the start and end symbols. * config/tc-msp430.h (TC_FORCE_RELOCATION_SUB_SAME): Also prevent adjustments to relocations in debug sections. (TC_LINKRELAX_FIXUP): Likewise. * elf32-msp430.c (msp430_elf_relax_delete_bytes): Adjust debug symbols at end of sections. Adjust function sizes.
2015-02-23 15:53:02 +01:00
2015-02-23 Nick Clifton <nickc@redhat.com>
PR 17940
* dwarf2dbg.c (out_header): When generating dwarf sections use
real symbols not temps for the start and end symbols.
* config/tc-msp430.h (TC_FORCE_RELOCATION_SUB_SAME): Also prevent
adjustments to relocations in debug sections.
(TC_LINKRELAX_FIXUP): Likewise.
gas doc warning fixes * doc/as.texinfo (Local Symbol Names): Don't use ':' in pxref. * doc/c-i386.texi: Reorder i386-Bugs after i386-Arch.
2015-02-14 09:02:48 +01:00
2015-02-19 Alan Modra <amodra@gmail.com>
* doc/as.texinfo (Local Symbol Names): Don't use ':' in pxref.
* doc/c-i386.texi: Reorder i386-Bugs after i386-Arch.
[AArch64] Fix code formatting in the cpu-table 2015-02-11 Matthew Wahab <matthew.wahab@arm.com> * config/tc-aarch64.c (aarch64_cpus): Fix code formatting.
2015-02-11 15:35:27 +01:00
2015-02-11 Matthew Wahab <matthew.wahab@arm.com>
* config/tc-aarch64.c (aarch64_cpus): Fix code formatting.
[ARM] Add support for Cortex-A72 2015-02-11 Matthew Wahab <matthew.wahab@arm.com> * config/tc-arm.c: Add support for Cortex-A72.
2015-02-11 11:54:50 +01:00
2015-02-11 Matthew Wahab <matthew.wahab@arm.com>
* config/tc-arm.c: Add support for Cortex-A72.
[ARM][gas] Use as_tsktsk instead of as_warn for deprecation messages. * config/tc-arm.c (warn_deprecated_sp): Use as_tsktsk instead of as_warn for deprecation messages. (encode_arm_addr_mode_2): Likewise. (check_obsolete): Likewise. (do_rd_rm_rn): Likewise. (do_co_reg): Likewise. (do_setend): Likewise. (do_t_mov_cmp): Likewise. (do_neon_ldr_str): Likewise. (opcode_lookup): Likewise. (if_fsm_post_encode): Likewise. (md_assemble): Likewise. * gas/arm/armv1.l: Remove 'Warning: ' from expected messages for deprecations. * gas/arm/armv8-a-bad.l: Likewise. * gas/arm/armv8-a-it-bad.l: Likewise. * gas/arm/depr-swp.l: Likewise. * gas/arm/ldsgeb.l: Likewise. * gas/arm/ldsgeh.l: Likewise. * gas/arm/thumb2_bad_reg.l: Likewise. * gas/arm/thumb32.l: Likewise. * gas/arm/udf.l: Likewise. * gas/arm/vstr-arm-bad.l: Likewise.
2015-02-09 12:20:30 +01:00
2015-02-09 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
* config/tc-arm.c (warn_deprecated_sp): Use as_tsktsk instead
of as_warn for deprecation messages.
(encode_arm_addr_mode_2): Likewise.
(check_obsolete): Likewise.
(do_rd_rm_rn): Likewise.
(do_co_reg): Likewise.
(do_setend): Likewise.
(do_t_mov_cmp): Likewise.
(do_neon_ldr_str): Likewise.
(opcode_lookup): Likewise.
(if_fsm_post_encode): Likewise.
(md_assemble): Likewise.
gas: fix a few omissions in .cfi_label handling While actually starting to use that new directive, I noticed a few oversights of the original commit. gas/ 2015-02-06 Jan Beulich <jbeulich@suse.com> * dw2gencfi.c (select_cie_for_fde): Also bail on CFI_label. (cfi_change_reg_numbers): Also do nothing for CFI_label. (cfi_pseudo_table): Also handle .cfi_label when not supporting CFI directives.
2015-02-06 09:11:09 +01:00
2015-02-06 Jan Beulich <jbeulich@suse.com>
* dw2gencfi.c (select_cie_for_fde): Also bail on CFI_label.
(cfi_change_reg_numbers): Also do nothing for CFI_label.
(cfi_pseudo_table): Also handle .cfi_label when not supporting
CFI directives.
Fix msp430 build with gcc-5 gcc-5 correctly complains "loop exit may only be reached after undefined behavior". I was going to correct this by checking the index before dereferencing the array rather than the other way around, but then I noticed it is possible for extract_cmd to write the terminating zero one past the end of "cmd". Fixing that means no index check is needed in md_assemble. * config/tc-msp430.c (md_assemble): Correct size passed to extract_cmd. Remove index check.
2015-02-04 23:44:56 +01:00
2015-02-05 Alan Modra <amodra@gmail.com>
* config/tc-msp430.c (md_assemble): Correct size passed to
extract_cmd. Remove index check.
[AArch64] Add support for Cortex-A72 2015-02-04 Matthew Wahab <matthew.wahab@arm.com> * config/tc-aarch64.c (aarch64_cpus): Add support for Cortex-A72. * doc/c-aarch64.texi (-mcpu=): Add "cortex-a72".
2015-02-04 20:17:12 +01:00
2015-02-04 Matthew Wahab <matthew.wahab@arm.com>
* config/tc-aarch64.c (aarch64_cpus): Add support for Cortex-A72.
* doc/c-aarch64.texi (-mcpu=): Add "cortex-a72".
Fix encoding of "addw ax, [hl]" and "subw ax, [hl]". * config/rl78-parse.y (addsubw): Fix encoding of [HL] variant of these instructions.
2015-02-04 13:00:58 +01:00
2015-02-04 Nick Clifton <nickc@redhat.com>
* config/rl78-parse.y (addsubw): Fix encoding of [HL] variant of
these instructions.
[AARCH64] Document .arch and .arch_extension directive 2015-02-03 Renlin Li <renlin.li@arm.com> gas/ * doc/c-aarch64.texi (.arch): Document the directive. (.arch_extension): Likewise.
2015-02-03 15:02:24 +01:00
2015-02-03 Renlin Li <renlin.li@arm.com>
* doc/c-aarch64.texi (.arch): Document the directive.
(.arch_extension): Likewise.
Fix use of uninitialised memory by the RL78 port of GAS. * config/tc-rl78.h (TC_PARSE_CONS_EXPRESSION): Define.
2015-02-03 11:10:51 +01:00
2015-02-03 Nick Clifton <nickc@redhat.com>
* config/tc-rl78.h (TC_PARSE_CONS_EXPRESSION): Define.
FT32 initial support FT32 is a new 32-bit RISC core developed by FTDI for embedded applications. * configure.ac: Add FT32 support. * configure: Regenerate. bfd/ * Makefile.am: Add FT32 files. * archures.c (enum bfd_architecture): Add bfd_arch_ft32. (bfd_mach_ft32): Define. (bfd_ft32_arch): Declare. (bfd_archures_list): Add bfd_ft32_arch. * config.bfd: Handle FT32. * configure.ac: Likewise. * cpu-ft32.c: New file. * elf32-ft32.c: New file. * reloc.c (BFD_RELOC_FT32_10, BFD_RELOC_FT32_20, BFD_RELOC_FT32_17, BFD_RELOC_FT32_18): Define. * targets.c (_bfd_target_vector): Add ft32_elf32_vec. * bfd-in2.h: Regenerate. * libbfd.h: Regenerate. * Makefile.in: Regenerate. * configure: Regenerate. * po/SRC-POTFILES.in: Regenerate. binutils/ * readelf.c: Add FT32 support. gas/ * Makefile.am: Add FT32 files. * config/tc-ft32.c: New file. * config/tc-ft32.h: New file. * configure.tgt: Add FT32 support. * Makefile.in: Regenerate. * po/POTFILES.in: Regenerate. gas/testsuite/ * gas/ft32/ft32.exp: New file. * gas/ft32/insn.d: New file. * gas/ft32/insn.s: New file. include/ * dis-asm.h (print_insn_ft32): Declare. include/elf/ * common.h (EM_FT32): Define. * ft32.h: New file. include/opcode/ * ft32.h: New file. ld/ * Makefile.am: Add FT32 files. * configure.tgt: Handle FT32 target. * emulparams/elf32ft32.sh: New file. * scripttempl/ft32.sc: New file. * Makefile.in: Regenerate. opcodes/ * Makefile.am: Add FT32 files. * configure.ac: Handle FT32. * disassemble.c (disassembler): Call print_insn_ft32. * ft32-dis.c: New file. * ft32-opc.c: New file. * Makefile.in: Regenerate. * configure: Regenerate. * po/POTFILES.in: Regenerate.
2015-01-28 06:06:43 +01:00
2015-01-28 James Bowman <james.bowman@ftdichip.com>
* Makefile.am: Add FT32 files.
* config/tc-ft32.c: New file.
* config/tc-ft32.h: New file.
* configure.tgt: Add FT32 support.
* Makefile.in: Regenerate.
* po/POTFILES.in: Regenerate.
NDS32/gas: Limit the format of pseudo instruction la.
2015-01-27 04:19:13 +01:00
2015-01-27 Kuan-Lin Chen <kuanlinchentw@gmail.com>
* config/tc-nds32.c (do_pseudo_la_internal): Limit the second argument
of instruction la to a symbol.
NDS32/gas: Fix md_parse_name hook.
2015-01-27 04:08:07 +01:00
2015-01-27 Kuan-Lin Chen <kuanlinchentw@gmail.com>
* config/tc-nds32.c (nds32_parse_name): Ignore when the input is
section name.
Extend .reloc to accept some BFD_RELOCs Tests that bfd_perform_reloc doesn't freak over a NONE reloc at end of section. gas/ * read.c (s_reloc): Match BFD_RELOC_NONE, BFD_RELOC{8,16,32,64}. * write.c (get_frag_for_reloc): Allow match just past end of frag. gas/testsuite/ * gas/all/none.s, * gas/all/none.d: New test. * gas/all/gas.exp: Run it.
2015-01-19 09:27:04 +01:00
2015-01-19 Alan Modra <amodra@gmail.com>
* read.c (s_reloc): Match BFD_RELOC_NONE, BFD_RELOC{8,16,32,64}.
* write.c (get_frag_for_reloc): Allow match just past end of frag.
S/390: Add support for IBM z13. - 32 128 bit vector registers (overlapping with the existing 16 64 bit floating point registers) - vector double instructions - vector integer instructions - scalar vector instructions (allowing to have more floating point registers for scalar operations) - vector string instructions gas/ChangeLog: * config/tc-s390.c (struct pd_reg): Remove. (pre_defined_registers): Remove. (REG_NAME_CNT): Remove. (reg_name_search): Calculate the register number instead of doing a lookup. (register_name, tc_s390_regname_to_dw2regnum): Adopt to the new reg_name_search signature. (s390_parse_cpu): Support the new arch string z13. (s390_insert_operand): Support for vector registers with the extra field for the fifth bit of each vector register operand. (md_gather_operand): Adjust to the new handling of optional parameters. * doc/as.texinfo: Document the z13 cpu string. gas/testsuite/ChangeLog: * gas/s390/esa-g5.d: Add a variant without the optional operand. * gas/s390/esa-g5.s: Likewise. * gas/s390/esa-z9-109.d: Likewise. * gas/s390/esa-z9-109.s: Likewise. * gas/s390/zarch-z9-109.d: Likewise. * gas/s390/zarch-z9-109.s: Likewise. * gas/s390/zarch-z10.d: For variants with a zero optional argument it is not dumped by objdump anymore. * gas/s390/zarch-zEC12.d: Likewise. * gas/s390/zarch-z13.d: New file. * gas/s390/zarch-z13.s: New file. * gas/s390/s390.exp: Run the test for the z13 files. include/opcode/ChangeLog: * s390.h (s390_opcode_cpu_val): Add S390_OPCODE_Z13. ld/testsuite/ChangeLog: * ld-s390/tlsbin.dd: The nopr register operand is optional and not printed if 0 anymore. opcodes/ChangeLog: * s390-dis.c (s390_extract_operand): Support vector register operands. (s390_print_insn_with_opcode): Support new operands types and add new handling of optional operands. * s390-mkopc.c (s390_opcode_mode_val, s390_opcode_cpu_val): Remove and include opcode/s390.h instead. (struct op_struct): New field `flags'. (insertOpcode, insertExpandedMnemonic): New parameter `flags'. (dumpTable): Dump flags. (main): Parse flags from the s390-opc.txt file. Add z13 as cpu string. * s390-opc.c: Add new operands types, instruction formats, and instruction masks. (s390_opformats): Add new formats for .insn. * s390-opc.txt: Add new instructions.
2015-01-16 12:19:21 +01:00
2015-01-16 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
* config/tc-s390.c (struct pd_reg): Remove.
(pre_defined_registers): Remove.
(REG_NAME_CNT): Remove.
(reg_name_search): Calculate the register number instead of doing
a lookup.
(register_name, tc_s390_regname_to_dw2regnum): Adopt to the new
reg_name_search signature.
(s390_parse_cpu): Support the new arch string z13.
(s390_insert_operand): Support for vector registers with the extra
field for the fifth bit of each vector register operand.
(md_gather_operand): Adjust to the new handling of optional
parameters.
* doc/as.texinfo: Document the z13 cpu string.
[ARM] vcmp/vcmpe should accept #0x0 as an operand gas/ 2015-01-13 Matthew Wahab <matthew.wahab@arm.com> * config/tc-arm.c (parse_ifimm_zero): Accept #0x0 as a synonym for #0, restoring previous behaviour. gas/testsuite/ 2015-01-13 Matthew Wahab <matthew.wahab@arm.com> * gas/arm/ual-vcmp.s: Add vcmp, vcmpe with #0x0 operand. * gas/ual/vcmp.d: Update expected output. * gas/ual/vcmp-zero-bad.l: Likewise
2015-01-13 16:44:47 +01:00
2015-01-13 Matthew Wahab <matthew.wahab@arm.com>
* config/tc-arm.c (parse_ifimm_zero): Accept #0x0 as a synonym for
#0, restoring previous behaviour.
gas: allow labeling of CFI instructions When runtime patching code (like e.g. done by the Linux kernel) there may be cases where the set of stack frame alterations differs between unpatched and patched code. Consequently the corresponding unwind data needs patching too. Locating the right places within an FDE, however, is rather cumbersome without a way to insert labels in the resulting section. Hence this patch introduces a new directive, .cfi_label. Note that with the way CFI data gets emitted currently (at the end of the assembly process) this can't support local FB- and dollar-labels. gas/ 2015-01-12 Jan Beulich <jbeulich@suse.com> * gas/dw2gencfi.c (cfi_add_label, dot_cfi_label): New. (cfi_pseudo_table): Add "cfi_label". (output_cfi_insn): Handle CFI_label. (select_cie_for_fde): Als terminate CIE when encountering CFI_label. * dw2gencfi.h (cfi_add_label): Declare. (struct cfi_insn_data): New member "sym_name". (CFI_label): New. * read.c (read_symbol_name): Drop "static". * read.h (read_symbol_name): Declare. gas/testsuite/ 2015-01-12 Jan Beulich <jbeulich@suse.com> gas/cfi/cfi-label.d, gas/cfi/cfi-label.s: New. gas/cfi/cfi.exp: Run new tests.
2015-01-12 15:24:20 +01:00
2015-01-12 Jan Beulich <jbeulich@suse.com>
* gas/dw2gencfi.c (cfi_add_label, dot_cfi_label): New.
(cfi_pseudo_table): Add "cfi_label".
(output_cfi_insn): Handle CFI_label.
(select_cie_for_fde): Als terminate CIE when encountering
CFI_label.
* dw2gencfi.h (cfi_add_label): Declare.
(struct cfi_insn_data): New member "sym_name".
(CFI_label): New.
* read.c (read_symbol_name): Drop "static".
* read.h (read_symbol_name): Declare.
arm: properly range check immediate operands of VSHL and VQSHL These two, other than VQSHLU, didn't have their immediates properly range checked so far. (Re-sending unchanged from the original v2 due to never having got an answer to https://sourceware.org/ml/binutils/2013-04/msg00121.html.) gas/ 2015-01-12 Jan Beulich <jbeulich@suse.com> * gas/config/tc-arm.c (do_neon_shl_imm): Check immediate range. (do_neon_qshl_imm): Likewise. gas/testsuite/ 2015-01-12 Jan Beulich <jbeulich@suse.com> * gas/arm/neon-addressing-bad.s: Add test for invalid VSHL, VQSHL, and VQSHLU immediates. * gas/arm/neon-addressing-bad.l: Update accordingly.
2015-01-12 09:05:19 +01:00
2015-01-12 Jan Beulich <jbeulich@suse.com>
* gas/config/tc-arm.c (do_neon_shl_imm): Check immediate range.
(do_neon_qshl_imm): Likewise.
Assorted compiler warning fixes The C standard doesn't guarantee a function pointer can be cast to void* and vice versa. binutils/ * prdbg.c (print_debugging_info): Don't use void* for function pointer param. * budbg.h (print_debugging_info): Update prototype. gas/ * read.c (s_altmacro, s_reloc): Make definition static.
2015-01-10 23:00:33 +01:00
2015-01-12 Alan Modra <amodra@gmail.com>
* read.c (s_altmacro, s_reloc): Make definition static.
gas/avr: Prevent incorrect overflow errors for diff fixups. When fixups are converted to a difference type within md_apply_fix, we previously left the contents of VALP (the value that was initially computed within write.c:fixup_segment) unchanged. This is harmless, except that this value is used within write.c:fixup_segment once we return from md_apply_fix to perform an overflow check. In some cases, the value computed in write.c:fixup_segment is so wrong that an overflow error can be triggered. These errors are incorrect. This patch avoids the overflow errors by adjusting the value in write.c:fixup_segment using the VALP pointer in md_apply_fix. A test for this issue is included. gas/ChangeLog: * config/tc-avr.c (md_apply_fix): Update the contents of VALP for diff fixups. gas/testsuite/ChangeLog: * gas/avr/large-debug-line-table.d: New file. * gas/avr/large-debug-line-table.s: New file.
2015-01-04 01:03:16 +01:00
2015-01-10 Andrew Burgess <andrew.burgess@embecosm.com>
* config/tc-avr.c (md_apply_fix): Update the contents of VALP for
diff fixups.
This patch adds the necessary support to the assembler to allow wiring the X-Gene scheduling description up in the respective GCC backend. * config/tc-arm.c (arm_cpus): Add support for APM X-Gene 1 and X-Gene 2. * doc/c-arm.texi (ARM Options): Mention xgene1 and xgene2.
2015-01-09 21:00:14 +01:00
2015-01-09 Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
* config/tc-arm.c (arm_cpus): Add support for APM X-Gene 1 and
X-Gene 2.
* doc/c-arm.texi (ARM Options): Mention xgene1 and xgene2.
arm: fix extension feature disabling Using e.g. .arch_extension simd .arch_extension nocrypto so far results in SIMD support getting disabled, which I can't see being the purpose of the "no"-prefixed variants of architecture extension specifications. Of course it is questionable whether the current, counter intuitive behavior needs to be retained, and the new behavior perhaps be made work through e.g. a newly recognized "no-" prefix. gas/ 2015-01-07 Jan Beulich <jbeulich@suse.com> * gas/config/tc-arm.c (struct arm_option_extension_value_table): Split field "value" into fields "merge_value" and "clear_value". (arm_extensions): Adjust initializer accordingly.
2015-01-07 09:39:27 +01:00
2015-01-07 Jan Beulich <jbeulich@suse.com>
* config/tc-arm.c (struct arm_option_extension_value_table):
Split field "value" into fields "merge_value" and "clear_value".
(arm_extensions): Adjust initializer accordingly.
Correct printed year in copyright notices
2015-01-01 15:38:15 +01:00
2015-01-01 Alan Modra <amodra@gmail.com>
* as.c (parse_args): Just print current year.
ChangeLog rotatation and copyright year update
2015-01-01 15:15:26 +01:00
2015-01-01 Alan Modra <amodra@gmail.com>
Limit moxie sto/ldo offsets to 16 bits
2014-12-27 16:57:04 +01:00
ChangeLog rotatation and copyright year update
2015-01-01 15:15:26 +01:00
Update year range in copyright notice of all files.
Limit moxie sto/ldo offsets to 16 bits
2014-12-27 16:57:04 +01:00
ChangeLog rotatation and copyright year update
2015-01-01 15:15:26 +01:00
For older changes see ChangeLog-2014
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ChangeLog rotatation and copyright year update
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Copyright (C) 2015 Free Software Foundation, Inc.
Add copyright notices
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Copying and distribution of this file, with or without modification,
are permitted in any medium without royalty provided the copyright
notice and this notice are preserved.
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