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[MIPS] Add i6500 CPU and fix i6400 default ASEs gas/ * config/tc-mips.c (mips_cpu_info_table): Add i6500. Update default ASEs for i6400. * doc/c-mips.texi (-march): Document i6500. * testsuite/gas/mips/elf_mach_i6400.d: New test. * testsuite/gas/mips/elf_mach_i6500.d: New test. * testsuite/gas/mips/mips.exp: Run the new tests.
2019-04-09 22:40:00 +02:00
2019-04-09 Matthew Fortune <matthew.fortune@mips.com>
* config/tc-mips.c (mips_cpu_info_table): Add i6500. Update
default ASEs for i6400.
* doc/c-mips.texi (-march): Document i6500.
* testsuite/gas/mips/elf_mach_i6400.d: New test.
* testsuite/gas/mips/elf_mach_i6500.d: New test.
* testsuite/gas/mips/mips.exp: Run the new tests.
[MIPS] Apply ASE information for the selected processor GAS does not enable implicit ASEs for most MIPS processors. The rework of option handling done as part of .module implementation left the implicit ASE logic broken and default enabled ASEs for most processors did not get applied. This patch ensures the ASE information is carried forward to the point where it is required. gas/ * config/tc-mips.c (mips_set_options) <init_ase>: New field. (file_mips_opts, mips_opts) <init_ase>: Initialize new field. (file_mips_check_options): Propagate initial ASE settings. (mips_after_parse_args, parse_code_option): Track the initial ASE settings for a CPU. (s_mipsset): Restore the initial ASE settings when reverting to the default arch. * testsuite/gas/mips/elf_mach_p6600.d: New test. * testsuite/gas/mips/mips.exp: Run the new test.
2019-04-09 19:34:48 +02:00
2019-04-09 Matthew Fortune <matthew.fortune@mips.com>
* config/tc-mips.c (mips_set_options) <init_ase>: New field.
(file_mips_opts, mips_opts) <init_ase>: Initialize new field.
(file_mips_check_options): Propagate initial ASE settings.
(mips_after_parse_args, parse_code_option): Track the initial
ASE settings for a CPU.
(s_mipsset): Restore the initial ASE settings when reverting
to the default arch.
* testsuite/gas/mips/elf_mach_p6600.d: New test.
* testsuite/gas/mips/mips.exp: Run the new test.
GAS: S12Z: Remove definition of macro TC_M68K. gas/config: * tc-s12z.h: Remove inappropriate macro definition.
2019-04-12 18:39:01 +02:00
2019-04-12 John Darrington <john@darrington.wattle.id.au>
config/tc-s12z.h: Remove definition of macro TC_M68K
GAS: tc-s12z.c: int -> bfd_boolean Use bfd_boolean where appropriate.
2019-04-12 18:39:01 +02:00
2019-04-01 John Darrington <john@darrington.wattle.id.au>
config/tc-s12z.c: Use bfd_boolean where appropriate.
xtensa: gas: add relaxations tests gas/ 2019-04-11 Max Filippov <jcmvbkbc@gmail.com> * testsuite/gas/xtensa/loop-relax-2.d: New test definition. * testsuite/gas/xtensa/loop-relax.d: New test definition. * testsuite/gas/xtensa/loop-relax.s: New test source. * testsuite/gas/xtensa/text-section-literals-1a.d: New test definition. * testsuite/gas/xtensa/text-section-literals-2.d: New test definition. * testsuite/gas/xtensa/text-section-literals-2.s: New test source. * testsuite/gas/xtensa/text-section-literals-2a.d: New test definition. * testsuite/gas/xtensa/text-section-literals-3.d: New test definition. * testsuite/gas/xtensa/text-section-literals-3.s: New test source. * testsuite/gas/xtensa/text-section-literals-4.d: New test definition. * testsuite/gas/xtensa/text-section-literals-4.s: New test source. * testsuite/gas/xtensa/text-section-literals-4a.d: New test definition.
2019-04-05 02:06:57 +02:00
2019-04-11 Max Filippov <jcmvbkbc@gmail.com>
* testsuite/gas/xtensa/loop-relax-2.d: New test definition.
* testsuite/gas/xtensa/loop-relax.d: New test definition.
* testsuite/gas/xtensa/loop-relax.s: New test source.
* testsuite/gas/xtensa/text-section-literals-1a.d: New test
definition.
* testsuite/gas/xtensa/text-section-literals-2.d: New test
definition.
* testsuite/gas/xtensa/text-section-literals-2.s: New test
source.
* testsuite/gas/xtensa/text-section-literals-2a.d: New test
definition.
* testsuite/gas/xtensa/text-section-literals-3.d: New test
definition.
* testsuite/gas/xtensa/text-section-literals-3.s: New test
source.
* testsuite/gas/xtensa/text-section-literals-4.d: New test
definition.
* testsuite/gas/xtensa/text-section-literals-4.s: New test
source.
* testsuite/gas/xtensa/text-section-literals-4a.d: New test
definition.
xtensa: gas: convert tests to run_dump_tests gas/ 2019-04-11 Max Filippov <jcmvbkbc@gmail.com> * testsuite/gas/xtensa/all.exp: Remove all expect-based tests and all explicit run_dump_test / run_list_test invocations. Add run_dump_tests for all .d files in the test subdirectory. * testsuite/gas/xtensa/entry_align.d: New test definition. * testsuite/gas/xtensa/entry_align.l: New test output. * testsuite/gas/xtensa/entry_misalign.d: New test definition. * testsuite/gas/xtensa/entry_misalign2.d: New test definition. * testsuite/gas/xtensa/j_too_far.d: New test definition. * testsuite/gas/xtensa/j_too_far.l: New test output. * testsuite/gas/xtensa/loop_align.d: New test definition. * testsuite/gas/xtensa/loop_misalign.d: New test definition. * testsuite/gas/xtensa/trampoline-2.d: New test definition. * testsuite/gas/xtensa/trampoline-2.l: Remove empty output. * testsuite/gas/xtensa/xtensa-err.exp: Use positive logic.
2019-04-05 02:51:00 +02:00
2019-04-11 Max Filippov <jcmvbkbc@gmail.com>
* testsuite/gas/xtensa/all.exp: Remove all expect-based
tests and all explicit run_dump_test / run_list_test
invocations. Add run_dump_tests for all .d files in the
test subdirectory.
* testsuite/gas/xtensa/entry_align.d: New test definition.
* testsuite/gas/xtensa/entry_align.l: New test output.
* testsuite/gas/xtensa/entry_misalign.d: New test definition.
* testsuite/gas/xtensa/entry_misalign2.d: New test definition.
* testsuite/gas/xtensa/j_too_far.d: New test definition.
* testsuite/gas/xtensa/j_too_far.l: New test output.
* testsuite/gas/xtensa/loop_align.d: New test definition.
* testsuite/gas/xtensa/loop_misalign.d: New test definition.
* testsuite/gas/xtensa/trampoline-2.d: New test definition.
* testsuite/gas/xtensa/trampoline-2.l: Remove empty output.
* testsuite/gas/xtensa/xtensa-err.exp: Use positive logic.
xtensa: gas: clean up literal management code gas/ 2019-04-11 Max Filippov <jcmvbkbc@gmail.com> * config/tc-xtensa.c (xtensa_literal_pseudo): Drop code that has no effect. (get_literal_pool_location): Only search for the literal pool when auto litpools is used, otherwise take one recorded in the tc_segment_info_data. (xtensa_assign_litpool_addresses): New function. (xtensa_move_literals): Don't duplicate 'literal pool location required...' error message. Call xtensa_assign_litpool_addresses.
2019-04-10 10:18:01 +02:00
2019-04-11 Max Filippov <jcmvbkbc@gmail.com>
* config/tc-xtensa.c (xtensa_literal_pseudo): Drop code that has
no effect.
(get_literal_pool_location): Only search for the literal pool
when auto litpools is used, otherwise take one recorded in the
tc_segment_info_data.
(xtensa_assign_litpool_addresses): New function.
(xtensa_move_literals): Don't duplicate 'literal pool location
required...' error message. Call xtensa_assign_litpool_addresses.
xtensa: gas: put .literal_position at section start Provide literal position at the beginning of each section for literal space reserved by relaxations when text-section-literals or auto-litpools options are used. Remove code that adds fill frag to the literal section for every .literal_position directive to avoid creation of empty literal sections. Fix auto-litpools tests that got literal pool address changes. gas/ 2019-04-11 Max Filippov <jcmvbkbc@gmail.com> * config/tc-xtensa.c (xtensa_is_init_fini): Add declaration. (xtensa_mark_literal_pool_location): Don't add fill frag to literal section that records literal pool location. (md_begin): Call xtensa_mark_literal_pool_location when text section literals or auto litpools are used. (xtensa_elf_section_change_hook): Call xtensa_mark_literal_pool_location when text section literals or auto litpools are used, there's no literal pool location defined for the current section and it's not .init or .fini. * testsuite/gas/xtensa/auto-litpools-first1.d: Fix up addresses. * testsuite/gas/xtensa/auto-litpools-first2.d: Likewise. * testsuite/gas/xtensa/auto-litpools.d: Likewise.
2019-04-08 22:47:18 +02:00
2019-04-11 Max Filippov <jcmvbkbc@gmail.com>
* config/tc-xtensa.c (xtensa_is_init_fini): Add declaration.
(xtensa_mark_literal_pool_location): Don't add fill frag to literal
section that records literal pool location.
(md_begin): Call xtensa_mark_literal_pool_location when text
section literals or auto litpools are used.
(xtensa_elf_section_change_hook): Call
xtensa_mark_literal_pool_location when text section literals or
auto litpools are used, there's no literal pool location defined
for the current section and it's not .init or .fini.
* testsuite/gas/xtensa/auto-litpools-first1.d: Fix up addresses.
* testsuite/gas/xtensa/auto-litpools-first2.d: Likewise.
* testsuite/gas/xtensa/auto-litpools.d: Likewise.
[BINUTILS, AArch64, 2/2] Update Store Allocation Tag instructions This patch updates the Store allocation tags instructions in Armv8.5-A Memory Tagging Extension. This is part of the changes that have been introduced recently in the 00bet10 release All of these instructions have an updated register operand (Xt -> <Xt|SP>) - STG <Xt|SP>, [<Xn|SP>, #<simm>] - STG <Xt|SP>, [<Xn|SP>, #<simm>]! - STG <Xt|SP>, [<Xn|SP>], #<simm> - STZG <Xt|SP>, [<Xn|SP>, #<simm>] - STZG <Xt|SP>, [<Xn|SP>, #<simm>]! - STZG <Xt|SP>, [<Xn|SP>], #<simm> - ST2G <Xt|SP>, [<Xn|SP>, #<simm>] - ST2G <Xt|SP>, [<Xn|SP>, #<simm>]! - ST2G <Xt|SP>, [<Xn|SP>], #<simm> - STZ2G <Xt|SP>, [<Xn|SP>, #<simm>] - STZ2G <Xt|SP>, [<Xn|SP>, #<simm>]! - STZ2G <Xt|SP>, [<Xn|SP>], #<simm> In order to accept <Rt|SP> a new operand type Rt_SP is introduced which has the same field as FLD_Rt but follows other semantics of Rn_SP. *** gas/ChangeLog *** 2019-04-11 Sudakshina Das <sudi.das@arm.com> * config/tc-aarch64.c (process_omitted_operand): Add case for AARCH64_OPND_Rt_SP. (parse_operands): Likewise. * testsuite/gas/aarch64/armv8_5-a-memtag.d: Update tests. * testsuite/gas/aarch64/armv8_5-a-memtag.s: Likewise. * testsuite/gas/aarch64/illegal-memtag.l: Likewise. * testsuite/gas/aarch64/illegal-memtag.s: Likewise. *** include/ChangeLog *** 2019-04-11 Sudakshina Das <sudi.das@arm.com> * opcode/aarch64.h (enum aarch64_opnd): Add AARCH64_OPND_Rt_SP. *** opcodes/ChangeLog *** 2019-04-11 Sudakshina Das <sudi.das@arm.com> * aarch64-opc.c (aarch64_print_operand): Add case for AARCH64_OPND_Rt_SP. (verify_constraints): Likewise. * aarch64-tbl.h (QL_LDST_AT): Update to add SP qualifier. (struct aarch64_opcode): Update stg, stzg, st2g, stz2g instructions to accept Rt|SP as first operand. (AARCH64_OPERANDS): Add new Rt_SP. * aarch64-asm-2.c: Regenerated. * aarch64-dis-2.c: Regenerated. * aarch64-opc-2.c: Regenerated.
2019-04-11 11:19:37 +02:00
2019-04-11 Sudakshina Das <sudi.das@arm.com>
* config/tc-aarch64.c (process_omitted_operand): Add case for
AARCH64_OPND_Rt_SP.
(parse_operands): Likewise.
* testsuite/gas/aarch64/armv8_5-a-memtag.d: Update tests.
* testsuite/gas/aarch64/armv8_5-a-memtag.s: Likewise.
* testsuite/gas/aarch64/illegal-memtag.l: Likewise.
* testsuite/gas/aarch64/illegal-memtag.s: Likewise.
[BINUTILS, AArch64, 1/2] Add new LDGM/STGM instruction This patch adds the new LDGM/STGM instructions of the Armv8.5-A Memory Tagging Extension. This is part of the changes that have been introduced recently in the 00bet10 release The instructions are as follows: LDGM Xt, [<Xn|SP>] STGM Xt, [<Xn|SP>] *** gas/ChangeLog *** 2019-04-11 Sudakshina Das <sudi.das@arm.com> * testsuite/gas/aarch64/armv8_5-a-memtag.d: New tests for ldgm and stgm. * testsuite/gas/aarch64/armv8_5-a-memtag.s: Likewise. * testsuite/gas/aarch64/illegal-memtag.l: Likewise. * testsuite/gas/aarch64/illegal-memtag.s: Likewise. *** opcodes/ChangeLog *** 2019-04-11 Sudakshina Das <sudi.das@arm.com> * aarch64-asm-2.c: Regenerated. * aarch64-dis-2.c: Likewise. * aarch64-opc-2.c: Likewise. * aarch64-tbl.h (aarch64_opcode): Add new ldgm and stgm.
2019-04-11 11:13:23 +02:00
2019-04-11 Sudakshina Das <sudi.das@arm.com>
* testsuite/gas/aarch64/armv8_5-a-memtag.d: New tests for ldgm and stgm.
* testsuite/gas/aarch64/armv8_5-a-memtag.s: Likewise.
* testsuite/gas/aarch64/illegal-memtag.l: Likewise.
* testsuite/gas/aarch64/illegal-memtag.s: Likewise.
Disable R_X86_64_PLT32 generation as branch marker on Solaris/x86 The fix H.J. implemented for PR gas/22791 in the thread starting at [PATCH] x86-64: Treat PC32 relocation with branch as PLT32 https://sourceware.org/ml/binutils/2018-02/msg00065.html is causing problems on Solaris/x86. The native linker is strongly preferred there, and there's no intention of implementing the linker optimization he plans there. Besides, the kernel runtime linker, otherwise has no need to deal with that reloc at all, and instead of adding (possibly even more) workarounds with no benefit, it seems appropriate to disable the R_X86_64_PLT32 generation as branch marker on Solaris/x86 in the first place. The patch itself is trivial, the only complication is adapting the testsuite. Since I've found no way to have conditional sections in the .d files, I've instead used the solution already found elsewhere of having separate .d files for the affected tests in an i386/solaris subdirectory and skipping the original ones. Tested on amd64-pc-solaris2.11 and x86_64-pc-linux-gnu without regressions. * config/tc-i386.c (need_plt32_p) [TE_SOLARIS]: Return FALSE. * testsuite/gas/i386/solaris/solaris.exp: New driver. * testsuite/gas/i386/solaris/reloc64.d, testsuite/gas/i386/solaris/x86-64-jump.d, testsuite/gas/i386/solaris/x86-64-mpx-branch-1.d, testsuite/gas/i386/solaris/x86-64-mpx-branch-2.d, testsuite/gas/i386/solaris/x86-64-nop-3.d, testsuite/gas/i386/solaris/x86-64-nop-4.d, testsuite/gas/i386/solaris/x86-64-nop-5.d, testsuite/gas/i386/solaris/x86-64-relax-2.d, testsuite/gas/i386/solaris/x86-64-relax-3.d: New tests. * testsuite/gas/i386/reloc64.d, testsuite/gas/i386/x86-64-jump.d, testsuite/gas/i386/x86-64-mpx-branch-1.d, testsuite/gas/i386/x86-64-mpx-branch-2.d, testsuite/gas/i386/x86-64-nop-3.d, testsuite/gas/i386/x86-64-nop-4.d, testsuite/gas/i386/x86-64-nop-5.d, testsuite/gas/i386/x86-64-relax-2.d, testsuite/gas/i386/x86-64-relax-3.d: Skip on *-*-solaris*.
2019-04-10 09:48:43 +02:00
2019-04-10 Rainer Orth <ro@CeBiTec.Uni-Bielefeld.DE>
* config/tc-i386.c (need_plt32_p) [TE_SOLARIS]: Return FALSE.
* testsuite/gas/i386/solaris/solaris.exp: New driver.
* testsuite/gas/i386/solaris/reloc64.d,
testsuite/gas/i386/solaris/x86-64-jump.d,
testsuite/gas/i386/solaris/x86-64-mpx-branch-1.d,
testsuite/gas/i386/solaris/x86-64-mpx-branch-2.d,
testsuite/gas/i386/solaris/x86-64-nop-3.d,
testsuite/gas/i386/solaris/x86-64-nop-4.d,
testsuite/gas/i386/solaris/x86-64-nop-5.d,
testsuite/gas/i386/solaris/x86-64-relax-2.d,
testsuite/gas/i386/solaris/x86-64-relax-3.d: New tests.
* testsuite/gas/i386/reloc64.d,
testsuite/gas/i386/x86-64-jump.d,
testsuite/gas/i386/x86-64-mpx-branch-1.d,
testsuite/gas/i386/x86-64-mpx-branch-2.d,
testsuite/gas/i386/x86-64-nop-3.d,
testsuite/gas/i386/x86-64-nop-4.d,
testsuite/gas/i386/x86-64-nop-5.d,
testsuite/gas/i386/x86-64-relax-2.d,
testsuite/gas/i386/x86-64-relax-3.d: Skip on *-*-solaris*.
te-cloudabi.h This patch is aimed a fixing large numbers of x86_64-cloudabi failures caused by gas selecting the wrong target name. * config/te-cloudabi.h: New file. * config/tc-aarch64.c (aarch64_after_parse_args): Use TE_CLOUDABI rather than TARGET_OS to select cloudabi. * config/tc-i386.h (ELF_TARGET_FORMAT64): Define for TE_CLOUDABI. * configure.tgt (*-*-cloudabi*): Set em=cloudabi.
2019-04-08 09:27:51 +02:00
2019-04-10 Alan Modra <amodra@gmail.com>
* config/te-cloudabi.h: New file.
* config/tc-aarch64.c (aarch64_after_parse_args): Use TE_CLOUDABI
rather than TARGET_OS to select cloudabi.
* config/tc-i386.h (ELF_TARGET_FORMAT64): Define for TE_CLOUDABI.
* configure.tgt (*-*-cloudabi*): Set em=cloudabi.
[MIPS] Add RDHWR with the SEL field for MIPS R6. In Release 6 of the MIPS architecture [1], instruction RDHWR supports a 3rd operand to serve as the 3-bit select field for the hardware register. [1] "MIPS Architecture for Programmers Volume II-A: The MIPS32 Instruction Set Manual", Imagination Technologies Ltd., Document Number: MD00086, Revision 6.06, December 15, 2016, Section 3.2 "Alphabetical List of Instructions", pp. 332-334 opcodes/ * mips-opc.c (mips_builtin_opcodes): Add RDHWR rt rd sel. gas/ * testsuite/gas/mips/mips.exp: Run hwr-names test. * testsuite/gas/mips/hwr-names.s: Add test cases for RDHWR with the SEL field. * testsuite/gas/mips/mipsr6@hwr-names.d: New file.
2019-04-09 11:30:26 +02:00
2019-04-09 Robert Suchanek <robert.suchanek@mips.com>
* testsuite/gas/mips/mips.exp: Run hwr-names test.
* testsuite/gas/mips/hwr-names.s: Add test cases for RDHWR with
the SEL field.
* testsuite/gas/mips/mipsr6@hwr-names.d: New file.
x86: Define GNU_PROPERTY_X86_ISA_1_AVX512_BF16 Update assembler and readelf to support #define GNU_PROPERTY_X86_ISA_1_AVX512_BF16 (1U << 24) for AVX512_BF16. binutils/ * readelf.c (decode_x86_isa): Handle GNU_PROPERTY_X86_ISA_1_AVX512_BF16. * testsuite/binutils-all/i386/pr21231b.d: Updated. * testsuite/binutils-all/x86-64/pr21231b.d: Likewise. gas/ * config/tc-i386.c (output_insn): Support GNU_PROPERTY_X86_ISA_1_AVX512_BF16. * testsuite/gas/i386/property-2.s: Add AVX512_BF16 test. * testsuite/gas/i386/property-2.d: Updated. * testsuite/gas/i386/x86-64-property-2.d: Likewise. include/ * elf/common.h (GNU_PROPERTY_X86_ISA_1_AVX512_BF16): New.
2019-04-09 02:04:01 +02:00
2019-04-08 H.J. Lu <hongjiu.lu@intel.com>
* config/tc-i386.c (output_insn): Support
GNU_PROPERTY_X86_ISA_1_AVX512_BF16.
* testsuite/gas/i386/property-2.s: Add AVX512_BF16 test.
* testsuite/gas/i386/property-2.d: Updated.
* testsuite/gas/i386/x86-64-property-2.d: Likewise.
x86: Remove i386-*-kaos* and i386-*-chaos targets Remove i386-*-kaos* and i386-*-chaos targets since they are no longer supported by config.sub: $ .../config.sub i386-kaos Invalid configuration `i386-kaos': system `kaos' not recognized $ .../config.sub i386-chaos Invalid configuration `i386-chaos': system `chaos' not recognized $ bfd/ * config.bfd: Remove i[3-7]86-*-kaos* and i[3-7]86-*-chaos targets. gas/ * configure.tgt: Remove i386-*-kaos* and i386-*-chaos targets. * testsuite/gas/i386/i386.exp: Remove *-*-caos* and "*-*-kaos* check. ld/ * Makefile.am (ALL_EMULATION_SOURCES): Remove eelf_i386_chaos.c. (eelf_i386_chaos.c): Removed. * Makefile.in: Regenerated. * configure.tgt: Remove i[3-7]86-*-kaos*. * emulparams/elf_i386_chaos.sh: Removed.
2019-04-08 20:58:51 +02:00
2019-04-08 H.J. Lu <hongjiu.lu@intel.com>
* configure.tgt: Remove i386-*-kaos* and i386-*-chaos targets.
* testsuite/gas/i386/i386.exp: Remove *-*-caos* and "*-*-kaos*
check.
x86: Add assembler -mx86-used-note=yes test Check assembler -mx86-used-note=yes option and readelf -n output. * testsuite/gas/i386/i386.exp: Run -mx86-used-note=yes tests. * testsuite/gas/i386/property-2.d: New file. * testsuite/gas/i386/property-2.s: Likewise. * testsuite/gas/i386/x86-64-property-2.d: Likewise.
2019-04-05 21:41:58 +02:00
2019-04-05 H.J. Lu <hongjiu.lu@intel.com>
* testsuite/gas/i386/i386.exp: Run -mx86-used-note=yes tests.
* testsuite/gas/i386/property-2.d: New file.
* testsuite/gas/i386/property-2.s: Likewise.
* testsuite/gas/i386/x86-64-property-2.d: Likewise.
x86: Support Intel AVX512 BF16 Add assembler and disassembler support Intel AVX512 BF16: https://software.intel.com/en-us/download/intel-architecture-instruction-set-extensions-programming-reference gas/ 2019-04-05 Xuepeng Guo <xuepeng.guo@intel.com> * config/tc-i386.c (cpu_arch): Add .avx512_bf16. (cpu_noarch): Add noavx512_bf16. * doc/c-i386.texi: Document avx512_bf16. * testsuite/gas/i386/avx512_bf16.d: New file. * testsuite/gas/i386/avx512_bf16.s: Likewise. * testsuite/gas/i386/avx512_bf16_vl-inval.l: Likewise. * testsuite/gas/i386/avx512_bf16_vl-inval.s: Likewise. * testsuite/gas/i386/avx512_bf16_vl.d: Likewise. * testsuite/gas/i386/avx512_bf16_vl.s: Likewise. * testsuite/gas/i386/x86-64-avx512_bf16.d: Likewise. * testsuite/gas/i386/x86-64-avx512_bf16.s: Likewise. * testsuite/gas/i386/x86-64-avx512_bf16_vl-inval.l: Likesie. * testsuite/gas/i386/x86-64-avx512_bf16_vl-inval.s: Likewise. * testsuite/gas/i386/x86-64-avx512_bf16_vl.d: Likewise. * testsuite/gas/i386/x86-64-avx512_bf16_vl.s: Likewise. * testsuite/gas/i386/i386.exp: Add BF16 related tests. opcodes/ 2019-04-05 Xuepeng Guo <xuepeng.guo@intel.com> * i386-dis-evex.h (evex_table): Updated to support BF16 instructions. * i386-dis.c (enum): Add EVEX_W_0F3852_P_1, EVEX_W_0F3872_P_1 and EVEX_W_0F3872_P_3. * i386-gen.c (cpu_flag_init): Add CPU_AVX512_BF16_FLAGS. (cpu_flags): Add bitfield for CpuAVX512_BF16. * i386-opc.h (enum): Add CpuAVX512_BF16. (i386_cpu_flags): Add bitfield for cpuavx512_bf16. * i386-opc.tbl: Add AVX512 BF16 instructions. * i386-init.h: Regenerated. * i386-tbl.h: Likewise.
2019-04-05 20:03:01 +02:00
2019-04-05 Xuepeng Guo <xuepeng.guo@intel.com>
* config/tc-i386.c (cpu_arch): Add .avx512_bf16.
(cpu_noarch): Add noavx512_bf16.
* doc/c-i386.texi: Document avx512_bf16.
* testsuite/gas/i386/avx512_bf16.d: New file.
* testsuite/gas/i386/avx512_bf16.s: Likewise.
* testsuite/gas/i386/avx512_bf16_vl-inval.l: Likewise.
* testsuite/gas/i386/avx512_bf16_vl-inval.s: Likewise.
* testsuite/gas/i386/avx512_bf16_vl.d: Likewise.
* testsuite/gas/i386/avx512_bf16_vl.s: Likewise.
* testsuite/gas/i386/x86-64-avx512_bf16.d: Likewise.
* testsuite/gas/i386/x86-64-avx512_bf16.s: Likewise.
* testsuite/gas/i386/x86-64-avx512_bf16_vl-inval.l: Likesie.
* testsuite/gas/i386/x86-64-avx512_bf16_vl-inval.s: Likewise.
* testsuite/gas/i386/x86-64-avx512_bf16_vl.d: Likewise.
* testsuite/gas/i386/x86-64-avx512_bf16_vl.s: Likewise.
* testsuite/gas/i386/i386.exp: Add BF16 related tests.
PowerPC conditional branch test Adds a new test checking conditional branch BO values. * testsuite/gas/ppc/bc.s, * testsuite/gas/ppc/bcat.d, * testsuite/gas/ppc/bcaterr.d, * testsuite/gas/ppc/bcaterr.l, * testsuite/gas/ppc/bcy.d, * testsuite/gas/ppc/bcyerr.d, * testsuite/gas/ppc/bcyerr.l: New tests. * testsuite/gas/ppc/ppc.exp: Run them.
2019-04-04 03:32:31 +02:00
2019-04-05 Alan Modra <amodra@gmail.com>
* testsuite/gas/ppc/bc.s,
* testsuite/gas/ppc/bcat.d,
* testsuite/gas/ppc/bcaterr.d,
* testsuite/gas/ppc/bcaterr.l,
* testsuite/gas/ppc/bcy.d,
* testsuite/gas/ppc/bcyerr.d,
* testsuite/gas/ppc/bcyerr.l: New tests.
* testsuite/gas/ppc/ppc.exp: Run them.
PowerPC disassembler: Don't emit trailing spaces When an instruction has operands, the PowerPC disassembler prints spaces after the opcode so as to line up operands. If the operands are all optional and all default value, then no operands are printed, leaving trailing spaces. This patch fixes that. opcodes/ * ppc-dis.c (print_insn_powerpc): Delay printing spaces after opcode until first operand is output. gas/ * testsuite/gas/ppc/476.d: Remove trailing spaces. * testsuite/gas/ppc/a2.d: Likewise. * testsuite/gas/ppc/booke.d: Likewise. * testsuite/gas/ppc/booke_xcoff.d: Likewise. * testsuite/gas/ppc/e500.d: Likewise. * testsuite/gas/ppc/e500mc.d: Likewise. * testsuite/gas/ppc/e6500.d: Likewise. * testsuite/gas/ppc/htm.d: Likewise. * testsuite/gas/ppc/power6.d: Likewise. * testsuite/gas/ppc/power8.d: Likewise. * testsuite/gas/ppc/power9.d: Likewise. * testsuite/gas/ppc/vle.d: Likewise. ld/ * testsuite/ld-powerpc/tlsexe32.d: Remove trailing spaces. * testsuite/ld-powerpc/tlsopt5.d: Likewise. * testsuite/ld-powerpc/tlsopt5_32.d: Likewise.
2019-04-05 00:50:16 +02:00
2019-04-05 Alan Modra <amodra@gmail.com>
* testsuite/gas/ppc/476.d: Remove trailing spaces.
* testsuite/gas/ppc/a2.d: Likewise.
* testsuite/gas/ppc/booke.d: Likewise.
* testsuite/gas/ppc/booke_xcoff.d: Likewise.
* testsuite/gas/ppc/e500.d: Likewise.
* testsuite/gas/ppc/e500mc.d: Likewise.
* testsuite/gas/ppc/e6500.d: Likewise.
* testsuite/gas/ppc/htm.d: Likewise.
* testsuite/gas/ppc/power6.d: Likewise.
* testsuite/gas/ppc/power8.d: Likewise.
* testsuite/gas/ppc/power9.d: Likewise.
* testsuite/gas/ppc/vle.d: Likewise.
Add extended mnemonics for bctar. Fix setting of 'at' branch hints. opcodes/ PR gas/24349 * ppc-opc.c (valid_bo_pre_v2): Add comments. (valid_bo_post_v2): Add support for 'at' branch hints. (insert_bo): Only error on branch on ctr. (get_bo_hint_mask): New function. (insert_boe): Add new 'branch_taken' formal argument. Add support for inserting 'at' branch hints. (extract_boe): Add new 'branch_taken' formal argument. Add support for extracting 'at' branch hints. (insert_bom, extract_bom, insert_bop, extract_bop): New functions. (BOE): Delete operand. (BOM, BOP): New operands. (RM): Update value. (XLYLK, XLYLK_MASK, XLYBB_MASK): Delete. (powerpc_opcodes) <bc-, bcl-, bca-, bcla-, bclr-, bclrl-, bcctr-, bcctrl-, bctar-, bctarl->: Replace BOE with BOM. (powerpc_opcodes) <bc+, bcl+, bca+, bcla+, bclr+, bclrl+, bcctr+, bcctrl+, bctar+, bctarl+>: Replace BOE with BOP. <bdnztar, bdnztarl, bdztar, bdztarl, btar, btarl, bdnztar-, bdnztarl-, bdnztar+, bdnztarl+, bdztar-, bdztarl-, bdztar+, bdztarl+, bgetar, bnltar, bgetarl, bnltarl, bletar, bngtar, bletarl, bngtarl, bnetar, bnetarl, bnstar, bnutar, bnstarl, bnutarl, bgetar-, bnltar-, bgetarl-, bnltarl-, bletar-, bngtar-, bletarl-, bngtarl-, bnetar-, bnetarl-, bnstar-, bnutar-, bnstarl-, bnutarl-, bgetar+, bnltar+, bgetarl+, bnltarl+, bletar+, bngtar+, bletarl+, bngtarl+, bnetar+, bnetarl+, bnstar+, bnutar+, bnstarl+, bnutarl+, blttar, blttarl, bgttar, bgttarl, beqtar, beqtarl, bsotar, buntar, bsotarl, buntarl, blttar-, blttarl-, bgttar-, bgttarl-, beqtar-, beqtarl-, bsotar-, buntar-, bsotarl-, buntarl-, blttar+, blttarl+, bgttar+, bgttarl+, beqtar+, beqtarl+, bsotar+, buntar+, bsotarl+, buntarl+, bdnzftar, bdnzftarl, bdzftar, bdzftarl, bftar, bftarl, bftar-, bftarl-, bftar+, bftarl+, bdnzttar, bdnzttarl, bdzttar, bdzttarl, bttar, bttarl, bttar-, bttarl-, bttar+, bttarl+>: New extended mnemonics. gas/ PR gas/24349 * testsuite/gas/ppc/power8.s: (bdnztar, bdnztarl, bdztar, bdztarl, btar, btarl, bdnztar-, bdnztarl-, bdnztar+, bdnztarl+, bdztar-, bdztarl-, bdztar+, bdztarl+, bgetar, bnltar, bgetarl, bnltarl, bletar, bngtar, bletarl, bngtarl, bnetar, bnetarl, bnstar, bnutar, bnstarl, bnutarl, bgetar-, bnltar-, bgetarl-, bnltarl-, bletar-, bngtar-, bletarl-, bngtarl-, bnetar-, bnetarl-, bnstar-, bnutar-, bnstarl-, bnutarl-, bgetar+, bnltar+, bgetarl+, bnltarl+, bletar+, bngtar+, bletarl+, bngtarl+, bnetar+, bnetarl+, bnstar+, bnutar+, bnstarl+, bnutarl+, blttar, blttarl, bgttar, bgttarl, beqtar, beqtarl, bsotar, buntar, bsotarl, buntarl, blttar-, blttarl-, bgttar-, bgttarl-, beqtar-, beqtarl-, bsotar-, buntar-, bsotarl-, buntarl-, blttar+, blttarl+, bgttar+, bgttarl+, beqtar+, beqtarl+, bsotar+, buntar+, bsotarl+, buntarl+, bdnzftar, bdnzftarl, bdzftar, bdzftarl, bftar, bftarl, bftar-, bftarl-, bftar+, bftarl+, bdnzttar, bdnzttarl, bdzttar, bdzttarl, bttar, bttarl, bttar-, bttarl-, bttar+, bttarl+): Add tests of extended mnemonics. * testsuite/gas/ppc/power8.d: Likewise. Update previous bctar tests to expect new extended mnemonics. * testsuite/gas/ppc/a2.s: <bc, bc-, bc+, bcl, bcl-, bcl+>: Update test to not use illegal BO value. Use a more convenient BI value. * testsuite/gas/ppc/a2.d: Update tests for new expect output.
2019-04-04 16:00:29 +02:00
2019-04-04 Peter Bergner <bergner@linux.ibm.com>
PR gas/24349
* testsuite/gas/ppc/power8.s: (bdnztar, bdnztarl, bdztar, bdztarl,
btar, btarl, bdnztar-, bdnztarl-, bdnztar+, bdnztarl+, bdztar-,
bdztarl-, bdztar+, bdztarl+, bgetar, bnltar, bgetarl, bnltarl,
bletar, bngtar, bletarl, bngtarl, bnetar, bnetarl, bnstar, bnutar,
bnstarl, bnutarl, bgetar-, bnltar-, bgetarl-, bnltarl-, bletar-,
bngtar-, bletarl-, bngtarl-, bnetar-, bnetarl-, bnstar-, bnutar-,
bnstarl-, bnutarl-, bgetar+, bnltar+, bgetarl+, bnltarl+, bletar+,
bngtar+, bletarl+, bngtarl+, bnetar+, bnetarl+, bnstar+, bnutar+,
bnstarl+, bnutarl+, blttar, blttarl, bgttar, bgttarl, beqtar,
beqtarl, bsotar, buntar, bsotarl, buntarl, blttar-, blttarl-,
bgttar-, bgttarl-, beqtar-, beqtarl-, bsotar-, buntar-, bsotarl-,
buntarl-, blttar+, blttarl+, bgttar+, bgttarl+, beqtar+, beqtarl+,
bsotar+, buntar+, bsotarl+, buntarl+, bdnzftar, bdnzftarl, bdzftar,
bdzftarl, bftar, bftarl, bftar-, bftarl-, bftar+, bftarl+, bdnzttar,
bdnzttarl, bdzttar, bdzttarl, bttar, bttarl, bttar-, bttarl-, bttar+,
bttarl+): Add tests of extended mnemonics.
* testsuite/gas/ppc/power8.d: Likewise. Update previous bctar tests
to expect new extended mnemonics.
* testsuite/gas/ppc/a2.s: <bc, bc-, bc+, bcl, bcl-, bcl+>: Update test
to not use illegal BO value. Use a more convenient BI value.
* testsuite/gas/ppc/a2.d: Update tests for new expect output.
gas: use literals/const16 for xtensa loop relaxation Loop opcode relaxation that uses addi/addmi doesn't work well with other relaxations that may cause code movement. Instead of encoding fixed loop end offset in the relaxed sequence use l32r or a pair of const16 to load loop end address. This way the address of the loop end gets a relocation record and it gets updated appropriately. gas/ 2019-04-03 Max Filippov <jcmvbkbc@gmail.com> * config/tc-xtensa.c (convert_frag_immed): Drop convert_frag_immed_finish_loop invocation. (convert_frag_immed_finish_loop): Drop declaration and definition. * config/xtensa-relax.c (widen_spec_list): Replace loop widening that uses addi/addmi with widening that uses l32r and const16.
2019-04-02 23:32:42 +02:00
2019-04-03 Max Filippov <jcmvbkbc@gmail.com>
* config/tc-xtensa.c (convert_frag_immed): Drop
convert_frag_immed_finish_loop invocation.
(convert_frag_immed_finish_loop): Drop declaration and
definition.
* config/xtensa-relax.c (widen_spec_list): Replace loop
widening that uses addi/addmi with widening that uses l32r
and const16.
[GAS, Arm] CLI with architecture sensitive extensions This patch adds a new framework to add architecture sensitive extensions, like GCC does. This patch also implements all architecture extensions currently available in GCC. This framework works as follows. To enable architecture sensitive extensions for a particular architecture, that architecture must contain an ARM_ARCH_OPT2 entry in the 'arm_archs' table. All fields here are the same as previous, with the addition of a new extra field at the end to <name> it's extension table. This <name>, corresponds to a <name>_ext_table of type 'struct arm_ext_table'. This struct can be filled with three types of entries: ARM_ADD (string <ext>, arm_feature_set <enable_bits>), which means +<ext> will enable <enable_bits> ARM_REMOVE (string <ext>, arm_feature_set <disable_bits>), which means +no<ext> will disable <disable_bits> ARM_EXT (string <ext>, arm_feature_set <enable_bits>, arm_feature_set <disable_bits>), which means +<ext> will enable <enable_bits> and +no<ext> will disable <disable_bits> (this is to be used instead of adding an ARM_ADD and ARM_REMOVE for the same <ext>) This patch does not disable the use of the old extensions, even if some of them are duplicated in the new tables. This is a "in-between-step" as we may want to deprecate the old table of extensions in later patches. For now, GAS will first look for the +<ext> or +no<ext> in the new table and if no entry is found it will continue searching in the old table, following old behaviour. If only an ARM_ADD or an ARM_REMOVE is defined for <ext> and +no<ext> or +<ext> resp. is used then it also continues to search the old table for it. A couple of caveats: - This patch does not enable the use of these architecture extensions with the '.arch_extension' directive. This is future work that I will tend to later. - This patch does not enable the use of these architecture extensions with the -mcpu option. This is future work that I will tend to later. - This patch does not change the current behaviour when combining an architecture extension and using -mfpu on the command-line. The current behaviour of GAS is to stage the union of feature bits enabled by both -march and -mfpu. GCC behaves differently here, so this is something we may want to revisit on a later date.
2019-04-01 11:43:32 +02:00
2019-04-01 Andre Vieira <andre.simoesdiasvieira@arm.com>
* config/tc-arm.c (arm_ext_table): New struct type.
(arm_arch_option_table): Add new 'arm_ext_table' field.
(ARM_EXT,ARM_ADD,ARM_REMOVE, ALL_FP): New macros.
(armv5te_ext_table, armv7ve_ext_table, armv7a_ext_table,
armv7r_ext_table, armv7em_ext_table, armv8a_ext_table,
armv81a_ext_table, armv82a_ext_table, armv84a_ext_table,
armv85a_ext_table, armv8m_main_ext_table,
armv8r_ext_table): New architecture extension tables.
(ARM_ARCH_OPT): Add new default field.
(ARM_ARCH_OPT2): New macro.
(arm_archs): Extend some architectures with the new architecture
extension tables mentioned above.
(arm_extensions): Add DEPRECATED comment with instructions to
use new table.
(arm_parse_extension): Change to use new extension tables.
(arm_parse_cpu): Don't change existing behavior.
(arm_parse_arch): Change to use new extension tables.
* doc/c-arm.texi: Document new architecture extensions.
* testsuite/gas/arm/attr-mfpu-neon-fp16.d: Change test to use new
extension option rather than -mfpu and change expected behaviour to
sane outputs.
* testsuite/gas/arm/armv8-2-fp16-scalar-bad-ext.d: New.
* testsuite/gas/arm/armv8-2-fp16-scalar-ext.d: New.
* testsuite/gas/arm/armv8-2-fp16-scalar-thumb-ext.d: New.
* testsuite/gas/arm/armv8-2-fp16-simd-ext.d: New.
* testsuite/gas/arm/armv8-2-fp16-simd-thumb-ext.d: New.
* testsuite/gas/arm/armv8-2-fp16-simd-warning-ext.d: New.
* testsuite/gas/arm/armv8-2-fp16-simd-warning-thumb-ext.d: New.
* testsuite/gas/arm/armv8_2+rdma-ext.d: New.
* testsuite/gas/arm/armv8_2-a-fp16-thumb2-ext.d: New.
* testsuite/gas/arm/armv8_2-a-fp16_ext.d: New.
* testsuite/gas/arm/armv8_3-a-fp-bad-ext.d: New.
* testsuite/gas/arm/armv8_3-a-fp-ext.d: New.
* testsuite/gas/arm/armv8_3-a-fp16-ext.d: New.
* testsuite/gas/arm/armv8_3-a-simd-bad-ext.d: New.
* testsuite/gas/arm/armv8_4-a-fp16-ext.d: New.
* testsuite/gas/arm/armv8m.main+fp.d: New.
* testsuite/gas/arm/armv8m.main+fp.dp.d: New.
* testsuite/gas/arm/attr-ext-fpv5-d16.d: New.
* testsuite/gas/arm/attr-ext-fpv5.d: New.
* testsuite/gas/arm/attr-ext-idiv.d: New.
* testsuite/gas/arm/attr-ext-mp.d: New.
* testsuite/gas/arm/attr-ext-neon-fp16.d: New.
* testsuite/gas/arm/attr-ext-neon-vfpv3.d: New.
* testsuite/gas/arm/attr-ext-neon-vfpv4.d: New.
* testsuite/gas/arm/attr-ext-sec.d: New.
* testsuite/gas/arm/attr-ext-vfpv3-d16-fp16.d: New.
* testsuite/gas/arm/attr-ext-vfpv3-d16.d: New.
* testsuite/gas/arm/attr-ext-vfpv3-fp16.d: New.
* testsuite/gas/arm/attr-ext-vfpv3.d: New.
* testsuite/gas/arm/attr-ext-vfpv3xd-fp.d: New.
* testsuite/gas/arm/attr-ext-vfpv3xd.d: New.
* testsuite/gas/arm/attr-ext-vfpv4-d16.d: New.
* testsuite/gas/arm/attr-ext-vfpv4-sp-d16.d: New.
* testsuite/gas/arm/attr-ext-vfpv4.d: New.
* testsuite/gas/arm/dotprod-mandatory-ext.d: New.
* testsuite/gas/arm/fpv5-d16.s: New.
* testsuite/gas/arm/fpv5-sp-d16.s: New.
PR24390, Don't decode mtfsb field as a cr field "mtfsb0 4*cr7+lt" doesn't make all that much sense, but unfortunately glibc uses just that instead of "mtfsb0 28" to clear the fpscr xe bit. So for backwards compatibility accept cr field expressions when assembling mtfsb operands, but disassemble to a plain number. PR 24390 include/ * opcode/ppc.h (PPC_OPERAND_CR_REG): Comment. opcodes/ * ppc-opc.c (BTF): Define. (powerpc_opcodes): Use for mtfsb*. * ppc-dis.c (print_insn_powerpc): Print fields with both PPC_OPERAND_CR_REG and PPC_OPERAND_CR_BIT as a plain number. gas/ * testsuite/gas/ppc/476.d: Update mtfsb*. * testsuite/gas/ppc/a2.d: Likewise.
2019-03-28 01:06:55 +01:00
2019-03-28 Alan Modra <amodra@gmail.com>
PR 24390
* testsuite/gas/ppc/476.d: Update mtfsb*.
* testsuite/gas/ppc/a2.d: Likewise.
Remove strip_underscore from struct emulation This field is unused. I would have liked to also remove leading_underscore and fake_label_name but in an i386-elf/coff/aout multi-obj setup those fields are used to select a different fake_label_name for aout. * emul.h (struct emulation): Delete strip_underscore. * emul-target.h (emul_strip_underscore): Don't define. (emul_struct_name): Update initialization.
2019-03-20 09:05:16 +01:00
2019-03-21 Alan Modra <amodra@gmail.com>
* emul.h (struct emulation): Delete strip_underscore.
* emul-target.h (emul_strip_underscore): Don't define.
(emul_struct_name): Update initialization.
Teach a few targets to resolve BFD_RELOC_8 and tidy "forward" test. I've removed some checks in d30v md_apply_fix that have no business being there. Any symbol problems will be caught later in tc_gen_reloc, and overflow checking is done in gas/write.c. * config/tc-d10v.c (md_apply_fix): Apply BFD_RELOC_8. * config/tc-pdp11.c (md_apply_fix): Likewise. * config/tc-d30v.c (md_apply_fix): Don't emit errors for BFD_RELOC_8, BFD_RELOC_16, and BFD_RELOC_64. * testsuite/gas/all/gas.exp: Move target exclusions for forward test, but not cr16, to.. * testsuite/gas/all/forward.d: ..here, with explanation. Remove d10v, d30v, and pdp11 xfails.
2019-03-19 23:50:55 +01:00
2019-03-21 Alan Modra <amodra@gmail.com>
* config/tc-d10v.c (md_apply_fix): Apply BFD_RELOC_8.
* config/tc-pdp11.c (md_apply_fix): Likewise.
* config/tc-d30v.c (md_apply_fix): Don't emit errors for BFD_RELOC_8,
BFD_RELOC_16, and BFD_RELOC_64.
* testsuite/gas/all/gas.exp: Move target exclusions for forward
test, but not cr16, to..
* testsuite/gas/all/forward.d: ..here, with explanation. Remove
d10v, d30v, and pdp11 xfails.
x86: Correct EVEX vector load/store optimization Update EVEX vector load/store optimization: 1. There is no need to check AVX since AVX2 is required for AVX512F. 2. We need to check both operands for ZMM register since AT&T syntax may not set zmmword on the first operand. 3. Update Opcode_SIMD_IntD check and set. 4. Since the VEX prefix has 2 or 3 bytes, the EVEX prefix has 4 bytes, EVEX Disp8 has 1 byte and VEX Disp32 has 4 bytes, we choose EVEX Disp8 over VEX Disp32. * config/tc-i386.c (optimize_encoding): Don't check AVX for EVEX vector load/store optimization. Check both operands for ZMM register. Update EVEX vector load/store opcode check. Choose EVEX Disp8 over VEX Disp32. * testsuite/gas/i386/optimize-1.d: Updated. * testsuite/gas/i386/optimize-1a.d: Likewise. * testsuite/gas/i386/optimize-2.d: Likewise. * testsuite/gas/i386/optimize-4.d: Likewise. * testsuite/gas/i386/optimize-5.d: Likewise. * testsuite/gas/i386/x86-64-optimize-2.d: Likewise. * testsuite/gas/i386/x86-64-optimize-2a.d: Likewise. * testsuite/gas/i386/x86-64-optimize-2b.d: Likewise. * testsuite/gas/i386/x86-64-optimize-3.d: Likewise. * testsuite/gas/i386/x86-64-optimize-5.d: Likewise. * testsuite/gas/i386/x86-64-optimize-6.d: Likewise. * testsuite/gas/i386/optimize-1.s: Add ZMM register load test. * testsuite/gas/i386/x86-64-optimize-2.s: Likewise.
2019-03-19 14:12:47 +01:00
2019-03-19 H.J. Lu <hongjiu.lu@intel.com>
* config/tc-i386.c (optimize_encoding): Don't check AVX for
EVEX vector load/store optimization. Check both operands for
ZMM register. Update EVEX vector load/store opcode check.
Choose EVEX Disp8 over VEX Disp32.
* testsuite/gas/i386/optimize-1.d: Updated.
* testsuite/gas/i386/optimize-1a.d: Likewise.
* testsuite/gas/i386/optimize-2.d: Likewise.
* testsuite/gas/i386/optimize-4.d: Likewise.
* testsuite/gas/i386/optimize-5.d: Likewise.
* testsuite/gas/i386/x86-64-optimize-2.d: Likewise.
* testsuite/gas/i386/x86-64-optimize-2a.d: Likewise.
* testsuite/gas/i386/x86-64-optimize-2b.d: Likewise.
* testsuite/gas/i386/x86-64-optimize-3.d: Likewise.
* testsuite/gas/i386/x86-64-optimize-5.d: Likewise.
* testsuite/gas/i386/x86-64-optimize-6.d: Likewise.
* testsuite/gas/i386/optimize-1.s: Add ZMM register load
test.
* testsuite/gas/i386/x86-64-optimize-2.s: Likewise.
x86: Correct EVEX to 128-bit EVEX optimization Since not all AVX512F processors support AVX512VL, we can optimize 512-bit EVEX to 128-bit EVEX encoding for upper 16 vector registers only when AVX512VL is enabled explicitly at command-line or via ".arch .avx512vl" directive. PR gas/24352 * config/tc-i386.c (optimize_encoding): Check only cpu_arch_flags.bitfield.cpuavx512vl. * testsuite/gas/i386/i386.exp: Run x86-64-optimize-2b. * testsuite/gas/i386/x86-64-optimize-2.d: Revert the last change. * testsuite/gas/i386/x86-64-optimize-2b.d: New file. * testsuite/gas/i386/x86-64-optimize-2b.s: Likewise.
2019-03-19 14:10:21 +01:00
2019-03-19 H.J. Lu <hongjiu.lu@intel.com>
PR gas/24352
* config/tc-i386.c (optimize_encoding): Check only
cpu_arch_flags.bitfield.cpuavx512vl.
* testsuite/gas/i386/i386.exp: Run x86-64-optimize-2b.
* testsuite/gas/i386/x86-64-optimize-2.d: Revert the last
change.
* testsuite/gas/i386/x86-64-optimize-2b.d: New file.
* testsuite/gas/i386/x86-64-optimize-2b.s: Likewise.
ix86: Disable AVX512F when disabling AVX2 Since AVX2 is required for AVX512F, we should disable AVX512F when AVX2 is disabled. gas/ PR gas/24359 * testsuite/gas/i386/i386.exp: Change optimize-6a, optimize-7, x86-64-optimize-7a and x86-64-optimize-8 tests to run_list_test. Remove optimize-6c and x86-64-optimize-7c tests. * testsuite/gas/i386/noavx-3.l: Updated. * testsuite/gas/i386/noavx-4.d: Likewise. * testsuite/gas/i386/noavx-5.d: Likewise. * testsuite/gas/i386/noavx-3.s: Add AVX512F tests. * testsuite/gas/i386/noavx-4.s: Remove AVX512F tests. * testsuite/gas/i386/nosse-5.s: Likewise. * testsuite/gas/i386/optimize-6a.d: Removed. * testsuite/gas/i386/optimize-6c.d: Likewise. * testsuite/gas/i386/optimize-7.d: Likewise. * testsuite/gas/i386/x86-64-optimize-7a.d: Likewise. * testsuite/gas/i386/x86-64-optimize-7c.d: Likewise. * testsuite/gas/i386/x86-64-optimize-8.d: Likewise. * testsuite/gas/i386/optimize-6a.l: New file. * testsuite/gas/i386/optimize-6a.s: Likewise. * testsuite/gas/i386/optimize-7.l: Likewise. * testsuite/gas/i386/x86-64-optimize-7a.l: Likewise. * testsuite/gas/i386/x86-64-optimize-7a.s: Likewise. * testsuite/gas/i386/x86-64-optimize-8.l: Likewise. opcodes/ PR gas/24359 * i386-gen.c (cpu_flag_init): Add CPU_ANY_AVX512F_FLAGS to CPU_ANY_AVX2_FLAGS. * i386-init.h: Regenerated.
2019-03-19 14:08:15 +01:00
2019-03-19 H.J. Lu <hongjiu.lu@intel.com>
PR gas/24359
* testsuite/gas/i386/i386.exp: Change optimize-6a, optimize-7,
x86-64-optimize-7a and x86-64-optimize-8 tests to run_list_test.
Remove optimize-6c and x86-64-optimize-7c tests.
* testsuite/gas/i386/noavx-3.l: Updated.
* testsuite/gas/i386/noavx-4.d: Likewise.
* testsuite/gas/i386/noavx-5.d: Likewise.
* testsuite/gas/i386/noavx-3.s: Add AVX512F tests.
* testsuite/gas/i386/noavx-4.s: Remove AVX512F tests.
* testsuite/gas/i386/nosse-5.s: Likewise.
* testsuite/gas/i386/optimize-6a.d: Removed.
* testsuite/gas/i386/optimize-6c.d: Likewise.
* testsuite/gas/i386/optimize-7.d: Likewise.
* testsuite/gas/i386/x86-64-optimize-7a.d: Likewise.
* testsuite/gas/i386/x86-64-optimize-7c.d: Likewise.
* testsuite/gas/i386/x86-64-optimize-8.d: Likewise.
* testsuite/gas/i386/optimize-6a.l: New file.
* testsuite/gas/i386/optimize-6a.s: Likewise.
* testsuite/gas/i386/optimize-7.l: Likewise.
* testsuite/gas/i386/x86-64-optimize-7a.l: Likewise.
* testsuite/gas/i386/x86-64-optimize-7a.s: Likewise.
* testsuite/gas/i386/x86-64-optimize-8.l: Likewise.
Fix MRI mode testsuite failures These fails were introduced by git commit 2469b3c584 with the inroduction of "input_from_string": m68k-linux FAIL: MRI structured for m68k-linux FAIL: MRI structured if m68k-linux FAIL: MRI structured repeat m68k-linux FAIL: MRI structured while Since the m68k parser called expression() without setting input_from_string, get_symbol_name rejected FAKE_LABEL_CHAR in names. * config/m68k-parse.y (yylex): Use temp_ilp and restore_ilp.
2019-03-18 12:46:24 +01:00
2019-03-18 Alan Modra <amodra@gmail.com>
* config/m68k-parse.y (yylex): Use temp_ilp and restore_ilp.
Use temp_ilp and restore_ilp in more places * as.c (macro_expr): Use temp_ilp and restore_ilp. * macro.c (buffer_and_nest): Likewise. * read.c (temp_ilp): Remove FIXME.
2019-03-18 13:04:36 +01:00
* as.c (macro_expr): Likewise.
* macro.c (buffer_and_nest): Likewise.
* read.c (temp_ilp): Remove FIXME.
Fix MRI mode testsuite failures These fails were introduced by git commit 2469b3c584 with the inroduction of "input_from_string": m68k-linux FAIL: MRI structured for m68k-linux FAIL: MRI structured if m68k-linux FAIL: MRI structured repeat m68k-linux FAIL: MRI structured while Since the m68k parser called expression() without setting input_from_string, get_symbol_name rejected FAKE_LABEL_CHAR in names. * config/m68k-parse.y (yylex): Use temp_ilp and restore_ilp.
2019-03-18 12:46:24 +01:00
x86: Pass -O0 to assembler for some tests * testsuite/gas/i386/att-regs.d: Pass -O0 to assembler. * testsuite/gas/i386/avx512bw-intel.d: Likewise. * testsuite/gas/i386/avx512bw.d: Likewise. * testsuite/gas/i386/avx512f-intel.d: Likewise. * testsuite/gas/i386/avx512f.d: Likewise. * testsuite/gas/i386/disp32.d: Likewise. * testsuite/gas/i386/intel-regs.d: Likewise. * testsuite/gas/i386/pseudos.d: Likewise. * testsuite/gas/i386/x86-64-disp32.d: Likewise. * testsuite/gas/i386/x86-64-pseudos.d: Likewise.
2019-03-18 02:19:45 +01:00
2019-03-18 H.J. Lu <hongjiu.lu@intel.com>
* testsuite/gas/i386/att-regs.d: Pass -O0 to assembler.
* testsuite/gas/i386/avx512bw-intel.d: Likewise.
* testsuite/gas/i386/avx512bw.d: Likewise.
* testsuite/gas/i386/avx512f-intel.d: Likewise.
* testsuite/gas/i386/avx512f.d: Likewise.
* testsuite/gas/i386/disp32.d: Likewise.
* testsuite/gas/i386/intel-regs.d: Likewise.
* testsuite/gas/i386/pseudos.d: Likewise.
* testsuite/gas/i386/x86-64-disp32.d: Likewise.
* testsuite/gas/i386/x86-64-pseudos.d: Likewise.
x86: Optimize EVEX vector load/store instructions When there is no write mask, we can encode lower 16 128-bit/256-bit EVEX vector register load and store instructions as VEX vector register load and store instructions with -O1. gas/ PR gas/24348 * config/tc-i386.c (optimize_encoding): Encode 128-bit and 256-bit EVEX vector register load/store instructions as VEX vector register load/store instructions for -O1. * doc/c-i386.texi: Update -O1 documentation. * testsuite/gas/i386/i386.exp: Run PR gas/24348 tests. * testsuite/gas/i386/optimize-1.s: Add tests for EVEX vector load/store instructions. * testsuite/gas/i386/optimize-2.s: Likewise. * testsuite/gas/i386/optimize-3.s: Likewise. * testsuite/gas/i386/optimize-5.s: Likewise. * testsuite/gas/i386/x86-64-optimize-2.s: Likewise. * testsuite/gas/i386/x86-64-optimize-3.s: Likewise. * testsuite/gas/i386/x86-64-optimize-4.s: Likewise. * testsuite/gas/i386/x86-64-optimize-5.s: Likewise. * testsuite/gas/i386/x86-64-optimize-6.s: Likewise. * testsuite/gas/i386/optimize-1.d: Updated. * testsuite/gas/i386/optimize-2.d: Likewise. * testsuite/gas/i386/optimize-3.d: Likewise. * testsuite/gas/i386/optimize-4.d: Likewise. * testsuite/gas/i386/optimize-5.d: Likewise. * testsuite/gas/i386/x86-64-optimize-2.d: Likewise. * testsuite/gas/i386/x86-64-optimize-3.d: Likewise. * testsuite/gas/i386/x86-64-optimize-4.d: Likewise. * testsuite/gas/i386/x86-64-optimize-5.d: Likewise. * testsuite/gas/i386/x86-64-optimize-6.d: Likewise. * testsuite/gas/i386/optimize-7.d: New file. * testsuite/gas/i386/optimize-7.s: Likewise. * testsuite/gas/i386/x86-64-optimize-8.d: Likewise. * testsuite/gas/i386/x86-64-optimize-8.s: Likewise. opcodes/ PR gas/24348 * i386-opc.tbl: Add Optimize to vmovdqa32, vmovdqa64, vmovdqu8, vmovdqu16, vmovdqu32 and vmovdqu64. * i386-tbl.h: Regenerated.
2019-03-18 01:56:10 +01:00
2019-03-18 H.J. Lu <hongjiu.lu@intel.com>
PR gas/24348
* config/tc-i386.c (optimize_encoding): Encode 128-bit and
256-bit EVEX vector register load/store instructions as VEX
vector register load/store instructions for -O1.
* doc/c-i386.texi: Update -O1 documentation.
* testsuite/gas/i386/i386.exp: Run PR gas/24348 tests.
* testsuite/gas/i386/optimize-1.s: Add tests for EVEX vector
load/store instructions.
* testsuite/gas/i386/optimize-2.s: Likewise.
* testsuite/gas/i386/optimize-3.s: Likewise.
* testsuite/gas/i386/optimize-5.s: Likewise.
* testsuite/gas/i386/x86-64-optimize-2.s: Likewise.
* testsuite/gas/i386/x86-64-optimize-3.s: Likewise.
* testsuite/gas/i386/x86-64-optimize-4.s: Likewise.
* testsuite/gas/i386/x86-64-optimize-5.s: Likewise.
* testsuite/gas/i386/x86-64-optimize-6.s: Likewise.
* testsuite/gas/i386/optimize-1.d: Updated.
* testsuite/gas/i386/optimize-2.d: Likewise.
* testsuite/gas/i386/optimize-3.d: Likewise.
* testsuite/gas/i386/optimize-4.d: Likewise.
* testsuite/gas/i386/optimize-5.d: Likewise.
* testsuite/gas/i386/x86-64-optimize-2.d: Likewise.
* testsuite/gas/i386/x86-64-optimize-3.d: Likewise.
* testsuite/gas/i386/x86-64-optimize-4.d: Likewise.
* testsuite/gas/i386/x86-64-optimize-5.d: Likewise.
* testsuite/gas/i386/x86-64-optimize-6.d: Likewise.
* testsuite/gas/i386/optimize-7.d: New file.
* testsuite/gas/i386/optimize-7.s: Likewise.
* testsuite/gas/i386/x86-64-optimize-8.d: Likewise.
* testsuite/gas/i386/x86-64-optimize-8.s: Likewise.
x86: Encode 256-bit/512-bit VEX/EVEX insns with 128-bit VEX Since all AVX512 processors support AVX, we can encode 256-bit/512-bit VEX/EVEX vector register clearing instructions with 128-bit VEX vector register clearing instructions at -O1. * config/tc-i386.c (optimize_encoding): Encode 256-bit/512-bit VEX/EVEX vector register clearing instructions with 128-bit VEX vector register clearing instructions at -O1. * doc/c-i386.texi: Update -O1 and -O2 documentation. * testsuite/gas/i386/i386.exp: Run optimize-1a and x86-64-optimize-2a. * testsuite/gas/i386/optimize-1a.d: New file. * testsuite/gas/i386/x86-64-optimize-2a.d: Likewise.
2019-03-17 20:50:45 +01:00
2019-03-18 H.J. Lu <hongjiu.lu@intel.com>
* config/tc-i386.c (optimize_encoding): Encode 256-bit/512-bit
VEX/EVEX vector register clearing instructions with 128-bit VEX
vector register clearing instructions at -O1.
* doc/c-i386.texi: Update -O1 and -O2 documentation.
* testsuite/gas/i386/i386.exp: Run optimize-1a and
x86-64-optimize-2a.
* testsuite/gas/i386/optimize-1a.d: New file.
* testsuite/gas/i386/x86-64-optimize-2a.d: Likewise.
x86: Set optimize to INT_MAX for -Os Set optimize to INT_MAX, instead of -1, for -Os so that -Os will include -O2 optimization. PR gas/24353 * config/tc-i386.c (md_parse_option): Set optimize to INT_MAX for -Os. * testsuite/gas/i386/optimize-2.s: Add a test. * testsuite/gas/i386/x86-64-optimize-3.s: Likewise. * testsuite/gas/i386/optimize-2.d: Updated. * testsuite/gas/i386/x86-64-optimize-3.d: Likewise.
2019-03-17 00:39:18 +01:00
2019-03-17 H.J. Lu <hongjiu.lu@intel.com>
PR gas/24353
* config/tc-i386.c: Include <limits.h> if it exists and try
including <sys/param.h> if we have it.
(INT_MAX): Define if not defined.
(md_parse_option): Set optimize to INT_MAX for -Os.
* testsuite/gas/i386/optimize-2.s: Add a test.
* testsuite/gas/i386/x86-64-optimize-3.s: Likewise.
* testsuite/gas/i386/optimize-2.d: Updated.
* testsuite/gas/i386/x86-64-optimize-3.d: Likewise.
x86: Correctly optimize EVEX to 128-bit VEX/EVEX We can optimize 512-bit EVEX to 128-bit EVEX encoding for upper 16 vector registers only when AVX512VL is enabled. We can't optimize EVEX to 128-bit VEX encoding when AVX isn't enabled. PR gas/24352 * config/tc-i386.c (optimize_encoding): Encode 512-bit EVEX with 128-bit VEX encoding only when AVX is enabled and with 128-bit EVEX encoding only when AVX512VL is enabled. * testsuite/gas/i386/i386.exp: Run PR gas/24352 tests. * testsuite/gas/i386/optimize-6.s: New file. * testsuite/gas/i386/optimize-6a.d: Likewise. * testsuite/gas/i386/optimize-6b.d: Likewise. * testsuite/gas/i386/optimize-6c.d: Likewise. * testsuite/gas/i386/x86-64-optimize-7.s: Likewise. * testsuite/gas/i386/x86-64-optimize-7a.d: Likewise. * testsuite/gas/i386/x86-64-optimize-7b.d: Likewise. * testsuite/gas/i386/x86-64-optimize-7c.d: Likewise. * testsuite/gas/i386/x86-64-optimize-2.d: Updated.
2019-03-17 00:25:08 +01:00
2019-03-17 H.J. Lu <hongjiu.lu@intel.com>
PR gas/24352
* config/tc-i386.c (optimize_encoding): Encode 512-bit EVEX
with 128-bit VEX encoding only when AVX is enabled and with
128-bit EVEX encoding only when AVX512VL is enabled.
* testsuite/gas/i386/i386.exp: Run PR gas/24352 tests.
* testsuite/gas/i386/optimize-6.s: New file.
* testsuite/gas/i386/optimize-6a.d: Likewise.
* testsuite/gas/i386/optimize-6b.d: Likewise.
* testsuite/gas/i386/optimize-6c.d: Likewise.
* testsuite/gas/i386/x86-64-optimize-7.s: Likewise.
* testsuite/gas/i386/x86-64-optimize-7a.d: Likewise.
* testsuite/gas/i386/x86-64-optimize-7b.d: Likewise.
* testsuite/gas/i386/x86-64-optimize-7c.d: Likewise.
* testsuite/gas/i386/x86-64-optimize-2.d: Updated.
Fix a potential illegal memory access whilt parsing an x86 insn. PR 24308 * config/tc-i386.c (parse_insn): Check mnemp before using it to determine if a suffix can be trimmed.
2019-03-15 12:58:05 +01:00
2019-03-15 Li Hao <li.hao296@zte.com.cn>
PR 24308
* config/tc-i386.c (parse_insn): Check mnemp before using it to
determine if a suffix can be trimmed.
dwarf2: Align relocation within .debug_line section All relocations specify a byte address. As dwarf debug information is organized in octets, some relocations may not be aligned. While it might be possible to define special relocations that operate at an octet offset from their address, it's easier to ensure the relocations are aligned by padding with "nop" statements. In most dwarf sections this requirement is already fulfilled, only relocations for symbol address within the .debug_line section can be misaligned. * dwarf2dbg.c (out_set_addr): Align relocation within .debug_line.
2019-03-10 19:21:58 +01:00
2019-03-13 Christian Eggers <ceggers@gmx.de>
* dwarf2dbg.c (out_set_addr): Align relocation within .debug_line.
dwarf2: Pad size of .debug_line section. As all dwarf debug information is organized in octets, the size of all dwarf sections must be aligned to OCTETS_PER_BYTE. Most DWARF sections meet this requirement, only the .debug_line section can reach an arbitrary octet size. In order to align the size to a multiple of OCTETS_PER_BYTE, the section is padded with "nop" statements at the end. * dwarf2dbg.c (out_debug_line): Pad size of .debug_line section.
2019-03-10 19:21:57 +01:00
2019-03-13 Christian Eggers <ceggers@gmx.de>
* dwarf2dbg.c (out_debug_line): Pad size of .debug_line section.
dwarf2: Use octets for .debug_string offsets Like other dwarf2 offsets, also the string offsets in the .debug_info section which points into the .debug_str section must be expressed in octets instead of bytes. * dwarf2dbg.c (out_debug_str): Use octets for .debug_string pointers.
2019-03-10 19:21:56 +01:00
2019-03-13 Christian Eggers <ceggers@gmx.de>
* dwarf2dbg.c (out_debug_str): Use octets for .debug_string pointers.
dwarf2: Use octets for .debug_line prologue Like the u32 size field at the beginning of the section, also the prologue size must be expressed in octets. * dwarf2dbg.c (out_debug_line): Use octets for .debug_line prologue.
2019-03-10 19:21:55 +01:00
2019-03-13 Christian Eggers <ceggers@gmx.de>
* dwarf2dbg.c (out_debug_line): Use octets for .debug_line prologue.
dwarf2: Use octets for dwarf2 headers The content of the dwarf2 sections .debug_line, .debug_aranges and .debug_info starts with an u32 containing the the size of the remaining data. According to the dwarf2 specification this value must be expressed in octets instead of bytes. * dwarf2dbg.c (out_debug_line): Use octets for dwarf2 headers. (out_debug_aranges, out_debug_info): Likewise.
2019-03-10 19:21:54 +01:00
2019-03-13 Christian Eggers <ceggers@gmx.de>
* dwarf2dbg.c (out_debug_line): Use octets for dwarf2 headers.
(out_debug_aranges, out_debug_info): Likewise.
Symbols with octets value Up to now, all symbol values are in units of bytes, where a "byte" can consist of one or more octets (e.g. 8 bit or 16 bit). Allow to specfiy that the "unit" of a newly created symbol is octets (exactly 8 bit), instead of bytes. * symbols.h (symbol_temp_new_now_octets): Declare. (symbol_set_value_now_octets, symbol_octets_p): Declare. * symbols.c (struct symbol_flags): New member sy_octets. (symbol_temp_new_now_octets): New function. (resolve_symbol_value): Return octets instead of bytes if sy_octets is set. (symbol_set_value_now_octets): New function. (symbol_octets_p): New function.
2019-03-10 19:21:53 +01:00
2019-03-13 Christian Eggers <ceggers@gmx.de>
* symbols.h (symbol_temp_new_now_octets): Declare.
(symbol_set_value_now_octets, symbol_octets_p): Declare.
* symbols.c (struct symbol_flags): New member sy_octets.
(symbol_temp_new_now_octets): New function.
(resolve_symbol_value): Return octets instead of bytes if
sy_octets is set.
(symbol_set_value_now_octets): New function.
(symbol_octets_p): New function.
dwarf2: Fix calculation of line info offset The units of the value returned by "frag_now_fix()" and "size" do not match. "frag_now_fix()" returns bytes (can be 8, 16 or 32 bit), while "size" is octets (exactly 8 bit). * dwarf2dbg.c (dwarf2_emit_insn): Fix calculation of line info offset.
2019-03-10 19:21:52 +01:00
2019-03-13 Christian Eggers <ceggers@gmx.de>
* dwarf2dbg.c (dwarf2_emit_insn): Fix calculation of line info offset.
Add missing changelogs for previous commits.
2019-03-12 14:23:10 +01:00
2019-03-12 Andreas Krebbel <krebbel@linux.ibm.com>
* testsuite/gas/s390/zarch-arch13.s: Adjust testcase to optable changes.
* testsuite/gas/s390/zarch-arch13.d: Likewise.
Testsuite: Allow multiple lines of "as" in testsuite. Committed on behalf of Matthew Malcomson. This allows checking the command line parsing more easily than before by allowing many command line invokations from the same .d file. Each line is used as a set of flags, and the tests are ran against the output of the assembler with each set. Each line of assembler is treated as another set of tests (as if the test file were copied to another with a different #as: line). This patch includes some example uses where multiple testcases can be merged into one file using this new functionality. binutils/ChangeLog: * testsuite/lib/binutils-common.exp: Allow multiple "as" lines. gas/ChangeLog: * testsuite/gas/aarch64/dotproduct.d: Use multiple "as" lines. * testsuite/gas/aarch64/dotproduct_armv8_4.d: Remove. * testsuite/gas/aarch64/dotproduct_armv8_4.s: Remove. * testsuite/gas/aarch64/illegal-dotproduct.d: Use multiple "as" lines. * testsuite/gas/aarch64/ldst-rcpc-armv8_2.d: Remove. * testsuite/gas/aarch64/ldst-rcpc.d: Use multiple "as" lines.
2019-02-27 14:15:10 +01:00
2019-02-27 Matthew Malcomson <matthew.malcomson@arm.com>
* testsuite/gas/aarch64/dotproduct.d: Use multiple "as" lines.
* testsuite/gas/aarch64/dotproduct_armv8_4.d: Remove.
* testsuite/gas/aarch64/dotproduct_armv8_4.s: Remove.
* testsuite/gas/aarch64/illegal-dotproduct.d: Use multiple "as"
lines.
* testsuite/gas/aarch64/ldst-rcpc-armv8_2.d: Remove.
* testsuite/gas/aarch64/ldst-rcpc.d: Use multiple "as" lines.
Re: PowerPC __tls_get_addr arg parsing Fixes non-ELF powerpc build failure: tc-ppc.c:3009:1: error: ‘parse_tls_arg’ defined but not used * config/tc-ppc.c (parse_tls_arg): Wrap in #ifdef OBJ_ELF.
2019-02-24 08:31:08 +01:00
2019-02-24 Alan Modra <amodra@gmail.com>
* config/tc-ppc.c (parse_tls_arg): Wrap in #ifdef OBJ_ELF.
PR24144, pdp11-ld overwriting section data with zeros bfd/ PR 24144 * pdp11.c (set_section_contents): Revert 2015-02-24 change. gas/ PR 24144 * config/obj-aout.c (obj_aout_frob_file_before_fix): Write to end of section to ensure file contents cover aligned section size.
2019-02-24 07:14:48 +01:00
2019-02-24 Alan Modra <amodra@gmail.com>
PR 24144
* config/obj-aout.c (obj_aout_frob_file_before_fix): Write to end
of section to ensure file contents cover aligned section size.
[arm][gas] Add support for Neoverse N1 This adds support for the Neoverse N1 CPU [1] to gas. This was previously enabled under the Ares codename, which remains as a valid option for -mcpu for compatibility reasons. make check-gas passes on arm-none-eabi. [1] https://community.arm.com/processors/b/blog/posts/arm-neoverse-n1-platform-accelerating-the-transformation-to-a-scalable-cloud-to-edge-infrastructure 2019-02-21 Kyrylo Tkachov <kyrylo.tkachov@arm.com> * config/tc-arm.c (arm_cpus): Add neoverse-n1. * doc/c-arm.texi (-mcpu): Document neoverse-n1 value.
2019-02-22 10:59:05 +01:00
2019-02-22 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
* config/tc-arm.c (arm_cpus): Add neoverse-n1.
* doc/c-arm.texi (-mcpu): Document neoverse-n1 value.
[AArch64][gas] Add support for Neoverse E1 This adds support for the Neoverse E1 CPU [1] to gas. make check-gas passes on aarch64-none-elf. [1] https://community.arm.com/processors/b/blog/posts/arm-neoverse-e1-platform-empowering-the-infrastructure-to-meet-next-generation-throughput-demands 2019-02-21 Kyrylo Tkachov <kyrylo.tkachov@arm.com> * config/tc-aarch64.c (aarch64_cpus): Add neoverse-e1. * doc/c-aarch64.texi (-mcpu): Document neoverse-e1 value.
2019-02-22 10:57:45 +01:00
2019-02-22 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
* config/tc-aarch64.c (aarch64_cpus): Add neoverse-e1.
* doc/c-aarch64.texi (-mcpu): Document neoverse-e1 value.
[AArch64][gas] Add support for Neoverse N1 This adds support for the Neoverse N1 [1] CPU to gas. This was previously enabled under the Ares codename, which remains as a valid option for -mcpu for compatibility reasons. make check-gas passes on aarch64-none-elf. [1] https://community.arm.com/processors/b/blog/posts/arm-neoverse-n1-platform-accelerating-the-transformation-to-a-scalable-cloud-to-edge-infrastructure 2019-02-21 Kyrylo Tkachov <kyrylo.tkachov@arm.com> * config/tc-aarch64.c (aarch64_cpus): Add neoverse-n1. * doc/c-aarch64.texi (-mcpu): Document neoverse-n1 value.
2019-02-22 10:56:50 +01:00
2019-02-22 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
* config/tc-aarch64.c (aarch64_cpus): Add neoverse-n1.
* doc/c-aarch64.texi (-mcpu): Document neoverse-n1 value.
Fix a potential deadlock in some older Loongson 3A1000 MIPS processors. * NEWS: Mention -m[no-]fix-loongson3-llsc. * configure.ac: Add --enable-mips-fix-loongson3-llsc. Define DEFAULT_MIPS_FIX_LOONGSON3_LLSC. * config.in: Regenerated. * configure: Likewise. * config/tc-mips.c (sync_insn, mips_fix_loongson3_llsc): New variables. (options): New OPTION_FIX_LOONGSON3_LLSC, OPTION_NO_FIX_LOONGSON3_LLSC. (md_longopts): Add -m[no-]fix-loongson3-llsc. (md_begin): Initialize sync insn. (fix_loongson3_llsc): New. (append_insn): Call fix_loongson3_llsc. (md_parse_option): Handle OPTION_FIX_LOONGSON3_LLSC, OPTION_NO_FIX_LOONGSON3_LLSC. (md_show_usage): Display -m[no-]fix-loongson3-llsc. * doc/c-mips.texi: Document -m[no-]fix-loongson3-llsc, --enable-mips-fix-loongson3-llsc=[yes|no].
2019-02-19 18:57:16 +01:00
2019-02-19 Paul Hua <paul.hua.gm@gmail.com>
* NEWS: Mention -m[no-]fix-loongson3-llsc.
* configure.ac: Add --enable-mips-fix-loongson3-llsc.
Define DEFAULT_MIPS_FIX_LOONGSON3_LLSC.
* config.in: Regenerated.
* configure: Likewise.
* config/tc-mips.c (sync_insn, mips_fix_loongson3_llsc):
New variables.
(options): New OPTION_FIX_LOONGSON3_LLSC,
OPTION_NO_FIX_LOONGSON3_LLSC.
(md_longopts): Add -m[no-]fix-loongson3-llsc.
(md_begin): Initialize sync insn.
(fix_loongson3_llsc): New.
(append_insn): Call fix_loongson3_llsc.
(md_parse_option): Handle OPTION_FIX_LOONGSON3_LLSC,
OPTION_NO_FIX_LOONGSON3_LLSC.
(md_show_usage): Display -m[no-]fix-loongson3-llsc.
* doc/c-mips.texi: Document -m[no-]fix-loongson3-llsc,
--enable-mips-fix-loongson3-llsc=[yes|no].
gas: Pass max_bytes to TC_FRAG_INIT ommit 3ae729d5a4f63740ed9a778960b17c2912b0bbdd Author: H.J. Lu <hjl.tools@gmail.com> Date: Wed Mar 7 04:18:45 2018 -0800 x86: Rewrite NOP generation for fill and alignment increased MAX_MEM_FOR_RS_ALIGN_CODE to 4095 which resulted in increase of assembler time and memory usage by 5 times for inputs with many .p2align directives, which is typical for LTO output. This patch passes max_bytes to TC_FRAG_INIT so that MAX_MEM_FOR_RS_ALIGN_CODE can be set as needed and tracked by backend it so that HANDLE_ALIGN can check the maximum alignment for each rs_align_code frag. Wall time to assemble the same cc1plus.s: before: 423.78user 0.89system 7:05.71elapsed 99%CPU after: 102.35user 0.27system 1:42.89elapsed 99%CPU PR gas/24165 * frags.c (frag_var_init): Pass max_chars to TC_FRAG_INIT as max_bytes. * config/tc-aarch64.h (TC_FRAG_INIT): Add and pass max_bytes to aarch64_init_frag. * /config/tc-arm.h (TC_FRAG_INIT): And and pass max_bytes to arm_init_frag. * config/tc-avr.h (TC_FRAG_INIT): And and ignore max_bytes. * config/tc-ia64.h (TC_FRAG_INIT): Likewise. * config/tc-mmix.h (TC_FRAG_INIT): Likewise. * config/tc-nds32.h (TC_FRAG_INIT): Likewise. * config/tc-ns32k.h (TC_FRAG_INIT): Likewise. * config/tc-rl78.h (TC_FRAG_INIT): Likewise. * config/tc-rx.h (TC_FRAG_INIT): Likewise. * config/tc-score.h (TC_FRAG_INIT): Likewise. * config/tc-tic54x.h (TC_FRAG_INIT): Likewise. * config/tc-tic6x.h (TC_FRAG_INIT): Likewise. * config/tc-xtensa.h (TC_FRAG_INIT): Likewise. * config/tc-i386.h (MAX_MEM_FOR_RS_ALIGN_CODE): Set to (alignment ? ((1 << alignment) - 1) : 1) (i386_tc_frag_data): Add max_bytes. (TC_FRAG_INIT): Add and track max_bytes. (HANDLE_ALIGN): Replace MAX_MEM_FOR_RS_ALIGN_CODE with fragP->tc_frag_data.max_bytes. * doc/internals.texi: Update TC_FRAG_TYPE with max_bytes.
2019-02-10 13:34:10 +01:00
2019-02-10 H.J. Lu <hongjiu.lu@intel.com>
PR gas/24165
* frags.c (frag_var_init): Pass max_chars to TC_FRAG_INIT as
max_bytes.
* config/tc-aarch64.h (TC_FRAG_INIT): Add and pass max_bytes to
aarch64_init_frag.
* /config/tc-arm.h (TC_FRAG_INIT): And and pass max_bytes to
arm_init_frag.
* config/tc-avr.h (TC_FRAG_INIT): And and ignore max_bytes.
* config/tc-ia64.h (TC_FRAG_INIT): Likewise.
* config/tc-mmix.h (TC_FRAG_INIT): Likewise.
* config/tc-nds32.h (TC_FRAG_INIT): Likewise.
* config/tc-ns32k.h (TC_FRAG_INIT): Likewise.
* config/tc-rl78.h (TC_FRAG_INIT): Likewise.
* config/tc-rx.h (TC_FRAG_INIT): Likewise.
* config/tc-score.h (TC_FRAG_INIT): Likewise.
* config/tc-tic54x.h (TC_FRAG_INIT): Likewise.
* config/tc-tic6x.h (TC_FRAG_INIT): Likewise.
* config/tc-xtensa.h (TC_FRAG_INIT): Likewise.
* config/tc-i386.h (MAX_MEM_FOR_RS_ALIGN_CODE): Set to
(alignment ? ((1 << alignment) - 1) : 1)
(i386_tc_frag_data): Add max_bytes.
(TC_FRAG_INIT): Add and track max_bytes.
(HANDLE_ALIGN): Replace MAX_MEM_FOR_RS_ALIGN_CODE with
fragP->tc_frag_data.max_bytes.
* doc/internals.texi: Update TC_FRAG_TYPE with max_bytes.
Add missing ChangeLog files for previous patch.
2019-02-08 22:21:52 +01:00
2019-02-08 Jim Wilson <jimw@sifive.com>
* config/tc-riscv.c (validate_riscv_insn) <'C'>: Add 'z' support.
(riscv_ip) <'C'>: Add 'z' support.
Arm: Backport hlt to all architectures. The software trap instruction HLT that was introduced in Armv8-a is used as the semihosting trap instruction in AArch64. In order to allow systems configured to run AArch64 code to also run AArch32 with semihosting it was decided that AArch32 should also use HLT in the case of the "mixed mode" environment. This requires that HLT also be backported to all earlier architectures. The instruction is in the undefined encoding space earlier architectures but must trigger a semihosting trap [3]. The Arm Architectural Reference Manual [1] doesn't explicitly mention this however this is an explicit requirement in the Semihosting-v2 protocol [2]. [1] https://developer.arm.com/docs/ddi0487/latest/arm-architecture-reference-manual-armv8-for-armv8-a-architecture-profile [2] https://developer.arm.com/docs/100863/latest/the-semihosting-interface [3] https://github.com/qemu/qemu/commit/19a6e31c9d2701ef648b70ddcfc3bf64cec8c37e gas/ChangeLog: * config/tc-arm.c (insns): Redefine THUMB_VARIANT and ARM_VARIANT for hlt to armv1. * testsuite/gas/arm/armv8a-automatic-hlt.d: Update TAGs * testsuite/gas/arm/hlt.d: New test. * testsuite/gas/arm/hlt.s: New test. opcodes/ChangeLog: * arm-dis.c (arm_opcodes): Redefine hlt to armv1.
2019-02-07 18:12:23 +01:00
2019-02-07 Tamar Christina <tamar.christina@arm.com>
* config/tc-arm.c (insns): Redefine THUMB_VARIANT and ARM_VARIANT for
hlt to armv1.
* testsuite/gas/arm/armv8a-automatic-hlt.d: Update TAGs
* testsuite/gas/arm/hlt.d: New test.
* testsuite/gas/arm/hlt.s: New test.
AArch64: Add negative tests for Armv8.3-a complex number instructions instructions. This patch just adds a few negative tests for the Armv8.3-a complex instructions. These already do the right disassembly without needing a verifier, but adding some tests to make sure that stays that way. gas/ChangeLog: * testsuite/gas/aarch64/undefined_advsimd_armv8_3.d: New test. * testsuite/gas/aarch64/undefined_advsimd_armv8_3.s: New test.
2019-02-07 17:58:29 +01:00
2019-02-07 Tamar Christina <tamar.christina@arm.com>
* testsuite/gas/aarch64/undefined_advsimd_armv8_3.d: New test.
* testsuite/gas/aarch64/undefined_advsimd_armv8_3.s: New test.
AArch64: Add verifier for By elem Single and Double sized instructions. The AArch64 instruction set has cut-outs inside instructions encodings for when a given encoding that would normally fall within the encoding space of an instruction is instead undefined. This updates the first few instructions FMLA, FMLA, FMUL and FMULX in the case where sz:L == 11. gas/ChangeLog: PR binutils/23212 * testsuite/gas/aarch64/undefined_by_elem_sz_l.s: New test. * testsuite/gas/aarch64/undefined_by_elem_sz_l.d: New test. opcodes/ChangeLog: PR binutils/23212 * aarch64-opc.h (enum aarch64_field_kind): Add FLD_sz. * aarch64-opc.c (verify_elem_sd): New. (fields): Add FLD_sz entr. * aarch64-tbl.h (_SIMD_INSN): New. (aarch64_opcode_table): Add elem_sd verifier to fmla, fmls, fmul and fmulx scalar and vector by element isns.
2019-02-07 17:55:23 +01:00
2019-02-07 Tamar Christina <tamar.christina@arm.com>
PR binutils/23212
* testsuite/gas/aarch64/undefined_by_elem_sz_l.s: New test.
* testsuite/gas/aarch64/undefined_by_elem_sz_l.d: New test.
Visium: align branch absolute instruction for the GR6 This is done in order to avoid a pipeline hazard on the GR6. gas/ * config/tc-visium.c (md_assemble) <mode_cad>: Align instruction on 64-bit boundaries for the GR6. * testsuite/gas/visium/allinsn_gr6.s: Tweak. * testsuite/gas/visium/allinsn_gr6.d: Likewise. * testsuite/gas/visium/bra-1.d: New test. * testsuite/gas/visium/bra-1.s: Likewise. * testsuite/gas/visium/visium.exp: Run bra-1 test.
2019-02-07 16:58:47 +01:00
2019-02-07 Eric Botcazou <ebotcazou@adacore.com>
* config/tc-visium.c (md_assemble) <mode_cad>: Align instruction on
64-bit boundaries for the GR6.
* testsuite/gas/visium/allinsn_gr6.s: Tweak.
* testsuite/gas/visium/allinsn_gr6.d: Likewise.
* testsuite/gas/visium/bra-1.d: New test.
* testsuite/gas/visium/bra-1.s: Likewise.
* testsuite/gas/visium/visium.exp: Run bra-1 test.
S12Z: GAS: Allow #_symbol operands as mov source mov.l, mov.p and mov.w (but not mov.b) when called with an immediate source operand should be accepted a relocatable expression. This change makes that possible. gas/ * config/tc-s12z.c (lex_imm): Add new argument exp_o. (emit_reloc): New function. (md_apply_fix): [BFD_RELOC_S12Z_OPR] Recognise that it can be either 2 bytes or 3 bytes long. * testsuite/gas/s12z/mov-imm-reloc.d: New file. * testsuite/gas/s12z/mov-imm-reloc.s: New file. * testsuite/gas/s12z/s12z.exp: Add them.
2019-02-01 17:42:54 +01:00
2019-01-31 John Darrington <john@darrington.wattle.id.au>
* config/tc-s12z.c (lex_imm): Add new argument exp_o.
(emit_reloc): New function.
(md_apply_fix): [BFD_RELOC_S12Z_OPR] Recognise that it
can be either 2 bytes or 3 bytes long.
* testsuite/gas/s12z/mov-imm-reloc.d: New file.
* testsuite/gas/s12z/mov-imm-reloc.s: New file.
* testsuite/gas/s12z/s12z.exp: Add them.
S12Z: GAS: Fix incorrect range test for 16-bit PC relative offsets. The limits for PC relative offsets were incorrect. This change fixes them and adds some tests. gas/ * config/tc-s12z.c (md_apply_fix): Fix incorrect limits. * testsuite/gas/s12z/pc-rel-bad.d: New file. * testsuite/gas/s12z/pc-rel-bad.l: New file. * testsuite/gas/s12z/pc-rel-bad.s: New file. * testsuite/gas/s12z/pc-rel-good.d: New file. * testsuite/gas/s12z/pc-rel-good.s: New file. * testsuite/gas/s12z/s12z.exp: Add them.
2019-02-01 17:42:54 +01:00
2019-01-31 John Darrington <john@darrington.wattle.id.au>
* config/tc-s12z.c (md_apply_fix): Fix incorrect limits.
* testsuite/gas/s12z/pc-rel-bad.d: New file.
* testsuite/gas/s12z/pc-rel-bad.l: New file.
* testsuite/gas/s12z/pc-rel-bad.s: New file.
* testsuite/gas/s12z/pc-rel-good.d: New file.
* testsuite/gas/s12z/pc-rel-good.s: New file.
* testsuite/gas/s12z/s12z.exp: Add them.
S12Z: GAS: Issue warning if TFR/EXG have identical source and destination. It is permissible for the source and destination operands of TFR and EXG to be the same register. However it is a pointless instruction and anyone writing it has probably made a mistake. This change emits a warning if such an instruction is encountered. gas/ * config/tc-s12z.c (tfr): Emit warning if operands are the same. * testsuite/gas/s12z/exg.d: New test case. * testsuite/gas/s12z/exg.l: New file.
2019-02-01 17:42:54 +01:00
2019-01-31 John Darrington <john@darrington.wattle.id.au>
* config/tc-s12z.c (tfr): Emit warning if operands are the same.
* testsuite/gas/s12z/exg.d: New test case.
* testsuite/gas/s12z/exg.l: New file.
S12Z: GAS: Disallow immediate destination operands The assembler permitted instructions which attempted to assign to an immediate operand. Bizarrely there is a valid machine code for such operations (although the documentation says it's "inappropriate"). This change causes such attempts to fail with an error message. gas/ * config/tc-s12z.c (lex_opr): Add a parameter to indicate whether immediate mode operands should be permitted. * testsuite/s12z/imm-dest.d: New file. * testsuite/s12z/imm-dest.l: New file. * testsuite/s12z/imm-dest.s: New file. * testsuite/s12z/s12z.exp: Add them.
2019-02-01 17:42:54 +01:00
2019-01-31 John Darrington <john@darrington.wattle.id.au>
* config/tc-s12z.c (lex_opr): Add a parameter to indicate whether
immediate mode operands should be permitted.
* testsuite/s12z/imm-dest.d: New file.
* testsuite/s12z/imm-dest.l: New file.
* testsuite/s12z/imm-dest.s: New file.
* testsuite/s12z/s12z.exp: Add them.
S/390: Implement instruction set extensions opcodes/ChangeLog: 2019-01-31 Andreas Krebbel <krebbel@linux.ibm.com> * s390-mkopc.c (main): Accept arch13 as cpu string. * s390-opc.c: Add new instruction formats and instruction opcode masks. * s390-opc.txt: Add new arch13 instructions. include/ChangeLog: 2019-01-31 Andreas Krebbel <krebbel@linux.ibm.com> * opcode/s390.h (enum s390_opcode_cpu_val): Add S390_OPCODE_ARCH13. gas/ChangeLog: 2019-01-31 Andreas Krebbel <krebbel@linux.ibm.com> * config/tc-s390.c (s390_parse_cpu): New entry for arch13. * doc/c-s390.texi: Document arch13 march option. * testsuite/gas/s390/s390.exp: Run the arch13 related tests. * testsuite/gas/s390/zarch-arch13.d: New test. * testsuite/gas/s390/zarch-arch13.s: New test. * testsuite/gas/s390/zarch-z13.d: Expect the renamed mnemonics also for z13.
2019-01-31 17:01:27 +01:00
2019-01-31 Andreas Krebbel <krebbel@linux.ibm.com>
* config/tc-s390.c (s390_parse_cpu): New entry for arch13.
* doc/c-s390.texi: Document arch13 march option.
* testsuite/gas/s390/s390.exp: Run the arch13 related tests.
* testsuite/gas/s390/zarch-arch13.d: New test.
* testsuite/gas/s390/zarch-arch13.s: New test.
* testsuite/gas/s390/zarch-z13.d: Expect the renamed mnemonics
also for z13.
Assorted warning fixes gcc-9 flagged warnings at the places I'm patching here, all real bugs. * config/tc-alpha.c (md_apply_fix): Correct range checks for BFD_RELOC_ALPHA_NOP, BFD_RELOC_ALPHA_LDA, BFD_RELOC_ALPHA_BSR. * config/tc-arm.c (md_apply_fix): Use llabs rather than abs. * config/tc-csky.c (get_macro_reg_vals): Pass s to csky_show_error.
2019-01-31 05:08:45 +01:00
2019-01-31 Alan Modra <amodra@gmail.com>
* config/tc-alpha.c (md_apply_fix): Correct range checks for
BFD_RELOC_ALPHA_NOP, BFD_RELOC_ALPHA_LDA, BFD_RELOC_ALPHA_BSR.
* config/tc-arm.c (md_apply_fix): Use llabs rather than abs.
* config/tc-csky.c (get_macro_reg_vals): Pass s to csky_show_error.
xtensa: gas: don't keep relocations for constants xtensa gas chokes on 8/16 bit data entries representing constant symbols because it leaves BFD_RELOC_8/BFD_RELOC_16 fixups for which xtensa BFD cannot emit relocations. Resolve fixups for constant symbols in md_apply_fix. gas/ 2019-01-28 Max Filippov <jcmvbkbc@gmail.com> * config/tc-xtensa.c (md_apply_fix): Mark fixups for constant symbols as done in md_apply_fix. * testsuite/gas/all/forward.d: Don't XFAIL for xtensa.
2019-01-26 03:52:32 +01:00
2019-01-28 Max Filippov <jcmvbkbc@gmail.com>
* config/tc-xtensa.c (md_apply_fix): Mark fixups for constant
symbols as done in md_apply_fix.
* testsuite/gas/all/forward.d: Don't XFAIL for xtensa.
Updated Russian and French translations for the gas sub-directory
2019-01-28 16:21:58 +01:00
2019-01-28 Nick Clifton <nickc@redhat.com>
* po/fr.po: Updated French translation.
* po/ru.po: Updated Russian translation.
Control gas enable-checking default by bfd/development.sh * configure.ac (ac_checking): Set from bfd/development.sh development variable. * configure: Regenerate.
2019-01-28 00:03:28 +01:00
2019-01-28 Alan Modra <amodra@gmail.com>
* configure.ac (ac_checking): Set from bfd/development.sh
development variable.
* configure: Regenerate.
AArch64: Add missing changelog for Update encodings for stg, st2g, stzg and st2zg
2019-01-25 16:50:01 +01:00
2019-01-25 Sudakshina Das <sudi.das@arm.com>
* config/tc-aarch64.c (warn_unpredictable_ldst): Exempt
stg, st2g, stzg and stz2g from Xt == Xn with writeback warning.
* testsuite/gas/aarch64/armv8_5-a-memtag.d: Change tests for
stg, stzg, st2g and stz2g.
* testsuite/gas/aarch64/armv8_5-a-memtag.s: Likewise.
* testsuite/gas/aarch64/illegal-memtag.l: Likewise.
* testsuite/gas/aarch64/illegal-memtag.s: Likewise.
AArch64: Add new STZGM instruction for Armv8.5-A Memory Tagging Extension. This patch is part of a series of patches to introduce a few changes to the Armv8.5-A Memory Tagging Extension. This patch adds the new STZGM instruction. STGZM Xt, [<Xn|SP>] Committed on behalf of Sudakshina Das. *** gas/ChangeLog *** * testsuite/gas/aarch64/armv8_5-a-memtag.d: New tests for stzgm. * testsuite/gas/aarch64/armv8_5-a-memtag.s: Likewise. * testsuite/gas/aarch64/illegal-memtag.l: Likewise. * testsuite/gas/aarch64/illegal-memtag.s: Likewise. *** opcodes/ChangeLog *** * aarch64-asm-2.c: Regenerated. * aarch64-dis-2.c: Likewise. * aarch64-opc-2.c: Likewise. * aarch64-tbl.h (aarch64_opcode): Add new stzgm.
2019-01-25 15:15:45 +01:00
2019-01-25 Sudakshina Das <sudi.das@arm.com>
* testsuite/gas/aarch64/armv8_5-a-memtag.d: New tests for stzgm.
* testsuite/gas/aarch64/armv8_5-a-memtag.s: Likewise.
* testsuite/gas/aarch64/illegal-memtag.l: Likewise.
* testsuite/gas/aarch64/illegal-memtag.s: Likewise.
AArch64: Remove ldgv and stgv instructions from Armv8.5-A Memory Tagging Extension. This patch is part of a series of patches to introduce a few changes to the Armv8.5-A Memory Tagging Extension. This patch removes the LDGV and STGV instructions. These instructions needed special infrastructure to support [base]! style for addressing mode. That is also removed now. Committed on behalf of Sudakshina Das. *** gas/ChangeLog *** * config/tc-aarch64.c (parse_address_main): Remove support for [base]! address expression. (parse_operands): Remove support for AARCH64_OPND_ADDR_SIMPLE_2. (warn_unpredictable_ldst): Remove support for ldstgv_indexed. * testsuite/gas/aarch64/armv8_5-a-memtag.d: Remove tests for ldgv and stgv. * testsuite/gas/aarch64/armv8_5-a-memtag.s: Likewise. * testsuite/gas/aarch64/illegal-memtag.l: Likewise. * testsuite/gas/aarch64/illegal-memtag.s: Likewise. *** include/ChangeLog *** * opcode/aarch64.h (enum aarch64_opnd): Remove AARCH64_OPND_ADDR_SIMPLE_2. (enum aarch64_insn_class): Remove ldstgv_indexed. *** opcodes/ChangeLog *** * aarch64-asm.c (aarch64_ins_addr_simple_2): Remove. * aarch64-asm.h (ins_addr_simple_2): Likeiwse. * aarch64-dis.c (aarch64_ext_addr_simple_2): Likewise. * aarch64-dis.h (ext_addr_simple_2): Likewise. * aarch64-opc.c (operand_general_constraint_met_p): Remove case for ldstgv_indexed. (aarch64_print_operand): Remove case for AARCH64_OPND_ADDR_SIMPLE_2. * aarch64-tbl.h (struct aarch64_opcode): Remove ldgv and stgv. (AARCH64_OPERANDS): Remove ADDR_SIMPLE_2. * aarch64-asm-2.c: Regenerated. * aarch64-dis-2.c: Regenerated. * aarch64-opc-2.c: Regenerated.
2019-01-25 14:57:14 +01:00
2019-01-25 Sudakshina Das <sudi.das@arm.com>
Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
* config/tc-aarch64.c (parse_address_main): Remove support for
[base]! address expression.
(parse_operands): Remove support for AARCH64_OPND_ADDR_SIMPLE_2.
(warn_unpredictable_ldst): Remove support for ldstgv_indexed.
* testsuite/gas/aarch64/armv8_5-a-memtag.d: Remove tests for ldgv
and stgv.
* testsuite/gas/aarch64/armv8_5-a-memtag.s: Likewise.
* testsuite/gas/aarch64/illegal-memtag.l: Likewise.
* testsuite/gas/aarch64/illegal-memtag.s: Likewise.
PR23940, check bounds before using PR gas/23940 * macro.c (getstring): Check array bound before accessing.
2019-01-25 04:11:47 +01:00
2019-01-25 Wu Heng <wu.heng@zte.com.cn>
PR gas/23940
* macro.c (getstring): Check array bound before accessing.
PR24125, Assertion failure with embedded NULs in string An assertion that can be triggered by user input is wrong, so remove it. I believe the NUL would have been accepted before the PR20902 patch. PR 20902 PR 24125 * read.c (stringer): Delete assertion.
2019-01-25 00:04:14 +01:00
2019-01-25 Alan Modra <amodra@gmail.com>
PR 20902
PR 24125
* read.c (stringer): Delete assertion.
Updated translations for various binutils subdirectories.
2019-01-21 13:59:20 +01:00
2019-01-21 Nick Clifton <nickc@redhat.com>
* po/uk.po: Updated Ukranian translation.
Change version to 2.32.51 and regenerate configure and pot files.
2019-01-19 17:51:42 +01:00
2019-01-19 Nick Clifton <nickc@redhat.com>
* config.in: Regenerate.
* configure: Regenerate.
* po/gas.pot: Regenerate.
Add markers for 2.32 branch to NEWS and ChangeLog files.
2019-01-19 16:55:50 +01:00
2018-06-24 Nick Clifton <nickc@redhat.com>
2.32 branch created.
Arm: Clean up PE GAS testsuite correct THUMB tests. The PE targets don't support mapping symbols and so the disassembler is unable to correctly output thumb instructions when the input was thumb. So for testcases that only have thumb output, I have copied them and skipped the ones for which auto-detection is supposed to work on PE, and added a new one that will force thumb output. This so that the tests still check the mapping symbols. For the tests that switch between thumb and arm in one file I just skip them entirely on PE targets. This cleans up the PE GAS testsuite. gas/ * testsuite/gas/arm/archv6t2-1-pe.d: New test. * testsuite/gas/arm/archv6t2-1.d: Skip pe. * testsuite/gas/arm/csdb.d: Skip pe. * testsuite/gas/arm/sb-thumb1-pe.d: New test. * testsuite/gas/arm/sb-thumb1.d: Skip pe. * testsuite/gas/arm/sb-thumb2-pe.d: New test. * testsuite/gas/arm/sb-thumb2.d: Skip pe. * testsuite/gas/arm/udf.d: Skip pe.
2019-01-17 17:05:37 +01:00
2019-01-17 Tamar Christina <tamar.christina@arm.com>
* testsuite/gas/arm/archv6t2-1-pe.d: New test.
* testsuite/gas/arm/archv6t2-1.d: Skip pe.
* testsuite/gas/arm/csdb.d: Skip pe.
* testsuite/gas/arm/sb-thumb1-pe.d: New test.
* testsuite/gas/arm/sb-thumb1.d: Skip pe.
* testsuite/gas/arm/sb-thumb2-pe.d: New test.
* testsuite/gas/arm/sb-thumb2.d: Skip pe.
* testsuite/gas/arm/udf.d: Skip pe.
Don't emit vendor attribute section if there is no attribute to emit. 2019-01-16 Kito Cheng <kito@andestech.com> bfd/ * elf-attrs.c (vendor_obj_attr_size): Return 0 if size is 0 even for OBJ_ATTR_PROC. gas/ * testsuite/gas/riscv/attribute-empty.d: New.
2019-01-16 22:37:35 +01:00
2019-01-16 Kito Cheng <kito@andestech.com>
* testsuite/gas/riscv/attribute-empty.d: New.
RISC-V: Support ELF attribute for gas and readelf. 2019-01-16 Kito Cheng <kito@andestech.com> Nelson Chu <nelson@andestech.com> bfd/ * elfnn-riscv.c (riscv_elf_obj_attrs_arg_type): New. (elf_backend_obj_attrs_vendor): Define. (elf_backend_obj_attrs_section_type): Likewise. (elf_backend_obj_attrs_section): Likewise. (elf_backend_obj_attrs_arg_type): Define as riscv_elf_obj_attrs_arg_type. * elfxx-riscv.c (riscv_estimate_digit): New. (riscv_estimate_arch_strlen1): Likewise. (riscv_estimate_arch_strlen): Likewise. (riscv_arch_str1): Likewise. (riscv_arch_str): Likewise. * elfxx-riscv.h (riscv_arch_str): Declare. binutils/ * readelf.c (get_riscv_section_type_name): New function. (get_section_type_name): Add handler for RISC-V. (riscv_attr_tag_t): Declare. (riscv_attr_tag): New. (display_riscv_attribute): New function. (process_attributes): Add handler for RISC-V. * testsuite/binutils-all/strip-3.d: Remove .riscv.attribute section. gas/ * config/tc-riscv.c (DEFAULT_RISCV_ATTR): Define to 0 if not defined. (riscv_set_options): Add `arch_attr` field. (riscv_opts): Set default value for arch_attr. (riscv_write_out_arch_attr): New. (riscv_set_public_attributes): Likewise. (riscv_md_end): Likewise. (riscv_convert_symbolic_attribute): Likewise. (s_riscv_attribute): Likewise. (explicit_arch_attr): Likewise. (riscv_pseudo_table): Add .attribute to the table. (options): Add OPTION_ARCH_ATTR and OPTION_NO_ARCH_ATTR enumeration constants. (md_longopts): Add `march-attr' and `mno-arch-attr' options. (md_parse_option): Handle the new options. (md_show_usage): Document the `march-attr' option. * config/tc-riscv.h (md_end): Define as riscv_md_end (riscv_md_end): Declare. (CONVERT_SYMBOLIC_ATTRIBUTE): Define as riscv_convert_symbolic_attribute. (riscv_convert_symbolic_attribute): Declare. (start_assemble): Declare. * testsuite/gas/elf/elf.exp: Adjust test case for section2.e. * testsuite/gas/elf/section2.e-riscv: New. * testsuite/gas/riscv/attribute-01.d: New test * testsuite/gas/riscv/attribute-02.d: Likewise. * testsuite/gas/riscv/attribute-03.d: Likewise. * testsuite/gas/riscv/attribute-04.d: Likewise. * testsuite/gas/riscv/attribute-04.s: Likewise. * testsuite/gas/riscv/attribute-05.d: Likewise. * testsuite/gas/riscv/attribute-05.s: Likewise. * testsuite/gas/riscv/attribute-06.d: Likewise. * testsuite/gas/riscv/attribute-06.s: Likewise. * testsuite/gas/riscv/attribute-07.d: Likewise. * testsuite/gas/riscv/attribute-07.s: Likewise. * testsuite/gas/riscv/attribute-08.d: Likewise. * testsuite/gas/riscv/attribute-08.s: Likewise. * testsuite/gas/riscv/attribute-unknown.d: Likewise. * testsuite/gas/riscv/attribute-unknown.s: Likewise. * testsuite/gas/riscv/empty.l: Likewise. * doc/c-riscv.texi (.attribute): Add documentation. * configure.ac (--enable-default-riscv-attribute): New options. * configure: Re-generate. * config.in: Re-generate. include/ * elf/riscv.h (SHT_RISCV_ATTRIBUTES): Define. (Tag_RISCV_arch): Likewise. (Tag_RISCV_priv_spec): Likewise. (Tag_RISCV_priv_spec_minor): Likewise. (Tag_RISCV_priv_spec_revision): Likewise. (Tag_RISCV_unaligned_access): Likewise. (Tag_RISCV_stack_align): Likewise.
2019-01-16 22:14:59 +01:00
2019-01-16 Kito Cheng <kito@andestech.com>
Nelson Chu <nelson@andestech.com>
* config/tc-riscv.c (DEFAULT_RISCV_ATTR): Define to 0 if not defined.
(riscv_set_options): Add `arch_attr` field.
(riscv_opts): Set default value for arch_attr.
(riscv_write_out_arch_attr): New.
(riscv_set_public_attributes): Likewise.
(riscv_md_end): Likewise.
(riscv_convert_symbolic_attribute): Likewise.
(s_riscv_attribute): Likewise.
(explicit_arch_attr): Likewise.
(riscv_pseudo_table): Add .attribute to the table.
(options): Add OPTION_ARCH_ATTR and OPTION_NO_ARCH_ATTR
enumeration constants.
(md_longopts): Add `march-attr' and `mno-arch-attr' options.
(md_parse_option): Handle the new options.
(md_show_usage): Document the `march-attr' option.
* config/tc-riscv.h (md_end): Define as riscv_md_end
(riscv_md_end): Declare.
(CONVERT_SYMBOLIC_ATTRIBUTE): Define as
riscv_convert_symbolic_attribute.
(riscv_convert_symbolic_attribute): Declare.
(start_assemble): Declare.
* testsuite/gas/elf/elf.exp: Adjust test case for section2.e.
* testsuite/gas/elf/section2.e-riscv: New.
* testsuite/gas/riscv/attribute-01.d: New test
* testsuite/gas/riscv/attribute-02.d: Likewise.
* testsuite/gas/riscv/attribute-03.d: Likewise.
* testsuite/gas/riscv/attribute-04.d: Likewise.
* testsuite/gas/riscv/attribute-04.s: Likewise.
* testsuite/gas/riscv/attribute-05.d: Likewise.
* testsuite/gas/riscv/attribute-05.s: Likewise.
* testsuite/gas/riscv/attribute-06.d: Likewise.
* testsuite/gas/riscv/attribute-06.s: Likewise.
* testsuite/gas/riscv/attribute-07.d: Likewise.
* testsuite/gas/riscv/attribute-07.s: Likewise.
* testsuite/gas/riscv/attribute-08.d: Likewise.
* testsuite/gas/riscv/attribute-08.s: Likewise.
* testsuite/gas/riscv/attribute-unknown.d: Likewise.
* testsuite/gas/riscv/attribute-unknown.s: Likewise.
* testsuite/gas/riscv/empty.l: Likewise.
* doc/c-riscv.texi (.attribute): Add documentation.
* configure.ac (--enable-default-riscv-attribute): New options.
* configure: Re-generate.
* config.in: Re-generate.
S12Z: Emit RELOC_S12Z_OPR instead of RELOC_EXT24 where appropriate. When assembling instructions which involve OPR references, emit RELOC_S12Z_OPR instead of RELOC_EXT24. bfd/ * bfd-in2.h [BFD_RELOC_S12Z_OPR]: New reloc. * libbfd.h: regen. * elf32-s12z.c (eld_s12z_howto_table): R_S12Z_OPR takes non zero source field. (md_apply_fix): Apply final fix to BFD_RELOC_S12Z_OPR. * reloc.c[BFD_RELOC_S12Z_OPR]: New reloc. gas/ * config/tc-s12z.c (emit_opr): Emit BFD_RELOC_S12Z_OPR instead of BFD_RELOC_24. * testsuite/gas/s12z/opr-indirect-expr.d: Expect R_S12Z_OPR instead of R_S12Z_EXT24.
2019-01-16 14:34:50 +01:00
2019-01-16 John Darrington <john@darrington.wattle.id.au>
S12Z: gas: Fix bug when a symbol name was the single letter 'c'. The assembler incorrectly recognised "c" as a register name, and refused to allow it where it expected a symbol/label. gas/ * config/tc-s12z.c (lex_reg_name): Compare the length of the strings before the contents. * testsuite/gas/s12z/labels.d: New file. * testsuite/gas/s12z/labels.s: New file. * testsuite/gas/s12z/s12z.exp: Add them.
2019-01-14 16:55:17 +01:00
* config/tc-s12z.c (lex_reg_name): Compare the length of the strings
before the contents.
* testsuite/gas/s12z/labels.d: New file.
* testsuite/gas/s12z/labels.s: New file.
* testsuite/gas/s12z/s12z.exp: Add them.
* config/tc-s12z.c (tfr): Change as_bad to as_warn.
S12Z: gas: Permit "extend" instructions which don't actually extend. Other assemblers permit "extending" a register into a register of a smaller size or the same size. It doesn't make much sense to do this but would appear to be a valid instruction. So change the error to a warning. gas/ * config/tc-s12z.c (tfr): Change as_bad to as_warn. Also fix message typo and semantics.
2019-01-16 14:34:50 +01:00
Also fix message typo and semantics.
S12Z: gas: Fix bug when a symbol name was the single letter 'c'. The assembler incorrectly recognised "c" as a register name, and refused to allow it where it expected a symbol/label. gas/ * config/tc-s12z.c (lex_reg_name): Compare the length of the strings before the contents. * testsuite/gas/s12z/labels.d: New file. * testsuite/gas/s12z/labels.s: New file. * testsuite/gas/s12z/s12z.exp: Add them.
2019-01-14 16:55:17 +01:00
* config/tc-s12z.c (emit_opr): Emit BFD_RELOC_S12Z_OPR instead of
S12Z: Emit RELOC_S12Z_OPR instead of RELOC_EXT24 where appropriate. When assembling instructions which involve OPR references, emit RELOC_S12Z_OPR instead of RELOC_EXT24. bfd/ * bfd-in2.h [BFD_RELOC_S12Z_OPR]: New reloc. * libbfd.h: regen. * elf32-s12z.c (eld_s12z_howto_table): R_S12Z_OPR takes non zero source field. (md_apply_fix): Apply final fix to BFD_RELOC_S12Z_OPR. * reloc.c[BFD_RELOC_S12Z_OPR]: New reloc. gas/ * config/tc-s12z.c (emit_opr): Emit BFD_RELOC_S12Z_OPR instead of BFD_RELOC_24. * testsuite/gas/s12z/opr-indirect-expr.d: Expect R_S12Z_OPR instead of R_S12Z_EXT24.
2019-01-16 14:34:50 +01:00
BFD_RELOC_24.
* testsuite/gas/s12z/opr-indirect-expr.d: Expect R_S12Z_OPR instead
of R_S12Z_EXT24.
Implement the assembly instructions yield, wfe, wfi and sev for ARMv6T2 in both ARM mode and Thumb mode. * config/tc-arm.c (arm_ext_v6k_v6t2): Define. (insns) [ARM_VARIANT]: Modified. (insns) [THUMB_VARIANT]: To implement few ARMv6K instructions in ARMv6T2 as well. * testsuite/gas/arm/archv6t2-1.d: New test. * testsuite/gas/arm/archv6t2-1.s: Likewise. * testsuite/gas/arm/archv6t2-2.d: Likewise.
2019-01-14 11:35:50 +01:00
2019-01-14 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
* config/tc-arm.c (arm_ext_v6k_v6t2): Define.
(insns) [ARM_VARIANT]: Modified.
(insns) [THUMB_VARIANT]: To implement few ARMv6K instructions
in ARMv6T2 as well.
* testsuite/gas/arm/archv6t2-1.d: New test.
* testsuite/gas/arm/archv6t2-1.s: Likewise.
* testsuite/gas/arm/archv6t2-2.d: Likewise.
More fallout from PR 23963 change PR 23963 * testsuite/gas/m68hc11/lbranch-dwarf2.d: Adjust for PR23963 change. * testsuite/gas/m68hc11/opers12-dwarf2.d: Likewise.
2019-01-11 12:52:30 +01:00
2019-01-11 Alan Modra <amodra@gmail.com>
PR 23963
* testsuite/gas/m68hc11/lbranch-dwarf2.d: Adjust for PR23963 change.
* testsuite/gas/m68hc11/opers12-dwarf2.d: Likewise.
Stop objdump from displaying control codes embedded in symbol names. PR 23963 binutils* objdump.c (sanitize_string): New function. Removes control characters from symbol names. (dump_section_header): Use new function. (objdump_print_symname): Likewise. (objdump_print_addr_with_sym): Likewise. (show_line): Likewise. (disassemble_bytes): Likewise. (disassemble_section): Likewise. (load_specific_debug_section): Likewise. (read_section_stabs): Likewise. (print_section_stabs): Likewise. (dump_section): Likewise. (dump_reloc_set): Likewise. (dump_relocs_in_section): Likewise. (dump_bfd): Likewise. (display_any_bfd): Likewise. gas * testsuite/gas/mips/mips16-branch-absolute-1.d: Adjust for the fact that control characters are now displayed as escape sequences. * testsuite/gas/mips/mips16-e.d: Likewise. * testsuite/gas/mips/mips16-pcrel-0.d: Likewise. * testsuite/gas/mips/mips16-pcrel-1.d: Likewise. * testsuite/gas/mips/mips16-pcrel-delay-0.d: Likewise. * testsuite/gas/mips/mips16-pcrel-delay-1.d: Likewise. * testsuite/gas/mips/mips16-pcrel-n32-0.d: Likewise. * testsuite/gas/mips/mips16-pcrel-n32-1.d: Likewise. * testsuite/gas/mips/mips16-pcrel-n64-sym32-0.d: Likewise. * testsuite/gas/mips/mips16-pcrel-n64-sym32-1.d: Likewise. * testsuite/gas/mips/mips16e2@mips16-pcrel-0.d: Likewise. * testsuite/gas/mips/mips16e2@mips16-pcrel-1.d: Likewise. * testsuite/gas/mips/mips16e2@mips16-pcrel-delay-0.d: Likewise. * testsuite/gas/mips/mips16e2@mips16-pcrel-delay-1.d: Likewise. * testsuite/gas/mips/mips16e2@mips16-pcrel-n32-0.d: Likewise. * testsuite/gas/mips/mips16e2@mips16-pcrel-n32-1.d: Likewise. * testsuite/gas/mips/mips16e2@mips16-pcrel-n64-sym32-0.d: Likewise. * testsuite/gas/mips/mips16e2@mips16-pcrel-n64-sym32-1.d: Likewise. * testsuite/gas/mips/mipsel16-e.d: Likewise. * testsuite/gas/mips/mipsr6@msa.d: Likewise. * testsuite/gas/mips/mipsr6@relax-swap3.d: Likewise. * testsuite/gas/mips/r6-64-n32.d: Likewise. * testsuite/gas/mips/r6-64-n64.d: Likewise. * testsuite/gas/mips/r6-n32.d: Likewise. * testsuite/gas/mips/r6-n64.d: Likewise. * testsuite/gas/mips/r6.d: Likewise. * testsuite/gas/mips/tmips16-e.d: Likewise. * testsuite/gas/mips/tmipsel16-e.d: Likewise. * testsuite/gas/mn10300/relax.d: Likewise.
2019-01-10 16:19:33 +01:00
2019-01-10 Nick Clifton <nickc@redhat.com>
PR 23963
Correct changelog entry.
2019-01-10 16:23:03 +01:00
* testsuite/gas/mips/mips16-branch-absolute-1.d: Adjust for the
fact that control characters are now displayed as escape
sequences.
Stop objdump from displaying control codes embedded in symbol names. PR 23963 binutils* objdump.c (sanitize_string): New function. Removes control characters from symbol names. (dump_section_header): Use new function. (objdump_print_symname): Likewise. (objdump_print_addr_with_sym): Likewise. (show_line): Likewise. (disassemble_bytes): Likewise. (disassemble_section): Likewise. (load_specific_debug_section): Likewise. (read_section_stabs): Likewise. (print_section_stabs): Likewise. (dump_section): Likewise. (dump_reloc_set): Likewise. (dump_relocs_in_section): Likewise. (dump_bfd): Likewise. (display_any_bfd): Likewise. gas * testsuite/gas/mips/mips16-branch-absolute-1.d: Adjust for the fact that control characters are now displayed as escape sequences. * testsuite/gas/mips/mips16-e.d: Likewise. * testsuite/gas/mips/mips16-pcrel-0.d: Likewise. * testsuite/gas/mips/mips16-pcrel-1.d: Likewise. * testsuite/gas/mips/mips16-pcrel-delay-0.d: Likewise. * testsuite/gas/mips/mips16-pcrel-delay-1.d: Likewise. * testsuite/gas/mips/mips16-pcrel-n32-0.d: Likewise. * testsuite/gas/mips/mips16-pcrel-n32-1.d: Likewise. * testsuite/gas/mips/mips16-pcrel-n64-sym32-0.d: Likewise. * testsuite/gas/mips/mips16-pcrel-n64-sym32-1.d: Likewise. * testsuite/gas/mips/mips16e2@mips16-pcrel-0.d: Likewise. * testsuite/gas/mips/mips16e2@mips16-pcrel-1.d: Likewise. * testsuite/gas/mips/mips16e2@mips16-pcrel-delay-0.d: Likewise. * testsuite/gas/mips/mips16e2@mips16-pcrel-delay-1.d: Likewise. * testsuite/gas/mips/mips16e2@mips16-pcrel-n32-0.d: Likewise. * testsuite/gas/mips/mips16e2@mips16-pcrel-n32-1.d: Likewise. * testsuite/gas/mips/mips16e2@mips16-pcrel-n64-sym32-0.d: Likewise. * testsuite/gas/mips/mips16e2@mips16-pcrel-n64-sym32-1.d: Likewise. * testsuite/gas/mips/mipsel16-e.d: Likewise. * testsuite/gas/mips/mipsr6@msa.d: Likewise. * testsuite/gas/mips/mipsr6@relax-swap3.d: Likewise. * testsuite/gas/mips/r6-64-n32.d: Likewise. * testsuite/gas/mips/r6-64-n64.d: Likewise. * testsuite/gas/mips/r6-n32.d: Likewise. * testsuite/gas/mips/r6-n64.d: Likewise. * testsuite/gas/mips/r6.d: Likewise. * testsuite/gas/mips/tmips16-e.d: Likewise. * testsuite/gas/mips/tmipsel16-e.d: Likewise. * testsuite/gas/mn10300/relax.d: Likewise.
2019-01-10 16:19:33 +01:00
* testsuite/gas/mips/mips16-e.d: Likewise.
* testsuite/gas/mips/mips16-pcrel-0.d: Likewise.
* testsuite/gas/mips/mips16-pcrel-1.d: Likewise.
* testsuite/gas/mips/mips16-pcrel-delay-0.d: Likewise.
* testsuite/gas/mips/mips16-pcrel-delay-1.d: Likewise.
* testsuite/gas/mips/mips16-pcrel-n32-0.d: Likewise.
* testsuite/gas/mips/mips16-pcrel-n32-1.d: Likewise.
* testsuite/gas/mips/mips16-pcrel-n64-sym32-0.d: Likewise.
* testsuite/gas/mips/mips16-pcrel-n64-sym32-1.d: Likewise.
* testsuite/gas/mips/mips16e2@mips16-pcrel-0.d: Likewise.
* testsuite/gas/mips/mips16e2@mips16-pcrel-1.d: Likewise.
* testsuite/gas/mips/mips16e2@mips16-pcrel-delay-0.d: Likewise.
* testsuite/gas/mips/mips16e2@mips16-pcrel-delay-1.d: Likewise.
* testsuite/gas/mips/mips16e2@mips16-pcrel-n32-0.d: Likewise.
* testsuite/gas/mips/mips16e2@mips16-pcrel-n32-1.d: Likewise.
* testsuite/gas/mips/mips16e2@mips16-pcrel-n64-sym32-0.d:
Likewise.
* testsuite/gas/mips/mips16e2@mips16-pcrel-n64-sym32-1.d:
Likewise.
* testsuite/gas/mips/mipsel16-e.d: Likewise.
* testsuite/gas/mips/mipsr6@msa.d: Likewise.
* testsuite/gas/mips/mipsr6@relax-swap3.d: Likewise.
* testsuite/gas/mips/r6-64-n32.d: Likewise.
* testsuite/gas/mips/r6-64-n64.d: Likewise.
* testsuite/gas/mips/r6-n32.d: Likewise.
* testsuite/gas/mips/r6-n64.d: Likewise.
* testsuite/gas/mips/r6.d: Likewise.
* testsuite/gas/mips/tmips16-e.d: Likewise.
* testsuite/gas/mips/tmipsel16-e.d: Likewise.
* testsuite/gas/mn10300/relax.d: Likewise.
S12Z: Fix disassembly of indexed OPR operands with zero index. gas/ * testsuite/gas/s12z/jsr.s: New case. * testsuite/gas/s12z/jsr.d: New case. opcodes/ * s12z-dis.c (opr_emit_disassembly): Do not omit an index if it is zero.
2018-12-31 08:48:10 +01:00
2019-01-09 John Darrington <john@darrington.wattle.id.au>
* testsuite/gas/s12z/jsr.s: New case.
* testsuite/gas/s12z/jsr.d: New case.
Adjust bfd/warning.m4 egrep patterns Adjust the `bfd/warning.m4` `egrep` patterns to handle preprocessors that do not define `__GNUC__`, leaving the string in the output. bfd/ * warning.m4: Adjust egrep pattern for non-GNU compilers. * configure: Regenerate. binutils/ * configure: Regenerate. gas/ * configure: Regenerate. gold/ * configure: Regenerate. gprof/ * configure: Regenerate. ld/ * configure: Regenerate. opcodes/ * configure: Regenerate.
2019-01-09 04:21:08 +01:00
2019-01-09 Andrew Paprocki <andrew@ishiboo.com>
* configure: Regenerate.
[AArch64][gas] Add -mcpu support for Arm Ares This adds support for the Arm Ares CPU for AArch64. It implements the Armv8.2-A architecture with the optional features of statistical profiling, dot product and FP16 on by default. Note: Ares is a codename to enable early adopters and in time we will add the final product name once it's announced. * config/tc-aarch64.c (aarch64_cpus): Add ares. * doc/c-aarch64.texi (-mcpu): Document ares value.
2019-01-08 16:18:32 +01:00
2019-01-08 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
* config/tc-aarch64.c (aarch64_cpus): Add ares.
* doc/c-aarch64.texi (-mcpu): Document ares value.
run_dump_test source in build directory Some existing tests build .s and .d files for run_dump_test, using an absolute #source: line in the .d file. This patch changes that scheme a little to instead use "#source: ./..." in .d files rather than "#source: $objdir/...", which is more useful in cases where the .d file is not generated. This allows RX gas test files to be built in the build directory, rather than in a source directory (which might be read-only). binutils/ * testsuite/lib/binutils-common.exp (run_dump_test): Don't prepend $srcdir/$subdir to source file name if it starts with "./". gas/ * testsuite/gas/rx/rx.exp: Create generated test source in current directory. * testsuite/gas/rx/Xtod.d, * testsuite/gas/rx/abs.d, * testsuite/gas/rx/adc.d, * testsuite/gas/rx/add.d, * testsuite/gas/rx/and.d, * testsuite/gas/rx/bclr.d, * testsuite/gas/rx/bcnd.d, * testsuite/gas/rx/bfmov.d, * testsuite/gas/rx/bmcnd.d, * testsuite/gas/rx/bnot.d, * testsuite/gas/rx/bra.d, * testsuite/gas/rx/brk.d, * testsuite/gas/rx/bset.d, * testsuite/gas/rx/bsr.d, * testsuite/gas/rx/btst.d, * testsuite/gas/rx/clrpsw.d, * testsuite/gas/rx/cmp.d, * testsuite/gas/rx/dabs.d, * testsuite/gas/rx/dadd.d, * testsuite/gas/rx/dbt.d, * testsuite/gas/rx/dcmp.d, * testsuite/gas/rx/ddiv.d, * testsuite/gas/rx/div.d, * testsuite/gas/rx/divu.d, * testsuite/gas/rx/dmov.d, * testsuite/gas/rx/dmul.d, * testsuite/gas/rx/dneg.d, * testsuite/gas/rx/dpopm.d, * testsuite/gas/rx/dpushm.d, * testsuite/gas/rx/dround.d, * testsuite/gas/rx/dsqrt.d, * testsuite/gas/rx/dsub.d, * testsuite/gas/rx/dtoX.d, * testsuite/gas/rx/emaca.d, * testsuite/gas/rx/emsba.d, * testsuite/gas/rx/emul.d, * testsuite/gas/rx/emula.d, * testsuite/gas/rx/emulu.d, * testsuite/gas/rx/fadd.d, * testsuite/gas/rx/fcmp.d, * testsuite/gas/rx/fdiv.d, * testsuite/gas/rx/fmul.d, * testsuite/gas/rx/fsqrt.d, * testsuite/gas/rx/fsub.d, * testsuite/gas/rx/ftoi.d, * testsuite/gas/rx/ftou.d, * testsuite/gas/rx/gprel.d, * testsuite/gas/rx/int.d, * testsuite/gas/rx/itof.d, * testsuite/gas/rx/jmp.d, * testsuite/gas/rx/jsr.d, * testsuite/gas/rx/machi.d, * testsuite/gas/rx/maclh.d, * testsuite/gas/rx/maclo.d, * testsuite/gas/rx/max.d, * testsuite/gas/rx/min.d, * testsuite/gas/rx/mov.d, * testsuite/gas/rx/movco.d, * testsuite/gas/rx/movli.d, * testsuite/gas/rx/movu.d, * testsuite/gas/rx/msbhi.d, * testsuite/gas/rx/msblh.d, * testsuite/gas/rx/msblo.d, * testsuite/gas/rx/mul.d, * testsuite/gas/rx/mulhi.d, * testsuite/gas/rx/mullh.d, * testsuite/gas/rx/mullo.d, * testsuite/gas/rx/mvfacgu.d, * testsuite/gas/rx/mvfachi.d, * testsuite/gas/rx/mvfaclo.d, * testsuite/gas/rx/mvfacmi.d, * testsuite/gas/rx/mvfc.d, * testsuite/gas/rx/mvfcp.d, * testsuite/gas/rx/mvfdc.d, * testsuite/gas/rx/mvfdr.d, * testsuite/gas/rx/mvtacgu.d, * testsuite/gas/rx/mvtachi.d, * testsuite/gas/rx/mvtaclo.d, * testsuite/gas/rx/mvtc.d, * testsuite/gas/rx/mvtcp.d, * testsuite/gas/rx/mvtdc.d, * testsuite/gas/rx/neg.d, * testsuite/gas/rx/nop.d, * testsuite/gas/rx/not.d, * testsuite/gas/rx/opecp.d, * testsuite/gas/rx/or.d, * testsuite/gas/rx/pop.d, * testsuite/gas/rx/popc.d, * testsuite/gas/rx/popm.d, * testsuite/gas/rx/push.d, * testsuite/gas/rx/pushc.d, * testsuite/gas/rx/pushm.d, * testsuite/gas/rx/r-bcc.d, * testsuite/gas/rx/r-bra.d, * testsuite/gas/rx/racl.d, * testsuite/gas/rx/racw.d, * testsuite/gas/rx/rdacl.d, * testsuite/gas/rx/rdacw.d, * testsuite/gas/rx/revl.d, * testsuite/gas/rx/revw.d, * testsuite/gas/rx/rmpa.d, * testsuite/gas/rx/rolc.d, * testsuite/gas/rx/rorc.d, * testsuite/gas/rx/rotl.d, * testsuite/gas/rx/rotr.d, * testsuite/gas/rx/round.d, * testsuite/gas/rx/rstr.d, * testsuite/gas/rx/rte.d, * testsuite/gas/rx/rtfi.d, * testsuite/gas/rx/rts.d, * testsuite/gas/rx/rtsd.d, * testsuite/gas/rx/sat.d, * testsuite/gas/rx/satr.d, * testsuite/gas/rx/save.d, * testsuite/gas/rx/sbb.d, * testsuite/gas/rx/sccnd.d, * testsuite/gas/rx/scmpu.d, * testsuite/gas/rx/setpsw.d, * testsuite/gas/rx/shar.d, * testsuite/gas/rx/shll.d, * testsuite/gas/rx/shlr.d, * testsuite/gas/rx/smovb.d, * testsuite/gas/rx/smovf.d, * testsuite/gas/rx/smovu.d, * testsuite/gas/rx/sstr.d, * testsuite/gas/rx/stnz.d, * testsuite/gas/rx/stz.d, * testsuite/gas/rx/sub.d, * testsuite/gas/rx/suntil.d, * testsuite/gas/rx/swhile.d, * testsuite/gas/rx/tst.d, * testsuite/gas/rx/utof.d, * testsuite/gas/rx/wait.d, * testsuite/gas/rx/xchg.d, * testsuite/gas/rx/xor.d: Add #source line. ld/ * testsuite/ld-elf/sec64k.exp: Use . rather than $objdir in generated source file names. * testsuite/ld-m68k/m68k-got.exp: Likewise.
2019-01-08 07:17:52 +01:00
2019-01-08 Alan Modra <amodra@gmail.com>
* testsuite/gas/rx/rx.exp: Create generated test source in
current directory.
* testsuite/gas/rx/Xtod.d, * testsuite/gas/rx/abs.d,
* testsuite/gas/rx/adc.d, * testsuite/gas/rx/add.d,
* testsuite/gas/rx/and.d, * testsuite/gas/rx/bclr.d,
* testsuite/gas/rx/bcnd.d, * testsuite/gas/rx/bfmov.d,
* testsuite/gas/rx/bmcnd.d, * testsuite/gas/rx/bnot.d,
* testsuite/gas/rx/bra.d, * testsuite/gas/rx/brk.d,
* testsuite/gas/rx/bset.d, * testsuite/gas/rx/bsr.d,
* testsuite/gas/rx/btst.d, * testsuite/gas/rx/clrpsw.d,
* testsuite/gas/rx/cmp.d, * testsuite/gas/rx/dabs.d,
* testsuite/gas/rx/dadd.d, * testsuite/gas/rx/dbt.d,
* testsuite/gas/rx/dcmp.d, * testsuite/gas/rx/ddiv.d,
* testsuite/gas/rx/div.d, * testsuite/gas/rx/divu.d,
* testsuite/gas/rx/dmov.d, * testsuite/gas/rx/dmul.d,
* testsuite/gas/rx/dneg.d, * testsuite/gas/rx/dpopm.d,
* testsuite/gas/rx/dpushm.d, * testsuite/gas/rx/dround.d,
* testsuite/gas/rx/dsqrt.d, * testsuite/gas/rx/dsub.d,
* testsuite/gas/rx/dtoX.d, * testsuite/gas/rx/emaca.d,
* testsuite/gas/rx/emsba.d, * testsuite/gas/rx/emul.d,
* testsuite/gas/rx/emula.d, * testsuite/gas/rx/emulu.d,
* testsuite/gas/rx/fadd.d, * testsuite/gas/rx/fcmp.d,
* testsuite/gas/rx/fdiv.d, * testsuite/gas/rx/fmul.d,
* testsuite/gas/rx/fsqrt.d, * testsuite/gas/rx/fsub.d,
* testsuite/gas/rx/ftoi.d, * testsuite/gas/rx/ftou.d,
* testsuite/gas/rx/gprel.d, * testsuite/gas/rx/int.d,
* testsuite/gas/rx/itof.d, * testsuite/gas/rx/jmp.d,
* testsuite/gas/rx/jsr.d, * testsuite/gas/rx/machi.d,
* testsuite/gas/rx/maclh.d, * testsuite/gas/rx/maclo.d,
* testsuite/gas/rx/max.d, * testsuite/gas/rx/min.d,
* testsuite/gas/rx/mov.d, * testsuite/gas/rx/movco.d,
* testsuite/gas/rx/movli.d, * testsuite/gas/rx/movu.d,
* testsuite/gas/rx/msbhi.d, * testsuite/gas/rx/msblh.d,
* testsuite/gas/rx/msblo.d, * testsuite/gas/rx/mul.d,
* testsuite/gas/rx/mulhi.d, * testsuite/gas/rx/mullh.d,
* testsuite/gas/rx/mullo.d, * testsuite/gas/rx/mvfacgu.d,
* testsuite/gas/rx/mvfachi.d, * testsuite/gas/rx/mvfaclo.d,
* testsuite/gas/rx/mvfacmi.d, * testsuite/gas/rx/mvfc.d,
* testsuite/gas/rx/mvfcp.d, * testsuite/gas/rx/mvfdc.d,
* testsuite/gas/rx/mvfdr.d, * testsuite/gas/rx/mvtacgu.d,
* testsuite/gas/rx/mvtachi.d, * testsuite/gas/rx/mvtaclo.d,
* testsuite/gas/rx/mvtc.d, * testsuite/gas/rx/mvtcp.d,
* testsuite/gas/rx/mvtdc.d, * testsuite/gas/rx/neg.d,
* testsuite/gas/rx/nop.d, * testsuite/gas/rx/not.d,
* testsuite/gas/rx/opecp.d, * testsuite/gas/rx/or.d,
* testsuite/gas/rx/pop.d, * testsuite/gas/rx/popc.d,
* testsuite/gas/rx/popm.d, * testsuite/gas/rx/push.d,
* testsuite/gas/rx/pushc.d, * testsuite/gas/rx/pushm.d,
* testsuite/gas/rx/r-bcc.d, * testsuite/gas/rx/r-bra.d,
* testsuite/gas/rx/racl.d, * testsuite/gas/rx/racw.d,
* testsuite/gas/rx/rdacl.d, * testsuite/gas/rx/rdacw.d,
* testsuite/gas/rx/revl.d, * testsuite/gas/rx/revw.d,
* testsuite/gas/rx/rmpa.d, * testsuite/gas/rx/rolc.d,
* testsuite/gas/rx/rorc.d, * testsuite/gas/rx/rotl.d,
* testsuite/gas/rx/rotr.d, * testsuite/gas/rx/round.d,
* testsuite/gas/rx/rstr.d, * testsuite/gas/rx/rte.d,
* testsuite/gas/rx/rtfi.d, * testsuite/gas/rx/rts.d,
* testsuite/gas/rx/rtsd.d, * testsuite/gas/rx/sat.d,
* testsuite/gas/rx/satr.d, * testsuite/gas/rx/save.d,
* testsuite/gas/rx/sbb.d, * testsuite/gas/rx/sccnd.d,
* testsuite/gas/rx/scmpu.d, * testsuite/gas/rx/setpsw.d,
* testsuite/gas/rx/shar.d, * testsuite/gas/rx/shll.d,
* testsuite/gas/rx/shlr.d, * testsuite/gas/rx/smovb.d,
* testsuite/gas/rx/smovf.d, * testsuite/gas/rx/smovu.d,
* testsuite/gas/rx/sstr.d, * testsuite/gas/rx/stnz.d,
* testsuite/gas/rx/stz.d, * testsuite/gas/rx/sub.d,
* testsuite/gas/rx/suntil.d, * testsuite/gas/rx/swhile.d,
* testsuite/gas/rx/tst.d, * testsuite/gas/rx/utof.d,
* testsuite/gas/rx/wait.d, * testsuite/gas/rx/xchg.d,
* testsuite/gas/rx/xor.d: Add #source line.
[arm][gas] Add -mcpu support for Arm Ares This adds support for the Arm Ares CPU in the arm port. It implements the Armv8.2-A architecture with the relevant optional features of dot product and FP16 on by default. Note: Ares is a codename to enable early adopters and in time we will add the final product name once it's announced. * config/tc-arm.c (arm_cpus): Add ares. * doc/c-arm.texi (-mcpu): Document ares value.
2019-01-07 10:22:55 +01:00
2019-01-07 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
* config/tc-arm.c (arm_cpus): Add ares.
* doc/c-arm.texi (-mcpu): Document ares value.
RX: gas - Add RXv3 instruction support. Instruction manual. https://www.renesas.com/us/en/doc/products/mpumcu/doc/rx_family/r01us0316ej0100-rxv3sm.pdf * config/rx-defs.h (rx_cpu_types): Add type RXV3 and RXV3FPU. (rx_bfield): Add prototype. (rx_post): Likewise. * config/rx-parse.y: Add v3 instructions and Double FPU registers. (DSIZE): Define. (POST): Define. (rx_check_v3): New. check v3 type. (rx_check_dfpu): New. check have double support. (double_condition_table): New. dcmp<cond> contiditon. (check_condition): Multiple condition support. (rx_lex): RXv3 instructions support. Add parse dcmp<cond> instruction and Double FPU registers. (immediate): Disable optimize in dmov #imm case. (displacement): Add double displacement in dmov instraction. * config/tc-rx.c (rx_use_conventional_section_names): Invert default value in rx-*-linux target. (cpu_type): Add additional ELF flags. (cpu_type_list): Add RXv3. (md_parse_option): Refer elf_flags from cpu_type_list. (md_show_usage): Add rxv3 and rxv3-dfpu. (rx_bytesT): Add post byte. (rx_bfield): New. generate bfmov / bfmovz "imm" field. (rx_post): New. Set instruction post byte. (md_assemble): Add post byte. doc/c-rx.texi: Add cpu types. * testsuite/gas/rx/Xtod.d: New. * testsuite/gas/rx/Xtod.sm: New. * testsuite/gas/rx/bfmov.d: New. * testsuite/gas/rx/bfmov.sm: New. * testsuite/gas/rx/dabs.d: New. * testsuite/gas/rx/dabs.sm: New. * testsuite/gas/rx/dadd.d: New. * testsuite/gas/rx/dadd.sm: New. * testsuite/gas/rx/dcmp.d: New. * testsuite/gas/rx/dcmp.sm: New. * testsuite/gas/rx/ddiv.d: New. * testsuite/gas/rx/ddiv.sm: New. * testsuite/gas/rx/dmov.d: New. * testsuite/gas/rx/dmov.sm: New. * testsuite/gas/rx/dmul.d: New. * testsuite/gas/rx/dmul.sm: New. * testsuite/gas/rx/dneg.d: New. * testsuite/gas/rx/dneg.sm: New. * testsuite/gas/rx/dpopm.d: New. * testsuite/gas/rx/dpopm.sm: New. * testsuite/gas/rx/dpushm.d: New. * testsuite/gas/rx/dpushm.sm: New. * testsuite/gas/rx/dround.d: New. * testsuite/gas/rx/dround.sm: New. * testsuite/gas/rx/dsqrt.d: New. * testsuite/gas/rx/dsqrt.sm: New. * testsuite/gas/rx/dsub.d: New. * testsuite/gas/rx/dsub.sm: New. * testsuite/gas/rx/dtoX.d: New. * testsuite/gas/rx/dtoX.sm: New. * testsuite/gas/rx/macros.inc: Add double FPU registers. * testsuite/gas/rx/mvfdc.d: New. * testsuite/gas/rx/mvfdc.sm: New. * testsuite/gas/rx/mvfdr.d: New. * testsuite/gas/rx/mvfdr.sm: New. * testsuite/gas/rx/mvtdc.d: New. * testsuite/gas/rx/mvtdc.sm: New. * testsuite/gas/rx/rstr.d: New. * testsuite/gas/rx/rstr.sm: New. * testsuite/gas/rx/rx.exp: Use rxv3-dfpu option. * testsuite/gas/rx/save.d: New. * testsuite/gas/rx/save.sm: New. * testsuite/gas/rx/xor.d: New. * testsuite/gas/rx/xor.sm: Add pattern.
2018-12-25 12:52:53 +01:00
2019-01-05 Yoshinori Sato <ysato@users.sourceforge.jp>
* config/rx-defs.h (rx_cpu_types): Add type RXV3 and RXV3FPU.
(rx_bfield): Add prototype.
(rx_post): Likewise.
* config/rx-parse.y: Add v3 instructions and Double FPU registers.
(DSIZE): Define.
(POST): Define.
(rx_check_v3): New. check v3 type.
(rx_check_dfpu): New. check have double support.
(double_condition_table): New. dcmp<cond> contiditon.
(check_condition): Multiple condition support.
(rx_lex): RXv3 instructions support.
Add parse dcmp<cond> instruction and Double FPU registers.
(immediate): Disable optimize in dmov #imm case.
(displacement): Add double displacement in dmov instraction.
* config/tc-rx.c (rx_use_conventional_section_names):
Invert default value in rx-*-linux target.
(cpu_type): Add additional ELF flags.
(cpu_type_list): Add RXv3.
(md_parse_option): Refer elf_flags from cpu_type_list.
(md_show_usage): Add rxv3 and rxv3-dfpu.
(rx_bytesT): Add post byte.
(rx_bfield): New. generate bfmov / bfmovz "imm" field.
(rx_post): New. Set instruction post byte.
(md_assemble): Add post byte.
doc/c-rx.texi: Add cpu types.
* testsuite/gas/rx/Xtod.d: New.
* testsuite/gas/rx/Xtod.sm: New.
* testsuite/gas/rx/bfmov.d: New.
* testsuite/gas/rx/bfmov.sm: New.
* testsuite/gas/rx/dabs.d: New.
* testsuite/gas/rx/dabs.sm: New.
* testsuite/gas/rx/dadd.d: New.
* testsuite/gas/rx/dadd.sm: New.
* testsuite/gas/rx/dcmp.d: New.
* testsuite/gas/rx/dcmp.sm: New.
* testsuite/gas/rx/ddiv.d: New.
* testsuite/gas/rx/ddiv.sm: New.
* testsuite/gas/rx/dmov.d: New.
* testsuite/gas/rx/dmov.sm: New.
* testsuite/gas/rx/dmul.d: New.
* testsuite/gas/rx/dmul.sm: New.
* testsuite/gas/rx/dneg.d: New.
* testsuite/gas/rx/dneg.sm: New.
* testsuite/gas/rx/dpopm.d: New.
* testsuite/gas/rx/dpopm.sm: New.
* testsuite/gas/rx/dpushm.d: New.
* testsuite/gas/rx/dpushm.sm: New.
* testsuite/gas/rx/dround.d: New.
* testsuite/gas/rx/dround.sm: New.
* testsuite/gas/rx/dsqrt.d: New.
* testsuite/gas/rx/dsqrt.sm: New.
* testsuite/gas/rx/dsub.d: New.
* testsuite/gas/rx/dsub.sm: New.
* testsuite/gas/rx/dtoX.d: New.
* testsuite/gas/rx/dtoX.sm: New.
* testsuite/gas/rx/macros.inc: Add double FPU registers.
* testsuite/gas/rx/mvfdc.d: New.
* testsuite/gas/rx/mvfdc.sm: New.
* testsuite/gas/rx/mvfdr.d: New.
* testsuite/gas/rx/mvfdr.sm: New.
* testsuite/gas/rx/mvtdc.d: New.
* testsuite/gas/rx/mvtdc.sm: New.
* testsuite/gas/rx/rstr.d: New.
* testsuite/gas/rx/rstr.sm: New.
* testsuite/gas/rx/rx.exp: Use rxv3-dfpu option.
* testsuite/gas/rx/save.d: New.
* testsuite/gas/rx/save.sm: New.
* testsuite/gas/rx/xor.d: New.
* testsuite/gas/rx/xor.sm: Add pattern.
Fix potential buffer overrun whilst scanning macro strings. PR 24010 * macro.c (get_any_string): Check for end of input whilst scanning for separators.
2019-01-04 17:18:59 +01:00
2019-01-04 Wu Heng <wu.heng@zte.com.cn>
PR 24010
* macro.c (get_any_string): Check for end of input whilst scanning
for separators.
Fix bug parsing angle bracketed string sequences. PR 24009 * read.c (stringer): Fix handling of missing '>' character at end of <...> sequence.
2019-01-04 16:58:02 +01:00
2019-01-04 Wu Heng <wu.heng@zte.com.cn>
PR 24009
* read.c (stringer): Fix handling of missing '>' character at end
of <...> sequence.
Update year range in copyright notice of binutils files
2019-01-01 11:31:27 +01:00
2019-01-01 Alan Modra <amodra@gmail.com>
Update year range in copyright notice of all files.
ChangeLog rotation
2019-01-01 11:53:15 +01:00
For older changes see ChangeLog-2018
New 2016 binutils ChangeLog files Note that this does not create bfd/doc/ChangeLog, */testsuite/ChangeLog and include/*/ChangeLog files.
2016-01-01 11:44:31 +01:00
ChangeLog rotation
2019-01-01 11:53:15 +01:00
Copyright (C) 2019 Free Software Foundation, Inc.
New 2016 binutils ChangeLog files Note that this does not create bfd/doc/ChangeLog, */testsuite/ChangeLog and include/*/ChangeLog files.
2016-01-01 11:44:31 +01:00
Copying and distribution of this file, with or without modification,
are permitted in any medium without royalty provided the copyright
notice and this notice are preserved.
Local Variables:
mode: change-log
left-margin: 8
fill-column: 74
version-control: never
End:
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