1999-05-03 09:29:11 +02:00
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/* Instruction printing code for the ARM
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2018-01-03 06:17:27 +01:00
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Copyright (C) 1994-2018 Free Software Foundation, Inc.
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1999-05-03 09:29:11 +02:00
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Contributed by Richard Earnshaw (rwe@pegasus.esprit.ec.org)
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Modification by James G. Smith (jsmith@cygnus.co.uk)
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2003-03-25 21:56:01 +01:00
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This file is part of libopcodes.
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1999-05-03 09:29:11 +02:00
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2007-07-05 11:49:03 +02:00
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This library is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 3 of the License, or
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(at your option) any later version.
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1999-05-03 09:29:11 +02:00
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2007-07-05 11:49:03 +02:00
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It is distributed in the hope that it will be useful, but WITHOUT
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ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
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License for more details.
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1999-05-03 09:29:11 +02:00
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2003-03-25 21:56:01 +01:00
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You should have received a copy of the GNU General Public License
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along with this program; if not, write to the Free Software
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2007-07-05 11:49:03 +02:00
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Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
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MA 02110-1301, USA. */
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1999-05-03 09:29:11 +02:00
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1999-10-27 20:14:17 +02:00
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#include "sysdep.h"
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2004-11-27 12:09:21 +01:00
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Don't use print_insn_XXX in GDB
This is a follow-up to
[PATCH 0/6] Unify the disassembler selection in gdb and objdump
https://sourceware.org/ml/binutils/2017-05/msg00192.html
that is, opcodes is able to select the right disassembler, so gdb
doesn't have to select them. Instead, gdb can just use
default_print_insn. As a result, these print_insn_XXX are not used
out of opcodes, so this patch also moves their declarations from
include/dis-asm.h to opcodes/disassemble.h. With this change,
GDB doesn't use any print_insn_XXX directly any more.
gdb:
2017-06-14 Yao Qi <yao.qi@linaro.org>
* aarch64-tdep.c (aarch64_gdb_print_insn): Call
default_print_insn instead of print_insn_aarch64.
* arm-tdep.c (gdb_print_insn_arm): Call
default_print_insn instead of print_insn_big_arm
and print_insn_little_arm.
* i386-tdep.c (i386_print_insn): Call default_print_insn
instead of print_insn_i386.
* ia64-tdep.c (ia64_print_insn): Call
default_print_insn instead of print_insn_ia64.
* mips-tdep.c (gdb_print_insn_mips): Call
default_print_insn instead of print_insn_big_mips
and print_insn_little_mips.
* spu-tdep.c (gdb_print_insn_spu): Call default_print_insn
instead of print_insn_spu.
include:
2017-06-14 Yao Qi <yao.qi@linaro.org>
* dis-asm.h (print_insn_aarch64): Move it to opcodes/disassemble.h.
(print_insn_big_arm, print_insn_big_mips): Likewise.
(print_insn_i386, print_insn_ia64): Likewise.
(print_insn_little_arm, print_insn_little_mips): Likewise.
(print_insn_spu): Likewise.
opcodes:
2017-06-14 Yao Qi <yao.qi@linaro.org>
* aarch64-dis.c: Include disassemble.h instead of dis-asm.h.
* arm-dis.c: Likewise.
* ia64-dis.c: Likewise.
* mips-dis.c: Likewise.
* spu-dis.c: Likewise.
* disassemble.h (print_insn_aarch64): New declaration, moved from
include/dis-asm.h.
(print_insn_big_arm, print_insn_big_mips): Likewise.
(print_insn_i386, print_insn_ia64): Likewise.
(print_insn_little_arm, print_insn_little_mips): Likewise.
2017-06-14 17:28:30 +02:00
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#include "disassemble.h"
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2004-11-27 12:09:21 +01:00
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#include "opcode/arm.h"
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1999-05-03 09:29:11 +02:00
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#include "opintl.h"
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2003-07-18 13:34:41 +02:00
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#include "safe-ctype.h"
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2017-02-28 19:32:07 +01:00
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#include "libiberty.h"
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2006-04-26 18:02:07 +02:00
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#include "floatformat.h"
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1999-05-03 09:29:11 +02:00
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2002-05-23 14:48:23 +02:00
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/* FIXME: This shouldn't be done here. */
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opcodes:
* arm-opc.h: Delete; fold contents into ...
* arm-dis.c: ... here. Move includes of internal COFF headers
next to includes of internal ELF headers.
(streq, WORD_ADDRESS, BDISP, BDISP23): Delete, unused.
(struct arm_opcode): Rename struct opcode32. Make 'assembler' const.
(struct thumb_opcode): Rename struct opcode16. Make 'assembler' const.
(arm_conditional, arm_fp_const, arm_shift, arm_regname, regnames)
(iwmmxt_wwnames, iwmmxt_wwssnames):
Make const.
(regnames): Remove iWMMXt coprocessor register sets.
(iwmmxt_regnames, iwmmxt_cregnames): New statics.
(get_arm_regnames): Adjust fourth argument to match above changes.
(set_iwmmxt_regnames): Delete.
(print_insn_arm): Constify 'c'. Use ISO syntax for function
pointer calls. Expand sole use of BDISP. Use iwmmxt_regnames
and iwmmxt_cregnames, not set_iwmmxt_regnames.
(print_insn_thumb16, print_insn_thumb32): Constify 'c'. Use
ISO syntax for function pointer calls.
include:
* dis-asm.h (get_arm_regnames): Update prototype.
2005-06-08 19:27:41 +02:00
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#include "coff/internal.h"
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#include "libcoff.h"
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1999-05-03 09:29:11 +02:00
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#include "elf-bfd.h"
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#include "elf/internal.h"
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#include "elf/arm.h"
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2015-11-20 17:24:52 +01:00
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#include "mach-o.h"
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1999-05-03 09:29:11 +02:00
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opcodes:
* arm-opc.h: Delete; fold contents into ...
* arm-dis.c: ... here. Move includes of internal COFF headers
next to includes of internal ELF headers.
(streq, WORD_ADDRESS, BDISP, BDISP23): Delete, unused.
(struct arm_opcode): Rename struct opcode32. Make 'assembler' const.
(struct thumb_opcode): Rename struct opcode16. Make 'assembler' const.
(arm_conditional, arm_fp_const, arm_shift, arm_regname, regnames)
(iwmmxt_wwnames, iwmmxt_wwssnames):
Make const.
(regnames): Remove iWMMXt coprocessor register sets.
(iwmmxt_regnames, iwmmxt_cregnames): New statics.
(get_arm_regnames): Adjust fourth argument to match above changes.
(set_iwmmxt_regnames): Delete.
(print_insn_arm): Constify 'c'. Use ISO syntax for function
pointer calls. Expand sole use of BDISP. Use iwmmxt_regnames
and iwmmxt_cregnames, not set_iwmmxt_regnames.
(print_insn_thumb16, print_insn_thumb32): Constify 'c'. Use
ISO syntax for function pointer calls.
include:
* dis-asm.h (get_arm_regnames): Update prototype.
2005-06-08 19:27:41 +02:00
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/* FIXME: Belongs in global header. */
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2000-01-03 21:50:57 +01:00
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#ifndef strneq
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2000-01-27 23:17:12 +01:00
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#define strneq(a,b,n) (strncmp ((a), (b), (n)) == 0)
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#endif
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2011-04-08 13:42:19 +02:00
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/* Cached mapping symbol state. */
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enum map_type
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{
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MAP_ARM,
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MAP_THUMB,
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MAP_DATA
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};
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2010-01-29 17:47:55 +01:00
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struct arm_private_data
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{
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/* The features to use when disassembling optional instructions. */
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arm_feature_set features;
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/* Whether any mapping symbols are present in the provided symbol
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table. -1 if we do not know yet, otherwise 0 or 1. */
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int has_mapping_symbols;
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2011-04-08 13:42:19 +02:00
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/* Track the last type (although this doesn't seem to be useful) */
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enum map_type last_type;
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/* Tracking symbol table information */
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int last_mapping_sym;
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bfd_vma last_mapping_addr;
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2010-01-29 17:47:55 +01:00
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};
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opcodes:
* arm-opc.h: Delete; fold contents into ...
* arm-dis.c: ... here. Move includes of internal COFF headers
next to includes of internal ELF headers.
(streq, WORD_ADDRESS, BDISP, BDISP23): Delete, unused.
(struct arm_opcode): Rename struct opcode32. Make 'assembler' const.
(struct thumb_opcode): Rename struct opcode16. Make 'assembler' const.
(arm_conditional, arm_fp_const, arm_shift, arm_regname, regnames)
(iwmmxt_wwnames, iwmmxt_wwssnames):
Make const.
(regnames): Remove iWMMXt coprocessor register sets.
(iwmmxt_regnames, iwmmxt_cregnames): New statics.
(get_arm_regnames): Adjust fourth argument to match above changes.
(set_iwmmxt_regnames): Delete.
(print_insn_arm): Constify 'c'. Use ISO syntax for function
pointer calls. Expand sole use of BDISP. Use iwmmxt_regnames
and iwmmxt_cregnames, not set_iwmmxt_regnames.
(print_insn_thumb16, print_insn_thumb32): Constify 'c'. Use
ISO syntax for function pointer calls.
include:
* dis-asm.h (get_arm_regnames): Update prototype.
2005-06-08 19:27:41 +02:00
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struct opcode32
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{
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2015-03-24 07:08:08 +01:00
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arm_feature_set arch; /* Architecture defining this insn. */
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unsigned long value; /* If arch is 0 then value is a sentinel. */
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2009-06-30 13:57:05 +02:00
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unsigned long mask; /* Recognise insn if (op & mask) == value. */
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2009-06-29 10:08:15 +02:00
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const char * assembler; /* How to disassemble this insn. */
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opcodes:
* arm-opc.h: Delete; fold contents into ...
* arm-dis.c: ... here. Move includes of internal COFF headers
next to includes of internal ELF headers.
(streq, WORD_ADDRESS, BDISP, BDISP23): Delete, unused.
(struct arm_opcode): Rename struct opcode32. Make 'assembler' const.
(struct thumb_opcode): Rename struct opcode16. Make 'assembler' const.
(arm_conditional, arm_fp_const, arm_shift, arm_regname, regnames)
(iwmmxt_wwnames, iwmmxt_wwssnames):
Make const.
(regnames): Remove iWMMXt coprocessor register sets.
(iwmmxt_regnames, iwmmxt_cregnames): New statics.
(get_arm_regnames): Adjust fourth argument to match above changes.
(set_iwmmxt_regnames): Delete.
(print_insn_arm): Constify 'c'. Use ISO syntax for function
pointer calls. Expand sole use of BDISP. Use iwmmxt_regnames
and iwmmxt_cregnames, not set_iwmmxt_regnames.
(print_insn_thumb16, print_insn_thumb32): Constify 'c'. Use
ISO syntax for function pointer calls.
include:
* dis-asm.h (get_arm_regnames): Update prototype.
2005-06-08 19:27:41 +02:00
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};
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struct opcode16
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{
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2015-03-24 07:08:08 +01:00
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arm_feature_set arch; /* Architecture defining this insn. */
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2009-11-17 18:20:26 +01:00
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unsigned short value, mask; /* Recognise insn if (op & mask) == value. */
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opcodes:
* arm-opc.h: Delete; fold contents into ...
* arm-dis.c: ... here. Move includes of internal COFF headers
next to includes of internal ELF headers.
(streq, WORD_ADDRESS, BDISP, BDISP23): Delete, unused.
(struct arm_opcode): Rename struct opcode32. Make 'assembler' const.
(struct thumb_opcode): Rename struct opcode16. Make 'assembler' const.
(arm_conditional, arm_fp_const, arm_shift, arm_regname, regnames)
(iwmmxt_wwnames, iwmmxt_wwssnames):
Make const.
(regnames): Remove iWMMXt coprocessor register sets.
(iwmmxt_regnames, iwmmxt_cregnames): New statics.
(get_arm_regnames): Adjust fourth argument to match above changes.
(set_iwmmxt_regnames): Delete.
(print_insn_arm): Constify 'c'. Use ISO syntax for function
pointer calls. Expand sole use of BDISP. Use iwmmxt_regnames
and iwmmxt_cregnames, not set_iwmmxt_regnames.
(print_insn_thumb16, print_insn_thumb32): Constify 'c'. Use
ISO syntax for function pointer calls.
include:
* dis-asm.h (get_arm_regnames): Update prototype.
2005-06-08 19:27:41 +02:00
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const char *assembler; /* How to disassemble this insn. */
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};
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bfd/
* elf32-arm.c (PLT_THUMB_STUB_SIZE): Define.
(elf32_arm_plt_thumb_stub): New.
(struct elf32_arm_link_hash_entry): Add plt_thumb_refcount
and plt_got_offset.
(elf32_arm_link_hash_traverse): Fix typo.
(elf32_arm_link_hash_table): Add obfd.
(elf32_arm_link_hash_newfunc): Initialize new fields.
(elf32_arm_copy_indirect_symbol): Copy plt_thumb_refcount.
(elf32_arm_link_hash_table_create): Initialize obfd.
(record_arm_to_thumb_glue): Mark the glue as a local ARM function.
(record_thumb_to_arm_glue): Mark the glue as a local Thumb function.
(bfd_elf32_arm_get_bfd_for_interworking): Verify that the
interworking BFD is not dynamic.
(bfd_elf32_arm_process_before_allocation): Handle R_ARM_PLT32. Do
not emit glue for PLT references.
(elf32_arm_final_link_relocate): Handle Thumb functions. Do not
emit glue for PLT references. Support the Thumb PLT prefix.
(elf32_arm_gc_sweep_hook): Handle R_ARM_THM_PC22 and
plt_thumb_refcount.
(elf32_arm_check_relocs): Likewise.
(elf32_arm_adjust_dynamic_symbol): Handle Thumb functions and
plt_thumb_refcount.
(allocate_dynrelocs): Handle Thumb PLT references.
(elf32_arm_finish_dynamic_symbol): Likewise.
(elf32_arm_symbol_processing): New function.
(elf_backend_symbol_processing): Define.
opcodes/
* arm-dis.c (WORD_ADDRESS): Define.
(print_insn): Use it. Correct big-endian end-of-section handling.
gas/testsuite/
* gas/arm/mapping.d: Expect F markers for Thumb code.
* gas/arm/unwind.d: Update big-endian pattern.
ld/
* emultempl/armelf.em (arm_elf_set_bfd_for_interworking): Don't use
a dynamic object for stubs.
ld/testsuite/
* ld-arm/mixed-app.d, ld-arm/mixed-app.r, ld-arm/mixed-app.s,
ld-arm/mixed-app.sym, ld-arm/mixed-lib.d, ld-arm/mixed-lib.r,
ld-arm/mixed-lib.s, ld-arm/mixed-lib.sym, ld-arm/arm-dyn.ld,
ld-arm/arm-lib.ld: New files.
* ld-arm/arm-app-abs32.d, ld-arm/arm-app-abs32.r, ld-arm/arm-app.d,
ld-arm/arm-app.r, ld-arm/arm-lib-plt32.d, ld-arm/arm-lib-plt32.r,
ld-arm/arm-lib.d, ld-arm/arm-lib.r, ld-arm/arm-static-app.d,
ld-arm/arm-static-app.r: Update for big-endian.
* ld-arm/arm-elf.exp: Run the new tests.
2004-11-17 18:50:28 +01:00
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2005-09-02 Paul Brook <paul@codesourcery.com>
bfd/
* libbdf.h: Regenerate.
* bfd-in2.h: Regenerate.
* reloc.c: Add BFD_RELOC_ARM_T32_CP_OFF_IMM and
BFD_RELOC_ARM_T32_CP_OFF_IMM_S2.
gas/
* config/tc-arm.c (encode_arm_cp_address): Use
BFD_RELOC_ARM_T32_CP_OFF_IMM in thumb mode.
(do_iwmmxt_wldstbh): Use BFD_RELOC_ARM_T32_CP_OFF_IMM_S2 in thumb
mode.
(md_assemble): Only allow coprocessor instructions when Thumb-2 is
available.
(cCE, cC3): Define.
(insns): Use them for coprocessor instructions.
(md_pcrel_from_section): Handle BFD_RELOC_ARM_T32_CP_OFF_IMM.
(get_thumb32_insn): New function.
(put_thumb32_insn): New function.
(md_apply_fix): Handle BFD_RELOC_ARM_T32_CP_OFF_IMM and
BFD_RELOC_ARM_T32_CP_OFF_IMM_S2.
gas/testsuite/
* gas/arm/vfp-bad_t2.d, gas/arm/vfp-bad_t2.l, arm/vfp-bad_t2.s,
gas/arm/vfp1_t2.d, gas/arm/vfp1_t2.s, gas/arm/vfp1xD_t2.d,
gas/arm/vfp1xD_t2.s, gas/arm/vfp2_t2.d, gas/arm/vfp2_t2.s): New files.
opcodes/
* arm-dis.c (coprocessor_opcodes): New.
(arm_opcodes, thumb32_opcodes): Remove coprocessor insns.
(print_insn_coprocessor): New function.
(print_insn_arm): Use print_insn_coprocessor. Remove coprocessor
format characters.
(print_insn_thumb32): Use print_insn_coprocessor.
2005-09-02 15:12:45 +02:00
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/* print_insn_coprocessor recognizes the following format control codes:
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2005-06-08 00:16:52 +02:00
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2004-11-27 12:09:21 +01:00
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%% %
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2005-06-08 00:16:52 +02:00
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2006-06-07 16:08:19 +02:00
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%c print condition code (always bits 28-31 in ARM mode)
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2007-04-21 21:44:09 +02:00
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%q print shifter argument
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2012-08-24 09:59:05 +02:00
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%u print condition code (unconditional in ARM mode,
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UNPREDICTABLE if not AL in Thumb)
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2005-06-08 00:16:52 +02:00
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%A print address for ldc/stc/ldf/stf instruction
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2006-04-26 17:40:55 +02:00
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%B print vstm/vldm register list
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2005-06-08 00:16:52 +02:00
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%I print cirrus signed shift immediate: bits 0..3|4..6
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%F print the COUNT field of a LFM/SFM instruction.
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%P print floating point precision in arithmetic insn
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%Q print floating point precision in ldf/stf insn
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%R print floating point rounding mode
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2012-08-24 10:06:36 +02:00
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%<bitfield>c print as a condition code (for vsel)
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2005-06-08 00:16:52 +02:00
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%<bitfield>r print as an ARM register
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2009-12-17 10:52:18 +01:00
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%<bitfield>R as %<>r but r15 is UNPREDICTABLE
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%<bitfield>ru as %<>r but each u register must be unique.
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2004-11-27 12:09:21 +01:00
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%<bitfield>d print the bitfield in decimal
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2006-04-26 17:40:55 +02:00
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%<bitfield>k print immediate for VFPv3 conversion instruction
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2004-11-27 12:09:21 +01:00
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%<bitfield>x print the bitfield in hex
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%<bitfield>X print the bitfield as 1 hex digit without leading "0x"
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%<bitfield>f print a floating point constant if >7 else a
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floating point register
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2005-06-08 00:16:52 +02:00
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%<bitfield>w print as an iWMMXt width field - [bhwd]ss/us
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%<bitfield>g print as an iWMMXt 64-bit register
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%<bitfield>G print as an iWMMXt general purpose or control register
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2006-04-26 17:40:55 +02:00
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%<bitfield>D print as a NEON D register
|
|
|
|
|
|
%<bitfield>Q print as a NEON Q register
|
2016-12-05 15:24:17 +01:00
|
|
|
|
%<bitfield>V print as a NEON D or Q register
|
2015-07-16 17:38:48 +02:00
|
|
|
|
%<bitfield>E print a quarter-float immediate value
|
2005-06-08 00:16:52 +02:00
|
|
|
|
|
2006-04-26 17:40:55 +02:00
|
|
|
|
%y<code> print a single precision VFP reg.
|
2004-11-27 12:09:21 +01:00
|
|
|
|
Codes: 0=>Sm, 1=>Sd, 2=>Sn, 3=>multi-list, 4=>Sm pair
|
2006-04-26 17:40:55 +02:00
|
|
|
|
%z<code> print a double precision VFP reg
|
2004-11-27 12:09:21 +01:00
|
|
|
|
Codes: 0=>Dm, 1=>Dd, 2=>Dn, 3=>multi-list
|
2005-06-08 00:16:52 +02:00
|
|
|
|
|
2006-04-26 17:40:55 +02:00
|
|
|
|
%<bitfield>'c print specified char iff bitfield is all ones
|
|
|
|
|
|
%<bitfield>`c print specified char iff bitfield is all zeroes
|
|
|
|
|
|
%<bitfield>?ab... select from array of values in big endian order
|
2015-08-12 13:45:07 +02:00
|
|
|
|
|
2004-11-27 12:09:21 +01:00
|
|
|
|
%L print as an iWMMXt N/M width field.
|
2005-06-08 00:16:52 +02:00
|
|
|
|
%Z print the Immediate of a WSHUFH instruction.
|
2005-09-02 Paul Brook <paul@codesourcery.com>
bfd/
* libbdf.h: Regenerate.
* bfd-in2.h: Regenerate.
* reloc.c: Add BFD_RELOC_ARM_T32_CP_OFF_IMM and
BFD_RELOC_ARM_T32_CP_OFF_IMM_S2.
gas/
* config/tc-arm.c (encode_arm_cp_address): Use
BFD_RELOC_ARM_T32_CP_OFF_IMM in thumb mode.
(do_iwmmxt_wldstbh): Use BFD_RELOC_ARM_T32_CP_OFF_IMM_S2 in thumb
mode.
(md_assemble): Only allow coprocessor instructions when Thumb-2 is
available.
(cCE, cC3): Define.
(insns): Use them for coprocessor instructions.
(md_pcrel_from_section): Handle BFD_RELOC_ARM_T32_CP_OFF_IMM.
(get_thumb32_insn): New function.
(put_thumb32_insn): New function.
(md_apply_fix): Handle BFD_RELOC_ARM_T32_CP_OFF_IMM and
BFD_RELOC_ARM_T32_CP_OFF_IMM_S2.
gas/testsuite/
* gas/arm/vfp-bad_t2.d, gas/arm/vfp-bad_t2.l, arm/vfp-bad_t2.s,
gas/arm/vfp1_t2.d, gas/arm/vfp1_t2.s, gas/arm/vfp1xD_t2.d,
gas/arm/vfp1xD_t2.s, gas/arm/vfp2_t2.d, gas/arm/vfp2_t2.s): New files.
opcodes/
* arm-dis.c (coprocessor_opcodes): New.
(arm_opcodes, thumb32_opcodes): Remove coprocessor insns.
(print_insn_coprocessor): New function.
(print_insn_arm): Use print_insn_coprocessor. Remove coprocessor
format characters.
(print_insn_thumb32): Use print_insn_coprocessor.
2005-09-02 15:12:45 +02:00
|
|
|
|
%l like 'A' except use byte offsets for 'B' & 'H'
|
bfd/
2006-09-26 Mark Shinwell <shinwell@codesourcery.com>
Joseph Myers <joseph@codesourcery.com>
Ian Lance Taylor <ian@wasabisystems.com>
Ben Elliston <bje@wasabisystems.com>
* archures.c: Add definition for bfd_mach_arm_iWMMXt2.
* cpu-arm.c (processors): Add bfd_mach_arm_iWMMXt2.
(arch_info_struct, bfd_arm_update_notes): Likewise.
(architectures): Likewise.
(bfd_arm_merge_machines): Check for iWMMXt2.
* bfd-in2.h: Rebuild.
gas/
2006-09-26 Mark Shinwell <shinwell@codesourcery.com>
Joseph Myers <joseph@codesourcery.com>
Ian Lance Taylor <ian@wasabisystems.com>
Ben Elliston <bje@wasabisystems.com>
* config/tc-arm.c (arm_cext_iwmmxt2): New.
(enum operand_parse_code): New code OP_RIWR_I32z.
(parse_operands): Handle OP_RIWR_I32z.
(do_iwmmxt_wmerge): New function.
(do_iwmmxt_wldstd): Handle iwmmxt2 case where second operand is
a register.
(do_iwmmxt_wrwrwr_or_imm5): New function.
(insns): Mark instructions as RIWR_I32z as appropriate.
Also add torvsc<b,h,w>, wabs<b,h,w>, wabsdiff<b,h,w>,
waddbhus<l,m>, waddhc, waddwc, waddsubhx, wavg4{r}, wmaddu{x,n},
wmadds{x,n}, wmerge, wmiaxy{n}, wmiawxy{n}, wmul<sm,um>{r},
wmulw<um,sm,l>{r}, wqmiaxy{n}, wqmulm{r}, wqmulwm{r}, wsubaddhx.
(md_begin): Handle IWMMXT2.
(arm_cpus): Add iwmmxt2.
(arm_extensions): Likewise.
(arm_archs): Likewise.
gas/testsuite/
2006-09-26 Mark Shinwell <shinwell@codesourcery.com>
Joseph Myers <joseph@codesourcery.com>
Ian Lance Taylor <ian@wasabisystems.com>
Ben Elliston <bje@wasabisystems.com>
* gas/arm/iwmmxt2.s: New file.
* gas/arm/iwmmxt2.d: New file.
include/opcode/
2006-09-26 Mark Shinwell <shinwell@codesourcery.com>
Joseph Myers <joseph@codesourcery.com>
Ian Lance Taylor <ian@wasabisystems.com>
Ben Elliston <bje@wasabisystems.com>
* arm.h (ARM_CEXT_IWMMXT2, ARM_ARCH_IWMMXT2): Define.
opcodes/
2006-09-26 Mark Shinwell <shinwell@codesourcery.com>
Joseph Myers <joseph@codesourcery.com>
Ian Lance Taylor <ian@wasabisystems.com>
Ben Elliston <bje@wasabisystems.com>
* arm-dis.c (coprocessor_opcodes): The X-qualifier to WMADD may
only be used with the default multiply-add operation, so if N is
set, don't bother printing X. Add new iwmmxt instructions.
(IWMMXT_INSN_COUNT): Update.
(iwmmxt_wwssnames): Qualify "wwss" names at index 2, 6, 10 and 14
with a 'c' suffix.
(print_insn_coprocessor): Check for iWMMXt2. Handle format
specifiers 'r', 'i'.
2006-09-26 14:04:45 +02:00
|
|
|
|
versions.
|
|
|
|
|
|
%i print 5-bit immediate in bits 8,3..0
|
|
|
|
|
|
(print "32" when 0)
|
2009-06-30 13:57:05 +02:00
|
|
|
|
%r print register offset address for wldt/wstr instruction. */
|
2004-11-27 12:09:21 +01:00
|
|
|
|
|
Update soruces to make alpha, arc and arm targets compile cleanly
with -Wc++-compat:
* config/tc-alpha.c: Add casts.
(extended_bfd_reloc_code_real_type): New type. Used to avoid
enumeration conversion warnings.
(struct alpha_fixup, void assemble_insn, assemble_insn)
(assemble_tokens): Use new type.
* ecoff.c: Add casts. (mark_stabs): Use enumeration names.
* config/obj-elf.c: Add cast
* config/tc-arc.c: Add casts.
* config/obj-aout.h (text_section,data_section,bss_section):
Make extern.
* config/obj-elf.c: Add cast.
* config/tc-arm.c: Add casts.
(X, TxCE, TxCE, TxC3, TxC3w, TxCM_, TxCM, TUE, TUF, CE, CL, cCE)
(cCL, C3E, xCM_, nUF, nCE_tag): Change input format to avoid the
need for keywords as arguments.
* ecoff.c: Add casts.
* ecofflink.c: Add casts.
* elf64-alpha.c: Add casts.
(struct alpha_elf_got_entry, struct alpha_elf_reloc_entry): Move
to top level.
(SKIP_HOWTO): Use enum name.
* elf32-arm.c: Add casts.
(elf32_arm_vxworks_bed): Update code to avoid multiple
declarations.
(struct map_stub): Move to top level.
* arc-dis.c Fix casts.
* arc-ext.c: Add casts.
* arm-dis.c (enum opcode_sentinel_enum): Gave name to anonymous
enum.
* emultempl/armelf.em: Add casts.
2009-09-25 21:13:27 +02:00
|
|
|
|
enum opcode_sentinel_enum
|
2009-06-29 10:08:15 +02:00
|
|
|
|
{
|
|
|
|
|
|
SENTINEL_IWMMXT_START = 1,
|
|
|
|
|
|
SENTINEL_IWMMXT_END,
|
|
|
|
|
|
SENTINEL_GENERIC_START
|
|
|
|
|
|
} opcode_sentinels;
|
|
|
|
|
|
|
2009-11-17 18:20:26 +01:00
|
|
|
|
#define UNDEFINED_INSTRUCTION "\t\t; <UNDEFINED> instruction: %0-31x"
|
2009-11-11 10:44:45 +01:00
|
|
|
|
#define UNPREDICTABLE_INSTRUCTION "\t; <UNPREDICTABLE>"
|
2009-06-29 10:08:15 +02:00
|
|
|
|
|
2005-09-02 Paul Brook <paul@codesourcery.com>
bfd/
* libbdf.h: Regenerate.
* bfd-in2.h: Regenerate.
* reloc.c: Add BFD_RELOC_ARM_T32_CP_OFF_IMM and
BFD_RELOC_ARM_T32_CP_OFF_IMM_S2.
gas/
* config/tc-arm.c (encode_arm_cp_address): Use
BFD_RELOC_ARM_T32_CP_OFF_IMM in thumb mode.
(do_iwmmxt_wldstbh): Use BFD_RELOC_ARM_T32_CP_OFF_IMM_S2 in thumb
mode.
(md_assemble): Only allow coprocessor instructions when Thumb-2 is
available.
(cCE, cC3): Define.
(insns): Use them for coprocessor instructions.
(md_pcrel_from_section): Handle BFD_RELOC_ARM_T32_CP_OFF_IMM.
(get_thumb32_insn): New function.
(put_thumb32_insn): New function.
(md_apply_fix): Handle BFD_RELOC_ARM_T32_CP_OFF_IMM and
BFD_RELOC_ARM_T32_CP_OFF_IMM_S2.
gas/testsuite/
* gas/arm/vfp-bad_t2.d, gas/arm/vfp-bad_t2.l, arm/vfp-bad_t2.s,
gas/arm/vfp1_t2.d, gas/arm/vfp1_t2.s, gas/arm/vfp1xD_t2.d,
gas/arm/vfp1xD_t2.s, gas/arm/vfp2_t2.d, gas/arm/vfp2_t2.s): New files.
opcodes/
* arm-dis.c (coprocessor_opcodes): New.
(arm_opcodes, thumb32_opcodes): Remove coprocessor insns.
(print_insn_coprocessor): New function.
(print_insn_arm): Use print_insn_coprocessor. Remove coprocessor
format characters.
(print_insn_thumb32): Use print_insn_coprocessor.
2005-09-02 15:12:45 +02:00
|
|
|
|
/* Common coprocessor opcodes shared between Arm and Thumb-2. */
|
2004-11-27 12:09:21 +01:00
|
|
|
|
|
2005-09-02 Paul Brook <paul@codesourcery.com>
bfd/
* libbdf.h: Regenerate.
* bfd-in2.h: Regenerate.
* reloc.c: Add BFD_RELOC_ARM_T32_CP_OFF_IMM and
BFD_RELOC_ARM_T32_CP_OFF_IMM_S2.
gas/
* config/tc-arm.c (encode_arm_cp_address): Use
BFD_RELOC_ARM_T32_CP_OFF_IMM in thumb mode.
(do_iwmmxt_wldstbh): Use BFD_RELOC_ARM_T32_CP_OFF_IMM_S2 in thumb
mode.
(md_assemble): Only allow coprocessor instructions when Thumb-2 is
available.
(cCE, cC3): Define.
(insns): Use them for coprocessor instructions.
(md_pcrel_from_section): Handle BFD_RELOC_ARM_T32_CP_OFF_IMM.
(get_thumb32_insn): New function.
(put_thumb32_insn): New function.
(md_apply_fix): Handle BFD_RELOC_ARM_T32_CP_OFF_IMM and
BFD_RELOC_ARM_T32_CP_OFF_IMM_S2.
gas/testsuite/
* gas/arm/vfp-bad_t2.d, gas/arm/vfp-bad_t2.l, arm/vfp-bad_t2.s,
gas/arm/vfp1_t2.d, gas/arm/vfp1_t2.s, gas/arm/vfp1xD_t2.d,
gas/arm/vfp1xD_t2.s, gas/arm/vfp2_t2.d, gas/arm/vfp2_t2.s): New files.
opcodes/
* arm-dis.c (coprocessor_opcodes): New.
(arm_opcodes, thumb32_opcodes): Remove coprocessor insns.
(print_insn_coprocessor): New function.
(print_insn_arm): Use print_insn_coprocessor. Remove coprocessor
format characters.
(print_insn_thumb32): Use print_insn_coprocessor.
2005-09-02 15:12:45 +02:00
|
|
|
|
static const struct opcode32 coprocessor_opcodes[] =
|
2004-11-27 12:09:21 +01:00
|
|
|
|
{
|
|
|
|
|
|
/* XScale instructions. */
|
2015-03-24 07:08:08 +01:00
|
|
|
|
{ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
|
|
|
|
|
|
0x0e200010, 0x0fff0ff0,
|
|
|
|
|
|
"mia%c\tacc0, %0-3r, %12-15r"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
|
|
|
|
|
|
0x0e280010, 0x0fff0ff0,
|
|
|
|
|
|
"miaph%c\tacc0, %0-3r, %12-15r"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
|
|
|
|
|
|
0x0e2c0010, 0x0ffc0ff0, "mia%17'T%17`B%16'T%16`B%c\tacc0, %0-3r, %12-15r"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
|
|
|
|
|
|
0x0c400000, 0x0ff00fff, "mar%c\tacc0, %12-15r, %16-19r"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
|
|
|
|
|
|
0x0c500000, 0x0ff00fff, "mra%c\t%12-15r, %16-19r, acc0"},
|
2009-06-29 10:08:15 +02:00
|
|
|
|
|
2004-11-27 12:09:21 +01:00
|
|
|
|
/* Intel Wireless MMX technology instructions. */
|
2015-03-24 07:08:08 +01:00
|
|
|
|
{ARM_FEATURE_CORE_LOW (0), SENTINEL_IWMMXT_START, 0, "" },
|
|
|
|
|
|
{ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT),
|
|
|
|
|
|
0x0e130130, 0x0f3f0fff, "tandc%22-23w%c\t%12-15r"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
|
|
|
|
|
|
0x0e400010, 0x0ff00f3f, "tbcst%6-7w%c\t%16-19g, %12-15r"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
|
|
|
|
|
|
0x0e130170, 0x0f3f0ff8, "textrc%22-23w%c\t%12-15r, #%0-2d"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
|
|
|
|
|
|
0x0e100070, 0x0f300ff0, "textrm%3?su%22-23w%c\t%12-15r, %16-19g, #%0-2d"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
|
|
|
|
|
|
0x0e600010, 0x0ff00f38, "tinsr%6-7w%c\t%16-19g, %12-15r, #%0-2d"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
|
|
|
|
|
|
0x0e000110, 0x0ff00fff, "tmcr%c\t%16-19G, %12-15r"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
|
|
|
|
|
|
0x0c400000, 0x0ff00ff0, "tmcrr%c\t%0-3g, %12-15r, %16-19r"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
|
|
|
|
|
|
0x0e2c0010, 0x0ffc0e10, "tmia%17?tb%16?tb%c\t%5-8g, %0-3r, %12-15r"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
|
|
|
|
|
|
0x0e200010, 0x0fff0e10, "tmia%c\t%5-8g, %0-3r, %12-15r"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
|
|
|
|
|
|
0x0e280010, 0x0fff0e10, "tmiaph%c\t%5-8g, %0-3r, %12-15r"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
|
|
|
|
|
|
0x0e100030, 0x0f300fff, "tmovmsk%22-23w%c\t%12-15r, %16-19g"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
|
|
|
|
|
|
0x0e100110, 0x0ff00ff0, "tmrc%c\t%12-15r, %16-19G"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
|
|
|
|
|
|
0x0c500000, 0x0ff00ff0, "tmrrc%c\t%12-15r, %16-19r, %0-3g"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
|
|
|
|
|
|
0x0e130150, 0x0f3f0fff, "torc%22-23w%c\t%12-15r"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
|
|
|
|
|
|
0x0e120190, 0x0f3f0fff, "torvsc%22-23w%c\t%12-15r"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
|
|
|
|
|
|
0x0e2001c0, 0x0f300fff, "wabs%22-23w%c\t%12-15g, %16-19g"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
|
|
|
|
|
|
0x0e0001c0, 0x0f300fff, "wacc%22-23w%c\t%12-15g, %16-19g"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
|
|
|
|
|
|
0x0e000180, 0x0f000ff0, "wadd%20-23w%c\t%12-15g, %16-19g, %0-3g"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
|
|
|
|
|
|
0x0e2001a0, 0x0fb00ff0, "waddbhus%22?ml%c\t%12-15g, %16-19g, %0-3g"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
|
|
|
|
|
|
0x0ea001a0, 0x0ff00ff0, "waddsubhx%c\t%12-15g, %16-19g, %0-3g"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
|
|
|
|
|
|
0x0e000020, 0x0f800ff0, "waligni%c\t%12-15g, %16-19g, %0-3g, #%20-22d"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
|
|
|
|
|
|
0x0e800020, 0x0fc00ff0, "walignr%20-21d%c\t%12-15g, %16-19g, %0-3g"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
|
|
|
|
|
|
0x0e200000, 0x0fe00ff0, "wand%20'n%c\t%12-15g, %16-19g, %0-3g"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
|
|
|
|
|
|
0x0e800000, 0x0fa00ff0, "wavg2%22?hb%20'r%c\t%12-15g, %16-19g, %0-3g"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
|
|
|
|
|
|
0x0e400000, 0x0fe00ff0, "wavg4%20'r%c\t%12-15g, %16-19g, %0-3g"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
|
|
|
|
|
|
0x0e000060, 0x0f300ff0, "wcmpeq%22-23w%c\t%12-15g, %16-19g, %0-3g"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
|
|
|
|
|
|
0x0e100060, 0x0f100ff0, "wcmpgt%21?su%22-23w%c\t%12-15g, %16-19g, %0-3g"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
|
|
|
|
|
|
0xfc500100, 0xfe500f00, "wldrd\t%12-15g, %r"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
|
|
|
|
|
|
0xfc100100, 0xfe500f00, "wldrw\t%12-15G, %A"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
|
|
|
|
|
|
0x0c100000, 0x0e100e00, "wldr%L%c\t%12-15g, %l"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
|
|
|
|
|
|
0x0e400100, 0x0fc00ff0, "wmac%21?su%20'z%c\t%12-15g, %16-19g, %0-3g"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
|
|
|
|
|
|
0x0e800100, 0x0fc00ff0, "wmadd%21?su%20'x%c\t%12-15g, %16-19g, %0-3g"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
|
|
|
|
|
|
0x0ec00100, 0x0fd00ff0, "wmadd%21?sun%c\t%12-15g, %16-19g, %0-3g"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
|
|
|
|
|
|
0x0e000160, 0x0f100ff0, "wmax%21?su%22-23w%c\t%12-15g, %16-19g, %0-3g"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
|
|
|
|
|
|
0x0e000080, 0x0f100fe0, "wmerge%c\t%12-15g, %16-19g, %0-3g, #%21-23d"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
|
|
|
|
|
|
0x0e0000a0, 0x0f800ff0, "wmia%21?tb%20?tb%22'n%c\t%12-15g, %16-19g, %0-3g"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
|
|
|
|
|
|
0x0e800120, 0x0f800ff0,
|
|
|
|
|
|
"wmiaw%21?tb%20?tb%22'n%c\t%12-15g, %16-19g, %0-3g"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
|
|
|
|
|
|
0x0e100160, 0x0f100ff0, "wmin%21?su%22-23w%c\t%12-15g, %16-19g, %0-3g"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
|
|
|
|
|
|
0x0e000100, 0x0fc00ff0, "wmul%21?su%20?ml%23'r%c\t%12-15g, %16-19g, %0-3g"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
|
|
|
|
|
|
0x0ed00100, 0x0fd00ff0, "wmul%21?sumr%c\t%12-15g, %16-19g, %0-3g"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
|
|
|
|
|
|
0x0ee000c0, 0x0fe00ff0, "wmulwsm%20`r%c\t%12-15g, %16-19g, %0-3g"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
|
|
|
|
|
|
0x0ec000c0, 0x0fe00ff0, "wmulwum%20`r%c\t%12-15g, %16-19g, %0-3g"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
|
|
|
|
|
|
0x0eb000c0, 0x0ff00ff0, "wmulwl%c\t%12-15g, %16-19g, %0-3g"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
|
|
|
|
|
|
0x0e8000a0, 0x0f800ff0,
|
|
|
|
|
|
"wqmia%21?tb%20?tb%22'n%c\t%12-15g, %16-19g, %0-3g"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
|
|
|
|
|
|
0x0e100080, 0x0fd00ff0, "wqmulm%21'r%c\t%12-15g, %16-19g, %0-3g"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
|
|
|
|
|
|
0x0ec000e0, 0x0fd00ff0, "wqmulwm%21'r%c\t%12-15g, %16-19g, %0-3g"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
|
|
|
|
|
|
0x0e000000, 0x0ff00ff0, "wor%c\t%12-15g, %16-19g, %0-3g"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
|
|
|
|
|
|
0x0e000080, 0x0f000ff0, "wpack%20-23w%c\t%12-15g, %16-19g, %0-3g"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
|
|
|
|
|
|
0xfe300040, 0xff300ef0, "wror%22-23w\t%12-15g, %16-19g, #%i"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
|
|
|
|
|
|
0x0e300040, 0x0f300ff0, "wror%22-23w%c\t%12-15g, %16-19g, %0-3g"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
|
|
|
|
|
|
0x0e300140, 0x0f300ff0, "wror%22-23wg%c\t%12-15g, %16-19g, %0-3G"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
|
|
|
|
|
|
0x0e000120, 0x0fa00ff0, "wsad%22?hb%20'z%c\t%12-15g, %16-19g, %0-3g"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
|
|
|
|
|
|
0x0e0001e0, 0x0f000ff0, "wshufh%c\t%12-15g, %16-19g, #%Z"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
|
|
|
|
|
|
0xfe100040, 0xff300ef0, "wsll%22-23w\t%12-15g, %16-19g, #%i"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
|
|
|
|
|
|
0x0e100040, 0x0f300ff0, "wsll%22-23w%8'g%c\t%12-15g, %16-19g, %0-3g"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
|
|
|
|
|
|
0x0e100148, 0x0f300ffc, "wsll%22-23w%8'g%c\t%12-15g, %16-19g, %0-3G"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
|
|
|
|
|
|
0xfe000040, 0xff300ef0, "wsra%22-23w\t%12-15g, %16-19g, #%i"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
|
|
|
|
|
|
0x0e000040, 0x0f300ff0, "wsra%22-23w%8'g%c\t%12-15g, %16-19g, %0-3g"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
|
|
|
|
|
|
0x0e000148, 0x0f300ffc, "wsra%22-23w%8'g%c\t%12-15g, %16-19g, %0-3G"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
|
|
|
|
|
|
0xfe200040, 0xff300ef0, "wsrl%22-23w\t%12-15g, %16-19g, #%i"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
|
|
|
|
|
|
0x0e200040, 0x0f300ff0, "wsrl%22-23w%8'g%c\t%12-15g, %16-19g, %0-3g"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
|
|
|
|
|
|
0x0e200148, 0x0f300ffc, "wsrl%22-23w%8'g%c\t%12-15g, %16-19g, %0-3G"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
|
|
|
|
|
|
0xfc400100, 0xfe500f00, "wstrd\t%12-15g, %r"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
|
|
|
|
|
|
0xfc000100, 0xfe500f00, "wstrw\t%12-15G, %A"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
|
|
|
|
|
|
0x0c000000, 0x0e100e00, "wstr%L%c\t%12-15g, %l"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
|
|
|
|
|
|
0x0e0001a0, 0x0f000ff0, "wsub%20-23w%c\t%12-15g, %16-19g, %0-3g"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
|
|
|
|
|
|
0x0ed001c0, 0x0ff00ff0, "wsubaddhx%c\t%12-15g, %16-19g, %0-3g"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
|
|
|
|
|
|
0x0e1001c0, 0x0f300ff0, "wabsdiff%22-23w%c\t%12-15g, %16-19g, %0-3g"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
|
|
|
|
|
|
0x0e0000c0, 0x0fd00fff, "wunpckeh%21?sub%c\t%12-15g, %16-19g"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
|
|
|
|
|
|
0x0e4000c0, 0x0fd00fff, "wunpckeh%21?suh%c\t%12-15g, %16-19g"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
|
|
|
|
|
|
0x0e8000c0, 0x0fd00fff, "wunpckeh%21?suw%c\t%12-15g, %16-19g"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
|
|
|
|
|
|
0x0e0000e0, 0x0f100fff, "wunpckel%21?su%22-23w%c\t%12-15g, %16-19g"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
|
|
|
|
|
|
0x0e1000c0, 0x0f300ff0, "wunpckih%22-23w%c\t%12-15g, %16-19g, %0-3g"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
|
|
|
|
|
|
0x0e1000e0, 0x0f300ff0, "wunpckil%22-23w%c\t%12-15g, %16-19g, %0-3g"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
|
|
|
|
|
|
0x0e100000, 0x0ff00ff0, "wxor%c\t%12-15g, %16-19g, %0-3g"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_LOW (0),
|
|
|
|
|
|
SENTINEL_IWMMXT_END, 0, "" },
|
2004-11-27 12:09:21 +01:00
|
|
|
|
|
2009-06-30 13:57:05 +02:00
|
|
|
|
/* Floating point coprocessor (FPA) instructions. */
|
2015-03-24 07:08:08 +01:00
|
|
|
|
{ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
|
|
|
|
|
|
0x0e000100, 0x0ff08f10, "adf%c%P%R\t%12-14f, %16-18f, %0-3f"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
|
|
|
|
|
|
0x0e100100, 0x0ff08f10, "muf%c%P%R\t%12-14f, %16-18f, %0-3f"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
|
|
|
|
|
|
0x0e200100, 0x0ff08f10, "suf%c%P%R\t%12-14f, %16-18f, %0-3f"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
|
|
|
|
|
|
0x0e300100, 0x0ff08f10, "rsf%c%P%R\t%12-14f, %16-18f, %0-3f"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
|
|
|
|
|
|
0x0e400100, 0x0ff08f10, "dvf%c%P%R\t%12-14f, %16-18f, %0-3f"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
|
|
|
|
|
|
0x0e500100, 0x0ff08f10, "rdf%c%P%R\t%12-14f, %16-18f, %0-3f"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
|
|
|
|
|
|
0x0e600100, 0x0ff08f10, "pow%c%P%R\t%12-14f, %16-18f, %0-3f"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
|
|
|
|
|
|
0x0e700100, 0x0ff08f10, "rpw%c%P%R\t%12-14f, %16-18f, %0-3f"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
|
|
|
|
|
|
0x0e800100, 0x0ff08f10, "rmf%c%P%R\t%12-14f, %16-18f, %0-3f"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
|
|
|
|
|
|
0x0e900100, 0x0ff08f10, "fml%c%P%R\t%12-14f, %16-18f, %0-3f"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
|
|
|
|
|
|
0x0ea00100, 0x0ff08f10, "fdv%c%P%R\t%12-14f, %16-18f, %0-3f"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
|
|
|
|
|
|
0x0eb00100, 0x0ff08f10, "frd%c%P%R\t%12-14f, %16-18f, %0-3f"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
|
|
|
|
|
|
0x0ec00100, 0x0ff08f10, "pol%c%P%R\t%12-14f, %16-18f, %0-3f"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
|
|
|
|
|
|
0x0e008100, 0x0ff08f10, "mvf%c%P%R\t%12-14f, %0-3f"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
|
|
|
|
|
|
0x0e108100, 0x0ff08f10, "mnf%c%P%R\t%12-14f, %0-3f"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
|
|
|
|
|
|
0x0e208100, 0x0ff08f10, "abs%c%P%R\t%12-14f, %0-3f"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
|
|
|
|
|
|
0x0e308100, 0x0ff08f10, "rnd%c%P%R\t%12-14f, %0-3f"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
|
|
|
|
|
|
0x0e408100, 0x0ff08f10, "sqt%c%P%R\t%12-14f, %0-3f"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
|
|
|
|
|
|
0x0e508100, 0x0ff08f10, "log%c%P%R\t%12-14f, %0-3f"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
|
|
|
|
|
|
0x0e608100, 0x0ff08f10, "lgn%c%P%R\t%12-14f, %0-3f"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
|
|
|
|
|
|
0x0e708100, 0x0ff08f10, "exp%c%P%R\t%12-14f, %0-3f"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
|
|
|
|
|
|
0x0e808100, 0x0ff08f10, "sin%c%P%R\t%12-14f, %0-3f"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
|
|
|
|
|
|
0x0e908100, 0x0ff08f10, "cos%c%P%R\t%12-14f, %0-3f"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
|
|
|
|
|
|
0x0ea08100, 0x0ff08f10, "tan%c%P%R\t%12-14f, %0-3f"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
|
|
|
|
|
|
0x0eb08100, 0x0ff08f10, "asn%c%P%R\t%12-14f, %0-3f"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
|
|
|
|
|
|
0x0ec08100, 0x0ff08f10, "acs%c%P%R\t%12-14f, %0-3f"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
|
|
|
|
|
|
0x0ed08100, 0x0ff08f10, "atn%c%P%R\t%12-14f, %0-3f"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
|
|
|
|
|
|
0x0ee08100, 0x0ff08f10, "urd%c%P%R\t%12-14f, %0-3f"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
|
|
|
|
|
|
0x0ef08100, 0x0ff08f10, "nrm%c%P%R\t%12-14f, %0-3f"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
|
|
|
|
|
|
0x0e000110, 0x0ff00f1f, "flt%c%P%R\t%16-18f, %12-15r"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
|
|
|
|
|
|
0x0e100110, 0x0fff0f98, "fix%c%R\t%12-15r, %0-2f"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
|
|
|
|
|
|
0x0e200110, 0x0fff0fff, "wfs%c\t%12-15r"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
|
|
|
|
|
|
0x0e300110, 0x0fff0fff, "rfs%c\t%12-15r"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
|
|
|
|
|
|
0x0e400110, 0x0fff0fff, "wfc%c\t%12-15r"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
|
|
|
|
|
|
0x0e500110, 0x0fff0fff, "rfc%c\t%12-15r"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
|
|
|
|
|
|
0x0e90f110, 0x0ff8fff0, "cmf%c\t%16-18f, %0-3f"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
|
|
|
|
|
|
0x0eb0f110, 0x0ff8fff0, "cnf%c\t%16-18f, %0-3f"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
|
|
|
|
|
|
0x0ed0f110, 0x0ff8fff0, "cmfe%c\t%16-18f, %0-3f"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
|
|
|
|
|
|
0x0ef0f110, 0x0ff8fff0, "cnfe%c\t%16-18f, %0-3f"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
|
|
|
|
|
|
0x0c000100, 0x0e100f00, "stf%c%Q\t%12-14f, %A"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
|
|
|
|
|
|
0x0c100100, 0x0e100f00, "ldf%c%Q\t%12-14f, %A"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (FPU_FPA_EXT_V2),
|
|
|
|
|
|
0x0c000200, 0x0e100f00, "sfm%c\t%12-14f, %F, %A"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (FPU_FPA_EXT_V2),
|
|
|
|
|
|
0x0c100200, 0x0e100f00, "lfm%c\t%12-14f, %F, %A"},
|
2004-11-27 12:09:21 +01:00
|
|
|
|
|
2016-05-10 16:01:53 +02:00
|
|
|
|
/* ARMv8-M Mainline Security Extensions instructions. */
|
|
|
|
|
|
{ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M_MAIN),
|
|
|
|
|
|
0xec300a00, 0xfff0ffff, "vlldm\t%16-19r"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M_MAIN),
|
|
|
|
|
|
0xec200a00, 0xfff0ffff, "vlstm\t%16-19r"},
|
|
|
|
|
|
|
2009-06-30 13:57:05 +02:00
|
|
|
|
/* Register load/store. */
|
2015-03-24 07:08:08 +01:00
|
|
|
|
{ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
|
|
|
|
|
|
0x0d2d0b00, 0x0fbf0f01, "vpush%c\t%B"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
|
|
|
|
|
|
0x0d200b00, 0x0fb00f01, "vstmdb%c\t%16-19r!, %B"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
|
|
|
|
|
|
0x0d300b00, 0x0fb00f01, "vldmdb%c\t%16-19r!, %B"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
|
|
|
|
|
|
0x0c800b00, 0x0f900f01, "vstmia%c\t%16-19r%21'!, %B"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
|
|
|
|
|
|
0x0cbd0b00, 0x0fbf0f01, "vpop%c\t%B"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
|
|
|
|
|
|
0x0c900b00, 0x0f900f01, "vldmia%c\t%16-19r%21'!, %B"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
|
|
|
|
|
|
0x0d000b00, 0x0f300f00, "vstr%c\t%12-15,22D, %A"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
|
|
|
|
|
|
0x0d100b00, 0x0f300f00, "vldr%c\t%12-15,22D, %A"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
|
|
|
|
|
|
0x0d2d0a00, 0x0fbf0f00, "vpush%c\t%y3"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
|
|
|
|
|
|
0x0d200a00, 0x0fb00f00, "vstmdb%c\t%16-19r!, %y3"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
|
|
|
|
|
|
0x0d300a00, 0x0fb00f00, "vldmdb%c\t%16-19r!, %y3"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
|
|
|
|
|
|
0x0c800a00, 0x0f900f00, "vstmia%c\t%16-19r%21'!, %y3"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
|
|
|
|
|
|
0x0cbd0a00, 0x0fbf0f00, "vpop%c\t%y3"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
|
|
|
|
|
|
0x0c900a00, 0x0f900f00, "vldmia%c\t%16-19r%21'!, %y3"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
|
|
|
|
|
|
0x0d000a00, 0x0f300f00, "vstr%c\t%y1, %A"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
|
|
|
|
|
|
0x0d100a00, 0x0f300f00, "vldr%c\t%y1, %A"},
|
|
|
|
|
|
|
|
|
|
|
|
{ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
|
|
|
|
|
|
0x0d200b01, 0x0fb00f01, "fstmdbx%c\t%16-19r!, %z3\t;@ Deprecated"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
|
|
|
|
|
|
0x0d300b01, 0x0fb00f01, "fldmdbx%c\t%16-19r!, %z3\t;@ Deprecated"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
|
|
|
|
|
|
0x0c800b01, 0x0f900f01, "fstmiax%c\t%16-19r%21'!, %z3\t;@ Deprecated"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
|
|
|
|
|
|
0x0c900b01, 0x0f900f01, "fldmiax%c\t%16-19r%21'!, %z3\t;@ Deprecated"},
|
2006-04-26 17:40:55 +02:00
|
|
|
|
|
2009-06-30 13:57:05 +02:00
|
|
|
|
/* Data transfer between ARM and NEON registers. */
|
2015-03-24 07:08:08 +01:00
|
|
|
|
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
|
|
|
|
|
|
0x0e800b10, 0x0ff00f70, "vdup%c.32\t%16-19,7D, %12-15r"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
|
|
|
|
|
|
0x0e800b30, 0x0ff00f70, "vdup%c.16\t%16-19,7D, %12-15r"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
|
|
|
|
|
|
0x0ea00b10, 0x0ff00f70, "vdup%c.32\t%16-19,7Q, %12-15r"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
|
|
|
|
|
|
0x0ea00b30, 0x0ff00f70, "vdup%c.16\t%16-19,7Q, %12-15r"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
|
|
|
|
|
|
0x0ec00b10, 0x0ff00f70, "vdup%c.8\t%16-19,7D, %12-15r"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
|
|
|
|
|
|
0x0ee00b10, 0x0ff00f70, "vdup%c.8\t%16-19,7Q, %12-15r"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
|
|
|
|
|
|
0x0c400b10, 0x0ff00fd0, "vmov%c\t%0-3,5D, %12-15r, %16-19r"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
|
|
|
|
|
|
0x0c500b10, 0x0ff00fd0, "vmov%c\t%12-15r, %16-19r, %0-3,5D"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
|
|
|
|
|
|
0x0e000b10, 0x0fd00f70, "vmov%c.32\t%16-19,7D[%21d], %12-15r"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
|
|
|
|
|
|
0x0e100b10, 0x0f500f70, "vmov%c.32\t%12-15r, %16-19,7D[%21d]"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
|
|
|
|
|
|
0x0e000b30, 0x0fd00f30, "vmov%c.16\t%16-19,7D[%6,21d], %12-15r"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
|
|
|
|
|
|
0x0e100b30, 0x0f500f30, "vmov%c.%23?us16\t%12-15r, %16-19,7D[%6,21d]"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
|
|
|
|
|
|
0x0e400b10, 0x0fd00f10, "vmov%c.8\t%16-19,7D[%5,6,21d], %12-15r"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
|
|
|
|
|
|
0x0e500b10, 0x0f500f10, "vmov%c.%23?us8\t%12-15r, %16-19,7D[%5,6,21d]"},
|
2008-11-18 16:45:05 +01:00
|
|
|
|
/* Half-precision conversion instructions. */
|
2015-03-24 07:08:08 +01:00
|
|
|
|
{ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
|
|
|
|
|
|
0x0eb20b40, 0x0fbf0f50, "vcvt%7?tb%c.f64.f16\t%z1, %y0"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
|
|
|
|
|
|
0x0eb30b40, 0x0fbf0f50, "vcvt%7?tb%c.f16.f64\t%y1, %z0"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16),
|
|
|
|
|
|
0x0eb20a40, 0x0fbf0f50, "vcvt%7?tb%c.f32.f16\t%y1, %y0"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16),
|
|
|
|
|
|
0x0eb30a40, 0x0fbf0f50, "vcvt%7?tb%c.f16.f32\t%y1, %y0"},
|
2006-04-26 17:40:55 +02:00
|
|
|
|
|
2009-06-30 13:57:05 +02:00
|
|
|
|
/* Floating point coprocessor (VFP) instructions. */
|
2015-03-24 07:08:08 +01:00
|
|
|
|
{ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
|
|
|
|
|
|
0x0ee00a10, 0x0fff0fff, "vmsr%c\tfpsid, %12-15r"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
|
|
|
|
|
|
0x0ee10a10, 0x0fff0fff, "vmsr%c\tfpscr, %12-15r"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
|
|
|
|
|
|
0x0ee60a10, 0x0fff0fff, "vmsr%c\tmvfr1, %12-15r"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
|
|
|
|
|
|
0x0ee70a10, 0x0fff0fff, "vmsr%c\tmvfr0, %12-15r"},
|
2017-07-04 17:18:47 +02:00
|
|
|
|
{ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
|
|
|
|
|
|
0x0ee50a10, 0x0fff0fff, "vmsr%c\tmvfr2, %12-15r"},
|
2015-03-24 07:08:08 +01:00
|
|
|
|
{ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
|
|
|
|
|
|
0x0ee80a10, 0x0fff0fff, "vmsr%c\tfpexc, %12-15r"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
|
|
|
|
|
|
0x0ee90a10, 0x0fff0fff, "vmsr%c\tfpinst, %12-15r\t@ Impl def"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
|
|
|
|
|
|
0x0eea0a10, 0x0fff0fff, "vmsr%c\tfpinst2, %12-15r\t@ Impl def"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
|
|
|
|
|
|
0x0ef00a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpsid"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
|
|
|
|
|
|
0x0ef1fa10, 0x0fffffff, "vmrs%c\tAPSR_nzcv, fpscr"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
|
|
|
|
|
|
0x0ef10a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpscr"},
|
2017-07-04 17:18:47 +02:00
|
|
|
|
{ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
|
|
|
|
|
|
0x0ef50a10, 0x0fff0fff, "vmrs%c\t%12-15r, mvfr2"},
|
2015-03-24 07:08:08 +01:00
|
|
|
|
{ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
|
|
|
|
|
|
0x0ef60a10, 0x0fff0fff, "vmrs%c\t%12-15r, mvfr1"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
|
|
|
|
|
|
0x0ef70a10, 0x0fff0fff, "vmrs%c\t%12-15r, mvfr0"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
|
|
|
|
|
|
0x0ef80a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpexc"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
|
|
|
|
|
|
0x0ef90a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpinst\t@ Impl def"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
|
|
|
|
|
|
0x0efa0a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpinst2\t@ Impl def"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
|
|
|
|
|
|
0x0e000b10, 0x0fd00fff, "vmov%c.32\t%z2[%21d], %12-15r"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
|
|
|
|
|
|
0x0e100b10, 0x0fd00fff, "vmov%c.32\t%12-15r, %z2[%21d]"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
|
|
|
|
|
|
0x0ee00a10, 0x0ff00fff, "vmsr%c\t<impl def %16-19x>, %12-15r"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
|
|
|
|
|
|
0x0ef00a10, 0x0ff00fff, "vmrs%c\t%12-15r, <impl def %16-19x>"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
|
|
|
|
|
|
0x0e000a10, 0x0ff00f7f, "vmov%c\t%y2, %12-15r"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
|
|
|
|
|
|
0x0e100a10, 0x0ff00f7f, "vmov%c\t%12-15r, %y2"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
|
|
|
|
|
|
0x0eb50a40, 0x0fbf0f70, "vcmp%7'e%c.f32\t%y1, #0.0"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
|
|
|
|
|
|
0x0eb50b40, 0x0fbf0f70, "vcmp%7'e%c.f64\t%z1, #0.0"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
|
|
|
|
|
|
0x0eb00a40, 0x0fbf0fd0, "vmov%c.f32\t%y1, %y0"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
|
|
|
|
|
|
0x0eb00ac0, 0x0fbf0fd0, "vabs%c.f32\t%y1, %y0"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
|
|
|
|
|
|
0x0eb00b40, 0x0fbf0fd0, "vmov%c.f64\t%z1, %z0"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
|
|
|
|
|
|
0x0eb00bc0, 0x0fbf0fd0, "vabs%c.f64\t%z1, %z0"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
|
|
|
|
|
|
0x0eb10a40, 0x0fbf0fd0, "vneg%c.f32\t%y1, %y0"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
|
|
|
|
|
|
0x0eb10ac0, 0x0fbf0fd0, "vsqrt%c.f32\t%y1, %y0"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
|
|
|
|
|
|
0x0eb10b40, 0x0fbf0fd0, "vneg%c.f64\t%z1, %z0"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
|
|
|
|
|
|
0x0eb10bc0, 0x0fbf0fd0, "vsqrt%c.f64\t%z1, %z0"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
|
|
|
|
|
|
0x0eb70ac0, 0x0fbf0fd0, "vcvt%c.f64.f32\t%z1, %y0"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
|
|
|
|
|
|
0x0eb70bc0, 0x0fbf0fd0, "vcvt%c.f32.f64\t%y1, %z0"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
|
|
|
|
|
|
0x0eb80a40, 0x0fbf0f50, "vcvt%c.f32.%7?su32\t%y1, %y0"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
|
|
|
|
|
|
0x0eb80b40, 0x0fbf0f50, "vcvt%c.f64.%7?su32\t%z1, %y0"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
|
|
|
|
|
|
0x0eb40a40, 0x0fbf0f50, "vcmp%7'e%c.f32\t%y1, %y0"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
|
|
|
|
|
|
0x0eb40b40, 0x0fbf0f50, "vcmp%7'e%c.f64\t%z1, %z0"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (FPU_VFP_EXT_V3xD),
|
|
|
|
|
|
0x0eba0a40, 0x0fbe0f50, "vcvt%c.f32.%16?us%7?31%7?26\t%y1, %y1, #%5,0-3k"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (FPU_VFP_EXT_V3),
|
|
|
|
|
|
0x0eba0b40, 0x0fbe0f50, "vcvt%c.f64.%16?us%7?31%7?26\t%z1, %z1, #%5,0-3k"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
|
|
|
|
|
|
0x0ebc0a40, 0x0fbe0f50, "vcvt%7`r%c.%16?su32.f32\t%y1, %y0"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
|
|
|
|
|
|
0x0ebc0b40, 0x0fbe0f50, "vcvt%7`r%c.%16?su32.f64\t%y1, %z0"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (FPU_VFP_EXT_V3xD),
|
|
|
|
|
|
0x0ebe0a40, 0x0fbe0f50, "vcvt%c.%16?us%7?31%7?26.f32\t%y1, %y1, #%5,0-3k"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (FPU_VFP_EXT_V3),
|
|
|
|
|
|
0x0ebe0b40, 0x0fbe0f50, "vcvt%c.%16?us%7?31%7?26.f64\t%z1, %z1, #%5,0-3k"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
|
|
|
|
|
|
0x0c500b10, 0x0fb00ff0, "vmov%c\t%12-15r, %16-19r, %z0"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (FPU_VFP_EXT_V3xD),
|
2015-07-16 17:38:48 +02:00
|
|
|
|
0x0eb00a00, 0x0fb00ff0, "vmov%c.f32\t%y1, #%0-3,16-19E"},
|
2015-03-24 07:08:08 +01:00
|
|
|
|
{ARM_FEATURE_COPROC (FPU_VFP_EXT_V3),
|
2015-07-16 17:38:48 +02:00
|
|
|
|
0x0eb00b00, 0x0fb00ff0, "vmov%c.f64\t%z1, #%0-3,16-19E"},
|
2015-03-24 07:08:08 +01:00
|
|
|
|
{ARM_FEATURE_COPROC (FPU_VFP_EXT_V2),
|
|
|
|
|
|
0x0c400a10, 0x0ff00fd0, "vmov%c\t%y4, %12-15r, %16-19r"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (FPU_VFP_EXT_V2),
|
|
|
|
|
|
0x0c400b10, 0x0ff00fd0, "vmov%c\t%z0, %12-15r, %16-19r"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (FPU_VFP_EXT_V2),
|
|
|
|
|
|
0x0c500a10, 0x0ff00fd0, "vmov%c\t%12-15r, %16-19r, %y4"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
|
|
|
|
|
|
0x0e000a00, 0x0fb00f50, "vmla%c.f32\t%y1, %y2, %y0"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
|
|
|
|
|
|
0x0e000a40, 0x0fb00f50, "vmls%c.f32\t%y1, %y2, %y0"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
|
|
|
|
|
|
0x0e000b00, 0x0fb00f50, "vmla%c.f64\t%z1, %z2, %z0"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
|
|
|
|
|
|
0x0e000b40, 0x0fb00f50, "vmls%c.f64\t%z1, %z2, %z0"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
|
|
|
|
|
|
0x0e100a00, 0x0fb00f50, "vnmls%c.f32\t%y1, %y2, %y0"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
|
|
|
|
|
|
0x0e100a40, 0x0fb00f50, "vnmla%c.f32\t%y1, %y2, %y0"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
|
|
|
|
|
|
0x0e100b00, 0x0fb00f50, "vnmls%c.f64\t%z1, %z2, %z0"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
|
|
|
|
|
|
0x0e100b40, 0x0fb00f50, "vnmla%c.f64\t%z1, %z2, %z0"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
|
|
|
|
|
|
0x0e200a00, 0x0fb00f50, "vmul%c.f32\t%y1, %y2, %y0"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
|
|
|
|
|
|
0x0e200a40, 0x0fb00f50, "vnmul%c.f32\t%y1, %y2, %y0"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
|
|
|
|
|
|
0x0e200b00, 0x0fb00f50, "vmul%c.f64\t%z1, %z2, %z0"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
|
|
|
|
|
|
0x0e200b40, 0x0fb00f50, "vnmul%c.f64\t%z1, %z2, %z0"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
|
|
|
|
|
|
0x0e300a00, 0x0fb00f50, "vadd%c.f32\t%y1, %y2, %y0"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
|
|
|
|
|
|
0x0e300a40, 0x0fb00f50, "vsub%c.f32\t%y1, %y2, %y0"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
|
|
|
|
|
|
0x0e300b00, 0x0fb00f50, "vadd%c.f64\t%z1, %z2, %z0"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
|
|
|
|
|
|
0x0e300b40, 0x0fb00f50, "vsub%c.f64\t%z1, %z2, %z0"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
|
|
|
|
|
|
0x0e800a00, 0x0fb00f50, "vdiv%c.f32\t%y1, %y2, %y0"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
|
|
|
|
|
|
0x0e800b00, 0x0fb00f50, "vdiv%c.f64\t%z1, %z2, %z0"},
|
2004-11-27 12:09:21 +01:00
|
|
|
|
|
|
|
|
|
|
/* Cirrus coprocessor instructions. */
|
2015-03-24 07:08:08 +01:00
|
|
|
|
{ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
|
|
|
|
|
|
0x0d100400, 0x0f500f00, "cfldrs%c\tmvf%12-15d, %A"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
|
|
|
|
|
|
0x0c100400, 0x0f500f00, "cfldrs%c\tmvf%12-15d, %A"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
|
|
|
|
|
|
0x0d500400, 0x0f500f00, "cfldrd%c\tmvd%12-15d, %A"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
|
|
|
|
|
|
0x0c500400, 0x0f500f00, "cfldrd%c\tmvd%12-15d, %A"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
|
|
|
|
|
|
0x0d100500, 0x0f500f00, "cfldr32%c\tmvfx%12-15d, %A"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
|
|
|
|
|
|
0x0c100500, 0x0f500f00, "cfldr32%c\tmvfx%12-15d, %A"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
|
|
|
|
|
|
0x0d500500, 0x0f500f00, "cfldr64%c\tmvdx%12-15d, %A"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
|
|
|
|
|
|
0x0c500500, 0x0f500f00, "cfldr64%c\tmvdx%12-15d, %A"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
|
|
|
|
|
|
0x0d000400, 0x0f500f00, "cfstrs%c\tmvf%12-15d, %A"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
|
|
|
|
|
|
0x0c000400, 0x0f500f00, "cfstrs%c\tmvf%12-15d, %A"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
|
|
|
|
|
|
0x0d400400, 0x0f500f00, "cfstrd%c\tmvd%12-15d, %A"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
|
|
|
|
|
|
0x0c400400, 0x0f500f00, "cfstrd%c\tmvd%12-15d, %A"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
|
|
|
|
|
|
0x0d000500, 0x0f500f00, "cfstr32%c\tmvfx%12-15d, %A"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
|
|
|
|
|
|
0x0c000500, 0x0f500f00, "cfstr32%c\tmvfx%12-15d, %A"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
|
|
|
|
|
|
0x0d400500, 0x0f500f00, "cfstr64%c\tmvdx%12-15d, %A"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
|
|
|
|
|
|
0x0c400500, 0x0f500f00, "cfstr64%c\tmvdx%12-15d, %A"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
|
|
|
|
|
|
0x0e000450, 0x0ff00ff0, "cfmvsr%c\tmvf%16-19d, %12-15r"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
|
|
|
|
|
|
0x0e100450, 0x0ff00ff0, "cfmvrs%c\t%12-15r, mvf%16-19d"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
|
|
|
|
|
|
0x0e000410, 0x0ff00ff0, "cfmvdlr%c\tmvd%16-19d, %12-15r"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
|
|
|
|
|
|
0x0e100410, 0x0ff00ff0, "cfmvrdl%c\t%12-15r, mvd%16-19d"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
|
|
|
|
|
|
0x0e000430, 0x0ff00ff0, "cfmvdhr%c\tmvd%16-19d, %12-15r"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
|
|
|
|
|
|
0x0e100430, 0x0ff00fff, "cfmvrdh%c\t%12-15r, mvd%16-19d"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
|
|
|
|
|
|
0x0e000510, 0x0ff00fff, "cfmv64lr%c\tmvdx%16-19d, %12-15r"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
|
|
|
|
|
|
0x0e100510, 0x0ff00fff, "cfmvr64l%c\t%12-15r, mvdx%16-19d"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
|
|
|
|
|
|
0x0e000530, 0x0ff00fff, "cfmv64hr%c\tmvdx%16-19d, %12-15r"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
|
|
|
|
|
|
0x0e100530, 0x0ff00fff, "cfmvr64h%c\t%12-15r, mvdx%16-19d"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
|
|
|
|
|
|
0x0e200440, 0x0ff00fff, "cfmval32%c\tmvax%12-15d, mvfx%16-19d"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
|
|
|
|
|
|
0x0e100440, 0x0ff00fff, "cfmv32al%c\tmvfx%12-15d, mvax%16-19d"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
|
|
|
|
|
|
0x0e200460, 0x0ff00fff, "cfmvam32%c\tmvax%12-15d, mvfx%16-19d"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
|
|
|
|
|
|
0x0e100460, 0x0ff00fff, "cfmv32am%c\tmvfx%12-15d, mvax%16-19d"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
|
|
|
|
|
|
0x0e200480, 0x0ff00fff, "cfmvah32%c\tmvax%12-15d, mvfx%16-19d"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
|
|
|
|
|
|
0x0e100480, 0x0ff00fff, "cfmv32ah%c\tmvfx%12-15d, mvax%16-19d"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
|
|
|
|
|
|
0x0e2004a0, 0x0ff00fff, "cfmva32%c\tmvax%12-15d, mvfx%16-19d"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
|
|
|
|
|
|
0x0e1004a0, 0x0ff00fff, "cfmv32a%c\tmvfx%12-15d, mvax%16-19d"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
|
|
|
|
|
|
0x0e2004c0, 0x0ff00fff, "cfmva64%c\tmvax%12-15d, mvdx%16-19d"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
|
|
|
|
|
|
0x0e1004c0, 0x0ff00fff, "cfmv64a%c\tmvdx%12-15d, mvax%16-19d"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
|
|
|
|
|
|
0x0e2004e0, 0x0fff0fff, "cfmvsc32%c\tdspsc, mvdx%12-15d"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
|
|
|
|
|
|
0x0e1004e0, 0x0fff0fff, "cfmv32sc%c\tmvdx%12-15d, dspsc"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
|
|
|
|
|
|
0x0e000400, 0x0ff00fff, "cfcpys%c\tmvf%12-15d, mvf%16-19d"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
|
|
|
|
|
|
0x0e000420, 0x0ff00fff, "cfcpyd%c\tmvd%12-15d, mvd%16-19d"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
|
|
|
|
|
|
0x0e000460, 0x0ff00fff, "cfcvtsd%c\tmvd%12-15d, mvf%16-19d"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
|
|
|
|
|
|
0x0e000440, 0x0ff00fff, "cfcvtds%c\tmvf%12-15d, mvd%16-19d"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
|
|
|
|
|
|
0x0e000480, 0x0ff00fff, "cfcvt32s%c\tmvf%12-15d, mvfx%16-19d"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
|
|
|
|
|
|
0x0e0004a0, 0x0ff00fff, "cfcvt32d%c\tmvd%12-15d, mvfx%16-19d"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
|
|
|
|
|
|
0x0e0004c0, 0x0ff00fff, "cfcvt64s%c\tmvf%12-15d, mvdx%16-19d"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
|
|
|
|
|
|
0x0e0004e0, 0x0ff00fff, "cfcvt64d%c\tmvd%12-15d, mvdx%16-19d"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
|
|
|
|
|
|
0x0e100580, 0x0ff00fff, "cfcvts32%c\tmvfx%12-15d, mvf%16-19d"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
|
|
|
|
|
|
0x0e1005a0, 0x0ff00fff, "cfcvtd32%c\tmvfx%12-15d, mvd%16-19d"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
|
|
|
|
|
|
0x0e1005c0, 0x0ff00fff, "cftruncs32%c\tmvfx%12-15d, mvf%16-19d"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
|
|
|
|
|
|
0x0e1005e0, 0x0ff00fff, "cftruncd32%c\tmvfx%12-15d, mvd%16-19d"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
|
|
|
|
|
|
0x0e000550, 0x0ff00ff0, "cfrshl32%c\tmvfx%16-19d, mvfx%0-3d, %12-15r"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
|
|
|
|
|
|
0x0e000570, 0x0ff00ff0, "cfrshl64%c\tmvdx%16-19d, mvdx%0-3d, %12-15r"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
|
|
|
|
|
|
0x0e000500, 0x0ff00f10, "cfsh32%c\tmvfx%12-15d, mvfx%16-19d, #%I"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
|
|
|
|
|
|
0x0e200500, 0x0ff00f10, "cfsh64%c\tmvdx%12-15d, mvdx%16-19d, #%I"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
|
|
|
|
|
|
0x0e100490, 0x0ff00ff0, "cfcmps%c\t%12-15r, mvf%16-19d, mvf%0-3d"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
|
|
|
|
|
|
0x0e1004b0, 0x0ff00ff0, "cfcmpd%c\t%12-15r, mvd%16-19d, mvd%0-3d"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
|
|
|
|
|
|
0x0e100590, 0x0ff00ff0, "cfcmp32%c\t%12-15r, mvfx%16-19d, mvfx%0-3d"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
|
|
|
|
|
|
0x0e1005b0, 0x0ff00ff0, "cfcmp64%c\t%12-15r, mvdx%16-19d, mvdx%0-3d"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
|
|
|
|
|
|
0x0e300400, 0x0ff00fff, "cfabss%c\tmvf%12-15d, mvf%16-19d"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
|
|
|
|
|
|
0x0e300420, 0x0ff00fff, "cfabsd%c\tmvd%12-15d, mvd%16-19d"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
|
|
|
|
|
|
0x0e300440, 0x0ff00fff, "cfnegs%c\tmvf%12-15d, mvf%16-19d"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
|
|
|
|
|
|
0x0e300460, 0x0ff00fff, "cfnegd%c\tmvd%12-15d, mvd%16-19d"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
|
|
|
|
|
|
0x0e300480, 0x0ff00ff0, "cfadds%c\tmvf%12-15d, mvf%16-19d, mvf%0-3d"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
|
|
|
|
|
|
0x0e3004a0, 0x0ff00ff0, "cfaddd%c\tmvd%12-15d, mvd%16-19d, mvd%0-3d"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
|
|
|
|
|
|
0x0e3004c0, 0x0ff00ff0, "cfsubs%c\tmvf%12-15d, mvf%16-19d, mvf%0-3d"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
|
|
|
|
|
|
0x0e3004e0, 0x0ff00ff0, "cfsubd%c\tmvd%12-15d, mvd%16-19d, mvd%0-3d"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
|
|
|
|
|
|
0x0e100400, 0x0ff00ff0, "cfmuls%c\tmvf%12-15d, mvf%16-19d, mvf%0-3d"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
|
|
|
|
|
|
0x0e100420, 0x0ff00ff0, "cfmuld%c\tmvd%12-15d, mvd%16-19d, mvd%0-3d"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
|
|
|
|
|
|
0x0e300500, 0x0ff00fff, "cfabs32%c\tmvfx%12-15d, mvfx%16-19d"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
|
|
|
|
|
|
0x0e300520, 0x0ff00fff, "cfabs64%c\tmvdx%12-15d, mvdx%16-19d"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
|
|
|
|
|
|
0x0e300540, 0x0ff00fff, "cfneg32%c\tmvfx%12-15d, mvfx%16-19d"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
|
|
|
|
|
|
0x0e300560, 0x0ff00fff, "cfneg64%c\tmvdx%12-15d, mvdx%16-19d"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
|
|
|
|
|
|
0x0e300580, 0x0ff00ff0, "cfadd32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
|
|
|
|
|
|
0x0e3005a0, 0x0ff00ff0, "cfadd64%c\tmvdx%12-15d, mvdx%16-19d, mvdx%0-3d"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
|
|
|
|
|
|
0x0e3005c0, 0x0ff00ff0, "cfsub32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
|
|
|
|
|
|
0x0e3005e0, 0x0ff00ff0, "cfsub64%c\tmvdx%12-15d, mvdx%16-19d, mvdx%0-3d"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
|
|
|
|
|
|
0x0e100500, 0x0ff00ff0, "cfmul32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
|
|
|
|
|
|
0x0e100520, 0x0ff00ff0, "cfmul64%c\tmvdx%12-15d, mvdx%16-19d, mvdx%0-3d"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
|
|
|
|
|
|
0x0e100540, 0x0ff00ff0, "cfmac32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
|
|
|
|
|
|
0x0e100560, 0x0ff00ff0, "cfmsc32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
|
|
|
|
|
|
0x0e000600, 0x0ff00f10,
|
|
|
|
|
|
"cfmadd32%c\tmvax%5-7d, mvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
|
|
|
|
|
|
0x0e100600, 0x0ff00f10,
|
|
|
|
|
|
"cfmsub32%c\tmvax%5-7d, mvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
|
|
|
|
|
|
0x0e200600, 0x0ff00f10,
|
|
|
|
|
|
"cfmadda32%c\tmvax%5-7d, mvax%12-15d, mvfx%16-19d, mvfx%0-3d"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
|
|
|
|
|
|
0x0e300600, 0x0ff00f10,
|
|
|
|
|
|
"cfmsuba32%c\tmvax%5-7d, mvax%12-15d, mvfx%16-19d, mvfx%0-3d"},
|
2004-11-27 12:09:21 +01:00
|
|
|
|
|
2009-11-02 Paul Brook <paul@codesourcery.com>
ld/testsuite/
* ld-arm/arm-elf.exp: Add new attr-merge-vfp tests.
* ld-arm/attr-merge-vfp-1.d: New test.
* ld-arm/attr-merge-vfp-1r.d: New test.
* ld-arm/attr-merge-vfp-2.d: New test.
* ld-arm/attr-merge-vfp-2r.d: New test.
* ld-arm/attr-merge-vfp-3.d: New test.
* ld-arm/attr-merge-vfp-3r.d: New test.
* ld-arm/attr-merge-vfp-4.d: New test.
* ld-arm/attr-merge-vfp-4r.d: New test.
* ld-arm/attr-merge-vfp-5.d: New test.
* ld-arm/attr-merge-vfp-5r.d: New test.
* ld-arm/attr-merge-vfp-2.s: New test.
* ld-arm/attr-merge-vfp-3.s: New test.
* ld-arm/attr-merge-vfp-3-d16.s: New test.
* ld-arm/attr-merge-vfp-4.s: New test.
* ld-arm/attr-merge-vfp-4-d16.s: New test.
gas/
* doc/c-arm.texi: Document new -mfpu options.
* config/tc-arm.c (fpu_vfp_ext_v3xd, fpu_vfp_fp16, fpu_neon_ext_fma,
fpu_vfp_ext_fma): New.
(NEON_ENC_TAB): Add vfma, vfms, vfnma and vfnms.
(do_vfp_nsyn_fma_fms, do_neon_fmac): New functions.
(insns): Move double precision load/store. Split out double
precision VFPv3 instrucitons. Add VFPv4 instructions.
(arm_fpus): Add VFPv3-FP16, VFPv3xD and VFPv4 variants.
(aeabi_set_public_attributes): Set VFPv4 variants
gas/testsuite/
* gas/arm/attr-mfpu-vfpv4.d: New test.
* gas/arm/attr-mfpu-vfpv4-d16.d: New test.
* gas/arm/neon-fma-cov.d: New test.
* gas/arm/neon-fma-cov.s: New test.
* gas/arm/vfp-fma-inc.s: New test.
* gas/arm/vfp-fma-arm.d: New test.
* gas/arm/vfp-fma-arm.s: New test.
* gas/arm/vfp-fma-thumb.d: New test.
* gas/arm/vfp-fma-thumb.s: New test.
* gas/arm/vfma1.d: New test.
* gas/arm/vfma1.s: New test.
* gas/arm/vfpv3xd.d: New test.
* gas/arm/vfpv3xd.s: New test.
include/opcode/
* arm.h (FPU_VFP_EXT_V3xD, FPU_VFP_EXT_FP16, FPU_NEON_EXT_FMA,
FPU_VFP_EXT_FMA, FPU_VFP_V3xD, FPU_VFP_V4D16, FPU_VFP_V4): Define.
(FPU_ARCH_VFP_V3D16_FP16, FPU_ARCH_VFP_V3_FP16, FPU_ARCH_VFP_V3xD,
FPU_ARCH_VFP_V3xD_FP16, FPU_ARCH_VFP_V4, FPU_ARCH_VFP_V4D16,
FPU_ARCH_NEON_VFP_V4): Define.
binutils/
* readelf.c (arm_attr_tag_VFP_arch): Add VFPv4 and VFPv4-D16.
bfd/
* elf32-arm.c (elf32_arm_merge_eabi_attributes): Handle VFPv4
attributes.
opcodes/
* arm-dis.c (coprocessor_opcodes): Update to use new feature flags.
Add VFPv4 instructions.
2009-11-02 14:44:05 +01:00
|
|
|
|
/* VFP Fused multiply add instructions. */
|
2015-03-24 07:08:08 +01:00
|
|
|
|
{ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
|
|
|
|
|
|
0x0ea00a00, 0x0fb00f50, "vfma%c.f32\t%y1, %y2, %y0"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
|
|
|
|
|
|
0x0ea00b00, 0x0fb00f50, "vfma%c.f64\t%z1, %z2, %z0"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
|
|
|
|
|
|
0x0ea00a40, 0x0fb00f50, "vfms%c.f32\t%y1, %y2, %y0"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
|
|
|
|
|
|
0x0ea00b40, 0x0fb00f50, "vfms%c.f64\t%z1, %z2, %z0"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
|
|
|
|
|
|
0x0e900a40, 0x0fb00f50, "vfnma%c.f32\t%y1, %y2, %y0"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
|
|
|
|
|
|
0x0e900b40, 0x0fb00f50, "vfnma%c.f64\t%z1, %z2, %z0"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
|
|
|
|
|
|
0x0e900a00, 0x0fb00f50, "vfnms%c.f32\t%y1, %y2, %y0"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
|
|
|
|
|
|
0x0e900b00, 0x0fb00f50, "vfnms%c.f64\t%z1, %z2, %z0"},
|
2009-11-02 Paul Brook <paul@codesourcery.com>
ld/testsuite/
* ld-arm/arm-elf.exp: Add new attr-merge-vfp tests.
* ld-arm/attr-merge-vfp-1.d: New test.
* ld-arm/attr-merge-vfp-1r.d: New test.
* ld-arm/attr-merge-vfp-2.d: New test.
* ld-arm/attr-merge-vfp-2r.d: New test.
* ld-arm/attr-merge-vfp-3.d: New test.
* ld-arm/attr-merge-vfp-3r.d: New test.
* ld-arm/attr-merge-vfp-4.d: New test.
* ld-arm/attr-merge-vfp-4r.d: New test.
* ld-arm/attr-merge-vfp-5.d: New test.
* ld-arm/attr-merge-vfp-5r.d: New test.
* ld-arm/attr-merge-vfp-2.s: New test.
* ld-arm/attr-merge-vfp-3.s: New test.
* ld-arm/attr-merge-vfp-3-d16.s: New test.
* ld-arm/attr-merge-vfp-4.s: New test.
* ld-arm/attr-merge-vfp-4-d16.s: New test.
gas/
* doc/c-arm.texi: Document new -mfpu options.
* config/tc-arm.c (fpu_vfp_ext_v3xd, fpu_vfp_fp16, fpu_neon_ext_fma,
fpu_vfp_ext_fma): New.
(NEON_ENC_TAB): Add vfma, vfms, vfnma and vfnms.
(do_vfp_nsyn_fma_fms, do_neon_fmac): New functions.
(insns): Move double precision load/store. Split out double
precision VFPv3 instrucitons. Add VFPv4 instructions.
(arm_fpus): Add VFPv3-FP16, VFPv3xD and VFPv4 variants.
(aeabi_set_public_attributes): Set VFPv4 variants
gas/testsuite/
* gas/arm/attr-mfpu-vfpv4.d: New test.
* gas/arm/attr-mfpu-vfpv4-d16.d: New test.
* gas/arm/neon-fma-cov.d: New test.
* gas/arm/neon-fma-cov.s: New test.
* gas/arm/vfp-fma-inc.s: New test.
* gas/arm/vfp-fma-arm.d: New test.
* gas/arm/vfp-fma-arm.s: New test.
* gas/arm/vfp-fma-thumb.d: New test.
* gas/arm/vfp-fma-thumb.s: New test.
* gas/arm/vfma1.d: New test.
* gas/arm/vfma1.s: New test.
* gas/arm/vfpv3xd.d: New test.
* gas/arm/vfpv3xd.s: New test.
include/opcode/
* arm.h (FPU_VFP_EXT_V3xD, FPU_VFP_EXT_FP16, FPU_NEON_EXT_FMA,
FPU_VFP_EXT_FMA, FPU_VFP_V3xD, FPU_VFP_V4D16, FPU_VFP_V4): Define.
(FPU_ARCH_VFP_V3D16_FP16, FPU_ARCH_VFP_V3_FP16, FPU_ARCH_VFP_V3xD,
FPU_ARCH_VFP_V3xD_FP16, FPU_ARCH_VFP_V4, FPU_ARCH_VFP_V4D16,
FPU_ARCH_NEON_VFP_V4): Define.
binutils/
* readelf.c (arm_attr_tag_VFP_arch): Add VFPv4 and VFPv4-D16.
bfd/
* elf32-arm.c (elf32_arm_merge_eabi_attributes): Handle VFPv4
attributes.
opcodes/
* arm-dis.c (coprocessor_opcodes): Update to use new feature flags.
Add VFPv4 instructions.
2009-11-02 14:44:05 +01:00
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2012-08-24 10:06:36 +02:00
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/* FP v5. */
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2015-03-24 07:08:08 +01:00
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{ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
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2016-02-24 14:55:30 +01:00
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0xfe000a00, 0xff800f50, "vsel%20-21c%u.f32\t%y1, %y2, %y0"},
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2015-03-24 07:08:08 +01:00
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{ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
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2016-02-24 14:55:30 +01:00
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0xfe000b00, 0xff800f50, "vsel%20-21c%u.f64\t%z1, %z2, %z0"},
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2015-03-24 07:08:08 +01:00
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{ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
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2016-02-24 14:55:30 +01:00
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0xfe800a00, 0xffb00f50, "vmaxnm%u.f32\t%y1, %y2, %y0"},
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2015-03-24 07:08:08 +01:00
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{ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
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2016-02-24 14:55:30 +01:00
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0xfe800b00, 0xffb00f50, "vmaxnm%u.f64\t%z1, %z2, %z0"},
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2015-03-24 07:08:08 +01:00
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{ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
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2016-02-24 14:55:30 +01:00
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0xfe800a40, 0xffb00f50, "vminnm%u.f32\t%y1, %y2, %y0"},
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2015-03-24 07:08:08 +01:00
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{ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
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2016-02-24 14:55:30 +01:00
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0xfe800b40, 0xffb00f50, "vminnm%u.f64\t%z1, %z2, %z0"},
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2015-03-24 07:08:08 +01:00
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{ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
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0xfebc0a40, 0xffbc0f50, "vcvt%16-17?mpna%u.%7?su32.f32\t%y1, %y0"},
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{ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
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0xfebc0b40, 0xffbc0f50, "vcvt%16-17?mpna%u.%7?su32.f64\t%y1, %z0"},
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{ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
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0x0eb60a40, 0x0fbe0f50, "vrint%7,16??xzr%c.f32\t%y1, %y0"},
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{ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
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0x0eb60b40, 0x0fbe0f50, "vrint%7,16??xzr%c.f64\t%z1, %z0"},
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{ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
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2016-02-24 14:55:30 +01:00
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0xfeb80a40, 0xffbc0fd0, "vrint%16-17?mpna%u.f32\t%y1, %y0"},
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2015-03-24 07:08:08 +01:00
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{ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
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2016-02-24 14:55:30 +01:00
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0xfeb80b40, 0xffbc0fd0, "vrint%16-17?mpna%u.f64\t%z1, %z0"},
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2012-08-24 10:06:36 +02:00
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2009-06-29 10:08:15 +02:00
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/* Generic coprocessor instructions. */
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2015-03-24 07:08:08 +01:00
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{ARM_FEATURE_CORE_LOW (0), SENTINEL_GENERIC_START, 0, "" },
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{ARM_FEATURE_CORE_LOW (ARM_EXT_V5E),
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0x0c400000, 0x0ff00000, "mcrr%c\t%8-11d, %4-7d, %12-15R, %16-19r, cr%0-3d"},
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{ARM_FEATURE_CORE_LOW (ARM_EXT_V5E),
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0x0c500000, 0x0ff00000,
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"mrrc%c\t%8-11d, %4-7d, %12-15Ru, %16-19Ru, cr%0-3d"},
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{ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
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0x0e000000, 0x0f000010,
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"cdp%c\t%8-11d, %20-23d, cr%12-15d, cr%16-19d, cr%0-3d, {%5-7d}"},
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{ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
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0x0e10f010, 0x0f10f010,
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"mrc%c\t%8-11d, %21-23d, APSR_nzcv, cr%16-19d, cr%0-3d, {%5-7d}"},
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{ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
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0x0e100010, 0x0f100010,
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"mrc%c\t%8-11d, %21-23d, %12-15r, cr%16-19d, cr%0-3d, {%5-7d}"},
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{ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
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0x0e000010, 0x0f100010,
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"mcr%c\t%8-11d, %21-23d, %12-15R, cr%16-19d, cr%0-3d, {%5-7d}"},
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{ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
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0x0c000000, 0x0e100000, "stc%22'l%c\t%8-11d, cr%12-15d, %A"},
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{ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
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0x0c100000, 0x0e100000, "ldc%22'l%c\t%8-11d, cr%12-15d, %A"},
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2004-11-27 12:09:21 +01:00
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2009-06-29 10:08:15 +02:00
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/* V6 coprocessor instructions. */
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2015-03-24 07:08:08 +01:00
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{ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
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0xfc500000, 0xfff00000,
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"mrrc2%c\t%8-11d, %4-7d, %12-15Ru, %16-19Ru, cr%0-3d"},
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{ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
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0xfc400000, 0xfff00000,
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"mcrr2%c\t%8-11d, %4-7d, %12-15R, %16-19R, cr%0-3d"},
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2005-09-02 Paul Brook <paul@codesourcery.com>
bfd/
* libbdf.h: Regenerate.
* bfd-in2.h: Regenerate.
* reloc.c: Add BFD_RELOC_ARM_T32_CP_OFF_IMM and
BFD_RELOC_ARM_T32_CP_OFF_IMM_S2.
gas/
* config/tc-arm.c (encode_arm_cp_address): Use
BFD_RELOC_ARM_T32_CP_OFF_IMM in thumb mode.
(do_iwmmxt_wldstbh): Use BFD_RELOC_ARM_T32_CP_OFF_IMM_S2 in thumb
mode.
(md_assemble): Only allow coprocessor instructions when Thumb-2 is
available.
(cCE, cC3): Define.
(insns): Use them for coprocessor instructions.
(md_pcrel_from_section): Handle BFD_RELOC_ARM_T32_CP_OFF_IMM.
(get_thumb32_insn): New function.
(put_thumb32_insn): New function.
(md_apply_fix): Handle BFD_RELOC_ARM_T32_CP_OFF_IMM and
BFD_RELOC_ARM_T32_CP_OFF_IMM_S2.
gas/testsuite/
* gas/arm/vfp-bad_t2.d, gas/arm/vfp-bad_t2.l, arm/vfp-bad_t2.s,
gas/arm/vfp1_t2.d, gas/arm/vfp1_t2.s, gas/arm/vfp1xD_t2.d,
gas/arm/vfp1xD_t2.s, gas/arm/vfp2_t2.d, gas/arm/vfp2_t2.s): New files.
opcodes/
* arm-dis.c (coprocessor_opcodes): New.
(arm_opcodes, thumb32_opcodes): Remove coprocessor insns.
(print_insn_coprocessor): New function.
(print_insn_arm): Use print_insn_coprocessor. Remove coprocessor
format characters.
(print_insn_thumb32): Use print_insn_coprocessor.
2005-09-02 15:12:45 +02:00
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2016-12-05 15:24:17 +01:00
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/* ARMv8.3 AdvSIMD instructions in the space of coprocessor 8. */
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{ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
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0xfc800800, 0xfeb00f10, "vcadd%c.f16\t%12-15,22V, %16-19,7V, %0-3,5V, #%24?29%24'70"},
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{ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
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0xfc900800, 0xfeb00f10, "vcadd%c.f32\t%12-15,22V, %16-19,7V, %0-3,5V, #%24?29%24'70"},
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{ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
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0xfc200800, 0xff300f10, "vcmla%c.f16\t%12-15,22V, %16-19,7V, %0-3,5V, #%23'90"},
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{ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
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0xfd200800, 0xff300f10, "vcmla%c.f16\t%12-15,22V, %16-19,7V, %0-3,5V, #%23?21%23?780"},
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{ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
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0xfc300800, 0xff300f10, "vcmla%c.f32\t%12-15,22V, %16-19,7V, %0-3,5V, #%23'90"},
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{ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
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0xfd300800, 0xff300f10, "vcmla%c.f32\t%12-15,22V, %16-19,7V, %0-3,5V, #%23?21%23?780"},
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{ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
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2017-01-18 18:08:34 +01:00
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0xfe000800, 0xffa00f10, "vcmla%c.f16\t%12-15,22V, %16-19,7V, %0-3D[%5?10], #%20'90"},
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2016-12-05 15:24:17 +01:00
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{ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
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2017-01-18 18:08:34 +01:00
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0xfe200800, 0xffa00f10, "vcmla%c.f16\t%12-15,22V, %16-19,7V, %0-3D[%5?10], #%20?21%20?780"},
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2016-12-05 15:24:17 +01:00
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{ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
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2017-01-18 18:08:34 +01:00
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0xfe800800, 0xffa00f10, "vcmla%c.f32\t%12-15,22V, %16-19,7V, %0-3,5D[0], #%20'90"},
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2016-12-05 15:24:17 +01:00
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{ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
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2017-01-18 18:08:34 +01:00
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0xfea00800, 0xffa00f10, "vcmla%c.f32\t%12-15,22V, %16-19,7V, %0-3,5D[0], #%20?21%20?780"},
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2016-12-05 15:24:17 +01:00
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2017-06-28 12:00:55 +02:00
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/* Dot Product instructions in the space of coprocessor 13. */
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{ARM_FEATURE_COPROC (FPU_NEON_EXT_DOTPROD),
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0xfc200d00, 0xffb00f00, "v%4?usdot.%4?us8\t%12-15,22V, %16-19,7V, %0-3,5V"},
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{ARM_FEATURE_COPROC (FPU_NEON_EXT_DOTPROD),
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0xfe000d00, 0xff000f00, "v%4?usdot.%4?us8\t%12-15,22V, %16-19,7V, %0-3D[%5?10]"},
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2017-11-08 14:15:12 +01:00
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/* ARMv8.2 FMAC Long instructions in the space of coprocessor 8. */
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{ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A),
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0xfc200810, 0xffb00f50, "vfmal.f16\t%12-15,22D, s%7,16-19d, s%5,0-3d"},
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{ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A),
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0xfca00810, 0xffb00f50, "vfmsl.f16\t%12-15,22D, s%7,16-19d, s%5,0-3d"},
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{ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A),
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0xfc200850, 0xffb00f50, "vfmal.f16\t%12-15,22Q, d%16-19,7d, d%0-3,5d"},
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{ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A),
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0xfca00850, 0xffb00f50, "vfmsl.f16\t%12-15,22Q, d%16-19,7d, d%0-3,5d"},
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{ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A),
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0xfe000810, 0xffb00f50, "vfmal.f16\t%12-15,22D, s%7,16-19d, s%5,0-2d[%3d]"},
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{ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A),
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0xfe100810, 0xffb00f50, "vfmsl.f16\t%12-15,22D, s%7,16-19d, s%5,0-2d[%3d]"},
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{ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A),
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0xfe000850, 0xffb00f50, "vfmal.f16\t%12-15,22Q, d%16-19,7d, d%0-2d[%3,5d]"},
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{ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A),
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0xfe100850, 0xffb00f50, "vfmsl.f16\t%12-15,22Q, d%16-19,7d, d%0-2d[%3,5d]"},
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2009-06-29 10:08:15 +02:00
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/* V5 coprocessor instructions. */
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2015-03-24 07:08:08 +01:00
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{ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
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0xfc100000, 0xfe100000, "ldc2%22'l%c\t%8-11d, cr%12-15d, %A"},
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{ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
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0xfc000000, 0xfe100000, "stc2%22'l%c\t%8-11d, cr%12-15d, %A"},
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{ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
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0xfe000000, 0xff000010,
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"cdp2%c\t%8-11d, %20-23d, cr%12-15d, cr%16-19d, cr%0-3d, {%5-7d}"},
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{ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
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0xfe000010, 0xff100010,
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"mcr2%c\t%8-11d, %21-23d, %12-15R, cr%16-19d, cr%0-3d, {%5-7d}"},
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{ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
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0xfe100010, 0xff100010,
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"mrc2%c\t%8-11d, %21-23d, %12-15r, cr%16-19d, cr%0-3d, {%5-7d}"},
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2016-02-24 15:08:39 +01:00
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/* ARMv8.2 half-precision Floating point coprocessor 9 (VFP) instructions.
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cp_num: bit <11:8> == 0b1001.
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cond: bit <31:28> == 0b1110, otherwise, it's UNPREDICTABLE. */
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{ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
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0x0eb009c0, 0x0fbf0fd0, "vabs%c.f16\t%y1, %y0"},
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{ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
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0x0e300900, 0x0fb00f50, "vadd%c.f16\t%y1, %y2, %y0"},
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{ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
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0x0eb40940, 0x0fbf0f50, "vcmp%7'e%c.f16\t%y1, %y0"},
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{ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
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0x0eb50940, 0x0fbf0f70, "vcmp%7'e%c.f16\t%y1, #0.0"},
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{ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
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0x0eba09c0, 0x0fbe0fd0, "vcvt%c.f16.%16?us%7?31%7?26\t%y1, %y1, #%5,0-3k"},
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{ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
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0x0ebe09c0, 0x0fbe0fd0, "vcvt%c.%16?us%7?31%7?26.f16\t%y1, %y1, #%5,0-3k"},
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{ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
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0x0ebc0940, 0x0fbe0f50, "vcvt%7`r%c.%16?su32.f16\t%y1, %y0"},
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{ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
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0x0eb80940, 0x0fbf0f50, "vcvt%c.f16.%7?su32\t%y1, %y0"},
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{ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
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0xfebc0940, 0xffbc0f50, "vcvt%16-17?mpna%u.%7?su32.f16\t%y1, %y0"},
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{ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
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0x0e800900, 0x0fb00f50, "vdiv%c.f16\t%y1, %y2, %y0"},
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{ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
|
|
|
|
|
|
0x0ea00900, 0x0fb00f50, "vfma%c.f16\t%y1, %y2, %y0"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
|
|
|
|
|
|
0x0ea00940, 0x0fb00f50, "vfms%c.f16\t%y1, %y2, %y0"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
|
|
|
|
|
|
0x0e900940, 0x0fb00f50, "vfnma%c.f16\t%y1, %y2, %y0"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
|
|
|
|
|
|
0x0e900900, 0x0fb00f50, "vfnms%c.f16\t%y1, %y2, %y0"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
|
|
|
|
|
|
0xfeb00ac0, 0xffbf0fd0, "vins.f16\t%y1, %y0"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
|
|
|
|
|
|
0xfeb00a40, 0xffbf0fd0, "vmovx%c.f16\t%y1, %y0"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
|
|
|
|
|
|
0x0d100900, 0x0f300f00, "vldr%c.16\t%y1, %A"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
|
|
|
|
|
|
0x0d000900, 0x0f300f00, "vstr%c.16\t%y1, %A"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
|
|
|
|
|
|
0xfe800900, 0xffb00f50, "vmaxnm%c.f16\t%y1, %y2, %y0"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
|
|
|
|
|
|
0xfe800940, 0xffb00f50, "vminnm%c.f16\t%y1, %y2, %y0"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
|
|
|
|
|
|
0x0e000900, 0x0fb00f50, "vmla%c.f16\t%y1, %y2, %y0"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
|
|
|
|
|
|
0x0e000940, 0x0fb00f50, "vmls%c.f16\t%y1, %y2, %y0"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
|
|
|
|
|
|
0x0e100910, 0x0ff00f7f, "vmov%c.f16\t%12-15r, %y2"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
|
|
|
|
|
|
0x0e000910, 0x0ff00f7f, "vmov%c.f16\t%y2, %12-15r"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
|
|
|
|
|
|
0xeb00900, 0x0fb00ff0, "vmov%c.f16\t%y1, #%0-3,16-19E"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
|
|
|
|
|
|
0x0e200900, 0x0fb00f50, "vmul%c.f16\t%y1, %y2, %y0"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
|
|
|
|
|
|
0x0eb10940, 0x0fbf0fd0, "vneg%c.f16\t%y1, %y0"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
|
|
|
|
|
|
0x0e100940, 0x0fb00f50, "vnmla%c.f16\t%y1, %y2, %y0"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
|
|
|
|
|
|
0x0e100900, 0x0fb00f50, "vnmls%c.f16\t%y1, %y2, %y0"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
|
|
|
|
|
|
0x0e200940, 0x0fb00f50, "vnmul%c.f16\t%y1, %y2, %y0"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
|
|
|
|
|
|
0x0eb60940, 0x0fbe0f50, "vrint%7,16??xzr%c.f16\t%y1, %y0"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
|
|
|
|
|
|
0xfeb80940, 0xffbc0fd0, "vrint%16-17?mpna%u.f16\t%y1, %y0"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
|
|
|
|
|
|
0xfe000900, 0xff800f50, "vsel%20-21c%u.f16\t%y1, %y2, %y0"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
|
|
|
|
|
|
0x0eb109c0, 0x0fbf0fd0, "vsqrt%c.f16\t%y1, %y0"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
|
|
|
|
|
|
0x0e300940, 0x0fb00f50, "vsub%c.f16\t%y1, %y2, %y0"},
|
|
|
|
|
|
|
2016-12-05 15:13:27 +01:00
|
|
|
|
/* ARMv8.3 javascript conversion instruction. */
|
|
|
|
|
|
{ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
|
|
|
|
|
|
0x0eb90bc0, 0x0fbf0fd0, "vjcvt%c.s32.f64\t%y1, %z0"},
|
|
|
|
|
|
|
2015-03-24 07:08:08 +01:00
|
|
|
|
{ARM_FEATURE_CORE_LOW (0), 0, 0, 0}
|
2004-11-27 12:09:21 +01:00
|
|
|
|
};
|
|
|
|
|
|
|
2006-04-26 17:40:55 +02:00
|
|
|
|
/* Neon opcode table: This does not encode the top byte -- that is
|
|
|
|
|
|
checked by the print_insn_neon routine, as it depends on whether we are
|
|
|
|
|
|
doing thumb32 or arm32 disassembly. */
|
|
|
|
|
|
|
|
|
|
|
|
/* print_insn_neon recognizes the following format control codes:
|
|
|
|
|
|
|
|
|
|
|
|
%% %
|
|
|
|
|
|
|
2006-06-07 16:08:19 +02:00
|
|
|
|
%c print condition code
|
2012-08-24 09:59:05 +02:00
|
|
|
|
%u print condition code (unconditional in ARM mode,
|
|
|
|
|
|
UNPREDICTABLE if not AL in Thumb)
|
2006-04-26 17:40:55 +02:00
|
|
|
|
%A print v{st,ld}[1234] operands
|
|
|
|
|
|
%B print v{st,ld}[1234] any one operands
|
|
|
|
|
|
%C print v{st,ld}[1234] single->all operands
|
|
|
|
|
|
%D print scalar
|
|
|
|
|
|
%E print vmov, vmvn, vorr, vbic encoded constant
|
|
|
|
|
|
%F print vtbl,vtbx register list
|
|
|
|
|
|
|
|
|
|
|
|
%<bitfield>r print as an ARM register
|
|
|
|
|
|
%<bitfield>d print the bitfield in decimal
|
|
|
|
|
|
%<bitfield>e print the 2^N - bitfield in decimal
|
|
|
|
|
|
%<bitfield>D print as a NEON D register
|
|
|
|
|
|
%<bitfield>Q print as a NEON Q register
|
|
|
|
|
|
%<bitfield>R print as a NEON D or Q register
|
|
|
|
|
|
%<bitfield>Sn print byte scaled width limited by n
|
|
|
|
|
|
%<bitfield>Tn print short scaled width limited by n
|
|
|
|
|
|
%<bitfield>Un print long scaled width limited by n
|
2015-08-12 13:45:07 +02:00
|
|
|
|
|
2006-04-26 17:40:55 +02:00
|
|
|
|
%<bitfield>'c print specified char iff bitfield is all ones
|
|
|
|
|
|
%<bitfield>`c print specified char iff bitfield is all zeroes
|
2009-06-30 13:57:05 +02:00
|
|
|
|
%<bitfield>?ab... select from array of values in big endian order. */
|
2006-04-26 17:40:55 +02:00
|
|
|
|
|
|
|
|
|
|
static const struct opcode32 neon_opcodes[] =
|
|
|
|
|
|
{
|
2009-06-30 13:57:05 +02:00
|
|
|
|
/* Extract. */
|
2015-03-24 07:08:08 +01:00
|
|
|
|
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
|
|
|
|
|
|
0xf2b00840, 0xffb00850,
|
|
|
|
|
|
"vext%c.8\t%12-15,22R, %16-19,7R, %0-3,5R, #%8-11d"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
|
|
|
|
|
|
0xf2b00000, 0xffb00810,
|
|
|
|
|
|
"vext%c.8\t%12-15,22R, %16-19,7R, %0-3,5R, #%8-11d"},
|
2006-04-26 17:40:55 +02:00
|
|
|
|
|
2009-06-30 13:57:05 +02:00
|
|
|
|
/* Move data element to all lanes. */
|
2015-03-24 07:08:08 +01:00
|
|
|
|
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
|
|
|
|
|
|
0xf3b40c00, 0xffb70f90, "vdup%c.32\t%12-15,22R, %0-3,5D[%19d]"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
|
|
|
|
|
|
0xf3b20c00, 0xffb30f90, "vdup%c.16\t%12-15,22R, %0-3,5D[%18-19d]"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
|
|
|
|
|
|
0xf3b10c00, 0xffb10f90, "vdup%c.8\t%12-15,22R, %0-3,5D[%17-19d]"},
|
2006-04-26 17:40:55 +02:00
|
|
|
|
|
2009-06-30 13:57:05 +02:00
|
|
|
|
/* Table lookup. */
|
2015-03-24 07:08:08 +01:00
|
|
|
|
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
|
|
|
|
|
|
0xf3b00800, 0xffb00c50, "vtbl%c.8\t%12-15,22D, %F, %0-3,5D"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
|
|
|
|
|
|
0xf3b00840, 0xffb00c50, "vtbx%c.8\t%12-15,22D, %F, %0-3,5D"},
|
|
|
|
|
|
|
2008-11-18 16:45:05 +01:00
|
|
|
|
/* Half-precision conversions. */
|
2015-03-24 07:08:08 +01:00
|
|
|
|
{ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16),
|
|
|
|
|
|
0xf3b60600, 0xffbf0fd0, "vcvt%c.f16.f32\t%12-15,22D, %0-3,5Q"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16),
|
|
|
|
|
|
0xf3b60700, 0xffbf0fd0, "vcvt%c.f32.f16\t%12-15,22Q, %0-3,5D"},
|
2009-11-02 Paul Brook <paul@codesourcery.com>
ld/testsuite/
* ld-arm/arm-elf.exp: Add new attr-merge-vfp tests.
* ld-arm/attr-merge-vfp-1.d: New test.
* ld-arm/attr-merge-vfp-1r.d: New test.
* ld-arm/attr-merge-vfp-2.d: New test.
* ld-arm/attr-merge-vfp-2r.d: New test.
* ld-arm/attr-merge-vfp-3.d: New test.
* ld-arm/attr-merge-vfp-3r.d: New test.
* ld-arm/attr-merge-vfp-4.d: New test.
* ld-arm/attr-merge-vfp-4r.d: New test.
* ld-arm/attr-merge-vfp-5.d: New test.
* ld-arm/attr-merge-vfp-5r.d: New test.
* ld-arm/attr-merge-vfp-2.s: New test.
* ld-arm/attr-merge-vfp-3.s: New test.
* ld-arm/attr-merge-vfp-3-d16.s: New test.
* ld-arm/attr-merge-vfp-4.s: New test.
* ld-arm/attr-merge-vfp-4-d16.s: New test.
gas/
* doc/c-arm.texi: Document new -mfpu options.
* config/tc-arm.c (fpu_vfp_ext_v3xd, fpu_vfp_fp16, fpu_neon_ext_fma,
fpu_vfp_ext_fma): New.
(NEON_ENC_TAB): Add vfma, vfms, vfnma and vfnms.
(do_vfp_nsyn_fma_fms, do_neon_fmac): New functions.
(insns): Move double precision load/store. Split out double
precision VFPv3 instrucitons. Add VFPv4 instructions.
(arm_fpus): Add VFPv3-FP16, VFPv3xD and VFPv4 variants.
(aeabi_set_public_attributes): Set VFPv4 variants
gas/testsuite/
* gas/arm/attr-mfpu-vfpv4.d: New test.
* gas/arm/attr-mfpu-vfpv4-d16.d: New test.
* gas/arm/neon-fma-cov.d: New test.
* gas/arm/neon-fma-cov.s: New test.
* gas/arm/vfp-fma-inc.s: New test.
* gas/arm/vfp-fma-arm.d: New test.
* gas/arm/vfp-fma-arm.s: New test.
* gas/arm/vfp-fma-thumb.d: New test.
* gas/arm/vfp-fma-thumb.s: New test.
* gas/arm/vfma1.d: New test.
* gas/arm/vfma1.s: New test.
* gas/arm/vfpv3xd.d: New test.
* gas/arm/vfpv3xd.s: New test.
include/opcode/
* arm.h (FPU_VFP_EXT_V3xD, FPU_VFP_EXT_FP16, FPU_NEON_EXT_FMA,
FPU_VFP_EXT_FMA, FPU_VFP_V3xD, FPU_VFP_V4D16, FPU_VFP_V4): Define.
(FPU_ARCH_VFP_V3D16_FP16, FPU_ARCH_VFP_V3_FP16, FPU_ARCH_VFP_V3xD,
FPU_ARCH_VFP_V3xD_FP16, FPU_ARCH_VFP_V4, FPU_ARCH_VFP_V4D16,
FPU_ARCH_NEON_VFP_V4): Define.
binutils/
* readelf.c (arm_attr_tag_VFP_arch): Add VFPv4 and VFPv4-D16.
bfd/
* elf32-arm.c (elf32_arm_merge_eabi_attributes): Handle VFPv4
attributes.
opcodes/
* arm-dis.c (coprocessor_opcodes): Update to use new feature flags.
Add VFPv4 instructions.
2009-11-02 14:44:05 +01:00
|
|
|
|
|
|
|
|
|
|
/* NEON fused multiply add instructions. */
|
2015-03-24 07:08:08 +01:00
|
|
|
|
{ARM_FEATURE_COPROC (FPU_NEON_EXT_FMA),
|
2016-03-16 17:11:59 +01:00
|
|
|
|
0xf2000c10, 0xffb00f10, "vfma%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
|
|
|
|
|
|
0xf2100c10, 0xffb00f10, "vfma%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
|
2015-03-24 07:08:08 +01:00
|
|
|
|
{ARM_FEATURE_COPROC (FPU_NEON_EXT_FMA),
|
2016-03-16 17:11:59 +01:00
|
|
|
|
0xf2200c10, 0xffb00f10, "vfms%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
|
|
|
|
|
|
0xf2300c10, 0xffb00f10, "vfms%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
|
2008-11-18 16:45:05 +01:00
|
|
|
|
|
2009-06-30 13:57:05 +02:00
|
|
|
|
/* Two registers, miscellaneous. */
|
2015-03-24 07:08:08 +01:00
|
|
|
|
{ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8),
|
|
|
|
|
|
0xf3ba0400, 0xffbf0c10, "vrint%7-9?p?m?zaxn%u.f32\t%12-15,22R, %0-3,5R"},
|
2016-03-16 17:11:59 +01:00
|
|
|
|
{ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
|
|
|
|
|
|
0xf3b60400, 0xffbf0c10, "vrint%7-9?p?m?zaxn%u.f16\t%12-15,22R, %0-3,5R"},
|
2015-03-24 07:08:08 +01:00
|
|
|
|
{ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8),
|
|
|
|
|
|
0xf3bb0000, 0xffbf0c10, "vcvt%8-9?mpna%u.%7?us32.f32\t%12-15,22R, %0-3,5R"},
|
2016-03-16 17:11:59 +01:00
|
|
|
|
{ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
|
|
|
|
|
|
0xf3b70000, 0xffbf0c10, "vcvt%8-9?mpna%u.%7?us16.f16\t%12-15,22R, %0-3,5R"},
|
2015-03-24 07:08:08 +01:00
|
|
|
|
{ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
|
|
|
|
|
|
0xf3b00300, 0xffbf0fd0, "aese%u.8\t%12-15,22Q, %0-3,5Q"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
|
|
|
|
|
|
0xf3b00340, 0xffbf0fd0, "aesd%u.8\t%12-15,22Q, %0-3,5Q"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
|
|
|
|
|
|
0xf3b00380, 0xffbf0fd0, "aesmc%u.8\t%12-15,22Q, %0-3,5Q"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
|
|
|
|
|
|
0xf3b003c0, 0xffbf0fd0, "aesimc%u.8\t%12-15,22Q, %0-3,5Q"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
|
|
|
|
|
|
0xf3b902c0, 0xffbf0fd0, "sha1h%u.32\t%12-15,22Q, %0-3,5Q"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
|
|
|
|
|
|
0xf3ba0380, 0xffbf0fd0, "sha1su1%u.32\t%12-15,22Q, %0-3,5Q"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
|
|
|
|
|
|
0xf3ba03c0, 0xffbf0fd0, "sha256su0%u.32\t%12-15,22Q, %0-3,5Q"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
|
|
|
|
|
|
0xf2880a10, 0xfebf0fd0, "vmovl%c.%24?us8\t%12-15,22Q, %0-3,5D"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
|
|
|
|
|
|
0xf2900a10, 0xfebf0fd0, "vmovl%c.%24?us16\t%12-15,22Q, %0-3,5D"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
|
|
|
|
|
|
0xf2a00a10, 0xfebf0fd0, "vmovl%c.%24?us32\t%12-15,22Q, %0-3,5D"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
|
|
|
|
|
|
0xf3b00500, 0xffbf0f90, "vcnt%c.8\t%12-15,22R, %0-3,5R"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
|
|
|
|
|
|
0xf3b00580, 0xffbf0f90, "vmvn%c\t%12-15,22R, %0-3,5R"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
|
|
|
|
|
|
0xf3b20000, 0xffbf0f90, "vswp%c\t%12-15,22R, %0-3,5R"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
|
|
|
|
|
|
0xf3b20200, 0xffb30fd0, "vmovn%c.i%18-19T2\t%12-15,22D, %0-3,5Q"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
|
|
|
|
|
|
0xf3b20240, 0xffb30fd0, "vqmovun%c.s%18-19T2\t%12-15,22D, %0-3,5Q"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
|
|
|
|
|
|
0xf3b20280, 0xffb30fd0, "vqmovn%c.s%18-19T2\t%12-15,22D, %0-3,5Q"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
|
|
|
|
|
|
0xf3b202c0, 0xffb30fd0, "vqmovn%c.u%18-19T2\t%12-15,22D, %0-3,5Q"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
|
|
|
|
|
|
0xf3b20300, 0xffb30fd0,
|
|
|
|
|
|
"vshll%c.i%18-19S2\t%12-15,22Q, %0-3,5D, #%18-19S2"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
|
|
|
|
|
|
0xf3bb0400, 0xffbf0e90, "vrecpe%c.%8?fu%18-19S2\t%12-15,22R, %0-3,5R"},
|
2016-03-16 17:11:59 +01:00
|
|
|
|
{ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
|
|
|
|
|
|
0xf3b70400, 0xffbf0e90, "vrecpe%c.%8?fu16\t%12-15,22R, %0-3,5R"},
|
2015-03-24 07:08:08 +01:00
|
|
|
|
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
|
|
|
|
|
|
0xf3bb0480, 0xffbf0e90, "vrsqrte%c.%8?fu%18-19S2\t%12-15,22R, %0-3,5R"},
|
2016-03-16 17:11:59 +01:00
|
|
|
|
{ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
|
|
|
|
|
|
0xf3b70480, 0xffbf0e90, "vrsqrte%c.%8?fu16\t%12-15,22R, %0-3,5R"},
|
2015-03-24 07:08:08 +01:00
|
|
|
|
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
|
|
|
|
|
|
0xf3b00000, 0xffb30f90, "vrev64%c.%18-19S2\t%12-15,22R, %0-3,5R"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
|
|
|
|
|
|
0xf3b00080, 0xffb30f90, "vrev32%c.%18-19S2\t%12-15,22R, %0-3,5R"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
|
|
|
|
|
|
0xf3b00100, 0xffb30f90, "vrev16%c.%18-19S2\t%12-15,22R, %0-3,5R"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
|
|
|
|
|
|
0xf3b00400, 0xffb30f90, "vcls%c.s%18-19S2\t%12-15,22R, %0-3,5R"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
|
|
|
|
|
|
0xf3b00480, 0xffb30f90, "vclz%c.i%18-19S2\t%12-15,22R, %0-3,5R"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
|
|
|
|
|
|
0xf3b00700, 0xffb30f90, "vqabs%c.s%18-19S2\t%12-15,22R, %0-3,5R"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
|
|
|
|
|
|
0xf3b00780, 0xffb30f90, "vqneg%c.s%18-19S2\t%12-15,22R, %0-3,5R"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
|
|
|
|
|
|
0xf3b20080, 0xffb30f90, "vtrn%c.%18-19S2\t%12-15,22R, %0-3,5R"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
|
|
|
|
|
|
0xf3b20100, 0xffb30f90, "vuzp%c.%18-19S2\t%12-15,22R, %0-3,5R"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
|
|
|
|
|
|
0xf3b20180, 0xffb30f90, "vzip%c.%18-19S2\t%12-15,22R, %0-3,5R"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
|
|
|
|
|
|
0xf3b10000, 0xffb30b90, "vcgt%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, #0"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
|
|
|
|
|
|
0xf3b10080, 0xffb30b90, "vcge%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, #0"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
|
|
|
|
|
|
0xf3b10100, 0xffb30b90, "vceq%c.%10?fi%18-19S2\t%12-15,22R, %0-3,5R, #0"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
|
|
|
|
|
|
0xf3b10180, 0xffb30b90, "vcle%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, #0"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
|
|
|
|
|
|
0xf3b10200, 0xffb30b90, "vclt%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, #0"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
|
|
|
|
|
|
0xf3b10300, 0xffb30b90, "vabs%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
|
|
|
|
|
|
0xf3b10380, 0xffb30b90, "vneg%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
|
|
|
|
|
|
0xf3b00200, 0xffb30f10, "vpaddl%c.%7?us%18-19S2\t%12-15,22R, %0-3,5R"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
|
|
|
|
|
|
0xf3b00600, 0xffb30f10, "vpadal%c.%7?us%18-19S2\t%12-15,22R, %0-3,5R"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
|
2016-03-16 17:11:59 +01:00
|
|
|
|
0xf3bb0600, 0xffbf0e10,
|
2015-03-24 07:08:08 +01:00
|
|
|
|
"vcvt%c.%7-8?usff%18-19Sa.%7-8?ffus%18-19Sa\t%12-15,22R, %0-3,5R"},
|
2016-03-16 17:11:59 +01:00
|
|
|
|
{ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
|
|
|
|
|
|
0xf3b70600, 0xffbf0e10,
|
|
|
|
|
|
"vcvt%c.%7-8?usff16.%7-8?ffus16\t%12-15,22R, %0-3,5R"},
|
2006-04-26 17:40:55 +02:00
|
|
|
|
|
2009-06-30 13:57:05 +02:00
|
|
|
|
/* Three registers of the same length. */
|
2015-03-24 07:08:08 +01:00
|
|
|
|
{ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
|
|
|
|
|
|
0xf2000c40, 0xffb00f50, "sha1c%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
|
|
|
|
|
|
0xf2100c40, 0xffb00f50, "sha1p%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
|
|
|
|
|
|
0xf2200c40, 0xffb00f50, "sha1m%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
|
|
|
|
|
|
0xf2300c40, 0xffb00f50, "sha1su0%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
|
|
|
|
|
|
0xf3000c40, 0xffb00f50, "sha256h%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
|
|
|
|
|
|
0xf3100c40, 0xffb00f50, "sha256h2%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
|
|
|
|
|
|
0xf3200c40, 0xffb00f50, "sha256su1%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8),
|
2016-03-16 17:11:59 +01:00
|
|
|
|
0xf3000f10, 0xffb00f10, "vmaxnm%u.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
|
|
|
|
|
|
0xf3100f10, 0xffb00f10, "vmaxnm%u.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
|
2015-03-24 07:08:08 +01:00
|
|
|
|
{ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8),
|
2016-03-16 17:11:59 +01:00
|
|
|
|
0xf3200f10, 0xffb00f10, "vminnm%u.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
|
|
|
|
|
|
0xf3300f10, 0xffb00f10, "vminnm%u.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
|
2015-03-24 07:08:08 +01:00
|
|
|
|
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
|
|
|
|
|
|
0xf2000110, 0xffb00f10, "vand%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
|
|
|
|
|
|
0xf2100110, 0xffb00f10, "vbic%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
|
|
|
|
|
|
0xf2200110, 0xffb00f10, "vorr%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
|
|
|
|
|
|
0xf2300110, 0xffb00f10, "vorn%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
|
|
|
|
|
|
0xf3000110, 0xffb00f10, "veor%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
|
|
|
|
|
|
0xf3100110, 0xffb00f10, "vbsl%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
|
|
|
|
|
|
0xf3200110, 0xffb00f10, "vbit%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
|
|
|
|
|
|
0xf3300110, 0xffb00f10, "vbif%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
|
2016-03-16 17:11:59 +01:00
|
|
|
|
0xf2000d00, 0xffb00f10, "vadd%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
|
|
|
|
|
|
0xf2100d00, 0xffb00f10, "vadd%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
|
2015-03-24 07:08:08 +01:00
|
|
|
|
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
|
2016-03-16 17:11:59 +01:00
|
|
|
|
0xf2000d10, 0xffb00f10, "vmla%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
|
|
|
|
|
|
0xf2100d10, 0xffb00f10, "vmla%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
|
2015-03-24 07:08:08 +01:00
|
|
|
|
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
|
2016-03-16 17:11:59 +01:00
|
|
|
|
0xf2000e00, 0xffb00f10, "vceq%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
|
|
|
|
|
|
0xf2100e00, 0xffb00f10, "vceq%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
|
2015-03-24 07:08:08 +01:00
|
|
|
|
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
|
2016-03-16 17:11:59 +01:00
|
|
|
|
0xf2000f00, 0xffb00f10, "vmax%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
|
|
|
|
|
|
0xf2100f00, 0xffb00f10, "vmax%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
|
2015-03-24 07:08:08 +01:00
|
|
|
|
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
|
2016-03-16 17:11:59 +01:00
|
|
|
|
0xf2000f10, 0xffb00f10, "vrecps%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
|
|
|
|
|
|
0xf2100f10, 0xffb00f10, "vrecps%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
|
2015-03-24 07:08:08 +01:00
|
|
|
|
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
|
2016-03-16 17:11:59 +01:00
|
|
|
|
0xf2200d00, 0xffb00f10, "vsub%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
|
|
|
|
|
|
0xf2300d00, 0xffb00f10, "vsub%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
|
2015-03-24 07:08:08 +01:00
|
|
|
|
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
|
2016-03-16 17:11:59 +01:00
|
|
|
|
0xf2200d10, 0xffb00f10, "vmls%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
|
|
|
|
|
|
0xf2300d10, 0xffb00f10, "vmls%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
|
2015-03-24 07:08:08 +01:00
|
|
|
|
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
|
2016-03-16 17:11:59 +01:00
|
|
|
|
0xf2200f00, 0xffb00f10, "vmin%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
|
|
|
|
|
|
0xf2300f00, 0xffb00f10, "vmin%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
|
2015-03-24 07:08:08 +01:00
|
|
|
|
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
|
2016-03-16 17:11:59 +01:00
|
|
|
|
0xf2200f10, 0xffb00f10, "vrsqrts%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
|
|
|
|
|
|
0xf2300f10, 0xffb00f10, "vrsqrts%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
|
2015-03-24 07:08:08 +01:00
|
|
|
|
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
|
2016-03-16 17:11:59 +01:00
|
|
|
|
0xf3000d00, 0xffb00f10, "vpadd%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
|
|
|
|
|
|
0xf3100d00, 0xffb00f10, "vpadd%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
|
2015-03-24 07:08:08 +01:00
|
|
|
|
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
|
2016-03-16 17:11:59 +01:00
|
|
|
|
0xf3000d10, 0xffb00f10, "vmul%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
|
|
|
|
|
|
0xf3100d10, 0xffb00f10, "vmul%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
|
2015-03-24 07:08:08 +01:00
|
|
|
|
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
|
2016-03-16 17:11:59 +01:00
|
|
|
|
0xf3000e00, 0xffb00f10, "vcge%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
|
|
|
|
|
|
0xf3100e00, 0xffb00f10, "vcge%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
|
2015-03-24 07:08:08 +01:00
|
|
|
|
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
|
2016-03-16 17:11:59 +01:00
|
|
|
|
0xf3000e10, 0xffb00f10, "vacge%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
|
|
|
|
|
|
0xf3100e10, 0xffb00f10, "vacge%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
|
2015-03-24 07:08:08 +01:00
|
|
|
|
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
|
2016-03-16 17:11:59 +01:00
|
|
|
|
0xf3000f00, 0xffb00f10, "vpmax%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
|
|
|
|
|
|
0xf3100f00, 0xffb00f10, "vpmax%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
|
2015-03-24 07:08:08 +01:00
|
|
|
|
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
|
2016-03-16 17:11:59 +01:00
|
|
|
|
0xf3200d00, 0xffb00f10, "vabd%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
|
|
|
|
|
|
0xf3300d00, 0xffb00f10, "vabd%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
|
2015-03-24 07:08:08 +01:00
|
|
|
|
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
|
2016-03-16 17:11:59 +01:00
|
|
|
|
0xf3200e00, 0xffb00f10, "vcgt%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
|
|
|
|
|
|
0xf3300e00, 0xffb00f10, "vcgt%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
|
2015-03-24 07:08:08 +01:00
|
|
|
|
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
|
2016-03-16 17:11:59 +01:00
|
|
|
|
0xf3200e10, 0xffb00f10, "vacgt%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
|
|
|
|
|
|
0xf3300e10, 0xffb00f10, "vacgt%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
|
2015-03-24 07:08:08 +01:00
|
|
|
|
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
|
2016-03-16 17:11:59 +01:00
|
|
|
|
0xf3200f00, 0xffb00f10, "vpmin%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
|
|
|
|
|
|
0xf3300f00, 0xffb00f10, "vpmin%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
|
2015-03-24 07:08:08 +01:00
|
|
|
|
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
|
|
|
|
|
|
0xf2000800, 0xff800f10, "vadd%c.i%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
|
|
|
|
|
|
0xf2000810, 0xff800f10, "vtst%c.%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
|
|
|
|
|
|
0xf2000900, 0xff800f10, "vmla%c.i%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
|
|
|
|
|
|
0xf2000b00, 0xff800f10,
|
|
|
|
|
|
"vqdmulh%c.s%20-21S6\t%12-15,22R, %16-19,7R, %0-3,5R"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
|
|
|
|
|
|
0xf2000b10, 0xff800f10,
|
|
|
|
|
|
"vpadd%c.i%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
|
|
|
|
|
|
0xf3000800, 0xff800f10, "vsub%c.i%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
|
|
|
|
|
|
0xf3000810, 0xff800f10, "vceq%c.i%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
|
|
|
|
|
|
0xf3000900, 0xff800f10, "vmls%c.i%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
|
|
|
|
|
|
0xf3000b00, 0xff800f10,
|
|
|
|
|
|
"vqrdmulh%c.s%20-21S6\t%12-15,22R, %16-19,7R, %0-3,5R"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
|
|
|
|
|
|
0xf2000000, 0xfe800f10,
|
|
|
|
|
|
"vhadd%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
|
|
|
|
|
|
0xf2000010, 0xfe800f10,
|
|
|
|
|
|
"vqadd%c.%24?us%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
|
|
|
|
|
|
0xf2000100, 0xfe800f10,
|
|
|
|
|
|
"vrhadd%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
|
|
|
|
|
|
0xf2000200, 0xfe800f10,
|
|
|
|
|
|
"vhsub%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
|
|
|
|
|
|
0xf2000210, 0xfe800f10,
|
|
|
|
|
|
"vqsub%c.%24?us%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
|
|
|
|
|
|
0xf2000300, 0xfe800f10,
|
|
|
|
|
|
"vcgt%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
|
|
|
|
|
|
0xf2000310, 0xfe800f10,
|
|
|
|
|
|
"vcge%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
|
|
|
|
|
|
0xf2000400, 0xfe800f10,
|
|
|
|
|
|
"vshl%c.%24?us%20-21S3\t%12-15,22R, %0-3,5R, %16-19,7R"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
|
|
|
|
|
|
0xf2000410, 0xfe800f10,
|
|
|
|
|
|
"vqshl%c.%24?us%20-21S3\t%12-15,22R, %0-3,5R, %16-19,7R"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
|
|
|
|
|
|
0xf2000500, 0xfe800f10,
|
|
|
|
|
|
"vrshl%c.%24?us%20-21S3\t%12-15,22R, %0-3,5R, %16-19,7R"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
|
|
|
|
|
|
0xf2000510, 0xfe800f10,
|
|
|
|
|
|
"vqrshl%c.%24?us%20-21S3\t%12-15,22R, %0-3,5R, %16-19,7R"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
|
|
|
|
|
|
0xf2000600, 0xfe800f10,
|
|
|
|
|
|
"vmax%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
|
|
|
|
|
|
0xf2000610, 0xfe800f10,
|
|
|
|
|
|
"vmin%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
|
|
|
|
|
|
0xf2000700, 0xfe800f10,
|
|
|
|
|
|
"vabd%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
|
|
|
|
|
|
0xf2000710, 0xfe800f10,
|
|
|
|
|
|
"vaba%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
|
|
|
|
|
|
0xf2000910, 0xfe800f10,
|
|
|
|
|
|
"vmul%c.%24?pi%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
|
|
|
|
|
|
0xf2000a00, 0xfe800f10,
|
|
|
|
|
|
"vpmax%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
|
|
|
|
|
|
0xf2000a10, 0xfe800f10,
|
|
|
|
|
|
"vpmin%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
|
2015-06-02 13:35:21 +02:00
|
|
|
|
{ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA),
|
|
|
|
|
|
0xf3000b10, 0xff800f10,
|
|
|
|
|
|
"vqrdmlah%c.s%20-21S6\t%12-15,22R, %16-19,7R, %0-3,5R"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA),
|
|
|
|
|
|
0xf3000c10, 0xff800f10,
|
|
|
|
|
|
"vqrdmlsh%c.s%20-21S6\t%12-15,22R, %16-19,7R, %0-3,5R"},
|
2006-04-26 17:40:55 +02:00
|
|
|
|
|
2009-06-30 13:57:05 +02:00
|
|
|
|
/* One register and an immediate value. */
|
2015-03-24 07:08:08 +01:00
|
|
|
|
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
|
|
|
|
|
|
0xf2800e10, 0xfeb80fb0, "vmov%c.i8\t%12-15,22R, %E"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
|
|
|
|
|
|
0xf2800e30, 0xfeb80fb0, "vmov%c.i64\t%12-15,22R, %E"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
|
|
|
|
|
|
0xf2800f10, 0xfeb80fb0, "vmov%c.f32\t%12-15,22R, %E"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
|
|
|
|
|
|
0xf2800810, 0xfeb80db0, "vmov%c.i16\t%12-15,22R, %E"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
|
|
|
|
|
|
0xf2800830, 0xfeb80db0, "vmvn%c.i16\t%12-15,22R, %E"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
|
|
|
|
|
|
0xf2800910, 0xfeb80db0, "vorr%c.i16\t%12-15,22R, %E"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
|
|
|
|
|
|
0xf2800930, 0xfeb80db0, "vbic%c.i16\t%12-15,22R, %E"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
|
|
|
|
|
|
0xf2800c10, 0xfeb80eb0, "vmov%c.i32\t%12-15,22R, %E"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
|
|
|
|
|
|
0xf2800c30, 0xfeb80eb0, "vmvn%c.i32\t%12-15,22R, %E"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
|
|
|
|
|
|
0xf2800110, 0xfeb809b0, "vorr%c.i32\t%12-15,22R, %E"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
|
|
|
|
|
|
0xf2800130, 0xfeb809b0, "vbic%c.i32\t%12-15,22R, %E"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
|
|
|
|
|
|
0xf2800010, 0xfeb808b0, "vmov%c.i32\t%12-15,22R, %E"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
|
|
|
|
|
|
0xf2800030, 0xfeb808b0, "vmvn%c.i32\t%12-15,22R, %E"},
|
2006-04-26 17:40:55 +02:00
|
|
|
|
|
2009-06-30 13:57:05 +02:00
|
|
|
|
/* Two registers and a shift amount. */
|
2015-03-24 07:08:08 +01:00
|
|
|
|
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
|
|
|
|
|
|
0xf2880810, 0xffb80fd0, "vshrn%c.i16\t%12-15,22D, %0-3,5Q, #%16-18e"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
|
|
|
|
|
|
0xf2880850, 0xffb80fd0, "vrshrn%c.i16\t%12-15,22D, %0-3,5Q, #%16-18e"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
|
|
|
|
|
|
0xf2880810, 0xfeb80fd0, "vqshrun%c.s16\t%12-15,22D, %0-3,5Q, #%16-18e"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
|
|
|
|
|
|
0xf2880850, 0xfeb80fd0, "vqrshrun%c.s16\t%12-15,22D, %0-3,5Q, #%16-18e"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
|
|
|
|
|
|
0xf2880910, 0xfeb80fd0, "vqshrn%c.%24?us16\t%12-15,22D, %0-3,5Q, #%16-18e"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
|
|
|
|
|
|
0xf2880950, 0xfeb80fd0,
|
|
|
|
|
|
"vqrshrn%c.%24?us16\t%12-15,22D, %0-3,5Q, #%16-18e"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
|
|
|
|
|
|
0xf2880a10, 0xfeb80fd0, "vshll%c.%24?us8\t%12-15,22Q, %0-3,5D, #%16-18d"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
|
|
|
|
|
|
0xf2900810, 0xffb00fd0, "vshrn%c.i32\t%12-15,22D, %0-3,5Q, #%16-19e"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
|
|
|
|
|
|
0xf2900850, 0xffb00fd0, "vrshrn%c.i32\t%12-15,22D, %0-3,5Q, #%16-19e"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
|
|
|
|
|
|
0xf2880510, 0xffb80f90, "vshl%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18d"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
|
|
|
|
|
|
0xf3880410, 0xffb80f90, "vsri%c.8\t%12-15,22R, %0-3,5R, #%16-18e"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
|
|
|
|
|
|
0xf3880510, 0xffb80f90, "vsli%c.8\t%12-15,22R, %0-3,5R, #%16-18d"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
|
|
|
|
|
|
0xf3880610, 0xffb80f90, "vqshlu%c.s8\t%12-15,22R, %0-3,5R, #%16-18d"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
|
|
|
|
|
|
0xf2900810, 0xfeb00fd0, "vqshrun%c.s32\t%12-15,22D, %0-3,5Q, #%16-19e"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
|
|
|
|
|
|
0xf2900850, 0xfeb00fd0, "vqrshrun%c.s32\t%12-15,22D, %0-3,5Q, #%16-19e"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
|
|
|
|
|
|
0xf2900910, 0xfeb00fd0, "vqshrn%c.%24?us32\t%12-15,22D, %0-3,5Q, #%16-19e"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
|
|
|
|
|
|
0xf2900950, 0xfeb00fd0,
|
|
|
|
|
|
"vqrshrn%c.%24?us32\t%12-15,22D, %0-3,5Q, #%16-19e"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
|
|
|
|
|
|
0xf2900a10, 0xfeb00fd0, "vshll%c.%24?us16\t%12-15,22Q, %0-3,5D, #%16-19d"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
|
|
|
|
|
|
0xf2880010, 0xfeb80f90, "vshr%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18e"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
|
|
|
|
|
|
0xf2880110, 0xfeb80f90, "vsra%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18e"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
|
|
|
|
|
|
0xf2880210, 0xfeb80f90, "vrshr%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18e"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
|
|
|
|
|
|
0xf2880310, 0xfeb80f90, "vrsra%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18e"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
|
|
|
|
|
|
0xf2880710, 0xfeb80f90, "vqshl%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18d"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
|
|
|
|
|
|
0xf2a00810, 0xffa00fd0, "vshrn%c.i64\t%12-15,22D, %0-3,5Q, #%16-20e"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
|
|
|
|
|
|
0xf2a00850, 0xffa00fd0, "vrshrn%c.i64\t%12-15,22D, %0-3,5Q, #%16-20e"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
|
|
|
|
|
|
0xf2900510, 0xffb00f90, "vshl%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19d"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
|
|
|
|
|
|
0xf3900410, 0xffb00f90, "vsri%c.16\t%12-15,22R, %0-3,5R, #%16-19e"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
|
|
|
|
|
|
0xf3900510, 0xffb00f90, "vsli%c.16\t%12-15,22R, %0-3,5R, #%16-19d"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
|
|
|
|
|
|
0xf3900610, 0xffb00f90, "vqshlu%c.s16\t%12-15,22R, %0-3,5R, #%16-19d"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
|
|
|
|
|
|
0xf2a00a10, 0xfea00fd0, "vshll%c.%24?us32\t%12-15,22Q, %0-3,5D, #%16-20d"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
|
|
|
|
|
|
0xf2900010, 0xfeb00f90, "vshr%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19e"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
|
|
|
|
|
|
0xf2900110, 0xfeb00f90, "vsra%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19e"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
|
|
|
|
|
|
0xf2900210, 0xfeb00f90, "vrshr%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19e"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
|
|
|
|
|
|
0xf2900310, 0xfeb00f90, "vrsra%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19e"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
|
|
|
|
|
|
0xf2900710, 0xfeb00f90, "vqshl%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19d"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
|
|
|
|
|
|
0xf2a00810, 0xfea00fd0, "vqshrun%c.s64\t%12-15,22D, %0-3,5Q, #%16-20e"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
|
|
|
|
|
|
0xf2a00850, 0xfea00fd0, "vqrshrun%c.s64\t%12-15,22D, %0-3,5Q, #%16-20e"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
|
|
|
|
|
|
0xf2a00910, 0xfea00fd0, "vqshrn%c.%24?us64\t%12-15,22D, %0-3,5Q, #%16-20e"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
|
|
|
|
|
|
0xf2a00950, 0xfea00fd0,
|
|
|
|
|
|
"vqrshrn%c.%24?us64\t%12-15,22D, %0-3,5Q, #%16-20e"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
|
|
|
|
|
|
0xf2a00510, 0xffa00f90, "vshl%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20d"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
|
|
|
|
|
|
0xf3a00410, 0xffa00f90, "vsri%c.32\t%12-15,22R, %0-3,5R, #%16-20e"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
|
|
|
|
|
|
0xf3a00510, 0xffa00f90, "vsli%c.32\t%12-15,22R, %0-3,5R, #%16-20d"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
|
|
|
|
|
|
0xf3a00610, 0xffa00f90, "vqshlu%c.s32\t%12-15,22R, %0-3,5R, #%16-20d"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
|
|
|
|
|
|
0xf2a00010, 0xfea00f90, "vshr%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20e"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
|
|
|
|
|
|
0xf2a00110, 0xfea00f90, "vsra%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20e"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
|
|
|
|
|
|
0xf2a00210, 0xfea00f90, "vrshr%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20e"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
|
|
|
|
|
|
0xf2a00310, 0xfea00f90, "vrsra%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20e"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
|
|
|
|
|
|
0xf2a00710, 0xfea00f90, "vqshl%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20d"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
|
|
|
|
|
|
0xf2800590, 0xff800f90, "vshl%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21d"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
|
|
|
|
|
|
0xf3800490, 0xff800f90, "vsri%c.64\t%12-15,22R, %0-3,5R, #%16-21e"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
|
|
|
|
|
|
0xf3800590, 0xff800f90, "vsli%c.64\t%12-15,22R, %0-3,5R, #%16-21d"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
|
|
|
|
|
|
0xf3800690, 0xff800f90, "vqshlu%c.s64\t%12-15,22R, %0-3,5R, #%16-21d"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
|
|
|
|
|
|
0xf2800090, 0xfe800f90, "vshr%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21e"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
|
|
|
|
|
|
0xf2800190, 0xfe800f90, "vsra%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21e"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
|
|
|
|
|
|
0xf2800290, 0xfe800f90, "vrshr%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21e"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
|
|
|
|
|
|
0xf2800390, 0xfe800f90, "vrsra%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21e"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
|
|
|
|
|
|
0xf2800790, 0xfe800f90, "vqshl%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21d"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
|
|
|
|
|
|
0xf2a00e10, 0xfea00e90,
|
|
|
|
|
|
"vcvt%c.%24,8?usff32.%24,8?ffus32\t%12-15,22R, %0-3,5R, #%16-20e"},
|
2016-03-16 17:11:59 +01:00
|
|
|
|
{ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
|
|
|
|
|
|
0xf2a00c10, 0xfea00e90,
|
|
|
|
|
|
"vcvt%c.%24,8?usff16.%24,8?ffus16\t%12-15,22R, %0-3,5R, #%16-20e"},
|
2006-04-26 17:40:55 +02:00
|
|
|
|
|
2009-06-30 13:57:05 +02:00
|
|
|
|
/* Three registers of different lengths. */
|
2015-03-24 07:08:08 +01:00
|
|
|
|
{ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
|
|
|
|
|
|
0xf2a00e00, 0xfeb00f50, "vmull%c.p64\t%12-15,22Q, %16-19,7D, %0-3,5D"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
|
|
|
|
|
|
0xf2800e00, 0xfea00f50, "vmull%c.p%20S0\t%12-15,22Q, %16-19,7D, %0-3,5D"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
|
|
|
|
|
|
0xf2800400, 0xff800f50,
|
|
|
|
|
|
"vaddhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
|
|
|
|
|
|
0xf2800600, 0xff800f50,
|
|
|
|
|
|
"vsubhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
|
|
|
|
|
|
0xf2800900, 0xff800f50,
|
|
|
|
|
|
"vqdmlal%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %0-3,5D"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
|
|
|
|
|
|
0xf2800b00, 0xff800f50,
|
|
|
|
|
|
"vqdmlsl%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %0-3,5D"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
|
|
|
|
|
|
0xf2800d00, 0xff800f50,
|
|
|
|
|
|
"vqdmull%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %0-3,5D"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
|
|
|
|
|
|
0xf3800400, 0xff800f50,
|
|
|
|
|
|
"vraddhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
|
|
|
|
|
|
0xf3800600, 0xff800f50,
|
|
|
|
|
|
"vrsubhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
|
|
|
|
|
|
0xf2800000, 0xfe800f50,
|
|
|
|
|
|
"vaddl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
|
|
|
|
|
|
0xf2800100, 0xfe800f50,
|
|
|
|
|
|
"vaddw%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7Q, %0-3,5D"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
|
|
|
|
|
|
0xf2800200, 0xfe800f50,
|
|
|
|
|
|
"vsubl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
|
|
|
|
|
|
0xf2800300, 0xfe800f50,
|
|
|
|
|
|
"vsubw%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7Q, %0-3,5D"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
|
|
|
|
|
|
0xf2800500, 0xfe800f50,
|
|
|
|
|
|
"vabal%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
|
|
|
|
|
|
0xf2800700, 0xfe800f50,
|
|
|
|
|
|
"vabdl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
|
|
|
|
|
|
0xf2800800, 0xfe800f50,
|
|
|
|
|
|
"vmlal%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
|
|
|
|
|
|
0xf2800a00, 0xfe800f50,
|
|
|
|
|
|
"vmlsl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
|
|
|
|
|
|
0xf2800c00, 0xfe800f50,
|
|
|
|
|
|
"vmull%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
|
2006-04-26 17:40:55 +02:00
|
|
|
|
|
2009-06-30 13:57:05 +02:00
|
|
|
|
/* Two registers and a scalar. */
|
2015-03-24 07:08:08 +01:00
|
|
|
|
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
|
|
|
|
|
|
0xf2800040, 0xff800f50, "vmla%c.i%20-21S6\t%12-15,22D, %16-19,7D, %D"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
|
2016-04-05 16:54:00 +02:00
|
|
|
|
0xf2800140, 0xff900f50, "vmla%c.f%20-21Sa\t%12-15,22D, %16-19,7D, %D"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST),
|
|
|
|
|
|
0xf2900140, 0xffb00f50, "vmla%c.f16\t%12-15,22D, %16-19,7D, %D"},
|
2015-03-24 07:08:08 +01:00
|
|
|
|
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
|
|
|
|
|
|
0xf2800340, 0xff800f50, "vqdmlal%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
|
|
|
|
|
|
0xf2800440, 0xff800f50, "vmls%c.i%20-21S6\t%12-15,22D, %16-19,7D, %D"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
|
2016-04-05 16:54:00 +02:00
|
|
|
|
0xf2800540, 0xff900f50, "vmls%c.f%20-21S6\t%12-15,22D, %16-19,7D, %D"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST),
|
|
|
|
|
|
0xf2900540, 0xffb00f50, "vmls%c.f16\t%12-15,22D, %16-19,7D, %D"},
|
2015-03-24 07:08:08 +01:00
|
|
|
|
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
|
|
|
|
|
|
0xf2800740, 0xff800f50, "vqdmlsl%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
|
|
|
|
|
|
0xf2800840, 0xff800f50, "vmul%c.i%20-21S6\t%12-15,22D, %16-19,7D, %D"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
|
2016-04-05 16:54:00 +02:00
|
|
|
|
0xf2800940, 0xff900f50, "vmul%c.f%20-21Sa\t%12-15,22D, %16-19,7D, %D"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST),
|
|
|
|
|
|
0xf2900940, 0xffb00f50, "vmul%c.f16\t%12-15,22D, %16-19,7D, %D"},
|
2015-03-24 07:08:08 +01:00
|
|
|
|
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
|
|
|
|
|
|
0xf2800b40, 0xff800f50, "vqdmull%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
|
|
|
|
|
|
0xf2800c40, 0xff800f50, "vqdmulh%c.s%20-21S6\t%12-15,22D, %16-19,7D, %D"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
|
|
|
|
|
|
0xf2800d40, 0xff800f50, "vqrdmulh%c.s%20-21S6\t%12-15,22D, %16-19,7D, %D"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
|
|
|
|
|
|
0xf3800040, 0xff800f50, "vmla%c.i%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
|
2016-04-05 16:54:00 +02:00
|
|
|
|
0xf3800140, 0xff900f50, "vmla%c.f%20-21Sa\t%12-15,22Q, %16-19,7Q, %D"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST),
|
|
|
|
|
|
0xf3900140, 0xffb00f50, "vmla%c.f16\t%12-15,22Q, %16-19,7Q, %D"},
|
2015-03-24 07:08:08 +01:00
|
|
|
|
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
|
|
|
|
|
|
0xf3800440, 0xff800f50, "vmls%c.i%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
|
2016-04-05 16:54:00 +02:00
|
|
|
|
0xf3800540, 0xff900f50, "vmls%c.f%20-21Sa\t%12-15,22Q, %16-19,7Q, %D"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST),
|
|
|
|
|
|
0xf3900540, 0xffb00f50, "vmls%c.f16\t%12-15,22Q, %16-19,7Q, %D"},
|
2015-03-24 07:08:08 +01:00
|
|
|
|
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
|
|
|
|
|
|
0xf3800840, 0xff800f50, "vmul%c.i%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
|
2016-04-05 16:54:00 +02:00
|
|
|
|
0xf3800940, 0xff900f50, "vmul%c.f%20-21Sa\t%12-15,22Q, %16-19,7Q, %D"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST),
|
|
|
|
|
|
0xf3900940, 0xffb00f50, "vmul%c.f16\t%12-15,22Q, %16-19,7Q, %D"},
|
2015-03-24 07:08:08 +01:00
|
|
|
|
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
|
|
|
|
|
|
0xf3800c40, 0xff800f50, "vqdmulh%c.s%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
|
|
|
|
|
|
0xf3800d40, 0xff800f50, "vqrdmulh%c.s%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
|
|
|
|
|
|
0xf2800240, 0xfe800f50,
|
|
|
|
|
|
"vmlal%c.%24?us%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
|
|
|
|
|
|
0xf2800640, 0xfe800f50,
|
|
|
|
|
|
"vmlsl%c.%24?us%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
|
|
|
|
|
|
0xf2800a40, 0xfe800f50,
|
|
|
|
|
|
"vmull%c.%24?us%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
|
2015-06-02 13:35:21 +02:00
|
|
|
|
{ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA),
|
|
|
|
|
|
0xf2800e40, 0xff800f50,
|
|
|
|
|
|
"vqrdmlah%c.s%20-21S6\t%12-15,22D, %16-19,7D, %D"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA),
|
|
|
|
|
|
0xf2800f40, 0xff800f50,
|
|
|
|
|
|
"vqrdmlsh%c.s%20-21S6\t%12-15,22D, %16-19,7D, %D"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA),
|
|
|
|
|
|
0xf3800e40, 0xff800f50,
|
|
|
|
|
|
"vqrdmlah%c.s%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA),
|
|
|
|
|
|
0xf3800f40, 0xff800f50,
|
|
|
|
|
|
"vqrdmlsh%c.s%20-21S6\t%12-15,22Q, %16-19,7Q, %D"
|
|
|
|
|
|
},
|
2006-04-26 17:40:55 +02:00
|
|
|
|
|
2009-06-30 13:57:05 +02:00
|
|
|
|
/* Element and structure load/store. */
|
2015-03-24 07:08:08 +01:00
|
|
|
|
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
|
|
|
|
|
|
0xf4a00fc0, 0xffb00fc0, "vld4%c.32\t%C"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
|
|
|
|
|
|
0xf4a00c00, 0xffb00f00, "vld1%c.%6-7S2\t%C"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
|
|
|
|
|
|
0xf4a00d00, 0xffb00f00, "vld2%c.%6-7S2\t%C"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
|
|
|
|
|
|
0xf4a00e00, 0xffb00f00, "vld3%c.%6-7S2\t%C"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
|
|
|
|
|
|
0xf4a00f00, 0xffb00f00, "vld4%c.%6-7S2\t%C"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
|
|
|
|
|
|
0xf4000200, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3\t%A"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
|
|
|
|
|
|
0xf4000300, 0xff900f00, "v%21?ls%21?dt2%c.%6-7S2\t%A"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
|
|
|
|
|
|
0xf4000400, 0xff900f00, "v%21?ls%21?dt3%c.%6-7S2\t%A"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
|
|
|
|
|
|
0xf4000500, 0xff900f00, "v%21?ls%21?dt3%c.%6-7S2\t%A"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
|
|
|
|
|
|
0xf4000600, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3\t%A"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
|
|
|
|
|
|
0xf4000700, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3\t%A"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
|
|
|
|
|
|
0xf4000800, 0xff900f00, "v%21?ls%21?dt2%c.%6-7S2\t%A"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
|
|
|
|
|
|
0xf4000900, 0xff900f00, "v%21?ls%21?dt2%c.%6-7S2\t%A"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
|
|
|
|
|
|
0xf4000a00, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3\t%A"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
|
|
|
|
|
|
0xf4000000, 0xff900e00, "v%21?ls%21?dt4%c.%6-7S2\t%A"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
|
|
|
|
|
|
0xf4800000, 0xff900300, "v%21?ls%21?dt1%c.%10-11S2\t%B"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
|
|
|
|
|
|
0xf4800100, 0xff900300, "v%21?ls%21?dt2%c.%10-11S2\t%B"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
|
|
|
|
|
|
0xf4800200, 0xff900300, "v%21?ls%21?dt3%c.%10-11S2\t%B"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
|
|
|
|
|
|
0xf4800300, 0xff900300, "v%21?ls%21?dt4%c.%10-11S2\t%B"},
|
|
|
|
|
|
|
|
|
|
|
|
{ARM_FEATURE_CORE_LOW (0), 0 ,0, 0}
|
2006-04-26 17:40:55 +02:00
|
|
|
|
};
|
|
|
|
|
|
|
2005-09-02 Paul Brook <paul@codesourcery.com>
bfd/
* libbdf.h: Regenerate.
* bfd-in2.h: Regenerate.
* reloc.c: Add BFD_RELOC_ARM_T32_CP_OFF_IMM and
BFD_RELOC_ARM_T32_CP_OFF_IMM_S2.
gas/
* config/tc-arm.c (encode_arm_cp_address): Use
BFD_RELOC_ARM_T32_CP_OFF_IMM in thumb mode.
(do_iwmmxt_wldstbh): Use BFD_RELOC_ARM_T32_CP_OFF_IMM_S2 in thumb
mode.
(md_assemble): Only allow coprocessor instructions when Thumb-2 is
available.
(cCE, cC3): Define.
(insns): Use them for coprocessor instructions.
(md_pcrel_from_section): Handle BFD_RELOC_ARM_T32_CP_OFF_IMM.
(get_thumb32_insn): New function.
(put_thumb32_insn): New function.
(md_apply_fix): Handle BFD_RELOC_ARM_T32_CP_OFF_IMM and
BFD_RELOC_ARM_T32_CP_OFF_IMM_S2.
gas/testsuite/
* gas/arm/vfp-bad_t2.d, gas/arm/vfp-bad_t2.l, arm/vfp-bad_t2.s,
gas/arm/vfp1_t2.d, gas/arm/vfp1_t2.s, gas/arm/vfp1xD_t2.d,
gas/arm/vfp1xD_t2.s, gas/arm/vfp2_t2.d, gas/arm/vfp2_t2.s): New files.
opcodes/
* arm-dis.c (coprocessor_opcodes): New.
(arm_opcodes, thumb32_opcodes): Remove coprocessor insns.
(print_insn_coprocessor): New function.
(print_insn_arm): Use print_insn_coprocessor. Remove coprocessor
format characters.
(print_insn_thumb32): Use print_insn_coprocessor.
2005-09-02 15:12:45 +02:00
|
|
|
|
/* Opcode tables: ARM, 16-bit Thumb, 32-bit Thumb. All three are partially
|
|
|
|
|
|
ordered: they must be searched linearly from the top to obtain a correct
|
|
|
|
|
|
match. */
|
|
|
|
|
|
|
|
|
|
|
|
/* print_insn_arm recognizes the following format control codes:
|
|
|
|
|
|
|
|
|
|
|
|
%% %
|
|
|
|
|
|
|
|
|
|
|
|
%a print address for ldr/str instruction
|
|
|
|
|
|
%s print address for ldr/str halfword/signextend instruction
|
2009-11-11 10:44:45 +01:00
|
|
|
|
%S like %s but allow UNPREDICTABLE addressing
|
2005-09-02 Paul Brook <paul@codesourcery.com>
bfd/
* libbdf.h: Regenerate.
* bfd-in2.h: Regenerate.
* reloc.c: Add BFD_RELOC_ARM_T32_CP_OFF_IMM and
BFD_RELOC_ARM_T32_CP_OFF_IMM_S2.
gas/
* config/tc-arm.c (encode_arm_cp_address): Use
BFD_RELOC_ARM_T32_CP_OFF_IMM in thumb mode.
(do_iwmmxt_wldstbh): Use BFD_RELOC_ARM_T32_CP_OFF_IMM_S2 in thumb
mode.
(md_assemble): Only allow coprocessor instructions when Thumb-2 is
available.
(cCE, cC3): Define.
(insns): Use them for coprocessor instructions.
(md_pcrel_from_section): Handle BFD_RELOC_ARM_T32_CP_OFF_IMM.
(get_thumb32_insn): New function.
(put_thumb32_insn): New function.
(md_apply_fix): Handle BFD_RELOC_ARM_T32_CP_OFF_IMM and
BFD_RELOC_ARM_T32_CP_OFF_IMM_S2.
gas/testsuite/
* gas/arm/vfp-bad_t2.d, gas/arm/vfp-bad_t2.l, arm/vfp-bad_t2.s,
gas/arm/vfp1_t2.d, gas/arm/vfp1_t2.s, gas/arm/vfp1xD_t2.d,
gas/arm/vfp1xD_t2.s, gas/arm/vfp2_t2.d, gas/arm/vfp2_t2.s): New files.
opcodes/
* arm-dis.c (coprocessor_opcodes): New.
(arm_opcodes, thumb32_opcodes): Remove coprocessor insns.
(print_insn_coprocessor): New function.
(print_insn_arm): Use print_insn_coprocessor. Remove coprocessor
format characters.
(print_insn_thumb32): Use print_insn_coprocessor.
2005-09-02 15:12:45 +02:00
|
|
|
|
%b print branch destination
|
|
|
|
|
|
%c print condition code (always bits 28-31)
|
|
|
|
|
|
%m print register mask for ldm/stm instruction
|
|
|
|
|
|
%o print operand2 (immediate or register + shift)
|
|
|
|
|
|
%p print 'p' iff bits 12-15 are 15
|
|
|
|
|
|
%t print 't' iff bit 21 set and bit 24 clear
|
|
|
|
|
|
%B print arm BLX(1) destination
|
|
|
|
|
|
%C print the PSR sub type.
|
2006-02-24 Paul Brook <paul@codesourcery.com>
gas/
* config/arm/tc-arm.c (arm_ext_v6_notm, arm_ext_div, arm_ext_v7,
arm_ext_v7a, arm_ext_v7r, arm_ext_v7m): New variables.
(struct asm_barrier_opt): Define.
(arm_v7m_psr_hsh, arm_barrier_opt_hsh): New variables.
(parse_psr): Accept V7M psr names.
(parse_barrier): New function.
(enum operand_parse_code): Add OP_oBARRIER.
(parse_operands): Implement OP_oBARRIER.
(do_barrier): New function.
(do_dbg, do_pli, do_t_barrier, do_t_dbg, do_t_div): New functions.
(do_t_cpsi): Add V7M restrictions.
(do_t_mrs, do_t_msr): Validate V7M variants.
(md_assemble): Check for NULL variants.
(v7m_psrs, barrier_opt_names): New tables.
(insns): Add V7 instructions. Mark V6 instructions absent from V7M.
(md_begin): Initialize arm_v7m_psr_hsh and arm_barrier_opt_hsh.
(arm_cpu_option_table): Add Cortex-M3, R4 and A8.
(arm_arch_option_table): Add armv7, armv7a, armv7r and armv7m.
(struct cpu_arch_ver_table): Define.
(cpu_arch_ver): New.
(aeabi_set_public_attributes): Use cpu_arch_ver. Set
Tag_CPU_arch_profile.
* doc/c-arm.texi: Document new cpu and arch options.
gas/testsuite/
* gas/arm/thumb32.d: Fix expected msr and mrs output.
* gas/arm/arch7.d: New test.
* gas/arm/arch7.s: New test.
* gas/arm/arch7m-bad.l: New test.
* gas/arm/arch7m-bad.d: New test.
* gas/arm/arch7m-bad.s: New test.
include/opcode/
* arm.h: Add V7 feature bits.
opcodes/
* arm-dis.c (arm_opcodes): Add V7 instructions.
(thumb32_opcodes): Ditto. Handle V7M MSR/MRS variants.
(print_arm_address): New function.
(print_insn_arm): Use it. Add 'P' and 'U' cases.
(psr_name): New function.
(print_insn_thumb32): Add 'U', 'C' and 'D' cases.
2006-02-24 16:36:36 +01:00
|
|
|
|
%U print barrier type.
|
|
|
|
|
|
%P print address for pli instruction.
|
2005-09-02 Paul Brook <paul@codesourcery.com>
bfd/
* libbdf.h: Regenerate.
* bfd-in2.h: Regenerate.
* reloc.c: Add BFD_RELOC_ARM_T32_CP_OFF_IMM and
BFD_RELOC_ARM_T32_CP_OFF_IMM_S2.
gas/
* config/tc-arm.c (encode_arm_cp_address): Use
BFD_RELOC_ARM_T32_CP_OFF_IMM in thumb mode.
(do_iwmmxt_wldstbh): Use BFD_RELOC_ARM_T32_CP_OFF_IMM_S2 in thumb
mode.
(md_assemble): Only allow coprocessor instructions when Thumb-2 is
available.
(cCE, cC3): Define.
(insns): Use them for coprocessor instructions.
(md_pcrel_from_section): Handle BFD_RELOC_ARM_T32_CP_OFF_IMM.
(get_thumb32_insn): New function.
(put_thumb32_insn): New function.
(md_apply_fix): Handle BFD_RELOC_ARM_T32_CP_OFF_IMM and
BFD_RELOC_ARM_T32_CP_OFF_IMM_S2.
gas/testsuite/
* gas/arm/vfp-bad_t2.d, gas/arm/vfp-bad_t2.l, arm/vfp-bad_t2.s,
gas/arm/vfp1_t2.d, gas/arm/vfp1_t2.s, gas/arm/vfp1xD_t2.d,
gas/arm/vfp1xD_t2.s, gas/arm/vfp2_t2.d, gas/arm/vfp2_t2.s): New files.
opcodes/
* arm-dis.c (coprocessor_opcodes): New.
(arm_opcodes, thumb32_opcodes): Remove coprocessor insns.
(print_insn_coprocessor): New function.
(print_insn_arm): Use print_insn_coprocessor. Remove coprocessor
format characters.
(print_insn_thumb32): Use print_insn_coprocessor.
2005-09-02 15:12:45 +02:00
|
|
|
|
|
|
|
|
|
|
%<bitfield>r print as an ARM register
|
2012-08-24 10:03:39 +02:00
|
|
|
|
%<bitfield>T print as an ARM register + 1
|
2009-12-17 10:52:18 +01:00
|
|
|
|
%<bitfield>R as %r but r15 is UNPREDICTABLE
|
|
|
|
|
|
%<bitfield>{r|R}u as %{r|R} but if matches the other %u field then is UNPREDICTABLE
|
|
|
|
|
|
%<bitfield>{r|R}U as %{r|R} but if matches the other %U field then is UNPREDICTABLE
|
2005-09-02 Paul Brook <paul@codesourcery.com>
bfd/
* libbdf.h: Regenerate.
* bfd-in2.h: Regenerate.
* reloc.c: Add BFD_RELOC_ARM_T32_CP_OFF_IMM and
BFD_RELOC_ARM_T32_CP_OFF_IMM_S2.
gas/
* config/tc-arm.c (encode_arm_cp_address): Use
BFD_RELOC_ARM_T32_CP_OFF_IMM in thumb mode.
(do_iwmmxt_wldstbh): Use BFD_RELOC_ARM_T32_CP_OFF_IMM_S2 in thumb
mode.
(md_assemble): Only allow coprocessor instructions when Thumb-2 is
available.
(cCE, cC3): Define.
(insns): Use them for coprocessor instructions.
(md_pcrel_from_section): Handle BFD_RELOC_ARM_T32_CP_OFF_IMM.
(get_thumb32_insn): New function.
(put_thumb32_insn): New function.
(md_apply_fix): Handle BFD_RELOC_ARM_T32_CP_OFF_IMM and
BFD_RELOC_ARM_T32_CP_OFF_IMM_S2.
gas/testsuite/
* gas/arm/vfp-bad_t2.d, gas/arm/vfp-bad_t2.l, arm/vfp-bad_t2.s,
gas/arm/vfp1_t2.d, gas/arm/vfp1_t2.s, gas/arm/vfp1xD_t2.d,
gas/arm/vfp1xD_t2.s, gas/arm/vfp2_t2.d, gas/arm/vfp2_t2.s): New files.
opcodes/
* arm-dis.c (coprocessor_opcodes): New.
(arm_opcodes, thumb32_opcodes): Remove coprocessor insns.
(print_insn_coprocessor): New function.
(print_insn_arm): Use print_insn_coprocessor. Remove coprocessor
format characters.
(print_insn_thumb32): Use print_insn_coprocessor.
2005-09-02 15:12:45 +02:00
|
|
|
|
%<bitfield>d print the bitfield in decimal
|
2015-08-12 13:45:07 +02:00
|
|
|
|
%<bitfield>W print the bitfield plus one in decimal
|
2005-09-02 Paul Brook <paul@codesourcery.com>
bfd/
* libbdf.h: Regenerate.
* bfd-in2.h: Regenerate.
* reloc.c: Add BFD_RELOC_ARM_T32_CP_OFF_IMM and
BFD_RELOC_ARM_T32_CP_OFF_IMM_S2.
gas/
* config/tc-arm.c (encode_arm_cp_address): Use
BFD_RELOC_ARM_T32_CP_OFF_IMM in thumb mode.
(do_iwmmxt_wldstbh): Use BFD_RELOC_ARM_T32_CP_OFF_IMM_S2 in thumb
mode.
(md_assemble): Only allow coprocessor instructions when Thumb-2 is
available.
(cCE, cC3): Define.
(insns): Use them for coprocessor instructions.
(md_pcrel_from_section): Handle BFD_RELOC_ARM_T32_CP_OFF_IMM.
(get_thumb32_insn): New function.
(put_thumb32_insn): New function.
(md_apply_fix): Handle BFD_RELOC_ARM_T32_CP_OFF_IMM and
BFD_RELOC_ARM_T32_CP_OFF_IMM_S2.
gas/testsuite/
* gas/arm/vfp-bad_t2.d, gas/arm/vfp-bad_t2.l, arm/vfp-bad_t2.s,
gas/arm/vfp1_t2.d, gas/arm/vfp1_t2.s, gas/arm/vfp1xD_t2.d,
gas/arm/vfp1xD_t2.s, gas/arm/vfp2_t2.d, gas/arm/vfp2_t2.s): New files.
opcodes/
* arm-dis.c (coprocessor_opcodes): New.
(arm_opcodes, thumb32_opcodes): Remove coprocessor insns.
(print_insn_coprocessor): New function.
(print_insn_arm): Use print_insn_coprocessor. Remove coprocessor
format characters.
(print_insn_thumb32): Use print_insn_coprocessor.
2005-09-02 15:12:45 +02:00
|
|
|
|
%<bitfield>x print the bitfield in hex
|
|
|
|
|
|
%<bitfield>X print the bitfield as 1 hex digit without leading "0x"
|
2015-08-12 13:45:07 +02:00
|
|
|
|
|
2006-04-26 17:40:55 +02:00
|
|
|
|
%<bitfield>'c print specified char iff bitfield is all ones
|
|
|
|
|
|
%<bitfield>`c print specified char iff bitfield is all zeroes
|
|
|
|
|
|
%<bitfield>?ab... select from array of values in big endian order
|
2005-06-08 00:16:52 +02:00
|
|
|
|
|
2005-09-02 Paul Brook <paul@codesourcery.com>
bfd/
* libbdf.h: Regenerate.
* bfd-in2.h: Regenerate.
* reloc.c: Add BFD_RELOC_ARM_T32_CP_OFF_IMM and
BFD_RELOC_ARM_T32_CP_OFF_IMM_S2.
gas/
* config/tc-arm.c (encode_arm_cp_address): Use
BFD_RELOC_ARM_T32_CP_OFF_IMM in thumb mode.
(do_iwmmxt_wldstbh): Use BFD_RELOC_ARM_T32_CP_OFF_IMM_S2 in thumb
mode.
(md_assemble): Only allow coprocessor instructions when Thumb-2 is
available.
(cCE, cC3): Define.
(insns): Use them for coprocessor instructions.
(md_pcrel_from_section): Handle BFD_RELOC_ARM_T32_CP_OFF_IMM.
(get_thumb32_insn): New function.
(put_thumb32_insn): New function.
(md_apply_fix): Handle BFD_RELOC_ARM_T32_CP_OFF_IMM and
BFD_RELOC_ARM_T32_CP_OFF_IMM_S2.
gas/testsuite/
* gas/arm/vfp-bad_t2.d, gas/arm/vfp-bad_t2.l, arm/vfp-bad_t2.s,
gas/arm/vfp1_t2.d, gas/arm/vfp1_t2.s, gas/arm/vfp1xD_t2.d,
gas/arm/vfp1xD_t2.s, gas/arm/vfp2_t2.d, gas/arm/vfp2_t2.s): New files.
opcodes/
* arm-dis.c (coprocessor_opcodes): New.
(arm_opcodes, thumb32_opcodes): Remove coprocessor insns.
(print_insn_coprocessor): New function.
(print_insn_arm): Use print_insn_coprocessor. Remove coprocessor
format characters.
(print_insn_thumb32): Use print_insn_coprocessor.
2005-09-02 15:12:45 +02:00
|
|
|
|
%e print arm SMI operand (bits 0..7,8..19).
|
|
|
|
|
|
%E print the LSB and WIDTH fields of a BFI or BFC instruction.
|
2010-09-23 17:52:19 +02:00
|
|
|
|
%V print the 16-bit immediate field of a MOVT or MOVW instruction.
|
|
|
|
|
|
%R print the SPSR/CPSR or banked register of an MRS. */
|
2004-11-27 12:09:21 +01:00
|
|
|
|
|
2005-09-02 Paul Brook <paul@codesourcery.com>
bfd/
* libbdf.h: Regenerate.
* bfd-in2.h: Regenerate.
* reloc.c: Add BFD_RELOC_ARM_T32_CP_OFF_IMM and
BFD_RELOC_ARM_T32_CP_OFF_IMM_S2.
gas/
* config/tc-arm.c (encode_arm_cp_address): Use
BFD_RELOC_ARM_T32_CP_OFF_IMM in thumb mode.
(do_iwmmxt_wldstbh): Use BFD_RELOC_ARM_T32_CP_OFF_IMM_S2 in thumb
mode.
(md_assemble): Only allow coprocessor instructions when Thumb-2 is
available.
(cCE, cC3): Define.
(insns): Use them for coprocessor instructions.
(md_pcrel_from_section): Handle BFD_RELOC_ARM_T32_CP_OFF_IMM.
(get_thumb32_insn): New function.
(put_thumb32_insn): New function.
(md_apply_fix): Handle BFD_RELOC_ARM_T32_CP_OFF_IMM and
BFD_RELOC_ARM_T32_CP_OFF_IMM_S2.
gas/testsuite/
* gas/arm/vfp-bad_t2.d, gas/arm/vfp-bad_t2.l, arm/vfp-bad_t2.s,
gas/arm/vfp1_t2.d, gas/arm/vfp1_t2.s, gas/arm/vfp1xD_t2.d,
gas/arm/vfp1xD_t2.s, gas/arm/vfp2_t2.d, gas/arm/vfp2_t2.s): New files.
opcodes/
* arm-dis.c (coprocessor_opcodes): New.
(arm_opcodes, thumb32_opcodes): Remove coprocessor insns.
(print_insn_coprocessor): New function.
(print_insn_arm): Use print_insn_coprocessor. Remove coprocessor
format characters.
(print_insn_thumb32): Use print_insn_coprocessor.
2005-09-02 15:12:45 +02:00
|
|
|
|
static const struct opcode32 arm_opcodes[] =
|
|
|
|
|
|
{
|
|
|
|
|
|
/* ARM instructions. */
|
2015-03-24 07:08:08 +01:00
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
|
|
|
|
|
|
0xe1a00000, 0xffffffff, "nop\t\t\t; (mov r0, r0)"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
|
|
|
|
|
|
0xe7f000f0, 0xfff000f0, "udf\t#%e"},
|
|
|
|
|
|
|
|
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V4T | ARM_EXT_V5),
|
|
|
|
|
|
0x012FFF10, 0x0ffffff0, "bx%c\t%0-3r"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
|
|
|
|
|
|
0x00000090, 0x0fe000f0, "mul%20's%c\t%16-19R, %0-3R, %8-11R"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
|
|
|
|
|
|
0x00200090, 0x0fe000f0, "mla%20's%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V2S),
|
|
|
|
|
|
0x01000090, 0x0fb00ff0, "swp%22'b%c\t%12-15RU, %0-3Ru, [%16-19RuU]"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V3M),
|
|
|
|
|
|
0x00800090, 0x0fa000f0,
|
|
|
|
|
|
"%22?sumull%20's%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V3M),
|
|
|
|
|
|
0x00a00090, 0x0fa000f0,
|
|
|
|
|
|
"%22?sumlal%20's%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
|
include/elf:
* arm.h: Import complete list of official relocation names
and numbers from AAELF. Define FAKE_RELOCs for old names.
Remove a few old names no longer used anywhere.
bfd:
* elf32-arm.c: Wherever possible, use official reloc names
from AAELF.
(elf32_arm_howto_table, elf32_arm_tls_gd32_howto)
(elf32_arm_tls_ldo32_howto, elf32_arm_tls_ldm32_howto)
(elf32_arm_tls_le32_howto, elf32_arm_tls_ie32_howto)
(elf32_arm_vtinherit_howto, elf32_arm_vtentry_howto)
(elf32_arm_pc11_howto, elf32_arm_thm_pc9_howto, elf32_arm_got_prel)
(elf32_arm_r_howto): Replace with elf32_arm_howto_table_1,
elf32_arm_howto_table_2, and elf32_arm_howto_table_3.
Add many new relocations from AAELF.
(elf32_arm_howto_from_type): Update to match.
(elf32_arm_reloc_map): Add entries for R_ARM_THM_JUMP24,
R_ARM_THM_JUMP11, R_ARM_THM_JUMP19, R_ARM_THM_JUMP8,
R_ARM_THM_JUMP6, R_ARM_GNU_VTINHERIT, and R_ARM_GNU_VTENTRY.
(elf32_arm_reloc_type_lookup): Use elf32_arm_howto_from_type.
(elf32_arm_final_link_relocate): Add support for
R_ARM_THM_JUMP24, R_ARM_THM_JUMP19, R_ARM_THM_JUMP6. Remove
case entries redundant with default.
* reloc.c: Reorganize ARM relocations. Add Thumb
assembler-internal relocations BFD_RELOC_ARM_T32_OFFSET_U8,
BFD_RELOC_ARM_T32_OFFSET_IMM, BFD_RELOC_ARM_T32_IMMEDIATE.
Add visible relocations BFD_RELOC_THUMB_PCREL_BRANCH7,
BFD_RELOC_THUMB_BRANCH20, BFD_RELOC_THUMB_BRANCH25.
Delete unused relocations BFD_RELOC_ARM_GOT12, BFD_RELOC_ARM_COPY.
* bfd-in2.h, libbfd.h: Regenerate.
opcodes:
* arm-dis.c (thumb_opcodes): Add disassembly for V6T2 16-bit
instructions. Adjust disassembly of some opcodes to match
unified syntax.
(thumb32_opcodes): New table.
(print_insn_thumb): Rename print_insn_thumb16; don't handle
two-halfword branches here.
(print_insn_thumb32): New function.
(print_insn): Choose among print_insn_arm, print_insn_thumb16,
and print_insn_thumb32. Be consistent about order of
halfwords when printing 32-bit instructions.
gas:
* hash.c (hash_lookup): Add len parameter. All callers changed.
(hash_find_n): New interface.
* hash.h: Prototype hash_find_n.
* sb.c: Include as.h.
(scrub_from_sb, sb_to_scrub, scrub_position): New statics.
(sb_scrub_and_add_sb): New interface.
* sb.h: Prototype sb_scrub_and_add_sb.
* input-scrub.c (input_scrub_include_sb): Use sb_scrub_and_add_sb.
* config/tc-arm.h (TC_FORCE_RELOCATION_LOCAL): Remove
reference to BFD_RELOC_ARM_GOT12 which is never generated.
* config/tc-arm.c: Rewrite, adding Thumb-2 support.
gas/testsuite:
* gas/arm/arm.exp: Convert all existing "gas_test" tests to
"run_dump_test" tests. Run more tests unconditionally. Run new tests.
* gas/arm/arch4t.s, gas/arm/arch6zk.s, gas/arm/arm3.s, gas/arm/arm6.s
* gas/arm/arm7dm.s, gas/arm/bignum1.s, gas/arm/float.s
* gas/arm/immed.s, gas/arm/iwmmxt.s, gas/arm/offset.s, gas/arm/thumb.s:
Adjust to work as a dump test.
* gas/arm/arch4t.d, gas/arm/arch6zk.d, gas/arm/arm3.d, gas/arm/arm6.d
* gas/arm/arm7dm.d, gas/arm/bignum1.d, gas/arm/float.d
* gas/arm/immed.d, gas/arm/iwmmxt.d, gas/arm/offset.d, gas/arm/thumb.d:
New files.
* gas/arm/armv1-bad.l, gas/arm/armv1-bad.s: Remove tests for
diagnostics that don't happen in the first pass anymore.
* gas/arm/iwmmxt-bad.l, gas/arm/r15-bad.l, gas/arm/req.l
* gas/arm/vfp-bad.l:
Update expected diagnostics.
* gas/arm/pic.d: Update expected reloc name.
* gas/arm/thumbv6.d: CPY no longer appears in disassembly.
* gas/arm/r15-bad.s: Avoid two-argument mul.
* gas/arm/req.s: Adjust comments.
* gas/arm/maverick.d, gas/arm/maverick.s: Avoid inappropriate
use of PC.
* gas/arm/macro-1.d, gas/arm/macro1.s
* gas/arm/t16-bad.l, gas/arm/t16-bad.s
* gas/arm/tcompat.d, gas/arm/tcompat.s
* gas/arm/tcompat2.d, gas/arm/tcompat2.s
* gas/arm/thumb32.d, gas/arm/thumb32.s
New test pair.
ld/testsuite:
* ld-arm/mixed-app.d: Adjust expected disassembly a little.
2005-05-18 07:40:12 +02:00
|
|
|
|
|
2016-01-12 17:35:30 +01:00
|
|
|
|
/* V8.2 RAS extension instructions. */
|
2016-06-07 10:56:42 +02:00
|
|
|
|
{ARM_FEATURE_CORE_HIGH (ARM_EXT2_RAS),
|
2016-01-12 17:35:30 +01:00
|
|
|
|
0xe320f010, 0xffffffff, "esb"},
|
|
|
|
|
|
|
2012-08-24 10:01:18 +02:00
|
|
|
|
/* V8 instructions. */
|
2015-03-24 07:08:08 +01:00
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
|
|
|
|
|
|
0x0320f005, 0x0fffffff, "sevl"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
|
|
|
|
|
|
0xe1000070, 0xfff000f0, "hlt\t0x%16-19X%12-15X%8-11X%0-3X"},
|
Add assembler support for ARMv8-M Mainline
2015-12-24 Thomas Preud'homme <thomas.preudhomme@arm.com>
bfd/
(tag_cpu_arch_combine): Adjust v4t_plus_v6_m and comb array to account
for new TAG_CPU_ARCH_V4T_PLUS_V6_M value. Deal with NULL values in
comb array.
binutils/
* readelf.c (arm_attr_tag_CPU_arch): Add ARMv8-M Mainline Tag_CPU_arch
value.
(arm_attr_tag_THUMB_ISA_use): Add ARMv8-M Mainline Tag_THUMB_ISA_use
value.
gas/
* config/tc-arm.c (arm_ext_m): Include ARMv8-M.
(arm_ext_v8m): New feature for ARMv8-M.
(arm_ext_atomics): New feature for ARMv8 atomics.
(do_tt): New encoding function for TT* instructions.
(insns): Add new entries for ARMv8-M specific instructions and
reorganize the ones shared by ARMv8-M Mainline and ARMv8-A.
(arm_archs): Define armv8-m.main architecture.
(cpu_arch_ver): Define ARM_ARCH_V8M_MAIN architecture version and
clarify the ordering rule.
(aeabi_set_public_attributes): Use TAG_CPU_ARCH_* macro to refer to
Tag_CPU_arch values for ARMv7e-M detection. Add logic to keep setting
Tag_CPU_arch to ARMv8-A for -march=all. Also set Tag_CPU_arch_profile
to 'A' if extension bit for atomic instructions is set, unless it is
ARMv8-M. Set Tag_THUMB_ISA_use to 3 for ARMv8-M. Set Tag_DIV_use to 0
for ARMv8-M Mainline.
gas/testsuite/
* gas/arm/archv8m.s: New file.
* gas/arm/archv8m-main.d: Likewise.
* gas/arm/attr-march-armv8m.main.d: Likewise.
* gas/arm/any-armv8m.s: Likewise.
* gas/arm/any-armv8m.d: Likewise.
include/elf/
* arm.h (TAG_CPU_ARCH_V8M_MAIN): Declare.
(MAX_TAG_CPU_ARCH): Define to TAG_CPU_ARCH_V8M_MAIN.
(TAG_CPU_ARCH_V4T_PLUS_V6_M): Define to unused value 15.
include/opcode/
* arm.h (ARM_EXT2_ATOMICS): New extension bit.
(ARM_EXT2_V8M): Likewise.
(ARM_EXT_V8): Adjust comment with regards to atomics and remove
mention of legacy use for that bit.
(ARM_AEXT2_V8_1A): New architecture extension bitfield.
(ARM_AEXT2_V8_2A): Likewise.
(ARM_AEXT_V8M_MAIN): Likewise.
(ARM_AEXT2_V8M): Likewise.
(ARM_ARCH_V8A): Use ARM_EXT2_ATOMICS for features in second bitfield.
(ARM_ARCH_V8_1A): Likewise with ARM_AEXT2_V8_1A.
(ARM_ARCH_V8_2A): Likewise with ARM_AEXT2_V8_2A.
(ARM_ARCH_V8M_MAIN): New architecture feature bitfield.
(ARM_ARCH_V8A_FP): Use ARM_EXT2_ATOMICS for features in second bitfield
and reindent.
(ARM_ARCH_V8A_SIMD): Likewise.
(ARM_ARCH_V8A_CRYPTOV1): Likewise.
(ARM_ARCH_V8_1A_FP): Use ARM_AEXT2_V8_1A to set second bitfield of
feature bits.
(ARM_ARCH_V8_1A_SIMD): Likewise.
(ARM_ARCH_V8_1A_CRYPTOV1): Likewise.
opcodes/
* arm-dis.c (arm_opcodes): Guard lda, ldab, ldaex, ldaexb, ldaexh, stl,
stlb, stlh, stlex, stlexb and stlexh by ARM_EXT2_ATOMICS instead of
ARM_EXT_V8.
(thumb32_opcodes): Add entries for wide ARMv8-M instructions.
2015-12-24 10:16:19 +01:00
|
|
|
|
{ARM_FEATURE_CORE_HIGH (ARM_EXT2_ATOMICS),
|
2015-03-24 07:08:08 +01:00
|
|
|
|
0x01800e90, 0x0ff00ff0, "stlex%c\t%12-15r, %0-3r, [%16-19R]"},
|
Add assembler support for ARMv8-M Mainline
2015-12-24 Thomas Preud'homme <thomas.preudhomme@arm.com>
bfd/
(tag_cpu_arch_combine): Adjust v4t_plus_v6_m and comb array to account
for new TAG_CPU_ARCH_V4T_PLUS_V6_M value. Deal with NULL values in
comb array.
binutils/
* readelf.c (arm_attr_tag_CPU_arch): Add ARMv8-M Mainline Tag_CPU_arch
value.
(arm_attr_tag_THUMB_ISA_use): Add ARMv8-M Mainline Tag_THUMB_ISA_use
value.
gas/
* config/tc-arm.c (arm_ext_m): Include ARMv8-M.
(arm_ext_v8m): New feature for ARMv8-M.
(arm_ext_atomics): New feature for ARMv8 atomics.
(do_tt): New encoding function for TT* instructions.
(insns): Add new entries for ARMv8-M specific instructions and
reorganize the ones shared by ARMv8-M Mainline and ARMv8-A.
(arm_archs): Define armv8-m.main architecture.
(cpu_arch_ver): Define ARM_ARCH_V8M_MAIN architecture version and
clarify the ordering rule.
(aeabi_set_public_attributes): Use TAG_CPU_ARCH_* macro to refer to
Tag_CPU_arch values for ARMv7e-M detection. Add logic to keep setting
Tag_CPU_arch to ARMv8-A for -march=all. Also set Tag_CPU_arch_profile
to 'A' if extension bit for atomic instructions is set, unless it is
ARMv8-M. Set Tag_THUMB_ISA_use to 3 for ARMv8-M. Set Tag_DIV_use to 0
for ARMv8-M Mainline.
gas/testsuite/
* gas/arm/archv8m.s: New file.
* gas/arm/archv8m-main.d: Likewise.
* gas/arm/attr-march-armv8m.main.d: Likewise.
* gas/arm/any-armv8m.s: Likewise.
* gas/arm/any-armv8m.d: Likewise.
include/elf/
* arm.h (TAG_CPU_ARCH_V8M_MAIN): Declare.
(MAX_TAG_CPU_ARCH): Define to TAG_CPU_ARCH_V8M_MAIN.
(TAG_CPU_ARCH_V4T_PLUS_V6_M): Define to unused value 15.
include/opcode/
* arm.h (ARM_EXT2_ATOMICS): New extension bit.
(ARM_EXT2_V8M): Likewise.
(ARM_EXT_V8): Adjust comment with regards to atomics and remove
mention of legacy use for that bit.
(ARM_AEXT2_V8_1A): New architecture extension bitfield.
(ARM_AEXT2_V8_2A): Likewise.
(ARM_AEXT_V8M_MAIN): Likewise.
(ARM_AEXT2_V8M): Likewise.
(ARM_ARCH_V8A): Use ARM_EXT2_ATOMICS for features in second bitfield.
(ARM_ARCH_V8_1A): Likewise with ARM_AEXT2_V8_1A.
(ARM_ARCH_V8_2A): Likewise with ARM_AEXT2_V8_2A.
(ARM_ARCH_V8M_MAIN): New architecture feature bitfield.
(ARM_ARCH_V8A_FP): Use ARM_EXT2_ATOMICS for features in second bitfield
and reindent.
(ARM_ARCH_V8A_SIMD): Likewise.
(ARM_ARCH_V8A_CRYPTOV1): Likewise.
(ARM_ARCH_V8_1A_FP): Use ARM_AEXT2_V8_1A to set second bitfield of
feature bits.
(ARM_ARCH_V8_1A_SIMD): Likewise.
(ARM_ARCH_V8_1A_CRYPTOV1): Likewise.
opcodes/
* arm-dis.c (arm_opcodes): Guard lda, ldab, ldaex, ldaexb, ldaexh, stl,
stlb, stlh, stlex, stlexb and stlexh by ARM_EXT2_ATOMICS instead of
ARM_EXT_V8.
(thumb32_opcodes): Add entries for wide ARMv8-M instructions.
2015-12-24 10:16:19 +01:00
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
|
2015-03-24 07:08:08 +01:00
|
|
|
|
0x01900e9f, 0x0ff00fff, "ldaex%c\t%12-15r, [%16-19R]"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
|
|
|
|
|
|
0x01a00e90, 0x0ff00ff0, "stlexd%c\t%12-15r, %0-3r, %0-3T, [%16-19R]"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
|
|
|
|
|
|
0x01b00e9f, 0x0ff00fff, "ldaexd%c\t%12-15r, %12-15T, [%16-19R]"},
|
Add assembler support for ARMv8-M Mainline
2015-12-24 Thomas Preud'homme <thomas.preudhomme@arm.com>
bfd/
(tag_cpu_arch_combine): Adjust v4t_plus_v6_m and comb array to account
for new TAG_CPU_ARCH_V4T_PLUS_V6_M value. Deal with NULL values in
comb array.
binutils/
* readelf.c (arm_attr_tag_CPU_arch): Add ARMv8-M Mainline Tag_CPU_arch
value.
(arm_attr_tag_THUMB_ISA_use): Add ARMv8-M Mainline Tag_THUMB_ISA_use
value.
gas/
* config/tc-arm.c (arm_ext_m): Include ARMv8-M.
(arm_ext_v8m): New feature for ARMv8-M.
(arm_ext_atomics): New feature for ARMv8 atomics.
(do_tt): New encoding function for TT* instructions.
(insns): Add new entries for ARMv8-M specific instructions and
reorganize the ones shared by ARMv8-M Mainline and ARMv8-A.
(arm_archs): Define armv8-m.main architecture.
(cpu_arch_ver): Define ARM_ARCH_V8M_MAIN architecture version and
clarify the ordering rule.
(aeabi_set_public_attributes): Use TAG_CPU_ARCH_* macro to refer to
Tag_CPU_arch values for ARMv7e-M detection. Add logic to keep setting
Tag_CPU_arch to ARMv8-A for -march=all. Also set Tag_CPU_arch_profile
to 'A' if extension bit for atomic instructions is set, unless it is
ARMv8-M. Set Tag_THUMB_ISA_use to 3 for ARMv8-M. Set Tag_DIV_use to 0
for ARMv8-M Mainline.
gas/testsuite/
* gas/arm/archv8m.s: New file.
* gas/arm/archv8m-main.d: Likewise.
* gas/arm/attr-march-armv8m.main.d: Likewise.
* gas/arm/any-armv8m.s: Likewise.
* gas/arm/any-armv8m.d: Likewise.
include/elf/
* arm.h (TAG_CPU_ARCH_V8M_MAIN): Declare.
(MAX_TAG_CPU_ARCH): Define to TAG_CPU_ARCH_V8M_MAIN.
(TAG_CPU_ARCH_V4T_PLUS_V6_M): Define to unused value 15.
include/opcode/
* arm.h (ARM_EXT2_ATOMICS): New extension bit.
(ARM_EXT2_V8M): Likewise.
(ARM_EXT_V8): Adjust comment with regards to atomics and remove
mention of legacy use for that bit.
(ARM_AEXT2_V8_1A): New architecture extension bitfield.
(ARM_AEXT2_V8_2A): Likewise.
(ARM_AEXT_V8M_MAIN): Likewise.
(ARM_AEXT2_V8M): Likewise.
(ARM_ARCH_V8A): Use ARM_EXT2_ATOMICS for features in second bitfield.
(ARM_ARCH_V8_1A): Likewise with ARM_AEXT2_V8_1A.
(ARM_ARCH_V8_2A): Likewise with ARM_AEXT2_V8_2A.
(ARM_ARCH_V8M_MAIN): New architecture feature bitfield.
(ARM_ARCH_V8A_FP): Use ARM_EXT2_ATOMICS for features in second bitfield
and reindent.
(ARM_ARCH_V8A_SIMD): Likewise.
(ARM_ARCH_V8A_CRYPTOV1): Likewise.
(ARM_ARCH_V8_1A_FP): Use ARM_AEXT2_V8_1A to set second bitfield of
feature bits.
(ARM_ARCH_V8_1A_SIMD): Likewise.
(ARM_ARCH_V8_1A_CRYPTOV1): Likewise.
opcodes/
* arm-dis.c (arm_opcodes): Guard lda, ldab, ldaex, ldaexb, ldaexh, stl,
stlb, stlh, stlex, stlexb and stlexh by ARM_EXT2_ATOMICS instead of
ARM_EXT_V8.
(thumb32_opcodes): Add entries for wide ARMv8-M instructions.
2015-12-24 10:16:19 +01:00
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
|
2015-03-24 07:08:08 +01:00
|
|
|
|
0x01c00e90, 0x0ff00ff0, "stlexb%c\t%12-15r, %0-3r, [%16-19R]"},
|
Add assembler support for ARMv8-M Mainline
2015-12-24 Thomas Preud'homme <thomas.preudhomme@arm.com>
bfd/
(tag_cpu_arch_combine): Adjust v4t_plus_v6_m and comb array to account
for new TAG_CPU_ARCH_V4T_PLUS_V6_M value. Deal with NULL values in
comb array.
binutils/
* readelf.c (arm_attr_tag_CPU_arch): Add ARMv8-M Mainline Tag_CPU_arch
value.
(arm_attr_tag_THUMB_ISA_use): Add ARMv8-M Mainline Tag_THUMB_ISA_use
value.
gas/
* config/tc-arm.c (arm_ext_m): Include ARMv8-M.
(arm_ext_v8m): New feature for ARMv8-M.
(arm_ext_atomics): New feature for ARMv8 atomics.
(do_tt): New encoding function for TT* instructions.
(insns): Add new entries for ARMv8-M specific instructions and
reorganize the ones shared by ARMv8-M Mainline and ARMv8-A.
(arm_archs): Define armv8-m.main architecture.
(cpu_arch_ver): Define ARM_ARCH_V8M_MAIN architecture version and
clarify the ordering rule.
(aeabi_set_public_attributes): Use TAG_CPU_ARCH_* macro to refer to
Tag_CPU_arch values for ARMv7e-M detection. Add logic to keep setting
Tag_CPU_arch to ARMv8-A for -march=all. Also set Tag_CPU_arch_profile
to 'A' if extension bit for atomic instructions is set, unless it is
ARMv8-M. Set Tag_THUMB_ISA_use to 3 for ARMv8-M. Set Tag_DIV_use to 0
for ARMv8-M Mainline.
gas/testsuite/
* gas/arm/archv8m.s: New file.
* gas/arm/archv8m-main.d: Likewise.
* gas/arm/attr-march-armv8m.main.d: Likewise.
* gas/arm/any-armv8m.s: Likewise.
* gas/arm/any-armv8m.d: Likewise.
include/elf/
* arm.h (TAG_CPU_ARCH_V8M_MAIN): Declare.
(MAX_TAG_CPU_ARCH): Define to TAG_CPU_ARCH_V8M_MAIN.
(TAG_CPU_ARCH_V4T_PLUS_V6_M): Define to unused value 15.
include/opcode/
* arm.h (ARM_EXT2_ATOMICS): New extension bit.
(ARM_EXT2_V8M): Likewise.
(ARM_EXT_V8): Adjust comment with regards to atomics and remove
mention of legacy use for that bit.
(ARM_AEXT2_V8_1A): New architecture extension bitfield.
(ARM_AEXT2_V8_2A): Likewise.
(ARM_AEXT_V8M_MAIN): Likewise.
(ARM_AEXT2_V8M): Likewise.
(ARM_ARCH_V8A): Use ARM_EXT2_ATOMICS for features in second bitfield.
(ARM_ARCH_V8_1A): Likewise with ARM_AEXT2_V8_1A.
(ARM_ARCH_V8_2A): Likewise with ARM_AEXT2_V8_2A.
(ARM_ARCH_V8M_MAIN): New architecture feature bitfield.
(ARM_ARCH_V8A_FP): Use ARM_EXT2_ATOMICS for features in second bitfield
and reindent.
(ARM_ARCH_V8A_SIMD): Likewise.
(ARM_ARCH_V8A_CRYPTOV1): Likewise.
(ARM_ARCH_V8_1A_FP): Use ARM_AEXT2_V8_1A to set second bitfield of
feature bits.
(ARM_ARCH_V8_1A_SIMD): Likewise.
(ARM_ARCH_V8_1A_CRYPTOV1): Likewise.
opcodes/
* arm-dis.c (arm_opcodes): Guard lda, ldab, ldaex, ldaexb, ldaexh, stl,
stlb, stlh, stlex, stlexb and stlexh by ARM_EXT2_ATOMICS instead of
ARM_EXT_V8.
(thumb32_opcodes): Add entries for wide ARMv8-M instructions.
2015-12-24 10:16:19 +01:00
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
|
2015-03-24 07:08:08 +01:00
|
|
|
|
0x01d00e9f, 0x0ff00fff, "ldaexb%c\t%12-15r, [%16-19R]"},
|
Add assembler support for ARMv8-M Mainline
2015-12-24 Thomas Preud'homme <thomas.preudhomme@arm.com>
bfd/
(tag_cpu_arch_combine): Adjust v4t_plus_v6_m and comb array to account
for new TAG_CPU_ARCH_V4T_PLUS_V6_M value. Deal with NULL values in
comb array.
binutils/
* readelf.c (arm_attr_tag_CPU_arch): Add ARMv8-M Mainline Tag_CPU_arch
value.
(arm_attr_tag_THUMB_ISA_use): Add ARMv8-M Mainline Tag_THUMB_ISA_use
value.
gas/
* config/tc-arm.c (arm_ext_m): Include ARMv8-M.
(arm_ext_v8m): New feature for ARMv8-M.
(arm_ext_atomics): New feature for ARMv8 atomics.
(do_tt): New encoding function for TT* instructions.
(insns): Add new entries for ARMv8-M specific instructions and
reorganize the ones shared by ARMv8-M Mainline and ARMv8-A.
(arm_archs): Define armv8-m.main architecture.
(cpu_arch_ver): Define ARM_ARCH_V8M_MAIN architecture version and
clarify the ordering rule.
(aeabi_set_public_attributes): Use TAG_CPU_ARCH_* macro to refer to
Tag_CPU_arch values for ARMv7e-M detection. Add logic to keep setting
Tag_CPU_arch to ARMv8-A for -march=all. Also set Tag_CPU_arch_profile
to 'A' if extension bit for atomic instructions is set, unless it is
ARMv8-M. Set Tag_THUMB_ISA_use to 3 for ARMv8-M. Set Tag_DIV_use to 0
for ARMv8-M Mainline.
gas/testsuite/
* gas/arm/archv8m.s: New file.
* gas/arm/archv8m-main.d: Likewise.
* gas/arm/attr-march-armv8m.main.d: Likewise.
* gas/arm/any-armv8m.s: Likewise.
* gas/arm/any-armv8m.d: Likewise.
include/elf/
* arm.h (TAG_CPU_ARCH_V8M_MAIN): Declare.
(MAX_TAG_CPU_ARCH): Define to TAG_CPU_ARCH_V8M_MAIN.
(TAG_CPU_ARCH_V4T_PLUS_V6_M): Define to unused value 15.
include/opcode/
* arm.h (ARM_EXT2_ATOMICS): New extension bit.
(ARM_EXT2_V8M): Likewise.
(ARM_EXT_V8): Adjust comment with regards to atomics and remove
mention of legacy use for that bit.
(ARM_AEXT2_V8_1A): New architecture extension bitfield.
(ARM_AEXT2_V8_2A): Likewise.
(ARM_AEXT_V8M_MAIN): Likewise.
(ARM_AEXT2_V8M): Likewise.
(ARM_ARCH_V8A): Use ARM_EXT2_ATOMICS for features in second bitfield.
(ARM_ARCH_V8_1A): Likewise with ARM_AEXT2_V8_1A.
(ARM_ARCH_V8_2A): Likewise with ARM_AEXT2_V8_2A.
(ARM_ARCH_V8M_MAIN): New architecture feature bitfield.
(ARM_ARCH_V8A_FP): Use ARM_EXT2_ATOMICS for features in second bitfield
and reindent.
(ARM_ARCH_V8A_SIMD): Likewise.
(ARM_ARCH_V8A_CRYPTOV1): Likewise.
(ARM_ARCH_V8_1A_FP): Use ARM_AEXT2_V8_1A to set second bitfield of
feature bits.
(ARM_ARCH_V8_1A_SIMD): Likewise.
(ARM_ARCH_V8_1A_CRYPTOV1): Likewise.
opcodes/
* arm-dis.c (arm_opcodes): Guard lda, ldab, ldaex, ldaexb, ldaexh, stl,
stlb, stlh, stlex, stlexb and stlexh by ARM_EXT2_ATOMICS instead of
ARM_EXT_V8.
(thumb32_opcodes): Add entries for wide ARMv8-M instructions.
2015-12-24 10:16:19 +01:00
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
|
2015-03-24 07:08:08 +01:00
|
|
|
|
0x01e00e90, 0x0ff00ff0, "stlexh%c\t%12-15r, %0-3r, [%16-19R]"},
|
Add assembler support for ARMv8-M Mainline
2015-12-24 Thomas Preud'homme <thomas.preudhomme@arm.com>
bfd/
(tag_cpu_arch_combine): Adjust v4t_plus_v6_m and comb array to account
for new TAG_CPU_ARCH_V4T_PLUS_V6_M value. Deal with NULL values in
comb array.
binutils/
* readelf.c (arm_attr_tag_CPU_arch): Add ARMv8-M Mainline Tag_CPU_arch
value.
(arm_attr_tag_THUMB_ISA_use): Add ARMv8-M Mainline Tag_THUMB_ISA_use
value.
gas/
* config/tc-arm.c (arm_ext_m): Include ARMv8-M.
(arm_ext_v8m): New feature for ARMv8-M.
(arm_ext_atomics): New feature for ARMv8 atomics.
(do_tt): New encoding function for TT* instructions.
(insns): Add new entries for ARMv8-M specific instructions and
reorganize the ones shared by ARMv8-M Mainline and ARMv8-A.
(arm_archs): Define armv8-m.main architecture.
(cpu_arch_ver): Define ARM_ARCH_V8M_MAIN architecture version and
clarify the ordering rule.
(aeabi_set_public_attributes): Use TAG_CPU_ARCH_* macro to refer to
Tag_CPU_arch values for ARMv7e-M detection. Add logic to keep setting
Tag_CPU_arch to ARMv8-A for -march=all. Also set Tag_CPU_arch_profile
to 'A' if extension bit for atomic instructions is set, unless it is
ARMv8-M. Set Tag_THUMB_ISA_use to 3 for ARMv8-M. Set Tag_DIV_use to 0
for ARMv8-M Mainline.
gas/testsuite/
* gas/arm/archv8m.s: New file.
* gas/arm/archv8m-main.d: Likewise.
* gas/arm/attr-march-armv8m.main.d: Likewise.
* gas/arm/any-armv8m.s: Likewise.
* gas/arm/any-armv8m.d: Likewise.
include/elf/
* arm.h (TAG_CPU_ARCH_V8M_MAIN): Declare.
(MAX_TAG_CPU_ARCH): Define to TAG_CPU_ARCH_V8M_MAIN.
(TAG_CPU_ARCH_V4T_PLUS_V6_M): Define to unused value 15.
include/opcode/
* arm.h (ARM_EXT2_ATOMICS): New extension bit.
(ARM_EXT2_V8M): Likewise.
(ARM_EXT_V8): Adjust comment with regards to atomics and remove
mention of legacy use for that bit.
(ARM_AEXT2_V8_1A): New architecture extension bitfield.
(ARM_AEXT2_V8_2A): Likewise.
(ARM_AEXT_V8M_MAIN): Likewise.
(ARM_AEXT2_V8M): Likewise.
(ARM_ARCH_V8A): Use ARM_EXT2_ATOMICS for features in second bitfield.
(ARM_ARCH_V8_1A): Likewise with ARM_AEXT2_V8_1A.
(ARM_ARCH_V8_2A): Likewise with ARM_AEXT2_V8_2A.
(ARM_ARCH_V8M_MAIN): New architecture feature bitfield.
(ARM_ARCH_V8A_FP): Use ARM_EXT2_ATOMICS for features in second bitfield
and reindent.
(ARM_ARCH_V8A_SIMD): Likewise.
(ARM_ARCH_V8A_CRYPTOV1): Likewise.
(ARM_ARCH_V8_1A_FP): Use ARM_AEXT2_V8_1A to set second bitfield of
feature bits.
(ARM_ARCH_V8_1A_SIMD): Likewise.
(ARM_ARCH_V8_1A_CRYPTOV1): Likewise.
opcodes/
* arm-dis.c (arm_opcodes): Guard lda, ldab, ldaex, ldaexb, ldaexh, stl,
stlb, stlh, stlex, stlexb and stlexh by ARM_EXT2_ATOMICS instead of
ARM_EXT_V8.
(thumb32_opcodes): Add entries for wide ARMv8-M instructions.
2015-12-24 10:16:19 +01:00
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
|
2015-03-24 07:08:08 +01:00
|
|
|
|
0x01f00e9f, 0x0ff00fff, "ldaexh%c\t%12-15r, [%16-19R]"},
|
Add assembler support for ARMv8-M Mainline
2015-12-24 Thomas Preud'homme <thomas.preudhomme@arm.com>
bfd/
(tag_cpu_arch_combine): Adjust v4t_plus_v6_m and comb array to account
for new TAG_CPU_ARCH_V4T_PLUS_V6_M value. Deal with NULL values in
comb array.
binutils/
* readelf.c (arm_attr_tag_CPU_arch): Add ARMv8-M Mainline Tag_CPU_arch
value.
(arm_attr_tag_THUMB_ISA_use): Add ARMv8-M Mainline Tag_THUMB_ISA_use
value.
gas/
* config/tc-arm.c (arm_ext_m): Include ARMv8-M.
(arm_ext_v8m): New feature for ARMv8-M.
(arm_ext_atomics): New feature for ARMv8 atomics.
(do_tt): New encoding function for TT* instructions.
(insns): Add new entries for ARMv8-M specific instructions and
reorganize the ones shared by ARMv8-M Mainline and ARMv8-A.
(arm_archs): Define armv8-m.main architecture.
(cpu_arch_ver): Define ARM_ARCH_V8M_MAIN architecture version and
clarify the ordering rule.
(aeabi_set_public_attributes): Use TAG_CPU_ARCH_* macro to refer to
Tag_CPU_arch values for ARMv7e-M detection. Add logic to keep setting
Tag_CPU_arch to ARMv8-A for -march=all. Also set Tag_CPU_arch_profile
to 'A' if extension bit for atomic instructions is set, unless it is
ARMv8-M. Set Tag_THUMB_ISA_use to 3 for ARMv8-M. Set Tag_DIV_use to 0
for ARMv8-M Mainline.
gas/testsuite/
* gas/arm/archv8m.s: New file.
* gas/arm/archv8m-main.d: Likewise.
* gas/arm/attr-march-armv8m.main.d: Likewise.
* gas/arm/any-armv8m.s: Likewise.
* gas/arm/any-armv8m.d: Likewise.
include/elf/
* arm.h (TAG_CPU_ARCH_V8M_MAIN): Declare.
(MAX_TAG_CPU_ARCH): Define to TAG_CPU_ARCH_V8M_MAIN.
(TAG_CPU_ARCH_V4T_PLUS_V6_M): Define to unused value 15.
include/opcode/
* arm.h (ARM_EXT2_ATOMICS): New extension bit.
(ARM_EXT2_V8M): Likewise.
(ARM_EXT_V8): Adjust comment with regards to atomics and remove
mention of legacy use for that bit.
(ARM_AEXT2_V8_1A): New architecture extension bitfield.
(ARM_AEXT2_V8_2A): Likewise.
(ARM_AEXT_V8M_MAIN): Likewise.
(ARM_AEXT2_V8M): Likewise.
(ARM_ARCH_V8A): Use ARM_EXT2_ATOMICS for features in second bitfield.
(ARM_ARCH_V8_1A): Likewise with ARM_AEXT2_V8_1A.
(ARM_ARCH_V8_2A): Likewise with ARM_AEXT2_V8_2A.
(ARM_ARCH_V8M_MAIN): New architecture feature bitfield.
(ARM_ARCH_V8A_FP): Use ARM_EXT2_ATOMICS for features in second bitfield
and reindent.
(ARM_ARCH_V8A_SIMD): Likewise.
(ARM_ARCH_V8A_CRYPTOV1): Likewise.
(ARM_ARCH_V8_1A_FP): Use ARM_AEXT2_V8_1A to set second bitfield of
feature bits.
(ARM_ARCH_V8_1A_SIMD): Likewise.
(ARM_ARCH_V8_1A_CRYPTOV1): Likewise.
opcodes/
* arm-dis.c (arm_opcodes): Guard lda, ldab, ldaex, ldaexb, ldaexh, stl,
stlb, stlh, stlex, stlexb and stlexh by ARM_EXT2_ATOMICS instead of
ARM_EXT_V8.
(thumb32_opcodes): Add entries for wide ARMv8-M instructions.
2015-12-24 10:16:19 +01:00
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
|
2015-03-24 07:08:08 +01:00
|
|
|
|
0x0180fc90, 0x0ff0fff0, "stl%c\t%0-3r, [%16-19R]"},
|
Add assembler support for ARMv8-M Mainline
2015-12-24 Thomas Preud'homme <thomas.preudhomme@arm.com>
bfd/
(tag_cpu_arch_combine): Adjust v4t_plus_v6_m and comb array to account
for new TAG_CPU_ARCH_V4T_PLUS_V6_M value. Deal with NULL values in
comb array.
binutils/
* readelf.c (arm_attr_tag_CPU_arch): Add ARMv8-M Mainline Tag_CPU_arch
value.
(arm_attr_tag_THUMB_ISA_use): Add ARMv8-M Mainline Tag_THUMB_ISA_use
value.
gas/
* config/tc-arm.c (arm_ext_m): Include ARMv8-M.
(arm_ext_v8m): New feature for ARMv8-M.
(arm_ext_atomics): New feature for ARMv8 atomics.
(do_tt): New encoding function for TT* instructions.
(insns): Add new entries for ARMv8-M specific instructions and
reorganize the ones shared by ARMv8-M Mainline and ARMv8-A.
(arm_archs): Define armv8-m.main architecture.
(cpu_arch_ver): Define ARM_ARCH_V8M_MAIN architecture version and
clarify the ordering rule.
(aeabi_set_public_attributes): Use TAG_CPU_ARCH_* macro to refer to
Tag_CPU_arch values for ARMv7e-M detection. Add logic to keep setting
Tag_CPU_arch to ARMv8-A for -march=all. Also set Tag_CPU_arch_profile
to 'A' if extension bit for atomic instructions is set, unless it is
ARMv8-M. Set Tag_THUMB_ISA_use to 3 for ARMv8-M. Set Tag_DIV_use to 0
for ARMv8-M Mainline.
gas/testsuite/
* gas/arm/archv8m.s: New file.
* gas/arm/archv8m-main.d: Likewise.
* gas/arm/attr-march-armv8m.main.d: Likewise.
* gas/arm/any-armv8m.s: Likewise.
* gas/arm/any-armv8m.d: Likewise.
include/elf/
* arm.h (TAG_CPU_ARCH_V8M_MAIN): Declare.
(MAX_TAG_CPU_ARCH): Define to TAG_CPU_ARCH_V8M_MAIN.
(TAG_CPU_ARCH_V4T_PLUS_V6_M): Define to unused value 15.
include/opcode/
* arm.h (ARM_EXT2_ATOMICS): New extension bit.
(ARM_EXT2_V8M): Likewise.
(ARM_EXT_V8): Adjust comment with regards to atomics and remove
mention of legacy use for that bit.
(ARM_AEXT2_V8_1A): New architecture extension bitfield.
(ARM_AEXT2_V8_2A): Likewise.
(ARM_AEXT_V8M_MAIN): Likewise.
(ARM_AEXT2_V8M): Likewise.
(ARM_ARCH_V8A): Use ARM_EXT2_ATOMICS for features in second bitfield.
(ARM_ARCH_V8_1A): Likewise with ARM_AEXT2_V8_1A.
(ARM_ARCH_V8_2A): Likewise with ARM_AEXT2_V8_2A.
(ARM_ARCH_V8M_MAIN): New architecture feature bitfield.
(ARM_ARCH_V8A_FP): Use ARM_EXT2_ATOMICS for features in second bitfield
and reindent.
(ARM_ARCH_V8A_SIMD): Likewise.
(ARM_ARCH_V8A_CRYPTOV1): Likewise.
(ARM_ARCH_V8_1A_FP): Use ARM_AEXT2_V8_1A to set second bitfield of
feature bits.
(ARM_ARCH_V8_1A_SIMD): Likewise.
(ARM_ARCH_V8_1A_CRYPTOV1): Likewise.
opcodes/
* arm-dis.c (arm_opcodes): Guard lda, ldab, ldaex, ldaexb, ldaexh, stl,
stlb, stlh, stlex, stlexb and stlexh by ARM_EXT2_ATOMICS instead of
ARM_EXT_V8.
(thumb32_opcodes): Add entries for wide ARMv8-M instructions.
2015-12-24 10:16:19 +01:00
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
|
2015-03-24 07:08:08 +01:00
|
|
|
|
0x01900c9f, 0x0ff00fff, "lda%c\t%12-15r, [%16-19R]"},
|
Add assembler support for ARMv8-M Mainline
2015-12-24 Thomas Preud'homme <thomas.preudhomme@arm.com>
bfd/
(tag_cpu_arch_combine): Adjust v4t_plus_v6_m and comb array to account
for new TAG_CPU_ARCH_V4T_PLUS_V6_M value. Deal with NULL values in
comb array.
binutils/
* readelf.c (arm_attr_tag_CPU_arch): Add ARMv8-M Mainline Tag_CPU_arch
value.
(arm_attr_tag_THUMB_ISA_use): Add ARMv8-M Mainline Tag_THUMB_ISA_use
value.
gas/
* config/tc-arm.c (arm_ext_m): Include ARMv8-M.
(arm_ext_v8m): New feature for ARMv8-M.
(arm_ext_atomics): New feature for ARMv8 atomics.
(do_tt): New encoding function for TT* instructions.
(insns): Add new entries for ARMv8-M specific instructions and
reorganize the ones shared by ARMv8-M Mainline and ARMv8-A.
(arm_archs): Define armv8-m.main architecture.
(cpu_arch_ver): Define ARM_ARCH_V8M_MAIN architecture version and
clarify the ordering rule.
(aeabi_set_public_attributes): Use TAG_CPU_ARCH_* macro to refer to
Tag_CPU_arch values for ARMv7e-M detection. Add logic to keep setting
Tag_CPU_arch to ARMv8-A for -march=all. Also set Tag_CPU_arch_profile
to 'A' if extension bit for atomic instructions is set, unless it is
ARMv8-M. Set Tag_THUMB_ISA_use to 3 for ARMv8-M. Set Tag_DIV_use to 0
for ARMv8-M Mainline.
gas/testsuite/
* gas/arm/archv8m.s: New file.
* gas/arm/archv8m-main.d: Likewise.
* gas/arm/attr-march-armv8m.main.d: Likewise.
* gas/arm/any-armv8m.s: Likewise.
* gas/arm/any-armv8m.d: Likewise.
include/elf/
* arm.h (TAG_CPU_ARCH_V8M_MAIN): Declare.
(MAX_TAG_CPU_ARCH): Define to TAG_CPU_ARCH_V8M_MAIN.
(TAG_CPU_ARCH_V4T_PLUS_V6_M): Define to unused value 15.
include/opcode/
* arm.h (ARM_EXT2_ATOMICS): New extension bit.
(ARM_EXT2_V8M): Likewise.
(ARM_EXT_V8): Adjust comment with regards to atomics and remove
mention of legacy use for that bit.
(ARM_AEXT2_V8_1A): New architecture extension bitfield.
(ARM_AEXT2_V8_2A): Likewise.
(ARM_AEXT_V8M_MAIN): Likewise.
(ARM_AEXT2_V8M): Likewise.
(ARM_ARCH_V8A): Use ARM_EXT2_ATOMICS for features in second bitfield.
(ARM_ARCH_V8_1A): Likewise with ARM_AEXT2_V8_1A.
(ARM_ARCH_V8_2A): Likewise with ARM_AEXT2_V8_2A.
(ARM_ARCH_V8M_MAIN): New architecture feature bitfield.
(ARM_ARCH_V8A_FP): Use ARM_EXT2_ATOMICS for features in second bitfield
and reindent.
(ARM_ARCH_V8A_SIMD): Likewise.
(ARM_ARCH_V8A_CRYPTOV1): Likewise.
(ARM_ARCH_V8_1A_FP): Use ARM_AEXT2_V8_1A to set second bitfield of
feature bits.
(ARM_ARCH_V8_1A_SIMD): Likewise.
(ARM_ARCH_V8_1A_CRYPTOV1): Likewise.
opcodes/
* arm-dis.c (arm_opcodes): Guard lda, ldab, ldaex, ldaexb, ldaexh, stl,
stlb, stlh, stlex, stlexb and stlexh by ARM_EXT2_ATOMICS instead of
ARM_EXT_V8.
(thumb32_opcodes): Add entries for wide ARMv8-M instructions.
2015-12-24 10:16:19 +01:00
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
|
2015-03-24 07:08:08 +01:00
|
|
|
|
0x01c0fc90, 0x0ff0fff0, "stlb%c\t%0-3r, [%16-19R]"},
|
Add assembler support for ARMv8-M Mainline
2015-12-24 Thomas Preud'homme <thomas.preudhomme@arm.com>
bfd/
(tag_cpu_arch_combine): Adjust v4t_plus_v6_m and comb array to account
for new TAG_CPU_ARCH_V4T_PLUS_V6_M value. Deal with NULL values in
comb array.
binutils/
* readelf.c (arm_attr_tag_CPU_arch): Add ARMv8-M Mainline Tag_CPU_arch
value.
(arm_attr_tag_THUMB_ISA_use): Add ARMv8-M Mainline Tag_THUMB_ISA_use
value.
gas/
* config/tc-arm.c (arm_ext_m): Include ARMv8-M.
(arm_ext_v8m): New feature for ARMv8-M.
(arm_ext_atomics): New feature for ARMv8 atomics.
(do_tt): New encoding function for TT* instructions.
(insns): Add new entries for ARMv8-M specific instructions and
reorganize the ones shared by ARMv8-M Mainline and ARMv8-A.
(arm_archs): Define armv8-m.main architecture.
(cpu_arch_ver): Define ARM_ARCH_V8M_MAIN architecture version and
clarify the ordering rule.
(aeabi_set_public_attributes): Use TAG_CPU_ARCH_* macro to refer to
Tag_CPU_arch values for ARMv7e-M detection. Add logic to keep setting
Tag_CPU_arch to ARMv8-A for -march=all. Also set Tag_CPU_arch_profile
to 'A' if extension bit for atomic instructions is set, unless it is
ARMv8-M. Set Tag_THUMB_ISA_use to 3 for ARMv8-M. Set Tag_DIV_use to 0
for ARMv8-M Mainline.
gas/testsuite/
* gas/arm/archv8m.s: New file.
* gas/arm/archv8m-main.d: Likewise.
* gas/arm/attr-march-armv8m.main.d: Likewise.
* gas/arm/any-armv8m.s: Likewise.
* gas/arm/any-armv8m.d: Likewise.
include/elf/
* arm.h (TAG_CPU_ARCH_V8M_MAIN): Declare.
(MAX_TAG_CPU_ARCH): Define to TAG_CPU_ARCH_V8M_MAIN.
(TAG_CPU_ARCH_V4T_PLUS_V6_M): Define to unused value 15.
include/opcode/
* arm.h (ARM_EXT2_ATOMICS): New extension bit.
(ARM_EXT2_V8M): Likewise.
(ARM_EXT_V8): Adjust comment with regards to atomics and remove
mention of legacy use for that bit.
(ARM_AEXT2_V8_1A): New architecture extension bitfield.
(ARM_AEXT2_V8_2A): Likewise.
(ARM_AEXT_V8M_MAIN): Likewise.
(ARM_AEXT2_V8M): Likewise.
(ARM_ARCH_V8A): Use ARM_EXT2_ATOMICS for features in second bitfield.
(ARM_ARCH_V8_1A): Likewise with ARM_AEXT2_V8_1A.
(ARM_ARCH_V8_2A): Likewise with ARM_AEXT2_V8_2A.
(ARM_ARCH_V8M_MAIN): New architecture feature bitfield.
(ARM_ARCH_V8A_FP): Use ARM_EXT2_ATOMICS for features in second bitfield
and reindent.
(ARM_ARCH_V8A_SIMD): Likewise.
(ARM_ARCH_V8A_CRYPTOV1): Likewise.
(ARM_ARCH_V8_1A_FP): Use ARM_AEXT2_V8_1A to set second bitfield of
feature bits.
(ARM_ARCH_V8_1A_SIMD): Likewise.
(ARM_ARCH_V8_1A_CRYPTOV1): Likewise.
opcodes/
* arm-dis.c (arm_opcodes): Guard lda, ldab, ldaex, ldaexb, ldaexh, stl,
stlb, stlh, stlex, stlexb and stlexh by ARM_EXT2_ATOMICS instead of
ARM_EXT_V8.
(thumb32_opcodes): Add entries for wide ARMv8-M instructions.
2015-12-24 10:16:19 +01:00
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
|
2015-03-24 07:08:08 +01:00
|
|
|
|
0x01d00c9f, 0x0ff00fff, "ldab%c\t%12-15r, [%16-19R]"},
|
Add assembler support for ARMv8-M Mainline
2015-12-24 Thomas Preud'homme <thomas.preudhomme@arm.com>
bfd/
(tag_cpu_arch_combine): Adjust v4t_plus_v6_m and comb array to account
for new TAG_CPU_ARCH_V4T_PLUS_V6_M value. Deal with NULL values in
comb array.
binutils/
* readelf.c (arm_attr_tag_CPU_arch): Add ARMv8-M Mainline Tag_CPU_arch
value.
(arm_attr_tag_THUMB_ISA_use): Add ARMv8-M Mainline Tag_THUMB_ISA_use
value.
gas/
* config/tc-arm.c (arm_ext_m): Include ARMv8-M.
(arm_ext_v8m): New feature for ARMv8-M.
(arm_ext_atomics): New feature for ARMv8 atomics.
(do_tt): New encoding function for TT* instructions.
(insns): Add new entries for ARMv8-M specific instructions and
reorganize the ones shared by ARMv8-M Mainline and ARMv8-A.
(arm_archs): Define armv8-m.main architecture.
(cpu_arch_ver): Define ARM_ARCH_V8M_MAIN architecture version and
clarify the ordering rule.
(aeabi_set_public_attributes): Use TAG_CPU_ARCH_* macro to refer to
Tag_CPU_arch values for ARMv7e-M detection. Add logic to keep setting
Tag_CPU_arch to ARMv8-A for -march=all. Also set Tag_CPU_arch_profile
to 'A' if extension bit for atomic instructions is set, unless it is
ARMv8-M. Set Tag_THUMB_ISA_use to 3 for ARMv8-M. Set Tag_DIV_use to 0
for ARMv8-M Mainline.
gas/testsuite/
* gas/arm/archv8m.s: New file.
* gas/arm/archv8m-main.d: Likewise.
* gas/arm/attr-march-armv8m.main.d: Likewise.
* gas/arm/any-armv8m.s: Likewise.
* gas/arm/any-armv8m.d: Likewise.
include/elf/
* arm.h (TAG_CPU_ARCH_V8M_MAIN): Declare.
(MAX_TAG_CPU_ARCH): Define to TAG_CPU_ARCH_V8M_MAIN.
(TAG_CPU_ARCH_V4T_PLUS_V6_M): Define to unused value 15.
include/opcode/
* arm.h (ARM_EXT2_ATOMICS): New extension bit.
(ARM_EXT2_V8M): Likewise.
(ARM_EXT_V8): Adjust comment with regards to atomics and remove
mention of legacy use for that bit.
(ARM_AEXT2_V8_1A): New architecture extension bitfield.
(ARM_AEXT2_V8_2A): Likewise.
(ARM_AEXT_V8M_MAIN): Likewise.
(ARM_AEXT2_V8M): Likewise.
(ARM_ARCH_V8A): Use ARM_EXT2_ATOMICS for features in second bitfield.
(ARM_ARCH_V8_1A): Likewise with ARM_AEXT2_V8_1A.
(ARM_ARCH_V8_2A): Likewise with ARM_AEXT2_V8_2A.
(ARM_ARCH_V8M_MAIN): New architecture feature bitfield.
(ARM_ARCH_V8A_FP): Use ARM_EXT2_ATOMICS for features in second bitfield
and reindent.
(ARM_ARCH_V8A_SIMD): Likewise.
(ARM_ARCH_V8A_CRYPTOV1): Likewise.
(ARM_ARCH_V8_1A_FP): Use ARM_AEXT2_V8_1A to set second bitfield of
feature bits.
(ARM_ARCH_V8_1A_SIMD): Likewise.
(ARM_ARCH_V8_1A_CRYPTOV1): Likewise.
opcodes/
* arm-dis.c (arm_opcodes): Guard lda, ldab, ldaex, ldaexb, ldaexh, stl,
stlb, stlh, stlex, stlexb and stlexh by ARM_EXT2_ATOMICS instead of
ARM_EXT_V8.
(thumb32_opcodes): Add entries for wide ARMv8-M instructions.
2015-12-24 10:16:19 +01:00
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
|
2015-03-24 07:08:08 +01:00
|
|
|
|
0x01e0fc90, 0x0ff0fff0, "stlh%c\t%0-3r, [%16-19R]"},
|
Add assembler support for ARMv8-M Mainline
2015-12-24 Thomas Preud'homme <thomas.preudhomme@arm.com>
bfd/
(tag_cpu_arch_combine): Adjust v4t_plus_v6_m and comb array to account
for new TAG_CPU_ARCH_V4T_PLUS_V6_M value. Deal with NULL values in
comb array.
binutils/
* readelf.c (arm_attr_tag_CPU_arch): Add ARMv8-M Mainline Tag_CPU_arch
value.
(arm_attr_tag_THUMB_ISA_use): Add ARMv8-M Mainline Tag_THUMB_ISA_use
value.
gas/
* config/tc-arm.c (arm_ext_m): Include ARMv8-M.
(arm_ext_v8m): New feature for ARMv8-M.
(arm_ext_atomics): New feature for ARMv8 atomics.
(do_tt): New encoding function for TT* instructions.
(insns): Add new entries for ARMv8-M specific instructions and
reorganize the ones shared by ARMv8-M Mainline and ARMv8-A.
(arm_archs): Define armv8-m.main architecture.
(cpu_arch_ver): Define ARM_ARCH_V8M_MAIN architecture version and
clarify the ordering rule.
(aeabi_set_public_attributes): Use TAG_CPU_ARCH_* macro to refer to
Tag_CPU_arch values for ARMv7e-M detection. Add logic to keep setting
Tag_CPU_arch to ARMv8-A for -march=all. Also set Tag_CPU_arch_profile
to 'A' if extension bit for atomic instructions is set, unless it is
ARMv8-M. Set Tag_THUMB_ISA_use to 3 for ARMv8-M. Set Tag_DIV_use to 0
for ARMv8-M Mainline.
gas/testsuite/
* gas/arm/archv8m.s: New file.
* gas/arm/archv8m-main.d: Likewise.
* gas/arm/attr-march-armv8m.main.d: Likewise.
* gas/arm/any-armv8m.s: Likewise.
* gas/arm/any-armv8m.d: Likewise.
include/elf/
* arm.h (TAG_CPU_ARCH_V8M_MAIN): Declare.
(MAX_TAG_CPU_ARCH): Define to TAG_CPU_ARCH_V8M_MAIN.
(TAG_CPU_ARCH_V4T_PLUS_V6_M): Define to unused value 15.
include/opcode/
* arm.h (ARM_EXT2_ATOMICS): New extension bit.
(ARM_EXT2_V8M): Likewise.
(ARM_EXT_V8): Adjust comment with regards to atomics and remove
mention of legacy use for that bit.
(ARM_AEXT2_V8_1A): New architecture extension bitfield.
(ARM_AEXT2_V8_2A): Likewise.
(ARM_AEXT_V8M_MAIN): Likewise.
(ARM_AEXT2_V8M): Likewise.
(ARM_ARCH_V8A): Use ARM_EXT2_ATOMICS for features in second bitfield.
(ARM_ARCH_V8_1A): Likewise with ARM_AEXT2_V8_1A.
(ARM_ARCH_V8_2A): Likewise with ARM_AEXT2_V8_2A.
(ARM_ARCH_V8M_MAIN): New architecture feature bitfield.
(ARM_ARCH_V8A_FP): Use ARM_EXT2_ATOMICS for features in second bitfield
and reindent.
(ARM_ARCH_V8A_SIMD): Likewise.
(ARM_ARCH_V8A_CRYPTOV1): Likewise.
(ARM_ARCH_V8_1A_FP): Use ARM_AEXT2_V8_1A to set second bitfield of
feature bits.
(ARM_ARCH_V8_1A_SIMD): Likewise.
(ARM_ARCH_V8_1A_CRYPTOV1): Likewise.
opcodes/
* arm-dis.c (arm_opcodes): Guard lda, ldab, ldaex, ldaexb, ldaexh, stl,
stlb, stlh, stlex, stlexb and stlexh by ARM_EXT2_ATOMICS instead of
ARM_EXT_V8.
(thumb32_opcodes): Add entries for wide ARMv8-M instructions.
2015-12-24 10:16:19 +01:00
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
|
2015-11-25 14:56:55 +01:00
|
|
|
|
0x01f00c9f, 0x0ff00fff, "ldah%c\t%12-15r, [%16-19R]"},
|
2013-03-11 12:09:33 +01:00
|
|
|
|
/* CRC32 instructions. */
|
2015-03-24 07:08:08 +01:00
|
|
|
|
{ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
|
|
|
|
|
|
0xe1000040, 0xfff00ff0, "crc32b\t%12-15R, %16-19R, %0-3R"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
|
|
|
|
|
|
0xe1200040, 0xfff00ff0, "crc32h\t%12-15R, %16-19R, %0-3R"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
|
|
|
|
|
|
0xe1400040, 0xfff00ff0, "crc32w\t%12-15R, %16-19R, %0-3R"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
|
|
|
|
|
|
0xe1000240, 0xfff00ff0, "crc32cb\t%12-15R, %16-19R, %0-3R"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
|
|
|
|
|
|
0xe1200240, 0xfff00ff0, "crc32ch\t%12-15R, %16-19R, %0-3R"},
|
|
|
|
|
|
{ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
|
|
|
|
|
|
0xe1400240, 0xfff00ff0, "crc32cw\t%12-15R, %16-19R, %0-3R"},
|
2012-08-24 10:01:18 +02:00
|
|
|
|
|
2015-06-02 13:30:38 +02:00
|
|
|
|
/* Privileged Access Never extension instructions. */
|
|
|
|
|
|
{ARM_FEATURE_CORE_HIGH (ARM_EXT2_PAN),
|
|
|
|
|
|
0xf1100000, 0xfffffdff, "setpan\t#%9-9d"},
|
|
|
|
|
|
|
2010-09-23 17:52:19 +02:00
|
|
|
|
/* Virtualization Extension instructions. */
|
2015-03-24 07:08:08 +01:00
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT), 0x0160006e, 0x0fffffff, "eret%c"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT), 0x01400070, 0x0ff000f0, "hvc%c\t%e"},
|
2010-09-23 17:52:19 +02:00
|
|
|
|
|
2010-09-23 17:37:45 +02:00
|
|
|
|
/* Integer Divide Extension instructions. */
|
2015-03-24 07:08:08 +01:00
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV),
|
|
|
|
|
|
0x0710f010, 0x0ff0f0f0, "sdiv%c\t%16-19r, %0-3r, %8-11r"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV),
|
|
|
|
|
|
0x0730f010, 0x0ff0f0f0, "udiv%c\t%16-19r, %0-3r, %8-11r"},
|
2010-09-23 17:37:45 +02:00
|
|
|
|
|
2010-09-23 17:18:19 +02:00
|
|
|
|
/* MP Extension instructions. */
|
2015-03-24 07:08:08 +01:00
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_MP), 0xf410f000, 0xfc70f000, "pldw\t%a"},
|
2010-09-23 17:18:19 +02:00
|
|
|
|
|
2018-07-11 19:05:34 +02:00
|
|
|
|
/* Speculation Barriers. */
|
|
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V3), 0xe320f014, 0xffffffff, "csdb"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V3), 0xf57ff040, 0xffffffff, "ssbb"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V3), 0xf57ff044, 0xffffffff, "pssbb"},
|
|
|
|
|
|
|
2006-02-24 Paul Brook <paul@codesourcery.com>
gas/
* config/arm/tc-arm.c (arm_ext_v6_notm, arm_ext_div, arm_ext_v7,
arm_ext_v7a, arm_ext_v7r, arm_ext_v7m): New variables.
(struct asm_barrier_opt): Define.
(arm_v7m_psr_hsh, arm_barrier_opt_hsh): New variables.
(parse_psr): Accept V7M psr names.
(parse_barrier): New function.
(enum operand_parse_code): Add OP_oBARRIER.
(parse_operands): Implement OP_oBARRIER.
(do_barrier): New function.
(do_dbg, do_pli, do_t_barrier, do_t_dbg, do_t_div): New functions.
(do_t_cpsi): Add V7M restrictions.
(do_t_mrs, do_t_msr): Validate V7M variants.
(md_assemble): Check for NULL variants.
(v7m_psrs, barrier_opt_names): New tables.
(insns): Add V7 instructions. Mark V6 instructions absent from V7M.
(md_begin): Initialize arm_v7m_psr_hsh and arm_barrier_opt_hsh.
(arm_cpu_option_table): Add Cortex-M3, R4 and A8.
(arm_arch_option_table): Add armv7, armv7a, armv7r and armv7m.
(struct cpu_arch_ver_table): Define.
(cpu_arch_ver): New.
(aeabi_set_public_attributes): Use cpu_arch_ver. Set
Tag_CPU_arch_profile.
* doc/c-arm.texi: Document new cpu and arch options.
gas/testsuite/
* gas/arm/thumb32.d: Fix expected msr and mrs output.
* gas/arm/arch7.d: New test.
* gas/arm/arch7.s: New test.
* gas/arm/arch7m-bad.l: New test.
* gas/arm/arch7m-bad.d: New test.
* gas/arm/arch7m-bad.s: New test.
include/opcode/
* arm.h: Add V7 feature bits.
opcodes/
* arm-dis.c (arm_opcodes): Add V7 instructions.
(thumb32_opcodes): Ditto. Handle V7M MSR/MRS variants.
(print_arm_address): New function.
(print_insn_arm): Use it. Add 'P' and 'U' cases.
(psr_name): New function.
(print_insn_thumb32): Add 'U', 'C' and 'D' cases.
2006-02-24 16:36:36 +01:00
|
|
|
|
/* V7 instructions. */
|
2015-03-24 07:08:08 +01:00
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf450f000, 0xfd70f000, "pli\t%P"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0x0320f0f0, 0x0ffffff0, "dbg%c\t#%0-3d"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xf57ff051, 0xfffffff3, "dmb\t%U"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xf57ff041, 0xfffffff3, "dsb\t%U"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf57ff050, 0xfffffff0, "dmb\t%U"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf57ff040, 0xfffffff0, "dsb\t%U"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf57ff060, 0xfffffff0, "isb\t%U"},
|
2015-08-13 12:39:08 +02:00
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V7),
|
|
|
|
|
|
0x0320f000, 0x0fffffff, "nop%c\t{%0-7d}"},
|
2006-02-24 Paul Brook <paul@codesourcery.com>
gas/
* config/arm/tc-arm.c (arm_ext_v6_notm, arm_ext_div, arm_ext_v7,
arm_ext_v7a, arm_ext_v7r, arm_ext_v7m): New variables.
(struct asm_barrier_opt): Define.
(arm_v7m_psr_hsh, arm_barrier_opt_hsh): New variables.
(parse_psr): Accept V7M psr names.
(parse_barrier): New function.
(enum operand_parse_code): Add OP_oBARRIER.
(parse_operands): Implement OP_oBARRIER.
(do_barrier): New function.
(do_dbg, do_pli, do_t_barrier, do_t_dbg, do_t_div): New functions.
(do_t_cpsi): Add V7M restrictions.
(do_t_mrs, do_t_msr): Validate V7M variants.
(md_assemble): Check for NULL variants.
(v7m_psrs, barrier_opt_names): New tables.
(insns): Add V7 instructions. Mark V6 instructions absent from V7M.
(md_begin): Initialize arm_v7m_psr_hsh and arm_barrier_opt_hsh.
(arm_cpu_option_table): Add Cortex-M3, R4 and A8.
(arm_arch_option_table): Add armv7, armv7a, armv7r and armv7m.
(struct cpu_arch_ver_table): Define.
(cpu_arch_ver): New.
(aeabi_set_public_attributes): Use cpu_arch_ver. Set
Tag_CPU_arch_profile.
* doc/c-arm.texi: Document new cpu and arch options.
gas/testsuite/
* gas/arm/thumb32.d: Fix expected msr and mrs output.
* gas/arm/arch7.d: New test.
* gas/arm/arch7.s: New test.
* gas/arm/arch7m-bad.l: New test.
* gas/arm/arch7m-bad.d: New test.
* gas/arm/arch7m-bad.s: New test.
include/opcode/
* arm.h: Add V7 feature bits.
opcodes/
* arm-dis.c (arm_opcodes): Add V7 instructions.
(thumb32_opcodes): Ditto. Handle V7M MSR/MRS variants.
(print_arm_address): New function.
(print_insn_arm): Use it. Add 'P' and 'U' cases.
(psr_name): New function.
(print_insn_thumb32): Add 'U', 'C' and 'D' cases.
2006-02-24 16:36:36 +01:00
|
|
|
|
|
include/elf:
* arm.h: Import complete list of official relocation names
and numbers from AAELF. Define FAKE_RELOCs for old names.
Remove a few old names no longer used anywhere.
bfd:
* elf32-arm.c: Wherever possible, use official reloc names
from AAELF.
(elf32_arm_howto_table, elf32_arm_tls_gd32_howto)
(elf32_arm_tls_ldo32_howto, elf32_arm_tls_ldm32_howto)
(elf32_arm_tls_le32_howto, elf32_arm_tls_ie32_howto)
(elf32_arm_vtinherit_howto, elf32_arm_vtentry_howto)
(elf32_arm_pc11_howto, elf32_arm_thm_pc9_howto, elf32_arm_got_prel)
(elf32_arm_r_howto): Replace with elf32_arm_howto_table_1,
elf32_arm_howto_table_2, and elf32_arm_howto_table_3.
Add many new relocations from AAELF.
(elf32_arm_howto_from_type): Update to match.
(elf32_arm_reloc_map): Add entries for R_ARM_THM_JUMP24,
R_ARM_THM_JUMP11, R_ARM_THM_JUMP19, R_ARM_THM_JUMP8,
R_ARM_THM_JUMP6, R_ARM_GNU_VTINHERIT, and R_ARM_GNU_VTENTRY.
(elf32_arm_reloc_type_lookup): Use elf32_arm_howto_from_type.
(elf32_arm_final_link_relocate): Add support for
R_ARM_THM_JUMP24, R_ARM_THM_JUMP19, R_ARM_THM_JUMP6. Remove
case entries redundant with default.
* reloc.c: Reorganize ARM relocations. Add Thumb
assembler-internal relocations BFD_RELOC_ARM_T32_OFFSET_U8,
BFD_RELOC_ARM_T32_OFFSET_IMM, BFD_RELOC_ARM_T32_IMMEDIATE.
Add visible relocations BFD_RELOC_THUMB_PCREL_BRANCH7,
BFD_RELOC_THUMB_BRANCH20, BFD_RELOC_THUMB_BRANCH25.
Delete unused relocations BFD_RELOC_ARM_GOT12, BFD_RELOC_ARM_COPY.
* bfd-in2.h, libbfd.h: Regenerate.
opcodes:
* arm-dis.c (thumb_opcodes): Add disassembly for V6T2 16-bit
instructions. Adjust disassembly of some opcodes to match
unified syntax.
(thumb32_opcodes): New table.
(print_insn_thumb): Rename print_insn_thumb16; don't handle
two-halfword branches here.
(print_insn_thumb32): New function.
(print_insn): Choose among print_insn_arm, print_insn_thumb16,
and print_insn_thumb32. Be consistent about order of
halfwords when printing 32-bit instructions.
gas:
* hash.c (hash_lookup): Add len parameter. All callers changed.
(hash_find_n): New interface.
* hash.h: Prototype hash_find_n.
* sb.c: Include as.h.
(scrub_from_sb, sb_to_scrub, scrub_position): New statics.
(sb_scrub_and_add_sb): New interface.
* sb.h: Prototype sb_scrub_and_add_sb.
* input-scrub.c (input_scrub_include_sb): Use sb_scrub_and_add_sb.
* config/tc-arm.h (TC_FORCE_RELOCATION_LOCAL): Remove
reference to BFD_RELOC_ARM_GOT12 which is never generated.
* config/tc-arm.c: Rewrite, adding Thumb-2 support.
gas/testsuite:
* gas/arm/arm.exp: Convert all existing "gas_test" tests to
"run_dump_test" tests. Run more tests unconditionally. Run new tests.
* gas/arm/arch4t.s, gas/arm/arch6zk.s, gas/arm/arm3.s, gas/arm/arm6.s
* gas/arm/arm7dm.s, gas/arm/bignum1.s, gas/arm/float.s
* gas/arm/immed.s, gas/arm/iwmmxt.s, gas/arm/offset.s, gas/arm/thumb.s:
Adjust to work as a dump test.
* gas/arm/arch4t.d, gas/arm/arch6zk.d, gas/arm/arm3.d, gas/arm/arm6.d
* gas/arm/arm7dm.d, gas/arm/bignum1.d, gas/arm/float.d
* gas/arm/immed.d, gas/arm/iwmmxt.d, gas/arm/offset.d, gas/arm/thumb.d:
New files.
* gas/arm/armv1-bad.l, gas/arm/armv1-bad.s: Remove tests for
diagnostics that don't happen in the first pass anymore.
* gas/arm/iwmmxt-bad.l, gas/arm/r15-bad.l, gas/arm/req.l
* gas/arm/vfp-bad.l:
Update expected diagnostics.
* gas/arm/pic.d: Update expected reloc name.
* gas/arm/thumbv6.d: CPY no longer appears in disassembly.
* gas/arm/r15-bad.s: Avoid two-argument mul.
* gas/arm/req.s: Adjust comments.
* gas/arm/maverick.d, gas/arm/maverick.s: Avoid inappropriate
use of PC.
* gas/arm/macro-1.d, gas/arm/macro1.s
* gas/arm/t16-bad.l, gas/arm/t16-bad.s
* gas/arm/tcompat.d, gas/arm/tcompat.s
* gas/arm/tcompat2.d, gas/arm/tcompat2.s
* gas/arm/thumb32.d, gas/arm/thumb32.s
New test pair.
ld/testsuite:
* ld-arm/mixed-app.d: Adjust expected disassembly a little.
2005-05-18 07:40:12 +02:00
|
|
|
|
/* ARM V6T2 instructions. */
|
2015-03-24 07:08:08 +01:00
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
|
|
|
|
|
|
0x07c0001f, 0x0fe0007f, "bfc%c\t%12-15R, %E"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
|
|
|
|
|
|
0x07c00010, 0x0fe00070, "bfi%c\t%12-15R, %0-3r, %E"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
|
|
|
|
|
|
0x00600090, 0x0ff000f0, "mls%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
|
|
|
|
|
|
0x002000b0, 0x0f3000f0, "strht%c\t%12-15R, %S"},
|
|
|
|
|
|
|
|
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
|
|
|
|
|
|
0x00300090, 0x0f3000f0, UNDEFINED_INSTRUCTION },
|
|
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
|
|
|
|
|
|
0x00300090, 0x0f300090, "ldr%6's%5?hbt%c\t%12-15R, %S"},
|
|
|
|
|
|
|
2015-12-24 10:26:08 +01:00
|
|
|
|
{ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
|
2015-03-24 07:08:08 +01:00
|
|
|
|
0x03000000, 0x0ff00000, "movw%c\t%12-15R, %V"},
|
2015-12-24 10:26:08 +01:00
|
|
|
|
{ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
|
2015-03-24 07:08:08 +01:00
|
|
|
|
0x03400000, 0x0ff00000, "movt%c\t%12-15R, %V"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
|
|
|
|
|
|
0x06ff0f30, 0x0fff0ff0, "rbit%c\t%12-15R, %0-3R"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
|
|
|
|
|
|
0x07a00050, 0x0fa00070, "%22?usbfx%c\t%12-15r, %0-3r, #%7-11d, #%16-20W"},
|
2005-03-12 19:25:47 +01:00
|
|
|
|
|
2010-09-23 17:26:24 +02:00
|
|
|
|
/* ARM Security extension instructions. */
|
2015-03-24 07:08:08 +01:00
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_SEC),
|
|
|
|
|
|
0x01600070, 0x0ff000f0, "smc%c\t%e"},
|
2004-11-27 12:09:21 +01:00
|
|
|
|
|
2005-09-02 Paul Brook <paul@codesourcery.com>
bfd/
* libbdf.h: Regenerate.
* bfd-in2.h: Regenerate.
* reloc.c: Add BFD_RELOC_ARM_T32_CP_OFF_IMM and
BFD_RELOC_ARM_T32_CP_OFF_IMM_S2.
gas/
* config/tc-arm.c (encode_arm_cp_address): Use
BFD_RELOC_ARM_T32_CP_OFF_IMM in thumb mode.
(do_iwmmxt_wldstbh): Use BFD_RELOC_ARM_T32_CP_OFF_IMM_S2 in thumb
mode.
(md_assemble): Only allow coprocessor instructions when Thumb-2 is
available.
(cCE, cC3): Define.
(insns): Use them for coprocessor instructions.
(md_pcrel_from_section): Handle BFD_RELOC_ARM_T32_CP_OFF_IMM.
(get_thumb32_insn): New function.
(put_thumb32_insn): New function.
(md_apply_fix): Handle BFD_RELOC_ARM_T32_CP_OFF_IMM and
BFD_RELOC_ARM_T32_CP_OFF_IMM_S2.
gas/testsuite/
* gas/arm/vfp-bad_t2.d, gas/arm/vfp-bad_t2.l, arm/vfp-bad_t2.s,
gas/arm/vfp1_t2.d, gas/arm/vfp1_t2.s, gas/arm/vfp1xD_t2.d,
gas/arm/vfp1xD_t2.s, gas/arm/vfp2_t2.d, gas/arm/vfp2_t2.s): New files.
opcodes/
* arm-dis.c (coprocessor_opcodes): New.
(arm_opcodes, thumb32_opcodes): Remove coprocessor insns.
(print_insn_coprocessor): New function.
(print_insn_arm): Use print_insn_coprocessor. Remove coprocessor
format characters.
(print_insn_thumb32): Use print_insn_coprocessor.
2005-09-02 15:12:45 +02:00
|
|
|
|
/* ARM V6K instructions. */
|
2015-03-24 07:08:08 +01:00
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
|
|
|
|
|
|
0xf57ff01f, 0xffffffff, "clrex"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
|
|
|
|
|
|
0x01d00f9f, 0x0ff00fff, "ldrexb%c\t%12-15R, [%16-19R]"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
|
|
|
|
|
|
0x01b00f9f, 0x0ff00fff, "ldrexd%c\t%12-15r, [%16-19R]"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
|
|
|
|
|
|
0x01f00f9f, 0x0ff00fff, "ldrexh%c\t%12-15R, [%16-19R]"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
|
|
|
|
|
|
0x01c00f90, 0x0ff00ff0, "strexb%c\t%12-15R, %0-3R, [%16-19R]"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
|
|
|
|
|
|
0x01a00f90, 0x0ff00ff0, "strexd%c\t%12-15R, %0-3r, [%16-19R]"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
|
|
|
|
|
|
0x01e00f90, 0x0ff00ff0, "strexh%c\t%12-15R, %0-3R, [%16-19R]"},
|
include/elf:
* arm.h: Import complete list of official relocation names
and numbers from AAELF. Define FAKE_RELOCs for old names.
Remove a few old names no longer used anywhere.
bfd:
* elf32-arm.c: Wherever possible, use official reloc names
from AAELF.
(elf32_arm_howto_table, elf32_arm_tls_gd32_howto)
(elf32_arm_tls_ldo32_howto, elf32_arm_tls_ldm32_howto)
(elf32_arm_tls_le32_howto, elf32_arm_tls_ie32_howto)
(elf32_arm_vtinherit_howto, elf32_arm_vtentry_howto)
(elf32_arm_pc11_howto, elf32_arm_thm_pc9_howto, elf32_arm_got_prel)
(elf32_arm_r_howto): Replace with elf32_arm_howto_table_1,
elf32_arm_howto_table_2, and elf32_arm_howto_table_3.
Add many new relocations from AAELF.
(elf32_arm_howto_from_type): Update to match.
(elf32_arm_reloc_map): Add entries for R_ARM_THM_JUMP24,
R_ARM_THM_JUMP11, R_ARM_THM_JUMP19, R_ARM_THM_JUMP8,
R_ARM_THM_JUMP6, R_ARM_GNU_VTINHERIT, and R_ARM_GNU_VTENTRY.
(elf32_arm_reloc_type_lookup): Use elf32_arm_howto_from_type.
(elf32_arm_final_link_relocate): Add support for
R_ARM_THM_JUMP24, R_ARM_THM_JUMP19, R_ARM_THM_JUMP6. Remove
case entries redundant with default.
* reloc.c: Reorganize ARM relocations. Add Thumb
assembler-internal relocations BFD_RELOC_ARM_T32_OFFSET_U8,
BFD_RELOC_ARM_T32_OFFSET_IMM, BFD_RELOC_ARM_T32_IMMEDIATE.
Add visible relocations BFD_RELOC_THUMB_PCREL_BRANCH7,
BFD_RELOC_THUMB_BRANCH20, BFD_RELOC_THUMB_BRANCH25.
Delete unused relocations BFD_RELOC_ARM_GOT12, BFD_RELOC_ARM_COPY.
* bfd-in2.h, libbfd.h: Regenerate.
opcodes:
* arm-dis.c (thumb_opcodes): Add disassembly for V6T2 16-bit
instructions. Adjust disassembly of some opcodes to match
unified syntax.
(thumb32_opcodes): New table.
(print_insn_thumb): Rename print_insn_thumb16; don't handle
two-halfword branches here.
(print_insn_thumb32): New function.
(print_insn): Choose among print_insn_arm, print_insn_thumb16,
and print_insn_thumb32. Be consistent about order of
halfwords when printing 32-bit instructions.
gas:
* hash.c (hash_lookup): Add len parameter. All callers changed.
(hash_find_n): New interface.
* hash.h: Prototype hash_find_n.
* sb.c: Include as.h.
(scrub_from_sb, sb_to_scrub, scrub_position): New statics.
(sb_scrub_and_add_sb): New interface.
* sb.h: Prototype sb_scrub_and_add_sb.
* input-scrub.c (input_scrub_include_sb): Use sb_scrub_and_add_sb.
* config/tc-arm.h (TC_FORCE_RELOCATION_LOCAL): Remove
reference to BFD_RELOC_ARM_GOT12 which is never generated.
* config/tc-arm.c: Rewrite, adding Thumb-2 support.
gas/testsuite:
* gas/arm/arm.exp: Convert all existing "gas_test" tests to
"run_dump_test" tests. Run more tests unconditionally. Run new tests.
* gas/arm/arch4t.s, gas/arm/arch6zk.s, gas/arm/arm3.s, gas/arm/arm6.s
* gas/arm/arm7dm.s, gas/arm/bignum1.s, gas/arm/float.s
* gas/arm/immed.s, gas/arm/iwmmxt.s, gas/arm/offset.s, gas/arm/thumb.s:
Adjust to work as a dump test.
* gas/arm/arch4t.d, gas/arm/arch6zk.d, gas/arm/arm3.d, gas/arm/arm6.d
* gas/arm/arm7dm.d, gas/arm/bignum1.d, gas/arm/float.d
* gas/arm/immed.d, gas/arm/iwmmxt.d, gas/arm/offset.d, gas/arm/thumb.d:
New files.
* gas/arm/armv1-bad.l, gas/arm/armv1-bad.s: Remove tests for
diagnostics that don't happen in the first pass anymore.
* gas/arm/iwmmxt-bad.l, gas/arm/r15-bad.l, gas/arm/req.l
* gas/arm/vfp-bad.l:
Update expected diagnostics.
* gas/arm/pic.d: Update expected reloc name.
* gas/arm/thumbv6.d: CPY no longer appears in disassembly.
* gas/arm/r15-bad.s: Avoid two-argument mul.
* gas/arm/req.s: Adjust comments.
* gas/arm/maverick.d, gas/arm/maverick.s: Avoid inappropriate
use of PC.
* gas/arm/macro-1.d, gas/arm/macro1.s
* gas/arm/t16-bad.l, gas/arm/t16-bad.s
* gas/arm/tcompat.d, gas/arm/tcompat.s
* gas/arm/tcompat2.d, gas/arm/tcompat2.s
* gas/arm/thumb32.d, gas/arm/thumb32.s
New test pair.
ld/testsuite:
* ld-arm/mixed-app.d: Adjust expected disassembly a little.
2005-05-18 07:40:12 +02:00
|
|
|
|
|
2005-09-02 Paul Brook <paul@codesourcery.com>
bfd/
* libbdf.h: Regenerate.
* bfd-in2.h: Regenerate.
* reloc.c: Add BFD_RELOC_ARM_T32_CP_OFF_IMM and
BFD_RELOC_ARM_T32_CP_OFF_IMM_S2.
gas/
* config/tc-arm.c (encode_arm_cp_address): Use
BFD_RELOC_ARM_T32_CP_OFF_IMM in thumb mode.
(do_iwmmxt_wldstbh): Use BFD_RELOC_ARM_T32_CP_OFF_IMM_S2 in thumb
mode.
(md_assemble): Only allow coprocessor instructions when Thumb-2 is
available.
(cCE, cC3): Define.
(insns): Use them for coprocessor instructions.
(md_pcrel_from_section): Handle BFD_RELOC_ARM_T32_CP_OFF_IMM.
(get_thumb32_insn): New function.
(put_thumb32_insn): New function.
(md_apply_fix): Handle BFD_RELOC_ARM_T32_CP_OFF_IMM and
BFD_RELOC_ARM_T32_CP_OFF_IMM_S2.
gas/testsuite/
* gas/arm/vfp-bad_t2.d, gas/arm/vfp-bad_t2.l, arm/vfp-bad_t2.s,
gas/arm/vfp1_t2.d, gas/arm/vfp1_t2.s, gas/arm/vfp1xD_t2.d,
gas/arm/vfp1xD_t2.s, gas/arm/vfp2_t2.d, gas/arm/vfp2_t2.s): New files.
opcodes/
* arm-dis.c (coprocessor_opcodes): New.
(arm_opcodes, thumb32_opcodes): Remove coprocessor insns.
(print_insn_coprocessor): New function.
(print_insn_arm): Use print_insn_coprocessor. Remove coprocessor
format characters.
(print_insn_thumb32): Use print_insn_coprocessor.
2005-09-02 15:12:45 +02:00
|
|
|
|
/* ARM V6K NOP hints. */
|
2015-03-24 07:08:08 +01:00
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
|
|
|
|
|
|
0x0320f001, 0x0fffffff, "yield%c"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
|
|
|
|
|
|
0x0320f002, 0x0fffffff, "wfe%c"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
|
|
|
|
|
|
0x0320f003, 0x0fffffff, "wfi%c"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
|
|
|
|
|
|
0x0320f004, 0x0fffffff, "sev%c"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
|
|
|
|
|
|
0x0320f000, 0x0fffff00, "nop%c\t{%0-7d}"},
|
include/elf:
* arm.h: Import complete list of official relocation names
and numbers from AAELF. Define FAKE_RELOCs for old names.
Remove a few old names no longer used anywhere.
bfd:
* elf32-arm.c: Wherever possible, use official reloc names
from AAELF.
(elf32_arm_howto_table, elf32_arm_tls_gd32_howto)
(elf32_arm_tls_ldo32_howto, elf32_arm_tls_ldm32_howto)
(elf32_arm_tls_le32_howto, elf32_arm_tls_ie32_howto)
(elf32_arm_vtinherit_howto, elf32_arm_vtentry_howto)
(elf32_arm_pc11_howto, elf32_arm_thm_pc9_howto, elf32_arm_got_prel)
(elf32_arm_r_howto): Replace with elf32_arm_howto_table_1,
elf32_arm_howto_table_2, and elf32_arm_howto_table_3.
Add many new relocations from AAELF.
(elf32_arm_howto_from_type): Update to match.
(elf32_arm_reloc_map): Add entries for R_ARM_THM_JUMP24,
R_ARM_THM_JUMP11, R_ARM_THM_JUMP19, R_ARM_THM_JUMP8,
R_ARM_THM_JUMP6, R_ARM_GNU_VTINHERIT, and R_ARM_GNU_VTENTRY.
(elf32_arm_reloc_type_lookup): Use elf32_arm_howto_from_type.
(elf32_arm_final_link_relocate): Add support for
R_ARM_THM_JUMP24, R_ARM_THM_JUMP19, R_ARM_THM_JUMP6. Remove
case entries redundant with default.
* reloc.c: Reorganize ARM relocations. Add Thumb
assembler-internal relocations BFD_RELOC_ARM_T32_OFFSET_U8,
BFD_RELOC_ARM_T32_OFFSET_IMM, BFD_RELOC_ARM_T32_IMMEDIATE.
Add visible relocations BFD_RELOC_THUMB_PCREL_BRANCH7,
BFD_RELOC_THUMB_BRANCH20, BFD_RELOC_THUMB_BRANCH25.
Delete unused relocations BFD_RELOC_ARM_GOT12, BFD_RELOC_ARM_COPY.
* bfd-in2.h, libbfd.h: Regenerate.
opcodes:
* arm-dis.c (thumb_opcodes): Add disassembly for V6T2 16-bit
instructions. Adjust disassembly of some opcodes to match
unified syntax.
(thumb32_opcodes): New table.
(print_insn_thumb): Rename print_insn_thumb16; don't handle
two-halfword branches here.
(print_insn_thumb32): New function.
(print_insn): Choose among print_insn_arm, print_insn_thumb16,
and print_insn_thumb32. Be consistent about order of
halfwords when printing 32-bit instructions.
gas:
* hash.c (hash_lookup): Add len parameter. All callers changed.
(hash_find_n): New interface.
* hash.h: Prototype hash_find_n.
* sb.c: Include as.h.
(scrub_from_sb, sb_to_scrub, scrub_position): New statics.
(sb_scrub_and_add_sb): New interface.
* sb.h: Prototype sb_scrub_and_add_sb.
* input-scrub.c (input_scrub_include_sb): Use sb_scrub_and_add_sb.
* config/tc-arm.h (TC_FORCE_RELOCATION_LOCAL): Remove
reference to BFD_RELOC_ARM_GOT12 which is never generated.
* config/tc-arm.c: Rewrite, adding Thumb-2 support.
gas/testsuite:
* gas/arm/arm.exp: Convert all existing "gas_test" tests to
"run_dump_test" tests. Run more tests unconditionally. Run new tests.
* gas/arm/arch4t.s, gas/arm/arch6zk.s, gas/arm/arm3.s, gas/arm/arm6.s
* gas/arm/arm7dm.s, gas/arm/bignum1.s, gas/arm/float.s
* gas/arm/immed.s, gas/arm/iwmmxt.s, gas/arm/offset.s, gas/arm/thumb.s:
Adjust to work as a dump test.
* gas/arm/arch4t.d, gas/arm/arch6zk.d, gas/arm/arm3.d, gas/arm/arm6.d
* gas/arm/arm7dm.d, gas/arm/bignum1.d, gas/arm/float.d
* gas/arm/immed.d, gas/arm/iwmmxt.d, gas/arm/offset.d, gas/arm/thumb.d:
New files.
* gas/arm/armv1-bad.l, gas/arm/armv1-bad.s: Remove tests for
diagnostics that don't happen in the first pass anymore.
* gas/arm/iwmmxt-bad.l, gas/arm/r15-bad.l, gas/arm/req.l
* gas/arm/vfp-bad.l:
Update expected diagnostics.
* gas/arm/pic.d: Update expected reloc name.
* gas/arm/thumbv6.d: CPY no longer appears in disassembly.
* gas/arm/r15-bad.s: Avoid two-argument mul.
* gas/arm/req.s: Adjust comments.
* gas/arm/maverick.d, gas/arm/maverick.s: Avoid inappropriate
use of PC.
* gas/arm/macro-1.d, gas/arm/macro1.s
* gas/arm/t16-bad.l, gas/arm/t16-bad.s
* gas/arm/tcompat.d, gas/arm/tcompat.s
* gas/arm/tcompat2.d, gas/arm/tcompat2.s
* gas/arm/thumb32.d, gas/arm/thumb32.s
New test pair.
ld/testsuite:
* ld-arm/mixed-app.d: Adjust expected disassembly a little.
2005-05-18 07:40:12 +02:00
|
|
|
|
|
2009-06-30 13:57:05 +02:00
|
|
|
|
/* ARM V6 instructions. */
|
2015-03-24 07:08:08 +01:00
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
|
|
|
|
|
|
0xf1080000, 0xfffffe3f, "cpsie\t%8'a%7'i%6'f"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
|
|
|
|
|
|
0xf10a0000, 0xfffffe20, "cpsie\t%8'a%7'i%6'f,#%0-4d"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
|
|
|
|
|
|
0xf10C0000, 0xfffffe3f, "cpsid\t%8'a%7'i%6'f"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
|
|
|
|
|
|
0xf10e0000, 0xfffffe20, "cpsid\t%8'a%7'i%6'f,#%0-4d"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
|
|
|
|
|
|
0xf1000000, 0xfff1fe20, "cps\t#%0-4d"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
|
|
|
|
|
|
0x06800010, 0x0ff00ff0, "pkhbt%c\t%12-15R, %16-19R, %0-3R"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
|
|
|
|
|
|
0x06800010, 0x0ff00070, "pkhbt%c\t%12-15R, %16-19R, %0-3R, lsl #%7-11d"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
|
|
|
|
|
|
0x06800050, 0x0ff00ff0, "pkhtb%c\t%12-15R, %16-19R, %0-3R, asr #32"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
|
|
|
|
|
|
0x06800050, 0x0ff00070, "pkhtb%c\t%12-15R, %16-19R, %0-3R, asr #%7-11d"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
|
|
|
|
|
|
0x01900f9f, 0x0ff00fff, "ldrex%c\tr%12-15d, [%16-19R]"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
|
|
|
|
|
|
0x06200f10, 0x0ff00ff0, "qadd16%c\t%12-15R, %16-19R, %0-3R"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
|
|
|
|
|
|
0x06200f90, 0x0ff00ff0, "qadd8%c\t%12-15R, %16-19R, %0-3R"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
|
|
|
|
|
|
0x06200f30, 0x0ff00ff0, "qasx%c\t%12-15R, %16-19R, %0-3R"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
|
|
|
|
|
|
0x06200f70, 0x0ff00ff0, "qsub16%c\t%12-15R, %16-19R, %0-3R"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
|
|
|
|
|
|
0x06200ff0, 0x0ff00ff0, "qsub8%c\t%12-15R, %16-19R, %0-3R"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
|
|
|
|
|
|
0x06200f50, 0x0ff00ff0, "qsax%c\t%12-15R, %16-19R, %0-3R"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
|
|
|
|
|
|
0x06100f10, 0x0ff00ff0, "sadd16%c\t%12-15R, %16-19R, %0-3R"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
|
|
|
|
|
|
0x06100f90, 0x0ff00ff0, "sadd8%c\t%12-15R, %16-19R, %0-3R"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
|
|
|
|
|
|
0x06100f30, 0x0ff00ff0, "sasx%c\t%12-15R, %16-19R, %0-3R"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
|
|
|
|
|
|
0x06300f10, 0x0ff00ff0, "shadd16%c\t%12-15R, %16-19R, %0-3R"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
|
|
|
|
|
|
0x06300f90, 0x0ff00ff0, "shadd8%c\t%12-15R, %16-19R, %0-3R"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
|
|
|
|
|
|
0x06300f30, 0x0ff00ff0, "shasx%c\t%12-15R, %16-19R, %0-3R"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
|
|
|
|
|
|
0x06300f70, 0x0ff00ff0, "shsub16%c\t%12-15R, %16-19R, %0-3R"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
|
|
|
|
|
|
0x06300ff0, 0x0ff00ff0, "shsub8%c\t%12-15R, %16-19R, %0-3R"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
|
|
|
|
|
|
0x06300f50, 0x0ff00ff0, "shsax%c\t%12-15R, %16-19R, %0-3R"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
|
|
|
|
|
|
0x06100f70, 0x0ff00ff0, "ssub16%c\t%12-15R, %16-19R, %0-3R"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
|
|
|
|
|
|
0x06100ff0, 0x0ff00ff0, "ssub8%c\t%12-15R, %16-19R, %0-3R"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
|
|
|
|
|
|
0x06100f50, 0x0ff00ff0, "ssax%c\t%12-15R, %16-19R, %0-3R"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
|
|
|
|
|
|
0x06500f10, 0x0ff00ff0, "uadd16%c\t%12-15R, %16-19R, %0-3R"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
|
|
|
|
|
|
0x06500f90, 0x0ff00ff0, "uadd8%c\t%12-15R, %16-19R, %0-3R"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
|
|
|
|
|
|
0x06500f30, 0x0ff00ff0, "uasx%c\t%12-15R, %16-19R, %0-3R"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
|
|
|
|
|
|
0x06700f10, 0x0ff00ff0, "uhadd16%c\t%12-15R, %16-19R, %0-3R"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
|
|
|
|
|
|
0x06700f90, 0x0ff00ff0, "uhadd8%c\t%12-15R, %16-19R, %0-3R"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
|
|
|
|
|
|
0x06700f30, 0x0ff00ff0, "uhasx%c\t%12-15R, %16-19R, %0-3R"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
|
|
|
|
|
|
0x06700f70, 0x0ff00ff0, "uhsub16%c\t%12-15R, %16-19R, %0-3R"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
|
|
|
|
|
|
0x06700ff0, 0x0ff00ff0, "uhsub8%c\t%12-15R, %16-19R, %0-3R"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
|
|
|
|
|
|
0x06700f50, 0x0ff00ff0, "uhsax%c\t%12-15R, %16-19R, %0-3R"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
|
|
|
|
|
|
0x06600f10, 0x0ff00ff0, "uqadd16%c\t%12-15R, %16-19R, %0-3R"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
|
|
|
|
|
|
0x06600f90, 0x0ff00ff0, "uqadd8%c\t%12-15R, %16-19R, %0-3R"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
|
|
|
|
|
|
0x06600f30, 0x0ff00ff0, "uqasx%c\t%12-15R, %16-19R, %0-3R"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
|
|
|
|
|
|
0x06600f70, 0x0ff00ff0, "uqsub16%c\t%12-15R, %16-19R, %0-3R"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
|
|
|
|
|
|
0x06600ff0, 0x0ff00ff0, "uqsub8%c\t%12-15R, %16-19R, %0-3R"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
|
|
|
|
|
|
0x06600f50, 0x0ff00ff0, "uqsax%c\t%12-15R, %16-19R, %0-3R"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
|
|
|
|
|
|
0x06500f70, 0x0ff00ff0, "usub16%c\t%12-15R, %16-19R, %0-3R"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
|
|
|
|
|
|
0x06500ff0, 0x0ff00ff0, "usub8%c\t%12-15R, %16-19R, %0-3R"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
|
|
|
|
|
|
0x06500f50, 0x0ff00ff0, "usax%c\t%12-15R, %16-19R, %0-3R"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
|
|
|
|
|
|
0x06bf0f30, 0x0fff0ff0, "rev%c\t%12-15R, %0-3R"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
|
|
|
|
|
|
0x06bf0fb0, 0x0fff0ff0, "rev16%c\t%12-15R, %0-3R"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
|
|
|
|
|
|
0x06ff0fb0, 0x0fff0ff0, "revsh%c\t%12-15R, %0-3R"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
|
|
|
|
|
|
0xf8100a00, 0xfe50ffff, "rfe%23?id%24?ba\t%16-19r%21'!"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
|
|
|
|
|
|
0x06bf0070, 0x0fff0ff0, "sxth%c\t%12-15R, %0-3R"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
|
|
|
|
|
|
0x06bf0470, 0x0fff0ff0, "sxth%c\t%12-15R, %0-3R, ror #8"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
|
|
|
|
|
|
0x06bf0870, 0x0fff0ff0, "sxth%c\t%12-15R, %0-3R, ror #16"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
|
|
|
|
|
|
0x06bf0c70, 0x0fff0ff0, "sxth%c\t%12-15R, %0-3R, ror #24"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
|
|
|
|
|
|
0x068f0070, 0x0fff0ff0, "sxtb16%c\t%12-15R, %0-3R"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
|
|
|
|
|
|
0x068f0470, 0x0fff0ff0, "sxtb16%c\t%12-15R, %0-3R, ror #8"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
|
|
|
|
|
|
0x068f0870, 0x0fff0ff0, "sxtb16%c\t%12-15R, %0-3R, ror #16"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
|
|
|
|
|
|
0x068f0c70, 0x0fff0ff0, "sxtb16%c\t%12-15R, %0-3R, ror #24"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
|
|
|
|
|
|
0x06af0070, 0x0fff0ff0, "sxtb%c\t%12-15R, %0-3R"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
|
|
|
|
|
|
0x06af0470, 0x0fff0ff0, "sxtb%c\t%12-15R, %0-3R, ror #8"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
|
|
|
|
|
|
0x06af0870, 0x0fff0ff0, "sxtb%c\t%12-15R, %0-3R, ror #16"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
|
|
|
|
|
|
0x06af0c70, 0x0fff0ff0, "sxtb%c\t%12-15R, %0-3R, ror #24"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
|
|
|
|
|
|
0x06ff0070, 0x0fff0ff0, "uxth%c\t%12-15R, %0-3R"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
|
|
|
|
|
|
0x06ff0470, 0x0fff0ff0, "uxth%c\t%12-15R, %0-3R, ror #8"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
|
|
|
|
|
|
0x06ff0870, 0x0fff0ff0, "uxth%c\t%12-15R, %0-3R, ror #16"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
|
|
|
|
|
|
0x06ff0c70, 0x0fff0ff0, "uxth%c\t%12-15R, %0-3R, ror #24"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
|
|
|
|
|
|
0x06cf0070, 0x0fff0ff0, "uxtb16%c\t%12-15R, %0-3R"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
|
|
|
|
|
|
0x06cf0470, 0x0fff0ff0, "uxtb16%c\t%12-15R, %0-3R, ror #8"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
|
|
|
|
|
|
0x06cf0870, 0x0fff0ff0, "uxtb16%c\t%12-15R, %0-3R, ror #16"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
|
|
|
|
|
|
0x06cf0c70, 0x0fff0ff0, "uxtb16%c\t%12-15R, %0-3R, ror #24"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
|
|
|
|
|
|
0x06ef0070, 0x0fff0ff0, "uxtb%c\t%12-15R, %0-3R"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
|
|
|
|
|
|
0x06ef0470, 0x0fff0ff0, "uxtb%c\t%12-15R, %0-3R, ror #8"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
|
|
|
|
|
|
0x06ef0870, 0x0fff0ff0, "uxtb%c\t%12-15R, %0-3R, ror #16"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
|
|
|
|
|
|
0x06ef0c70, 0x0fff0ff0, "uxtb%c\t%12-15R, %0-3R, ror #24"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
|
|
|
|
|
|
0x06b00070, 0x0ff00ff0, "sxtah%c\t%12-15R, %16-19r, %0-3R"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
|
|
|
|
|
|
0x06b00470, 0x0ff00ff0, "sxtah%c\t%12-15R, %16-19r, %0-3R, ror #8"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
|
|
|
|
|
|
0x06b00870, 0x0ff00ff0, "sxtah%c\t%12-15R, %16-19r, %0-3R, ror #16"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
|
|
|
|
|
|
0x06b00c70, 0x0ff00ff0, "sxtah%c\t%12-15R, %16-19r, %0-3R, ror #24"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
|
|
|
|
|
|
0x06800070, 0x0ff00ff0, "sxtab16%c\t%12-15R, %16-19r, %0-3R"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
|
|
|
|
|
|
0x06800470, 0x0ff00ff0, "sxtab16%c\t%12-15R, %16-19r, %0-3R, ror #8"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
|
|
|
|
|
|
0x06800870, 0x0ff00ff0, "sxtab16%c\t%12-15R, %16-19r, %0-3R, ror #16"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
|
|
|
|
|
|
0x06800c70, 0x0ff00ff0, "sxtab16%c\t%12-15R, %16-19r, %0-3R, ror #24"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
|
|
|
|
|
|
0x06a00070, 0x0ff00ff0, "sxtab%c\t%12-15R, %16-19r, %0-3R"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
|
|
|
|
|
|
0x06a00470, 0x0ff00ff0, "sxtab%c\t%12-15R, %16-19r, %0-3R, ror #8"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
|
|
|
|
|
|
0x06a00870, 0x0ff00ff0, "sxtab%c\t%12-15R, %16-19r, %0-3R, ror #16"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
|
|
|
|
|
|
0x06a00c70, 0x0ff00ff0, "sxtab%c\t%12-15R, %16-19r, %0-3R, ror #24"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
|
|
|
|
|
|
0x06f00070, 0x0ff00ff0, "uxtah%c\t%12-15R, %16-19r, %0-3R"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
|
|
|
|
|
|
0x06f00470, 0x0ff00ff0, "uxtah%c\t%12-15R, %16-19r, %0-3R, ror #8"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
|
|
|
|
|
|
0x06f00870, 0x0ff00ff0, "uxtah%c\t%12-15R, %16-19r, %0-3R, ror #16"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
|
|
|
|
|
|
0x06f00c70, 0x0ff00ff0, "uxtah%c\t%12-15R, %16-19r, %0-3R, ror #24"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
|
|
|
|
|
|
0x06c00070, 0x0ff00ff0, "uxtab16%c\t%12-15R, %16-19r, %0-3R"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
|
|
|
|
|
|
0x06c00470, 0x0ff00ff0, "uxtab16%c\t%12-15R, %16-19r, %0-3R, ror #8"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
|
|
|
|
|
|
0x06c00870, 0x0ff00ff0, "uxtab16%c\t%12-15R, %16-19r, %0-3R, ror #16"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
|
|
|
|
|
|
0x06c00c70, 0x0ff00ff0, "uxtab16%c\t%12-15R, %16-19r, %0-3R, ROR #24"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
|
|
|
|
|
|
0x06e00070, 0x0ff00ff0, "uxtab%c\t%12-15R, %16-19r, %0-3R"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
|
|
|
|
|
|
0x06e00470, 0x0ff00ff0, "uxtab%c\t%12-15R, %16-19r, %0-3R, ror #8"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
|
|
|
|
|
|
0x06e00870, 0x0ff00ff0, "uxtab%c\t%12-15R, %16-19r, %0-3R, ror #16"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
|
|
|
|
|
|
0x06e00c70, 0x0ff00ff0, "uxtab%c\t%12-15R, %16-19r, %0-3R, ror #24"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
|
|
|
|
|
|
0x06800fb0, 0x0ff00ff0, "sel%c\t%12-15R, %16-19R, %0-3R"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
|
|
|
|
|
|
0xf1010000, 0xfffffc00, "setend\t%9?ble"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
|
|
|
|
|
|
0x0700f010, 0x0ff0f0d0, "smuad%5'x%c\t%16-19R, %0-3R, %8-11R"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
|
|
|
|
|
|
0x0700f050, 0x0ff0f0d0, "smusd%5'x%c\t%16-19R, %0-3R, %8-11R"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
|
|
|
|
|
|
0x07000010, 0x0ff000d0, "smlad%5'x%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
|
|
|
|
|
|
0x07400010, 0x0ff000d0, "smlald%5'x%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
|
|
|
|
|
|
0x07000050, 0x0ff000d0, "smlsd%5'x%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
|
|
|
|
|
|
0x07400050, 0x0ff000d0, "smlsld%5'x%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
|
|
|
|
|
|
0x0750f010, 0x0ff0f0d0, "smmul%5'r%c\t%16-19R, %0-3R, %8-11R"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
|
|
|
|
|
|
0x07500010, 0x0ff000d0, "smmla%5'r%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
|
|
|
|
|
|
0x075000d0, 0x0ff000d0, "smmls%5'r%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
|
|
|
|
|
|
0xf84d0500, 0xfe5fffe0, "srs%23?id%24?ba\t%16-19r%21'!, #%0-4d"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
|
|
|
|
|
|
0x06a00010, 0x0fe00ff0, "ssat%c\t%12-15R, #%16-20W, %0-3R"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
|
|
|
|
|
|
0x06a00010, 0x0fe00070, "ssat%c\t%12-15R, #%16-20W, %0-3R, lsl #%7-11d"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
|
|
|
|
|
|
0x06a00050, 0x0fe00070, "ssat%c\t%12-15R, #%16-20W, %0-3R, asr #%7-11d"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
|
|
|
|
|
|
0x06a00f30, 0x0ff00ff0, "ssat16%c\t%12-15r, #%16-19W, %0-3r"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
|
|
|
|
|
|
0x01800f90, 0x0ff00ff0, "strex%c\t%12-15R, %0-3R, [%16-19R]"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
|
|
|
|
|
|
0x00400090, 0x0ff000f0, "umaal%c\t%12-15R, %16-19R, %0-3R, %8-11R"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
|
|
|
|
|
|
0x0780f010, 0x0ff0f0f0, "usad8%c\t%16-19R, %0-3R, %8-11R"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
|
|
|
|
|
|
0x07800010, 0x0ff000f0, "usada8%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
|
|
|
|
|
|
0x06e00010, 0x0fe00ff0, "usat%c\t%12-15R, #%16-20d, %0-3R"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
|
|
|
|
|
|
0x06e00010, 0x0fe00070, "usat%c\t%12-15R, #%16-20d, %0-3R, lsl #%7-11d"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
|
|
|
|
|
|
0x06e00050, 0x0fe00070, "usat%c\t%12-15R, #%16-20d, %0-3R, asr #%7-11d"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
|
|
|
|
|
|
0x06e00f30, 0x0ff00ff0, "usat16%c\t%12-15R, #%16-19d, %0-3R"},
|
include/elf:
* arm.h: Import complete list of official relocation names
and numbers from AAELF. Define FAKE_RELOCs for old names.
Remove a few old names no longer used anywhere.
bfd:
* elf32-arm.c: Wherever possible, use official reloc names
from AAELF.
(elf32_arm_howto_table, elf32_arm_tls_gd32_howto)
(elf32_arm_tls_ldo32_howto, elf32_arm_tls_ldm32_howto)
(elf32_arm_tls_le32_howto, elf32_arm_tls_ie32_howto)
(elf32_arm_vtinherit_howto, elf32_arm_vtentry_howto)
(elf32_arm_pc11_howto, elf32_arm_thm_pc9_howto, elf32_arm_got_prel)
(elf32_arm_r_howto): Replace with elf32_arm_howto_table_1,
elf32_arm_howto_table_2, and elf32_arm_howto_table_3.
Add many new relocations from AAELF.
(elf32_arm_howto_from_type): Update to match.
(elf32_arm_reloc_map): Add entries for R_ARM_THM_JUMP24,
R_ARM_THM_JUMP11, R_ARM_THM_JUMP19, R_ARM_THM_JUMP8,
R_ARM_THM_JUMP6, R_ARM_GNU_VTINHERIT, and R_ARM_GNU_VTENTRY.
(elf32_arm_reloc_type_lookup): Use elf32_arm_howto_from_type.
(elf32_arm_final_link_relocate): Add support for
R_ARM_THM_JUMP24, R_ARM_THM_JUMP19, R_ARM_THM_JUMP6. Remove
case entries redundant with default.
* reloc.c: Reorganize ARM relocations. Add Thumb
assembler-internal relocations BFD_RELOC_ARM_T32_OFFSET_U8,
BFD_RELOC_ARM_T32_OFFSET_IMM, BFD_RELOC_ARM_T32_IMMEDIATE.
Add visible relocations BFD_RELOC_THUMB_PCREL_BRANCH7,
BFD_RELOC_THUMB_BRANCH20, BFD_RELOC_THUMB_BRANCH25.
Delete unused relocations BFD_RELOC_ARM_GOT12, BFD_RELOC_ARM_COPY.
* bfd-in2.h, libbfd.h: Regenerate.
opcodes:
* arm-dis.c (thumb_opcodes): Add disassembly for V6T2 16-bit
instructions. Adjust disassembly of some opcodes to match
unified syntax.
(thumb32_opcodes): New table.
(print_insn_thumb): Rename print_insn_thumb16; don't handle
two-halfword branches here.
(print_insn_thumb32): New function.
(print_insn): Choose among print_insn_arm, print_insn_thumb16,
and print_insn_thumb32. Be consistent about order of
halfwords when printing 32-bit instructions.
gas:
* hash.c (hash_lookup): Add len parameter. All callers changed.
(hash_find_n): New interface.
* hash.h: Prototype hash_find_n.
* sb.c: Include as.h.
(scrub_from_sb, sb_to_scrub, scrub_position): New statics.
(sb_scrub_and_add_sb): New interface.
* sb.h: Prototype sb_scrub_and_add_sb.
* input-scrub.c (input_scrub_include_sb): Use sb_scrub_and_add_sb.
* config/tc-arm.h (TC_FORCE_RELOCATION_LOCAL): Remove
reference to BFD_RELOC_ARM_GOT12 which is never generated.
* config/tc-arm.c: Rewrite, adding Thumb-2 support.
gas/testsuite:
* gas/arm/arm.exp: Convert all existing "gas_test" tests to
"run_dump_test" tests. Run more tests unconditionally. Run new tests.
* gas/arm/arch4t.s, gas/arm/arch6zk.s, gas/arm/arm3.s, gas/arm/arm6.s
* gas/arm/arm7dm.s, gas/arm/bignum1.s, gas/arm/float.s
* gas/arm/immed.s, gas/arm/iwmmxt.s, gas/arm/offset.s, gas/arm/thumb.s:
Adjust to work as a dump test.
* gas/arm/arch4t.d, gas/arm/arch6zk.d, gas/arm/arm3.d, gas/arm/arm6.d
* gas/arm/arm7dm.d, gas/arm/bignum1.d, gas/arm/float.d
* gas/arm/immed.d, gas/arm/iwmmxt.d, gas/arm/offset.d, gas/arm/thumb.d:
New files.
* gas/arm/armv1-bad.l, gas/arm/armv1-bad.s: Remove tests for
diagnostics that don't happen in the first pass anymore.
* gas/arm/iwmmxt-bad.l, gas/arm/r15-bad.l, gas/arm/req.l
* gas/arm/vfp-bad.l:
Update expected diagnostics.
* gas/arm/pic.d: Update expected reloc name.
* gas/arm/thumbv6.d: CPY no longer appears in disassembly.
* gas/arm/r15-bad.s: Avoid two-argument mul.
* gas/arm/req.s: Adjust comments.
* gas/arm/maverick.d, gas/arm/maverick.s: Avoid inappropriate
use of PC.
* gas/arm/macro-1.d, gas/arm/macro1.s
* gas/arm/t16-bad.l, gas/arm/t16-bad.s
* gas/arm/tcompat.d, gas/arm/tcompat.s
* gas/arm/tcompat2.d, gas/arm/tcompat2.s
* gas/arm/thumb32.d, gas/arm/thumb32.s
New test pair.
ld/testsuite:
* ld-arm/mixed-app.d: Adjust expected disassembly a little.
2005-05-18 07:40:12 +02:00
|
|
|
|
|
2005-09-02 Paul Brook <paul@codesourcery.com>
bfd/
* libbdf.h: Regenerate.
* bfd-in2.h: Regenerate.
* reloc.c: Add BFD_RELOC_ARM_T32_CP_OFF_IMM and
BFD_RELOC_ARM_T32_CP_OFF_IMM_S2.
gas/
* config/tc-arm.c (encode_arm_cp_address): Use
BFD_RELOC_ARM_T32_CP_OFF_IMM in thumb mode.
(do_iwmmxt_wldstbh): Use BFD_RELOC_ARM_T32_CP_OFF_IMM_S2 in thumb
mode.
(md_assemble): Only allow coprocessor instructions when Thumb-2 is
available.
(cCE, cC3): Define.
(insns): Use them for coprocessor instructions.
(md_pcrel_from_section): Handle BFD_RELOC_ARM_T32_CP_OFF_IMM.
(get_thumb32_insn): New function.
(put_thumb32_insn): New function.
(md_apply_fix): Handle BFD_RELOC_ARM_T32_CP_OFF_IMM and
BFD_RELOC_ARM_T32_CP_OFF_IMM_S2.
gas/testsuite/
* gas/arm/vfp-bad_t2.d, gas/arm/vfp-bad_t2.l, arm/vfp-bad_t2.s,
gas/arm/vfp1_t2.d, gas/arm/vfp1_t2.s, gas/arm/vfp1xD_t2.d,
gas/arm/vfp1xD_t2.s, gas/arm/vfp2_t2.d, gas/arm/vfp2_t2.s): New files.
opcodes/
* arm-dis.c (coprocessor_opcodes): New.
(arm_opcodes, thumb32_opcodes): Remove coprocessor insns.
(print_insn_coprocessor): New function.
(print_insn_arm): Use print_insn_coprocessor. Remove coprocessor
format characters.
(print_insn_thumb32): Use print_insn_coprocessor.
2005-09-02 15:12:45 +02:00
|
|
|
|
/* V5J instruction. */
|
2015-03-24 07:08:08 +01:00
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V5J),
|
|
|
|
|
|
0x012fff20, 0x0ffffff0, "bxj%c\t%0-3R"},
|
include/elf:
* arm.h: Import complete list of official relocation names
and numbers from AAELF. Define FAKE_RELOCs for old names.
Remove a few old names no longer used anywhere.
bfd:
* elf32-arm.c: Wherever possible, use official reloc names
from AAELF.
(elf32_arm_howto_table, elf32_arm_tls_gd32_howto)
(elf32_arm_tls_ldo32_howto, elf32_arm_tls_ldm32_howto)
(elf32_arm_tls_le32_howto, elf32_arm_tls_ie32_howto)
(elf32_arm_vtinherit_howto, elf32_arm_vtentry_howto)
(elf32_arm_pc11_howto, elf32_arm_thm_pc9_howto, elf32_arm_got_prel)
(elf32_arm_r_howto): Replace with elf32_arm_howto_table_1,
elf32_arm_howto_table_2, and elf32_arm_howto_table_3.
Add many new relocations from AAELF.
(elf32_arm_howto_from_type): Update to match.
(elf32_arm_reloc_map): Add entries for R_ARM_THM_JUMP24,
R_ARM_THM_JUMP11, R_ARM_THM_JUMP19, R_ARM_THM_JUMP8,
R_ARM_THM_JUMP6, R_ARM_GNU_VTINHERIT, and R_ARM_GNU_VTENTRY.
(elf32_arm_reloc_type_lookup): Use elf32_arm_howto_from_type.
(elf32_arm_final_link_relocate): Add support for
R_ARM_THM_JUMP24, R_ARM_THM_JUMP19, R_ARM_THM_JUMP6. Remove
case entries redundant with default.
* reloc.c: Reorganize ARM relocations. Add Thumb
assembler-internal relocations BFD_RELOC_ARM_T32_OFFSET_U8,
BFD_RELOC_ARM_T32_OFFSET_IMM, BFD_RELOC_ARM_T32_IMMEDIATE.
Add visible relocations BFD_RELOC_THUMB_PCREL_BRANCH7,
BFD_RELOC_THUMB_BRANCH20, BFD_RELOC_THUMB_BRANCH25.
Delete unused relocations BFD_RELOC_ARM_GOT12, BFD_RELOC_ARM_COPY.
* bfd-in2.h, libbfd.h: Regenerate.
opcodes:
* arm-dis.c (thumb_opcodes): Add disassembly for V6T2 16-bit
instructions. Adjust disassembly of some opcodes to match
unified syntax.
(thumb32_opcodes): New table.
(print_insn_thumb): Rename print_insn_thumb16; don't handle
two-halfword branches here.
(print_insn_thumb32): New function.
(print_insn): Choose among print_insn_arm, print_insn_thumb16,
and print_insn_thumb32. Be consistent about order of
halfwords when printing 32-bit instructions.
gas:
* hash.c (hash_lookup): Add len parameter. All callers changed.
(hash_find_n): New interface.
* hash.h: Prototype hash_find_n.
* sb.c: Include as.h.
(scrub_from_sb, sb_to_scrub, scrub_position): New statics.
(sb_scrub_and_add_sb): New interface.
* sb.h: Prototype sb_scrub_and_add_sb.
* input-scrub.c (input_scrub_include_sb): Use sb_scrub_and_add_sb.
* config/tc-arm.h (TC_FORCE_RELOCATION_LOCAL): Remove
reference to BFD_RELOC_ARM_GOT12 which is never generated.
* config/tc-arm.c: Rewrite, adding Thumb-2 support.
gas/testsuite:
* gas/arm/arm.exp: Convert all existing "gas_test" tests to
"run_dump_test" tests. Run more tests unconditionally. Run new tests.
* gas/arm/arch4t.s, gas/arm/arch6zk.s, gas/arm/arm3.s, gas/arm/arm6.s
* gas/arm/arm7dm.s, gas/arm/bignum1.s, gas/arm/float.s
* gas/arm/immed.s, gas/arm/iwmmxt.s, gas/arm/offset.s, gas/arm/thumb.s:
Adjust to work as a dump test.
* gas/arm/arch4t.d, gas/arm/arch6zk.d, gas/arm/arm3.d, gas/arm/arm6.d
* gas/arm/arm7dm.d, gas/arm/bignum1.d, gas/arm/float.d
* gas/arm/immed.d, gas/arm/iwmmxt.d, gas/arm/offset.d, gas/arm/thumb.d:
New files.
* gas/arm/armv1-bad.l, gas/arm/armv1-bad.s: Remove tests for
diagnostics that don't happen in the first pass anymore.
* gas/arm/iwmmxt-bad.l, gas/arm/r15-bad.l, gas/arm/req.l
* gas/arm/vfp-bad.l:
Update expected diagnostics.
* gas/arm/pic.d: Update expected reloc name.
* gas/arm/thumbv6.d: CPY no longer appears in disassembly.
* gas/arm/r15-bad.s: Avoid two-argument mul.
* gas/arm/req.s: Adjust comments.
* gas/arm/maverick.d, gas/arm/maverick.s: Avoid inappropriate
use of PC.
* gas/arm/macro-1.d, gas/arm/macro1.s
* gas/arm/t16-bad.l, gas/arm/t16-bad.s
* gas/arm/tcompat.d, gas/arm/tcompat.s
* gas/arm/tcompat2.d, gas/arm/tcompat2.s
* gas/arm/thumb32.d, gas/arm/thumb32.s
New test pair.
ld/testsuite:
* ld-arm/mixed-app.d: Adjust expected disassembly a little.
2005-05-18 07:40:12 +02:00
|
|
|
|
|
2005-09-02 Paul Brook <paul@codesourcery.com>
bfd/
* libbdf.h: Regenerate.
* bfd-in2.h: Regenerate.
* reloc.c: Add BFD_RELOC_ARM_T32_CP_OFF_IMM and
BFD_RELOC_ARM_T32_CP_OFF_IMM_S2.
gas/
* config/tc-arm.c (encode_arm_cp_address): Use
BFD_RELOC_ARM_T32_CP_OFF_IMM in thumb mode.
(do_iwmmxt_wldstbh): Use BFD_RELOC_ARM_T32_CP_OFF_IMM_S2 in thumb
mode.
(md_assemble): Only allow coprocessor instructions when Thumb-2 is
available.
(cCE, cC3): Define.
(insns): Use them for coprocessor instructions.
(md_pcrel_from_section): Handle BFD_RELOC_ARM_T32_CP_OFF_IMM.
(get_thumb32_insn): New function.
(put_thumb32_insn): New function.
(md_apply_fix): Handle BFD_RELOC_ARM_T32_CP_OFF_IMM and
BFD_RELOC_ARM_T32_CP_OFF_IMM_S2.
gas/testsuite/
* gas/arm/vfp-bad_t2.d, gas/arm/vfp-bad_t2.l, arm/vfp-bad_t2.s,
gas/arm/vfp1_t2.d, gas/arm/vfp1_t2.s, gas/arm/vfp1xD_t2.d,
gas/arm/vfp1xD_t2.s, gas/arm/vfp2_t2.d, gas/arm/vfp2_t2.s): New files.
opcodes/
* arm-dis.c (coprocessor_opcodes): New.
(arm_opcodes, thumb32_opcodes): Remove coprocessor insns.
(print_insn_coprocessor): New function.
(print_insn_arm): Use print_insn_coprocessor. Remove coprocessor
format characters.
(print_insn_thumb32): Use print_insn_coprocessor.
2005-09-02 15:12:45 +02:00
|
|
|
|
/* V5 Instructions. */
|
2015-03-24 07:08:08 +01:00
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
|
|
|
|
|
|
0xe1200070, 0xfff000f0,
|
|
|
|
|
|
"bkpt\t0x%16-19X%12-15X%8-11X%0-3X"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
|
|
|
|
|
|
0xfa000000, 0xfe000000, "blx\t%B"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
|
|
|
|
|
|
0x012fff30, 0x0ffffff0, "blx%c\t%0-3R"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
|
|
|
|
|
|
0x016f0f10, 0x0fff0ff0, "clz%c\t%12-15R, %0-3R"},
|
|
|
|
|
|
|
|
|
|
|
|
/* V5E "El Segundo" Instructions. */
|
|
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V5E),
|
|
|
|
|
|
0x000000d0, 0x0e1000f0, "ldrd%c\t%12-15r, %s"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V5E),
|
|
|
|
|
|
0x000000f0, 0x0e1000f0, "strd%c\t%12-15r, %s"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V5E),
|
|
|
|
|
|
0xf450f000, 0xfc70f000, "pld\t%a"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
|
|
|
|
|
|
0x01000080, 0x0ff000f0, "smlabb%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
|
|
|
|
|
|
0x010000a0, 0x0ff000f0, "smlatb%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
|
|
|
|
|
|
0x010000c0, 0x0ff000f0, "smlabt%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
|
|
|
|
|
|
0x010000e0, 0x0ff000f0, "smlatt%c\t%16-19r, %0-3r, %8-11R, %12-15R"},
|
|
|
|
|
|
|
|
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
|
|
|
|
|
|
0x01200080, 0x0ff000f0, "smlawb%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
|
|
|
|
|
|
0x012000c0, 0x0ff000f0, "smlawt%c\t%16-19R, %0-3r, %8-11R, %12-15R"},
|
|
|
|
|
|
|
|
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
|
|
|
|
|
|
0x01400080, 0x0ff000f0, "smlalbb%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
|
|
|
|
|
|
0x014000a0, 0x0ff000f0, "smlaltb%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
|
|
|
|
|
|
0x014000c0, 0x0ff000f0, "smlalbt%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
|
|
|
|
|
|
0x014000e0, 0x0ff000f0, "smlaltt%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
|
|
|
|
|
|
|
|
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
|
|
|
|
|
|
0x01600080, 0x0ff0f0f0, "smulbb%c\t%16-19R, %0-3R, %8-11R"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
|
|
|
|
|
|
0x016000a0, 0x0ff0f0f0, "smultb%c\t%16-19R, %0-3R, %8-11R"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
|
|
|
|
|
|
0x016000c0, 0x0ff0f0f0, "smulbt%c\t%16-19R, %0-3R, %8-11R"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
|
|
|
|
|
|
0x016000e0, 0x0ff0f0f0, "smultt%c\t%16-19R, %0-3R, %8-11R"},
|
|
|
|
|
|
|
|
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
|
|
|
|
|
|
0x012000a0, 0x0ff0f0f0, "smulwb%c\t%16-19R, %0-3R, %8-11R"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
|
|
|
|
|
|
0x012000e0, 0x0ff0f0f0, "smulwt%c\t%16-19R, %0-3R, %8-11R"},
|
|
|
|
|
|
|
|
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
|
|
|
|
|
|
0x01000050, 0x0ff00ff0, "qadd%c\t%12-15R, %0-3R, %16-19R"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
|
|
|
|
|
|
0x01400050, 0x0ff00ff0, "qdadd%c\t%12-15R, %0-3R, %16-19R"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
|
|
|
|
|
|
0x01200050, 0x0ff00ff0, "qsub%c\t%12-15R, %0-3R, %16-19R"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
|
|
|
|
|
|
0x01600050, 0x0ff00ff0, "qdsub%c\t%12-15R, %0-3R, %16-19R"},
|
include/elf:
* arm.h: Import complete list of official relocation names
and numbers from AAELF. Define FAKE_RELOCs for old names.
Remove a few old names no longer used anywhere.
bfd:
* elf32-arm.c: Wherever possible, use official reloc names
from AAELF.
(elf32_arm_howto_table, elf32_arm_tls_gd32_howto)
(elf32_arm_tls_ldo32_howto, elf32_arm_tls_ldm32_howto)
(elf32_arm_tls_le32_howto, elf32_arm_tls_ie32_howto)
(elf32_arm_vtinherit_howto, elf32_arm_vtentry_howto)
(elf32_arm_pc11_howto, elf32_arm_thm_pc9_howto, elf32_arm_got_prel)
(elf32_arm_r_howto): Replace with elf32_arm_howto_table_1,
elf32_arm_howto_table_2, and elf32_arm_howto_table_3.
Add many new relocations from AAELF.
(elf32_arm_howto_from_type): Update to match.
(elf32_arm_reloc_map): Add entries for R_ARM_THM_JUMP24,
R_ARM_THM_JUMP11, R_ARM_THM_JUMP19, R_ARM_THM_JUMP8,
R_ARM_THM_JUMP6, R_ARM_GNU_VTINHERIT, and R_ARM_GNU_VTENTRY.
(elf32_arm_reloc_type_lookup): Use elf32_arm_howto_from_type.
(elf32_arm_final_link_relocate): Add support for
R_ARM_THM_JUMP24, R_ARM_THM_JUMP19, R_ARM_THM_JUMP6. Remove
case entries redundant with default.
* reloc.c: Reorganize ARM relocations. Add Thumb
assembler-internal relocations BFD_RELOC_ARM_T32_OFFSET_U8,
BFD_RELOC_ARM_T32_OFFSET_IMM, BFD_RELOC_ARM_T32_IMMEDIATE.
Add visible relocations BFD_RELOC_THUMB_PCREL_BRANCH7,
BFD_RELOC_THUMB_BRANCH20, BFD_RELOC_THUMB_BRANCH25.
Delete unused relocations BFD_RELOC_ARM_GOT12, BFD_RELOC_ARM_COPY.
* bfd-in2.h, libbfd.h: Regenerate.
opcodes:
* arm-dis.c (thumb_opcodes): Add disassembly for V6T2 16-bit
instructions. Adjust disassembly of some opcodes to match
unified syntax.
(thumb32_opcodes): New table.
(print_insn_thumb): Rename print_insn_thumb16; don't handle
two-halfword branches here.
(print_insn_thumb32): New function.
(print_insn): Choose among print_insn_arm, print_insn_thumb16,
and print_insn_thumb32. Be consistent about order of
halfwords when printing 32-bit instructions.
gas:
* hash.c (hash_lookup): Add len parameter. All callers changed.
(hash_find_n): New interface.
* hash.h: Prototype hash_find_n.
* sb.c: Include as.h.
(scrub_from_sb, sb_to_scrub, scrub_position): New statics.
(sb_scrub_and_add_sb): New interface.
* sb.h: Prototype sb_scrub_and_add_sb.
* input-scrub.c (input_scrub_include_sb): Use sb_scrub_and_add_sb.
* config/tc-arm.h (TC_FORCE_RELOCATION_LOCAL): Remove
reference to BFD_RELOC_ARM_GOT12 which is never generated.
* config/tc-arm.c: Rewrite, adding Thumb-2 support.
gas/testsuite:
* gas/arm/arm.exp: Convert all existing "gas_test" tests to
"run_dump_test" tests. Run more tests unconditionally. Run new tests.
* gas/arm/arch4t.s, gas/arm/arch6zk.s, gas/arm/arm3.s, gas/arm/arm6.s
* gas/arm/arm7dm.s, gas/arm/bignum1.s, gas/arm/float.s
* gas/arm/immed.s, gas/arm/iwmmxt.s, gas/arm/offset.s, gas/arm/thumb.s:
Adjust to work as a dump test.
* gas/arm/arch4t.d, gas/arm/arch6zk.d, gas/arm/arm3.d, gas/arm/arm6.d
* gas/arm/arm7dm.d, gas/arm/bignum1.d, gas/arm/float.d
* gas/arm/immed.d, gas/arm/iwmmxt.d, gas/arm/offset.d, gas/arm/thumb.d:
New files.
* gas/arm/armv1-bad.l, gas/arm/armv1-bad.s: Remove tests for
diagnostics that don't happen in the first pass anymore.
* gas/arm/iwmmxt-bad.l, gas/arm/r15-bad.l, gas/arm/req.l
* gas/arm/vfp-bad.l:
Update expected diagnostics.
* gas/arm/pic.d: Update expected reloc name.
* gas/arm/thumbv6.d: CPY no longer appears in disassembly.
* gas/arm/r15-bad.s: Avoid two-argument mul.
* gas/arm/req.s: Adjust comments.
* gas/arm/maverick.d, gas/arm/maverick.s: Avoid inappropriate
use of PC.
* gas/arm/macro-1.d, gas/arm/macro1.s
* gas/arm/t16-bad.l, gas/arm/t16-bad.s
* gas/arm/tcompat.d, gas/arm/tcompat.s
* gas/arm/tcompat2.d, gas/arm/tcompat2.s
* gas/arm/thumb32.d, gas/arm/thumb32.s
New test pair.
ld/testsuite:
* ld-arm/mixed-app.d: Adjust expected disassembly a little.
2005-05-18 07:40:12 +02:00
|
|
|
|
|
2005-09-02 Paul Brook <paul@codesourcery.com>
bfd/
* libbdf.h: Regenerate.
* bfd-in2.h: Regenerate.
* reloc.c: Add BFD_RELOC_ARM_T32_CP_OFF_IMM and
BFD_RELOC_ARM_T32_CP_OFF_IMM_S2.
gas/
* config/tc-arm.c (encode_arm_cp_address): Use
BFD_RELOC_ARM_T32_CP_OFF_IMM in thumb mode.
(do_iwmmxt_wldstbh): Use BFD_RELOC_ARM_T32_CP_OFF_IMM_S2 in thumb
mode.
(md_assemble): Only allow coprocessor instructions when Thumb-2 is
available.
(cCE, cC3): Define.
(insns): Use them for coprocessor instructions.
(md_pcrel_from_section): Handle BFD_RELOC_ARM_T32_CP_OFF_IMM.
(get_thumb32_insn): New function.
(put_thumb32_insn): New function.
(md_apply_fix): Handle BFD_RELOC_ARM_T32_CP_OFF_IMM and
BFD_RELOC_ARM_T32_CP_OFF_IMM_S2.
gas/testsuite/
* gas/arm/vfp-bad_t2.d, gas/arm/vfp-bad_t2.l, arm/vfp-bad_t2.s,
gas/arm/vfp1_t2.d, gas/arm/vfp1_t2.s, gas/arm/vfp1xD_t2.d,
gas/arm/vfp1xD_t2.s, gas/arm/vfp2_t2.d, gas/arm/vfp2_t2.s): New files.
opcodes/
* arm-dis.c (coprocessor_opcodes): New.
(arm_opcodes, thumb32_opcodes): Remove coprocessor insns.
(print_insn_coprocessor): New function.
(print_insn_arm): Use print_insn_coprocessor. Remove coprocessor
format characters.
(print_insn_thumb32): Use print_insn_coprocessor.
2005-09-02 15:12:45 +02:00
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/* ARM Instructions. */
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2015-03-24 07:08:08 +01:00
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{ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
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0x052d0004, 0x0fff0fff, "push%c\t{%12-15r}\t\t; (str%c %12-15r, %a)"},
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{ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
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0x04400000, 0x0e500000, "strb%t%c\t%12-15R, %a"},
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{ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
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0x04000000, 0x0e500000, "str%t%c\t%12-15r, %a"},
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{ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
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0x06400000, 0x0e500ff0, "strb%t%c\t%12-15R, %a"},
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{ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
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0x06000000, 0x0e500ff0, "str%t%c\t%12-15r, %a"},
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{ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
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0x04400000, 0x0c500010, "strb%t%c\t%12-15R, %a"},
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{ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
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0x04000000, 0x0c500010, "str%t%c\t%12-15r, %a"},
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{ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
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0x04400000, 0x0e500000, "strb%c\t%12-15R, %a"},
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{ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
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0x06400000, 0x0e500010, "strb%c\t%12-15R, %a"},
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{ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
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0x004000b0, 0x0e5000f0, "strh%c\t%12-15R, %s"},
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{ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
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0x000000b0, 0x0e500ff0, "strh%c\t%12-15R, %s"},
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{ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
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0x00500090, 0x0e5000f0, UNDEFINED_INSTRUCTION},
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{ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
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0x00500090, 0x0e500090, "ldr%6's%5?hb%c\t%12-15R, %s"},
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{ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
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0x00100090, 0x0e500ff0, UNDEFINED_INSTRUCTION},
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{ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
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0x00100090, 0x0e500f90, "ldr%6's%5?hb%c\t%12-15R, %s"},
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{ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
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0x02000000, 0x0fe00000, "and%20's%c\t%12-15r, %16-19r, %o"},
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{ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
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0x00000000, 0x0fe00010, "and%20's%c\t%12-15r, %16-19r, %o"},
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{ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
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0x00000010, 0x0fe00090, "and%20's%c\t%12-15R, %16-19R, %o"},
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{ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
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0x02200000, 0x0fe00000, "eor%20's%c\t%12-15r, %16-19r, %o"},
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{ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
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0x00200000, 0x0fe00010, "eor%20's%c\t%12-15r, %16-19r, %o"},
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{ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
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0x00200010, 0x0fe00090, "eor%20's%c\t%12-15R, %16-19R, %o"},
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{ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
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0x02400000, 0x0fe00000, "sub%20's%c\t%12-15r, %16-19r, %o"},
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{ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
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0x00400000, 0x0fe00010, "sub%20's%c\t%12-15r, %16-19r, %o"},
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{ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
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0x00400010, 0x0fe00090, "sub%20's%c\t%12-15R, %16-19R, %o"},
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{ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
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0x02600000, 0x0fe00000, "rsb%20's%c\t%12-15r, %16-19r, %o"},
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{ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
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0x00600000, 0x0fe00010, "rsb%20's%c\t%12-15r, %16-19r, %o"},
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{ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
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0x00600010, 0x0fe00090, "rsb%20's%c\t%12-15R, %16-19R, %o"},
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{ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
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0x02800000, 0x0fe00000, "add%20's%c\t%12-15r, %16-19r, %o"},
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{ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
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0x00800000, 0x0fe00010, "add%20's%c\t%12-15r, %16-19r, %o"},
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{ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
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0x00800010, 0x0fe00090, "add%20's%c\t%12-15R, %16-19R, %o"},
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{ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
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0x02a00000, 0x0fe00000, "adc%20's%c\t%12-15r, %16-19r, %o"},
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{ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
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0x00a00000, 0x0fe00010, "adc%20's%c\t%12-15r, %16-19r, %o"},
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{ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
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0x00a00010, 0x0fe00090, "adc%20's%c\t%12-15R, %16-19R, %o"},
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{ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
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0x02c00000, 0x0fe00000, "sbc%20's%c\t%12-15r, %16-19r, %o"},
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{ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
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0x00c00000, 0x0fe00010, "sbc%20's%c\t%12-15r, %16-19r, %o"},
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{ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
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0x00c00010, 0x0fe00090, "sbc%20's%c\t%12-15R, %16-19R, %o"},
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{ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
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0x02e00000, 0x0fe00000, "rsc%20's%c\t%12-15r, %16-19r, %o"},
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{ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
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0x00e00000, 0x0fe00010, "rsc%20's%c\t%12-15r, %16-19r, %o"},
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{ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
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0x00e00010, 0x0fe00090, "rsc%20's%c\t%12-15R, %16-19R, %o"},
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{ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT),
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0x0120f200, 0x0fb0f200, "msr%c\t%C, %0-3r"},
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{ARM_FEATURE_CORE_LOW (ARM_EXT_V3),
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0x0120f000, 0x0db0f000, "msr%c\t%C, %o"},
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{ARM_FEATURE_CORE_LOW (ARM_EXT_V3),
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0x01000000, 0x0fb00cff, "mrs%c\t%12-15R, %R"},
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{ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
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0x03000000, 0x0fe00000, "tst%p%c\t%16-19r, %o"},
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{ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
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0x01000000, 0x0fe00010, "tst%p%c\t%16-19r, %o"},
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{ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
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0x01000010, 0x0fe00090, "tst%p%c\t%16-19R, %o"},
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{ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
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2015-08-13 12:39:08 +02:00
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0x03300000, 0x0ff00000, "teq%p%c\t%16-19r, %o"},
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2015-03-24 07:08:08 +01:00
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{ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
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2015-08-13 12:39:08 +02:00
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0x01300000, 0x0ff00010, "teq%p%c\t%16-19r, %o"},
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2015-03-24 07:08:08 +01:00
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{ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
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2015-08-13 12:39:08 +02:00
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0x01300010, 0x0ff00010, "teq%p%c\t%16-19R, %o"},
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2015-03-24 07:08:08 +01:00
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{ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
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0x03400000, 0x0fe00000, "cmp%p%c\t%16-19r, %o"},
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{ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
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0x01400000, 0x0fe00010, "cmp%p%c\t%16-19r, %o"},
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{ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
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0x01400010, 0x0fe00090, "cmp%p%c\t%16-19R, %o"},
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{ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
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0x03600000, 0x0fe00000, "cmn%p%c\t%16-19r, %o"},
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{ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
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0x01600000, 0x0fe00010, "cmn%p%c\t%16-19r, %o"},
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{ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
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0x01600010, 0x0fe00090, "cmn%p%c\t%16-19R, %o"},
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{ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
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0x03800000, 0x0fe00000, "orr%20's%c\t%12-15r, %16-19r, %o"},
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{ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
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0x01800000, 0x0fe00010, "orr%20's%c\t%12-15r, %16-19r, %o"},
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{ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
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0x01800010, 0x0fe00090, "orr%20's%c\t%12-15R, %16-19R, %o"},
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{ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
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0x03a00000, 0x0fef0000, "mov%20's%c\t%12-15r, %o"},
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{ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
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0x01a00000, 0x0def0ff0, "mov%20's%c\t%12-15r, %0-3r"},
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{ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
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0x01a00000, 0x0def0060, "lsl%20's%c\t%12-15R, %q"},
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{ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
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0x01a00020, 0x0def0060, "lsr%20's%c\t%12-15R, %q"},
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{ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
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0x01a00040, 0x0def0060, "asr%20's%c\t%12-15R, %q"},
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{ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
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0x01a00060, 0x0def0ff0, "rrx%20's%c\t%12-15r, %0-3r"},
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{ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
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0x01a00060, 0x0def0060, "ror%20's%c\t%12-15R, %q"},
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{ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
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0x03c00000, 0x0fe00000, "bic%20's%c\t%12-15r, %16-19r, %o"},
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{ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
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0x01c00000, 0x0fe00010, "bic%20's%c\t%12-15r, %16-19r, %o"},
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{ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
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0x01c00010, 0x0fe00090, "bic%20's%c\t%12-15R, %16-19R, %o"},
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{ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
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0x03e00000, 0x0fe00000, "mvn%20's%c\t%12-15r, %o"},
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{ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
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0x01e00000, 0x0fe00010, "mvn%20's%c\t%12-15r, %o"},
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{ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
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0x01e00010, 0x0fe00090, "mvn%20's%c\t%12-15R, %o"},
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{ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
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0x06000010, 0x0e000010, UNDEFINED_INSTRUCTION},
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{ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
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0x049d0004, 0x0fff0fff, "pop%c\t{%12-15r}\t\t; (ldr%c %12-15r, %a)"},
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{ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
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0x04500000, 0x0c500000, "ldrb%t%c\t%12-15R, %a"},
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{ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
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0x04300000, 0x0d700000, "ldrt%c\t%12-15R, %a"},
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{ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
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0x04100000, 0x0c500000, "ldr%c\t%12-15r, %a"},
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{ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
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0x092d0001, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
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{ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
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0x092d0002, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
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{ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
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0x092d0004, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
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|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
|
|
|
|
|
|
0x092d0008, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
|
|
|
|
|
|
0x092d0010, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
|
|
|
|
|
|
0x092d0020, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
|
|
|
|
|
|
0x092d0040, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
|
|
|
|
|
|
0x092d0080, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
|
|
|
|
|
|
0x092d0100, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
|
|
|
|
|
|
0x092d0200, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
|
|
|
|
|
|
0x092d0400, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
|
|
|
|
|
|
0x092d0800, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
|
|
|
|
|
|
0x092d1000, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
|
|
|
|
|
|
0x092d2000, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
|
|
|
|
|
|
0x092d4000, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
|
|
|
|
|
|
0x092d8000, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
|
|
|
|
|
|
0x092d0000, 0x0fff0000, "push%c\t%m"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
|
|
|
|
|
|
0x08800000, 0x0ff00000, "stm%c\t%16-19R%21'!, %m%22'^"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
|
|
|
|
|
|
0x08000000, 0x0e100000, "stm%23?id%24?ba%c\t%16-19R%21'!, %m%22'^"},
|
|
|
|
|
|
|
|
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
|
|
|
|
|
|
0x08bd0001, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
|
|
|
|
|
|
0x08bd0002, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
|
|
|
|
|
|
0x08bd0004, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
|
|
|
|
|
|
0x08bd0008, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
|
|
|
|
|
|
0x08bd0010, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
|
|
|
|
|
|
0x08bd0020, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
|
|
|
|
|
|
0x08bd0040, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
|
|
|
|
|
|
0x08bd0080, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
|
|
|
|
|
|
0x08bd0100, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
|
|
|
|
|
|
0x08bd0200, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
|
|
|
|
|
|
0x08bd0400, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
|
|
|
|
|
|
0x08bd0800, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
|
|
|
|
|
|
0x08bd1000, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
|
|
|
|
|
|
0x08bd2000, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
|
|
|
|
|
|
0x08bd4000, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
|
|
|
|
|
|
0x08bd8000, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
|
|
|
|
|
|
0x08bd0000, 0x0fff0000, "pop%c\t%m"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
|
|
|
|
|
|
0x08900000, 0x0f900000, "ldm%c\t%16-19R%21'!, %m%22'^"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
|
|
|
|
|
|
0x08100000, 0x0e100000, "ldm%23?id%24?ba%c\t%16-19R%21'!, %m%22'^"},
|
|
|
|
|
|
|
|
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
|
|
|
|
|
|
0x0a000000, 0x0e000000, "b%24'l%c\t%b"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
|
|
|
|
|
|
0x0f000000, 0x0f000000, "svc%c\t%0-23x"},
|
2005-09-02 Paul Brook <paul@codesourcery.com>
bfd/
* libbdf.h: Regenerate.
* bfd-in2.h: Regenerate.
* reloc.c: Add BFD_RELOC_ARM_T32_CP_OFF_IMM and
BFD_RELOC_ARM_T32_CP_OFF_IMM_S2.
gas/
* config/tc-arm.c (encode_arm_cp_address): Use
BFD_RELOC_ARM_T32_CP_OFF_IMM in thumb mode.
(do_iwmmxt_wldstbh): Use BFD_RELOC_ARM_T32_CP_OFF_IMM_S2 in thumb
mode.
(md_assemble): Only allow coprocessor instructions when Thumb-2 is
available.
(cCE, cC3): Define.
(insns): Use them for coprocessor instructions.
(md_pcrel_from_section): Handle BFD_RELOC_ARM_T32_CP_OFF_IMM.
(get_thumb32_insn): New function.
(put_thumb32_insn): New function.
(md_apply_fix): Handle BFD_RELOC_ARM_T32_CP_OFF_IMM and
BFD_RELOC_ARM_T32_CP_OFF_IMM_S2.
gas/testsuite/
* gas/arm/vfp-bad_t2.d, gas/arm/vfp-bad_t2.l, arm/vfp-bad_t2.s,
gas/arm/vfp1_t2.d, gas/arm/vfp1_t2.s, gas/arm/vfp1xD_t2.d,
gas/arm/vfp1xD_t2.s, gas/arm/vfp2_t2.d, gas/arm/vfp2_t2.s): New files.
opcodes/
* arm-dis.c (coprocessor_opcodes): New.
(arm_opcodes, thumb32_opcodes): Remove coprocessor insns.
(print_insn_coprocessor): New function.
(print_insn_arm): Use print_insn_coprocessor. Remove coprocessor
format characters.
(print_insn_thumb32): Use print_insn_coprocessor.
2005-09-02 15:12:45 +02:00
|
|
|
|
|
|
|
|
|
|
/* The rest. */
|
2015-08-13 12:39:08 +02:00
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V7),
|
|
|
|
|
|
0x03200000, 0x0fff00ff, "nop%c\t{%0-7d}" UNPREDICTABLE_INSTRUCTION},
|
2015-03-24 07:08:08 +01:00
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
|
|
|
|
|
|
0x00000000, 0x00000000, UNDEFINED_INSTRUCTION},
|
|
|
|
|
|
{ARM_FEATURE_CORE_LOW (0),
|
|
|
|
|
|
0x00000000, 0x00000000, 0}
|
2005-09-02 Paul Brook <paul@codesourcery.com>
bfd/
* libbdf.h: Regenerate.
* bfd-in2.h: Regenerate.
* reloc.c: Add BFD_RELOC_ARM_T32_CP_OFF_IMM and
BFD_RELOC_ARM_T32_CP_OFF_IMM_S2.
gas/
* config/tc-arm.c (encode_arm_cp_address): Use
BFD_RELOC_ARM_T32_CP_OFF_IMM in thumb mode.
(do_iwmmxt_wldstbh): Use BFD_RELOC_ARM_T32_CP_OFF_IMM_S2 in thumb
mode.
(md_assemble): Only allow coprocessor instructions when Thumb-2 is
available.
(cCE, cC3): Define.
(insns): Use them for coprocessor instructions.
(md_pcrel_from_section): Handle BFD_RELOC_ARM_T32_CP_OFF_IMM.
(get_thumb32_insn): New function.
(put_thumb32_insn): New function.
(md_apply_fix): Handle BFD_RELOC_ARM_T32_CP_OFF_IMM and
BFD_RELOC_ARM_T32_CP_OFF_IMM_S2.
gas/testsuite/
* gas/arm/vfp-bad_t2.d, gas/arm/vfp-bad_t2.l, arm/vfp-bad_t2.s,
gas/arm/vfp1_t2.d, gas/arm/vfp1_t2.s, gas/arm/vfp1xD_t2.d,
gas/arm/vfp1xD_t2.s, gas/arm/vfp2_t2.d, gas/arm/vfp2_t2.s): New files.
opcodes/
* arm-dis.c (coprocessor_opcodes): New.
(arm_opcodes, thumb32_opcodes): Remove coprocessor insns.
(print_insn_coprocessor): New function.
(print_insn_arm): Use print_insn_coprocessor. Remove coprocessor
format characters.
(print_insn_thumb32): Use print_insn_coprocessor.
2005-09-02 15:12:45 +02:00
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
|
|
/* print_insn_thumb16 recognizes the following format control codes:
|
|
|
|
|
|
|
|
|
|
|
|
%S print Thumb register (bits 3..5 as high number if bit 6 set)
|
|
|
|
|
|
%D print Thumb register (bits 0..2 as high number if bit 7 set)
|
|
|
|
|
|
%<bitfield>I print bitfield as a signed decimal
|
|
|
|
|
|
(top bit of range being the sign bit)
|
|
|
|
|
|
%N print Thumb register mask (with LR)
|
|
|
|
|
|
%O print Thumb register mask (with PC)
|
|
|
|
|
|
%M print Thumb register mask
|
|
|
|
|
|
%b print CZB's 6-bit unsigned branch destination
|
|
|
|
|
|
%s print Thumb right-shift immediate (6..10; 0 == 32).
|
2006-06-07 16:08:19 +02:00
|
|
|
|
%c print the condition code
|
|
|
|
|
|
%C print the condition code, or "s" if not conditional
|
|
|
|
|
|
%x print warning if conditional an not at end of IT block"
|
|
|
|
|
|
%X print "\t; unpredictable <IT:code>" if conditional
|
|
|
|
|
|
%I print IT instruction suffix and operands
|
2010-05-11 19:36:33 +02:00
|
|
|
|
%W print Thumb Writeback indicator for LDMIA
|
2005-09-02 Paul Brook <paul@codesourcery.com>
bfd/
* libbdf.h: Regenerate.
* bfd-in2.h: Regenerate.
* reloc.c: Add BFD_RELOC_ARM_T32_CP_OFF_IMM and
BFD_RELOC_ARM_T32_CP_OFF_IMM_S2.
gas/
* config/tc-arm.c (encode_arm_cp_address): Use
BFD_RELOC_ARM_T32_CP_OFF_IMM in thumb mode.
(do_iwmmxt_wldstbh): Use BFD_RELOC_ARM_T32_CP_OFF_IMM_S2 in thumb
mode.
(md_assemble): Only allow coprocessor instructions when Thumb-2 is
available.
(cCE, cC3): Define.
(insns): Use them for coprocessor instructions.
(md_pcrel_from_section): Handle BFD_RELOC_ARM_T32_CP_OFF_IMM.
(get_thumb32_insn): New function.
(put_thumb32_insn): New function.
(md_apply_fix): Handle BFD_RELOC_ARM_T32_CP_OFF_IMM and
BFD_RELOC_ARM_T32_CP_OFF_IMM_S2.
gas/testsuite/
* gas/arm/vfp-bad_t2.d, gas/arm/vfp-bad_t2.l, arm/vfp-bad_t2.s,
gas/arm/vfp1_t2.d, gas/arm/vfp1_t2.s, gas/arm/vfp1xD_t2.d,
gas/arm/vfp1xD_t2.s, gas/arm/vfp2_t2.d, gas/arm/vfp2_t2.s): New files.
opcodes/
* arm-dis.c (coprocessor_opcodes): New.
(arm_opcodes, thumb32_opcodes): Remove coprocessor insns.
(print_insn_coprocessor): New function.
(print_insn_arm): Use print_insn_coprocessor. Remove coprocessor
format characters.
(print_insn_thumb32): Use print_insn_coprocessor.
2005-09-02 15:12:45 +02:00
|
|
|
|
%<bitfield>r print bitfield as an ARM register
|
|
|
|
|
|
%<bitfield>d print bitfield as a decimal
|
|
|
|
|
|
%<bitfield>H print (bitfield * 2) as a decimal
|
|
|
|
|
|
%<bitfield>W print (bitfield * 4) as a decimal
|
|
|
|
|
|
%<bitfield>a print (bitfield * 4) as a pc-rel offset + decoded symbol
|
|
|
|
|
|
%<bitfield>B print Thumb branch destination (signed displacement)
|
|
|
|
|
|
%<bitfield>c print bitfield as a condition code
|
|
|
|
|
|
%<bitnum>'c print specified char iff bit is one
|
|
|
|
|
|
%<bitnum>?ab print a if bit is one else print b. */
|
|
|
|
|
|
|
|
|
|
|
|
static const struct opcode16 thumb_opcodes[] =
|
|
|
|
|
|
{
|
|
|
|
|
|
/* Thumb instructions. */
|
|
|
|
|
|
|
2016-05-10 16:01:53 +02:00
|
|
|
|
/* ARMv8-M Security Extensions instructions. */
|
|
|
|
|
|
{ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M), 0x4784, 0xff87, "blxns\t%3-6r"},
|
2018-02-19 13:05:18 +01:00
|
|
|
|
{ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M), 0x4704, 0xff87, "bxns\t%3-6r"},
|
2016-05-10 16:01:53 +02:00
|
|
|
|
|
2012-08-24 10:01:18 +02:00
|
|
|
|
/* ARM V8 instructions. */
|
2015-03-24 07:08:08 +01:00
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xbf50, 0xffff, "sevl%c"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xba80, 0xffc0, "hlt\t%0-5x"},
|
2015-06-02 13:30:38 +02:00
|
|
|
|
{ARM_FEATURE_CORE_HIGH (ARM_EXT2_PAN), 0xb610, 0xfff7, "setpan\t#%3-3d"},
|
2012-08-24 10:01:18 +02:00
|
|
|
|
|
2005-09-02 Paul Brook <paul@codesourcery.com>
bfd/
* libbdf.h: Regenerate.
* bfd-in2.h: Regenerate.
* reloc.c: Add BFD_RELOC_ARM_T32_CP_OFF_IMM and
BFD_RELOC_ARM_T32_CP_OFF_IMM_S2.
gas/
* config/tc-arm.c (encode_arm_cp_address): Use
BFD_RELOC_ARM_T32_CP_OFF_IMM in thumb mode.
(do_iwmmxt_wldstbh): Use BFD_RELOC_ARM_T32_CP_OFF_IMM_S2 in thumb
mode.
(md_assemble): Only allow coprocessor instructions when Thumb-2 is
available.
(cCE, cC3): Define.
(insns): Use them for coprocessor instructions.
(md_pcrel_from_section): Handle BFD_RELOC_ARM_T32_CP_OFF_IMM.
(get_thumb32_insn): New function.
(put_thumb32_insn): New function.
(md_apply_fix): Handle BFD_RELOC_ARM_T32_CP_OFF_IMM and
BFD_RELOC_ARM_T32_CP_OFF_IMM_S2.
gas/testsuite/
* gas/arm/vfp-bad_t2.d, gas/arm/vfp-bad_t2.l, arm/vfp-bad_t2.s,
gas/arm/vfp1_t2.d, gas/arm/vfp1_t2.s, gas/arm/vfp1xD_t2.d,
gas/arm/vfp1xD_t2.s, gas/arm/vfp2_t2.d, gas/arm/vfp2_t2.s): New files.
opcodes/
* arm-dis.c (coprocessor_opcodes): New.
(arm_opcodes, thumb32_opcodes): Remove coprocessor insns.
(print_insn_coprocessor): New function.
(print_insn_arm): Use print_insn_coprocessor. Remove coprocessor
format characters.
(print_insn_thumb32): Use print_insn_coprocessor.
2005-09-02 15:12:45 +02:00
|
|
|
|
/* ARM V6K no-argument instructions. */
|
2015-03-24 07:08:08 +01:00
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf00, 0xffff, "nop%c"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf10, 0xffff, "yield%c"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf20, 0xffff, "wfe%c"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf30, 0xffff, "wfi%c"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf40, 0xffff, "sev%c"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf00, 0xff0f, "nop%c\t{%4-7d}"},
|
2005-09-02 Paul Brook <paul@codesourcery.com>
bfd/
* libbdf.h: Regenerate.
* bfd-in2.h: Regenerate.
* reloc.c: Add BFD_RELOC_ARM_T32_CP_OFF_IMM and
BFD_RELOC_ARM_T32_CP_OFF_IMM_S2.
gas/
* config/tc-arm.c (encode_arm_cp_address): Use
BFD_RELOC_ARM_T32_CP_OFF_IMM in thumb mode.
(do_iwmmxt_wldstbh): Use BFD_RELOC_ARM_T32_CP_OFF_IMM_S2 in thumb
mode.
(md_assemble): Only allow coprocessor instructions when Thumb-2 is
available.
(cCE, cC3): Define.
(insns): Use them for coprocessor instructions.
(md_pcrel_from_section): Handle BFD_RELOC_ARM_T32_CP_OFF_IMM.
(get_thumb32_insn): New function.
(put_thumb32_insn): New function.
(md_apply_fix): Handle BFD_RELOC_ARM_T32_CP_OFF_IMM and
BFD_RELOC_ARM_T32_CP_OFF_IMM_S2.
gas/testsuite/
* gas/arm/vfp-bad_t2.d, gas/arm/vfp-bad_t2.l, arm/vfp-bad_t2.s,
gas/arm/vfp1_t2.d, gas/arm/vfp1_t2.s, gas/arm/vfp1xD_t2.d,
gas/arm/vfp1xD_t2.s, gas/arm/vfp2_t2.d, gas/arm/vfp2_t2.s): New files.
opcodes/
* arm-dis.c (coprocessor_opcodes): New.
(arm_opcodes, thumb32_opcodes): Remove coprocessor insns.
(print_insn_coprocessor): New function.
(print_insn_arm): Use print_insn_coprocessor. Remove coprocessor
format characters.
(print_insn_thumb32): Use print_insn_coprocessor.
2005-09-02 15:12:45 +02:00
|
|
|
|
|
|
|
|
|
|
/* ARM V6T2 instructions. */
|
2015-12-24 10:26:08 +01:00
|
|
|
|
{ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
|
|
|
|
|
|
0xb900, 0xfd00, "cbnz\t%0-2r, %b%X"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
|
|
|
|
|
|
0xb100, 0xfd00, "cbz\t%0-2r, %b%X"},
|
2015-03-24 07:08:08 +01:00
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xbf00, 0xff00, "it%I%X"},
|
2005-09-02 Paul Brook <paul@codesourcery.com>
bfd/
* libbdf.h: Regenerate.
* bfd-in2.h: Regenerate.
* reloc.c: Add BFD_RELOC_ARM_T32_CP_OFF_IMM and
BFD_RELOC_ARM_T32_CP_OFF_IMM_S2.
gas/
* config/tc-arm.c (encode_arm_cp_address): Use
BFD_RELOC_ARM_T32_CP_OFF_IMM in thumb mode.
(do_iwmmxt_wldstbh): Use BFD_RELOC_ARM_T32_CP_OFF_IMM_S2 in thumb
mode.
(md_assemble): Only allow coprocessor instructions when Thumb-2 is
available.
(cCE, cC3): Define.
(insns): Use them for coprocessor instructions.
(md_pcrel_from_section): Handle BFD_RELOC_ARM_T32_CP_OFF_IMM.
(get_thumb32_insn): New function.
(put_thumb32_insn): New function.
(md_apply_fix): Handle BFD_RELOC_ARM_T32_CP_OFF_IMM and
BFD_RELOC_ARM_T32_CP_OFF_IMM_S2.
gas/testsuite/
* gas/arm/vfp-bad_t2.d, gas/arm/vfp-bad_t2.l, arm/vfp-bad_t2.s,
gas/arm/vfp1_t2.d, gas/arm/vfp1_t2.s, gas/arm/vfp1xD_t2.d,
gas/arm/vfp1xD_t2.s, gas/arm/vfp2_t2.d, gas/arm/vfp2_t2.s): New files.
opcodes/
* arm-dis.c (coprocessor_opcodes): New.
(arm_opcodes, thumb32_opcodes): Remove coprocessor insns.
(print_insn_coprocessor): New function.
(print_insn_arm): Use print_insn_coprocessor. Remove coprocessor
format characters.
(print_insn_thumb32): Use print_insn_coprocessor.
2005-09-02 15:12:45 +02:00
|
|
|
|
|
|
|
|
|
|
/* ARM V6. */
|
2015-03-24 07:08:08 +01:00
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb660, 0xfff8, "cpsie\t%2'a%1'i%0'f%X"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb670, 0xfff8, "cpsid\t%2'a%1'i%0'f%X"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0x4600, 0xffc0, "mov%c\t%0-2r, %3-5r"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xba00, 0xffc0, "rev%c\t%0-2r, %3-5r"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xba40, 0xffc0, "rev16%c\t%0-2r, %3-5r"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xbac0, 0xffc0, "revsh%c\t%0-2r, %3-5r"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb650, 0xfff7, "setend\t%3?ble%X"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb200, 0xffc0, "sxth%c\t%0-2r, %3-5r"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb240, 0xffc0, "sxtb%c\t%0-2r, %3-5r"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb280, 0xffc0, "uxth%c\t%0-2r, %3-5r"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb2c0, 0xffc0, "uxtb%c\t%0-2r, %3-5r"},
|
2005-09-02 Paul Brook <paul@codesourcery.com>
bfd/
* libbdf.h: Regenerate.
* bfd-in2.h: Regenerate.
* reloc.c: Add BFD_RELOC_ARM_T32_CP_OFF_IMM and
BFD_RELOC_ARM_T32_CP_OFF_IMM_S2.
gas/
* config/tc-arm.c (encode_arm_cp_address): Use
BFD_RELOC_ARM_T32_CP_OFF_IMM in thumb mode.
(do_iwmmxt_wldstbh): Use BFD_RELOC_ARM_T32_CP_OFF_IMM_S2 in thumb
mode.
(md_assemble): Only allow coprocessor instructions when Thumb-2 is
available.
(cCE, cC3): Define.
(insns): Use them for coprocessor instructions.
(md_pcrel_from_section): Handle BFD_RELOC_ARM_T32_CP_OFF_IMM.
(get_thumb32_insn): New function.
(put_thumb32_insn): New function.
(md_apply_fix): Handle BFD_RELOC_ARM_T32_CP_OFF_IMM and
BFD_RELOC_ARM_T32_CP_OFF_IMM_S2.
gas/testsuite/
* gas/arm/vfp-bad_t2.d, gas/arm/vfp-bad_t2.l, arm/vfp-bad_t2.s,
gas/arm/vfp1_t2.d, gas/arm/vfp1_t2.s, gas/arm/vfp1xD_t2.d,
gas/arm/vfp1xD_t2.s, gas/arm/vfp2_t2.d, gas/arm/vfp2_t2.s): New files.
opcodes/
* arm-dis.c (coprocessor_opcodes): New.
(arm_opcodes, thumb32_opcodes): Remove coprocessor insns.
(print_insn_coprocessor): New function.
(print_insn_arm): Use print_insn_coprocessor. Remove coprocessor
format characters.
(print_insn_thumb32): Use print_insn_coprocessor.
2005-09-02 15:12:45 +02:00
|
|
|
|
|
|
|
|
|
|
/* ARM V5 ISA extends Thumb. */
|
2015-03-24 07:08:08 +01:00
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V5T),
|
|
|
|
|
|
0xbe00, 0xff00, "bkpt\t%0-7x"}, /* Is always unconditional. */
|
2005-09-02 Paul Brook <paul@codesourcery.com>
bfd/
* libbdf.h: Regenerate.
* bfd-in2.h: Regenerate.
* reloc.c: Add BFD_RELOC_ARM_T32_CP_OFF_IMM and
BFD_RELOC_ARM_T32_CP_OFF_IMM_S2.
gas/
* config/tc-arm.c (encode_arm_cp_address): Use
BFD_RELOC_ARM_T32_CP_OFF_IMM in thumb mode.
(do_iwmmxt_wldstbh): Use BFD_RELOC_ARM_T32_CP_OFF_IMM_S2 in thumb
mode.
(md_assemble): Only allow coprocessor instructions when Thumb-2 is
available.
(cCE, cC3): Define.
(insns): Use them for coprocessor instructions.
(md_pcrel_from_section): Handle BFD_RELOC_ARM_T32_CP_OFF_IMM.
(get_thumb32_insn): New function.
(put_thumb32_insn): New function.
(md_apply_fix): Handle BFD_RELOC_ARM_T32_CP_OFF_IMM and
BFD_RELOC_ARM_T32_CP_OFF_IMM_S2.
gas/testsuite/
* gas/arm/vfp-bad_t2.d, gas/arm/vfp-bad_t2.l, arm/vfp-bad_t2.s,
gas/arm/vfp1_t2.d, gas/arm/vfp1_t2.s, gas/arm/vfp1xD_t2.d,
gas/arm/vfp1xD_t2.s, gas/arm/vfp2_t2.d, gas/arm/vfp2_t2.s): New files.
opcodes/
* arm-dis.c (coprocessor_opcodes): New.
(arm_opcodes, thumb32_opcodes): Remove coprocessor insns.
(print_insn_coprocessor): New function.
(print_insn_arm): Use print_insn_coprocessor. Remove coprocessor
format characters.
(print_insn_thumb32): Use print_insn_coprocessor.
2005-09-02 15:12:45 +02:00
|
|
|
|
/* This is BLX(2). BLX(1) is a 32-bit instruction. */
|
2015-03-24 07:08:08 +01:00
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V5T),
|
|
|
|
|
|
0x4780, 0xff87, "blx%c\t%3-6r%x"}, /* note: 4 bit register number. */
|
2005-09-02 Paul Brook <paul@codesourcery.com>
bfd/
* libbdf.h: Regenerate.
* bfd-in2.h: Regenerate.
* reloc.c: Add BFD_RELOC_ARM_T32_CP_OFF_IMM and
BFD_RELOC_ARM_T32_CP_OFF_IMM_S2.
gas/
* config/tc-arm.c (encode_arm_cp_address): Use
BFD_RELOC_ARM_T32_CP_OFF_IMM in thumb mode.
(do_iwmmxt_wldstbh): Use BFD_RELOC_ARM_T32_CP_OFF_IMM_S2 in thumb
mode.
(md_assemble): Only allow coprocessor instructions when Thumb-2 is
available.
(cCE, cC3): Define.
(insns): Use them for coprocessor instructions.
(md_pcrel_from_section): Handle BFD_RELOC_ARM_T32_CP_OFF_IMM.
(get_thumb32_insn): New function.
(put_thumb32_insn): New function.
(md_apply_fix): Handle BFD_RELOC_ARM_T32_CP_OFF_IMM and
BFD_RELOC_ARM_T32_CP_OFF_IMM_S2.
gas/testsuite/
* gas/arm/vfp-bad_t2.d, gas/arm/vfp-bad_t2.l, arm/vfp-bad_t2.s,
gas/arm/vfp1_t2.d, gas/arm/vfp1_t2.s, gas/arm/vfp1xD_t2.d,
gas/arm/vfp1xD_t2.s, gas/arm/vfp2_t2.d, gas/arm/vfp2_t2.s): New files.
opcodes/
* arm-dis.c (coprocessor_opcodes): New.
(arm_opcodes, thumb32_opcodes): Remove coprocessor insns.
(print_insn_coprocessor): New function.
(print_insn_arm): Use print_insn_coprocessor. Remove coprocessor
format characters.
(print_insn_thumb32): Use print_insn_coprocessor.
2005-09-02 15:12:45 +02:00
|
|
|
|
/* ARM V4T ISA (Thumb v1). */
|
2015-03-24 07:08:08 +01:00
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
|
|
|
|
|
|
0x46C0, 0xFFFF, "nop%c\t\t\t; (mov r8, r8)"},
|
2005-09-02 Paul Brook <paul@codesourcery.com>
bfd/
* libbdf.h: Regenerate.
* bfd-in2.h: Regenerate.
* reloc.c: Add BFD_RELOC_ARM_T32_CP_OFF_IMM and
BFD_RELOC_ARM_T32_CP_OFF_IMM_S2.
gas/
* config/tc-arm.c (encode_arm_cp_address): Use
BFD_RELOC_ARM_T32_CP_OFF_IMM in thumb mode.
(do_iwmmxt_wldstbh): Use BFD_RELOC_ARM_T32_CP_OFF_IMM_S2 in thumb
mode.
(md_assemble): Only allow coprocessor instructions when Thumb-2 is
available.
(cCE, cC3): Define.
(insns): Use them for coprocessor instructions.
(md_pcrel_from_section): Handle BFD_RELOC_ARM_T32_CP_OFF_IMM.
(get_thumb32_insn): New function.
(put_thumb32_insn): New function.
(md_apply_fix): Handle BFD_RELOC_ARM_T32_CP_OFF_IMM and
BFD_RELOC_ARM_T32_CP_OFF_IMM_S2.
gas/testsuite/
* gas/arm/vfp-bad_t2.d, gas/arm/vfp-bad_t2.l, arm/vfp-bad_t2.s,
gas/arm/vfp1_t2.d, gas/arm/vfp1_t2.s, gas/arm/vfp1xD_t2.d,
gas/arm/vfp1xD_t2.s, gas/arm/vfp2_t2.d, gas/arm/vfp2_t2.s): New files.
opcodes/
* arm-dis.c (coprocessor_opcodes): New.
(arm_opcodes, thumb32_opcodes): Remove coprocessor insns.
(print_insn_coprocessor): New function.
(print_insn_arm): Use print_insn_coprocessor. Remove coprocessor
format characters.
(print_insn_thumb32): Use print_insn_coprocessor.
2005-09-02 15:12:45 +02:00
|
|
|
|
/* Format 4. */
|
2015-03-24 07:08:08 +01:00
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4000, 0xFFC0, "and%C\t%0-2r, %3-5r"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4040, 0xFFC0, "eor%C\t%0-2r, %3-5r"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4080, 0xFFC0, "lsl%C\t%0-2r, %3-5r"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x40C0, 0xFFC0, "lsr%C\t%0-2r, %3-5r"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4100, 0xFFC0, "asr%C\t%0-2r, %3-5r"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4140, 0xFFC0, "adc%C\t%0-2r, %3-5r"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4180, 0xFFC0, "sbc%C\t%0-2r, %3-5r"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x41C0, 0xFFC0, "ror%C\t%0-2r, %3-5r"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4200, 0xFFC0, "tst%c\t%0-2r, %3-5r"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4240, 0xFFC0, "neg%C\t%0-2r, %3-5r"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4280, 0xFFC0, "cmp%c\t%0-2r, %3-5r"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x42C0, 0xFFC0, "cmn%c\t%0-2r, %3-5r"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4300, 0xFFC0, "orr%C\t%0-2r, %3-5r"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4340, 0xFFC0, "mul%C\t%0-2r, %3-5r"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4380, 0xFFC0, "bic%C\t%0-2r, %3-5r"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x43C0, 0xFFC0, "mvn%C\t%0-2r, %3-5r"},
|
2005-09-02 Paul Brook <paul@codesourcery.com>
bfd/
* libbdf.h: Regenerate.
* bfd-in2.h: Regenerate.
* reloc.c: Add BFD_RELOC_ARM_T32_CP_OFF_IMM and
BFD_RELOC_ARM_T32_CP_OFF_IMM_S2.
gas/
* config/tc-arm.c (encode_arm_cp_address): Use
BFD_RELOC_ARM_T32_CP_OFF_IMM in thumb mode.
(do_iwmmxt_wldstbh): Use BFD_RELOC_ARM_T32_CP_OFF_IMM_S2 in thumb
mode.
(md_assemble): Only allow coprocessor instructions when Thumb-2 is
available.
(cCE, cC3): Define.
(insns): Use them for coprocessor instructions.
(md_pcrel_from_section): Handle BFD_RELOC_ARM_T32_CP_OFF_IMM.
(get_thumb32_insn): New function.
(put_thumb32_insn): New function.
(md_apply_fix): Handle BFD_RELOC_ARM_T32_CP_OFF_IMM and
BFD_RELOC_ARM_T32_CP_OFF_IMM_S2.
gas/testsuite/
* gas/arm/vfp-bad_t2.d, gas/arm/vfp-bad_t2.l, arm/vfp-bad_t2.s,
gas/arm/vfp1_t2.d, gas/arm/vfp1_t2.s, gas/arm/vfp1xD_t2.d,
gas/arm/vfp1xD_t2.s, gas/arm/vfp2_t2.d, gas/arm/vfp2_t2.s): New files.
opcodes/
* arm-dis.c (coprocessor_opcodes): New.
(arm_opcodes, thumb32_opcodes): Remove coprocessor insns.
(print_insn_coprocessor): New function.
(print_insn_arm): Use print_insn_coprocessor. Remove coprocessor
format characters.
(print_insn_thumb32): Use print_insn_coprocessor.
2005-09-02 15:12:45 +02:00
|
|
|
|
/* format 13 */
|
2015-03-24 07:08:08 +01:00
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xB000, 0xFF80, "add%c\tsp, #%0-6W"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xB080, 0xFF80, "sub%c\tsp, #%0-6W"},
|
2005-09-02 Paul Brook <paul@codesourcery.com>
bfd/
* libbdf.h: Regenerate.
* bfd-in2.h: Regenerate.
* reloc.c: Add BFD_RELOC_ARM_T32_CP_OFF_IMM and
BFD_RELOC_ARM_T32_CP_OFF_IMM_S2.
gas/
* config/tc-arm.c (encode_arm_cp_address): Use
BFD_RELOC_ARM_T32_CP_OFF_IMM in thumb mode.
(do_iwmmxt_wldstbh): Use BFD_RELOC_ARM_T32_CP_OFF_IMM_S2 in thumb
mode.
(md_assemble): Only allow coprocessor instructions when Thumb-2 is
available.
(cCE, cC3): Define.
(insns): Use them for coprocessor instructions.
(md_pcrel_from_section): Handle BFD_RELOC_ARM_T32_CP_OFF_IMM.
(get_thumb32_insn): New function.
(put_thumb32_insn): New function.
(md_apply_fix): Handle BFD_RELOC_ARM_T32_CP_OFF_IMM and
BFD_RELOC_ARM_T32_CP_OFF_IMM_S2.
gas/testsuite/
* gas/arm/vfp-bad_t2.d, gas/arm/vfp-bad_t2.l, arm/vfp-bad_t2.s,
gas/arm/vfp1_t2.d, gas/arm/vfp1_t2.s, gas/arm/vfp1xD_t2.d,
gas/arm/vfp1xD_t2.s, gas/arm/vfp2_t2.d, gas/arm/vfp2_t2.s): New files.
opcodes/
* arm-dis.c (coprocessor_opcodes): New.
(arm_opcodes, thumb32_opcodes): Remove coprocessor insns.
(print_insn_coprocessor): New function.
(print_insn_arm): Use print_insn_coprocessor. Remove coprocessor
format characters.
(print_insn_thumb32): Use print_insn_coprocessor.
2005-09-02 15:12:45 +02:00
|
|
|
|
/* format 5 */
|
2015-03-24 07:08:08 +01:00
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4700, 0xFF80, "bx%c\t%S%x"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4400, 0xFF00, "add%c\t%D, %S"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4500, 0xFF00, "cmp%c\t%D, %S"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4600, 0xFF00, "mov%c\t%D, %S"},
|
2005-09-02 Paul Brook <paul@codesourcery.com>
bfd/
* libbdf.h: Regenerate.
* bfd-in2.h: Regenerate.
* reloc.c: Add BFD_RELOC_ARM_T32_CP_OFF_IMM and
BFD_RELOC_ARM_T32_CP_OFF_IMM_S2.
gas/
* config/tc-arm.c (encode_arm_cp_address): Use
BFD_RELOC_ARM_T32_CP_OFF_IMM in thumb mode.
(do_iwmmxt_wldstbh): Use BFD_RELOC_ARM_T32_CP_OFF_IMM_S2 in thumb
mode.
(md_assemble): Only allow coprocessor instructions when Thumb-2 is
available.
(cCE, cC3): Define.
(insns): Use them for coprocessor instructions.
(md_pcrel_from_section): Handle BFD_RELOC_ARM_T32_CP_OFF_IMM.
(get_thumb32_insn): New function.
(put_thumb32_insn): New function.
(md_apply_fix): Handle BFD_RELOC_ARM_T32_CP_OFF_IMM and
BFD_RELOC_ARM_T32_CP_OFF_IMM_S2.
gas/testsuite/
* gas/arm/vfp-bad_t2.d, gas/arm/vfp-bad_t2.l, arm/vfp-bad_t2.s,
gas/arm/vfp1_t2.d, gas/arm/vfp1_t2.s, gas/arm/vfp1xD_t2.d,
gas/arm/vfp1xD_t2.s, gas/arm/vfp2_t2.d, gas/arm/vfp2_t2.s): New files.
opcodes/
* arm-dis.c (coprocessor_opcodes): New.
(arm_opcodes, thumb32_opcodes): Remove coprocessor insns.
(print_insn_coprocessor): New function.
(print_insn_arm): Use print_insn_coprocessor. Remove coprocessor
format characters.
(print_insn_thumb32): Use print_insn_coprocessor.
2005-09-02 15:12:45 +02:00
|
|
|
|
/* format 14 */
|
2015-03-24 07:08:08 +01:00
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xB400, 0xFE00, "push%c\t%N"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xBC00, 0xFE00, "pop%c\t%O"},
|
2005-09-02 Paul Brook <paul@codesourcery.com>
bfd/
* libbdf.h: Regenerate.
* bfd-in2.h: Regenerate.
* reloc.c: Add BFD_RELOC_ARM_T32_CP_OFF_IMM and
BFD_RELOC_ARM_T32_CP_OFF_IMM_S2.
gas/
* config/tc-arm.c (encode_arm_cp_address): Use
BFD_RELOC_ARM_T32_CP_OFF_IMM in thumb mode.
(do_iwmmxt_wldstbh): Use BFD_RELOC_ARM_T32_CP_OFF_IMM_S2 in thumb
mode.
(md_assemble): Only allow coprocessor instructions when Thumb-2 is
available.
(cCE, cC3): Define.
(insns): Use them for coprocessor instructions.
(md_pcrel_from_section): Handle BFD_RELOC_ARM_T32_CP_OFF_IMM.
(get_thumb32_insn): New function.
(put_thumb32_insn): New function.
(md_apply_fix): Handle BFD_RELOC_ARM_T32_CP_OFF_IMM and
BFD_RELOC_ARM_T32_CP_OFF_IMM_S2.
gas/testsuite/
* gas/arm/vfp-bad_t2.d, gas/arm/vfp-bad_t2.l, arm/vfp-bad_t2.s,
gas/arm/vfp1_t2.d, gas/arm/vfp1_t2.s, gas/arm/vfp1xD_t2.d,
gas/arm/vfp1xD_t2.s, gas/arm/vfp2_t2.d, gas/arm/vfp2_t2.s): New files.
opcodes/
* arm-dis.c (coprocessor_opcodes): New.
(arm_opcodes, thumb32_opcodes): Remove coprocessor insns.
(print_insn_coprocessor): New function.
(print_insn_arm): Use print_insn_coprocessor. Remove coprocessor
format characters.
(print_insn_thumb32): Use print_insn_coprocessor.
2005-09-02 15:12:45 +02:00
|
|
|
|
/* format 2 */
|
2015-03-24 07:08:08 +01:00
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
|
|
|
|
|
|
0x1800, 0xFE00, "add%C\t%0-2r, %3-5r, %6-8r"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
|
|
|
|
|
|
0x1A00, 0xFE00, "sub%C\t%0-2r, %3-5r, %6-8r"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
|
|
|
|
|
|
0x1C00, 0xFE00, "add%C\t%0-2r, %3-5r, #%6-8d"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
|
|
|
|
|
|
0x1E00, 0xFE00, "sub%C\t%0-2r, %3-5r, #%6-8d"},
|
2005-09-02 Paul Brook <paul@codesourcery.com>
bfd/
* libbdf.h: Regenerate.
* bfd-in2.h: Regenerate.
* reloc.c: Add BFD_RELOC_ARM_T32_CP_OFF_IMM and
BFD_RELOC_ARM_T32_CP_OFF_IMM_S2.
gas/
* config/tc-arm.c (encode_arm_cp_address): Use
BFD_RELOC_ARM_T32_CP_OFF_IMM in thumb mode.
(do_iwmmxt_wldstbh): Use BFD_RELOC_ARM_T32_CP_OFF_IMM_S2 in thumb
mode.
(md_assemble): Only allow coprocessor instructions when Thumb-2 is
available.
(cCE, cC3): Define.
(insns): Use them for coprocessor instructions.
(md_pcrel_from_section): Handle BFD_RELOC_ARM_T32_CP_OFF_IMM.
(get_thumb32_insn): New function.
(put_thumb32_insn): New function.
(md_apply_fix): Handle BFD_RELOC_ARM_T32_CP_OFF_IMM and
BFD_RELOC_ARM_T32_CP_OFF_IMM_S2.
gas/testsuite/
* gas/arm/vfp-bad_t2.d, gas/arm/vfp-bad_t2.l, arm/vfp-bad_t2.s,
gas/arm/vfp1_t2.d, gas/arm/vfp1_t2.s, gas/arm/vfp1xD_t2.d,
gas/arm/vfp1xD_t2.s, gas/arm/vfp2_t2.d, gas/arm/vfp2_t2.s): New files.
opcodes/
* arm-dis.c (coprocessor_opcodes): New.
(arm_opcodes, thumb32_opcodes): Remove coprocessor insns.
(print_insn_coprocessor): New function.
(print_insn_arm): Use print_insn_coprocessor. Remove coprocessor
format characters.
(print_insn_thumb32): Use print_insn_coprocessor.
2005-09-02 15:12:45 +02:00
|
|
|
|
/* format 8 */
|
2015-03-24 07:08:08 +01:00
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
|
|
|
|
|
|
0x5200, 0xFE00, "strh%c\t%0-2r, [%3-5r, %6-8r]"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
|
|
|
|
|
|
0x5A00, 0xFE00, "ldrh%c\t%0-2r, [%3-5r, %6-8r]"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
|
|
|
|
|
|
0x5600, 0xF600, "ldrs%11?hb%c\t%0-2r, [%3-5r, %6-8r]"},
|
2005-09-02 Paul Brook <paul@codesourcery.com>
bfd/
* libbdf.h: Regenerate.
* bfd-in2.h: Regenerate.
* reloc.c: Add BFD_RELOC_ARM_T32_CP_OFF_IMM and
BFD_RELOC_ARM_T32_CP_OFF_IMM_S2.
gas/
* config/tc-arm.c (encode_arm_cp_address): Use
BFD_RELOC_ARM_T32_CP_OFF_IMM in thumb mode.
(do_iwmmxt_wldstbh): Use BFD_RELOC_ARM_T32_CP_OFF_IMM_S2 in thumb
mode.
(md_assemble): Only allow coprocessor instructions when Thumb-2 is
available.
(cCE, cC3): Define.
(insns): Use them for coprocessor instructions.
(md_pcrel_from_section): Handle BFD_RELOC_ARM_T32_CP_OFF_IMM.
(get_thumb32_insn): New function.
(put_thumb32_insn): New function.
(md_apply_fix): Handle BFD_RELOC_ARM_T32_CP_OFF_IMM and
BFD_RELOC_ARM_T32_CP_OFF_IMM_S2.
gas/testsuite/
* gas/arm/vfp-bad_t2.d, gas/arm/vfp-bad_t2.l, arm/vfp-bad_t2.s,
gas/arm/vfp1_t2.d, gas/arm/vfp1_t2.s, gas/arm/vfp1xD_t2.d,
gas/arm/vfp1xD_t2.s, gas/arm/vfp2_t2.d, gas/arm/vfp2_t2.s): New files.
opcodes/
* arm-dis.c (coprocessor_opcodes): New.
(arm_opcodes, thumb32_opcodes): Remove coprocessor insns.
(print_insn_coprocessor): New function.
(print_insn_arm): Use print_insn_coprocessor. Remove coprocessor
format characters.
(print_insn_thumb32): Use print_insn_coprocessor.
2005-09-02 15:12:45 +02:00
|
|
|
|
/* format 7 */
|
2015-03-24 07:08:08 +01:00
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
|
|
|
|
|
|
0x5000, 0xFA00, "str%10'b%c\t%0-2r, [%3-5r, %6-8r]"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
|
|
|
|
|
|
0x5800, 0xFA00, "ldr%10'b%c\t%0-2r, [%3-5r, %6-8r]"},
|
2005-09-02 Paul Brook <paul@codesourcery.com>
bfd/
* libbdf.h: Regenerate.
* bfd-in2.h: Regenerate.
* reloc.c: Add BFD_RELOC_ARM_T32_CP_OFF_IMM and
BFD_RELOC_ARM_T32_CP_OFF_IMM_S2.
gas/
* config/tc-arm.c (encode_arm_cp_address): Use
BFD_RELOC_ARM_T32_CP_OFF_IMM in thumb mode.
(do_iwmmxt_wldstbh): Use BFD_RELOC_ARM_T32_CP_OFF_IMM_S2 in thumb
mode.
(md_assemble): Only allow coprocessor instructions when Thumb-2 is
available.
(cCE, cC3): Define.
(insns): Use them for coprocessor instructions.
(md_pcrel_from_section): Handle BFD_RELOC_ARM_T32_CP_OFF_IMM.
(get_thumb32_insn): New function.
(put_thumb32_insn): New function.
(md_apply_fix): Handle BFD_RELOC_ARM_T32_CP_OFF_IMM and
BFD_RELOC_ARM_T32_CP_OFF_IMM_S2.
gas/testsuite/
* gas/arm/vfp-bad_t2.d, gas/arm/vfp-bad_t2.l, arm/vfp-bad_t2.s,
gas/arm/vfp1_t2.d, gas/arm/vfp1_t2.s, gas/arm/vfp1xD_t2.d,
gas/arm/vfp1xD_t2.s, gas/arm/vfp2_t2.d, gas/arm/vfp2_t2.s): New files.
opcodes/
* arm-dis.c (coprocessor_opcodes): New.
(arm_opcodes, thumb32_opcodes): Remove coprocessor insns.
(print_insn_coprocessor): New function.
(print_insn_arm): Use print_insn_coprocessor. Remove coprocessor
format characters.
(print_insn_thumb32): Use print_insn_coprocessor.
2005-09-02 15:12:45 +02:00
|
|
|
|
/* format 1 */
|
2015-03-24 07:08:08 +01:00
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x0000, 0xFFC0, "mov%C\t%0-2r, %3-5r"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
|
|
|
|
|
|
0x0000, 0xF800, "lsl%C\t%0-2r, %3-5r, #%6-10d"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x0800, 0xF800, "lsr%C\t%0-2r, %3-5r, %s"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x1000, 0xF800, "asr%C\t%0-2r, %3-5r, %s"},
|
2005-09-02 Paul Brook <paul@codesourcery.com>
bfd/
* libbdf.h: Regenerate.
* bfd-in2.h: Regenerate.
* reloc.c: Add BFD_RELOC_ARM_T32_CP_OFF_IMM and
BFD_RELOC_ARM_T32_CP_OFF_IMM_S2.
gas/
* config/tc-arm.c (encode_arm_cp_address): Use
BFD_RELOC_ARM_T32_CP_OFF_IMM in thumb mode.
(do_iwmmxt_wldstbh): Use BFD_RELOC_ARM_T32_CP_OFF_IMM_S2 in thumb
mode.
(md_assemble): Only allow coprocessor instructions when Thumb-2 is
available.
(cCE, cC3): Define.
(insns): Use them for coprocessor instructions.
(md_pcrel_from_section): Handle BFD_RELOC_ARM_T32_CP_OFF_IMM.
(get_thumb32_insn): New function.
(put_thumb32_insn): New function.
(md_apply_fix): Handle BFD_RELOC_ARM_T32_CP_OFF_IMM and
BFD_RELOC_ARM_T32_CP_OFF_IMM_S2.
gas/testsuite/
* gas/arm/vfp-bad_t2.d, gas/arm/vfp-bad_t2.l, arm/vfp-bad_t2.s,
gas/arm/vfp1_t2.d, gas/arm/vfp1_t2.s, gas/arm/vfp1xD_t2.d,
gas/arm/vfp1xD_t2.s, gas/arm/vfp2_t2.d, gas/arm/vfp2_t2.s): New files.
opcodes/
* arm-dis.c (coprocessor_opcodes): New.
(arm_opcodes, thumb32_opcodes): Remove coprocessor insns.
(print_insn_coprocessor): New function.
(print_insn_arm): Use print_insn_coprocessor. Remove coprocessor
format characters.
(print_insn_thumb32): Use print_insn_coprocessor.
2005-09-02 15:12:45 +02:00
|
|
|
|
/* format 3 */
|
2015-03-24 07:08:08 +01:00
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x2000, 0xF800, "mov%C\t%8-10r, #%0-7d"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x2800, 0xF800, "cmp%c\t%8-10r, #%0-7d"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x3000, 0xF800, "add%C\t%8-10r, #%0-7d"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x3800, 0xF800, "sub%C\t%8-10r, #%0-7d"},
|
2005-09-02 Paul Brook <paul@codesourcery.com>
bfd/
* libbdf.h: Regenerate.
* bfd-in2.h: Regenerate.
* reloc.c: Add BFD_RELOC_ARM_T32_CP_OFF_IMM and
BFD_RELOC_ARM_T32_CP_OFF_IMM_S2.
gas/
* config/tc-arm.c (encode_arm_cp_address): Use
BFD_RELOC_ARM_T32_CP_OFF_IMM in thumb mode.
(do_iwmmxt_wldstbh): Use BFD_RELOC_ARM_T32_CP_OFF_IMM_S2 in thumb
mode.
(md_assemble): Only allow coprocessor instructions when Thumb-2 is
available.
(cCE, cC3): Define.
(insns): Use them for coprocessor instructions.
(md_pcrel_from_section): Handle BFD_RELOC_ARM_T32_CP_OFF_IMM.
(get_thumb32_insn): New function.
(put_thumb32_insn): New function.
(md_apply_fix): Handle BFD_RELOC_ARM_T32_CP_OFF_IMM and
BFD_RELOC_ARM_T32_CP_OFF_IMM_S2.
gas/testsuite/
* gas/arm/vfp-bad_t2.d, gas/arm/vfp-bad_t2.l, arm/vfp-bad_t2.s,
gas/arm/vfp1_t2.d, gas/arm/vfp1_t2.s, gas/arm/vfp1xD_t2.d,
gas/arm/vfp1xD_t2.s, gas/arm/vfp2_t2.d, gas/arm/vfp2_t2.s): New files.
opcodes/
* arm-dis.c (coprocessor_opcodes): New.
(arm_opcodes, thumb32_opcodes): Remove coprocessor insns.
(print_insn_coprocessor): New function.
(print_insn_arm): Use print_insn_coprocessor. Remove coprocessor
format characters.
(print_insn_thumb32): Use print_insn_coprocessor.
2005-09-02 15:12:45 +02:00
|
|
|
|
/* format 6 */
|
2015-03-24 07:08:08 +01:00
|
|
|
|
/* TODO: Disassemble PC relative "LDR rD,=<symbolic>" */
|
|
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
|
|
|
|
|
|
0x4800, 0xF800,
|
|
|
|
|
|
"ldr%c\t%8-10r, [pc, #%0-7W]\t; (%0-7a)"},
|
2005-09-02 Paul Brook <paul@codesourcery.com>
bfd/
* libbdf.h: Regenerate.
* bfd-in2.h: Regenerate.
* reloc.c: Add BFD_RELOC_ARM_T32_CP_OFF_IMM and
BFD_RELOC_ARM_T32_CP_OFF_IMM_S2.
gas/
* config/tc-arm.c (encode_arm_cp_address): Use
BFD_RELOC_ARM_T32_CP_OFF_IMM in thumb mode.
(do_iwmmxt_wldstbh): Use BFD_RELOC_ARM_T32_CP_OFF_IMM_S2 in thumb
mode.
(md_assemble): Only allow coprocessor instructions when Thumb-2 is
available.
(cCE, cC3): Define.
(insns): Use them for coprocessor instructions.
(md_pcrel_from_section): Handle BFD_RELOC_ARM_T32_CP_OFF_IMM.
(get_thumb32_insn): New function.
(put_thumb32_insn): New function.
(md_apply_fix): Handle BFD_RELOC_ARM_T32_CP_OFF_IMM and
BFD_RELOC_ARM_T32_CP_OFF_IMM_S2.
gas/testsuite/
* gas/arm/vfp-bad_t2.d, gas/arm/vfp-bad_t2.l, arm/vfp-bad_t2.s,
gas/arm/vfp1_t2.d, gas/arm/vfp1_t2.s, gas/arm/vfp1xD_t2.d,
gas/arm/vfp1xD_t2.s, gas/arm/vfp2_t2.d, gas/arm/vfp2_t2.s): New files.
opcodes/
* arm-dis.c (coprocessor_opcodes): New.
(arm_opcodes, thumb32_opcodes): Remove coprocessor insns.
(print_insn_coprocessor): New function.
(print_insn_arm): Use print_insn_coprocessor. Remove coprocessor
format characters.
(print_insn_thumb32): Use print_insn_coprocessor.
2005-09-02 15:12:45 +02:00
|
|
|
|
/* format 9 */
|
2015-03-24 07:08:08 +01:00
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
|
|
|
|
|
|
0x6000, 0xF800, "str%c\t%0-2r, [%3-5r, #%6-10W]"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
|
|
|
|
|
|
0x6800, 0xF800, "ldr%c\t%0-2r, [%3-5r, #%6-10W]"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
|
|
|
|
|
|
0x7000, 0xF800, "strb%c\t%0-2r, [%3-5r, #%6-10d]"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
|
|
|
|
|
|
0x7800, 0xF800, "ldrb%c\t%0-2r, [%3-5r, #%6-10d]"},
|
2005-09-02 Paul Brook <paul@codesourcery.com>
bfd/
* libbdf.h: Regenerate.
* bfd-in2.h: Regenerate.
* reloc.c: Add BFD_RELOC_ARM_T32_CP_OFF_IMM and
BFD_RELOC_ARM_T32_CP_OFF_IMM_S2.
gas/
* config/tc-arm.c (encode_arm_cp_address): Use
BFD_RELOC_ARM_T32_CP_OFF_IMM in thumb mode.
(do_iwmmxt_wldstbh): Use BFD_RELOC_ARM_T32_CP_OFF_IMM_S2 in thumb
mode.
(md_assemble): Only allow coprocessor instructions when Thumb-2 is
available.
(cCE, cC3): Define.
(insns): Use them for coprocessor instructions.
(md_pcrel_from_section): Handle BFD_RELOC_ARM_T32_CP_OFF_IMM.
(get_thumb32_insn): New function.
(put_thumb32_insn): New function.
(md_apply_fix): Handle BFD_RELOC_ARM_T32_CP_OFF_IMM and
BFD_RELOC_ARM_T32_CP_OFF_IMM_S2.
gas/testsuite/
* gas/arm/vfp-bad_t2.d, gas/arm/vfp-bad_t2.l, arm/vfp-bad_t2.s,
gas/arm/vfp1_t2.d, gas/arm/vfp1_t2.s, gas/arm/vfp1xD_t2.d,
gas/arm/vfp1xD_t2.s, gas/arm/vfp2_t2.d, gas/arm/vfp2_t2.s): New files.
opcodes/
* arm-dis.c (coprocessor_opcodes): New.
(arm_opcodes, thumb32_opcodes): Remove coprocessor insns.
(print_insn_coprocessor): New function.
(print_insn_arm): Use print_insn_coprocessor. Remove coprocessor
format characters.
(print_insn_thumb32): Use print_insn_coprocessor.
2005-09-02 15:12:45 +02:00
|
|
|
|
/* format 10 */
|
2015-03-24 07:08:08 +01:00
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
|
|
|
|
|
|
0x8000, 0xF800, "strh%c\t%0-2r, [%3-5r, #%6-10H]"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
|
|
|
|
|
|
0x8800, 0xF800, "ldrh%c\t%0-2r, [%3-5r, #%6-10H]"},
|
2005-09-02 Paul Brook <paul@codesourcery.com>
bfd/
* libbdf.h: Regenerate.
* bfd-in2.h: Regenerate.
* reloc.c: Add BFD_RELOC_ARM_T32_CP_OFF_IMM and
BFD_RELOC_ARM_T32_CP_OFF_IMM_S2.
gas/
* config/tc-arm.c (encode_arm_cp_address): Use
BFD_RELOC_ARM_T32_CP_OFF_IMM in thumb mode.
(do_iwmmxt_wldstbh): Use BFD_RELOC_ARM_T32_CP_OFF_IMM_S2 in thumb
mode.
(md_assemble): Only allow coprocessor instructions when Thumb-2 is
available.
(cCE, cC3): Define.
(insns): Use them for coprocessor instructions.
(md_pcrel_from_section): Handle BFD_RELOC_ARM_T32_CP_OFF_IMM.
(get_thumb32_insn): New function.
(put_thumb32_insn): New function.
(md_apply_fix): Handle BFD_RELOC_ARM_T32_CP_OFF_IMM and
BFD_RELOC_ARM_T32_CP_OFF_IMM_S2.
gas/testsuite/
* gas/arm/vfp-bad_t2.d, gas/arm/vfp-bad_t2.l, arm/vfp-bad_t2.s,
gas/arm/vfp1_t2.d, gas/arm/vfp1_t2.s, gas/arm/vfp1xD_t2.d,
gas/arm/vfp1xD_t2.s, gas/arm/vfp2_t2.d, gas/arm/vfp2_t2.s): New files.
opcodes/
* arm-dis.c (coprocessor_opcodes): New.
(arm_opcodes, thumb32_opcodes): Remove coprocessor insns.
(print_insn_coprocessor): New function.
(print_insn_arm): Use print_insn_coprocessor. Remove coprocessor
format characters.
(print_insn_thumb32): Use print_insn_coprocessor.
2005-09-02 15:12:45 +02:00
|
|
|
|
/* format 11 */
|
2015-03-24 07:08:08 +01:00
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
|
|
|
|
|
|
0x9000, 0xF800, "str%c\t%8-10r, [sp, #%0-7W]"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
|
|
|
|
|
|
0x9800, 0xF800, "ldr%c\t%8-10r, [sp, #%0-7W]"},
|
2005-09-02 Paul Brook <paul@codesourcery.com>
bfd/
* libbdf.h: Regenerate.
* bfd-in2.h: Regenerate.
* reloc.c: Add BFD_RELOC_ARM_T32_CP_OFF_IMM and
BFD_RELOC_ARM_T32_CP_OFF_IMM_S2.
gas/
* config/tc-arm.c (encode_arm_cp_address): Use
BFD_RELOC_ARM_T32_CP_OFF_IMM in thumb mode.
(do_iwmmxt_wldstbh): Use BFD_RELOC_ARM_T32_CP_OFF_IMM_S2 in thumb
mode.
(md_assemble): Only allow coprocessor instructions when Thumb-2 is
available.
(cCE, cC3): Define.
(insns): Use them for coprocessor instructions.
(md_pcrel_from_section): Handle BFD_RELOC_ARM_T32_CP_OFF_IMM.
(get_thumb32_insn): New function.
(put_thumb32_insn): New function.
(md_apply_fix): Handle BFD_RELOC_ARM_T32_CP_OFF_IMM and
BFD_RELOC_ARM_T32_CP_OFF_IMM_S2.
gas/testsuite/
* gas/arm/vfp-bad_t2.d, gas/arm/vfp-bad_t2.l, arm/vfp-bad_t2.s,
gas/arm/vfp1_t2.d, gas/arm/vfp1_t2.s, gas/arm/vfp1xD_t2.d,
gas/arm/vfp1xD_t2.s, gas/arm/vfp2_t2.d, gas/arm/vfp2_t2.s): New files.
opcodes/
* arm-dis.c (coprocessor_opcodes): New.
(arm_opcodes, thumb32_opcodes): Remove coprocessor insns.
(print_insn_coprocessor): New function.
(print_insn_arm): Use print_insn_coprocessor. Remove coprocessor
format characters.
(print_insn_thumb32): Use print_insn_coprocessor.
2005-09-02 15:12:45 +02:00
|
|
|
|
/* format 12 */
|
2015-03-24 07:08:08 +01:00
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
|
|
|
|
|
|
0xA000, 0xF800, "add%c\t%8-10r, pc, #%0-7W\t; (adr %8-10r, %0-7a)"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
|
|
|
|
|
|
0xA800, 0xF800, "add%c\t%8-10r, sp, #%0-7W"},
|
2005-09-02 Paul Brook <paul@codesourcery.com>
bfd/
* libbdf.h: Regenerate.
* bfd-in2.h: Regenerate.
* reloc.c: Add BFD_RELOC_ARM_T32_CP_OFF_IMM and
BFD_RELOC_ARM_T32_CP_OFF_IMM_S2.
gas/
* config/tc-arm.c (encode_arm_cp_address): Use
BFD_RELOC_ARM_T32_CP_OFF_IMM in thumb mode.
(do_iwmmxt_wldstbh): Use BFD_RELOC_ARM_T32_CP_OFF_IMM_S2 in thumb
mode.
(md_assemble): Only allow coprocessor instructions when Thumb-2 is
available.
(cCE, cC3): Define.
(insns): Use them for coprocessor instructions.
(md_pcrel_from_section): Handle BFD_RELOC_ARM_T32_CP_OFF_IMM.
(get_thumb32_insn): New function.
(put_thumb32_insn): New function.
(md_apply_fix): Handle BFD_RELOC_ARM_T32_CP_OFF_IMM and
BFD_RELOC_ARM_T32_CP_OFF_IMM_S2.
gas/testsuite/
* gas/arm/vfp-bad_t2.d, gas/arm/vfp-bad_t2.l, arm/vfp-bad_t2.s,
gas/arm/vfp1_t2.d, gas/arm/vfp1_t2.s, gas/arm/vfp1xD_t2.d,
gas/arm/vfp1xD_t2.s, gas/arm/vfp2_t2.d, gas/arm/vfp2_t2.s): New files.
opcodes/
* arm-dis.c (coprocessor_opcodes): New.
(arm_opcodes, thumb32_opcodes): Remove coprocessor insns.
(print_insn_coprocessor): New function.
(print_insn_arm): Use print_insn_coprocessor. Remove coprocessor
format characters.
(print_insn_thumb32): Use print_insn_coprocessor.
2005-09-02 15:12:45 +02:00
|
|
|
|
/* format 15 */
|
2015-03-24 07:08:08 +01:00
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xC000, 0xF800, "stmia%c\t%8-10r!, %M"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xC800, 0xF800, "ldmia%c\t%8-10r%W, %M"},
|
2005-09-02 Paul Brook <paul@codesourcery.com>
bfd/
* libbdf.h: Regenerate.
* bfd-in2.h: Regenerate.
* reloc.c: Add BFD_RELOC_ARM_T32_CP_OFF_IMM and
BFD_RELOC_ARM_T32_CP_OFF_IMM_S2.
gas/
* config/tc-arm.c (encode_arm_cp_address): Use
BFD_RELOC_ARM_T32_CP_OFF_IMM in thumb mode.
(do_iwmmxt_wldstbh): Use BFD_RELOC_ARM_T32_CP_OFF_IMM_S2 in thumb
mode.
(md_assemble): Only allow coprocessor instructions when Thumb-2 is
available.
(cCE, cC3): Define.
(insns): Use them for coprocessor instructions.
(md_pcrel_from_section): Handle BFD_RELOC_ARM_T32_CP_OFF_IMM.
(get_thumb32_insn): New function.
(put_thumb32_insn): New function.
(md_apply_fix): Handle BFD_RELOC_ARM_T32_CP_OFF_IMM and
BFD_RELOC_ARM_T32_CP_OFF_IMM_S2.
gas/testsuite/
* gas/arm/vfp-bad_t2.d, gas/arm/vfp-bad_t2.l, arm/vfp-bad_t2.s,
gas/arm/vfp1_t2.d, gas/arm/vfp1_t2.s, gas/arm/vfp1xD_t2.d,
gas/arm/vfp1xD_t2.s, gas/arm/vfp2_t2.d, gas/arm/vfp2_t2.s): New files.
opcodes/
* arm-dis.c (coprocessor_opcodes): New.
(arm_opcodes, thumb32_opcodes): Remove coprocessor insns.
(print_insn_coprocessor): New function.
(print_insn_arm): Use print_insn_coprocessor. Remove coprocessor
format characters.
(print_insn_thumb32): Use print_insn_coprocessor.
2005-09-02 15:12:45 +02:00
|
|
|
|
/* format 17 */
|
2015-03-24 07:08:08 +01:00
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xDF00, 0xFF00, "svc%c\t%0-7d"},
|
2005-09-02 Paul Brook <paul@codesourcery.com>
bfd/
* libbdf.h: Regenerate.
* bfd-in2.h: Regenerate.
* reloc.c: Add BFD_RELOC_ARM_T32_CP_OFF_IMM and
BFD_RELOC_ARM_T32_CP_OFF_IMM_S2.
gas/
* config/tc-arm.c (encode_arm_cp_address): Use
BFD_RELOC_ARM_T32_CP_OFF_IMM in thumb mode.
(do_iwmmxt_wldstbh): Use BFD_RELOC_ARM_T32_CP_OFF_IMM_S2 in thumb
mode.
(md_assemble): Only allow coprocessor instructions when Thumb-2 is
available.
(cCE, cC3): Define.
(insns): Use them for coprocessor instructions.
(md_pcrel_from_section): Handle BFD_RELOC_ARM_T32_CP_OFF_IMM.
(get_thumb32_insn): New function.
(put_thumb32_insn): New function.
(md_apply_fix): Handle BFD_RELOC_ARM_T32_CP_OFF_IMM and
BFD_RELOC_ARM_T32_CP_OFF_IMM_S2.
gas/testsuite/
* gas/arm/vfp-bad_t2.d, gas/arm/vfp-bad_t2.l, arm/vfp-bad_t2.s,
gas/arm/vfp1_t2.d, gas/arm/vfp1_t2.s, gas/arm/vfp1xD_t2.d,
gas/arm/vfp1xD_t2.s, gas/arm/vfp2_t2.d, gas/arm/vfp2_t2.s): New files.
opcodes/
* arm-dis.c (coprocessor_opcodes): New.
(arm_opcodes, thumb32_opcodes): Remove coprocessor insns.
(print_insn_coprocessor): New function.
(print_insn_arm): Use print_insn_coprocessor. Remove coprocessor
format characters.
(print_insn_thumb32): Use print_insn_coprocessor.
2005-09-02 15:12:45 +02:00
|
|
|
|
/* format 16 */
|
2015-03-24 07:08:08 +01:00
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xDE00, 0xFF00, "udf%c\t#%0-7d"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xDE00, 0xFE00, UNDEFINED_INSTRUCTION},
|
|
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xD000, 0xF000, "b%8-11c.n\t%0-7B%X"},
|
2005-09-02 Paul Brook <paul@codesourcery.com>
bfd/
* libbdf.h: Regenerate.
* bfd-in2.h: Regenerate.
* reloc.c: Add BFD_RELOC_ARM_T32_CP_OFF_IMM and
BFD_RELOC_ARM_T32_CP_OFF_IMM_S2.
gas/
* config/tc-arm.c (encode_arm_cp_address): Use
BFD_RELOC_ARM_T32_CP_OFF_IMM in thumb mode.
(do_iwmmxt_wldstbh): Use BFD_RELOC_ARM_T32_CP_OFF_IMM_S2 in thumb
mode.
(md_assemble): Only allow coprocessor instructions when Thumb-2 is
available.
(cCE, cC3): Define.
(insns): Use them for coprocessor instructions.
(md_pcrel_from_section): Handle BFD_RELOC_ARM_T32_CP_OFF_IMM.
(get_thumb32_insn): New function.
(put_thumb32_insn): New function.
(md_apply_fix): Handle BFD_RELOC_ARM_T32_CP_OFF_IMM and
BFD_RELOC_ARM_T32_CP_OFF_IMM_S2.
gas/testsuite/
* gas/arm/vfp-bad_t2.d, gas/arm/vfp-bad_t2.l, arm/vfp-bad_t2.s,
gas/arm/vfp1_t2.d, gas/arm/vfp1_t2.s, gas/arm/vfp1xD_t2.d,
gas/arm/vfp1xD_t2.s, gas/arm/vfp2_t2.d, gas/arm/vfp2_t2.s): New files.
opcodes/
* arm-dis.c (coprocessor_opcodes): New.
(arm_opcodes, thumb32_opcodes): Remove coprocessor insns.
(print_insn_coprocessor): New function.
(print_insn_arm): Use print_insn_coprocessor. Remove coprocessor
format characters.
(print_insn_thumb32): Use print_insn_coprocessor.
2005-09-02 15:12:45 +02:00
|
|
|
|
/* format 18 */
|
2015-03-24 07:08:08 +01:00
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xE000, 0xF800, "b%c.n\t%0-10B%x"},
|
2005-09-02 Paul Brook <paul@codesourcery.com>
bfd/
* libbdf.h: Regenerate.
* bfd-in2.h: Regenerate.
* reloc.c: Add BFD_RELOC_ARM_T32_CP_OFF_IMM and
BFD_RELOC_ARM_T32_CP_OFF_IMM_S2.
gas/
* config/tc-arm.c (encode_arm_cp_address): Use
BFD_RELOC_ARM_T32_CP_OFF_IMM in thumb mode.
(do_iwmmxt_wldstbh): Use BFD_RELOC_ARM_T32_CP_OFF_IMM_S2 in thumb
mode.
(md_assemble): Only allow coprocessor instructions when Thumb-2 is
available.
(cCE, cC3): Define.
(insns): Use them for coprocessor instructions.
(md_pcrel_from_section): Handle BFD_RELOC_ARM_T32_CP_OFF_IMM.
(get_thumb32_insn): New function.
(put_thumb32_insn): New function.
(md_apply_fix): Handle BFD_RELOC_ARM_T32_CP_OFF_IMM and
BFD_RELOC_ARM_T32_CP_OFF_IMM_S2.
gas/testsuite/
* gas/arm/vfp-bad_t2.d, gas/arm/vfp-bad_t2.l, arm/vfp-bad_t2.s,
gas/arm/vfp1_t2.d, gas/arm/vfp1_t2.s, gas/arm/vfp1xD_t2.d,
gas/arm/vfp1xD_t2.s, gas/arm/vfp2_t2.d, gas/arm/vfp2_t2.s): New files.
opcodes/
* arm-dis.c (coprocessor_opcodes): New.
(arm_opcodes, thumb32_opcodes): Remove coprocessor insns.
(print_insn_coprocessor): New function.
(print_insn_arm): Use print_insn_coprocessor. Remove coprocessor
format characters.
(print_insn_thumb32): Use print_insn_coprocessor.
2005-09-02 15:12:45 +02:00
|
|
|
|
|
|
|
|
|
|
/* The E800 .. FFFF range is unconditionally redirected to the
|
|
|
|
|
|
32-bit table, because even in pre-V6T2 ISAs, BL and BLX(1) pairs
|
|
|
|
|
|
are processed via that table. Thus, we can never encounter a
|
|
|
|
|
|
bare "second half of BL/BLX(1)" instruction here. */
|
2015-03-24 07:08:08 +01:00
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 0x0000, 0x0000, UNDEFINED_INSTRUCTION},
|
|
|
|
|
|
{ARM_FEATURE_CORE_LOW (0), 0, 0, 0}
|
2005-09-02 Paul Brook <paul@codesourcery.com>
bfd/
* libbdf.h: Regenerate.
* bfd-in2.h: Regenerate.
* reloc.c: Add BFD_RELOC_ARM_T32_CP_OFF_IMM and
BFD_RELOC_ARM_T32_CP_OFF_IMM_S2.
gas/
* config/tc-arm.c (encode_arm_cp_address): Use
BFD_RELOC_ARM_T32_CP_OFF_IMM in thumb mode.
(do_iwmmxt_wldstbh): Use BFD_RELOC_ARM_T32_CP_OFF_IMM_S2 in thumb
mode.
(md_assemble): Only allow coprocessor instructions when Thumb-2 is
available.
(cCE, cC3): Define.
(insns): Use them for coprocessor instructions.
(md_pcrel_from_section): Handle BFD_RELOC_ARM_T32_CP_OFF_IMM.
(get_thumb32_insn): New function.
(put_thumb32_insn): New function.
(md_apply_fix): Handle BFD_RELOC_ARM_T32_CP_OFF_IMM and
BFD_RELOC_ARM_T32_CP_OFF_IMM_S2.
gas/testsuite/
* gas/arm/vfp-bad_t2.d, gas/arm/vfp-bad_t2.l, arm/vfp-bad_t2.s,
gas/arm/vfp1_t2.d, gas/arm/vfp1_t2.s, gas/arm/vfp1xD_t2.d,
gas/arm/vfp1xD_t2.s, gas/arm/vfp2_t2.d, gas/arm/vfp2_t2.s): New files.
opcodes/
* arm-dis.c (coprocessor_opcodes): New.
(arm_opcodes, thumb32_opcodes): Remove coprocessor insns.
(print_insn_coprocessor): New function.
(print_insn_arm): Use print_insn_coprocessor. Remove coprocessor
format characters.
(print_insn_thumb32): Use print_insn_coprocessor.
2005-09-02 15:12:45 +02:00
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
|
|
/* Thumb32 opcodes use the same table structure as the ARM opcodes.
|
|
|
|
|
|
We adopt the convention that hw1 is the high 16 bits of .value and
|
|
|
|
|
|
.mask, hw2 the low 16 bits.
|
|
|
|
|
|
|
|
|
|
|
|
print_insn_thumb32 recognizes the following format control codes:
|
|
|
|
|
|
|
|
|
|
|
|
%% %
|
|
|
|
|
|
|
|
|
|
|
|
%I print a 12-bit immediate from hw1[10],hw2[14:12,7:0]
|
|
|
|
|
|
%M print a modified 12-bit immediate (same location)
|
|
|
|
|
|
%J print a 16-bit immediate from hw1[3:0,10],hw2[14:12,7:0]
|
|
|
|
|
|
%K print a 16-bit immediate from hw2[3:0],hw1[3:0],hw2[11:4]
|
2010-09-23 17:52:19 +02:00
|
|
|
|
%H print a 16-bit immediate from hw2[3:0],hw1[11:0]
|
2005-09-02 Paul Brook <paul@codesourcery.com>
bfd/
* libbdf.h: Regenerate.
* bfd-in2.h: Regenerate.
* reloc.c: Add BFD_RELOC_ARM_T32_CP_OFF_IMM and
BFD_RELOC_ARM_T32_CP_OFF_IMM_S2.
gas/
* config/tc-arm.c (encode_arm_cp_address): Use
BFD_RELOC_ARM_T32_CP_OFF_IMM in thumb mode.
(do_iwmmxt_wldstbh): Use BFD_RELOC_ARM_T32_CP_OFF_IMM_S2 in thumb
mode.
(md_assemble): Only allow coprocessor instructions when Thumb-2 is
available.
(cCE, cC3): Define.
(insns): Use them for coprocessor instructions.
(md_pcrel_from_section): Handle BFD_RELOC_ARM_T32_CP_OFF_IMM.
(get_thumb32_insn): New function.
(put_thumb32_insn): New function.
(md_apply_fix): Handle BFD_RELOC_ARM_T32_CP_OFF_IMM and
BFD_RELOC_ARM_T32_CP_OFF_IMM_S2.
gas/testsuite/
* gas/arm/vfp-bad_t2.d, gas/arm/vfp-bad_t2.l, arm/vfp-bad_t2.s,
gas/arm/vfp1_t2.d, gas/arm/vfp1_t2.s, gas/arm/vfp1xD_t2.d,
gas/arm/vfp1xD_t2.s, gas/arm/vfp2_t2.d, gas/arm/vfp2_t2.s): New files.
opcodes/
* arm-dis.c (coprocessor_opcodes): New.
(arm_opcodes, thumb32_opcodes): Remove coprocessor insns.
(print_insn_coprocessor): New function.
(print_insn_arm): Use print_insn_coprocessor. Remove coprocessor
format characters.
(print_insn_thumb32): Use print_insn_coprocessor.
2005-09-02 15:12:45 +02:00
|
|
|
|
%S print a possibly-shifted Rm
|
|
|
|
|
|
|
2011-04-12 18:01:48 +02:00
|
|
|
|
%L print address for a ldrd/strd instruction
|
2005-09-02 Paul Brook <paul@codesourcery.com>
bfd/
* libbdf.h: Regenerate.
* bfd-in2.h: Regenerate.
* reloc.c: Add BFD_RELOC_ARM_T32_CP_OFF_IMM and
BFD_RELOC_ARM_T32_CP_OFF_IMM_S2.
gas/
* config/tc-arm.c (encode_arm_cp_address): Use
BFD_RELOC_ARM_T32_CP_OFF_IMM in thumb mode.
(do_iwmmxt_wldstbh): Use BFD_RELOC_ARM_T32_CP_OFF_IMM_S2 in thumb
mode.
(md_assemble): Only allow coprocessor instructions when Thumb-2 is
available.
(cCE, cC3): Define.
(insns): Use them for coprocessor instructions.
(md_pcrel_from_section): Handle BFD_RELOC_ARM_T32_CP_OFF_IMM.
(get_thumb32_insn): New function.
(put_thumb32_insn): New function.
(md_apply_fix): Handle BFD_RELOC_ARM_T32_CP_OFF_IMM and
BFD_RELOC_ARM_T32_CP_OFF_IMM_S2.
gas/testsuite/
* gas/arm/vfp-bad_t2.d, gas/arm/vfp-bad_t2.l, arm/vfp-bad_t2.s,
gas/arm/vfp1_t2.d, gas/arm/vfp1_t2.s, gas/arm/vfp1xD_t2.d,
gas/arm/vfp1xD_t2.s, gas/arm/vfp2_t2.d, gas/arm/vfp2_t2.s): New files.
opcodes/
* arm-dis.c (coprocessor_opcodes): New.
(arm_opcodes, thumb32_opcodes): Remove coprocessor insns.
(print_insn_coprocessor): New function.
(print_insn_arm): Use print_insn_coprocessor. Remove coprocessor
format characters.
(print_insn_thumb32): Use print_insn_coprocessor.
2005-09-02 15:12:45 +02:00
|
|
|
|
%a print the address of a plain load/store
|
|
|
|
|
|
%w print the width and signedness of a core load/store
|
|
|
|
|
|
%m print register mask for ldm/stm
|
|
|
|
|
|
|
|
|
|
|
|
%E print the lsb and width fields of a bfc/bfi instruction
|
|
|
|
|
|
%F print the lsb and width fields of a sbfx/ubfx instruction
|
|
|
|
|
|
%b print a conditional branch offset
|
|
|
|
|
|
%B print an unconditional branch offset
|
|
|
|
|
|
%s print the shift field of an SSAT instruction
|
|
|
|
|
|
%R print the rotation field of an SXT instruction
|
2006-02-24 Paul Brook <paul@codesourcery.com>
gas/
* config/arm/tc-arm.c (arm_ext_v6_notm, arm_ext_div, arm_ext_v7,
arm_ext_v7a, arm_ext_v7r, arm_ext_v7m): New variables.
(struct asm_barrier_opt): Define.
(arm_v7m_psr_hsh, arm_barrier_opt_hsh): New variables.
(parse_psr): Accept V7M psr names.
(parse_barrier): New function.
(enum operand_parse_code): Add OP_oBARRIER.
(parse_operands): Implement OP_oBARRIER.
(do_barrier): New function.
(do_dbg, do_pli, do_t_barrier, do_t_dbg, do_t_div): New functions.
(do_t_cpsi): Add V7M restrictions.
(do_t_mrs, do_t_msr): Validate V7M variants.
(md_assemble): Check for NULL variants.
(v7m_psrs, barrier_opt_names): New tables.
(insns): Add V7 instructions. Mark V6 instructions absent from V7M.
(md_begin): Initialize arm_v7m_psr_hsh and arm_barrier_opt_hsh.
(arm_cpu_option_table): Add Cortex-M3, R4 and A8.
(arm_arch_option_table): Add armv7, armv7a, armv7r and armv7m.
(struct cpu_arch_ver_table): Define.
(cpu_arch_ver): New.
(aeabi_set_public_attributes): Use cpu_arch_ver. Set
Tag_CPU_arch_profile.
* doc/c-arm.texi: Document new cpu and arch options.
gas/testsuite/
* gas/arm/thumb32.d: Fix expected msr and mrs output.
* gas/arm/arch7.d: New test.
* gas/arm/arch7.s: New test.
* gas/arm/arch7m-bad.l: New test.
* gas/arm/arch7m-bad.d: New test.
* gas/arm/arch7m-bad.s: New test.
include/opcode/
* arm.h: Add V7 feature bits.
opcodes/
* arm-dis.c (arm_opcodes): Add V7 instructions.
(thumb32_opcodes): Ditto. Handle V7M MSR/MRS variants.
(print_arm_address): New function.
(print_insn_arm): Use it. Add 'P' and 'U' cases.
(psr_name): New function.
(print_insn_thumb32): Add 'U', 'C' and 'D' cases.
2006-02-24 16:36:36 +01:00
|
|
|
|
%U print barrier type.
|
|
|
|
|
|
%P print address for pli instruction.
|
2006-06-07 16:08:19 +02:00
|
|
|
|
%c print the condition code
|
|
|
|
|
|
%x print warning if conditional an not at end of IT block"
|
|
|
|
|
|
%X print "\t; unpredictable <IT:code>" if conditional
|
2005-09-02 Paul Brook <paul@codesourcery.com>
bfd/
* libbdf.h: Regenerate.
* bfd-in2.h: Regenerate.
* reloc.c: Add BFD_RELOC_ARM_T32_CP_OFF_IMM and
BFD_RELOC_ARM_T32_CP_OFF_IMM_S2.
gas/
* config/tc-arm.c (encode_arm_cp_address): Use
BFD_RELOC_ARM_T32_CP_OFF_IMM in thumb mode.
(do_iwmmxt_wldstbh): Use BFD_RELOC_ARM_T32_CP_OFF_IMM_S2 in thumb
mode.
(md_assemble): Only allow coprocessor instructions when Thumb-2 is
available.
(cCE, cC3): Define.
(insns): Use them for coprocessor instructions.
(md_pcrel_from_section): Handle BFD_RELOC_ARM_T32_CP_OFF_IMM.
(get_thumb32_insn): New function.
(put_thumb32_insn): New function.
(md_apply_fix): Handle BFD_RELOC_ARM_T32_CP_OFF_IMM and
BFD_RELOC_ARM_T32_CP_OFF_IMM_S2.
gas/testsuite/
* gas/arm/vfp-bad_t2.d, gas/arm/vfp-bad_t2.l, arm/vfp-bad_t2.s,
gas/arm/vfp1_t2.d, gas/arm/vfp1_t2.s, gas/arm/vfp1xD_t2.d,
gas/arm/vfp1xD_t2.s, gas/arm/vfp2_t2.d, gas/arm/vfp2_t2.s): New files.
opcodes/
* arm-dis.c (coprocessor_opcodes): New.
(arm_opcodes, thumb32_opcodes): Remove coprocessor insns.
(print_insn_coprocessor): New function.
(print_insn_arm): Use print_insn_coprocessor. Remove coprocessor
format characters.
(print_insn_thumb32): Use print_insn_coprocessor.
2005-09-02 15:12:45 +02:00
|
|
|
|
|
|
|
|
|
|
%<bitfield>d print bitfield in decimal
|
2015-04-15 18:44:03 +02:00
|
|
|
|
%<bitfield>D print bitfield plus one in decimal
|
2005-09-02 Paul Brook <paul@codesourcery.com>
bfd/
* libbdf.h: Regenerate.
* bfd-in2.h: Regenerate.
* reloc.c: Add BFD_RELOC_ARM_T32_CP_OFF_IMM and
BFD_RELOC_ARM_T32_CP_OFF_IMM_S2.
gas/
* config/tc-arm.c (encode_arm_cp_address): Use
BFD_RELOC_ARM_T32_CP_OFF_IMM in thumb mode.
(do_iwmmxt_wldstbh): Use BFD_RELOC_ARM_T32_CP_OFF_IMM_S2 in thumb
mode.
(md_assemble): Only allow coprocessor instructions when Thumb-2 is
available.
(cCE, cC3): Define.
(insns): Use them for coprocessor instructions.
(md_pcrel_from_section): Handle BFD_RELOC_ARM_T32_CP_OFF_IMM.
(get_thumb32_insn): New function.
(put_thumb32_insn): New function.
(md_apply_fix): Handle BFD_RELOC_ARM_T32_CP_OFF_IMM and
BFD_RELOC_ARM_T32_CP_OFF_IMM_S2.
gas/testsuite/
* gas/arm/vfp-bad_t2.d, gas/arm/vfp-bad_t2.l, arm/vfp-bad_t2.s,
gas/arm/vfp1_t2.d, gas/arm/vfp1_t2.s, gas/arm/vfp1xD_t2.d,
gas/arm/vfp1xD_t2.s, gas/arm/vfp2_t2.d, gas/arm/vfp2_t2.s): New files.
opcodes/
* arm-dis.c (coprocessor_opcodes): New.
(arm_opcodes, thumb32_opcodes): Remove coprocessor insns.
(print_insn_coprocessor): New function.
(print_insn_arm): Use print_insn_coprocessor. Remove coprocessor
format characters.
(print_insn_thumb32): Use print_insn_coprocessor.
2005-09-02 15:12:45 +02:00
|
|
|
|
%<bitfield>W print bitfield*4 in decimal
|
|
|
|
|
|
%<bitfield>r print bitfield as an ARM register
|
2013-03-11 12:09:33 +01:00
|
|
|
|
%<bitfield>R as %<>r but r15 is UNPREDICTABLE
|
2005-09-02 Paul Brook <paul@codesourcery.com>
bfd/
* libbdf.h: Regenerate.
* bfd-in2.h: Regenerate.
* reloc.c: Add BFD_RELOC_ARM_T32_CP_OFF_IMM and
BFD_RELOC_ARM_T32_CP_OFF_IMM_S2.
gas/
* config/tc-arm.c (encode_arm_cp_address): Use
BFD_RELOC_ARM_T32_CP_OFF_IMM in thumb mode.
(do_iwmmxt_wldstbh): Use BFD_RELOC_ARM_T32_CP_OFF_IMM_S2 in thumb
mode.
(md_assemble): Only allow coprocessor instructions when Thumb-2 is
available.
(cCE, cC3): Define.
(insns): Use them for coprocessor instructions.
(md_pcrel_from_section): Handle BFD_RELOC_ARM_T32_CP_OFF_IMM.
(get_thumb32_insn): New function.
(put_thumb32_insn): New function.
(md_apply_fix): Handle BFD_RELOC_ARM_T32_CP_OFF_IMM and
BFD_RELOC_ARM_T32_CP_OFF_IMM_S2.
gas/testsuite/
* gas/arm/vfp-bad_t2.d, gas/arm/vfp-bad_t2.l, arm/vfp-bad_t2.s,
gas/arm/vfp1_t2.d, gas/arm/vfp1_t2.s, gas/arm/vfp1xD_t2.d,
gas/arm/vfp1xD_t2.s, gas/arm/vfp2_t2.d, gas/arm/vfp2_t2.s): New files.
opcodes/
* arm-dis.c (coprocessor_opcodes): New.
(arm_opcodes, thumb32_opcodes): Remove coprocessor insns.
(print_insn_coprocessor): New function.
(print_insn_arm): Use print_insn_coprocessor. Remove coprocessor
format characters.
(print_insn_thumb32): Use print_insn_coprocessor.
2005-09-02 15:12:45 +02:00
|
|
|
|
%<bitfield>c print bitfield as a condition code
|
|
|
|
|
|
|
2006-04-26 17:40:55 +02:00
|
|
|
|
%<bitfield>'c print specified char iff bitfield is all ones
|
|
|
|
|
|
%<bitfield>`c print specified char iff bitfield is all zeroes
|
|
|
|
|
|
%<bitfield>?ab... select from array of values in big endian order
|
2005-09-02 Paul Brook <paul@codesourcery.com>
bfd/
* libbdf.h: Regenerate.
* bfd-in2.h: Regenerate.
* reloc.c: Add BFD_RELOC_ARM_T32_CP_OFF_IMM and
BFD_RELOC_ARM_T32_CP_OFF_IMM_S2.
gas/
* config/tc-arm.c (encode_arm_cp_address): Use
BFD_RELOC_ARM_T32_CP_OFF_IMM in thumb mode.
(do_iwmmxt_wldstbh): Use BFD_RELOC_ARM_T32_CP_OFF_IMM_S2 in thumb
mode.
(md_assemble): Only allow coprocessor instructions when Thumb-2 is
available.
(cCE, cC3): Define.
(insns): Use them for coprocessor instructions.
(md_pcrel_from_section): Handle BFD_RELOC_ARM_T32_CP_OFF_IMM.
(get_thumb32_insn): New function.
(put_thumb32_insn): New function.
(md_apply_fix): Handle BFD_RELOC_ARM_T32_CP_OFF_IMM and
BFD_RELOC_ARM_T32_CP_OFF_IMM_S2.
gas/testsuite/
* gas/arm/vfp-bad_t2.d, gas/arm/vfp-bad_t2.l, arm/vfp-bad_t2.s,
gas/arm/vfp1_t2.d, gas/arm/vfp1_t2.s, gas/arm/vfp1xD_t2.d,
gas/arm/vfp1xD_t2.s, gas/arm/vfp2_t2.d, gas/arm/vfp2_t2.s): New files.
opcodes/
* arm-dis.c (coprocessor_opcodes): New.
(arm_opcodes, thumb32_opcodes): Remove coprocessor insns.
(print_insn_coprocessor): New function.
(print_insn_arm): Use print_insn_coprocessor. Remove coprocessor
format characters.
(print_insn_thumb32): Use print_insn_coprocessor.
2005-09-02 15:12:45 +02:00
|
|
|
|
|
|
|
|
|
|
With one exception at the bottom (done because BL and BLX(1) need
|
|
|
|
|
|
to come dead last), this table was machine-sorted first in
|
|
|
|
|
|
decreasing order of number of bits set in the mask, then in
|
|
|
|
|
|
increasing numeric order of mask, then in increasing numeric order
|
|
|
|
|
|
of opcode. This order is not the clearest for a human reader, but
|
|
|
|
|
|
is guaranteed never to catch a special-case bit pattern with a more
|
|
|
|
|
|
general mask, which is important, because this instruction encoding
|
|
|
|
|
|
makes heavy use of special-case bit patterns. */
|
|
|
|
|
|
static const struct opcode32 thumb32_opcodes[] =
|
|
|
|
|
|
{
|
2016-05-10 16:01:53 +02:00
|
|
|
|
/* ARMv8-M and ARMv8-M Security Extensions instructions. */
|
|
|
|
|
|
{ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M), 0xe97fe97f, 0xffffffff, "sg"},
|
Add assembler support for ARMv8-M Mainline
2015-12-24 Thomas Preud'homme <thomas.preudhomme@arm.com>
bfd/
(tag_cpu_arch_combine): Adjust v4t_plus_v6_m and comb array to account
for new TAG_CPU_ARCH_V4T_PLUS_V6_M value. Deal with NULL values in
comb array.
binutils/
* readelf.c (arm_attr_tag_CPU_arch): Add ARMv8-M Mainline Tag_CPU_arch
value.
(arm_attr_tag_THUMB_ISA_use): Add ARMv8-M Mainline Tag_THUMB_ISA_use
value.
gas/
* config/tc-arm.c (arm_ext_m): Include ARMv8-M.
(arm_ext_v8m): New feature for ARMv8-M.
(arm_ext_atomics): New feature for ARMv8 atomics.
(do_tt): New encoding function for TT* instructions.
(insns): Add new entries for ARMv8-M specific instructions and
reorganize the ones shared by ARMv8-M Mainline and ARMv8-A.
(arm_archs): Define armv8-m.main architecture.
(cpu_arch_ver): Define ARM_ARCH_V8M_MAIN architecture version and
clarify the ordering rule.
(aeabi_set_public_attributes): Use TAG_CPU_ARCH_* macro to refer to
Tag_CPU_arch values for ARMv7e-M detection. Add logic to keep setting
Tag_CPU_arch to ARMv8-A for -march=all. Also set Tag_CPU_arch_profile
to 'A' if extension bit for atomic instructions is set, unless it is
ARMv8-M. Set Tag_THUMB_ISA_use to 3 for ARMv8-M. Set Tag_DIV_use to 0
for ARMv8-M Mainline.
gas/testsuite/
* gas/arm/archv8m.s: New file.
* gas/arm/archv8m-main.d: Likewise.
* gas/arm/attr-march-armv8m.main.d: Likewise.
* gas/arm/any-armv8m.s: Likewise.
* gas/arm/any-armv8m.d: Likewise.
include/elf/
* arm.h (TAG_CPU_ARCH_V8M_MAIN): Declare.
(MAX_TAG_CPU_ARCH): Define to TAG_CPU_ARCH_V8M_MAIN.
(TAG_CPU_ARCH_V4T_PLUS_V6_M): Define to unused value 15.
include/opcode/
* arm.h (ARM_EXT2_ATOMICS): New extension bit.
(ARM_EXT2_V8M): Likewise.
(ARM_EXT_V8): Adjust comment with regards to atomics and remove
mention of legacy use for that bit.
(ARM_AEXT2_V8_1A): New architecture extension bitfield.
(ARM_AEXT2_V8_2A): Likewise.
(ARM_AEXT_V8M_MAIN): Likewise.
(ARM_AEXT2_V8M): Likewise.
(ARM_ARCH_V8A): Use ARM_EXT2_ATOMICS for features in second bitfield.
(ARM_ARCH_V8_1A): Likewise with ARM_AEXT2_V8_1A.
(ARM_ARCH_V8_2A): Likewise with ARM_AEXT2_V8_2A.
(ARM_ARCH_V8M_MAIN): New architecture feature bitfield.
(ARM_ARCH_V8A_FP): Use ARM_EXT2_ATOMICS for features in second bitfield
and reindent.
(ARM_ARCH_V8A_SIMD): Likewise.
(ARM_ARCH_V8A_CRYPTOV1): Likewise.
(ARM_ARCH_V8_1A_FP): Use ARM_AEXT2_V8_1A to set second bitfield of
feature bits.
(ARM_ARCH_V8_1A_SIMD): Likewise.
(ARM_ARCH_V8_1A_CRYPTOV1): Likewise.
opcodes/
* arm-dis.c (arm_opcodes): Guard lda, ldab, ldaex, ldaexb, ldaexh, stl,
stlb, stlh, stlex, stlexb and stlexh by ARM_EXT2_ATOMICS instead of
ARM_EXT_V8.
(thumb32_opcodes): Add entries for wide ARMv8-M instructions.
2015-12-24 10:16:19 +01:00
|
|
|
|
{ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M),
|
|
|
|
|
|
0xe840f000, 0xfff0f0ff, "tt\t%8-11r, %16-19r"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M),
|
|
|
|
|
|
0xe840f040, 0xfff0f0ff, "ttt\t%8-11r, %16-19r"},
|
2016-05-10 16:01:53 +02:00
|
|
|
|
{ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M),
|
|
|
|
|
|
0xe840f080, 0xfff0f0ff, "tta\t%8-11r, %16-19r"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M),
|
|
|
|
|
|
0xe840f0c0, 0xfff0f0ff, "ttat\t%8-11r, %16-19r"},
|
Add assembler support for ARMv8-M Mainline
2015-12-24 Thomas Preud'homme <thomas.preudhomme@arm.com>
bfd/
(tag_cpu_arch_combine): Adjust v4t_plus_v6_m and comb array to account
for new TAG_CPU_ARCH_V4T_PLUS_V6_M value. Deal with NULL values in
comb array.
binutils/
* readelf.c (arm_attr_tag_CPU_arch): Add ARMv8-M Mainline Tag_CPU_arch
value.
(arm_attr_tag_THUMB_ISA_use): Add ARMv8-M Mainline Tag_THUMB_ISA_use
value.
gas/
* config/tc-arm.c (arm_ext_m): Include ARMv8-M.
(arm_ext_v8m): New feature for ARMv8-M.
(arm_ext_atomics): New feature for ARMv8 atomics.
(do_tt): New encoding function for TT* instructions.
(insns): Add new entries for ARMv8-M specific instructions and
reorganize the ones shared by ARMv8-M Mainline and ARMv8-A.
(arm_archs): Define armv8-m.main architecture.
(cpu_arch_ver): Define ARM_ARCH_V8M_MAIN architecture version and
clarify the ordering rule.
(aeabi_set_public_attributes): Use TAG_CPU_ARCH_* macro to refer to
Tag_CPU_arch values for ARMv7e-M detection. Add logic to keep setting
Tag_CPU_arch to ARMv8-A for -march=all. Also set Tag_CPU_arch_profile
to 'A' if extension bit for atomic instructions is set, unless it is
ARMv8-M. Set Tag_THUMB_ISA_use to 3 for ARMv8-M. Set Tag_DIV_use to 0
for ARMv8-M Mainline.
gas/testsuite/
* gas/arm/archv8m.s: New file.
* gas/arm/archv8m-main.d: Likewise.
* gas/arm/attr-march-armv8m.main.d: Likewise.
* gas/arm/any-armv8m.s: Likewise.
* gas/arm/any-armv8m.d: Likewise.
include/elf/
* arm.h (TAG_CPU_ARCH_V8M_MAIN): Declare.
(MAX_TAG_CPU_ARCH): Define to TAG_CPU_ARCH_V8M_MAIN.
(TAG_CPU_ARCH_V4T_PLUS_V6_M): Define to unused value 15.
include/opcode/
* arm.h (ARM_EXT2_ATOMICS): New extension bit.
(ARM_EXT2_V8M): Likewise.
(ARM_EXT_V8): Adjust comment with regards to atomics and remove
mention of legacy use for that bit.
(ARM_AEXT2_V8_1A): New architecture extension bitfield.
(ARM_AEXT2_V8_2A): Likewise.
(ARM_AEXT_V8M_MAIN): Likewise.
(ARM_AEXT2_V8M): Likewise.
(ARM_ARCH_V8A): Use ARM_EXT2_ATOMICS for features in second bitfield.
(ARM_ARCH_V8_1A): Likewise with ARM_AEXT2_V8_1A.
(ARM_ARCH_V8_2A): Likewise with ARM_AEXT2_V8_2A.
(ARM_ARCH_V8M_MAIN): New architecture feature bitfield.
(ARM_ARCH_V8A_FP): Use ARM_EXT2_ATOMICS for features in second bitfield
and reindent.
(ARM_ARCH_V8A_SIMD): Likewise.
(ARM_ARCH_V8A_CRYPTOV1): Likewise.
(ARM_ARCH_V8_1A_FP): Use ARM_AEXT2_V8_1A to set second bitfield of
feature bits.
(ARM_ARCH_V8_1A_SIMD): Likewise.
(ARM_ARCH_V8_1A_CRYPTOV1): Likewise.
opcodes/
* arm-dis.c (arm_opcodes): Guard lda, ldab, ldaex, ldaexb, ldaexh, stl,
stlb, stlh, stlex, stlexb and stlexh by ARM_EXT2_ATOMICS instead of
ARM_EXT_V8.
(thumb32_opcodes): Add entries for wide ARMv8-M instructions.
2015-12-24 10:16:19 +01:00
|
|
|
|
|
2016-01-12 17:35:30 +01:00
|
|
|
|
/* ARM V8.2 RAS extension instructions. */
|
2016-06-07 10:56:42 +02:00
|
|
|
|
{ARM_FEATURE_CORE_HIGH (ARM_EXT2_RAS),
|
2016-01-12 17:35:30 +01:00
|
|
|
|
0xf3af8010, 0xffffffff, "esb"},
|
|
|
|
|
|
|
2012-08-24 10:01:18 +02:00
|
|
|
|
/* V8 instructions. */
|
2015-03-24 07:08:08 +01:00
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
|
|
|
|
|
|
0xf3af8005, 0xffffffff, "sevl%c.w"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
|
|
|
|
|
|
0xf78f8000, 0xfffffffc, "dcps%0-1d"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
|
|
|
|
|
|
0xe8c00f8f, 0xfff00fff, "stlb%c\t%12-15r, [%16-19R]"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
|
|
|
|
|
|
0xe8c00f9f, 0xfff00fff, "stlh%c\t%12-15r, [%16-19R]"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
|
|
|
|
|
|
0xe8c00faf, 0xfff00fff, "stl%c\t%12-15r, [%16-19R]"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
|
|
|
|
|
|
0xe8c00fc0, 0xfff00ff0, "stlexb%c\t%0-3r, %12-15r, [%16-19R]"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
|
|
|
|
|
|
0xe8c00fd0, 0xfff00ff0, "stlexh%c\t%0-3r, %12-15r, [%16-19R]"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
|
|
|
|
|
|
0xe8c00fe0, 0xfff00ff0, "stlex%c\t%0-3r, %12-15r, [%16-19R]"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
|
|
|
|
|
|
0xe8c000f0, 0xfff000f0, "stlexd%c\t%0-3r, %12-15r, %8-11r, [%16-19R]"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
|
|
|
|
|
|
0xe8d00f8f, 0xfff00fff, "ldab%c\t%12-15r, [%16-19R]"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
|
|
|
|
|
|
0xe8d00f9f, 0xfff00fff, "ldah%c\t%12-15r, [%16-19R]"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
|
|
|
|
|
|
0xe8d00faf, 0xfff00fff, "lda%c\t%12-15r, [%16-19R]"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
|
|
|
|
|
|
0xe8d00fcf, 0xfff00fff, "ldaexb%c\t%12-15r, [%16-19R]"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
|
|
|
|
|
|
0xe8d00fdf, 0xfff00fff, "ldaexh%c\t%12-15r, [%16-19R]"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
|
|
|
|
|
|
0xe8d00fef, 0xfff00fff, "ldaex%c\t%12-15r, [%16-19R]"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
|
|
|
|
|
|
0xe8d000ff, 0xfff000ff, "ldaexd%c\t%12-15r, %8-11r, [%16-19R]"},
|
2012-08-24 10:01:18 +02:00
|
|
|
|
|
2013-03-11 12:09:33 +01:00
|
|
|
|
/* CRC32 instructions. */
|
2015-03-24 07:08:08 +01:00
|
|
|
|
{ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
|
2017-08-09 18:52:54 +02:00
|
|
|
|
0xfac0f080, 0xfff0f0f0, "crc32b\t%8-11R, %16-19R, %0-3R"},
|
2015-03-24 07:08:08 +01:00
|
|
|
|
{ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
|
2017-08-09 18:52:54 +02:00
|
|
|
|
0xfac0f090, 0xfff0f0f0, "crc32h\t%9-11R, %16-19R, %0-3R"},
|
2015-03-24 07:08:08 +01:00
|
|
|
|
{ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
|
2017-08-09 18:52:54 +02:00
|
|
|
|
0xfac0f0a0, 0xfff0f0f0, "crc32w\t%8-11R, %16-19R, %0-3R"},
|
2015-03-24 07:08:08 +01:00
|
|
|
|
{ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
|
2017-08-09 18:52:54 +02:00
|
|
|
|
0xfad0f080, 0xfff0f0f0, "crc32cb\t%8-11R, %16-19R, %0-3R"},
|
2015-03-24 07:08:08 +01:00
|
|
|
|
{ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
|
2017-08-09 18:52:54 +02:00
|
|
|
|
0xfad0f090, 0xfff0f0f0, "crc32ch\t%8-11R, %16-19R, %0-3R"},
|
2015-03-24 07:08:08 +01:00
|
|
|
|
{ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
|
2017-08-09 18:52:54 +02:00
|
|
|
|
0xfad0f0a0, 0xfff0f0f0, "crc32cw\t%8-11R, %16-19R, %0-3R"},
|
2013-03-11 12:09:33 +01:00
|
|
|
|
|
2018-07-11 19:05:34 +02:00
|
|
|
|
/* Speculation Barriers. */
|
|
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8014, 0xffffffff, "csdb"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3bf8f40, 0xffffffff, "ssbb"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3bf8f44, 0xffffffff, "pssbb"},
|
|
|
|
|
|
|
2006-02-24 Paul Brook <paul@codesourcery.com>
gas/
* config/arm/tc-arm.c (arm_ext_v6_notm, arm_ext_div, arm_ext_v7,
arm_ext_v7a, arm_ext_v7r, arm_ext_v7m): New variables.
(struct asm_barrier_opt): Define.
(arm_v7m_psr_hsh, arm_barrier_opt_hsh): New variables.
(parse_psr): Accept V7M psr names.
(parse_barrier): New function.
(enum operand_parse_code): Add OP_oBARRIER.
(parse_operands): Implement OP_oBARRIER.
(do_barrier): New function.
(do_dbg, do_pli, do_t_barrier, do_t_dbg, do_t_div): New functions.
(do_t_cpsi): Add V7M restrictions.
(do_t_mrs, do_t_msr): Validate V7M variants.
(md_assemble): Check for NULL variants.
(v7m_psrs, barrier_opt_names): New tables.
(insns): Add V7 instructions. Mark V6 instructions absent from V7M.
(md_begin): Initialize arm_v7m_psr_hsh and arm_barrier_opt_hsh.
(arm_cpu_option_table): Add Cortex-M3, R4 and A8.
(arm_arch_option_table): Add armv7, armv7a, armv7r and armv7m.
(struct cpu_arch_ver_table): Define.
(cpu_arch_ver): New.
(aeabi_set_public_attributes): Use cpu_arch_ver. Set
Tag_CPU_arch_profile.
* doc/c-arm.texi: Document new cpu and arch options.
gas/testsuite/
* gas/arm/thumb32.d: Fix expected msr and mrs output.
* gas/arm/arch7.d: New test.
* gas/arm/arch7.s: New test.
* gas/arm/arch7m-bad.l: New test.
* gas/arm/arch7m-bad.d: New test.
* gas/arm/arch7m-bad.s: New test.
include/opcode/
* arm.h: Add V7 feature bits.
opcodes/
* arm-dis.c (arm_opcodes): Add V7 instructions.
(thumb32_opcodes): Ditto. Handle V7M MSR/MRS variants.
(print_arm_address): New function.
(print_insn_arm): Use it. Add 'P' and 'U' cases.
(psr_name): New function.
(print_insn_thumb32): Add 'U', 'C' and 'D' cases.
2006-02-24 16:36:36 +01:00
|
|
|
|
/* V7 instructions. */
|
2015-03-24 07:08:08 +01:00
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf910f000, 0xff70f000, "pli%c\t%a"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf3af80f0, 0xfffffff0, "dbg%c\t#%0-3d"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xf3bf8f51, 0xfffffff3, "dmb%c\t%U"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xf3bf8f41, 0xfffffff3, "dsb%c\t%U"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf3bf8f50, 0xfffffff0, "dmb%c\t%U"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf3bf8f40, 0xfffffff0, "dsb%c\t%U"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf3bf8f60, 0xfffffff0, "isb%c\t%U"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_DIV),
|
|
|
|
|
|
0xfb90f0f0, 0xfff0f0f0, "sdiv%c\t%8-11r, %16-19r, %0-3r"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_DIV),
|
|
|
|
|
|
0xfbb0f0f0, 0xfff0f0f0, "udiv%c\t%8-11r, %16-19r, %0-3r"},
|
2006-02-24 Paul Brook <paul@codesourcery.com>
gas/
* config/arm/tc-arm.c (arm_ext_v6_notm, arm_ext_div, arm_ext_v7,
arm_ext_v7a, arm_ext_v7r, arm_ext_v7m): New variables.
(struct asm_barrier_opt): Define.
(arm_v7m_psr_hsh, arm_barrier_opt_hsh): New variables.
(parse_psr): Accept V7M psr names.
(parse_barrier): New function.
(enum operand_parse_code): Add OP_oBARRIER.
(parse_operands): Implement OP_oBARRIER.
(do_barrier): New function.
(do_dbg, do_pli, do_t_barrier, do_t_dbg, do_t_div): New functions.
(do_t_cpsi): Add V7M restrictions.
(do_t_mrs, do_t_msr): Validate V7M variants.
(md_assemble): Check for NULL variants.
(v7m_psrs, barrier_opt_names): New tables.
(insns): Add V7 instructions. Mark V6 instructions absent from V7M.
(md_begin): Initialize arm_v7m_psr_hsh and arm_barrier_opt_hsh.
(arm_cpu_option_table): Add Cortex-M3, R4 and A8.
(arm_arch_option_table): Add armv7, armv7a, armv7r and armv7m.
(struct cpu_arch_ver_table): Define.
(cpu_arch_ver): New.
(aeabi_set_public_attributes): Use cpu_arch_ver. Set
Tag_CPU_arch_profile.
* doc/c-arm.texi: Document new cpu and arch options.
gas/testsuite/
* gas/arm/thumb32.d: Fix expected msr and mrs output.
* gas/arm/arch7.d: New test.
* gas/arm/arch7.s: New test.
* gas/arm/arch7m-bad.l: New test.
* gas/arm/arch7m-bad.d: New test.
* gas/arm/arch7m-bad.s: New test.
include/opcode/
* arm.h: Add V7 feature bits.
opcodes/
* arm-dis.c (arm_opcodes): Add V7 instructions.
(thumb32_opcodes): Ditto. Handle V7M MSR/MRS variants.
(print_arm_address): New function.
(print_insn_arm): Use it. Add 'P' and 'U' cases.
(psr_name): New function.
(print_insn_thumb32): Add 'U', 'C' and 'D' cases.
2006-02-24 16:36:36 +01:00
|
|
|
|
|
2010-09-23 17:52:19 +02:00
|
|
|
|
/* Virtualization Extension instructions. */
|
2015-03-24 07:08:08 +01:00
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT), 0xf7e08000, 0xfff0f000, "hvc%c\t%V"},
|
2010-09-23 17:52:19 +02:00
|
|
|
|
/* We skip ERET as that is SUBS pc, lr, #0. */
|
|
|
|
|
|
|
2010-09-23 17:18:19 +02:00
|
|
|
|
/* MP Extension instructions. */
|
2015-03-24 07:08:08 +01:00
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_MP), 0xf830f000, 0xff70f000, "pldw%c\t%a"},
|
2010-09-23 17:18:19 +02:00
|
|
|
|
|
2010-09-23 17:26:24 +02:00
|
|
|
|
/* Security extension instructions. */
|
2015-03-24 07:08:08 +01:00
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_SEC), 0xf7f08000, 0xfff0f000, "smc%c\t%K"},
|
2010-09-23 17:26:24 +02:00
|
|
|
|
|
2005-09-02 Paul Brook <paul@codesourcery.com>
bfd/
* libbdf.h: Regenerate.
* bfd-in2.h: Regenerate.
* reloc.c: Add BFD_RELOC_ARM_T32_CP_OFF_IMM and
BFD_RELOC_ARM_T32_CP_OFF_IMM_S2.
gas/
* config/tc-arm.c (encode_arm_cp_address): Use
BFD_RELOC_ARM_T32_CP_OFF_IMM in thumb mode.
(do_iwmmxt_wldstbh): Use BFD_RELOC_ARM_T32_CP_OFF_IMM_S2 in thumb
mode.
(md_assemble): Only allow coprocessor instructions when Thumb-2 is
available.
(cCE, cC3): Define.
(insns): Use them for coprocessor instructions.
(md_pcrel_from_section): Handle BFD_RELOC_ARM_T32_CP_OFF_IMM.
(get_thumb32_insn): New function.
(put_thumb32_insn): New function.
(md_apply_fix): Handle BFD_RELOC_ARM_T32_CP_OFF_IMM and
BFD_RELOC_ARM_T32_CP_OFF_IMM_S2.
gas/testsuite/
* gas/arm/vfp-bad_t2.d, gas/arm/vfp-bad_t2.l, arm/vfp-bad_t2.s,
gas/arm/vfp1_t2.d, gas/arm/vfp1_t2.s, gas/arm/vfp1xD_t2.d,
gas/arm/vfp1xD_t2.s, gas/arm/vfp2_t2.d, gas/arm/vfp2_t2.s): New files.
opcodes/
* arm-dis.c (coprocessor_opcodes): New.
(arm_opcodes, thumb32_opcodes): Remove coprocessor insns.
(print_insn_coprocessor): New function.
(print_insn_arm): Use print_insn_coprocessor. Remove coprocessor
format characters.
(print_insn_thumb32): Use print_insn_coprocessor.
2005-09-02 15:12:45 +02:00
|
|
|
|
/* Instructions defined in the basic V6T2 set. */
|
2015-03-24 07:08:08 +01:00
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8000, 0xffffffff, "nop%c.w"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8001, 0xffffffff, "yield%c.w"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8002, 0xffffffff, "wfe%c.w"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8003, 0xffffffff, "wfi%c.w"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8004, 0xffffffff, "sev%c.w"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
|
|
|
|
|
|
0xf3af8000, 0xffffff00, "nop%c.w\t{%0-7d}"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf7f0a000, 0xfff0f000, "udf%c.w\t%H"},
|
|
|
|
|
|
|
2015-12-24 10:26:08 +01:00
|
|
|
|
{ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
|
2015-03-24 07:08:08 +01:00
|
|
|
|
0xf3bf8f2f, 0xffffffff, "clrex%c"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
|
|
|
|
|
|
0xf3af8400, 0xffffff1f, "cpsie.w\t%7'a%6'i%5'f%X"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
|
|
|
|
|
|
0xf3af8600, 0xffffff1f, "cpsid.w\t%7'a%6'i%5'f%X"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
|
|
|
|
|
|
0xf3c08f00, 0xfff0ffff, "bxj%c\t%16-19r%x"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
|
|
|
|
|
|
0xe810c000, 0xffd0ffff, "rfedb%c\t%16-19r%21'!"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
|
|
|
|
|
|
0xe990c000, 0xffd0ffff, "rfeia%c\t%16-19r%21'!"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
|
|
|
|
|
|
0xf3e08000, 0xffe0f000, "mrs%c\t%8-11r, %D"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
|
|
|
|
|
|
0xf3af8100, 0xffffffe0, "cps\t#%0-4d%X"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
|
|
|
|
|
|
0xe8d0f000, 0xfff0fff0, "tbb%c\t[%16-19r, %0-3r]%x"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
|
|
|
|
|
|
0xe8d0f010, 0xfff0fff0, "tbh%c\t[%16-19r, %0-3r, lsl #1]%x"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
|
|
|
|
|
|
0xf3af8500, 0xffffff00, "cpsie\t%7'a%6'i%5'f, #%0-4d%X"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
|
|
|
|
|
|
0xf3af8700, 0xffffff00, "cpsid\t%7'a%6'i%5'f, #%0-4d%X"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
|
|
|
|
|
|
0xf3de8f00, 0xffffff00, "subs%c\tpc, lr, #%0-7d"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
|
|
|
|
|
|
0xf3808000, 0xffe0f000, "msr%c\t%C, %16-19r"},
|
2015-12-24 10:26:08 +01:00
|
|
|
|
{ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
|
2015-03-24 07:08:08 +01:00
|
|
|
|
0xe8500f00, 0xfff00fff, "ldrex%c\t%12-15r, [%16-19r]"},
|
2015-12-24 10:26:08 +01:00
|
|
|
|
{ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
|
2015-03-24 07:08:08 +01:00
|
|
|
|
0xe8d00f4f, 0xfff00fef, "ldrex%4?hb%c\t%12-15r, [%16-19r]"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
|
|
|
|
|
|
0xe800c000, 0xffd0ffe0, "srsdb%c\t%16-19r%21'!, #%0-4d"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
|
|
|
|
|
|
0xe980c000, 0xffd0ffe0, "srsia%c\t%16-19r%21'!, #%0-4d"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
|
|
|
|
|
|
0xfa0ff080, 0xfffff0c0, "sxth%c.w\t%8-11r, %0-3r%R"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
|
|
|
|
|
|
0xfa1ff080, 0xfffff0c0, "uxth%c.w\t%8-11r, %0-3r%R"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
|
|
|
|
|
|
0xfa2ff080, 0xfffff0c0, "sxtb16%c\t%8-11r, %0-3r%R"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
|
|
|
|
|
|
0xfa3ff080, 0xfffff0c0, "uxtb16%c\t%8-11r, %0-3r%R"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
|
|
|
|
|
|
0xfa4ff080, 0xfffff0c0, "sxtb%c.w\t%8-11r, %0-3r%R"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
|
|
|
|
|
|
0xfa5ff080, 0xfffff0c0, "uxtb%c.w\t%8-11r, %0-3r%R"},
|
2015-12-24 10:26:08 +01:00
|
|
|
|
{ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
|
2015-03-24 07:08:08 +01:00
|
|
|
|
0xe8400000, 0xfff000ff, "strex%c\t%8-11r, %12-15r, [%16-19r]"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
|
|
|
|
|
|
0xe8d0007f, 0xfff000ff, "ldrexd%c\t%12-15r, %8-11r, [%16-19r]"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
|
|
|
|
|
|
0xfa80f000, 0xfff0f0f0, "sadd8%c\t%8-11r, %16-19r, %0-3r"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
|
|
|
|
|
|
0xfa80f010, 0xfff0f0f0, "qadd8%c\t%8-11r, %16-19r, %0-3r"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
|
|
|
|
|
|
0xfa80f020, 0xfff0f0f0, "shadd8%c\t%8-11r, %16-19r, %0-3r"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
|
|
|
|
|
|
0xfa80f040, 0xfff0f0f0, "uadd8%c\t%8-11r, %16-19r, %0-3r"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
|
|
|
|
|
|
0xfa80f050, 0xfff0f0f0, "uqadd8%c\t%8-11r, %16-19r, %0-3r"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
|
|
|
|
|
|
0xfa80f060, 0xfff0f0f0, "uhadd8%c\t%8-11r, %16-19r, %0-3r"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
|
|
|
|
|
|
0xfa80f080, 0xfff0f0f0, "qadd%c\t%8-11r, %0-3r, %16-19r"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
|
|
|
|
|
|
0xfa80f090, 0xfff0f0f0, "qdadd%c\t%8-11r, %0-3r, %16-19r"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
|
|
|
|
|
|
0xfa80f0a0, 0xfff0f0f0, "qsub%c\t%8-11r, %0-3r, %16-19r"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
|
|
|
|
|
|
0xfa80f0b0, 0xfff0f0f0, "qdsub%c\t%8-11r, %0-3r, %16-19r"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
|
|
|
|
|
|
0xfa90f000, 0xfff0f0f0, "sadd16%c\t%8-11r, %16-19r, %0-3r"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
|
|
|
|
|
|
0xfa90f010, 0xfff0f0f0, "qadd16%c\t%8-11r, %16-19r, %0-3r"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
|
|
|
|
|
|
0xfa90f020, 0xfff0f0f0, "shadd16%c\t%8-11r, %16-19r, %0-3r"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
|
|
|
|
|
|
0xfa90f040, 0xfff0f0f0, "uadd16%c\t%8-11r, %16-19r, %0-3r"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
|
|
|
|
|
|
0xfa90f050, 0xfff0f0f0, "uqadd16%c\t%8-11r, %16-19r, %0-3r"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
|
|
|
|
|
|
0xfa90f060, 0xfff0f0f0, "uhadd16%c\t%8-11r, %16-19r, %0-3r"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
|
|
|
|
|
|
0xfa90f080, 0xfff0f0f0, "rev%c.w\t%8-11r, %16-19r"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
|
|
|
|
|
|
0xfa90f090, 0xfff0f0f0, "rev16%c.w\t%8-11r, %16-19r"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
|
|
|
|
|
|
0xfa90f0a0, 0xfff0f0f0, "rbit%c\t%8-11r, %16-19r"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
|
|
|
|
|
|
0xfa90f0b0, 0xfff0f0f0, "revsh%c.w\t%8-11r, %16-19r"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
|
|
|
|
|
|
0xfaa0f000, 0xfff0f0f0, "sasx%c\t%8-11r, %16-19r, %0-3r"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
|
|
|
|
|
|
0xfaa0f010, 0xfff0f0f0, "qasx%c\t%8-11r, %16-19r, %0-3r"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
|
|
|
|
|
|
0xfaa0f020, 0xfff0f0f0, "shasx%c\t%8-11r, %16-19r, %0-3r"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
|
|
|
|
|
|
0xfaa0f040, 0xfff0f0f0, "uasx%c\t%8-11r, %16-19r, %0-3r"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
|
|
|
|
|
|
0xfaa0f050, 0xfff0f0f0, "uqasx%c\t%8-11r, %16-19r, %0-3r"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
|
|
|
|
|
|
0xfaa0f060, 0xfff0f0f0, "uhasx%c\t%8-11r, %16-19r, %0-3r"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
|
|
|
|
|
|
0xfaa0f080, 0xfff0f0f0, "sel%c\t%8-11r, %16-19r, %0-3r"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
|
|
|
|
|
|
0xfab0f080, 0xfff0f0f0, "clz%c\t%8-11r, %16-19r"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
|
|
|
|
|
|
0xfac0f000, 0xfff0f0f0, "ssub8%c\t%8-11r, %16-19r, %0-3r"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
|
|
|
|
|
|
0xfac0f010, 0xfff0f0f0, "qsub8%c\t%8-11r, %16-19r, %0-3r"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
|
|
|
|
|
|
0xfac0f020, 0xfff0f0f0, "shsub8%c\t%8-11r, %16-19r, %0-3r"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
|
|
|
|
|
|
0xfac0f040, 0xfff0f0f0, "usub8%c\t%8-11r, %16-19r, %0-3r"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
|
|
|
|
|
|
0xfac0f050, 0xfff0f0f0, "uqsub8%c\t%8-11r, %16-19r, %0-3r"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
|
|
|
|
|
|
0xfac0f060, 0xfff0f0f0, "uhsub8%c\t%8-11r, %16-19r, %0-3r"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
|
|
|
|
|
|
0xfad0f000, 0xfff0f0f0, "ssub16%c\t%8-11r, %16-19r, %0-3r"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
|
|
|
|
|
|
0xfad0f010, 0xfff0f0f0, "qsub16%c\t%8-11r, %16-19r, %0-3r"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
|
|
|
|
|
|
0xfad0f020, 0xfff0f0f0, "shsub16%c\t%8-11r, %16-19r, %0-3r"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
|
|
|
|
|
|
0xfad0f040, 0xfff0f0f0, "usub16%c\t%8-11r, %16-19r, %0-3r"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
|
|
|
|
|
|
0xfad0f050, 0xfff0f0f0, "uqsub16%c\t%8-11r, %16-19r, %0-3r"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
|
|
|
|
|
|
0xfad0f060, 0xfff0f0f0, "uhsub16%c\t%8-11r, %16-19r, %0-3r"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
|
|
|
|
|
|
0xfae0f000, 0xfff0f0f0, "ssax%c\t%8-11r, %16-19r, %0-3r"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
|
|
|
|
|
|
0xfae0f010, 0xfff0f0f0, "qsax%c\t%8-11r, %16-19r, %0-3r"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
|
|
|
|
|
|
0xfae0f020, 0xfff0f0f0, "shsax%c\t%8-11r, %16-19r, %0-3r"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
|
|
|
|
|
|
0xfae0f040, 0xfff0f0f0, "usax%c\t%8-11r, %16-19r, %0-3r"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
|
|
|
|
|
|
0xfae0f050, 0xfff0f0f0, "uqsax%c\t%8-11r, %16-19r, %0-3r"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
|
|
|
|
|
|
0xfae0f060, 0xfff0f0f0, "uhsax%c\t%8-11r, %16-19r, %0-3r"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
|
|
|
|
|
|
0xfb00f000, 0xfff0f0f0, "mul%c.w\t%8-11r, %16-19r, %0-3r"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
|
|
|
|
|
|
0xfb70f000, 0xfff0f0f0, "usad8%c\t%8-11r, %16-19r, %0-3r"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
|
|
|
|
|
|
0xfa00f000, 0xffe0f0f0, "lsl%20's%c.w\t%8-11R, %16-19R, %0-3R"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
|
|
|
|
|
|
0xfa20f000, 0xffe0f0f0, "lsr%20's%c.w\t%8-11R, %16-19R, %0-3R"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
|
|
|
|
|
|
0xfa40f000, 0xffe0f0f0, "asr%20's%c.w\t%8-11R, %16-19R, %0-3R"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
|
|
|
|
|
|
0xfa60f000, 0xffe0f0f0, "ror%20's%c.w\t%8-11r, %16-19r, %0-3r"},
|
2015-12-24 10:26:08 +01:00
|
|
|
|
{ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
|
2015-03-24 07:08:08 +01:00
|
|
|
|
0xe8c00f40, 0xfff00fe0, "strex%4?hb%c\t%0-3r, %12-15r, [%16-19r]"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
|
2015-04-15 18:44:03 +02:00
|
|
|
|
0xf3200000, 0xfff0f0e0, "ssat16%c\t%8-11r, #%0-4D, %16-19r"},
|
2015-03-24 07:08:08 +01:00
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
|
|
|
|
|
|
0xf3a00000, 0xfff0f0e0, "usat16%c\t%8-11r, #%0-4d, %16-19r"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
|
|
|
|
|
|
0xfb20f000, 0xfff0f0e0, "smuad%4'x%c\t%8-11r, %16-19r, %0-3r"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
|
|
|
|
|
|
0xfb30f000, 0xfff0f0e0, "smulw%4?tb%c\t%8-11r, %16-19r, %0-3r"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
|
|
|
|
|
|
0xfb40f000, 0xfff0f0e0, "smusd%4'x%c\t%8-11r, %16-19r, %0-3r"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
|
|
|
|
|
|
0xfb50f000, 0xfff0f0e0, "smmul%4'r%c\t%8-11r, %16-19r, %0-3r"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
|
|
|
|
|
|
0xfa00f080, 0xfff0f0c0, "sxtah%c\t%8-11r, %16-19r, %0-3r%R"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
|
|
|
|
|
|
0xfa10f080, 0xfff0f0c0, "uxtah%c\t%8-11r, %16-19r, %0-3r%R"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
|
|
|
|
|
|
0xfa20f080, 0xfff0f0c0, "sxtab16%c\t%8-11r, %16-19r, %0-3r%R"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
|
|
|
|
|
|
0xfa30f080, 0xfff0f0c0, "uxtab16%c\t%8-11r, %16-19r, %0-3r%R"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
|
|
|
|
|
|
0xfa40f080, 0xfff0f0c0, "sxtab%c\t%8-11r, %16-19r, %0-3r%R"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
|
|
|
|
|
|
0xfa50f080, 0xfff0f0c0, "uxtab%c\t%8-11r, %16-19r, %0-3r%R"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
|
|
|
|
|
|
0xfb10f000, 0xfff0f0c0, "smul%5?tb%4?tb%c\t%8-11r, %16-19r, %0-3r"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
|
|
|
|
|
|
0xf36f0000, 0xffff8020, "bfc%c\t%8-11r, %E"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
|
|
|
|
|
|
0xea100f00, 0xfff08f00, "tst%c.w\t%16-19r, %S"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
|
|
|
|
|
|
0xea900f00, 0xfff08f00, "teq%c\t%16-19r, %S"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
|
|
|
|
|
|
0xeb100f00, 0xfff08f00, "cmn%c.w\t%16-19r, %S"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
|
|
|
|
|
|
0xebb00f00, 0xfff08f00, "cmp%c.w\t%16-19r, %S"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
|
|
|
|
|
|
0xf0100f00, 0xfbf08f00, "tst%c.w\t%16-19r, %M"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
|
|
|
|
|
|
0xf0900f00, 0xfbf08f00, "teq%c\t%16-19r, %M"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
|
|
|
|
|
|
0xf1100f00, 0xfbf08f00, "cmn%c.w\t%16-19r, %M"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
|
|
|
|
|
|
0xf1b00f00, 0xfbf08f00, "cmp%c.w\t%16-19r, %M"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
|
|
|
|
|
|
0xea4f0000, 0xffef8000, "mov%20's%c.w\t%8-11r, %S"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
|
|
|
|
|
|
0xea6f0000, 0xffef8000, "mvn%20's%c.w\t%8-11r, %S"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
|
|
|
|
|
|
0xe8c00070, 0xfff000f0, "strexd%c\t%0-3r, %12-15r, %8-11r, [%16-19r]"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
|
|
|
|
|
|
0xfb000000, 0xfff000f0, "mla%c\t%8-11r, %16-19r, %0-3r, %12-15r"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
|
|
|
|
|
|
0xfb000010, 0xfff000f0, "mls%c\t%8-11r, %16-19r, %0-3r, %12-15r"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
|
|
|
|
|
|
0xfb700000, 0xfff000f0, "usada8%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
|
|
|
|
|
|
0xfb800000, 0xfff000f0, "smull%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
|
|
|
|
|
|
0xfba00000, 0xfff000f0, "umull%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
|
|
|
|
|
|
0xfbc00000, 0xfff000f0, "smlal%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
|
|
|
|
|
|
0xfbe00000, 0xfff000f0, "umlal%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
|
|
|
|
|
|
0xfbe00060, 0xfff000f0, "umaal%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
|
2015-12-24 10:26:08 +01:00
|
|
|
|
{ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
|
2015-03-24 07:08:08 +01:00
|
|
|
|
0xe8500f00, 0xfff00f00, "ldrex%c\t%12-15r, [%16-19r, #%0-7W]"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
|
|
|
|
|
|
0xf04f0000, 0xfbef8000, "mov%20's%c.w\t%8-11r, %M"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
|
|
|
|
|
|
0xf06f0000, 0xfbef8000, "mvn%20's%c.w\t%8-11r, %M"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
|
|
|
|
|
|
0xf810f000, 0xff70f000, "pld%c\t%a"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
|
|
|
|
|
|
0xfb200000, 0xfff000e0, "smlad%4'x%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
|
|
|
|
|
|
0xfb300000, 0xfff000e0, "smlaw%4?tb%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
|
|
|
|
|
|
0xfb400000, 0xfff000e0, "smlsd%4'x%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
|
|
|
|
|
|
0xfb500000, 0xfff000e0, "smmla%4'r%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
|
|
|
|
|
|
0xfb600000, 0xfff000e0, "smmls%4'r%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
|
|
|
|
|
|
0xfbc000c0, 0xfff000e0, "smlald%4'x%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
|
|
|
|
|
|
0xfbd000c0, 0xfff000e0, "smlsld%4'x%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
|
|
|
|
|
|
0xeac00000, 0xfff08030, "pkhbt%c\t%8-11r, %16-19r, %S"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
|
|
|
|
|
|
0xeac00020, 0xfff08030, "pkhtb%c\t%8-11r, %16-19r, %S"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
|
|
|
|
|
|
0xf3400000, 0xfff08020, "sbfx%c\t%8-11r, %16-19r, %F"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
|
|
|
|
|
|
0xf3c00000, 0xfff08020, "ubfx%c\t%8-11r, %16-19r, %F"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
|
|
|
|
|
|
0xf8000e00, 0xff900f00, "str%wt%c\t%12-15r, %a"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
|
|
|
|
|
|
0xfb100000, 0xfff000c0,
|
|
|
|
|
|
"smla%5?tb%4?tb%c\t%8-11r, %16-19r, %0-3r, %12-15r"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
|
|
|
|
|
|
0xfbc00080, 0xfff000c0,
|
|
|
|
|
|
"smlal%5?tb%4?tb%c\t%12-15r, %8-11r, %16-19r, %0-3r"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
|
|
|
|
|
|
0xf3600000, 0xfff08020, "bfi%c\t%8-11r, %16-19r, %E"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
|
|
|
|
|
|
0xf8100e00, 0xfe900f00, "ldr%wt%c\t%12-15r, %a"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
|
2015-04-15 18:44:03 +02:00
|
|
|
|
0xf3000000, 0xffd08020, "ssat%c\t%8-11r, #%0-4D, %16-19r%s"},
|
2015-03-24 07:08:08 +01:00
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
|
|
|
|
|
|
0xf3800000, 0xffd08020, "usat%c\t%8-11r, #%0-4d, %16-19r%s"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
|
|
|
|
|
|
0xf2000000, 0xfbf08000, "addw%c\t%8-11r, %16-19r, %I"},
|
2015-12-24 10:26:08 +01:00
|
|
|
|
{ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
|
2015-03-24 07:08:08 +01:00
|
|
|
|
0xf2400000, 0xfbf08000, "movw%c\t%8-11r, %J"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
|
|
|
|
|
|
0xf2a00000, 0xfbf08000, "subw%c\t%8-11r, %16-19r, %I"},
|
2015-12-24 10:26:08 +01:00
|
|
|
|
{ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
|
2015-03-24 07:08:08 +01:00
|
|
|
|
0xf2c00000, 0xfbf08000, "movt%c\t%8-11r, %J"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
|
|
|
|
|
|
0xea000000, 0xffe08000, "and%20's%c.w\t%8-11r, %16-19r, %S"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
|
|
|
|
|
|
0xea200000, 0xffe08000, "bic%20's%c.w\t%8-11r, %16-19r, %S"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
|
|
|
|
|
|
0xea400000, 0xffe08000, "orr%20's%c.w\t%8-11r, %16-19r, %S"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
|
|
|
|
|
|
0xea600000, 0xffe08000, "orn%20's%c\t%8-11r, %16-19r, %S"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
|
|
|
|
|
|
0xea800000, 0xffe08000, "eor%20's%c.w\t%8-11r, %16-19r, %S"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
|
|
|
|
|
|
0xeb000000, 0xffe08000, "add%20's%c.w\t%8-11r, %16-19r, %S"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
|
|
|
|
|
|
0xeb400000, 0xffe08000, "adc%20's%c.w\t%8-11r, %16-19r, %S"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
|
|
|
|
|
|
0xeb600000, 0xffe08000, "sbc%20's%c.w\t%8-11r, %16-19r, %S"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
|
|
|
|
|
|
0xeba00000, 0xffe08000, "sub%20's%c.w\t%8-11r, %16-19r, %S"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
|
|
|
|
|
|
0xebc00000, 0xffe08000, "rsb%20's%c\t%8-11r, %16-19r, %S"},
|
2015-12-24 10:26:08 +01:00
|
|
|
|
{ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
|
2015-03-24 07:08:08 +01:00
|
|
|
|
0xe8400000, 0xfff00000, "strex%c\t%8-11r, %12-15r, [%16-19r, #%0-7W]"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
|
|
|
|
|
|
0xf0000000, 0xfbe08000, "and%20's%c.w\t%8-11r, %16-19r, %M"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
|
|
|
|
|
|
0xf0200000, 0xfbe08000, "bic%20's%c.w\t%8-11r, %16-19r, %M"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
|
|
|
|
|
|
0xf0400000, 0xfbe08000, "orr%20's%c.w\t%8-11r, %16-19r, %M"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
|
|
|
|
|
|
0xf0600000, 0xfbe08000, "orn%20's%c\t%8-11r, %16-19r, %M"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
|
|
|
|
|
|
0xf0800000, 0xfbe08000, "eor%20's%c.w\t%8-11r, %16-19r, %M"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
|
|
|
|
|
|
0xf1000000, 0xfbe08000, "add%20's%c.w\t%8-11r, %16-19r, %M"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
|
|
|
|
|
|
0xf1400000, 0xfbe08000, "adc%20's%c.w\t%8-11r, %16-19r, %M"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
|
|
|
|
|
|
0xf1600000, 0xfbe08000, "sbc%20's%c.w\t%8-11r, %16-19r, %M"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
|
|
|
|
|
|
0xf1a00000, 0xfbe08000, "sub%20's%c.w\t%8-11r, %16-19r, %M"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
|
|
|
|
|
|
0xf1c00000, 0xfbe08000, "rsb%20's%c\t%8-11r, %16-19r, %M"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
|
|
|
|
|
|
0xe8800000, 0xffd00000, "stmia%c.w\t%16-19r%21'!, %m"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
|
|
|
|
|
|
0xe8900000, 0xffd00000, "ldmia%c.w\t%16-19r%21'!, %m"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
|
|
|
|
|
|
0xe9000000, 0xffd00000, "stmdb%c\t%16-19r%21'!, %m"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
|
|
|
|
|
|
0xe9100000, 0xffd00000, "ldmdb%c\t%16-19r%21'!, %m"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
|
|
|
|
|
|
0xe9c00000, 0xffd000ff, "strd%c\t%12-15r, %8-11r, [%16-19r]"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
|
|
|
|
|
|
0xe9d00000, 0xffd000ff, "ldrd%c\t%12-15r, %8-11r, [%16-19r]"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
|
|
|
|
|
|
0xe9400000, 0xff500000,
|
|
|
|
|
|
"strd%c\t%12-15r, %8-11r, [%16-19r, #%23`-%0-7W]%21'!%L"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
|
|
|
|
|
|
0xe9500000, 0xff500000,
|
|
|
|
|
|
"ldrd%c\t%12-15r, %8-11r, [%16-19r, #%23`-%0-7W]%21'!%L"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
|
|
|
|
|
|
0xe8600000, 0xff700000,
|
|
|
|
|
|
"strd%c\t%12-15r, %8-11r, [%16-19r], #%23`-%0-7W%L"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
|
|
|
|
|
|
0xe8700000, 0xff700000,
|
|
|
|
|
|
"ldrd%c\t%12-15r, %8-11r, [%16-19r], #%23`-%0-7W%L"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
|
|
|
|
|
|
0xf8000000, 0xff100000, "str%w%c.w\t%12-15r, %a"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
|
|
|
|
|
|
0xf8100000, 0xfe100000, "ldr%w%c.w\t%12-15r, %a"},
|
include/elf:
* arm.h: Import complete list of official relocation names
and numbers from AAELF. Define FAKE_RELOCs for old names.
Remove a few old names no longer used anywhere.
bfd:
* elf32-arm.c: Wherever possible, use official reloc names
from AAELF.
(elf32_arm_howto_table, elf32_arm_tls_gd32_howto)
(elf32_arm_tls_ldo32_howto, elf32_arm_tls_ldm32_howto)
(elf32_arm_tls_le32_howto, elf32_arm_tls_ie32_howto)
(elf32_arm_vtinherit_howto, elf32_arm_vtentry_howto)
(elf32_arm_pc11_howto, elf32_arm_thm_pc9_howto, elf32_arm_got_prel)
(elf32_arm_r_howto): Replace with elf32_arm_howto_table_1,
elf32_arm_howto_table_2, and elf32_arm_howto_table_3.
Add many new relocations from AAELF.
(elf32_arm_howto_from_type): Update to match.
(elf32_arm_reloc_map): Add entries for R_ARM_THM_JUMP24,
R_ARM_THM_JUMP11, R_ARM_THM_JUMP19, R_ARM_THM_JUMP8,
R_ARM_THM_JUMP6, R_ARM_GNU_VTINHERIT, and R_ARM_GNU_VTENTRY.
(elf32_arm_reloc_type_lookup): Use elf32_arm_howto_from_type.
(elf32_arm_final_link_relocate): Add support for
R_ARM_THM_JUMP24, R_ARM_THM_JUMP19, R_ARM_THM_JUMP6. Remove
case entries redundant with default.
* reloc.c: Reorganize ARM relocations. Add Thumb
assembler-internal relocations BFD_RELOC_ARM_T32_OFFSET_U8,
BFD_RELOC_ARM_T32_OFFSET_IMM, BFD_RELOC_ARM_T32_IMMEDIATE.
Add visible relocations BFD_RELOC_THUMB_PCREL_BRANCH7,
BFD_RELOC_THUMB_BRANCH20, BFD_RELOC_THUMB_BRANCH25.
Delete unused relocations BFD_RELOC_ARM_GOT12, BFD_RELOC_ARM_COPY.
* bfd-in2.h, libbfd.h: Regenerate.
opcodes:
* arm-dis.c (thumb_opcodes): Add disassembly for V6T2 16-bit
instructions. Adjust disassembly of some opcodes to match
unified syntax.
(thumb32_opcodes): New table.
(print_insn_thumb): Rename print_insn_thumb16; don't handle
two-halfword branches here.
(print_insn_thumb32): New function.
(print_insn): Choose among print_insn_arm, print_insn_thumb16,
and print_insn_thumb32. Be consistent about order of
halfwords when printing 32-bit instructions.
gas:
* hash.c (hash_lookup): Add len parameter. All callers changed.
(hash_find_n): New interface.
* hash.h: Prototype hash_find_n.
* sb.c: Include as.h.
(scrub_from_sb, sb_to_scrub, scrub_position): New statics.
(sb_scrub_and_add_sb): New interface.
* sb.h: Prototype sb_scrub_and_add_sb.
* input-scrub.c (input_scrub_include_sb): Use sb_scrub_and_add_sb.
* config/tc-arm.h (TC_FORCE_RELOCATION_LOCAL): Remove
reference to BFD_RELOC_ARM_GOT12 which is never generated.
* config/tc-arm.c: Rewrite, adding Thumb-2 support.
gas/testsuite:
* gas/arm/arm.exp: Convert all existing "gas_test" tests to
"run_dump_test" tests. Run more tests unconditionally. Run new tests.
* gas/arm/arch4t.s, gas/arm/arch6zk.s, gas/arm/arm3.s, gas/arm/arm6.s
* gas/arm/arm7dm.s, gas/arm/bignum1.s, gas/arm/float.s
* gas/arm/immed.s, gas/arm/iwmmxt.s, gas/arm/offset.s, gas/arm/thumb.s:
Adjust to work as a dump test.
* gas/arm/arch4t.d, gas/arm/arch6zk.d, gas/arm/arm3.d, gas/arm/arm6.d
* gas/arm/arm7dm.d, gas/arm/bignum1.d, gas/arm/float.d
* gas/arm/immed.d, gas/arm/iwmmxt.d, gas/arm/offset.d, gas/arm/thumb.d:
New files.
* gas/arm/armv1-bad.l, gas/arm/armv1-bad.s: Remove tests for
diagnostics that don't happen in the first pass anymore.
* gas/arm/iwmmxt-bad.l, gas/arm/r15-bad.l, gas/arm/req.l
* gas/arm/vfp-bad.l:
Update expected diagnostics.
* gas/arm/pic.d: Update expected reloc name.
* gas/arm/thumbv6.d: CPY no longer appears in disassembly.
* gas/arm/r15-bad.s: Avoid two-argument mul.
* gas/arm/req.s: Adjust comments.
* gas/arm/maverick.d, gas/arm/maverick.s: Avoid inappropriate
use of PC.
* gas/arm/macro-1.d, gas/arm/macro1.s
* gas/arm/t16-bad.l, gas/arm/t16-bad.s
* gas/arm/tcompat.d, gas/arm/tcompat.s
* gas/arm/tcompat2.d, gas/arm/tcompat2.s
* gas/arm/thumb32.d, gas/arm/thumb32.s
New test pair.
ld/testsuite:
* ld-arm/mixed-app.d: Adjust expected disassembly a little.
2005-05-18 07:40:12 +02:00
|
|
|
|
|
|
|
|
|
|
/* Filter out Bcc with cond=E or F, which are used for other instructions. */
|
2015-03-24 07:08:08 +01:00
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
|
|
|
|
|
|
0xf3c08000, 0xfbc0d000, "undefined (bcc, cond=0xF)"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
|
|
|
|
|
|
0xf3808000, 0xfbc0d000, "undefined (bcc, cond=0xE)"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
|
|
|
|
|
|
0xf0008000, 0xf800d000, "b%22-25c.w\t%b%X"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
|
|
|
|
|
|
0xf0009000, 0xf800d000, "b%c.w\t%B%x"},
|
include/elf:
* arm.h: Import complete list of official relocation names
and numbers from AAELF. Define FAKE_RELOCs for old names.
Remove a few old names no longer used anywhere.
bfd:
* elf32-arm.c: Wherever possible, use official reloc names
from AAELF.
(elf32_arm_howto_table, elf32_arm_tls_gd32_howto)
(elf32_arm_tls_ldo32_howto, elf32_arm_tls_ldm32_howto)
(elf32_arm_tls_le32_howto, elf32_arm_tls_ie32_howto)
(elf32_arm_vtinherit_howto, elf32_arm_vtentry_howto)
(elf32_arm_pc11_howto, elf32_arm_thm_pc9_howto, elf32_arm_got_prel)
(elf32_arm_r_howto): Replace with elf32_arm_howto_table_1,
elf32_arm_howto_table_2, and elf32_arm_howto_table_3.
Add many new relocations from AAELF.
(elf32_arm_howto_from_type): Update to match.
(elf32_arm_reloc_map): Add entries for R_ARM_THM_JUMP24,
R_ARM_THM_JUMP11, R_ARM_THM_JUMP19, R_ARM_THM_JUMP8,
R_ARM_THM_JUMP6, R_ARM_GNU_VTINHERIT, and R_ARM_GNU_VTENTRY.
(elf32_arm_reloc_type_lookup): Use elf32_arm_howto_from_type.
(elf32_arm_final_link_relocate): Add support for
R_ARM_THM_JUMP24, R_ARM_THM_JUMP19, R_ARM_THM_JUMP6. Remove
case entries redundant with default.
* reloc.c: Reorganize ARM relocations. Add Thumb
assembler-internal relocations BFD_RELOC_ARM_T32_OFFSET_U8,
BFD_RELOC_ARM_T32_OFFSET_IMM, BFD_RELOC_ARM_T32_IMMEDIATE.
Add visible relocations BFD_RELOC_THUMB_PCREL_BRANCH7,
BFD_RELOC_THUMB_BRANCH20, BFD_RELOC_THUMB_BRANCH25.
Delete unused relocations BFD_RELOC_ARM_GOT12, BFD_RELOC_ARM_COPY.
* bfd-in2.h, libbfd.h: Regenerate.
opcodes:
* arm-dis.c (thumb_opcodes): Add disassembly for V6T2 16-bit
instructions. Adjust disassembly of some opcodes to match
unified syntax.
(thumb32_opcodes): New table.
(print_insn_thumb): Rename print_insn_thumb16; don't handle
two-halfword branches here.
(print_insn_thumb32): New function.
(print_insn): Choose among print_insn_arm, print_insn_thumb16,
and print_insn_thumb32. Be consistent about order of
halfwords when printing 32-bit instructions.
gas:
* hash.c (hash_lookup): Add len parameter. All callers changed.
(hash_find_n): New interface.
* hash.h: Prototype hash_find_n.
* sb.c: Include as.h.
(scrub_from_sb, sb_to_scrub, scrub_position): New statics.
(sb_scrub_and_add_sb): New interface.
* sb.h: Prototype sb_scrub_and_add_sb.
* input-scrub.c (input_scrub_include_sb): Use sb_scrub_and_add_sb.
* config/tc-arm.h (TC_FORCE_RELOCATION_LOCAL): Remove
reference to BFD_RELOC_ARM_GOT12 which is never generated.
* config/tc-arm.c: Rewrite, adding Thumb-2 support.
gas/testsuite:
* gas/arm/arm.exp: Convert all existing "gas_test" tests to
"run_dump_test" tests. Run more tests unconditionally. Run new tests.
* gas/arm/arch4t.s, gas/arm/arch6zk.s, gas/arm/arm3.s, gas/arm/arm6.s
* gas/arm/arm7dm.s, gas/arm/bignum1.s, gas/arm/float.s
* gas/arm/immed.s, gas/arm/iwmmxt.s, gas/arm/offset.s, gas/arm/thumb.s:
Adjust to work as a dump test.
* gas/arm/arch4t.d, gas/arm/arch6zk.d, gas/arm/arm3.d, gas/arm/arm6.d
* gas/arm/arm7dm.d, gas/arm/bignum1.d, gas/arm/float.d
* gas/arm/immed.d, gas/arm/iwmmxt.d, gas/arm/offset.d, gas/arm/thumb.d:
New files.
* gas/arm/armv1-bad.l, gas/arm/armv1-bad.s: Remove tests for
diagnostics that don't happen in the first pass anymore.
* gas/arm/iwmmxt-bad.l, gas/arm/r15-bad.l, gas/arm/req.l
* gas/arm/vfp-bad.l:
Update expected diagnostics.
* gas/arm/pic.d: Update expected reloc name.
* gas/arm/thumbv6.d: CPY no longer appears in disassembly.
* gas/arm/r15-bad.s: Avoid two-argument mul.
* gas/arm/req.s: Adjust comments.
* gas/arm/maverick.d, gas/arm/maverick.s: Avoid inappropriate
use of PC.
* gas/arm/macro-1.d, gas/arm/macro1.s
* gas/arm/t16-bad.l, gas/arm/t16-bad.s
* gas/arm/tcompat.d, gas/arm/tcompat.s
* gas/arm/tcompat2.d, gas/arm/tcompat2.s
* gas/arm/thumb32.d, gas/arm/thumb32.s
New test pair.
ld/testsuite:
* ld-arm/mixed-app.d: Adjust expected disassembly a little.
2005-05-18 07:40:12 +02:00
|
|
|
|
|
2005-09-02 Paul Brook <paul@codesourcery.com>
bfd/
* libbdf.h: Regenerate.
* bfd-in2.h: Regenerate.
* reloc.c: Add BFD_RELOC_ARM_T32_CP_OFF_IMM and
BFD_RELOC_ARM_T32_CP_OFF_IMM_S2.
gas/
* config/tc-arm.c (encode_arm_cp_address): Use
BFD_RELOC_ARM_T32_CP_OFF_IMM in thumb mode.
(do_iwmmxt_wldstbh): Use BFD_RELOC_ARM_T32_CP_OFF_IMM_S2 in thumb
mode.
(md_assemble): Only allow coprocessor instructions when Thumb-2 is
available.
(cCE, cC3): Define.
(insns): Use them for coprocessor instructions.
(md_pcrel_from_section): Handle BFD_RELOC_ARM_T32_CP_OFF_IMM.
(get_thumb32_insn): New function.
(put_thumb32_insn): New function.
(md_apply_fix): Handle BFD_RELOC_ARM_T32_CP_OFF_IMM and
BFD_RELOC_ARM_T32_CP_OFF_IMM_S2.
gas/testsuite/
* gas/arm/vfp-bad_t2.d, gas/arm/vfp-bad_t2.l, arm/vfp-bad_t2.s,
gas/arm/vfp1_t2.d, gas/arm/vfp1_t2.s, gas/arm/vfp1xD_t2.d,
gas/arm/vfp1xD_t2.s, gas/arm/vfp2_t2.d, gas/arm/vfp2_t2.s): New files.
opcodes/
* arm-dis.c (coprocessor_opcodes): New.
(arm_opcodes, thumb32_opcodes): Remove coprocessor insns.
(print_insn_coprocessor): New function.
(print_insn_arm): Use print_insn_coprocessor. Remove coprocessor
format characters.
(print_insn_thumb32): Use print_insn_coprocessor.
2005-09-02 15:12:45 +02:00
|
|
|
|
/* These have been 32-bit since the invention of Thumb. */
|
2015-03-24 07:08:08 +01:00
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
|
|
|
|
|
|
0xf000c000, 0xf800d001, "blx%c\t%B%x"},
|
|
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
|
|
|
|
|
|
0xf000d000, 0xf800d000, "bl%c\t%B%x"},
|
2005-09-02 Paul Brook <paul@codesourcery.com>
bfd/
* libbdf.h: Regenerate.
* bfd-in2.h: Regenerate.
* reloc.c: Add BFD_RELOC_ARM_T32_CP_OFF_IMM and
BFD_RELOC_ARM_T32_CP_OFF_IMM_S2.
gas/
* config/tc-arm.c (encode_arm_cp_address): Use
BFD_RELOC_ARM_T32_CP_OFF_IMM in thumb mode.
(do_iwmmxt_wldstbh): Use BFD_RELOC_ARM_T32_CP_OFF_IMM_S2 in thumb
mode.
(md_assemble): Only allow coprocessor instructions when Thumb-2 is
available.
(cCE, cC3): Define.
(insns): Use them for coprocessor instructions.
(md_pcrel_from_section): Handle BFD_RELOC_ARM_T32_CP_OFF_IMM.
(get_thumb32_insn): New function.
(put_thumb32_insn): New function.
(md_apply_fix): Handle BFD_RELOC_ARM_T32_CP_OFF_IMM and
BFD_RELOC_ARM_T32_CP_OFF_IMM_S2.
gas/testsuite/
* gas/arm/vfp-bad_t2.d, gas/arm/vfp-bad_t2.l, arm/vfp-bad_t2.s,
gas/arm/vfp1_t2.d, gas/arm/vfp1_t2.s, gas/arm/vfp1xD_t2.d,
gas/arm/vfp1xD_t2.s, gas/arm/vfp2_t2.d, gas/arm/vfp2_t2.s): New files.
opcodes/
* arm-dis.c (coprocessor_opcodes): New.
(arm_opcodes, thumb32_opcodes): Remove coprocessor insns.
(print_insn_coprocessor): New function.
(print_insn_arm): Use print_insn_coprocessor. Remove coprocessor
format characters.
(print_insn_thumb32): Use print_insn_coprocessor.
2005-09-02 15:12:45 +02:00
|
|
|
|
|
|
|
|
|
|
/* Fallback. */
|
2015-03-24 07:08:08 +01:00
|
|
|
|
{ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
|
|
|
|
|
|
0x00000000, 0x00000000, UNDEFINED_INSTRUCTION},
|
|
|
|
|
|
{ARM_FEATURE_CORE_LOW (0), 0, 0, 0}
|
2005-09-02 Paul Brook <paul@codesourcery.com>
bfd/
* libbdf.h: Regenerate.
* bfd-in2.h: Regenerate.
* reloc.c: Add BFD_RELOC_ARM_T32_CP_OFF_IMM and
BFD_RELOC_ARM_T32_CP_OFF_IMM_S2.
gas/
* config/tc-arm.c (encode_arm_cp_address): Use
BFD_RELOC_ARM_T32_CP_OFF_IMM in thumb mode.
(do_iwmmxt_wldstbh): Use BFD_RELOC_ARM_T32_CP_OFF_IMM_S2 in thumb
mode.
(md_assemble): Only allow coprocessor instructions when Thumb-2 is
available.
(cCE, cC3): Define.
(insns): Use them for coprocessor instructions.
(md_pcrel_from_section): Handle BFD_RELOC_ARM_T32_CP_OFF_IMM.
(get_thumb32_insn): New function.
(put_thumb32_insn): New function.
(md_apply_fix): Handle BFD_RELOC_ARM_T32_CP_OFF_IMM and
BFD_RELOC_ARM_T32_CP_OFF_IMM_S2.
gas/testsuite/
* gas/arm/vfp-bad_t2.d, gas/arm/vfp-bad_t2.l, arm/vfp-bad_t2.s,
gas/arm/vfp1_t2.d, gas/arm/vfp1_t2.s, gas/arm/vfp1xD_t2.d,
gas/arm/vfp1xD_t2.s, gas/arm/vfp2_t2.d, gas/arm/vfp2_t2.s): New files.
opcodes/
* arm-dis.c (coprocessor_opcodes): New.
(arm_opcodes, thumb32_opcodes): Remove coprocessor insns.
(print_insn_coprocessor): New function.
(print_insn_arm): Use print_insn_coprocessor. Remove coprocessor
format characters.
(print_insn_thumb32): Use print_insn_coprocessor.
2005-09-02 15:12:45 +02:00
|
|
|
|
};
|
2009-12-17 10:52:18 +01:00
|
|
|
|
|
2005-09-02 Paul Brook <paul@codesourcery.com>
bfd/
* libbdf.h: Regenerate.
* bfd-in2.h: Regenerate.
* reloc.c: Add BFD_RELOC_ARM_T32_CP_OFF_IMM and
BFD_RELOC_ARM_T32_CP_OFF_IMM_S2.
gas/
* config/tc-arm.c (encode_arm_cp_address): Use
BFD_RELOC_ARM_T32_CP_OFF_IMM in thumb mode.
(do_iwmmxt_wldstbh): Use BFD_RELOC_ARM_T32_CP_OFF_IMM_S2 in thumb
mode.
(md_assemble): Only allow coprocessor instructions when Thumb-2 is
available.
(cCE, cC3): Define.
(insns): Use them for coprocessor instructions.
(md_pcrel_from_section): Handle BFD_RELOC_ARM_T32_CP_OFF_IMM.
(get_thumb32_insn): New function.
(put_thumb32_insn): New function.
(md_apply_fix): Handle BFD_RELOC_ARM_T32_CP_OFF_IMM and
BFD_RELOC_ARM_T32_CP_OFF_IMM_S2.
gas/testsuite/
* gas/arm/vfp-bad_t2.d, gas/arm/vfp-bad_t2.l, arm/vfp-bad_t2.s,
gas/arm/vfp1_t2.d, gas/arm/vfp1_t2.s, gas/arm/vfp1xD_t2.d,
gas/arm/vfp1xD_t2.s, gas/arm/vfp2_t2.d, gas/arm/vfp2_t2.s): New files.
opcodes/
* arm-dis.c (coprocessor_opcodes): New.
(arm_opcodes, thumb32_opcodes): Remove coprocessor insns.
(print_insn_coprocessor): New function.
(print_insn_arm): Use print_insn_coprocessor. Remove coprocessor
format characters.
(print_insn_thumb32): Use print_insn_coprocessor.
2005-09-02 15:12:45 +02:00
|
|
|
|
static const char *const arm_conditional[] =
|
|
|
|
|
|
{"eq", "ne", "cs", "cc", "mi", "pl", "vs", "vc",
|
2006-06-07 16:08:19 +02:00
|
|
|
|
"hi", "ls", "ge", "lt", "gt", "le", "al", "<und>", ""};
|
2005-09-02 Paul Brook <paul@codesourcery.com>
bfd/
* libbdf.h: Regenerate.
* bfd-in2.h: Regenerate.
* reloc.c: Add BFD_RELOC_ARM_T32_CP_OFF_IMM and
BFD_RELOC_ARM_T32_CP_OFF_IMM_S2.
gas/
* config/tc-arm.c (encode_arm_cp_address): Use
BFD_RELOC_ARM_T32_CP_OFF_IMM in thumb mode.
(do_iwmmxt_wldstbh): Use BFD_RELOC_ARM_T32_CP_OFF_IMM_S2 in thumb
mode.
(md_assemble): Only allow coprocessor instructions when Thumb-2 is
available.
(cCE, cC3): Define.
(insns): Use them for coprocessor instructions.
(md_pcrel_from_section): Handle BFD_RELOC_ARM_T32_CP_OFF_IMM.
(get_thumb32_insn): New function.
(put_thumb32_insn): New function.
(md_apply_fix): Handle BFD_RELOC_ARM_T32_CP_OFF_IMM and
BFD_RELOC_ARM_T32_CP_OFF_IMM_S2.
gas/testsuite/
* gas/arm/vfp-bad_t2.d, gas/arm/vfp-bad_t2.l, arm/vfp-bad_t2.s,
gas/arm/vfp1_t2.d, gas/arm/vfp1_t2.s, gas/arm/vfp1xD_t2.d,
gas/arm/vfp1xD_t2.s, gas/arm/vfp2_t2.d, gas/arm/vfp2_t2.s): New files.
opcodes/
* arm-dis.c (coprocessor_opcodes): New.
(arm_opcodes, thumb32_opcodes): Remove coprocessor insns.
(print_insn_coprocessor): New function.
(print_insn_arm): Use print_insn_coprocessor. Remove coprocessor
format characters.
(print_insn_thumb32): Use print_insn_coprocessor.
2005-09-02 15:12:45 +02:00
|
|
|
|
|
|
|
|
|
|
static const char *const arm_fp_const[] =
|
|
|
|
|
|
{"0.0", "1.0", "2.0", "3.0", "4.0", "5.0", "0.5", "10.0"};
|
|
|
|
|
|
|
|
|
|
|
|
static const char *const arm_shift[] =
|
|
|
|
|
|
{"lsl", "lsr", "asr", "ror"};
|
|
|
|
|
|
|
|
|
|
|
|
typedef struct
|
|
|
|
|
|
{
|
|
|
|
|
|
const char *name;
|
|
|
|
|
|
const char *description;
|
|
|
|
|
|
const char *reg_names[16];
|
|
|
|
|
|
}
|
|
|
|
|
|
arm_regname;
|
|
|
|
|
|
|
|
|
|
|
|
static const arm_regname regnames[] =
|
|
|
|
|
|
{
|
2017-02-28 19:32:07 +01:00
|
|
|
|
{ "reg-names-raw", N_("Select raw register names"),
|
2005-09-02 Paul Brook <paul@codesourcery.com>
bfd/
* libbdf.h: Regenerate.
* bfd-in2.h: Regenerate.
* reloc.c: Add BFD_RELOC_ARM_T32_CP_OFF_IMM and
BFD_RELOC_ARM_T32_CP_OFF_IMM_S2.
gas/
* config/tc-arm.c (encode_arm_cp_address): Use
BFD_RELOC_ARM_T32_CP_OFF_IMM in thumb mode.
(do_iwmmxt_wldstbh): Use BFD_RELOC_ARM_T32_CP_OFF_IMM_S2 in thumb
mode.
(md_assemble): Only allow coprocessor instructions when Thumb-2 is
available.
(cCE, cC3): Define.
(insns): Use them for coprocessor instructions.
(md_pcrel_from_section): Handle BFD_RELOC_ARM_T32_CP_OFF_IMM.
(get_thumb32_insn): New function.
(put_thumb32_insn): New function.
(md_apply_fix): Handle BFD_RELOC_ARM_T32_CP_OFF_IMM and
BFD_RELOC_ARM_T32_CP_OFF_IMM_S2.
gas/testsuite/
* gas/arm/vfp-bad_t2.d, gas/arm/vfp-bad_t2.l, arm/vfp-bad_t2.s,
gas/arm/vfp1_t2.d, gas/arm/vfp1_t2.s, gas/arm/vfp1xD_t2.d,
gas/arm/vfp1xD_t2.s, gas/arm/vfp2_t2.d, gas/arm/vfp2_t2.s): New files.
opcodes/
* arm-dis.c (coprocessor_opcodes): New.
(arm_opcodes, thumb32_opcodes): Remove coprocessor insns.
(print_insn_coprocessor): New function.
(print_insn_arm): Use print_insn_coprocessor. Remove coprocessor
format characters.
(print_insn_thumb32): Use print_insn_coprocessor.
2005-09-02 15:12:45 +02:00
|
|
|
|
{ "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"}},
|
2017-02-28 19:32:07 +01:00
|
|
|
|
{ "reg-names-gcc", N_("Select register names used by GCC"),
|
2005-09-02 Paul Brook <paul@codesourcery.com>
bfd/
* libbdf.h: Regenerate.
* bfd-in2.h: Regenerate.
* reloc.c: Add BFD_RELOC_ARM_T32_CP_OFF_IMM and
BFD_RELOC_ARM_T32_CP_OFF_IMM_S2.
gas/
* config/tc-arm.c (encode_arm_cp_address): Use
BFD_RELOC_ARM_T32_CP_OFF_IMM in thumb mode.
(do_iwmmxt_wldstbh): Use BFD_RELOC_ARM_T32_CP_OFF_IMM_S2 in thumb
mode.
(md_assemble): Only allow coprocessor instructions when Thumb-2 is
available.
(cCE, cC3): Define.
(insns): Use them for coprocessor instructions.
(md_pcrel_from_section): Handle BFD_RELOC_ARM_T32_CP_OFF_IMM.
(get_thumb32_insn): New function.
(put_thumb32_insn): New function.
(md_apply_fix): Handle BFD_RELOC_ARM_T32_CP_OFF_IMM and
BFD_RELOC_ARM_T32_CP_OFF_IMM_S2.
gas/testsuite/
* gas/arm/vfp-bad_t2.d, gas/arm/vfp-bad_t2.l, arm/vfp-bad_t2.s,
gas/arm/vfp1_t2.d, gas/arm/vfp1_t2.s, gas/arm/vfp1xD_t2.d,
gas/arm/vfp1xD_t2.s, gas/arm/vfp2_t2.d, gas/arm/vfp2_t2.s): New files.
opcodes/
* arm-dis.c (coprocessor_opcodes): New.
(arm_opcodes, thumb32_opcodes): Remove coprocessor insns.
(print_insn_coprocessor): New function.
(print_insn_arm): Use print_insn_coprocessor. Remove coprocessor
format characters.
(print_insn_thumb32): Use print_insn_coprocessor.
2005-09-02 15:12:45 +02:00
|
|
|
|
{ "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "sl", "fp", "ip", "sp", "lr", "pc" }},
|
2017-02-28 19:32:07 +01:00
|
|
|
|
{ "reg-names-std", N_("Select register names used in ARM's ISA documentation"),
|
2005-09-02 Paul Brook <paul@codesourcery.com>
bfd/
* libbdf.h: Regenerate.
* bfd-in2.h: Regenerate.
* reloc.c: Add BFD_RELOC_ARM_T32_CP_OFF_IMM and
BFD_RELOC_ARM_T32_CP_OFF_IMM_S2.
gas/
* config/tc-arm.c (encode_arm_cp_address): Use
BFD_RELOC_ARM_T32_CP_OFF_IMM in thumb mode.
(do_iwmmxt_wldstbh): Use BFD_RELOC_ARM_T32_CP_OFF_IMM_S2 in thumb
mode.
(md_assemble): Only allow coprocessor instructions when Thumb-2 is
available.
(cCE, cC3): Define.
(insns): Use them for coprocessor instructions.
(md_pcrel_from_section): Handle BFD_RELOC_ARM_T32_CP_OFF_IMM.
(get_thumb32_insn): New function.
(put_thumb32_insn): New function.
(md_apply_fix): Handle BFD_RELOC_ARM_T32_CP_OFF_IMM and
BFD_RELOC_ARM_T32_CP_OFF_IMM_S2.
gas/testsuite/
* gas/arm/vfp-bad_t2.d, gas/arm/vfp-bad_t2.l, arm/vfp-bad_t2.s,
gas/arm/vfp1_t2.d, gas/arm/vfp1_t2.s, gas/arm/vfp1xD_t2.d,
gas/arm/vfp1xD_t2.s, gas/arm/vfp2_t2.d, gas/arm/vfp2_t2.s): New files.
opcodes/
* arm-dis.c (coprocessor_opcodes): New.
(arm_opcodes, thumb32_opcodes): Remove coprocessor insns.
(print_insn_coprocessor): New function.
(print_insn_arm): Use print_insn_coprocessor. Remove coprocessor
format characters.
(print_insn_thumb32): Use print_insn_coprocessor.
2005-09-02 15:12:45 +02:00
|
|
|
|
{ "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", "r12", "sp", "lr", "pc" }},
|
2017-02-28 19:32:07 +01:00
|
|
|
|
{ "force-thumb", N_("Assume all insns are Thumb insns"), {NULL} },
|
|
|
|
|
|
{ "no-force-thumb", N_("Examine preceding label to determine an insn's type"), {NULL} },
|
|
|
|
|
|
{ "reg-names-apcs", N_("Select register names used in the APCS"),
|
2005-09-02 Paul Brook <paul@codesourcery.com>
bfd/
* libbdf.h: Regenerate.
* bfd-in2.h: Regenerate.
* reloc.c: Add BFD_RELOC_ARM_T32_CP_OFF_IMM and
BFD_RELOC_ARM_T32_CP_OFF_IMM_S2.
gas/
* config/tc-arm.c (encode_arm_cp_address): Use
BFD_RELOC_ARM_T32_CP_OFF_IMM in thumb mode.
(do_iwmmxt_wldstbh): Use BFD_RELOC_ARM_T32_CP_OFF_IMM_S2 in thumb
mode.
(md_assemble): Only allow coprocessor instructions when Thumb-2 is
available.
(cCE, cC3): Define.
(insns): Use them for coprocessor instructions.
(md_pcrel_from_section): Handle BFD_RELOC_ARM_T32_CP_OFF_IMM.
(get_thumb32_insn): New function.
(put_thumb32_insn): New function.
(md_apply_fix): Handle BFD_RELOC_ARM_T32_CP_OFF_IMM and
BFD_RELOC_ARM_T32_CP_OFF_IMM_S2.
gas/testsuite/
* gas/arm/vfp-bad_t2.d, gas/arm/vfp-bad_t2.l, arm/vfp-bad_t2.s,
gas/arm/vfp1_t2.d, gas/arm/vfp1_t2.s, gas/arm/vfp1xD_t2.d,
gas/arm/vfp1xD_t2.s, gas/arm/vfp2_t2.d, gas/arm/vfp2_t2.s): New files.
opcodes/
* arm-dis.c (coprocessor_opcodes): New.
(arm_opcodes, thumb32_opcodes): Remove coprocessor insns.
(print_insn_coprocessor): New function.
(print_insn_arm): Use print_insn_coprocessor. Remove coprocessor
format characters.
(print_insn_thumb32): Use print_insn_coprocessor.
2005-09-02 15:12:45 +02:00
|
|
|
|
{ "a1", "a2", "a3", "a4", "v1", "v2", "v3", "v4", "v5", "v6", "sl", "fp", "ip", "sp", "lr", "pc" }},
|
2017-02-28 19:32:07 +01:00
|
|
|
|
{ "reg-names-atpcs", N_("Select register names used in the ATPCS"),
|
2005-09-02 Paul Brook <paul@codesourcery.com>
bfd/
* libbdf.h: Regenerate.
* bfd-in2.h: Regenerate.
* reloc.c: Add BFD_RELOC_ARM_T32_CP_OFF_IMM and
BFD_RELOC_ARM_T32_CP_OFF_IMM_S2.
gas/
* config/tc-arm.c (encode_arm_cp_address): Use
BFD_RELOC_ARM_T32_CP_OFF_IMM in thumb mode.
(do_iwmmxt_wldstbh): Use BFD_RELOC_ARM_T32_CP_OFF_IMM_S2 in thumb
mode.
(md_assemble): Only allow coprocessor instructions when Thumb-2 is
available.
(cCE, cC3): Define.
(insns): Use them for coprocessor instructions.
(md_pcrel_from_section): Handle BFD_RELOC_ARM_T32_CP_OFF_IMM.
(get_thumb32_insn): New function.
(put_thumb32_insn): New function.
(md_apply_fix): Handle BFD_RELOC_ARM_T32_CP_OFF_IMM and
BFD_RELOC_ARM_T32_CP_OFF_IMM_S2.
gas/testsuite/
* gas/arm/vfp-bad_t2.d, gas/arm/vfp-bad_t2.l, arm/vfp-bad_t2.s,
gas/arm/vfp1_t2.d, gas/arm/vfp1_t2.s, gas/arm/vfp1xD_t2.d,
gas/arm/vfp1xD_t2.s, gas/arm/vfp2_t2.d, gas/arm/vfp2_t2.s): New files.
opcodes/
* arm-dis.c (coprocessor_opcodes): New.
(arm_opcodes, thumb32_opcodes): Remove coprocessor insns.
(print_insn_coprocessor): New function.
(print_insn_arm): Use print_insn_coprocessor. Remove coprocessor
format characters.
(print_insn_thumb32): Use print_insn_coprocessor.
2005-09-02 15:12:45 +02:00
|
|
|
|
{ "a1", "a2", "a3", "a4", "v1", "v2", "v3", "v4", "v5", "v6", "v7", "v8", "IP", "SP", "LR", "PC" }},
|
2017-02-28 19:32:07 +01:00
|
|
|
|
{ "reg-names-special-atpcs", N_("Select special register names used in the ATPCS"),
|
|
|
|
|
|
{ "a1", "a2", "a3", "a4", "v1", "v2", "v3", "WR", "v5", "SB", "SL", "FP", "IP", "SP", "LR", "PC" }}
|
2005-09-02 Paul Brook <paul@codesourcery.com>
bfd/
* libbdf.h: Regenerate.
* bfd-in2.h: Regenerate.
* reloc.c: Add BFD_RELOC_ARM_T32_CP_OFF_IMM and
BFD_RELOC_ARM_T32_CP_OFF_IMM_S2.
gas/
* config/tc-arm.c (encode_arm_cp_address): Use
BFD_RELOC_ARM_T32_CP_OFF_IMM in thumb mode.
(do_iwmmxt_wldstbh): Use BFD_RELOC_ARM_T32_CP_OFF_IMM_S2 in thumb
mode.
(md_assemble): Only allow coprocessor instructions when Thumb-2 is
available.
(cCE, cC3): Define.
(insns): Use them for coprocessor instructions.
(md_pcrel_from_section): Handle BFD_RELOC_ARM_T32_CP_OFF_IMM.
(get_thumb32_insn): New function.
(put_thumb32_insn): New function.
(md_apply_fix): Handle BFD_RELOC_ARM_T32_CP_OFF_IMM and
BFD_RELOC_ARM_T32_CP_OFF_IMM_S2.
gas/testsuite/
* gas/arm/vfp-bad_t2.d, gas/arm/vfp-bad_t2.l, arm/vfp-bad_t2.s,
gas/arm/vfp1_t2.d, gas/arm/vfp1_t2.s, gas/arm/vfp1xD_t2.d,
gas/arm/vfp1xD_t2.s, gas/arm/vfp2_t2.d, gas/arm/vfp2_t2.s): New files.
opcodes/
* arm-dis.c (coprocessor_opcodes): New.
(arm_opcodes, thumb32_opcodes): Remove coprocessor insns.
(print_insn_coprocessor): New function.
(print_insn_arm): Use print_insn_coprocessor. Remove coprocessor
format characters.
(print_insn_thumb32): Use print_insn_coprocessor.
2005-09-02 15:12:45 +02:00
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
|
|
static const char *const iwmmxt_wwnames[] =
|
|
|
|
|
|
{"b", "h", "w", "d"};
|
|
|
|
|
|
|
|
|
|
|
|
static const char *const iwmmxt_wwssnames[] =
|
bfd/
2006-09-26 Mark Shinwell <shinwell@codesourcery.com>
Joseph Myers <joseph@codesourcery.com>
Ian Lance Taylor <ian@wasabisystems.com>
Ben Elliston <bje@wasabisystems.com>
* archures.c: Add definition for bfd_mach_arm_iWMMXt2.
* cpu-arm.c (processors): Add bfd_mach_arm_iWMMXt2.
(arch_info_struct, bfd_arm_update_notes): Likewise.
(architectures): Likewise.
(bfd_arm_merge_machines): Check for iWMMXt2.
* bfd-in2.h: Rebuild.
gas/
2006-09-26 Mark Shinwell <shinwell@codesourcery.com>
Joseph Myers <joseph@codesourcery.com>
Ian Lance Taylor <ian@wasabisystems.com>
Ben Elliston <bje@wasabisystems.com>
* config/tc-arm.c (arm_cext_iwmmxt2): New.
(enum operand_parse_code): New code OP_RIWR_I32z.
(parse_operands): Handle OP_RIWR_I32z.
(do_iwmmxt_wmerge): New function.
(do_iwmmxt_wldstd): Handle iwmmxt2 case where second operand is
a register.
(do_iwmmxt_wrwrwr_or_imm5): New function.
(insns): Mark instructions as RIWR_I32z as appropriate.
Also add torvsc<b,h,w>, wabs<b,h,w>, wabsdiff<b,h,w>,
waddbhus<l,m>, waddhc, waddwc, waddsubhx, wavg4{r}, wmaddu{x,n},
wmadds{x,n}, wmerge, wmiaxy{n}, wmiawxy{n}, wmul<sm,um>{r},
wmulw<um,sm,l>{r}, wqmiaxy{n}, wqmulm{r}, wqmulwm{r}, wsubaddhx.
(md_begin): Handle IWMMXT2.
(arm_cpus): Add iwmmxt2.
(arm_extensions): Likewise.
(arm_archs): Likewise.
gas/testsuite/
2006-09-26 Mark Shinwell <shinwell@codesourcery.com>
Joseph Myers <joseph@codesourcery.com>
Ian Lance Taylor <ian@wasabisystems.com>
Ben Elliston <bje@wasabisystems.com>
* gas/arm/iwmmxt2.s: New file.
* gas/arm/iwmmxt2.d: New file.
include/opcode/
2006-09-26 Mark Shinwell <shinwell@codesourcery.com>
Joseph Myers <joseph@codesourcery.com>
Ian Lance Taylor <ian@wasabisystems.com>
Ben Elliston <bje@wasabisystems.com>
* arm.h (ARM_CEXT_IWMMXT2, ARM_ARCH_IWMMXT2): Define.
opcodes/
2006-09-26 Mark Shinwell <shinwell@codesourcery.com>
Joseph Myers <joseph@codesourcery.com>
Ian Lance Taylor <ian@wasabisystems.com>
Ben Elliston <bje@wasabisystems.com>
* arm-dis.c (coprocessor_opcodes): The X-qualifier to WMADD may
only be used with the default multiply-add operation, so if N is
set, don't bother printing X. Add new iwmmxt instructions.
(IWMMXT_INSN_COUNT): Update.
(iwmmxt_wwssnames): Qualify "wwss" names at index 2, 6, 10 and 14
with a 'c' suffix.
(print_insn_coprocessor): Check for iWMMXt2. Handle format
specifiers 'r', 'i'.
2006-09-26 14:04:45 +02:00
|
|
|
|
{"b", "bus", "bc", "bss",
|
|
|
|
|
|
"h", "hus", "hc", "hss",
|
|
|
|
|
|
"w", "wus", "wc", "wss",
|
|
|
|
|
|
"d", "dus", "dc", "dss"
|
2005-09-02 Paul Brook <paul@codesourcery.com>
bfd/
* libbdf.h: Regenerate.
* bfd-in2.h: Regenerate.
* reloc.c: Add BFD_RELOC_ARM_T32_CP_OFF_IMM and
BFD_RELOC_ARM_T32_CP_OFF_IMM_S2.
gas/
* config/tc-arm.c (encode_arm_cp_address): Use
BFD_RELOC_ARM_T32_CP_OFF_IMM in thumb mode.
(do_iwmmxt_wldstbh): Use BFD_RELOC_ARM_T32_CP_OFF_IMM_S2 in thumb
mode.
(md_assemble): Only allow coprocessor instructions when Thumb-2 is
available.
(cCE, cC3): Define.
(insns): Use them for coprocessor instructions.
(md_pcrel_from_section): Handle BFD_RELOC_ARM_T32_CP_OFF_IMM.
(get_thumb32_insn): New function.
(put_thumb32_insn): New function.
(md_apply_fix): Handle BFD_RELOC_ARM_T32_CP_OFF_IMM and
BFD_RELOC_ARM_T32_CP_OFF_IMM_S2.
gas/testsuite/
* gas/arm/vfp-bad_t2.d, gas/arm/vfp-bad_t2.l, arm/vfp-bad_t2.s,
gas/arm/vfp1_t2.d, gas/arm/vfp1_t2.s, gas/arm/vfp1xD_t2.d,
gas/arm/vfp1xD_t2.s, gas/arm/vfp2_t2.d, gas/arm/vfp2_t2.s): New files.
opcodes/
* arm-dis.c (coprocessor_opcodes): New.
(arm_opcodes, thumb32_opcodes): Remove coprocessor insns.
(print_insn_coprocessor): New function.
(print_insn_arm): Use print_insn_coprocessor. Remove coprocessor
format characters.
(print_insn_thumb32): Use print_insn_coprocessor.
2005-09-02 15:12:45 +02:00
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
|
|
static const char *const iwmmxt_regnames[] =
|
|
|
|
|
|
{ "wr0", "wr1", "wr2", "wr3", "wr4", "wr5", "wr6", "wr7",
|
|
|
|
|
|
"wr8", "wr9", "wr10", "wr11", "wr12", "wr13", "wr14", "wr15"
|
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
|
|
static const char *const iwmmxt_cregnames[] =
|
|
|
|
|
|
{ "wcid", "wcon", "wcssf", "wcasf", "reserved", "reserved", "reserved", "reserved",
|
|
|
|
|
|
"wcgr0", "wcgr1", "wcgr2", "wcgr3", "reserved", "reserved", "reserved", "reserved"
|
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
|
|
/* Default to GCC register name set. */
|
|
|
|
|
|
static unsigned int regname_selected = 1;
|
|
|
|
|
|
|
2017-02-28 19:32:07 +01:00
|
|
|
|
#define NUM_ARM_OPTIONS ARRAY_SIZE (regnames)
|
2005-09-02 Paul Brook <paul@codesourcery.com>
bfd/
* libbdf.h: Regenerate.
* bfd-in2.h: Regenerate.
* reloc.c: Add BFD_RELOC_ARM_T32_CP_OFF_IMM and
BFD_RELOC_ARM_T32_CP_OFF_IMM_S2.
gas/
* config/tc-arm.c (encode_arm_cp_address): Use
BFD_RELOC_ARM_T32_CP_OFF_IMM in thumb mode.
(do_iwmmxt_wldstbh): Use BFD_RELOC_ARM_T32_CP_OFF_IMM_S2 in thumb
mode.
(md_assemble): Only allow coprocessor instructions when Thumb-2 is
available.
(cCE, cC3): Define.
(insns): Use them for coprocessor instructions.
(md_pcrel_from_section): Handle BFD_RELOC_ARM_T32_CP_OFF_IMM.
(get_thumb32_insn): New function.
(put_thumb32_insn): New function.
(md_apply_fix): Handle BFD_RELOC_ARM_T32_CP_OFF_IMM and
BFD_RELOC_ARM_T32_CP_OFF_IMM_S2.
gas/testsuite/
* gas/arm/vfp-bad_t2.d, gas/arm/vfp-bad_t2.l, arm/vfp-bad_t2.s,
gas/arm/vfp1_t2.d, gas/arm/vfp1_t2.s, gas/arm/vfp1xD_t2.d,
gas/arm/vfp1xD_t2.s, gas/arm/vfp2_t2.d, gas/arm/vfp2_t2.s): New files.
opcodes/
* arm-dis.c (coprocessor_opcodes): New.
(arm_opcodes, thumb32_opcodes): Remove coprocessor insns.
(print_insn_coprocessor): New function.
(print_insn_arm): Use print_insn_coprocessor. Remove coprocessor
format characters.
(print_insn_thumb32): Use print_insn_coprocessor.
2005-09-02 15:12:45 +02:00
|
|
|
|
#define arm_regnames regnames[regname_selected].reg_names
|
|
|
|
|
|
|
|
|
|
|
|
static bfd_boolean force_thumb = FALSE;
|
|
|
|
|
|
|
2006-06-07 16:08:19 +02:00
|
|
|
|
/* Current IT instruction state. This contains the same state as the IT
|
|
|
|
|
|
bits in the CPSR. */
|
|
|
|
|
|
static unsigned int ifthen_state;
|
|
|
|
|
|
/* IT state for the next instruction. */
|
|
|
|
|
|
static unsigned int ifthen_next_state;
|
|
|
|
|
|
/* The address of the insn for which the IT state is valid. */
|
|
|
|
|
|
static bfd_vma ifthen_address;
|
|
|
|
|
|
#define IFTHEN_COND ((ifthen_state >> 4) & 0xf)
|
2012-08-24 09:59:05 +02:00
|
|
|
|
/* Indicates that the current Conditional state is unconditional or outside
|
|
|
|
|
|
an IT block. */
|
|
|
|
|
|
#define COND_UNCOND 16
|
2006-06-07 16:08:19 +02:00
|
|
|
|
|
2005-09-02 Paul Brook <paul@codesourcery.com>
bfd/
* libbdf.h: Regenerate.
* bfd-in2.h: Regenerate.
* reloc.c: Add BFD_RELOC_ARM_T32_CP_OFF_IMM and
BFD_RELOC_ARM_T32_CP_OFF_IMM_S2.
gas/
* config/tc-arm.c (encode_arm_cp_address): Use
BFD_RELOC_ARM_T32_CP_OFF_IMM in thumb mode.
(do_iwmmxt_wldstbh): Use BFD_RELOC_ARM_T32_CP_OFF_IMM_S2 in thumb
mode.
(md_assemble): Only allow coprocessor instructions when Thumb-2 is
available.
(cCE, cC3): Define.
(insns): Use them for coprocessor instructions.
(md_pcrel_from_section): Handle BFD_RELOC_ARM_T32_CP_OFF_IMM.
(get_thumb32_insn): New function.
(put_thumb32_insn): New function.
(md_apply_fix): Handle BFD_RELOC_ARM_T32_CP_OFF_IMM and
BFD_RELOC_ARM_T32_CP_OFF_IMM_S2.
gas/testsuite/
* gas/arm/vfp-bad_t2.d, gas/arm/vfp-bad_t2.l, arm/vfp-bad_t2.s,
gas/arm/vfp1_t2.d, gas/arm/vfp1_t2.s, gas/arm/vfp1xD_t2.d,
gas/arm/vfp1xD_t2.s, gas/arm/vfp2_t2.d, gas/arm/vfp2_t2.s): New files.
opcodes/
* arm-dis.c (coprocessor_opcodes): New.
(arm_opcodes, thumb32_opcodes): Remove coprocessor insns.
(print_insn_coprocessor): New function.
(print_insn_arm): Use print_insn_coprocessor. Remove coprocessor
format characters.
(print_insn_thumb32): Use print_insn_coprocessor.
2005-09-02 15:12:45 +02:00
|
|
|
|
|
|
|
|
|
|
/* Functions. */
|
|
|
|
|
|
|
2006-04-26 17:40:55 +02:00
|
|
|
|
/* Decode a bitfield of the form matching regexp (N(-N)?,)*N(-N)?.
|
|
|
|
|
|
Returns pointer to following character of the format string and
|
|
|
|
|
|
fills in *VALUEP and *WIDTHP with the extracted value and number of
|
2009-06-30 13:57:05 +02:00
|
|
|
|
bits extracted. WIDTHP can be NULL. */
|
2006-04-26 17:40:55 +02:00
|
|
|
|
|
|
|
|
|
|
static const char *
|
2009-06-30 13:57:05 +02:00
|
|
|
|
arm_decode_bitfield (const char *ptr,
|
|
|
|
|
|
unsigned long insn,
|
|
|
|
|
|
unsigned long *valuep,
|
|
|
|
|
|
int *widthp)
|
2006-04-26 17:40:55 +02:00
|
|
|
|
{
|
|
|
|
|
|
unsigned long value = 0;
|
|
|
|
|
|
int width = 0;
|
2015-08-12 13:45:07 +02:00
|
|
|
|
|
|
|
|
|
|
do
|
2006-04-26 17:40:55 +02:00
|
|
|
|
{
|
|
|
|
|
|
int start, end;
|
|
|
|
|
|
int bits;
|
|
|
|
|
|
|
|
|
|
|
|
for (start = 0; *ptr >= '0' && *ptr <= '9'; ptr++)
|
|
|
|
|
|
start = start * 10 + *ptr - '0';
|
|
|
|
|
|
if (*ptr == '-')
|
|
|
|
|
|
for (end = 0, ptr++; *ptr >= '0' && *ptr <= '9'; ptr++)
|
|
|
|
|
|
end = end * 10 + *ptr - '0';
|
|
|
|
|
|
else
|
|
|
|
|
|
end = start;
|
|
|
|
|
|
bits = end - start;
|
|
|
|
|
|
if (bits < 0)
|
|
|
|
|
|
abort ();
|
|
|
|
|
|
value |= ((insn >> start) & ((2ul << bits) - 1)) << width;
|
|
|
|
|
|
width += bits + 1;
|
|
|
|
|
|
}
|
|
|
|
|
|
while (*ptr++ == ',');
|
|
|
|
|
|
*valuep = value;
|
|
|
|
|
|
if (widthp)
|
|
|
|
|
|
*widthp = width;
|
|
|
|
|
|
return ptr - 1;
|
|
|
|
|
|
}
|
|
|
|
|
|
|
2005-09-02 Paul Brook <paul@codesourcery.com>
bfd/
* libbdf.h: Regenerate.
* bfd-in2.h: Regenerate.
* reloc.c: Add BFD_RELOC_ARM_T32_CP_OFF_IMM and
BFD_RELOC_ARM_T32_CP_OFF_IMM_S2.
gas/
* config/tc-arm.c (encode_arm_cp_address): Use
BFD_RELOC_ARM_T32_CP_OFF_IMM in thumb mode.
(do_iwmmxt_wldstbh): Use BFD_RELOC_ARM_T32_CP_OFF_IMM_S2 in thumb
mode.
(md_assemble): Only allow coprocessor instructions when Thumb-2 is
available.
(cCE, cC3): Define.
(insns): Use them for coprocessor instructions.
(md_pcrel_from_section): Handle BFD_RELOC_ARM_T32_CP_OFF_IMM.
(get_thumb32_insn): New function.
(put_thumb32_insn): New function.
(md_apply_fix): Handle BFD_RELOC_ARM_T32_CP_OFF_IMM and
BFD_RELOC_ARM_T32_CP_OFF_IMM_S2.
gas/testsuite/
* gas/arm/vfp-bad_t2.d, gas/arm/vfp-bad_t2.l, arm/vfp-bad_t2.s,
gas/arm/vfp1_t2.d, gas/arm/vfp1_t2.s, gas/arm/vfp1xD_t2.d,
gas/arm/vfp1xD_t2.s, gas/arm/vfp2_t2.d, gas/arm/vfp2_t2.s): New files.
opcodes/
* arm-dis.c (coprocessor_opcodes): New.
(arm_opcodes, thumb32_opcodes): Remove coprocessor insns.
(print_insn_coprocessor): New function.
(print_insn_arm): Use print_insn_coprocessor. Remove coprocessor
format characters.
(print_insn_thumb32): Use print_insn_coprocessor.
2005-09-02 15:12:45 +02:00
|
|
|
|
static void
|
2007-04-21 21:44:09 +02:00
|
|
|
|
arm_decode_shift (long given, fprintf_ftype func, void *stream,
|
2009-07-07 16:46:14 +02:00
|
|
|
|
bfd_boolean print_shift)
|
2005-09-02 Paul Brook <paul@codesourcery.com>
bfd/
* libbdf.h: Regenerate.
* bfd-in2.h: Regenerate.
* reloc.c: Add BFD_RELOC_ARM_T32_CP_OFF_IMM and
BFD_RELOC_ARM_T32_CP_OFF_IMM_S2.
gas/
* config/tc-arm.c (encode_arm_cp_address): Use
BFD_RELOC_ARM_T32_CP_OFF_IMM in thumb mode.
(do_iwmmxt_wldstbh): Use BFD_RELOC_ARM_T32_CP_OFF_IMM_S2 in thumb
mode.
(md_assemble): Only allow coprocessor instructions when Thumb-2 is
available.
(cCE, cC3): Define.
(insns): Use them for coprocessor instructions.
(md_pcrel_from_section): Handle BFD_RELOC_ARM_T32_CP_OFF_IMM.
(get_thumb32_insn): New function.
(put_thumb32_insn): New function.
(md_apply_fix): Handle BFD_RELOC_ARM_T32_CP_OFF_IMM and
BFD_RELOC_ARM_T32_CP_OFF_IMM_S2.
gas/testsuite/
* gas/arm/vfp-bad_t2.d, gas/arm/vfp-bad_t2.l, arm/vfp-bad_t2.s,
gas/arm/vfp1_t2.d, gas/arm/vfp1_t2.s, gas/arm/vfp1xD_t2.d,
gas/arm/vfp1xD_t2.s, gas/arm/vfp2_t2.d, gas/arm/vfp2_t2.s): New files.
opcodes/
* arm-dis.c (coprocessor_opcodes): New.
(arm_opcodes, thumb32_opcodes): Remove coprocessor insns.
(print_insn_coprocessor): New function.
(print_insn_arm): Use print_insn_coprocessor. Remove coprocessor
format characters.
(print_insn_thumb32): Use print_insn_coprocessor.
2005-09-02 15:12:45 +02:00
|
|
|
|
{
|
|
|
|
|
|
func (stream, "%s", arm_regnames[given & 0xf]);
|
|
|
|
|
|
|
|
|
|
|
|
if ((given & 0xff0) != 0)
|
|
|
|
|
|
{
|
|
|
|
|
|
if ((given & 0x10) == 0)
|
|
|
|
|
|
{
|
|
|
|
|
|
int amount = (given & 0xf80) >> 7;
|
|
|
|
|
|
int shift = (given & 0x60) >> 5;
|
|
|
|
|
|
|
|
|
|
|
|
if (amount == 0)
|
|
|
|
|
|
{
|
|
|
|
|
|
if (shift == 3)
|
|
|
|
|
|
{
|
|
|
|
|
|
func (stream, ", rrx");
|
|
|
|
|
|
return;
|
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
amount = 32;
|
|
|
|
|
|
}
|
|
|
|
|
|
|
2007-04-21 21:44:09 +02:00
|
|
|
|
if (print_shift)
|
|
|
|
|
|
func (stream, ", %s #%d", arm_shift[shift], amount);
|
|
|
|
|
|
else
|
|
|
|
|
|
func (stream, ", #%d", amount);
|
2005-09-02 Paul Brook <paul@codesourcery.com>
bfd/
* libbdf.h: Regenerate.
* bfd-in2.h: Regenerate.
* reloc.c: Add BFD_RELOC_ARM_T32_CP_OFF_IMM and
BFD_RELOC_ARM_T32_CP_OFF_IMM_S2.
gas/
* config/tc-arm.c (encode_arm_cp_address): Use
BFD_RELOC_ARM_T32_CP_OFF_IMM in thumb mode.
(do_iwmmxt_wldstbh): Use BFD_RELOC_ARM_T32_CP_OFF_IMM_S2 in thumb
mode.
(md_assemble): Only allow coprocessor instructions when Thumb-2 is
available.
(cCE, cC3): Define.
(insns): Use them for coprocessor instructions.
(md_pcrel_from_section): Handle BFD_RELOC_ARM_T32_CP_OFF_IMM.
(get_thumb32_insn): New function.
(put_thumb32_insn): New function.
(md_apply_fix): Handle BFD_RELOC_ARM_T32_CP_OFF_IMM and
BFD_RELOC_ARM_T32_CP_OFF_IMM_S2.
gas/testsuite/
* gas/arm/vfp-bad_t2.d, gas/arm/vfp-bad_t2.l, arm/vfp-bad_t2.s,
gas/arm/vfp1_t2.d, gas/arm/vfp1_t2.s, gas/arm/vfp1xD_t2.d,
gas/arm/vfp1xD_t2.s, gas/arm/vfp2_t2.d, gas/arm/vfp2_t2.s): New files.
opcodes/
* arm-dis.c (coprocessor_opcodes): New.
(arm_opcodes, thumb32_opcodes): Remove coprocessor insns.
(print_insn_coprocessor): New function.
(print_insn_arm): Use print_insn_coprocessor. Remove coprocessor
format characters.
(print_insn_thumb32): Use print_insn_coprocessor.
2005-09-02 15:12:45 +02:00
|
|
|
|
}
|
2009-07-14 16:16:34 +02:00
|
|
|
|
else if ((given & 0x80) == 0x80)
|
2009-11-17 18:20:26 +01:00
|
|
|
|
func (stream, "\t; <illegal shifter operand>");
|
2007-04-21 21:44:09 +02:00
|
|
|
|
else if (print_shift)
|
2005-09-02 Paul Brook <paul@codesourcery.com>
bfd/
* libbdf.h: Regenerate.
* bfd-in2.h: Regenerate.
* reloc.c: Add BFD_RELOC_ARM_T32_CP_OFF_IMM and
BFD_RELOC_ARM_T32_CP_OFF_IMM_S2.
gas/
* config/tc-arm.c (encode_arm_cp_address): Use
BFD_RELOC_ARM_T32_CP_OFF_IMM in thumb mode.
(do_iwmmxt_wldstbh): Use BFD_RELOC_ARM_T32_CP_OFF_IMM_S2 in thumb
mode.
(md_assemble): Only allow coprocessor instructions when Thumb-2 is
available.
(cCE, cC3): Define.
(insns): Use them for coprocessor instructions.
(md_pcrel_from_section): Handle BFD_RELOC_ARM_T32_CP_OFF_IMM.
(get_thumb32_insn): New function.
(put_thumb32_insn): New function.
(md_apply_fix): Handle BFD_RELOC_ARM_T32_CP_OFF_IMM and
BFD_RELOC_ARM_T32_CP_OFF_IMM_S2.
gas/testsuite/
* gas/arm/vfp-bad_t2.d, gas/arm/vfp-bad_t2.l, arm/vfp-bad_t2.s,
gas/arm/vfp1_t2.d, gas/arm/vfp1_t2.s, gas/arm/vfp1xD_t2.d,
gas/arm/vfp1xD_t2.s, gas/arm/vfp2_t2.d, gas/arm/vfp2_t2.s): New files.
opcodes/
* arm-dis.c (coprocessor_opcodes): New.
(arm_opcodes, thumb32_opcodes): Remove coprocessor insns.
(print_insn_coprocessor): New function.
(print_insn_arm): Use print_insn_coprocessor. Remove coprocessor
format characters.
(print_insn_thumb32): Use print_insn_coprocessor.
2005-09-02 15:12:45 +02:00
|
|
|
|
func (stream, ", %s %s", arm_shift[(given & 0x60) >> 5],
|
|
|
|
|
|
arm_regnames[(given & 0xf00) >> 8]);
|
2007-04-21 21:44:09 +02:00
|
|
|
|
else
|
|
|
|
|
|
func (stream, ", %s", arm_regnames[(given & 0xf00) >> 8]);
|
2005-09-02 Paul Brook <paul@codesourcery.com>
bfd/
* libbdf.h: Regenerate.
* bfd-in2.h: Regenerate.
* reloc.c: Add BFD_RELOC_ARM_T32_CP_OFF_IMM and
BFD_RELOC_ARM_T32_CP_OFF_IMM_S2.
gas/
* config/tc-arm.c (encode_arm_cp_address): Use
BFD_RELOC_ARM_T32_CP_OFF_IMM in thumb mode.
(do_iwmmxt_wldstbh): Use BFD_RELOC_ARM_T32_CP_OFF_IMM_S2 in thumb
mode.
(md_assemble): Only allow coprocessor instructions when Thumb-2 is
available.
(cCE, cC3): Define.
(insns): Use them for coprocessor instructions.
(md_pcrel_from_section): Handle BFD_RELOC_ARM_T32_CP_OFF_IMM.
(get_thumb32_insn): New function.
(put_thumb32_insn): New function.
(md_apply_fix): Handle BFD_RELOC_ARM_T32_CP_OFF_IMM and
BFD_RELOC_ARM_T32_CP_OFF_IMM_S2.
gas/testsuite/
* gas/arm/vfp-bad_t2.d, gas/arm/vfp-bad_t2.l, arm/vfp-bad_t2.s,
gas/arm/vfp1_t2.d, gas/arm/vfp1_t2.s, gas/arm/vfp1xD_t2.d,
gas/arm/vfp1xD_t2.s, gas/arm/vfp2_t2.d, gas/arm/vfp2_t2.s): New files.
opcodes/
* arm-dis.c (coprocessor_opcodes): New.
(arm_opcodes, thumb32_opcodes): Remove coprocessor insns.
(print_insn_coprocessor): New function.
(print_insn_arm): Use print_insn_coprocessor. Remove coprocessor
format characters.
(print_insn_thumb32): Use print_insn_coprocessor.
2005-09-02 15:12:45 +02:00
|
|
|
|
}
|
|
|
|
|
|
}
|
|
|
|
|
|
|
2009-11-11 10:44:45 +01:00
|
|
|
|
#define W_BIT 21
|
|
|
|
|
|
#define I_BIT 22
|
|
|
|
|
|
#define U_BIT 23
|
|
|
|
|
|
#define P_BIT 24
|
|
|
|
|
|
|
|
|
|
|
|
#define WRITEBACK_BIT_SET (given & (1 << W_BIT))
|
|
|
|
|
|
#define IMMEDIATE_BIT_SET (given & (1 << I_BIT))
|
|
|
|
|
|
#define NEGATIVE_BIT_SET ((given & (1 << U_BIT)) == 0)
|
|
|
|
|
|
#define PRE_BIT_SET (given & (1 << P_BIT))
|
|
|
|
|
|
|
2005-09-02 Paul Brook <paul@codesourcery.com>
bfd/
* libbdf.h: Regenerate.
* bfd-in2.h: Regenerate.
* reloc.c: Add BFD_RELOC_ARM_T32_CP_OFF_IMM and
BFD_RELOC_ARM_T32_CP_OFF_IMM_S2.
gas/
* config/tc-arm.c (encode_arm_cp_address): Use
BFD_RELOC_ARM_T32_CP_OFF_IMM in thumb mode.
(do_iwmmxt_wldstbh): Use BFD_RELOC_ARM_T32_CP_OFF_IMM_S2 in thumb
mode.
(md_assemble): Only allow coprocessor instructions when Thumb-2 is
available.
(cCE, cC3): Define.
(insns): Use them for coprocessor instructions.
(md_pcrel_from_section): Handle BFD_RELOC_ARM_T32_CP_OFF_IMM.
(get_thumb32_insn): New function.
(put_thumb32_insn): New function.
(md_apply_fix): Handle BFD_RELOC_ARM_T32_CP_OFF_IMM and
BFD_RELOC_ARM_T32_CP_OFF_IMM_S2.
gas/testsuite/
* gas/arm/vfp-bad_t2.d, gas/arm/vfp-bad_t2.l, arm/vfp-bad_t2.s,
gas/arm/vfp1_t2.d, gas/arm/vfp1_t2.s, gas/arm/vfp1xD_t2.d,
gas/arm/vfp1xD_t2.s, gas/arm/vfp2_t2.d, gas/arm/vfp2_t2.s): New files.
opcodes/
* arm-dis.c (coprocessor_opcodes): New.
(arm_opcodes, thumb32_opcodes): Remove coprocessor insns.
(print_insn_coprocessor): New function.
(print_insn_arm): Use print_insn_coprocessor. Remove coprocessor
format characters.
(print_insn_thumb32): Use print_insn_coprocessor.
2005-09-02 15:12:45 +02:00
|
|
|
|
/* Print one coprocessor instruction on INFO->STREAM.
|
|
|
|
|
|
Return TRUE if the instuction matched, FALSE if this is not a
|
|
|
|
|
|
recognised coprocessor instruction. */
|
|
|
|
|
|
|
|
|
|
|
|
static bfd_boolean
|
2009-06-30 13:57:05 +02:00
|
|
|
|
print_insn_coprocessor (bfd_vma pc,
|
|
|
|
|
|
struct disassemble_info *info,
|
|
|
|
|
|
long given,
|
2005-09-02 Paul Brook <paul@codesourcery.com>
bfd/
* libbdf.h: Regenerate.
* bfd-in2.h: Regenerate.
* reloc.c: Add BFD_RELOC_ARM_T32_CP_OFF_IMM and
BFD_RELOC_ARM_T32_CP_OFF_IMM_S2.
gas/
* config/tc-arm.c (encode_arm_cp_address): Use
BFD_RELOC_ARM_T32_CP_OFF_IMM in thumb mode.
(do_iwmmxt_wldstbh): Use BFD_RELOC_ARM_T32_CP_OFF_IMM_S2 in thumb
mode.
(md_assemble): Only allow coprocessor instructions when Thumb-2 is
available.
(cCE, cC3): Define.
(insns): Use them for coprocessor instructions.
(md_pcrel_from_section): Handle BFD_RELOC_ARM_T32_CP_OFF_IMM.
(get_thumb32_insn): New function.
(put_thumb32_insn): New function.
(md_apply_fix): Handle BFD_RELOC_ARM_T32_CP_OFF_IMM and
BFD_RELOC_ARM_T32_CP_OFF_IMM_S2.
gas/testsuite/
* gas/arm/vfp-bad_t2.d, gas/arm/vfp-bad_t2.l, arm/vfp-bad_t2.s,
gas/arm/vfp1_t2.d, gas/arm/vfp1_t2.s, gas/arm/vfp1xD_t2.d,
gas/arm/vfp1xD_t2.s, gas/arm/vfp2_t2.d, gas/arm/vfp2_t2.s): New files.
opcodes/
* arm-dis.c (coprocessor_opcodes): New.
(arm_opcodes, thumb32_opcodes): Remove coprocessor insns.
(print_insn_coprocessor): New function.
(print_insn_arm): Use print_insn_coprocessor. Remove coprocessor
format characters.
(print_insn_thumb32): Use print_insn_coprocessor.
2005-09-02 15:12:45 +02:00
|
|
|
|
bfd_boolean thumb)
|
|
|
|
|
|
{
|
|
|
|
|
|
const struct opcode32 *insn;
|
|
|
|
|
|
void *stream = info->stream;
|
|
|
|
|
|
fprintf_ftype func = info->fprintf_func;
|
|
|
|
|
|
unsigned long mask;
|
2010-01-04 11:18:32 +01:00
|
|
|
|
unsigned long value = 0;
|
2006-06-07 16:08:19 +02:00
|
|
|
|
int cond;
|
2016-02-24 14:48:59 +01:00
|
|
|
|
int cp_num;
|
2015-03-24 07:08:08 +01:00
|
|
|
|
struct arm_private_data *private_data = info->private_data;
|
|
|
|
|
|
arm_feature_set allowed_arches = ARM_ARCH_NONE;
|
|
|
|
|
|
|
2018-02-27 17:40:45 +01:00
|
|
|
|
allowed_arches = private_data->features;
|
2005-09-02 Paul Brook <paul@codesourcery.com>
bfd/
* libbdf.h: Regenerate.
* bfd-in2.h: Regenerate.
* reloc.c: Add BFD_RELOC_ARM_T32_CP_OFF_IMM and
BFD_RELOC_ARM_T32_CP_OFF_IMM_S2.
gas/
* config/tc-arm.c (encode_arm_cp_address): Use
BFD_RELOC_ARM_T32_CP_OFF_IMM in thumb mode.
(do_iwmmxt_wldstbh): Use BFD_RELOC_ARM_T32_CP_OFF_IMM_S2 in thumb
mode.
(md_assemble): Only allow coprocessor instructions when Thumb-2 is
available.
(cCE, cC3): Define.
(insns): Use them for coprocessor instructions.
(md_pcrel_from_section): Handle BFD_RELOC_ARM_T32_CP_OFF_IMM.
(get_thumb32_insn): New function.
(put_thumb32_insn): New function.
(md_apply_fix): Handle BFD_RELOC_ARM_T32_CP_OFF_IMM and
BFD_RELOC_ARM_T32_CP_OFF_IMM_S2.
gas/testsuite/
* gas/arm/vfp-bad_t2.d, gas/arm/vfp-bad_t2.l, arm/vfp-bad_t2.s,
gas/arm/vfp1_t2.d, gas/arm/vfp1_t2.s, gas/arm/vfp1xD_t2.d,
gas/arm/vfp1xD_t2.s, gas/arm/vfp2_t2.d, gas/arm/vfp2_t2.s): New files.
opcodes/
* arm-dis.c (coprocessor_opcodes): New.
(arm_opcodes, thumb32_opcodes): Remove coprocessor insns.
(print_insn_coprocessor): New function.
(print_insn_arm): Use print_insn_coprocessor. Remove coprocessor
format characters.
(print_insn_thumb32): Use print_insn_coprocessor.
2005-09-02 15:12:45 +02:00
|
|
|
|
|
|
|
|
|
|
for (insn = coprocessor_opcodes; insn->assembler; insn++)
|
|
|
|
|
|
{
|
2009-12-17 10:52:18 +01:00
|
|
|
|
unsigned long u_reg = 16;
|
|
|
|
|
|
bfd_boolean is_unpredictable = FALSE;
|
2009-06-29 10:08:15 +02:00
|
|
|
|
signed long value_in_comment = 0;
|
2009-06-18 12:31:21 +02:00
|
|
|
|
const char *c;
|
|
|
|
|
|
|
2015-03-24 07:08:08 +01:00
|
|
|
|
if (ARM_FEATURE_ZERO (insn->arch))
|
2009-06-29 10:08:15 +02:00
|
|
|
|
switch (insn->value)
|
|
|
|
|
|
{
|
|
|
|
|
|
case SENTINEL_IWMMXT_START:
|
|
|
|
|
|
if (info->mach != bfd_mach_arm_XScale
|
|
|
|
|
|
&& info->mach != bfd_mach_arm_iWMMXt
|
|
|
|
|
|
&& info->mach != bfd_mach_arm_iWMMXt2)
|
|
|
|
|
|
do
|
|
|
|
|
|
insn++;
|
2015-03-24 07:08:08 +01:00
|
|
|
|
while ((! ARM_FEATURE_ZERO (insn->arch))
|
|
|
|
|
|
&& insn->value != SENTINEL_IWMMXT_END);
|
2009-06-29 10:08:15 +02:00
|
|
|
|
continue;
|
|
|
|
|
|
|
|
|
|
|
|
case SENTINEL_IWMMXT_END:
|
|
|
|
|
|
continue;
|
|
|
|
|
|
|
|
|
|
|
|
case SENTINEL_GENERIC_START:
|
2018-02-27 17:40:45 +01:00
|
|
|
|
allowed_arches = private_data->features;
|
2009-06-29 10:08:15 +02:00
|
|
|
|
continue;
|
|
|
|
|
|
|
|
|
|
|
|
default:
|
|
|
|
|
|
abort ();
|
|
|
|
|
|
}
|
2005-09-02 Paul Brook <paul@codesourcery.com>
bfd/
* libbdf.h: Regenerate.
* bfd-in2.h: Regenerate.
* reloc.c: Add BFD_RELOC_ARM_T32_CP_OFF_IMM and
BFD_RELOC_ARM_T32_CP_OFF_IMM_S2.
gas/
* config/tc-arm.c (encode_arm_cp_address): Use
BFD_RELOC_ARM_T32_CP_OFF_IMM in thumb mode.
(do_iwmmxt_wldstbh): Use BFD_RELOC_ARM_T32_CP_OFF_IMM_S2 in thumb
mode.
(md_assemble): Only allow coprocessor instructions when Thumb-2 is
available.
(cCE, cC3): Define.
(insns): Use them for coprocessor instructions.
(md_pcrel_from_section): Handle BFD_RELOC_ARM_T32_CP_OFF_IMM.
(get_thumb32_insn): New function.
(put_thumb32_insn): New function.
(md_apply_fix): Handle BFD_RELOC_ARM_T32_CP_OFF_IMM and
BFD_RELOC_ARM_T32_CP_OFF_IMM_S2.
gas/testsuite/
* gas/arm/vfp-bad_t2.d, gas/arm/vfp-bad_t2.l, arm/vfp-bad_t2.s,
gas/arm/vfp1_t2.d, gas/arm/vfp1_t2.s, gas/arm/vfp1xD_t2.d,
gas/arm/vfp1xD_t2.s, gas/arm/vfp2_t2.d, gas/arm/vfp2_t2.s): New files.
opcodes/
* arm-dis.c (coprocessor_opcodes): New.
(arm_opcodes, thumb32_opcodes): Remove coprocessor insns.
(print_insn_coprocessor): New function.
(print_insn_arm): Use print_insn_coprocessor. Remove coprocessor
format characters.
(print_insn_thumb32): Use print_insn_coprocessor.
2005-09-02 15:12:45 +02:00
|
|
|
|
|
|
|
|
|
|
mask = insn->mask;
|
|
|
|
|
|
value = insn->value;
|
2016-02-24 14:48:59 +01:00
|
|
|
|
cp_num = (given >> 8) & 0xf;
|
|
|
|
|
|
|
2005-09-02 Paul Brook <paul@codesourcery.com>
bfd/
* libbdf.h: Regenerate.
* bfd-in2.h: Regenerate.
* reloc.c: Add BFD_RELOC_ARM_T32_CP_OFF_IMM and
BFD_RELOC_ARM_T32_CP_OFF_IMM_S2.
gas/
* config/tc-arm.c (encode_arm_cp_address): Use
BFD_RELOC_ARM_T32_CP_OFF_IMM in thumb mode.
(do_iwmmxt_wldstbh): Use BFD_RELOC_ARM_T32_CP_OFF_IMM_S2 in thumb
mode.
(md_assemble): Only allow coprocessor instructions when Thumb-2 is
available.
(cCE, cC3): Define.
(insns): Use them for coprocessor instructions.
(md_pcrel_from_section): Handle BFD_RELOC_ARM_T32_CP_OFF_IMM.
(get_thumb32_insn): New function.
(put_thumb32_insn): New function.
(md_apply_fix): Handle BFD_RELOC_ARM_T32_CP_OFF_IMM and
BFD_RELOC_ARM_T32_CP_OFF_IMM_S2.
gas/testsuite/
* gas/arm/vfp-bad_t2.d, gas/arm/vfp-bad_t2.l, arm/vfp-bad_t2.s,
gas/arm/vfp1_t2.d, gas/arm/vfp1_t2.s, gas/arm/vfp1xD_t2.d,
gas/arm/vfp1xD_t2.s, gas/arm/vfp2_t2.d, gas/arm/vfp2_t2.s): New files.
opcodes/
* arm-dis.c (coprocessor_opcodes): New.
(arm_opcodes, thumb32_opcodes): Remove coprocessor insns.
(print_insn_coprocessor): New function.
(print_insn_arm): Use print_insn_coprocessor. Remove coprocessor
format characters.
(print_insn_thumb32): Use print_insn_coprocessor.
2005-09-02 15:12:45 +02:00
|
|
|
|
if (thumb)
|
|
|
|
|
|
{
|
|
|
|
|
|
/* The high 4 bits are 0xe for Arm conditional instructions, and
|
|
|
|
|
|
0xe for arm unconditional instructions. The rest of the
|
|
|
|
|
|
encoding is the same. */
|
|
|
|
|
|
mask |= 0xf0000000;
|
|
|
|
|
|
value |= 0xe0000000;
|
2006-06-07 16:08:19 +02:00
|
|
|
|
if (ifthen_state)
|
|
|
|
|
|
cond = IFTHEN_COND;
|
|
|
|
|
|
else
|
2012-08-24 09:59:05 +02:00
|
|
|
|
cond = COND_UNCOND;
|
2005-09-02 Paul Brook <paul@codesourcery.com>
bfd/
* libbdf.h: Regenerate.
* bfd-in2.h: Regenerate.
* reloc.c: Add BFD_RELOC_ARM_T32_CP_OFF_IMM and
BFD_RELOC_ARM_T32_CP_OFF_IMM_S2.
gas/
* config/tc-arm.c (encode_arm_cp_address): Use
BFD_RELOC_ARM_T32_CP_OFF_IMM in thumb mode.
(do_iwmmxt_wldstbh): Use BFD_RELOC_ARM_T32_CP_OFF_IMM_S2 in thumb
mode.
(md_assemble): Only allow coprocessor instructions when Thumb-2 is
available.
(cCE, cC3): Define.
(insns): Use them for coprocessor instructions.
(md_pcrel_from_section): Handle BFD_RELOC_ARM_T32_CP_OFF_IMM.
(get_thumb32_insn): New function.
(put_thumb32_insn): New function.
(md_apply_fix): Handle BFD_RELOC_ARM_T32_CP_OFF_IMM and
BFD_RELOC_ARM_T32_CP_OFF_IMM_S2.
gas/testsuite/
* gas/arm/vfp-bad_t2.d, gas/arm/vfp-bad_t2.l, arm/vfp-bad_t2.s,
gas/arm/vfp1_t2.d, gas/arm/vfp1_t2.s, gas/arm/vfp1xD_t2.d,
gas/arm/vfp1xD_t2.s, gas/arm/vfp2_t2.d, gas/arm/vfp2_t2.s): New files.
opcodes/
* arm-dis.c (coprocessor_opcodes): New.
(arm_opcodes, thumb32_opcodes): Remove coprocessor insns.
(print_insn_coprocessor): New function.
(print_insn_arm): Use print_insn_coprocessor. Remove coprocessor
format characters.
(print_insn_thumb32): Use print_insn_coprocessor.
2005-09-02 15:12:45 +02:00
|
|
|
|
}
|
|
|
|
|
|
else
|
|
|
|
|
|
{
|
|
|
|
|
|
/* Only match unconditional instuctions against unconditional
|
|
|
|
|
|
patterns. */
|
|
|
|
|
|
if ((given & 0xf0000000) == 0xf0000000)
|
2006-06-07 16:08:19 +02:00
|
|
|
|
{
|
|
|
|
|
|
mask |= 0xf0000000;
|
2012-08-24 09:59:05 +02:00
|
|
|
|
cond = COND_UNCOND;
|
2006-06-07 16:08:19 +02:00
|
|
|
|
}
|
|
|
|
|
|
else
|
|
|
|
|
|
{
|
|
|
|
|
|
cond = (given >> 28) & 0xf;
|
|
|
|
|
|
if (cond == 0xe)
|
2012-08-24 09:59:05 +02:00
|
|
|
|
cond = COND_UNCOND;
|
2006-06-07 16:08:19 +02:00
|
|
|
|
}
|
2005-09-02 Paul Brook <paul@codesourcery.com>
bfd/
* libbdf.h: Regenerate.
* bfd-in2.h: Regenerate.
* reloc.c: Add BFD_RELOC_ARM_T32_CP_OFF_IMM and
BFD_RELOC_ARM_T32_CP_OFF_IMM_S2.
gas/
* config/tc-arm.c (encode_arm_cp_address): Use
BFD_RELOC_ARM_T32_CP_OFF_IMM in thumb mode.
(do_iwmmxt_wldstbh): Use BFD_RELOC_ARM_T32_CP_OFF_IMM_S2 in thumb
mode.
(md_assemble): Only allow coprocessor instructions when Thumb-2 is
available.
(cCE, cC3): Define.
(insns): Use them for coprocessor instructions.
(md_pcrel_from_section): Handle BFD_RELOC_ARM_T32_CP_OFF_IMM.
(get_thumb32_insn): New function.
(put_thumb32_insn): New function.
(md_apply_fix): Handle BFD_RELOC_ARM_T32_CP_OFF_IMM and
BFD_RELOC_ARM_T32_CP_OFF_IMM_S2.
gas/testsuite/
* gas/arm/vfp-bad_t2.d, gas/arm/vfp-bad_t2.l, arm/vfp-bad_t2.s,
gas/arm/vfp1_t2.d, gas/arm/vfp1_t2.s, gas/arm/vfp1xD_t2.d,
gas/arm/vfp1xD_t2.s, gas/arm/vfp2_t2.d, gas/arm/vfp2_t2.s): New files.
opcodes/
* arm-dis.c (coprocessor_opcodes): New.
(arm_opcodes, thumb32_opcodes): Remove coprocessor insns.
(print_insn_coprocessor): New function.
(print_insn_arm): Use print_insn_coprocessor. Remove coprocessor
format characters.
(print_insn_thumb32): Use print_insn_coprocessor.
2005-09-02 15:12:45 +02:00
|
|
|
|
}
|
2015-03-24 07:08:08 +01:00
|
|
|
|
|
2009-06-18 12:31:21 +02:00
|
|
|
|
if ((given & mask) != value)
|
|
|
|
|
|
continue;
|
2005-09-02 Paul Brook <paul@codesourcery.com>
bfd/
* libbdf.h: Regenerate.
* bfd-in2.h: Regenerate.
* reloc.c: Add BFD_RELOC_ARM_T32_CP_OFF_IMM and
BFD_RELOC_ARM_T32_CP_OFF_IMM_S2.
gas/
* config/tc-arm.c (encode_arm_cp_address): Use
BFD_RELOC_ARM_T32_CP_OFF_IMM in thumb mode.
(do_iwmmxt_wldstbh): Use BFD_RELOC_ARM_T32_CP_OFF_IMM_S2 in thumb
mode.
(md_assemble): Only allow coprocessor instructions when Thumb-2 is
available.
(cCE, cC3): Define.
(insns): Use them for coprocessor instructions.
(md_pcrel_from_section): Handle BFD_RELOC_ARM_T32_CP_OFF_IMM.
(get_thumb32_insn): New function.
(put_thumb32_insn): New function.
(md_apply_fix): Handle BFD_RELOC_ARM_T32_CP_OFF_IMM and
BFD_RELOC_ARM_T32_CP_OFF_IMM_S2.
gas/testsuite/
* gas/arm/vfp-bad_t2.d, gas/arm/vfp-bad_t2.l, arm/vfp-bad_t2.s,
gas/arm/vfp1_t2.d, gas/arm/vfp1_t2.s, gas/arm/vfp1xD_t2.d,
gas/arm/vfp1xD_t2.s, gas/arm/vfp2_t2.d, gas/arm/vfp2_t2.s): New files.
opcodes/
* arm-dis.c (coprocessor_opcodes): New.
(arm_opcodes, thumb32_opcodes): Remove coprocessor insns.
(print_insn_coprocessor): New function.
(print_insn_arm): Use print_insn_coprocessor. Remove coprocessor
format characters.
(print_insn_thumb32): Use print_insn_coprocessor.
2005-09-02 15:12:45 +02:00
|
|
|
|
|
2015-03-24 07:08:08 +01:00
|
|
|
|
if (! ARM_CPU_HAS_FEATURE (insn->arch, allowed_arches))
|
2009-06-18 12:31:21 +02:00
|
|
|
|
continue;
|
|
|
|
|
|
|
2016-02-24 14:48:59 +01:00
|
|
|
|
if (insn->value == 0xfe000010 /* mcr2 */
|
|
|
|
|
|
|| insn->value == 0xfe100010 /* mrc2 */
|
|
|
|
|
|
|| insn->value == 0xfc100000 /* ldc2 */
|
|
|
|
|
|
|| insn->value == 0xfc000000) /* stc2 */
|
|
|
|
|
|
{
|
2016-02-24 15:08:39 +01:00
|
|
|
|
if (cp_num == 9 || cp_num == 10 || cp_num == 11)
|
2016-02-24 14:48:59 +01:00
|
|
|
|
is_unpredictable = TRUE;
|
|
|
|
|
|
}
|
|
|
|
|
|
else if (insn->value == 0x0e000000 /* cdp */
|
|
|
|
|
|
|| insn->value == 0xfe000000 /* cdp2 */
|
|
|
|
|
|
|| insn->value == 0x0e000010 /* mcr */
|
|
|
|
|
|
|| insn->value == 0x0e100010 /* mrc */
|
|
|
|
|
|
|| insn->value == 0x0c100000 /* ldc */
|
|
|
|
|
|
|| insn->value == 0x0c000000) /* stc */
|
|
|
|
|
|
{
|
|
|
|
|
|
/* Floating-point instructions. */
|
2016-02-24 15:08:39 +01:00
|
|
|
|
if (cp_num == 9 || cp_num == 10 || cp_num == 11)
|
2016-02-24 14:48:59 +01:00
|
|
|
|
continue;
|
|
|
|
|
|
}
|
|
|
|
|
|
|
2009-06-18 12:31:21 +02:00
|
|
|
|
for (c = insn->assembler; *c; c++)
|
|
|
|
|
|
{
|
|
|
|
|
|
if (*c == '%')
|
2005-09-02 Paul Brook <paul@codesourcery.com>
bfd/
* libbdf.h: Regenerate.
* bfd-in2.h: Regenerate.
* reloc.c: Add BFD_RELOC_ARM_T32_CP_OFF_IMM and
BFD_RELOC_ARM_T32_CP_OFF_IMM_S2.
gas/
* config/tc-arm.c (encode_arm_cp_address): Use
BFD_RELOC_ARM_T32_CP_OFF_IMM in thumb mode.
(do_iwmmxt_wldstbh): Use BFD_RELOC_ARM_T32_CP_OFF_IMM_S2 in thumb
mode.
(md_assemble): Only allow coprocessor instructions when Thumb-2 is
available.
(cCE, cC3): Define.
(insns): Use them for coprocessor instructions.
(md_pcrel_from_section): Handle BFD_RELOC_ARM_T32_CP_OFF_IMM.
(get_thumb32_insn): New function.
(put_thumb32_insn): New function.
(md_apply_fix): Handle BFD_RELOC_ARM_T32_CP_OFF_IMM and
BFD_RELOC_ARM_T32_CP_OFF_IMM_S2.
gas/testsuite/
* gas/arm/vfp-bad_t2.d, gas/arm/vfp-bad_t2.l, arm/vfp-bad_t2.s,
gas/arm/vfp1_t2.d, gas/arm/vfp1_t2.s, gas/arm/vfp1xD_t2.d,
gas/arm/vfp1xD_t2.s, gas/arm/vfp2_t2.d, gas/arm/vfp2_t2.s): New files.
opcodes/
* arm-dis.c (coprocessor_opcodes): New.
(arm_opcodes, thumb32_opcodes): Remove coprocessor insns.
(print_insn_coprocessor): New function.
(print_insn_arm): Use print_insn_coprocessor. Remove coprocessor
format characters.
(print_insn_thumb32): Use print_insn_coprocessor.
2005-09-02 15:12:45 +02:00
|
|
|
|
{
|
2009-06-18 12:31:21 +02:00
|
|
|
|
switch (*++c)
|
2005-09-02 Paul Brook <paul@codesourcery.com>
bfd/
* libbdf.h: Regenerate.
* bfd-in2.h: Regenerate.
* reloc.c: Add BFD_RELOC_ARM_T32_CP_OFF_IMM and
BFD_RELOC_ARM_T32_CP_OFF_IMM_S2.
gas/
* config/tc-arm.c (encode_arm_cp_address): Use
BFD_RELOC_ARM_T32_CP_OFF_IMM in thumb mode.
(do_iwmmxt_wldstbh): Use BFD_RELOC_ARM_T32_CP_OFF_IMM_S2 in thumb
mode.
(md_assemble): Only allow coprocessor instructions when Thumb-2 is
available.
(cCE, cC3): Define.
(insns): Use them for coprocessor instructions.
(md_pcrel_from_section): Handle BFD_RELOC_ARM_T32_CP_OFF_IMM.
(get_thumb32_insn): New function.
(put_thumb32_insn): New function.
(md_apply_fix): Handle BFD_RELOC_ARM_T32_CP_OFF_IMM and
BFD_RELOC_ARM_T32_CP_OFF_IMM_S2.
gas/testsuite/
* gas/arm/vfp-bad_t2.d, gas/arm/vfp-bad_t2.l, arm/vfp-bad_t2.s,
gas/arm/vfp1_t2.d, gas/arm/vfp1_t2.s, gas/arm/vfp1xD_t2.d,
gas/arm/vfp1xD_t2.s, gas/arm/vfp2_t2.d, gas/arm/vfp2_t2.s): New files.
opcodes/
* arm-dis.c (coprocessor_opcodes): New.
(arm_opcodes, thumb32_opcodes): Remove coprocessor insns.
(print_insn_coprocessor): New function.
(print_insn_arm): Use print_insn_coprocessor. Remove coprocessor
format characters.
(print_insn_thumb32): Use print_insn_coprocessor.
2005-09-02 15:12:45 +02:00
|
|
|
|
{
|
2009-06-18 12:31:21 +02:00
|
|
|
|
case '%':
|
|
|
|
|
|
func (stream, "%%");
|
|
|
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
|
|
case 'A':
|
2009-06-29 10:08:15 +02:00
|
|
|
|
{
|
2009-11-12 15:49:45 +01:00
|
|
|
|
int rn = (given >> 16) & 0xf;
|
2016-02-24 15:08:39 +01:00
|
|
|
|
bfd_vma offset = given & 0xff;
|
2009-06-18 12:31:21 +02:00
|
|
|
|
|
2009-06-29 10:08:15 +02:00
|
|
|
|
func (stream, "[%s", arm_regnames [(given >> 16) & 0xf]);
|
2005-09-02 Paul Brook <paul@codesourcery.com>
bfd/
* libbdf.h: Regenerate.
* bfd-in2.h: Regenerate.
* reloc.c: Add BFD_RELOC_ARM_T32_CP_OFF_IMM and
BFD_RELOC_ARM_T32_CP_OFF_IMM_S2.
gas/
* config/tc-arm.c (encode_arm_cp_address): Use
BFD_RELOC_ARM_T32_CP_OFF_IMM in thumb mode.
(do_iwmmxt_wldstbh): Use BFD_RELOC_ARM_T32_CP_OFF_IMM_S2 in thumb
mode.
(md_assemble): Only allow coprocessor instructions when Thumb-2 is
available.
(cCE, cC3): Define.
(insns): Use them for coprocessor instructions.
(md_pcrel_from_section): Handle BFD_RELOC_ARM_T32_CP_OFF_IMM.
(get_thumb32_insn): New function.
(put_thumb32_insn): New function.
(md_apply_fix): Handle BFD_RELOC_ARM_T32_CP_OFF_IMM and
BFD_RELOC_ARM_T32_CP_OFF_IMM_S2.
gas/testsuite/
* gas/arm/vfp-bad_t2.d, gas/arm/vfp-bad_t2.l, arm/vfp-bad_t2.s,
gas/arm/vfp1_t2.d, gas/arm/vfp1_t2.s, gas/arm/vfp1xD_t2.d,
gas/arm/vfp1xD_t2.s, gas/arm/vfp2_t2.d, gas/arm/vfp2_t2.s): New files.
opcodes/
* arm-dis.c (coprocessor_opcodes): New.
(arm_opcodes, thumb32_opcodes): Remove coprocessor insns.
(print_insn_coprocessor): New function.
(print_insn_arm): Use print_insn_coprocessor. Remove coprocessor
format characters.
(print_insn_thumb32): Use print_insn_coprocessor.
2005-09-02 15:12:45 +02:00
|
|
|
|
|
2009-11-12 15:49:45 +01:00
|
|
|
|
if (PRE_BIT_SET || WRITEBACK_BIT_SET)
|
|
|
|
|
|
{
|
|
|
|
|
|
/* Not unindexed. The offset is scaled. */
|
2016-02-24 15:08:39 +01:00
|
|
|
|
if (cp_num == 9)
|
|
|
|
|
|
/* vldr.16/vstr.16 will shift the address
|
|
|
|
|
|
left by 1 bit only. */
|
|
|
|
|
|
offset = offset * 2;
|
|
|
|
|
|
else
|
|
|
|
|
|
offset = offset * 4;
|
|
|
|
|
|
|
2009-11-12 15:49:45 +01:00
|
|
|
|
if (NEGATIVE_BIT_SET)
|
|
|
|
|
|
offset = - offset;
|
|
|
|
|
|
if (rn != 15)
|
|
|
|
|
|
value_in_comment = offset;
|
|
|
|
|
|
}
|
|
|
|
|
|
|
2009-11-11 10:44:45 +01:00
|
|
|
|
if (PRE_BIT_SET)
|
2009-06-29 10:08:15 +02:00
|
|
|
|
{
|
|
|
|
|
|
if (offset)
|
2009-06-30 13:57:05 +02:00
|
|
|
|
func (stream, ", #%d]%s",
|
2012-07-24 14:56:47 +02:00
|
|
|
|
(int) offset,
|
2009-11-11 10:44:45 +01:00
|
|
|
|
WRITEBACK_BIT_SET ? "!" : "");
|
2011-06-02 17:32:10 +02:00
|
|
|
|
else if (NEGATIVE_BIT_SET)
|
|
|
|
|
|
func (stream, ", #-0]");
|
2009-06-29 10:08:15 +02:00
|
|
|
|
else
|
|
|
|
|
|
func (stream, "]");
|
|
|
|
|
|
}
|
|
|
|
|
|
else
|
|
|
|
|
|
{
|
2009-06-18 12:31:21 +02:00
|
|
|
|
func (stream, "]");
|
2005-09-02 Paul Brook <paul@codesourcery.com>
bfd/
* libbdf.h: Regenerate.
* bfd-in2.h: Regenerate.
* reloc.c: Add BFD_RELOC_ARM_T32_CP_OFF_IMM and
BFD_RELOC_ARM_T32_CP_OFF_IMM_S2.
gas/
* config/tc-arm.c (encode_arm_cp_address): Use
BFD_RELOC_ARM_T32_CP_OFF_IMM in thumb mode.
(do_iwmmxt_wldstbh): Use BFD_RELOC_ARM_T32_CP_OFF_IMM_S2 in thumb
mode.
(md_assemble): Only allow coprocessor instructions when Thumb-2 is
available.
(cCE, cC3): Define.
(insns): Use them for coprocessor instructions.
(md_pcrel_from_section): Handle BFD_RELOC_ARM_T32_CP_OFF_IMM.
(get_thumb32_insn): New function.
(put_thumb32_insn): New function.
(md_apply_fix): Handle BFD_RELOC_ARM_T32_CP_OFF_IMM and
BFD_RELOC_ARM_T32_CP_OFF_IMM_S2.
gas/testsuite/
* gas/arm/vfp-bad_t2.d, gas/arm/vfp-bad_t2.l, arm/vfp-bad_t2.s,
gas/arm/vfp1_t2.d, gas/arm/vfp1_t2.s, gas/arm/vfp1xD_t2.d,
gas/arm/vfp1xD_t2.s, gas/arm/vfp2_t2.d, gas/arm/vfp2_t2.s): New files.
opcodes/
* arm-dis.c (coprocessor_opcodes): New.
(arm_opcodes, thumb32_opcodes): Remove coprocessor insns.
(print_insn_coprocessor): New function.
(print_insn_arm): Use print_insn_coprocessor. Remove coprocessor
format characters.
(print_insn_thumb32): Use print_insn_coprocessor.
2005-09-02 15:12:45 +02:00
|
|
|
|
|
2009-11-11 10:44:45 +01:00
|
|
|
|
if (WRITEBACK_BIT_SET)
|
2009-06-29 10:08:15 +02:00
|
|
|
|
{
|
|
|
|
|
|
if (offset)
|
2012-07-24 14:56:47 +02:00
|
|
|
|
func (stream, ", #%d", (int) offset);
|
2011-06-02 17:32:10 +02:00
|
|
|
|
else if (NEGATIVE_BIT_SET)
|
|
|
|
|
|
func (stream, ", #-0");
|
2009-06-29 10:08:15 +02:00
|
|
|
|
}
|
|
|
|
|
|
else
|
2009-06-30 13:57:05 +02:00
|
|
|
|
{
|
2011-06-02 17:32:10 +02:00
|
|
|
|
func (stream, ", {%s%d}",
|
|
|
|
|
|
(NEGATIVE_BIT_SET && !offset) ? "-" : "",
|
2012-07-24 14:56:47 +02:00
|
|
|
|
(int) offset);
|
2009-06-30 13:57:05 +02:00
|
|
|
|
value_in_comment = offset;
|
|
|
|
|
|
}
|
2009-06-29 10:08:15 +02:00
|
|
|
|
}
|
2009-11-12 15:49:45 +01:00
|
|
|
|
if (rn == 15 && (PRE_BIT_SET || WRITEBACK_BIT_SET))
|
|
|
|
|
|
{
|
|
|
|
|
|
func (stream, "\t; ");
|
2010-09-27 11:47:05 +02:00
|
|
|
|
/* For unaligned PCs, apply off-by-alignment
|
|
|
|
|
|
correction. */
|
2015-08-12 13:45:07 +02:00
|
|
|
|
info->print_address_func (offset + pc
|
2010-09-27 11:47:05 +02:00
|
|
|
|
+ info->bytes_per_chunk * 2
|
|
|
|
|
|
- (pc & 3),
|
|
|
|
|
|
info);
|
2009-11-12 15:49:45 +01:00
|
|
|
|
}
|
2009-06-29 10:08:15 +02:00
|
|
|
|
}
|
2009-06-18 12:31:21 +02:00
|
|
|
|
break;
|
2005-09-02 Paul Brook <paul@codesourcery.com>
bfd/
* libbdf.h: Regenerate.
* bfd-in2.h: Regenerate.
* reloc.c: Add BFD_RELOC_ARM_T32_CP_OFF_IMM and
BFD_RELOC_ARM_T32_CP_OFF_IMM_S2.
gas/
* config/tc-arm.c (encode_arm_cp_address): Use
BFD_RELOC_ARM_T32_CP_OFF_IMM in thumb mode.
(do_iwmmxt_wldstbh): Use BFD_RELOC_ARM_T32_CP_OFF_IMM_S2 in thumb
mode.
(md_assemble): Only allow coprocessor instructions when Thumb-2 is
available.
(cCE, cC3): Define.
(insns): Use them for coprocessor instructions.
(md_pcrel_from_section): Handle BFD_RELOC_ARM_T32_CP_OFF_IMM.
(get_thumb32_insn): New function.
(put_thumb32_insn): New function.
(md_apply_fix): Handle BFD_RELOC_ARM_T32_CP_OFF_IMM and
BFD_RELOC_ARM_T32_CP_OFF_IMM_S2.
gas/testsuite/
* gas/arm/vfp-bad_t2.d, gas/arm/vfp-bad_t2.l, arm/vfp-bad_t2.s,
gas/arm/vfp1_t2.d, gas/arm/vfp1_t2.s, gas/arm/vfp1xD_t2.d,
gas/arm/vfp1xD_t2.s, gas/arm/vfp2_t2.d, gas/arm/vfp2_t2.s): New files.
opcodes/
* arm-dis.c (coprocessor_opcodes): New.
(arm_opcodes, thumb32_opcodes): Remove coprocessor insns.
(print_insn_coprocessor): New function.
(print_insn_arm): Use print_insn_coprocessor. Remove coprocessor
format characters.
(print_insn_thumb32): Use print_insn_coprocessor.
2005-09-02 15:12:45 +02:00
|
|
|
|
|
2009-06-18 12:31:21 +02:00
|
|
|
|
case 'B':
|
|
|
|
|
|
{
|
|
|
|
|
|
int regno = ((given >> 12) & 0xf) | ((given >> (22 - 4)) & 0x10);
|
|
|
|
|
|
int offset = (given >> 1) & 0x3f;
|
|
|
|
|
|
|
|
|
|
|
|
if (offset == 1)
|
|
|
|
|
|
func (stream, "{d%d}", regno);
|
|
|
|
|
|
else if (regno + offset > 32)
|
|
|
|
|
|
func (stream, "{d%d-<overflow reg d%d>}", regno, regno + offset - 1);
|
|
|
|
|
|
else
|
|
|
|
|
|
func (stream, "{d%d-d%d}", regno, regno + offset - 1);
|
|
|
|
|
|
}
|
|
|
|
|
|
break;
|
2005-09-02 Paul Brook <paul@codesourcery.com>
bfd/
* libbdf.h: Regenerate.
* bfd-in2.h: Regenerate.
* reloc.c: Add BFD_RELOC_ARM_T32_CP_OFF_IMM and
BFD_RELOC_ARM_T32_CP_OFF_IMM_S2.
gas/
* config/tc-arm.c (encode_arm_cp_address): Use
BFD_RELOC_ARM_T32_CP_OFF_IMM in thumb mode.
(do_iwmmxt_wldstbh): Use BFD_RELOC_ARM_T32_CP_OFF_IMM_S2 in thumb
mode.
(md_assemble): Only allow coprocessor instructions when Thumb-2 is
available.
(cCE, cC3): Define.
(insns): Use them for coprocessor instructions.
(md_pcrel_from_section): Handle BFD_RELOC_ARM_T32_CP_OFF_IMM.
(get_thumb32_insn): New function.
(put_thumb32_insn): New function.
(md_apply_fix): Handle BFD_RELOC_ARM_T32_CP_OFF_IMM and
BFD_RELOC_ARM_T32_CP_OFF_IMM_S2.
gas/testsuite/
* gas/arm/vfp-bad_t2.d, gas/arm/vfp-bad_t2.l, arm/vfp-bad_t2.s,
gas/arm/vfp1_t2.d, gas/arm/vfp1_t2.s, gas/arm/vfp1xD_t2.d,
gas/arm/vfp1xD_t2.s, gas/arm/vfp2_t2.d, gas/arm/vfp2_t2.s): New files.
opcodes/
* arm-dis.c (coprocessor_opcodes): New.
(arm_opcodes, thumb32_opcodes): Remove coprocessor insns.
(print_insn_coprocessor): New function.
(print_insn_arm): Use print_insn_coprocessor. Remove coprocessor
format characters.
(print_insn_thumb32): Use print_insn_coprocessor.
2005-09-02 15:12:45 +02:00
|
|
|
|
|
2012-08-24 09:59:05 +02:00
|
|
|
|
case 'u':
|
|
|
|
|
|
if (cond != COND_UNCOND)
|
|
|
|
|
|
is_unpredictable = TRUE;
|
|
|
|
|
|
|
|
|
|
|
|
/* Fall through. */
|
2009-06-18 12:31:21 +02:00
|
|
|
|
case 'c':
|
2016-02-24 15:08:39 +01:00
|
|
|
|
if (cond != COND_UNCOND && cp_num == 9)
|
|
|
|
|
|
is_unpredictable = TRUE;
|
|
|
|
|
|
|
2009-06-18 12:31:21 +02:00
|
|
|
|
func (stream, "%s", arm_conditional[cond]);
|
|
|
|
|
|
break;
|
2005-09-02 Paul Brook <paul@codesourcery.com>
bfd/
* libbdf.h: Regenerate.
* bfd-in2.h: Regenerate.
* reloc.c: Add BFD_RELOC_ARM_T32_CP_OFF_IMM and
BFD_RELOC_ARM_T32_CP_OFF_IMM_S2.
gas/
* config/tc-arm.c (encode_arm_cp_address): Use
BFD_RELOC_ARM_T32_CP_OFF_IMM in thumb mode.
(do_iwmmxt_wldstbh): Use BFD_RELOC_ARM_T32_CP_OFF_IMM_S2 in thumb
mode.
(md_assemble): Only allow coprocessor instructions when Thumb-2 is
available.
(cCE, cC3): Define.
(insns): Use them for coprocessor instructions.
(md_pcrel_from_section): Handle BFD_RELOC_ARM_T32_CP_OFF_IMM.
(get_thumb32_insn): New function.
(put_thumb32_insn): New function.
(md_apply_fix): Handle BFD_RELOC_ARM_T32_CP_OFF_IMM and
BFD_RELOC_ARM_T32_CP_OFF_IMM_S2.
gas/testsuite/
* gas/arm/vfp-bad_t2.d, gas/arm/vfp-bad_t2.l, arm/vfp-bad_t2.s,
gas/arm/vfp1_t2.d, gas/arm/vfp1_t2.s, gas/arm/vfp1xD_t2.d,
gas/arm/vfp1xD_t2.s, gas/arm/vfp2_t2.d, gas/arm/vfp2_t2.s): New files.
opcodes/
* arm-dis.c (coprocessor_opcodes): New.
(arm_opcodes, thumb32_opcodes): Remove coprocessor insns.
(print_insn_coprocessor): New function.
(print_insn_arm): Use print_insn_coprocessor. Remove coprocessor
format characters.
(print_insn_thumb32): Use print_insn_coprocessor.
2005-09-02 15:12:45 +02:00
|
|
|
|
|
2009-06-18 12:31:21 +02:00
|
|
|
|
case 'I':
|
|
|
|
|
|
/* Print a Cirrus/DSP shift immediate. */
|
|
|
|
|
|
/* Immediates are 7bit signed ints with bits 0..3 in
|
|
|
|
|
|
bits 0..3 of opcode and bits 4..6 in bits 5..7
|
|
|
|
|
|
of opcode. */
|
|
|
|
|
|
{
|
|
|
|
|
|
int imm;
|
2005-09-02 Paul Brook <paul@codesourcery.com>
bfd/
* libbdf.h: Regenerate.
* bfd-in2.h: Regenerate.
* reloc.c: Add BFD_RELOC_ARM_T32_CP_OFF_IMM and
BFD_RELOC_ARM_T32_CP_OFF_IMM_S2.
gas/
* config/tc-arm.c (encode_arm_cp_address): Use
BFD_RELOC_ARM_T32_CP_OFF_IMM in thumb mode.
(do_iwmmxt_wldstbh): Use BFD_RELOC_ARM_T32_CP_OFF_IMM_S2 in thumb
mode.
(md_assemble): Only allow coprocessor instructions when Thumb-2 is
available.
(cCE, cC3): Define.
(insns): Use them for coprocessor instructions.
(md_pcrel_from_section): Handle BFD_RELOC_ARM_T32_CP_OFF_IMM.
(get_thumb32_insn): New function.
(put_thumb32_insn): New function.
(md_apply_fix): Handle BFD_RELOC_ARM_T32_CP_OFF_IMM and
BFD_RELOC_ARM_T32_CP_OFF_IMM_S2.
gas/testsuite/
* gas/arm/vfp-bad_t2.d, gas/arm/vfp-bad_t2.l, arm/vfp-bad_t2.s,
gas/arm/vfp1_t2.d, gas/arm/vfp1_t2.s, gas/arm/vfp1xD_t2.d,
gas/arm/vfp1xD_t2.s, gas/arm/vfp2_t2.d, gas/arm/vfp2_t2.s): New files.
opcodes/
* arm-dis.c (coprocessor_opcodes): New.
(arm_opcodes, thumb32_opcodes): Remove coprocessor insns.
(print_insn_coprocessor): New function.
(print_insn_arm): Use print_insn_coprocessor. Remove coprocessor
format characters.
(print_insn_thumb32): Use print_insn_coprocessor.
2005-09-02 15:12:45 +02:00
|
|
|
|
|
2009-06-18 12:31:21 +02:00
|
|
|
|
imm = (given & 0xf) | ((given & 0xe0) >> 1);
|
2005-09-02 Paul Brook <paul@codesourcery.com>
bfd/
* libbdf.h: Regenerate.
* bfd-in2.h: Regenerate.
* reloc.c: Add BFD_RELOC_ARM_T32_CP_OFF_IMM and
BFD_RELOC_ARM_T32_CP_OFF_IMM_S2.
gas/
* config/tc-arm.c (encode_arm_cp_address): Use
BFD_RELOC_ARM_T32_CP_OFF_IMM in thumb mode.
(do_iwmmxt_wldstbh): Use BFD_RELOC_ARM_T32_CP_OFF_IMM_S2 in thumb
mode.
(md_assemble): Only allow coprocessor instructions when Thumb-2 is
available.
(cCE, cC3): Define.
(insns): Use them for coprocessor instructions.
(md_pcrel_from_section): Handle BFD_RELOC_ARM_T32_CP_OFF_IMM.
(get_thumb32_insn): New function.
(put_thumb32_insn): New function.
(md_apply_fix): Handle BFD_RELOC_ARM_T32_CP_OFF_IMM and
BFD_RELOC_ARM_T32_CP_OFF_IMM_S2.
gas/testsuite/
* gas/arm/vfp-bad_t2.d, gas/arm/vfp-bad_t2.l, arm/vfp-bad_t2.s,
gas/arm/vfp1_t2.d, gas/arm/vfp1_t2.s, gas/arm/vfp1xD_t2.d,
gas/arm/vfp1xD_t2.s, gas/arm/vfp2_t2.d, gas/arm/vfp2_t2.s): New files.
opcodes/
* arm-dis.c (coprocessor_opcodes): New.
(arm_opcodes, thumb32_opcodes): Remove coprocessor insns.
(print_insn_coprocessor): New function.
(print_insn_arm): Use print_insn_coprocessor. Remove coprocessor
format characters.
(print_insn_thumb32): Use print_insn_coprocessor.
2005-09-02 15:12:45 +02:00
|
|
|
|
|
2009-06-18 12:31:21 +02:00
|
|
|
|
/* Is ``imm'' a negative number? */
|
|
|
|
|
|
if (imm & 0x40)
|
2015-06-16 14:35:33 +02:00
|
|
|
|
imm -= 0x80;
|
2005-09-02 Paul Brook <paul@codesourcery.com>
bfd/
* libbdf.h: Regenerate.
* bfd-in2.h: Regenerate.
* reloc.c: Add BFD_RELOC_ARM_T32_CP_OFF_IMM and
BFD_RELOC_ARM_T32_CP_OFF_IMM_S2.
gas/
* config/tc-arm.c (encode_arm_cp_address): Use
BFD_RELOC_ARM_T32_CP_OFF_IMM in thumb mode.
(do_iwmmxt_wldstbh): Use BFD_RELOC_ARM_T32_CP_OFF_IMM_S2 in thumb
mode.
(md_assemble): Only allow coprocessor instructions when Thumb-2 is
available.
(cCE, cC3): Define.
(insns): Use them for coprocessor instructions.
(md_pcrel_from_section): Handle BFD_RELOC_ARM_T32_CP_OFF_IMM.
(get_thumb32_insn): New function.
(put_thumb32_insn): New function.
(md_apply_fix): Handle BFD_RELOC_ARM_T32_CP_OFF_IMM and
BFD_RELOC_ARM_T32_CP_OFF_IMM_S2.
gas/testsuite/
* gas/arm/vfp-bad_t2.d, gas/arm/vfp-bad_t2.l, arm/vfp-bad_t2.s,
gas/arm/vfp1_t2.d, gas/arm/vfp1_t2.s, gas/arm/vfp1xD_t2.d,
gas/arm/vfp1xD_t2.s, gas/arm/vfp2_t2.d, gas/arm/vfp2_t2.s): New files.
opcodes/
* arm-dis.c (coprocessor_opcodes): New.
(arm_opcodes, thumb32_opcodes): Remove coprocessor insns.
(print_insn_coprocessor): New function.
(print_insn_arm): Use print_insn_coprocessor. Remove coprocessor
format characters.
(print_insn_thumb32): Use print_insn_coprocessor.
2005-09-02 15:12:45 +02:00
|
|
|
|
|
2009-06-18 12:31:21 +02:00
|
|
|
|
func (stream, "%d", imm);
|
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
break;
|
2005-09-02 Paul Brook <paul@codesourcery.com>
bfd/
* libbdf.h: Regenerate.
* bfd-in2.h: Regenerate.
* reloc.c: Add BFD_RELOC_ARM_T32_CP_OFF_IMM and
BFD_RELOC_ARM_T32_CP_OFF_IMM_S2.
gas/
* config/tc-arm.c (encode_arm_cp_address): Use
BFD_RELOC_ARM_T32_CP_OFF_IMM in thumb mode.
(do_iwmmxt_wldstbh): Use BFD_RELOC_ARM_T32_CP_OFF_IMM_S2 in thumb
mode.
(md_assemble): Only allow coprocessor instructions when Thumb-2 is
available.
(cCE, cC3): Define.
(insns): Use them for coprocessor instructions.
(md_pcrel_from_section): Handle BFD_RELOC_ARM_T32_CP_OFF_IMM.
(get_thumb32_insn): New function.
(put_thumb32_insn): New function.
(md_apply_fix): Handle BFD_RELOC_ARM_T32_CP_OFF_IMM and
BFD_RELOC_ARM_T32_CP_OFF_IMM_S2.
gas/testsuite/
* gas/arm/vfp-bad_t2.d, gas/arm/vfp-bad_t2.l, arm/vfp-bad_t2.s,
gas/arm/vfp1_t2.d, gas/arm/vfp1_t2.s, gas/arm/vfp1xD_t2.d,
gas/arm/vfp1xD_t2.s, gas/arm/vfp2_t2.d, gas/arm/vfp2_t2.s): New files.
opcodes/
* arm-dis.c (coprocessor_opcodes): New.
(arm_opcodes, thumb32_opcodes): Remove coprocessor insns.
(print_insn_coprocessor): New function.
(print_insn_arm): Use print_insn_coprocessor. Remove coprocessor
format characters.
(print_insn_thumb32): Use print_insn_coprocessor.
2005-09-02 15:12:45 +02:00
|
|
|
|
|
2009-06-18 12:31:21 +02:00
|
|
|
|
case 'F':
|
|
|
|
|
|
switch (given & 0x00408000)
|
|
|
|
|
|
{
|
|
|
|
|
|
case 0:
|
|
|
|
|
|
func (stream, "4");
|
|
|
|
|
|
break;
|
|
|
|
|
|
case 0x8000:
|
|
|
|
|
|
func (stream, "1");
|
|
|
|
|
|
break;
|
|
|
|
|
|
case 0x00400000:
|
|
|
|
|
|
func (stream, "2");
|
2005-09-02 Paul Brook <paul@codesourcery.com>
bfd/
* libbdf.h: Regenerate.
* bfd-in2.h: Regenerate.
* reloc.c: Add BFD_RELOC_ARM_T32_CP_OFF_IMM and
BFD_RELOC_ARM_T32_CP_OFF_IMM_S2.
gas/
* config/tc-arm.c (encode_arm_cp_address): Use
BFD_RELOC_ARM_T32_CP_OFF_IMM in thumb mode.
(do_iwmmxt_wldstbh): Use BFD_RELOC_ARM_T32_CP_OFF_IMM_S2 in thumb
mode.
(md_assemble): Only allow coprocessor instructions when Thumb-2 is
available.
(cCE, cC3): Define.
(insns): Use them for coprocessor instructions.
(md_pcrel_from_section): Handle BFD_RELOC_ARM_T32_CP_OFF_IMM.
(get_thumb32_insn): New function.
(put_thumb32_insn): New function.
(md_apply_fix): Handle BFD_RELOC_ARM_T32_CP_OFF_IMM and
BFD_RELOC_ARM_T32_CP_OFF_IMM_S2.
gas/testsuite/
* gas/arm/vfp-bad_t2.d, gas/arm/vfp-bad_t2.l, arm/vfp-bad_t2.s,
gas/arm/vfp1_t2.d, gas/arm/vfp1_t2.s, gas/arm/vfp1xD_t2.d,
gas/arm/vfp1xD_t2.s, gas/arm/vfp2_t2.d, gas/arm/vfp2_t2.s): New files.
opcodes/
* arm-dis.c (coprocessor_opcodes): New.
(arm_opcodes, thumb32_opcodes): Remove coprocessor insns.
(print_insn_coprocessor): New function.
(print_insn_arm): Use print_insn_coprocessor. Remove coprocessor
format characters.
(print_insn_thumb32): Use print_insn_coprocessor.
2005-09-02 15:12:45 +02:00
|
|
|
|
break;
|
2009-06-18 12:31:21 +02:00
|
|
|
|
default:
|
|
|
|
|
|
func (stream, "3");
|
|
|
|
|
|
}
|
|
|
|
|
|
break;
|
2005-09-02 Paul Brook <paul@codesourcery.com>
bfd/
* libbdf.h: Regenerate.
* bfd-in2.h: Regenerate.
* reloc.c: Add BFD_RELOC_ARM_T32_CP_OFF_IMM and
BFD_RELOC_ARM_T32_CP_OFF_IMM_S2.
gas/
* config/tc-arm.c (encode_arm_cp_address): Use
BFD_RELOC_ARM_T32_CP_OFF_IMM in thumb mode.
(do_iwmmxt_wldstbh): Use BFD_RELOC_ARM_T32_CP_OFF_IMM_S2 in thumb
mode.
(md_assemble): Only allow coprocessor instructions when Thumb-2 is
available.
(cCE, cC3): Define.
(insns): Use them for coprocessor instructions.
(md_pcrel_from_section): Handle BFD_RELOC_ARM_T32_CP_OFF_IMM.
(get_thumb32_insn): New function.
(put_thumb32_insn): New function.
(md_apply_fix): Handle BFD_RELOC_ARM_T32_CP_OFF_IMM and
BFD_RELOC_ARM_T32_CP_OFF_IMM_S2.
gas/testsuite/
* gas/arm/vfp-bad_t2.d, gas/arm/vfp-bad_t2.l, arm/vfp-bad_t2.s,
gas/arm/vfp1_t2.d, gas/arm/vfp1_t2.s, gas/arm/vfp1xD_t2.d,
gas/arm/vfp1xD_t2.s, gas/arm/vfp2_t2.d, gas/arm/vfp2_t2.s): New files.
opcodes/
* arm-dis.c (coprocessor_opcodes): New.
(arm_opcodes, thumb32_opcodes): Remove coprocessor insns.
(print_insn_coprocessor): New function.
(print_insn_arm): Use print_insn_coprocessor. Remove coprocessor
format characters.
(print_insn_thumb32): Use print_insn_coprocessor.
2005-09-02 15:12:45 +02:00
|
|
|
|
|
2009-06-18 12:31:21 +02:00
|
|
|
|
case 'P':
|
|
|
|
|
|
switch (given & 0x00080080)
|
|
|
|
|
|
{
|
|
|
|
|
|
case 0:
|
|
|
|
|
|
func (stream, "s");
|
|
|
|
|
|
break;
|
|
|
|
|
|
case 0x80:
|
|
|
|
|
|
func (stream, "d");
|
|
|
|
|
|
break;
|
|
|
|
|
|
case 0x00080000:
|
|
|
|
|
|
func (stream, "e");
|
|
|
|
|
|
break;
|
|
|
|
|
|
default:
|
|
|
|
|
|
func (stream, _("<illegal precision>"));
|
2005-09-02 Paul Brook <paul@codesourcery.com>
bfd/
* libbdf.h: Regenerate.
* bfd-in2.h: Regenerate.
* reloc.c: Add BFD_RELOC_ARM_T32_CP_OFF_IMM and
BFD_RELOC_ARM_T32_CP_OFF_IMM_S2.
gas/
* config/tc-arm.c (encode_arm_cp_address): Use
BFD_RELOC_ARM_T32_CP_OFF_IMM in thumb mode.
(do_iwmmxt_wldstbh): Use BFD_RELOC_ARM_T32_CP_OFF_IMM_S2 in thumb
mode.
(md_assemble): Only allow coprocessor instructions when Thumb-2 is
available.
(cCE, cC3): Define.
(insns): Use them for coprocessor instructions.
(md_pcrel_from_section): Handle BFD_RELOC_ARM_T32_CP_OFF_IMM.
(get_thumb32_insn): New function.
(put_thumb32_insn): New function.
(md_apply_fix): Handle BFD_RELOC_ARM_T32_CP_OFF_IMM and
BFD_RELOC_ARM_T32_CP_OFF_IMM_S2.
gas/testsuite/
* gas/arm/vfp-bad_t2.d, gas/arm/vfp-bad_t2.l, arm/vfp-bad_t2.s,
gas/arm/vfp1_t2.d, gas/arm/vfp1_t2.s, gas/arm/vfp1xD_t2.d,
gas/arm/vfp1xD_t2.s, gas/arm/vfp2_t2.d, gas/arm/vfp2_t2.s): New files.
opcodes/
* arm-dis.c (coprocessor_opcodes): New.
(arm_opcodes, thumb32_opcodes): Remove coprocessor insns.
(print_insn_coprocessor): New function.
(print_insn_arm): Use print_insn_coprocessor. Remove coprocessor
format characters.
(print_insn_thumb32): Use print_insn_coprocessor.
2005-09-02 15:12:45 +02:00
|
|
|
|
break;
|
2009-06-18 12:31:21 +02:00
|
|
|
|
}
|
|
|
|
|
|
break;
|
2005-09-02 Paul Brook <paul@codesourcery.com>
bfd/
* libbdf.h: Regenerate.
* bfd-in2.h: Regenerate.
* reloc.c: Add BFD_RELOC_ARM_T32_CP_OFF_IMM and
BFD_RELOC_ARM_T32_CP_OFF_IMM_S2.
gas/
* config/tc-arm.c (encode_arm_cp_address): Use
BFD_RELOC_ARM_T32_CP_OFF_IMM in thumb mode.
(do_iwmmxt_wldstbh): Use BFD_RELOC_ARM_T32_CP_OFF_IMM_S2 in thumb
mode.
(md_assemble): Only allow coprocessor instructions when Thumb-2 is
available.
(cCE, cC3): Define.
(insns): Use them for coprocessor instructions.
(md_pcrel_from_section): Handle BFD_RELOC_ARM_T32_CP_OFF_IMM.
(get_thumb32_insn): New function.
(put_thumb32_insn): New function.
(md_apply_fix): Handle BFD_RELOC_ARM_T32_CP_OFF_IMM and
BFD_RELOC_ARM_T32_CP_OFF_IMM_S2.
gas/testsuite/
* gas/arm/vfp-bad_t2.d, gas/arm/vfp-bad_t2.l, arm/vfp-bad_t2.s,
gas/arm/vfp1_t2.d, gas/arm/vfp1_t2.s, gas/arm/vfp1xD_t2.d,
gas/arm/vfp1xD_t2.s, gas/arm/vfp2_t2.d, gas/arm/vfp2_t2.s): New files.
opcodes/
* arm-dis.c (coprocessor_opcodes): New.
(arm_opcodes, thumb32_opcodes): Remove coprocessor insns.
(print_insn_coprocessor): New function.
(print_insn_arm): Use print_insn_coprocessor. Remove coprocessor
format characters.
(print_insn_thumb32): Use print_insn_coprocessor.
2005-09-02 15:12:45 +02:00
|
|
|
|
|
2009-06-18 12:31:21 +02:00
|
|
|
|
case 'Q':
|
|
|
|
|
|
switch (given & 0x00408000)
|
|
|
|
|
|
{
|
|
|
|
|
|
case 0:
|
|
|
|
|
|
func (stream, "s");
|
2005-09-02 Paul Brook <paul@codesourcery.com>
bfd/
* libbdf.h: Regenerate.
* bfd-in2.h: Regenerate.
* reloc.c: Add BFD_RELOC_ARM_T32_CP_OFF_IMM and
BFD_RELOC_ARM_T32_CP_OFF_IMM_S2.
gas/
* config/tc-arm.c (encode_arm_cp_address): Use
BFD_RELOC_ARM_T32_CP_OFF_IMM in thumb mode.
(do_iwmmxt_wldstbh): Use BFD_RELOC_ARM_T32_CP_OFF_IMM_S2 in thumb
mode.
(md_assemble): Only allow coprocessor instructions when Thumb-2 is
available.
(cCE, cC3): Define.
(insns): Use them for coprocessor instructions.
(md_pcrel_from_section): Handle BFD_RELOC_ARM_T32_CP_OFF_IMM.
(get_thumb32_insn): New function.
(put_thumb32_insn): New function.
(md_apply_fix): Handle BFD_RELOC_ARM_T32_CP_OFF_IMM and
BFD_RELOC_ARM_T32_CP_OFF_IMM_S2.
gas/testsuite/
* gas/arm/vfp-bad_t2.d, gas/arm/vfp-bad_t2.l, arm/vfp-bad_t2.s,
gas/arm/vfp1_t2.d, gas/arm/vfp1_t2.s, gas/arm/vfp1xD_t2.d,
gas/arm/vfp1xD_t2.s, gas/arm/vfp2_t2.d, gas/arm/vfp2_t2.s): New files.
opcodes/
* arm-dis.c (coprocessor_opcodes): New.
(arm_opcodes, thumb32_opcodes): Remove coprocessor insns.
(print_insn_coprocessor): New function.
(print_insn_arm): Use print_insn_coprocessor. Remove coprocessor
format characters.
(print_insn_thumb32): Use print_insn_coprocessor.
2005-09-02 15:12:45 +02:00
|
|
|
|
break;
|
2009-06-18 12:31:21 +02:00
|
|
|
|
case 0x8000:
|
|
|
|
|
|
func (stream, "d");
|
2005-09-02 Paul Brook <paul@codesourcery.com>
bfd/
* libbdf.h: Regenerate.
* bfd-in2.h: Regenerate.
* reloc.c: Add BFD_RELOC_ARM_T32_CP_OFF_IMM and
BFD_RELOC_ARM_T32_CP_OFF_IMM_S2.
gas/
* config/tc-arm.c (encode_arm_cp_address): Use
BFD_RELOC_ARM_T32_CP_OFF_IMM in thumb mode.
(do_iwmmxt_wldstbh): Use BFD_RELOC_ARM_T32_CP_OFF_IMM_S2 in thumb
mode.
(md_assemble): Only allow coprocessor instructions when Thumb-2 is
available.
(cCE, cC3): Define.
(insns): Use them for coprocessor instructions.
(md_pcrel_from_section): Handle BFD_RELOC_ARM_T32_CP_OFF_IMM.
(get_thumb32_insn): New function.
(put_thumb32_insn): New function.
(md_apply_fix): Handle BFD_RELOC_ARM_T32_CP_OFF_IMM and
BFD_RELOC_ARM_T32_CP_OFF_IMM_S2.
gas/testsuite/
* gas/arm/vfp-bad_t2.d, gas/arm/vfp-bad_t2.l, arm/vfp-bad_t2.s,
gas/arm/vfp1_t2.d, gas/arm/vfp1_t2.s, gas/arm/vfp1xD_t2.d,
gas/arm/vfp1xD_t2.s, gas/arm/vfp2_t2.d, gas/arm/vfp2_t2.s): New files.
opcodes/
* arm-dis.c (coprocessor_opcodes): New.
(arm_opcodes, thumb32_opcodes): Remove coprocessor insns.
(print_insn_coprocessor): New function.
(print_insn_arm): Use print_insn_coprocessor. Remove coprocessor
format characters.
(print_insn_thumb32): Use print_insn_coprocessor.
2005-09-02 15:12:45 +02:00
|
|
|
|
break;
|
2009-06-18 12:31:21 +02:00
|
|
|
|
case 0x00400000:
|
|
|
|
|
|
func (stream, "e");
|
|
|
|
|
|
break;
|
|
|
|
|
|
default:
|
|
|
|
|
|
func (stream, "p");
|
2005-09-02 Paul Brook <paul@codesourcery.com>
bfd/
* libbdf.h: Regenerate.
* bfd-in2.h: Regenerate.
* reloc.c: Add BFD_RELOC_ARM_T32_CP_OFF_IMM and
BFD_RELOC_ARM_T32_CP_OFF_IMM_S2.
gas/
* config/tc-arm.c (encode_arm_cp_address): Use
BFD_RELOC_ARM_T32_CP_OFF_IMM in thumb mode.
(do_iwmmxt_wldstbh): Use BFD_RELOC_ARM_T32_CP_OFF_IMM_S2 in thumb
mode.
(md_assemble): Only allow coprocessor instructions when Thumb-2 is
available.
(cCE, cC3): Define.
(insns): Use them for coprocessor instructions.
(md_pcrel_from_section): Handle BFD_RELOC_ARM_T32_CP_OFF_IMM.
(get_thumb32_insn): New function.
(put_thumb32_insn): New function.
(md_apply_fix): Handle BFD_RELOC_ARM_T32_CP_OFF_IMM and
BFD_RELOC_ARM_T32_CP_OFF_IMM_S2.
gas/testsuite/
* gas/arm/vfp-bad_t2.d, gas/arm/vfp-bad_t2.l, arm/vfp-bad_t2.s,
gas/arm/vfp1_t2.d, gas/arm/vfp1_t2.s, gas/arm/vfp1xD_t2.d,
gas/arm/vfp1xD_t2.s, gas/arm/vfp2_t2.d, gas/arm/vfp2_t2.s): New files.
opcodes/
* arm-dis.c (coprocessor_opcodes): New.
(arm_opcodes, thumb32_opcodes): Remove coprocessor insns.
(print_insn_coprocessor): New function.
(print_insn_arm): Use print_insn_coprocessor. Remove coprocessor
format characters.
(print_insn_thumb32): Use print_insn_coprocessor.
2005-09-02 15:12:45 +02:00
|
|
|
|
break;
|
2009-06-18 12:31:21 +02:00
|
|
|
|
}
|
|
|
|
|
|
break;
|
2005-09-02 Paul Brook <paul@codesourcery.com>
bfd/
* libbdf.h: Regenerate.
* bfd-in2.h: Regenerate.
* reloc.c: Add BFD_RELOC_ARM_T32_CP_OFF_IMM and
BFD_RELOC_ARM_T32_CP_OFF_IMM_S2.
gas/
* config/tc-arm.c (encode_arm_cp_address): Use
BFD_RELOC_ARM_T32_CP_OFF_IMM in thumb mode.
(do_iwmmxt_wldstbh): Use BFD_RELOC_ARM_T32_CP_OFF_IMM_S2 in thumb
mode.
(md_assemble): Only allow coprocessor instructions when Thumb-2 is
available.
(cCE, cC3): Define.
(insns): Use them for coprocessor instructions.
(md_pcrel_from_section): Handle BFD_RELOC_ARM_T32_CP_OFF_IMM.
(get_thumb32_insn): New function.
(put_thumb32_insn): New function.
(md_apply_fix): Handle BFD_RELOC_ARM_T32_CP_OFF_IMM and
BFD_RELOC_ARM_T32_CP_OFF_IMM_S2.
gas/testsuite/
* gas/arm/vfp-bad_t2.d, gas/arm/vfp-bad_t2.l, arm/vfp-bad_t2.s,
gas/arm/vfp1_t2.d, gas/arm/vfp1_t2.s, gas/arm/vfp1xD_t2.d,
gas/arm/vfp1xD_t2.s, gas/arm/vfp2_t2.d, gas/arm/vfp2_t2.s): New files.
opcodes/
* arm-dis.c (coprocessor_opcodes): New.
(arm_opcodes, thumb32_opcodes): Remove coprocessor insns.
(print_insn_coprocessor): New function.
(print_insn_arm): Use print_insn_coprocessor. Remove coprocessor
format characters.
(print_insn_thumb32): Use print_insn_coprocessor.
2005-09-02 15:12:45 +02:00
|
|
|
|
|
2009-06-18 12:31:21 +02:00
|
|
|
|
case 'R':
|
|
|
|
|
|
switch (given & 0x60)
|
|
|
|
|
|
{
|
|
|
|
|
|
case 0:
|
|
|
|
|
|
break;
|
|
|
|
|
|
case 0x20:
|
|
|
|
|
|
func (stream, "p");
|
|
|
|
|
|
break;
|
|
|
|
|
|
case 0x40:
|
|
|
|
|
|
func (stream, "m");
|
|
|
|
|
|
break;
|
|
|
|
|
|
default:
|
|
|
|
|
|
func (stream, "z");
|
|
|
|
|
|
break;
|
|
|
|
|
|
}
|
|
|
|
|
|
break;
|
2006-04-26 17:40:55 +02:00
|
|
|
|
|
2009-06-18 12:31:21 +02:00
|
|
|
|
case '0': case '1': case '2': case '3': case '4':
|
|
|
|
|
|
case '5': case '6': case '7': case '8': case '9':
|
|
|
|
|
|
{
|
|
|
|
|
|
int width;
|
2005-09-02 Paul Brook <paul@codesourcery.com>
bfd/
* libbdf.h: Regenerate.
* bfd-in2.h: Regenerate.
* reloc.c: Add BFD_RELOC_ARM_T32_CP_OFF_IMM and
BFD_RELOC_ARM_T32_CP_OFF_IMM_S2.
gas/
* config/tc-arm.c (encode_arm_cp_address): Use
BFD_RELOC_ARM_T32_CP_OFF_IMM in thumb mode.
(do_iwmmxt_wldstbh): Use BFD_RELOC_ARM_T32_CP_OFF_IMM_S2 in thumb
mode.
(md_assemble): Only allow coprocessor instructions when Thumb-2 is
available.
(cCE, cC3): Define.
(insns): Use them for coprocessor instructions.
(md_pcrel_from_section): Handle BFD_RELOC_ARM_T32_CP_OFF_IMM.
(get_thumb32_insn): New function.
(put_thumb32_insn): New function.
(md_apply_fix): Handle BFD_RELOC_ARM_T32_CP_OFF_IMM and
BFD_RELOC_ARM_T32_CP_OFF_IMM_S2.
gas/testsuite/
* gas/arm/vfp-bad_t2.d, gas/arm/vfp-bad_t2.l, arm/vfp-bad_t2.s,
gas/arm/vfp1_t2.d, gas/arm/vfp1_t2.s, gas/arm/vfp1xD_t2.d,
gas/arm/vfp1xD_t2.s, gas/arm/vfp2_t2.d, gas/arm/vfp2_t2.s): New files.
opcodes/
* arm-dis.c (coprocessor_opcodes): New.
(arm_opcodes, thumb32_opcodes): Remove coprocessor insns.
(print_insn_coprocessor): New function.
(print_insn_arm): Use print_insn_coprocessor. Remove coprocessor
format characters.
(print_insn_thumb32): Use print_insn_coprocessor.
2005-09-02 15:12:45 +02:00
|
|
|
|
|
2009-06-18 12:31:21 +02:00
|
|
|
|
c = arm_decode_bitfield (c, given, &value, &width);
|
2005-09-02 Paul Brook <paul@codesourcery.com>
bfd/
* libbdf.h: Regenerate.
* bfd-in2.h: Regenerate.
* reloc.c: Add BFD_RELOC_ARM_T32_CP_OFF_IMM and
BFD_RELOC_ARM_T32_CP_OFF_IMM_S2.
gas/
* config/tc-arm.c (encode_arm_cp_address): Use
BFD_RELOC_ARM_T32_CP_OFF_IMM in thumb mode.
(do_iwmmxt_wldstbh): Use BFD_RELOC_ARM_T32_CP_OFF_IMM_S2 in thumb
mode.
(md_assemble): Only allow coprocessor instructions when Thumb-2 is
available.
(cCE, cC3): Define.
(insns): Use them for coprocessor instructions.
(md_pcrel_from_section): Handle BFD_RELOC_ARM_T32_CP_OFF_IMM.
(get_thumb32_insn): New function.
(put_thumb32_insn): New function.
(md_apply_fix): Handle BFD_RELOC_ARM_T32_CP_OFF_IMM and
BFD_RELOC_ARM_T32_CP_OFF_IMM_S2.
gas/testsuite/
* gas/arm/vfp-bad_t2.d, gas/arm/vfp-bad_t2.l, arm/vfp-bad_t2.s,
gas/arm/vfp1_t2.d, gas/arm/vfp1_t2.s, gas/arm/vfp1xD_t2.d,
gas/arm/vfp1xD_t2.s, gas/arm/vfp2_t2.d, gas/arm/vfp2_t2.s): New files.
opcodes/
* arm-dis.c (coprocessor_opcodes): New.
(arm_opcodes, thumb32_opcodes): Remove coprocessor insns.
(print_insn_coprocessor): New function.
(print_insn_arm): Use print_insn_coprocessor. Remove coprocessor
format characters.
(print_insn_thumb32): Use print_insn_coprocessor.
2005-09-02 15:12:45 +02:00
|
|
|
|
|
2009-06-18 12:31:21 +02:00
|
|
|
|
switch (*c)
|
|
|
|
|
|
{
|
2009-12-17 10:52:18 +01:00
|
|
|
|
case 'R':
|
|
|
|
|
|
if (value == 15)
|
|
|
|
|
|
is_unpredictable = TRUE;
|
|
|
|
|
|
/* Fall through. */
|
2009-06-18 12:31:21 +02:00
|
|
|
|
case 'r':
|
2009-12-17 10:52:18 +01:00
|
|
|
|
if (c[1] == 'u')
|
|
|
|
|
|
{
|
|
|
|
|
|
/* Eat the 'u' character. */
|
|
|
|
|
|
++ c;
|
|
|
|
|
|
|
|
|
|
|
|
if (u_reg == value)
|
|
|
|
|
|
is_unpredictable = TRUE;
|
|
|
|
|
|
u_reg = value;
|
|
|
|
|
|
}
|
2009-06-18 12:31:21 +02:00
|
|
|
|
func (stream, "%s", arm_regnames[value]);
|
|
|
|
|
|
break;
|
2016-12-05 15:24:17 +01:00
|
|
|
|
case 'V':
|
|
|
|
|
|
if (given & (1 << 6))
|
|
|
|
|
|
goto Q;
|
|
|
|
|
|
/* FALLTHROUGH */
|
2009-06-18 12:31:21 +02:00
|
|
|
|
case 'D':
|
|
|
|
|
|
func (stream, "d%ld", value);
|
|
|
|
|
|
break;
|
|
|
|
|
|
case 'Q':
|
2016-12-05 15:24:17 +01:00
|
|
|
|
Q:
|
2009-06-18 12:31:21 +02:00
|
|
|
|
if (value & 1)
|
|
|
|
|
|
func (stream, "<illegal reg q%ld.5>", value >> 1);
|
|
|
|
|
|
else
|
|
|
|
|
|
func (stream, "q%ld", value >> 1);
|
|
|
|
|
|
break;
|
|
|
|
|
|
case 'd':
|
|
|
|
|
|
func (stream, "%ld", value);
|
2009-06-29 10:08:15 +02:00
|
|
|
|
value_in_comment = value;
|
2009-06-18 12:31:21 +02:00
|
|
|
|
break;
|
2015-07-16 17:38:48 +02:00
|
|
|
|
case 'E':
|
|
|
|
|
|
{
|
|
|
|
|
|
/* Converts immediate 8 bit back to float value. */
|
|
|
|
|
|
unsigned floatVal = (value & 0x80) << 24
|
|
|
|
|
|
| (value & 0x3F) << 19
|
|
|
|
|
|
| ((value & 0x40) ? (0xF8 << 22) : (1 << 30));
|
|
|
|
|
|
|
|
|
|
|
|
/* Quarter float have a maximum value of 31.0.
|
|
|
|
|
|
Get floating point value multiplied by 1e7.
|
|
|
|
|
|
The maximum value stays in limit of a 32-bit int. */
|
|
|
|
|
|
unsigned decVal =
|
|
|
|
|
|
(78125 << (((floatVal >> 23) & 0xFF) - 124)) *
|
|
|
|
|
|
(16 + (value & 0xF));
|
|
|
|
|
|
|
|
|
|
|
|
if (!(decVal % 1000000))
|
|
|
|
|
|
func (stream, "%ld\t; 0x%08x %c%u.%01u", value,
|
|
|
|
|
|
floatVal, value & 0x80 ? '-' : ' ',
|
|
|
|
|
|
decVal / 10000000,
|
|
|
|
|
|
decVal % 10000000 / 1000000);
|
|
|
|
|
|
else if (!(decVal % 10000))
|
|
|
|
|
|
func (stream, "%ld\t; 0x%08x %c%u.%03u", value,
|
|
|
|
|
|
floatVal, value & 0x80 ? '-' : ' ',
|
|
|
|
|
|
decVal / 10000000,
|
|
|
|
|
|
decVal % 10000000 / 10000);
|
|
|
|
|
|
else
|
|
|
|
|
|
func (stream, "%ld\t; 0x%08x %c%u.%07u", value,
|
|
|
|
|
|
floatVal, value & 0x80 ? '-' : ' ',
|
|
|
|
|
|
decVal / 10000000, decVal % 10000000);
|
|
|
|
|
|
break;
|
|
|
|
|
|
}
|
2009-06-18 12:31:21 +02:00
|
|
|
|
case 'k':
|
|
|
|
|
|
{
|
|
|
|
|
|
int from = (given & (1 << 7)) ? 32 : 16;
|
|
|
|
|
|
func (stream, "%ld", from - value);
|
|
|
|
|
|
}
|
|
|
|
|
|
break;
|
2005-09-02 Paul Brook <paul@codesourcery.com>
bfd/
* libbdf.h: Regenerate.
* bfd-in2.h: Regenerate.
* reloc.c: Add BFD_RELOC_ARM_T32_CP_OFF_IMM and
BFD_RELOC_ARM_T32_CP_OFF_IMM_S2.
gas/
* config/tc-arm.c (encode_arm_cp_address): Use
BFD_RELOC_ARM_T32_CP_OFF_IMM in thumb mode.
(do_iwmmxt_wldstbh): Use BFD_RELOC_ARM_T32_CP_OFF_IMM_S2 in thumb
mode.
(md_assemble): Only allow coprocessor instructions when Thumb-2 is
available.
(cCE, cC3): Define.
(insns): Use them for coprocessor instructions.
(md_pcrel_from_section): Handle BFD_RELOC_ARM_T32_CP_OFF_IMM.
(get_thumb32_insn): New function.
(put_thumb32_insn): New function.
(md_apply_fix): Handle BFD_RELOC_ARM_T32_CP_OFF_IMM and
BFD_RELOC_ARM_T32_CP_OFF_IMM_S2.
gas/testsuite/
* gas/arm/vfp-bad_t2.d, gas/arm/vfp-bad_t2.l, arm/vfp-bad_t2.s,
gas/arm/vfp1_t2.d, gas/arm/vfp1_t2.s, gas/arm/vfp1xD_t2.d,
gas/arm/vfp1xD_t2.s, gas/arm/vfp2_t2.d, gas/arm/vfp2_t2.s): New files.
opcodes/
* arm-dis.c (coprocessor_opcodes): New.
(arm_opcodes, thumb32_opcodes): Remove coprocessor insns.
(print_insn_coprocessor): New function.
(print_insn_arm): Use print_insn_coprocessor. Remove coprocessor
format characters.
(print_insn_thumb32): Use print_insn_coprocessor.
2005-09-02 15:12:45 +02:00
|
|
|
|
|
2009-06-18 12:31:21 +02:00
|
|
|
|
case 'f':
|
|
|
|
|
|
if (value > 7)
|
|
|
|
|
|
func (stream, "#%s", arm_fp_const[value & 7]);
|
|
|
|
|
|
else
|
|
|
|
|
|
func (stream, "f%ld", value);
|
|
|
|
|
|
break;
|
2007-03-24 03:51:28 +01:00
|
|
|
|
|
2009-06-18 12:31:21 +02:00
|
|
|
|
case 'w':
|
|
|
|
|
|
if (width == 2)
|
|
|
|
|
|
func (stream, "%s", iwmmxt_wwnames[value]);
|
|
|
|
|
|
else
|
|
|
|
|
|
func (stream, "%s", iwmmxt_wwssnames[value]);
|
|
|
|
|
|
break;
|
2007-03-24 03:51:28 +01:00
|
|
|
|
|
2009-06-18 12:31:21 +02:00
|
|
|
|
case 'g':
|
|
|
|
|
|
func (stream, "%s", iwmmxt_regnames[value]);
|
|
|
|
|
|
break;
|
|
|
|
|
|
case 'G':
|
|
|
|
|
|
func (stream, "%s", iwmmxt_cregnames[value]);
|
2006-04-26 17:40:55 +02:00
|
|
|
|
break;
|
2005-09-02 Paul Brook <paul@codesourcery.com>
bfd/
* libbdf.h: Regenerate.
* bfd-in2.h: Regenerate.
* reloc.c: Add BFD_RELOC_ARM_T32_CP_OFF_IMM and
BFD_RELOC_ARM_T32_CP_OFF_IMM_S2.
gas/
* config/tc-arm.c (encode_arm_cp_address): Use
BFD_RELOC_ARM_T32_CP_OFF_IMM in thumb mode.
(do_iwmmxt_wldstbh): Use BFD_RELOC_ARM_T32_CP_OFF_IMM_S2 in thumb
mode.
(md_assemble): Only allow coprocessor instructions when Thumb-2 is
available.
(cCE, cC3): Define.
(insns): Use them for coprocessor instructions.
(md_pcrel_from_section): Handle BFD_RELOC_ARM_T32_CP_OFF_IMM.
(get_thumb32_insn): New function.
(put_thumb32_insn): New function.
(md_apply_fix): Handle BFD_RELOC_ARM_T32_CP_OFF_IMM and
BFD_RELOC_ARM_T32_CP_OFF_IMM_S2.
gas/testsuite/
* gas/arm/vfp-bad_t2.d, gas/arm/vfp-bad_t2.l, arm/vfp-bad_t2.s,
gas/arm/vfp1_t2.d, gas/arm/vfp1_t2.s, gas/arm/vfp1xD_t2.d,
gas/arm/vfp1xD_t2.s, gas/arm/vfp2_t2.d, gas/arm/vfp2_t2.s): New files.
opcodes/
* arm-dis.c (coprocessor_opcodes): New.
(arm_opcodes, thumb32_opcodes): Remove coprocessor insns.
(print_insn_coprocessor): New function.
(print_insn_arm): Use print_insn_coprocessor. Remove coprocessor
format characters.
(print_insn_thumb32): Use print_insn_coprocessor.
2005-09-02 15:12:45 +02:00
|
|
|
|
|
2009-06-18 12:31:21 +02:00
|
|
|
|
case 'x':
|
2009-07-10 18:58:54 +02:00
|
|
|
|
func (stream, "0x%lx", (value & 0xffffffffUL));
|
2009-06-18 12:31:21 +02:00
|
|
|
|
break;
|
2005-09-02 Paul Brook <paul@codesourcery.com>
bfd/
* libbdf.h: Regenerate.
* bfd-in2.h: Regenerate.
* reloc.c: Add BFD_RELOC_ARM_T32_CP_OFF_IMM and
BFD_RELOC_ARM_T32_CP_OFF_IMM_S2.
gas/
* config/tc-arm.c (encode_arm_cp_address): Use
BFD_RELOC_ARM_T32_CP_OFF_IMM in thumb mode.
(do_iwmmxt_wldstbh): Use BFD_RELOC_ARM_T32_CP_OFF_IMM_S2 in thumb
mode.
(md_assemble): Only allow coprocessor instructions when Thumb-2 is
available.
(cCE, cC3): Define.
(insns): Use them for coprocessor instructions.
(md_pcrel_from_section): Handle BFD_RELOC_ARM_T32_CP_OFF_IMM.
(get_thumb32_insn): New function.
(put_thumb32_insn): New function.
(md_apply_fix): Handle BFD_RELOC_ARM_T32_CP_OFF_IMM and
BFD_RELOC_ARM_T32_CP_OFF_IMM_S2.
gas/testsuite/
* gas/arm/vfp-bad_t2.d, gas/arm/vfp-bad_t2.l, arm/vfp-bad_t2.s,
gas/arm/vfp1_t2.d, gas/arm/vfp1_t2.s, gas/arm/vfp1xD_t2.d,
gas/arm/vfp1xD_t2.s, gas/arm/vfp2_t2.d, gas/arm/vfp2_t2.s): New files.
opcodes/
* arm-dis.c (coprocessor_opcodes): New.
(arm_opcodes, thumb32_opcodes): Remove coprocessor insns.
(print_insn_coprocessor): New function.
(print_insn_arm): Use print_insn_coprocessor. Remove coprocessor
format characters.
(print_insn_thumb32): Use print_insn_coprocessor.
2005-09-02 15:12:45 +02:00
|
|
|
|
|
2012-08-24 10:06:36 +02:00
|
|
|
|
case 'c':
|
|
|
|
|
|
switch (value)
|
|
|
|
|
|
{
|
|
|
|
|
|
case 0:
|
|
|
|
|
|
func (stream, "eq");
|
|
|
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
|
|
case 1:
|
|
|
|
|
|
func (stream, "vs");
|
|
|
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
|
|
case 2:
|
|
|
|
|
|
func (stream, "ge");
|
|
|
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
|
|
case 3:
|
|
|
|
|
|
func (stream, "gt");
|
|
|
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
|
|
default:
|
|
|
|
|
|
func (stream, "??");
|
|
|
|
|
|
break;
|
|
|
|
|
|
}
|
|
|
|
|
|
break;
|
|
|
|
|
|
|
2009-06-18 12:31:21 +02:00
|
|
|
|
case '`':
|
|
|
|
|
|
c++;
|
|
|
|
|
|
if (value == 0)
|
|
|
|
|
|
func (stream, "%c", *c);
|
|
|
|
|
|
break;
|
|
|
|
|
|
case '\'':
|
|
|
|
|
|
c++;
|
|
|
|
|
|
if (value == ((1ul << width) - 1))
|
|
|
|
|
|
func (stream, "%c", *c);
|
|
|
|
|
|
break;
|
|
|
|
|
|
case '?':
|
2009-06-30 13:57:05 +02:00
|
|
|
|
func (stream, "%c", c[(1 << width) - (int) value]);
|
2009-06-18 12:31:21 +02:00
|
|
|
|
c += 1 << width;
|
|
|
|
|
|
break;
|
|
|
|
|
|
default:
|
|
|
|
|
|
abort ();
|
|
|
|
|
|
}
|
|
|
|
|
|
break;
|
2005-09-02 Paul Brook <paul@codesourcery.com>
bfd/
* libbdf.h: Regenerate.
* bfd-in2.h: Regenerate.
* reloc.c: Add BFD_RELOC_ARM_T32_CP_OFF_IMM and
BFD_RELOC_ARM_T32_CP_OFF_IMM_S2.
gas/
* config/tc-arm.c (encode_arm_cp_address): Use
BFD_RELOC_ARM_T32_CP_OFF_IMM in thumb mode.
(do_iwmmxt_wldstbh): Use BFD_RELOC_ARM_T32_CP_OFF_IMM_S2 in thumb
mode.
(md_assemble): Only allow coprocessor instructions when Thumb-2 is
available.
(cCE, cC3): Define.
(insns): Use them for coprocessor instructions.
(md_pcrel_from_section): Handle BFD_RELOC_ARM_T32_CP_OFF_IMM.
(get_thumb32_insn): New function.
(put_thumb32_insn): New function.
(md_apply_fix): Handle BFD_RELOC_ARM_T32_CP_OFF_IMM and
BFD_RELOC_ARM_T32_CP_OFF_IMM_S2.
gas/testsuite/
* gas/arm/vfp-bad_t2.d, gas/arm/vfp-bad_t2.l, arm/vfp-bad_t2.s,
gas/arm/vfp1_t2.d, gas/arm/vfp1_t2.s, gas/arm/vfp1xD_t2.d,
gas/arm/vfp1xD_t2.s, gas/arm/vfp2_t2.d, gas/arm/vfp2_t2.s): New files.
opcodes/
* arm-dis.c (coprocessor_opcodes): New.
(arm_opcodes, thumb32_opcodes): Remove coprocessor insns.
(print_insn_coprocessor): New function.
(print_insn_arm): Use print_insn_coprocessor. Remove coprocessor
format characters.
(print_insn_thumb32): Use print_insn_coprocessor.
2005-09-02 15:12:45 +02:00
|
|
|
|
|
2009-06-18 12:31:21 +02:00
|
|
|
|
case 'y':
|
|
|
|
|
|
case 'z':
|
|
|
|
|
|
{
|
|
|
|
|
|
int single = *c++ == 'y';
|
|
|
|
|
|
int regno;
|
|
|
|
|
|
|
|
|
|
|
|
switch (*c)
|
|
|
|
|
|
{
|
|
|
|
|
|
case '4': /* Sm pair */
|
|
|
|
|
|
case '0': /* Sm, Dm */
|
|
|
|
|
|
regno = given & 0x0000000f;
|
|
|
|
|
|
if (single)
|
|
|
|
|
|
{
|
|
|
|
|
|
regno <<= 1;
|
|
|
|
|
|
regno += (given >> 5) & 1;
|
2006-04-26 17:40:55 +02:00
|
|
|
|
}
|
2009-06-18 12:31:21 +02:00
|
|
|
|
else
|
|
|
|
|
|
regno += ((given >> 5) & 1) << 4;
|
|
|
|
|
|
break;
|
2005-09-02 Paul Brook <paul@codesourcery.com>
bfd/
* libbdf.h: Regenerate.
* bfd-in2.h: Regenerate.
* reloc.c: Add BFD_RELOC_ARM_T32_CP_OFF_IMM and
BFD_RELOC_ARM_T32_CP_OFF_IMM_S2.
gas/
* config/tc-arm.c (encode_arm_cp_address): Use
BFD_RELOC_ARM_T32_CP_OFF_IMM in thumb mode.
(do_iwmmxt_wldstbh): Use BFD_RELOC_ARM_T32_CP_OFF_IMM_S2 in thumb
mode.
(md_assemble): Only allow coprocessor instructions when Thumb-2 is
available.
(cCE, cC3): Define.
(insns): Use them for coprocessor instructions.
(md_pcrel_from_section): Handle BFD_RELOC_ARM_T32_CP_OFF_IMM.
(get_thumb32_insn): New function.
(put_thumb32_insn): New function.
(md_apply_fix): Handle BFD_RELOC_ARM_T32_CP_OFF_IMM and
BFD_RELOC_ARM_T32_CP_OFF_IMM_S2.
gas/testsuite/
* gas/arm/vfp-bad_t2.d, gas/arm/vfp-bad_t2.l, arm/vfp-bad_t2.s,
gas/arm/vfp1_t2.d, gas/arm/vfp1_t2.s, gas/arm/vfp1xD_t2.d,
gas/arm/vfp1xD_t2.s, gas/arm/vfp2_t2.d, gas/arm/vfp2_t2.s): New files.
opcodes/
* arm-dis.c (coprocessor_opcodes): New.
(arm_opcodes, thumb32_opcodes): Remove coprocessor insns.
(print_insn_coprocessor): New function.
(print_insn_arm): Use print_insn_coprocessor. Remove coprocessor
format characters.
(print_insn_thumb32): Use print_insn_coprocessor.
2005-09-02 15:12:45 +02:00
|
|
|
|
|
2009-06-18 12:31:21 +02:00
|
|
|
|
case '1': /* Sd, Dd */
|
|
|
|
|
|
regno = (given >> 12) & 0x0000000f;
|
|
|
|
|
|
if (single)
|
|
|
|
|
|
{
|
|
|
|
|
|
regno <<= 1;
|
|
|
|
|
|
regno += (given >> 22) & 1;
|
|
|
|
|
|
}
|
|
|
|
|
|
else
|
|
|
|
|
|
regno += ((given >> 22) & 1) << 4;
|
|
|
|
|
|
break;
|
2005-09-02 Paul Brook <paul@codesourcery.com>
bfd/
* libbdf.h: Regenerate.
* bfd-in2.h: Regenerate.
* reloc.c: Add BFD_RELOC_ARM_T32_CP_OFF_IMM and
BFD_RELOC_ARM_T32_CP_OFF_IMM_S2.
gas/
* config/tc-arm.c (encode_arm_cp_address): Use
BFD_RELOC_ARM_T32_CP_OFF_IMM in thumb mode.
(do_iwmmxt_wldstbh): Use BFD_RELOC_ARM_T32_CP_OFF_IMM_S2 in thumb
mode.
(md_assemble): Only allow coprocessor instructions when Thumb-2 is
available.
(cCE, cC3): Define.
(insns): Use them for coprocessor instructions.
(md_pcrel_from_section): Handle BFD_RELOC_ARM_T32_CP_OFF_IMM.
(get_thumb32_insn): New function.
(put_thumb32_insn): New function.
(md_apply_fix): Handle BFD_RELOC_ARM_T32_CP_OFF_IMM and
BFD_RELOC_ARM_T32_CP_OFF_IMM_S2.
gas/testsuite/
* gas/arm/vfp-bad_t2.d, gas/arm/vfp-bad_t2.l, arm/vfp-bad_t2.s,
gas/arm/vfp1_t2.d, gas/arm/vfp1_t2.s, gas/arm/vfp1xD_t2.d,
gas/arm/vfp1xD_t2.s, gas/arm/vfp2_t2.d, gas/arm/vfp2_t2.s): New files.
opcodes/
* arm-dis.c (coprocessor_opcodes): New.
(arm_opcodes, thumb32_opcodes): Remove coprocessor insns.
(print_insn_coprocessor): New function.
(print_insn_arm): Use print_insn_coprocessor. Remove coprocessor
format characters.
(print_insn_thumb32): Use print_insn_coprocessor.
2005-09-02 15:12:45 +02:00
|
|
|
|
|
2009-06-18 12:31:21 +02:00
|
|
|
|
case '2': /* Sn, Dn */
|
|
|
|
|
|
regno = (given >> 16) & 0x0000000f;
|
|
|
|
|
|
if (single)
|
2005-09-02 Paul Brook <paul@codesourcery.com>
bfd/
* libbdf.h: Regenerate.
* bfd-in2.h: Regenerate.
* reloc.c: Add BFD_RELOC_ARM_T32_CP_OFF_IMM and
BFD_RELOC_ARM_T32_CP_OFF_IMM_S2.
gas/
* config/tc-arm.c (encode_arm_cp_address): Use
BFD_RELOC_ARM_T32_CP_OFF_IMM in thumb mode.
(do_iwmmxt_wldstbh): Use BFD_RELOC_ARM_T32_CP_OFF_IMM_S2 in thumb
mode.
(md_assemble): Only allow coprocessor instructions when Thumb-2 is
available.
(cCE, cC3): Define.
(insns): Use them for coprocessor instructions.
(md_pcrel_from_section): Handle BFD_RELOC_ARM_T32_CP_OFF_IMM.
(get_thumb32_insn): New function.
(put_thumb32_insn): New function.
(md_apply_fix): Handle BFD_RELOC_ARM_T32_CP_OFF_IMM and
BFD_RELOC_ARM_T32_CP_OFF_IMM_S2.
gas/testsuite/
* gas/arm/vfp-bad_t2.d, gas/arm/vfp-bad_t2.l, arm/vfp-bad_t2.s,
gas/arm/vfp1_t2.d, gas/arm/vfp1_t2.s, gas/arm/vfp1xD_t2.d,
gas/arm/vfp1xD_t2.s, gas/arm/vfp2_t2.d, gas/arm/vfp2_t2.s): New files.
opcodes/
* arm-dis.c (coprocessor_opcodes): New.
(arm_opcodes, thumb32_opcodes): Remove coprocessor insns.
(print_insn_coprocessor): New function.
(print_insn_arm): Use print_insn_coprocessor. Remove coprocessor
format characters.
(print_insn_thumb32): Use print_insn_coprocessor.
2005-09-02 15:12:45 +02:00
|
|
|
|
{
|
2009-06-18 12:31:21 +02:00
|
|
|
|
regno <<= 1;
|
|
|
|
|
|
regno += (given >> 7) & 1;
|
2005-09-02 Paul Brook <paul@codesourcery.com>
bfd/
* libbdf.h: Regenerate.
* bfd-in2.h: Regenerate.
* reloc.c: Add BFD_RELOC_ARM_T32_CP_OFF_IMM and
BFD_RELOC_ARM_T32_CP_OFF_IMM_S2.
gas/
* config/tc-arm.c (encode_arm_cp_address): Use
BFD_RELOC_ARM_T32_CP_OFF_IMM in thumb mode.
(do_iwmmxt_wldstbh): Use BFD_RELOC_ARM_T32_CP_OFF_IMM_S2 in thumb
mode.
(md_assemble): Only allow coprocessor instructions when Thumb-2 is
available.
(cCE, cC3): Define.
(insns): Use them for coprocessor instructions.
(md_pcrel_from_section): Handle BFD_RELOC_ARM_T32_CP_OFF_IMM.
(get_thumb32_insn): New function.
(put_thumb32_insn): New function.
(md_apply_fix): Handle BFD_RELOC_ARM_T32_CP_OFF_IMM and
BFD_RELOC_ARM_T32_CP_OFF_IMM_S2.
gas/testsuite/
* gas/arm/vfp-bad_t2.d, gas/arm/vfp-bad_t2.l, arm/vfp-bad_t2.s,
gas/arm/vfp1_t2.d, gas/arm/vfp1_t2.s, gas/arm/vfp1xD_t2.d,
gas/arm/vfp1xD_t2.s, gas/arm/vfp2_t2.d, gas/arm/vfp2_t2.s): New files.
opcodes/
* arm-dis.c (coprocessor_opcodes): New.
(arm_opcodes, thumb32_opcodes): Remove coprocessor insns.
(print_insn_coprocessor): New function.
(print_insn_arm): Use print_insn_coprocessor. Remove coprocessor
format characters.
(print_insn_thumb32): Use print_insn_coprocessor.
2005-09-02 15:12:45 +02:00
|
|
|
|
}
|
2009-06-18 12:31:21 +02:00
|
|
|
|
else
|
|
|
|
|
|
regno += ((given >> 7) & 1) << 4;
|
|
|
|
|
|
break;
|
2008-12-15 18:24:13 +01:00
|
|
|
|
|
2009-06-18 12:31:21 +02:00
|
|
|
|
case '3': /* List */
|
|
|
|
|
|
func (stream, "{");
|
|
|
|
|
|
regno = (given >> 12) & 0x0000000f;
|
|
|
|
|
|
if (single)
|
|
|
|
|
|
{
|
|
|
|
|
|
regno <<= 1;
|
|
|
|
|
|
regno += (given >> 22) & 1;
|
|
|
|
|
|
}
|
|
|
|
|
|
else
|
|
|
|
|
|
regno += ((given >> 22) & 1) << 4;
|
|
|
|
|
|
break;
|
2000-02-14 20:02:47 +01:00
|
|
|
|
|
2009-06-18 12:31:21 +02:00
|
|
|
|
default:
|
|
|
|
|
|
abort ();
|
2005-09-02 Paul Brook <paul@codesourcery.com>
bfd/
* libbdf.h: Regenerate.
* bfd-in2.h: Regenerate.
* reloc.c: Add BFD_RELOC_ARM_T32_CP_OFF_IMM and
BFD_RELOC_ARM_T32_CP_OFF_IMM_S2.
gas/
* config/tc-arm.c (encode_arm_cp_address): Use
BFD_RELOC_ARM_T32_CP_OFF_IMM in thumb mode.
(do_iwmmxt_wldstbh): Use BFD_RELOC_ARM_T32_CP_OFF_IMM_S2 in thumb
mode.
(md_assemble): Only allow coprocessor instructions when Thumb-2 is
available.
(cCE, cC3): Define.
(insns): Use them for coprocessor instructions.
(md_pcrel_from_section): Handle BFD_RELOC_ARM_T32_CP_OFF_IMM.
(get_thumb32_insn): New function.
(put_thumb32_insn): New function.
(md_apply_fix): Handle BFD_RELOC_ARM_T32_CP_OFF_IMM and
BFD_RELOC_ARM_T32_CP_OFF_IMM_S2.
gas/testsuite/
* gas/arm/vfp-bad_t2.d, gas/arm/vfp-bad_t2.l, arm/vfp-bad_t2.s,
gas/arm/vfp1_t2.d, gas/arm/vfp1_t2.s, gas/arm/vfp1xD_t2.d,
gas/arm/vfp1xD_t2.s, gas/arm/vfp2_t2.d, gas/arm/vfp2_t2.s): New files.
opcodes/
* arm-dis.c (coprocessor_opcodes): New.
(arm_opcodes, thumb32_opcodes): Remove coprocessor insns.
(print_insn_coprocessor): New function.
(print_insn_arm): Use print_insn_coprocessor. Remove coprocessor
format characters.
(print_insn_thumb32): Use print_insn_coprocessor.
2005-09-02 15:12:45 +02:00
|
|
|
|
}
|
2000-02-14 20:02:47 +01:00
|
|
|
|
|
2009-06-18 12:31:21 +02:00
|
|
|
|
func (stream, "%c%d", single ? 's' : 'd', regno);
|
|
|
|
|
|
|
|
|
|
|
|
if (*c == '3')
|
2005-09-02 Paul Brook <paul@codesourcery.com>
bfd/
* libbdf.h: Regenerate.
* bfd-in2.h: Regenerate.
* reloc.c: Add BFD_RELOC_ARM_T32_CP_OFF_IMM and
BFD_RELOC_ARM_T32_CP_OFF_IMM_S2.
gas/
* config/tc-arm.c (encode_arm_cp_address): Use
BFD_RELOC_ARM_T32_CP_OFF_IMM in thumb mode.
(do_iwmmxt_wldstbh): Use BFD_RELOC_ARM_T32_CP_OFF_IMM_S2 in thumb
mode.
(md_assemble): Only allow coprocessor instructions when Thumb-2 is
available.
(cCE, cC3): Define.
(insns): Use them for coprocessor instructions.
(md_pcrel_from_section): Handle BFD_RELOC_ARM_T32_CP_OFF_IMM.
(get_thumb32_insn): New function.
(put_thumb32_insn): New function.
(md_apply_fix): Handle BFD_RELOC_ARM_T32_CP_OFF_IMM and
BFD_RELOC_ARM_T32_CP_OFF_IMM_S2.
gas/testsuite/
* gas/arm/vfp-bad_t2.d, gas/arm/vfp-bad_t2.l, arm/vfp-bad_t2.s,
gas/arm/vfp1_t2.d, gas/arm/vfp1_t2.s, gas/arm/vfp1xD_t2.d,
gas/arm/vfp1xD_t2.s, gas/arm/vfp2_t2.d, gas/arm/vfp2_t2.s): New files.
opcodes/
* arm-dis.c (coprocessor_opcodes): New.
(arm_opcodes, thumb32_opcodes): Remove coprocessor insns.
(print_insn_coprocessor): New function.
(print_insn_arm): Use print_insn_coprocessor. Remove coprocessor
format characters.
(print_insn_thumb32): Use print_insn_coprocessor.
2005-09-02 15:12:45 +02:00
|
|
|
|
{
|
2009-06-18 12:31:21 +02:00
|
|
|
|
int count = given & 0xff;
|
2000-02-14 20:02:47 +01:00
|
|
|
|
|
2009-06-18 12:31:21 +02:00
|
|
|
|
if (single == 0)
|
|
|
|
|
|
count >>= 1;
|
2002-11-30 09:39:46 +01:00
|
|
|
|
|
2009-06-18 12:31:21 +02:00
|
|
|
|
if (--count)
|
2005-09-02 Paul Brook <paul@codesourcery.com>
bfd/
* libbdf.h: Regenerate.
* bfd-in2.h: Regenerate.
* reloc.c: Add BFD_RELOC_ARM_T32_CP_OFF_IMM and
BFD_RELOC_ARM_T32_CP_OFF_IMM_S2.
gas/
* config/tc-arm.c (encode_arm_cp_address): Use
BFD_RELOC_ARM_T32_CP_OFF_IMM in thumb mode.
(do_iwmmxt_wldstbh): Use BFD_RELOC_ARM_T32_CP_OFF_IMM_S2 in thumb
mode.
(md_assemble): Only allow coprocessor instructions when Thumb-2 is
available.
(cCE, cC3): Define.
(insns): Use them for coprocessor instructions.
(md_pcrel_from_section): Handle BFD_RELOC_ARM_T32_CP_OFF_IMM.
(get_thumb32_insn): New function.
(put_thumb32_insn): New function.
(md_apply_fix): Handle BFD_RELOC_ARM_T32_CP_OFF_IMM and
BFD_RELOC_ARM_T32_CP_OFF_IMM_S2.
gas/testsuite/
* gas/arm/vfp-bad_t2.d, gas/arm/vfp-bad_t2.l, arm/vfp-bad_t2.s,
gas/arm/vfp1_t2.d, gas/arm/vfp1_t2.s, gas/arm/vfp1xD_t2.d,
gas/arm/vfp1xD_t2.s, gas/arm/vfp2_t2.d, gas/arm/vfp2_t2.s): New files.
opcodes/
* arm-dis.c (coprocessor_opcodes): New.
(arm_opcodes, thumb32_opcodes): Remove coprocessor insns.
(print_insn_coprocessor): New function.
(print_insn_arm): Use print_insn_coprocessor. Remove coprocessor
format characters.
(print_insn_thumb32): Use print_insn_coprocessor.
2005-09-02 15:12:45 +02:00
|
|
|
|
{
|
2009-06-18 12:31:21 +02:00
|
|
|
|
func (stream, "-%c%d",
|
|
|
|
|
|
single ? 's' : 'd',
|
|
|
|
|
|
regno + count);
|
2005-09-02 Paul Brook <paul@codesourcery.com>
bfd/
* libbdf.h: Regenerate.
* bfd-in2.h: Regenerate.
* reloc.c: Add BFD_RELOC_ARM_T32_CP_OFF_IMM and
BFD_RELOC_ARM_T32_CP_OFF_IMM_S2.
gas/
* config/tc-arm.c (encode_arm_cp_address): Use
BFD_RELOC_ARM_T32_CP_OFF_IMM in thumb mode.
(do_iwmmxt_wldstbh): Use BFD_RELOC_ARM_T32_CP_OFF_IMM_S2 in thumb
mode.
(md_assemble): Only allow coprocessor instructions when Thumb-2 is
available.
(cCE, cC3): Define.
(insns): Use them for coprocessor instructions.
(md_pcrel_from_section): Handle BFD_RELOC_ARM_T32_CP_OFF_IMM.
(get_thumb32_insn): New function.
(put_thumb32_insn): New function.
(md_apply_fix): Handle BFD_RELOC_ARM_T32_CP_OFF_IMM and
BFD_RELOC_ARM_T32_CP_OFF_IMM_S2.
gas/testsuite/
* gas/arm/vfp-bad_t2.d, gas/arm/vfp-bad_t2.l, arm/vfp-bad_t2.s,
gas/arm/vfp1_t2.d, gas/arm/vfp1_t2.s, gas/arm/vfp1xD_t2.d,
gas/arm/vfp1xD_t2.s, gas/arm/vfp2_t2.d, gas/arm/vfp2_t2.s): New files.
opcodes/
* arm-dis.c (coprocessor_opcodes): New.
(arm_opcodes, thumb32_opcodes): Remove coprocessor insns.
(print_insn_coprocessor): New function.
(print_insn_arm): Use print_insn_coprocessor. Remove coprocessor
format characters.
(print_insn_thumb32): Use print_insn_coprocessor.
2005-09-02 15:12:45 +02:00
|
|
|
|
}
|
2009-06-18 12:31:21 +02:00
|
|
|
|
|
|
|
|
|
|
func (stream, "}");
|
2005-09-02 Paul Brook <paul@codesourcery.com>
bfd/
* libbdf.h: Regenerate.
* bfd-in2.h: Regenerate.
* reloc.c: Add BFD_RELOC_ARM_T32_CP_OFF_IMM and
BFD_RELOC_ARM_T32_CP_OFF_IMM_S2.
gas/
* config/tc-arm.c (encode_arm_cp_address): Use
BFD_RELOC_ARM_T32_CP_OFF_IMM in thumb mode.
(do_iwmmxt_wldstbh): Use BFD_RELOC_ARM_T32_CP_OFF_IMM_S2 in thumb
mode.
(md_assemble): Only allow coprocessor instructions when Thumb-2 is
available.
(cCE, cC3): Define.
(insns): Use them for coprocessor instructions.
(md_pcrel_from_section): Handle BFD_RELOC_ARM_T32_CP_OFF_IMM.
(get_thumb32_insn): New function.
(put_thumb32_insn): New function.
(md_apply_fix): Handle BFD_RELOC_ARM_T32_CP_OFF_IMM and
BFD_RELOC_ARM_T32_CP_OFF_IMM_S2.
gas/testsuite/
* gas/arm/vfp-bad_t2.d, gas/arm/vfp-bad_t2.l, arm/vfp-bad_t2.s,
gas/arm/vfp1_t2.d, gas/arm/vfp1_t2.s, gas/arm/vfp1xD_t2.d,
gas/arm/vfp1xD_t2.s, gas/arm/vfp2_t2.d, gas/arm/vfp2_t2.s): New files.
opcodes/
* arm-dis.c (coprocessor_opcodes): New.
(arm_opcodes, thumb32_opcodes): Remove coprocessor insns.
(print_insn_coprocessor): New function.
(print_insn_arm): Use print_insn_coprocessor. Remove coprocessor
format characters.
(print_insn_thumb32): Use print_insn_coprocessor.
2005-09-02 15:12:45 +02:00
|
|
|
|
}
|
2009-06-18 12:31:21 +02:00
|
|
|
|
else if (*c == '4')
|
|
|
|
|
|
func (stream, ", %c%d", single ? 's' : 'd',
|
|
|
|
|
|
regno + 1);
|
|
|
|
|
|
}
|
|
|
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
|
|
case 'L':
|
|
|
|
|
|
switch (given & 0x00400100)
|
|
|
|
|
|
{
|
|
|
|
|
|
case 0x00000000: func (stream, "b"); break;
|
|
|
|
|
|
case 0x00400000: func (stream, "h"); break;
|
|
|
|
|
|
case 0x00000100: func (stream, "w"); break;
|
|
|
|
|
|
case 0x00400100: func (stream, "d"); break;
|
|
|
|
|
|
default:
|
2005-09-02 Paul Brook <paul@codesourcery.com>
bfd/
* libbdf.h: Regenerate.
* bfd-in2.h: Regenerate.
* reloc.c: Add BFD_RELOC_ARM_T32_CP_OFF_IMM and
BFD_RELOC_ARM_T32_CP_OFF_IMM_S2.
gas/
* config/tc-arm.c (encode_arm_cp_address): Use
BFD_RELOC_ARM_T32_CP_OFF_IMM in thumb mode.
(do_iwmmxt_wldstbh): Use BFD_RELOC_ARM_T32_CP_OFF_IMM_S2 in thumb
mode.
(md_assemble): Only allow coprocessor instructions when Thumb-2 is
available.
(cCE, cC3): Define.
(insns): Use them for coprocessor instructions.
(md_pcrel_from_section): Handle BFD_RELOC_ARM_T32_CP_OFF_IMM.
(get_thumb32_insn): New function.
(put_thumb32_insn): New function.
(md_apply_fix): Handle BFD_RELOC_ARM_T32_CP_OFF_IMM and
BFD_RELOC_ARM_T32_CP_OFF_IMM_S2.
gas/testsuite/
* gas/arm/vfp-bad_t2.d, gas/arm/vfp-bad_t2.l, arm/vfp-bad_t2.s,
gas/arm/vfp1_t2.d, gas/arm/vfp1_t2.s, gas/arm/vfp1xD_t2.d,
gas/arm/vfp1xD_t2.s, gas/arm/vfp2_t2.d, gas/arm/vfp2_t2.s): New files.
opcodes/
* arm-dis.c (coprocessor_opcodes): New.
(arm_opcodes, thumb32_opcodes): Remove coprocessor insns.
(print_insn_coprocessor): New function.
(print_insn_arm): Use print_insn_coprocessor. Remove coprocessor
format characters.
(print_insn_thumb32): Use print_insn_coprocessor.
2005-09-02 15:12:45 +02:00
|
|
|
|
break;
|
2009-06-18 12:31:21 +02:00
|
|
|
|
}
|
|
|
|
|
|
break;
|
2002-11-30 09:39:46 +01:00
|
|
|
|
|
2009-06-18 12:31:21 +02:00
|
|
|
|
case 'Z':
|
|
|
|
|
|
{
|
|
|
|
|
|
/* given (20, 23) | given (0, 3) */
|
|
|
|
|
|
value = ((given >> 16) & 0xf0) | (given & 0xf);
|
2012-07-24 14:56:47 +02:00
|
|
|
|
func (stream, "%d", (int) value);
|
2009-06-18 12:31:21 +02:00
|
|
|
|
}
|
|
|
|
|
|
break;
|
bfd/
2006-09-26 Mark Shinwell <shinwell@codesourcery.com>
Joseph Myers <joseph@codesourcery.com>
Ian Lance Taylor <ian@wasabisystems.com>
Ben Elliston <bje@wasabisystems.com>
* archures.c: Add definition for bfd_mach_arm_iWMMXt2.
* cpu-arm.c (processors): Add bfd_mach_arm_iWMMXt2.
(arch_info_struct, bfd_arm_update_notes): Likewise.
(architectures): Likewise.
(bfd_arm_merge_machines): Check for iWMMXt2.
* bfd-in2.h: Rebuild.
gas/
2006-09-26 Mark Shinwell <shinwell@codesourcery.com>
Joseph Myers <joseph@codesourcery.com>
Ian Lance Taylor <ian@wasabisystems.com>
Ben Elliston <bje@wasabisystems.com>
* config/tc-arm.c (arm_cext_iwmmxt2): New.
(enum operand_parse_code): New code OP_RIWR_I32z.
(parse_operands): Handle OP_RIWR_I32z.
(do_iwmmxt_wmerge): New function.
(do_iwmmxt_wldstd): Handle iwmmxt2 case where second operand is
a register.
(do_iwmmxt_wrwrwr_or_imm5): New function.
(insns): Mark instructions as RIWR_I32z as appropriate.
Also add torvsc<b,h,w>, wabs<b,h,w>, wabsdiff<b,h,w>,
waddbhus<l,m>, waddhc, waddwc, waddsubhx, wavg4{r}, wmaddu{x,n},
wmadds{x,n}, wmerge, wmiaxy{n}, wmiawxy{n}, wmul<sm,um>{r},
wmulw<um,sm,l>{r}, wqmiaxy{n}, wqmulm{r}, wqmulwm{r}, wsubaddhx.
(md_begin): Handle IWMMXT2.
(arm_cpus): Add iwmmxt2.
(arm_extensions): Likewise.
(arm_archs): Likewise.
gas/testsuite/
2006-09-26 Mark Shinwell <shinwell@codesourcery.com>
Joseph Myers <joseph@codesourcery.com>
Ian Lance Taylor <ian@wasabisystems.com>
Ben Elliston <bje@wasabisystems.com>
* gas/arm/iwmmxt2.s: New file.
* gas/arm/iwmmxt2.d: New file.
include/opcode/
2006-09-26 Mark Shinwell <shinwell@codesourcery.com>
Joseph Myers <joseph@codesourcery.com>
Ian Lance Taylor <ian@wasabisystems.com>
Ben Elliston <bje@wasabisystems.com>
* arm.h (ARM_CEXT_IWMMXT2, ARM_ARCH_IWMMXT2): Define.
opcodes/
2006-09-26 Mark Shinwell <shinwell@codesourcery.com>
Joseph Myers <joseph@codesourcery.com>
Ian Lance Taylor <ian@wasabisystems.com>
Ben Elliston <bje@wasabisystems.com>
* arm-dis.c (coprocessor_opcodes): The X-qualifier to WMADD may
only be used with the default multiply-add operation, so if N is
set, don't bother printing X. Add new iwmmxt instructions.
(IWMMXT_INSN_COUNT): Update.
(iwmmxt_wwssnames): Qualify "wwss" names at index 2, 6, 10 and 14
with a 'c' suffix.
(print_insn_coprocessor): Check for iWMMXt2. Handle format
specifiers 'r', 'i'.
2006-09-26 14:04:45 +02:00
|
|
|
|
|
2009-06-18 12:31:21 +02:00
|
|
|
|
case 'l':
|
|
|
|
|
|
/* This is like the 'A' operator, except that if
|
|
|
|
|
|
the width field "M" is zero, then the offset is
|
|
|
|
|
|
*not* multiplied by four. */
|
|
|
|
|
|
{
|
|
|
|
|
|
int offset = given & 0xff;
|
|
|
|
|
|
int multiplier = (given & 0x00000100) ? 4 : 1;
|
|
|
|
|
|
|
|
|
|
|
|
func (stream, "[%s", arm_regnames [(given >> 16) & 0xf]);
|
|
|
|
|
|
|
2009-06-29 10:08:15 +02:00
|
|
|
|
if (multiplier > 1)
|
|
|
|
|
|
{
|
|
|
|
|
|
value_in_comment = offset * multiplier;
|
2009-11-11 10:44:45 +01:00
|
|
|
|
if (NEGATIVE_BIT_SET)
|
2009-06-29 10:08:15 +02:00
|
|
|
|
value_in_comment = - value_in_comment;
|
|
|
|
|
|
}
|
|
|
|
|
|
|
2009-06-18 12:31:21 +02:00
|
|
|
|
if (offset)
|
|
|
|
|
|
{
|
2009-11-11 10:44:45 +01:00
|
|
|
|
if (PRE_BIT_SET)
|
2009-06-18 12:31:21 +02:00
|
|
|
|
func (stream, ", #%s%d]%s",
|
2009-11-11 10:44:45 +01:00
|
|
|
|
NEGATIVE_BIT_SET ? "-" : "",
|
2009-06-18 12:31:21 +02:00
|
|
|
|
offset * multiplier,
|
2009-11-11 10:44:45 +01:00
|
|
|
|
WRITEBACK_BIT_SET ? "!" : "");
|
2009-06-18 12:31:21 +02:00
|
|
|
|
else
|
|
|
|
|
|
func (stream, "], #%s%d",
|
2009-11-11 10:44:45 +01:00
|
|
|
|
NEGATIVE_BIT_SET ? "-" : "",
|
2009-06-18 12:31:21 +02:00
|
|
|
|
offset * multiplier);
|
bfd/
2006-09-26 Mark Shinwell <shinwell@codesourcery.com>
Joseph Myers <joseph@codesourcery.com>
Ian Lance Taylor <ian@wasabisystems.com>
Ben Elliston <bje@wasabisystems.com>
* archures.c: Add definition for bfd_mach_arm_iWMMXt2.
* cpu-arm.c (processors): Add bfd_mach_arm_iWMMXt2.
(arch_info_struct, bfd_arm_update_notes): Likewise.
(architectures): Likewise.
(bfd_arm_merge_machines): Check for iWMMXt2.
* bfd-in2.h: Rebuild.
gas/
2006-09-26 Mark Shinwell <shinwell@codesourcery.com>
Joseph Myers <joseph@codesourcery.com>
Ian Lance Taylor <ian@wasabisystems.com>
Ben Elliston <bje@wasabisystems.com>
* config/tc-arm.c (arm_cext_iwmmxt2): New.
(enum operand_parse_code): New code OP_RIWR_I32z.
(parse_operands): Handle OP_RIWR_I32z.
(do_iwmmxt_wmerge): New function.
(do_iwmmxt_wldstd): Handle iwmmxt2 case where second operand is
a register.
(do_iwmmxt_wrwrwr_or_imm5): New function.
(insns): Mark instructions as RIWR_I32z as appropriate.
Also add torvsc<b,h,w>, wabs<b,h,w>, wabsdiff<b,h,w>,
waddbhus<l,m>, waddhc, waddwc, waddsubhx, wavg4{r}, wmaddu{x,n},
wmadds{x,n}, wmerge, wmiaxy{n}, wmiawxy{n}, wmul<sm,um>{r},
wmulw<um,sm,l>{r}, wqmiaxy{n}, wqmulm{r}, wqmulwm{r}, wsubaddhx.
(md_begin): Handle IWMMXT2.
(arm_cpus): Add iwmmxt2.
(arm_extensions): Likewise.
(arm_archs): Likewise.
gas/testsuite/
2006-09-26 Mark Shinwell <shinwell@codesourcery.com>
Joseph Myers <joseph@codesourcery.com>
Ian Lance Taylor <ian@wasabisystems.com>
Ben Elliston <bje@wasabisystems.com>
* gas/arm/iwmmxt2.s: New file.
* gas/arm/iwmmxt2.d: New file.
include/opcode/
2006-09-26 Mark Shinwell <shinwell@codesourcery.com>
Joseph Myers <joseph@codesourcery.com>
Ian Lance Taylor <ian@wasabisystems.com>
Ben Elliston <bje@wasabisystems.com>
* arm.h (ARM_CEXT_IWMMXT2, ARM_ARCH_IWMMXT2): Define.
opcodes/
2006-09-26 Mark Shinwell <shinwell@codesourcery.com>
Joseph Myers <joseph@codesourcery.com>
Ian Lance Taylor <ian@wasabisystems.com>
Ben Elliston <bje@wasabisystems.com>
* arm-dis.c (coprocessor_opcodes): The X-qualifier to WMADD may
only be used with the default multiply-add operation, so if N is
set, don't bother printing X. Add new iwmmxt instructions.
(IWMMXT_INSN_COUNT): Update.
(iwmmxt_wwssnames): Qualify "wwss" names at index 2, 6, 10 and 14
with a 'c' suffix.
(print_insn_coprocessor): Check for iWMMXt2. Handle format
specifiers 'r', 'i'.
2006-09-26 14:04:45 +02:00
|
|
|
|
}
|
2009-06-18 12:31:21 +02:00
|
|
|
|
else
|
|
|
|
|
|
func (stream, "]");
|
|
|
|
|
|
}
|
|
|
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
|
|
case 'r':
|
|
|
|
|
|
{
|
|
|
|
|
|
int imm4 = (given >> 4) & 0xf;
|
2009-11-11 10:44:45 +01:00
|
|
|
|
int puw_bits = ((given >> 22) & 6) | ((given >> W_BIT) & 1);
|
|
|
|
|
|
int ubit = ! NEGATIVE_BIT_SET;
|
2009-06-18 12:31:21 +02:00
|
|
|
|
const char *rm = arm_regnames [given & 0xf];
|
|
|
|
|
|
const char *rn = arm_regnames [(given >> 16) & 0xf];
|
bfd/
2006-09-26 Mark Shinwell <shinwell@codesourcery.com>
Joseph Myers <joseph@codesourcery.com>
Ian Lance Taylor <ian@wasabisystems.com>
Ben Elliston <bje@wasabisystems.com>
* archures.c: Add definition for bfd_mach_arm_iWMMXt2.
* cpu-arm.c (processors): Add bfd_mach_arm_iWMMXt2.
(arch_info_struct, bfd_arm_update_notes): Likewise.
(architectures): Likewise.
(bfd_arm_merge_machines): Check for iWMMXt2.
* bfd-in2.h: Rebuild.
gas/
2006-09-26 Mark Shinwell <shinwell@codesourcery.com>
Joseph Myers <joseph@codesourcery.com>
Ian Lance Taylor <ian@wasabisystems.com>
Ben Elliston <bje@wasabisystems.com>
* config/tc-arm.c (arm_cext_iwmmxt2): New.
(enum operand_parse_code): New code OP_RIWR_I32z.
(parse_operands): Handle OP_RIWR_I32z.
(do_iwmmxt_wmerge): New function.
(do_iwmmxt_wldstd): Handle iwmmxt2 case where second operand is
a register.
(do_iwmmxt_wrwrwr_or_imm5): New function.
(insns): Mark instructions as RIWR_I32z as appropriate.
Also add torvsc<b,h,w>, wabs<b,h,w>, wabsdiff<b,h,w>,
waddbhus<l,m>, waddhc, waddwc, waddsubhx, wavg4{r}, wmaddu{x,n},
wmadds{x,n}, wmerge, wmiaxy{n}, wmiawxy{n}, wmul<sm,um>{r},
wmulw<um,sm,l>{r}, wqmiaxy{n}, wqmulm{r}, wqmulwm{r}, wsubaddhx.
(md_begin): Handle IWMMXT2.
(arm_cpus): Add iwmmxt2.
(arm_extensions): Likewise.
(arm_archs): Likewise.
gas/testsuite/
2006-09-26 Mark Shinwell <shinwell@codesourcery.com>
Joseph Myers <joseph@codesourcery.com>
Ian Lance Taylor <ian@wasabisystems.com>
Ben Elliston <bje@wasabisystems.com>
* gas/arm/iwmmxt2.s: New file.
* gas/arm/iwmmxt2.d: New file.
include/opcode/
2006-09-26 Mark Shinwell <shinwell@codesourcery.com>
Joseph Myers <joseph@codesourcery.com>
Ian Lance Taylor <ian@wasabisystems.com>
Ben Elliston <bje@wasabisystems.com>
* arm.h (ARM_CEXT_IWMMXT2, ARM_ARCH_IWMMXT2): Define.
opcodes/
2006-09-26 Mark Shinwell <shinwell@codesourcery.com>
Joseph Myers <joseph@codesourcery.com>
Ian Lance Taylor <ian@wasabisystems.com>
Ben Elliston <bje@wasabisystems.com>
* arm-dis.c (coprocessor_opcodes): The X-qualifier to WMADD may
only be used with the default multiply-add operation, so if N is
set, don't bother printing X. Add new iwmmxt instructions.
(IWMMXT_INSN_COUNT): Update.
(iwmmxt_wwssnames): Qualify "wwss" names at index 2, 6, 10 and 14
with a 'c' suffix.
(print_insn_coprocessor): Check for iWMMXt2. Handle format
specifiers 'r', 'i'.
2006-09-26 14:04:45 +02:00
|
|
|
|
|
2009-06-18 12:31:21 +02:00
|
|
|
|
switch (puw_bits)
|
bfd/
2006-09-26 Mark Shinwell <shinwell@codesourcery.com>
Joseph Myers <joseph@codesourcery.com>
Ian Lance Taylor <ian@wasabisystems.com>
Ben Elliston <bje@wasabisystems.com>
* archures.c: Add definition for bfd_mach_arm_iWMMXt2.
* cpu-arm.c (processors): Add bfd_mach_arm_iWMMXt2.
(arch_info_struct, bfd_arm_update_notes): Likewise.
(architectures): Likewise.
(bfd_arm_merge_machines): Check for iWMMXt2.
* bfd-in2.h: Rebuild.
gas/
2006-09-26 Mark Shinwell <shinwell@codesourcery.com>
Joseph Myers <joseph@codesourcery.com>
Ian Lance Taylor <ian@wasabisystems.com>
Ben Elliston <bje@wasabisystems.com>
* config/tc-arm.c (arm_cext_iwmmxt2): New.
(enum operand_parse_code): New code OP_RIWR_I32z.
(parse_operands): Handle OP_RIWR_I32z.
(do_iwmmxt_wmerge): New function.
(do_iwmmxt_wldstd): Handle iwmmxt2 case where second operand is
a register.
(do_iwmmxt_wrwrwr_or_imm5): New function.
(insns): Mark instructions as RIWR_I32z as appropriate.
Also add torvsc<b,h,w>, wabs<b,h,w>, wabsdiff<b,h,w>,
waddbhus<l,m>, waddhc, waddwc, waddsubhx, wavg4{r}, wmaddu{x,n},
wmadds{x,n}, wmerge, wmiaxy{n}, wmiawxy{n}, wmul<sm,um>{r},
wmulw<um,sm,l>{r}, wqmiaxy{n}, wqmulm{r}, wqmulwm{r}, wsubaddhx.
(md_begin): Handle IWMMXT2.
(arm_cpus): Add iwmmxt2.
(arm_extensions): Likewise.
(arm_archs): Likewise.
gas/testsuite/
2006-09-26 Mark Shinwell <shinwell@codesourcery.com>
Joseph Myers <joseph@codesourcery.com>
Ian Lance Taylor <ian@wasabisystems.com>
Ben Elliston <bje@wasabisystems.com>
* gas/arm/iwmmxt2.s: New file.
* gas/arm/iwmmxt2.d: New file.
include/opcode/
2006-09-26 Mark Shinwell <shinwell@codesourcery.com>
Joseph Myers <joseph@codesourcery.com>
Ian Lance Taylor <ian@wasabisystems.com>
Ben Elliston <bje@wasabisystems.com>
* arm.h (ARM_CEXT_IWMMXT2, ARM_ARCH_IWMMXT2): Define.
opcodes/
2006-09-26 Mark Shinwell <shinwell@codesourcery.com>
Joseph Myers <joseph@codesourcery.com>
Ian Lance Taylor <ian@wasabisystems.com>
Ben Elliston <bje@wasabisystems.com>
* arm-dis.c (coprocessor_opcodes): The X-qualifier to WMADD may
only be used with the default multiply-add operation, so if N is
set, don't bother printing X. Add new iwmmxt instructions.
(IWMMXT_INSN_COUNT): Update.
(iwmmxt_wwssnames): Qualify "wwss" names at index 2, 6, 10 and 14
with a 'c' suffix.
(print_insn_coprocessor): Check for iWMMXt2. Handle format
specifiers 'r', 'i'.
2006-09-26 14:04:45 +02:00
|
|
|
|
{
|
2009-06-18 12:31:21 +02:00
|
|
|
|
case 1:
|
|
|
|
|
|
case 3:
|
|
|
|
|
|
func (stream, "[%s], %c%s", rn, ubit ? '+' : '-', rm);
|
|
|
|
|
|
if (imm4)
|
|
|
|
|
|
func (stream, ", lsl #%d", imm4);
|
|
|
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
|
|
case 4:
|
|
|
|
|
|
case 5:
|
|
|
|
|
|
case 6:
|
|
|
|
|
|
case 7:
|
|
|
|
|
|
func (stream, "[%s, %c%s", rn, ubit ? '+' : '-', rm);
|
|
|
|
|
|
if (imm4 > 0)
|
|
|
|
|
|
func (stream, ", lsl #%d", imm4);
|
|
|
|
|
|
func (stream, "]");
|
|
|
|
|
|
if (puw_bits == 5 || puw_bits == 7)
|
|
|
|
|
|
func (stream, "!");
|
|
|
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
|
|
default:
|
|
|
|
|
|
func (stream, "INVALID");
|
bfd/
2006-09-26 Mark Shinwell <shinwell@codesourcery.com>
Joseph Myers <joseph@codesourcery.com>
Ian Lance Taylor <ian@wasabisystems.com>
Ben Elliston <bje@wasabisystems.com>
* archures.c: Add definition for bfd_mach_arm_iWMMXt2.
* cpu-arm.c (processors): Add bfd_mach_arm_iWMMXt2.
(arch_info_struct, bfd_arm_update_notes): Likewise.
(architectures): Likewise.
(bfd_arm_merge_machines): Check for iWMMXt2.
* bfd-in2.h: Rebuild.
gas/
2006-09-26 Mark Shinwell <shinwell@codesourcery.com>
Joseph Myers <joseph@codesourcery.com>
Ian Lance Taylor <ian@wasabisystems.com>
Ben Elliston <bje@wasabisystems.com>
* config/tc-arm.c (arm_cext_iwmmxt2): New.
(enum operand_parse_code): New code OP_RIWR_I32z.
(parse_operands): Handle OP_RIWR_I32z.
(do_iwmmxt_wmerge): New function.
(do_iwmmxt_wldstd): Handle iwmmxt2 case where second operand is
a register.
(do_iwmmxt_wrwrwr_or_imm5): New function.
(insns): Mark instructions as RIWR_I32z as appropriate.
Also add torvsc<b,h,w>, wabs<b,h,w>, wabsdiff<b,h,w>,
waddbhus<l,m>, waddhc, waddwc, waddsubhx, wavg4{r}, wmaddu{x,n},
wmadds{x,n}, wmerge, wmiaxy{n}, wmiawxy{n}, wmul<sm,um>{r},
wmulw<um,sm,l>{r}, wqmiaxy{n}, wqmulm{r}, wqmulwm{r}, wsubaddhx.
(md_begin): Handle IWMMXT2.
(arm_cpus): Add iwmmxt2.
(arm_extensions): Likewise.
(arm_archs): Likewise.
gas/testsuite/
2006-09-26 Mark Shinwell <shinwell@codesourcery.com>
Joseph Myers <joseph@codesourcery.com>
Ian Lance Taylor <ian@wasabisystems.com>
Ben Elliston <bje@wasabisystems.com>
* gas/arm/iwmmxt2.s: New file.
* gas/arm/iwmmxt2.d: New file.
include/opcode/
2006-09-26 Mark Shinwell <shinwell@codesourcery.com>
Joseph Myers <joseph@codesourcery.com>
Ian Lance Taylor <ian@wasabisystems.com>
Ben Elliston <bje@wasabisystems.com>
* arm.h (ARM_CEXT_IWMMXT2, ARM_ARCH_IWMMXT2): Define.
opcodes/
2006-09-26 Mark Shinwell <shinwell@codesourcery.com>
Joseph Myers <joseph@codesourcery.com>
Ian Lance Taylor <ian@wasabisystems.com>
Ben Elliston <bje@wasabisystems.com>
* arm-dis.c (coprocessor_opcodes): The X-qualifier to WMADD may
only be used with the default multiply-add operation, so if N is
set, don't bother printing X. Add new iwmmxt instructions.
(IWMMXT_INSN_COUNT): Update.
(iwmmxt_wwssnames): Qualify "wwss" names at index 2, 6, 10 and 14
with a 'c' suffix.
(print_insn_coprocessor): Check for iWMMXt2. Handle format
specifiers 'r', 'i'.
2006-09-26 14:04:45 +02:00
|
|
|
|
}
|
2009-06-18 12:31:21 +02:00
|
|
|
|
}
|
|
|
|
|
|
break;
|
bfd/
2006-09-26 Mark Shinwell <shinwell@codesourcery.com>
Joseph Myers <joseph@codesourcery.com>
Ian Lance Taylor <ian@wasabisystems.com>
Ben Elliston <bje@wasabisystems.com>
* archures.c: Add definition for bfd_mach_arm_iWMMXt2.
* cpu-arm.c (processors): Add bfd_mach_arm_iWMMXt2.
(arch_info_struct, bfd_arm_update_notes): Likewise.
(architectures): Likewise.
(bfd_arm_merge_machines): Check for iWMMXt2.
* bfd-in2.h: Rebuild.
gas/
2006-09-26 Mark Shinwell <shinwell@codesourcery.com>
Joseph Myers <joseph@codesourcery.com>
Ian Lance Taylor <ian@wasabisystems.com>
Ben Elliston <bje@wasabisystems.com>
* config/tc-arm.c (arm_cext_iwmmxt2): New.
(enum operand_parse_code): New code OP_RIWR_I32z.
(parse_operands): Handle OP_RIWR_I32z.
(do_iwmmxt_wmerge): New function.
(do_iwmmxt_wldstd): Handle iwmmxt2 case where second operand is
a register.
(do_iwmmxt_wrwrwr_or_imm5): New function.
(insns): Mark instructions as RIWR_I32z as appropriate.
Also add torvsc<b,h,w>, wabs<b,h,w>, wabsdiff<b,h,w>,
waddbhus<l,m>, waddhc, waddwc, waddsubhx, wavg4{r}, wmaddu{x,n},
wmadds{x,n}, wmerge, wmiaxy{n}, wmiawxy{n}, wmul<sm,um>{r},
wmulw<um,sm,l>{r}, wqmiaxy{n}, wqmulm{r}, wqmulwm{r}, wsubaddhx.
(md_begin): Handle IWMMXT2.
(arm_cpus): Add iwmmxt2.
(arm_extensions): Likewise.
(arm_archs): Likewise.
gas/testsuite/
2006-09-26 Mark Shinwell <shinwell@codesourcery.com>
Joseph Myers <joseph@codesourcery.com>
Ian Lance Taylor <ian@wasabisystems.com>
Ben Elliston <bje@wasabisystems.com>
* gas/arm/iwmmxt2.s: New file.
* gas/arm/iwmmxt2.d: New file.
include/opcode/
2006-09-26 Mark Shinwell <shinwell@codesourcery.com>
Joseph Myers <joseph@codesourcery.com>
Ian Lance Taylor <ian@wasabisystems.com>
Ben Elliston <bje@wasabisystems.com>
* arm.h (ARM_CEXT_IWMMXT2, ARM_ARCH_IWMMXT2): Define.
opcodes/
2006-09-26 Mark Shinwell <shinwell@codesourcery.com>
Joseph Myers <joseph@codesourcery.com>
Ian Lance Taylor <ian@wasabisystems.com>
Ben Elliston <bje@wasabisystems.com>
* arm-dis.c (coprocessor_opcodes): The X-qualifier to WMADD may
only be used with the default multiply-add operation, so if N is
set, don't bother printing X. Add new iwmmxt instructions.
(IWMMXT_INSN_COUNT): Update.
(iwmmxt_wwssnames): Qualify "wwss" names at index 2, 6, 10 and 14
with a 'c' suffix.
(print_insn_coprocessor): Check for iWMMXt2. Handle format
specifiers 'r', 'i'.
2006-09-26 14:04:45 +02:00
|
|
|
|
|
2009-06-18 12:31:21 +02:00
|
|
|
|
case 'i':
|
|
|
|
|
|
{
|
|
|
|
|
|
long imm5;
|
|
|
|
|
|
imm5 = ((given & 0x100) >> 4) | (given & 0xf);
|
|
|
|
|
|
func (stream, "%ld", (imm5 == 0) ? 32 : imm5);
|
2005-09-02 Paul Brook <paul@codesourcery.com>
bfd/
* libbdf.h: Regenerate.
* bfd-in2.h: Regenerate.
* reloc.c: Add BFD_RELOC_ARM_T32_CP_OFF_IMM and
BFD_RELOC_ARM_T32_CP_OFF_IMM_S2.
gas/
* config/tc-arm.c (encode_arm_cp_address): Use
BFD_RELOC_ARM_T32_CP_OFF_IMM in thumb mode.
(do_iwmmxt_wldstbh): Use BFD_RELOC_ARM_T32_CP_OFF_IMM_S2 in thumb
mode.
(md_assemble): Only allow coprocessor instructions when Thumb-2 is
available.
(cCE, cC3): Define.
(insns): Use them for coprocessor instructions.
(md_pcrel_from_section): Handle BFD_RELOC_ARM_T32_CP_OFF_IMM.
(get_thumb32_insn): New function.
(put_thumb32_insn): New function.
(md_apply_fix): Handle BFD_RELOC_ARM_T32_CP_OFF_IMM and
BFD_RELOC_ARM_T32_CP_OFF_IMM_S2.
gas/testsuite/
* gas/arm/vfp-bad_t2.d, gas/arm/vfp-bad_t2.l, arm/vfp-bad_t2.s,
gas/arm/vfp1_t2.d, gas/arm/vfp1_t2.s, gas/arm/vfp1xD_t2.d,
gas/arm/vfp1xD_t2.s, gas/arm/vfp2_t2.d, gas/arm/vfp2_t2.s): New files.
opcodes/
* arm-dis.c (coprocessor_opcodes): New.
(arm_opcodes, thumb32_opcodes): Remove coprocessor insns.
(print_insn_coprocessor): New function.
(print_insn_arm): Use print_insn_coprocessor. Remove coprocessor
format characters.
(print_insn_thumb32): Use print_insn_coprocessor.
2005-09-02 15:12:45 +02:00
|
|
|
|
}
|
2009-06-18 12:31:21 +02:00
|
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
|
|
default:
|
|
|
|
|
|
abort ();
|
|
|
|
|
|
}
|
1999-05-03 09:29:11 +02:00
|
|
|
|
}
|
|
|
|
|
|
}
|
2009-06-18 12:31:21 +02:00
|
|
|
|
else
|
|
|
|
|
|
func (stream, "%c", *c);
|
1999-05-03 09:29:11 +02:00
|
|
|
|
}
|
2009-06-29 10:08:15 +02:00
|
|
|
|
|
|
|
|
|
|
if (value_in_comment > 32 || value_in_comment < -16)
|
2009-07-10 18:58:54 +02:00
|
|
|
|
func (stream, "\t; 0x%lx", (value_in_comment & 0xffffffffUL));
|
2009-06-29 10:08:15 +02:00
|
|
|
|
|
2009-12-17 10:52:18 +01:00
|
|
|
|
if (is_unpredictable)
|
|
|
|
|
|
func (stream, UNPREDICTABLE_INSTRUCTION);
|
|
|
|
|
|
|
2009-06-18 12:31:21 +02:00
|
|
|
|
return TRUE;
|
1999-05-03 09:29:11 +02:00
|
|
|
|
}
|
2005-09-02 Paul Brook <paul@codesourcery.com>
bfd/
* libbdf.h: Regenerate.
* bfd-in2.h: Regenerate.
* reloc.c: Add BFD_RELOC_ARM_T32_CP_OFF_IMM and
BFD_RELOC_ARM_T32_CP_OFF_IMM_S2.
gas/
* config/tc-arm.c (encode_arm_cp_address): Use
BFD_RELOC_ARM_T32_CP_OFF_IMM in thumb mode.
(do_iwmmxt_wldstbh): Use BFD_RELOC_ARM_T32_CP_OFF_IMM_S2 in thumb
mode.
(md_assemble): Only allow coprocessor instructions when Thumb-2 is
available.
(cCE, cC3): Define.
(insns): Use them for coprocessor instructions.
(md_pcrel_from_section): Handle BFD_RELOC_ARM_T32_CP_OFF_IMM.
(get_thumb32_insn): New function.
(put_thumb32_insn): New function.
(md_apply_fix): Handle BFD_RELOC_ARM_T32_CP_OFF_IMM and
BFD_RELOC_ARM_T32_CP_OFF_IMM_S2.
gas/testsuite/
* gas/arm/vfp-bad_t2.d, gas/arm/vfp-bad_t2.l, arm/vfp-bad_t2.s,
gas/arm/vfp1_t2.d, gas/arm/vfp1_t2.s, gas/arm/vfp1xD_t2.d,
gas/arm/vfp1xD_t2.s, gas/arm/vfp2_t2.d, gas/arm/vfp2_t2.s): New files.
opcodes/
* arm-dis.c (coprocessor_opcodes): New.
(arm_opcodes, thumb32_opcodes): Remove coprocessor insns.
(print_insn_coprocessor): New function.
(print_insn_arm): Use print_insn_coprocessor. Remove coprocessor
format characters.
(print_insn_thumb32): Use print_insn_coprocessor.
2005-09-02 15:12:45 +02:00
|
|
|
|
return FALSE;
|
1999-05-03 09:29:11 +02:00
|
|
|
|
}
|
|
|
|
|
|
|
2009-06-29 10:08:15 +02:00
|
|
|
|
/* Decodes and prints ARM addressing modes. Returns the offset
|
|
|
|
|
|
used in the address, if any, if it is worthwhile printing the
|
|
|
|
|
|
offset as a hexadecimal value in a comment at the end of the
|
|
|
|
|
|
line of disassembly. */
|
|
|
|
|
|
|
|
|
|
|
|
static signed long
|
2006-02-24 Paul Brook <paul@codesourcery.com>
gas/
* config/arm/tc-arm.c (arm_ext_v6_notm, arm_ext_div, arm_ext_v7,
arm_ext_v7a, arm_ext_v7r, arm_ext_v7m): New variables.
(struct asm_barrier_opt): Define.
(arm_v7m_psr_hsh, arm_barrier_opt_hsh): New variables.
(parse_psr): Accept V7M psr names.
(parse_barrier): New function.
(enum operand_parse_code): Add OP_oBARRIER.
(parse_operands): Implement OP_oBARRIER.
(do_barrier): New function.
(do_dbg, do_pli, do_t_barrier, do_t_dbg, do_t_div): New functions.
(do_t_cpsi): Add V7M restrictions.
(do_t_mrs, do_t_msr): Validate V7M variants.
(md_assemble): Check for NULL variants.
(v7m_psrs, barrier_opt_names): New tables.
(insns): Add V7 instructions. Mark V6 instructions absent from V7M.
(md_begin): Initialize arm_v7m_psr_hsh and arm_barrier_opt_hsh.
(arm_cpu_option_table): Add Cortex-M3, R4 and A8.
(arm_arch_option_table): Add armv7, armv7a, armv7r and armv7m.
(struct cpu_arch_ver_table): Define.
(cpu_arch_ver): New.
(aeabi_set_public_attributes): Use cpu_arch_ver. Set
Tag_CPU_arch_profile.
* doc/c-arm.texi: Document new cpu and arch options.
gas/testsuite/
* gas/arm/thumb32.d: Fix expected msr and mrs output.
* gas/arm/arch7.d: New test.
* gas/arm/arch7.s: New test.
* gas/arm/arch7m-bad.l: New test.
* gas/arm/arch7m-bad.d: New test.
* gas/arm/arch7m-bad.s: New test.
include/opcode/
* arm.h: Add V7 feature bits.
opcodes/
* arm-dis.c (arm_opcodes): Add V7 instructions.
(thumb32_opcodes): Ditto. Handle V7M MSR/MRS variants.
(print_arm_address): New function.
(print_insn_arm): Use it. Add 'P' and 'U' cases.
(psr_name): New function.
(print_insn_thumb32): Add 'U', 'C' and 'D' cases.
2006-02-24 16:36:36 +01:00
|
|
|
|
print_arm_address (bfd_vma pc, struct disassemble_info *info, long given)
|
|
|
|
|
|
{
|
|
|
|
|
|
void *stream = info->stream;
|
|
|
|
|
|
fprintf_ftype func = info->fprintf_func;
|
2011-06-03 12:04:03 +02:00
|
|
|
|
bfd_vma offset = 0;
|
2006-02-24 Paul Brook <paul@codesourcery.com>
gas/
* config/arm/tc-arm.c (arm_ext_v6_notm, arm_ext_div, arm_ext_v7,
arm_ext_v7a, arm_ext_v7r, arm_ext_v7m): New variables.
(struct asm_barrier_opt): Define.
(arm_v7m_psr_hsh, arm_barrier_opt_hsh): New variables.
(parse_psr): Accept V7M psr names.
(parse_barrier): New function.
(enum operand_parse_code): Add OP_oBARRIER.
(parse_operands): Implement OP_oBARRIER.
(do_barrier): New function.
(do_dbg, do_pli, do_t_barrier, do_t_dbg, do_t_div): New functions.
(do_t_cpsi): Add V7M restrictions.
(do_t_mrs, do_t_msr): Validate V7M variants.
(md_assemble): Check for NULL variants.
(v7m_psrs, barrier_opt_names): New tables.
(insns): Add V7 instructions. Mark V6 instructions absent from V7M.
(md_begin): Initialize arm_v7m_psr_hsh and arm_barrier_opt_hsh.
(arm_cpu_option_table): Add Cortex-M3, R4 and A8.
(arm_arch_option_table): Add armv7, armv7a, armv7r and armv7m.
(struct cpu_arch_ver_table): Define.
(cpu_arch_ver): New.
(aeabi_set_public_attributes): Use cpu_arch_ver. Set
Tag_CPU_arch_profile.
* doc/c-arm.texi: Document new cpu and arch options.
gas/testsuite/
* gas/arm/thumb32.d: Fix expected msr and mrs output.
* gas/arm/arch7.d: New test.
* gas/arm/arch7.s: New test.
* gas/arm/arch7m-bad.l: New test.
* gas/arm/arch7m-bad.d: New test.
* gas/arm/arch7m-bad.s: New test.
include/opcode/
* arm.h: Add V7 feature bits.
opcodes/
* arm-dis.c (arm_opcodes): Add V7 instructions.
(thumb32_opcodes): Ditto. Handle V7M MSR/MRS variants.
(print_arm_address): New function.
(print_insn_arm): Use it. Add 'P' and 'U' cases.
(psr_name): New function.
(print_insn_thumb32): Add 'U', 'C' and 'D' cases.
2006-02-24 16:36:36 +01:00
|
|
|
|
|
|
|
|
|
|
if (((given & 0x000f0000) == 0x000f0000)
|
|
|
|
|
|
&& ((given & 0x02000000) == 0))
|
|
|
|
|
|
{
|
2009-06-29 10:08:15 +02:00
|
|
|
|
offset = given & 0xfff;
|
2006-02-24 Paul Brook <paul@codesourcery.com>
gas/
* config/arm/tc-arm.c (arm_ext_v6_notm, arm_ext_div, arm_ext_v7,
arm_ext_v7a, arm_ext_v7r, arm_ext_v7m): New variables.
(struct asm_barrier_opt): Define.
(arm_v7m_psr_hsh, arm_barrier_opt_hsh): New variables.
(parse_psr): Accept V7M psr names.
(parse_barrier): New function.
(enum operand_parse_code): Add OP_oBARRIER.
(parse_operands): Implement OP_oBARRIER.
(do_barrier): New function.
(do_dbg, do_pli, do_t_barrier, do_t_dbg, do_t_div): New functions.
(do_t_cpsi): Add V7M restrictions.
(do_t_mrs, do_t_msr): Validate V7M variants.
(md_assemble): Check for NULL variants.
(v7m_psrs, barrier_opt_names): New tables.
(insns): Add V7 instructions. Mark V6 instructions absent from V7M.
(md_begin): Initialize arm_v7m_psr_hsh and arm_barrier_opt_hsh.
(arm_cpu_option_table): Add Cortex-M3, R4 and A8.
(arm_arch_option_table): Add armv7, armv7a, armv7r and armv7m.
(struct cpu_arch_ver_table): Define.
(cpu_arch_ver): New.
(aeabi_set_public_attributes): Use cpu_arch_ver. Set
Tag_CPU_arch_profile.
* doc/c-arm.texi: Document new cpu and arch options.
gas/testsuite/
* gas/arm/thumb32.d: Fix expected msr and mrs output.
* gas/arm/arch7.d: New test.
* gas/arm/arch7.s: New test.
* gas/arm/arch7m-bad.l: New test.
* gas/arm/arch7m-bad.d: New test.
* gas/arm/arch7m-bad.s: New test.
include/opcode/
* arm.h: Add V7 feature bits.
opcodes/
* arm-dis.c (arm_opcodes): Add V7 instructions.
(thumb32_opcodes): Ditto. Handle V7M MSR/MRS variants.
(print_arm_address): New function.
(print_insn_arm): Use it. Add 'P' and 'U' cases.
(psr_name): New function.
(print_insn_thumb32): Add 'U', 'C' and 'D' cases.
2006-02-24 16:36:36 +01:00
|
|
|
|
|
|
|
|
|
|
func (stream, "[pc");
|
|
|
|
|
|
|
2009-11-11 10:44:45 +01:00
|
|
|
|
if (PRE_BIT_SET)
|
2006-02-24 Paul Brook <paul@codesourcery.com>
gas/
* config/arm/tc-arm.c (arm_ext_v6_notm, arm_ext_div, arm_ext_v7,
arm_ext_v7a, arm_ext_v7r, arm_ext_v7m): New variables.
(struct asm_barrier_opt): Define.
(arm_v7m_psr_hsh, arm_barrier_opt_hsh): New variables.
(parse_psr): Accept V7M psr names.
(parse_barrier): New function.
(enum operand_parse_code): Add OP_oBARRIER.
(parse_operands): Implement OP_oBARRIER.
(do_barrier): New function.
(do_dbg, do_pli, do_t_barrier, do_t_dbg, do_t_div): New functions.
(do_t_cpsi): Add V7M restrictions.
(do_t_mrs, do_t_msr): Validate V7M variants.
(md_assemble): Check for NULL variants.
(v7m_psrs, barrier_opt_names): New tables.
(insns): Add V7 instructions. Mark V6 instructions absent from V7M.
(md_begin): Initialize arm_v7m_psr_hsh and arm_barrier_opt_hsh.
(arm_cpu_option_table): Add Cortex-M3, R4 and A8.
(arm_arch_option_table): Add armv7, armv7a, armv7r and armv7m.
(struct cpu_arch_ver_table): Define.
(cpu_arch_ver): New.
(aeabi_set_public_attributes): Use cpu_arch_ver. Set
Tag_CPU_arch_profile.
* doc/c-arm.texi: Document new cpu and arch options.
gas/testsuite/
* gas/arm/thumb32.d: Fix expected msr and mrs output.
* gas/arm/arch7.d: New test.
* gas/arm/arch7.s: New test.
* gas/arm/arch7m-bad.l: New test.
* gas/arm/arch7m-bad.d: New test.
* gas/arm/arch7m-bad.s: New test.
include/opcode/
* arm.h: Add V7 feature bits.
opcodes/
* arm-dis.c (arm_opcodes): Add V7 instructions.
(thumb32_opcodes): Ditto. Handle V7M MSR/MRS variants.
(print_arm_address): New function.
(print_insn_arm): Use it. Add 'P' and 'U' cases.
(psr_name): New function.
(print_insn_thumb32): Add 'U', 'C' and 'D' cases.
2006-02-24 16:36:36 +01:00
|
|
|
|
{
|
2011-06-02 17:32:10 +02:00
|
|
|
|
/* Pre-indexed. Elide offset of positive zero when
|
|
|
|
|
|
non-writeback. */
|
|
|
|
|
|
if (WRITEBACK_BIT_SET || NEGATIVE_BIT_SET || offset)
|
2012-07-24 14:56:47 +02:00
|
|
|
|
func (stream, ", #%s%d", NEGATIVE_BIT_SET ? "-" : "", (int) offset);
|
2011-06-02 17:32:10 +02:00
|
|
|
|
|
|
|
|
|
|
if (NEGATIVE_BIT_SET)
|
|
|
|
|
|
offset = -offset;
|
2006-02-24 Paul Brook <paul@codesourcery.com>
gas/
* config/arm/tc-arm.c (arm_ext_v6_notm, arm_ext_div, arm_ext_v7,
arm_ext_v7a, arm_ext_v7r, arm_ext_v7m): New variables.
(struct asm_barrier_opt): Define.
(arm_v7m_psr_hsh, arm_barrier_opt_hsh): New variables.
(parse_psr): Accept V7M psr names.
(parse_barrier): New function.
(enum operand_parse_code): Add OP_oBARRIER.
(parse_operands): Implement OP_oBARRIER.
(do_barrier): New function.
(do_dbg, do_pli, do_t_barrier, do_t_dbg, do_t_div): New functions.
(do_t_cpsi): Add V7M restrictions.
(do_t_mrs, do_t_msr): Validate V7M variants.
(md_assemble): Check for NULL variants.
(v7m_psrs, barrier_opt_names): New tables.
(insns): Add V7 instructions. Mark V6 instructions absent from V7M.
(md_begin): Initialize arm_v7m_psr_hsh and arm_barrier_opt_hsh.
(arm_cpu_option_table): Add Cortex-M3, R4 and A8.
(arm_arch_option_table): Add armv7, armv7a, armv7r and armv7m.
(struct cpu_arch_ver_table): Define.
(cpu_arch_ver): New.
(aeabi_set_public_attributes): Use cpu_arch_ver. Set
Tag_CPU_arch_profile.
* doc/c-arm.texi: Document new cpu and arch options.
gas/testsuite/
* gas/arm/thumb32.d: Fix expected msr and mrs output.
* gas/arm/arch7.d: New test.
* gas/arm/arch7.s: New test.
* gas/arm/arch7m-bad.l: New test.
* gas/arm/arch7m-bad.d: New test.
* gas/arm/arch7m-bad.s: New test.
include/opcode/
* arm.h: Add V7 feature bits.
opcodes/
* arm-dis.c (arm_opcodes): Add V7 instructions.
(thumb32_opcodes): Ditto. Handle V7M MSR/MRS variants.
(print_arm_address): New function.
(print_insn_arm): Use it. Add 'P' and 'U' cases.
(psr_name): New function.
(print_insn_thumb32): Add 'U', 'C' and 'D' cases.
2006-02-24 16:36:36 +01:00
|
|
|
|
|
|
|
|
|
|
offset += pc + 8;
|
|
|
|
|
|
|
|
|
|
|
|
/* Cope with the possibility of write-back
|
|
|
|
|
|
being used. Probably a very dangerous thing
|
|
|
|
|
|
for the programmer to do, but who are we to
|
|
|
|
|
|
argue ? */
|
2011-06-02 17:32:10 +02:00
|
|
|
|
func (stream, "]%s", WRITEBACK_BIT_SET ? "!" : "");
|
2006-02-24 Paul Brook <paul@codesourcery.com>
gas/
* config/arm/tc-arm.c (arm_ext_v6_notm, arm_ext_div, arm_ext_v7,
arm_ext_v7a, arm_ext_v7r, arm_ext_v7m): New variables.
(struct asm_barrier_opt): Define.
(arm_v7m_psr_hsh, arm_barrier_opt_hsh): New variables.
(parse_psr): Accept V7M psr names.
(parse_barrier): New function.
(enum operand_parse_code): Add OP_oBARRIER.
(parse_operands): Implement OP_oBARRIER.
(do_barrier): New function.
(do_dbg, do_pli, do_t_barrier, do_t_dbg, do_t_div): New functions.
(do_t_cpsi): Add V7M restrictions.
(do_t_mrs, do_t_msr): Validate V7M variants.
(md_assemble): Check for NULL variants.
(v7m_psrs, barrier_opt_names): New tables.
(insns): Add V7 instructions. Mark V6 instructions absent from V7M.
(md_begin): Initialize arm_v7m_psr_hsh and arm_barrier_opt_hsh.
(arm_cpu_option_table): Add Cortex-M3, R4 and A8.
(arm_arch_option_table): Add armv7, armv7a, armv7r and armv7m.
(struct cpu_arch_ver_table): Define.
(cpu_arch_ver): New.
(aeabi_set_public_attributes): Use cpu_arch_ver. Set
Tag_CPU_arch_profile.
* doc/c-arm.texi: Document new cpu and arch options.
gas/testsuite/
* gas/arm/thumb32.d: Fix expected msr and mrs output.
* gas/arm/arch7.d: New test.
* gas/arm/arch7.s: New test.
* gas/arm/arch7m-bad.l: New test.
* gas/arm/arch7m-bad.d: New test.
* gas/arm/arch7m-bad.s: New test.
include/opcode/
* arm.h: Add V7 feature bits.
opcodes/
* arm-dis.c (arm_opcodes): Add V7 instructions.
(thumb32_opcodes): Ditto. Handle V7M MSR/MRS variants.
(print_arm_address): New function.
(print_insn_arm): Use it. Add 'P' and 'U' cases.
(psr_name): New function.
(print_insn_thumb32): Add 'U', 'C' and 'D' cases.
2006-02-24 16:36:36 +01:00
|
|
|
|
}
|
2009-11-11 10:44:45 +01:00
|
|
|
|
else /* Post indexed. */
|
2006-02-24 Paul Brook <paul@codesourcery.com>
gas/
* config/arm/tc-arm.c (arm_ext_v6_notm, arm_ext_div, arm_ext_v7,
arm_ext_v7a, arm_ext_v7r, arm_ext_v7m): New variables.
(struct asm_barrier_opt): Define.
(arm_v7m_psr_hsh, arm_barrier_opt_hsh): New variables.
(parse_psr): Accept V7M psr names.
(parse_barrier): New function.
(enum operand_parse_code): Add OP_oBARRIER.
(parse_operands): Implement OP_oBARRIER.
(do_barrier): New function.
(do_dbg, do_pli, do_t_barrier, do_t_dbg, do_t_div): New functions.
(do_t_cpsi): Add V7M restrictions.
(do_t_mrs, do_t_msr): Validate V7M variants.
(md_assemble): Check for NULL variants.
(v7m_psrs, barrier_opt_names): New tables.
(insns): Add V7 instructions. Mark V6 instructions absent from V7M.
(md_begin): Initialize arm_v7m_psr_hsh and arm_barrier_opt_hsh.
(arm_cpu_option_table): Add Cortex-M3, R4 and A8.
(arm_arch_option_table): Add armv7, armv7a, armv7r and armv7m.
(struct cpu_arch_ver_table): Define.
(cpu_arch_ver): New.
(aeabi_set_public_attributes): Use cpu_arch_ver. Set
Tag_CPU_arch_profile.
* doc/c-arm.texi: Document new cpu and arch options.
gas/testsuite/
* gas/arm/thumb32.d: Fix expected msr and mrs output.
* gas/arm/arch7.d: New test.
* gas/arm/arch7.s: New test.
* gas/arm/arch7m-bad.l: New test.
* gas/arm/arch7m-bad.d: New test.
* gas/arm/arch7m-bad.s: New test.
include/opcode/
* arm.h: Add V7 feature bits.
opcodes/
* arm-dis.c (arm_opcodes): Add V7 instructions.
(thumb32_opcodes): Ditto. Handle V7M MSR/MRS variants.
(print_arm_address): New function.
(print_insn_arm): Use it. Add 'P' and 'U' cases.
(psr_name): New function.
(print_insn_thumb32): Add 'U', 'C' and 'D' cases.
2006-02-24 16:36:36 +01:00
|
|
|
|
{
|
2012-07-24 14:56:47 +02:00
|
|
|
|
func (stream, "], #%s%d", NEGATIVE_BIT_SET ? "-" : "", (int) offset);
|
2006-02-24 Paul Brook <paul@codesourcery.com>
gas/
* config/arm/tc-arm.c (arm_ext_v6_notm, arm_ext_div, arm_ext_v7,
arm_ext_v7a, arm_ext_v7r, arm_ext_v7m): New variables.
(struct asm_barrier_opt): Define.
(arm_v7m_psr_hsh, arm_barrier_opt_hsh): New variables.
(parse_psr): Accept V7M psr names.
(parse_barrier): New function.
(enum operand_parse_code): Add OP_oBARRIER.
(parse_operands): Implement OP_oBARRIER.
(do_barrier): New function.
(do_dbg, do_pli, do_t_barrier, do_t_dbg, do_t_div): New functions.
(do_t_cpsi): Add V7M restrictions.
(do_t_mrs, do_t_msr): Validate V7M variants.
(md_assemble): Check for NULL variants.
(v7m_psrs, barrier_opt_names): New tables.
(insns): Add V7 instructions. Mark V6 instructions absent from V7M.
(md_begin): Initialize arm_v7m_psr_hsh and arm_barrier_opt_hsh.
(arm_cpu_option_table): Add Cortex-M3, R4 and A8.
(arm_arch_option_table): Add armv7, armv7a, armv7r and armv7m.
(struct cpu_arch_ver_table): Define.
(cpu_arch_ver): New.
(aeabi_set_public_attributes): Use cpu_arch_ver. Set
Tag_CPU_arch_profile.
* doc/c-arm.texi: Document new cpu and arch options.
gas/testsuite/
* gas/arm/thumb32.d: Fix expected msr and mrs output.
* gas/arm/arch7.d: New test.
* gas/arm/arch7.s: New test.
* gas/arm/arch7m-bad.l: New test.
* gas/arm/arch7m-bad.d: New test.
* gas/arm/arch7m-bad.s: New test.
include/opcode/
* arm.h: Add V7 feature bits.
opcodes/
* arm-dis.c (arm_opcodes): Add V7 instructions.
(thumb32_opcodes): Ditto. Handle V7M MSR/MRS variants.
(print_arm_address): New function.
(print_insn_arm): Use it. Add 'P' and 'U' cases.
(psr_name): New function.
(print_insn_thumb32): Add 'U', 'C' and 'D' cases.
2006-02-24 16:36:36 +01:00
|
|
|
|
|
2009-11-11 10:44:45 +01:00
|
|
|
|
/* Ie ignore the offset. */
|
2006-02-24 Paul Brook <paul@codesourcery.com>
gas/
* config/arm/tc-arm.c (arm_ext_v6_notm, arm_ext_div, arm_ext_v7,
arm_ext_v7a, arm_ext_v7r, arm_ext_v7m): New variables.
(struct asm_barrier_opt): Define.
(arm_v7m_psr_hsh, arm_barrier_opt_hsh): New variables.
(parse_psr): Accept V7M psr names.
(parse_barrier): New function.
(enum operand_parse_code): Add OP_oBARRIER.
(parse_operands): Implement OP_oBARRIER.
(do_barrier): New function.
(do_dbg, do_pli, do_t_barrier, do_t_dbg, do_t_div): New functions.
(do_t_cpsi): Add V7M restrictions.
(do_t_mrs, do_t_msr): Validate V7M variants.
(md_assemble): Check for NULL variants.
(v7m_psrs, barrier_opt_names): New tables.
(insns): Add V7 instructions. Mark V6 instructions absent from V7M.
(md_begin): Initialize arm_v7m_psr_hsh and arm_barrier_opt_hsh.
(arm_cpu_option_table): Add Cortex-M3, R4 and A8.
(arm_arch_option_table): Add armv7, armv7a, armv7r and armv7m.
(struct cpu_arch_ver_table): Define.
(cpu_arch_ver): New.
(aeabi_set_public_attributes): Use cpu_arch_ver. Set
Tag_CPU_arch_profile.
* doc/c-arm.texi: Document new cpu and arch options.
gas/testsuite/
* gas/arm/thumb32.d: Fix expected msr and mrs output.
* gas/arm/arch7.d: New test.
* gas/arm/arch7.s: New test.
* gas/arm/arch7m-bad.l: New test.
* gas/arm/arch7m-bad.d: New test.
* gas/arm/arch7m-bad.s: New test.
include/opcode/
* arm.h: Add V7 feature bits.
opcodes/
* arm-dis.c (arm_opcodes): Add V7 instructions.
(thumb32_opcodes): Ditto. Handle V7M MSR/MRS variants.
(print_arm_address): New function.
(print_insn_arm): Use it. Add 'P' and 'U' cases.
(psr_name): New function.
(print_insn_thumb32): Add 'U', 'C' and 'D' cases.
2006-02-24 16:36:36 +01:00
|
|
|
|
offset = pc + 8;
|
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
func (stream, "\t; ");
|
|
|
|
|
|
info->print_address_func (offset, info);
|
2009-06-29 10:08:15 +02:00
|
|
|
|
offset = 0;
|
2006-02-24 Paul Brook <paul@codesourcery.com>
gas/
* config/arm/tc-arm.c (arm_ext_v6_notm, arm_ext_div, arm_ext_v7,
arm_ext_v7a, arm_ext_v7r, arm_ext_v7m): New variables.
(struct asm_barrier_opt): Define.
(arm_v7m_psr_hsh, arm_barrier_opt_hsh): New variables.
(parse_psr): Accept V7M psr names.
(parse_barrier): New function.
(enum operand_parse_code): Add OP_oBARRIER.
(parse_operands): Implement OP_oBARRIER.
(do_barrier): New function.
(do_dbg, do_pli, do_t_barrier, do_t_dbg, do_t_div): New functions.
(do_t_cpsi): Add V7M restrictions.
(do_t_mrs, do_t_msr): Validate V7M variants.
(md_assemble): Check for NULL variants.
(v7m_psrs, barrier_opt_names): New tables.
(insns): Add V7 instructions. Mark V6 instructions absent from V7M.
(md_begin): Initialize arm_v7m_psr_hsh and arm_barrier_opt_hsh.
(arm_cpu_option_table): Add Cortex-M3, R4 and A8.
(arm_arch_option_table): Add armv7, armv7a, armv7r and armv7m.
(struct cpu_arch_ver_table): Define.
(cpu_arch_ver): New.
(aeabi_set_public_attributes): Use cpu_arch_ver. Set
Tag_CPU_arch_profile.
* doc/c-arm.texi: Document new cpu and arch options.
gas/testsuite/
* gas/arm/thumb32.d: Fix expected msr and mrs output.
* gas/arm/arch7.d: New test.
* gas/arm/arch7.s: New test.
* gas/arm/arch7m-bad.l: New test.
* gas/arm/arch7m-bad.d: New test.
* gas/arm/arch7m-bad.s: New test.
include/opcode/
* arm.h: Add V7 feature bits.
opcodes/
* arm-dis.c (arm_opcodes): Add V7 instructions.
(thumb32_opcodes): Ditto. Handle V7M MSR/MRS variants.
(print_arm_address): New function.
(print_insn_arm): Use it. Add 'P' and 'U' cases.
(psr_name): New function.
(print_insn_thumb32): Add 'U', 'C' and 'D' cases.
2006-02-24 16:36:36 +01:00
|
|
|
|
}
|
|
|
|
|
|
else
|
|
|
|
|
|
{
|
|
|
|
|
|
func (stream, "[%s",
|
|
|
|
|
|
arm_regnames[(given >> 16) & 0xf]);
|
2009-11-11 10:44:45 +01:00
|
|
|
|
|
|
|
|
|
|
if (PRE_BIT_SET)
|
2006-02-24 Paul Brook <paul@codesourcery.com>
gas/
* config/arm/tc-arm.c (arm_ext_v6_notm, arm_ext_div, arm_ext_v7,
arm_ext_v7a, arm_ext_v7r, arm_ext_v7m): New variables.
(struct asm_barrier_opt): Define.
(arm_v7m_psr_hsh, arm_barrier_opt_hsh): New variables.
(parse_psr): Accept V7M psr names.
(parse_barrier): New function.
(enum operand_parse_code): Add OP_oBARRIER.
(parse_operands): Implement OP_oBARRIER.
(do_barrier): New function.
(do_dbg, do_pli, do_t_barrier, do_t_dbg, do_t_div): New functions.
(do_t_cpsi): Add V7M restrictions.
(do_t_mrs, do_t_msr): Validate V7M variants.
(md_assemble): Check for NULL variants.
(v7m_psrs, barrier_opt_names): New tables.
(insns): Add V7 instructions. Mark V6 instructions absent from V7M.
(md_begin): Initialize arm_v7m_psr_hsh and arm_barrier_opt_hsh.
(arm_cpu_option_table): Add Cortex-M3, R4 and A8.
(arm_arch_option_table): Add armv7, armv7a, armv7r and armv7m.
(struct cpu_arch_ver_table): Define.
(cpu_arch_ver): New.
(aeabi_set_public_attributes): Use cpu_arch_ver. Set
Tag_CPU_arch_profile.
* doc/c-arm.texi: Document new cpu and arch options.
gas/testsuite/
* gas/arm/thumb32.d: Fix expected msr and mrs output.
* gas/arm/arch7.d: New test.
* gas/arm/arch7.s: New test.
* gas/arm/arch7m-bad.l: New test.
* gas/arm/arch7m-bad.d: New test.
* gas/arm/arch7m-bad.s: New test.
include/opcode/
* arm.h: Add V7 feature bits.
opcodes/
* arm-dis.c (arm_opcodes): Add V7 instructions.
(thumb32_opcodes): Ditto. Handle V7M MSR/MRS variants.
(print_arm_address): New function.
(print_insn_arm): Use it. Add 'P' and 'U' cases.
(psr_name): New function.
(print_insn_thumb32): Add 'U', 'C' and 'D' cases.
2006-02-24 16:36:36 +01:00
|
|
|
|
{
|
|
|
|
|
|
if ((given & 0x02000000) == 0)
|
|
|
|
|
|
{
|
2011-06-02 17:32:10 +02:00
|
|
|
|
/* Elide offset of positive zero when non-writeback. */
|
2009-06-29 10:08:15 +02:00
|
|
|
|
offset = given & 0xfff;
|
2011-06-02 17:32:10 +02:00
|
|
|
|
if (WRITEBACK_BIT_SET || NEGATIVE_BIT_SET || offset)
|
2012-07-24 14:56:47 +02:00
|
|
|
|
func (stream, ", #%s%d", NEGATIVE_BIT_SET ? "-" : "", (int) offset);
|
2006-02-24 Paul Brook <paul@codesourcery.com>
gas/
* config/arm/tc-arm.c (arm_ext_v6_notm, arm_ext_div, arm_ext_v7,
arm_ext_v7a, arm_ext_v7r, arm_ext_v7m): New variables.
(struct asm_barrier_opt): Define.
(arm_v7m_psr_hsh, arm_barrier_opt_hsh): New variables.
(parse_psr): Accept V7M psr names.
(parse_barrier): New function.
(enum operand_parse_code): Add OP_oBARRIER.
(parse_operands): Implement OP_oBARRIER.
(do_barrier): New function.
(do_dbg, do_pli, do_t_barrier, do_t_dbg, do_t_div): New functions.
(do_t_cpsi): Add V7M restrictions.
(do_t_mrs, do_t_msr): Validate V7M variants.
(md_assemble): Check for NULL variants.
(v7m_psrs, barrier_opt_names): New tables.
(insns): Add V7 instructions. Mark V6 instructions absent from V7M.
(md_begin): Initialize arm_v7m_psr_hsh and arm_barrier_opt_hsh.
(arm_cpu_option_table): Add Cortex-M3, R4 and A8.
(arm_arch_option_table): Add armv7, armv7a, armv7r and armv7m.
(struct cpu_arch_ver_table): Define.
(cpu_arch_ver): New.
(aeabi_set_public_attributes): Use cpu_arch_ver. Set
Tag_CPU_arch_profile.
* doc/c-arm.texi: Document new cpu and arch options.
gas/testsuite/
* gas/arm/thumb32.d: Fix expected msr and mrs output.
* gas/arm/arch7.d: New test.
* gas/arm/arch7.s: New test.
* gas/arm/arch7m-bad.l: New test.
* gas/arm/arch7m-bad.d: New test.
* gas/arm/arch7m-bad.s: New test.
include/opcode/
* arm.h: Add V7 feature bits.
opcodes/
* arm-dis.c (arm_opcodes): Add V7 instructions.
(thumb32_opcodes): Ditto. Handle V7M MSR/MRS variants.
(print_arm_address): New function.
(print_insn_arm): Use it. Add 'P' and 'U' cases.
(psr_name): New function.
(print_insn_thumb32): Add 'U', 'C' and 'D' cases.
2006-02-24 16:36:36 +01:00
|
|
|
|
}
|
|
|
|
|
|
else
|
|
|
|
|
|
{
|
2011-06-02 17:32:10 +02:00
|
|
|
|
func (stream, ", %s", NEGATIVE_BIT_SET ? "-" : "");
|
2009-07-07 16:46:14 +02:00
|
|
|
|
arm_decode_shift (given, func, stream, TRUE);
|
2006-02-24 Paul Brook <paul@codesourcery.com>
gas/
* config/arm/tc-arm.c (arm_ext_v6_notm, arm_ext_div, arm_ext_v7,
arm_ext_v7a, arm_ext_v7r, arm_ext_v7m): New variables.
(struct asm_barrier_opt): Define.
(arm_v7m_psr_hsh, arm_barrier_opt_hsh): New variables.
(parse_psr): Accept V7M psr names.
(parse_barrier): New function.
(enum operand_parse_code): Add OP_oBARRIER.
(parse_operands): Implement OP_oBARRIER.
(do_barrier): New function.
(do_dbg, do_pli, do_t_barrier, do_t_dbg, do_t_div): New functions.
(do_t_cpsi): Add V7M restrictions.
(do_t_mrs, do_t_msr): Validate V7M variants.
(md_assemble): Check for NULL variants.
(v7m_psrs, barrier_opt_names): New tables.
(insns): Add V7 instructions. Mark V6 instructions absent from V7M.
(md_begin): Initialize arm_v7m_psr_hsh and arm_barrier_opt_hsh.
(arm_cpu_option_table): Add Cortex-M3, R4 and A8.
(arm_arch_option_table): Add armv7, armv7a, armv7r and armv7m.
(struct cpu_arch_ver_table): Define.
(cpu_arch_ver): New.
(aeabi_set_public_attributes): Use cpu_arch_ver. Set
Tag_CPU_arch_profile.
* doc/c-arm.texi: Document new cpu and arch options.
gas/testsuite/
* gas/arm/thumb32.d: Fix expected msr and mrs output.
* gas/arm/arch7.d: New test.
* gas/arm/arch7.s: New test.
* gas/arm/arch7m-bad.l: New test.
* gas/arm/arch7m-bad.d: New test.
* gas/arm/arch7m-bad.s: New test.
include/opcode/
* arm.h: Add V7 feature bits.
opcodes/
* arm-dis.c (arm_opcodes): Add V7 instructions.
(thumb32_opcodes): Ditto. Handle V7M MSR/MRS variants.
(print_arm_address): New function.
(print_insn_arm): Use it. Add 'P' and 'U' cases.
(psr_name): New function.
(print_insn_thumb32): Add 'U', 'C' and 'D' cases.
2006-02-24 16:36:36 +01:00
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
func (stream, "]%s",
|
2009-11-11 10:44:45 +01:00
|
|
|
|
WRITEBACK_BIT_SET ? "!" : "");
|
2006-02-24 Paul Brook <paul@codesourcery.com>
gas/
* config/arm/tc-arm.c (arm_ext_v6_notm, arm_ext_div, arm_ext_v7,
arm_ext_v7a, arm_ext_v7r, arm_ext_v7m): New variables.
(struct asm_barrier_opt): Define.
(arm_v7m_psr_hsh, arm_barrier_opt_hsh): New variables.
(parse_psr): Accept V7M psr names.
(parse_barrier): New function.
(enum operand_parse_code): Add OP_oBARRIER.
(parse_operands): Implement OP_oBARRIER.
(do_barrier): New function.
(do_dbg, do_pli, do_t_barrier, do_t_dbg, do_t_div): New functions.
(do_t_cpsi): Add V7M restrictions.
(do_t_mrs, do_t_msr): Validate V7M variants.
(md_assemble): Check for NULL variants.
(v7m_psrs, barrier_opt_names): New tables.
(insns): Add V7 instructions. Mark V6 instructions absent from V7M.
(md_begin): Initialize arm_v7m_psr_hsh and arm_barrier_opt_hsh.
(arm_cpu_option_table): Add Cortex-M3, R4 and A8.
(arm_arch_option_table): Add armv7, armv7a, armv7r and armv7m.
(struct cpu_arch_ver_table): Define.
(cpu_arch_ver): New.
(aeabi_set_public_attributes): Use cpu_arch_ver. Set
Tag_CPU_arch_profile.
* doc/c-arm.texi: Document new cpu and arch options.
gas/testsuite/
* gas/arm/thumb32.d: Fix expected msr and mrs output.
* gas/arm/arch7.d: New test.
* gas/arm/arch7.s: New test.
* gas/arm/arch7m-bad.l: New test.
* gas/arm/arch7m-bad.d: New test.
* gas/arm/arch7m-bad.s: New test.
include/opcode/
* arm.h: Add V7 feature bits.
opcodes/
* arm-dis.c (arm_opcodes): Add V7 instructions.
(thumb32_opcodes): Ditto. Handle V7M MSR/MRS variants.
(print_arm_address): New function.
(print_insn_arm): Use it. Add 'P' and 'U' cases.
(psr_name): New function.
(print_insn_thumb32): Add 'U', 'C' and 'D' cases.
2006-02-24 16:36:36 +01:00
|
|
|
|
}
|
|
|
|
|
|
else
|
|
|
|
|
|
{
|
|
|
|
|
|
if ((given & 0x02000000) == 0)
|
|
|
|
|
|
{
|
2011-06-02 17:32:10 +02:00
|
|
|
|
/* Always show offset. */
|
2009-06-29 10:08:15 +02:00
|
|
|
|
offset = given & 0xfff;
|
2011-06-02 17:32:10 +02:00
|
|
|
|
func (stream, "], #%s%d",
|
2012-07-24 14:56:47 +02:00
|
|
|
|
NEGATIVE_BIT_SET ? "-" : "", (int) offset);
|
2006-02-24 Paul Brook <paul@codesourcery.com>
gas/
* config/arm/tc-arm.c (arm_ext_v6_notm, arm_ext_div, arm_ext_v7,
arm_ext_v7a, arm_ext_v7r, arm_ext_v7m): New variables.
(struct asm_barrier_opt): Define.
(arm_v7m_psr_hsh, arm_barrier_opt_hsh): New variables.
(parse_psr): Accept V7M psr names.
(parse_barrier): New function.
(enum operand_parse_code): Add OP_oBARRIER.
(parse_operands): Implement OP_oBARRIER.
(do_barrier): New function.
(do_dbg, do_pli, do_t_barrier, do_t_dbg, do_t_div): New functions.
(do_t_cpsi): Add V7M restrictions.
(do_t_mrs, do_t_msr): Validate V7M variants.
(md_assemble): Check for NULL variants.
(v7m_psrs, barrier_opt_names): New tables.
(insns): Add V7 instructions. Mark V6 instructions absent from V7M.
(md_begin): Initialize arm_v7m_psr_hsh and arm_barrier_opt_hsh.
(arm_cpu_option_table): Add Cortex-M3, R4 and A8.
(arm_arch_option_table): Add armv7, armv7a, armv7r and armv7m.
(struct cpu_arch_ver_table): Define.
(cpu_arch_ver): New.
(aeabi_set_public_attributes): Use cpu_arch_ver. Set
Tag_CPU_arch_profile.
* doc/c-arm.texi: Document new cpu and arch options.
gas/testsuite/
* gas/arm/thumb32.d: Fix expected msr and mrs output.
* gas/arm/arch7.d: New test.
* gas/arm/arch7.s: New test.
* gas/arm/arch7m-bad.l: New test.
* gas/arm/arch7m-bad.d: New test.
* gas/arm/arch7m-bad.s: New test.
include/opcode/
* arm.h: Add V7 feature bits.
opcodes/
* arm-dis.c (arm_opcodes): Add V7 instructions.
(thumb32_opcodes): Ditto. Handle V7M MSR/MRS variants.
(print_arm_address): New function.
(print_insn_arm): Use it. Add 'P' and 'U' cases.
(psr_name): New function.
(print_insn_thumb32): Add 'U', 'C' and 'D' cases.
2006-02-24 16:36:36 +01:00
|
|
|
|
}
|
|
|
|
|
|
else
|
|
|
|
|
|
{
|
|
|
|
|
|
func (stream, "], %s",
|
2009-11-11 10:44:45 +01:00
|
|
|
|
NEGATIVE_BIT_SET ? "-" : "");
|
2009-07-07 16:46:14 +02:00
|
|
|
|
arm_decode_shift (given, func, stream, TRUE);
|
2006-02-24 Paul Brook <paul@codesourcery.com>
gas/
* config/arm/tc-arm.c (arm_ext_v6_notm, arm_ext_div, arm_ext_v7,
arm_ext_v7a, arm_ext_v7r, arm_ext_v7m): New variables.
(struct asm_barrier_opt): Define.
(arm_v7m_psr_hsh, arm_barrier_opt_hsh): New variables.
(parse_psr): Accept V7M psr names.
(parse_barrier): New function.
(enum operand_parse_code): Add OP_oBARRIER.
(parse_operands): Implement OP_oBARRIER.
(do_barrier): New function.
(do_dbg, do_pli, do_t_barrier, do_t_dbg, do_t_div): New functions.
(do_t_cpsi): Add V7M restrictions.
(do_t_mrs, do_t_msr): Validate V7M variants.
(md_assemble): Check for NULL variants.
(v7m_psrs, barrier_opt_names): New tables.
(insns): Add V7 instructions. Mark V6 instructions absent from V7M.
(md_begin): Initialize arm_v7m_psr_hsh and arm_barrier_opt_hsh.
(arm_cpu_option_table): Add Cortex-M3, R4 and A8.
(arm_arch_option_table): Add armv7, armv7a, armv7r and armv7m.
(struct cpu_arch_ver_table): Define.
(cpu_arch_ver): New.
(aeabi_set_public_attributes): Use cpu_arch_ver. Set
Tag_CPU_arch_profile.
* doc/c-arm.texi: Document new cpu and arch options.
gas/testsuite/
* gas/arm/thumb32.d: Fix expected msr and mrs output.
* gas/arm/arch7.d: New test.
* gas/arm/arch7.s: New test.
* gas/arm/arch7m-bad.l: New test.
* gas/arm/arch7m-bad.d: New test.
* gas/arm/arch7m-bad.s: New test.
include/opcode/
* arm.h: Add V7 feature bits.
opcodes/
* arm-dis.c (arm_opcodes): Add V7 instructions.
(thumb32_opcodes): Ditto. Handle V7M MSR/MRS variants.
(print_arm_address): New function.
(print_insn_arm): Use it. Add 'P' and 'U' cases.
(psr_name): New function.
(print_insn_thumb32): Add 'U', 'C' and 'D' cases.
2006-02-24 16:36:36 +01:00
|
|
|
|
}
|
|
|
|
|
|
}
|
2014-08-22 17:42:12 +02:00
|
|
|
|
if (NEGATIVE_BIT_SET)
|
|
|
|
|
|
offset = -offset;
|
2006-02-24 Paul Brook <paul@codesourcery.com>
gas/
* config/arm/tc-arm.c (arm_ext_v6_notm, arm_ext_div, arm_ext_v7,
arm_ext_v7a, arm_ext_v7r, arm_ext_v7m): New variables.
(struct asm_barrier_opt): Define.
(arm_v7m_psr_hsh, arm_barrier_opt_hsh): New variables.
(parse_psr): Accept V7M psr names.
(parse_barrier): New function.
(enum operand_parse_code): Add OP_oBARRIER.
(parse_operands): Implement OP_oBARRIER.
(do_barrier): New function.
(do_dbg, do_pli, do_t_barrier, do_t_dbg, do_t_div): New functions.
(do_t_cpsi): Add V7M restrictions.
(do_t_mrs, do_t_msr): Validate V7M variants.
(md_assemble): Check for NULL variants.
(v7m_psrs, barrier_opt_names): New tables.
(insns): Add V7 instructions. Mark V6 instructions absent from V7M.
(md_begin): Initialize arm_v7m_psr_hsh and arm_barrier_opt_hsh.
(arm_cpu_option_table): Add Cortex-M3, R4 and A8.
(arm_arch_option_table): Add armv7, armv7a, armv7r and armv7m.
(struct cpu_arch_ver_table): Define.
(cpu_arch_ver): New.
(aeabi_set_public_attributes): Use cpu_arch_ver. Set
Tag_CPU_arch_profile.
* doc/c-arm.texi: Document new cpu and arch options.
gas/testsuite/
* gas/arm/thumb32.d: Fix expected msr and mrs output.
* gas/arm/arch7.d: New test.
* gas/arm/arch7.s: New test.
* gas/arm/arch7m-bad.l: New test.
* gas/arm/arch7m-bad.d: New test.
* gas/arm/arch7m-bad.s: New test.
include/opcode/
* arm.h: Add V7 feature bits.
opcodes/
* arm-dis.c (arm_opcodes): Add V7 instructions.
(thumb32_opcodes): Ditto. Handle V7M MSR/MRS variants.
(print_arm_address): New function.
(print_insn_arm): Use it. Add 'P' and 'U' cases.
(psr_name): New function.
(print_insn_thumb32): Add 'U', 'C' and 'D' cases.
2006-02-24 16:36:36 +01:00
|
|
|
|
}
|
2009-06-29 10:08:15 +02:00
|
|
|
|
|
|
|
|
|
|
return (signed long) offset;
|
2006-02-24 Paul Brook <paul@codesourcery.com>
gas/
* config/arm/tc-arm.c (arm_ext_v6_notm, arm_ext_div, arm_ext_v7,
arm_ext_v7a, arm_ext_v7r, arm_ext_v7m): New variables.
(struct asm_barrier_opt): Define.
(arm_v7m_psr_hsh, arm_barrier_opt_hsh): New variables.
(parse_psr): Accept V7M psr names.
(parse_barrier): New function.
(enum operand_parse_code): Add OP_oBARRIER.
(parse_operands): Implement OP_oBARRIER.
(do_barrier): New function.
(do_dbg, do_pli, do_t_barrier, do_t_dbg, do_t_div): New functions.
(do_t_cpsi): Add V7M restrictions.
(do_t_mrs, do_t_msr): Validate V7M variants.
(md_assemble): Check for NULL variants.
(v7m_psrs, barrier_opt_names): New tables.
(insns): Add V7 instructions. Mark V6 instructions absent from V7M.
(md_begin): Initialize arm_v7m_psr_hsh and arm_barrier_opt_hsh.
(arm_cpu_option_table): Add Cortex-M3, R4 and A8.
(arm_arch_option_table): Add armv7, armv7a, armv7r and armv7m.
(struct cpu_arch_ver_table): Define.
(cpu_arch_ver): New.
(aeabi_set_public_attributes): Use cpu_arch_ver. Set
Tag_CPU_arch_profile.
* doc/c-arm.texi: Document new cpu and arch options.
gas/testsuite/
* gas/arm/thumb32.d: Fix expected msr and mrs output.
* gas/arm/arch7.d: New test.
* gas/arm/arch7.s: New test.
* gas/arm/arch7m-bad.l: New test.
* gas/arm/arch7m-bad.d: New test.
* gas/arm/arch7m-bad.s: New test.
include/opcode/
* arm.h: Add V7 feature bits.
opcodes/
* arm-dis.c (arm_opcodes): Add V7 instructions.
(thumb32_opcodes): Ditto. Handle V7M MSR/MRS variants.
(print_arm_address): New function.
(print_insn_arm): Use it. Add 'P' and 'U' cases.
(psr_name): New function.
(print_insn_thumb32): Add 'U', 'C' and 'D' cases.
2006-02-24 16:36:36 +01:00
|
|
|
|
}
|
|
|
|
|
|
|
2006-04-26 17:40:55 +02:00
|
|
|
|
/* Print one neon instruction on INFO->STREAM.
|
|
|
|
|
|
Return TRUE if the instuction matched, FALSE if this is not a
|
|
|
|
|
|
recognised neon instruction. */
|
|
|
|
|
|
|
|
|
|
|
|
static bfd_boolean
|
|
|
|
|
|
print_insn_neon (struct disassemble_info *info, long given, bfd_boolean thumb)
|
|
|
|
|
|
{
|
|
|
|
|
|
const struct opcode32 *insn;
|
|
|
|
|
|
void *stream = info->stream;
|
|
|
|
|
|
fprintf_ftype func = info->fprintf_func;
|
|
|
|
|
|
|
|
|
|
|
|
if (thumb)
|
|
|
|
|
|
{
|
|
|
|
|
|
if ((given & 0xef000000) == 0xef000000)
|
|
|
|
|
|
{
|
2009-06-18 12:31:21 +02:00
|
|
|
|
/* Move bit 28 to bit 24 to translate Thumb2 to ARM encoding. */
|
2006-04-26 17:40:55 +02:00
|
|
|
|
unsigned long bit28 = given & (1 << 28);
|
|
|
|
|
|
|
|
|
|
|
|
given &= 0x00ffffff;
|
|
|
|
|
|
if (bit28)
|
|
|
|
|
|
given |= 0xf3000000;
|
|
|
|
|
|
else
|
|
|
|
|
|
given |= 0xf2000000;
|
|
|
|
|
|
}
|
|
|
|
|
|
else if ((given & 0xff000000) == 0xf9000000)
|
|
|
|
|
|
given ^= 0xf9000000 ^ 0xf4000000;
|
|
|
|
|
|
else
|
|
|
|
|
|
return FALSE;
|
|
|
|
|
|
}
|
2015-08-12 13:45:07 +02:00
|
|
|
|
|
2006-04-26 17:40:55 +02:00
|
|
|
|
for (insn = neon_opcodes; insn->assembler; insn++)
|
|
|
|
|
|
{
|
|
|
|
|
|
if ((given & insn->mask) == insn->value)
|
|
|
|
|
|
{
|
2009-06-29 10:08:15 +02:00
|
|
|
|
signed long value_in_comment = 0;
|
2012-08-24 09:59:05 +02:00
|
|
|
|
bfd_boolean is_unpredictable = FALSE;
|
2006-04-26 17:40:55 +02:00
|
|
|
|
const char *c;
|
|
|
|
|
|
|
|
|
|
|
|
for (c = insn->assembler; *c; c++)
|
|
|
|
|
|
{
|
|
|
|
|
|
if (*c == '%')
|
|
|
|
|
|
{
|
|
|
|
|
|
switch (*++c)
|
|
|
|
|
|
{
|
|
|
|
|
|
case '%':
|
|
|
|
|
|
func (stream, "%%");
|
|
|
|
|
|
break;
|
|
|
|
|
|
|
2012-08-24 09:59:05 +02:00
|
|
|
|
case 'u':
|
|
|
|
|
|
if (thumb && ifthen_state)
|
|
|
|
|
|
is_unpredictable = TRUE;
|
|
|
|
|
|
|
|
|
|
|
|
/* Fall through. */
|
2006-06-07 16:08:19 +02:00
|
|
|
|
case 'c':
|
|
|
|
|
|
if (thumb && ifthen_state)
|
|
|
|
|
|
func (stream, "%s", arm_conditional[IFTHEN_COND]);
|
|
|
|
|
|
break;
|
|
|
|
|
|
|
2006-04-26 17:40:55 +02:00
|
|
|
|
case 'A':
|
|
|
|
|
|
{
|
2015-08-12 13:45:07 +02:00
|
|
|
|
static const unsigned char enc[16] =
|
2006-04-26 17:40:55 +02:00
|
|
|
|
{
|
|
|
|
|
|
0x4, 0x14, /* st4 0,1 */
|
|
|
|
|
|
0x4, /* st1 2 */
|
|
|
|
|
|
0x4, /* st2 3 */
|
|
|
|
|
|
0x3, /* st3 4 */
|
|
|
|
|
|
0x13, /* st3 5 */
|
|
|
|
|
|
0x3, /* st1 6 */
|
|
|
|
|
|
0x1, /* st1 7 */
|
|
|
|
|
|
0x2, /* st2 8 */
|
|
|
|
|
|
0x12, /* st2 9 */
|
|
|
|
|
|
0x2, /* st1 10 */
|
|
|
|
|
|
0, 0, 0, 0, 0
|
|
|
|
|
|
};
|
|
|
|
|
|
int rd = ((given >> 12) & 0xf) | (((given >> 22) & 1) << 4);
|
|
|
|
|
|
int rn = ((given >> 16) & 0xf);
|
|
|
|
|
|
int rm = ((given >> 0) & 0xf);
|
|
|
|
|
|
int align = ((given >> 4) & 0x3);
|
|
|
|
|
|
int type = ((given >> 8) & 0xf);
|
|
|
|
|
|
int n = enc[type] & 0xf;
|
|
|
|
|
|
int stride = (enc[type] >> 4) + 1;
|
|
|
|
|
|
int ix;
|
2015-08-12 13:45:07 +02:00
|
|
|
|
|
2006-04-26 17:40:55 +02:00
|
|
|
|
func (stream, "{");
|
|
|
|
|
|
if (stride > 1)
|
|
|
|
|
|
for (ix = 0; ix != n; ix++)
|
|
|
|
|
|
func (stream, "%sd%d", ix ? "," : "", rd + ix * stride);
|
|
|
|
|
|
else if (n == 1)
|
|
|
|
|
|
func (stream, "d%d", rd);
|
|
|
|
|
|
else
|
|
|
|
|
|
func (stream, "d%d-d%d", rd, rd + n - 1);
|
|
|
|
|
|
func (stream, "}, [%s", arm_regnames[rn]);
|
|
|
|
|
|
if (align)
|
2010-06-28 11:10:25 +02:00
|
|
|
|
func (stream, " :%d", 32 << align);
|
2006-04-26 17:40:55 +02:00
|
|
|
|
func (stream, "]");
|
|
|
|
|
|
if (rm == 0xd)
|
|
|
|
|
|
func (stream, "!");
|
|
|
|
|
|
else if (rm != 0xf)
|
|
|
|
|
|
func (stream, ", %s", arm_regnames[rm]);
|
|
|
|
|
|
}
|
|
|
|
|
|
break;
|
2015-08-12 13:45:07 +02:00
|
|
|
|
|
2006-04-26 17:40:55 +02:00
|
|
|
|
case 'B':
|
|
|
|
|
|
{
|
|
|
|
|
|
int rd = ((given >> 12) & 0xf) | (((given >> 22) & 1) << 4);
|
|
|
|
|
|
int rn = ((given >> 16) & 0xf);
|
|
|
|
|
|
int rm = ((given >> 0) & 0xf);
|
|
|
|
|
|
int idx_align = ((given >> 4) & 0xf);
|
|
|
|
|
|
int align = 0;
|
|
|
|
|
|
int size = ((given >> 10) & 0x3);
|
|
|
|
|
|
int idx = idx_align >> (size + 1);
|
|
|
|
|
|
int length = ((given >> 8) & 3) + 1;
|
|
|
|
|
|
int stride = 1;
|
|
|
|
|
|
int i;
|
|
|
|
|
|
|
|
|
|
|
|
if (length > 1 && size > 0)
|
|
|
|
|
|
stride = (idx_align & (1 << size)) ? 2 : 1;
|
2015-08-12 13:45:07 +02:00
|
|
|
|
|
2006-04-26 17:40:55 +02:00
|
|
|
|
switch (length)
|
|
|
|
|
|
{
|
|
|
|
|
|
case 1:
|
|
|
|
|
|
{
|
|
|
|
|
|
int amask = (1 << size) - 1;
|
|
|
|
|
|
if ((idx_align & (1 << size)) != 0)
|
|
|
|
|
|
return FALSE;
|
|
|
|
|
|
if (size > 0)
|
|
|
|
|
|
{
|
|
|
|
|
|
if ((idx_align & amask) == amask)
|
|
|
|
|
|
align = 8 << size;
|
|
|
|
|
|
else if ((idx_align & amask) != 0)
|
|
|
|
|
|
return FALSE;
|
|
|
|
|
|
}
|
|
|
|
|
|
}
|
|
|
|
|
|
break;
|
2015-08-12 13:45:07 +02:00
|
|
|
|
|
2006-04-26 17:40:55 +02:00
|
|
|
|
case 2:
|
|
|
|
|
|
if (size == 2 && (idx_align & 2) != 0)
|
|
|
|
|
|
return FALSE;
|
|
|
|
|
|
align = (idx_align & 1) ? 16 << size : 0;
|
|
|
|
|
|
break;
|
2015-08-12 13:45:07 +02:00
|
|
|
|
|
2006-04-26 17:40:55 +02:00
|
|
|
|
case 3:
|
|
|
|
|
|
if ((size == 2 && (idx_align & 3) != 0)
|
|
|
|
|
|
|| (idx_align & 1) != 0)
|
|
|
|
|
|
return FALSE;
|
|
|
|
|
|
break;
|
2015-08-12 13:45:07 +02:00
|
|
|
|
|
2006-04-26 17:40:55 +02:00
|
|
|
|
case 4:
|
|
|
|
|
|
if (size == 2)
|
|
|
|
|
|
{
|
|
|
|
|
|
if ((idx_align & 3) == 3)
|
|
|
|
|
|
return FALSE;
|
|
|
|
|
|
align = (idx_align & 3) * 64;
|
|
|
|
|
|
}
|
|
|
|
|
|
else
|
|
|
|
|
|
align = (idx_align & 1) ? 32 << size : 0;
|
|
|
|
|
|
break;
|
2015-08-12 13:45:07 +02:00
|
|
|
|
|
2006-04-26 17:40:55 +02:00
|
|
|
|
default:
|
|
|
|
|
|
abort ();
|
|
|
|
|
|
}
|
2015-08-12 13:45:07 +02:00
|
|
|
|
|
2006-04-26 17:40:55 +02:00
|
|
|
|
func (stream, "{");
|
|
|
|
|
|
for (i = 0; i < length; i++)
|
|
|
|
|
|
func (stream, "%sd%d[%d]", (i == 0) ? "" : ",",
|
|
|
|
|
|
rd + i * stride, idx);
|
|
|
|
|
|
func (stream, "}, [%s", arm_regnames[rn]);
|
|
|
|
|
|
if (align)
|
2010-06-28 11:10:25 +02:00
|
|
|
|
func (stream, " :%d", align);
|
2006-04-26 17:40:55 +02:00
|
|
|
|
func (stream, "]");
|
|
|
|
|
|
if (rm == 0xd)
|
|
|
|
|
|
func (stream, "!");
|
|
|
|
|
|
else if (rm != 0xf)
|
|
|
|
|
|
func (stream, ", %s", arm_regnames[rm]);
|
|
|
|
|
|
}
|
|
|
|
|
|
break;
|
2015-08-12 13:45:07 +02:00
|
|
|
|
|
2006-04-26 17:40:55 +02:00
|
|
|
|
case 'C':
|
|
|
|
|
|
{
|
|
|
|
|
|
int rd = ((given >> 12) & 0xf) | (((given >> 22) & 1) << 4);
|
|
|
|
|
|
int rn = ((given >> 16) & 0xf);
|
|
|
|
|
|
int rm = ((given >> 0) & 0xf);
|
|
|
|
|
|
int align = ((given >> 4) & 0x1);
|
|
|
|
|
|
int size = ((given >> 6) & 0x3);
|
|
|
|
|
|
int type = ((given >> 8) & 0x3);
|
|
|
|
|
|
int n = type + 1;
|
|
|
|
|
|
int stride = ((given >> 5) & 0x1);
|
|
|
|
|
|
int ix;
|
2015-08-12 13:45:07 +02:00
|
|
|
|
|
2006-04-26 17:40:55 +02:00
|
|
|
|
if (stride && (n == 1))
|
|
|
|
|
|
n++;
|
|
|
|
|
|
else
|
|
|
|
|
|
stride++;
|
2015-08-12 13:45:07 +02:00
|
|
|
|
|
2006-04-26 17:40:55 +02:00
|
|
|
|
func (stream, "{");
|
|
|
|
|
|
if (stride > 1)
|
|
|
|
|
|
for (ix = 0; ix != n; ix++)
|
|
|
|
|
|
func (stream, "%sd%d[]", ix ? "," : "", rd + ix * stride);
|
|
|
|
|
|
else if (n == 1)
|
|
|
|
|
|
func (stream, "d%d[]", rd);
|
|
|
|
|
|
else
|
|
|
|
|
|
func (stream, "d%d[]-d%d[]", rd, rd + n - 1);
|
|
|
|
|
|
func (stream, "}, [%s", arm_regnames[rn]);
|
|
|
|
|
|
if (align)
|
|
|
|
|
|
{
|
2009-12-11 14:42:17 +01:00
|
|
|
|
align = (8 * (type + 1)) << size;
|
2006-04-26 17:40:55 +02:00
|
|
|
|
if (type == 3)
|
|
|
|
|
|
align = (size > 1) ? align >> 1 : align;
|
|
|
|
|
|
if (type == 2 || (type == 0 && !size))
|
2010-06-28 11:10:25 +02:00
|
|
|
|
func (stream, " :<bad align %d>", align);
|
2006-04-26 17:40:55 +02:00
|
|
|
|
else
|
2010-06-28 11:10:25 +02:00
|
|
|
|
func (stream, " :%d", align);
|
2006-04-26 17:40:55 +02:00
|
|
|
|
}
|
|
|
|
|
|
func (stream, "]");
|
|
|
|
|
|
if (rm == 0xd)
|
|
|
|
|
|
func (stream, "!");
|
|
|
|
|
|
else if (rm != 0xf)
|
|
|
|
|
|
func (stream, ", %s", arm_regnames[rm]);
|
|
|
|
|
|
}
|
|
|
|
|
|
break;
|
2015-08-12 13:45:07 +02:00
|
|
|
|
|
2006-04-26 17:40:55 +02:00
|
|
|
|
case 'D':
|
|
|
|
|
|
{
|
|
|
|
|
|
int raw_reg = (given & 0xf) | ((given >> 1) & 0x10);
|
|
|
|
|
|
int size = (given >> 20) & 3;
|
|
|
|
|
|
int reg = raw_reg & ((4 << size) - 1);
|
|
|
|
|
|
int ix = raw_reg >> size >> 2;
|
2015-08-12 13:45:07 +02:00
|
|
|
|
|
2006-04-26 17:40:55 +02:00
|
|
|
|
func (stream, "d%d[%d]", reg, ix);
|
|
|
|
|
|
}
|
|
|
|
|
|
break;
|
2015-08-12 13:45:07 +02:00
|
|
|
|
|
2006-04-26 17:40:55 +02:00
|
|
|
|
case 'E':
|
2009-06-30 13:57:05 +02:00
|
|
|
|
/* Neon encoded constant for mov, mvn, vorr, vbic. */
|
2006-04-26 17:40:55 +02:00
|
|
|
|
{
|
|
|
|
|
|
int bits = 0;
|
|
|
|
|
|
int cmode = (given >> 8) & 0xf;
|
|
|
|
|
|
int op = (given >> 5) & 0x1;
|
|
|
|
|
|
unsigned long value = 0, hival = 0;
|
|
|
|
|
|
unsigned shift;
|
|
|
|
|
|
int size = 0;
|
2006-04-26 18:02:07 +02:00
|
|
|
|
int isfloat = 0;
|
2015-08-12 13:45:07 +02:00
|
|
|
|
|
2006-04-26 17:40:55 +02:00
|
|
|
|
bits |= ((given >> 24) & 1) << 7;
|
|
|
|
|
|
bits |= ((given >> 16) & 7) << 4;
|
|
|
|
|
|
bits |= ((given >> 0) & 15) << 0;
|
2015-08-12 13:45:07 +02:00
|
|
|
|
|
2006-04-26 17:40:55 +02:00
|
|
|
|
if (cmode < 8)
|
|
|
|
|
|
{
|
|
|
|
|
|
shift = (cmode >> 1) & 3;
|
2009-06-30 13:57:05 +02:00
|
|
|
|
value = (unsigned long) bits << (8 * shift);
|
2006-04-26 17:40:55 +02:00
|
|
|
|
size = 32;
|
|
|
|
|
|
}
|
|
|
|
|
|
else if (cmode < 12)
|
|
|
|
|
|
{
|
|
|
|
|
|
shift = (cmode >> 1) & 1;
|
2009-06-30 13:57:05 +02:00
|
|
|
|
value = (unsigned long) bits << (8 * shift);
|
2006-04-26 17:40:55 +02:00
|
|
|
|
size = 16;
|
|
|
|
|
|
}
|
|
|
|
|
|
else if (cmode < 14)
|
|
|
|
|
|
{
|
|
|
|
|
|
shift = (cmode & 1) + 1;
|
2009-06-30 13:57:05 +02:00
|
|
|
|
value = (unsigned long) bits << (8 * shift);
|
2006-04-26 17:40:55 +02:00
|
|
|
|
value |= (1ul << (8 * shift)) - 1;
|
|
|
|
|
|
size = 32;
|
|
|
|
|
|
}
|
|
|
|
|
|
else if (cmode == 14)
|
|
|
|
|
|
{
|
|
|
|
|
|
if (op)
|
|
|
|
|
|
{
|
2009-06-30 13:57:05 +02:00
|
|
|
|
/* Bit replication into bytes. */
|
2006-04-26 17:40:55 +02:00
|
|
|
|
int ix;
|
|
|
|
|
|
unsigned long mask;
|
2015-08-12 13:45:07 +02:00
|
|
|
|
|
2006-04-26 17:40:55 +02:00
|
|
|
|
value = 0;
|
|
|
|
|
|
hival = 0;
|
|
|
|
|
|
for (ix = 7; ix >= 0; ix--)
|
|
|
|
|
|
{
|
|
|
|
|
|
mask = ((bits >> ix) & 1) ? 0xff : 0;
|
|
|
|
|
|
if (ix <= 3)
|
|
|
|
|
|
value = (value << 8) | mask;
|
|
|
|
|
|
else
|
|
|
|
|
|
hival = (hival << 8) | mask;
|
|
|
|
|
|
}
|
|
|
|
|
|
size = 64;
|
|
|
|
|
|
}
|
|
|
|
|
|
else
|
|
|
|
|
|
{
|
2009-06-30 13:57:05 +02:00
|
|
|
|
/* Byte replication. */
|
|
|
|
|
|
value = (unsigned long) bits;
|
2006-04-26 17:40:55 +02:00
|
|
|
|
size = 8;
|
|
|
|
|
|
}
|
|
|
|
|
|
}
|
|
|
|
|
|
else if (!op)
|
|
|
|
|
|
{
|
2009-06-30 13:57:05 +02:00
|
|
|
|
/* Floating point encoding. */
|
2006-04-26 17:40:55 +02:00
|
|
|
|
int tmp;
|
2015-08-12 13:45:07 +02:00
|
|
|
|
|
2009-06-30 13:57:05 +02:00
|
|
|
|
value = (unsigned long) (bits & 0x7f) << 19;
|
|
|
|
|
|
value |= (unsigned long) (bits & 0x80) << 24;
|
2006-04-26 17:40:55 +02:00
|
|
|
|
tmp = bits & 0x40 ? 0x3c : 0x40;
|
2009-06-30 13:57:05 +02:00
|
|
|
|
value |= (unsigned long) tmp << 24;
|
2006-04-26 17:40:55 +02:00
|
|
|
|
size = 32;
|
2006-04-26 18:02:07 +02:00
|
|
|
|
isfloat = 1;
|
2006-04-26 17:40:55 +02:00
|
|
|
|
}
|
|
|
|
|
|
else
|
|
|
|
|
|
{
|
|
|
|
|
|
func (stream, "<illegal constant %.8x:%x:%x>",
|
|
|
|
|
|
bits, cmode, op);
|
|
|
|
|
|
size = 32;
|
|
|
|
|
|
break;
|
|
|
|
|
|
}
|
|
|
|
|
|
switch (size)
|
|
|
|
|
|
{
|
|
|
|
|
|
case 8:
|
|
|
|
|
|
func (stream, "#%ld\t; 0x%.2lx", value, value);
|
|
|
|
|
|
break;
|
2015-08-12 13:45:07 +02:00
|
|
|
|
|
2006-04-26 17:40:55 +02:00
|
|
|
|
case 16:
|
|
|
|
|
|
func (stream, "#%ld\t; 0x%.4lx", value, value);
|
|
|
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
|
|
case 32:
|
2006-04-26 18:02:07 +02:00
|
|
|
|
if (isfloat)
|
|
|
|
|
|
{
|
|
|
|
|
|
unsigned char valbytes[4];
|
|
|
|
|
|
double fvalue;
|
2015-08-12 13:45:07 +02:00
|
|
|
|
|
2006-04-26 18:02:07 +02:00
|
|
|
|
/* Do this a byte at a time so we don't have to
|
|
|
|
|
|
worry about the host's endianness. */
|
|
|
|
|
|
valbytes[0] = value & 0xff;
|
|
|
|
|
|
valbytes[1] = (value >> 8) & 0xff;
|
|
|
|
|
|
valbytes[2] = (value >> 16) & 0xff;
|
|
|
|
|
|
valbytes[3] = (value >> 24) & 0xff;
|
2015-08-12 13:45:07 +02:00
|
|
|
|
|
|
|
|
|
|
floatformat_to_double
|
2009-11-11 10:44:45 +01:00
|
|
|
|
(& floatformat_ieee_single_little, valbytes,
|
|
|
|
|
|
& fvalue);
|
2015-08-12 13:45:07 +02:00
|
|
|
|
|
2006-04-26 18:02:07 +02:00
|
|
|
|
func (stream, "#%.7g\t; 0x%.8lx", fvalue,
|
|
|
|
|
|
value);
|
|
|
|
|
|
}
|
|
|
|
|
|
else
|
2006-06-12 17:31:28 +02:00
|
|
|
|
func (stream, "#%ld\t; 0x%.8lx",
|
2015-08-12 13:45:07 +02:00
|
|
|
|
(long) (((value & 0x80000000L) != 0)
|
2010-05-28 18:04:21 +02:00
|
|
|
|
? value | ~0xffffffffL : value),
|
2009-11-11 10:44:45 +01:00
|
|
|
|
value);
|
2006-04-26 17:40:55 +02:00
|
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
|
|
case 64:
|
|
|
|
|
|
func (stream, "#0x%.8lx%.8lx", hival, value);
|
|
|
|
|
|
break;
|
2015-08-12 13:45:07 +02:00
|
|
|
|
|
2006-04-26 17:40:55 +02:00
|
|
|
|
default:
|
|
|
|
|
|
abort ();
|
|
|
|
|
|
}
|
|
|
|
|
|
}
|
|
|
|
|
|
break;
|
2015-08-12 13:45:07 +02:00
|
|
|
|
|
2006-04-26 17:40:55 +02:00
|
|
|
|
case 'F':
|
|
|
|
|
|
{
|
|
|
|
|
|
int regno = ((given >> 16) & 0xf) | ((given >> (7 - 4)) & 0x10);
|
|
|
|
|
|
int num = (given >> 8) & 0x3;
|
2015-08-12 13:45:07 +02:00
|
|
|
|
|
2006-04-26 17:40:55 +02:00
|
|
|
|
if (!num)
|
|
|
|
|
|
func (stream, "{d%d}", regno);
|
|
|
|
|
|
else if (num + regno >= 32)
|
|
|
|
|
|
func (stream, "{d%d-<overflow reg d%d}", regno, regno + num);
|
|
|
|
|
|
else
|
|
|
|
|
|
func (stream, "{d%d-d%d}", regno, regno + num);
|
|
|
|
|
|
}
|
|
|
|
|
|
break;
|
2012-08-24 10:09:50 +02:00
|
|
|
|
|
2006-04-26 17:40:55 +02:00
|
|
|
|
|
|
|
|
|
|
case '0': case '1': case '2': case '3': case '4':
|
|
|
|
|
|
case '5': case '6': case '7': case '8': case '9':
|
|
|
|
|
|
{
|
|
|
|
|
|
int width;
|
|
|
|
|
|
unsigned long value;
|
|
|
|
|
|
|
|
|
|
|
|
c = arm_decode_bitfield (c, given, &value, &width);
|
2015-08-12 13:45:07 +02:00
|
|
|
|
|
2006-04-26 17:40:55 +02:00
|
|
|
|
switch (*c)
|
|
|
|
|
|
{
|
|
|
|
|
|
case 'r':
|
|
|
|
|
|
func (stream, "%s", arm_regnames[value]);
|
|
|
|
|
|
break;
|
|
|
|
|
|
case 'd':
|
|
|
|
|
|
func (stream, "%ld", value);
|
2009-06-29 10:08:15 +02:00
|
|
|
|
value_in_comment = value;
|
2006-04-26 17:40:55 +02:00
|
|
|
|
break;
|
|
|
|
|
|
case 'e':
|
|
|
|
|
|
func (stream, "%ld", (1ul << width) - value);
|
|
|
|
|
|
break;
|
2015-08-12 13:45:07 +02:00
|
|
|
|
|
2006-04-26 17:40:55 +02:00
|
|
|
|
case 'S':
|
|
|
|
|
|
case 'T':
|
|
|
|
|
|
case 'U':
|
2009-06-29 10:08:15 +02:00
|
|
|
|
/* Various width encodings. */
|
2006-04-26 17:40:55 +02:00
|
|
|
|
{
|
|
|
|
|
|
int base = 8 << (*c - 'S'); /* 8,16 or 32 */
|
|
|
|
|
|
int limit;
|
|
|
|
|
|
unsigned low, high;
|
|
|
|
|
|
|
|
|
|
|
|
c++;
|
|
|
|
|
|
if (*c >= '0' && *c <= '9')
|
|
|
|
|
|
limit = *c - '0';
|
|
|
|
|
|
else if (*c >= 'a' && *c <= 'f')
|
|
|
|
|
|
limit = *c - 'a' + 10;
|
|
|
|
|
|
else
|
|
|
|
|
|
abort ();
|
|
|
|
|
|
low = limit >> 2;
|
|
|
|
|
|
high = limit & 3;
|
|
|
|
|
|
|
|
|
|
|
|
if (value < low || value > high)
|
|
|
|
|
|
func (stream, "<illegal width %d>", base << value);
|
|
|
|
|
|
else
|
|
|
|
|
|
func (stream, "%d", base << value);
|
|
|
|
|
|
}
|
|
|
|
|
|
break;
|
|
|
|
|
|
case 'R':
|
|
|
|
|
|
if (given & (1 << 6))
|
|
|
|
|
|
goto Q;
|
|
|
|
|
|
/* FALLTHROUGH */
|
|
|
|
|
|
case 'D':
|
|
|
|
|
|
func (stream, "d%ld", value);
|
|
|
|
|
|
break;
|
|
|
|
|
|
case 'Q':
|
|
|
|
|
|
Q:
|
|
|
|
|
|
if (value & 1)
|
|
|
|
|
|
func (stream, "<illegal reg q%ld.5>", value >> 1);
|
|
|
|
|
|
else
|
|
|
|
|
|
func (stream, "q%ld", value >> 1);
|
|
|
|
|
|
break;
|
2015-08-12 13:45:07 +02:00
|
|
|
|
|
2006-04-26 17:40:55 +02:00
|
|
|
|
case '`':
|
|
|
|
|
|
c++;
|
|
|
|
|
|
if (value == 0)
|
|
|
|
|
|
func (stream, "%c", *c);
|
|
|
|
|
|
break;
|
|
|
|
|
|
case '\'':
|
|
|
|
|
|
c++;
|
|
|
|
|
|
if (value == ((1ul << width) - 1))
|
|
|
|
|
|
func (stream, "%c", *c);
|
|
|
|
|
|
break;
|
|
|
|
|
|
case '?':
|
2009-06-30 13:57:05 +02:00
|
|
|
|
func (stream, "%c", c[(1 << width) - (int) value]);
|
2006-04-26 17:40:55 +02:00
|
|
|
|
c += 1 << width;
|
|
|
|
|
|
break;
|
|
|
|
|
|
default:
|
|
|
|
|
|
abort ();
|
|
|
|
|
|
}
|
|
|
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
|
|
default:
|
|
|
|
|
|
abort ();
|
|
|
|
|
|
}
|
|
|
|
|
|
}
|
|
|
|
|
|
}
|
|
|
|
|
|
else
|
|
|
|
|
|
func (stream, "%c", *c);
|
|
|
|
|
|
}
|
2009-06-29 10:08:15 +02:00
|
|
|
|
|
|
|
|
|
|
if (value_in_comment > 32 || value_in_comment < -16)
|
|
|
|
|
|
func (stream, "\t; 0x%lx", value_in_comment);
|
|
|
|
|
|
|
2012-08-24 09:59:05 +02:00
|
|
|
|
if (is_unpredictable)
|
|
|
|
|
|
func (stream, UNPREDICTABLE_INSTRUCTION);
|
|
|
|
|
|
|
2006-04-26 17:40:55 +02:00
|
|
|
|
return TRUE;
|
|
|
|
|
|
}
|
|
|
|
|
|
}
|
|
|
|
|
|
return FALSE;
|
|
|
|
|
|
}
|
|
|
|
|
|
|
2010-09-23 17:52:19 +02:00
|
|
|
|
/* Return the name of a v7A special register. */
|
|
|
|
|
|
|
2015-08-12 13:45:07 +02:00
|
|
|
|
static const char *
|
2010-09-23 17:52:19 +02:00
|
|
|
|
banked_regname (unsigned reg)
|
|
|
|
|
|
{
|
|
|
|
|
|
switch (reg)
|
|
|
|
|
|
{
|
|
|
|
|
|
case 15: return "CPSR";
|
2015-08-12 13:45:07 +02:00
|
|
|
|
case 32: return "R8_usr";
|
2010-09-23 17:52:19 +02:00
|
|
|
|
case 33: return "R9_usr";
|
|
|
|
|
|
case 34: return "R10_usr";
|
|
|
|
|
|
case 35: return "R11_usr";
|
|
|
|
|
|
case 36: return "R12_usr";
|
|
|
|
|
|
case 37: return "SP_usr";
|
|
|
|
|
|
case 38: return "LR_usr";
|
2015-08-12 13:45:07 +02:00
|
|
|
|
case 40: return "R8_fiq";
|
2010-09-23 17:52:19 +02:00
|
|
|
|
case 41: return "R9_fiq";
|
|
|
|
|
|
case 42: return "R10_fiq";
|
|
|
|
|
|
case 43: return "R11_fiq";
|
|
|
|
|
|
case 44: return "R12_fiq";
|
|
|
|
|
|
case 45: return "SP_fiq";
|
|
|
|
|
|
case 46: return "LR_fiq";
|
|
|
|
|
|
case 48: return "LR_irq";
|
|
|
|
|
|
case 49: return "SP_irq";
|
|
|
|
|
|
case 50: return "LR_svc";
|
|
|
|
|
|
case 51: return "SP_svc";
|
|
|
|
|
|
case 52: return "LR_abt";
|
|
|
|
|
|
case 53: return "SP_abt";
|
|
|
|
|
|
case 54: return "LR_und";
|
|
|
|
|
|
case 55: return "SP_und";
|
|
|
|
|
|
case 60: return "LR_mon";
|
|
|
|
|
|
case 61: return "SP_mon";
|
|
|
|
|
|
case 62: return "ELR_hyp";
|
|
|
|
|
|
case 63: return "SP_hyp";
|
|
|
|
|
|
case 79: return "SPSR";
|
|
|
|
|
|
case 110: return "SPSR_fiq";
|
|
|
|
|
|
case 112: return "SPSR_irq";
|
|
|
|
|
|
case 114: return "SPSR_svc";
|
|
|
|
|
|
case 116: return "SPSR_abt";
|
|
|
|
|
|
case 118: return "SPSR_und";
|
|
|
|
|
|
case 124: return "SPSR_mon";
|
|
|
|
|
|
case 126: return "SPSR_hyp";
|
|
|
|
|
|
default: return NULL;
|
|
|
|
|
|
}
|
|
|
|
|
|
}
|
|
|
|
|
|
|
2012-08-24 10:00:20 +02:00
|
|
|
|
/* Return the name of the DMB/DSB option. */
|
|
|
|
|
|
static const char *
|
|
|
|
|
|
data_barrier_option (unsigned option)
|
|
|
|
|
|
{
|
|
|
|
|
|
switch (option & 0xf)
|
|
|
|
|
|
{
|
|
|
|
|
|
case 0xf: return "sy";
|
|
|
|
|
|
case 0xe: return "st";
|
|
|
|
|
|
case 0xd: return "ld";
|
|
|
|
|
|
case 0xb: return "ish";
|
|
|
|
|
|
case 0xa: return "ishst";
|
|
|
|
|
|
case 0x9: return "ishld";
|
|
|
|
|
|
case 0x7: return "un";
|
|
|
|
|
|
case 0x6: return "unst";
|
|
|
|
|
|
case 0x5: return "nshld";
|
|
|
|
|
|
case 0x3: return "osh";
|
|
|
|
|
|
case 0x2: return "oshst";
|
|
|
|
|
|
case 0x1: return "oshld";
|
|
|
|
|
|
default: return NULL;
|
|
|
|
|
|
}
|
|
|
|
|
|
}
|
|
|
|
|
|
|
2005-06-08 00:16:52 +02:00
|
|
|
|
/* Print one ARM instruction from PC on INFO->STREAM. */
|
|
|
|
|
|
|
|
|
|
|
|
static void
|
|
|
|
|
|
print_insn_arm (bfd_vma pc, struct disassemble_info *info, long given)
|
1999-05-03 09:29:11 +02:00
|
|
|
|
{
|
opcodes:
* arm-opc.h: Delete; fold contents into ...
* arm-dis.c: ... here. Move includes of internal COFF headers
next to includes of internal ELF headers.
(streq, WORD_ADDRESS, BDISP, BDISP23): Delete, unused.
(struct arm_opcode): Rename struct opcode32. Make 'assembler' const.
(struct thumb_opcode): Rename struct opcode16. Make 'assembler' const.
(arm_conditional, arm_fp_const, arm_shift, arm_regname, regnames)
(iwmmxt_wwnames, iwmmxt_wwssnames):
Make const.
(regnames): Remove iWMMXt coprocessor register sets.
(iwmmxt_regnames, iwmmxt_cregnames): New statics.
(get_arm_regnames): Adjust fourth argument to match above changes.
(set_iwmmxt_regnames): Delete.
(print_insn_arm): Constify 'c'. Use ISO syntax for function
pointer calls. Expand sole use of BDISP. Use iwmmxt_regnames
and iwmmxt_cregnames, not set_iwmmxt_regnames.
(print_insn_thumb16, print_insn_thumb32): Constify 'c'. Use
ISO syntax for function pointer calls.
include:
* dis-asm.h (get_arm_regnames): Update prototype.
2005-06-08 19:27:41 +02:00
|
|
|
|
const struct opcode32 *insn;
|
2002-12-02 14:13:37 +01:00
|
|
|
|
void *stream = info->stream;
|
opcodes:
* arm-opc.h: Delete; fold contents into ...
* arm-dis.c: ... here. Move includes of internal COFF headers
next to includes of internal ELF headers.
(streq, WORD_ADDRESS, BDISP, BDISP23): Delete, unused.
(struct arm_opcode): Rename struct opcode32. Make 'assembler' const.
(struct thumb_opcode): Rename struct opcode16. Make 'assembler' const.
(arm_conditional, arm_fp_const, arm_shift, arm_regname, regnames)
(iwmmxt_wwnames, iwmmxt_wwssnames):
Make const.
(regnames): Remove iWMMXt coprocessor register sets.
(iwmmxt_regnames, iwmmxt_cregnames): New statics.
(get_arm_regnames): Adjust fourth argument to match above changes.
(set_iwmmxt_regnames): Delete.
(print_insn_arm): Constify 'c'. Use ISO syntax for function
pointer calls. Expand sole use of BDISP. Use iwmmxt_regnames
and iwmmxt_cregnames, not set_iwmmxt_regnames.
(print_insn_thumb16, print_insn_thumb32): Constify 'c'. Use
ISO syntax for function pointer calls.
include:
* dis-asm.h (get_arm_regnames): Update prototype.
2005-06-08 19:27:41 +02:00
|
|
|
|
fprintf_ftype func = info->fprintf_func;
|
2010-01-29 17:47:55 +01:00
|
|
|
|
struct arm_private_data *private_data = info->private_data;
|
1999-05-03 09:29:11 +02:00
|
|
|
|
|
2006-04-26 17:40:55 +02:00
|
|
|
|
if (print_insn_coprocessor (pc, info, given, FALSE))
|
|
|
|
|
|
return;
|
|
|
|
|
|
|
|
|
|
|
|
if (print_insn_neon (info, given, FALSE))
|
2005-09-02 Paul Brook <paul@codesourcery.com>
bfd/
* libbdf.h: Regenerate.
* bfd-in2.h: Regenerate.
* reloc.c: Add BFD_RELOC_ARM_T32_CP_OFF_IMM and
BFD_RELOC_ARM_T32_CP_OFF_IMM_S2.
gas/
* config/tc-arm.c (encode_arm_cp_address): Use
BFD_RELOC_ARM_T32_CP_OFF_IMM in thumb mode.
(do_iwmmxt_wldstbh): Use BFD_RELOC_ARM_T32_CP_OFF_IMM_S2 in thumb
mode.
(md_assemble): Only allow coprocessor instructions when Thumb-2 is
available.
(cCE, cC3): Define.
(insns): Use them for coprocessor instructions.
(md_pcrel_from_section): Handle BFD_RELOC_ARM_T32_CP_OFF_IMM.
(get_thumb32_insn): New function.
(put_thumb32_insn): New function.
(md_apply_fix): Handle BFD_RELOC_ARM_T32_CP_OFF_IMM and
BFD_RELOC_ARM_T32_CP_OFF_IMM_S2.
gas/testsuite/
* gas/arm/vfp-bad_t2.d, gas/arm/vfp-bad_t2.l, arm/vfp-bad_t2.s,
gas/arm/vfp1_t2.d, gas/arm/vfp1_t2.s, gas/arm/vfp1xD_t2.d,
gas/arm/vfp1xD_t2.s, gas/arm/vfp2_t2.d, gas/arm/vfp2_t2.s): New files.
opcodes/
* arm-dis.c (coprocessor_opcodes): New.
(arm_opcodes, thumb32_opcodes): Remove coprocessor insns.
(print_insn_coprocessor): New function.
(print_insn_arm): Use print_insn_coprocessor. Remove coprocessor
format characters.
(print_insn_thumb32): Use print_insn_coprocessor.
2005-09-02 15:12:45 +02:00
|
|
|
|
return;
|
|
|
|
|
|
|
1999-05-03 09:29:11 +02:00
|
|
|
|
for (insn = arm_opcodes; insn->assembler; insn++)
|
|
|
|
|
|
{
|
2009-06-18 12:31:21 +02:00
|
|
|
|
if ((given & insn->mask) != insn->value)
|
|
|
|
|
|
continue;
|
2015-03-24 07:08:08 +01:00
|
|
|
|
|
|
|
|
|
|
if (! ARM_CPU_HAS_FEATURE (insn->arch, private_data->features))
|
2009-06-18 12:31:21 +02:00
|
|
|
|
continue;
|
|
|
|
|
|
|
|
|
|
|
|
/* Special case: an instruction with all bits set in the condition field
|
|
|
|
|
|
(0xFnnn_nnnn) is only matched if all those bits are set in insn->mask,
|
|
|
|
|
|
or by the catchall at the end of the table. */
|
|
|
|
|
|
if ((given & 0xF0000000) != 0xF0000000
|
|
|
|
|
|
|| (insn->mask & 0xF0000000) == 0xF0000000
|
|
|
|
|
|
|| (insn->mask == 0 && insn->value == 0))
|
1999-05-03 09:29:11 +02:00
|
|
|
|
{
|
2009-12-17 10:52:18 +01:00
|
|
|
|
unsigned long u_reg = 16;
|
|
|
|
|
|
unsigned long U_reg = 16;
|
2009-12-14 17:38:23 +01:00
|
|
|
|
bfd_boolean is_unpredictable = FALSE;
|
2009-06-29 10:08:15 +02:00
|
|
|
|
signed long value_in_comment = 0;
|
opcodes:
* arm-opc.h: Delete; fold contents into ...
* arm-dis.c: ... here. Move includes of internal COFF headers
next to includes of internal ELF headers.
(streq, WORD_ADDRESS, BDISP, BDISP23): Delete, unused.
(struct arm_opcode): Rename struct opcode32. Make 'assembler' const.
(struct thumb_opcode): Rename struct opcode16. Make 'assembler' const.
(arm_conditional, arm_fp_const, arm_shift, arm_regname, regnames)
(iwmmxt_wwnames, iwmmxt_wwssnames):
Make const.
(regnames): Remove iWMMXt coprocessor register sets.
(iwmmxt_regnames, iwmmxt_cregnames): New statics.
(get_arm_regnames): Adjust fourth argument to match above changes.
(set_iwmmxt_regnames): Delete.
(print_insn_arm): Constify 'c'. Use ISO syntax for function
pointer calls. Expand sole use of BDISP. Use iwmmxt_regnames
and iwmmxt_cregnames, not set_iwmmxt_regnames.
(print_insn_thumb16, print_insn_thumb32): Constify 'c'. Use
ISO syntax for function pointer calls.
include:
* dis-asm.h (get_arm_regnames): Update prototype.
2005-06-08 19:27:41 +02:00
|
|
|
|
const char *c;
|
2002-11-30 09:39:46 +01:00
|
|
|
|
|
1999-05-03 09:29:11 +02:00
|
|
|
|
for (c = insn->assembler; *c; c++)
|
|
|
|
|
|
{
|
|
|
|
|
|
if (*c == '%')
|
|
|
|
|
|
{
|
2009-11-11 10:44:45 +01:00
|
|
|
|
bfd_boolean allow_unpredictable = FALSE;
|
|
|
|
|
|
|
1999-05-03 09:29:11 +02:00
|
|
|
|
switch (*++c)
|
|
|
|
|
|
{
|
|
|
|
|
|
case '%':
|
|
|
|
|
|
func (stream, "%%");
|
|
|
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
|
|
case 'a':
|
2009-06-29 10:08:15 +02:00
|
|
|
|
value_in_comment = print_arm_address (pc, info, given);
|
2006-02-24 Paul Brook <paul@codesourcery.com>
gas/
* config/arm/tc-arm.c (arm_ext_v6_notm, arm_ext_div, arm_ext_v7,
arm_ext_v7a, arm_ext_v7r, arm_ext_v7m): New variables.
(struct asm_barrier_opt): Define.
(arm_v7m_psr_hsh, arm_barrier_opt_hsh): New variables.
(parse_psr): Accept V7M psr names.
(parse_barrier): New function.
(enum operand_parse_code): Add OP_oBARRIER.
(parse_operands): Implement OP_oBARRIER.
(do_barrier): New function.
(do_dbg, do_pli, do_t_barrier, do_t_dbg, do_t_div): New functions.
(do_t_cpsi): Add V7M restrictions.
(do_t_mrs, do_t_msr): Validate V7M variants.
(md_assemble): Check for NULL variants.
(v7m_psrs, barrier_opt_names): New tables.
(insns): Add V7 instructions. Mark V6 instructions absent from V7M.
(md_begin): Initialize arm_v7m_psr_hsh and arm_barrier_opt_hsh.
(arm_cpu_option_table): Add Cortex-M3, R4 and A8.
(arm_arch_option_table): Add armv7, armv7a, armv7r and armv7m.
(struct cpu_arch_ver_table): Define.
(cpu_arch_ver): New.
(aeabi_set_public_attributes): Use cpu_arch_ver. Set
Tag_CPU_arch_profile.
* doc/c-arm.texi: Document new cpu and arch options.
gas/testsuite/
* gas/arm/thumb32.d: Fix expected msr and mrs output.
* gas/arm/arch7.d: New test.
* gas/arm/arch7.s: New test.
* gas/arm/arch7m-bad.l: New test.
* gas/arm/arch7m-bad.d: New test.
* gas/arm/arch7m-bad.s: New test.
include/opcode/
* arm.h: Add V7 feature bits.
opcodes/
* arm-dis.c (arm_opcodes): Add V7 instructions.
(thumb32_opcodes): Ditto. Handle V7M MSR/MRS variants.
(print_arm_address): New function.
(print_insn_arm): Use it. Add 'P' and 'U' cases.
(psr_name): New function.
(print_insn_thumb32): Add 'U', 'C' and 'D' cases.
2006-02-24 16:36:36 +01:00
|
|
|
|
break;
|
1999-05-03 09:29:11 +02:00
|
|
|
|
|
2006-02-24 Paul Brook <paul@codesourcery.com>
gas/
* config/arm/tc-arm.c (arm_ext_v6_notm, arm_ext_div, arm_ext_v7,
arm_ext_v7a, arm_ext_v7r, arm_ext_v7m): New variables.
(struct asm_barrier_opt): Define.
(arm_v7m_psr_hsh, arm_barrier_opt_hsh): New variables.
(parse_psr): Accept V7M psr names.
(parse_barrier): New function.
(enum operand_parse_code): Add OP_oBARRIER.
(parse_operands): Implement OP_oBARRIER.
(do_barrier): New function.
(do_dbg, do_pli, do_t_barrier, do_t_dbg, do_t_div): New functions.
(do_t_cpsi): Add V7M restrictions.
(do_t_mrs, do_t_msr): Validate V7M variants.
(md_assemble): Check for NULL variants.
(v7m_psrs, barrier_opt_names): New tables.
(insns): Add V7 instructions. Mark V6 instructions absent from V7M.
(md_begin): Initialize arm_v7m_psr_hsh and arm_barrier_opt_hsh.
(arm_cpu_option_table): Add Cortex-M3, R4 and A8.
(arm_arch_option_table): Add armv7, armv7a, armv7r and armv7m.
(struct cpu_arch_ver_table): Define.
(cpu_arch_ver): New.
(aeabi_set_public_attributes): Use cpu_arch_ver. Set
Tag_CPU_arch_profile.
* doc/c-arm.texi: Document new cpu and arch options.
gas/testsuite/
* gas/arm/thumb32.d: Fix expected msr and mrs output.
* gas/arm/arch7.d: New test.
* gas/arm/arch7.s: New test.
* gas/arm/arch7m-bad.l: New test.
* gas/arm/arch7m-bad.d: New test.
* gas/arm/arch7m-bad.s: New test.
include/opcode/
* arm.h: Add V7 feature bits.
opcodes/
* arm-dis.c (arm_opcodes): Add V7 instructions.
(thumb32_opcodes): Ditto. Handle V7M MSR/MRS variants.
(print_arm_address): New function.
(print_insn_arm): Use it. Add 'P' and 'U' cases.
(psr_name): New function.
(print_insn_thumb32): Add 'U', 'C' and 'D' cases.
2006-02-24 16:36:36 +01:00
|
|
|
|
case 'P':
|
|
|
|
|
|
/* Set P address bit and use normal address
|
|
|
|
|
|
printing routine. */
|
2009-11-11 10:44:45 +01:00
|
|
|
|
value_in_comment = print_arm_address (pc, info, given | (1 << P_BIT));
|
1999-05-03 09:29:11 +02:00
|
|
|
|
break;
|
|
|
|
|
|
|
2009-11-11 10:44:45 +01:00
|
|
|
|
case 'S':
|
|
|
|
|
|
allow_unpredictable = TRUE;
|
2016-10-05 09:47:02 +02:00
|
|
|
|
/* Fall through. */
|
1999-05-03 09:29:11 +02:00
|
|
|
|
case 's':
|
|
|
|
|
|
if ((given & 0x004f0000) == 0x004f0000)
|
|
|
|
|
|
{
|
2000-01-27 23:17:12 +01:00
|
|
|
|
/* PC relative with immediate offset. */
|
2011-06-03 12:04:03 +02:00
|
|
|
|
bfd_vma offset = ((given & 0xf00) >> 4) | (given & 0xf);
|
2002-11-30 09:39:46 +01:00
|
|
|
|
|
2009-11-17 18:20:26 +01:00
|
|
|
|
if (PRE_BIT_SET)
|
|
|
|
|
|
{
|
2011-06-02 17:32:10 +02:00
|
|
|
|
/* Elide positive zero offset. */
|
|
|
|
|
|
if (offset || NEGATIVE_BIT_SET)
|
|
|
|
|
|
func (stream, "[pc, #%s%d]\t; ",
|
2012-07-24 14:56:47 +02:00
|
|
|
|
NEGATIVE_BIT_SET ? "-" : "", (int) offset);
|
2009-11-19 15:07:11 +01:00
|
|
|
|
else
|
2011-06-02 17:32:10 +02:00
|
|
|
|
func (stream, "[pc]\t; ");
|
|
|
|
|
|
if (NEGATIVE_BIT_SET)
|
|
|
|
|
|
offset = -offset;
|
2009-11-17 18:20:26 +01:00
|
|
|
|
info->print_address_func (offset + pc + 8, info);
|
|
|
|
|
|
}
|
|
|
|
|
|
else
|
|
|
|
|
|
{
|
2011-06-02 17:32:10 +02:00
|
|
|
|
/* Always show the offset. */
|
|
|
|
|
|
func (stream, "[pc], #%s%d",
|
2012-07-24 14:56:47 +02:00
|
|
|
|
NEGATIVE_BIT_SET ? "-" : "", (int) offset);
|
2009-12-17 10:52:18 +01:00
|
|
|
|
if (! allow_unpredictable)
|
|
|
|
|
|
is_unpredictable = TRUE;
|
2009-11-17 18:20:26 +01:00
|
|
|
|
}
|
1999-05-03 09:29:11 +02:00
|
|
|
|
}
|
|
|
|
|
|
else
|
|
|
|
|
|
{
|
2009-06-30 13:57:05 +02:00
|
|
|
|
int offset = ((given & 0xf00) >> 4) | (given & 0xf);
|
|
|
|
|
|
|
2002-11-30 09:39:46 +01:00
|
|
|
|
func (stream, "[%s",
|
1999-05-03 09:29:11 +02:00
|
|
|
|
arm_regnames[(given >> 16) & 0xf]);
|
2009-06-30 13:57:05 +02:00
|
|
|
|
|
2009-11-11 10:44:45 +01:00
|
|
|
|
if (PRE_BIT_SET)
|
1999-05-03 09:29:11 +02:00
|
|
|
|
{
|
2009-11-11 10:44:45 +01:00
|
|
|
|
if (IMMEDIATE_BIT_SET)
|
1999-05-03 09:29:11 +02:00
|
|
|
|
{
|
2011-06-02 17:32:10 +02:00
|
|
|
|
/* Elide offset for non-writeback
|
|
|
|
|
|
positive zero. */
|
|
|
|
|
|
if (WRITEBACK_BIT_SET || NEGATIVE_BIT_SET
|
|
|
|
|
|
|| offset)
|
|
|
|
|
|
func (stream, ", #%s%d",
|
|
|
|
|
|
NEGATIVE_BIT_SET ? "-" : "", offset);
|
|
|
|
|
|
|
|
|
|
|
|
if (NEGATIVE_BIT_SET)
|
|
|
|
|
|
offset = -offset;
|
2009-11-19 15:07:11 +01:00
|
|
|
|
|
2009-06-30 13:57:05 +02:00
|
|
|
|
value_in_comment = offset;
|
1999-05-03 09:29:11 +02:00
|
|
|
|
}
|
2009-11-19 15:07:11 +01:00
|
|
|
|
else
|
2009-12-17 10:52:18 +01:00
|
|
|
|
{
|
|
|
|
|
|
/* Register Offset or Register Pre-Indexed. */
|
|
|
|
|
|
func (stream, ", %s%s",
|
|
|
|
|
|
NEGATIVE_BIT_SET ? "-" : "",
|
|
|
|
|
|
arm_regnames[given & 0xf]);
|
|
|
|
|
|
|
|
|
|
|
|
/* Writing back to the register that is the source/
|
|
|
|
|
|
destination of the load/store is unpredictable. */
|
|
|
|
|
|
if (! allow_unpredictable
|
|
|
|
|
|
&& WRITEBACK_BIT_SET
|
|
|
|
|
|
&& ((given & 0xf) == ((given >> 12) & 0xf)))
|
|
|
|
|
|
is_unpredictable = TRUE;
|
|
|
|
|
|
}
|
1999-05-03 09:29:11 +02:00
|
|
|
|
|
2002-11-30 09:39:46 +01:00
|
|
|
|
func (stream, "]%s",
|
2009-11-11 10:44:45 +01:00
|
|
|
|
WRITEBACK_BIT_SET ? "!" : "");
|
1999-05-03 09:29:11 +02:00
|
|
|
|
}
|
2009-11-19 15:07:11 +01:00
|
|
|
|
else
|
1999-05-03 09:29:11 +02:00
|
|
|
|
{
|
2009-11-11 10:44:45 +01:00
|
|
|
|
if (IMMEDIATE_BIT_SET)
|
1999-05-03 09:29:11 +02:00
|
|
|
|
{
|
2009-11-19 15:07:11 +01:00
|
|
|
|
/* Immediate Post-indexed. */
|
2009-11-17 18:20:26 +01:00
|
|
|
|
/* PR 10924: Offset must be printed, even if it is zero. */
|
2011-06-02 17:32:10 +02:00
|
|
|
|
func (stream, "], #%s%d",
|
|
|
|
|
|
NEGATIVE_BIT_SET ? "-" : "", offset);
|
|
|
|
|
|
if (NEGATIVE_BIT_SET)
|
|
|
|
|
|
offset = -offset;
|
2009-06-30 13:57:05 +02:00
|
|
|
|
value_in_comment = offset;
|
1999-05-03 09:29:11 +02:00
|
|
|
|
}
|
2009-11-19 15:07:11 +01:00
|
|
|
|
else
|
2009-12-17 10:52:18 +01:00
|
|
|
|
{
|
|
|
|
|
|
/* Register Post-indexed. */
|
|
|
|
|
|
func (stream, "], %s%s",
|
|
|
|
|
|
NEGATIVE_BIT_SET ? "-" : "",
|
|
|
|
|
|
arm_regnames[given & 0xf]);
|
|
|
|
|
|
|
|
|
|
|
|
/* Writing back to the register that is the source/
|
|
|
|
|
|
destination of the load/store is unpredictable. */
|
|
|
|
|
|
if (! allow_unpredictable
|
|
|
|
|
|
&& (given & 0xf) == ((given >> 12) & 0xf))
|
|
|
|
|
|
is_unpredictable = TRUE;
|
|
|
|
|
|
}
|
2009-11-11 10:44:45 +01:00
|
|
|
|
|
2009-12-09 09:38:04 +01:00
|
|
|
|
if (! allow_unpredictable)
|
|
|
|
|
|
{
|
|
|
|
|
|
/* Writeback is automatically implied by post- addressing.
|
|
|
|
|
|
Setting the W bit is unnecessary and ARM specify it as
|
|
|
|
|
|
being unpredictable. */
|
|
|
|
|
|
if (WRITEBACK_BIT_SET
|
|
|
|
|
|
/* Specifying the PC register as the post-indexed
|
|
|
|
|
|
registers is also unpredictable. */
|
2009-12-14 17:38:23 +01:00
|
|
|
|
|| (! IMMEDIATE_BIT_SET && ((given & 0xf) == 0xf)))
|
|
|
|
|
|
is_unpredictable = TRUE;
|
2009-12-09 09:38:04 +01:00
|
|
|
|
}
|
1999-05-03 09:29:11 +02:00
|
|
|
|
}
|
|
|
|
|
|
}
|
|
|
|
|
|
break;
|
2002-11-30 09:39:46 +01:00
|
|
|
|
|
1999-05-03 09:29:11 +02:00
|
|
|
|
case 'b':
|
opcodes:
* arm-opc.h: Delete; fold contents into ...
* arm-dis.c: ... here. Move includes of internal COFF headers
next to includes of internal ELF headers.
(streq, WORD_ADDRESS, BDISP, BDISP23): Delete, unused.
(struct arm_opcode): Rename struct opcode32. Make 'assembler' const.
(struct thumb_opcode): Rename struct opcode16. Make 'assembler' const.
(arm_conditional, arm_fp_const, arm_shift, arm_regname, regnames)
(iwmmxt_wwnames, iwmmxt_wwssnames):
Make const.
(regnames): Remove iWMMXt coprocessor register sets.
(iwmmxt_regnames, iwmmxt_cregnames): New statics.
(get_arm_regnames): Adjust fourth argument to match above changes.
(set_iwmmxt_regnames): Delete.
(print_insn_arm): Constify 'c'. Use ISO syntax for function
pointer calls. Expand sole use of BDISP. Use iwmmxt_regnames
and iwmmxt_cregnames, not set_iwmmxt_regnames.
(print_insn_thumb16, print_insn_thumb32): Constify 'c'. Use
ISO syntax for function pointer calls.
include:
* dis-asm.h (get_arm_regnames): Update prototype.
2005-06-08 19:27:41 +02:00
|
|
|
|
{
|
2011-06-03 12:04:03 +02:00
|
|
|
|
bfd_vma disp = (((given & 0xffffff) ^ 0x800000) - 0x800000);
|
2009-06-29 10:08:15 +02:00
|
|
|
|
info->print_address_func (disp * 4 + pc + 8, info);
|
opcodes:
* arm-opc.h: Delete; fold contents into ...
* arm-dis.c: ... here. Move includes of internal COFF headers
next to includes of internal ELF headers.
(streq, WORD_ADDRESS, BDISP, BDISP23): Delete, unused.
(struct arm_opcode): Rename struct opcode32. Make 'assembler' const.
(struct thumb_opcode): Rename struct opcode16. Make 'assembler' const.
(arm_conditional, arm_fp_const, arm_shift, arm_regname, regnames)
(iwmmxt_wwnames, iwmmxt_wwssnames):
Make const.
(regnames): Remove iWMMXt coprocessor register sets.
(iwmmxt_regnames, iwmmxt_cregnames): New statics.
(get_arm_regnames): Adjust fourth argument to match above changes.
(set_iwmmxt_regnames): Delete.
(print_insn_arm): Constify 'c'. Use ISO syntax for function
pointer calls. Expand sole use of BDISP. Use iwmmxt_regnames
and iwmmxt_cregnames, not set_iwmmxt_regnames.
(print_insn_thumb16, print_insn_thumb32): Constify 'c'. Use
ISO syntax for function pointer calls.
include:
* dis-asm.h (get_arm_regnames): Update prototype.
2005-06-08 19:27:41 +02:00
|
|
|
|
}
|
1999-05-03 09:29:11 +02:00
|
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
|
|
case 'c':
|
2006-06-07 16:08:19 +02:00
|
|
|
|
if (((given >> 28) & 0xf) != 0xe)
|
|
|
|
|
|
func (stream, "%s",
|
|
|
|
|
|
arm_conditional [(given >> 28) & 0xf]);
|
1999-05-03 09:29:11 +02:00
|
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
|
|
case 'm':
|
|
|
|
|
|
{
|
|
|
|
|
|
int started = 0;
|
|
|
|
|
|
int reg;
|
|
|
|
|
|
|
|
|
|
|
|
func (stream, "{");
|
|
|
|
|
|
for (reg = 0; reg < 16; reg++)
|
|
|
|
|
|
if ((given & (1 << reg)) != 0)
|
|
|
|
|
|
{
|
|
|
|
|
|
if (started)
|
|
|
|
|
|
func (stream, ", ");
|
|
|
|
|
|
started = 1;
|
|
|
|
|
|
func (stream, "%s", arm_regnames[reg]);
|
|
|
|
|
|
}
|
|
|
|
|
|
func (stream, "}");
|
2009-12-14 17:38:23 +01:00
|
|
|
|
if (! started)
|
|
|
|
|
|
is_unpredictable = TRUE;
|
1999-05-03 09:29:11 +02:00
|
|
|
|
}
|
|
|
|
|
|
break;
|
|
|
|
|
|
|
2007-04-21 21:44:09 +02:00
|
|
|
|
case 'q':
|
2009-07-07 16:46:14 +02:00
|
|
|
|
arm_decode_shift (given, func, stream, FALSE);
|
2007-04-21 21:44:09 +02:00
|
|
|
|
break;
|
|
|
|
|
|
|
1999-05-03 09:29:11 +02:00
|
|
|
|
case 'o':
|
|
|
|
|
|
if ((given & 0x02000000) != 0)
|
|
|
|
|
|
{
|
2011-10-18 16:41:55 +02:00
|
|
|
|
unsigned int rotate = (given & 0xf00) >> 7;
|
|
|
|
|
|
unsigned int immed = (given & 0xff);
|
|
|
|
|
|
unsigned int a, i;
|
|
|
|
|
|
|
|
|
|
|
|
a = (((immed << (32 - rotate))
|
|
|
|
|
|
| (immed >> rotate)) & 0xffffffff);
|
|
|
|
|
|
/* If there is another encoding with smaller rotate,
|
|
|
|
|
|
the rotate should be specified directly. */
|
|
|
|
|
|
for (i = 0; i < 32; i += 2)
|
|
|
|
|
|
if ((a << i | a >> (32 - i)) <= 0xff)
|
|
|
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
|
|
if (i != rotate)
|
|
|
|
|
|
func (stream, "#%d, %d", immed, rotate);
|
|
|
|
|
|
else
|
|
|
|
|
|
func (stream, "#%d", a);
|
|
|
|
|
|
value_in_comment = a;
|
1999-05-03 09:29:11 +02:00
|
|
|
|
}
|
|
|
|
|
|
else
|
2009-07-07 16:46:14 +02:00
|
|
|
|
arm_decode_shift (given, func, stream, TRUE);
|
1999-05-03 09:29:11 +02:00
|
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
|
|
case 'p':
|
|
|
|
|
|
if ((given & 0x0000f000) == 0x0000f000)
|
2009-11-17 18:20:26 +01:00
|
|
|
|
{
|
2015-03-24 07:08:08 +01:00
|
|
|
|
arm_feature_set arm_ext_v6 =
|
|
|
|
|
|
ARM_FEATURE_CORE_LOW (ARM_EXT_V6);
|
|
|
|
|
|
|
2009-11-17 18:20:26 +01:00
|
|
|
|
/* The p-variants of tst/cmp/cmn/teq are the pre-V6
|
|
|
|
|
|
mechanism for setting PSR flag bits. They are
|
|
|
|
|
|
obsolete in V6 onwards. */
|
2015-03-24 07:08:08 +01:00
|
|
|
|
if (! ARM_CPU_HAS_FEATURE (private_data->features, \
|
|
|
|
|
|
arm_ext_v6))
|
2009-11-17 18:20:26 +01:00
|
|
|
|
func (stream, "p");
|
2015-08-13 12:39:08 +02:00
|
|
|
|
else
|
|
|
|
|
|
is_unpredictable = TRUE;
|
2009-11-17 18:20:26 +01:00
|
|
|
|
}
|
1999-05-03 09:29:11 +02:00
|
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
|
|
case 't':
|
|
|
|
|
|
if ((given & 0x01200000) == 0x00200000)
|
|
|
|
|
|
func (stream, "t");
|
|
|
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
|
|
case 'A':
|
2009-06-29 10:08:15 +02:00
|
|
|
|
{
|
|
|
|
|
|
int offset = given & 0xff;
|
2003-08-19 15:05:42 +02:00
|
|
|
|
|
2009-06-29 10:08:15 +02:00
|
|
|
|
value_in_comment = offset * 4;
|
2009-11-11 10:44:45 +01:00
|
|
|
|
if (NEGATIVE_BIT_SET)
|
2009-06-29 10:08:15 +02:00
|
|
|
|
value_in_comment = - value_in_comment;
|
2003-08-19 15:05:42 +02:00
|
|
|
|
|
2009-06-29 10:08:15 +02:00
|
|
|
|
func (stream, "[%s", arm_regnames [(given >> 16) & 0xf]);
|
2003-08-19 15:05:42 +02:00
|
|
|
|
|
2009-11-11 10:44:45 +01:00
|
|
|
|
if (PRE_BIT_SET)
|
2009-06-29 10:08:15 +02:00
|
|
|
|
{
|
|
|
|
|
|
if (offset)
|
2009-06-30 13:57:05 +02:00
|
|
|
|
func (stream, ", #%d]%s",
|
2012-07-24 14:56:47 +02:00
|
|
|
|
(int) value_in_comment,
|
2009-11-11 10:44:45 +01:00
|
|
|
|
WRITEBACK_BIT_SET ? "!" : "");
|
2009-06-29 10:08:15 +02:00
|
|
|
|
else
|
|
|
|
|
|
func (stream, "]");
|
|
|
|
|
|
}
|
|
|
|
|
|
else
|
|
|
|
|
|
{
|
|
|
|
|
|
func (stream, "]");
|
2003-08-19 15:05:42 +02:00
|
|
|
|
|
2009-11-11 10:44:45 +01:00
|
|
|
|
if (WRITEBACK_BIT_SET)
|
2009-06-29 10:08:15 +02:00
|
|
|
|
{
|
|
|
|
|
|
if (offset)
|
2012-07-24 14:56:47 +02:00
|
|
|
|
func (stream, ", #%d", (int) value_in_comment);
|
2009-06-29 10:08:15 +02:00
|
|
|
|
}
|
|
|
|
|
|
else
|
2009-06-30 13:57:05 +02:00
|
|
|
|
{
|
2012-07-24 14:56:47 +02:00
|
|
|
|
func (stream, ", {%d}", (int) offset);
|
2009-06-30 13:57:05 +02:00
|
|
|
|
value_in_comment = offset;
|
|
|
|
|
|
}
|
2009-06-29 10:08:15 +02:00
|
|
|
|
}
|
|
|
|
|
|
}
|
1999-05-03 09:29:11 +02:00
|
|
|
|
break;
|
|
|
|
|
|
|
2000-11-25 01:21:40 +01:00
|
|
|
|
case 'B':
|
|
|
|
|
|
/* Print ARM V5 BLX(1) address: pc+25 bits. */
|
|
|
|
|
|
{
|
|
|
|
|
|
bfd_vma address;
|
|
|
|
|
|
bfd_vma offset = 0;
|
2002-11-30 09:39:46 +01:00
|
|
|
|
|
2009-11-11 10:44:45 +01:00
|
|
|
|
if (! NEGATIVE_BIT_SET)
|
2000-11-25 01:21:40 +01:00
|
|
|
|
/* Is signed, hi bits should be ones. */
|
|
|
|
|
|
offset = (-1) ^ 0x00ffffff;
|
|
|
|
|
|
|
|
|
|
|
|
/* Offset is (SignExtend(offset field)<<2). */
|
|
|
|
|
|
offset += given & 0x00ffffff;
|
|
|
|
|
|
offset <<= 2;
|
|
|
|
|
|
address = offset + pc + 8;
|
2002-11-30 09:39:46 +01:00
|
|
|
|
|
2005-09-02 Paul Brook <paul@codesourcery.com>
bfd/
* libbdf.h: Regenerate.
* bfd-in2.h: Regenerate.
* reloc.c: Add BFD_RELOC_ARM_T32_CP_OFF_IMM and
BFD_RELOC_ARM_T32_CP_OFF_IMM_S2.
gas/
* config/tc-arm.c (encode_arm_cp_address): Use
BFD_RELOC_ARM_T32_CP_OFF_IMM in thumb mode.
(do_iwmmxt_wldstbh): Use BFD_RELOC_ARM_T32_CP_OFF_IMM_S2 in thumb
mode.
(md_assemble): Only allow coprocessor instructions when Thumb-2 is
available.
(cCE, cC3): Define.
(insns): Use them for coprocessor instructions.
(md_pcrel_from_section): Handle BFD_RELOC_ARM_T32_CP_OFF_IMM.
(get_thumb32_insn): New function.
(put_thumb32_insn): New function.
(md_apply_fix): Handle BFD_RELOC_ARM_T32_CP_OFF_IMM and
BFD_RELOC_ARM_T32_CP_OFF_IMM_S2.
gas/testsuite/
* gas/arm/vfp-bad_t2.d, gas/arm/vfp-bad_t2.l, arm/vfp-bad_t2.s,
gas/arm/vfp1_t2.d, gas/arm/vfp1_t2.s, gas/arm/vfp1xD_t2.d,
gas/arm/vfp1xD_t2.s, gas/arm/vfp2_t2.d, gas/arm/vfp2_t2.s): New files.
opcodes/
* arm-dis.c (coprocessor_opcodes): New.
(arm_opcodes, thumb32_opcodes): Remove coprocessor insns.
(print_insn_coprocessor): New function.
(print_insn_arm): Use print_insn_coprocessor. Remove coprocessor
format characters.
(print_insn_thumb32): Use print_insn_coprocessor.
2005-09-02 15:12:45 +02:00
|
|
|
|
if (given & 0x01000000)
|
|
|
|
|
|
/* H bit allows addressing to 2-byte boundaries. */
|
|
|
|
|
|
address += 2;
|
2001-10-08 20:50:37 +02:00
|
|
|
|
|
2005-09-02 Paul Brook <paul@codesourcery.com>
bfd/
* libbdf.h: Regenerate.
* bfd-in2.h: Regenerate.
* reloc.c: Add BFD_RELOC_ARM_T32_CP_OFF_IMM and
BFD_RELOC_ARM_T32_CP_OFF_IMM_S2.
gas/
* config/tc-arm.c (encode_arm_cp_address): Use
BFD_RELOC_ARM_T32_CP_OFF_IMM in thumb mode.
(do_iwmmxt_wldstbh): Use BFD_RELOC_ARM_T32_CP_OFF_IMM_S2 in thumb
mode.
(md_assemble): Only allow coprocessor instructions when Thumb-2 is
available.
(cCE, cC3): Define.
(insns): Use them for coprocessor instructions.
(md_pcrel_from_section): Handle BFD_RELOC_ARM_T32_CP_OFF_IMM.
(get_thumb32_insn): New function.
(put_thumb32_insn): New function.
(md_apply_fix): Handle BFD_RELOC_ARM_T32_CP_OFF_IMM and
BFD_RELOC_ARM_T32_CP_OFF_IMM_S2.
gas/testsuite/
* gas/arm/vfp-bad_t2.d, gas/arm/vfp-bad_t2.l, arm/vfp-bad_t2.s,
gas/arm/vfp1_t2.d, gas/arm/vfp1_t2.s, gas/arm/vfp1xD_t2.d,
gas/arm/vfp1xD_t2.s, gas/arm/vfp2_t2.d, gas/arm/vfp2_t2.s): New files.
opcodes/
* arm-dis.c (coprocessor_opcodes): New.
(arm_opcodes, thumb32_opcodes): Remove coprocessor insns.
(print_insn_coprocessor): New function.
(print_insn_arm): Use print_insn_coprocessor. Remove coprocessor
format characters.
(print_insn_thumb32): Use print_insn_coprocessor.
2005-09-02 15:12:45 +02:00
|
|
|
|
info->print_address_func (address, info);
|
2001-10-08 20:50:37 +02:00
|
|
|
|
}
|
|
|
|
|
|
break;
|
|
|
|
|
|
|
1999-05-03 09:29:11 +02:00
|
|
|
|
case 'C':
|
2010-09-23 17:52:19 +02:00
|
|
|
|
if ((given & 0x02000200) == 0x200)
|
|
|
|
|
|
{
|
|
|
|
|
|
const char * name;
|
|
|
|
|
|
unsigned sysm = (given & 0x004f0000) >> 16;
|
|
|
|
|
|
|
|
|
|
|
|
sysm |= (given & 0x300) >> 4;
|
|
|
|
|
|
name = banked_regname (sysm);
|
|
|
|
|
|
|
|
|
|
|
|
if (name != NULL)
|
|
|
|
|
|
func (stream, "%s", name);
|
|
|
|
|
|
else
|
2012-07-24 14:56:47 +02:00
|
|
|
|
func (stream, "(UNDEF: %lu)", (unsigned long) sysm);
|
2010-09-23 17:52:19 +02:00
|
|
|
|
}
|
|
|
|
|
|
else
|
|
|
|
|
|
{
|
2015-08-12 13:45:07 +02:00
|
|
|
|
func (stream, "%cPSR_",
|
2010-09-23 17:52:19 +02:00
|
|
|
|
(given & 0x00400000) ? 'S' : 'C');
|
|
|
|
|
|
if (given & 0x80000)
|
|
|
|
|
|
func (stream, "f");
|
|
|
|
|
|
if (given & 0x40000)
|
|
|
|
|
|
func (stream, "s");
|
|
|
|
|
|
if (given & 0x20000)
|
|
|
|
|
|
func (stream, "x");
|
|
|
|
|
|
if (given & 0x10000)
|
|
|
|
|
|
func (stream, "c");
|
|
|
|
|
|
}
|
1999-05-03 09:29:11 +02:00
|
|
|
|
break;
|
|
|
|
|
|
|
2006-02-24 Paul Brook <paul@codesourcery.com>
gas/
* config/arm/tc-arm.c (arm_ext_v6_notm, arm_ext_div, arm_ext_v7,
arm_ext_v7a, arm_ext_v7r, arm_ext_v7m): New variables.
(struct asm_barrier_opt): Define.
(arm_v7m_psr_hsh, arm_barrier_opt_hsh): New variables.
(parse_psr): Accept V7M psr names.
(parse_barrier): New function.
(enum operand_parse_code): Add OP_oBARRIER.
(parse_operands): Implement OP_oBARRIER.
(do_barrier): New function.
(do_dbg, do_pli, do_t_barrier, do_t_dbg, do_t_div): New functions.
(do_t_cpsi): Add V7M restrictions.
(do_t_mrs, do_t_msr): Validate V7M variants.
(md_assemble): Check for NULL variants.
(v7m_psrs, barrier_opt_names): New tables.
(insns): Add V7 instructions. Mark V6 instructions absent from V7M.
(md_begin): Initialize arm_v7m_psr_hsh and arm_barrier_opt_hsh.
(arm_cpu_option_table): Add Cortex-M3, R4 and A8.
(arm_arch_option_table): Add armv7, armv7a, armv7r and armv7m.
(struct cpu_arch_ver_table): Define.
(cpu_arch_ver): New.
(aeabi_set_public_attributes): Use cpu_arch_ver. Set
Tag_CPU_arch_profile.
* doc/c-arm.texi: Document new cpu and arch options.
gas/testsuite/
* gas/arm/thumb32.d: Fix expected msr and mrs output.
* gas/arm/arch7.d: New test.
* gas/arm/arch7.s: New test.
* gas/arm/arch7m-bad.l: New test.
* gas/arm/arch7m-bad.d: New test.
* gas/arm/arch7m-bad.s: New test.
include/opcode/
* arm.h: Add V7 feature bits.
opcodes/
* arm-dis.c (arm_opcodes): Add V7 instructions.
(thumb32_opcodes): Ditto. Handle V7M MSR/MRS variants.
(print_arm_address): New function.
(print_insn_arm): Use it. Add 'P' and 'U' cases.
(psr_name): New function.
(print_insn_thumb32): Add 'U', 'C' and 'D' cases.
2006-02-24 16:36:36 +01:00
|
|
|
|
case 'U':
|
2015-08-12 13:45:07 +02:00
|
|
|
|
if ((given & 0xf0) == 0x60)
|
2006-02-24 Paul Brook <paul@codesourcery.com>
gas/
* config/arm/tc-arm.c (arm_ext_v6_notm, arm_ext_div, arm_ext_v7,
arm_ext_v7a, arm_ext_v7r, arm_ext_v7m): New variables.
(struct asm_barrier_opt): Define.
(arm_v7m_psr_hsh, arm_barrier_opt_hsh): New variables.
(parse_psr): Accept V7M psr names.
(parse_barrier): New function.
(enum operand_parse_code): Add OP_oBARRIER.
(parse_operands): Implement OP_oBARRIER.
(do_barrier): New function.
(do_dbg, do_pli, do_t_barrier, do_t_dbg, do_t_div): New functions.
(do_t_cpsi): Add V7M restrictions.
(do_t_mrs, do_t_msr): Validate V7M variants.
(md_assemble): Check for NULL variants.
(v7m_psrs, barrier_opt_names): New tables.
(insns): Add V7 instructions. Mark V6 instructions absent from V7M.
(md_begin): Initialize arm_v7m_psr_hsh and arm_barrier_opt_hsh.
(arm_cpu_option_table): Add Cortex-M3, R4 and A8.
(arm_arch_option_table): Add armv7, armv7a, armv7r and armv7m.
(struct cpu_arch_ver_table): Define.
(cpu_arch_ver): New.
(aeabi_set_public_attributes): Use cpu_arch_ver. Set
Tag_CPU_arch_profile.
* doc/c-arm.texi: Document new cpu and arch options.
gas/testsuite/
* gas/arm/thumb32.d: Fix expected msr and mrs output.
* gas/arm/arch7.d: New test.
* gas/arm/arch7.s: New test.
* gas/arm/arch7m-bad.l: New test.
* gas/arm/arch7m-bad.d: New test.
* gas/arm/arch7m-bad.s: New test.
include/opcode/
* arm.h: Add V7 feature bits.
opcodes/
* arm-dis.c (arm_opcodes): Add V7 instructions.
(thumb32_opcodes): Ditto. Handle V7M MSR/MRS variants.
(print_arm_address): New function.
(print_insn_arm): Use it. Add 'P' and 'U' cases.
(psr_name): New function.
(print_insn_thumb32): Add 'U', 'C' and 'D' cases.
2006-02-24 16:36:36 +01:00
|
|
|
|
{
|
2010-07-09 00:40:28 +02:00
|
|
|
|
switch (given & 0xf)
|
|
|
|
|
|
{
|
|
|
|
|
|
case 0xf: func (stream, "sy"); break;
|
|
|
|
|
|
default:
|
|
|
|
|
|
func (stream, "#%d", (int) given & 0xf);
|
|
|
|
|
|
break;
|
|
|
|
|
|
}
|
2015-08-12 13:45:07 +02:00
|
|
|
|
}
|
|
|
|
|
|
else
|
2010-07-09 00:40:28 +02:00
|
|
|
|
{
|
2012-08-24 10:00:20 +02:00
|
|
|
|
const char * opt = data_barrier_option (given & 0xf);
|
|
|
|
|
|
if (opt != NULL)
|
|
|
|
|
|
func (stream, "%s", opt);
|
|
|
|
|
|
else
|
2010-07-09 00:40:28 +02:00
|
|
|
|
func (stream, "#%d", (int) given & 0xf);
|
2006-02-24 Paul Brook <paul@codesourcery.com>
gas/
* config/arm/tc-arm.c (arm_ext_v6_notm, arm_ext_div, arm_ext_v7,
arm_ext_v7a, arm_ext_v7r, arm_ext_v7m): New variables.
(struct asm_barrier_opt): Define.
(arm_v7m_psr_hsh, arm_barrier_opt_hsh): New variables.
(parse_psr): Accept V7M psr names.
(parse_barrier): New function.
(enum operand_parse_code): Add OP_oBARRIER.
(parse_operands): Implement OP_oBARRIER.
(do_barrier): New function.
(do_dbg, do_pli, do_t_barrier, do_t_dbg, do_t_div): New functions.
(do_t_cpsi): Add V7M restrictions.
(do_t_mrs, do_t_msr): Validate V7M variants.
(md_assemble): Check for NULL variants.
(v7m_psrs, barrier_opt_names): New tables.
(insns): Add V7 instructions. Mark V6 instructions absent from V7M.
(md_begin): Initialize arm_v7m_psr_hsh and arm_barrier_opt_hsh.
(arm_cpu_option_table): Add Cortex-M3, R4 and A8.
(arm_arch_option_table): Add armv7, armv7a, armv7r and armv7m.
(struct cpu_arch_ver_table): Define.
(cpu_arch_ver): New.
(aeabi_set_public_attributes): Use cpu_arch_ver. Set
Tag_CPU_arch_profile.
* doc/c-arm.texi: Document new cpu and arch options.
gas/testsuite/
* gas/arm/thumb32.d: Fix expected msr and mrs output.
* gas/arm/arch7.d: New test.
* gas/arm/arch7.s: New test.
* gas/arm/arch7m-bad.l: New test.
* gas/arm/arch7m-bad.d: New test.
* gas/arm/arch7m-bad.s: New test.
include/opcode/
* arm.h: Add V7 feature bits.
opcodes/
* arm-dis.c (arm_opcodes): Add V7 instructions.
(thumb32_opcodes): Ditto. Handle V7M MSR/MRS variants.
(print_arm_address): New function.
(print_insn_arm): Use it. Add 'P' and 'U' cases.
(psr_name): New function.
(print_insn_thumb32): Add 'U', 'C' and 'D' cases.
2006-02-24 16:36:36 +01:00
|
|
|
|
}
|
|
|
|
|
|
break;
|
|
|
|
|
|
|
2002-11-30 09:39:46 +01:00
|
|
|
|
case '0': case '1': case '2': case '3': case '4':
|
1999-05-03 09:29:11 +02:00
|
|
|
|
case '5': case '6': case '7': case '8': case '9':
|
|
|
|
|
|
{
|
2006-04-26 17:40:55 +02:00
|
|
|
|
int width;
|
|
|
|
|
|
unsigned long value;
|
1999-05-03 09:29:11 +02:00
|
|
|
|
|
2006-04-26 17:40:55 +02:00
|
|
|
|
c = arm_decode_bitfield (c, given, &value, &width);
|
2015-08-12 13:45:07 +02:00
|
|
|
|
|
1999-05-03 09:29:11 +02:00
|
|
|
|
switch (*c)
|
|
|
|
|
|
{
|
2009-12-14 17:38:23 +01:00
|
|
|
|
case 'R':
|
|
|
|
|
|
if (value == 15)
|
|
|
|
|
|
is_unpredictable = TRUE;
|
|
|
|
|
|
/* Fall through. */
|
2006-04-26 17:40:55 +02:00
|
|
|
|
case 'r':
|
2012-08-24 10:03:39 +02:00
|
|
|
|
case 'T':
|
|
|
|
|
|
/* We want register + 1 when decoding T. */
|
|
|
|
|
|
if (*c == 'T')
|
|
|
|
|
|
++value;
|
|
|
|
|
|
|
2009-12-17 10:52:18 +01:00
|
|
|
|
if (c[1] == 'u')
|
|
|
|
|
|
{
|
|
|
|
|
|
/* Eat the 'u' character. */
|
|
|
|
|
|
++ c;
|
|
|
|
|
|
|
|
|
|
|
|
if (u_reg == value)
|
|
|
|
|
|
is_unpredictable = TRUE;
|
|
|
|
|
|
u_reg = value;
|
|
|
|
|
|
}
|
|
|
|
|
|
if (c[1] == 'U')
|
|
|
|
|
|
{
|
|
|
|
|
|
/* Eat the 'U' character. */
|
|
|
|
|
|
++ c;
|
|
|
|
|
|
|
|
|
|
|
|
if (U_reg == value)
|
|
|
|
|
|
is_unpredictable = TRUE;
|
|
|
|
|
|
U_reg = value;
|
|
|
|
|
|
}
|
2006-04-26 17:40:55 +02:00
|
|
|
|
func (stream, "%s", arm_regnames[value]);
|
|
|
|
|
|
break;
|
|
|
|
|
|
case 'd':
|
|
|
|
|
|
func (stream, "%ld", value);
|
2009-06-29 10:08:15 +02:00
|
|
|
|
value_in_comment = value;
|
2006-04-26 17:40:55 +02:00
|
|
|
|
break;
|
|
|
|
|
|
case 'b':
|
|
|
|
|
|
func (stream, "%ld", value * 8);
|
2009-06-29 10:08:15 +02:00
|
|
|
|
value_in_comment = value * 8;
|
2006-04-26 17:40:55 +02:00
|
|
|
|
break;
|
|
|
|
|
|
case 'W':
|
|
|
|
|
|
func (stream, "%ld", value + 1);
|
2009-06-29 10:08:15 +02:00
|
|
|
|
value_in_comment = value + 1;
|
2006-04-26 17:40:55 +02:00
|
|
|
|
break;
|
|
|
|
|
|
case 'x':
|
|
|
|
|
|
func (stream, "0x%08lx", value);
|
|
|
|
|
|
|
|
|
|
|
|
/* Some SWI instructions have special
|
|
|
|
|
|
meanings. */
|
|
|
|
|
|
if ((given & 0x0fffffff) == 0x0FF00000)
|
|
|
|
|
|
func (stream, "\t; IMB");
|
|
|
|
|
|
else if ((given & 0x0fffffff) == 0x0FF00001)
|
|
|
|
|
|
func (stream, "\t; IMBRange");
|
|
|
|
|
|
break;
|
|
|
|
|
|
case 'X':
|
|
|
|
|
|
func (stream, "%01lx", value & 0xf);
|
2009-06-29 10:08:15 +02:00
|
|
|
|
value_in_comment = value;
|
1999-05-03 09:29:11 +02:00
|
|
|
|
break;
|
|
|
|
|
|
case '`':
|
|
|
|
|
|
c++;
|
2006-04-26 17:40:55 +02:00
|
|
|
|
if (value == 0)
|
1999-05-03 09:29:11 +02:00
|
|
|
|
func (stream, "%c", *c);
|
|
|
|
|
|
break;
|
|
|
|
|
|
case '\'':
|
|
|
|
|
|
c++;
|
2006-04-26 17:40:55 +02:00
|
|
|
|
if (value == ((1ul << width) - 1))
|
1999-05-03 09:29:11 +02:00
|
|
|
|
func (stream, "%c", *c);
|
|
|
|
|
|
break;
|
|
|
|
|
|
case '?':
|
2009-06-30 13:57:05 +02:00
|
|
|
|
func (stream, "%c", c[(1 << width) - (int) value]);
|
2006-04-26 17:40:55 +02:00
|
|
|
|
c += 1 << width;
|
1999-05-03 09:29:11 +02:00
|
|
|
|
break;
|
|
|
|
|
|
default:
|
|
|
|
|
|
abort ();
|
|
|
|
|
|
}
|
|
|
|
|
|
break;
|
|
|
|
|
|
|
2004-09-30 18:21:50 +02:00
|
|
|
|
case 'e':
|
|
|
|
|
|
{
|
|
|
|
|
|
int imm;
|
|
|
|
|
|
|
|
|
|
|
|
imm = (given & 0xf) | ((given & 0xfff00) >> 4);
|
|
|
|
|
|
func (stream, "%d", imm);
|
2009-06-30 13:57:05 +02:00
|
|
|
|
value_in_comment = imm;
|
2004-09-30 18:21:50 +02:00
|
|
|
|
}
|
|
|
|
|
|
break;
|
|
|
|
|
|
|
2005-03-12 19:14:05 +01:00
|
|
|
|
case 'E':
|
|
|
|
|
|
/* LSB and WIDTH fields of BFI or BFC. The machine-
|
|
|
|
|
|
language instruction encodes LSB and MSB. */
|
|
|
|
|
|
{
|
|
|
|
|
|
long msb = (given & 0x001f0000) >> 16;
|
|
|
|
|
|
long lsb = (given & 0x00000f80) >> 7;
|
2009-12-11 14:42:17 +01:00
|
|
|
|
long w = msb - lsb + 1;
|
2009-06-30 13:57:05 +02:00
|
|
|
|
|
2009-12-11 14:42:17 +01:00
|
|
|
|
if (w > 0)
|
|
|
|
|
|
func (stream, "#%lu, #%lu", lsb, w);
|
2005-03-12 19:14:05 +01:00
|
|
|
|
else
|
|
|
|
|
|
func (stream, "(invalid: %lu:%lu)", lsb, msb);
|
|
|
|
|
|
}
|
|
|
|
|
|
break;
|
|
|
|
|
|
|
2010-09-23 17:52:19 +02:00
|
|
|
|
case 'R':
|
|
|
|
|
|
/* Get the PSR/banked register name. */
|
|
|
|
|
|
{
|
|
|
|
|
|
const char * name;
|
|
|
|
|
|
unsigned sysm = (given & 0x004f0000) >> 16;
|
|
|
|
|
|
|
|
|
|
|
|
sysm |= (given & 0x300) >> 4;
|
|
|
|
|
|
name = banked_regname (sysm);
|
|
|
|
|
|
|
|
|
|
|
|
if (name != NULL)
|
|
|
|
|
|
func (stream, "%s", name);
|
|
|
|
|
|
else
|
2012-07-24 14:56:47 +02:00
|
|
|
|
func (stream, "(UNDEF: %lu)", (unsigned long) sysm);
|
2010-09-23 17:52:19 +02:00
|
|
|
|
}
|
|
|
|
|
|
break;
|
|
|
|
|
|
|
2005-03-12 19:14:05 +01:00
|
|
|
|
case 'V':
|
|
|
|
|
|
/* 16-bit unsigned immediate from a MOVT or MOVW
|
|
|
|
|
|
instruction, encoded in bits 0:11 and 15:19. */
|
|
|
|
|
|
{
|
|
|
|
|
|
long hi = (given & 0x000f0000) >> 4;
|
|
|
|
|
|
long lo = (given & 0x00000fff);
|
|
|
|
|
|
long imm16 = hi | lo;
|
2009-06-30 13:57:05 +02:00
|
|
|
|
|
|
|
|
|
|
func (stream, "#%lu", imm16);
|
|
|
|
|
|
value_in_comment = imm16;
|
2005-03-12 19:14:05 +01:00
|
|
|
|
}
|
|
|
|
|
|
break;
|
|
|
|
|
|
|
1999-05-03 09:29:11 +02:00
|
|
|
|
default:
|
|
|
|
|
|
abort ();
|
|
|
|
|
|
}
|
|
|
|
|
|
}
|
|
|
|
|
|
}
|
|
|
|
|
|
else
|
|
|
|
|
|
func (stream, "%c", *c);
|
|
|
|
|
|
}
|
2009-06-29 10:08:15 +02:00
|
|
|
|
|
|
|
|
|
|
if (value_in_comment > 32 || value_in_comment < -16)
|
2009-07-10 18:58:54 +02:00
|
|
|
|
func (stream, "\t; 0x%lx", (value_in_comment & 0xffffffffUL));
|
2009-12-14 17:38:23 +01:00
|
|
|
|
|
|
|
|
|
|
if (is_unpredictable)
|
|
|
|
|
|
func (stream, UNPREDICTABLE_INSTRUCTION);
|
2009-12-17 10:52:18 +01:00
|
|
|
|
|
2005-06-08 00:16:52 +02:00
|
|
|
|
return;
|
1999-05-03 09:29:11 +02:00
|
|
|
|
}
|
|
|
|
|
|
}
|
|
|
|
|
|
abort ();
|
|
|
|
|
|
}
|
|
|
|
|
|
|
2005-06-08 00:16:52 +02:00
|
|
|
|
/* Print one 16-bit Thumb instruction from PC on INFO->STREAM. */
|
2002-05-23 14:48:23 +02:00
|
|
|
|
|
2005-06-08 00:16:52 +02:00
|
|
|
|
static void
|
|
|
|
|
|
print_insn_thumb16 (bfd_vma pc, struct disassemble_info *info, long given)
|
1999-05-03 09:29:11 +02:00
|
|
|
|
{
|
opcodes:
* arm-opc.h: Delete; fold contents into ...
* arm-dis.c: ... here. Move includes of internal COFF headers
next to includes of internal ELF headers.
(streq, WORD_ADDRESS, BDISP, BDISP23): Delete, unused.
(struct arm_opcode): Rename struct opcode32. Make 'assembler' const.
(struct thumb_opcode): Rename struct opcode16. Make 'assembler' const.
(arm_conditional, arm_fp_const, arm_shift, arm_regname, regnames)
(iwmmxt_wwnames, iwmmxt_wwssnames):
Make const.
(regnames): Remove iWMMXt coprocessor register sets.
(iwmmxt_regnames, iwmmxt_cregnames): New statics.
(get_arm_regnames): Adjust fourth argument to match above changes.
(set_iwmmxt_regnames): Delete.
(print_insn_arm): Constify 'c'. Use ISO syntax for function
pointer calls. Expand sole use of BDISP. Use iwmmxt_regnames
and iwmmxt_cregnames, not set_iwmmxt_regnames.
(print_insn_thumb16, print_insn_thumb32): Constify 'c'. Use
ISO syntax for function pointer calls.
include:
* dis-asm.h (get_arm_regnames): Update prototype.
2005-06-08 19:27:41 +02:00
|
|
|
|
const struct opcode16 *insn;
|
2002-12-02 14:13:37 +01:00
|
|
|
|
void *stream = info->stream;
|
|
|
|
|
|
fprintf_ftype func = info->fprintf_func;
|
1999-05-03 09:29:11 +02:00
|
|
|
|
|
|
|
|
|
|
for (insn = thumb_opcodes; insn->assembler; insn++)
|
include/elf:
* arm.h: Import complete list of official relocation names
and numbers from AAELF. Define FAKE_RELOCs for old names.
Remove a few old names no longer used anywhere.
bfd:
* elf32-arm.c: Wherever possible, use official reloc names
from AAELF.
(elf32_arm_howto_table, elf32_arm_tls_gd32_howto)
(elf32_arm_tls_ldo32_howto, elf32_arm_tls_ldm32_howto)
(elf32_arm_tls_le32_howto, elf32_arm_tls_ie32_howto)
(elf32_arm_vtinherit_howto, elf32_arm_vtentry_howto)
(elf32_arm_pc11_howto, elf32_arm_thm_pc9_howto, elf32_arm_got_prel)
(elf32_arm_r_howto): Replace with elf32_arm_howto_table_1,
elf32_arm_howto_table_2, and elf32_arm_howto_table_3.
Add many new relocations from AAELF.
(elf32_arm_howto_from_type): Update to match.
(elf32_arm_reloc_map): Add entries for R_ARM_THM_JUMP24,
R_ARM_THM_JUMP11, R_ARM_THM_JUMP19, R_ARM_THM_JUMP8,
R_ARM_THM_JUMP6, R_ARM_GNU_VTINHERIT, and R_ARM_GNU_VTENTRY.
(elf32_arm_reloc_type_lookup): Use elf32_arm_howto_from_type.
(elf32_arm_final_link_relocate): Add support for
R_ARM_THM_JUMP24, R_ARM_THM_JUMP19, R_ARM_THM_JUMP6. Remove
case entries redundant with default.
* reloc.c: Reorganize ARM relocations. Add Thumb
assembler-internal relocations BFD_RELOC_ARM_T32_OFFSET_U8,
BFD_RELOC_ARM_T32_OFFSET_IMM, BFD_RELOC_ARM_T32_IMMEDIATE.
Add visible relocations BFD_RELOC_THUMB_PCREL_BRANCH7,
BFD_RELOC_THUMB_BRANCH20, BFD_RELOC_THUMB_BRANCH25.
Delete unused relocations BFD_RELOC_ARM_GOT12, BFD_RELOC_ARM_COPY.
* bfd-in2.h, libbfd.h: Regenerate.
opcodes:
* arm-dis.c (thumb_opcodes): Add disassembly for V6T2 16-bit
instructions. Adjust disassembly of some opcodes to match
unified syntax.
(thumb32_opcodes): New table.
(print_insn_thumb): Rename print_insn_thumb16; don't handle
two-halfword branches here.
(print_insn_thumb32): New function.
(print_insn): Choose among print_insn_arm, print_insn_thumb16,
and print_insn_thumb32. Be consistent about order of
halfwords when printing 32-bit instructions.
gas:
* hash.c (hash_lookup): Add len parameter. All callers changed.
(hash_find_n): New interface.
* hash.h: Prototype hash_find_n.
* sb.c: Include as.h.
(scrub_from_sb, sb_to_scrub, scrub_position): New statics.
(sb_scrub_and_add_sb): New interface.
* sb.h: Prototype sb_scrub_and_add_sb.
* input-scrub.c (input_scrub_include_sb): Use sb_scrub_and_add_sb.
* config/tc-arm.h (TC_FORCE_RELOCATION_LOCAL): Remove
reference to BFD_RELOC_ARM_GOT12 which is never generated.
* config/tc-arm.c: Rewrite, adding Thumb-2 support.
gas/testsuite:
* gas/arm/arm.exp: Convert all existing "gas_test" tests to
"run_dump_test" tests. Run more tests unconditionally. Run new tests.
* gas/arm/arch4t.s, gas/arm/arch6zk.s, gas/arm/arm3.s, gas/arm/arm6.s
* gas/arm/arm7dm.s, gas/arm/bignum1.s, gas/arm/float.s
* gas/arm/immed.s, gas/arm/iwmmxt.s, gas/arm/offset.s, gas/arm/thumb.s:
Adjust to work as a dump test.
* gas/arm/arch4t.d, gas/arm/arch6zk.d, gas/arm/arm3.d, gas/arm/arm6.d
* gas/arm/arm7dm.d, gas/arm/bignum1.d, gas/arm/float.d
* gas/arm/immed.d, gas/arm/iwmmxt.d, gas/arm/offset.d, gas/arm/thumb.d:
New files.
* gas/arm/armv1-bad.l, gas/arm/armv1-bad.s: Remove tests for
diagnostics that don't happen in the first pass anymore.
* gas/arm/iwmmxt-bad.l, gas/arm/r15-bad.l, gas/arm/req.l
* gas/arm/vfp-bad.l:
Update expected diagnostics.
* gas/arm/pic.d: Update expected reloc name.
* gas/arm/thumbv6.d: CPY no longer appears in disassembly.
* gas/arm/r15-bad.s: Avoid two-argument mul.
* gas/arm/req.s: Adjust comments.
* gas/arm/maverick.d, gas/arm/maverick.s: Avoid inappropriate
use of PC.
* gas/arm/macro-1.d, gas/arm/macro1.s
* gas/arm/t16-bad.l, gas/arm/t16-bad.s
* gas/arm/tcompat.d, gas/arm/tcompat.s
* gas/arm/tcompat2.d, gas/arm/tcompat2.s
* gas/arm/thumb32.d, gas/arm/thumb32.s
New test pair.
ld/testsuite:
* ld-arm/mixed-app.d: Adjust expected disassembly a little.
2005-05-18 07:40:12 +02:00
|
|
|
|
if ((given & insn->mask) == insn->value)
|
|
|
|
|
|
{
|
2009-06-29 10:08:15 +02:00
|
|
|
|
signed long value_in_comment = 0;
|
opcodes:
* arm-opc.h: Delete; fold contents into ...
* arm-dis.c: ... here. Move includes of internal COFF headers
next to includes of internal ELF headers.
(streq, WORD_ADDRESS, BDISP, BDISP23): Delete, unused.
(struct arm_opcode): Rename struct opcode32. Make 'assembler' const.
(struct thumb_opcode): Rename struct opcode16. Make 'assembler' const.
(arm_conditional, arm_fp_const, arm_shift, arm_regname, regnames)
(iwmmxt_wwnames, iwmmxt_wwssnames):
Make const.
(regnames): Remove iWMMXt coprocessor register sets.
(iwmmxt_regnames, iwmmxt_cregnames): New statics.
(get_arm_regnames): Adjust fourth argument to match above changes.
(set_iwmmxt_regnames): Delete.
(print_insn_arm): Constify 'c'. Use ISO syntax for function
pointer calls. Expand sole use of BDISP. Use iwmmxt_regnames
and iwmmxt_cregnames, not set_iwmmxt_regnames.
(print_insn_thumb16, print_insn_thumb32): Constify 'c'. Use
ISO syntax for function pointer calls.
include:
* dis-asm.h (get_arm_regnames): Update prototype.
2005-06-08 19:27:41 +02:00
|
|
|
|
const char *c = insn->assembler;
|
2009-06-29 10:08:15 +02:00
|
|
|
|
|
include/elf:
* arm.h: Import complete list of official relocation names
and numbers from AAELF. Define FAKE_RELOCs for old names.
Remove a few old names no longer used anywhere.
bfd:
* elf32-arm.c: Wherever possible, use official reloc names
from AAELF.
(elf32_arm_howto_table, elf32_arm_tls_gd32_howto)
(elf32_arm_tls_ldo32_howto, elf32_arm_tls_ldm32_howto)
(elf32_arm_tls_le32_howto, elf32_arm_tls_ie32_howto)
(elf32_arm_vtinherit_howto, elf32_arm_vtentry_howto)
(elf32_arm_pc11_howto, elf32_arm_thm_pc9_howto, elf32_arm_got_prel)
(elf32_arm_r_howto): Replace with elf32_arm_howto_table_1,
elf32_arm_howto_table_2, and elf32_arm_howto_table_3.
Add many new relocations from AAELF.
(elf32_arm_howto_from_type): Update to match.
(elf32_arm_reloc_map): Add entries for R_ARM_THM_JUMP24,
R_ARM_THM_JUMP11, R_ARM_THM_JUMP19, R_ARM_THM_JUMP8,
R_ARM_THM_JUMP6, R_ARM_GNU_VTINHERIT, and R_ARM_GNU_VTENTRY.
(elf32_arm_reloc_type_lookup): Use elf32_arm_howto_from_type.
(elf32_arm_final_link_relocate): Add support for
R_ARM_THM_JUMP24, R_ARM_THM_JUMP19, R_ARM_THM_JUMP6. Remove
case entries redundant with default.
* reloc.c: Reorganize ARM relocations. Add Thumb
assembler-internal relocations BFD_RELOC_ARM_T32_OFFSET_U8,
BFD_RELOC_ARM_T32_OFFSET_IMM, BFD_RELOC_ARM_T32_IMMEDIATE.
Add visible relocations BFD_RELOC_THUMB_PCREL_BRANCH7,
BFD_RELOC_THUMB_BRANCH20, BFD_RELOC_THUMB_BRANCH25.
Delete unused relocations BFD_RELOC_ARM_GOT12, BFD_RELOC_ARM_COPY.
* bfd-in2.h, libbfd.h: Regenerate.
opcodes:
* arm-dis.c (thumb_opcodes): Add disassembly for V6T2 16-bit
instructions. Adjust disassembly of some opcodes to match
unified syntax.
(thumb32_opcodes): New table.
(print_insn_thumb): Rename print_insn_thumb16; don't handle
two-halfword branches here.
(print_insn_thumb32): New function.
(print_insn): Choose among print_insn_arm, print_insn_thumb16,
and print_insn_thumb32. Be consistent about order of
halfwords when printing 32-bit instructions.
gas:
* hash.c (hash_lookup): Add len parameter. All callers changed.
(hash_find_n): New interface.
* hash.h: Prototype hash_find_n.
* sb.c: Include as.h.
(scrub_from_sb, sb_to_scrub, scrub_position): New statics.
(sb_scrub_and_add_sb): New interface.
* sb.h: Prototype sb_scrub_and_add_sb.
* input-scrub.c (input_scrub_include_sb): Use sb_scrub_and_add_sb.
* config/tc-arm.h (TC_FORCE_RELOCATION_LOCAL): Remove
reference to BFD_RELOC_ARM_GOT12 which is never generated.
* config/tc-arm.c: Rewrite, adding Thumb-2 support.
gas/testsuite:
* gas/arm/arm.exp: Convert all existing "gas_test" tests to
"run_dump_test" tests. Run more tests unconditionally. Run new tests.
* gas/arm/arch4t.s, gas/arm/arch6zk.s, gas/arm/arm3.s, gas/arm/arm6.s
* gas/arm/arm7dm.s, gas/arm/bignum1.s, gas/arm/float.s
* gas/arm/immed.s, gas/arm/iwmmxt.s, gas/arm/offset.s, gas/arm/thumb.s:
Adjust to work as a dump test.
* gas/arm/arch4t.d, gas/arm/arch6zk.d, gas/arm/arm3.d, gas/arm/arm6.d
* gas/arm/arm7dm.d, gas/arm/bignum1.d, gas/arm/float.d
* gas/arm/immed.d, gas/arm/iwmmxt.d, gas/arm/offset.d, gas/arm/thumb.d:
New files.
* gas/arm/armv1-bad.l, gas/arm/armv1-bad.s: Remove tests for
diagnostics that don't happen in the first pass anymore.
* gas/arm/iwmmxt-bad.l, gas/arm/r15-bad.l, gas/arm/req.l
* gas/arm/vfp-bad.l:
Update expected diagnostics.
* gas/arm/pic.d: Update expected reloc name.
* gas/arm/thumbv6.d: CPY no longer appears in disassembly.
* gas/arm/r15-bad.s: Avoid two-argument mul.
* gas/arm/req.s: Adjust comments.
* gas/arm/maverick.d, gas/arm/maverick.s: Avoid inappropriate
use of PC.
* gas/arm/macro-1.d, gas/arm/macro1.s
* gas/arm/t16-bad.l, gas/arm/t16-bad.s
* gas/arm/tcompat.d, gas/arm/tcompat.s
* gas/arm/tcompat2.d, gas/arm/tcompat2.s
* gas/arm/thumb32.d, gas/arm/thumb32.s
New test pair.
ld/testsuite:
* ld-arm/mixed-app.d: Adjust expected disassembly a little.
2005-05-18 07:40:12 +02:00
|
|
|
|
for (; *c; c++)
|
|
|
|
|
|
{
|
|
|
|
|
|
int domaskpc = 0;
|
|
|
|
|
|
int domasklr = 0;
|
|
|
|
|
|
|
|
|
|
|
|
if (*c != '%')
|
|
|
|
|
|
{
|
|
|
|
|
|
func (stream, "%c", *c);
|
|
|
|
|
|
continue;
|
|
|
|
|
|
}
|
1999-05-03 09:29:11 +02:00
|
|
|
|
|
include/elf:
* arm.h: Import complete list of official relocation names
and numbers from AAELF. Define FAKE_RELOCs for old names.
Remove a few old names no longer used anywhere.
bfd:
* elf32-arm.c: Wherever possible, use official reloc names
from AAELF.
(elf32_arm_howto_table, elf32_arm_tls_gd32_howto)
(elf32_arm_tls_ldo32_howto, elf32_arm_tls_ldm32_howto)
(elf32_arm_tls_le32_howto, elf32_arm_tls_ie32_howto)
(elf32_arm_vtinherit_howto, elf32_arm_vtentry_howto)
(elf32_arm_pc11_howto, elf32_arm_thm_pc9_howto, elf32_arm_got_prel)
(elf32_arm_r_howto): Replace with elf32_arm_howto_table_1,
elf32_arm_howto_table_2, and elf32_arm_howto_table_3.
Add many new relocations from AAELF.
(elf32_arm_howto_from_type): Update to match.
(elf32_arm_reloc_map): Add entries for R_ARM_THM_JUMP24,
R_ARM_THM_JUMP11, R_ARM_THM_JUMP19, R_ARM_THM_JUMP8,
R_ARM_THM_JUMP6, R_ARM_GNU_VTINHERIT, and R_ARM_GNU_VTENTRY.
(elf32_arm_reloc_type_lookup): Use elf32_arm_howto_from_type.
(elf32_arm_final_link_relocate): Add support for
R_ARM_THM_JUMP24, R_ARM_THM_JUMP19, R_ARM_THM_JUMP6. Remove
case entries redundant with default.
* reloc.c: Reorganize ARM relocations. Add Thumb
assembler-internal relocations BFD_RELOC_ARM_T32_OFFSET_U8,
BFD_RELOC_ARM_T32_OFFSET_IMM, BFD_RELOC_ARM_T32_IMMEDIATE.
Add visible relocations BFD_RELOC_THUMB_PCREL_BRANCH7,
BFD_RELOC_THUMB_BRANCH20, BFD_RELOC_THUMB_BRANCH25.
Delete unused relocations BFD_RELOC_ARM_GOT12, BFD_RELOC_ARM_COPY.
* bfd-in2.h, libbfd.h: Regenerate.
opcodes:
* arm-dis.c (thumb_opcodes): Add disassembly for V6T2 16-bit
instructions. Adjust disassembly of some opcodes to match
unified syntax.
(thumb32_opcodes): New table.
(print_insn_thumb): Rename print_insn_thumb16; don't handle
two-halfword branches here.
(print_insn_thumb32): New function.
(print_insn): Choose among print_insn_arm, print_insn_thumb16,
and print_insn_thumb32. Be consistent about order of
halfwords when printing 32-bit instructions.
gas:
* hash.c (hash_lookup): Add len parameter. All callers changed.
(hash_find_n): New interface.
* hash.h: Prototype hash_find_n.
* sb.c: Include as.h.
(scrub_from_sb, sb_to_scrub, scrub_position): New statics.
(sb_scrub_and_add_sb): New interface.
* sb.h: Prototype sb_scrub_and_add_sb.
* input-scrub.c (input_scrub_include_sb): Use sb_scrub_and_add_sb.
* config/tc-arm.h (TC_FORCE_RELOCATION_LOCAL): Remove
reference to BFD_RELOC_ARM_GOT12 which is never generated.
* config/tc-arm.c: Rewrite, adding Thumb-2 support.
gas/testsuite:
* gas/arm/arm.exp: Convert all existing "gas_test" tests to
"run_dump_test" tests. Run more tests unconditionally. Run new tests.
* gas/arm/arch4t.s, gas/arm/arch6zk.s, gas/arm/arm3.s, gas/arm/arm6.s
* gas/arm/arm7dm.s, gas/arm/bignum1.s, gas/arm/float.s
* gas/arm/immed.s, gas/arm/iwmmxt.s, gas/arm/offset.s, gas/arm/thumb.s:
Adjust to work as a dump test.
* gas/arm/arch4t.d, gas/arm/arch6zk.d, gas/arm/arm3.d, gas/arm/arm6.d
* gas/arm/arm7dm.d, gas/arm/bignum1.d, gas/arm/float.d
* gas/arm/immed.d, gas/arm/iwmmxt.d, gas/arm/offset.d, gas/arm/thumb.d:
New files.
* gas/arm/armv1-bad.l, gas/arm/armv1-bad.s: Remove tests for
diagnostics that don't happen in the first pass anymore.
* gas/arm/iwmmxt-bad.l, gas/arm/r15-bad.l, gas/arm/req.l
* gas/arm/vfp-bad.l:
Update expected diagnostics.
* gas/arm/pic.d: Update expected reloc name.
* gas/arm/thumbv6.d: CPY no longer appears in disassembly.
* gas/arm/r15-bad.s: Avoid two-argument mul.
* gas/arm/req.s: Adjust comments.
* gas/arm/maverick.d, gas/arm/maverick.s: Avoid inappropriate
use of PC.
* gas/arm/macro-1.d, gas/arm/macro1.s
* gas/arm/t16-bad.l, gas/arm/t16-bad.s
* gas/arm/tcompat.d, gas/arm/tcompat.s
* gas/arm/tcompat2.d, gas/arm/tcompat2.s
* gas/arm/thumb32.d, gas/arm/thumb32.s
New test pair.
ld/testsuite:
* ld-arm/mixed-app.d: Adjust expected disassembly a little.
2005-05-18 07:40:12 +02:00
|
|
|
|
switch (*++c)
|
|
|
|
|
|
{
|
|
|
|
|
|
case '%':
|
|
|
|
|
|
func (stream, "%%");
|
|
|
|
|
|
break;
|
2002-11-30 09:39:46 +01:00
|
|
|
|
|
2006-06-07 16:08:19 +02:00
|
|
|
|
case 'c':
|
|
|
|
|
|
if (ifthen_state)
|
|
|
|
|
|
func (stream, "%s", arm_conditional[IFTHEN_COND]);
|
|
|
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
|
|
case 'C':
|
|
|
|
|
|
if (ifthen_state)
|
|
|
|
|
|
func (stream, "%s", arm_conditional[IFTHEN_COND]);
|
|
|
|
|
|
else
|
|
|
|
|
|
func (stream, "s");
|
|
|
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
|
|
case 'I':
|
|
|
|
|
|
{
|
|
|
|
|
|
unsigned int tmp;
|
|
|
|
|
|
|
|
|
|
|
|
ifthen_next_state = given & 0xff;
|
|
|
|
|
|
for (tmp = given << 1; tmp & 0xf; tmp <<= 1)
|
|
|
|
|
|
func (stream, ((given ^ tmp) & 0x10) ? "e" : "t");
|
|
|
|
|
|
func (stream, "\t%s", arm_conditional[(given >> 4) & 0xf]);
|
|
|
|
|
|
}
|
|
|
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
|
|
case 'x':
|
|
|
|
|
|
if (ifthen_next_state)
|
|
|
|
|
|
func (stream, "\t; unpredictable branch in IT block\n");
|
|
|
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
|
|
case 'X':
|
|
|
|
|
|
if (ifthen_state)
|
|
|
|
|
|
func (stream, "\t; unpredictable <IT:%s>",
|
|
|
|
|
|
arm_conditional[IFTHEN_COND]);
|
|
|
|
|
|
break;
|
|
|
|
|
|
|
include/elf:
* arm.h: Import complete list of official relocation names
and numbers from AAELF. Define FAKE_RELOCs for old names.
Remove a few old names no longer used anywhere.
bfd:
* elf32-arm.c: Wherever possible, use official reloc names
from AAELF.
(elf32_arm_howto_table, elf32_arm_tls_gd32_howto)
(elf32_arm_tls_ldo32_howto, elf32_arm_tls_ldm32_howto)
(elf32_arm_tls_le32_howto, elf32_arm_tls_ie32_howto)
(elf32_arm_vtinherit_howto, elf32_arm_vtentry_howto)
(elf32_arm_pc11_howto, elf32_arm_thm_pc9_howto, elf32_arm_got_prel)
(elf32_arm_r_howto): Replace with elf32_arm_howto_table_1,
elf32_arm_howto_table_2, and elf32_arm_howto_table_3.
Add many new relocations from AAELF.
(elf32_arm_howto_from_type): Update to match.
(elf32_arm_reloc_map): Add entries for R_ARM_THM_JUMP24,
R_ARM_THM_JUMP11, R_ARM_THM_JUMP19, R_ARM_THM_JUMP8,
R_ARM_THM_JUMP6, R_ARM_GNU_VTINHERIT, and R_ARM_GNU_VTENTRY.
(elf32_arm_reloc_type_lookup): Use elf32_arm_howto_from_type.
(elf32_arm_final_link_relocate): Add support for
R_ARM_THM_JUMP24, R_ARM_THM_JUMP19, R_ARM_THM_JUMP6. Remove
case entries redundant with default.
* reloc.c: Reorganize ARM relocations. Add Thumb
assembler-internal relocations BFD_RELOC_ARM_T32_OFFSET_U8,
BFD_RELOC_ARM_T32_OFFSET_IMM, BFD_RELOC_ARM_T32_IMMEDIATE.
Add visible relocations BFD_RELOC_THUMB_PCREL_BRANCH7,
BFD_RELOC_THUMB_BRANCH20, BFD_RELOC_THUMB_BRANCH25.
Delete unused relocations BFD_RELOC_ARM_GOT12, BFD_RELOC_ARM_COPY.
* bfd-in2.h, libbfd.h: Regenerate.
opcodes:
* arm-dis.c (thumb_opcodes): Add disassembly for V6T2 16-bit
instructions. Adjust disassembly of some opcodes to match
unified syntax.
(thumb32_opcodes): New table.
(print_insn_thumb): Rename print_insn_thumb16; don't handle
two-halfword branches here.
(print_insn_thumb32): New function.
(print_insn): Choose among print_insn_arm, print_insn_thumb16,
and print_insn_thumb32. Be consistent about order of
halfwords when printing 32-bit instructions.
gas:
* hash.c (hash_lookup): Add len parameter. All callers changed.
(hash_find_n): New interface.
* hash.h: Prototype hash_find_n.
* sb.c: Include as.h.
(scrub_from_sb, sb_to_scrub, scrub_position): New statics.
(sb_scrub_and_add_sb): New interface.
* sb.h: Prototype sb_scrub_and_add_sb.
* input-scrub.c (input_scrub_include_sb): Use sb_scrub_and_add_sb.
* config/tc-arm.h (TC_FORCE_RELOCATION_LOCAL): Remove
reference to BFD_RELOC_ARM_GOT12 which is never generated.
* config/tc-arm.c: Rewrite, adding Thumb-2 support.
gas/testsuite:
* gas/arm/arm.exp: Convert all existing "gas_test" tests to
"run_dump_test" tests. Run more tests unconditionally. Run new tests.
* gas/arm/arch4t.s, gas/arm/arch6zk.s, gas/arm/arm3.s, gas/arm/arm6.s
* gas/arm/arm7dm.s, gas/arm/bignum1.s, gas/arm/float.s
* gas/arm/immed.s, gas/arm/iwmmxt.s, gas/arm/offset.s, gas/arm/thumb.s:
Adjust to work as a dump test.
* gas/arm/arch4t.d, gas/arm/arch6zk.d, gas/arm/arm3.d, gas/arm/arm6.d
* gas/arm/arm7dm.d, gas/arm/bignum1.d, gas/arm/float.d
* gas/arm/immed.d, gas/arm/iwmmxt.d, gas/arm/offset.d, gas/arm/thumb.d:
New files.
* gas/arm/armv1-bad.l, gas/arm/armv1-bad.s: Remove tests for
diagnostics that don't happen in the first pass anymore.
* gas/arm/iwmmxt-bad.l, gas/arm/r15-bad.l, gas/arm/req.l
* gas/arm/vfp-bad.l:
Update expected diagnostics.
* gas/arm/pic.d: Update expected reloc name.
* gas/arm/thumbv6.d: CPY no longer appears in disassembly.
* gas/arm/r15-bad.s: Avoid two-argument mul.
* gas/arm/req.s: Adjust comments.
* gas/arm/maverick.d, gas/arm/maverick.s: Avoid inappropriate
use of PC.
* gas/arm/macro-1.d, gas/arm/macro1.s
* gas/arm/t16-bad.l, gas/arm/t16-bad.s
* gas/arm/tcompat.d, gas/arm/tcompat.s
* gas/arm/tcompat2.d, gas/arm/tcompat2.s
* gas/arm/thumb32.d, gas/arm/thumb32.s
New test pair.
ld/testsuite:
* ld-arm/mixed-app.d: Adjust expected disassembly a little.
2005-05-18 07:40:12 +02:00
|
|
|
|
case 'S':
|
|
|
|
|
|
{
|
|
|
|
|
|
long reg;
|
|
|
|
|
|
|
|
|
|
|
|
reg = (given >> 3) & 0x7;
|
|
|
|
|
|
if (given & (1 << 6))
|
|
|
|
|
|
reg += 8;
|
2001-03-06 23:33:47 +01:00
|
|
|
|
|
include/elf:
* arm.h: Import complete list of official relocation names
and numbers from AAELF. Define FAKE_RELOCs for old names.
Remove a few old names no longer used anywhere.
bfd:
* elf32-arm.c: Wherever possible, use official reloc names
from AAELF.
(elf32_arm_howto_table, elf32_arm_tls_gd32_howto)
(elf32_arm_tls_ldo32_howto, elf32_arm_tls_ldm32_howto)
(elf32_arm_tls_le32_howto, elf32_arm_tls_ie32_howto)
(elf32_arm_vtinherit_howto, elf32_arm_vtentry_howto)
(elf32_arm_pc11_howto, elf32_arm_thm_pc9_howto, elf32_arm_got_prel)
(elf32_arm_r_howto): Replace with elf32_arm_howto_table_1,
elf32_arm_howto_table_2, and elf32_arm_howto_table_3.
Add many new relocations from AAELF.
(elf32_arm_howto_from_type): Update to match.
(elf32_arm_reloc_map): Add entries for R_ARM_THM_JUMP24,
R_ARM_THM_JUMP11, R_ARM_THM_JUMP19, R_ARM_THM_JUMP8,
R_ARM_THM_JUMP6, R_ARM_GNU_VTINHERIT, and R_ARM_GNU_VTENTRY.
(elf32_arm_reloc_type_lookup): Use elf32_arm_howto_from_type.
(elf32_arm_final_link_relocate): Add support for
R_ARM_THM_JUMP24, R_ARM_THM_JUMP19, R_ARM_THM_JUMP6. Remove
case entries redundant with default.
* reloc.c: Reorganize ARM relocations. Add Thumb
assembler-internal relocations BFD_RELOC_ARM_T32_OFFSET_U8,
BFD_RELOC_ARM_T32_OFFSET_IMM, BFD_RELOC_ARM_T32_IMMEDIATE.
Add visible relocations BFD_RELOC_THUMB_PCREL_BRANCH7,
BFD_RELOC_THUMB_BRANCH20, BFD_RELOC_THUMB_BRANCH25.
Delete unused relocations BFD_RELOC_ARM_GOT12, BFD_RELOC_ARM_COPY.
* bfd-in2.h, libbfd.h: Regenerate.
opcodes:
* arm-dis.c (thumb_opcodes): Add disassembly for V6T2 16-bit
instructions. Adjust disassembly of some opcodes to match
unified syntax.
(thumb32_opcodes): New table.
(print_insn_thumb): Rename print_insn_thumb16; don't handle
two-halfword branches here.
(print_insn_thumb32): New function.
(print_insn): Choose among print_insn_arm, print_insn_thumb16,
and print_insn_thumb32. Be consistent about order of
halfwords when printing 32-bit instructions.
gas:
* hash.c (hash_lookup): Add len parameter. All callers changed.
(hash_find_n): New interface.
* hash.h: Prototype hash_find_n.
* sb.c: Include as.h.
(scrub_from_sb, sb_to_scrub, scrub_position): New statics.
(sb_scrub_and_add_sb): New interface.
* sb.h: Prototype sb_scrub_and_add_sb.
* input-scrub.c (input_scrub_include_sb): Use sb_scrub_and_add_sb.
* config/tc-arm.h (TC_FORCE_RELOCATION_LOCAL): Remove
reference to BFD_RELOC_ARM_GOT12 which is never generated.
* config/tc-arm.c: Rewrite, adding Thumb-2 support.
gas/testsuite:
* gas/arm/arm.exp: Convert all existing "gas_test" tests to
"run_dump_test" tests. Run more tests unconditionally. Run new tests.
* gas/arm/arch4t.s, gas/arm/arch6zk.s, gas/arm/arm3.s, gas/arm/arm6.s
* gas/arm/arm7dm.s, gas/arm/bignum1.s, gas/arm/float.s
* gas/arm/immed.s, gas/arm/iwmmxt.s, gas/arm/offset.s, gas/arm/thumb.s:
Adjust to work as a dump test.
* gas/arm/arch4t.d, gas/arm/arch6zk.d, gas/arm/arm3.d, gas/arm/arm6.d
* gas/arm/arm7dm.d, gas/arm/bignum1.d, gas/arm/float.d
* gas/arm/immed.d, gas/arm/iwmmxt.d, gas/arm/offset.d, gas/arm/thumb.d:
New files.
* gas/arm/armv1-bad.l, gas/arm/armv1-bad.s: Remove tests for
diagnostics that don't happen in the first pass anymore.
* gas/arm/iwmmxt-bad.l, gas/arm/r15-bad.l, gas/arm/req.l
* gas/arm/vfp-bad.l:
Update expected diagnostics.
* gas/arm/pic.d: Update expected reloc name.
* gas/arm/thumbv6.d: CPY no longer appears in disassembly.
* gas/arm/r15-bad.s: Avoid two-argument mul.
* gas/arm/req.s: Adjust comments.
* gas/arm/maverick.d, gas/arm/maverick.s: Avoid inappropriate
use of PC.
* gas/arm/macro-1.d, gas/arm/macro1.s
* gas/arm/t16-bad.l, gas/arm/t16-bad.s
* gas/arm/tcompat.d, gas/arm/tcompat.s
* gas/arm/tcompat2.d, gas/arm/tcompat2.s
* gas/arm/thumb32.d, gas/arm/thumb32.s
New test pair.
ld/testsuite:
* ld-arm/mixed-app.d: Adjust expected disassembly a little.
2005-05-18 07:40:12 +02:00
|
|
|
|
func (stream, "%s", arm_regnames[reg]);
|
|
|
|
|
|
}
|
|
|
|
|
|
break;
|
2002-05-23 14:48:23 +02:00
|
|
|
|
|
include/elf:
* arm.h: Import complete list of official relocation names
and numbers from AAELF. Define FAKE_RELOCs for old names.
Remove a few old names no longer used anywhere.
bfd:
* elf32-arm.c: Wherever possible, use official reloc names
from AAELF.
(elf32_arm_howto_table, elf32_arm_tls_gd32_howto)
(elf32_arm_tls_ldo32_howto, elf32_arm_tls_ldm32_howto)
(elf32_arm_tls_le32_howto, elf32_arm_tls_ie32_howto)
(elf32_arm_vtinherit_howto, elf32_arm_vtentry_howto)
(elf32_arm_pc11_howto, elf32_arm_thm_pc9_howto, elf32_arm_got_prel)
(elf32_arm_r_howto): Replace with elf32_arm_howto_table_1,
elf32_arm_howto_table_2, and elf32_arm_howto_table_3.
Add many new relocations from AAELF.
(elf32_arm_howto_from_type): Update to match.
(elf32_arm_reloc_map): Add entries for R_ARM_THM_JUMP24,
R_ARM_THM_JUMP11, R_ARM_THM_JUMP19, R_ARM_THM_JUMP8,
R_ARM_THM_JUMP6, R_ARM_GNU_VTINHERIT, and R_ARM_GNU_VTENTRY.
(elf32_arm_reloc_type_lookup): Use elf32_arm_howto_from_type.
(elf32_arm_final_link_relocate): Add support for
R_ARM_THM_JUMP24, R_ARM_THM_JUMP19, R_ARM_THM_JUMP6. Remove
case entries redundant with default.
* reloc.c: Reorganize ARM relocations. Add Thumb
assembler-internal relocations BFD_RELOC_ARM_T32_OFFSET_U8,
BFD_RELOC_ARM_T32_OFFSET_IMM, BFD_RELOC_ARM_T32_IMMEDIATE.
Add visible relocations BFD_RELOC_THUMB_PCREL_BRANCH7,
BFD_RELOC_THUMB_BRANCH20, BFD_RELOC_THUMB_BRANCH25.
Delete unused relocations BFD_RELOC_ARM_GOT12, BFD_RELOC_ARM_COPY.
* bfd-in2.h, libbfd.h: Regenerate.
opcodes:
* arm-dis.c (thumb_opcodes): Add disassembly for V6T2 16-bit
instructions. Adjust disassembly of some opcodes to match
unified syntax.
(thumb32_opcodes): New table.
(print_insn_thumb): Rename print_insn_thumb16; don't handle
two-halfword branches here.
(print_insn_thumb32): New function.
(print_insn): Choose among print_insn_arm, print_insn_thumb16,
and print_insn_thumb32. Be consistent about order of
halfwords when printing 32-bit instructions.
gas:
* hash.c (hash_lookup): Add len parameter. All callers changed.
(hash_find_n): New interface.
* hash.h: Prototype hash_find_n.
* sb.c: Include as.h.
(scrub_from_sb, sb_to_scrub, scrub_position): New statics.
(sb_scrub_and_add_sb): New interface.
* sb.h: Prototype sb_scrub_and_add_sb.
* input-scrub.c (input_scrub_include_sb): Use sb_scrub_and_add_sb.
* config/tc-arm.h (TC_FORCE_RELOCATION_LOCAL): Remove
reference to BFD_RELOC_ARM_GOT12 which is never generated.
* config/tc-arm.c: Rewrite, adding Thumb-2 support.
gas/testsuite:
* gas/arm/arm.exp: Convert all existing "gas_test" tests to
"run_dump_test" tests. Run more tests unconditionally. Run new tests.
* gas/arm/arch4t.s, gas/arm/arch6zk.s, gas/arm/arm3.s, gas/arm/arm6.s
* gas/arm/arm7dm.s, gas/arm/bignum1.s, gas/arm/float.s
* gas/arm/immed.s, gas/arm/iwmmxt.s, gas/arm/offset.s, gas/arm/thumb.s:
Adjust to work as a dump test.
* gas/arm/arch4t.d, gas/arm/arch6zk.d, gas/arm/arm3.d, gas/arm/arm6.d
* gas/arm/arm7dm.d, gas/arm/bignum1.d, gas/arm/float.d
* gas/arm/immed.d, gas/arm/iwmmxt.d, gas/arm/offset.d, gas/arm/thumb.d:
New files.
* gas/arm/armv1-bad.l, gas/arm/armv1-bad.s: Remove tests for
diagnostics that don't happen in the first pass anymore.
* gas/arm/iwmmxt-bad.l, gas/arm/r15-bad.l, gas/arm/req.l
* gas/arm/vfp-bad.l:
Update expected diagnostics.
* gas/arm/pic.d: Update expected reloc name.
* gas/arm/thumbv6.d: CPY no longer appears in disassembly.
* gas/arm/r15-bad.s: Avoid two-argument mul.
* gas/arm/req.s: Adjust comments.
* gas/arm/maverick.d, gas/arm/maverick.s: Avoid inappropriate
use of PC.
* gas/arm/macro-1.d, gas/arm/macro1.s
* gas/arm/t16-bad.l, gas/arm/t16-bad.s
* gas/arm/tcompat.d, gas/arm/tcompat.s
* gas/arm/tcompat2.d, gas/arm/tcompat2.s
* gas/arm/thumb32.d, gas/arm/thumb32.s
New test pair.
ld/testsuite:
* ld-arm/mixed-app.d: Adjust expected disassembly a little.
2005-05-18 07:40:12 +02:00
|
|
|
|
case 'D':
|
2001-03-06 23:33:47 +01:00
|
|
|
|
{
|
include/elf:
* arm.h: Import complete list of official relocation names
and numbers from AAELF. Define FAKE_RELOCs for old names.
Remove a few old names no longer used anywhere.
bfd:
* elf32-arm.c: Wherever possible, use official reloc names
from AAELF.
(elf32_arm_howto_table, elf32_arm_tls_gd32_howto)
(elf32_arm_tls_ldo32_howto, elf32_arm_tls_ldm32_howto)
(elf32_arm_tls_le32_howto, elf32_arm_tls_ie32_howto)
(elf32_arm_vtinherit_howto, elf32_arm_vtentry_howto)
(elf32_arm_pc11_howto, elf32_arm_thm_pc9_howto, elf32_arm_got_prel)
(elf32_arm_r_howto): Replace with elf32_arm_howto_table_1,
elf32_arm_howto_table_2, and elf32_arm_howto_table_3.
Add many new relocations from AAELF.
(elf32_arm_howto_from_type): Update to match.
(elf32_arm_reloc_map): Add entries for R_ARM_THM_JUMP24,
R_ARM_THM_JUMP11, R_ARM_THM_JUMP19, R_ARM_THM_JUMP8,
R_ARM_THM_JUMP6, R_ARM_GNU_VTINHERIT, and R_ARM_GNU_VTENTRY.
(elf32_arm_reloc_type_lookup): Use elf32_arm_howto_from_type.
(elf32_arm_final_link_relocate): Add support for
R_ARM_THM_JUMP24, R_ARM_THM_JUMP19, R_ARM_THM_JUMP6. Remove
case entries redundant with default.
* reloc.c: Reorganize ARM relocations. Add Thumb
assembler-internal relocations BFD_RELOC_ARM_T32_OFFSET_U8,
BFD_RELOC_ARM_T32_OFFSET_IMM, BFD_RELOC_ARM_T32_IMMEDIATE.
Add visible relocations BFD_RELOC_THUMB_PCREL_BRANCH7,
BFD_RELOC_THUMB_BRANCH20, BFD_RELOC_THUMB_BRANCH25.
Delete unused relocations BFD_RELOC_ARM_GOT12, BFD_RELOC_ARM_COPY.
* bfd-in2.h, libbfd.h: Regenerate.
opcodes:
* arm-dis.c (thumb_opcodes): Add disassembly for V6T2 16-bit
instructions. Adjust disassembly of some opcodes to match
unified syntax.
(thumb32_opcodes): New table.
(print_insn_thumb): Rename print_insn_thumb16; don't handle
two-halfword branches here.
(print_insn_thumb32): New function.
(print_insn): Choose among print_insn_arm, print_insn_thumb16,
and print_insn_thumb32. Be consistent about order of
halfwords when printing 32-bit instructions.
gas:
* hash.c (hash_lookup): Add len parameter. All callers changed.
(hash_find_n): New interface.
* hash.h: Prototype hash_find_n.
* sb.c: Include as.h.
(scrub_from_sb, sb_to_scrub, scrub_position): New statics.
(sb_scrub_and_add_sb): New interface.
* sb.h: Prototype sb_scrub_and_add_sb.
* input-scrub.c (input_scrub_include_sb): Use sb_scrub_and_add_sb.
* config/tc-arm.h (TC_FORCE_RELOCATION_LOCAL): Remove
reference to BFD_RELOC_ARM_GOT12 which is never generated.
* config/tc-arm.c: Rewrite, adding Thumb-2 support.
gas/testsuite:
* gas/arm/arm.exp: Convert all existing "gas_test" tests to
"run_dump_test" tests. Run more tests unconditionally. Run new tests.
* gas/arm/arch4t.s, gas/arm/arch6zk.s, gas/arm/arm3.s, gas/arm/arm6.s
* gas/arm/arm7dm.s, gas/arm/bignum1.s, gas/arm/float.s
* gas/arm/immed.s, gas/arm/iwmmxt.s, gas/arm/offset.s, gas/arm/thumb.s:
Adjust to work as a dump test.
* gas/arm/arch4t.d, gas/arm/arch6zk.d, gas/arm/arm3.d, gas/arm/arm6.d
* gas/arm/arm7dm.d, gas/arm/bignum1.d, gas/arm/float.d
* gas/arm/immed.d, gas/arm/iwmmxt.d, gas/arm/offset.d, gas/arm/thumb.d:
New files.
* gas/arm/armv1-bad.l, gas/arm/armv1-bad.s: Remove tests for
diagnostics that don't happen in the first pass anymore.
* gas/arm/iwmmxt-bad.l, gas/arm/r15-bad.l, gas/arm/req.l
* gas/arm/vfp-bad.l:
Update expected diagnostics.
* gas/arm/pic.d: Update expected reloc name.
* gas/arm/thumbv6.d: CPY no longer appears in disassembly.
* gas/arm/r15-bad.s: Avoid two-argument mul.
* gas/arm/req.s: Adjust comments.
* gas/arm/maverick.d, gas/arm/maverick.s: Avoid inappropriate
use of PC.
* gas/arm/macro-1.d, gas/arm/macro1.s
* gas/arm/t16-bad.l, gas/arm/t16-bad.s
* gas/arm/tcompat.d, gas/arm/tcompat.s
* gas/arm/tcompat2.d, gas/arm/tcompat2.s
* gas/arm/thumb32.d, gas/arm/thumb32.s
New test pair.
ld/testsuite:
* ld-arm/mixed-app.d: Adjust expected disassembly a little.
2005-05-18 07:40:12 +02:00
|
|
|
|
long reg;
|
|
|
|
|
|
|
|
|
|
|
|
reg = given & 0x7;
|
|
|
|
|
|
if (given & (1 << 7))
|
|
|
|
|
|
reg += 8;
|
|
|
|
|
|
|
|
|
|
|
|
func (stream, "%s", arm_regnames[reg]);
|
2001-03-06 23:33:47 +01:00
|
|
|
|
}
|
include/elf:
* arm.h: Import complete list of official relocation names
and numbers from AAELF. Define FAKE_RELOCs for old names.
Remove a few old names no longer used anywhere.
bfd:
* elf32-arm.c: Wherever possible, use official reloc names
from AAELF.
(elf32_arm_howto_table, elf32_arm_tls_gd32_howto)
(elf32_arm_tls_ldo32_howto, elf32_arm_tls_ldm32_howto)
(elf32_arm_tls_le32_howto, elf32_arm_tls_ie32_howto)
(elf32_arm_vtinherit_howto, elf32_arm_vtentry_howto)
(elf32_arm_pc11_howto, elf32_arm_thm_pc9_howto, elf32_arm_got_prel)
(elf32_arm_r_howto): Replace with elf32_arm_howto_table_1,
elf32_arm_howto_table_2, and elf32_arm_howto_table_3.
Add many new relocations from AAELF.
(elf32_arm_howto_from_type): Update to match.
(elf32_arm_reloc_map): Add entries for R_ARM_THM_JUMP24,
R_ARM_THM_JUMP11, R_ARM_THM_JUMP19, R_ARM_THM_JUMP8,
R_ARM_THM_JUMP6, R_ARM_GNU_VTINHERIT, and R_ARM_GNU_VTENTRY.
(elf32_arm_reloc_type_lookup): Use elf32_arm_howto_from_type.
(elf32_arm_final_link_relocate): Add support for
R_ARM_THM_JUMP24, R_ARM_THM_JUMP19, R_ARM_THM_JUMP6. Remove
case entries redundant with default.
* reloc.c: Reorganize ARM relocations. Add Thumb
assembler-internal relocations BFD_RELOC_ARM_T32_OFFSET_U8,
BFD_RELOC_ARM_T32_OFFSET_IMM, BFD_RELOC_ARM_T32_IMMEDIATE.
Add visible relocations BFD_RELOC_THUMB_PCREL_BRANCH7,
BFD_RELOC_THUMB_BRANCH20, BFD_RELOC_THUMB_BRANCH25.
Delete unused relocations BFD_RELOC_ARM_GOT12, BFD_RELOC_ARM_COPY.
* bfd-in2.h, libbfd.h: Regenerate.
opcodes:
* arm-dis.c (thumb_opcodes): Add disassembly for V6T2 16-bit
instructions. Adjust disassembly of some opcodes to match
unified syntax.
(thumb32_opcodes): New table.
(print_insn_thumb): Rename print_insn_thumb16; don't handle
two-halfword branches here.
(print_insn_thumb32): New function.
(print_insn): Choose among print_insn_arm, print_insn_thumb16,
and print_insn_thumb32. Be consistent about order of
halfwords when printing 32-bit instructions.
gas:
* hash.c (hash_lookup): Add len parameter. All callers changed.
(hash_find_n): New interface.
* hash.h: Prototype hash_find_n.
* sb.c: Include as.h.
(scrub_from_sb, sb_to_scrub, scrub_position): New statics.
(sb_scrub_and_add_sb): New interface.
* sb.h: Prototype sb_scrub_and_add_sb.
* input-scrub.c (input_scrub_include_sb): Use sb_scrub_and_add_sb.
* config/tc-arm.h (TC_FORCE_RELOCATION_LOCAL): Remove
reference to BFD_RELOC_ARM_GOT12 which is never generated.
* config/tc-arm.c: Rewrite, adding Thumb-2 support.
gas/testsuite:
* gas/arm/arm.exp: Convert all existing "gas_test" tests to
"run_dump_test" tests. Run more tests unconditionally. Run new tests.
* gas/arm/arch4t.s, gas/arm/arch6zk.s, gas/arm/arm3.s, gas/arm/arm6.s
* gas/arm/arm7dm.s, gas/arm/bignum1.s, gas/arm/float.s
* gas/arm/immed.s, gas/arm/iwmmxt.s, gas/arm/offset.s, gas/arm/thumb.s:
Adjust to work as a dump test.
* gas/arm/arch4t.d, gas/arm/arch6zk.d, gas/arm/arm3.d, gas/arm/arm6.d
* gas/arm/arm7dm.d, gas/arm/bignum1.d, gas/arm/float.d
* gas/arm/immed.d, gas/arm/iwmmxt.d, gas/arm/offset.d, gas/arm/thumb.d:
New files.
* gas/arm/armv1-bad.l, gas/arm/armv1-bad.s: Remove tests for
diagnostics that don't happen in the first pass anymore.
* gas/arm/iwmmxt-bad.l, gas/arm/r15-bad.l, gas/arm/req.l
* gas/arm/vfp-bad.l:
Update expected diagnostics.
* gas/arm/pic.d: Update expected reloc name.
* gas/arm/thumbv6.d: CPY no longer appears in disassembly.
* gas/arm/r15-bad.s: Avoid two-argument mul.
* gas/arm/req.s: Adjust comments.
* gas/arm/maverick.d, gas/arm/maverick.s: Avoid inappropriate
use of PC.
* gas/arm/macro-1.d, gas/arm/macro1.s
* gas/arm/t16-bad.l, gas/arm/t16-bad.s
* gas/arm/tcompat.d, gas/arm/tcompat.s
* gas/arm/tcompat2.d, gas/arm/tcompat2.s
* gas/arm/thumb32.d, gas/arm/thumb32.s
New test pair.
ld/testsuite:
* ld-arm/mixed-app.d: Adjust expected disassembly a little.
2005-05-18 07:40:12 +02:00
|
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
|
|
case 'N':
|
|
|
|
|
|
if (given & (1 << 8))
|
|
|
|
|
|
domasklr = 1;
|
|
|
|
|
|
/* Fall through. */
|
|
|
|
|
|
case 'O':
|
|
|
|
|
|
if (*c == 'O' && (given & (1 << 8)))
|
|
|
|
|
|
domaskpc = 1;
|
|
|
|
|
|
/* Fall through. */
|
|
|
|
|
|
case 'M':
|
|
|
|
|
|
{
|
|
|
|
|
|
int started = 0;
|
|
|
|
|
|
int reg;
|
|
|
|
|
|
|
|
|
|
|
|
func (stream, "{");
|
|
|
|
|
|
|
|
|
|
|
|
/* It would be nice if we could spot
|
|
|
|
|
|
ranges, and generate the rS-rE format: */
|
|
|
|
|
|
for (reg = 0; (reg < 8); reg++)
|
|
|
|
|
|
if ((given & (1 << reg)) != 0)
|
|
|
|
|
|
{
|
|
|
|
|
|
if (started)
|
|
|
|
|
|
func (stream, ", ");
|
|
|
|
|
|
started = 1;
|
|
|
|
|
|
func (stream, "%s", arm_regnames[reg]);
|
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
if (domasklr)
|
|
|
|
|
|
{
|
|
|
|
|
|
if (started)
|
|
|
|
|
|
func (stream, ", ");
|
|
|
|
|
|
started = 1;
|
2012-07-24 14:56:47 +02:00
|
|
|
|
func (stream, "%s", arm_regnames[14] /* "lr" */);
|
include/elf:
* arm.h: Import complete list of official relocation names
and numbers from AAELF. Define FAKE_RELOCs for old names.
Remove a few old names no longer used anywhere.
bfd:
* elf32-arm.c: Wherever possible, use official reloc names
from AAELF.
(elf32_arm_howto_table, elf32_arm_tls_gd32_howto)
(elf32_arm_tls_ldo32_howto, elf32_arm_tls_ldm32_howto)
(elf32_arm_tls_le32_howto, elf32_arm_tls_ie32_howto)
(elf32_arm_vtinherit_howto, elf32_arm_vtentry_howto)
(elf32_arm_pc11_howto, elf32_arm_thm_pc9_howto, elf32_arm_got_prel)
(elf32_arm_r_howto): Replace with elf32_arm_howto_table_1,
elf32_arm_howto_table_2, and elf32_arm_howto_table_3.
Add many new relocations from AAELF.
(elf32_arm_howto_from_type): Update to match.
(elf32_arm_reloc_map): Add entries for R_ARM_THM_JUMP24,
R_ARM_THM_JUMP11, R_ARM_THM_JUMP19, R_ARM_THM_JUMP8,
R_ARM_THM_JUMP6, R_ARM_GNU_VTINHERIT, and R_ARM_GNU_VTENTRY.
(elf32_arm_reloc_type_lookup): Use elf32_arm_howto_from_type.
(elf32_arm_final_link_relocate): Add support for
R_ARM_THM_JUMP24, R_ARM_THM_JUMP19, R_ARM_THM_JUMP6. Remove
case entries redundant with default.
* reloc.c: Reorganize ARM relocations. Add Thumb
assembler-internal relocations BFD_RELOC_ARM_T32_OFFSET_U8,
BFD_RELOC_ARM_T32_OFFSET_IMM, BFD_RELOC_ARM_T32_IMMEDIATE.
Add visible relocations BFD_RELOC_THUMB_PCREL_BRANCH7,
BFD_RELOC_THUMB_BRANCH20, BFD_RELOC_THUMB_BRANCH25.
Delete unused relocations BFD_RELOC_ARM_GOT12, BFD_RELOC_ARM_COPY.
* bfd-in2.h, libbfd.h: Regenerate.
opcodes:
* arm-dis.c (thumb_opcodes): Add disassembly for V6T2 16-bit
instructions. Adjust disassembly of some opcodes to match
unified syntax.
(thumb32_opcodes): New table.
(print_insn_thumb): Rename print_insn_thumb16; don't handle
two-halfword branches here.
(print_insn_thumb32): New function.
(print_insn): Choose among print_insn_arm, print_insn_thumb16,
and print_insn_thumb32. Be consistent about order of
halfwords when printing 32-bit instructions.
gas:
* hash.c (hash_lookup): Add len parameter. All callers changed.
(hash_find_n): New interface.
* hash.h: Prototype hash_find_n.
* sb.c: Include as.h.
(scrub_from_sb, sb_to_scrub, scrub_position): New statics.
(sb_scrub_and_add_sb): New interface.
* sb.h: Prototype sb_scrub_and_add_sb.
* input-scrub.c (input_scrub_include_sb): Use sb_scrub_and_add_sb.
* config/tc-arm.h (TC_FORCE_RELOCATION_LOCAL): Remove
reference to BFD_RELOC_ARM_GOT12 which is never generated.
* config/tc-arm.c: Rewrite, adding Thumb-2 support.
gas/testsuite:
* gas/arm/arm.exp: Convert all existing "gas_test" tests to
"run_dump_test" tests. Run more tests unconditionally. Run new tests.
* gas/arm/arch4t.s, gas/arm/arch6zk.s, gas/arm/arm3.s, gas/arm/arm6.s
* gas/arm/arm7dm.s, gas/arm/bignum1.s, gas/arm/float.s
* gas/arm/immed.s, gas/arm/iwmmxt.s, gas/arm/offset.s, gas/arm/thumb.s:
Adjust to work as a dump test.
* gas/arm/arch4t.d, gas/arm/arch6zk.d, gas/arm/arm3.d, gas/arm/arm6.d
* gas/arm/arm7dm.d, gas/arm/bignum1.d, gas/arm/float.d
* gas/arm/immed.d, gas/arm/iwmmxt.d, gas/arm/offset.d, gas/arm/thumb.d:
New files.
* gas/arm/armv1-bad.l, gas/arm/armv1-bad.s: Remove tests for
diagnostics that don't happen in the first pass anymore.
* gas/arm/iwmmxt-bad.l, gas/arm/r15-bad.l, gas/arm/req.l
* gas/arm/vfp-bad.l:
Update expected diagnostics.
* gas/arm/pic.d: Update expected reloc name.
* gas/arm/thumbv6.d: CPY no longer appears in disassembly.
* gas/arm/r15-bad.s: Avoid two-argument mul.
* gas/arm/req.s: Adjust comments.
* gas/arm/maverick.d, gas/arm/maverick.s: Avoid inappropriate
use of PC.
* gas/arm/macro-1.d, gas/arm/macro1.s
* gas/arm/t16-bad.l, gas/arm/t16-bad.s
* gas/arm/tcompat.d, gas/arm/tcompat.s
* gas/arm/tcompat2.d, gas/arm/tcompat2.s
* gas/arm/thumb32.d, gas/arm/thumb32.s
New test pair.
ld/testsuite:
* ld-arm/mixed-app.d: Adjust expected disassembly a little.
2005-05-18 07:40:12 +02:00
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
if (domaskpc)
|
|
|
|
|
|
{
|
|
|
|
|
|
if (started)
|
|
|
|
|
|
func (stream, ", ");
|
2012-07-24 14:56:47 +02:00
|
|
|
|
func (stream, "%s", arm_regnames[15] /* "pc" */);
|
include/elf:
* arm.h: Import complete list of official relocation names
and numbers from AAELF. Define FAKE_RELOCs for old names.
Remove a few old names no longer used anywhere.
bfd:
* elf32-arm.c: Wherever possible, use official reloc names
from AAELF.
(elf32_arm_howto_table, elf32_arm_tls_gd32_howto)
(elf32_arm_tls_ldo32_howto, elf32_arm_tls_ldm32_howto)
(elf32_arm_tls_le32_howto, elf32_arm_tls_ie32_howto)
(elf32_arm_vtinherit_howto, elf32_arm_vtentry_howto)
(elf32_arm_pc11_howto, elf32_arm_thm_pc9_howto, elf32_arm_got_prel)
(elf32_arm_r_howto): Replace with elf32_arm_howto_table_1,
elf32_arm_howto_table_2, and elf32_arm_howto_table_3.
Add many new relocations from AAELF.
(elf32_arm_howto_from_type): Update to match.
(elf32_arm_reloc_map): Add entries for R_ARM_THM_JUMP24,
R_ARM_THM_JUMP11, R_ARM_THM_JUMP19, R_ARM_THM_JUMP8,
R_ARM_THM_JUMP6, R_ARM_GNU_VTINHERIT, and R_ARM_GNU_VTENTRY.
(elf32_arm_reloc_type_lookup): Use elf32_arm_howto_from_type.
(elf32_arm_final_link_relocate): Add support for
R_ARM_THM_JUMP24, R_ARM_THM_JUMP19, R_ARM_THM_JUMP6. Remove
case entries redundant with default.
* reloc.c: Reorganize ARM relocations. Add Thumb
assembler-internal relocations BFD_RELOC_ARM_T32_OFFSET_U8,
BFD_RELOC_ARM_T32_OFFSET_IMM, BFD_RELOC_ARM_T32_IMMEDIATE.
Add visible relocations BFD_RELOC_THUMB_PCREL_BRANCH7,
BFD_RELOC_THUMB_BRANCH20, BFD_RELOC_THUMB_BRANCH25.
Delete unused relocations BFD_RELOC_ARM_GOT12, BFD_RELOC_ARM_COPY.
* bfd-in2.h, libbfd.h: Regenerate.
opcodes:
* arm-dis.c (thumb_opcodes): Add disassembly for V6T2 16-bit
instructions. Adjust disassembly of some opcodes to match
unified syntax.
(thumb32_opcodes): New table.
(print_insn_thumb): Rename print_insn_thumb16; don't handle
two-halfword branches here.
(print_insn_thumb32): New function.
(print_insn): Choose among print_insn_arm, print_insn_thumb16,
and print_insn_thumb32. Be consistent about order of
halfwords when printing 32-bit instructions.
gas:
* hash.c (hash_lookup): Add len parameter. All callers changed.
(hash_find_n): New interface.
* hash.h: Prototype hash_find_n.
* sb.c: Include as.h.
(scrub_from_sb, sb_to_scrub, scrub_position): New statics.
(sb_scrub_and_add_sb): New interface.
* sb.h: Prototype sb_scrub_and_add_sb.
* input-scrub.c (input_scrub_include_sb): Use sb_scrub_and_add_sb.
* config/tc-arm.h (TC_FORCE_RELOCATION_LOCAL): Remove
reference to BFD_RELOC_ARM_GOT12 which is never generated.
* config/tc-arm.c: Rewrite, adding Thumb-2 support.
gas/testsuite:
* gas/arm/arm.exp: Convert all existing "gas_test" tests to
"run_dump_test" tests. Run more tests unconditionally. Run new tests.
* gas/arm/arch4t.s, gas/arm/arch6zk.s, gas/arm/arm3.s, gas/arm/arm6.s
* gas/arm/arm7dm.s, gas/arm/bignum1.s, gas/arm/float.s
* gas/arm/immed.s, gas/arm/iwmmxt.s, gas/arm/offset.s, gas/arm/thumb.s:
Adjust to work as a dump test.
* gas/arm/arch4t.d, gas/arm/arch6zk.d, gas/arm/arm3.d, gas/arm/arm6.d
* gas/arm/arm7dm.d, gas/arm/bignum1.d, gas/arm/float.d
* gas/arm/immed.d, gas/arm/iwmmxt.d, gas/arm/offset.d, gas/arm/thumb.d:
New files.
* gas/arm/armv1-bad.l, gas/arm/armv1-bad.s: Remove tests for
diagnostics that don't happen in the first pass anymore.
* gas/arm/iwmmxt-bad.l, gas/arm/r15-bad.l, gas/arm/req.l
* gas/arm/vfp-bad.l:
Update expected diagnostics.
* gas/arm/pic.d: Update expected reloc name.
* gas/arm/thumbv6.d: CPY no longer appears in disassembly.
* gas/arm/r15-bad.s: Avoid two-argument mul.
* gas/arm/req.s: Adjust comments.
* gas/arm/maverick.d, gas/arm/maverick.s: Avoid inappropriate
use of PC.
* gas/arm/macro-1.d, gas/arm/macro1.s
* gas/arm/t16-bad.l, gas/arm/t16-bad.s
* gas/arm/tcompat.d, gas/arm/tcompat.s
* gas/arm/tcompat2.d, gas/arm/tcompat2.s
* gas/arm/thumb32.d, gas/arm/thumb32.s
New test pair.
ld/testsuite:
* ld-arm/mixed-app.d: Adjust expected disassembly a little.
2005-05-18 07:40:12 +02:00
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
func (stream, "}");
|
|
|
|
|
|
}
|
|
|
|
|
|
break;
|
|
|
|
|
|
|
2010-05-11 19:36:33 +02:00
|
|
|
|
case 'W':
|
|
|
|
|
|
/* Print writeback indicator for a LDMIA. We are doing a
|
|
|
|
|
|
writeback if the base register is not in the register
|
|
|
|
|
|
mask. */
|
|
|
|
|
|
if ((given & (1 << ((given & 0x0700) >> 8))) == 0)
|
|
|
|
|
|
func (stream, "!");
|
|
|
|
|
|
break;
|
|
|
|
|
|
|
include/elf:
* arm.h: Import complete list of official relocation names
and numbers from AAELF. Define FAKE_RELOCs for old names.
Remove a few old names no longer used anywhere.
bfd:
* elf32-arm.c: Wherever possible, use official reloc names
from AAELF.
(elf32_arm_howto_table, elf32_arm_tls_gd32_howto)
(elf32_arm_tls_ldo32_howto, elf32_arm_tls_ldm32_howto)
(elf32_arm_tls_le32_howto, elf32_arm_tls_ie32_howto)
(elf32_arm_vtinherit_howto, elf32_arm_vtentry_howto)
(elf32_arm_pc11_howto, elf32_arm_thm_pc9_howto, elf32_arm_got_prel)
(elf32_arm_r_howto): Replace with elf32_arm_howto_table_1,
elf32_arm_howto_table_2, and elf32_arm_howto_table_3.
Add many new relocations from AAELF.
(elf32_arm_howto_from_type): Update to match.
(elf32_arm_reloc_map): Add entries for R_ARM_THM_JUMP24,
R_ARM_THM_JUMP11, R_ARM_THM_JUMP19, R_ARM_THM_JUMP8,
R_ARM_THM_JUMP6, R_ARM_GNU_VTINHERIT, and R_ARM_GNU_VTENTRY.
(elf32_arm_reloc_type_lookup): Use elf32_arm_howto_from_type.
(elf32_arm_final_link_relocate): Add support for
R_ARM_THM_JUMP24, R_ARM_THM_JUMP19, R_ARM_THM_JUMP6. Remove
case entries redundant with default.
* reloc.c: Reorganize ARM relocations. Add Thumb
assembler-internal relocations BFD_RELOC_ARM_T32_OFFSET_U8,
BFD_RELOC_ARM_T32_OFFSET_IMM, BFD_RELOC_ARM_T32_IMMEDIATE.
Add visible relocations BFD_RELOC_THUMB_PCREL_BRANCH7,
BFD_RELOC_THUMB_BRANCH20, BFD_RELOC_THUMB_BRANCH25.
Delete unused relocations BFD_RELOC_ARM_GOT12, BFD_RELOC_ARM_COPY.
* bfd-in2.h, libbfd.h: Regenerate.
opcodes:
* arm-dis.c (thumb_opcodes): Add disassembly for V6T2 16-bit
instructions. Adjust disassembly of some opcodes to match
unified syntax.
(thumb32_opcodes): New table.
(print_insn_thumb): Rename print_insn_thumb16; don't handle
two-halfword branches here.
(print_insn_thumb32): New function.
(print_insn): Choose among print_insn_arm, print_insn_thumb16,
and print_insn_thumb32. Be consistent about order of
halfwords when printing 32-bit instructions.
gas:
* hash.c (hash_lookup): Add len parameter. All callers changed.
(hash_find_n): New interface.
* hash.h: Prototype hash_find_n.
* sb.c: Include as.h.
(scrub_from_sb, sb_to_scrub, scrub_position): New statics.
(sb_scrub_and_add_sb): New interface.
* sb.h: Prototype sb_scrub_and_add_sb.
* input-scrub.c (input_scrub_include_sb): Use sb_scrub_and_add_sb.
* config/tc-arm.h (TC_FORCE_RELOCATION_LOCAL): Remove
reference to BFD_RELOC_ARM_GOT12 which is never generated.
* config/tc-arm.c: Rewrite, adding Thumb-2 support.
gas/testsuite:
* gas/arm/arm.exp: Convert all existing "gas_test" tests to
"run_dump_test" tests. Run more tests unconditionally. Run new tests.
* gas/arm/arch4t.s, gas/arm/arch6zk.s, gas/arm/arm3.s, gas/arm/arm6.s
* gas/arm/arm7dm.s, gas/arm/bignum1.s, gas/arm/float.s
* gas/arm/immed.s, gas/arm/iwmmxt.s, gas/arm/offset.s, gas/arm/thumb.s:
Adjust to work as a dump test.
* gas/arm/arch4t.d, gas/arm/arch6zk.d, gas/arm/arm3.d, gas/arm/arm6.d
* gas/arm/arm7dm.d, gas/arm/bignum1.d, gas/arm/float.d
* gas/arm/immed.d, gas/arm/iwmmxt.d, gas/arm/offset.d, gas/arm/thumb.d:
New files.
* gas/arm/armv1-bad.l, gas/arm/armv1-bad.s: Remove tests for
diagnostics that don't happen in the first pass anymore.
* gas/arm/iwmmxt-bad.l, gas/arm/r15-bad.l, gas/arm/req.l
* gas/arm/vfp-bad.l:
Update expected diagnostics.
* gas/arm/pic.d: Update expected reloc name.
* gas/arm/thumbv6.d: CPY no longer appears in disassembly.
* gas/arm/r15-bad.s: Avoid two-argument mul.
* gas/arm/req.s: Adjust comments.
* gas/arm/maverick.d, gas/arm/maverick.s: Avoid inappropriate
use of PC.
* gas/arm/macro-1.d, gas/arm/macro1.s
* gas/arm/t16-bad.l, gas/arm/t16-bad.s
* gas/arm/tcompat.d, gas/arm/tcompat.s
* gas/arm/tcompat2.d, gas/arm/tcompat2.s
* gas/arm/thumb32.d, gas/arm/thumb32.s
New test pair.
ld/testsuite:
* ld-arm/mixed-app.d: Adjust expected disassembly a little.
2005-05-18 07:40:12 +02:00
|
|
|
|
case 'b':
|
|
|
|
|
|
/* Print ARM V6T2 CZB address: pc+4+6 bits. */
|
|
|
|
|
|
{
|
|
|
|
|
|
bfd_vma address = (pc + 4
|
|
|
|
|
|
+ ((given & 0x00f8) >> 2)
|
|
|
|
|
|
+ ((given & 0x0200) >> 3));
|
|
|
|
|
|
info->print_address_func (address, info);
|
|
|
|
|
|
}
|
|
|
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
|
|
case 's':
|
|
|
|
|
|
/* Right shift immediate -- bits 6..10; 1-31 print
|
|
|
|
|
|
as themselves, 0 prints as 32. */
|
|
|
|
|
|
{
|
|
|
|
|
|
long imm = (given & 0x07c0) >> 6;
|
|
|
|
|
|
if (imm == 0)
|
|
|
|
|
|
imm = 32;
|
Kaveh Ghazi's printf format attribute checking patch.
bfd:
* elf32-xtensa.c (vsprint_msg): Add format attribute. Fix
format bugs.
* vms.h (_bfd_vms_debug): Add format attribute.
(_bfd_vms_debug, _bfd_hexdump): Fix typos.
binutils:
* bucomm.h (report): Add format attribute.
* dlltool.c (inform): Likewise.
* dllwrap.c (display, inform, warn): Likewise.
* objdump.c (objdump_sprintf): Likewise.
* readelf.c (error, warn): Likewise. Fix format bugs.
gas:
* config/tc-tic30.c (debug): Add format attribute. Fix format
bugs.
include:
* dis-asm.h (fprintf_ftype): Add format attribute.
opcodes:
* arc-dis.c, arm-dis.c, cris-dis.c, crx-dis.c, d10v-dis.c,
d30v-dis.c, fr30-dis.c, h8300-dis.c, h8500-dis.c, i860-dis.c,
ia64-dis.c, ip2k-dis.c, m10200-dis.c, m10300-dis.c,
m88k-dis.c, mcore-dis.c, mips-dis.c, ms1-dis.c, or32-dis.c,
ppc-dis.c, sh64-dis.c, sparc-dis.c, tic4x-dis.c, tic80-dis.c,
v850-dis.c: Fix format bugs.
* ia64-gen.c (fail, warn): Add format attribute.
* or32-opc.c (debug): Likewise.
2005-07-07 21:27:52 +02:00
|
|
|
|
func (stream, "#%ld", imm);
|
include/elf:
* arm.h: Import complete list of official relocation names
and numbers from AAELF. Define FAKE_RELOCs for old names.
Remove a few old names no longer used anywhere.
bfd:
* elf32-arm.c: Wherever possible, use official reloc names
from AAELF.
(elf32_arm_howto_table, elf32_arm_tls_gd32_howto)
(elf32_arm_tls_ldo32_howto, elf32_arm_tls_ldm32_howto)
(elf32_arm_tls_le32_howto, elf32_arm_tls_ie32_howto)
(elf32_arm_vtinherit_howto, elf32_arm_vtentry_howto)
(elf32_arm_pc11_howto, elf32_arm_thm_pc9_howto, elf32_arm_got_prel)
(elf32_arm_r_howto): Replace with elf32_arm_howto_table_1,
elf32_arm_howto_table_2, and elf32_arm_howto_table_3.
Add many new relocations from AAELF.
(elf32_arm_howto_from_type): Update to match.
(elf32_arm_reloc_map): Add entries for R_ARM_THM_JUMP24,
R_ARM_THM_JUMP11, R_ARM_THM_JUMP19, R_ARM_THM_JUMP8,
R_ARM_THM_JUMP6, R_ARM_GNU_VTINHERIT, and R_ARM_GNU_VTENTRY.
(elf32_arm_reloc_type_lookup): Use elf32_arm_howto_from_type.
(elf32_arm_final_link_relocate): Add support for
R_ARM_THM_JUMP24, R_ARM_THM_JUMP19, R_ARM_THM_JUMP6. Remove
case entries redundant with default.
* reloc.c: Reorganize ARM relocations. Add Thumb
assembler-internal relocations BFD_RELOC_ARM_T32_OFFSET_U8,
BFD_RELOC_ARM_T32_OFFSET_IMM, BFD_RELOC_ARM_T32_IMMEDIATE.
Add visible relocations BFD_RELOC_THUMB_PCREL_BRANCH7,
BFD_RELOC_THUMB_BRANCH20, BFD_RELOC_THUMB_BRANCH25.
Delete unused relocations BFD_RELOC_ARM_GOT12, BFD_RELOC_ARM_COPY.
* bfd-in2.h, libbfd.h: Regenerate.
opcodes:
* arm-dis.c (thumb_opcodes): Add disassembly for V6T2 16-bit
instructions. Adjust disassembly of some opcodes to match
unified syntax.
(thumb32_opcodes): New table.
(print_insn_thumb): Rename print_insn_thumb16; don't handle
two-halfword branches here.
(print_insn_thumb32): New function.
(print_insn): Choose among print_insn_arm, print_insn_thumb16,
and print_insn_thumb32. Be consistent about order of
halfwords when printing 32-bit instructions.
gas:
* hash.c (hash_lookup): Add len parameter. All callers changed.
(hash_find_n): New interface.
* hash.h: Prototype hash_find_n.
* sb.c: Include as.h.
(scrub_from_sb, sb_to_scrub, scrub_position): New statics.
(sb_scrub_and_add_sb): New interface.
* sb.h: Prototype sb_scrub_and_add_sb.
* input-scrub.c (input_scrub_include_sb): Use sb_scrub_and_add_sb.
* config/tc-arm.h (TC_FORCE_RELOCATION_LOCAL): Remove
reference to BFD_RELOC_ARM_GOT12 which is never generated.
* config/tc-arm.c: Rewrite, adding Thumb-2 support.
gas/testsuite:
* gas/arm/arm.exp: Convert all existing "gas_test" tests to
"run_dump_test" tests. Run more tests unconditionally. Run new tests.
* gas/arm/arch4t.s, gas/arm/arch6zk.s, gas/arm/arm3.s, gas/arm/arm6.s
* gas/arm/arm7dm.s, gas/arm/bignum1.s, gas/arm/float.s
* gas/arm/immed.s, gas/arm/iwmmxt.s, gas/arm/offset.s, gas/arm/thumb.s:
Adjust to work as a dump test.
* gas/arm/arch4t.d, gas/arm/arch6zk.d, gas/arm/arm3.d, gas/arm/arm6.d
* gas/arm/arm7dm.d, gas/arm/bignum1.d, gas/arm/float.d
* gas/arm/immed.d, gas/arm/iwmmxt.d, gas/arm/offset.d, gas/arm/thumb.d:
New files.
* gas/arm/armv1-bad.l, gas/arm/armv1-bad.s: Remove tests for
diagnostics that don't happen in the first pass anymore.
* gas/arm/iwmmxt-bad.l, gas/arm/r15-bad.l, gas/arm/req.l
* gas/arm/vfp-bad.l:
Update expected diagnostics.
* gas/arm/pic.d: Update expected reloc name.
* gas/arm/thumbv6.d: CPY no longer appears in disassembly.
* gas/arm/r15-bad.s: Avoid two-argument mul.
* gas/arm/req.s: Adjust comments.
* gas/arm/maverick.d, gas/arm/maverick.s: Avoid inappropriate
use of PC.
* gas/arm/macro-1.d, gas/arm/macro1.s
* gas/arm/t16-bad.l, gas/arm/t16-bad.s
* gas/arm/tcompat.d, gas/arm/tcompat.s
* gas/arm/tcompat2.d, gas/arm/tcompat2.s
* gas/arm/thumb32.d, gas/arm/thumb32.s
New test pair.
ld/testsuite:
* ld-arm/mixed-app.d: Adjust expected disassembly a little.
2005-05-18 07:40:12 +02:00
|
|
|
|
}
|
|
|
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
|
|
case '0': case '1': case '2': case '3': case '4':
|
|
|
|
|
|
case '5': case '6': case '7': case '8': case '9':
|
|
|
|
|
|
{
|
|
|
|
|
|
int bitstart = *c++ - '0';
|
|
|
|
|
|
int bitend = 0;
|
|
|
|
|
|
|
|
|
|
|
|
while (*c >= '0' && *c <= '9')
|
|
|
|
|
|
bitstart = (bitstart * 10) + *c++ - '0';
|
|
|
|
|
|
|
|
|
|
|
|
switch (*c)
|
|
|
|
|
|
{
|
|
|
|
|
|
case '-':
|
|
|
|
|
|
{
|
2011-06-03 12:04:03 +02:00
|
|
|
|
bfd_vma reg;
|
include/elf:
* arm.h: Import complete list of official relocation names
and numbers from AAELF. Define FAKE_RELOCs for old names.
Remove a few old names no longer used anywhere.
bfd:
* elf32-arm.c: Wherever possible, use official reloc names
from AAELF.
(elf32_arm_howto_table, elf32_arm_tls_gd32_howto)
(elf32_arm_tls_ldo32_howto, elf32_arm_tls_ldm32_howto)
(elf32_arm_tls_le32_howto, elf32_arm_tls_ie32_howto)
(elf32_arm_vtinherit_howto, elf32_arm_vtentry_howto)
(elf32_arm_pc11_howto, elf32_arm_thm_pc9_howto, elf32_arm_got_prel)
(elf32_arm_r_howto): Replace with elf32_arm_howto_table_1,
elf32_arm_howto_table_2, and elf32_arm_howto_table_3.
Add many new relocations from AAELF.
(elf32_arm_howto_from_type): Update to match.
(elf32_arm_reloc_map): Add entries for R_ARM_THM_JUMP24,
R_ARM_THM_JUMP11, R_ARM_THM_JUMP19, R_ARM_THM_JUMP8,
R_ARM_THM_JUMP6, R_ARM_GNU_VTINHERIT, and R_ARM_GNU_VTENTRY.
(elf32_arm_reloc_type_lookup): Use elf32_arm_howto_from_type.
(elf32_arm_final_link_relocate): Add support for
R_ARM_THM_JUMP24, R_ARM_THM_JUMP19, R_ARM_THM_JUMP6. Remove
case entries redundant with default.
* reloc.c: Reorganize ARM relocations. Add Thumb
assembler-internal relocations BFD_RELOC_ARM_T32_OFFSET_U8,
BFD_RELOC_ARM_T32_OFFSET_IMM, BFD_RELOC_ARM_T32_IMMEDIATE.
Add visible relocations BFD_RELOC_THUMB_PCREL_BRANCH7,
BFD_RELOC_THUMB_BRANCH20, BFD_RELOC_THUMB_BRANCH25.
Delete unused relocations BFD_RELOC_ARM_GOT12, BFD_RELOC_ARM_COPY.
* bfd-in2.h, libbfd.h: Regenerate.
opcodes:
* arm-dis.c (thumb_opcodes): Add disassembly for V6T2 16-bit
instructions. Adjust disassembly of some opcodes to match
unified syntax.
(thumb32_opcodes): New table.
(print_insn_thumb): Rename print_insn_thumb16; don't handle
two-halfword branches here.
(print_insn_thumb32): New function.
(print_insn): Choose among print_insn_arm, print_insn_thumb16,
and print_insn_thumb32. Be consistent about order of
halfwords when printing 32-bit instructions.
gas:
* hash.c (hash_lookup): Add len parameter. All callers changed.
(hash_find_n): New interface.
* hash.h: Prototype hash_find_n.
* sb.c: Include as.h.
(scrub_from_sb, sb_to_scrub, scrub_position): New statics.
(sb_scrub_and_add_sb): New interface.
* sb.h: Prototype sb_scrub_and_add_sb.
* input-scrub.c (input_scrub_include_sb): Use sb_scrub_and_add_sb.
* config/tc-arm.h (TC_FORCE_RELOCATION_LOCAL): Remove
reference to BFD_RELOC_ARM_GOT12 which is never generated.
* config/tc-arm.c: Rewrite, adding Thumb-2 support.
gas/testsuite:
* gas/arm/arm.exp: Convert all existing "gas_test" tests to
"run_dump_test" tests. Run more tests unconditionally. Run new tests.
* gas/arm/arch4t.s, gas/arm/arch6zk.s, gas/arm/arm3.s, gas/arm/arm6.s
* gas/arm/arm7dm.s, gas/arm/bignum1.s, gas/arm/float.s
* gas/arm/immed.s, gas/arm/iwmmxt.s, gas/arm/offset.s, gas/arm/thumb.s:
Adjust to work as a dump test.
* gas/arm/arch4t.d, gas/arm/arch6zk.d, gas/arm/arm3.d, gas/arm/arm6.d
* gas/arm/arm7dm.d, gas/arm/bignum1.d, gas/arm/float.d
* gas/arm/immed.d, gas/arm/iwmmxt.d, gas/arm/offset.d, gas/arm/thumb.d:
New files.
* gas/arm/armv1-bad.l, gas/arm/armv1-bad.s: Remove tests for
diagnostics that don't happen in the first pass anymore.
* gas/arm/iwmmxt-bad.l, gas/arm/r15-bad.l, gas/arm/req.l
* gas/arm/vfp-bad.l:
Update expected diagnostics.
* gas/arm/pic.d: Update expected reloc name.
* gas/arm/thumbv6.d: CPY no longer appears in disassembly.
* gas/arm/r15-bad.s: Avoid two-argument mul.
* gas/arm/req.s: Adjust comments.
* gas/arm/maverick.d, gas/arm/maverick.s: Avoid inappropriate
use of PC.
* gas/arm/macro-1.d, gas/arm/macro1.s
* gas/arm/t16-bad.l, gas/arm/t16-bad.s
* gas/arm/tcompat.d, gas/arm/tcompat.s
* gas/arm/tcompat2.d, gas/arm/tcompat2.s
* gas/arm/thumb32.d, gas/arm/thumb32.s
New test pair.
ld/testsuite:
* ld-arm/mixed-app.d: Adjust expected disassembly a little.
2005-05-18 07:40:12 +02:00
|
|
|
|
|
|
|
|
|
|
c++;
|
|
|
|
|
|
while (*c >= '0' && *c <= '9')
|
|
|
|
|
|
bitend = (bitend * 10) + *c++ - '0';
|
|
|
|
|
|
if (!bitend)
|
|
|
|
|
|
abort ();
|
|
|
|
|
|
reg = given >> bitstart;
|
|
|
|
|
|
reg &= (2 << (bitend - bitstart)) - 1;
|
2009-12-17 10:52:18 +01:00
|
|
|
|
|
include/elf:
* arm.h: Import complete list of official relocation names
and numbers from AAELF. Define FAKE_RELOCs for old names.
Remove a few old names no longer used anywhere.
bfd:
* elf32-arm.c: Wherever possible, use official reloc names
from AAELF.
(elf32_arm_howto_table, elf32_arm_tls_gd32_howto)
(elf32_arm_tls_ldo32_howto, elf32_arm_tls_ldm32_howto)
(elf32_arm_tls_le32_howto, elf32_arm_tls_ie32_howto)
(elf32_arm_vtinherit_howto, elf32_arm_vtentry_howto)
(elf32_arm_pc11_howto, elf32_arm_thm_pc9_howto, elf32_arm_got_prel)
(elf32_arm_r_howto): Replace with elf32_arm_howto_table_1,
elf32_arm_howto_table_2, and elf32_arm_howto_table_3.
Add many new relocations from AAELF.
(elf32_arm_howto_from_type): Update to match.
(elf32_arm_reloc_map): Add entries for R_ARM_THM_JUMP24,
R_ARM_THM_JUMP11, R_ARM_THM_JUMP19, R_ARM_THM_JUMP8,
R_ARM_THM_JUMP6, R_ARM_GNU_VTINHERIT, and R_ARM_GNU_VTENTRY.
(elf32_arm_reloc_type_lookup): Use elf32_arm_howto_from_type.
(elf32_arm_final_link_relocate): Add support for
R_ARM_THM_JUMP24, R_ARM_THM_JUMP19, R_ARM_THM_JUMP6. Remove
case entries redundant with default.
* reloc.c: Reorganize ARM relocations. Add Thumb
assembler-internal relocations BFD_RELOC_ARM_T32_OFFSET_U8,
BFD_RELOC_ARM_T32_OFFSET_IMM, BFD_RELOC_ARM_T32_IMMEDIATE.
Add visible relocations BFD_RELOC_THUMB_PCREL_BRANCH7,
BFD_RELOC_THUMB_BRANCH20, BFD_RELOC_THUMB_BRANCH25.
Delete unused relocations BFD_RELOC_ARM_GOT12, BFD_RELOC_ARM_COPY.
* bfd-in2.h, libbfd.h: Regenerate.
opcodes:
* arm-dis.c (thumb_opcodes): Add disassembly for V6T2 16-bit
instructions. Adjust disassembly of some opcodes to match
unified syntax.
(thumb32_opcodes): New table.
(print_insn_thumb): Rename print_insn_thumb16; don't handle
two-halfword branches here.
(print_insn_thumb32): New function.
(print_insn): Choose among print_insn_arm, print_insn_thumb16,
and print_insn_thumb32. Be consistent about order of
halfwords when printing 32-bit instructions.
gas:
* hash.c (hash_lookup): Add len parameter. All callers changed.
(hash_find_n): New interface.
* hash.h: Prototype hash_find_n.
* sb.c: Include as.h.
(scrub_from_sb, sb_to_scrub, scrub_position): New statics.
(sb_scrub_and_add_sb): New interface.
* sb.h: Prototype sb_scrub_and_add_sb.
* input-scrub.c (input_scrub_include_sb): Use sb_scrub_and_add_sb.
* config/tc-arm.h (TC_FORCE_RELOCATION_LOCAL): Remove
reference to BFD_RELOC_ARM_GOT12 which is never generated.
* config/tc-arm.c: Rewrite, adding Thumb-2 support.
gas/testsuite:
* gas/arm/arm.exp: Convert all existing "gas_test" tests to
"run_dump_test" tests. Run more tests unconditionally. Run new tests.
* gas/arm/arch4t.s, gas/arm/arch6zk.s, gas/arm/arm3.s, gas/arm/arm6.s
* gas/arm/arm7dm.s, gas/arm/bignum1.s, gas/arm/float.s
* gas/arm/immed.s, gas/arm/iwmmxt.s, gas/arm/offset.s, gas/arm/thumb.s:
Adjust to work as a dump test.
* gas/arm/arch4t.d, gas/arm/arch6zk.d, gas/arm/arm3.d, gas/arm/arm6.d
* gas/arm/arm7dm.d, gas/arm/bignum1.d, gas/arm/float.d
* gas/arm/immed.d, gas/arm/iwmmxt.d, gas/arm/offset.d, gas/arm/thumb.d:
New files.
* gas/arm/armv1-bad.l, gas/arm/armv1-bad.s: Remove tests for
diagnostics that don't happen in the first pass anymore.
* gas/arm/iwmmxt-bad.l, gas/arm/r15-bad.l, gas/arm/req.l
* gas/arm/vfp-bad.l:
Update expected diagnostics.
* gas/arm/pic.d: Update expected reloc name.
* gas/arm/thumbv6.d: CPY no longer appears in disassembly.
* gas/arm/r15-bad.s: Avoid two-argument mul.
* gas/arm/req.s: Adjust comments.
* gas/arm/maverick.d, gas/arm/maverick.s: Avoid inappropriate
use of PC.
* gas/arm/macro-1.d, gas/arm/macro1.s
* gas/arm/t16-bad.l, gas/arm/t16-bad.s
* gas/arm/tcompat.d, gas/arm/tcompat.s
* gas/arm/tcompat2.d, gas/arm/tcompat2.s
* gas/arm/thumb32.d, gas/arm/thumb32.s
New test pair.
ld/testsuite:
* ld-arm/mixed-app.d: Adjust expected disassembly a little.
2005-05-18 07:40:12 +02:00
|
|
|
|
switch (*c)
|
|
|
|
|
|
{
|
|
|
|
|
|
case 'r':
|
|
|
|
|
|
func (stream, "%s", arm_regnames[reg]);
|
|
|
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
|
|
case 'd':
|
2012-07-24 14:56:47 +02:00
|
|
|
|
func (stream, "%ld", (long) reg);
|
2009-06-29 10:08:15 +02:00
|
|
|
|
value_in_comment = reg;
|
include/elf:
* arm.h: Import complete list of official relocation names
and numbers from AAELF. Define FAKE_RELOCs for old names.
Remove a few old names no longer used anywhere.
bfd:
* elf32-arm.c: Wherever possible, use official reloc names
from AAELF.
(elf32_arm_howto_table, elf32_arm_tls_gd32_howto)
(elf32_arm_tls_ldo32_howto, elf32_arm_tls_ldm32_howto)
(elf32_arm_tls_le32_howto, elf32_arm_tls_ie32_howto)
(elf32_arm_vtinherit_howto, elf32_arm_vtentry_howto)
(elf32_arm_pc11_howto, elf32_arm_thm_pc9_howto, elf32_arm_got_prel)
(elf32_arm_r_howto): Replace with elf32_arm_howto_table_1,
elf32_arm_howto_table_2, and elf32_arm_howto_table_3.
Add many new relocations from AAELF.
(elf32_arm_howto_from_type): Update to match.
(elf32_arm_reloc_map): Add entries for R_ARM_THM_JUMP24,
R_ARM_THM_JUMP11, R_ARM_THM_JUMP19, R_ARM_THM_JUMP8,
R_ARM_THM_JUMP6, R_ARM_GNU_VTINHERIT, and R_ARM_GNU_VTENTRY.
(elf32_arm_reloc_type_lookup): Use elf32_arm_howto_from_type.
(elf32_arm_final_link_relocate): Add support for
R_ARM_THM_JUMP24, R_ARM_THM_JUMP19, R_ARM_THM_JUMP6. Remove
case entries redundant with default.
* reloc.c: Reorganize ARM relocations. Add Thumb
assembler-internal relocations BFD_RELOC_ARM_T32_OFFSET_U8,
BFD_RELOC_ARM_T32_OFFSET_IMM, BFD_RELOC_ARM_T32_IMMEDIATE.
Add visible relocations BFD_RELOC_THUMB_PCREL_BRANCH7,
BFD_RELOC_THUMB_BRANCH20, BFD_RELOC_THUMB_BRANCH25.
Delete unused relocations BFD_RELOC_ARM_GOT12, BFD_RELOC_ARM_COPY.
* bfd-in2.h, libbfd.h: Regenerate.
opcodes:
* arm-dis.c (thumb_opcodes): Add disassembly for V6T2 16-bit
instructions. Adjust disassembly of some opcodes to match
unified syntax.
(thumb32_opcodes): New table.
(print_insn_thumb): Rename print_insn_thumb16; don't handle
two-halfword branches here.
(print_insn_thumb32): New function.
(print_insn): Choose among print_insn_arm, print_insn_thumb16,
and print_insn_thumb32. Be consistent about order of
halfwords when printing 32-bit instructions.
gas:
* hash.c (hash_lookup): Add len parameter. All callers changed.
(hash_find_n): New interface.
* hash.h: Prototype hash_find_n.
* sb.c: Include as.h.
(scrub_from_sb, sb_to_scrub, scrub_position): New statics.
(sb_scrub_and_add_sb): New interface.
* sb.h: Prototype sb_scrub_and_add_sb.
* input-scrub.c (input_scrub_include_sb): Use sb_scrub_and_add_sb.
* config/tc-arm.h (TC_FORCE_RELOCATION_LOCAL): Remove
reference to BFD_RELOC_ARM_GOT12 which is never generated.
* config/tc-arm.c: Rewrite, adding Thumb-2 support.
gas/testsuite:
* gas/arm/arm.exp: Convert all existing "gas_test" tests to
"run_dump_test" tests. Run more tests unconditionally. Run new tests.
* gas/arm/arch4t.s, gas/arm/arch6zk.s, gas/arm/arm3.s, gas/arm/arm6.s
* gas/arm/arm7dm.s, gas/arm/bignum1.s, gas/arm/float.s
* gas/arm/immed.s, gas/arm/iwmmxt.s, gas/arm/offset.s, gas/arm/thumb.s:
Adjust to work as a dump test.
* gas/arm/arch4t.d, gas/arm/arch6zk.d, gas/arm/arm3.d, gas/arm/arm6.d
* gas/arm/arm7dm.d, gas/arm/bignum1.d, gas/arm/float.d
* gas/arm/immed.d, gas/arm/iwmmxt.d, gas/arm/offset.d, gas/arm/thumb.d:
New files.
* gas/arm/armv1-bad.l, gas/arm/armv1-bad.s: Remove tests for
diagnostics that don't happen in the first pass anymore.
* gas/arm/iwmmxt-bad.l, gas/arm/r15-bad.l, gas/arm/req.l
* gas/arm/vfp-bad.l:
Update expected diagnostics.
* gas/arm/pic.d: Update expected reloc name.
* gas/arm/thumbv6.d: CPY no longer appears in disassembly.
* gas/arm/r15-bad.s: Avoid two-argument mul.
* gas/arm/req.s: Adjust comments.
* gas/arm/maverick.d, gas/arm/maverick.s: Avoid inappropriate
use of PC.
* gas/arm/macro-1.d, gas/arm/macro1.s
* gas/arm/t16-bad.l, gas/arm/t16-bad.s
* gas/arm/tcompat.d, gas/arm/tcompat.s
* gas/arm/tcompat2.d, gas/arm/tcompat2.s
* gas/arm/thumb32.d, gas/arm/thumb32.s
New test pair.
ld/testsuite:
* ld-arm/mixed-app.d: Adjust expected disassembly a little.
2005-05-18 07:40:12 +02:00
|
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
|
|
case 'H':
|
2012-07-24 14:56:47 +02:00
|
|
|
|
func (stream, "%ld", (long) (reg << 1));
|
2009-06-29 10:08:15 +02:00
|
|
|
|
value_in_comment = reg << 1;
|
include/elf:
* arm.h: Import complete list of official relocation names
and numbers from AAELF. Define FAKE_RELOCs for old names.
Remove a few old names no longer used anywhere.
bfd:
* elf32-arm.c: Wherever possible, use official reloc names
from AAELF.
(elf32_arm_howto_table, elf32_arm_tls_gd32_howto)
(elf32_arm_tls_ldo32_howto, elf32_arm_tls_ldm32_howto)
(elf32_arm_tls_le32_howto, elf32_arm_tls_ie32_howto)
(elf32_arm_vtinherit_howto, elf32_arm_vtentry_howto)
(elf32_arm_pc11_howto, elf32_arm_thm_pc9_howto, elf32_arm_got_prel)
(elf32_arm_r_howto): Replace with elf32_arm_howto_table_1,
elf32_arm_howto_table_2, and elf32_arm_howto_table_3.
Add many new relocations from AAELF.
(elf32_arm_howto_from_type): Update to match.
(elf32_arm_reloc_map): Add entries for R_ARM_THM_JUMP24,
R_ARM_THM_JUMP11, R_ARM_THM_JUMP19, R_ARM_THM_JUMP8,
R_ARM_THM_JUMP6, R_ARM_GNU_VTINHERIT, and R_ARM_GNU_VTENTRY.
(elf32_arm_reloc_type_lookup): Use elf32_arm_howto_from_type.
(elf32_arm_final_link_relocate): Add support for
R_ARM_THM_JUMP24, R_ARM_THM_JUMP19, R_ARM_THM_JUMP6. Remove
case entries redundant with default.
* reloc.c: Reorganize ARM relocations. Add Thumb
assembler-internal relocations BFD_RELOC_ARM_T32_OFFSET_U8,
BFD_RELOC_ARM_T32_OFFSET_IMM, BFD_RELOC_ARM_T32_IMMEDIATE.
Add visible relocations BFD_RELOC_THUMB_PCREL_BRANCH7,
BFD_RELOC_THUMB_BRANCH20, BFD_RELOC_THUMB_BRANCH25.
Delete unused relocations BFD_RELOC_ARM_GOT12, BFD_RELOC_ARM_COPY.
* bfd-in2.h, libbfd.h: Regenerate.
opcodes:
* arm-dis.c (thumb_opcodes): Add disassembly for V6T2 16-bit
instructions. Adjust disassembly of some opcodes to match
unified syntax.
(thumb32_opcodes): New table.
(print_insn_thumb): Rename print_insn_thumb16; don't handle
two-halfword branches here.
(print_insn_thumb32): New function.
(print_insn): Choose among print_insn_arm, print_insn_thumb16,
and print_insn_thumb32. Be consistent about order of
halfwords when printing 32-bit instructions.
gas:
* hash.c (hash_lookup): Add len parameter. All callers changed.
(hash_find_n): New interface.
* hash.h: Prototype hash_find_n.
* sb.c: Include as.h.
(scrub_from_sb, sb_to_scrub, scrub_position): New statics.
(sb_scrub_and_add_sb): New interface.
* sb.h: Prototype sb_scrub_and_add_sb.
* input-scrub.c (input_scrub_include_sb): Use sb_scrub_and_add_sb.
* config/tc-arm.h (TC_FORCE_RELOCATION_LOCAL): Remove
reference to BFD_RELOC_ARM_GOT12 which is never generated.
* config/tc-arm.c: Rewrite, adding Thumb-2 support.
gas/testsuite:
* gas/arm/arm.exp: Convert all existing "gas_test" tests to
"run_dump_test" tests. Run more tests unconditionally. Run new tests.
* gas/arm/arch4t.s, gas/arm/arch6zk.s, gas/arm/arm3.s, gas/arm/arm6.s
* gas/arm/arm7dm.s, gas/arm/bignum1.s, gas/arm/float.s
* gas/arm/immed.s, gas/arm/iwmmxt.s, gas/arm/offset.s, gas/arm/thumb.s:
Adjust to work as a dump test.
* gas/arm/arch4t.d, gas/arm/arch6zk.d, gas/arm/arm3.d, gas/arm/arm6.d
* gas/arm/arm7dm.d, gas/arm/bignum1.d, gas/arm/float.d
* gas/arm/immed.d, gas/arm/iwmmxt.d, gas/arm/offset.d, gas/arm/thumb.d:
New files.
* gas/arm/armv1-bad.l, gas/arm/armv1-bad.s: Remove tests for
diagnostics that don't happen in the first pass anymore.
* gas/arm/iwmmxt-bad.l, gas/arm/r15-bad.l, gas/arm/req.l
* gas/arm/vfp-bad.l:
Update expected diagnostics.
* gas/arm/pic.d: Update expected reloc name.
* gas/arm/thumbv6.d: CPY no longer appears in disassembly.
* gas/arm/r15-bad.s: Avoid two-argument mul.
* gas/arm/req.s: Adjust comments.
* gas/arm/maverick.d, gas/arm/maverick.s: Avoid inappropriate
use of PC.
* gas/arm/macro-1.d, gas/arm/macro1.s
* gas/arm/t16-bad.l, gas/arm/t16-bad.s
* gas/arm/tcompat.d, gas/arm/tcompat.s
* gas/arm/tcompat2.d, gas/arm/tcompat2.s
* gas/arm/thumb32.d, gas/arm/thumb32.s
New test pair.
ld/testsuite:
* ld-arm/mixed-app.d: Adjust expected disassembly a little.
2005-05-18 07:40:12 +02:00
|
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
|
|
case 'W':
|
2012-07-24 14:56:47 +02:00
|
|
|
|
func (stream, "%ld", (long) (reg << 2));
|
2009-06-29 10:08:15 +02:00
|
|
|
|
value_in_comment = reg << 2;
|
include/elf:
* arm.h: Import complete list of official relocation names
and numbers from AAELF. Define FAKE_RELOCs for old names.
Remove a few old names no longer used anywhere.
bfd:
* elf32-arm.c: Wherever possible, use official reloc names
from AAELF.
(elf32_arm_howto_table, elf32_arm_tls_gd32_howto)
(elf32_arm_tls_ldo32_howto, elf32_arm_tls_ldm32_howto)
(elf32_arm_tls_le32_howto, elf32_arm_tls_ie32_howto)
(elf32_arm_vtinherit_howto, elf32_arm_vtentry_howto)
(elf32_arm_pc11_howto, elf32_arm_thm_pc9_howto, elf32_arm_got_prel)
(elf32_arm_r_howto): Replace with elf32_arm_howto_table_1,
elf32_arm_howto_table_2, and elf32_arm_howto_table_3.
Add many new relocations from AAELF.
(elf32_arm_howto_from_type): Update to match.
(elf32_arm_reloc_map): Add entries for R_ARM_THM_JUMP24,
R_ARM_THM_JUMP11, R_ARM_THM_JUMP19, R_ARM_THM_JUMP8,
R_ARM_THM_JUMP6, R_ARM_GNU_VTINHERIT, and R_ARM_GNU_VTENTRY.
(elf32_arm_reloc_type_lookup): Use elf32_arm_howto_from_type.
(elf32_arm_final_link_relocate): Add support for
R_ARM_THM_JUMP24, R_ARM_THM_JUMP19, R_ARM_THM_JUMP6. Remove
case entries redundant with default.
* reloc.c: Reorganize ARM relocations. Add Thumb
assembler-internal relocations BFD_RELOC_ARM_T32_OFFSET_U8,
BFD_RELOC_ARM_T32_OFFSET_IMM, BFD_RELOC_ARM_T32_IMMEDIATE.
Add visible relocations BFD_RELOC_THUMB_PCREL_BRANCH7,
BFD_RELOC_THUMB_BRANCH20, BFD_RELOC_THUMB_BRANCH25.
Delete unused relocations BFD_RELOC_ARM_GOT12, BFD_RELOC_ARM_COPY.
* bfd-in2.h, libbfd.h: Regenerate.
opcodes:
* arm-dis.c (thumb_opcodes): Add disassembly for V6T2 16-bit
instructions. Adjust disassembly of some opcodes to match
unified syntax.
(thumb32_opcodes): New table.
(print_insn_thumb): Rename print_insn_thumb16; don't handle
two-halfword branches here.
(print_insn_thumb32): New function.
(print_insn): Choose among print_insn_arm, print_insn_thumb16,
and print_insn_thumb32. Be consistent about order of
halfwords when printing 32-bit instructions.
gas:
* hash.c (hash_lookup): Add len parameter. All callers changed.
(hash_find_n): New interface.
* hash.h: Prototype hash_find_n.
* sb.c: Include as.h.
(scrub_from_sb, sb_to_scrub, scrub_position): New statics.
(sb_scrub_and_add_sb): New interface.
* sb.h: Prototype sb_scrub_and_add_sb.
* input-scrub.c (input_scrub_include_sb): Use sb_scrub_and_add_sb.
* config/tc-arm.h (TC_FORCE_RELOCATION_LOCAL): Remove
reference to BFD_RELOC_ARM_GOT12 which is never generated.
* config/tc-arm.c: Rewrite, adding Thumb-2 support.
gas/testsuite:
* gas/arm/arm.exp: Convert all existing "gas_test" tests to
"run_dump_test" tests. Run more tests unconditionally. Run new tests.
* gas/arm/arch4t.s, gas/arm/arch6zk.s, gas/arm/arm3.s, gas/arm/arm6.s
* gas/arm/arm7dm.s, gas/arm/bignum1.s, gas/arm/float.s
* gas/arm/immed.s, gas/arm/iwmmxt.s, gas/arm/offset.s, gas/arm/thumb.s:
Adjust to work as a dump test.
* gas/arm/arch4t.d, gas/arm/arch6zk.d, gas/arm/arm3.d, gas/arm/arm6.d
* gas/arm/arm7dm.d, gas/arm/bignum1.d, gas/arm/float.d
* gas/arm/immed.d, gas/arm/iwmmxt.d, gas/arm/offset.d, gas/arm/thumb.d:
New files.
* gas/arm/armv1-bad.l, gas/arm/armv1-bad.s: Remove tests for
diagnostics that don't happen in the first pass anymore.
* gas/arm/iwmmxt-bad.l, gas/arm/r15-bad.l, gas/arm/req.l
* gas/arm/vfp-bad.l:
Update expected diagnostics.
* gas/arm/pic.d: Update expected reloc name.
* gas/arm/thumbv6.d: CPY no longer appears in disassembly.
* gas/arm/r15-bad.s: Avoid two-argument mul.
* gas/arm/req.s: Adjust comments.
* gas/arm/maverick.d, gas/arm/maverick.s: Avoid inappropriate
use of PC.
* gas/arm/macro-1.d, gas/arm/macro1.s
* gas/arm/t16-bad.l, gas/arm/t16-bad.s
* gas/arm/tcompat.d, gas/arm/tcompat.s
* gas/arm/tcompat2.d, gas/arm/tcompat2.s
* gas/arm/thumb32.d, gas/arm/thumb32.s
New test pair.
ld/testsuite:
* ld-arm/mixed-app.d: Adjust expected disassembly a little.
2005-05-18 07:40:12 +02:00
|
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
|
|
case 'a':
|
|
|
|
|
|
/* PC-relative address -- the bottom two
|
|
|
|
|
|
bits of the address are dropped
|
|
|
|
|
|
before the calculation. */
|
|
|
|
|
|
info->print_address_func
|
|
|
|
|
|
(((pc + 4) & ~3) + (reg << 2), info);
|
2009-06-29 10:08:15 +02:00
|
|
|
|
value_in_comment = 0;
|
include/elf:
* arm.h: Import complete list of official relocation names
and numbers from AAELF. Define FAKE_RELOCs for old names.
Remove a few old names no longer used anywhere.
bfd:
* elf32-arm.c: Wherever possible, use official reloc names
from AAELF.
(elf32_arm_howto_table, elf32_arm_tls_gd32_howto)
(elf32_arm_tls_ldo32_howto, elf32_arm_tls_ldm32_howto)
(elf32_arm_tls_le32_howto, elf32_arm_tls_ie32_howto)
(elf32_arm_vtinherit_howto, elf32_arm_vtentry_howto)
(elf32_arm_pc11_howto, elf32_arm_thm_pc9_howto, elf32_arm_got_prel)
(elf32_arm_r_howto): Replace with elf32_arm_howto_table_1,
elf32_arm_howto_table_2, and elf32_arm_howto_table_3.
Add many new relocations from AAELF.
(elf32_arm_howto_from_type): Update to match.
(elf32_arm_reloc_map): Add entries for R_ARM_THM_JUMP24,
R_ARM_THM_JUMP11, R_ARM_THM_JUMP19, R_ARM_THM_JUMP8,
R_ARM_THM_JUMP6, R_ARM_GNU_VTINHERIT, and R_ARM_GNU_VTENTRY.
(elf32_arm_reloc_type_lookup): Use elf32_arm_howto_from_type.
(elf32_arm_final_link_relocate): Add support for
R_ARM_THM_JUMP24, R_ARM_THM_JUMP19, R_ARM_THM_JUMP6. Remove
case entries redundant with default.
* reloc.c: Reorganize ARM relocations. Add Thumb
assembler-internal relocations BFD_RELOC_ARM_T32_OFFSET_U8,
BFD_RELOC_ARM_T32_OFFSET_IMM, BFD_RELOC_ARM_T32_IMMEDIATE.
Add visible relocations BFD_RELOC_THUMB_PCREL_BRANCH7,
BFD_RELOC_THUMB_BRANCH20, BFD_RELOC_THUMB_BRANCH25.
Delete unused relocations BFD_RELOC_ARM_GOT12, BFD_RELOC_ARM_COPY.
* bfd-in2.h, libbfd.h: Regenerate.
opcodes:
* arm-dis.c (thumb_opcodes): Add disassembly for V6T2 16-bit
instructions. Adjust disassembly of some opcodes to match
unified syntax.
(thumb32_opcodes): New table.
(print_insn_thumb): Rename print_insn_thumb16; don't handle
two-halfword branches here.
(print_insn_thumb32): New function.
(print_insn): Choose among print_insn_arm, print_insn_thumb16,
and print_insn_thumb32. Be consistent about order of
halfwords when printing 32-bit instructions.
gas:
* hash.c (hash_lookup): Add len parameter. All callers changed.
(hash_find_n): New interface.
* hash.h: Prototype hash_find_n.
* sb.c: Include as.h.
(scrub_from_sb, sb_to_scrub, scrub_position): New statics.
(sb_scrub_and_add_sb): New interface.
* sb.h: Prototype sb_scrub_and_add_sb.
* input-scrub.c (input_scrub_include_sb): Use sb_scrub_and_add_sb.
* config/tc-arm.h (TC_FORCE_RELOCATION_LOCAL): Remove
reference to BFD_RELOC_ARM_GOT12 which is never generated.
* config/tc-arm.c: Rewrite, adding Thumb-2 support.
gas/testsuite:
* gas/arm/arm.exp: Convert all existing "gas_test" tests to
"run_dump_test" tests. Run more tests unconditionally. Run new tests.
* gas/arm/arch4t.s, gas/arm/arch6zk.s, gas/arm/arm3.s, gas/arm/arm6.s
* gas/arm/arm7dm.s, gas/arm/bignum1.s, gas/arm/float.s
* gas/arm/immed.s, gas/arm/iwmmxt.s, gas/arm/offset.s, gas/arm/thumb.s:
Adjust to work as a dump test.
* gas/arm/arch4t.d, gas/arm/arch6zk.d, gas/arm/arm3.d, gas/arm/arm6.d
* gas/arm/arm7dm.d, gas/arm/bignum1.d, gas/arm/float.d
* gas/arm/immed.d, gas/arm/iwmmxt.d, gas/arm/offset.d, gas/arm/thumb.d:
New files.
* gas/arm/armv1-bad.l, gas/arm/armv1-bad.s: Remove tests for
diagnostics that don't happen in the first pass anymore.
* gas/arm/iwmmxt-bad.l, gas/arm/r15-bad.l, gas/arm/req.l
* gas/arm/vfp-bad.l:
Update expected diagnostics.
* gas/arm/pic.d: Update expected reloc name.
* gas/arm/thumbv6.d: CPY no longer appears in disassembly.
* gas/arm/r15-bad.s: Avoid two-argument mul.
* gas/arm/req.s: Adjust comments.
* gas/arm/maverick.d, gas/arm/maverick.s: Avoid inappropriate
use of PC.
* gas/arm/macro-1.d, gas/arm/macro1.s
* gas/arm/t16-bad.l, gas/arm/t16-bad.s
* gas/arm/tcompat.d, gas/arm/tcompat.s
* gas/arm/tcompat2.d, gas/arm/tcompat2.s
* gas/arm/thumb32.d, gas/arm/thumb32.s
New test pair.
ld/testsuite:
* ld-arm/mixed-app.d: Adjust expected disassembly a little.
2005-05-18 07:40:12 +02:00
|
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
|
|
case 'x':
|
2012-07-24 14:56:47 +02:00
|
|
|
|
func (stream, "0x%04lx", (long) reg);
|
include/elf:
* arm.h: Import complete list of official relocation names
and numbers from AAELF. Define FAKE_RELOCs for old names.
Remove a few old names no longer used anywhere.
bfd:
* elf32-arm.c: Wherever possible, use official reloc names
from AAELF.
(elf32_arm_howto_table, elf32_arm_tls_gd32_howto)
(elf32_arm_tls_ldo32_howto, elf32_arm_tls_ldm32_howto)
(elf32_arm_tls_le32_howto, elf32_arm_tls_ie32_howto)
(elf32_arm_vtinherit_howto, elf32_arm_vtentry_howto)
(elf32_arm_pc11_howto, elf32_arm_thm_pc9_howto, elf32_arm_got_prel)
(elf32_arm_r_howto): Replace with elf32_arm_howto_table_1,
elf32_arm_howto_table_2, and elf32_arm_howto_table_3.
Add many new relocations from AAELF.
(elf32_arm_howto_from_type): Update to match.
(elf32_arm_reloc_map): Add entries for R_ARM_THM_JUMP24,
R_ARM_THM_JUMP11, R_ARM_THM_JUMP19, R_ARM_THM_JUMP8,
R_ARM_THM_JUMP6, R_ARM_GNU_VTINHERIT, and R_ARM_GNU_VTENTRY.
(elf32_arm_reloc_type_lookup): Use elf32_arm_howto_from_type.
(elf32_arm_final_link_relocate): Add support for
R_ARM_THM_JUMP24, R_ARM_THM_JUMP19, R_ARM_THM_JUMP6. Remove
case entries redundant with default.
* reloc.c: Reorganize ARM relocations. Add Thumb
assembler-internal relocations BFD_RELOC_ARM_T32_OFFSET_U8,
BFD_RELOC_ARM_T32_OFFSET_IMM, BFD_RELOC_ARM_T32_IMMEDIATE.
Add visible relocations BFD_RELOC_THUMB_PCREL_BRANCH7,
BFD_RELOC_THUMB_BRANCH20, BFD_RELOC_THUMB_BRANCH25.
Delete unused relocations BFD_RELOC_ARM_GOT12, BFD_RELOC_ARM_COPY.
* bfd-in2.h, libbfd.h: Regenerate.
opcodes:
* arm-dis.c (thumb_opcodes): Add disassembly for V6T2 16-bit
instructions. Adjust disassembly of some opcodes to match
unified syntax.
(thumb32_opcodes): New table.
(print_insn_thumb): Rename print_insn_thumb16; don't handle
two-halfword branches here.
(print_insn_thumb32): New function.
(print_insn): Choose among print_insn_arm, print_insn_thumb16,
and print_insn_thumb32. Be consistent about order of
halfwords when printing 32-bit instructions.
gas:
* hash.c (hash_lookup): Add len parameter. All callers changed.
(hash_find_n): New interface.
* hash.h: Prototype hash_find_n.
* sb.c: Include as.h.
(scrub_from_sb, sb_to_scrub, scrub_position): New statics.
(sb_scrub_and_add_sb): New interface.
* sb.h: Prototype sb_scrub_and_add_sb.
* input-scrub.c (input_scrub_include_sb): Use sb_scrub_and_add_sb.
* config/tc-arm.h (TC_FORCE_RELOCATION_LOCAL): Remove
reference to BFD_RELOC_ARM_GOT12 which is never generated.
* config/tc-arm.c: Rewrite, adding Thumb-2 support.
gas/testsuite:
* gas/arm/arm.exp: Convert all existing "gas_test" tests to
"run_dump_test" tests. Run more tests unconditionally. Run new tests.
* gas/arm/arch4t.s, gas/arm/arch6zk.s, gas/arm/arm3.s, gas/arm/arm6.s
* gas/arm/arm7dm.s, gas/arm/bignum1.s, gas/arm/float.s
* gas/arm/immed.s, gas/arm/iwmmxt.s, gas/arm/offset.s, gas/arm/thumb.s:
Adjust to work as a dump test.
* gas/arm/arch4t.d, gas/arm/arch6zk.d, gas/arm/arm3.d, gas/arm/arm6.d
* gas/arm/arm7dm.d, gas/arm/bignum1.d, gas/arm/float.d
* gas/arm/immed.d, gas/arm/iwmmxt.d, gas/arm/offset.d, gas/arm/thumb.d:
New files.
* gas/arm/armv1-bad.l, gas/arm/armv1-bad.s: Remove tests for
diagnostics that don't happen in the first pass anymore.
* gas/arm/iwmmxt-bad.l, gas/arm/r15-bad.l, gas/arm/req.l
* gas/arm/vfp-bad.l:
Update expected diagnostics.
* gas/arm/pic.d: Update expected reloc name.
* gas/arm/thumbv6.d: CPY no longer appears in disassembly.
* gas/arm/r15-bad.s: Avoid two-argument mul.
* gas/arm/req.s: Adjust comments.
* gas/arm/maverick.d, gas/arm/maverick.s: Avoid inappropriate
use of PC.
* gas/arm/macro-1.d, gas/arm/macro1.s
* gas/arm/t16-bad.l, gas/arm/t16-bad.s
* gas/arm/tcompat.d, gas/arm/tcompat.s
* gas/arm/tcompat2.d, gas/arm/tcompat2.s
* gas/arm/thumb32.d, gas/arm/thumb32.s
New test pair.
ld/testsuite:
* ld-arm/mixed-app.d: Adjust expected disassembly a little.
2005-05-18 07:40:12 +02:00
|
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
|
|
case 'B':
|
|
|
|
|
|
reg = ((reg ^ (1 << bitend)) - (1 << bitend));
|
opcodes:
* arm-opc.h: Delete; fold contents into ...
* arm-dis.c: ... here. Move includes of internal COFF headers
next to includes of internal ELF headers.
(streq, WORD_ADDRESS, BDISP, BDISP23): Delete, unused.
(struct arm_opcode): Rename struct opcode32. Make 'assembler' const.
(struct thumb_opcode): Rename struct opcode16. Make 'assembler' const.
(arm_conditional, arm_fp_const, arm_shift, arm_regname, regnames)
(iwmmxt_wwnames, iwmmxt_wwssnames):
Make const.
(regnames): Remove iWMMXt coprocessor register sets.
(iwmmxt_regnames, iwmmxt_cregnames): New statics.
(get_arm_regnames): Adjust fourth argument to match above changes.
(set_iwmmxt_regnames): Delete.
(print_insn_arm): Constify 'c'. Use ISO syntax for function
pointer calls. Expand sole use of BDISP. Use iwmmxt_regnames
and iwmmxt_cregnames, not set_iwmmxt_regnames.
(print_insn_thumb16, print_insn_thumb32): Constify 'c'. Use
ISO syntax for function pointer calls.
include:
* dis-asm.h (get_arm_regnames): Update prototype.
2005-06-08 19:27:41 +02:00
|
|
|
|
info->print_address_func (reg * 2 + pc + 4, info);
|
2009-06-29 10:08:15 +02:00
|
|
|
|
value_in_comment = 0;
|
include/elf:
* arm.h: Import complete list of official relocation names
and numbers from AAELF. Define FAKE_RELOCs for old names.
Remove a few old names no longer used anywhere.
bfd:
* elf32-arm.c: Wherever possible, use official reloc names
from AAELF.
(elf32_arm_howto_table, elf32_arm_tls_gd32_howto)
(elf32_arm_tls_ldo32_howto, elf32_arm_tls_ldm32_howto)
(elf32_arm_tls_le32_howto, elf32_arm_tls_ie32_howto)
(elf32_arm_vtinherit_howto, elf32_arm_vtentry_howto)
(elf32_arm_pc11_howto, elf32_arm_thm_pc9_howto, elf32_arm_got_prel)
(elf32_arm_r_howto): Replace with elf32_arm_howto_table_1,
elf32_arm_howto_table_2, and elf32_arm_howto_table_3.
Add many new relocations from AAELF.
(elf32_arm_howto_from_type): Update to match.
(elf32_arm_reloc_map): Add entries for R_ARM_THM_JUMP24,
R_ARM_THM_JUMP11, R_ARM_THM_JUMP19, R_ARM_THM_JUMP8,
R_ARM_THM_JUMP6, R_ARM_GNU_VTINHERIT, and R_ARM_GNU_VTENTRY.
(elf32_arm_reloc_type_lookup): Use elf32_arm_howto_from_type.
(elf32_arm_final_link_relocate): Add support for
R_ARM_THM_JUMP24, R_ARM_THM_JUMP19, R_ARM_THM_JUMP6. Remove
case entries redundant with default.
* reloc.c: Reorganize ARM relocations. Add Thumb
assembler-internal relocations BFD_RELOC_ARM_T32_OFFSET_U8,
BFD_RELOC_ARM_T32_OFFSET_IMM, BFD_RELOC_ARM_T32_IMMEDIATE.
Add visible relocations BFD_RELOC_THUMB_PCREL_BRANCH7,
BFD_RELOC_THUMB_BRANCH20, BFD_RELOC_THUMB_BRANCH25.
Delete unused relocations BFD_RELOC_ARM_GOT12, BFD_RELOC_ARM_COPY.
* bfd-in2.h, libbfd.h: Regenerate.
opcodes:
* arm-dis.c (thumb_opcodes): Add disassembly for V6T2 16-bit
instructions. Adjust disassembly of some opcodes to match
unified syntax.
(thumb32_opcodes): New table.
(print_insn_thumb): Rename print_insn_thumb16; don't handle
two-halfword branches here.
(print_insn_thumb32): New function.
(print_insn): Choose among print_insn_arm, print_insn_thumb16,
and print_insn_thumb32. Be consistent about order of
halfwords when printing 32-bit instructions.
gas:
* hash.c (hash_lookup): Add len parameter. All callers changed.
(hash_find_n): New interface.
* hash.h: Prototype hash_find_n.
* sb.c: Include as.h.
(scrub_from_sb, sb_to_scrub, scrub_position): New statics.
(sb_scrub_and_add_sb): New interface.
* sb.h: Prototype sb_scrub_and_add_sb.
* input-scrub.c (input_scrub_include_sb): Use sb_scrub_and_add_sb.
* config/tc-arm.h (TC_FORCE_RELOCATION_LOCAL): Remove
reference to BFD_RELOC_ARM_GOT12 which is never generated.
* config/tc-arm.c: Rewrite, adding Thumb-2 support.
gas/testsuite:
* gas/arm/arm.exp: Convert all existing "gas_test" tests to
"run_dump_test" tests. Run more tests unconditionally. Run new tests.
* gas/arm/arch4t.s, gas/arm/arch6zk.s, gas/arm/arm3.s, gas/arm/arm6.s
* gas/arm/arm7dm.s, gas/arm/bignum1.s, gas/arm/float.s
* gas/arm/immed.s, gas/arm/iwmmxt.s, gas/arm/offset.s, gas/arm/thumb.s:
Adjust to work as a dump test.
* gas/arm/arch4t.d, gas/arm/arch6zk.d, gas/arm/arm3.d, gas/arm/arm6.d
* gas/arm/arm7dm.d, gas/arm/bignum1.d, gas/arm/float.d
* gas/arm/immed.d, gas/arm/iwmmxt.d, gas/arm/offset.d, gas/arm/thumb.d:
New files.
* gas/arm/armv1-bad.l, gas/arm/armv1-bad.s: Remove tests for
diagnostics that don't happen in the first pass anymore.
* gas/arm/iwmmxt-bad.l, gas/arm/r15-bad.l, gas/arm/req.l
* gas/arm/vfp-bad.l:
Update expected diagnostics.
* gas/arm/pic.d: Update expected reloc name.
* gas/arm/thumbv6.d: CPY no longer appears in disassembly.
* gas/arm/r15-bad.s: Avoid two-argument mul.
* gas/arm/req.s: Adjust comments.
* gas/arm/maverick.d, gas/arm/maverick.s: Avoid inappropriate
use of PC.
* gas/arm/macro-1.d, gas/arm/macro1.s
* gas/arm/t16-bad.l, gas/arm/t16-bad.s
* gas/arm/tcompat.d, gas/arm/tcompat.s
* gas/arm/tcompat2.d, gas/arm/tcompat2.s
* gas/arm/thumb32.d, gas/arm/thumb32.s
New test pair.
ld/testsuite:
* ld-arm/mixed-app.d: Adjust expected disassembly a little.
2005-05-18 07:40:12 +02:00
|
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
|
|
case 'c':
|
2006-06-07 16:08:19 +02:00
|
|
|
|
func (stream, "%s", arm_conditional [reg]);
|
include/elf:
* arm.h: Import complete list of official relocation names
and numbers from AAELF. Define FAKE_RELOCs for old names.
Remove a few old names no longer used anywhere.
bfd:
* elf32-arm.c: Wherever possible, use official reloc names
from AAELF.
(elf32_arm_howto_table, elf32_arm_tls_gd32_howto)
(elf32_arm_tls_ldo32_howto, elf32_arm_tls_ldm32_howto)
(elf32_arm_tls_le32_howto, elf32_arm_tls_ie32_howto)
(elf32_arm_vtinherit_howto, elf32_arm_vtentry_howto)
(elf32_arm_pc11_howto, elf32_arm_thm_pc9_howto, elf32_arm_got_prel)
(elf32_arm_r_howto): Replace with elf32_arm_howto_table_1,
elf32_arm_howto_table_2, and elf32_arm_howto_table_3.
Add many new relocations from AAELF.
(elf32_arm_howto_from_type): Update to match.
(elf32_arm_reloc_map): Add entries for R_ARM_THM_JUMP24,
R_ARM_THM_JUMP11, R_ARM_THM_JUMP19, R_ARM_THM_JUMP8,
R_ARM_THM_JUMP6, R_ARM_GNU_VTINHERIT, and R_ARM_GNU_VTENTRY.
(elf32_arm_reloc_type_lookup): Use elf32_arm_howto_from_type.
(elf32_arm_final_link_relocate): Add support for
R_ARM_THM_JUMP24, R_ARM_THM_JUMP19, R_ARM_THM_JUMP6. Remove
case entries redundant with default.
* reloc.c: Reorganize ARM relocations. Add Thumb
assembler-internal relocations BFD_RELOC_ARM_T32_OFFSET_U8,
BFD_RELOC_ARM_T32_OFFSET_IMM, BFD_RELOC_ARM_T32_IMMEDIATE.
Add visible relocations BFD_RELOC_THUMB_PCREL_BRANCH7,
BFD_RELOC_THUMB_BRANCH20, BFD_RELOC_THUMB_BRANCH25.
Delete unused relocations BFD_RELOC_ARM_GOT12, BFD_RELOC_ARM_COPY.
* bfd-in2.h, libbfd.h: Regenerate.
opcodes:
* arm-dis.c (thumb_opcodes): Add disassembly for V6T2 16-bit
instructions. Adjust disassembly of some opcodes to match
unified syntax.
(thumb32_opcodes): New table.
(print_insn_thumb): Rename print_insn_thumb16; don't handle
two-halfword branches here.
(print_insn_thumb32): New function.
(print_insn): Choose among print_insn_arm, print_insn_thumb16,
and print_insn_thumb32. Be consistent about order of
halfwords when printing 32-bit instructions.
gas:
* hash.c (hash_lookup): Add len parameter. All callers changed.
(hash_find_n): New interface.
* hash.h: Prototype hash_find_n.
* sb.c: Include as.h.
(scrub_from_sb, sb_to_scrub, scrub_position): New statics.
(sb_scrub_and_add_sb): New interface.
* sb.h: Prototype sb_scrub_and_add_sb.
* input-scrub.c (input_scrub_include_sb): Use sb_scrub_and_add_sb.
* config/tc-arm.h (TC_FORCE_RELOCATION_LOCAL): Remove
reference to BFD_RELOC_ARM_GOT12 which is never generated.
* config/tc-arm.c: Rewrite, adding Thumb-2 support.
gas/testsuite:
* gas/arm/arm.exp: Convert all existing "gas_test" tests to
"run_dump_test" tests. Run more tests unconditionally. Run new tests.
* gas/arm/arch4t.s, gas/arm/arch6zk.s, gas/arm/arm3.s, gas/arm/arm6.s
* gas/arm/arm7dm.s, gas/arm/bignum1.s, gas/arm/float.s
* gas/arm/immed.s, gas/arm/iwmmxt.s, gas/arm/offset.s, gas/arm/thumb.s:
Adjust to work as a dump test.
* gas/arm/arch4t.d, gas/arm/arch6zk.d, gas/arm/arm3.d, gas/arm/arm6.d
* gas/arm/arm7dm.d, gas/arm/bignum1.d, gas/arm/float.d
* gas/arm/immed.d, gas/arm/iwmmxt.d, gas/arm/offset.d, gas/arm/thumb.d:
New files.
* gas/arm/armv1-bad.l, gas/arm/armv1-bad.s: Remove tests for
diagnostics that don't happen in the first pass anymore.
* gas/arm/iwmmxt-bad.l, gas/arm/r15-bad.l, gas/arm/req.l
* gas/arm/vfp-bad.l:
Update expected diagnostics.
* gas/arm/pic.d: Update expected reloc name.
* gas/arm/thumbv6.d: CPY no longer appears in disassembly.
* gas/arm/r15-bad.s: Avoid two-argument mul.
* gas/arm/req.s: Adjust comments.
* gas/arm/maverick.d, gas/arm/maverick.s: Avoid inappropriate
use of PC.
* gas/arm/macro-1.d, gas/arm/macro1.s
* gas/arm/t16-bad.l, gas/arm/t16-bad.s
* gas/arm/tcompat.d, gas/arm/tcompat.s
* gas/arm/tcompat2.d, gas/arm/tcompat2.s
* gas/arm/thumb32.d, gas/arm/thumb32.s
New test pair.
ld/testsuite:
* ld-arm/mixed-app.d: Adjust expected disassembly a little.
2005-05-18 07:40:12 +02:00
|
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
|
|
default:
|
|
|
|
|
|
abort ();
|
|
|
|
|
|
}
|
|
|
|
|
|
}
|
|
|
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
|
|
case '\'':
|
|
|
|
|
|
c++;
|
|
|
|
|
|
if ((given & (1 << bitstart)) != 0)
|
|
|
|
|
|
func (stream, "%c", *c);
|
|
|
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
|
|
case '?':
|
|
|
|
|
|
++c;
|
|
|
|
|
|
if ((given & (1 << bitstart)) != 0)
|
|
|
|
|
|
func (stream, "%c", *c++);
|
|
|
|
|
|
else
|
|
|
|
|
|
func (stream, "%c", *++c);
|
|
|
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
|
|
default:
|
|
|
|
|
|
abort ();
|
|
|
|
|
|
}
|
|
|
|
|
|
}
|
|
|
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
|
|
default:
|
|
|
|
|
|
abort ();
|
|
|
|
|
|
}
|
|
|
|
|
|
}
|
2009-06-29 10:08:15 +02:00
|
|
|
|
|
|
|
|
|
|
if (value_in_comment > 32 || value_in_comment < -16)
|
|
|
|
|
|
func (stream, "\t; 0x%lx", value_in_comment);
|
2005-06-08 00:16:52 +02:00
|
|
|
|
return;
|
include/elf:
* arm.h: Import complete list of official relocation names
and numbers from AAELF. Define FAKE_RELOCs for old names.
Remove a few old names no longer used anywhere.
bfd:
* elf32-arm.c: Wherever possible, use official reloc names
from AAELF.
(elf32_arm_howto_table, elf32_arm_tls_gd32_howto)
(elf32_arm_tls_ldo32_howto, elf32_arm_tls_ldm32_howto)
(elf32_arm_tls_le32_howto, elf32_arm_tls_ie32_howto)
(elf32_arm_vtinherit_howto, elf32_arm_vtentry_howto)
(elf32_arm_pc11_howto, elf32_arm_thm_pc9_howto, elf32_arm_got_prel)
(elf32_arm_r_howto): Replace with elf32_arm_howto_table_1,
elf32_arm_howto_table_2, and elf32_arm_howto_table_3.
Add many new relocations from AAELF.
(elf32_arm_howto_from_type): Update to match.
(elf32_arm_reloc_map): Add entries for R_ARM_THM_JUMP24,
R_ARM_THM_JUMP11, R_ARM_THM_JUMP19, R_ARM_THM_JUMP8,
R_ARM_THM_JUMP6, R_ARM_GNU_VTINHERIT, and R_ARM_GNU_VTENTRY.
(elf32_arm_reloc_type_lookup): Use elf32_arm_howto_from_type.
(elf32_arm_final_link_relocate): Add support for
R_ARM_THM_JUMP24, R_ARM_THM_JUMP19, R_ARM_THM_JUMP6. Remove
case entries redundant with default.
* reloc.c: Reorganize ARM relocations. Add Thumb
assembler-internal relocations BFD_RELOC_ARM_T32_OFFSET_U8,
BFD_RELOC_ARM_T32_OFFSET_IMM, BFD_RELOC_ARM_T32_IMMEDIATE.
Add visible relocations BFD_RELOC_THUMB_PCREL_BRANCH7,
BFD_RELOC_THUMB_BRANCH20, BFD_RELOC_THUMB_BRANCH25.
Delete unused relocations BFD_RELOC_ARM_GOT12, BFD_RELOC_ARM_COPY.
* bfd-in2.h, libbfd.h: Regenerate.
opcodes:
* arm-dis.c (thumb_opcodes): Add disassembly for V6T2 16-bit
instructions. Adjust disassembly of some opcodes to match
unified syntax.
(thumb32_opcodes): New table.
(print_insn_thumb): Rename print_insn_thumb16; don't handle
two-halfword branches here.
(print_insn_thumb32): New function.
(print_insn): Choose among print_insn_arm, print_insn_thumb16,
and print_insn_thumb32. Be consistent about order of
halfwords when printing 32-bit instructions.
gas:
* hash.c (hash_lookup): Add len parameter. All callers changed.
(hash_find_n): New interface.
* hash.h: Prototype hash_find_n.
* sb.c: Include as.h.
(scrub_from_sb, sb_to_scrub, scrub_position): New statics.
(sb_scrub_and_add_sb): New interface.
* sb.h: Prototype sb_scrub_and_add_sb.
* input-scrub.c (input_scrub_include_sb): Use sb_scrub_and_add_sb.
* config/tc-arm.h (TC_FORCE_RELOCATION_LOCAL): Remove
reference to BFD_RELOC_ARM_GOT12 which is never generated.
* config/tc-arm.c: Rewrite, adding Thumb-2 support.
gas/testsuite:
* gas/arm/arm.exp: Convert all existing "gas_test" tests to
"run_dump_test" tests. Run more tests unconditionally. Run new tests.
* gas/arm/arch4t.s, gas/arm/arch6zk.s, gas/arm/arm3.s, gas/arm/arm6.s
* gas/arm/arm7dm.s, gas/arm/bignum1.s, gas/arm/float.s
* gas/arm/immed.s, gas/arm/iwmmxt.s, gas/arm/offset.s, gas/arm/thumb.s:
Adjust to work as a dump test.
* gas/arm/arch4t.d, gas/arm/arch6zk.d, gas/arm/arm3.d, gas/arm/arm6.d
* gas/arm/arm7dm.d, gas/arm/bignum1.d, gas/arm/float.d
* gas/arm/immed.d, gas/arm/iwmmxt.d, gas/arm/offset.d, gas/arm/thumb.d:
New files.
* gas/arm/armv1-bad.l, gas/arm/armv1-bad.s: Remove tests for
diagnostics that don't happen in the first pass anymore.
* gas/arm/iwmmxt-bad.l, gas/arm/r15-bad.l, gas/arm/req.l
* gas/arm/vfp-bad.l:
Update expected diagnostics.
* gas/arm/pic.d: Update expected reloc name.
* gas/arm/thumbv6.d: CPY no longer appears in disassembly.
* gas/arm/r15-bad.s: Avoid two-argument mul.
* gas/arm/req.s: Adjust comments.
* gas/arm/maverick.d, gas/arm/maverick.s: Avoid inappropriate
use of PC.
* gas/arm/macro-1.d, gas/arm/macro1.s
* gas/arm/t16-bad.l, gas/arm/t16-bad.s
* gas/arm/tcompat.d, gas/arm/tcompat.s
* gas/arm/tcompat2.d, gas/arm/tcompat2.s
* gas/arm/thumb32.d, gas/arm/thumb32.s
New test pair.
ld/testsuite:
* ld-arm/mixed-app.d: Adjust expected disassembly a little.
2005-05-18 07:40:12 +02:00
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
/* No match. */
|
|
|
|
|
|
abort ();
|
|
|
|
|
|
}
|
|
|
|
|
|
|
2006-02-24 Paul Brook <paul@codesourcery.com>
gas/
* config/arm/tc-arm.c (arm_ext_v6_notm, arm_ext_div, arm_ext_v7,
arm_ext_v7a, arm_ext_v7r, arm_ext_v7m): New variables.
(struct asm_barrier_opt): Define.
(arm_v7m_psr_hsh, arm_barrier_opt_hsh): New variables.
(parse_psr): Accept V7M psr names.
(parse_barrier): New function.
(enum operand_parse_code): Add OP_oBARRIER.
(parse_operands): Implement OP_oBARRIER.
(do_barrier): New function.
(do_dbg, do_pli, do_t_barrier, do_t_dbg, do_t_div): New functions.
(do_t_cpsi): Add V7M restrictions.
(do_t_mrs, do_t_msr): Validate V7M variants.
(md_assemble): Check for NULL variants.
(v7m_psrs, barrier_opt_names): New tables.
(insns): Add V7 instructions. Mark V6 instructions absent from V7M.
(md_begin): Initialize arm_v7m_psr_hsh and arm_barrier_opt_hsh.
(arm_cpu_option_table): Add Cortex-M3, R4 and A8.
(arm_arch_option_table): Add armv7, armv7a, armv7r and armv7m.
(struct cpu_arch_ver_table): Define.
(cpu_arch_ver): New.
(aeabi_set_public_attributes): Use cpu_arch_ver. Set
Tag_CPU_arch_profile.
* doc/c-arm.texi: Document new cpu and arch options.
gas/testsuite/
* gas/arm/thumb32.d: Fix expected msr and mrs output.
* gas/arm/arch7.d: New test.
* gas/arm/arch7.s: New test.
* gas/arm/arch7m-bad.l: New test.
* gas/arm/arch7m-bad.d: New test.
* gas/arm/arch7m-bad.s: New test.
include/opcode/
* arm.h: Add V7 feature bits.
opcodes/
* arm-dis.c (arm_opcodes): Add V7 instructions.
(thumb32_opcodes): Ditto. Handle V7M MSR/MRS variants.
(print_arm_address): New function.
(print_insn_arm): Use it. Add 'P' and 'U' cases.
(psr_name): New function.
(print_insn_thumb32): Add 'U', 'C' and 'D' cases.
2006-02-24 16:36:36 +01:00
|
|
|
|
/* Return the name of an V7M special register. */
|
2009-06-30 13:57:05 +02:00
|
|
|
|
|
2006-02-24 Paul Brook <paul@codesourcery.com>
gas/
* config/arm/tc-arm.c (arm_ext_v6_notm, arm_ext_div, arm_ext_v7,
arm_ext_v7a, arm_ext_v7r, arm_ext_v7m): New variables.
(struct asm_barrier_opt): Define.
(arm_v7m_psr_hsh, arm_barrier_opt_hsh): New variables.
(parse_psr): Accept V7M psr names.
(parse_barrier): New function.
(enum operand_parse_code): Add OP_oBARRIER.
(parse_operands): Implement OP_oBARRIER.
(do_barrier): New function.
(do_dbg, do_pli, do_t_barrier, do_t_dbg, do_t_div): New functions.
(do_t_cpsi): Add V7M restrictions.
(do_t_mrs, do_t_msr): Validate V7M variants.
(md_assemble): Check for NULL variants.
(v7m_psrs, barrier_opt_names): New tables.
(insns): Add V7 instructions. Mark V6 instructions absent from V7M.
(md_begin): Initialize arm_v7m_psr_hsh and arm_barrier_opt_hsh.
(arm_cpu_option_table): Add Cortex-M3, R4 and A8.
(arm_arch_option_table): Add armv7, armv7a, armv7r and armv7m.
(struct cpu_arch_ver_table): Define.
(cpu_arch_ver): New.
(aeabi_set_public_attributes): Use cpu_arch_ver. Set
Tag_CPU_arch_profile.
* doc/c-arm.texi: Document new cpu and arch options.
gas/testsuite/
* gas/arm/thumb32.d: Fix expected msr and mrs output.
* gas/arm/arch7.d: New test.
* gas/arm/arch7.s: New test.
* gas/arm/arch7m-bad.l: New test.
* gas/arm/arch7m-bad.d: New test.
* gas/arm/arch7m-bad.s: New test.
include/opcode/
* arm.h: Add V7 feature bits.
opcodes/
* arm-dis.c (arm_opcodes): Add V7 instructions.
(thumb32_opcodes): Ditto. Handle V7M MSR/MRS variants.
(print_arm_address): New function.
(print_insn_arm): Use it. Add 'P' and 'U' cases.
(psr_name): New function.
(print_insn_thumb32): Add 'U', 'C' and 'D' cases.
2006-02-24 16:36:36 +01:00
|
|
|
|
static const char *
|
|
|
|
|
|
psr_name (int regno)
|
|
|
|
|
|
{
|
|
|
|
|
|
switch (regno)
|
|
|
|
|
|
{
|
Add missing ARMv8-M special registers
2016-08-26 Thomas Preud'homme <thomas.preudhomme@arm.com>
gas/
* config/tc-arm.c (v7m_psrs): Add MSPLIM, PSPLIM, MSPLIM_NS,
PSPLIM_NS, PRIMASK_NS, BASEPRI_NS, FAULTMASK_NS, CONTROL_NS, SP_NS and
their lowecase counterpart special registers. Write register
identifier in hex.
* testsuite/gas/arm/archv8m-cmse-msr.s: Reorganize tests per
operation, special register and then case. Use different register for
each operation. Add tests for new special registers.
* testsuite/gas/arm/archv8m-cmse-msr-base.d: Adapt expected result
accordingly.
* testsuite/gas/arm/archv8m-cmse-msr-main.d: Likewise.
* testsuite/gas/arm/archv8m-main-dsp-4.d: Likewise.
opcodes/
* arm-dis.c (psr_name): Use hex as case labels. Add detection for
MSPLIM, PSPLIM, MSPLIM_NS, PSPLIM_NS, PRIMASK_NS, BASEPRI_NS,
FAULTMASK_NS, CONTROL_NS and SP_NS special registers.
2016-08-26 12:53:30 +02:00
|
|
|
|
case 0x0: return "APSR";
|
|
|
|
|
|
case 0x1: return "IAPSR";
|
|
|
|
|
|
case 0x2: return "EAPSR";
|
|
|
|
|
|
case 0x3: return "PSR";
|
|
|
|
|
|
case 0x5: return "IPSR";
|
|
|
|
|
|
case 0x6: return "EPSR";
|
|
|
|
|
|
case 0x7: return "IEPSR";
|
|
|
|
|
|
case 0x8: return "MSP";
|
|
|
|
|
|
case 0x9: return "PSP";
|
|
|
|
|
|
case 0xa: return "MSPLIM";
|
|
|
|
|
|
case 0xb: return "PSPLIM";
|
|
|
|
|
|
case 0x10: return "PRIMASK";
|
|
|
|
|
|
case 0x11: return "BASEPRI";
|
|
|
|
|
|
case 0x12: return "BASEPRI_MAX";
|
|
|
|
|
|
case 0x13: return "FAULTMASK";
|
|
|
|
|
|
case 0x14: return "CONTROL";
|
2016-05-10 16:01:53 +02:00
|
|
|
|
case 0x88: return "MSP_NS";
|
|
|
|
|
|
case 0x89: return "PSP_NS";
|
Add missing ARMv8-M special registers
2016-08-26 Thomas Preud'homme <thomas.preudhomme@arm.com>
gas/
* config/tc-arm.c (v7m_psrs): Add MSPLIM, PSPLIM, MSPLIM_NS,
PSPLIM_NS, PRIMASK_NS, BASEPRI_NS, FAULTMASK_NS, CONTROL_NS, SP_NS and
their lowecase counterpart special registers. Write register
identifier in hex.
* testsuite/gas/arm/archv8m-cmse-msr.s: Reorganize tests per
operation, special register and then case. Use different register for
each operation. Add tests for new special registers.
* testsuite/gas/arm/archv8m-cmse-msr-base.d: Adapt expected result
accordingly.
* testsuite/gas/arm/archv8m-cmse-msr-main.d: Likewise.
* testsuite/gas/arm/archv8m-main-dsp-4.d: Likewise.
opcodes/
* arm-dis.c (psr_name): Use hex as case labels. Add detection for
MSPLIM, PSPLIM, MSPLIM_NS, PSPLIM_NS, PRIMASK_NS, BASEPRI_NS,
FAULTMASK_NS, CONTROL_NS and SP_NS special registers.
2016-08-26 12:53:30 +02:00
|
|
|
|
case 0x8a: return "MSPLIM_NS";
|
|
|
|
|
|
case 0x8b: return "PSPLIM_NS";
|
|
|
|
|
|
case 0x90: return "PRIMASK_NS";
|
|
|
|
|
|
case 0x91: return "BASEPRI_NS";
|
|
|
|
|
|
case 0x93: return "FAULTMASK_NS";
|
|
|
|
|
|
case 0x94: return "CONTROL_NS";
|
|
|
|
|
|
case 0x98: return "SP_NS";
|
2006-02-24 Paul Brook <paul@codesourcery.com>
gas/
* config/arm/tc-arm.c (arm_ext_v6_notm, arm_ext_div, arm_ext_v7,
arm_ext_v7a, arm_ext_v7r, arm_ext_v7m): New variables.
(struct asm_barrier_opt): Define.
(arm_v7m_psr_hsh, arm_barrier_opt_hsh): New variables.
(parse_psr): Accept V7M psr names.
(parse_barrier): New function.
(enum operand_parse_code): Add OP_oBARRIER.
(parse_operands): Implement OP_oBARRIER.
(do_barrier): New function.
(do_dbg, do_pli, do_t_barrier, do_t_dbg, do_t_div): New functions.
(do_t_cpsi): Add V7M restrictions.
(do_t_mrs, do_t_msr): Validate V7M variants.
(md_assemble): Check for NULL variants.
(v7m_psrs, barrier_opt_names): New tables.
(insns): Add V7 instructions. Mark V6 instructions absent from V7M.
(md_begin): Initialize arm_v7m_psr_hsh and arm_barrier_opt_hsh.
(arm_cpu_option_table): Add Cortex-M3, R4 and A8.
(arm_arch_option_table): Add armv7, armv7a, armv7r and armv7m.
(struct cpu_arch_ver_table): Define.
(cpu_arch_ver): New.
(aeabi_set_public_attributes): Use cpu_arch_ver. Set
Tag_CPU_arch_profile.
* doc/c-arm.texi: Document new cpu and arch options.
gas/testsuite/
* gas/arm/thumb32.d: Fix expected msr and mrs output.
* gas/arm/arch7.d: New test.
* gas/arm/arch7.s: New test.
* gas/arm/arch7m-bad.l: New test.
* gas/arm/arch7m-bad.d: New test.
* gas/arm/arch7m-bad.s: New test.
include/opcode/
* arm.h: Add V7 feature bits.
opcodes/
* arm-dis.c (arm_opcodes): Add V7 instructions.
(thumb32_opcodes): Ditto. Handle V7M MSR/MRS variants.
(print_arm_address): New function.
(print_insn_arm): Use it. Add 'P' and 'U' cases.
(psr_name): New function.
(print_insn_thumb32): Add 'U', 'C' and 'D' cases.
2006-02-24 16:36:36 +01:00
|
|
|
|
default: return "<unknown>";
|
|
|
|
|
|
}
|
|
|
|
|
|
}
|
|
|
|
|
|
|
2005-06-08 00:16:52 +02:00
|
|
|
|
/* Print one 32-bit Thumb instruction from PC on INFO->STREAM. */
|
|
|
|
|
|
|
|
|
|
|
|
static void
|
|
|
|
|
|
print_insn_thumb32 (bfd_vma pc, struct disassemble_info *info, long given)
|
include/elf:
* arm.h: Import complete list of official relocation names
and numbers from AAELF. Define FAKE_RELOCs for old names.
Remove a few old names no longer used anywhere.
bfd:
* elf32-arm.c: Wherever possible, use official reloc names
from AAELF.
(elf32_arm_howto_table, elf32_arm_tls_gd32_howto)
(elf32_arm_tls_ldo32_howto, elf32_arm_tls_ldm32_howto)
(elf32_arm_tls_le32_howto, elf32_arm_tls_ie32_howto)
(elf32_arm_vtinherit_howto, elf32_arm_vtentry_howto)
(elf32_arm_pc11_howto, elf32_arm_thm_pc9_howto, elf32_arm_got_prel)
(elf32_arm_r_howto): Replace with elf32_arm_howto_table_1,
elf32_arm_howto_table_2, and elf32_arm_howto_table_3.
Add many new relocations from AAELF.
(elf32_arm_howto_from_type): Update to match.
(elf32_arm_reloc_map): Add entries for R_ARM_THM_JUMP24,
R_ARM_THM_JUMP11, R_ARM_THM_JUMP19, R_ARM_THM_JUMP8,
R_ARM_THM_JUMP6, R_ARM_GNU_VTINHERIT, and R_ARM_GNU_VTENTRY.
(elf32_arm_reloc_type_lookup): Use elf32_arm_howto_from_type.
(elf32_arm_final_link_relocate): Add support for
R_ARM_THM_JUMP24, R_ARM_THM_JUMP19, R_ARM_THM_JUMP6. Remove
case entries redundant with default.
* reloc.c: Reorganize ARM relocations. Add Thumb
assembler-internal relocations BFD_RELOC_ARM_T32_OFFSET_U8,
BFD_RELOC_ARM_T32_OFFSET_IMM, BFD_RELOC_ARM_T32_IMMEDIATE.
Add visible relocations BFD_RELOC_THUMB_PCREL_BRANCH7,
BFD_RELOC_THUMB_BRANCH20, BFD_RELOC_THUMB_BRANCH25.
Delete unused relocations BFD_RELOC_ARM_GOT12, BFD_RELOC_ARM_COPY.
* bfd-in2.h, libbfd.h: Regenerate.
opcodes:
* arm-dis.c (thumb_opcodes): Add disassembly for V6T2 16-bit
instructions. Adjust disassembly of some opcodes to match
unified syntax.
(thumb32_opcodes): New table.
(print_insn_thumb): Rename print_insn_thumb16; don't handle
two-halfword branches here.
(print_insn_thumb32): New function.
(print_insn): Choose among print_insn_arm, print_insn_thumb16,
and print_insn_thumb32. Be consistent about order of
halfwords when printing 32-bit instructions.
gas:
* hash.c (hash_lookup): Add len parameter. All callers changed.
(hash_find_n): New interface.
* hash.h: Prototype hash_find_n.
* sb.c: Include as.h.
(scrub_from_sb, sb_to_scrub, scrub_position): New statics.
(sb_scrub_and_add_sb): New interface.
* sb.h: Prototype sb_scrub_and_add_sb.
* input-scrub.c (input_scrub_include_sb): Use sb_scrub_and_add_sb.
* config/tc-arm.h (TC_FORCE_RELOCATION_LOCAL): Remove
reference to BFD_RELOC_ARM_GOT12 which is never generated.
* config/tc-arm.c: Rewrite, adding Thumb-2 support.
gas/testsuite:
* gas/arm/arm.exp: Convert all existing "gas_test" tests to
"run_dump_test" tests. Run more tests unconditionally. Run new tests.
* gas/arm/arch4t.s, gas/arm/arch6zk.s, gas/arm/arm3.s, gas/arm/arm6.s
* gas/arm/arm7dm.s, gas/arm/bignum1.s, gas/arm/float.s
* gas/arm/immed.s, gas/arm/iwmmxt.s, gas/arm/offset.s, gas/arm/thumb.s:
Adjust to work as a dump test.
* gas/arm/arch4t.d, gas/arm/arch6zk.d, gas/arm/arm3.d, gas/arm/arm6.d
* gas/arm/arm7dm.d, gas/arm/bignum1.d, gas/arm/float.d
* gas/arm/immed.d, gas/arm/iwmmxt.d, gas/arm/offset.d, gas/arm/thumb.d:
New files.
* gas/arm/armv1-bad.l, gas/arm/armv1-bad.s: Remove tests for
diagnostics that don't happen in the first pass anymore.
* gas/arm/iwmmxt-bad.l, gas/arm/r15-bad.l, gas/arm/req.l
* gas/arm/vfp-bad.l:
Update expected diagnostics.
* gas/arm/pic.d: Update expected reloc name.
* gas/arm/thumbv6.d: CPY no longer appears in disassembly.
* gas/arm/r15-bad.s: Avoid two-argument mul.
* gas/arm/req.s: Adjust comments.
* gas/arm/maverick.d, gas/arm/maverick.s: Avoid inappropriate
use of PC.
* gas/arm/macro-1.d, gas/arm/macro1.s
* gas/arm/t16-bad.l, gas/arm/t16-bad.s
* gas/arm/tcompat.d, gas/arm/tcompat.s
* gas/arm/tcompat2.d, gas/arm/tcompat2.s
* gas/arm/thumb32.d, gas/arm/thumb32.s
New test pair.
ld/testsuite:
* ld-arm/mixed-app.d: Adjust expected disassembly a little.
2005-05-18 07:40:12 +02:00
|
|
|
|
{
|
opcodes:
* arm-opc.h: Delete; fold contents into ...
* arm-dis.c: ... here. Move includes of internal COFF headers
next to includes of internal ELF headers.
(streq, WORD_ADDRESS, BDISP, BDISP23): Delete, unused.
(struct arm_opcode): Rename struct opcode32. Make 'assembler' const.
(struct thumb_opcode): Rename struct opcode16. Make 'assembler' const.
(arm_conditional, arm_fp_const, arm_shift, arm_regname, regnames)
(iwmmxt_wwnames, iwmmxt_wwssnames):
Make const.
(regnames): Remove iWMMXt coprocessor register sets.
(iwmmxt_regnames, iwmmxt_cregnames): New statics.
(get_arm_regnames): Adjust fourth argument to match above changes.
(set_iwmmxt_regnames): Delete.
(print_insn_arm): Constify 'c'. Use ISO syntax for function
pointer calls. Expand sole use of BDISP. Use iwmmxt_regnames
and iwmmxt_cregnames, not set_iwmmxt_regnames.
(print_insn_thumb16, print_insn_thumb32): Constify 'c'. Use
ISO syntax for function pointer calls.
include:
* dis-asm.h (get_arm_regnames): Update prototype.
2005-06-08 19:27:41 +02:00
|
|
|
|
const struct opcode32 *insn;
|
include/elf:
* arm.h: Import complete list of official relocation names
and numbers from AAELF. Define FAKE_RELOCs for old names.
Remove a few old names no longer used anywhere.
bfd:
* elf32-arm.c: Wherever possible, use official reloc names
from AAELF.
(elf32_arm_howto_table, elf32_arm_tls_gd32_howto)
(elf32_arm_tls_ldo32_howto, elf32_arm_tls_ldm32_howto)
(elf32_arm_tls_le32_howto, elf32_arm_tls_ie32_howto)
(elf32_arm_vtinherit_howto, elf32_arm_vtentry_howto)
(elf32_arm_pc11_howto, elf32_arm_thm_pc9_howto, elf32_arm_got_prel)
(elf32_arm_r_howto): Replace with elf32_arm_howto_table_1,
elf32_arm_howto_table_2, and elf32_arm_howto_table_3.
Add many new relocations from AAELF.
(elf32_arm_howto_from_type): Update to match.
(elf32_arm_reloc_map): Add entries for R_ARM_THM_JUMP24,
R_ARM_THM_JUMP11, R_ARM_THM_JUMP19, R_ARM_THM_JUMP8,
R_ARM_THM_JUMP6, R_ARM_GNU_VTINHERIT, and R_ARM_GNU_VTENTRY.
(elf32_arm_reloc_type_lookup): Use elf32_arm_howto_from_type.
(elf32_arm_final_link_relocate): Add support for
R_ARM_THM_JUMP24, R_ARM_THM_JUMP19, R_ARM_THM_JUMP6. Remove
case entries redundant with default.
* reloc.c: Reorganize ARM relocations. Add Thumb
assembler-internal relocations BFD_RELOC_ARM_T32_OFFSET_U8,
BFD_RELOC_ARM_T32_OFFSET_IMM, BFD_RELOC_ARM_T32_IMMEDIATE.
Add visible relocations BFD_RELOC_THUMB_PCREL_BRANCH7,
BFD_RELOC_THUMB_BRANCH20, BFD_RELOC_THUMB_BRANCH25.
Delete unused relocations BFD_RELOC_ARM_GOT12, BFD_RELOC_ARM_COPY.
* bfd-in2.h, libbfd.h: Regenerate.
opcodes:
* arm-dis.c (thumb_opcodes): Add disassembly for V6T2 16-bit
instructions. Adjust disassembly of some opcodes to match
unified syntax.
(thumb32_opcodes): New table.
(print_insn_thumb): Rename print_insn_thumb16; don't handle
two-halfword branches here.
(print_insn_thumb32): New function.
(print_insn): Choose among print_insn_arm, print_insn_thumb16,
and print_insn_thumb32. Be consistent about order of
halfwords when printing 32-bit instructions.
gas:
* hash.c (hash_lookup): Add len parameter. All callers changed.
(hash_find_n): New interface.
* hash.h: Prototype hash_find_n.
* sb.c: Include as.h.
(scrub_from_sb, sb_to_scrub, scrub_position): New statics.
(sb_scrub_and_add_sb): New interface.
* sb.h: Prototype sb_scrub_and_add_sb.
* input-scrub.c (input_scrub_include_sb): Use sb_scrub_and_add_sb.
* config/tc-arm.h (TC_FORCE_RELOCATION_LOCAL): Remove
reference to BFD_RELOC_ARM_GOT12 which is never generated.
* config/tc-arm.c: Rewrite, adding Thumb-2 support.
gas/testsuite:
* gas/arm/arm.exp: Convert all existing "gas_test" tests to
"run_dump_test" tests. Run more tests unconditionally. Run new tests.
* gas/arm/arch4t.s, gas/arm/arch6zk.s, gas/arm/arm3.s, gas/arm/arm6.s
* gas/arm/arm7dm.s, gas/arm/bignum1.s, gas/arm/float.s
* gas/arm/immed.s, gas/arm/iwmmxt.s, gas/arm/offset.s, gas/arm/thumb.s:
Adjust to work as a dump test.
* gas/arm/arch4t.d, gas/arm/arch6zk.d, gas/arm/arm3.d, gas/arm/arm6.d
* gas/arm/arm7dm.d, gas/arm/bignum1.d, gas/arm/float.d
* gas/arm/immed.d, gas/arm/iwmmxt.d, gas/arm/offset.d, gas/arm/thumb.d:
New files.
* gas/arm/armv1-bad.l, gas/arm/armv1-bad.s: Remove tests for
diagnostics that don't happen in the first pass anymore.
* gas/arm/iwmmxt-bad.l, gas/arm/r15-bad.l, gas/arm/req.l
* gas/arm/vfp-bad.l:
Update expected diagnostics.
* gas/arm/pic.d: Update expected reloc name.
* gas/arm/thumbv6.d: CPY no longer appears in disassembly.
* gas/arm/r15-bad.s: Avoid two-argument mul.
* gas/arm/req.s: Adjust comments.
* gas/arm/maverick.d, gas/arm/maverick.s: Avoid inappropriate
use of PC.
* gas/arm/macro-1.d, gas/arm/macro1.s
* gas/arm/t16-bad.l, gas/arm/t16-bad.s
* gas/arm/tcompat.d, gas/arm/tcompat.s
* gas/arm/tcompat2.d, gas/arm/tcompat2.s
* gas/arm/thumb32.d, gas/arm/thumb32.s
New test pair.
ld/testsuite:
* ld-arm/mixed-app.d: Adjust expected disassembly a little.
2005-05-18 07:40:12 +02:00
|
|
|
|
void *stream = info->stream;
|
|
|
|
|
|
fprintf_ftype func = info->fprintf_func;
|
|
|
|
|
|
|
2006-04-26 17:40:55 +02:00
|
|
|
|
if (print_insn_coprocessor (pc, info, given, TRUE))
|
|
|
|
|
|
return;
|
|
|
|
|
|
|
|
|
|
|
|
if (print_insn_neon (info, given, TRUE))
|
2005-09-02 Paul Brook <paul@codesourcery.com>
bfd/
* libbdf.h: Regenerate.
* bfd-in2.h: Regenerate.
* reloc.c: Add BFD_RELOC_ARM_T32_CP_OFF_IMM and
BFD_RELOC_ARM_T32_CP_OFF_IMM_S2.
gas/
* config/tc-arm.c (encode_arm_cp_address): Use
BFD_RELOC_ARM_T32_CP_OFF_IMM in thumb mode.
(do_iwmmxt_wldstbh): Use BFD_RELOC_ARM_T32_CP_OFF_IMM_S2 in thumb
mode.
(md_assemble): Only allow coprocessor instructions when Thumb-2 is
available.
(cCE, cC3): Define.
(insns): Use them for coprocessor instructions.
(md_pcrel_from_section): Handle BFD_RELOC_ARM_T32_CP_OFF_IMM.
(get_thumb32_insn): New function.
(put_thumb32_insn): New function.
(md_apply_fix): Handle BFD_RELOC_ARM_T32_CP_OFF_IMM and
BFD_RELOC_ARM_T32_CP_OFF_IMM_S2.
gas/testsuite/
* gas/arm/vfp-bad_t2.d, gas/arm/vfp-bad_t2.l, arm/vfp-bad_t2.s,
gas/arm/vfp1_t2.d, gas/arm/vfp1_t2.s, gas/arm/vfp1xD_t2.d,
gas/arm/vfp1xD_t2.s, gas/arm/vfp2_t2.d, gas/arm/vfp2_t2.s): New files.
opcodes/
* arm-dis.c (coprocessor_opcodes): New.
(arm_opcodes, thumb32_opcodes): Remove coprocessor insns.
(print_insn_coprocessor): New function.
(print_insn_arm): Use print_insn_coprocessor. Remove coprocessor
format characters.
(print_insn_thumb32): Use print_insn_coprocessor.
2005-09-02 15:12:45 +02:00
|
|
|
|
return;
|
|
|
|
|
|
|
include/elf:
* arm.h: Import complete list of official relocation names
and numbers from AAELF. Define FAKE_RELOCs for old names.
Remove a few old names no longer used anywhere.
bfd:
* elf32-arm.c: Wherever possible, use official reloc names
from AAELF.
(elf32_arm_howto_table, elf32_arm_tls_gd32_howto)
(elf32_arm_tls_ldo32_howto, elf32_arm_tls_ldm32_howto)
(elf32_arm_tls_le32_howto, elf32_arm_tls_ie32_howto)
(elf32_arm_vtinherit_howto, elf32_arm_vtentry_howto)
(elf32_arm_pc11_howto, elf32_arm_thm_pc9_howto, elf32_arm_got_prel)
(elf32_arm_r_howto): Replace with elf32_arm_howto_table_1,
elf32_arm_howto_table_2, and elf32_arm_howto_table_3.
Add many new relocations from AAELF.
(elf32_arm_howto_from_type): Update to match.
(elf32_arm_reloc_map): Add entries for R_ARM_THM_JUMP24,
R_ARM_THM_JUMP11, R_ARM_THM_JUMP19, R_ARM_THM_JUMP8,
R_ARM_THM_JUMP6, R_ARM_GNU_VTINHERIT, and R_ARM_GNU_VTENTRY.
(elf32_arm_reloc_type_lookup): Use elf32_arm_howto_from_type.
(elf32_arm_final_link_relocate): Add support for
R_ARM_THM_JUMP24, R_ARM_THM_JUMP19, R_ARM_THM_JUMP6. Remove
case entries redundant with default.
* reloc.c: Reorganize ARM relocations. Add Thumb
assembler-internal relocations BFD_RELOC_ARM_T32_OFFSET_U8,
BFD_RELOC_ARM_T32_OFFSET_IMM, BFD_RELOC_ARM_T32_IMMEDIATE.
Add visible relocations BFD_RELOC_THUMB_PCREL_BRANCH7,
BFD_RELOC_THUMB_BRANCH20, BFD_RELOC_THUMB_BRANCH25.
Delete unused relocations BFD_RELOC_ARM_GOT12, BFD_RELOC_ARM_COPY.
* bfd-in2.h, libbfd.h: Regenerate.
opcodes:
* arm-dis.c (thumb_opcodes): Add disassembly for V6T2 16-bit
instructions. Adjust disassembly of some opcodes to match
unified syntax.
(thumb32_opcodes): New table.
(print_insn_thumb): Rename print_insn_thumb16; don't handle
two-halfword branches here.
(print_insn_thumb32): New function.
(print_insn): Choose among print_insn_arm, print_insn_thumb16,
and print_insn_thumb32. Be consistent about order of
halfwords when printing 32-bit instructions.
gas:
* hash.c (hash_lookup): Add len parameter. All callers changed.
(hash_find_n): New interface.
* hash.h: Prototype hash_find_n.
* sb.c: Include as.h.
(scrub_from_sb, sb_to_scrub, scrub_position): New statics.
(sb_scrub_and_add_sb): New interface.
* sb.h: Prototype sb_scrub_and_add_sb.
* input-scrub.c (input_scrub_include_sb): Use sb_scrub_and_add_sb.
* config/tc-arm.h (TC_FORCE_RELOCATION_LOCAL): Remove
reference to BFD_RELOC_ARM_GOT12 which is never generated.
* config/tc-arm.c: Rewrite, adding Thumb-2 support.
gas/testsuite:
* gas/arm/arm.exp: Convert all existing "gas_test" tests to
"run_dump_test" tests. Run more tests unconditionally. Run new tests.
* gas/arm/arch4t.s, gas/arm/arch6zk.s, gas/arm/arm3.s, gas/arm/arm6.s
* gas/arm/arm7dm.s, gas/arm/bignum1.s, gas/arm/float.s
* gas/arm/immed.s, gas/arm/iwmmxt.s, gas/arm/offset.s, gas/arm/thumb.s:
Adjust to work as a dump test.
* gas/arm/arch4t.d, gas/arm/arch6zk.d, gas/arm/arm3.d, gas/arm/arm6.d
* gas/arm/arm7dm.d, gas/arm/bignum1.d, gas/arm/float.d
* gas/arm/immed.d, gas/arm/iwmmxt.d, gas/arm/offset.d, gas/arm/thumb.d:
New files.
* gas/arm/armv1-bad.l, gas/arm/armv1-bad.s: Remove tests for
diagnostics that don't happen in the first pass anymore.
* gas/arm/iwmmxt-bad.l, gas/arm/r15-bad.l, gas/arm/req.l
* gas/arm/vfp-bad.l:
Update expected diagnostics.
* gas/arm/pic.d: Update expected reloc name.
* gas/arm/thumbv6.d: CPY no longer appears in disassembly.
* gas/arm/r15-bad.s: Avoid two-argument mul.
* gas/arm/req.s: Adjust comments.
* gas/arm/maverick.d, gas/arm/maverick.s: Avoid inappropriate
use of PC.
* gas/arm/macro-1.d, gas/arm/macro1.s
* gas/arm/t16-bad.l, gas/arm/t16-bad.s
* gas/arm/tcompat.d, gas/arm/tcompat.s
* gas/arm/tcompat2.d, gas/arm/tcompat2.s
* gas/arm/thumb32.d, gas/arm/thumb32.s
New test pair.
ld/testsuite:
* ld-arm/mixed-app.d: Adjust expected disassembly a little.
2005-05-18 07:40:12 +02:00
|
|
|
|
for (insn = thumb32_opcodes; insn->assembler; insn++)
|
|
|
|
|
|
if ((given & insn->mask) == insn->value)
|
|
|
|
|
|
{
|
2009-12-17 10:52:18 +01:00
|
|
|
|
bfd_boolean is_unpredictable = FALSE;
|
2009-06-29 10:08:15 +02:00
|
|
|
|
signed long value_in_comment = 0;
|
opcodes:
* arm-opc.h: Delete; fold contents into ...
* arm-dis.c: ... here. Move includes of internal COFF headers
next to includes of internal ELF headers.
(streq, WORD_ADDRESS, BDISP, BDISP23): Delete, unused.
(struct arm_opcode): Rename struct opcode32. Make 'assembler' const.
(struct thumb_opcode): Rename struct opcode16. Make 'assembler' const.
(arm_conditional, arm_fp_const, arm_shift, arm_regname, regnames)
(iwmmxt_wwnames, iwmmxt_wwssnames):
Make const.
(regnames): Remove iWMMXt coprocessor register sets.
(iwmmxt_regnames, iwmmxt_cregnames): New statics.
(get_arm_regnames): Adjust fourth argument to match above changes.
(set_iwmmxt_regnames): Delete.
(print_insn_arm): Constify 'c'. Use ISO syntax for function
pointer calls. Expand sole use of BDISP. Use iwmmxt_regnames
and iwmmxt_cregnames, not set_iwmmxt_regnames.
(print_insn_thumb16, print_insn_thumb32): Constify 'c'. Use
ISO syntax for function pointer calls.
include:
* dis-asm.h (get_arm_regnames): Update prototype.
2005-06-08 19:27:41 +02:00
|
|
|
|
const char *c = insn->assembler;
|
2009-06-29 10:08:15 +02:00
|
|
|
|
|
include/elf:
* arm.h: Import complete list of official relocation names
and numbers from AAELF. Define FAKE_RELOCs for old names.
Remove a few old names no longer used anywhere.
bfd:
* elf32-arm.c: Wherever possible, use official reloc names
from AAELF.
(elf32_arm_howto_table, elf32_arm_tls_gd32_howto)
(elf32_arm_tls_ldo32_howto, elf32_arm_tls_ldm32_howto)
(elf32_arm_tls_le32_howto, elf32_arm_tls_ie32_howto)
(elf32_arm_vtinherit_howto, elf32_arm_vtentry_howto)
(elf32_arm_pc11_howto, elf32_arm_thm_pc9_howto, elf32_arm_got_prel)
(elf32_arm_r_howto): Replace with elf32_arm_howto_table_1,
elf32_arm_howto_table_2, and elf32_arm_howto_table_3.
Add many new relocations from AAELF.
(elf32_arm_howto_from_type): Update to match.
(elf32_arm_reloc_map): Add entries for R_ARM_THM_JUMP24,
R_ARM_THM_JUMP11, R_ARM_THM_JUMP19, R_ARM_THM_JUMP8,
R_ARM_THM_JUMP6, R_ARM_GNU_VTINHERIT, and R_ARM_GNU_VTENTRY.
(elf32_arm_reloc_type_lookup): Use elf32_arm_howto_from_type.
(elf32_arm_final_link_relocate): Add support for
R_ARM_THM_JUMP24, R_ARM_THM_JUMP19, R_ARM_THM_JUMP6. Remove
case entries redundant with default.
* reloc.c: Reorganize ARM relocations. Add Thumb
assembler-internal relocations BFD_RELOC_ARM_T32_OFFSET_U8,
BFD_RELOC_ARM_T32_OFFSET_IMM, BFD_RELOC_ARM_T32_IMMEDIATE.
Add visible relocations BFD_RELOC_THUMB_PCREL_BRANCH7,
BFD_RELOC_THUMB_BRANCH20, BFD_RELOC_THUMB_BRANCH25.
Delete unused relocations BFD_RELOC_ARM_GOT12, BFD_RELOC_ARM_COPY.
* bfd-in2.h, libbfd.h: Regenerate.
opcodes:
* arm-dis.c (thumb_opcodes): Add disassembly for V6T2 16-bit
instructions. Adjust disassembly of some opcodes to match
unified syntax.
(thumb32_opcodes): New table.
(print_insn_thumb): Rename print_insn_thumb16; don't handle
two-halfword branches here.
(print_insn_thumb32): New function.
(print_insn): Choose among print_insn_arm, print_insn_thumb16,
and print_insn_thumb32. Be consistent about order of
halfwords when printing 32-bit instructions.
gas:
* hash.c (hash_lookup): Add len parameter. All callers changed.
(hash_find_n): New interface.
* hash.h: Prototype hash_find_n.
* sb.c: Include as.h.
(scrub_from_sb, sb_to_scrub, scrub_position): New statics.
(sb_scrub_and_add_sb): New interface.
* sb.h: Prototype sb_scrub_and_add_sb.
* input-scrub.c (input_scrub_include_sb): Use sb_scrub_and_add_sb.
* config/tc-arm.h (TC_FORCE_RELOCATION_LOCAL): Remove
reference to BFD_RELOC_ARM_GOT12 which is never generated.
* config/tc-arm.c: Rewrite, adding Thumb-2 support.
gas/testsuite:
* gas/arm/arm.exp: Convert all existing "gas_test" tests to
"run_dump_test" tests. Run more tests unconditionally. Run new tests.
* gas/arm/arch4t.s, gas/arm/arch6zk.s, gas/arm/arm3.s, gas/arm/arm6.s
* gas/arm/arm7dm.s, gas/arm/bignum1.s, gas/arm/float.s
* gas/arm/immed.s, gas/arm/iwmmxt.s, gas/arm/offset.s, gas/arm/thumb.s:
Adjust to work as a dump test.
* gas/arm/arch4t.d, gas/arm/arch6zk.d, gas/arm/arm3.d, gas/arm/arm6.d
* gas/arm/arm7dm.d, gas/arm/bignum1.d, gas/arm/float.d
* gas/arm/immed.d, gas/arm/iwmmxt.d, gas/arm/offset.d, gas/arm/thumb.d:
New files.
* gas/arm/armv1-bad.l, gas/arm/armv1-bad.s: Remove tests for
diagnostics that don't happen in the first pass anymore.
* gas/arm/iwmmxt-bad.l, gas/arm/r15-bad.l, gas/arm/req.l
* gas/arm/vfp-bad.l:
Update expected diagnostics.
* gas/arm/pic.d: Update expected reloc name.
* gas/arm/thumbv6.d: CPY no longer appears in disassembly.
* gas/arm/r15-bad.s: Avoid two-argument mul.
* gas/arm/req.s: Adjust comments.
* gas/arm/maverick.d, gas/arm/maverick.s: Avoid inappropriate
use of PC.
* gas/arm/macro-1.d, gas/arm/macro1.s
* gas/arm/t16-bad.l, gas/arm/t16-bad.s
* gas/arm/tcompat.d, gas/arm/tcompat.s
* gas/arm/tcompat2.d, gas/arm/tcompat2.s
* gas/arm/thumb32.d, gas/arm/thumb32.s
New test pair.
ld/testsuite:
* ld-arm/mixed-app.d: Adjust expected disassembly a little.
2005-05-18 07:40:12 +02:00
|
|
|
|
for (; *c; c++)
|
|
|
|
|
|
{
|
|
|
|
|
|
if (*c != '%')
|
|
|
|
|
|
{
|
|
|
|
|
|
func (stream, "%c", *c);
|
|
|
|
|
|
continue;
|
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
switch (*++c)
|
|
|
|
|
|
{
|
|
|
|
|
|
case '%':
|
|
|
|
|
|
func (stream, "%%");
|
|
|
|
|
|
break;
|
|
|
|
|
|
|
2006-06-07 16:08:19 +02:00
|
|
|
|
case 'c':
|
|
|
|
|
|
if (ifthen_state)
|
|
|
|
|
|
func (stream, "%s", arm_conditional[IFTHEN_COND]);
|
|
|
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
|
|
case 'x':
|
|
|
|
|
|
if (ifthen_next_state)
|
|
|
|
|
|
func (stream, "\t; unpredictable branch in IT block\n");
|
|
|
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
|
|
case 'X':
|
|
|
|
|
|
if (ifthen_state)
|
|
|
|
|
|
func (stream, "\t; unpredictable <IT:%s>",
|
|
|
|
|
|
arm_conditional[IFTHEN_COND]);
|
|
|
|
|
|
break;
|
|
|
|
|
|
|
include/elf:
* arm.h: Import complete list of official relocation names
and numbers from AAELF. Define FAKE_RELOCs for old names.
Remove a few old names no longer used anywhere.
bfd:
* elf32-arm.c: Wherever possible, use official reloc names
from AAELF.
(elf32_arm_howto_table, elf32_arm_tls_gd32_howto)
(elf32_arm_tls_ldo32_howto, elf32_arm_tls_ldm32_howto)
(elf32_arm_tls_le32_howto, elf32_arm_tls_ie32_howto)
(elf32_arm_vtinherit_howto, elf32_arm_vtentry_howto)
(elf32_arm_pc11_howto, elf32_arm_thm_pc9_howto, elf32_arm_got_prel)
(elf32_arm_r_howto): Replace with elf32_arm_howto_table_1,
elf32_arm_howto_table_2, and elf32_arm_howto_table_3.
Add many new relocations from AAELF.
(elf32_arm_howto_from_type): Update to match.
(elf32_arm_reloc_map): Add entries for R_ARM_THM_JUMP24,
R_ARM_THM_JUMP11, R_ARM_THM_JUMP19, R_ARM_THM_JUMP8,
R_ARM_THM_JUMP6, R_ARM_GNU_VTINHERIT, and R_ARM_GNU_VTENTRY.
(elf32_arm_reloc_type_lookup): Use elf32_arm_howto_from_type.
(elf32_arm_final_link_relocate): Add support for
R_ARM_THM_JUMP24, R_ARM_THM_JUMP19, R_ARM_THM_JUMP6. Remove
case entries redundant with default.
* reloc.c: Reorganize ARM relocations. Add Thumb
assembler-internal relocations BFD_RELOC_ARM_T32_OFFSET_U8,
BFD_RELOC_ARM_T32_OFFSET_IMM, BFD_RELOC_ARM_T32_IMMEDIATE.
Add visible relocations BFD_RELOC_THUMB_PCREL_BRANCH7,
BFD_RELOC_THUMB_BRANCH20, BFD_RELOC_THUMB_BRANCH25.
Delete unused relocations BFD_RELOC_ARM_GOT12, BFD_RELOC_ARM_COPY.
* bfd-in2.h, libbfd.h: Regenerate.
opcodes:
* arm-dis.c (thumb_opcodes): Add disassembly for V6T2 16-bit
instructions. Adjust disassembly of some opcodes to match
unified syntax.
(thumb32_opcodes): New table.
(print_insn_thumb): Rename print_insn_thumb16; don't handle
two-halfword branches here.
(print_insn_thumb32): New function.
(print_insn): Choose among print_insn_arm, print_insn_thumb16,
and print_insn_thumb32. Be consistent about order of
halfwords when printing 32-bit instructions.
gas:
* hash.c (hash_lookup): Add len parameter. All callers changed.
(hash_find_n): New interface.
* hash.h: Prototype hash_find_n.
* sb.c: Include as.h.
(scrub_from_sb, sb_to_scrub, scrub_position): New statics.
(sb_scrub_and_add_sb): New interface.
* sb.h: Prototype sb_scrub_and_add_sb.
* input-scrub.c (input_scrub_include_sb): Use sb_scrub_and_add_sb.
* config/tc-arm.h (TC_FORCE_RELOCATION_LOCAL): Remove
reference to BFD_RELOC_ARM_GOT12 which is never generated.
* config/tc-arm.c: Rewrite, adding Thumb-2 support.
gas/testsuite:
* gas/arm/arm.exp: Convert all existing "gas_test" tests to
"run_dump_test" tests. Run more tests unconditionally. Run new tests.
* gas/arm/arch4t.s, gas/arm/arch6zk.s, gas/arm/arm3.s, gas/arm/arm6.s
* gas/arm/arm7dm.s, gas/arm/bignum1.s, gas/arm/float.s
* gas/arm/immed.s, gas/arm/iwmmxt.s, gas/arm/offset.s, gas/arm/thumb.s:
Adjust to work as a dump test.
* gas/arm/arch4t.d, gas/arm/arch6zk.d, gas/arm/arm3.d, gas/arm/arm6.d
* gas/arm/arm7dm.d, gas/arm/bignum1.d, gas/arm/float.d
* gas/arm/immed.d, gas/arm/iwmmxt.d, gas/arm/offset.d, gas/arm/thumb.d:
New files.
* gas/arm/armv1-bad.l, gas/arm/armv1-bad.s: Remove tests for
diagnostics that don't happen in the first pass anymore.
* gas/arm/iwmmxt-bad.l, gas/arm/r15-bad.l, gas/arm/req.l
* gas/arm/vfp-bad.l:
Update expected diagnostics.
* gas/arm/pic.d: Update expected reloc name.
* gas/arm/thumbv6.d: CPY no longer appears in disassembly.
* gas/arm/r15-bad.s: Avoid two-argument mul.
* gas/arm/req.s: Adjust comments.
* gas/arm/maverick.d, gas/arm/maverick.s: Avoid inappropriate
use of PC.
* gas/arm/macro-1.d, gas/arm/macro1.s
* gas/arm/t16-bad.l, gas/arm/t16-bad.s
* gas/arm/tcompat.d, gas/arm/tcompat.s
* gas/arm/tcompat2.d, gas/arm/tcompat2.s
* gas/arm/thumb32.d, gas/arm/thumb32.s
New test pair.
ld/testsuite:
* ld-arm/mixed-app.d: Adjust expected disassembly a little.
2005-05-18 07:40:12 +02:00
|
|
|
|
case 'I':
|
|
|
|
|
|
{
|
|
|
|
|
|
unsigned int imm12 = 0;
|
2009-06-30 13:57:05 +02:00
|
|
|
|
|
include/elf:
* arm.h: Import complete list of official relocation names
and numbers from AAELF. Define FAKE_RELOCs for old names.
Remove a few old names no longer used anywhere.
bfd:
* elf32-arm.c: Wherever possible, use official reloc names
from AAELF.
(elf32_arm_howto_table, elf32_arm_tls_gd32_howto)
(elf32_arm_tls_ldo32_howto, elf32_arm_tls_ldm32_howto)
(elf32_arm_tls_le32_howto, elf32_arm_tls_ie32_howto)
(elf32_arm_vtinherit_howto, elf32_arm_vtentry_howto)
(elf32_arm_pc11_howto, elf32_arm_thm_pc9_howto, elf32_arm_got_prel)
(elf32_arm_r_howto): Replace with elf32_arm_howto_table_1,
elf32_arm_howto_table_2, and elf32_arm_howto_table_3.
Add many new relocations from AAELF.
(elf32_arm_howto_from_type): Update to match.
(elf32_arm_reloc_map): Add entries for R_ARM_THM_JUMP24,
R_ARM_THM_JUMP11, R_ARM_THM_JUMP19, R_ARM_THM_JUMP8,
R_ARM_THM_JUMP6, R_ARM_GNU_VTINHERIT, and R_ARM_GNU_VTENTRY.
(elf32_arm_reloc_type_lookup): Use elf32_arm_howto_from_type.
(elf32_arm_final_link_relocate): Add support for
R_ARM_THM_JUMP24, R_ARM_THM_JUMP19, R_ARM_THM_JUMP6. Remove
case entries redundant with default.
* reloc.c: Reorganize ARM relocations. Add Thumb
assembler-internal relocations BFD_RELOC_ARM_T32_OFFSET_U8,
BFD_RELOC_ARM_T32_OFFSET_IMM, BFD_RELOC_ARM_T32_IMMEDIATE.
Add visible relocations BFD_RELOC_THUMB_PCREL_BRANCH7,
BFD_RELOC_THUMB_BRANCH20, BFD_RELOC_THUMB_BRANCH25.
Delete unused relocations BFD_RELOC_ARM_GOT12, BFD_RELOC_ARM_COPY.
* bfd-in2.h, libbfd.h: Regenerate.
opcodes:
* arm-dis.c (thumb_opcodes): Add disassembly for V6T2 16-bit
instructions. Adjust disassembly of some opcodes to match
unified syntax.
(thumb32_opcodes): New table.
(print_insn_thumb): Rename print_insn_thumb16; don't handle
two-halfword branches here.
(print_insn_thumb32): New function.
(print_insn): Choose among print_insn_arm, print_insn_thumb16,
and print_insn_thumb32. Be consistent about order of
halfwords when printing 32-bit instructions.
gas:
* hash.c (hash_lookup): Add len parameter. All callers changed.
(hash_find_n): New interface.
* hash.h: Prototype hash_find_n.
* sb.c: Include as.h.
(scrub_from_sb, sb_to_scrub, scrub_position): New statics.
(sb_scrub_and_add_sb): New interface.
* sb.h: Prototype sb_scrub_and_add_sb.
* input-scrub.c (input_scrub_include_sb): Use sb_scrub_and_add_sb.
* config/tc-arm.h (TC_FORCE_RELOCATION_LOCAL): Remove
reference to BFD_RELOC_ARM_GOT12 which is never generated.
* config/tc-arm.c: Rewrite, adding Thumb-2 support.
gas/testsuite:
* gas/arm/arm.exp: Convert all existing "gas_test" tests to
"run_dump_test" tests. Run more tests unconditionally. Run new tests.
* gas/arm/arch4t.s, gas/arm/arch6zk.s, gas/arm/arm3.s, gas/arm/arm6.s
* gas/arm/arm7dm.s, gas/arm/bignum1.s, gas/arm/float.s
* gas/arm/immed.s, gas/arm/iwmmxt.s, gas/arm/offset.s, gas/arm/thumb.s:
Adjust to work as a dump test.
* gas/arm/arch4t.d, gas/arm/arch6zk.d, gas/arm/arm3.d, gas/arm/arm6.d
* gas/arm/arm7dm.d, gas/arm/bignum1.d, gas/arm/float.d
* gas/arm/immed.d, gas/arm/iwmmxt.d, gas/arm/offset.d, gas/arm/thumb.d:
New files.
* gas/arm/armv1-bad.l, gas/arm/armv1-bad.s: Remove tests for
diagnostics that don't happen in the first pass anymore.
* gas/arm/iwmmxt-bad.l, gas/arm/r15-bad.l, gas/arm/req.l
* gas/arm/vfp-bad.l:
Update expected diagnostics.
* gas/arm/pic.d: Update expected reloc name.
* gas/arm/thumbv6.d: CPY no longer appears in disassembly.
* gas/arm/r15-bad.s: Avoid two-argument mul.
* gas/arm/req.s: Adjust comments.
* gas/arm/maverick.d, gas/arm/maverick.s: Avoid inappropriate
use of PC.
* gas/arm/macro-1.d, gas/arm/macro1.s
* gas/arm/t16-bad.l, gas/arm/t16-bad.s
* gas/arm/tcompat.d, gas/arm/tcompat.s
* gas/arm/tcompat2.d, gas/arm/tcompat2.s
* gas/arm/thumb32.d, gas/arm/thumb32.s
New test pair.
ld/testsuite:
* ld-arm/mixed-app.d: Adjust expected disassembly a little.
2005-05-18 07:40:12 +02:00
|
|
|
|
imm12 |= (given & 0x000000ffu);
|
|
|
|
|
|
imm12 |= (given & 0x00007000u) >> 4;
|
2005-07-29 19:28:33 +02:00
|
|
|
|
imm12 |= (given & 0x04000000u) >> 15;
|
2009-06-30 13:57:05 +02:00
|
|
|
|
func (stream, "#%u", imm12);
|
|
|
|
|
|
value_in_comment = imm12;
|
include/elf:
* arm.h: Import complete list of official relocation names
and numbers from AAELF. Define FAKE_RELOCs for old names.
Remove a few old names no longer used anywhere.
bfd:
* elf32-arm.c: Wherever possible, use official reloc names
from AAELF.
(elf32_arm_howto_table, elf32_arm_tls_gd32_howto)
(elf32_arm_tls_ldo32_howto, elf32_arm_tls_ldm32_howto)
(elf32_arm_tls_le32_howto, elf32_arm_tls_ie32_howto)
(elf32_arm_vtinherit_howto, elf32_arm_vtentry_howto)
(elf32_arm_pc11_howto, elf32_arm_thm_pc9_howto, elf32_arm_got_prel)
(elf32_arm_r_howto): Replace with elf32_arm_howto_table_1,
elf32_arm_howto_table_2, and elf32_arm_howto_table_3.
Add many new relocations from AAELF.
(elf32_arm_howto_from_type): Update to match.
(elf32_arm_reloc_map): Add entries for R_ARM_THM_JUMP24,
R_ARM_THM_JUMP11, R_ARM_THM_JUMP19, R_ARM_THM_JUMP8,
R_ARM_THM_JUMP6, R_ARM_GNU_VTINHERIT, and R_ARM_GNU_VTENTRY.
(elf32_arm_reloc_type_lookup): Use elf32_arm_howto_from_type.
(elf32_arm_final_link_relocate): Add support for
R_ARM_THM_JUMP24, R_ARM_THM_JUMP19, R_ARM_THM_JUMP6. Remove
case entries redundant with default.
* reloc.c: Reorganize ARM relocations. Add Thumb
assembler-internal relocations BFD_RELOC_ARM_T32_OFFSET_U8,
BFD_RELOC_ARM_T32_OFFSET_IMM, BFD_RELOC_ARM_T32_IMMEDIATE.
Add visible relocations BFD_RELOC_THUMB_PCREL_BRANCH7,
BFD_RELOC_THUMB_BRANCH20, BFD_RELOC_THUMB_BRANCH25.
Delete unused relocations BFD_RELOC_ARM_GOT12, BFD_RELOC_ARM_COPY.
* bfd-in2.h, libbfd.h: Regenerate.
opcodes:
* arm-dis.c (thumb_opcodes): Add disassembly for V6T2 16-bit
instructions. Adjust disassembly of some opcodes to match
unified syntax.
(thumb32_opcodes): New table.
(print_insn_thumb): Rename print_insn_thumb16; don't handle
two-halfword branches here.
(print_insn_thumb32): New function.
(print_insn): Choose among print_insn_arm, print_insn_thumb16,
and print_insn_thumb32. Be consistent about order of
halfwords when printing 32-bit instructions.
gas:
* hash.c (hash_lookup): Add len parameter. All callers changed.
(hash_find_n): New interface.
* hash.h: Prototype hash_find_n.
* sb.c: Include as.h.
(scrub_from_sb, sb_to_scrub, scrub_position): New statics.
(sb_scrub_and_add_sb): New interface.
* sb.h: Prototype sb_scrub_and_add_sb.
* input-scrub.c (input_scrub_include_sb): Use sb_scrub_and_add_sb.
* config/tc-arm.h (TC_FORCE_RELOCATION_LOCAL): Remove
reference to BFD_RELOC_ARM_GOT12 which is never generated.
* config/tc-arm.c: Rewrite, adding Thumb-2 support.
gas/testsuite:
* gas/arm/arm.exp: Convert all existing "gas_test" tests to
"run_dump_test" tests. Run more tests unconditionally. Run new tests.
* gas/arm/arch4t.s, gas/arm/arch6zk.s, gas/arm/arm3.s, gas/arm/arm6.s
* gas/arm/arm7dm.s, gas/arm/bignum1.s, gas/arm/float.s
* gas/arm/immed.s, gas/arm/iwmmxt.s, gas/arm/offset.s, gas/arm/thumb.s:
Adjust to work as a dump test.
* gas/arm/arch4t.d, gas/arm/arch6zk.d, gas/arm/arm3.d, gas/arm/arm6.d
* gas/arm/arm7dm.d, gas/arm/bignum1.d, gas/arm/float.d
* gas/arm/immed.d, gas/arm/iwmmxt.d, gas/arm/offset.d, gas/arm/thumb.d:
New files.
* gas/arm/armv1-bad.l, gas/arm/armv1-bad.s: Remove tests for
diagnostics that don't happen in the first pass anymore.
* gas/arm/iwmmxt-bad.l, gas/arm/r15-bad.l, gas/arm/req.l
* gas/arm/vfp-bad.l:
Update expected diagnostics.
* gas/arm/pic.d: Update expected reloc name.
* gas/arm/thumbv6.d: CPY no longer appears in disassembly.
* gas/arm/r15-bad.s: Avoid two-argument mul.
* gas/arm/req.s: Adjust comments.
* gas/arm/maverick.d, gas/arm/maverick.s: Avoid inappropriate
use of PC.
* gas/arm/macro-1.d, gas/arm/macro1.s
* gas/arm/t16-bad.l, gas/arm/t16-bad.s
* gas/arm/tcompat.d, gas/arm/tcompat.s
* gas/arm/tcompat2.d, gas/arm/tcompat2.s
* gas/arm/thumb32.d, gas/arm/thumb32.s
New test pair.
ld/testsuite:
* ld-arm/mixed-app.d: Adjust expected disassembly a little.
2005-05-18 07:40:12 +02:00
|
|
|
|
}
|
|
|
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
|
|
case 'M':
|
|
|
|
|
|
{
|
|
|
|
|
|
unsigned int bits = 0, imm, imm8, mod;
|
2009-06-30 13:57:05 +02:00
|
|
|
|
|
include/elf:
* arm.h: Import complete list of official relocation names
and numbers from AAELF. Define FAKE_RELOCs for old names.
Remove a few old names no longer used anywhere.
bfd:
* elf32-arm.c: Wherever possible, use official reloc names
from AAELF.
(elf32_arm_howto_table, elf32_arm_tls_gd32_howto)
(elf32_arm_tls_ldo32_howto, elf32_arm_tls_ldm32_howto)
(elf32_arm_tls_le32_howto, elf32_arm_tls_ie32_howto)
(elf32_arm_vtinherit_howto, elf32_arm_vtentry_howto)
(elf32_arm_pc11_howto, elf32_arm_thm_pc9_howto, elf32_arm_got_prel)
(elf32_arm_r_howto): Replace with elf32_arm_howto_table_1,
elf32_arm_howto_table_2, and elf32_arm_howto_table_3.
Add many new relocations from AAELF.
(elf32_arm_howto_from_type): Update to match.
(elf32_arm_reloc_map): Add entries for R_ARM_THM_JUMP24,
R_ARM_THM_JUMP11, R_ARM_THM_JUMP19, R_ARM_THM_JUMP8,
R_ARM_THM_JUMP6, R_ARM_GNU_VTINHERIT, and R_ARM_GNU_VTENTRY.
(elf32_arm_reloc_type_lookup): Use elf32_arm_howto_from_type.
(elf32_arm_final_link_relocate): Add support for
R_ARM_THM_JUMP24, R_ARM_THM_JUMP19, R_ARM_THM_JUMP6. Remove
case entries redundant with default.
* reloc.c: Reorganize ARM relocations. Add Thumb
assembler-internal relocations BFD_RELOC_ARM_T32_OFFSET_U8,
BFD_RELOC_ARM_T32_OFFSET_IMM, BFD_RELOC_ARM_T32_IMMEDIATE.
Add visible relocations BFD_RELOC_THUMB_PCREL_BRANCH7,
BFD_RELOC_THUMB_BRANCH20, BFD_RELOC_THUMB_BRANCH25.
Delete unused relocations BFD_RELOC_ARM_GOT12, BFD_RELOC_ARM_COPY.
* bfd-in2.h, libbfd.h: Regenerate.
opcodes:
* arm-dis.c (thumb_opcodes): Add disassembly for V6T2 16-bit
instructions. Adjust disassembly of some opcodes to match
unified syntax.
(thumb32_opcodes): New table.
(print_insn_thumb): Rename print_insn_thumb16; don't handle
two-halfword branches here.
(print_insn_thumb32): New function.
(print_insn): Choose among print_insn_arm, print_insn_thumb16,
and print_insn_thumb32. Be consistent about order of
halfwords when printing 32-bit instructions.
gas:
* hash.c (hash_lookup): Add len parameter. All callers changed.
(hash_find_n): New interface.
* hash.h: Prototype hash_find_n.
* sb.c: Include as.h.
(scrub_from_sb, sb_to_scrub, scrub_position): New statics.
(sb_scrub_and_add_sb): New interface.
* sb.h: Prototype sb_scrub_and_add_sb.
* input-scrub.c (input_scrub_include_sb): Use sb_scrub_and_add_sb.
* config/tc-arm.h (TC_FORCE_RELOCATION_LOCAL): Remove
reference to BFD_RELOC_ARM_GOT12 which is never generated.
* config/tc-arm.c: Rewrite, adding Thumb-2 support.
gas/testsuite:
* gas/arm/arm.exp: Convert all existing "gas_test" tests to
"run_dump_test" tests. Run more tests unconditionally. Run new tests.
* gas/arm/arch4t.s, gas/arm/arch6zk.s, gas/arm/arm3.s, gas/arm/arm6.s
* gas/arm/arm7dm.s, gas/arm/bignum1.s, gas/arm/float.s
* gas/arm/immed.s, gas/arm/iwmmxt.s, gas/arm/offset.s, gas/arm/thumb.s:
Adjust to work as a dump test.
* gas/arm/arch4t.d, gas/arm/arch6zk.d, gas/arm/arm3.d, gas/arm/arm6.d
* gas/arm/arm7dm.d, gas/arm/bignum1.d, gas/arm/float.d
* gas/arm/immed.d, gas/arm/iwmmxt.d, gas/arm/offset.d, gas/arm/thumb.d:
New files.
* gas/arm/armv1-bad.l, gas/arm/armv1-bad.s: Remove tests for
diagnostics that don't happen in the first pass anymore.
* gas/arm/iwmmxt-bad.l, gas/arm/r15-bad.l, gas/arm/req.l
* gas/arm/vfp-bad.l:
Update expected diagnostics.
* gas/arm/pic.d: Update expected reloc name.
* gas/arm/thumbv6.d: CPY no longer appears in disassembly.
* gas/arm/r15-bad.s: Avoid two-argument mul.
* gas/arm/req.s: Adjust comments.
* gas/arm/maverick.d, gas/arm/maverick.s: Avoid inappropriate
use of PC.
* gas/arm/macro-1.d, gas/arm/macro1.s
* gas/arm/t16-bad.l, gas/arm/t16-bad.s
* gas/arm/tcompat.d, gas/arm/tcompat.s
* gas/arm/tcompat2.d, gas/arm/tcompat2.s
* gas/arm/thumb32.d, gas/arm/thumb32.s
New test pair.
ld/testsuite:
* ld-arm/mixed-app.d: Adjust expected disassembly a little.
2005-05-18 07:40:12 +02:00
|
|
|
|
bits |= (given & 0x000000ffu);
|
|
|
|
|
|
bits |= (given & 0x00007000u) >> 4;
|
|
|
|
|
|
bits |= (given & 0x04000000u) >> 15;
|
|
|
|
|
|
imm8 = (bits & 0x0ff);
|
|
|
|
|
|
mod = (bits & 0xf00) >> 8;
|
|
|
|
|
|
switch (mod)
|
|
|
|
|
|
{
|
|
|
|
|
|
case 0: imm = imm8; break;
|
2009-11-11 10:44:45 +01:00
|
|
|
|
case 1: imm = ((imm8 << 16) | imm8); break;
|
|
|
|
|
|
case 2: imm = ((imm8 << 24) | (imm8 << 8)); break;
|
|
|
|
|
|
case 3: imm = ((imm8 << 24) | (imm8 << 16) | (imm8 << 8) | imm8); break;
|
include/elf:
* arm.h: Import complete list of official relocation names
and numbers from AAELF. Define FAKE_RELOCs for old names.
Remove a few old names no longer used anywhere.
bfd:
* elf32-arm.c: Wherever possible, use official reloc names
from AAELF.
(elf32_arm_howto_table, elf32_arm_tls_gd32_howto)
(elf32_arm_tls_ldo32_howto, elf32_arm_tls_ldm32_howto)
(elf32_arm_tls_le32_howto, elf32_arm_tls_ie32_howto)
(elf32_arm_vtinherit_howto, elf32_arm_vtentry_howto)
(elf32_arm_pc11_howto, elf32_arm_thm_pc9_howto, elf32_arm_got_prel)
(elf32_arm_r_howto): Replace with elf32_arm_howto_table_1,
elf32_arm_howto_table_2, and elf32_arm_howto_table_3.
Add many new relocations from AAELF.
(elf32_arm_howto_from_type): Update to match.
(elf32_arm_reloc_map): Add entries for R_ARM_THM_JUMP24,
R_ARM_THM_JUMP11, R_ARM_THM_JUMP19, R_ARM_THM_JUMP8,
R_ARM_THM_JUMP6, R_ARM_GNU_VTINHERIT, and R_ARM_GNU_VTENTRY.
(elf32_arm_reloc_type_lookup): Use elf32_arm_howto_from_type.
(elf32_arm_final_link_relocate): Add support for
R_ARM_THM_JUMP24, R_ARM_THM_JUMP19, R_ARM_THM_JUMP6. Remove
case entries redundant with default.
* reloc.c: Reorganize ARM relocations. Add Thumb
assembler-internal relocations BFD_RELOC_ARM_T32_OFFSET_U8,
BFD_RELOC_ARM_T32_OFFSET_IMM, BFD_RELOC_ARM_T32_IMMEDIATE.
Add visible relocations BFD_RELOC_THUMB_PCREL_BRANCH7,
BFD_RELOC_THUMB_BRANCH20, BFD_RELOC_THUMB_BRANCH25.
Delete unused relocations BFD_RELOC_ARM_GOT12, BFD_RELOC_ARM_COPY.
* bfd-in2.h, libbfd.h: Regenerate.
opcodes:
* arm-dis.c (thumb_opcodes): Add disassembly for V6T2 16-bit
instructions. Adjust disassembly of some opcodes to match
unified syntax.
(thumb32_opcodes): New table.
(print_insn_thumb): Rename print_insn_thumb16; don't handle
two-halfword branches here.
(print_insn_thumb32): New function.
(print_insn): Choose among print_insn_arm, print_insn_thumb16,
and print_insn_thumb32. Be consistent about order of
halfwords when printing 32-bit instructions.
gas:
* hash.c (hash_lookup): Add len parameter. All callers changed.
(hash_find_n): New interface.
* hash.h: Prototype hash_find_n.
* sb.c: Include as.h.
(scrub_from_sb, sb_to_scrub, scrub_position): New statics.
(sb_scrub_and_add_sb): New interface.
* sb.h: Prototype sb_scrub_and_add_sb.
* input-scrub.c (input_scrub_include_sb): Use sb_scrub_and_add_sb.
* config/tc-arm.h (TC_FORCE_RELOCATION_LOCAL): Remove
reference to BFD_RELOC_ARM_GOT12 which is never generated.
* config/tc-arm.c: Rewrite, adding Thumb-2 support.
gas/testsuite:
* gas/arm/arm.exp: Convert all existing "gas_test" tests to
"run_dump_test" tests. Run more tests unconditionally. Run new tests.
* gas/arm/arch4t.s, gas/arm/arch6zk.s, gas/arm/arm3.s, gas/arm/arm6.s
* gas/arm/arm7dm.s, gas/arm/bignum1.s, gas/arm/float.s
* gas/arm/immed.s, gas/arm/iwmmxt.s, gas/arm/offset.s, gas/arm/thumb.s:
Adjust to work as a dump test.
* gas/arm/arch4t.d, gas/arm/arch6zk.d, gas/arm/arm3.d, gas/arm/arm6.d
* gas/arm/arm7dm.d, gas/arm/bignum1.d, gas/arm/float.d
* gas/arm/immed.d, gas/arm/iwmmxt.d, gas/arm/offset.d, gas/arm/thumb.d:
New files.
* gas/arm/armv1-bad.l, gas/arm/armv1-bad.s: Remove tests for
diagnostics that don't happen in the first pass anymore.
* gas/arm/iwmmxt-bad.l, gas/arm/r15-bad.l, gas/arm/req.l
* gas/arm/vfp-bad.l:
Update expected diagnostics.
* gas/arm/pic.d: Update expected reloc name.
* gas/arm/thumbv6.d: CPY no longer appears in disassembly.
* gas/arm/r15-bad.s: Avoid two-argument mul.
* gas/arm/req.s: Adjust comments.
* gas/arm/maverick.d, gas/arm/maverick.s: Avoid inappropriate
use of PC.
* gas/arm/macro-1.d, gas/arm/macro1.s
* gas/arm/t16-bad.l, gas/arm/t16-bad.s
* gas/arm/tcompat.d, gas/arm/tcompat.s
* gas/arm/tcompat2.d, gas/arm/tcompat2.s
* gas/arm/thumb32.d, gas/arm/thumb32.s
New test pair.
ld/testsuite:
* ld-arm/mixed-app.d: Adjust expected disassembly a little.
2005-05-18 07:40:12 +02:00
|
|
|
|
default:
|
|
|
|
|
|
mod = (bits & 0xf80) >> 7;
|
|
|
|
|
|
imm8 = (bits & 0x07f) | 0x80;
|
|
|
|
|
|
imm = (((imm8 << (32 - mod)) | (imm8 >> mod)) & 0xffffffff);
|
|
|
|
|
|
}
|
2009-06-30 13:57:05 +02:00
|
|
|
|
func (stream, "#%u", imm);
|
|
|
|
|
|
value_in_comment = imm;
|
include/elf:
* arm.h: Import complete list of official relocation names
and numbers from AAELF. Define FAKE_RELOCs for old names.
Remove a few old names no longer used anywhere.
bfd:
* elf32-arm.c: Wherever possible, use official reloc names
from AAELF.
(elf32_arm_howto_table, elf32_arm_tls_gd32_howto)
(elf32_arm_tls_ldo32_howto, elf32_arm_tls_ldm32_howto)
(elf32_arm_tls_le32_howto, elf32_arm_tls_ie32_howto)
(elf32_arm_vtinherit_howto, elf32_arm_vtentry_howto)
(elf32_arm_pc11_howto, elf32_arm_thm_pc9_howto, elf32_arm_got_prel)
(elf32_arm_r_howto): Replace with elf32_arm_howto_table_1,
elf32_arm_howto_table_2, and elf32_arm_howto_table_3.
Add many new relocations from AAELF.
(elf32_arm_howto_from_type): Update to match.
(elf32_arm_reloc_map): Add entries for R_ARM_THM_JUMP24,
R_ARM_THM_JUMP11, R_ARM_THM_JUMP19, R_ARM_THM_JUMP8,
R_ARM_THM_JUMP6, R_ARM_GNU_VTINHERIT, and R_ARM_GNU_VTENTRY.
(elf32_arm_reloc_type_lookup): Use elf32_arm_howto_from_type.
(elf32_arm_final_link_relocate): Add support for
R_ARM_THM_JUMP24, R_ARM_THM_JUMP19, R_ARM_THM_JUMP6. Remove
case entries redundant with default.
* reloc.c: Reorganize ARM relocations. Add Thumb
assembler-internal relocations BFD_RELOC_ARM_T32_OFFSET_U8,
BFD_RELOC_ARM_T32_OFFSET_IMM, BFD_RELOC_ARM_T32_IMMEDIATE.
Add visible relocations BFD_RELOC_THUMB_PCREL_BRANCH7,
BFD_RELOC_THUMB_BRANCH20, BFD_RELOC_THUMB_BRANCH25.
Delete unused relocations BFD_RELOC_ARM_GOT12, BFD_RELOC_ARM_COPY.
* bfd-in2.h, libbfd.h: Regenerate.
opcodes:
* arm-dis.c (thumb_opcodes): Add disassembly for V6T2 16-bit
instructions. Adjust disassembly of some opcodes to match
unified syntax.
(thumb32_opcodes): New table.
(print_insn_thumb): Rename print_insn_thumb16; don't handle
two-halfword branches here.
(print_insn_thumb32): New function.
(print_insn): Choose among print_insn_arm, print_insn_thumb16,
and print_insn_thumb32. Be consistent about order of
halfwords when printing 32-bit instructions.
gas:
* hash.c (hash_lookup): Add len parameter. All callers changed.
(hash_find_n): New interface.
* hash.h: Prototype hash_find_n.
* sb.c: Include as.h.
(scrub_from_sb, sb_to_scrub, scrub_position): New statics.
(sb_scrub_and_add_sb): New interface.
* sb.h: Prototype sb_scrub_and_add_sb.
* input-scrub.c (input_scrub_include_sb): Use sb_scrub_and_add_sb.
* config/tc-arm.h (TC_FORCE_RELOCATION_LOCAL): Remove
reference to BFD_RELOC_ARM_GOT12 which is never generated.
* config/tc-arm.c: Rewrite, adding Thumb-2 support.
gas/testsuite:
* gas/arm/arm.exp: Convert all existing "gas_test" tests to
"run_dump_test" tests. Run more tests unconditionally. Run new tests.
* gas/arm/arch4t.s, gas/arm/arch6zk.s, gas/arm/arm3.s, gas/arm/arm6.s
* gas/arm/arm7dm.s, gas/arm/bignum1.s, gas/arm/float.s
* gas/arm/immed.s, gas/arm/iwmmxt.s, gas/arm/offset.s, gas/arm/thumb.s:
Adjust to work as a dump test.
* gas/arm/arch4t.d, gas/arm/arch6zk.d, gas/arm/arm3.d, gas/arm/arm6.d
* gas/arm/arm7dm.d, gas/arm/bignum1.d, gas/arm/float.d
* gas/arm/immed.d, gas/arm/iwmmxt.d, gas/arm/offset.d, gas/arm/thumb.d:
New files.
* gas/arm/armv1-bad.l, gas/arm/armv1-bad.s: Remove tests for
diagnostics that don't happen in the first pass anymore.
* gas/arm/iwmmxt-bad.l, gas/arm/r15-bad.l, gas/arm/req.l
* gas/arm/vfp-bad.l:
Update expected diagnostics.
* gas/arm/pic.d: Update expected reloc name.
* gas/arm/thumbv6.d: CPY no longer appears in disassembly.
* gas/arm/r15-bad.s: Avoid two-argument mul.
* gas/arm/req.s: Adjust comments.
* gas/arm/maverick.d, gas/arm/maverick.s: Avoid inappropriate
use of PC.
* gas/arm/macro-1.d, gas/arm/macro1.s
* gas/arm/t16-bad.l, gas/arm/t16-bad.s
* gas/arm/tcompat.d, gas/arm/tcompat.s
* gas/arm/tcompat2.d, gas/arm/tcompat2.s
* gas/arm/thumb32.d, gas/arm/thumb32.s
New test pair.
ld/testsuite:
* ld-arm/mixed-app.d: Adjust expected disassembly a little.
2005-05-18 07:40:12 +02:00
|
|
|
|
}
|
|
|
|
|
|
break;
|
2015-08-12 13:45:07 +02:00
|
|
|
|
|
include/elf:
* arm.h: Import complete list of official relocation names
and numbers from AAELF. Define FAKE_RELOCs for old names.
Remove a few old names no longer used anywhere.
bfd:
* elf32-arm.c: Wherever possible, use official reloc names
from AAELF.
(elf32_arm_howto_table, elf32_arm_tls_gd32_howto)
(elf32_arm_tls_ldo32_howto, elf32_arm_tls_ldm32_howto)
(elf32_arm_tls_le32_howto, elf32_arm_tls_ie32_howto)
(elf32_arm_vtinherit_howto, elf32_arm_vtentry_howto)
(elf32_arm_pc11_howto, elf32_arm_thm_pc9_howto, elf32_arm_got_prel)
(elf32_arm_r_howto): Replace with elf32_arm_howto_table_1,
elf32_arm_howto_table_2, and elf32_arm_howto_table_3.
Add many new relocations from AAELF.
(elf32_arm_howto_from_type): Update to match.
(elf32_arm_reloc_map): Add entries for R_ARM_THM_JUMP24,
R_ARM_THM_JUMP11, R_ARM_THM_JUMP19, R_ARM_THM_JUMP8,
R_ARM_THM_JUMP6, R_ARM_GNU_VTINHERIT, and R_ARM_GNU_VTENTRY.
(elf32_arm_reloc_type_lookup): Use elf32_arm_howto_from_type.
(elf32_arm_final_link_relocate): Add support for
R_ARM_THM_JUMP24, R_ARM_THM_JUMP19, R_ARM_THM_JUMP6. Remove
case entries redundant with default.
* reloc.c: Reorganize ARM relocations. Add Thumb
assembler-internal relocations BFD_RELOC_ARM_T32_OFFSET_U8,
BFD_RELOC_ARM_T32_OFFSET_IMM, BFD_RELOC_ARM_T32_IMMEDIATE.
Add visible relocations BFD_RELOC_THUMB_PCREL_BRANCH7,
BFD_RELOC_THUMB_BRANCH20, BFD_RELOC_THUMB_BRANCH25.
Delete unused relocations BFD_RELOC_ARM_GOT12, BFD_RELOC_ARM_COPY.
* bfd-in2.h, libbfd.h: Regenerate.
opcodes:
* arm-dis.c (thumb_opcodes): Add disassembly for V6T2 16-bit
instructions. Adjust disassembly of some opcodes to match
unified syntax.
(thumb32_opcodes): New table.
(print_insn_thumb): Rename print_insn_thumb16; don't handle
two-halfword branches here.
(print_insn_thumb32): New function.
(print_insn): Choose among print_insn_arm, print_insn_thumb16,
and print_insn_thumb32. Be consistent about order of
halfwords when printing 32-bit instructions.
gas:
* hash.c (hash_lookup): Add len parameter. All callers changed.
(hash_find_n): New interface.
* hash.h: Prototype hash_find_n.
* sb.c: Include as.h.
(scrub_from_sb, sb_to_scrub, scrub_position): New statics.
(sb_scrub_and_add_sb): New interface.
* sb.h: Prototype sb_scrub_and_add_sb.
* input-scrub.c (input_scrub_include_sb): Use sb_scrub_and_add_sb.
* config/tc-arm.h (TC_FORCE_RELOCATION_LOCAL): Remove
reference to BFD_RELOC_ARM_GOT12 which is never generated.
* config/tc-arm.c: Rewrite, adding Thumb-2 support.
gas/testsuite:
* gas/arm/arm.exp: Convert all existing "gas_test" tests to
"run_dump_test" tests. Run more tests unconditionally. Run new tests.
* gas/arm/arch4t.s, gas/arm/arch6zk.s, gas/arm/arm3.s, gas/arm/arm6.s
* gas/arm/arm7dm.s, gas/arm/bignum1.s, gas/arm/float.s
* gas/arm/immed.s, gas/arm/iwmmxt.s, gas/arm/offset.s, gas/arm/thumb.s:
Adjust to work as a dump test.
* gas/arm/arch4t.d, gas/arm/arch6zk.d, gas/arm/arm3.d, gas/arm/arm6.d
* gas/arm/arm7dm.d, gas/arm/bignum1.d, gas/arm/float.d
* gas/arm/immed.d, gas/arm/iwmmxt.d, gas/arm/offset.d, gas/arm/thumb.d:
New files.
* gas/arm/armv1-bad.l, gas/arm/armv1-bad.s: Remove tests for
diagnostics that don't happen in the first pass anymore.
* gas/arm/iwmmxt-bad.l, gas/arm/r15-bad.l, gas/arm/req.l
* gas/arm/vfp-bad.l:
Update expected diagnostics.
* gas/arm/pic.d: Update expected reloc name.
* gas/arm/thumbv6.d: CPY no longer appears in disassembly.
* gas/arm/r15-bad.s: Avoid two-argument mul.
* gas/arm/req.s: Adjust comments.
* gas/arm/maverick.d, gas/arm/maverick.s: Avoid inappropriate
use of PC.
* gas/arm/macro-1.d, gas/arm/macro1.s
* gas/arm/t16-bad.l, gas/arm/t16-bad.s
* gas/arm/tcompat.d, gas/arm/tcompat.s
* gas/arm/tcompat2.d, gas/arm/tcompat2.s
* gas/arm/thumb32.d, gas/arm/thumb32.s
New test pair.
ld/testsuite:
* ld-arm/mixed-app.d: Adjust expected disassembly a little.
2005-05-18 07:40:12 +02:00
|
|
|
|
case 'J':
|
|
|
|
|
|
{
|
|
|
|
|
|
unsigned int imm = 0;
|
2009-06-30 13:57:05 +02:00
|
|
|
|
|
include/elf:
* arm.h: Import complete list of official relocation names
and numbers from AAELF. Define FAKE_RELOCs for old names.
Remove a few old names no longer used anywhere.
bfd:
* elf32-arm.c: Wherever possible, use official reloc names
from AAELF.
(elf32_arm_howto_table, elf32_arm_tls_gd32_howto)
(elf32_arm_tls_ldo32_howto, elf32_arm_tls_ldm32_howto)
(elf32_arm_tls_le32_howto, elf32_arm_tls_ie32_howto)
(elf32_arm_vtinherit_howto, elf32_arm_vtentry_howto)
(elf32_arm_pc11_howto, elf32_arm_thm_pc9_howto, elf32_arm_got_prel)
(elf32_arm_r_howto): Replace with elf32_arm_howto_table_1,
elf32_arm_howto_table_2, and elf32_arm_howto_table_3.
Add many new relocations from AAELF.
(elf32_arm_howto_from_type): Update to match.
(elf32_arm_reloc_map): Add entries for R_ARM_THM_JUMP24,
R_ARM_THM_JUMP11, R_ARM_THM_JUMP19, R_ARM_THM_JUMP8,
R_ARM_THM_JUMP6, R_ARM_GNU_VTINHERIT, and R_ARM_GNU_VTENTRY.
(elf32_arm_reloc_type_lookup): Use elf32_arm_howto_from_type.
(elf32_arm_final_link_relocate): Add support for
R_ARM_THM_JUMP24, R_ARM_THM_JUMP19, R_ARM_THM_JUMP6. Remove
case entries redundant with default.
* reloc.c: Reorganize ARM relocations. Add Thumb
assembler-internal relocations BFD_RELOC_ARM_T32_OFFSET_U8,
BFD_RELOC_ARM_T32_OFFSET_IMM, BFD_RELOC_ARM_T32_IMMEDIATE.
Add visible relocations BFD_RELOC_THUMB_PCREL_BRANCH7,
BFD_RELOC_THUMB_BRANCH20, BFD_RELOC_THUMB_BRANCH25.
Delete unused relocations BFD_RELOC_ARM_GOT12, BFD_RELOC_ARM_COPY.
* bfd-in2.h, libbfd.h: Regenerate.
opcodes:
* arm-dis.c (thumb_opcodes): Add disassembly for V6T2 16-bit
instructions. Adjust disassembly of some opcodes to match
unified syntax.
(thumb32_opcodes): New table.
(print_insn_thumb): Rename print_insn_thumb16; don't handle
two-halfword branches here.
(print_insn_thumb32): New function.
(print_insn): Choose among print_insn_arm, print_insn_thumb16,
and print_insn_thumb32. Be consistent about order of
halfwords when printing 32-bit instructions.
gas:
* hash.c (hash_lookup): Add len parameter. All callers changed.
(hash_find_n): New interface.
* hash.h: Prototype hash_find_n.
* sb.c: Include as.h.
(scrub_from_sb, sb_to_scrub, scrub_position): New statics.
(sb_scrub_and_add_sb): New interface.
* sb.h: Prototype sb_scrub_and_add_sb.
* input-scrub.c (input_scrub_include_sb): Use sb_scrub_and_add_sb.
* config/tc-arm.h (TC_FORCE_RELOCATION_LOCAL): Remove
reference to BFD_RELOC_ARM_GOT12 which is never generated.
* config/tc-arm.c: Rewrite, adding Thumb-2 support.
gas/testsuite:
* gas/arm/arm.exp: Convert all existing "gas_test" tests to
"run_dump_test" tests. Run more tests unconditionally. Run new tests.
* gas/arm/arch4t.s, gas/arm/arch6zk.s, gas/arm/arm3.s, gas/arm/arm6.s
* gas/arm/arm7dm.s, gas/arm/bignum1.s, gas/arm/float.s
* gas/arm/immed.s, gas/arm/iwmmxt.s, gas/arm/offset.s, gas/arm/thumb.s:
Adjust to work as a dump test.
* gas/arm/arch4t.d, gas/arm/arch6zk.d, gas/arm/arm3.d, gas/arm/arm6.d
* gas/arm/arm7dm.d, gas/arm/bignum1.d, gas/arm/float.d
* gas/arm/immed.d, gas/arm/iwmmxt.d, gas/arm/offset.d, gas/arm/thumb.d:
New files.
* gas/arm/armv1-bad.l, gas/arm/armv1-bad.s: Remove tests for
diagnostics that don't happen in the first pass anymore.
* gas/arm/iwmmxt-bad.l, gas/arm/r15-bad.l, gas/arm/req.l
* gas/arm/vfp-bad.l:
Update expected diagnostics.
* gas/arm/pic.d: Update expected reloc name.
* gas/arm/thumbv6.d: CPY no longer appears in disassembly.
* gas/arm/r15-bad.s: Avoid two-argument mul.
* gas/arm/req.s: Adjust comments.
* gas/arm/maverick.d, gas/arm/maverick.s: Avoid inappropriate
use of PC.
* gas/arm/macro-1.d, gas/arm/macro1.s
* gas/arm/t16-bad.l, gas/arm/t16-bad.s
* gas/arm/tcompat.d, gas/arm/tcompat.s
* gas/arm/tcompat2.d, gas/arm/tcompat2.s
* gas/arm/thumb32.d, gas/arm/thumb32.s
New test pair.
ld/testsuite:
* ld-arm/mixed-app.d: Adjust expected disassembly a little.
2005-05-18 07:40:12 +02:00
|
|
|
|
imm |= (given & 0x000000ffu);
|
|
|
|
|
|
imm |= (given & 0x00007000u) >> 4;
|
|
|
|
|
|
imm |= (given & 0x04000000u) >> 15;
|
|
|
|
|
|
imm |= (given & 0x000f0000u) >> 4;
|
2009-06-30 13:57:05 +02:00
|
|
|
|
func (stream, "#%u", imm);
|
|
|
|
|
|
value_in_comment = imm;
|
include/elf:
* arm.h: Import complete list of official relocation names
and numbers from AAELF. Define FAKE_RELOCs for old names.
Remove a few old names no longer used anywhere.
bfd:
* elf32-arm.c: Wherever possible, use official reloc names
from AAELF.
(elf32_arm_howto_table, elf32_arm_tls_gd32_howto)
(elf32_arm_tls_ldo32_howto, elf32_arm_tls_ldm32_howto)
(elf32_arm_tls_le32_howto, elf32_arm_tls_ie32_howto)
(elf32_arm_vtinherit_howto, elf32_arm_vtentry_howto)
(elf32_arm_pc11_howto, elf32_arm_thm_pc9_howto, elf32_arm_got_prel)
(elf32_arm_r_howto): Replace with elf32_arm_howto_table_1,
elf32_arm_howto_table_2, and elf32_arm_howto_table_3.
Add many new relocations from AAELF.
(elf32_arm_howto_from_type): Update to match.
(elf32_arm_reloc_map): Add entries for R_ARM_THM_JUMP24,
R_ARM_THM_JUMP11, R_ARM_THM_JUMP19, R_ARM_THM_JUMP8,
R_ARM_THM_JUMP6, R_ARM_GNU_VTINHERIT, and R_ARM_GNU_VTENTRY.
(elf32_arm_reloc_type_lookup): Use elf32_arm_howto_from_type.
(elf32_arm_final_link_relocate): Add support for
R_ARM_THM_JUMP24, R_ARM_THM_JUMP19, R_ARM_THM_JUMP6. Remove
case entries redundant with default.
* reloc.c: Reorganize ARM relocations. Add Thumb
assembler-internal relocations BFD_RELOC_ARM_T32_OFFSET_U8,
BFD_RELOC_ARM_T32_OFFSET_IMM, BFD_RELOC_ARM_T32_IMMEDIATE.
Add visible relocations BFD_RELOC_THUMB_PCREL_BRANCH7,
BFD_RELOC_THUMB_BRANCH20, BFD_RELOC_THUMB_BRANCH25.
Delete unused relocations BFD_RELOC_ARM_GOT12, BFD_RELOC_ARM_COPY.
* bfd-in2.h, libbfd.h: Regenerate.
opcodes:
* arm-dis.c (thumb_opcodes): Add disassembly for V6T2 16-bit
instructions. Adjust disassembly of some opcodes to match
unified syntax.
(thumb32_opcodes): New table.
(print_insn_thumb): Rename print_insn_thumb16; don't handle
two-halfword branches here.
(print_insn_thumb32): New function.
(print_insn): Choose among print_insn_arm, print_insn_thumb16,
and print_insn_thumb32. Be consistent about order of
halfwords when printing 32-bit instructions.
gas:
* hash.c (hash_lookup): Add len parameter. All callers changed.
(hash_find_n): New interface.
* hash.h: Prototype hash_find_n.
* sb.c: Include as.h.
(scrub_from_sb, sb_to_scrub, scrub_position): New statics.
(sb_scrub_and_add_sb): New interface.
* sb.h: Prototype sb_scrub_and_add_sb.
* input-scrub.c (input_scrub_include_sb): Use sb_scrub_and_add_sb.
* config/tc-arm.h (TC_FORCE_RELOCATION_LOCAL): Remove
reference to BFD_RELOC_ARM_GOT12 which is never generated.
* config/tc-arm.c: Rewrite, adding Thumb-2 support.
gas/testsuite:
* gas/arm/arm.exp: Convert all existing "gas_test" tests to
"run_dump_test" tests. Run more tests unconditionally. Run new tests.
* gas/arm/arch4t.s, gas/arm/arch6zk.s, gas/arm/arm3.s, gas/arm/arm6.s
* gas/arm/arm7dm.s, gas/arm/bignum1.s, gas/arm/float.s
* gas/arm/immed.s, gas/arm/iwmmxt.s, gas/arm/offset.s, gas/arm/thumb.s:
Adjust to work as a dump test.
* gas/arm/arch4t.d, gas/arm/arch6zk.d, gas/arm/arm3.d, gas/arm/arm6.d
* gas/arm/arm7dm.d, gas/arm/bignum1.d, gas/arm/float.d
* gas/arm/immed.d, gas/arm/iwmmxt.d, gas/arm/offset.d, gas/arm/thumb.d:
New files.
* gas/arm/armv1-bad.l, gas/arm/armv1-bad.s: Remove tests for
diagnostics that don't happen in the first pass anymore.
* gas/arm/iwmmxt-bad.l, gas/arm/r15-bad.l, gas/arm/req.l
* gas/arm/vfp-bad.l:
Update expected diagnostics.
* gas/arm/pic.d: Update expected reloc name.
* gas/arm/thumbv6.d: CPY no longer appears in disassembly.
* gas/arm/r15-bad.s: Avoid two-argument mul.
* gas/arm/req.s: Adjust comments.
* gas/arm/maverick.d, gas/arm/maverick.s: Avoid inappropriate
use of PC.
* gas/arm/macro-1.d, gas/arm/macro1.s
* gas/arm/t16-bad.l, gas/arm/t16-bad.s
* gas/arm/tcompat.d, gas/arm/tcompat.s
* gas/arm/tcompat2.d, gas/arm/tcompat2.s
* gas/arm/thumb32.d, gas/arm/thumb32.s
New test pair.
ld/testsuite:
* ld-arm/mixed-app.d: Adjust expected disassembly a little.
2005-05-18 07:40:12 +02:00
|
|
|
|
}
|
|
|
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
|
|
case 'K':
|
|
|
|
|
|
{
|
|
|
|
|
|
unsigned int imm = 0;
|
2009-06-30 13:57:05 +02:00
|
|
|
|
|
include/elf:
* arm.h: Import complete list of official relocation names
and numbers from AAELF. Define FAKE_RELOCs for old names.
Remove a few old names no longer used anywhere.
bfd:
* elf32-arm.c: Wherever possible, use official reloc names
from AAELF.
(elf32_arm_howto_table, elf32_arm_tls_gd32_howto)
(elf32_arm_tls_ldo32_howto, elf32_arm_tls_ldm32_howto)
(elf32_arm_tls_le32_howto, elf32_arm_tls_ie32_howto)
(elf32_arm_vtinherit_howto, elf32_arm_vtentry_howto)
(elf32_arm_pc11_howto, elf32_arm_thm_pc9_howto, elf32_arm_got_prel)
(elf32_arm_r_howto): Replace with elf32_arm_howto_table_1,
elf32_arm_howto_table_2, and elf32_arm_howto_table_3.
Add many new relocations from AAELF.
(elf32_arm_howto_from_type): Update to match.
(elf32_arm_reloc_map): Add entries for R_ARM_THM_JUMP24,
R_ARM_THM_JUMP11, R_ARM_THM_JUMP19, R_ARM_THM_JUMP8,
R_ARM_THM_JUMP6, R_ARM_GNU_VTINHERIT, and R_ARM_GNU_VTENTRY.
(elf32_arm_reloc_type_lookup): Use elf32_arm_howto_from_type.
(elf32_arm_final_link_relocate): Add support for
R_ARM_THM_JUMP24, R_ARM_THM_JUMP19, R_ARM_THM_JUMP6. Remove
case entries redundant with default.
* reloc.c: Reorganize ARM relocations. Add Thumb
assembler-internal relocations BFD_RELOC_ARM_T32_OFFSET_U8,
BFD_RELOC_ARM_T32_OFFSET_IMM, BFD_RELOC_ARM_T32_IMMEDIATE.
Add visible relocations BFD_RELOC_THUMB_PCREL_BRANCH7,
BFD_RELOC_THUMB_BRANCH20, BFD_RELOC_THUMB_BRANCH25.
Delete unused relocations BFD_RELOC_ARM_GOT12, BFD_RELOC_ARM_COPY.
* bfd-in2.h, libbfd.h: Regenerate.
opcodes:
* arm-dis.c (thumb_opcodes): Add disassembly for V6T2 16-bit
instructions. Adjust disassembly of some opcodes to match
unified syntax.
(thumb32_opcodes): New table.
(print_insn_thumb): Rename print_insn_thumb16; don't handle
two-halfword branches here.
(print_insn_thumb32): New function.
(print_insn): Choose among print_insn_arm, print_insn_thumb16,
and print_insn_thumb32. Be consistent about order of
halfwords when printing 32-bit instructions.
gas:
* hash.c (hash_lookup): Add len parameter. All callers changed.
(hash_find_n): New interface.
* hash.h: Prototype hash_find_n.
* sb.c: Include as.h.
(scrub_from_sb, sb_to_scrub, scrub_position): New statics.
(sb_scrub_and_add_sb): New interface.
* sb.h: Prototype sb_scrub_and_add_sb.
* input-scrub.c (input_scrub_include_sb): Use sb_scrub_and_add_sb.
* config/tc-arm.h (TC_FORCE_RELOCATION_LOCAL): Remove
reference to BFD_RELOC_ARM_GOT12 which is never generated.
* config/tc-arm.c: Rewrite, adding Thumb-2 support.
gas/testsuite:
* gas/arm/arm.exp: Convert all existing "gas_test" tests to
"run_dump_test" tests. Run more tests unconditionally. Run new tests.
* gas/arm/arch4t.s, gas/arm/arch6zk.s, gas/arm/arm3.s, gas/arm/arm6.s
* gas/arm/arm7dm.s, gas/arm/bignum1.s, gas/arm/float.s
* gas/arm/immed.s, gas/arm/iwmmxt.s, gas/arm/offset.s, gas/arm/thumb.s:
Adjust to work as a dump test.
* gas/arm/arch4t.d, gas/arm/arch6zk.d, gas/arm/arm3.d, gas/arm/arm6.d
* gas/arm/arm7dm.d, gas/arm/bignum1.d, gas/arm/float.d
* gas/arm/immed.d, gas/arm/iwmmxt.d, gas/arm/offset.d, gas/arm/thumb.d:
New files.
* gas/arm/armv1-bad.l, gas/arm/armv1-bad.s: Remove tests for
diagnostics that don't happen in the first pass anymore.
* gas/arm/iwmmxt-bad.l, gas/arm/r15-bad.l, gas/arm/req.l
* gas/arm/vfp-bad.l:
Update expected diagnostics.
* gas/arm/pic.d: Update expected reloc name.
* gas/arm/thumbv6.d: CPY no longer appears in disassembly.
* gas/arm/r15-bad.s: Avoid two-argument mul.
* gas/arm/req.s: Adjust comments.
* gas/arm/maverick.d, gas/arm/maverick.s: Avoid inappropriate
use of PC.
* gas/arm/macro-1.d, gas/arm/macro1.s
* gas/arm/t16-bad.l, gas/arm/t16-bad.s
* gas/arm/tcompat.d, gas/arm/tcompat.s
* gas/arm/tcompat2.d, gas/arm/tcompat2.s
* gas/arm/thumb32.d, gas/arm/thumb32.s
New test pair.
ld/testsuite:
* ld-arm/mixed-app.d: Adjust expected disassembly a little.
2005-05-18 07:40:12 +02:00
|
|
|
|
imm |= (given & 0x000f0000u) >> 16;
|
|
|
|
|
|
imm |= (given & 0x00000ff0u) >> 0;
|
|
|
|
|
|
imm |= (given & 0x0000000fu) << 12;
|
2009-06-30 13:57:05 +02:00
|
|
|
|
func (stream, "#%u", imm);
|
|
|
|
|
|
value_in_comment = imm;
|
include/elf:
* arm.h: Import complete list of official relocation names
and numbers from AAELF. Define FAKE_RELOCs for old names.
Remove a few old names no longer used anywhere.
bfd:
* elf32-arm.c: Wherever possible, use official reloc names
from AAELF.
(elf32_arm_howto_table, elf32_arm_tls_gd32_howto)
(elf32_arm_tls_ldo32_howto, elf32_arm_tls_ldm32_howto)
(elf32_arm_tls_le32_howto, elf32_arm_tls_ie32_howto)
(elf32_arm_vtinherit_howto, elf32_arm_vtentry_howto)
(elf32_arm_pc11_howto, elf32_arm_thm_pc9_howto, elf32_arm_got_prel)
(elf32_arm_r_howto): Replace with elf32_arm_howto_table_1,
elf32_arm_howto_table_2, and elf32_arm_howto_table_3.
Add many new relocations from AAELF.
(elf32_arm_howto_from_type): Update to match.
(elf32_arm_reloc_map): Add entries for R_ARM_THM_JUMP24,
R_ARM_THM_JUMP11, R_ARM_THM_JUMP19, R_ARM_THM_JUMP8,
R_ARM_THM_JUMP6, R_ARM_GNU_VTINHERIT, and R_ARM_GNU_VTENTRY.
(elf32_arm_reloc_type_lookup): Use elf32_arm_howto_from_type.
(elf32_arm_final_link_relocate): Add support for
R_ARM_THM_JUMP24, R_ARM_THM_JUMP19, R_ARM_THM_JUMP6. Remove
case entries redundant with default.
* reloc.c: Reorganize ARM relocations. Add Thumb
assembler-internal relocations BFD_RELOC_ARM_T32_OFFSET_U8,
BFD_RELOC_ARM_T32_OFFSET_IMM, BFD_RELOC_ARM_T32_IMMEDIATE.
Add visible relocations BFD_RELOC_THUMB_PCREL_BRANCH7,
BFD_RELOC_THUMB_BRANCH20, BFD_RELOC_THUMB_BRANCH25.
Delete unused relocations BFD_RELOC_ARM_GOT12, BFD_RELOC_ARM_COPY.
* bfd-in2.h, libbfd.h: Regenerate.
opcodes:
* arm-dis.c (thumb_opcodes): Add disassembly for V6T2 16-bit
instructions. Adjust disassembly of some opcodes to match
unified syntax.
(thumb32_opcodes): New table.
(print_insn_thumb): Rename print_insn_thumb16; don't handle
two-halfword branches here.
(print_insn_thumb32): New function.
(print_insn): Choose among print_insn_arm, print_insn_thumb16,
and print_insn_thumb32. Be consistent about order of
halfwords when printing 32-bit instructions.
gas:
* hash.c (hash_lookup): Add len parameter. All callers changed.
(hash_find_n): New interface.
* hash.h: Prototype hash_find_n.
* sb.c: Include as.h.
(scrub_from_sb, sb_to_scrub, scrub_position): New statics.
(sb_scrub_and_add_sb): New interface.
* sb.h: Prototype sb_scrub_and_add_sb.
* input-scrub.c (input_scrub_include_sb): Use sb_scrub_and_add_sb.
* config/tc-arm.h (TC_FORCE_RELOCATION_LOCAL): Remove
reference to BFD_RELOC_ARM_GOT12 which is never generated.
* config/tc-arm.c: Rewrite, adding Thumb-2 support.
gas/testsuite:
* gas/arm/arm.exp: Convert all existing "gas_test" tests to
"run_dump_test" tests. Run more tests unconditionally. Run new tests.
* gas/arm/arch4t.s, gas/arm/arch6zk.s, gas/arm/arm3.s, gas/arm/arm6.s
* gas/arm/arm7dm.s, gas/arm/bignum1.s, gas/arm/float.s
* gas/arm/immed.s, gas/arm/iwmmxt.s, gas/arm/offset.s, gas/arm/thumb.s:
Adjust to work as a dump test.
* gas/arm/arch4t.d, gas/arm/arch6zk.d, gas/arm/arm3.d, gas/arm/arm6.d
* gas/arm/arm7dm.d, gas/arm/bignum1.d, gas/arm/float.d
* gas/arm/immed.d, gas/arm/iwmmxt.d, gas/arm/offset.d, gas/arm/thumb.d:
New files.
* gas/arm/armv1-bad.l, gas/arm/armv1-bad.s: Remove tests for
diagnostics that don't happen in the first pass anymore.
* gas/arm/iwmmxt-bad.l, gas/arm/r15-bad.l, gas/arm/req.l
* gas/arm/vfp-bad.l:
Update expected diagnostics.
* gas/arm/pic.d: Update expected reloc name.
* gas/arm/thumbv6.d: CPY no longer appears in disassembly.
* gas/arm/r15-bad.s: Avoid two-argument mul.
* gas/arm/req.s: Adjust comments.
* gas/arm/maverick.d, gas/arm/maverick.s: Avoid inappropriate
use of PC.
* gas/arm/macro-1.d, gas/arm/macro1.s
* gas/arm/t16-bad.l, gas/arm/t16-bad.s
* gas/arm/tcompat.d, gas/arm/tcompat.s
* gas/arm/tcompat2.d, gas/arm/tcompat2.s
* gas/arm/thumb32.d, gas/arm/thumb32.s
New test pair.
ld/testsuite:
* ld-arm/mixed-app.d: Adjust expected disassembly a little.
2005-05-18 07:40:12 +02:00
|
|
|
|
}
|
|
|
|
|
|
break;
|
|
|
|
|
|
|
2013-09-04 09:59:33 +02:00
|
|
|
|
case 'H':
|
|
|
|
|
|
{
|
|
|
|
|
|
unsigned int imm = 0;
|
|
|
|
|
|
|
|
|
|
|
|
imm |= (given & 0x000f0000u) >> 4;
|
|
|
|
|
|
imm |= (given & 0x00000fffu) >> 0;
|
|
|
|
|
|
func (stream, "#%u", imm);
|
|
|
|
|
|
value_in_comment = imm;
|
|
|
|
|
|
}
|
|
|
|
|
|
break;
|
|
|
|
|
|
|
2010-09-23 17:52:19 +02:00
|
|
|
|
case 'V':
|
|
|
|
|
|
{
|
|
|
|
|
|
unsigned int imm = 0;
|
|
|
|
|
|
|
|
|
|
|
|
imm |= (given & 0x00000fffu);
|
|
|
|
|
|
imm |= (given & 0x000f0000u) >> 4;
|
|
|
|
|
|
func (stream, "#%u", imm);
|
|
|
|
|
|
value_in_comment = imm;
|
|
|
|
|
|
}
|
|
|
|
|
|
break;
|
|
|
|
|
|
|
include/elf:
* arm.h: Import complete list of official relocation names
and numbers from AAELF. Define FAKE_RELOCs for old names.
Remove a few old names no longer used anywhere.
bfd:
* elf32-arm.c: Wherever possible, use official reloc names
from AAELF.
(elf32_arm_howto_table, elf32_arm_tls_gd32_howto)
(elf32_arm_tls_ldo32_howto, elf32_arm_tls_ldm32_howto)
(elf32_arm_tls_le32_howto, elf32_arm_tls_ie32_howto)
(elf32_arm_vtinherit_howto, elf32_arm_vtentry_howto)
(elf32_arm_pc11_howto, elf32_arm_thm_pc9_howto, elf32_arm_got_prel)
(elf32_arm_r_howto): Replace with elf32_arm_howto_table_1,
elf32_arm_howto_table_2, and elf32_arm_howto_table_3.
Add many new relocations from AAELF.
(elf32_arm_howto_from_type): Update to match.
(elf32_arm_reloc_map): Add entries for R_ARM_THM_JUMP24,
R_ARM_THM_JUMP11, R_ARM_THM_JUMP19, R_ARM_THM_JUMP8,
R_ARM_THM_JUMP6, R_ARM_GNU_VTINHERIT, and R_ARM_GNU_VTENTRY.
(elf32_arm_reloc_type_lookup): Use elf32_arm_howto_from_type.
(elf32_arm_final_link_relocate): Add support for
R_ARM_THM_JUMP24, R_ARM_THM_JUMP19, R_ARM_THM_JUMP6. Remove
case entries redundant with default.
* reloc.c: Reorganize ARM relocations. Add Thumb
assembler-internal relocations BFD_RELOC_ARM_T32_OFFSET_U8,
BFD_RELOC_ARM_T32_OFFSET_IMM, BFD_RELOC_ARM_T32_IMMEDIATE.
Add visible relocations BFD_RELOC_THUMB_PCREL_BRANCH7,
BFD_RELOC_THUMB_BRANCH20, BFD_RELOC_THUMB_BRANCH25.
Delete unused relocations BFD_RELOC_ARM_GOT12, BFD_RELOC_ARM_COPY.
* bfd-in2.h, libbfd.h: Regenerate.
opcodes:
* arm-dis.c (thumb_opcodes): Add disassembly for V6T2 16-bit
instructions. Adjust disassembly of some opcodes to match
unified syntax.
(thumb32_opcodes): New table.
(print_insn_thumb): Rename print_insn_thumb16; don't handle
two-halfword branches here.
(print_insn_thumb32): New function.
(print_insn): Choose among print_insn_arm, print_insn_thumb16,
and print_insn_thumb32. Be consistent about order of
halfwords when printing 32-bit instructions.
gas:
* hash.c (hash_lookup): Add len parameter. All callers changed.
(hash_find_n): New interface.
* hash.h: Prototype hash_find_n.
* sb.c: Include as.h.
(scrub_from_sb, sb_to_scrub, scrub_position): New statics.
(sb_scrub_and_add_sb): New interface.
* sb.h: Prototype sb_scrub_and_add_sb.
* input-scrub.c (input_scrub_include_sb): Use sb_scrub_and_add_sb.
* config/tc-arm.h (TC_FORCE_RELOCATION_LOCAL): Remove
reference to BFD_RELOC_ARM_GOT12 which is never generated.
* config/tc-arm.c: Rewrite, adding Thumb-2 support.
gas/testsuite:
* gas/arm/arm.exp: Convert all existing "gas_test" tests to
"run_dump_test" tests. Run more tests unconditionally. Run new tests.
* gas/arm/arch4t.s, gas/arm/arch6zk.s, gas/arm/arm3.s, gas/arm/arm6.s
* gas/arm/arm7dm.s, gas/arm/bignum1.s, gas/arm/float.s
* gas/arm/immed.s, gas/arm/iwmmxt.s, gas/arm/offset.s, gas/arm/thumb.s:
Adjust to work as a dump test.
* gas/arm/arch4t.d, gas/arm/arch6zk.d, gas/arm/arm3.d, gas/arm/arm6.d
* gas/arm/arm7dm.d, gas/arm/bignum1.d, gas/arm/float.d
* gas/arm/immed.d, gas/arm/iwmmxt.d, gas/arm/offset.d, gas/arm/thumb.d:
New files.
* gas/arm/armv1-bad.l, gas/arm/armv1-bad.s: Remove tests for
diagnostics that don't happen in the first pass anymore.
* gas/arm/iwmmxt-bad.l, gas/arm/r15-bad.l, gas/arm/req.l
* gas/arm/vfp-bad.l:
Update expected diagnostics.
* gas/arm/pic.d: Update expected reloc name.
* gas/arm/thumbv6.d: CPY no longer appears in disassembly.
* gas/arm/r15-bad.s: Avoid two-argument mul.
* gas/arm/req.s: Adjust comments.
* gas/arm/maverick.d, gas/arm/maverick.s: Avoid inappropriate
use of PC.
* gas/arm/macro-1.d, gas/arm/macro1.s
* gas/arm/t16-bad.l, gas/arm/t16-bad.s
* gas/arm/tcompat.d, gas/arm/tcompat.s
* gas/arm/tcompat2.d, gas/arm/tcompat2.s
* gas/arm/thumb32.d, gas/arm/thumb32.s
New test pair.
ld/testsuite:
* ld-arm/mixed-app.d: Adjust expected disassembly a little.
2005-05-18 07:40:12 +02:00
|
|
|
|
case 'S':
|
|
|
|
|
|
{
|
|
|
|
|
|
unsigned int reg = (given & 0x0000000fu);
|
|
|
|
|
|
unsigned int stp = (given & 0x00000030u) >> 4;
|
|
|
|
|
|
unsigned int imm = 0;
|
|
|
|
|
|
imm |= (given & 0x000000c0u) >> 6;
|
|
|
|
|
|
imm |= (given & 0x00007000u) >> 10;
|
|
|
|
|
|
|
|
|
|
|
|
func (stream, "%s", arm_regnames[reg]);
|
|
|
|
|
|
switch (stp)
|
|
|
|
|
|
{
|
|
|
|
|
|
case 0:
|
|
|
|
|
|
if (imm > 0)
|
|
|
|
|
|
func (stream, ", lsl #%u", imm);
|
|
|
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
|
|
case 1:
|
|
|
|
|
|
if (imm == 0)
|
|
|
|
|
|
imm = 32;
|
|
|
|
|
|
func (stream, ", lsr #%u", imm);
|
|
|
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
|
|
case 2:
|
|
|
|
|
|
if (imm == 0)
|
|
|
|
|
|
imm = 32;
|
|
|
|
|
|
func (stream, ", asr #%u", imm);
|
|
|
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
|
|
case 3:
|
|
|
|
|
|
if (imm == 0)
|
|
|
|
|
|
func (stream, ", rrx");
|
|
|
|
|
|
else
|
|
|
|
|
|
func (stream, ", ror #%u", imm);
|
|
|
|
|
|
}
|
|
|
|
|
|
}
|
|
|
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
|
|
case 'a':
|
|
|
|
|
|
{
|
|
|
|
|
|
unsigned int Rn = (given & 0x000f0000) >> 16;
|
2009-11-11 10:44:45 +01:00
|
|
|
|
unsigned int U = ! NEGATIVE_BIT_SET;
|
include/elf:
* arm.h: Import complete list of official relocation names
and numbers from AAELF. Define FAKE_RELOCs for old names.
Remove a few old names no longer used anywhere.
bfd:
* elf32-arm.c: Wherever possible, use official reloc names
from AAELF.
(elf32_arm_howto_table, elf32_arm_tls_gd32_howto)
(elf32_arm_tls_ldo32_howto, elf32_arm_tls_ldm32_howto)
(elf32_arm_tls_le32_howto, elf32_arm_tls_ie32_howto)
(elf32_arm_vtinherit_howto, elf32_arm_vtentry_howto)
(elf32_arm_pc11_howto, elf32_arm_thm_pc9_howto, elf32_arm_got_prel)
(elf32_arm_r_howto): Replace with elf32_arm_howto_table_1,
elf32_arm_howto_table_2, and elf32_arm_howto_table_3.
Add many new relocations from AAELF.
(elf32_arm_howto_from_type): Update to match.
(elf32_arm_reloc_map): Add entries for R_ARM_THM_JUMP24,
R_ARM_THM_JUMP11, R_ARM_THM_JUMP19, R_ARM_THM_JUMP8,
R_ARM_THM_JUMP6, R_ARM_GNU_VTINHERIT, and R_ARM_GNU_VTENTRY.
(elf32_arm_reloc_type_lookup): Use elf32_arm_howto_from_type.
(elf32_arm_final_link_relocate): Add support for
R_ARM_THM_JUMP24, R_ARM_THM_JUMP19, R_ARM_THM_JUMP6. Remove
case entries redundant with default.
* reloc.c: Reorganize ARM relocations. Add Thumb
assembler-internal relocations BFD_RELOC_ARM_T32_OFFSET_U8,
BFD_RELOC_ARM_T32_OFFSET_IMM, BFD_RELOC_ARM_T32_IMMEDIATE.
Add visible relocations BFD_RELOC_THUMB_PCREL_BRANCH7,
BFD_RELOC_THUMB_BRANCH20, BFD_RELOC_THUMB_BRANCH25.
Delete unused relocations BFD_RELOC_ARM_GOT12, BFD_RELOC_ARM_COPY.
* bfd-in2.h, libbfd.h: Regenerate.
opcodes:
* arm-dis.c (thumb_opcodes): Add disassembly for V6T2 16-bit
instructions. Adjust disassembly of some opcodes to match
unified syntax.
(thumb32_opcodes): New table.
(print_insn_thumb): Rename print_insn_thumb16; don't handle
two-halfword branches here.
(print_insn_thumb32): New function.
(print_insn): Choose among print_insn_arm, print_insn_thumb16,
and print_insn_thumb32. Be consistent about order of
halfwords when printing 32-bit instructions.
gas:
* hash.c (hash_lookup): Add len parameter. All callers changed.
(hash_find_n): New interface.
* hash.h: Prototype hash_find_n.
* sb.c: Include as.h.
(scrub_from_sb, sb_to_scrub, scrub_position): New statics.
(sb_scrub_and_add_sb): New interface.
* sb.h: Prototype sb_scrub_and_add_sb.
* input-scrub.c (input_scrub_include_sb): Use sb_scrub_and_add_sb.
* config/tc-arm.h (TC_FORCE_RELOCATION_LOCAL): Remove
reference to BFD_RELOC_ARM_GOT12 which is never generated.
* config/tc-arm.c: Rewrite, adding Thumb-2 support.
gas/testsuite:
* gas/arm/arm.exp: Convert all existing "gas_test" tests to
"run_dump_test" tests. Run more tests unconditionally. Run new tests.
* gas/arm/arch4t.s, gas/arm/arch6zk.s, gas/arm/arm3.s, gas/arm/arm6.s
* gas/arm/arm7dm.s, gas/arm/bignum1.s, gas/arm/float.s
* gas/arm/immed.s, gas/arm/iwmmxt.s, gas/arm/offset.s, gas/arm/thumb.s:
Adjust to work as a dump test.
* gas/arm/arch4t.d, gas/arm/arch6zk.d, gas/arm/arm3.d, gas/arm/arm6.d
* gas/arm/arm7dm.d, gas/arm/bignum1.d, gas/arm/float.d
* gas/arm/immed.d, gas/arm/iwmmxt.d, gas/arm/offset.d, gas/arm/thumb.d:
New files.
* gas/arm/armv1-bad.l, gas/arm/armv1-bad.s: Remove tests for
diagnostics that don't happen in the first pass anymore.
* gas/arm/iwmmxt-bad.l, gas/arm/r15-bad.l, gas/arm/req.l
* gas/arm/vfp-bad.l:
Update expected diagnostics.
* gas/arm/pic.d: Update expected reloc name.
* gas/arm/thumbv6.d: CPY no longer appears in disassembly.
* gas/arm/r15-bad.s: Avoid two-argument mul.
* gas/arm/req.s: Adjust comments.
* gas/arm/maverick.d, gas/arm/maverick.s: Avoid inappropriate
use of PC.
* gas/arm/macro-1.d, gas/arm/macro1.s
* gas/arm/t16-bad.l, gas/arm/t16-bad.s
* gas/arm/tcompat.d, gas/arm/tcompat.s
* gas/arm/tcompat2.d, gas/arm/tcompat2.s
* gas/arm/thumb32.d, gas/arm/thumb32.s
New test pair.
ld/testsuite:
* ld-arm/mixed-app.d: Adjust expected disassembly a little.
2005-05-18 07:40:12 +02:00
|
|
|
|
unsigned int op = (given & 0x00000f00) >> 8;
|
|
|
|
|
|
unsigned int i12 = (given & 0x00000fff);
|
|
|
|
|
|
unsigned int i8 = (given & 0x000000ff);
|
|
|
|
|
|
bfd_boolean writeback = FALSE, postind = FALSE;
|
2011-06-03 12:04:03 +02:00
|
|
|
|
bfd_vma offset = 0;
|
include/elf:
* arm.h: Import complete list of official relocation names
and numbers from AAELF. Define FAKE_RELOCs for old names.
Remove a few old names no longer used anywhere.
bfd:
* elf32-arm.c: Wherever possible, use official reloc names
from AAELF.
(elf32_arm_howto_table, elf32_arm_tls_gd32_howto)
(elf32_arm_tls_ldo32_howto, elf32_arm_tls_ldm32_howto)
(elf32_arm_tls_le32_howto, elf32_arm_tls_ie32_howto)
(elf32_arm_vtinherit_howto, elf32_arm_vtentry_howto)
(elf32_arm_pc11_howto, elf32_arm_thm_pc9_howto, elf32_arm_got_prel)
(elf32_arm_r_howto): Replace with elf32_arm_howto_table_1,
elf32_arm_howto_table_2, and elf32_arm_howto_table_3.
Add many new relocations from AAELF.
(elf32_arm_howto_from_type): Update to match.
(elf32_arm_reloc_map): Add entries for R_ARM_THM_JUMP24,
R_ARM_THM_JUMP11, R_ARM_THM_JUMP19, R_ARM_THM_JUMP8,
R_ARM_THM_JUMP6, R_ARM_GNU_VTINHERIT, and R_ARM_GNU_VTENTRY.
(elf32_arm_reloc_type_lookup): Use elf32_arm_howto_from_type.
(elf32_arm_final_link_relocate): Add support for
R_ARM_THM_JUMP24, R_ARM_THM_JUMP19, R_ARM_THM_JUMP6. Remove
case entries redundant with default.
* reloc.c: Reorganize ARM relocations. Add Thumb
assembler-internal relocations BFD_RELOC_ARM_T32_OFFSET_U8,
BFD_RELOC_ARM_T32_OFFSET_IMM, BFD_RELOC_ARM_T32_IMMEDIATE.
Add visible relocations BFD_RELOC_THUMB_PCREL_BRANCH7,
BFD_RELOC_THUMB_BRANCH20, BFD_RELOC_THUMB_BRANCH25.
Delete unused relocations BFD_RELOC_ARM_GOT12, BFD_RELOC_ARM_COPY.
* bfd-in2.h, libbfd.h: Regenerate.
opcodes:
* arm-dis.c (thumb_opcodes): Add disassembly for V6T2 16-bit
instructions. Adjust disassembly of some opcodes to match
unified syntax.
(thumb32_opcodes): New table.
(print_insn_thumb): Rename print_insn_thumb16; don't handle
two-halfword branches here.
(print_insn_thumb32): New function.
(print_insn): Choose among print_insn_arm, print_insn_thumb16,
and print_insn_thumb32. Be consistent about order of
halfwords when printing 32-bit instructions.
gas:
* hash.c (hash_lookup): Add len parameter. All callers changed.
(hash_find_n): New interface.
* hash.h: Prototype hash_find_n.
* sb.c: Include as.h.
(scrub_from_sb, sb_to_scrub, scrub_position): New statics.
(sb_scrub_and_add_sb): New interface.
* sb.h: Prototype sb_scrub_and_add_sb.
* input-scrub.c (input_scrub_include_sb): Use sb_scrub_and_add_sb.
* config/tc-arm.h (TC_FORCE_RELOCATION_LOCAL): Remove
reference to BFD_RELOC_ARM_GOT12 which is never generated.
* config/tc-arm.c: Rewrite, adding Thumb-2 support.
gas/testsuite:
* gas/arm/arm.exp: Convert all existing "gas_test" tests to
"run_dump_test" tests. Run more tests unconditionally. Run new tests.
* gas/arm/arch4t.s, gas/arm/arch6zk.s, gas/arm/arm3.s, gas/arm/arm6.s
* gas/arm/arm7dm.s, gas/arm/bignum1.s, gas/arm/float.s
* gas/arm/immed.s, gas/arm/iwmmxt.s, gas/arm/offset.s, gas/arm/thumb.s:
Adjust to work as a dump test.
* gas/arm/arch4t.d, gas/arm/arch6zk.d, gas/arm/arm3.d, gas/arm/arm6.d
* gas/arm/arm7dm.d, gas/arm/bignum1.d, gas/arm/float.d
* gas/arm/immed.d, gas/arm/iwmmxt.d, gas/arm/offset.d, gas/arm/thumb.d:
New files.
* gas/arm/armv1-bad.l, gas/arm/armv1-bad.s: Remove tests for
diagnostics that don't happen in the first pass anymore.
* gas/arm/iwmmxt-bad.l, gas/arm/r15-bad.l, gas/arm/req.l
* gas/arm/vfp-bad.l:
Update expected diagnostics.
* gas/arm/pic.d: Update expected reloc name.
* gas/arm/thumbv6.d: CPY no longer appears in disassembly.
* gas/arm/r15-bad.s: Avoid two-argument mul.
* gas/arm/req.s: Adjust comments.
* gas/arm/maverick.d, gas/arm/maverick.s: Avoid inappropriate
use of PC.
* gas/arm/macro-1.d, gas/arm/macro1.s
* gas/arm/t16-bad.l, gas/arm/t16-bad.s
* gas/arm/tcompat.d, gas/arm/tcompat.s
* gas/arm/tcompat2.d, gas/arm/tcompat2.s
* gas/arm/thumb32.d, gas/arm/thumb32.s
New test pair.
ld/testsuite:
* ld-arm/mixed-app.d: Adjust expected disassembly a little.
2005-05-18 07:40:12 +02:00
|
|
|
|
|
|
|
|
|
|
func (stream, "[%s", arm_regnames[Rn]);
|
2009-06-29 10:08:15 +02:00
|
|
|
|
if (U) /* 12-bit positive immediate offset. */
|
|
|
|
|
|
{
|
|
|
|
|
|
offset = i12;
|
|
|
|
|
|
if (Rn != 15)
|
|
|
|
|
|
value_in_comment = offset;
|
|
|
|
|
|
}
|
|
|
|
|
|
else if (Rn == 15) /* 12-bit negative immediate offset. */
|
|
|
|
|
|
offset = - (int) i12;
|
|
|
|
|
|
else if (op == 0x0) /* Shifted register offset. */
|
include/elf:
* arm.h: Import complete list of official relocation names
and numbers from AAELF. Define FAKE_RELOCs for old names.
Remove a few old names no longer used anywhere.
bfd:
* elf32-arm.c: Wherever possible, use official reloc names
from AAELF.
(elf32_arm_howto_table, elf32_arm_tls_gd32_howto)
(elf32_arm_tls_ldo32_howto, elf32_arm_tls_ldm32_howto)
(elf32_arm_tls_le32_howto, elf32_arm_tls_ie32_howto)
(elf32_arm_vtinherit_howto, elf32_arm_vtentry_howto)
(elf32_arm_pc11_howto, elf32_arm_thm_pc9_howto, elf32_arm_got_prel)
(elf32_arm_r_howto): Replace with elf32_arm_howto_table_1,
elf32_arm_howto_table_2, and elf32_arm_howto_table_3.
Add many new relocations from AAELF.
(elf32_arm_howto_from_type): Update to match.
(elf32_arm_reloc_map): Add entries for R_ARM_THM_JUMP24,
R_ARM_THM_JUMP11, R_ARM_THM_JUMP19, R_ARM_THM_JUMP8,
R_ARM_THM_JUMP6, R_ARM_GNU_VTINHERIT, and R_ARM_GNU_VTENTRY.
(elf32_arm_reloc_type_lookup): Use elf32_arm_howto_from_type.
(elf32_arm_final_link_relocate): Add support for
R_ARM_THM_JUMP24, R_ARM_THM_JUMP19, R_ARM_THM_JUMP6. Remove
case entries redundant with default.
* reloc.c: Reorganize ARM relocations. Add Thumb
assembler-internal relocations BFD_RELOC_ARM_T32_OFFSET_U8,
BFD_RELOC_ARM_T32_OFFSET_IMM, BFD_RELOC_ARM_T32_IMMEDIATE.
Add visible relocations BFD_RELOC_THUMB_PCREL_BRANCH7,
BFD_RELOC_THUMB_BRANCH20, BFD_RELOC_THUMB_BRANCH25.
Delete unused relocations BFD_RELOC_ARM_GOT12, BFD_RELOC_ARM_COPY.
* bfd-in2.h, libbfd.h: Regenerate.
opcodes:
* arm-dis.c (thumb_opcodes): Add disassembly for V6T2 16-bit
instructions. Adjust disassembly of some opcodes to match
unified syntax.
(thumb32_opcodes): New table.
(print_insn_thumb): Rename print_insn_thumb16; don't handle
two-halfword branches here.
(print_insn_thumb32): New function.
(print_insn): Choose among print_insn_arm, print_insn_thumb16,
and print_insn_thumb32. Be consistent about order of
halfwords when printing 32-bit instructions.
gas:
* hash.c (hash_lookup): Add len parameter. All callers changed.
(hash_find_n): New interface.
* hash.h: Prototype hash_find_n.
* sb.c: Include as.h.
(scrub_from_sb, sb_to_scrub, scrub_position): New statics.
(sb_scrub_and_add_sb): New interface.
* sb.h: Prototype sb_scrub_and_add_sb.
* input-scrub.c (input_scrub_include_sb): Use sb_scrub_and_add_sb.
* config/tc-arm.h (TC_FORCE_RELOCATION_LOCAL): Remove
reference to BFD_RELOC_ARM_GOT12 which is never generated.
* config/tc-arm.c: Rewrite, adding Thumb-2 support.
gas/testsuite:
* gas/arm/arm.exp: Convert all existing "gas_test" tests to
"run_dump_test" tests. Run more tests unconditionally. Run new tests.
* gas/arm/arch4t.s, gas/arm/arch6zk.s, gas/arm/arm3.s, gas/arm/arm6.s
* gas/arm/arm7dm.s, gas/arm/bignum1.s, gas/arm/float.s
* gas/arm/immed.s, gas/arm/iwmmxt.s, gas/arm/offset.s, gas/arm/thumb.s:
Adjust to work as a dump test.
* gas/arm/arch4t.d, gas/arm/arch6zk.d, gas/arm/arm3.d, gas/arm/arm6.d
* gas/arm/arm7dm.d, gas/arm/bignum1.d, gas/arm/float.d
* gas/arm/immed.d, gas/arm/iwmmxt.d, gas/arm/offset.d, gas/arm/thumb.d:
New files.
* gas/arm/armv1-bad.l, gas/arm/armv1-bad.s: Remove tests for
diagnostics that don't happen in the first pass anymore.
* gas/arm/iwmmxt-bad.l, gas/arm/r15-bad.l, gas/arm/req.l
* gas/arm/vfp-bad.l:
Update expected diagnostics.
* gas/arm/pic.d: Update expected reloc name.
* gas/arm/thumbv6.d: CPY no longer appears in disassembly.
* gas/arm/r15-bad.s: Avoid two-argument mul.
* gas/arm/req.s: Adjust comments.
* gas/arm/maverick.d, gas/arm/maverick.s: Avoid inappropriate
use of PC.
* gas/arm/macro-1.d, gas/arm/macro1.s
* gas/arm/t16-bad.l, gas/arm/t16-bad.s
* gas/arm/tcompat.d, gas/arm/tcompat.s
* gas/arm/tcompat2.d, gas/arm/tcompat2.s
* gas/arm/thumb32.d, gas/arm/thumb32.s
New test pair.
ld/testsuite:
* ld-arm/mixed-app.d: Adjust expected disassembly a little.
2005-05-18 07:40:12 +02:00
|
|
|
|
{
|
|
|
|
|
|
unsigned int Rm = (i8 & 0x0f);
|
|
|
|
|
|
unsigned int sh = (i8 & 0x30) >> 4;
|
2009-06-29 10:08:15 +02:00
|
|
|
|
|
include/elf:
* arm.h: Import complete list of official relocation names
and numbers from AAELF. Define FAKE_RELOCs for old names.
Remove a few old names no longer used anywhere.
bfd:
* elf32-arm.c: Wherever possible, use official reloc names
from AAELF.
(elf32_arm_howto_table, elf32_arm_tls_gd32_howto)
(elf32_arm_tls_ldo32_howto, elf32_arm_tls_ldm32_howto)
(elf32_arm_tls_le32_howto, elf32_arm_tls_ie32_howto)
(elf32_arm_vtinherit_howto, elf32_arm_vtentry_howto)
(elf32_arm_pc11_howto, elf32_arm_thm_pc9_howto, elf32_arm_got_prel)
(elf32_arm_r_howto): Replace with elf32_arm_howto_table_1,
elf32_arm_howto_table_2, and elf32_arm_howto_table_3.
Add many new relocations from AAELF.
(elf32_arm_howto_from_type): Update to match.
(elf32_arm_reloc_map): Add entries for R_ARM_THM_JUMP24,
R_ARM_THM_JUMP11, R_ARM_THM_JUMP19, R_ARM_THM_JUMP8,
R_ARM_THM_JUMP6, R_ARM_GNU_VTINHERIT, and R_ARM_GNU_VTENTRY.
(elf32_arm_reloc_type_lookup): Use elf32_arm_howto_from_type.
(elf32_arm_final_link_relocate): Add support for
R_ARM_THM_JUMP24, R_ARM_THM_JUMP19, R_ARM_THM_JUMP6. Remove
case entries redundant with default.
* reloc.c: Reorganize ARM relocations. Add Thumb
assembler-internal relocations BFD_RELOC_ARM_T32_OFFSET_U8,
BFD_RELOC_ARM_T32_OFFSET_IMM, BFD_RELOC_ARM_T32_IMMEDIATE.
Add visible relocations BFD_RELOC_THUMB_PCREL_BRANCH7,
BFD_RELOC_THUMB_BRANCH20, BFD_RELOC_THUMB_BRANCH25.
Delete unused relocations BFD_RELOC_ARM_GOT12, BFD_RELOC_ARM_COPY.
* bfd-in2.h, libbfd.h: Regenerate.
opcodes:
* arm-dis.c (thumb_opcodes): Add disassembly for V6T2 16-bit
instructions. Adjust disassembly of some opcodes to match
unified syntax.
(thumb32_opcodes): New table.
(print_insn_thumb): Rename print_insn_thumb16; don't handle
two-halfword branches here.
(print_insn_thumb32): New function.
(print_insn): Choose among print_insn_arm, print_insn_thumb16,
and print_insn_thumb32. Be consistent about order of
halfwords when printing 32-bit instructions.
gas:
* hash.c (hash_lookup): Add len parameter. All callers changed.
(hash_find_n): New interface.
* hash.h: Prototype hash_find_n.
* sb.c: Include as.h.
(scrub_from_sb, sb_to_scrub, scrub_position): New statics.
(sb_scrub_and_add_sb): New interface.
* sb.h: Prototype sb_scrub_and_add_sb.
* input-scrub.c (input_scrub_include_sb): Use sb_scrub_and_add_sb.
* config/tc-arm.h (TC_FORCE_RELOCATION_LOCAL): Remove
reference to BFD_RELOC_ARM_GOT12 which is never generated.
* config/tc-arm.c: Rewrite, adding Thumb-2 support.
gas/testsuite:
* gas/arm/arm.exp: Convert all existing "gas_test" tests to
"run_dump_test" tests. Run more tests unconditionally. Run new tests.
* gas/arm/arch4t.s, gas/arm/arch6zk.s, gas/arm/arm3.s, gas/arm/arm6.s
* gas/arm/arm7dm.s, gas/arm/bignum1.s, gas/arm/float.s
* gas/arm/immed.s, gas/arm/iwmmxt.s, gas/arm/offset.s, gas/arm/thumb.s:
Adjust to work as a dump test.
* gas/arm/arch4t.d, gas/arm/arch6zk.d, gas/arm/arm3.d, gas/arm/arm6.d
* gas/arm/arm7dm.d, gas/arm/bignum1.d, gas/arm/float.d
* gas/arm/immed.d, gas/arm/iwmmxt.d, gas/arm/offset.d, gas/arm/thumb.d:
New files.
* gas/arm/armv1-bad.l, gas/arm/armv1-bad.s: Remove tests for
diagnostics that don't happen in the first pass anymore.
* gas/arm/iwmmxt-bad.l, gas/arm/r15-bad.l, gas/arm/req.l
* gas/arm/vfp-bad.l:
Update expected diagnostics.
* gas/arm/pic.d: Update expected reloc name.
* gas/arm/thumbv6.d: CPY no longer appears in disassembly.
* gas/arm/r15-bad.s: Avoid two-argument mul.
* gas/arm/req.s: Adjust comments.
* gas/arm/maverick.d, gas/arm/maverick.s: Avoid inappropriate
use of PC.
* gas/arm/macro-1.d, gas/arm/macro1.s
* gas/arm/t16-bad.l, gas/arm/t16-bad.s
* gas/arm/tcompat.d, gas/arm/tcompat.s
* gas/arm/tcompat2.d, gas/arm/tcompat2.s
* gas/arm/thumb32.d, gas/arm/thumb32.s
New test pair.
ld/testsuite:
* ld-arm/mixed-app.d: Adjust expected disassembly a little.
2005-05-18 07:40:12 +02:00
|
|
|
|
func (stream, ", %s", arm_regnames[Rm]);
|
|
|
|
|
|
if (sh)
|
|
|
|
|
|
func (stream, ", lsl #%u", sh);
|
|
|
|
|
|
func (stream, "]");
|
|
|
|
|
|
break;
|
|
|
|
|
|
}
|
|
|
|
|
|
else switch (op)
|
|
|
|
|
|
{
|
2009-06-29 10:08:15 +02:00
|
|
|
|
case 0xE: /* 8-bit positive immediate offset. */
|
include/elf:
* arm.h: Import complete list of official relocation names
and numbers from AAELF. Define FAKE_RELOCs for old names.
Remove a few old names no longer used anywhere.
bfd:
* elf32-arm.c: Wherever possible, use official reloc names
from AAELF.
(elf32_arm_howto_table, elf32_arm_tls_gd32_howto)
(elf32_arm_tls_ldo32_howto, elf32_arm_tls_ldm32_howto)
(elf32_arm_tls_le32_howto, elf32_arm_tls_ie32_howto)
(elf32_arm_vtinherit_howto, elf32_arm_vtentry_howto)
(elf32_arm_pc11_howto, elf32_arm_thm_pc9_howto, elf32_arm_got_prel)
(elf32_arm_r_howto): Replace with elf32_arm_howto_table_1,
elf32_arm_howto_table_2, and elf32_arm_howto_table_3.
Add many new relocations from AAELF.
(elf32_arm_howto_from_type): Update to match.
(elf32_arm_reloc_map): Add entries for R_ARM_THM_JUMP24,
R_ARM_THM_JUMP11, R_ARM_THM_JUMP19, R_ARM_THM_JUMP8,
R_ARM_THM_JUMP6, R_ARM_GNU_VTINHERIT, and R_ARM_GNU_VTENTRY.
(elf32_arm_reloc_type_lookup): Use elf32_arm_howto_from_type.
(elf32_arm_final_link_relocate): Add support for
R_ARM_THM_JUMP24, R_ARM_THM_JUMP19, R_ARM_THM_JUMP6. Remove
case entries redundant with default.
* reloc.c: Reorganize ARM relocations. Add Thumb
assembler-internal relocations BFD_RELOC_ARM_T32_OFFSET_U8,
BFD_RELOC_ARM_T32_OFFSET_IMM, BFD_RELOC_ARM_T32_IMMEDIATE.
Add visible relocations BFD_RELOC_THUMB_PCREL_BRANCH7,
BFD_RELOC_THUMB_BRANCH20, BFD_RELOC_THUMB_BRANCH25.
Delete unused relocations BFD_RELOC_ARM_GOT12, BFD_RELOC_ARM_COPY.
* bfd-in2.h, libbfd.h: Regenerate.
opcodes:
* arm-dis.c (thumb_opcodes): Add disassembly for V6T2 16-bit
instructions. Adjust disassembly of some opcodes to match
unified syntax.
(thumb32_opcodes): New table.
(print_insn_thumb): Rename print_insn_thumb16; don't handle
two-halfword branches here.
(print_insn_thumb32): New function.
(print_insn): Choose among print_insn_arm, print_insn_thumb16,
and print_insn_thumb32. Be consistent about order of
halfwords when printing 32-bit instructions.
gas:
* hash.c (hash_lookup): Add len parameter. All callers changed.
(hash_find_n): New interface.
* hash.h: Prototype hash_find_n.
* sb.c: Include as.h.
(scrub_from_sb, sb_to_scrub, scrub_position): New statics.
(sb_scrub_and_add_sb): New interface.
* sb.h: Prototype sb_scrub_and_add_sb.
* input-scrub.c (input_scrub_include_sb): Use sb_scrub_and_add_sb.
* config/tc-arm.h (TC_FORCE_RELOCATION_LOCAL): Remove
reference to BFD_RELOC_ARM_GOT12 which is never generated.
* config/tc-arm.c: Rewrite, adding Thumb-2 support.
gas/testsuite:
* gas/arm/arm.exp: Convert all existing "gas_test" tests to
"run_dump_test" tests. Run more tests unconditionally. Run new tests.
* gas/arm/arch4t.s, gas/arm/arch6zk.s, gas/arm/arm3.s, gas/arm/arm6.s
* gas/arm/arm7dm.s, gas/arm/bignum1.s, gas/arm/float.s
* gas/arm/immed.s, gas/arm/iwmmxt.s, gas/arm/offset.s, gas/arm/thumb.s:
Adjust to work as a dump test.
* gas/arm/arch4t.d, gas/arm/arch6zk.d, gas/arm/arm3.d, gas/arm/arm6.d
* gas/arm/arm7dm.d, gas/arm/bignum1.d, gas/arm/float.d
* gas/arm/immed.d, gas/arm/iwmmxt.d, gas/arm/offset.d, gas/arm/thumb.d:
New files.
* gas/arm/armv1-bad.l, gas/arm/armv1-bad.s: Remove tests for
diagnostics that don't happen in the first pass anymore.
* gas/arm/iwmmxt-bad.l, gas/arm/r15-bad.l, gas/arm/req.l
* gas/arm/vfp-bad.l:
Update expected diagnostics.
* gas/arm/pic.d: Update expected reloc name.
* gas/arm/thumbv6.d: CPY no longer appears in disassembly.
* gas/arm/r15-bad.s: Avoid two-argument mul.
* gas/arm/req.s: Adjust comments.
* gas/arm/maverick.d, gas/arm/maverick.s: Avoid inappropriate
use of PC.
* gas/arm/macro-1.d, gas/arm/macro1.s
* gas/arm/t16-bad.l, gas/arm/t16-bad.s
* gas/arm/tcompat.d, gas/arm/tcompat.s
* gas/arm/tcompat2.d, gas/arm/tcompat2.s
* gas/arm/thumb32.d, gas/arm/thumb32.s
New test pair.
ld/testsuite:
* ld-arm/mixed-app.d: Adjust expected disassembly a little.
2005-05-18 07:40:12 +02:00
|
|
|
|
offset = i8;
|
|
|
|
|
|
break;
|
|
|
|
|
|
|
2009-06-29 10:08:15 +02:00
|
|
|
|
case 0xC: /* 8-bit negative immediate offset. */
|
include/elf:
* arm.h: Import complete list of official relocation names
and numbers from AAELF. Define FAKE_RELOCs for old names.
Remove a few old names no longer used anywhere.
bfd:
* elf32-arm.c: Wherever possible, use official reloc names
from AAELF.
(elf32_arm_howto_table, elf32_arm_tls_gd32_howto)
(elf32_arm_tls_ldo32_howto, elf32_arm_tls_ldm32_howto)
(elf32_arm_tls_le32_howto, elf32_arm_tls_ie32_howto)
(elf32_arm_vtinherit_howto, elf32_arm_vtentry_howto)
(elf32_arm_pc11_howto, elf32_arm_thm_pc9_howto, elf32_arm_got_prel)
(elf32_arm_r_howto): Replace with elf32_arm_howto_table_1,
elf32_arm_howto_table_2, and elf32_arm_howto_table_3.
Add many new relocations from AAELF.
(elf32_arm_howto_from_type): Update to match.
(elf32_arm_reloc_map): Add entries for R_ARM_THM_JUMP24,
R_ARM_THM_JUMP11, R_ARM_THM_JUMP19, R_ARM_THM_JUMP8,
R_ARM_THM_JUMP6, R_ARM_GNU_VTINHERIT, and R_ARM_GNU_VTENTRY.
(elf32_arm_reloc_type_lookup): Use elf32_arm_howto_from_type.
(elf32_arm_final_link_relocate): Add support for
R_ARM_THM_JUMP24, R_ARM_THM_JUMP19, R_ARM_THM_JUMP6. Remove
case entries redundant with default.
* reloc.c: Reorganize ARM relocations. Add Thumb
assembler-internal relocations BFD_RELOC_ARM_T32_OFFSET_U8,
BFD_RELOC_ARM_T32_OFFSET_IMM, BFD_RELOC_ARM_T32_IMMEDIATE.
Add visible relocations BFD_RELOC_THUMB_PCREL_BRANCH7,
BFD_RELOC_THUMB_BRANCH20, BFD_RELOC_THUMB_BRANCH25.
Delete unused relocations BFD_RELOC_ARM_GOT12, BFD_RELOC_ARM_COPY.
* bfd-in2.h, libbfd.h: Regenerate.
opcodes:
* arm-dis.c (thumb_opcodes): Add disassembly for V6T2 16-bit
instructions. Adjust disassembly of some opcodes to match
unified syntax.
(thumb32_opcodes): New table.
(print_insn_thumb): Rename print_insn_thumb16; don't handle
two-halfword branches here.
(print_insn_thumb32): New function.
(print_insn): Choose among print_insn_arm, print_insn_thumb16,
and print_insn_thumb32. Be consistent about order of
halfwords when printing 32-bit instructions.
gas:
* hash.c (hash_lookup): Add len parameter. All callers changed.
(hash_find_n): New interface.
* hash.h: Prototype hash_find_n.
* sb.c: Include as.h.
(scrub_from_sb, sb_to_scrub, scrub_position): New statics.
(sb_scrub_and_add_sb): New interface.
* sb.h: Prototype sb_scrub_and_add_sb.
* input-scrub.c (input_scrub_include_sb): Use sb_scrub_and_add_sb.
* config/tc-arm.h (TC_FORCE_RELOCATION_LOCAL): Remove
reference to BFD_RELOC_ARM_GOT12 which is never generated.
* config/tc-arm.c: Rewrite, adding Thumb-2 support.
gas/testsuite:
* gas/arm/arm.exp: Convert all existing "gas_test" tests to
"run_dump_test" tests. Run more tests unconditionally. Run new tests.
* gas/arm/arch4t.s, gas/arm/arch6zk.s, gas/arm/arm3.s, gas/arm/arm6.s
* gas/arm/arm7dm.s, gas/arm/bignum1.s, gas/arm/float.s
* gas/arm/immed.s, gas/arm/iwmmxt.s, gas/arm/offset.s, gas/arm/thumb.s:
Adjust to work as a dump test.
* gas/arm/arch4t.d, gas/arm/arch6zk.d, gas/arm/arm3.d, gas/arm/arm6.d
* gas/arm/arm7dm.d, gas/arm/bignum1.d, gas/arm/float.d
* gas/arm/immed.d, gas/arm/iwmmxt.d, gas/arm/offset.d, gas/arm/thumb.d:
New files.
* gas/arm/armv1-bad.l, gas/arm/armv1-bad.s: Remove tests for
diagnostics that don't happen in the first pass anymore.
* gas/arm/iwmmxt-bad.l, gas/arm/r15-bad.l, gas/arm/req.l
* gas/arm/vfp-bad.l:
Update expected diagnostics.
* gas/arm/pic.d: Update expected reloc name.
* gas/arm/thumbv6.d: CPY no longer appears in disassembly.
* gas/arm/r15-bad.s: Avoid two-argument mul.
* gas/arm/req.s: Adjust comments.
* gas/arm/maverick.d, gas/arm/maverick.s: Avoid inappropriate
use of PC.
* gas/arm/macro-1.d, gas/arm/macro1.s
* gas/arm/t16-bad.l, gas/arm/t16-bad.s
* gas/arm/tcompat.d, gas/arm/tcompat.s
* gas/arm/tcompat2.d, gas/arm/tcompat2.s
* gas/arm/thumb32.d, gas/arm/thumb32.s
New test pair.
ld/testsuite:
* ld-arm/mixed-app.d: Adjust expected disassembly a little.
2005-05-18 07:40:12 +02:00
|
|
|
|
offset = -i8;
|
|
|
|
|
|
break;
|
|
|
|
|
|
|
2009-06-29 10:08:15 +02:00
|
|
|
|
case 0xF: /* 8-bit + preindex with wb. */
|
include/elf:
* arm.h: Import complete list of official relocation names
and numbers from AAELF. Define FAKE_RELOCs for old names.
Remove a few old names no longer used anywhere.
bfd:
* elf32-arm.c: Wherever possible, use official reloc names
from AAELF.
(elf32_arm_howto_table, elf32_arm_tls_gd32_howto)
(elf32_arm_tls_ldo32_howto, elf32_arm_tls_ldm32_howto)
(elf32_arm_tls_le32_howto, elf32_arm_tls_ie32_howto)
(elf32_arm_vtinherit_howto, elf32_arm_vtentry_howto)
(elf32_arm_pc11_howto, elf32_arm_thm_pc9_howto, elf32_arm_got_prel)
(elf32_arm_r_howto): Replace with elf32_arm_howto_table_1,
elf32_arm_howto_table_2, and elf32_arm_howto_table_3.
Add many new relocations from AAELF.
(elf32_arm_howto_from_type): Update to match.
(elf32_arm_reloc_map): Add entries for R_ARM_THM_JUMP24,
R_ARM_THM_JUMP11, R_ARM_THM_JUMP19, R_ARM_THM_JUMP8,
R_ARM_THM_JUMP6, R_ARM_GNU_VTINHERIT, and R_ARM_GNU_VTENTRY.
(elf32_arm_reloc_type_lookup): Use elf32_arm_howto_from_type.
(elf32_arm_final_link_relocate): Add support for
R_ARM_THM_JUMP24, R_ARM_THM_JUMP19, R_ARM_THM_JUMP6. Remove
case entries redundant with default.
* reloc.c: Reorganize ARM relocations. Add Thumb
assembler-internal relocations BFD_RELOC_ARM_T32_OFFSET_U8,
BFD_RELOC_ARM_T32_OFFSET_IMM, BFD_RELOC_ARM_T32_IMMEDIATE.
Add visible relocations BFD_RELOC_THUMB_PCREL_BRANCH7,
BFD_RELOC_THUMB_BRANCH20, BFD_RELOC_THUMB_BRANCH25.
Delete unused relocations BFD_RELOC_ARM_GOT12, BFD_RELOC_ARM_COPY.
* bfd-in2.h, libbfd.h: Regenerate.
opcodes:
* arm-dis.c (thumb_opcodes): Add disassembly for V6T2 16-bit
instructions. Adjust disassembly of some opcodes to match
unified syntax.
(thumb32_opcodes): New table.
(print_insn_thumb): Rename print_insn_thumb16; don't handle
two-halfword branches here.
(print_insn_thumb32): New function.
(print_insn): Choose among print_insn_arm, print_insn_thumb16,
and print_insn_thumb32. Be consistent about order of
halfwords when printing 32-bit instructions.
gas:
* hash.c (hash_lookup): Add len parameter. All callers changed.
(hash_find_n): New interface.
* hash.h: Prototype hash_find_n.
* sb.c: Include as.h.
(scrub_from_sb, sb_to_scrub, scrub_position): New statics.
(sb_scrub_and_add_sb): New interface.
* sb.h: Prototype sb_scrub_and_add_sb.
* input-scrub.c (input_scrub_include_sb): Use sb_scrub_and_add_sb.
* config/tc-arm.h (TC_FORCE_RELOCATION_LOCAL): Remove
reference to BFD_RELOC_ARM_GOT12 which is never generated.
* config/tc-arm.c: Rewrite, adding Thumb-2 support.
gas/testsuite:
* gas/arm/arm.exp: Convert all existing "gas_test" tests to
"run_dump_test" tests. Run more tests unconditionally. Run new tests.
* gas/arm/arch4t.s, gas/arm/arch6zk.s, gas/arm/arm3.s, gas/arm/arm6.s
* gas/arm/arm7dm.s, gas/arm/bignum1.s, gas/arm/float.s
* gas/arm/immed.s, gas/arm/iwmmxt.s, gas/arm/offset.s, gas/arm/thumb.s:
Adjust to work as a dump test.
* gas/arm/arch4t.d, gas/arm/arch6zk.d, gas/arm/arm3.d, gas/arm/arm6.d
* gas/arm/arm7dm.d, gas/arm/bignum1.d, gas/arm/float.d
* gas/arm/immed.d, gas/arm/iwmmxt.d, gas/arm/offset.d, gas/arm/thumb.d:
New files.
* gas/arm/armv1-bad.l, gas/arm/armv1-bad.s: Remove tests for
diagnostics that don't happen in the first pass anymore.
* gas/arm/iwmmxt-bad.l, gas/arm/r15-bad.l, gas/arm/req.l
* gas/arm/vfp-bad.l:
Update expected diagnostics.
* gas/arm/pic.d: Update expected reloc name.
* gas/arm/thumbv6.d: CPY no longer appears in disassembly.
* gas/arm/r15-bad.s: Avoid two-argument mul.
* gas/arm/req.s: Adjust comments.
* gas/arm/maverick.d, gas/arm/maverick.s: Avoid inappropriate
use of PC.
* gas/arm/macro-1.d, gas/arm/macro1.s
* gas/arm/t16-bad.l, gas/arm/t16-bad.s
* gas/arm/tcompat.d, gas/arm/tcompat.s
* gas/arm/tcompat2.d, gas/arm/tcompat2.s
* gas/arm/thumb32.d, gas/arm/thumb32.s
New test pair.
ld/testsuite:
* ld-arm/mixed-app.d: Adjust expected disassembly a little.
2005-05-18 07:40:12 +02:00
|
|
|
|
offset = i8;
|
|
|
|
|
|
writeback = TRUE;
|
|
|
|
|
|
break;
|
|
|
|
|
|
|
2009-06-29 10:08:15 +02:00
|
|
|
|
case 0xD: /* 8-bit - preindex with wb. */
|
include/elf:
* arm.h: Import complete list of official relocation names
and numbers from AAELF. Define FAKE_RELOCs for old names.
Remove a few old names no longer used anywhere.
bfd:
* elf32-arm.c: Wherever possible, use official reloc names
from AAELF.
(elf32_arm_howto_table, elf32_arm_tls_gd32_howto)
(elf32_arm_tls_ldo32_howto, elf32_arm_tls_ldm32_howto)
(elf32_arm_tls_le32_howto, elf32_arm_tls_ie32_howto)
(elf32_arm_vtinherit_howto, elf32_arm_vtentry_howto)
(elf32_arm_pc11_howto, elf32_arm_thm_pc9_howto, elf32_arm_got_prel)
(elf32_arm_r_howto): Replace with elf32_arm_howto_table_1,
elf32_arm_howto_table_2, and elf32_arm_howto_table_3.
Add many new relocations from AAELF.
(elf32_arm_howto_from_type): Update to match.
(elf32_arm_reloc_map): Add entries for R_ARM_THM_JUMP24,
R_ARM_THM_JUMP11, R_ARM_THM_JUMP19, R_ARM_THM_JUMP8,
R_ARM_THM_JUMP6, R_ARM_GNU_VTINHERIT, and R_ARM_GNU_VTENTRY.
(elf32_arm_reloc_type_lookup): Use elf32_arm_howto_from_type.
(elf32_arm_final_link_relocate): Add support for
R_ARM_THM_JUMP24, R_ARM_THM_JUMP19, R_ARM_THM_JUMP6. Remove
case entries redundant with default.
* reloc.c: Reorganize ARM relocations. Add Thumb
assembler-internal relocations BFD_RELOC_ARM_T32_OFFSET_U8,
BFD_RELOC_ARM_T32_OFFSET_IMM, BFD_RELOC_ARM_T32_IMMEDIATE.
Add visible relocations BFD_RELOC_THUMB_PCREL_BRANCH7,
BFD_RELOC_THUMB_BRANCH20, BFD_RELOC_THUMB_BRANCH25.
Delete unused relocations BFD_RELOC_ARM_GOT12, BFD_RELOC_ARM_COPY.
* bfd-in2.h, libbfd.h: Regenerate.
opcodes:
* arm-dis.c (thumb_opcodes): Add disassembly for V6T2 16-bit
instructions. Adjust disassembly of some opcodes to match
unified syntax.
(thumb32_opcodes): New table.
(print_insn_thumb): Rename print_insn_thumb16; don't handle
two-halfword branches here.
(print_insn_thumb32): New function.
(print_insn): Choose among print_insn_arm, print_insn_thumb16,
and print_insn_thumb32. Be consistent about order of
halfwords when printing 32-bit instructions.
gas:
* hash.c (hash_lookup): Add len parameter. All callers changed.
(hash_find_n): New interface.
* hash.h: Prototype hash_find_n.
* sb.c: Include as.h.
(scrub_from_sb, sb_to_scrub, scrub_position): New statics.
(sb_scrub_and_add_sb): New interface.
* sb.h: Prototype sb_scrub_and_add_sb.
* input-scrub.c (input_scrub_include_sb): Use sb_scrub_and_add_sb.
* config/tc-arm.h (TC_FORCE_RELOCATION_LOCAL): Remove
reference to BFD_RELOC_ARM_GOT12 which is never generated.
* config/tc-arm.c: Rewrite, adding Thumb-2 support.
gas/testsuite:
* gas/arm/arm.exp: Convert all existing "gas_test" tests to
"run_dump_test" tests. Run more tests unconditionally. Run new tests.
* gas/arm/arch4t.s, gas/arm/arch6zk.s, gas/arm/arm3.s, gas/arm/arm6.s
* gas/arm/arm7dm.s, gas/arm/bignum1.s, gas/arm/float.s
* gas/arm/immed.s, gas/arm/iwmmxt.s, gas/arm/offset.s, gas/arm/thumb.s:
Adjust to work as a dump test.
* gas/arm/arch4t.d, gas/arm/arch6zk.d, gas/arm/arm3.d, gas/arm/arm6.d
* gas/arm/arm7dm.d, gas/arm/bignum1.d, gas/arm/float.d
* gas/arm/immed.d, gas/arm/iwmmxt.d, gas/arm/offset.d, gas/arm/thumb.d:
New files.
* gas/arm/armv1-bad.l, gas/arm/armv1-bad.s: Remove tests for
diagnostics that don't happen in the first pass anymore.
* gas/arm/iwmmxt-bad.l, gas/arm/r15-bad.l, gas/arm/req.l
* gas/arm/vfp-bad.l:
Update expected diagnostics.
* gas/arm/pic.d: Update expected reloc name.
* gas/arm/thumbv6.d: CPY no longer appears in disassembly.
* gas/arm/r15-bad.s: Avoid two-argument mul.
* gas/arm/req.s: Adjust comments.
* gas/arm/maverick.d, gas/arm/maverick.s: Avoid inappropriate
use of PC.
* gas/arm/macro-1.d, gas/arm/macro1.s
* gas/arm/t16-bad.l, gas/arm/t16-bad.s
* gas/arm/tcompat.d, gas/arm/tcompat.s
* gas/arm/tcompat2.d, gas/arm/tcompat2.s
* gas/arm/thumb32.d, gas/arm/thumb32.s
New test pair.
ld/testsuite:
* ld-arm/mixed-app.d: Adjust expected disassembly a little.
2005-05-18 07:40:12 +02:00
|
|
|
|
offset = -i8;
|
|
|
|
|
|
writeback = TRUE;
|
|
|
|
|
|
break;
|
|
|
|
|
|
|
2009-06-29 10:08:15 +02:00
|
|
|
|
case 0xB: /* 8-bit + postindex. */
|
include/elf:
* arm.h: Import complete list of official relocation names
and numbers from AAELF. Define FAKE_RELOCs for old names.
Remove a few old names no longer used anywhere.
bfd:
* elf32-arm.c: Wherever possible, use official reloc names
from AAELF.
(elf32_arm_howto_table, elf32_arm_tls_gd32_howto)
(elf32_arm_tls_ldo32_howto, elf32_arm_tls_ldm32_howto)
(elf32_arm_tls_le32_howto, elf32_arm_tls_ie32_howto)
(elf32_arm_vtinherit_howto, elf32_arm_vtentry_howto)
(elf32_arm_pc11_howto, elf32_arm_thm_pc9_howto, elf32_arm_got_prel)
(elf32_arm_r_howto): Replace with elf32_arm_howto_table_1,
elf32_arm_howto_table_2, and elf32_arm_howto_table_3.
Add many new relocations from AAELF.
(elf32_arm_howto_from_type): Update to match.
(elf32_arm_reloc_map): Add entries for R_ARM_THM_JUMP24,
R_ARM_THM_JUMP11, R_ARM_THM_JUMP19, R_ARM_THM_JUMP8,
R_ARM_THM_JUMP6, R_ARM_GNU_VTINHERIT, and R_ARM_GNU_VTENTRY.
(elf32_arm_reloc_type_lookup): Use elf32_arm_howto_from_type.
(elf32_arm_final_link_relocate): Add support for
R_ARM_THM_JUMP24, R_ARM_THM_JUMP19, R_ARM_THM_JUMP6. Remove
case entries redundant with default.
* reloc.c: Reorganize ARM relocations. Add Thumb
assembler-internal relocations BFD_RELOC_ARM_T32_OFFSET_U8,
BFD_RELOC_ARM_T32_OFFSET_IMM, BFD_RELOC_ARM_T32_IMMEDIATE.
Add visible relocations BFD_RELOC_THUMB_PCREL_BRANCH7,
BFD_RELOC_THUMB_BRANCH20, BFD_RELOC_THUMB_BRANCH25.
Delete unused relocations BFD_RELOC_ARM_GOT12, BFD_RELOC_ARM_COPY.
* bfd-in2.h, libbfd.h: Regenerate.
opcodes:
* arm-dis.c (thumb_opcodes): Add disassembly for V6T2 16-bit
instructions. Adjust disassembly of some opcodes to match
unified syntax.
(thumb32_opcodes): New table.
(print_insn_thumb): Rename print_insn_thumb16; don't handle
two-halfword branches here.
(print_insn_thumb32): New function.
(print_insn): Choose among print_insn_arm, print_insn_thumb16,
and print_insn_thumb32. Be consistent about order of
halfwords when printing 32-bit instructions.
gas:
* hash.c (hash_lookup): Add len parameter. All callers changed.
(hash_find_n): New interface.
* hash.h: Prototype hash_find_n.
* sb.c: Include as.h.
(scrub_from_sb, sb_to_scrub, scrub_position): New statics.
(sb_scrub_and_add_sb): New interface.
* sb.h: Prototype sb_scrub_and_add_sb.
* input-scrub.c (input_scrub_include_sb): Use sb_scrub_and_add_sb.
* config/tc-arm.h (TC_FORCE_RELOCATION_LOCAL): Remove
reference to BFD_RELOC_ARM_GOT12 which is never generated.
* config/tc-arm.c: Rewrite, adding Thumb-2 support.
gas/testsuite:
* gas/arm/arm.exp: Convert all existing "gas_test" tests to
"run_dump_test" tests. Run more tests unconditionally. Run new tests.
* gas/arm/arch4t.s, gas/arm/arch6zk.s, gas/arm/arm3.s, gas/arm/arm6.s
* gas/arm/arm7dm.s, gas/arm/bignum1.s, gas/arm/float.s
* gas/arm/immed.s, gas/arm/iwmmxt.s, gas/arm/offset.s, gas/arm/thumb.s:
Adjust to work as a dump test.
* gas/arm/arch4t.d, gas/arm/arch6zk.d, gas/arm/arm3.d, gas/arm/arm6.d
* gas/arm/arm7dm.d, gas/arm/bignum1.d, gas/arm/float.d
* gas/arm/immed.d, gas/arm/iwmmxt.d, gas/arm/offset.d, gas/arm/thumb.d:
New files.
* gas/arm/armv1-bad.l, gas/arm/armv1-bad.s: Remove tests for
diagnostics that don't happen in the first pass anymore.
* gas/arm/iwmmxt-bad.l, gas/arm/r15-bad.l, gas/arm/req.l
* gas/arm/vfp-bad.l:
Update expected diagnostics.
* gas/arm/pic.d: Update expected reloc name.
* gas/arm/thumbv6.d: CPY no longer appears in disassembly.
* gas/arm/r15-bad.s: Avoid two-argument mul.
* gas/arm/req.s: Adjust comments.
* gas/arm/maverick.d, gas/arm/maverick.s: Avoid inappropriate
use of PC.
* gas/arm/macro-1.d, gas/arm/macro1.s
* gas/arm/t16-bad.l, gas/arm/t16-bad.s
* gas/arm/tcompat.d, gas/arm/tcompat.s
* gas/arm/tcompat2.d, gas/arm/tcompat2.s
* gas/arm/thumb32.d, gas/arm/thumb32.s
New test pair.
ld/testsuite:
* ld-arm/mixed-app.d: Adjust expected disassembly a little.
2005-05-18 07:40:12 +02:00
|
|
|
|
offset = i8;
|
|
|
|
|
|
postind = TRUE;
|
|
|
|
|
|
break;
|
|
|
|
|
|
|
2009-06-29 10:08:15 +02:00
|
|
|
|
case 0x9: /* 8-bit - postindex. */
|
include/elf:
* arm.h: Import complete list of official relocation names
and numbers from AAELF. Define FAKE_RELOCs for old names.
Remove a few old names no longer used anywhere.
bfd:
* elf32-arm.c: Wherever possible, use official reloc names
from AAELF.
(elf32_arm_howto_table, elf32_arm_tls_gd32_howto)
(elf32_arm_tls_ldo32_howto, elf32_arm_tls_ldm32_howto)
(elf32_arm_tls_le32_howto, elf32_arm_tls_ie32_howto)
(elf32_arm_vtinherit_howto, elf32_arm_vtentry_howto)
(elf32_arm_pc11_howto, elf32_arm_thm_pc9_howto, elf32_arm_got_prel)
(elf32_arm_r_howto): Replace with elf32_arm_howto_table_1,
elf32_arm_howto_table_2, and elf32_arm_howto_table_3.
Add many new relocations from AAELF.
(elf32_arm_howto_from_type): Update to match.
(elf32_arm_reloc_map): Add entries for R_ARM_THM_JUMP24,
R_ARM_THM_JUMP11, R_ARM_THM_JUMP19, R_ARM_THM_JUMP8,
R_ARM_THM_JUMP6, R_ARM_GNU_VTINHERIT, and R_ARM_GNU_VTENTRY.
(elf32_arm_reloc_type_lookup): Use elf32_arm_howto_from_type.
(elf32_arm_final_link_relocate): Add support for
R_ARM_THM_JUMP24, R_ARM_THM_JUMP19, R_ARM_THM_JUMP6. Remove
case entries redundant with default.
* reloc.c: Reorganize ARM relocations. Add Thumb
assembler-internal relocations BFD_RELOC_ARM_T32_OFFSET_U8,
BFD_RELOC_ARM_T32_OFFSET_IMM, BFD_RELOC_ARM_T32_IMMEDIATE.
Add visible relocations BFD_RELOC_THUMB_PCREL_BRANCH7,
BFD_RELOC_THUMB_BRANCH20, BFD_RELOC_THUMB_BRANCH25.
Delete unused relocations BFD_RELOC_ARM_GOT12, BFD_RELOC_ARM_COPY.
* bfd-in2.h, libbfd.h: Regenerate.
opcodes:
* arm-dis.c (thumb_opcodes): Add disassembly for V6T2 16-bit
instructions. Adjust disassembly of some opcodes to match
unified syntax.
(thumb32_opcodes): New table.
(print_insn_thumb): Rename print_insn_thumb16; don't handle
two-halfword branches here.
(print_insn_thumb32): New function.
(print_insn): Choose among print_insn_arm, print_insn_thumb16,
and print_insn_thumb32. Be consistent about order of
halfwords when printing 32-bit instructions.
gas:
* hash.c (hash_lookup): Add len parameter. All callers changed.
(hash_find_n): New interface.
* hash.h: Prototype hash_find_n.
* sb.c: Include as.h.
(scrub_from_sb, sb_to_scrub, scrub_position): New statics.
(sb_scrub_and_add_sb): New interface.
* sb.h: Prototype sb_scrub_and_add_sb.
* input-scrub.c (input_scrub_include_sb): Use sb_scrub_and_add_sb.
* config/tc-arm.h (TC_FORCE_RELOCATION_LOCAL): Remove
reference to BFD_RELOC_ARM_GOT12 which is never generated.
* config/tc-arm.c: Rewrite, adding Thumb-2 support.
gas/testsuite:
* gas/arm/arm.exp: Convert all existing "gas_test" tests to
"run_dump_test" tests. Run more tests unconditionally. Run new tests.
* gas/arm/arch4t.s, gas/arm/arch6zk.s, gas/arm/arm3.s, gas/arm/arm6.s
* gas/arm/arm7dm.s, gas/arm/bignum1.s, gas/arm/float.s
* gas/arm/immed.s, gas/arm/iwmmxt.s, gas/arm/offset.s, gas/arm/thumb.s:
Adjust to work as a dump test.
* gas/arm/arch4t.d, gas/arm/arch6zk.d, gas/arm/arm3.d, gas/arm/arm6.d
* gas/arm/arm7dm.d, gas/arm/bignum1.d, gas/arm/float.d
* gas/arm/immed.d, gas/arm/iwmmxt.d, gas/arm/offset.d, gas/arm/thumb.d:
New files.
* gas/arm/armv1-bad.l, gas/arm/armv1-bad.s: Remove tests for
diagnostics that don't happen in the first pass anymore.
* gas/arm/iwmmxt-bad.l, gas/arm/r15-bad.l, gas/arm/req.l
* gas/arm/vfp-bad.l:
Update expected diagnostics.
* gas/arm/pic.d: Update expected reloc name.
* gas/arm/thumbv6.d: CPY no longer appears in disassembly.
* gas/arm/r15-bad.s: Avoid two-argument mul.
* gas/arm/req.s: Adjust comments.
* gas/arm/maverick.d, gas/arm/maverick.s: Avoid inappropriate
use of PC.
* gas/arm/macro-1.d, gas/arm/macro1.s
* gas/arm/t16-bad.l, gas/arm/t16-bad.s
* gas/arm/tcompat.d, gas/arm/tcompat.s
* gas/arm/tcompat2.d, gas/arm/tcompat2.s
* gas/arm/thumb32.d, gas/arm/thumb32.s
New test pair.
ld/testsuite:
* ld-arm/mixed-app.d: Adjust expected disassembly a little.
2005-05-18 07:40:12 +02:00
|
|
|
|
offset = -i8;
|
|
|
|
|
|
postind = TRUE;
|
|
|
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
|
|
default:
|
|
|
|
|
|
func (stream, ", <undefined>]");
|
|
|
|
|
|
goto skip;
|
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
if (postind)
|
2012-07-24 14:56:47 +02:00
|
|
|
|
func (stream, "], #%d", (int) offset);
|
include/elf:
* arm.h: Import complete list of official relocation names
and numbers from AAELF. Define FAKE_RELOCs for old names.
Remove a few old names no longer used anywhere.
bfd:
* elf32-arm.c: Wherever possible, use official reloc names
from AAELF.
(elf32_arm_howto_table, elf32_arm_tls_gd32_howto)
(elf32_arm_tls_ldo32_howto, elf32_arm_tls_ldm32_howto)
(elf32_arm_tls_le32_howto, elf32_arm_tls_ie32_howto)
(elf32_arm_vtinherit_howto, elf32_arm_vtentry_howto)
(elf32_arm_pc11_howto, elf32_arm_thm_pc9_howto, elf32_arm_got_prel)
(elf32_arm_r_howto): Replace with elf32_arm_howto_table_1,
elf32_arm_howto_table_2, and elf32_arm_howto_table_3.
Add many new relocations from AAELF.
(elf32_arm_howto_from_type): Update to match.
(elf32_arm_reloc_map): Add entries for R_ARM_THM_JUMP24,
R_ARM_THM_JUMP11, R_ARM_THM_JUMP19, R_ARM_THM_JUMP8,
R_ARM_THM_JUMP6, R_ARM_GNU_VTINHERIT, and R_ARM_GNU_VTENTRY.
(elf32_arm_reloc_type_lookup): Use elf32_arm_howto_from_type.
(elf32_arm_final_link_relocate): Add support for
R_ARM_THM_JUMP24, R_ARM_THM_JUMP19, R_ARM_THM_JUMP6. Remove
case entries redundant with default.
* reloc.c: Reorganize ARM relocations. Add Thumb
assembler-internal relocations BFD_RELOC_ARM_T32_OFFSET_U8,
BFD_RELOC_ARM_T32_OFFSET_IMM, BFD_RELOC_ARM_T32_IMMEDIATE.
Add visible relocations BFD_RELOC_THUMB_PCREL_BRANCH7,
BFD_RELOC_THUMB_BRANCH20, BFD_RELOC_THUMB_BRANCH25.
Delete unused relocations BFD_RELOC_ARM_GOT12, BFD_RELOC_ARM_COPY.
* bfd-in2.h, libbfd.h: Regenerate.
opcodes:
* arm-dis.c (thumb_opcodes): Add disassembly for V6T2 16-bit
instructions. Adjust disassembly of some opcodes to match
unified syntax.
(thumb32_opcodes): New table.
(print_insn_thumb): Rename print_insn_thumb16; don't handle
two-halfword branches here.
(print_insn_thumb32): New function.
(print_insn): Choose among print_insn_arm, print_insn_thumb16,
and print_insn_thumb32. Be consistent about order of
halfwords when printing 32-bit instructions.
gas:
* hash.c (hash_lookup): Add len parameter. All callers changed.
(hash_find_n): New interface.
* hash.h: Prototype hash_find_n.
* sb.c: Include as.h.
(scrub_from_sb, sb_to_scrub, scrub_position): New statics.
(sb_scrub_and_add_sb): New interface.
* sb.h: Prototype sb_scrub_and_add_sb.
* input-scrub.c (input_scrub_include_sb): Use sb_scrub_and_add_sb.
* config/tc-arm.h (TC_FORCE_RELOCATION_LOCAL): Remove
reference to BFD_RELOC_ARM_GOT12 which is never generated.
* config/tc-arm.c: Rewrite, adding Thumb-2 support.
gas/testsuite:
* gas/arm/arm.exp: Convert all existing "gas_test" tests to
"run_dump_test" tests. Run more tests unconditionally. Run new tests.
* gas/arm/arch4t.s, gas/arm/arch6zk.s, gas/arm/arm3.s, gas/arm/arm6.s
* gas/arm/arm7dm.s, gas/arm/bignum1.s, gas/arm/float.s
* gas/arm/immed.s, gas/arm/iwmmxt.s, gas/arm/offset.s, gas/arm/thumb.s:
Adjust to work as a dump test.
* gas/arm/arch4t.d, gas/arm/arch6zk.d, gas/arm/arm3.d, gas/arm/arm6.d
* gas/arm/arm7dm.d, gas/arm/bignum1.d, gas/arm/float.d
* gas/arm/immed.d, gas/arm/iwmmxt.d, gas/arm/offset.d, gas/arm/thumb.d:
New files.
* gas/arm/armv1-bad.l, gas/arm/armv1-bad.s: Remove tests for
diagnostics that don't happen in the first pass anymore.
* gas/arm/iwmmxt-bad.l, gas/arm/r15-bad.l, gas/arm/req.l
* gas/arm/vfp-bad.l:
Update expected diagnostics.
* gas/arm/pic.d: Update expected reloc name.
* gas/arm/thumbv6.d: CPY no longer appears in disassembly.
* gas/arm/r15-bad.s: Avoid two-argument mul.
* gas/arm/req.s: Adjust comments.
* gas/arm/maverick.d, gas/arm/maverick.s: Avoid inappropriate
use of PC.
* gas/arm/macro-1.d, gas/arm/macro1.s
* gas/arm/t16-bad.l, gas/arm/t16-bad.s
* gas/arm/tcompat.d, gas/arm/tcompat.s
* gas/arm/tcompat2.d, gas/arm/tcompat2.s
* gas/arm/thumb32.d, gas/arm/thumb32.s
New test pair.
ld/testsuite:
* ld-arm/mixed-app.d: Adjust expected disassembly a little.
2005-05-18 07:40:12 +02:00
|
|
|
|
else
|
|
|
|
|
|
{
|
|
|
|
|
|
if (offset)
|
2012-07-24 14:56:47 +02:00
|
|
|
|
func (stream, ", #%d", (int) offset);
|
include/elf:
* arm.h: Import complete list of official relocation names
and numbers from AAELF. Define FAKE_RELOCs for old names.
Remove a few old names no longer used anywhere.
bfd:
* elf32-arm.c: Wherever possible, use official reloc names
from AAELF.
(elf32_arm_howto_table, elf32_arm_tls_gd32_howto)
(elf32_arm_tls_ldo32_howto, elf32_arm_tls_ldm32_howto)
(elf32_arm_tls_le32_howto, elf32_arm_tls_ie32_howto)
(elf32_arm_vtinherit_howto, elf32_arm_vtentry_howto)
(elf32_arm_pc11_howto, elf32_arm_thm_pc9_howto, elf32_arm_got_prel)
(elf32_arm_r_howto): Replace with elf32_arm_howto_table_1,
elf32_arm_howto_table_2, and elf32_arm_howto_table_3.
Add many new relocations from AAELF.
(elf32_arm_howto_from_type): Update to match.
(elf32_arm_reloc_map): Add entries for R_ARM_THM_JUMP24,
R_ARM_THM_JUMP11, R_ARM_THM_JUMP19, R_ARM_THM_JUMP8,
R_ARM_THM_JUMP6, R_ARM_GNU_VTINHERIT, and R_ARM_GNU_VTENTRY.
(elf32_arm_reloc_type_lookup): Use elf32_arm_howto_from_type.
(elf32_arm_final_link_relocate): Add support for
R_ARM_THM_JUMP24, R_ARM_THM_JUMP19, R_ARM_THM_JUMP6. Remove
case entries redundant with default.
* reloc.c: Reorganize ARM relocations. Add Thumb
assembler-internal relocations BFD_RELOC_ARM_T32_OFFSET_U8,
BFD_RELOC_ARM_T32_OFFSET_IMM, BFD_RELOC_ARM_T32_IMMEDIATE.
Add visible relocations BFD_RELOC_THUMB_PCREL_BRANCH7,
BFD_RELOC_THUMB_BRANCH20, BFD_RELOC_THUMB_BRANCH25.
Delete unused relocations BFD_RELOC_ARM_GOT12, BFD_RELOC_ARM_COPY.
* bfd-in2.h, libbfd.h: Regenerate.
opcodes:
* arm-dis.c (thumb_opcodes): Add disassembly for V6T2 16-bit
instructions. Adjust disassembly of some opcodes to match
unified syntax.
(thumb32_opcodes): New table.
(print_insn_thumb): Rename print_insn_thumb16; don't handle
two-halfword branches here.
(print_insn_thumb32): New function.
(print_insn): Choose among print_insn_arm, print_insn_thumb16,
and print_insn_thumb32. Be consistent about order of
halfwords when printing 32-bit instructions.
gas:
* hash.c (hash_lookup): Add len parameter. All callers changed.
(hash_find_n): New interface.
* hash.h: Prototype hash_find_n.
* sb.c: Include as.h.
(scrub_from_sb, sb_to_scrub, scrub_position): New statics.
(sb_scrub_and_add_sb): New interface.
* sb.h: Prototype sb_scrub_and_add_sb.
* input-scrub.c (input_scrub_include_sb): Use sb_scrub_and_add_sb.
* config/tc-arm.h (TC_FORCE_RELOCATION_LOCAL): Remove
reference to BFD_RELOC_ARM_GOT12 which is never generated.
* config/tc-arm.c: Rewrite, adding Thumb-2 support.
gas/testsuite:
* gas/arm/arm.exp: Convert all existing "gas_test" tests to
"run_dump_test" tests. Run more tests unconditionally. Run new tests.
* gas/arm/arch4t.s, gas/arm/arch6zk.s, gas/arm/arm3.s, gas/arm/arm6.s
* gas/arm/arm7dm.s, gas/arm/bignum1.s, gas/arm/float.s
* gas/arm/immed.s, gas/arm/iwmmxt.s, gas/arm/offset.s, gas/arm/thumb.s:
Adjust to work as a dump test.
* gas/arm/arch4t.d, gas/arm/arch6zk.d, gas/arm/arm3.d, gas/arm/arm6.d
* gas/arm/arm7dm.d, gas/arm/bignum1.d, gas/arm/float.d
* gas/arm/immed.d, gas/arm/iwmmxt.d, gas/arm/offset.d, gas/arm/thumb.d:
New files.
* gas/arm/armv1-bad.l, gas/arm/armv1-bad.s: Remove tests for
diagnostics that don't happen in the first pass anymore.
* gas/arm/iwmmxt-bad.l, gas/arm/r15-bad.l, gas/arm/req.l
* gas/arm/vfp-bad.l:
Update expected diagnostics.
* gas/arm/pic.d: Update expected reloc name.
* gas/arm/thumbv6.d: CPY no longer appears in disassembly.
* gas/arm/r15-bad.s: Avoid two-argument mul.
* gas/arm/req.s: Adjust comments.
* gas/arm/maverick.d, gas/arm/maverick.s: Avoid inappropriate
use of PC.
* gas/arm/macro-1.d, gas/arm/macro1.s
* gas/arm/t16-bad.l, gas/arm/t16-bad.s
* gas/arm/tcompat.d, gas/arm/tcompat.s
* gas/arm/tcompat2.d, gas/arm/tcompat2.s
* gas/arm/thumb32.d, gas/arm/thumb32.s
New test pair.
ld/testsuite:
* ld-arm/mixed-app.d: Adjust expected disassembly a little.
2005-05-18 07:40:12 +02:00
|
|
|
|
func (stream, writeback ? "]!" : "]");
|
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
if (Rn == 15)
|
|
|
|
|
|
{
|
|
|
|
|
|
func (stream, "\t; ");
|
|
|
|
|
|
info->print_address_func (((pc + 4) & ~3) + offset, info);
|
|
|
|
|
|
}
|
|
|
|
|
|
}
|
|
|
|
|
|
skip:
|
|
|
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
|
|
case 'A':
|
|
|
|
|
|
{
|
2009-11-11 10:44:45 +01:00
|
|
|
|
unsigned int U = ! NEGATIVE_BIT_SET;
|
|
|
|
|
|
unsigned int W = WRITEBACK_BIT_SET;
|
include/elf:
* arm.h: Import complete list of official relocation names
and numbers from AAELF. Define FAKE_RELOCs for old names.
Remove a few old names no longer used anywhere.
bfd:
* elf32-arm.c: Wherever possible, use official reloc names
from AAELF.
(elf32_arm_howto_table, elf32_arm_tls_gd32_howto)
(elf32_arm_tls_ldo32_howto, elf32_arm_tls_ldm32_howto)
(elf32_arm_tls_le32_howto, elf32_arm_tls_ie32_howto)
(elf32_arm_vtinherit_howto, elf32_arm_vtentry_howto)
(elf32_arm_pc11_howto, elf32_arm_thm_pc9_howto, elf32_arm_got_prel)
(elf32_arm_r_howto): Replace with elf32_arm_howto_table_1,
elf32_arm_howto_table_2, and elf32_arm_howto_table_3.
Add many new relocations from AAELF.
(elf32_arm_howto_from_type): Update to match.
(elf32_arm_reloc_map): Add entries for R_ARM_THM_JUMP24,
R_ARM_THM_JUMP11, R_ARM_THM_JUMP19, R_ARM_THM_JUMP8,
R_ARM_THM_JUMP6, R_ARM_GNU_VTINHERIT, and R_ARM_GNU_VTENTRY.
(elf32_arm_reloc_type_lookup): Use elf32_arm_howto_from_type.
(elf32_arm_final_link_relocate): Add support for
R_ARM_THM_JUMP24, R_ARM_THM_JUMP19, R_ARM_THM_JUMP6. Remove
case entries redundant with default.
* reloc.c: Reorganize ARM relocations. Add Thumb
assembler-internal relocations BFD_RELOC_ARM_T32_OFFSET_U8,
BFD_RELOC_ARM_T32_OFFSET_IMM, BFD_RELOC_ARM_T32_IMMEDIATE.
Add visible relocations BFD_RELOC_THUMB_PCREL_BRANCH7,
BFD_RELOC_THUMB_BRANCH20, BFD_RELOC_THUMB_BRANCH25.
Delete unused relocations BFD_RELOC_ARM_GOT12, BFD_RELOC_ARM_COPY.
* bfd-in2.h, libbfd.h: Regenerate.
opcodes:
* arm-dis.c (thumb_opcodes): Add disassembly for V6T2 16-bit
instructions. Adjust disassembly of some opcodes to match
unified syntax.
(thumb32_opcodes): New table.
(print_insn_thumb): Rename print_insn_thumb16; don't handle
two-halfword branches here.
(print_insn_thumb32): New function.
(print_insn): Choose among print_insn_arm, print_insn_thumb16,
and print_insn_thumb32. Be consistent about order of
halfwords when printing 32-bit instructions.
gas:
* hash.c (hash_lookup): Add len parameter. All callers changed.
(hash_find_n): New interface.
* hash.h: Prototype hash_find_n.
* sb.c: Include as.h.
(scrub_from_sb, sb_to_scrub, scrub_position): New statics.
(sb_scrub_and_add_sb): New interface.
* sb.h: Prototype sb_scrub_and_add_sb.
* input-scrub.c (input_scrub_include_sb): Use sb_scrub_and_add_sb.
* config/tc-arm.h (TC_FORCE_RELOCATION_LOCAL): Remove
reference to BFD_RELOC_ARM_GOT12 which is never generated.
* config/tc-arm.c: Rewrite, adding Thumb-2 support.
gas/testsuite:
* gas/arm/arm.exp: Convert all existing "gas_test" tests to
"run_dump_test" tests. Run more tests unconditionally. Run new tests.
* gas/arm/arch4t.s, gas/arm/arch6zk.s, gas/arm/arm3.s, gas/arm/arm6.s
* gas/arm/arm7dm.s, gas/arm/bignum1.s, gas/arm/float.s
* gas/arm/immed.s, gas/arm/iwmmxt.s, gas/arm/offset.s, gas/arm/thumb.s:
Adjust to work as a dump test.
* gas/arm/arch4t.d, gas/arm/arch6zk.d, gas/arm/arm3.d, gas/arm/arm6.d
* gas/arm/arm7dm.d, gas/arm/bignum1.d, gas/arm/float.d
* gas/arm/immed.d, gas/arm/iwmmxt.d, gas/arm/offset.d, gas/arm/thumb.d:
New files.
* gas/arm/armv1-bad.l, gas/arm/armv1-bad.s: Remove tests for
diagnostics that don't happen in the first pass anymore.
* gas/arm/iwmmxt-bad.l, gas/arm/r15-bad.l, gas/arm/req.l
* gas/arm/vfp-bad.l:
Update expected diagnostics.
* gas/arm/pic.d: Update expected reloc name.
* gas/arm/thumbv6.d: CPY no longer appears in disassembly.
* gas/arm/r15-bad.s: Avoid two-argument mul.
* gas/arm/req.s: Adjust comments.
* gas/arm/maverick.d, gas/arm/maverick.s: Avoid inappropriate
use of PC.
* gas/arm/macro-1.d, gas/arm/macro1.s
* gas/arm/t16-bad.l, gas/arm/t16-bad.s
* gas/arm/tcompat.d, gas/arm/tcompat.s
* gas/arm/tcompat2.d, gas/arm/tcompat2.s
* gas/arm/thumb32.d, gas/arm/thumb32.s
New test pair.
ld/testsuite:
* ld-arm/mixed-app.d: Adjust expected disassembly a little.
2005-05-18 07:40:12 +02:00
|
|
|
|
unsigned int Rn = (given & 0x000f0000) >> 16;
|
|
|
|
|
|
unsigned int off = (given & 0x000000ff);
|
|
|
|
|
|
|
|
|
|
|
|
func (stream, "[%s", arm_regnames[Rn]);
|
2009-11-11 10:44:45 +01:00
|
|
|
|
|
|
|
|
|
|
if (PRE_BIT_SET)
|
include/elf:
* arm.h: Import complete list of official relocation names
and numbers from AAELF. Define FAKE_RELOCs for old names.
Remove a few old names no longer used anywhere.
bfd:
* elf32-arm.c: Wherever possible, use official reloc names
from AAELF.
(elf32_arm_howto_table, elf32_arm_tls_gd32_howto)
(elf32_arm_tls_ldo32_howto, elf32_arm_tls_ldm32_howto)
(elf32_arm_tls_le32_howto, elf32_arm_tls_ie32_howto)
(elf32_arm_vtinherit_howto, elf32_arm_vtentry_howto)
(elf32_arm_pc11_howto, elf32_arm_thm_pc9_howto, elf32_arm_got_prel)
(elf32_arm_r_howto): Replace with elf32_arm_howto_table_1,
elf32_arm_howto_table_2, and elf32_arm_howto_table_3.
Add many new relocations from AAELF.
(elf32_arm_howto_from_type): Update to match.
(elf32_arm_reloc_map): Add entries for R_ARM_THM_JUMP24,
R_ARM_THM_JUMP11, R_ARM_THM_JUMP19, R_ARM_THM_JUMP8,
R_ARM_THM_JUMP6, R_ARM_GNU_VTINHERIT, and R_ARM_GNU_VTENTRY.
(elf32_arm_reloc_type_lookup): Use elf32_arm_howto_from_type.
(elf32_arm_final_link_relocate): Add support for
R_ARM_THM_JUMP24, R_ARM_THM_JUMP19, R_ARM_THM_JUMP6. Remove
case entries redundant with default.
* reloc.c: Reorganize ARM relocations. Add Thumb
assembler-internal relocations BFD_RELOC_ARM_T32_OFFSET_U8,
BFD_RELOC_ARM_T32_OFFSET_IMM, BFD_RELOC_ARM_T32_IMMEDIATE.
Add visible relocations BFD_RELOC_THUMB_PCREL_BRANCH7,
BFD_RELOC_THUMB_BRANCH20, BFD_RELOC_THUMB_BRANCH25.
Delete unused relocations BFD_RELOC_ARM_GOT12, BFD_RELOC_ARM_COPY.
* bfd-in2.h, libbfd.h: Regenerate.
opcodes:
* arm-dis.c (thumb_opcodes): Add disassembly for V6T2 16-bit
instructions. Adjust disassembly of some opcodes to match
unified syntax.
(thumb32_opcodes): New table.
(print_insn_thumb): Rename print_insn_thumb16; don't handle
two-halfword branches here.
(print_insn_thumb32): New function.
(print_insn): Choose among print_insn_arm, print_insn_thumb16,
and print_insn_thumb32. Be consistent about order of
halfwords when printing 32-bit instructions.
gas:
* hash.c (hash_lookup): Add len parameter. All callers changed.
(hash_find_n): New interface.
* hash.h: Prototype hash_find_n.
* sb.c: Include as.h.
(scrub_from_sb, sb_to_scrub, scrub_position): New statics.
(sb_scrub_and_add_sb): New interface.
* sb.h: Prototype sb_scrub_and_add_sb.
* input-scrub.c (input_scrub_include_sb): Use sb_scrub_and_add_sb.
* config/tc-arm.h (TC_FORCE_RELOCATION_LOCAL): Remove
reference to BFD_RELOC_ARM_GOT12 which is never generated.
* config/tc-arm.c: Rewrite, adding Thumb-2 support.
gas/testsuite:
* gas/arm/arm.exp: Convert all existing "gas_test" tests to
"run_dump_test" tests. Run more tests unconditionally. Run new tests.
* gas/arm/arch4t.s, gas/arm/arch6zk.s, gas/arm/arm3.s, gas/arm/arm6.s
* gas/arm/arm7dm.s, gas/arm/bignum1.s, gas/arm/float.s
* gas/arm/immed.s, gas/arm/iwmmxt.s, gas/arm/offset.s, gas/arm/thumb.s:
Adjust to work as a dump test.
* gas/arm/arch4t.d, gas/arm/arch6zk.d, gas/arm/arm3.d, gas/arm/arm6.d
* gas/arm/arm7dm.d, gas/arm/bignum1.d, gas/arm/float.d
* gas/arm/immed.d, gas/arm/iwmmxt.d, gas/arm/offset.d, gas/arm/thumb.d:
New files.
* gas/arm/armv1-bad.l, gas/arm/armv1-bad.s: Remove tests for
diagnostics that don't happen in the first pass anymore.
* gas/arm/iwmmxt-bad.l, gas/arm/r15-bad.l, gas/arm/req.l
* gas/arm/vfp-bad.l:
Update expected diagnostics.
* gas/arm/pic.d: Update expected reloc name.
* gas/arm/thumbv6.d: CPY no longer appears in disassembly.
* gas/arm/r15-bad.s: Avoid two-argument mul.
* gas/arm/req.s: Adjust comments.
* gas/arm/maverick.d, gas/arm/maverick.s: Avoid inappropriate
use of PC.
* gas/arm/macro-1.d, gas/arm/macro1.s
* gas/arm/t16-bad.l, gas/arm/t16-bad.s
* gas/arm/tcompat.d, gas/arm/tcompat.s
* gas/arm/tcompat2.d, gas/arm/tcompat2.s
* gas/arm/thumb32.d, gas/arm/thumb32.s
New test pair.
ld/testsuite:
* ld-arm/mixed-app.d: Adjust expected disassembly a little.
2005-05-18 07:40:12 +02:00
|
|
|
|
{
|
|
|
|
|
|
if (off || !U)
|
2009-06-29 10:08:15 +02:00
|
|
|
|
{
|
|
|
|
|
|
func (stream, ", #%c%u", U ? '+' : '-', off * 4);
|
2017-05-02 11:28:09 +02:00
|
|
|
|
value_in_comment = off * 4 * (U ? 1 : -1);
|
2009-06-29 10:08:15 +02:00
|
|
|
|
}
|
include/elf:
* arm.h: Import complete list of official relocation names
and numbers from AAELF. Define FAKE_RELOCs for old names.
Remove a few old names no longer used anywhere.
bfd:
* elf32-arm.c: Wherever possible, use official reloc names
from AAELF.
(elf32_arm_howto_table, elf32_arm_tls_gd32_howto)
(elf32_arm_tls_ldo32_howto, elf32_arm_tls_ldm32_howto)
(elf32_arm_tls_le32_howto, elf32_arm_tls_ie32_howto)
(elf32_arm_vtinherit_howto, elf32_arm_vtentry_howto)
(elf32_arm_pc11_howto, elf32_arm_thm_pc9_howto, elf32_arm_got_prel)
(elf32_arm_r_howto): Replace with elf32_arm_howto_table_1,
elf32_arm_howto_table_2, and elf32_arm_howto_table_3.
Add many new relocations from AAELF.
(elf32_arm_howto_from_type): Update to match.
(elf32_arm_reloc_map): Add entries for R_ARM_THM_JUMP24,
R_ARM_THM_JUMP11, R_ARM_THM_JUMP19, R_ARM_THM_JUMP8,
R_ARM_THM_JUMP6, R_ARM_GNU_VTINHERIT, and R_ARM_GNU_VTENTRY.
(elf32_arm_reloc_type_lookup): Use elf32_arm_howto_from_type.
(elf32_arm_final_link_relocate): Add support for
R_ARM_THM_JUMP24, R_ARM_THM_JUMP19, R_ARM_THM_JUMP6. Remove
case entries redundant with default.
* reloc.c: Reorganize ARM relocations. Add Thumb
assembler-internal relocations BFD_RELOC_ARM_T32_OFFSET_U8,
BFD_RELOC_ARM_T32_OFFSET_IMM, BFD_RELOC_ARM_T32_IMMEDIATE.
Add visible relocations BFD_RELOC_THUMB_PCREL_BRANCH7,
BFD_RELOC_THUMB_BRANCH20, BFD_RELOC_THUMB_BRANCH25.
Delete unused relocations BFD_RELOC_ARM_GOT12, BFD_RELOC_ARM_COPY.
* bfd-in2.h, libbfd.h: Regenerate.
opcodes:
* arm-dis.c (thumb_opcodes): Add disassembly for V6T2 16-bit
instructions. Adjust disassembly of some opcodes to match
unified syntax.
(thumb32_opcodes): New table.
(print_insn_thumb): Rename print_insn_thumb16; don't handle
two-halfword branches here.
(print_insn_thumb32): New function.
(print_insn): Choose among print_insn_arm, print_insn_thumb16,
and print_insn_thumb32. Be consistent about order of
halfwords when printing 32-bit instructions.
gas:
* hash.c (hash_lookup): Add len parameter. All callers changed.
(hash_find_n): New interface.
* hash.h: Prototype hash_find_n.
* sb.c: Include as.h.
(scrub_from_sb, sb_to_scrub, scrub_position): New statics.
(sb_scrub_and_add_sb): New interface.
* sb.h: Prototype sb_scrub_and_add_sb.
* input-scrub.c (input_scrub_include_sb): Use sb_scrub_and_add_sb.
* config/tc-arm.h (TC_FORCE_RELOCATION_LOCAL): Remove
reference to BFD_RELOC_ARM_GOT12 which is never generated.
* config/tc-arm.c: Rewrite, adding Thumb-2 support.
gas/testsuite:
* gas/arm/arm.exp: Convert all existing "gas_test" tests to
"run_dump_test" tests. Run more tests unconditionally. Run new tests.
* gas/arm/arch4t.s, gas/arm/arch6zk.s, gas/arm/arm3.s, gas/arm/arm6.s
* gas/arm/arm7dm.s, gas/arm/bignum1.s, gas/arm/float.s
* gas/arm/immed.s, gas/arm/iwmmxt.s, gas/arm/offset.s, gas/arm/thumb.s:
Adjust to work as a dump test.
* gas/arm/arch4t.d, gas/arm/arch6zk.d, gas/arm/arm3.d, gas/arm/arm6.d
* gas/arm/arm7dm.d, gas/arm/bignum1.d, gas/arm/float.d
* gas/arm/immed.d, gas/arm/iwmmxt.d, gas/arm/offset.d, gas/arm/thumb.d:
New files.
* gas/arm/armv1-bad.l, gas/arm/armv1-bad.s: Remove tests for
diagnostics that don't happen in the first pass anymore.
* gas/arm/iwmmxt-bad.l, gas/arm/r15-bad.l, gas/arm/req.l
* gas/arm/vfp-bad.l:
Update expected diagnostics.
* gas/arm/pic.d: Update expected reloc name.
* gas/arm/thumbv6.d: CPY no longer appears in disassembly.
* gas/arm/r15-bad.s: Avoid two-argument mul.
* gas/arm/req.s: Adjust comments.
* gas/arm/maverick.d, gas/arm/maverick.s: Avoid inappropriate
use of PC.
* gas/arm/macro-1.d, gas/arm/macro1.s
* gas/arm/t16-bad.l, gas/arm/t16-bad.s
* gas/arm/tcompat.d, gas/arm/tcompat.s
* gas/arm/tcompat2.d, gas/arm/tcompat2.s
* gas/arm/thumb32.d, gas/arm/thumb32.s
New test pair.
ld/testsuite:
* ld-arm/mixed-app.d: Adjust expected disassembly a little.
2005-05-18 07:40:12 +02:00
|
|
|
|
func (stream, "]");
|
|
|
|
|
|
if (W)
|
|
|
|
|
|
func (stream, "!");
|
|
|
|
|
|
}
|
|
|
|
|
|
else
|
|
|
|
|
|
{
|
|
|
|
|
|
func (stream, "], ");
|
|
|
|
|
|
if (W)
|
2009-06-29 10:08:15 +02:00
|
|
|
|
{
|
|
|
|
|
|
func (stream, "#%c%u", U ? '+' : '-', off * 4);
|
2017-05-02 11:28:09 +02:00
|
|
|
|
value_in_comment = off * 4 * (U ? 1 : -1);
|
2009-06-29 10:08:15 +02:00
|
|
|
|
}
|
include/elf:
* arm.h: Import complete list of official relocation names
and numbers from AAELF. Define FAKE_RELOCs for old names.
Remove a few old names no longer used anywhere.
bfd:
* elf32-arm.c: Wherever possible, use official reloc names
from AAELF.
(elf32_arm_howto_table, elf32_arm_tls_gd32_howto)
(elf32_arm_tls_ldo32_howto, elf32_arm_tls_ldm32_howto)
(elf32_arm_tls_le32_howto, elf32_arm_tls_ie32_howto)
(elf32_arm_vtinherit_howto, elf32_arm_vtentry_howto)
(elf32_arm_pc11_howto, elf32_arm_thm_pc9_howto, elf32_arm_got_prel)
(elf32_arm_r_howto): Replace with elf32_arm_howto_table_1,
elf32_arm_howto_table_2, and elf32_arm_howto_table_3.
Add many new relocations from AAELF.
(elf32_arm_howto_from_type): Update to match.
(elf32_arm_reloc_map): Add entries for R_ARM_THM_JUMP24,
R_ARM_THM_JUMP11, R_ARM_THM_JUMP19, R_ARM_THM_JUMP8,
R_ARM_THM_JUMP6, R_ARM_GNU_VTINHERIT, and R_ARM_GNU_VTENTRY.
(elf32_arm_reloc_type_lookup): Use elf32_arm_howto_from_type.
(elf32_arm_final_link_relocate): Add support for
R_ARM_THM_JUMP24, R_ARM_THM_JUMP19, R_ARM_THM_JUMP6. Remove
case entries redundant with default.
* reloc.c: Reorganize ARM relocations. Add Thumb
assembler-internal relocations BFD_RELOC_ARM_T32_OFFSET_U8,
BFD_RELOC_ARM_T32_OFFSET_IMM, BFD_RELOC_ARM_T32_IMMEDIATE.
Add visible relocations BFD_RELOC_THUMB_PCREL_BRANCH7,
BFD_RELOC_THUMB_BRANCH20, BFD_RELOC_THUMB_BRANCH25.
Delete unused relocations BFD_RELOC_ARM_GOT12, BFD_RELOC_ARM_COPY.
* bfd-in2.h, libbfd.h: Regenerate.
opcodes:
* arm-dis.c (thumb_opcodes): Add disassembly for V6T2 16-bit
instructions. Adjust disassembly of some opcodes to match
unified syntax.
(thumb32_opcodes): New table.
(print_insn_thumb): Rename print_insn_thumb16; don't handle
two-halfword branches here.
(print_insn_thumb32): New function.
(print_insn): Choose among print_insn_arm, print_insn_thumb16,
and print_insn_thumb32. Be consistent about order of
halfwords when printing 32-bit instructions.
gas:
* hash.c (hash_lookup): Add len parameter. All callers changed.
(hash_find_n): New interface.
* hash.h: Prototype hash_find_n.
* sb.c: Include as.h.
(scrub_from_sb, sb_to_scrub, scrub_position): New statics.
(sb_scrub_and_add_sb): New interface.
* sb.h: Prototype sb_scrub_and_add_sb.
* input-scrub.c (input_scrub_include_sb): Use sb_scrub_and_add_sb.
* config/tc-arm.h (TC_FORCE_RELOCATION_LOCAL): Remove
reference to BFD_RELOC_ARM_GOT12 which is never generated.
* config/tc-arm.c: Rewrite, adding Thumb-2 support.
gas/testsuite:
* gas/arm/arm.exp: Convert all existing "gas_test" tests to
"run_dump_test" tests. Run more tests unconditionally. Run new tests.
* gas/arm/arch4t.s, gas/arm/arch6zk.s, gas/arm/arm3.s, gas/arm/arm6.s
* gas/arm/arm7dm.s, gas/arm/bignum1.s, gas/arm/float.s
* gas/arm/immed.s, gas/arm/iwmmxt.s, gas/arm/offset.s, gas/arm/thumb.s:
Adjust to work as a dump test.
* gas/arm/arch4t.d, gas/arm/arch6zk.d, gas/arm/arm3.d, gas/arm/arm6.d
* gas/arm/arm7dm.d, gas/arm/bignum1.d, gas/arm/float.d
* gas/arm/immed.d, gas/arm/iwmmxt.d, gas/arm/offset.d, gas/arm/thumb.d:
New files.
* gas/arm/armv1-bad.l, gas/arm/armv1-bad.s: Remove tests for
diagnostics that don't happen in the first pass anymore.
* gas/arm/iwmmxt-bad.l, gas/arm/r15-bad.l, gas/arm/req.l
* gas/arm/vfp-bad.l:
Update expected diagnostics.
* gas/arm/pic.d: Update expected reloc name.
* gas/arm/thumbv6.d: CPY no longer appears in disassembly.
* gas/arm/r15-bad.s: Avoid two-argument mul.
* gas/arm/req.s: Adjust comments.
* gas/arm/maverick.d, gas/arm/maverick.s: Avoid inappropriate
use of PC.
* gas/arm/macro-1.d, gas/arm/macro1.s
* gas/arm/t16-bad.l, gas/arm/t16-bad.s
* gas/arm/tcompat.d, gas/arm/tcompat.s
* gas/arm/tcompat2.d, gas/arm/tcompat2.s
* gas/arm/thumb32.d, gas/arm/thumb32.s
New test pair.
ld/testsuite:
* ld-arm/mixed-app.d: Adjust expected disassembly a little.
2005-05-18 07:40:12 +02:00
|
|
|
|
else
|
2009-06-30 13:57:05 +02:00
|
|
|
|
{
|
|
|
|
|
|
func (stream, "{%u}", off);
|
|
|
|
|
|
value_in_comment = off;
|
|
|
|
|
|
}
|
include/elf:
* arm.h: Import complete list of official relocation names
and numbers from AAELF. Define FAKE_RELOCs for old names.
Remove a few old names no longer used anywhere.
bfd:
* elf32-arm.c: Wherever possible, use official reloc names
from AAELF.
(elf32_arm_howto_table, elf32_arm_tls_gd32_howto)
(elf32_arm_tls_ldo32_howto, elf32_arm_tls_ldm32_howto)
(elf32_arm_tls_le32_howto, elf32_arm_tls_ie32_howto)
(elf32_arm_vtinherit_howto, elf32_arm_vtentry_howto)
(elf32_arm_pc11_howto, elf32_arm_thm_pc9_howto, elf32_arm_got_prel)
(elf32_arm_r_howto): Replace with elf32_arm_howto_table_1,
elf32_arm_howto_table_2, and elf32_arm_howto_table_3.
Add many new relocations from AAELF.
(elf32_arm_howto_from_type): Update to match.
(elf32_arm_reloc_map): Add entries for R_ARM_THM_JUMP24,
R_ARM_THM_JUMP11, R_ARM_THM_JUMP19, R_ARM_THM_JUMP8,
R_ARM_THM_JUMP6, R_ARM_GNU_VTINHERIT, and R_ARM_GNU_VTENTRY.
(elf32_arm_reloc_type_lookup): Use elf32_arm_howto_from_type.
(elf32_arm_final_link_relocate): Add support for
R_ARM_THM_JUMP24, R_ARM_THM_JUMP19, R_ARM_THM_JUMP6. Remove
case entries redundant with default.
* reloc.c: Reorganize ARM relocations. Add Thumb
assembler-internal relocations BFD_RELOC_ARM_T32_OFFSET_U8,
BFD_RELOC_ARM_T32_OFFSET_IMM, BFD_RELOC_ARM_T32_IMMEDIATE.
Add visible relocations BFD_RELOC_THUMB_PCREL_BRANCH7,
BFD_RELOC_THUMB_BRANCH20, BFD_RELOC_THUMB_BRANCH25.
Delete unused relocations BFD_RELOC_ARM_GOT12, BFD_RELOC_ARM_COPY.
* bfd-in2.h, libbfd.h: Regenerate.
opcodes:
* arm-dis.c (thumb_opcodes): Add disassembly for V6T2 16-bit
instructions. Adjust disassembly of some opcodes to match
unified syntax.
(thumb32_opcodes): New table.
(print_insn_thumb): Rename print_insn_thumb16; don't handle
two-halfword branches here.
(print_insn_thumb32): New function.
(print_insn): Choose among print_insn_arm, print_insn_thumb16,
and print_insn_thumb32. Be consistent about order of
halfwords when printing 32-bit instructions.
gas:
* hash.c (hash_lookup): Add len parameter. All callers changed.
(hash_find_n): New interface.
* hash.h: Prototype hash_find_n.
* sb.c: Include as.h.
(scrub_from_sb, sb_to_scrub, scrub_position): New statics.
(sb_scrub_and_add_sb): New interface.
* sb.h: Prototype sb_scrub_and_add_sb.
* input-scrub.c (input_scrub_include_sb): Use sb_scrub_and_add_sb.
* config/tc-arm.h (TC_FORCE_RELOCATION_LOCAL): Remove
reference to BFD_RELOC_ARM_GOT12 which is never generated.
* config/tc-arm.c: Rewrite, adding Thumb-2 support.
gas/testsuite:
* gas/arm/arm.exp: Convert all existing "gas_test" tests to
"run_dump_test" tests. Run more tests unconditionally. Run new tests.
* gas/arm/arch4t.s, gas/arm/arch6zk.s, gas/arm/arm3.s, gas/arm/arm6.s
* gas/arm/arm7dm.s, gas/arm/bignum1.s, gas/arm/float.s
* gas/arm/immed.s, gas/arm/iwmmxt.s, gas/arm/offset.s, gas/arm/thumb.s:
Adjust to work as a dump test.
* gas/arm/arch4t.d, gas/arm/arch6zk.d, gas/arm/arm3.d, gas/arm/arm6.d
* gas/arm/arm7dm.d, gas/arm/bignum1.d, gas/arm/float.d
* gas/arm/immed.d, gas/arm/iwmmxt.d, gas/arm/offset.d, gas/arm/thumb.d:
New files.
* gas/arm/armv1-bad.l, gas/arm/armv1-bad.s: Remove tests for
diagnostics that don't happen in the first pass anymore.
* gas/arm/iwmmxt-bad.l, gas/arm/r15-bad.l, gas/arm/req.l
* gas/arm/vfp-bad.l:
Update expected diagnostics.
* gas/arm/pic.d: Update expected reloc name.
* gas/arm/thumbv6.d: CPY no longer appears in disassembly.
* gas/arm/r15-bad.s: Avoid two-argument mul.
* gas/arm/req.s: Adjust comments.
* gas/arm/maverick.d, gas/arm/maverick.s: Avoid inappropriate
use of PC.
* gas/arm/macro-1.d, gas/arm/macro1.s
* gas/arm/t16-bad.l, gas/arm/t16-bad.s
* gas/arm/tcompat.d, gas/arm/tcompat.s
* gas/arm/tcompat2.d, gas/arm/tcompat2.s
* gas/arm/thumb32.d, gas/arm/thumb32.s
New test pair.
ld/testsuite:
* ld-arm/mixed-app.d: Adjust expected disassembly a little.
2005-05-18 07:40:12 +02:00
|
|
|
|
}
|
|
|
|
|
|
}
|
|
|
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
|
|
case 'w':
|
|
|
|
|
|
{
|
|
|
|
|
|
unsigned int Sbit = (given & 0x01000000) >> 24;
|
|
|
|
|
|
unsigned int type = (given & 0x00600000) >> 21;
|
2009-06-29 10:08:15 +02:00
|
|
|
|
|
include/elf:
* arm.h: Import complete list of official relocation names
and numbers from AAELF. Define FAKE_RELOCs for old names.
Remove a few old names no longer used anywhere.
bfd:
* elf32-arm.c: Wherever possible, use official reloc names
from AAELF.
(elf32_arm_howto_table, elf32_arm_tls_gd32_howto)
(elf32_arm_tls_ldo32_howto, elf32_arm_tls_ldm32_howto)
(elf32_arm_tls_le32_howto, elf32_arm_tls_ie32_howto)
(elf32_arm_vtinherit_howto, elf32_arm_vtentry_howto)
(elf32_arm_pc11_howto, elf32_arm_thm_pc9_howto, elf32_arm_got_prel)
(elf32_arm_r_howto): Replace with elf32_arm_howto_table_1,
elf32_arm_howto_table_2, and elf32_arm_howto_table_3.
Add many new relocations from AAELF.
(elf32_arm_howto_from_type): Update to match.
(elf32_arm_reloc_map): Add entries for R_ARM_THM_JUMP24,
R_ARM_THM_JUMP11, R_ARM_THM_JUMP19, R_ARM_THM_JUMP8,
R_ARM_THM_JUMP6, R_ARM_GNU_VTINHERIT, and R_ARM_GNU_VTENTRY.
(elf32_arm_reloc_type_lookup): Use elf32_arm_howto_from_type.
(elf32_arm_final_link_relocate): Add support for
R_ARM_THM_JUMP24, R_ARM_THM_JUMP19, R_ARM_THM_JUMP6. Remove
case entries redundant with default.
* reloc.c: Reorganize ARM relocations. Add Thumb
assembler-internal relocations BFD_RELOC_ARM_T32_OFFSET_U8,
BFD_RELOC_ARM_T32_OFFSET_IMM, BFD_RELOC_ARM_T32_IMMEDIATE.
Add visible relocations BFD_RELOC_THUMB_PCREL_BRANCH7,
BFD_RELOC_THUMB_BRANCH20, BFD_RELOC_THUMB_BRANCH25.
Delete unused relocations BFD_RELOC_ARM_GOT12, BFD_RELOC_ARM_COPY.
* bfd-in2.h, libbfd.h: Regenerate.
opcodes:
* arm-dis.c (thumb_opcodes): Add disassembly for V6T2 16-bit
instructions. Adjust disassembly of some opcodes to match
unified syntax.
(thumb32_opcodes): New table.
(print_insn_thumb): Rename print_insn_thumb16; don't handle
two-halfword branches here.
(print_insn_thumb32): New function.
(print_insn): Choose among print_insn_arm, print_insn_thumb16,
and print_insn_thumb32. Be consistent about order of
halfwords when printing 32-bit instructions.
gas:
* hash.c (hash_lookup): Add len parameter. All callers changed.
(hash_find_n): New interface.
* hash.h: Prototype hash_find_n.
* sb.c: Include as.h.
(scrub_from_sb, sb_to_scrub, scrub_position): New statics.
(sb_scrub_and_add_sb): New interface.
* sb.h: Prototype sb_scrub_and_add_sb.
* input-scrub.c (input_scrub_include_sb): Use sb_scrub_and_add_sb.
* config/tc-arm.h (TC_FORCE_RELOCATION_LOCAL): Remove
reference to BFD_RELOC_ARM_GOT12 which is never generated.
* config/tc-arm.c: Rewrite, adding Thumb-2 support.
gas/testsuite:
* gas/arm/arm.exp: Convert all existing "gas_test" tests to
"run_dump_test" tests. Run more tests unconditionally. Run new tests.
* gas/arm/arch4t.s, gas/arm/arch6zk.s, gas/arm/arm3.s, gas/arm/arm6.s
* gas/arm/arm7dm.s, gas/arm/bignum1.s, gas/arm/float.s
* gas/arm/immed.s, gas/arm/iwmmxt.s, gas/arm/offset.s, gas/arm/thumb.s:
Adjust to work as a dump test.
* gas/arm/arch4t.d, gas/arm/arch6zk.d, gas/arm/arm3.d, gas/arm/arm6.d
* gas/arm/arm7dm.d, gas/arm/bignum1.d, gas/arm/float.d
* gas/arm/immed.d, gas/arm/iwmmxt.d, gas/arm/offset.d, gas/arm/thumb.d:
New files.
* gas/arm/armv1-bad.l, gas/arm/armv1-bad.s: Remove tests for
diagnostics that don't happen in the first pass anymore.
* gas/arm/iwmmxt-bad.l, gas/arm/r15-bad.l, gas/arm/req.l
* gas/arm/vfp-bad.l:
Update expected diagnostics.
* gas/arm/pic.d: Update expected reloc name.
* gas/arm/thumbv6.d: CPY no longer appears in disassembly.
* gas/arm/r15-bad.s: Avoid two-argument mul.
* gas/arm/req.s: Adjust comments.
* gas/arm/maverick.d, gas/arm/maverick.s: Avoid inappropriate
use of PC.
* gas/arm/macro-1.d, gas/arm/macro1.s
* gas/arm/t16-bad.l, gas/arm/t16-bad.s
* gas/arm/tcompat.d, gas/arm/tcompat.s
* gas/arm/tcompat2.d, gas/arm/tcompat2.s
* gas/arm/thumb32.d, gas/arm/thumb32.s
New test pair.
ld/testsuite:
* ld-arm/mixed-app.d: Adjust expected disassembly a little.
2005-05-18 07:40:12 +02:00
|
|
|
|
switch (type)
|
|
|
|
|
|
{
|
|
|
|
|
|
case 0: func (stream, Sbit ? "sb" : "b"); break;
|
|
|
|
|
|
case 1: func (stream, Sbit ? "sh" : "h"); break;
|
|
|
|
|
|
case 2:
|
|
|
|
|
|
if (Sbit)
|
|
|
|
|
|
func (stream, "??");
|
|
|
|
|
|
break;
|
|
|
|
|
|
case 3:
|
|
|
|
|
|
func (stream, "??");
|
|
|
|
|
|
break;
|
|
|
|
|
|
}
|
|
|
|
|
|
}
|
|
|
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
|
|
case 'm':
|
|
|
|
|
|
{
|
|
|
|
|
|
int started = 0;
|
|
|
|
|
|
int reg;
|
|
|
|
|
|
|
|
|
|
|
|
func (stream, "{");
|
|
|
|
|
|
for (reg = 0; reg < 16; reg++)
|
|
|
|
|
|
if ((given & (1 << reg)) != 0)
|
|
|
|
|
|
{
|
|
|
|
|
|
if (started)
|
|
|
|
|
|
func (stream, ", ");
|
|
|
|
|
|
started = 1;
|
|
|
|
|
|
func (stream, "%s", arm_regnames[reg]);
|
|
|
|
|
|
}
|
|
|
|
|
|
func (stream, "}");
|
|
|
|
|
|
}
|
|
|
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
|
|
case 'E':
|
|
|
|
|
|
{
|
|
|
|
|
|
unsigned int msb = (given & 0x0000001f);
|
|
|
|
|
|
unsigned int lsb = 0;
|
2009-06-30 13:57:05 +02:00
|
|
|
|
|
include/elf:
* arm.h: Import complete list of official relocation names
and numbers from AAELF. Define FAKE_RELOCs for old names.
Remove a few old names no longer used anywhere.
bfd:
* elf32-arm.c: Wherever possible, use official reloc names
from AAELF.
(elf32_arm_howto_table, elf32_arm_tls_gd32_howto)
(elf32_arm_tls_ldo32_howto, elf32_arm_tls_ldm32_howto)
(elf32_arm_tls_le32_howto, elf32_arm_tls_ie32_howto)
(elf32_arm_vtinherit_howto, elf32_arm_vtentry_howto)
(elf32_arm_pc11_howto, elf32_arm_thm_pc9_howto, elf32_arm_got_prel)
(elf32_arm_r_howto): Replace with elf32_arm_howto_table_1,
elf32_arm_howto_table_2, and elf32_arm_howto_table_3.
Add many new relocations from AAELF.
(elf32_arm_howto_from_type): Update to match.
(elf32_arm_reloc_map): Add entries for R_ARM_THM_JUMP24,
R_ARM_THM_JUMP11, R_ARM_THM_JUMP19, R_ARM_THM_JUMP8,
R_ARM_THM_JUMP6, R_ARM_GNU_VTINHERIT, and R_ARM_GNU_VTENTRY.
(elf32_arm_reloc_type_lookup): Use elf32_arm_howto_from_type.
(elf32_arm_final_link_relocate): Add support for
R_ARM_THM_JUMP24, R_ARM_THM_JUMP19, R_ARM_THM_JUMP6. Remove
case entries redundant with default.
* reloc.c: Reorganize ARM relocations. Add Thumb
assembler-internal relocations BFD_RELOC_ARM_T32_OFFSET_U8,
BFD_RELOC_ARM_T32_OFFSET_IMM, BFD_RELOC_ARM_T32_IMMEDIATE.
Add visible relocations BFD_RELOC_THUMB_PCREL_BRANCH7,
BFD_RELOC_THUMB_BRANCH20, BFD_RELOC_THUMB_BRANCH25.
Delete unused relocations BFD_RELOC_ARM_GOT12, BFD_RELOC_ARM_COPY.
* bfd-in2.h, libbfd.h: Regenerate.
opcodes:
* arm-dis.c (thumb_opcodes): Add disassembly for V6T2 16-bit
instructions. Adjust disassembly of some opcodes to match
unified syntax.
(thumb32_opcodes): New table.
(print_insn_thumb): Rename print_insn_thumb16; don't handle
two-halfword branches here.
(print_insn_thumb32): New function.
(print_insn): Choose among print_insn_arm, print_insn_thumb16,
and print_insn_thumb32. Be consistent about order of
halfwords when printing 32-bit instructions.
gas:
* hash.c (hash_lookup): Add len parameter. All callers changed.
(hash_find_n): New interface.
* hash.h: Prototype hash_find_n.
* sb.c: Include as.h.
(scrub_from_sb, sb_to_scrub, scrub_position): New statics.
(sb_scrub_and_add_sb): New interface.
* sb.h: Prototype sb_scrub_and_add_sb.
* input-scrub.c (input_scrub_include_sb): Use sb_scrub_and_add_sb.
* config/tc-arm.h (TC_FORCE_RELOCATION_LOCAL): Remove
reference to BFD_RELOC_ARM_GOT12 which is never generated.
* config/tc-arm.c: Rewrite, adding Thumb-2 support.
gas/testsuite:
* gas/arm/arm.exp: Convert all existing "gas_test" tests to
"run_dump_test" tests. Run more tests unconditionally. Run new tests.
* gas/arm/arch4t.s, gas/arm/arch6zk.s, gas/arm/arm3.s, gas/arm/arm6.s
* gas/arm/arm7dm.s, gas/arm/bignum1.s, gas/arm/float.s
* gas/arm/immed.s, gas/arm/iwmmxt.s, gas/arm/offset.s, gas/arm/thumb.s:
Adjust to work as a dump test.
* gas/arm/arch4t.d, gas/arm/arch6zk.d, gas/arm/arm3.d, gas/arm/arm6.d
* gas/arm/arm7dm.d, gas/arm/bignum1.d, gas/arm/float.d
* gas/arm/immed.d, gas/arm/iwmmxt.d, gas/arm/offset.d, gas/arm/thumb.d:
New files.
* gas/arm/armv1-bad.l, gas/arm/armv1-bad.s: Remove tests for
diagnostics that don't happen in the first pass anymore.
* gas/arm/iwmmxt-bad.l, gas/arm/r15-bad.l, gas/arm/req.l
* gas/arm/vfp-bad.l:
Update expected diagnostics.
* gas/arm/pic.d: Update expected reloc name.
* gas/arm/thumbv6.d: CPY no longer appears in disassembly.
* gas/arm/r15-bad.s: Avoid two-argument mul.
* gas/arm/req.s: Adjust comments.
* gas/arm/maverick.d, gas/arm/maverick.s: Avoid inappropriate
use of PC.
* gas/arm/macro-1.d, gas/arm/macro1.s
* gas/arm/t16-bad.l, gas/arm/t16-bad.s
* gas/arm/tcompat.d, gas/arm/tcompat.s
* gas/arm/tcompat2.d, gas/arm/tcompat2.s
* gas/arm/thumb32.d, gas/arm/thumb32.s
New test pair.
ld/testsuite:
* ld-arm/mixed-app.d: Adjust expected disassembly a little.
2005-05-18 07:40:12 +02:00
|
|
|
|
lsb |= (given & 0x000000c0u) >> 6;
|
|
|
|
|
|
lsb |= (given & 0x00007000u) >> 10;
|
|
|
|
|
|
func (stream, "#%u, #%u", lsb, msb - lsb + 1);
|
|
|
|
|
|
}
|
|
|
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
|
|
case 'F':
|
|
|
|
|
|
{
|
|
|
|
|
|
unsigned int width = (given & 0x0000001f) + 1;
|
|
|
|
|
|
unsigned int lsb = 0;
|
2009-06-30 13:57:05 +02:00
|
|
|
|
|
include/elf:
* arm.h: Import complete list of official relocation names
and numbers from AAELF. Define FAKE_RELOCs for old names.
Remove a few old names no longer used anywhere.
bfd:
* elf32-arm.c: Wherever possible, use official reloc names
from AAELF.
(elf32_arm_howto_table, elf32_arm_tls_gd32_howto)
(elf32_arm_tls_ldo32_howto, elf32_arm_tls_ldm32_howto)
(elf32_arm_tls_le32_howto, elf32_arm_tls_ie32_howto)
(elf32_arm_vtinherit_howto, elf32_arm_vtentry_howto)
(elf32_arm_pc11_howto, elf32_arm_thm_pc9_howto, elf32_arm_got_prel)
(elf32_arm_r_howto): Replace with elf32_arm_howto_table_1,
elf32_arm_howto_table_2, and elf32_arm_howto_table_3.
Add many new relocations from AAELF.
(elf32_arm_howto_from_type): Update to match.
(elf32_arm_reloc_map): Add entries for R_ARM_THM_JUMP24,
R_ARM_THM_JUMP11, R_ARM_THM_JUMP19, R_ARM_THM_JUMP8,
R_ARM_THM_JUMP6, R_ARM_GNU_VTINHERIT, and R_ARM_GNU_VTENTRY.
(elf32_arm_reloc_type_lookup): Use elf32_arm_howto_from_type.
(elf32_arm_final_link_relocate): Add support for
R_ARM_THM_JUMP24, R_ARM_THM_JUMP19, R_ARM_THM_JUMP6. Remove
case entries redundant with default.
* reloc.c: Reorganize ARM relocations. Add Thumb
assembler-internal relocations BFD_RELOC_ARM_T32_OFFSET_U8,
BFD_RELOC_ARM_T32_OFFSET_IMM, BFD_RELOC_ARM_T32_IMMEDIATE.
Add visible relocations BFD_RELOC_THUMB_PCREL_BRANCH7,
BFD_RELOC_THUMB_BRANCH20, BFD_RELOC_THUMB_BRANCH25.
Delete unused relocations BFD_RELOC_ARM_GOT12, BFD_RELOC_ARM_COPY.
* bfd-in2.h, libbfd.h: Regenerate.
opcodes:
* arm-dis.c (thumb_opcodes): Add disassembly for V6T2 16-bit
instructions. Adjust disassembly of some opcodes to match
unified syntax.
(thumb32_opcodes): New table.
(print_insn_thumb): Rename print_insn_thumb16; don't handle
two-halfword branches here.
(print_insn_thumb32): New function.
(print_insn): Choose among print_insn_arm, print_insn_thumb16,
and print_insn_thumb32. Be consistent about order of
halfwords when printing 32-bit instructions.
gas:
* hash.c (hash_lookup): Add len parameter. All callers changed.
(hash_find_n): New interface.
* hash.h: Prototype hash_find_n.
* sb.c: Include as.h.
(scrub_from_sb, sb_to_scrub, scrub_position): New statics.
(sb_scrub_and_add_sb): New interface.
* sb.h: Prototype sb_scrub_and_add_sb.
* input-scrub.c (input_scrub_include_sb): Use sb_scrub_and_add_sb.
* config/tc-arm.h (TC_FORCE_RELOCATION_LOCAL): Remove
reference to BFD_RELOC_ARM_GOT12 which is never generated.
* config/tc-arm.c: Rewrite, adding Thumb-2 support.
gas/testsuite:
* gas/arm/arm.exp: Convert all existing "gas_test" tests to
"run_dump_test" tests. Run more tests unconditionally. Run new tests.
* gas/arm/arch4t.s, gas/arm/arch6zk.s, gas/arm/arm3.s, gas/arm/arm6.s
* gas/arm/arm7dm.s, gas/arm/bignum1.s, gas/arm/float.s
* gas/arm/immed.s, gas/arm/iwmmxt.s, gas/arm/offset.s, gas/arm/thumb.s:
Adjust to work as a dump test.
* gas/arm/arch4t.d, gas/arm/arch6zk.d, gas/arm/arm3.d, gas/arm/arm6.d
* gas/arm/arm7dm.d, gas/arm/bignum1.d, gas/arm/float.d
* gas/arm/immed.d, gas/arm/iwmmxt.d, gas/arm/offset.d, gas/arm/thumb.d:
New files.
* gas/arm/armv1-bad.l, gas/arm/armv1-bad.s: Remove tests for
diagnostics that don't happen in the first pass anymore.
* gas/arm/iwmmxt-bad.l, gas/arm/r15-bad.l, gas/arm/req.l
* gas/arm/vfp-bad.l:
Update expected diagnostics.
* gas/arm/pic.d: Update expected reloc name.
* gas/arm/thumbv6.d: CPY no longer appears in disassembly.
* gas/arm/r15-bad.s: Avoid two-argument mul.
* gas/arm/req.s: Adjust comments.
* gas/arm/maverick.d, gas/arm/maverick.s: Avoid inappropriate
use of PC.
* gas/arm/macro-1.d, gas/arm/macro1.s
* gas/arm/t16-bad.l, gas/arm/t16-bad.s
* gas/arm/tcompat.d, gas/arm/tcompat.s
* gas/arm/tcompat2.d, gas/arm/tcompat2.s
* gas/arm/thumb32.d, gas/arm/thumb32.s
New test pair.
ld/testsuite:
* ld-arm/mixed-app.d: Adjust expected disassembly a little.
2005-05-18 07:40:12 +02:00
|
|
|
|
lsb |= (given & 0x000000c0u) >> 6;
|
|
|
|
|
|
lsb |= (given & 0x00007000u) >> 10;
|
|
|
|
|
|
func (stream, "#%u, #%u", lsb, width);
|
|
|
|
|
|
}
|
|
|
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
|
|
case 'b':
|
|
|
|
|
|
{
|
|
|
|
|
|
unsigned int S = (given & 0x04000000u) >> 26;
|
|
|
|
|
|
unsigned int J1 = (given & 0x00002000u) >> 13;
|
|
|
|
|
|
unsigned int J2 = (given & 0x00000800u) >> 11;
|
2011-06-03 12:04:03 +02:00
|
|
|
|
bfd_vma offset = 0;
|
include/elf:
* arm.h: Import complete list of official relocation names
and numbers from AAELF. Define FAKE_RELOCs for old names.
Remove a few old names no longer used anywhere.
bfd:
* elf32-arm.c: Wherever possible, use official reloc names
from AAELF.
(elf32_arm_howto_table, elf32_arm_tls_gd32_howto)
(elf32_arm_tls_ldo32_howto, elf32_arm_tls_ldm32_howto)
(elf32_arm_tls_le32_howto, elf32_arm_tls_ie32_howto)
(elf32_arm_vtinherit_howto, elf32_arm_vtentry_howto)
(elf32_arm_pc11_howto, elf32_arm_thm_pc9_howto, elf32_arm_got_prel)
(elf32_arm_r_howto): Replace with elf32_arm_howto_table_1,
elf32_arm_howto_table_2, and elf32_arm_howto_table_3.
Add many new relocations from AAELF.
(elf32_arm_howto_from_type): Update to match.
(elf32_arm_reloc_map): Add entries for R_ARM_THM_JUMP24,
R_ARM_THM_JUMP11, R_ARM_THM_JUMP19, R_ARM_THM_JUMP8,
R_ARM_THM_JUMP6, R_ARM_GNU_VTINHERIT, and R_ARM_GNU_VTENTRY.
(elf32_arm_reloc_type_lookup): Use elf32_arm_howto_from_type.
(elf32_arm_final_link_relocate): Add support for
R_ARM_THM_JUMP24, R_ARM_THM_JUMP19, R_ARM_THM_JUMP6. Remove
case entries redundant with default.
* reloc.c: Reorganize ARM relocations. Add Thumb
assembler-internal relocations BFD_RELOC_ARM_T32_OFFSET_U8,
BFD_RELOC_ARM_T32_OFFSET_IMM, BFD_RELOC_ARM_T32_IMMEDIATE.
Add visible relocations BFD_RELOC_THUMB_PCREL_BRANCH7,
BFD_RELOC_THUMB_BRANCH20, BFD_RELOC_THUMB_BRANCH25.
Delete unused relocations BFD_RELOC_ARM_GOT12, BFD_RELOC_ARM_COPY.
* bfd-in2.h, libbfd.h: Regenerate.
opcodes:
* arm-dis.c (thumb_opcodes): Add disassembly for V6T2 16-bit
instructions. Adjust disassembly of some opcodes to match
unified syntax.
(thumb32_opcodes): New table.
(print_insn_thumb): Rename print_insn_thumb16; don't handle
two-halfword branches here.
(print_insn_thumb32): New function.
(print_insn): Choose among print_insn_arm, print_insn_thumb16,
and print_insn_thumb32. Be consistent about order of
halfwords when printing 32-bit instructions.
gas:
* hash.c (hash_lookup): Add len parameter. All callers changed.
(hash_find_n): New interface.
* hash.h: Prototype hash_find_n.
* sb.c: Include as.h.
(scrub_from_sb, sb_to_scrub, scrub_position): New statics.
(sb_scrub_and_add_sb): New interface.
* sb.h: Prototype sb_scrub_and_add_sb.
* input-scrub.c (input_scrub_include_sb): Use sb_scrub_and_add_sb.
* config/tc-arm.h (TC_FORCE_RELOCATION_LOCAL): Remove
reference to BFD_RELOC_ARM_GOT12 which is never generated.
* config/tc-arm.c: Rewrite, adding Thumb-2 support.
gas/testsuite:
* gas/arm/arm.exp: Convert all existing "gas_test" tests to
"run_dump_test" tests. Run more tests unconditionally. Run new tests.
* gas/arm/arch4t.s, gas/arm/arch6zk.s, gas/arm/arm3.s, gas/arm/arm6.s
* gas/arm/arm7dm.s, gas/arm/bignum1.s, gas/arm/float.s
* gas/arm/immed.s, gas/arm/iwmmxt.s, gas/arm/offset.s, gas/arm/thumb.s:
Adjust to work as a dump test.
* gas/arm/arch4t.d, gas/arm/arch6zk.d, gas/arm/arm3.d, gas/arm/arm6.d
* gas/arm/arm7dm.d, gas/arm/bignum1.d, gas/arm/float.d
* gas/arm/immed.d, gas/arm/iwmmxt.d, gas/arm/offset.d, gas/arm/thumb.d:
New files.
* gas/arm/armv1-bad.l, gas/arm/armv1-bad.s: Remove tests for
diagnostics that don't happen in the first pass anymore.
* gas/arm/iwmmxt-bad.l, gas/arm/r15-bad.l, gas/arm/req.l
* gas/arm/vfp-bad.l:
Update expected diagnostics.
* gas/arm/pic.d: Update expected reloc name.
* gas/arm/thumbv6.d: CPY no longer appears in disassembly.
* gas/arm/r15-bad.s: Avoid two-argument mul.
* gas/arm/req.s: Adjust comments.
* gas/arm/maverick.d, gas/arm/maverick.s: Avoid inappropriate
use of PC.
* gas/arm/macro-1.d, gas/arm/macro1.s
* gas/arm/t16-bad.l, gas/arm/t16-bad.s
* gas/arm/tcompat.d, gas/arm/tcompat.s
* gas/arm/tcompat2.d, gas/arm/tcompat2.s
* gas/arm/thumb32.d, gas/arm/thumb32.s
New test pair.
ld/testsuite:
* ld-arm/mixed-app.d: Adjust expected disassembly a little.
2005-05-18 07:40:12 +02:00
|
|
|
|
|
|
|
|
|
|
offset |= !S << 20;
|
|
|
|
|
|
offset |= J2 << 19;
|
|
|
|
|
|
offset |= J1 << 18;
|
|
|
|
|
|
offset |= (given & 0x003f0000) >> 4;
|
|
|
|
|
|
offset |= (given & 0x000007ff) << 1;
|
|
|
|
|
|
offset -= (1 << 20);
|
|
|
|
|
|
|
|
|
|
|
|
info->print_address_func (pc + 4 + offset, info);
|
|
|
|
|
|
}
|
|
|
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
|
|
case 'B':
|
|
|
|
|
|
{
|
|
|
|
|
|
unsigned int S = (given & 0x04000000u) >> 26;
|
|
|
|
|
|
unsigned int I1 = (given & 0x00002000u) >> 13;
|
|
|
|
|
|
unsigned int I2 = (given & 0x00000800u) >> 11;
|
2011-06-03 12:04:03 +02:00
|
|
|
|
bfd_vma offset = 0;
|
include/elf:
* arm.h: Import complete list of official relocation names
and numbers from AAELF. Define FAKE_RELOCs for old names.
Remove a few old names no longer used anywhere.
bfd:
* elf32-arm.c: Wherever possible, use official reloc names
from AAELF.
(elf32_arm_howto_table, elf32_arm_tls_gd32_howto)
(elf32_arm_tls_ldo32_howto, elf32_arm_tls_ldm32_howto)
(elf32_arm_tls_le32_howto, elf32_arm_tls_ie32_howto)
(elf32_arm_vtinherit_howto, elf32_arm_vtentry_howto)
(elf32_arm_pc11_howto, elf32_arm_thm_pc9_howto, elf32_arm_got_prel)
(elf32_arm_r_howto): Replace with elf32_arm_howto_table_1,
elf32_arm_howto_table_2, and elf32_arm_howto_table_3.
Add many new relocations from AAELF.
(elf32_arm_howto_from_type): Update to match.
(elf32_arm_reloc_map): Add entries for R_ARM_THM_JUMP24,
R_ARM_THM_JUMP11, R_ARM_THM_JUMP19, R_ARM_THM_JUMP8,
R_ARM_THM_JUMP6, R_ARM_GNU_VTINHERIT, and R_ARM_GNU_VTENTRY.
(elf32_arm_reloc_type_lookup): Use elf32_arm_howto_from_type.
(elf32_arm_final_link_relocate): Add support for
R_ARM_THM_JUMP24, R_ARM_THM_JUMP19, R_ARM_THM_JUMP6. Remove
case entries redundant with default.
* reloc.c: Reorganize ARM relocations. Add Thumb
assembler-internal relocations BFD_RELOC_ARM_T32_OFFSET_U8,
BFD_RELOC_ARM_T32_OFFSET_IMM, BFD_RELOC_ARM_T32_IMMEDIATE.
Add visible relocations BFD_RELOC_THUMB_PCREL_BRANCH7,
BFD_RELOC_THUMB_BRANCH20, BFD_RELOC_THUMB_BRANCH25.
Delete unused relocations BFD_RELOC_ARM_GOT12, BFD_RELOC_ARM_COPY.
* bfd-in2.h, libbfd.h: Regenerate.
opcodes:
* arm-dis.c (thumb_opcodes): Add disassembly for V6T2 16-bit
instructions. Adjust disassembly of some opcodes to match
unified syntax.
(thumb32_opcodes): New table.
(print_insn_thumb): Rename print_insn_thumb16; don't handle
two-halfword branches here.
(print_insn_thumb32): New function.
(print_insn): Choose among print_insn_arm, print_insn_thumb16,
and print_insn_thumb32. Be consistent about order of
halfwords when printing 32-bit instructions.
gas:
* hash.c (hash_lookup): Add len parameter. All callers changed.
(hash_find_n): New interface.
* hash.h: Prototype hash_find_n.
* sb.c: Include as.h.
(scrub_from_sb, sb_to_scrub, scrub_position): New statics.
(sb_scrub_and_add_sb): New interface.
* sb.h: Prototype sb_scrub_and_add_sb.
* input-scrub.c (input_scrub_include_sb): Use sb_scrub_and_add_sb.
* config/tc-arm.h (TC_FORCE_RELOCATION_LOCAL): Remove
reference to BFD_RELOC_ARM_GOT12 which is never generated.
* config/tc-arm.c: Rewrite, adding Thumb-2 support.
gas/testsuite:
* gas/arm/arm.exp: Convert all existing "gas_test" tests to
"run_dump_test" tests. Run more tests unconditionally. Run new tests.
* gas/arm/arch4t.s, gas/arm/arch6zk.s, gas/arm/arm3.s, gas/arm/arm6.s
* gas/arm/arm7dm.s, gas/arm/bignum1.s, gas/arm/float.s
* gas/arm/immed.s, gas/arm/iwmmxt.s, gas/arm/offset.s, gas/arm/thumb.s:
Adjust to work as a dump test.
* gas/arm/arch4t.d, gas/arm/arch6zk.d, gas/arm/arm3.d, gas/arm/arm6.d
* gas/arm/arm7dm.d, gas/arm/bignum1.d, gas/arm/float.d
* gas/arm/immed.d, gas/arm/iwmmxt.d, gas/arm/offset.d, gas/arm/thumb.d:
New files.
* gas/arm/armv1-bad.l, gas/arm/armv1-bad.s: Remove tests for
diagnostics that don't happen in the first pass anymore.
* gas/arm/iwmmxt-bad.l, gas/arm/r15-bad.l, gas/arm/req.l
* gas/arm/vfp-bad.l:
Update expected diagnostics.
* gas/arm/pic.d: Update expected reloc name.
* gas/arm/thumbv6.d: CPY no longer appears in disassembly.
* gas/arm/r15-bad.s: Avoid two-argument mul.
* gas/arm/req.s: Adjust comments.
* gas/arm/maverick.d, gas/arm/maverick.s: Avoid inappropriate
use of PC.
* gas/arm/macro-1.d, gas/arm/macro1.s
* gas/arm/t16-bad.l, gas/arm/t16-bad.s
* gas/arm/tcompat.d, gas/arm/tcompat.s
* gas/arm/tcompat2.d, gas/arm/tcompat2.s
* gas/arm/thumb32.d, gas/arm/thumb32.s
New test pair.
ld/testsuite:
* ld-arm/mixed-app.d: Adjust expected disassembly a little.
2005-05-18 07:40:12 +02:00
|
|
|
|
|
|
|
|
|
|
offset |= !S << 24;
|
|
|
|
|
|
offset |= !(I1 ^ S) << 23;
|
|
|
|
|
|
offset |= !(I2 ^ S) << 22;
|
|
|
|
|
|
offset |= (given & 0x03ff0000u) >> 4;
|
|
|
|
|
|
offset |= (given & 0x000007ffu) << 1;
|
|
|
|
|
|
offset -= (1 << 24);
|
2005-11-02 17:53:11 +01:00
|
|
|
|
offset += pc + 4;
|
include/elf:
* arm.h: Import complete list of official relocation names
and numbers from AAELF. Define FAKE_RELOCs for old names.
Remove a few old names no longer used anywhere.
bfd:
* elf32-arm.c: Wherever possible, use official reloc names
from AAELF.
(elf32_arm_howto_table, elf32_arm_tls_gd32_howto)
(elf32_arm_tls_ldo32_howto, elf32_arm_tls_ldm32_howto)
(elf32_arm_tls_le32_howto, elf32_arm_tls_ie32_howto)
(elf32_arm_vtinherit_howto, elf32_arm_vtentry_howto)
(elf32_arm_pc11_howto, elf32_arm_thm_pc9_howto, elf32_arm_got_prel)
(elf32_arm_r_howto): Replace with elf32_arm_howto_table_1,
elf32_arm_howto_table_2, and elf32_arm_howto_table_3.
Add many new relocations from AAELF.
(elf32_arm_howto_from_type): Update to match.
(elf32_arm_reloc_map): Add entries for R_ARM_THM_JUMP24,
R_ARM_THM_JUMP11, R_ARM_THM_JUMP19, R_ARM_THM_JUMP8,
R_ARM_THM_JUMP6, R_ARM_GNU_VTINHERIT, and R_ARM_GNU_VTENTRY.
(elf32_arm_reloc_type_lookup): Use elf32_arm_howto_from_type.
(elf32_arm_final_link_relocate): Add support for
R_ARM_THM_JUMP24, R_ARM_THM_JUMP19, R_ARM_THM_JUMP6. Remove
case entries redundant with default.
* reloc.c: Reorganize ARM relocations. Add Thumb
assembler-internal relocations BFD_RELOC_ARM_T32_OFFSET_U8,
BFD_RELOC_ARM_T32_OFFSET_IMM, BFD_RELOC_ARM_T32_IMMEDIATE.
Add visible relocations BFD_RELOC_THUMB_PCREL_BRANCH7,
BFD_RELOC_THUMB_BRANCH20, BFD_RELOC_THUMB_BRANCH25.
Delete unused relocations BFD_RELOC_ARM_GOT12, BFD_RELOC_ARM_COPY.
* bfd-in2.h, libbfd.h: Regenerate.
opcodes:
* arm-dis.c (thumb_opcodes): Add disassembly for V6T2 16-bit
instructions. Adjust disassembly of some opcodes to match
unified syntax.
(thumb32_opcodes): New table.
(print_insn_thumb): Rename print_insn_thumb16; don't handle
two-halfword branches here.
(print_insn_thumb32): New function.
(print_insn): Choose among print_insn_arm, print_insn_thumb16,
and print_insn_thumb32. Be consistent about order of
halfwords when printing 32-bit instructions.
gas:
* hash.c (hash_lookup): Add len parameter. All callers changed.
(hash_find_n): New interface.
* hash.h: Prototype hash_find_n.
* sb.c: Include as.h.
(scrub_from_sb, sb_to_scrub, scrub_position): New statics.
(sb_scrub_and_add_sb): New interface.
* sb.h: Prototype sb_scrub_and_add_sb.
* input-scrub.c (input_scrub_include_sb): Use sb_scrub_and_add_sb.
* config/tc-arm.h (TC_FORCE_RELOCATION_LOCAL): Remove
reference to BFD_RELOC_ARM_GOT12 which is never generated.
* config/tc-arm.c: Rewrite, adding Thumb-2 support.
gas/testsuite:
* gas/arm/arm.exp: Convert all existing "gas_test" tests to
"run_dump_test" tests. Run more tests unconditionally. Run new tests.
* gas/arm/arch4t.s, gas/arm/arch6zk.s, gas/arm/arm3.s, gas/arm/arm6.s
* gas/arm/arm7dm.s, gas/arm/bignum1.s, gas/arm/float.s
* gas/arm/immed.s, gas/arm/iwmmxt.s, gas/arm/offset.s, gas/arm/thumb.s:
Adjust to work as a dump test.
* gas/arm/arch4t.d, gas/arm/arch6zk.d, gas/arm/arm3.d, gas/arm/arm6.d
* gas/arm/arm7dm.d, gas/arm/bignum1.d, gas/arm/float.d
* gas/arm/immed.d, gas/arm/iwmmxt.d, gas/arm/offset.d, gas/arm/thumb.d:
New files.
* gas/arm/armv1-bad.l, gas/arm/armv1-bad.s: Remove tests for
diagnostics that don't happen in the first pass anymore.
* gas/arm/iwmmxt-bad.l, gas/arm/r15-bad.l, gas/arm/req.l
* gas/arm/vfp-bad.l:
Update expected diagnostics.
* gas/arm/pic.d: Update expected reloc name.
* gas/arm/thumbv6.d: CPY no longer appears in disassembly.
* gas/arm/r15-bad.s: Avoid two-argument mul.
* gas/arm/req.s: Adjust comments.
* gas/arm/maverick.d, gas/arm/maverick.s: Avoid inappropriate
use of PC.
* gas/arm/macro-1.d, gas/arm/macro1.s
* gas/arm/t16-bad.l, gas/arm/t16-bad.s
* gas/arm/tcompat.d, gas/arm/tcompat.s
* gas/arm/tcompat2.d, gas/arm/tcompat2.s
* gas/arm/thumb32.d, gas/arm/thumb32.s
New test pair.
ld/testsuite:
* ld-arm/mixed-app.d: Adjust expected disassembly a little.
2005-05-18 07:40:12 +02:00
|
|
|
|
|
2005-11-02 17:53:11 +01:00
|
|
|
|
/* BLX target addresses are always word aligned. */
|
|
|
|
|
|
if ((given & 0x00001000u) == 0)
|
|
|
|
|
|
offset &= ~2u;
|
|
|
|
|
|
|
|
|
|
|
|
info->print_address_func (offset, info);
|
include/elf:
* arm.h: Import complete list of official relocation names
and numbers from AAELF. Define FAKE_RELOCs for old names.
Remove a few old names no longer used anywhere.
bfd:
* elf32-arm.c: Wherever possible, use official reloc names
from AAELF.
(elf32_arm_howto_table, elf32_arm_tls_gd32_howto)
(elf32_arm_tls_ldo32_howto, elf32_arm_tls_ldm32_howto)
(elf32_arm_tls_le32_howto, elf32_arm_tls_ie32_howto)
(elf32_arm_vtinherit_howto, elf32_arm_vtentry_howto)
(elf32_arm_pc11_howto, elf32_arm_thm_pc9_howto, elf32_arm_got_prel)
(elf32_arm_r_howto): Replace with elf32_arm_howto_table_1,
elf32_arm_howto_table_2, and elf32_arm_howto_table_3.
Add many new relocations from AAELF.
(elf32_arm_howto_from_type): Update to match.
(elf32_arm_reloc_map): Add entries for R_ARM_THM_JUMP24,
R_ARM_THM_JUMP11, R_ARM_THM_JUMP19, R_ARM_THM_JUMP8,
R_ARM_THM_JUMP6, R_ARM_GNU_VTINHERIT, and R_ARM_GNU_VTENTRY.
(elf32_arm_reloc_type_lookup): Use elf32_arm_howto_from_type.
(elf32_arm_final_link_relocate): Add support for
R_ARM_THM_JUMP24, R_ARM_THM_JUMP19, R_ARM_THM_JUMP6. Remove
case entries redundant with default.
* reloc.c: Reorganize ARM relocations. Add Thumb
assembler-internal relocations BFD_RELOC_ARM_T32_OFFSET_U8,
BFD_RELOC_ARM_T32_OFFSET_IMM, BFD_RELOC_ARM_T32_IMMEDIATE.
Add visible relocations BFD_RELOC_THUMB_PCREL_BRANCH7,
BFD_RELOC_THUMB_BRANCH20, BFD_RELOC_THUMB_BRANCH25.
Delete unused relocations BFD_RELOC_ARM_GOT12, BFD_RELOC_ARM_COPY.
* bfd-in2.h, libbfd.h: Regenerate.
opcodes:
* arm-dis.c (thumb_opcodes): Add disassembly for V6T2 16-bit
instructions. Adjust disassembly of some opcodes to match
unified syntax.
(thumb32_opcodes): New table.
(print_insn_thumb): Rename print_insn_thumb16; don't handle
two-halfword branches here.
(print_insn_thumb32): New function.
(print_insn): Choose among print_insn_arm, print_insn_thumb16,
and print_insn_thumb32. Be consistent about order of
halfwords when printing 32-bit instructions.
gas:
* hash.c (hash_lookup): Add len parameter. All callers changed.
(hash_find_n): New interface.
* hash.h: Prototype hash_find_n.
* sb.c: Include as.h.
(scrub_from_sb, sb_to_scrub, scrub_position): New statics.
(sb_scrub_and_add_sb): New interface.
* sb.h: Prototype sb_scrub_and_add_sb.
* input-scrub.c (input_scrub_include_sb): Use sb_scrub_and_add_sb.
* config/tc-arm.h (TC_FORCE_RELOCATION_LOCAL): Remove
reference to BFD_RELOC_ARM_GOT12 which is never generated.
* config/tc-arm.c: Rewrite, adding Thumb-2 support.
gas/testsuite:
* gas/arm/arm.exp: Convert all existing "gas_test" tests to
"run_dump_test" tests. Run more tests unconditionally. Run new tests.
* gas/arm/arch4t.s, gas/arm/arch6zk.s, gas/arm/arm3.s, gas/arm/arm6.s
* gas/arm/arm7dm.s, gas/arm/bignum1.s, gas/arm/float.s
* gas/arm/immed.s, gas/arm/iwmmxt.s, gas/arm/offset.s, gas/arm/thumb.s:
Adjust to work as a dump test.
* gas/arm/arch4t.d, gas/arm/arch6zk.d, gas/arm/arm3.d, gas/arm/arm6.d
* gas/arm/arm7dm.d, gas/arm/bignum1.d, gas/arm/float.d
* gas/arm/immed.d, gas/arm/iwmmxt.d, gas/arm/offset.d, gas/arm/thumb.d:
New files.
* gas/arm/armv1-bad.l, gas/arm/armv1-bad.s: Remove tests for
diagnostics that don't happen in the first pass anymore.
* gas/arm/iwmmxt-bad.l, gas/arm/r15-bad.l, gas/arm/req.l
* gas/arm/vfp-bad.l:
Update expected diagnostics.
* gas/arm/pic.d: Update expected reloc name.
* gas/arm/thumbv6.d: CPY no longer appears in disassembly.
* gas/arm/r15-bad.s: Avoid two-argument mul.
* gas/arm/req.s: Adjust comments.
* gas/arm/maverick.d, gas/arm/maverick.s: Avoid inappropriate
use of PC.
* gas/arm/macro-1.d, gas/arm/macro1.s
* gas/arm/t16-bad.l, gas/arm/t16-bad.s
* gas/arm/tcompat.d, gas/arm/tcompat.s
* gas/arm/tcompat2.d, gas/arm/tcompat2.s
* gas/arm/thumb32.d, gas/arm/thumb32.s
New test pair.
ld/testsuite:
* ld-arm/mixed-app.d: Adjust expected disassembly a little.
2005-05-18 07:40:12 +02:00
|
|
|
|
}
|
|
|
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
|
|
case 's':
|
|
|
|
|
|
{
|
|
|
|
|
|
unsigned int shift = 0;
|
2009-06-30 13:57:05 +02:00
|
|
|
|
|
include/elf:
* arm.h: Import complete list of official relocation names
and numbers from AAELF. Define FAKE_RELOCs for old names.
Remove a few old names no longer used anywhere.
bfd:
* elf32-arm.c: Wherever possible, use official reloc names
from AAELF.
(elf32_arm_howto_table, elf32_arm_tls_gd32_howto)
(elf32_arm_tls_ldo32_howto, elf32_arm_tls_ldm32_howto)
(elf32_arm_tls_le32_howto, elf32_arm_tls_ie32_howto)
(elf32_arm_vtinherit_howto, elf32_arm_vtentry_howto)
(elf32_arm_pc11_howto, elf32_arm_thm_pc9_howto, elf32_arm_got_prel)
(elf32_arm_r_howto): Replace with elf32_arm_howto_table_1,
elf32_arm_howto_table_2, and elf32_arm_howto_table_3.
Add many new relocations from AAELF.
(elf32_arm_howto_from_type): Update to match.
(elf32_arm_reloc_map): Add entries for R_ARM_THM_JUMP24,
R_ARM_THM_JUMP11, R_ARM_THM_JUMP19, R_ARM_THM_JUMP8,
R_ARM_THM_JUMP6, R_ARM_GNU_VTINHERIT, and R_ARM_GNU_VTENTRY.
(elf32_arm_reloc_type_lookup): Use elf32_arm_howto_from_type.
(elf32_arm_final_link_relocate): Add support for
R_ARM_THM_JUMP24, R_ARM_THM_JUMP19, R_ARM_THM_JUMP6. Remove
case entries redundant with default.
* reloc.c: Reorganize ARM relocations. Add Thumb
assembler-internal relocations BFD_RELOC_ARM_T32_OFFSET_U8,
BFD_RELOC_ARM_T32_OFFSET_IMM, BFD_RELOC_ARM_T32_IMMEDIATE.
Add visible relocations BFD_RELOC_THUMB_PCREL_BRANCH7,
BFD_RELOC_THUMB_BRANCH20, BFD_RELOC_THUMB_BRANCH25.
Delete unused relocations BFD_RELOC_ARM_GOT12, BFD_RELOC_ARM_COPY.
* bfd-in2.h, libbfd.h: Regenerate.
opcodes:
* arm-dis.c (thumb_opcodes): Add disassembly for V6T2 16-bit
instructions. Adjust disassembly of some opcodes to match
unified syntax.
(thumb32_opcodes): New table.
(print_insn_thumb): Rename print_insn_thumb16; don't handle
two-halfword branches here.
(print_insn_thumb32): New function.
(print_insn): Choose among print_insn_arm, print_insn_thumb16,
and print_insn_thumb32. Be consistent about order of
halfwords when printing 32-bit instructions.
gas:
* hash.c (hash_lookup): Add len parameter. All callers changed.
(hash_find_n): New interface.
* hash.h: Prototype hash_find_n.
* sb.c: Include as.h.
(scrub_from_sb, sb_to_scrub, scrub_position): New statics.
(sb_scrub_and_add_sb): New interface.
* sb.h: Prototype sb_scrub_and_add_sb.
* input-scrub.c (input_scrub_include_sb): Use sb_scrub_and_add_sb.
* config/tc-arm.h (TC_FORCE_RELOCATION_LOCAL): Remove
reference to BFD_RELOC_ARM_GOT12 which is never generated.
* config/tc-arm.c: Rewrite, adding Thumb-2 support.
gas/testsuite:
* gas/arm/arm.exp: Convert all existing "gas_test" tests to
"run_dump_test" tests. Run more tests unconditionally. Run new tests.
* gas/arm/arch4t.s, gas/arm/arch6zk.s, gas/arm/arm3.s, gas/arm/arm6.s
* gas/arm/arm7dm.s, gas/arm/bignum1.s, gas/arm/float.s
* gas/arm/immed.s, gas/arm/iwmmxt.s, gas/arm/offset.s, gas/arm/thumb.s:
Adjust to work as a dump test.
* gas/arm/arch4t.d, gas/arm/arch6zk.d, gas/arm/arm3.d, gas/arm/arm6.d
* gas/arm/arm7dm.d, gas/arm/bignum1.d, gas/arm/float.d
* gas/arm/immed.d, gas/arm/iwmmxt.d, gas/arm/offset.d, gas/arm/thumb.d:
New files.
* gas/arm/armv1-bad.l, gas/arm/armv1-bad.s: Remove tests for
diagnostics that don't happen in the first pass anymore.
* gas/arm/iwmmxt-bad.l, gas/arm/r15-bad.l, gas/arm/req.l
* gas/arm/vfp-bad.l:
Update expected diagnostics.
* gas/arm/pic.d: Update expected reloc name.
* gas/arm/thumbv6.d: CPY no longer appears in disassembly.
* gas/arm/r15-bad.s: Avoid two-argument mul.
* gas/arm/req.s: Adjust comments.
* gas/arm/maverick.d, gas/arm/maverick.s: Avoid inappropriate
use of PC.
* gas/arm/macro-1.d, gas/arm/macro1.s
* gas/arm/t16-bad.l, gas/arm/t16-bad.s
* gas/arm/tcompat.d, gas/arm/tcompat.s
* gas/arm/tcompat2.d, gas/arm/tcompat2.s
* gas/arm/thumb32.d, gas/arm/thumb32.s
New test pair.
ld/testsuite:
* ld-arm/mixed-app.d: Adjust expected disassembly a little.
2005-05-18 07:40:12 +02:00
|
|
|
|
shift |= (given & 0x000000c0u) >> 6;
|
|
|
|
|
|
shift |= (given & 0x00007000u) >> 10;
|
2009-11-11 10:44:45 +01:00
|
|
|
|
if (WRITEBACK_BIT_SET)
|
include/elf:
* arm.h: Import complete list of official relocation names
and numbers from AAELF. Define FAKE_RELOCs for old names.
Remove a few old names no longer used anywhere.
bfd:
* elf32-arm.c: Wherever possible, use official reloc names
from AAELF.
(elf32_arm_howto_table, elf32_arm_tls_gd32_howto)
(elf32_arm_tls_ldo32_howto, elf32_arm_tls_ldm32_howto)
(elf32_arm_tls_le32_howto, elf32_arm_tls_ie32_howto)
(elf32_arm_vtinherit_howto, elf32_arm_vtentry_howto)
(elf32_arm_pc11_howto, elf32_arm_thm_pc9_howto, elf32_arm_got_prel)
(elf32_arm_r_howto): Replace with elf32_arm_howto_table_1,
elf32_arm_howto_table_2, and elf32_arm_howto_table_3.
Add many new relocations from AAELF.
(elf32_arm_howto_from_type): Update to match.
(elf32_arm_reloc_map): Add entries for R_ARM_THM_JUMP24,
R_ARM_THM_JUMP11, R_ARM_THM_JUMP19, R_ARM_THM_JUMP8,
R_ARM_THM_JUMP6, R_ARM_GNU_VTINHERIT, and R_ARM_GNU_VTENTRY.
(elf32_arm_reloc_type_lookup): Use elf32_arm_howto_from_type.
(elf32_arm_final_link_relocate): Add support for
R_ARM_THM_JUMP24, R_ARM_THM_JUMP19, R_ARM_THM_JUMP6. Remove
case entries redundant with default.
* reloc.c: Reorganize ARM relocations. Add Thumb
assembler-internal relocations BFD_RELOC_ARM_T32_OFFSET_U8,
BFD_RELOC_ARM_T32_OFFSET_IMM, BFD_RELOC_ARM_T32_IMMEDIATE.
Add visible relocations BFD_RELOC_THUMB_PCREL_BRANCH7,
BFD_RELOC_THUMB_BRANCH20, BFD_RELOC_THUMB_BRANCH25.
Delete unused relocations BFD_RELOC_ARM_GOT12, BFD_RELOC_ARM_COPY.
* bfd-in2.h, libbfd.h: Regenerate.
opcodes:
* arm-dis.c (thumb_opcodes): Add disassembly for V6T2 16-bit
instructions. Adjust disassembly of some opcodes to match
unified syntax.
(thumb32_opcodes): New table.
(print_insn_thumb): Rename print_insn_thumb16; don't handle
two-halfword branches here.
(print_insn_thumb32): New function.
(print_insn): Choose among print_insn_arm, print_insn_thumb16,
and print_insn_thumb32. Be consistent about order of
halfwords when printing 32-bit instructions.
gas:
* hash.c (hash_lookup): Add len parameter. All callers changed.
(hash_find_n): New interface.
* hash.h: Prototype hash_find_n.
* sb.c: Include as.h.
(scrub_from_sb, sb_to_scrub, scrub_position): New statics.
(sb_scrub_and_add_sb): New interface.
* sb.h: Prototype sb_scrub_and_add_sb.
* input-scrub.c (input_scrub_include_sb): Use sb_scrub_and_add_sb.
* config/tc-arm.h (TC_FORCE_RELOCATION_LOCAL): Remove
reference to BFD_RELOC_ARM_GOT12 which is never generated.
* config/tc-arm.c: Rewrite, adding Thumb-2 support.
gas/testsuite:
* gas/arm/arm.exp: Convert all existing "gas_test" tests to
"run_dump_test" tests. Run more tests unconditionally. Run new tests.
* gas/arm/arch4t.s, gas/arm/arch6zk.s, gas/arm/arm3.s, gas/arm/arm6.s
* gas/arm/arm7dm.s, gas/arm/bignum1.s, gas/arm/float.s
* gas/arm/immed.s, gas/arm/iwmmxt.s, gas/arm/offset.s, gas/arm/thumb.s:
Adjust to work as a dump test.
* gas/arm/arch4t.d, gas/arm/arch6zk.d, gas/arm/arm3.d, gas/arm/arm6.d
* gas/arm/arm7dm.d, gas/arm/bignum1.d, gas/arm/float.d
* gas/arm/immed.d, gas/arm/iwmmxt.d, gas/arm/offset.d, gas/arm/thumb.d:
New files.
* gas/arm/armv1-bad.l, gas/arm/armv1-bad.s: Remove tests for
diagnostics that don't happen in the first pass anymore.
* gas/arm/iwmmxt-bad.l, gas/arm/r15-bad.l, gas/arm/req.l
* gas/arm/vfp-bad.l:
Update expected diagnostics.
* gas/arm/pic.d: Update expected reloc name.
* gas/arm/thumbv6.d: CPY no longer appears in disassembly.
* gas/arm/r15-bad.s: Avoid two-argument mul.
* gas/arm/req.s: Adjust comments.
* gas/arm/maverick.d, gas/arm/maverick.s: Avoid inappropriate
use of PC.
* gas/arm/macro-1.d, gas/arm/macro1.s
* gas/arm/t16-bad.l, gas/arm/t16-bad.s
* gas/arm/tcompat.d, gas/arm/tcompat.s
* gas/arm/tcompat2.d, gas/arm/tcompat2.s
* gas/arm/thumb32.d, gas/arm/thumb32.s
New test pair.
ld/testsuite:
* ld-arm/mixed-app.d: Adjust expected disassembly a little.
2005-05-18 07:40:12 +02:00
|
|
|
|
func (stream, ", asr #%u", shift);
|
|
|
|
|
|
else if (shift)
|
|
|
|
|
|
func (stream, ", lsl #%u", shift);
|
|
|
|
|
|
/* else print nothing - lsl #0 */
|
|
|
|
|
|
}
|
|
|
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
|
|
case 'R':
|
|
|
|
|
|
{
|
|
|
|
|
|
unsigned int rot = (given & 0x00000030) >> 4;
|
2009-06-30 13:57:05 +02:00
|
|
|
|
|
include/elf:
* arm.h: Import complete list of official relocation names
and numbers from AAELF. Define FAKE_RELOCs for old names.
Remove a few old names no longer used anywhere.
bfd:
* elf32-arm.c: Wherever possible, use official reloc names
from AAELF.
(elf32_arm_howto_table, elf32_arm_tls_gd32_howto)
(elf32_arm_tls_ldo32_howto, elf32_arm_tls_ldm32_howto)
(elf32_arm_tls_le32_howto, elf32_arm_tls_ie32_howto)
(elf32_arm_vtinherit_howto, elf32_arm_vtentry_howto)
(elf32_arm_pc11_howto, elf32_arm_thm_pc9_howto, elf32_arm_got_prel)
(elf32_arm_r_howto): Replace with elf32_arm_howto_table_1,
elf32_arm_howto_table_2, and elf32_arm_howto_table_3.
Add many new relocations from AAELF.
(elf32_arm_howto_from_type): Update to match.
(elf32_arm_reloc_map): Add entries for R_ARM_THM_JUMP24,
R_ARM_THM_JUMP11, R_ARM_THM_JUMP19, R_ARM_THM_JUMP8,
R_ARM_THM_JUMP6, R_ARM_GNU_VTINHERIT, and R_ARM_GNU_VTENTRY.
(elf32_arm_reloc_type_lookup): Use elf32_arm_howto_from_type.
(elf32_arm_final_link_relocate): Add support for
R_ARM_THM_JUMP24, R_ARM_THM_JUMP19, R_ARM_THM_JUMP6. Remove
case entries redundant with default.
* reloc.c: Reorganize ARM relocations. Add Thumb
assembler-internal relocations BFD_RELOC_ARM_T32_OFFSET_U8,
BFD_RELOC_ARM_T32_OFFSET_IMM, BFD_RELOC_ARM_T32_IMMEDIATE.
Add visible relocations BFD_RELOC_THUMB_PCREL_BRANCH7,
BFD_RELOC_THUMB_BRANCH20, BFD_RELOC_THUMB_BRANCH25.
Delete unused relocations BFD_RELOC_ARM_GOT12, BFD_RELOC_ARM_COPY.
* bfd-in2.h, libbfd.h: Regenerate.
opcodes:
* arm-dis.c (thumb_opcodes): Add disassembly for V6T2 16-bit
instructions. Adjust disassembly of some opcodes to match
unified syntax.
(thumb32_opcodes): New table.
(print_insn_thumb): Rename print_insn_thumb16; don't handle
two-halfword branches here.
(print_insn_thumb32): New function.
(print_insn): Choose among print_insn_arm, print_insn_thumb16,
and print_insn_thumb32. Be consistent about order of
halfwords when printing 32-bit instructions.
gas:
* hash.c (hash_lookup): Add len parameter. All callers changed.
(hash_find_n): New interface.
* hash.h: Prototype hash_find_n.
* sb.c: Include as.h.
(scrub_from_sb, sb_to_scrub, scrub_position): New statics.
(sb_scrub_and_add_sb): New interface.
* sb.h: Prototype sb_scrub_and_add_sb.
* input-scrub.c (input_scrub_include_sb): Use sb_scrub_and_add_sb.
* config/tc-arm.h (TC_FORCE_RELOCATION_LOCAL): Remove
reference to BFD_RELOC_ARM_GOT12 which is never generated.
* config/tc-arm.c: Rewrite, adding Thumb-2 support.
gas/testsuite:
* gas/arm/arm.exp: Convert all existing "gas_test" tests to
"run_dump_test" tests. Run more tests unconditionally. Run new tests.
* gas/arm/arch4t.s, gas/arm/arch6zk.s, gas/arm/arm3.s, gas/arm/arm6.s
* gas/arm/arm7dm.s, gas/arm/bignum1.s, gas/arm/float.s
* gas/arm/immed.s, gas/arm/iwmmxt.s, gas/arm/offset.s, gas/arm/thumb.s:
Adjust to work as a dump test.
* gas/arm/arch4t.d, gas/arm/arch6zk.d, gas/arm/arm3.d, gas/arm/arm6.d
* gas/arm/arm7dm.d, gas/arm/bignum1.d, gas/arm/float.d
* gas/arm/immed.d, gas/arm/iwmmxt.d, gas/arm/offset.d, gas/arm/thumb.d:
New files.
* gas/arm/armv1-bad.l, gas/arm/armv1-bad.s: Remove tests for
diagnostics that don't happen in the first pass anymore.
* gas/arm/iwmmxt-bad.l, gas/arm/r15-bad.l, gas/arm/req.l
* gas/arm/vfp-bad.l:
Update expected diagnostics.
* gas/arm/pic.d: Update expected reloc name.
* gas/arm/thumbv6.d: CPY no longer appears in disassembly.
* gas/arm/r15-bad.s: Avoid two-argument mul.
* gas/arm/req.s: Adjust comments.
* gas/arm/maverick.d, gas/arm/maverick.s: Avoid inappropriate
use of PC.
* gas/arm/macro-1.d, gas/arm/macro1.s
* gas/arm/t16-bad.l, gas/arm/t16-bad.s
* gas/arm/tcompat.d, gas/arm/tcompat.s
* gas/arm/tcompat2.d, gas/arm/tcompat2.s
* gas/arm/thumb32.d, gas/arm/thumb32.s
New test pair.
ld/testsuite:
* ld-arm/mixed-app.d: Adjust expected disassembly a little.
2005-05-18 07:40:12 +02:00
|
|
|
|
if (rot)
|
|
|
|
|
|
func (stream, ", ror #%u", rot * 8);
|
|
|
|
|
|
}
|
|
|
|
|
|
break;
|
|
|
|
|
|
|
2006-02-24 Paul Brook <paul@codesourcery.com>
gas/
* config/arm/tc-arm.c (arm_ext_v6_notm, arm_ext_div, arm_ext_v7,
arm_ext_v7a, arm_ext_v7r, arm_ext_v7m): New variables.
(struct asm_barrier_opt): Define.
(arm_v7m_psr_hsh, arm_barrier_opt_hsh): New variables.
(parse_psr): Accept V7M psr names.
(parse_barrier): New function.
(enum operand_parse_code): Add OP_oBARRIER.
(parse_operands): Implement OP_oBARRIER.
(do_barrier): New function.
(do_dbg, do_pli, do_t_barrier, do_t_dbg, do_t_div): New functions.
(do_t_cpsi): Add V7M restrictions.
(do_t_mrs, do_t_msr): Validate V7M variants.
(md_assemble): Check for NULL variants.
(v7m_psrs, barrier_opt_names): New tables.
(insns): Add V7 instructions. Mark V6 instructions absent from V7M.
(md_begin): Initialize arm_v7m_psr_hsh and arm_barrier_opt_hsh.
(arm_cpu_option_table): Add Cortex-M3, R4 and A8.
(arm_arch_option_table): Add armv7, armv7a, armv7r and armv7m.
(struct cpu_arch_ver_table): Define.
(cpu_arch_ver): New.
(aeabi_set_public_attributes): Use cpu_arch_ver. Set
Tag_CPU_arch_profile.
* doc/c-arm.texi: Document new cpu and arch options.
gas/testsuite/
* gas/arm/thumb32.d: Fix expected msr and mrs output.
* gas/arm/arch7.d: New test.
* gas/arm/arch7.s: New test.
* gas/arm/arch7m-bad.l: New test.
* gas/arm/arch7m-bad.d: New test.
* gas/arm/arch7m-bad.s: New test.
include/opcode/
* arm.h: Add V7 feature bits.
opcodes/
* arm-dis.c (arm_opcodes): Add V7 instructions.
(thumb32_opcodes): Ditto. Handle V7M MSR/MRS variants.
(print_arm_address): New function.
(print_insn_arm): Use it. Add 'P' and 'U' cases.
(psr_name): New function.
(print_insn_thumb32): Add 'U', 'C' and 'D' cases.
2006-02-24 16:36:36 +01:00
|
|
|
|
case 'U':
|
2015-08-12 13:45:07 +02:00
|
|
|
|
if ((given & 0xf0) == 0x60)
|
2006-02-24 Paul Brook <paul@codesourcery.com>
gas/
* config/arm/tc-arm.c (arm_ext_v6_notm, arm_ext_div, arm_ext_v7,
arm_ext_v7a, arm_ext_v7r, arm_ext_v7m): New variables.
(struct asm_barrier_opt): Define.
(arm_v7m_psr_hsh, arm_barrier_opt_hsh): New variables.
(parse_psr): Accept V7M psr names.
(parse_barrier): New function.
(enum operand_parse_code): Add OP_oBARRIER.
(parse_operands): Implement OP_oBARRIER.
(do_barrier): New function.
(do_dbg, do_pli, do_t_barrier, do_t_dbg, do_t_div): New functions.
(do_t_cpsi): Add V7M restrictions.
(do_t_mrs, do_t_msr): Validate V7M variants.
(md_assemble): Check for NULL variants.
(v7m_psrs, barrier_opt_names): New tables.
(insns): Add V7 instructions. Mark V6 instructions absent from V7M.
(md_begin): Initialize arm_v7m_psr_hsh and arm_barrier_opt_hsh.
(arm_cpu_option_table): Add Cortex-M3, R4 and A8.
(arm_arch_option_table): Add armv7, armv7a, armv7r and armv7m.
(struct cpu_arch_ver_table): Define.
(cpu_arch_ver): New.
(aeabi_set_public_attributes): Use cpu_arch_ver. Set
Tag_CPU_arch_profile.
* doc/c-arm.texi: Document new cpu and arch options.
gas/testsuite/
* gas/arm/thumb32.d: Fix expected msr and mrs output.
* gas/arm/arch7.d: New test.
* gas/arm/arch7.s: New test.
* gas/arm/arch7m-bad.l: New test.
* gas/arm/arch7m-bad.d: New test.
* gas/arm/arch7m-bad.s: New test.
include/opcode/
* arm.h: Add V7 feature bits.
opcodes/
* arm-dis.c (arm_opcodes): Add V7 instructions.
(thumb32_opcodes): Ditto. Handle V7M MSR/MRS variants.
(print_arm_address): New function.
(print_insn_arm): Use it. Add 'P' and 'U' cases.
(psr_name): New function.
(print_insn_thumb32): Add 'U', 'C' and 'D' cases.
2006-02-24 16:36:36 +01:00
|
|
|
|
{
|
2010-07-09 00:40:28 +02:00
|
|
|
|
switch (given & 0xf)
|
|
|
|
|
|
{
|
|
|
|
|
|
case 0xf: func (stream, "sy"); break;
|
|
|
|
|
|
default:
|
|
|
|
|
|
func (stream, "#%d", (int) given & 0xf);
|
|
|
|
|
|
break;
|
|
|
|
|
|
}
|
2006-02-24 Paul Brook <paul@codesourcery.com>
gas/
* config/arm/tc-arm.c (arm_ext_v6_notm, arm_ext_div, arm_ext_v7,
arm_ext_v7a, arm_ext_v7r, arm_ext_v7m): New variables.
(struct asm_barrier_opt): Define.
(arm_v7m_psr_hsh, arm_barrier_opt_hsh): New variables.
(parse_psr): Accept V7M psr names.
(parse_barrier): New function.
(enum operand_parse_code): Add OP_oBARRIER.
(parse_operands): Implement OP_oBARRIER.
(do_barrier): New function.
(do_dbg, do_pli, do_t_barrier, do_t_dbg, do_t_div): New functions.
(do_t_cpsi): Add V7M restrictions.
(do_t_mrs, do_t_msr): Validate V7M variants.
(md_assemble): Check for NULL variants.
(v7m_psrs, barrier_opt_names): New tables.
(insns): Add V7 instructions. Mark V6 instructions absent from V7M.
(md_begin): Initialize arm_v7m_psr_hsh and arm_barrier_opt_hsh.
(arm_cpu_option_table): Add Cortex-M3, R4 and A8.
(arm_arch_option_table): Add armv7, armv7a, armv7r and armv7m.
(struct cpu_arch_ver_table): Define.
(cpu_arch_ver): New.
(aeabi_set_public_attributes): Use cpu_arch_ver. Set
Tag_CPU_arch_profile.
* doc/c-arm.texi: Document new cpu and arch options.
gas/testsuite/
* gas/arm/thumb32.d: Fix expected msr and mrs output.
* gas/arm/arch7.d: New test.
* gas/arm/arch7.s: New test.
* gas/arm/arch7m-bad.l: New test.
* gas/arm/arch7m-bad.d: New test.
* gas/arm/arch7m-bad.s: New test.
include/opcode/
* arm.h: Add V7 feature bits.
opcodes/
* arm-dis.c (arm_opcodes): Add V7 instructions.
(thumb32_opcodes): Ditto. Handle V7M MSR/MRS variants.
(print_arm_address): New function.
(print_insn_arm): Use it. Add 'P' and 'U' cases.
(psr_name): New function.
(print_insn_thumb32): Add 'U', 'C' and 'D' cases.
2006-02-24 16:36:36 +01:00
|
|
|
|
}
|
2015-08-12 13:45:07 +02:00
|
|
|
|
else
|
2010-07-09 00:40:28 +02:00
|
|
|
|
{
|
2012-08-24 10:00:20 +02:00
|
|
|
|
const char * opt = data_barrier_option (given & 0xf);
|
|
|
|
|
|
if (opt != NULL)
|
|
|
|
|
|
func (stream, "%s", opt);
|
|
|
|
|
|
else
|
|
|
|
|
|
func (stream, "#%d", (int) given & 0xf);
|
2010-07-09 00:40:28 +02:00
|
|
|
|
}
|
2006-02-24 Paul Brook <paul@codesourcery.com>
gas/
* config/arm/tc-arm.c (arm_ext_v6_notm, arm_ext_div, arm_ext_v7,
arm_ext_v7a, arm_ext_v7r, arm_ext_v7m): New variables.
(struct asm_barrier_opt): Define.
(arm_v7m_psr_hsh, arm_barrier_opt_hsh): New variables.
(parse_psr): Accept V7M psr names.
(parse_barrier): New function.
(enum operand_parse_code): Add OP_oBARRIER.
(parse_operands): Implement OP_oBARRIER.
(do_barrier): New function.
(do_dbg, do_pli, do_t_barrier, do_t_dbg, do_t_div): New functions.
(do_t_cpsi): Add V7M restrictions.
(do_t_mrs, do_t_msr): Validate V7M variants.
(md_assemble): Check for NULL variants.
(v7m_psrs, barrier_opt_names): New tables.
(insns): Add V7 instructions. Mark V6 instructions absent from V7M.
(md_begin): Initialize arm_v7m_psr_hsh and arm_barrier_opt_hsh.
(arm_cpu_option_table): Add Cortex-M3, R4 and A8.
(arm_arch_option_table): Add armv7, armv7a, armv7r and armv7m.
(struct cpu_arch_ver_table): Define.
(cpu_arch_ver): New.
(aeabi_set_public_attributes): Use cpu_arch_ver. Set
Tag_CPU_arch_profile.
* doc/c-arm.texi: Document new cpu and arch options.
gas/testsuite/
* gas/arm/thumb32.d: Fix expected msr and mrs output.
* gas/arm/arch7.d: New test.
* gas/arm/arch7.s: New test.
* gas/arm/arch7m-bad.l: New test.
* gas/arm/arch7m-bad.d: New test.
* gas/arm/arch7m-bad.s: New test.
include/opcode/
* arm.h: Add V7 feature bits.
opcodes/
* arm-dis.c (arm_opcodes): Add V7 instructions.
(thumb32_opcodes): Ditto. Handle V7M MSR/MRS variants.
(print_arm_address): New function.
(print_insn_arm): Use it. Add 'P' and 'U' cases.
(psr_name): New function.
(print_insn_thumb32): Add 'U', 'C' and 'D' cases.
2006-02-24 16:36:36 +01:00
|
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
|
|
case 'C':
|
|
|
|
|
|
if ((given & 0xff) == 0)
|
|
|
|
|
|
{
|
|
|
|
|
|
func (stream, "%cPSR_", (given & 0x100000) ? 'S' : 'C');
|
|
|
|
|
|
if (given & 0x800)
|
|
|
|
|
|
func (stream, "f");
|
|
|
|
|
|
if (given & 0x400)
|
|
|
|
|
|
func (stream, "s");
|
|
|
|
|
|
if (given & 0x200)
|
|
|
|
|
|
func (stream, "x");
|
|
|
|
|
|
if (given & 0x100)
|
|
|
|
|
|
func (stream, "c");
|
|
|
|
|
|
}
|
2010-09-23 17:52:19 +02:00
|
|
|
|
else if ((given & 0x20) == 0x20)
|
|
|
|
|
|
{
|
|
|
|
|
|
char const* name;
|
|
|
|
|
|
unsigned sysm = (given & 0xf00) >> 8;
|
|
|
|
|
|
|
|
|
|
|
|
sysm |= (given & 0x30);
|
|
|
|
|
|
sysm |= (given & 0x00100000) >> 14;
|
|
|
|
|
|
name = banked_regname (sysm);
|
2015-08-12 13:45:07 +02:00
|
|
|
|
|
2010-09-23 17:52:19 +02:00
|
|
|
|
if (name != NULL)
|
|
|
|
|
|
func (stream, "%s", name);
|
|
|
|
|
|
else
|
2012-07-24 14:56:47 +02:00
|
|
|
|
func (stream, "(UNDEF: %lu)", (unsigned long) sysm);
|
2010-09-23 17:52:19 +02:00
|
|
|
|
}
|
2006-02-24 Paul Brook <paul@codesourcery.com>
gas/
* config/arm/tc-arm.c (arm_ext_v6_notm, arm_ext_div, arm_ext_v7,
arm_ext_v7a, arm_ext_v7r, arm_ext_v7m): New variables.
(struct asm_barrier_opt): Define.
(arm_v7m_psr_hsh, arm_barrier_opt_hsh): New variables.
(parse_psr): Accept V7M psr names.
(parse_barrier): New function.
(enum operand_parse_code): Add OP_oBARRIER.
(parse_operands): Implement OP_oBARRIER.
(do_barrier): New function.
(do_dbg, do_pli, do_t_barrier, do_t_dbg, do_t_div): New functions.
(do_t_cpsi): Add V7M restrictions.
(do_t_mrs, do_t_msr): Validate V7M variants.
(md_assemble): Check for NULL variants.
(v7m_psrs, barrier_opt_names): New tables.
(insns): Add V7 instructions. Mark V6 instructions absent from V7M.
(md_begin): Initialize arm_v7m_psr_hsh and arm_barrier_opt_hsh.
(arm_cpu_option_table): Add Cortex-M3, R4 and A8.
(arm_arch_option_table): Add armv7, armv7a, armv7r and armv7m.
(struct cpu_arch_ver_table): Define.
(cpu_arch_ver): New.
(aeabi_set_public_attributes): Use cpu_arch_ver. Set
Tag_CPU_arch_profile.
* doc/c-arm.texi: Document new cpu and arch options.
gas/testsuite/
* gas/arm/thumb32.d: Fix expected msr and mrs output.
* gas/arm/arch7.d: New test.
* gas/arm/arch7.s: New test.
* gas/arm/arch7m-bad.l: New test.
* gas/arm/arch7m-bad.d: New test.
* gas/arm/arch7m-bad.s: New test.
include/opcode/
* arm.h: Add V7 feature bits.
opcodes/
* arm-dis.c (arm_opcodes): Add V7 instructions.
(thumb32_opcodes): Ditto. Handle V7M MSR/MRS variants.
(print_arm_address): New function.
(print_insn_arm): Use it. Add 'P' and 'U' cases.
(psr_name): New function.
(print_insn_thumb32): Add 'U', 'C' and 'D' cases.
2006-02-24 16:36:36 +01:00
|
|
|
|
else
|
|
|
|
|
|
{
|
2012-07-24 14:56:47 +02:00
|
|
|
|
func (stream, "%s", psr_name (given & 0xff));
|
2006-02-24 Paul Brook <paul@codesourcery.com>
gas/
* config/arm/tc-arm.c (arm_ext_v6_notm, arm_ext_div, arm_ext_v7,
arm_ext_v7a, arm_ext_v7r, arm_ext_v7m): New variables.
(struct asm_barrier_opt): Define.
(arm_v7m_psr_hsh, arm_barrier_opt_hsh): New variables.
(parse_psr): Accept V7M psr names.
(parse_barrier): New function.
(enum operand_parse_code): Add OP_oBARRIER.
(parse_operands): Implement OP_oBARRIER.
(do_barrier): New function.
(do_dbg, do_pli, do_t_barrier, do_t_dbg, do_t_div): New functions.
(do_t_cpsi): Add V7M restrictions.
(do_t_mrs, do_t_msr): Validate V7M variants.
(md_assemble): Check for NULL variants.
(v7m_psrs, barrier_opt_names): New tables.
(insns): Add V7 instructions. Mark V6 instructions absent from V7M.
(md_begin): Initialize arm_v7m_psr_hsh and arm_barrier_opt_hsh.
(arm_cpu_option_table): Add Cortex-M3, R4 and A8.
(arm_arch_option_table): Add armv7, armv7a, armv7r and armv7m.
(struct cpu_arch_ver_table): Define.
(cpu_arch_ver): New.
(aeabi_set_public_attributes): Use cpu_arch_ver. Set
Tag_CPU_arch_profile.
* doc/c-arm.texi: Document new cpu and arch options.
gas/testsuite/
* gas/arm/thumb32.d: Fix expected msr and mrs output.
* gas/arm/arch7.d: New test.
* gas/arm/arch7.s: New test.
* gas/arm/arch7m-bad.l: New test.
* gas/arm/arch7m-bad.d: New test.
* gas/arm/arch7m-bad.s: New test.
include/opcode/
* arm.h: Add V7 feature bits.
opcodes/
* arm-dis.c (arm_opcodes): Add V7 instructions.
(thumb32_opcodes): Ditto. Handle V7M MSR/MRS variants.
(print_arm_address): New function.
(print_insn_arm): Use it. Add 'P' and 'U' cases.
(psr_name): New function.
(print_insn_thumb32): Add 'U', 'C' and 'D' cases.
2006-02-24 16:36:36 +01:00
|
|
|
|
}
|
|
|
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
|
|
case 'D':
|
2010-09-23 17:52:19 +02:00
|
|
|
|
if (((given & 0xff) == 0)
|
|
|
|
|
|
|| ((given & 0x20) == 0x20))
|
|
|
|
|
|
{
|
|
|
|
|
|
char const* name;
|
|
|
|
|
|
unsigned sm = (given & 0xf0000) >> 16;
|
|
|
|
|
|
|
|
|
|
|
|
sm |= (given & 0x30);
|
|
|
|
|
|
sm |= (given & 0x00100000) >> 14;
|
|
|
|
|
|
name = banked_regname (sm);
|
|
|
|
|
|
|
|
|
|
|
|
if (name != NULL)
|
|
|
|
|
|
func (stream, "%s", name);
|
|
|
|
|
|
else
|
2012-07-24 14:56:47 +02:00
|
|
|
|
func (stream, "(UNDEF: %lu)", (unsigned long) sm);
|
2010-09-23 17:52:19 +02:00
|
|
|
|
}
|
2006-02-24 Paul Brook <paul@codesourcery.com>
gas/
* config/arm/tc-arm.c (arm_ext_v6_notm, arm_ext_div, arm_ext_v7,
arm_ext_v7a, arm_ext_v7r, arm_ext_v7m): New variables.
(struct asm_barrier_opt): Define.
(arm_v7m_psr_hsh, arm_barrier_opt_hsh): New variables.
(parse_psr): Accept V7M psr names.
(parse_barrier): New function.
(enum operand_parse_code): Add OP_oBARRIER.
(parse_operands): Implement OP_oBARRIER.
(do_barrier): New function.
(do_dbg, do_pli, do_t_barrier, do_t_dbg, do_t_div): New functions.
(do_t_cpsi): Add V7M restrictions.
(do_t_mrs, do_t_msr): Validate V7M variants.
(md_assemble): Check for NULL variants.
(v7m_psrs, barrier_opt_names): New tables.
(insns): Add V7 instructions. Mark V6 instructions absent from V7M.
(md_begin): Initialize arm_v7m_psr_hsh and arm_barrier_opt_hsh.
(arm_cpu_option_table): Add Cortex-M3, R4 and A8.
(arm_arch_option_table): Add armv7, armv7a, armv7r and armv7m.
(struct cpu_arch_ver_table): Define.
(cpu_arch_ver): New.
(aeabi_set_public_attributes): Use cpu_arch_ver. Set
Tag_CPU_arch_profile.
* doc/c-arm.texi: Document new cpu and arch options.
gas/testsuite/
* gas/arm/thumb32.d: Fix expected msr and mrs output.
* gas/arm/arch7.d: New test.
* gas/arm/arch7.s: New test.
* gas/arm/arch7m-bad.l: New test.
* gas/arm/arch7m-bad.d: New test.
* gas/arm/arch7m-bad.s: New test.
include/opcode/
* arm.h: Add V7 feature bits.
opcodes/
* arm-dis.c (arm_opcodes): Add V7 instructions.
(thumb32_opcodes): Ditto. Handle V7M MSR/MRS variants.
(print_arm_address): New function.
(print_insn_arm): Use it. Add 'P' and 'U' cases.
(psr_name): New function.
(print_insn_thumb32): Add 'U', 'C' and 'D' cases.
2006-02-24 16:36:36 +01:00
|
|
|
|
else
|
2012-07-24 14:56:47 +02:00
|
|
|
|
func (stream, "%s", psr_name (given & 0xff));
|
2006-02-24 Paul Brook <paul@codesourcery.com>
gas/
* config/arm/tc-arm.c (arm_ext_v6_notm, arm_ext_div, arm_ext_v7,
arm_ext_v7a, arm_ext_v7r, arm_ext_v7m): New variables.
(struct asm_barrier_opt): Define.
(arm_v7m_psr_hsh, arm_barrier_opt_hsh): New variables.
(parse_psr): Accept V7M psr names.
(parse_barrier): New function.
(enum operand_parse_code): Add OP_oBARRIER.
(parse_operands): Implement OP_oBARRIER.
(do_barrier): New function.
(do_dbg, do_pli, do_t_barrier, do_t_dbg, do_t_div): New functions.
(do_t_cpsi): Add V7M restrictions.
(do_t_mrs, do_t_msr): Validate V7M variants.
(md_assemble): Check for NULL variants.
(v7m_psrs, barrier_opt_names): New tables.
(insns): Add V7 instructions. Mark V6 instructions absent from V7M.
(md_begin): Initialize arm_v7m_psr_hsh and arm_barrier_opt_hsh.
(arm_cpu_option_table): Add Cortex-M3, R4 and A8.
(arm_arch_option_table): Add armv7, armv7a, armv7r and armv7m.
(struct cpu_arch_ver_table): Define.
(cpu_arch_ver): New.
(aeabi_set_public_attributes): Use cpu_arch_ver. Set
Tag_CPU_arch_profile.
* doc/c-arm.texi: Document new cpu and arch options.
gas/testsuite/
* gas/arm/thumb32.d: Fix expected msr and mrs output.
* gas/arm/arch7.d: New test.
* gas/arm/arch7.s: New test.
* gas/arm/arch7m-bad.l: New test.
* gas/arm/arch7m-bad.d: New test.
* gas/arm/arch7m-bad.s: New test.
include/opcode/
* arm.h: Add V7 feature bits.
opcodes/
* arm-dis.c (arm_opcodes): Add V7 instructions.
(thumb32_opcodes): Ditto. Handle V7M MSR/MRS variants.
(print_arm_address): New function.
(print_insn_arm): Use it. Add 'P' and 'U' cases.
(psr_name): New function.
(print_insn_thumb32): Add 'U', 'C' and 'D' cases.
2006-02-24 16:36:36 +01:00
|
|
|
|
break;
|
|
|
|
|
|
|
include/elf:
* arm.h: Import complete list of official relocation names
and numbers from AAELF. Define FAKE_RELOCs for old names.
Remove a few old names no longer used anywhere.
bfd:
* elf32-arm.c: Wherever possible, use official reloc names
from AAELF.
(elf32_arm_howto_table, elf32_arm_tls_gd32_howto)
(elf32_arm_tls_ldo32_howto, elf32_arm_tls_ldm32_howto)
(elf32_arm_tls_le32_howto, elf32_arm_tls_ie32_howto)
(elf32_arm_vtinherit_howto, elf32_arm_vtentry_howto)
(elf32_arm_pc11_howto, elf32_arm_thm_pc9_howto, elf32_arm_got_prel)
(elf32_arm_r_howto): Replace with elf32_arm_howto_table_1,
elf32_arm_howto_table_2, and elf32_arm_howto_table_3.
Add many new relocations from AAELF.
(elf32_arm_howto_from_type): Update to match.
(elf32_arm_reloc_map): Add entries for R_ARM_THM_JUMP24,
R_ARM_THM_JUMP11, R_ARM_THM_JUMP19, R_ARM_THM_JUMP8,
R_ARM_THM_JUMP6, R_ARM_GNU_VTINHERIT, and R_ARM_GNU_VTENTRY.
(elf32_arm_reloc_type_lookup): Use elf32_arm_howto_from_type.
(elf32_arm_final_link_relocate): Add support for
R_ARM_THM_JUMP24, R_ARM_THM_JUMP19, R_ARM_THM_JUMP6. Remove
case entries redundant with default.
* reloc.c: Reorganize ARM relocations. Add Thumb
assembler-internal relocations BFD_RELOC_ARM_T32_OFFSET_U8,
BFD_RELOC_ARM_T32_OFFSET_IMM, BFD_RELOC_ARM_T32_IMMEDIATE.
Add visible relocations BFD_RELOC_THUMB_PCREL_BRANCH7,
BFD_RELOC_THUMB_BRANCH20, BFD_RELOC_THUMB_BRANCH25.
Delete unused relocations BFD_RELOC_ARM_GOT12, BFD_RELOC_ARM_COPY.
* bfd-in2.h, libbfd.h: Regenerate.
opcodes:
* arm-dis.c (thumb_opcodes): Add disassembly for V6T2 16-bit
instructions. Adjust disassembly of some opcodes to match
unified syntax.
(thumb32_opcodes): New table.
(print_insn_thumb): Rename print_insn_thumb16; don't handle
two-halfword branches here.
(print_insn_thumb32): New function.
(print_insn): Choose among print_insn_arm, print_insn_thumb16,
and print_insn_thumb32. Be consistent about order of
halfwords when printing 32-bit instructions.
gas:
* hash.c (hash_lookup): Add len parameter. All callers changed.
(hash_find_n): New interface.
* hash.h: Prototype hash_find_n.
* sb.c: Include as.h.
(scrub_from_sb, sb_to_scrub, scrub_position): New statics.
(sb_scrub_and_add_sb): New interface.
* sb.h: Prototype sb_scrub_and_add_sb.
* input-scrub.c (input_scrub_include_sb): Use sb_scrub_and_add_sb.
* config/tc-arm.h (TC_FORCE_RELOCATION_LOCAL): Remove
reference to BFD_RELOC_ARM_GOT12 which is never generated.
* config/tc-arm.c: Rewrite, adding Thumb-2 support.
gas/testsuite:
* gas/arm/arm.exp: Convert all existing "gas_test" tests to
"run_dump_test" tests. Run more tests unconditionally. Run new tests.
* gas/arm/arch4t.s, gas/arm/arch6zk.s, gas/arm/arm3.s, gas/arm/arm6.s
* gas/arm/arm7dm.s, gas/arm/bignum1.s, gas/arm/float.s
* gas/arm/immed.s, gas/arm/iwmmxt.s, gas/arm/offset.s, gas/arm/thumb.s:
Adjust to work as a dump test.
* gas/arm/arch4t.d, gas/arm/arch6zk.d, gas/arm/arm3.d, gas/arm/arm6.d
* gas/arm/arm7dm.d, gas/arm/bignum1.d, gas/arm/float.d
* gas/arm/immed.d, gas/arm/iwmmxt.d, gas/arm/offset.d, gas/arm/thumb.d:
New files.
* gas/arm/armv1-bad.l, gas/arm/armv1-bad.s: Remove tests for
diagnostics that don't happen in the first pass anymore.
* gas/arm/iwmmxt-bad.l, gas/arm/r15-bad.l, gas/arm/req.l
* gas/arm/vfp-bad.l:
Update expected diagnostics.
* gas/arm/pic.d: Update expected reloc name.
* gas/arm/thumbv6.d: CPY no longer appears in disassembly.
* gas/arm/r15-bad.s: Avoid two-argument mul.
* gas/arm/req.s: Adjust comments.
* gas/arm/maverick.d, gas/arm/maverick.s: Avoid inappropriate
use of PC.
* gas/arm/macro-1.d, gas/arm/macro1.s
* gas/arm/t16-bad.l, gas/arm/t16-bad.s
* gas/arm/tcompat.d, gas/arm/tcompat.s
* gas/arm/tcompat2.d, gas/arm/tcompat2.s
* gas/arm/thumb32.d, gas/arm/thumb32.s
New test pair.
ld/testsuite:
* ld-arm/mixed-app.d: Adjust expected disassembly a little.
2005-05-18 07:40:12 +02:00
|
|
|
|
case '0': case '1': case '2': case '3': case '4':
|
|
|
|
|
|
case '5': case '6': case '7': case '8': case '9':
|
|
|
|
|
|
{
|
2006-04-26 17:40:55 +02:00
|
|
|
|
int width;
|
|
|
|
|
|
unsigned long val;
|
include/elf:
* arm.h: Import complete list of official relocation names
and numbers from AAELF. Define FAKE_RELOCs for old names.
Remove a few old names no longer used anywhere.
bfd:
* elf32-arm.c: Wherever possible, use official reloc names
from AAELF.
(elf32_arm_howto_table, elf32_arm_tls_gd32_howto)
(elf32_arm_tls_ldo32_howto, elf32_arm_tls_ldm32_howto)
(elf32_arm_tls_le32_howto, elf32_arm_tls_ie32_howto)
(elf32_arm_vtinherit_howto, elf32_arm_vtentry_howto)
(elf32_arm_pc11_howto, elf32_arm_thm_pc9_howto, elf32_arm_got_prel)
(elf32_arm_r_howto): Replace with elf32_arm_howto_table_1,
elf32_arm_howto_table_2, and elf32_arm_howto_table_3.
Add many new relocations from AAELF.
(elf32_arm_howto_from_type): Update to match.
(elf32_arm_reloc_map): Add entries for R_ARM_THM_JUMP24,
R_ARM_THM_JUMP11, R_ARM_THM_JUMP19, R_ARM_THM_JUMP8,
R_ARM_THM_JUMP6, R_ARM_GNU_VTINHERIT, and R_ARM_GNU_VTENTRY.
(elf32_arm_reloc_type_lookup): Use elf32_arm_howto_from_type.
(elf32_arm_final_link_relocate): Add support for
R_ARM_THM_JUMP24, R_ARM_THM_JUMP19, R_ARM_THM_JUMP6. Remove
case entries redundant with default.
* reloc.c: Reorganize ARM relocations. Add Thumb
assembler-internal relocations BFD_RELOC_ARM_T32_OFFSET_U8,
BFD_RELOC_ARM_T32_OFFSET_IMM, BFD_RELOC_ARM_T32_IMMEDIATE.
Add visible relocations BFD_RELOC_THUMB_PCREL_BRANCH7,
BFD_RELOC_THUMB_BRANCH20, BFD_RELOC_THUMB_BRANCH25.
Delete unused relocations BFD_RELOC_ARM_GOT12, BFD_RELOC_ARM_COPY.
* bfd-in2.h, libbfd.h: Regenerate.
opcodes:
* arm-dis.c (thumb_opcodes): Add disassembly for V6T2 16-bit
instructions. Adjust disassembly of some opcodes to match
unified syntax.
(thumb32_opcodes): New table.
(print_insn_thumb): Rename print_insn_thumb16; don't handle
two-halfword branches here.
(print_insn_thumb32): New function.
(print_insn): Choose among print_insn_arm, print_insn_thumb16,
and print_insn_thumb32. Be consistent about order of
halfwords when printing 32-bit instructions.
gas:
* hash.c (hash_lookup): Add len parameter. All callers changed.
(hash_find_n): New interface.
* hash.h: Prototype hash_find_n.
* sb.c: Include as.h.
(scrub_from_sb, sb_to_scrub, scrub_position): New statics.
(sb_scrub_and_add_sb): New interface.
* sb.h: Prototype sb_scrub_and_add_sb.
* input-scrub.c (input_scrub_include_sb): Use sb_scrub_and_add_sb.
* config/tc-arm.h (TC_FORCE_RELOCATION_LOCAL): Remove
reference to BFD_RELOC_ARM_GOT12 which is never generated.
* config/tc-arm.c: Rewrite, adding Thumb-2 support.
gas/testsuite:
* gas/arm/arm.exp: Convert all existing "gas_test" tests to
"run_dump_test" tests. Run more tests unconditionally. Run new tests.
* gas/arm/arch4t.s, gas/arm/arch6zk.s, gas/arm/arm3.s, gas/arm/arm6.s
* gas/arm/arm7dm.s, gas/arm/bignum1.s, gas/arm/float.s
* gas/arm/immed.s, gas/arm/iwmmxt.s, gas/arm/offset.s, gas/arm/thumb.s:
Adjust to work as a dump test.
* gas/arm/arch4t.d, gas/arm/arch6zk.d, gas/arm/arm3.d, gas/arm/arm6.d
* gas/arm/arm7dm.d, gas/arm/bignum1.d, gas/arm/float.d
* gas/arm/immed.d, gas/arm/iwmmxt.d, gas/arm/offset.d, gas/arm/thumb.d:
New files.
* gas/arm/armv1-bad.l, gas/arm/armv1-bad.s: Remove tests for
diagnostics that don't happen in the first pass anymore.
* gas/arm/iwmmxt-bad.l, gas/arm/r15-bad.l, gas/arm/req.l
* gas/arm/vfp-bad.l:
Update expected diagnostics.
* gas/arm/pic.d: Update expected reloc name.
* gas/arm/thumbv6.d: CPY no longer appears in disassembly.
* gas/arm/r15-bad.s: Avoid two-argument mul.
* gas/arm/req.s: Adjust comments.
* gas/arm/maverick.d, gas/arm/maverick.s: Avoid inappropriate
use of PC.
* gas/arm/macro-1.d, gas/arm/macro1.s
* gas/arm/t16-bad.l, gas/arm/t16-bad.s
* gas/arm/tcompat.d, gas/arm/tcompat.s
* gas/arm/tcompat2.d, gas/arm/tcompat2.s
* gas/arm/thumb32.d, gas/arm/thumb32.s
New test pair.
ld/testsuite:
* ld-arm/mixed-app.d: Adjust expected disassembly a little.
2005-05-18 07:40:12 +02:00
|
|
|
|
|
2006-04-26 17:40:55 +02:00
|
|
|
|
c = arm_decode_bitfield (c, given, &val, &width);
|
2015-08-12 13:45:07 +02:00
|
|
|
|
|
include/elf:
* arm.h: Import complete list of official relocation names
and numbers from AAELF. Define FAKE_RELOCs for old names.
Remove a few old names no longer used anywhere.
bfd:
* elf32-arm.c: Wherever possible, use official reloc names
from AAELF.
(elf32_arm_howto_table, elf32_arm_tls_gd32_howto)
(elf32_arm_tls_ldo32_howto, elf32_arm_tls_ldm32_howto)
(elf32_arm_tls_le32_howto, elf32_arm_tls_ie32_howto)
(elf32_arm_vtinherit_howto, elf32_arm_vtentry_howto)
(elf32_arm_pc11_howto, elf32_arm_thm_pc9_howto, elf32_arm_got_prel)
(elf32_arm_r_howto): Replace with elf32_arm_howto_table_1,
elf32_arm_howto_table_2, and elf32_arm_howto_table_3.
Add many new relocations from AAELF.
(elf32_arm_howto_from_type): Update to match.
(elf32_arm_reloc_map): Add entries for R_ARM_THM_JUMP24,
R_ARM_THM_JUMP11, R_ARM_THM_JUMP19, R_ARM_THM_JUMP8,
R_ARM_THM_JUMP6, R_ARM_GNU_VTINHERIT, and R_ARM_GNU_VTENTRY.
(elf32_arm_reloc_type_lookup): Use elf32_arm_howto_from_type.
(elf32_arm_final_link_relocate): Add support for
R_ARM_THM_JUMP24, R_ARM_THM_JUMP19, R_ARM_THM_JUMP6. Remove
case entries redundant with default.
* reloc.c: Reorganize ARM relocations. Add Thumb
assembler-internal relocations BFD_RELOC_ARM_T32_OFFSET_U8,
BFD_RELOC_ARM_T32_OFFSET_IMM, BFD_RELOC_ARM_T32_IMMEDIATE.
Add visible relocations BFD_RELOC_THUMB_PCREL_BRANCH7,
BFD_RELOC_THUMB_BRANCH20, BFD_RELOC_THUMB_BRANCH25.
Delete unused relocations BFD_RELOC_ARM_GOT12, BFD_RELOC_ARM_COPY.
* bfd-in2.h, libbfd.h: Regenerate.
opcodes:
* arm-dis.c (thumb_opcodes): Add disassembly for V6T2 16-bit
instructions. Adjust disassembly of some opcodes to match
unified syntax.
(thumb32_opcodes): New table.
(print_insn_thumb): Rename print_insn_thumb16; don't handle
two-halfword branches here.
(print_insn_thumb32): New function.
(print_insn): Choose among print_insn_arm, print_insn_thumb16,
and print_insn_thumb32. Be consistent about order of
halfwords when printing 32-bit instructions.
gas:
* hash.c (hash_lookup): Add len parameter. All callers changed.
(hash_find_n): New interface.
* hash.h: Prototype hash_find_n.
* sb.c: Include as.h.
(scrub_from_sb, sb_to_scrub, scrub_position): New statics.
(sb_scrub_and_add_sb): New interface.
* sb.h: Prototype sb_scrub_and_add_sb.
* input-scrub.c (input_scrub_include_sb): Use sb_scrub_and_add_sb.
* config/tc-arm.h (TC_FORCE_RELOCATION_LOCAL): Remove
reference to BFD_RELOC_ARM_GOT12 which is never generated.
* config/tc-arm.c: Rewrite, adding Thumb-2 support.
gas/testsuite:
* gas/arm/arm.exp: Convert all existing "gas_test" tests to
"run_dump_test" tests. Run more tests unconditionally. Run new tests.
* gas/arm/arch4t.s, gas/arm/arch6zk.s, gas/arm/arm3.s, gas/arm/arm6.s
* gas/arm/arm7dm.s, gas/arm/bignum1.s, gas/arm/float.s
* gas/arm/immed.s, gas/arm/iwmmxt.s, gas/arm/offset.s, gas/arm/thumb.s:
Adjust to work as a dump test.
* gas/arm/arch4t.d, gas/arm/arch6zk.d, gas/arm/arm3.d, gas/arm/arm6.d
* gas/arm/arm7dm.d, gas/arm/bignum1.d, gas/arm/float.d
* gas/arm/immed.d, gas/arm/iwmmxt.d, gas/arm/offset.d, gas/arm/thumb.d:
New files.
* gas/arm/armv1-bad.l, gas/arm/armv1-bad.s: Remove tests for
diagnostics that don't happen in the first pass anymore.
* gas/arm/iwmmxt-bad.l, gas/arm/r15-bad.l, gas/arm/req.l
* gas/arm/vfp-bad.l:
Update expected diagnostics.
* gas/arm/pic.d: Update expected reloc name.
* gas/arm/thumbv6.d: CPY no longer appears in disassembly.
* gas/arm/r15-bad.s: Avoid two-argument mul.
* gas/arm/req.s: Adjust comments.
* gas/arm/maverick.d, gas/arm/maverick.s: Avoid inappropriate
use of PC.
* gas/arm/macro-1.d, gas/arm/macro1.s
* gas/arm/t16-bad.l, gas/arm/t16-bad.s
* gas/arm/tcompat.d, gas/arm/tcompat.s
* gas/arm/tcompat2.d, gas/arm/tcompat2.s
* gas/arm/thumb32.d, gas/arm/thumb32.s
New test pair.
ld/testsuite:
* ld-arm/mixed-app.d: Adjust expected disassembly a little.
2005-05-18 07:40:12 +02:00
|
|
|
|
switch (*c)
|
|
|
|
|
|
{
|
2009-06-29 10:08:15 +02:00
|
|
|
|
case 'd':
|
|
|
|
|
|
func (stream, "%lu", val);
|
|
|
|
|
|
value_in_comment = val;
|
|
|
|
|
|
break;
|
2009-12-17 10:52:18 +01:00
|
|
|
|
|
2015-04-15 18:44:03 +02:00
|
|
|
|
case 'D':
|
|
|
|
|
|
func (stream, "%lu", val + 1);
|
|
|
|
|
|
value_in_comment = val + 1;
|
|
|
|
|
|
break;
|
|
|
|
|
|
|
2009-06-29 10:08:15 +02:00
|
|
|
|
case 'W':
|
|
|
|
|
|
func (stream, "%lu", val * 4);
|
|
|
|
|
|
value_in_comment = val * 4;
|
|
|
|
|
|
break;
|
2009-12-17 10:52:18 +01:00
|
|
|
|
|
|
|
|
|
|
case 'R':
|
|
|
|
|
|
if (val == 15)
|
|
|
|
|
|
is_unpredictable = TRUE;
|
|
|
|
|
|
/* Fall through. */
|
|
|
|
|
|
case 'r':
|
|
|
|
|
|
func (stream, "%s", arm_regnames[val]);
|
|
|
|
|
|
break;
|
include/elf:
* arm.h: Import complete list of official relocation names
and numbers from AAELF. Define FAKE_RELOCs for old names.
Remove a few old names no longer used anywhere.
bfd:
* elf32-arm.c: Wherever possible, use official reloc names
from AAELF.
(elf32_arm_howto_table, elf32_arm_tls_gd32_howto)
(elf32_arm_tls_ldo32_howto, elf32_arm_tls_ldm32_howto)
(elf32_arm_tls_le32_howto, elf32_arm_tls_ie32_howto)
(elf32_arm_vtinherit_howto, elf32_arm_vtentry_howto)
(elf32_arm_pc11_howto, elf32_arm_thm_pc9_howto, elf32_arm_got_prel)
(elf32_arm_r_howto): Replace with elf32_arm_howto_table_1,
elf32_arm_howto_table_2, and elf32_arm_howto_table_3.
Add many new relocations from AAELF.
(elf32_arm_howto_from_type): Update to match.
(elf32_arm_reloc_map): Add entries for R_ARM_THM_JUMP24,
R_ARM_THM_JUMP11, R_ARM_THM_JUMP19, R_ARM_THM_JUMP8,
R_ARM_THM_JUMP6, R_ARM_GNU_VTINHERIT, and R_ARM_GNU_VTENTRY.
(elf32_arm_reloc_type_lookup): Use elf32_arm_howto_from_type.
(elf32_arm_final_link_relocate): Add support for
R_ARM_THM_JUMP24, R_ARM_THM_JUMP19, R_ARM_THM_JUMP6. Remove
case entries redundant with default.
* reloc.c: Reorganize ARM relocations. Add Thumb
assembler-internal relocations BFD_RELOC_ARM_T32_OFFSET_U8,
BFD_RELOC_ARM_T32_OFFSET_IMM, BFD_RELOC_ARM_T32_IMMEDIATE.
Add visible relocations BFD_RELOC_THUMB_PCREL_BRANCH7,
BFD_RELOC_THUMB_BRANCH20, BFD_RELOC_THUMB_BRANCH25.
Delete unused relocations BFD_RELOC_ARM_GOT12, BFD_RELOC_ARM_COPY.
* bfd-in2.h, libbfd.h: Regenerate.
opcodes:
* arm-dis.c (thumb_opcodes): Add disassembly for V6T2 16-bit
instructions. Adjust disassembly of some opcodes to match
unified syntax.
(thumb32_opcodes): New table.
(print_insn_thumb): Rename print_insn_thumb16; don't handle
two-halfword branches here.
(print_insn_thumb32): New function.
(print_insn): Choose among print_insn_arm, print_insn_thumb16,
and print_insn_thumb32. Be consistent about order of
halfwords when printing 32-bit instructions.
gas:
* hash.c (hash_lookup): Add len parameter. All callers changed.
(hash_find_n): New interface.
* hash.h: Prototype hash_find_n.
* sb.c: Include as.h.
(scrub_from_sb, sb_to_scrub, scrub_position): New statics.
(sb_scrub_and_add_sb): New interface.
* sb.h: Prototype sb_scrub_and_add_sb.
* input-scrub.c (input_scrub_include_sb): Use sb_scrub_and_add_sb.
* config/tc-arm.h (TC_FORCE_RELOCATION_LOCAL): Remove
reference to BFD_RELOC_ARM_GOT12 which is never generated.
* config/tc-arm.c: Rewrite, adding Thumb-2 support.
gas/testsuite:
* gas/arm/arm.exp: Convert all existing "gas_test" tests to
"run_dump_test" tests. Run more tests unconditionally. Run new tests.
* gas/arm/arch4t.s, gas/arm/arch6zk.s, gas/arm/arm3.s, gas/arm/arm6.s
* gas/arm/arm7dm.s, gas/arm/bignum1.s, gas/arm/float.s
* gas/arm/immed.s, gas/arm/iwmmxt.s, gas/arm/offset.s, gas/arm/thumb.s:
Adjust to work as a dump test.
* gas/arm/arch4t.d, gas/arm/arch6zk.d, gas/arm/arm3.d, gas/arm/arm6.d
* gas/arm/arm7dm.d, gas/arm/bignum1.d, gas/arm/float.d
* gas/arm/immed.d, gas/arm/iwmmxt.d, gas/arm/offset.d, gas/arm/thumb.d:
New files.
* gas/arm/armv1-bad.l, gas/arm/armv1-bad.s: Remove tests for
diagnostics that don't happen in the first pass anymore.
* gas/arm/iwmmxt-bad.l, gas/arm/r15-bad.l, gas/arm/req.l
* gas/arm/vfp-bad.l:
Update expected diagnostics.
* gas/arm/pic.d: Update expected reloc name.
* gas/arm/thumbv6.d: CPY no longer appears in disassembly.
* gas/arm/r15-bad.s: Avoid two-argument mul.
* gas/arm/req.s: Adjust comments.
* gas/arm/maverick.d, gas/arm/maverick.s: Avoid inappropriate
use of PC.
* gas/arm/macro-1.d, gas/arm/macro1.s
* gas/arm/t16-bad.l, gas/arm/t16-bad.s
* gas/arm/tcompat.d, gas/arm/tcompat.s
* gas/arm/tcompat2.d, gas/arm/tcompat2.s
* gas/arm/thumb32.d, gas/arm/thumb32.s
New test pair.
ld/testsuite:
* ld-arm/mixed-app.d: Adjust expected disassembly a little.
2005-05-18 07:40:12 +02:00
|
|
|
|
|
|
|
|
|
|
case 'c':
|
2006-06-07 16:08:19 +02:00
|
|
|
|
func (stream, "%s", arm_conditional[val]);
|
include/elf:
* arm.h: Import complete list of official relocation names
and numbers from AAELF. Define FAKE_RELOCs for old names.
Remove a few old names no longer used anywhere.
bfd:
* elf32-arm.c: Wherever possible, use official reloc names
from AAELF.
(elf32_arm_howto_table, elf32_arm_tls_gd32_howto)
(elf32_arm_tls_ldo32_howto, elf32_arm_tls_ldm32_howto)
(elf32_arm_tls_le32_howto, elf32_arm_tls_ie32_howto)
(elf32_arm_vtinherit_howto, elf32_arm_vtentry_howto)
(elf32_arm_pc11_howto, elf32_arm_thm_pc9_howto, elf32_arm_got_prel)
(elf32_arm_r_howto): Replace with elf32_arm_howto_table_1,
elf32_arm_howto_table_2, and elf32_arm_howto_table_3.
Add many new relocations from AAELF.
(elf32_arm_howto_from_type): Update to match.
(elf32_arm_reloc_map): Add entries for R_ARM_THM_JUMP24,
R_ARM_THM_JUMP11, R_ARM_THM_JUMP19, R_ARM_THM_JUMP8,
R_ARM_THM_JUMP6, R_ARM_GNU_VTINHERIT, and R_ARM_GNU_VTENTRY.
(elf32_arm_reloc_type_lookup): Use elf32_arm_howto_from_type.
(elf32_arm_final_link_relocate): Add support for
R_ARM_THM_JUMP24, R_ARM_THM_JUMP19, R_ARM_THM_JUMP6. Remove
case entries redundant with default.
* reloc.c: Reorganize ARM relocations. Add Thumb
assembler-internal relocations BFD_RELOC_ARM_T32_OFFSET_U8,
BFD_RELOC_ARM_T32_OFFSET_IMM, BFD_RELOC_ARM_T32_IMMEDIATE.
Add visible relocations BFD_RELOC_THUMB_PCREL_BRANCH7,
BFD_RELOC_THUMB_BRANCH20, BFD_RELOC_THUMB_BRANCH25.
Delete unused relocations BFD_RELOC_ARM_GOT12, BFD_RELOC_ARM_COPY.
* bfd-in2.h, libbfd.h: Regenerate.
opcodes:
* arm-dis.c (thumb_opcodes): Add disassembly for V6T2 16-bit
instructions. Adjust disassembly of some opcodes to match
unified syntax.
(thumb32_opcodes): New table.
(print_insn_thumb): Rename print_insn_thumb16; don't handle
two-halfword branches here.
(print_insn_thumb32): New function.
(print_insn): Choose among print_insn_arm, print_insn_thumb16,
and print_insn_thumb32. Be consistent about order of
halfwords when printing 32-bit instructions.
gas:
* hash.c (hash_lookup): Add len parameter. All callers changed.
(hash_find_n): New interface.
* hash.h: Prototype hash_find_n.
* sb.c: Include as.h.
(scrub_from_sb, sb_to_scrub, scrub_position): New statics.
(sb_scrub_and_add_sb): New interface.
* sb.h: Prototype sb_scrub_and_add_sb.
* input-scrub.c (input_scrub_include_sb): Use sb_scrub_and_add_sb.
* config/tc-arm.h (TC_FORCE_RELOCATION_LOCAL): Remove
reference to BFD_RELOC_ARM_GOT12 which is never generated.
* config/tc-arm.c: Rewrite, adding Thumb-2 support.
gas/testsuite:
* gas/arm/arm.exp: Convert all existing "gas_test" tests to
"run_dump_test" tests. Run more tests unconditionally. Run new tests.
* gas/arm/arch4t.s, gas/arm/arch6zk.s, gas/arm/arm3.s, gas/arm/arm6.s
* gas/arm/arm7dm.s, gas/arm/bignum1.s, gas/arm/float.s
* gas/arm/immed.s, gas/arm/iwmmxt.s, gas/arm/offset.s, gas/arm/thumb.s:
Adjust to work as a dump test.
* gas/arm/arch4t.d, gas/arm/arch6zk.d, gas/arm/arm3.d, gas/arm/arm6.d
* gas/arm/arm7dm.d, gas/arm/bignum1.d, gas/arm/float.d
* gas/arm/immed.d, gas/arm/iwmmxt.d, gas/arm/offset.d, gas/arm/thumb.d:
New files.
* gas/arm/armv1-bad.l, gas/arm/armv1-bad.s: Remove tests for
diagnostics that don't happen in the first pass anymore.
* gas/arm/iwmmxt-bad.l, gas/arm/r15-bad.l, gas/arm/req.l
* gas/arm/vfp-bad.l:
Update expected diagnostics.
* gas/arm/pic.d: Update expected reloc name.
* gas/arm/thumbv6.d: CPY no longer appears in disassembly.
* gas/arm/r15-bad.s: Avoid two-argument mul.
* gas/arm/req.s: Adjust comments.
* gas/arm/maverick.d, gas/arm/maverick.s: Avoid inappropriate
use of PC.
* gas/arm/macro-1.d, gas/arm/macro1.s
* gas/arm/t16-bad.l, gas/arm/t16-bad.s
* gas/arm/tcompat.d, gas/arm/tcompat.s
* gas/arm/tcompat2.d, gas/arm/tcompat2.s
* gas/arm/thumb32.d, gas/arm/thumb32.s
New test pair.
ld/testsuite:
* ld-arm/mixed-app.d: Adjust expected disassembly a little.
2005-05-18 07:40:12 +02:00
|
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
|
|
case '\'':
|
|
|
|
|
|
c++;
|
2006-04-26 17:40:55 +02:00
|
|
|
|
if (val == ((1ul << width) - 1))
|
|
|
|
|
|
func (stream, "%c", *c);
|
include/elf:
* arm.h: Import complete list of official relocation names
and numbers from AAELF. Define FAKE_RELOCs for old names.
Remove a few old names no longer used anywhere.
bfd:
* elf32-arm.c: Wherever possible, use official reloc names
from AAELF.
(elf32_arm_howto_table, elf32_arm_tls_gd32_howto)
(elf32_arm_tls_ldo32_howto, elf32_arm_tls_ldm32_howto)
(elf32_arm_tls_le32_howto, elf32_arm_tls_ie32_howto)
(elf32_arm_vtinherit_howto, elf32_arm_vtentry_howto)
(elf32_arm_pc11_howto, elf32_arm_thm_pc9_howto, elf32_arm_got_prel)
(elf32_arm_r_howto): Replace with elf32_arm_howto_table_1,
elf32_arm_howto_table_2, and elf32_arm_howto_table_3.
Add many new relocations from AAELF.
(elf32_arm_howto_from_type): Update to match.
(elf32_arm_reloc_map): Add entries for R_ARM_THM_JUMP24,
R_ARM_THM_JUMP11, R_ARM_THM_JUMP19, R_ARM_THM_JUMP8,
R_ARM_THM_JUMP6, R_ARM_GNU_VTINHERIT, and R_ARM_GNU_VTENTRY.
(elf32_arm_reloc_type_lookup): Use elf32_arm_howto_from_type.
(elf32_arm_final_link_relocate): Add support for
R_ARM_THM_JUMP24, R_ARM_THM_JUMP19, R_ARM_THM_JUMP6. Remove
case entries redundant with default.
* reloc.c: Reorganize ARM relocations. Add Thumb
assembler-internal relocations BFD_RELOC_ARM_T32_OFFSET_U8,
BFD_RELOC_ARM_T32_OFFSET_IMM, BFD_RELOC_ARM_T32_IMMEDIATE.
Add visible relocations BFD_RELOC_THUMB_PCREL_BRANCH7,
BFD_RELOC_THUMB_BRANCH20, BFD_RELOC_THUMB_BRANCH25.
Delete unused relocations BFD_RELOC_ARM_GOT12, BFD_RELOC_ARM_COPY.
* bfd-in2.h, libbfd.h: Regenerate.
opcodes:
* arm-dis.c (thumb_opcodes): Add disassembly for V6T2 16-bit
instructions. Adjust disassembly of some opcodes to match
unified syntax.
(thumb32_opcodes): New table.
(print_insn_thumb): Rename print_insn_thumb16; don't handle
two-halfword branches here.
(print_insn_thumb32): New function.
(print_insn): Choose among print_insn_arm, print_insn_thumb16,
and print_insn_thumb32. Be consistent about order of
halfwords when printing 32-bit instructions.
gas:
* hash.c (hash_lookup): Add len parameter. All callers changed.
(hash_find_n): New interface.
* hash.h: Prototype hash_find_n.
* sb.c: Include as.h.
(scrub_from_sb, sb_to_scrub, scrub_position): New statics.
(sb_scrub_and_add_sb): New interface.
* sb.h: Prototype sb_scrub_and_add_sb.
* input-scrub.c (input_scrub_include_sb): Use sb_scrub_and_add_sb.
* config/tc-arm.h (TC_FORCE_RELOCATION_LOCAL): Remove
reference to BFD_RELOC_ARM_GOT12 which is never generated.
* config/tc-arm.c: Rewrite, adding Thumb-2 support.
gas/testsuite:
* gas/arm/arm.exp: Convert all existing "gas_test" tests to
"run_dump_test" tests. Run more tests unconditionally. Run new tests.
* gas/arm/arch4t.s, gas/arm/arch6zk.s, gas/arm/arm3.s, gas/arm/arm6.s
* gas/arm/arm7dm.s, gas/arm/bignum1.s, gas/arm/float.s
* gas/arm/immed.s, gas/arm/iwmmxt.s, gas/arm/offset.s, gas/arm/thumb.s:
Adjust to work as a dump test.
* gas/arm/arch4t.d, gas/arm/arch6zk.d, gas/arm/arm3.d, gas/arm/arm6.d
* gas/arm/arm7dm.d, gas/arm/bignum1.d, gas/arm/float.d
* gas/arm/immed.d, gas/arm/iwmmxt.d, gas/arm/offset.d, gas/arm/thumb.d:
New files.
* gas/arm/armv1-bad.l, gas/arm/armv1-bad.s: Remove tests for
diagnostics that don't happen in the first pass anymore.
* gas/arm/iwmmxt-bad.l, gas/arm/r15-bad.l, gas/arm/req.l
* gas/arm/vfp-bad.l:
Update expected diagnostics.
* gas/arm/pic.d: Update expected reloc name.
* gas/arm/thumbv6.d: CPY no longer appears in disassembly.
* gas/arm/r15-bad.s: Avoid two-argument mul.
* gas/arm/req.s: Adjust comments.
* gas/arm/maverick.d, gas/arm/maverick.s: Avoid inappropriate
use of PC.
* gas/arm/macro-1.d, gas/arm/macro1.s
* gas/arm/t16-bad.l, gas/arm/t16-bad.s
* gas/arm/tcompat.d, gas/arm/tcompat.s
* gas/arm/tcompat2.d, gas/arm/tcompat2.s
* gas/arm/thumb32.d, gas/arm/thumb32.s
New test pair.
ld/testsuite:
* ld-arm/mixed-app.d: Adjust expected disassembly a little.
2005-05-18 07:40:12 +02:00
|
|
|
|
break;
|
2015-08-12 13:45:07 +02:00
|
|
|
|
|
include/elf:
* arm.h: Import complete list of official relocation names
and numbers from AAELF. Define FAKE_RELOCs for old names.
Remove a few old names no longer used anywhere.
bfd:
* elf32-arm.c: Wherever possible, use official reloc names
from AAELF.
(elf32_arm_howto_table, elf32_arm_tls_gd32_howto)
(elf32_arm_tls_ldo32_howto, elf32_arm_tls_ldm32_howto)
(elf32_arm_tls_le32_howto, elf32_arm_tls_ie32_howto)
(elf32_arm_vtinherit_howto, elf32_arm_vtentry_howto)
(elf32_arm_pc11_howto, elf32_arm_thm_pc9_howto, elf32_arm_got_prel)
(elf32_arm_r_howto): Replace with elf32_arm_howto_table_1,
elf32_arm_howto_table_2, and elf32_arm_howto_table_3.
Add many new relocations from AAELF.
(elf32_arm_howto_from_type): Update to match.
(elf32_arm_reloc_map): Add entries for R_ARM_THM_JUMP24,
R_ARM_THM_JUMP11, R_ARM_THM_JUMP19, R_ARM_THM_JUMP8,
R_ARM_THM_JUMP6, R_ARM_GNU_VTINHERIT, and R_ARM_GNU_VTENTRY.
(elf32_arm_reloc_type_lookup): Use elf32_arm_howto_from_type.
(elf32_arm_final_link_relocate): Add support for
R_ARM_THM_JUMP24, R_ARM_THM_JUMP19, R_ARM_THM_JUMP6. Remove
case entries redundant with default.
* reloc.c: Reorganize ARM relocations. Add Thumb
assembler-internal relocations BFD_RELOC_ARM_T32_OFFSET_U8,
BFD_RELOC_ARM_T32_OFFSET_IMM, BFD_RELOC_ARM_T32_IMMEDIATE.
Add visible relocations BFD_RELOC_THUMB_PCREL_BRANCH7,
BFD_RELOC_THUMB_BRANCH20, BFD_RELOC_THUMB_BRANCH25.
Delete unused relocations BFD_RELOC_ARM_GOT12, BFD_RELOC_ARM_COPY.
* bfd-in2.h, libbfd.h: Regenerate.
opcodes:
* arm-dis.c (thumb_opcodes): Add disassembly for V6T2 16-bit
instructions. Adjust disassembly of some opcodes to match
unified syntax.
(thumb32_opcodes): New table.
(print_insn_thumb): Rename print_insn_thumb16; don't handle
two-halfword branches here.
(print_insn_thumb32): New function.
(print_insn): Choose among print_insn_arm, print_insn_thumb16,
and print_insn_thumb32. Be consistent about order of
halfwords when printing 32-bit instructions.
gas:
* hash.c (hash_lookup): Add len parameter. All callers changed.
(hash_find_n): New interface.
* hash.h: Prototype hash_find_n.
* sb.c: Include as.h.
(scrub_from_sb, sb_to_scrub, scrub_position): New statics.
(sb_scrub_and_add_sb): New interface.
* sb.h: Prototype sb_scrub_and_add_sb.
* input-scrub.c (input_scrub_include_sb): Use sb_scrub_and_add_sb.
* config/tc-arm.h (TC_FORCE_RELOCATION_LOCAL): Remove
reference to BFD_RELOC_ARM_GOT12 which is never generated.
* config/tc-arm.c: Rewrite, adding Thumb-2 support.
gas/testsuite:
* gas/arm/arm.exp: Convert all existing "gas_test" tests to
"run_dump_test" tests. Run more tests unconditionally. Run new tests.
* gas/arm/arch4t.s, gas/arm/arch6zk.s, gas/arm/arm3.s, gas/arm/arm6.s
* gas/arm/arm7dm.s, gas/arm/bignum1.s, gas/arm/float.s
* gas/arm/immed.s, gas/arm/iwmmxt.s, gas/arm/offset.s, gas/arm/thumb.s:
Adjust to work as a dump test.
* gas/arm/arch4t.d, gas/arm/arch6zk.d, gas/arm/arm3.d, gas/arm/arm6.d
* gas/arm/arm7dm.d, gas/arm/bignum1.d, gas/arm/float.d
* gas/arm/immed.d, gas/arm/iwmmxt.d, gas/arm/offset.d, gas/arm/thumb.d:
New files.
* gas/arm/armv1-bad.l, gas/arm/armv1-bad.s: Remove tests for
diagnostics that don't happen in the first pass anymore.
* gas/arm/iwmmxt-bad.l, gas/arm/r15-bad.l, gas/arm/req.l
* gas/arm/vfp-bad.l:
Update expected diagnostics.
* gas/arm/pic.d: Update expected reloc name.
* gas/arm/thumbv6.d: CPY no longer appears in disassembly.
* gas/arm/r15-bad.s: Avoid two-argument mul.
* gas/arm/req.s: Adjust comments.
* gas/arm/maverick.d, gas/arm/maverick.s: Avoid inappropriate
use of PC.
* gas/arm/macro-1.d, gas/arm/macro1.s
* gas/arm/t16-bad.l, gas/arm/t16-bad.s
* gas/arm/tcompat.d, gas/arm/tcompat.s
* gas/arm/tcompat2.d, gas/arm/tcompat2.s
* gas/arm/thumb32.d, gas/arm/thumb32.s
New test pair.
ld/testsuite:
* ld-arm/mixed-app.d: Adjust expected disassembly a little.
2005-05-18 07:40:12 +02:00
|
|
|
|
case '`':
|
|
|
|
|
|
c++;
|
2006-04-26 17:40:55 +02:00
|
|
|
|
if (val == 0)
|
|
|
|
|
|
func (stream, "%c", *c);
|
include/elf:
* arm.h: Import complete list of official relocation names
and numbers from AAELF. Define FAKE_RELOCs for old names.
Remove a few old names no longer used anywhere.
bfd:
* elf32-arm.c: Wherever possible, use official reloc names
from AAELF.
(elf32_arm_howto_table, elf32_arm_tls_gd32_howto)
(elf32_arm_tls_ldo32_howto, elf32_arm_tls_ldm32_howto)
(elf32_arm_tls_le32_howto, elf32_arm_tls_ie32_howto)
(elf32_arm_vtinherit_howto, elf32_arm_vtentry_howto)
(elf32_arm_pc11_howto, elf32_arm_thm_pc9_howto, elf32_arm_got_prel)
(elf32_arm_r_howto): Replace with elf32_arm_howto_table_1,
elf32_arm_howto_table_2, and elf32_arm_howto_table_3.
Add many new relocations from AAELF.
(elf32_arm_howto_from_type): Update to match.
(elf32_arm_reloc_map): Add entries for R_ARM_THM_JUMP24,
R_ARM_THM_JUMP11, R_ARM_THM_JUMP19, R_ARM_THM_JUMP8,
R_ARM_THM_JUMP6, R_ARM_GNU_VTINHERIT, and R_ARM_GNU_VTENTRY.
(elf32_arm_reloc_type_lookup): Use elf32_arm_howto_from_type.
(elf32_arm_final_link_relocate): Add support for
R_ARM_THM_JUMP24, R_ARM_THM_JUMP19, R_ARM_THM_JUMP6. Remove
case entries redundant with default.
* reloc.c: Reorganize ARM relocations. Add Thumb
assembler-internal relocations BFD_RELOC_ARM_T32_OFFSET_U8,
BFD_RELOC_ARM_T32_OFFSET_IMM, BFD_RELOC_ARM_T32_IMMEDIATE.
Add visible relocations BFD_RELOC_THUMB_PCREL_BRANCH7,
BFD_RELOC_THUMB_BRANCH20, BFD_RELOC_THUMB_BRANCH25.
Delete unused relocations BFD_RELOC_ARM_GOT12, BFD_RELOC_ARM_COPY.
* bfd-in2.h, libbfd.h: Regenerate.
opcodes:
* arm-dis.c (thumb_opcodes): Add disassembly for V6T2 16-bit
instructions. Adjust disassembly of some opcodes to match
unified syntax.
(thumb32_opcodes): New table.
(print_insn_thumb): Rename print_insn_thumb16; don't handle
two-halfword branches here.
(print_insn_thumb32): New function.
(print_insn): Choose among print_insn_arm, print_insn_thumb16,
and print_insn_thumb32. Be consistent about order of
halfwords when printing 32-bit instructions.
gas:
* hash.c (hash_lookup): Add len parameter. All callers changed.
(hash_find_n): New interface.
* hash.h: Prototype hash_find_n.
* sb.c: Include as.h.
(scrub_from_sb, sb_to_scrub, scrub_position): New statics.
(sb_scrub_and_add_sb): New interface.
* sb.h: Prototype sb_scrub_and_add_sb.
* input-scrub.c (input_scrub_include_sb): Use sb_scrub_and_add_sb.
* config/tc-arm.h (TC_FORCE_RELOCATION_LOCAL): Remove
reference to BFD_RELOC_ARM_GOT12 which is never generated.
* config/tc-arm.c: Rewrite, adding Thumb-2 support.
gas/testsuite:
* gas/arm/arm.exp: Convert all existing "gas_test" tests to
"run_dump_test" tests. Run more tests unconditionally. Run new tests.
* gas/arm/arch4t.s, gas/arm/arch6zk.s, gas/arm/arm3.s, gas/arm/arm6.s
* gas/arm/arm7dm.s, gas/arm/bignum1.s, gas/arm/float.s
* gas/arm/immed.s, gas/arm/iwmmxt.s, gas/arm/offset.s, gas/arm/thumb.s:
Adjust to work as a dump test.
* gas/arm/arch4t.d, gas/arm/arch6zk.d, gas/arm/arm3.d, gas/arm/arm6.d
* gas/arm/arm7dm.d, gas/arm/bignum1.d, gas/arm/float.d
* gas/arm/immed.d, gas/arm/iwmmxt.d, gas/arm/offset.d, gas/arm/thumb.d:
New files.
* gas/arm/armv1-bad.l, gas/arm/armv1-bad.s: Remove tests for
diagnostics that don't happen in the first pass anymore.
* gas/arm/iwmmxt-bad.l, gas/arm/r15-bad.l, gas/arm/req.l
* gas/arm/vfp-bad.l:
Update expected diagnostics.
* gas/arm/pic.d: Update expected reloc name.
* gas/arm/thumbv6.d: CPY no longer appears in disassembly.
* gas/arm/r15-bad.s: Avoid two-argument mul.
* gas/arm/req.s: Adjust comments.
* gas/arm/maverick.d, gas/arm/maverick.s: Avoid inappropriate
use of PC.
* gas/arm/macro-1.d, gas/arm/macro1.s
* gas/arm/t16-bad.l, gas/arm/t16-bad.s
* gas/arm/tcompat.d, gas/arm/tcompat.s
* gas/arm/tcompat2.d, gas/arm/tcompat2.s
* gas/arm/thumb32.d, gas/arm/thumb32.s
New test pair.
ld/testsuite:
* ld-arm/mixed-app.d: Adjust expected disassembly a little.
2005-05-18 07:40:12 +02:00
|
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
|
|
case '?':
|
2009-06-30 13:57:05 +02:00
|
|
|
|
func (stream, "%c", c[(1 << width) - (int) val]);
|
2006-04-26 17:40:55 +02:00
|
|
|
|
c += 1 << width;
|
include/elf:
* arm.h: Import complete list of official relocation names
and numbers from AAELF. Define FAKE_RELOCs for old names.
Remove a few old names no longer used anywhere.
bfd:
* elf32-arm.c: Wherever possible, use official reloc names
from AAELF.
(elf32_arm_howto_table, elf32_arm_tls_gd32_howto)
(elf32_arm_tls_ldo32_howto, elf32_arm_tls_ldm32_howto)
(elf32_arm_tls_le32_howto, elf32_arm_tls_ie32_howto)
(elf32_arm_vtinherit_howto, elf32_arm_vtentry_howto)
(elf32_arm_pc11_howto, elf32_arm_thm_pc9_howto, elf32_arm_got_prel)
(elf32_arm_r_howto): Replace with elf32_arm_howto_table_1,
elf32_arm_howto_table_2, and elf32_arm_howto_table_3.
Add many new relocations from AAELF.
(elf32_arm_howto_from_type): Update to match.
(elf32_arm_reloc_map): Add entries for R_ARM_THM_JUMP24,
R_ARM_THM_JUMP11, R_ARM_THM_JUMP19, R_ARM_THM_JUMP8,
R_ARM_THM_JUMP6, R_ARM_GNU_VTINHERIT, and R_ARM_GNU_VTENTRY.
(elf32_arm_reloc_type_lookup): Use elf32_arm_howto_from_type.
(elf32_arm_final_link_relocate): Add support for
R_ARM_THM_JUMP24, R_ARM_THM_JUMP19, R_ARM_THM_JUMP6. Remove
case entries redundant with default.
* reloc.c: Reorganize ARM relocations. Add Thumb
assembler-internal relocations BFD_RELOC_ARM_T32_OFFSET_U8,
BFD_RELOC_ARM_T32_OFFSET_IMM, BFD_RELOC_ARM_T32_IMMEDIATE.
Add visible relocations BFD_RELOC_THUMB_PCREL_BRANCH7,
BFD_RELOC_THUMB_BRANCH20, BFD_RELOC_THUMB_BRANCH25.
Delete unused relocations BFD_RELOC_ARM_GOT12, BFD_RELOC_ARM_COPY.
* bfd-in2.h, libbfd.h: Regenerate.
opcodes:
* arm-dis.c (thumb_opcodes): Add disassembly for V6T2 16-bit
instructions. Adjust disassembly of some opcodes to match
unified syntax.
(thumb32_opcodes): New table.
(print_insn_thumb): Rename print_insn_thumb16; don't handle
two-halfword branches here.
(print_insn_thumb32): New function.
(print_insn): Choose among print_insn_arm, print_insn_thumb16,
and print_insn_thumb32. Be consistent about order of
halfwords when printing 32-bit instructions.
gas:
* hash.c (hash_lookup): Add len parameter. All callers changed.
(hash_find_n): New interface.
* hash.h: Prototype hash_find_n.
* sb.c: Include as.h.
(scrub_from_sb, sb_to_scrub, scrub_position): New statics.
(sb_scrub_and_add_sb): New interface.
* sb.h: Prototype sb_scrub_and_add_sb.
* input-scrub.c (input_scrub_include_sb): Use sb_scrub_and_add_sb.
* config/tc-arm.h (TC_FORCE_RELOCATION_LOCAL): Remove
reference to BFD_RELOC_ARM_GOT12 which is never generated.
* config/tc-arm.c: Rewrite, adding Thumb-2 support.
gas/testsuite:
* gas/arm/arm.exp: Convert all existing "gas_test" tests to
"run_dump_test" tests. Run more tests unconditionally. Run new tests.
* gas/arm/arch4t.s, gas/arm/arch6zk.s, gas/arm/arm3.s, gas/arm/arm6.s
* gas/arm/arm7dm.s, gas/arm/bignum1.s, gas/arm/float.s
* gas/arm/immed.s, gas/arm/iwmmxt.s, gas/arm/offset.s, gas/arm/thumb.s:
Adjust to work as a dump test.
* gas/arm/arch4t.d, gas/arm/arch6zk.d, gas/arm/arm3.d, gas/arm/arm6.d
* gas/arm/arm7dm.d, gas/arm/bignum1.d, gas/arm/float.d
* gas/arm/immed.d, gas/arm/iwmmxt.d, gas/arm/offset.d, gas/arm/thumb.d:
New files.
* gas/arm/armv1-bad.l, gas/arm/armv1-bad.s: Remove tests for
diagnostics that don't happen in the first pass anymore.
* gas/arm/iwmmxt-bad.l, gas/arm/r15-bad.l, gas/arm/req.l
* gas/arm/vfp-bad.l:
Update expected diagnostics.
* gas/arm/pic.d: Update expected reloc name.
* gas/arm/thumbv6.d: CPY no longer appears in disassembly.
* gas/arm/r15-bad.s: Avoid two-argument mul.
* gas/arm/req.s: Adjust comments.
* gas/arm/maverick.d, gas/arm/maverick.s: Avoid inappropriate
use of PC.
* gas/arm/macro-1.d, gas/arm/macro1.s
* gas/arm/t16-bad.l, gas/arm/t16-bad.s
* gas/arm/tcompat.d, gas/arm/tcompat.s
* gas/arm/tcompat2.d, gas/arm/tcompat2.s
* gas/arm/thumb32.d, gas/arm/thumb32.s
New test pair.
ld/testsuite:
* ld-arm/mixed-app.d: Adjust expected disassembly a little.
2005-05-18 07:40:12 +02:00
|
|
|
|
break;
|
2015-08-12 13:45:07 +02:00
|
|
|
|
|
2009-11-17 11:43:09 +01:00
|
|
|
|
case 'x':
|
|
|
|
|
|
func (stream, "0x%lx", val & 0xffffffffUL);
|
|
|
|
|
|
break;
|
include/elf:
* arm.h: Import complete list of official relocation names
and numbers from AAELF. Define FAKE_RELOCs for old names.
Remove a few old names no longer used anywhere.
bfd:
* elf32-arm.c: Wherever possible, use official reloc names
from AAELF.
(elf32_arm_howto_table, elf32_arm_tls_gd32_howto)
(elf32_arm_tls_ldo32_howto, elf32_arm_tls_ldm32_howto)
(elf32_arm_tls_le32_howto, elf32_arm_tls_ie32_howto)
(elf32_arm_vtinherit_howto, elf32_arm_vtentry_howto)
(elf32_arm_pc11_howto, elf32_arm_thm_pc9_howto, elf32_arm_got_prel)
(elf32_arm_r_howto): Replace with elf32_arm_howto_table_1,
elf32_arm_howto_table_2, and elf32_arm_howto_table_3.
Add many new relocations from AAELF.
(elf32_arm_howto_from_type): Update to match.
(elf32_arm_reloc_map): Add entries for R_ARM_THM_JUMP24,
R_ARM_THM_JUMP11, R_ARM_THM_JUMP19, R_ARM_THM_JUMP8,
R_ARM_THM_JUMP6, R_ARM_GNU_VTINHERIT, and R_ARM_GNU_VTENTRY.
(elf32_arm_reloc_type_lookup): Use elf32_arm_howto_from_type.
(elf32_arm_final_link_relocate): Add support for
R_ARM_THM_JUMP24, R_ARM_THM_JUMP19, R_ARM_THM_JUMP6. Remove
case entries redundant with default.
* reloc.c: Reorganize ARM relocations. Add Thumb
assembler-internal relocations BFD_RELOC_ARM_T32_OFFSET_U8,
BFD_RELOC_ARM_T32_OFFSET_IMM, BFD_RELOC_ARM_T32_IMMEDIATE.
Add visible relocations BFD_RELOC_THUMB_PCREL_BRANCH7,
BFD_RELOC_THUMB_BRANCH20, BFD_RELOC_THUMB_BRANCH25.
Delete unused relocations BFD_RELOC_ARM_GOT12, BFD_RELOC_ARM_COPY.
* bfd-in2.h, libbfd.h: Regenerate.
opcodes:
* arm-dis.c (thumb_opcodes): Add disassembly for V6T2 16-bit
instructions. Adjust disassembly of some opcodes to match
unified syntax.
(thumb32_opcodes): New table.
(print_insn_thumb): Rename print_insn_thumb16; don't handle
two-halfword branches here.
(print_insn_thumb32): New function.
(print_insn): Choose among print_insn_arm, print_insn_thumb16,
and print_insn_thumb32. Be consistent about order of
halfwords when printing 32-bit instructions.
gas:
* hash.c (hash_lookup): Add len parameter. All callers changed.
(hash_find_n): New interface.
* hash.h: Prototype hash_find_n.
* sb.c: Include as.h.
(scrub_from_sb, sb_to_scrub, scrub_position): New statics.
(sb_scrub_and_add_sb): New interface.
* sb.h: Prototype sb_scrub_and_add_sb.
* input-scrub.c (input_scrub_include_sb): Use sb_scrub_and_add_sb.
* config/tc-arm.h (TC_FORCE_RELOCATION_LOCAL): Remove
reference to BFD_RELOC_ARM_GOT12 which is never generated.
* config/tc-arm.c: Rewrite, adding Thumb-2 support.
gas/testsuite:
* gas/arm/arm.exp: Convert all existing "gas_test" tests to
"run_dump_test" tests. Run more tests unconditionally. Run new tests.
* gas/arm/arch4t.s, gas/arm/arch6zk.s, gas/arm/arm3.s, gas/arm/arm6.s
* gas/arm/arm7dm.s, gas/arm/bignum1.s, gas/arm/float.s
* gas/arm/immed.s, gas/arm/iwmmxt.s, gas/arm/offset.s, gas/arm/thumb.s:
Adjust to work as a dump test.
* gas/arm/arch4t.d, gas/arm/arch6zk.d, gas/arm/arm3.d, gas/arm/arm6.d
* gas/arm/arm7dm.d, gas/arm/bignum1.d, gas/arm/float.d
* gas/arm/immed.d, gas/arm/iwmmxt.d, gas/arm/offset.d, gas/arm/thumb.d:
New files.
* gas/arm/armv1-bad.l, gas/arm/armv1-bad.s: Remove tests for
diagnostics that don't happen in the first pass anymore.
* gas/arm/iwmmxt-bad.l, gas/arm/r15-bad.l, gas/arm/req.l
* gas/arm/vfp-bad.l:
Update expected diagnostics.
* gas/arm/pic.d: Update expected reloc name.
* gas/arm/thumbv6.d: CPY no longer appears in disassembly.
* gas/arm/r15-bad.s: Avoid two-argument mul.
* gas/arm/req.s: Adjust comments.
* gas/arm/maverick.d, gas/arm/maverick.s: Avoid inappropriate
use of PC.
* gas/arm/macro-1.d, gas/arm/macro1.s
* gas/arm/t16-bad.l, gas/arm/t16-bad.s
* gas/arm/tcompat.d, gas/arm/tcompat.s
* gas/arm/tcompat2.d, gas/arm/tcompat2.s
* gas/arm/thumb32.d, gas/arm/thumb32.s
New test pair.
ld/testsuite:
* ld-arm/mixed-app.d: Adjust expected disassembly a little.
2005-05-18 07:40:12 +02:00
|
|
|
|
|
|
|
|
|
|
default:
|
|
|
|
|
|
abort ();
|
|
|
|
|
|
}
|
|
|
|
|
|
}
|
|
|
|
|
|
break;
|
|
|
|
|
|
|
2011-04-12 18:01:48 +02:00
|
|
|
|
case 'L':
|
|
|
|
|
|
/* PR binutils/12534
|
|
|
|
|
|
If we have a PC relative offset in an LDRD or STRD
|
|
|
|
|
|
instructions then display the decoded address. */
|
|
|
|
|
|
if (((given >> 16) & 0xf) == 0xf)
|
|
|
|
|
|
{
|
|
|
|
|
|
bfd_vma offset = (given & 0xff) * 4;
|
|
|
|
|
|
|
|
|
|
|
|
if ((given & (1 << 23)) == 0)
|
|
|
|
|
|
offset = - offset;
|
|
|
|
|
|
func (stream, "\t; ");
|
|
|
|
|
|
info->print_address_func ((pc & ~3) + 4 + offset, info);
|
|
|
|
|
|
}
|
|
|
|
|
|
break;
|
|
|
|
|
|
|
include/elf:
* arm.h: Import complete list of official relocation names
and numbers from AAELF. Define FAKE_RELOCs for old names.
Remove a few old names no longer used anywhere.
bfd:
* elf32-arm.c: Wherever possible, use official reloc names
from AAELF.
(elf32_arm_howto_table, elf32_arm_tls_gd32_howto)
(elf32_arm_tls_ldo32_howto, elf32_arm_tls_ldm32_howto)
(elf32_arm_tls_le32_howto, elf32_arm_tls_ie32_howto)
(elf32_arm_vtinherit_howto, elf32_arm_vtentry_howto)
(elf32_arm_pc11_howto, elf32_arm_thm_pc9_howto, elf32_arm_got_prel)
(elf32_arm_r_howto): Replace with elf32_arm_howto_table_1,
elf32_arm_howto_table_2, and elf32_arm_howto_table_3.
Add many new relocations from AAELF.
(elf32_arm_howto_from_type): Update to match.
(elf32_arm_reloc_map): Add entries for R_ARM_THM_JUMP24,
R_ARM_THM_JUMP11, R_ARM_THM_JUMP19, R_ARM_THM_JUMP8,
R_ARM_THM_JUMP6, R_ARM_GNU_VTINHERIT, and R_ARM_GNU_VTENTRY.
(elf32_arm_reloc_type_lookup): Use elf32_arm_howto_from_type.
(elf32_arm_final_link_relocate): Add support for
R_ARM_THM_JUMP24, R_ARM_THM_JUMP19, R_ARM_THM_JUMP6. Remove
case entries redundant with default.
* reloc.c: Reorganize ARM relocations. Add Thumb
assembler-internal relocations BFD_RELOC_ARM_T32_OFFSET_U8,
BFD_RELOC_ARM_T32_OFFSET_IMM, BFD_RELOC_ARM_T32_IMMEDIATE.
Add visible relocations BFD_RELOC_THUMB_PCREL_BRANCH7,
BFD_RELOC_THUMB_BRANCH20, BFD_RELOC_THUMB_BRANCH25.
Delete unused relocations BFD_RELOC_ARM_GOT12, BFD_RELOC_ARM_COPY.
* bfd-in2.h, libbfd.h: Regenerate.
opcodes:
* arm-dis.c (thumb_opcodes): Add disassembly for V6T2 16-bit
instructions. Adjust disassembly of some opcodes to match
unified syntax.
(thumb32_opcodes): New table.
(print_insn_thumb): Rename print_insn_thumb16; don't handle
two-halfword branches here.
(print_insn_thumb32): New function.
(print_insn): Choose among print_insn_arm, print_insn_thumb16,
and print_insn_thumb32. Be consistent about order of
halfwords when printing 32-bit instructions.
gas:
* hash.c (hash_lookup): Add len parameter. All callers changed.
(hash_find_n): New interface.
* hash.h: Prototype hash_find_n.
* sb.c: Include as.h.
(scrub_from_sb, sb_to_scrub, scrub_position): New statics.
(sb_scrub_and_add_sb): New interface.
* sb.h: Prototype sb_scrub_and_add_sb.
* input-scrub.c (input_scrub_include_sb): Use sb_scrub_and_add_sb.
* config/tc-arm.h (TC_FORCE_RELOCATION_LOCAL): Remove
reference to BFD_RELOC_ARM_GOT12 which is never generated.
* config/tc-arm.c: Rewrite, adding Thumb-2 support.
gas/testsuite:
* gas/arm/arm.exp: Convert all existing "gas_test" tests to
"run_dump_test" tests. Run more tests unconditionally. Run new tests.
* gas/arm/arch4t.s, gas/arm/arch6zk.s, gas/arm/arm3.s, gas/arm/arm6.s
* gas/arm/arm7dm.s, gas/arm/bignum1.s, gas/arm/float.s
* gas/arm/immed.s, gas/arm/iwmmxt.s, gas/arm/offset.s, gas/arm/thumb.s:
Adjust to work as a dump test.
* gas/arm/arch4t.d, gas/arm/arch6zk.d, gas/arm/arm3.d, gas/arm/arm6.d
* gas/arm/arm7dm.d, gas/arm/bignum1.d, gas/arm/float.d
* gas/arm/immed.d, gas/arm/iwmmxt.d, gas/arm/offset.d, gas/arm/thumb.d:
New files.
* gas/arm/armv1-bad.l, gas/arm/armv1-bad.s: Remove tests for
diagnostics that don't happen in the first pass anymore.
* gas/arm/iwmmxt-bad.l, gas/arm/r15-bad.l, gas/arm/req.l
* gas/arm/vfp-bad.l:
Update expected diagnostics.
* gas/arm/pic.d: Update expected reloc name.
* gas/arm/thumbv6.d: CPY no longer appears in disassembly.
* gas/arm/r15-bad.s: Avoid two-argument mul.
* gas/arm/req.s: Adjust comments.
* gas/arm/maverick.d, gas/arm/maverick.s: Avoid inappropriate
use of PC.
* gas/arm/macro-1.d, gas/arm/macro1.s
* gas/arm/t16-bad.l, gas/arm/t16-bad.s
* gas/arm/tcompat.d, gas/arm/tcompat.s
* gas/arm/tcompat2.d, gas/arm/tcompat2.s
* gas/arm/thumb32.d, gas/arm/thumb32.s
New test pair.
ld/testsuite:
* ld-arm/mixed-app.d: Adjust expected disassembly a little.
2005-05-18 07:40:12 +02:00
|
|
|
|
default:
|
|
|
|
|
|
abort ();
|
|
|
|
|
|
}
|
|
|
|
|
|
}
|
2009-06-29 10:08:15 +02:00
|
|
|
|
|
|
|
|
|
|
if (value_in_comment > 32 || value_in_comment < -16)
|
|
|
|
|
|
func (stream, "\t; 0x%lx", value_in_comment);
|
2009-12-17 10:52:18 +01:00
|
|
|
|
|
|
|
|
|
|
if (is_unpredictable)
|
|
|
|
|
|
func (stream, UNPREDICTABLE_INSTRUCTION);
|
|
|
|
|
|
|
2005-06-08 00:16:52 +02:00
|
|
|
|
return;
|
include/elf:
* arm.h: Import complete list of official relocation names
and numbers from AAELF. Define FAKE_RELOCs for old names.
Remove a few old names no longer used anywhere.
bfd:
* elf32-arm.c: Wherever possible, use official reloc names
from AAELF.
(elf32_arm_howto_table, elf32_arm_tls_gd32_howto)
(elf32_arm_tls_ldo32_howto, elf32_arm_tls_ldm32_howto)
(elf32_arm_tls_le32_howto, elf32_arm_tls_ie32_howto)
(elf32_arm_vtinherit_howto, elf32_arm_vtentry_howto)
(elf32_arm_pc11_howto, elf32_arm_thm_pc9_howto, elf32_arm_got_prel)
(elf32_arm_r_howto): Replace with elf32_arm_howto_table_1,
elf32_arm_howto_table_2, and elf32_arm_howto_table_3.
Add many new relocations from AAELF.
(elf32_arm_howto_from_type): Update to match.
(elf32_arm_reloc_map): Add entries for R_ARM_THM_JUMP24,
R_ARM_THM_JUMP11, R_ARM_THM_JUMP19, R_ARM_THM_JUMP8,
R_ARM_THM_JUMP6, R_ARM_GNU_VTINHERIT, and R_ARM_GNU_VTENTRY.
(elf32_arm_reloc_type_lookup): Use elf32_arm_howto_from_type.
(elf32_arm_final_link_relocate): Add support for
R_ARM_THM_JUMP24, R_ARM_THM_JUMP19, R_ARM_THM_JUMP6. Remove
case entries redundant with default.
* reloc.c: Reorganize ARM relocations. Add Thumb
assembler-internal relocations BFD_RELOC_ARM_T32_OFFSET_U8,
BFD_RELOC_ARM_T32_OFFSET_IMM, BFD_RELOC_ARM_T32_IMMEDIATE.
Add visible relocations BFD_RELOC_THUMB_PCREL_BRANCH7,
BFD_RELOC_THUMB_BRANCH20, BFD_RELOC_THUMB_BRANCH25.
Delete unused relocations BFD_RELOC_ARM_GOT12, BFD_RELOC_ARM_COPY.
* bfd-in2.h, libbfd.h: Regenerate.
opcodes:
* arm-dis.c (thumb_opcodes): Add disassembly for V6T2 16-bit
instructions. Adjust disassembly of some opcodes to match
unified syntax.
(thumb32_opcodes): New table.
(print_insn_thumb): Rename print_insn_thumb16; don't handle
two-halfword branches here.
(print_insn_thumb32): New function.
(print_insn): Choose among print_insn_arm, print_insn_thumb16,
and print_insn_thumb32. Be consistent about order of
halfwords when printing 32-bit instructions.
gas:
* hash.c (hash_lookup): Add len parameter. All callers changed.
(hash_find_n): New interface.
* hash.h: Prototype hash_find_n.
* sb.c: Include as.h.
(scrub_from_sb, sb_to_scrub, scrub_position): New statics.
(sb_scrub_and_add_sb): New interface.
* sb.h: Prototype sb_scrub_and_add_sb.
* input-scrub.c (input_scrub_include_sb): Use sb_scrub_and_add_sb.
* config/tc-arm.h (TC_FORCE_RELOCATION_LOCAL): Remove
reference to BFD_RELOC_ARM_GOT12 which is never generated.
* config/tc-arm.c: Rewrite, adding Thumb-2 support.
gas/testsuite:
* gas/arm/arm.exp: Convert all existing "gas_test" tests to
"run_dump_test" tests. Run more tests unconditionally. Run new tests.
* gas/arm/arch4t.s, gas/arm/arch6zk.s, gas/arm/arm3.s, gas/arm/arm6.s
* gas/arm/arm7dm.s, gas/arm/bignum1.s, gas/arm/float.s
* gas/arm/immed.s, gas/arm/iwmmxt.s, gas/arm/offset.s, gas/arm/thumb.s:
Adjust to work as a dump test.
* gas/arm/arch4t.d, gas/arm/arch6zk.d, gas/arm/arm3.d, gas/arm/arm6.d
* gas/arm/arm7dm.d, gas/arm/bignum1.d, gas/arm/float.d
* gas/arm/immed.d, gas/arm/iwmmxt.d, gas/arm/offset.d, gas/arm/thumb.d:
New files.
* gas/arm/armv1-bad.l, gas/arm/armv1-bad.s: Remove tests for
diagnostics that don't happen in the first pass anymore.
* gas/arm/iwmmxt-bad.l, gas/arm/r15-bad.l, gas/arm/req.l
* gas/arm/vfp-bad.l:
Update expected diagnostics.
* gas/arm/pic.d: Update expected reloc name.
* gas/arm/thumbv6.d: CPY no longer appears in disassembly.
* gas/arm/r15-bad.s: Avoid two-argument mul.
* gas/arm/req.s: Adjust comments.
* gas/arm/maverick.d, gas/arm/maverick.s: Avoid inappropriate
use of PC.
* gas/arm/macro-1.d, gas/arm/macro1.s
* gas/arm/t16-bad.l, gas/arm/t16-bad.s
* gas/arm/tcompat.d, gas/arm/tcompat.s
* gas/arm/tcompat2.d, gas/arm/tcompat2.s
* gas/arm/thumb32.d, gas/arm/thumb32.s
New test pair.
ld/testsuite:
* ld-arm/mixed-app.d: Adjust expected disassembly a little.
2005-05-18 07:40:12 +02:00
|
|
|
|
}
|
1999-05-03 09:29:11 +02:00
|
|
|
|
|
2000-01-27 23:17:12 +01:00
|
|
|
|
/* No match. */
|
1999-05-03 09:29:11 +02:00
|
|
|
|
abort ();
|
|
|
|
|
|
}
|
|
|
|
|
|
|
2006-11-22 18:45:57 +01:00
|
|
|
|
/* Print data bytes on INFO->STREAM. */
|
|
|
|
|
|
|
|
|
|
|
|
static void
|
2009-06-30 13:57:05 +02:00
|
|
|
|
print_insn_data (bfd_vma pc ATTRIBUTE_UNUSED,
|
|
|
|
|
|
struct disassemble_info *info,
|
2006-11-22 18:45:57 +01:00
|
|
|
|
long given)
|
|
|
|
|
|
{
|
|
|
|
|
|
switch (info->bytes_per_chunk)
|
|
|
|
|
|
{
|
|
|
|
|
|
case 1:
|
|
|
|
|
|
info->fprintf_func (info->stream, ".byte\t0x%02lx", given);
|
|
|
|
|
|
break;
|
|
|
|
|
|
case 2:
|
|
|
|
|
|
info->fprintf_func (info->stream, ".short\t0x%04lx", given);
|
|
|
|
|
|
break;
|
|
|
|
|
|
case 4:
|
|
|
|
|
|
info->fprintf_func (info->stream, ".word\t0x%08lx", given);
|
|
|
|
|
|
break;
|
|
|
|
|
|
default:
|
|
|
|
|
|
abort ();
|
|
|
|
|
|
}
|
|
|
|
|
|
}
|
|
|
|
|
|
|
2003-11-14 16:12:44 +01:00
|
|
|
|
/* Disallow mapping symbols ($a, $b, $d, $t etc) from
|
2015-03-03 16:00:59 +01:00
|
|
|
|
being displayed in symbol relative addresses.
|
|
|
|
|
|
|
|
|
|
|
|
Also disallow private symbol, with __tagsym$$ prefix,
|
|
|
|
|
|
from ARM RVCT toolchain being displayed. */
|
2003-11-14 16:12:44 +01:00
|
|
|
|
|
|
|
|
|
|
bfd_boolean
|
|
|
|
|
|
arm_symbol_is_valid (asymbol * sym,
|
|
|
|
|
|
struct disassemble_info * info ATTRIBUTE_UNUSED)
|
|
|
|
|
|
{
|
|
|
|
|
|
const char * name;
|
2015-08-12 13:45:07 +02:00
|
|
|
|
|
2003-11-14 16:12:44 +01:00
|
|
|
|
if (sym == NULL)
|
|
|
|
|
|
return FALSE;
|
|
|
|
|
|
|
|
|
|
|
|
name = bfd_asymbol_name (sym);
|
|
|
|
|
|
|
2015-03-03 16:00:59 +01:00
|
|
|
|
return (name && *name != '$' && strncmp (name, "__tagsym$$", 10));
|
2003-11-14 16:12:44 +01:00
|
|
|
|
}
|
|
|
|
|
|
|
2017-02-28 19:32:07 +01:00
|
|
|
|
/* Parse the string of disassembler options. */
|
2002-05-23 14:48:23 +02:00
|
|
|
|
|
2017-02-28 19:32:07 +01:00
|
|
|
|
static void
|
2017-04-05 20:21:33 +02:00
|
|
|
|
parse_arm_disassembler_options (const char *options)
|
1999-06-16 04:24:36 +02:00
|
|
|
|
{
|
2017-04-05 20:21:33 +02:00
|
|
|
|
const char *opt;
|
2002-11-30 09:39:46 +01:00
|
|
|
|
|
2017-02-28 19:32:07 +01:00
|
|
|
|
FOR_EACH_DISASSEMBLER_OPTION (opt, options)
|
1999-06-16 04:24:36 +02:00
|
|
|
|
{
|
2017-02-28 19:32:07 +01:00
|
|
|
|
if (CONST_STRNEQ (opt, "reg-names-"))
|
|
|
|
|
|
{
|
|
|
|
|
|
unsigned int i;
|
|
|
|
|
|
for (i = 0; i < NUM_ARM_OPTIONS; i++)
|
|
|
|
|
|
if (disassembler_options_cmp (opt, regnames[i].name) == 0)
|
|
|
|
|
|
{
|
|
|
|
|
|
regname_selected = i;
|
|
|
|
|
|
break;
|
|
|
|
|
|
}
|
2002-11-30 09:39:46 +01:00
|
|
|
|
|
2017-02-28 19:32:07 +01:00
|
|
|
|
if (i >= NUM_ARM_OPTIONS)
|
opcodes error messages
Another patch aimed at making binutils comply with the GNU coding
standard. The generated files require
https://sourceware.org/ml/cgen/2018-q1/msg00004.html
cpu/
* frv.opc: Include opintl.h.
(add_next_to_vliw): Use opcodes_error_handler to print error.
Standardize error message.
(fr500_check_insn_major_constraints, frv_vliw_add_insn): Likewise.
opcodes/
* sysdep.h (opcodes_error_handler): Define.
(_bfd_error_handler): Declare.
* Makefile.am: Remove stray #.
* opc2c.c (main): Remove bogus -l arg handling. Print "DO NOT
EDIT" comment.
* aarch64-dis.c, * arc-dis.c, * arm-dis.c, * avr-dis.c,
* d30v-dis.c, * h8300-dis.c, * mmix-dis.c, * ppc-dis.c,
* riscv-dis.c, * s390-dis.c, * sparc-dis.c, * v850-dis.c: Use
opcodes_error_handler to print errors. Standardize error messages.
* msp430-decode.opc, * nios2-dis.c, * rl78-decode.opc: Likewise,
and include opintl.h.
* nds32-asm.c: Likewise, and include sysdep.h and opintl.h.
* i386-gen.c: Standardize error messages.
* msp430-decode.c, * rl78-decode.c, rx-decode.c: Regenerate.
* Makefile.in: Regenerate.
* epiphany-asm.c, * epiphany-desc.c, * epiphany-dis.c,
* epiphany-ibld.c, * fr30-asm.c, * fr30-desc.c, * fr30-dis.c,
* fr30-ibld.c, * frv-asm.c, * frv-desc.c, * frv-dis.c, * frv-ibld.c,
* frv-opc.c, * ip2k-asm.c, * ip2k-desc.c, * ip2k-dis.c, * ip2k-ibld.c,
* iq2000-asm.c, * iq2000-desc.c, * iq2000-dis.c, * iq2000-ibld.c,
* lm32-asm.c, * lm32-desc.c, * lm32-dis.c, * lm32-ibld.c,
* m32c-asm.c, * m32c-desc.c, * m32c-dis.c, * m32c-ibld.c,
* m32r-asm.c, * m32r-desc.c, * m32r-dis.c, * m32r-ibld.c,
* mep-asm.c, * mep-desc.c, * mep-dis.c, * mep-ibld.c, * mt-asm.c,
* mt-desc.c, * mt-dis.c, * mt-ibld.c, * or1k-asm.c, * or1k-desc.c,
* or1k-dis.c, * or1k-ibld.c, * xc16x-asm.c, * xc16x-desc.c,
* xc16x-dis.c, * xc16x-ibld.c, * xstormy16-asm.c, * xstormy16-desc.c,
* xstormy16-dis.c, * xstormy16-ibld.c: Regenerate.
2018-03-01 22:53:50 +01:00
|
|
|
|
/* xgettext: c-format */
|
|
|
|
|
|
opcodes_error_handler (_("unrecognised register name set: %s"),
|
|
|
|
|
|
opt);
|
2017-02-28 19:32:07 +01:00
|
|
|
|
}
|
|
|
|
|
|
else if (CONST_STRNEQ (opt, "force-thumb"))
|
|
|
|
|
|
force_thumb = 1;
|
|
|
|
|
|
else if (CONST_STRNEQ (opt, "no-force-thumb"))
|
|
|
|
|
|
force_thumb = 0;
|
|
|
|
|
|
else
|
opcodes error messages
Another patch aimed at making binutils comply with the GNU coding
standard. The generated files require
https://sourceware.org/ml/cgen/2018-q1/msg00004.html
cpu/
* frv.opc: Include opintl.h.
(add_next_to_vliw): Use opcodes_error_handler to print error.
Standardize error message.
(fr500_check_insn_major_constraints, frv_vliw_add_insn): Likewise.
opcodes/
* sysdep.h (opcodes_error_handler): Define.
(_bfd_error_handler): Declare.
* Makefile.am: Remove stray #.
* opc2c.c (main): Remove bogus -l arg handling. Print "DO NOT
EDIT" comment.
* aarch64-dis.c, * arc-dis.c, * arm-dis.c, * avr-dis.c,
* d30v-dis.c, * h8300-dis.c, * mmix-dis.c, * ppc-dis.c,
* riscv-dis.c, * s390-dis.c, * sparc-dis.c, * v850-dis.c: Use
opcodes_error_handler to print errors. Standardize error messages.
* msp430-decode.opc, * nios2-dis.c, * rl78-decode.opc: Likewise,
and include opintl.h.
* nds32-asm.c: Likewise, and include sysdep.h and opintl.h.
* i386-gen.c: Standardize error messages.
* msp430-decode.c, * rl78-decode.c, rx-decode.c: Regenerate.
* Makefile.in: Regenerate.
* epiphany-asm.c, * epiphany-desc.c, * epiphany-dis.c,
* epiphany-ibld.c, * fr30-asm.c, * fr30-desc.c, * fr30-dis.c,
* fr30-ibld.c, * frv-asm.c, * frv-desc.c, * frv-dis.c, * frv-ibld.c,
* frv-opc.c, * ip2k-asm.c, * ip2k-desc.c, * ip2k-dis.c, * ip2k-ibld.c,
* iq2000-asm.c, * iq2000-desc.c, * iq2000-dis.c, * iq2000-ibld.c,
* lm32-asm.c, * lm32-desc.c, * lm32-dis.c, * lm32-ibld.c,
* m32c-asm.c, * m32c-desc.c, * m32c-dis.c, * m32c-ibld.c,
* m32r-asm.c, * m32r-desc.c, * m32r-dis.c, * m32r-ibld.c,
* mep-asm.c, * mep-desc.c, * mep-dis.c, * mep-ibld.c, * mt-asm.c,
* mt-desc.c, * mt-dis.c, * mt-ibld.c, * or1k-asm.c, * or1k-desc.c,
* or1k-dis.c, * or1k-ibld.c, * xc16x-asm.c, * xc16x-desc.c,
* xc16x-dis.c, * xc16x-ibld.c, * xstormy16-asm.c, * xstormy16-desc.c,
* xstormy16-dis.c, * xstormy16-ibld.c: Regenerate.
2018-03-01 22:53:50 +01:00
|
|
|
|
/* xgettext: c-format */
|
|
|
|
|
|
opcodes_error_handler (_("unrecognised disassembler option: %s"), opt);
|
1999-06-16 04:24:36 +02:00
|
|
|
|
}
|
2002-11-30 09:39:46 +01:00
|
|
|
|
|
1999-06-16 04:24:36 +02:00
|
|
|
|
return;
|
|
|
|
|
|
}
|
|
|
|
|
|
|
2016-01-25 16:06:54 +01:00
|
|
|
|
static bfd_boolean
|
|
|
|
|
|
mapping_symbol_for_insn (bfd_vma pc, struct disassemble_info *info,
|
|
|
|
|
|
enum map_type *map_symbol);
|
|
|
|
|
|
|
2006-06-07 16:08:19 +02:00
|
|
|
|
/* Search back through the insn stream to determine if this instruction is
|
|
|
|
|
|
conditionally executed. */
|
2009-06-30 13:57:05 +02:00
|
|
|
|
|
2006-06-07 16:08:19 +02:00
|
|
|
|
static void
|
2009-06-30 13:57:05 +02:00
|
|
|
|
find_ifthen_state (bfd_vma pc,
|
|
|
|
|
|
struct disassemble_info *info,
|
2006-06-07 16:08:19 +02:00
|
|
|
|
bfd_boolean little)
|
|
|
|
|
|
{
|
|
|
|
|
|
unsigned char b[2];
|
|
|
|
|
|
unsigned int insn;
|
|
|
|
|
|
int status;
|
|
|
|
|
|
/* COUNT is twice the number of instructions seen. It will be odd if we
|
|
|
|
|
|
just crossed an instruction boundary. */
|
|
|
|
|
|
int count;
|
|
|
|
|
|
int it_count;
|
|
|
|
|
|
unsigned int seen_it;
|
|
|
|
|
|
bfd_vma addr;
|
|
|
|
|
|
|
|
|
|
|
|
ifthen_address = pc;
|
|
|
|
|
|
ifthen_state = 0;
|
|
|
|
|
|
|
|
|
|
|
|
addr = pc;
|
|
|
|
|
|
count = 1;
|
|
|
|
|
|
it_count = 0;
|
|
|
|
|
|
seen_it = 0;
|
|
|
|
|
|
/* Scan backwards looking for IT instructions, keeping track of where
|
|
|
|
|
|
instruction boundaries are. We don't know if something is actually an
|
|
|
|
|
|
IT instruction until we find a definite instruction boundary. */
|
|
|
|
|
|
for (;;)
|
|
|
|
|
|
{
|
2009-06-30 13:57:05 +02:00
|
|
|
|
if (addr == 0 || info->symbol_at_address_func (addr, info))
|
2006-06-07 16:08:19 +02:00
|
|
|
|
{
|
|
|
|
|
|
/* A symbol must be on an instruction boundary, and will not
|
|
|
|
|
|
be within an IT block. */
|
|
|
|
|
|
if (seen_it && (count & 1))
|
|
|
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
|
|
return;
|
|
|
|
|
|
}
|
|
|
|
|
|
addr -= 2;
|
2009-06-30 13:57:05 +02:00
|
|
|
|
status = info->read_memory_func (addr, (bfd_byte *) b, 2, info);
|
2006-06-07 16:08:19 +02:00
|
|
|
|
if (status)
|
|
|
|
|
|
return;
|
|
|
|
|
|
|
|
|
|
|
|
if (little)
|
|
|
|
|
|
insn = (b[0]) | (b[1] << 8);
|
|
|
|
|
|
else
|
|
|
|
|
|
insn = (b[1]) | (b[0] << 8);
|
|
|
|
|
|
if (seen_it)
|
|
|
|
|
|
{
|
|
|
|
|
|
if ((insn & 0xf800) < 0xe800)
|
|
|
|
|
|
{
|
|
|
|
|
|
/* Addr + 2 is an instruction boundary. See if this matches
|
|
|
|
|
|
the expected boundary based on the position of the last
|
|
|
|
|
|
IT candidate. */
|
|
|
|
|
|
if (count & 1)
|
|
|
|
|
|
break;
|
|
|
|
|
|
seen_it = 0;
|
|
|
|
|
|
}
|
|
|
|
|
|
}
|
|
|
|
|
|
if ((insn & 0xff00) == 0xbf00 && (insn & 0xf) != 0)
|
|
|
|
|
|
{
|
2016-01-25 16:06:54 +01:00
|
|
|
|
enum map_type type = MAP_ARM;
|
|
|
|
|
|
bfd_boolean found = mapping_symbol_for_insn (addr, info, &type);
|
|
|
|
|
|
|
|
|
|
|
|
if (!found || (found && type == MAP_THUMB))
|
|
|
|
|
|
{
|
|
|
|
|
|
/* This could be an IT instruction. */
|
|
|
|
|
|
seen_it = insn;
|
|
|
|
|
|
it_count = count >> 1;
|
|
|
|
|
|
}
|
2006-06-07 16:08:19 +02:00
|
|
|
|
}
|
|
|
|
|
|
if ((insn & 0xf800) >= 0xe800)
|
|
|
|
|
|
count++;
|
|
|
|
|
|
else
|
|
|
|
|
|
count = (count + 2) | 1;
|
|
|
|
|
|
/* IT blocks contain at most 4 instructions. */
|
|
|
|
|
|
if (count >= 8 && !seen_it)
|
|
|
|
|
|
return;
|
|
|
|
|
|
}
|
|
|
|
|
|
/* We found an IT instruction. */
|
|
|
|
|
|
ifthen_state = (seen_it & 0xe0) | ((seen_it << it_count) & 0x1f);
|
|
|
|
|
|
if ((ifthen_state & 0xf) == 0)
|
|
|
|
|
|
ifthen_state = 0;
|
|
|
|
|
|
}
|
|
|
|
|
|
|
2010-01-29 17:47:55 +01:00
|
|
|
|
/* Returns nonzero and sets *MAP_TYPE if the N'th symbol is a
|
|
|
|
|
|
mapping symbol. */
|
|
|
|
|
|
|
|
|
|
|
|
static int
|
|
|
|
|
|
is_mapping_symbol (struct disassemble_info *info, int n,
|
|
|
|
|
|
enum map_type *map_type)
|
|
|
|
|
|
{
|
|
|
|
|
|
const char *name;
|
|
|
|
|
|
|
|
|
|
|
|
name = bfd_asymbol_name (info->symtab[n]);
|
|
|
|
|
|
if (name[0] == '$' && (name[1] == 'a' || name[1] == 't' || name[1] == 'd')
|
|
|
|
|
|
&& (name[2] == 0 || name[2] == '.'))
|
|
|
|
|
|
{
|
|
|
|
|
|
*map_type = ((name[1] == 'a') ? MAP_ARM
|
|
|
|
|
|
: (name[1] == 't') ? MAP_THUMB
|
|
|
|
|
|
: MAP_DATA);
|
|
|
|
|
|
return TRUE;
|
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
return FALSE;
|
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
/* Try to infer the code type (ARM or Thumb) from a mapping symbol.
|
|
|
|
|
|
Returns nonzero if *MAP_TYPE was set. */
|
|
|
|
|
|
|
|
|
|
|
|
static int
|
|
|
|
|
|
get_map_sym_type (struct disassemble_info *info,
|
|
|
|
|
|
int n,
|
|
|
|
|
|
enum map_type *map_type)
|
|
|
|
|
|
{
|
|
|
|
|
|
/* If the symbol is in a different section, ignore it. */
|
|
|
|
|
|
if (info->section != NULL && info->section != info->symtab[n]->section)
|
|
|
|
|
|
return FALSE;
|
|
|
|
|
|
|
|
|
|
|
|
return is_mapping_symbol (info, n, map_type);
|
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
/* Try to infer the code type (ARM or Thumb) from a non-mapping symbol.
|
2006-11-22 18:45:57 +01:00
|
|
|
|
Returns nonzero if *MAP_TYPE was set. */
|
2006-10-31 21:21:57 +01:00
|
|
|
|
|
|
|
|
|
|
static int
|
2009-06-30 13:57:05 +02:00
|
|
|
|
get_sym_code_type (struct disassemble_info *info,
|
|
|
|
|
|
int n,
|
2006-11-22 18:45:57 +01:00
|
|
|
|
enum map_type *map_type)
|
2006-10-31 21:21:57 +01:00
|
|
|
|
{
|
|
|
|
|
|
elf_symbol_type *es;
|
|
|
|
|
|
unsigned int type;
|
2010-01-29 17:47:55 +01:00
|
|
|
|
|
|
|
|
|
|
/* If the symbol is in a different section, ignore it. */
|
|
|
|
|
|
if (info->section != NULL && info->section != info->symtab[n]->section)
|
|
|
|
|
|
return FALSE;
|
2006-10-31 21:21:57 +01:00
|
|
|
|
|
2006-11-22 18:45:57 +01:00
|
|
|
|
es = *(elf_symbol_type **)(info->symtab + n);
|
2006-10-31 21:21:57 +01:00
|
|
|
|
type = ELF_ST_TYPE (es->internal_elf_sym.st_info);
|
|
|
|
|
|
|
|
|
|
|
|
/* If the symbol has function type then use that. */
|
include/elf/
* arm.h (R_ARM_IRELATIVE): New relocation.
bfd/
* reloc.c (BFD_RELOC_ARM_IRELATIVE): New relocation.
* bfd-in2.h: Regenerate.
* elf32-arm.c (elf32_arm_howto_table_2): Rename existing definition
to elf32_arm_howto_table_3 and replace with a single R_ARM_IRELATIVE
entry.
(elf32_arm_howto_from_type): Update accordingly.
(elf32_arm_reloc_map): Map BFD_RELOC_ARM_IRELATIVE to R_ARM_IRELATIVE.
(elf32_arm_reloc_name_lookup): Handle elf32_arm_howto_table_3.
(arm_plt_info): New structure, split out from elf32_arm_link_hash_entry
with an extra noncall_refcount field.
(arm_local_iplt_info): New structure.
(elf_arm_obj_tdata): Add local_iplt.
(elf32_arm_local_iplt): New accessor macro.
(elf32_arm_link_hash_entry): Replace plt_thumb_refcount,
plt_maybe_thumb_refcount and plt_got_offset with an arm_plt_info.
Change tls_type to a bitfield and add is_iplt.
(elf32_arm_link_hash_newfunc): Update accordingly.
(elf32_arm_allocate_local_sym_info): New function.
(elf32_arm_create_local_iplt): Likewise.
(elf32_arm_get_plt_info): Likewise.
(elf32_arm_plt_needs_thumb_stub_p): Likewise.
(elf32_arm_get_local_dynreloc_list): Likewise.
(create_ifunc_sections): Likewise.
(elf32_arm_copy_indirect_symbol): Update after the changes to
elf32_arm_link_hash_entry. Assert the is_iplt has not yet been set.
(arm_type_of_stub): Add an st_type argument. Use elf32_arm_get_plt_info
to get PLT information. Assert that all STT_GNU_IFUNC references
are turned into PLT references.
(arm_build_one_stub): Pass the symbol type to
elf32_arm_final_link_relocate.
(elf32_arm_size_stubs): Pass the symbol type to arm_type_of_stub.
(elf32_arm_allocate_irelocs): New function.
(elf32_arm_add_dynreloc): In static objects, use .rel.iplt for
all R_ARM_IRELATIVE.
(elf32_arm_allocate_plt_entry): New function.
(elf32_arm_populate_plt_entry): Likewise.
(elf32_arm_final_link_relocate): Add an st_type parameter.
Set srelgot to null for static objects. Use separate variables
to record which st_value and st_type should be used when generating
a dynamic relocation. Use elf32_arm_get_plt_info to find the
symbol's PLT information, setting has_iplt_entry, splt,
plt_offset and gotplt_offset accordingly. Check whether
STT_GNU_IFUNC symbols should resolve to an .iplt entry, and change
the relocation target accordingly. Broaden assert to include
.iplts. Don't set sreloc for static relocations. Assert that
we only generate dynamic R_ARM_RELATIVE relocations for R_ARM_ABS32
and R_ARM_ABS32_NOI. Generate R_ARM_IRELATIVE relocations instead
of R_ARM_RELATIVE relocations if the target is an STT_GNU_IFUNC
symbol. Pass the symbol type to arm_type_of_stub. Conditionally
resolve GOT references to the .igot.plt entry.
(elf32_arm_relocate_section): Update the call to
elf32_arm_final_link_relocate.
(elf32_arm_gc_sweep_hook): Use elf32_arm_get_plt_info to get PLT
information. Treat R_ARM_REL32 and R_ARM_REL32_NOI as call
relocations in shared libraries and relocatable executables.
Count non-call PLT references. Use elf32_arm_get_local_dynreloc_list
to get the list of dynamic relocations for a local symbol.
(elf32_arm_check_relocs): Always create ifunc sections. Set isym
at the same time as setting h. Use elf32_arm_allocate_local_sym_info
to allocate local symbol information. Treat R_ARM_REL32 and
R_ARM_REL32_NOI as call relocations in shared libraries and
relocatable executables. Record PLT information for local
STT_GNU_IFUNC functions as well as global functions. Count
non-call PLT references. Use elf32_arm_get_local_dynreloc_list
to get the list of dynamic relocations for a local symbol.
(elf32_arm_adjust_dynamic_symbol): Handle STT_GNU_IFUNC symbols.
Don't remove STT_GNU_IFUNC PLTs unless all references have been
removed. Update after the changes to elf32_arm_link_hash_entry.
(allocate_dynrelocs_for_symbol): Decide whether STT_GNU_IFUNC PLT
entries should live in .plt or .iplt. Check whether the .igot.plt
and .got entries can be combined. Use elf32_arm_allocate_plt_entry
to allocate .plt and .(i)got.plt entries. Detect which .got
entries will need R_ARM_IRELATIVE relocations and use
elf32_arm_allocate_irelocs to allocate them. Likewise other
non-.got dynamic relocations.
(elf32_arm_size_dynamic_sections): Allocate .iplt, .igot.plt
and dynamic relocations for local STT_GNU_IFUNC symbols.
Check whether the .igot.plt and .got entries can be combined.
Detect which .got entries will need R_ARM_IRELATIVE relocations
and use elf32_arm_allocate_irelocs to allocate them. Use stashed
section pointers intead of strcmp checks. Handle iplt and igotplt.
(elf32_arm_finish_dynamic_symbol): Use elf32_arm_populate_plt_entry
to fill in .plt, .got.plt and .rel(a).plt entries. Point
STT_GNU_IFUNC symbols at an .iplt entry if non-call relocations
resolve to it.
(elf32_arm_output_plt_map_1): New function, split out from
elf32_arm_output_plt_map. Handle .iplt entries. Use
elf32_arm_plt_needs_thumb_stub_p.
(elf32_arm_output_plt_map): Call it.
(elf32_arm_output_arch_local_syms): Add mapping symbols for
local .iplt entries.
(elf32_arm_swap_symbol_in): Handle Thumb STT_GNU_IFUNC symbols.
(elf32_arm_swap_symbol_out): Likewise.
(elf32_arm_add_symbol_hook): New function.
(elf_backend_add_symbol_hook): Define for all targets.
opcodes/
* arm-dis.c (get_sym_code_type): Treat STT_GNU_IFUNCs as code.
gas/
* config/tc-arm.c (md_pcrel_from_section): Use S_FORCE_RELOC to
determine whether a relocation is needed.
(md_apply_fix, arm_apply_sym_value): Likewise.
ld/testsuite/
* ld-arm/ifunc-1.s, ld-arm/ifunc-1.dd, ld-arm/ifunc-1.gd,
ld-arm/ifunc-1.rd, ld-arm/ifunc-2.s, ld-arm/ifunc-2.dd,
ld-arm/ifunc-2.gd, ld-arm/ifunc-2.rd, ld-arm/ifunc-3.s,
ld-arm/ifunc-3.dd, ld-arm/ifunc-3.gd, ld-arm/ifunc-3.rd,
ld-arm/ifunc-4.s, ld-arm/ifunc-4.dd, ld-arm/ifunc-4.gd,
ld-arm/ifunc-4.rd, ld-arm/ifunc-5.s, ld-arm/ifunc-5.dd,
ld-arm/ifunc-5.gd, ld-arm/ifunc-5.rd, ld-arm/ifunc-6.s,
ld-arm/ifunc-6.dd, ld-arm/ifunc-6.gd, ld-arm/ifunc-6.rd,
ld-arm/ifunc-7.s, ld-arm/ifunc-7.dd, ld-arm/ifunc-7.gd,
ld-arm/ifunc-7.rd, ld-arm/ifunc-8.s, ld-arm/ifunc-8.dd,
ld-arm/ifunc-8.gd, ld-arm/ifunc-8.rd, ld-arm/ifunc-9.s,
ld-arm/ifunc-9.dd, ld-arm/ifunc-9.gd, ld-arm/ifunc-9.rd,
ld-arm/ifunc-10.s, ld-arm/ifunc-10.dd, ld-arm/ifunc-10.gd,
ld-arm/ifunc-10.rd, ld-arm/ifunc-11.s, ld-arm/ifunc-11.dd,
ld-arm/ifunc-11.gd, ld-arm/ifunc-11.rd, ld-arm/ifunc-12.s,
ld-arm/ifunc-12.dd, ld-arm/ifunc-12.gd, ld-arm/ifunc-12.rd,
ld-arm/ifunc-13.s, ld-arm/ifunc-13.dd, ld-arm/ifunc-13.gd,
ld-arm/ifunc-13.rd, ld-arm/ifunc-14.s, ld-arm/ifunc-14.dd,
ld-arm/ifunc-14.gd, ld-arm/ifunc-14.rd, ld-arm/ifunc-15.s,
ld-arm/ifunc-15.dd, ld-arm/ifunc-15.gd, ld-arm/ifunc-15.rd,
ld-arm/ifunc-16.s, ld-arm/ifunc-16.dd, ld-arm/ifunc-16.gd,
ld-arm/ifunc-16.rd, ld-arm/ifunc-dynamic.ld,
ld-arm/ifunc-static.ld: New tests.
* ld-arm/farcall-group.d, ld-arm/farcall-group-size2.d,
ld-arm/farcall-mixed-lib-v4t.d, ld-arm/farcall-mixed-lib.d: Update
for new stub hashes.
* ld-arm/arm-elf.exp: Run them.
2011-03-14 17:04:16 +01:00
|
|
|
|
if (type == STT_FUNC || type == STT_GNU_IFUNC)
|
2006-10-31 21:21:57 +01:00
|
|
|
|
{
|
2016-05-10 17:14:23 +02:00
|
|
|
|
if (ARM_GET_SYM_BRANCH_TYPE (es->internal_elf_sym.st_target_internal)
|
|
|
|
|
|
== ST_BRANCH_TO_THUMB)
|
2011-03-14 16:55:04 +01:00
|
|
|
|
*map_type = MAP_THUMB;
|
|
|
|
|
|
else
|
|
|
|
|
|
*map_type = MAP_ARM;
|
2006-10-31 21:21:57 +01:00
|
|
|
|
return TRUE;
|
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
return FALSE;
|
|
|
|
|
|
}
|
|
|
|
|
|
|
2016-01-25 16:06:54 +01:00
|
|
|
|
/* Search the mapping symbol state for instruction at pc. This is only
|
|
|
|
|
|
applicable for elf target.
|
|
|
|
|
|
|
|
|
|
|
|
There is an assumption Here, info->private_data contains the correct AND
|
|
|
|
|
|
up-to-date information about current scan process. The information will be
|
|
|
|
|
|
used to speed this search process.
|
|
|
|
|
|
|
|
|
|
|
|
Return TRUE if the mapping state can be determined, and map_symbol
|
|
|
|
|
|
will be updated accordingly. Otherwise, return FALSE. */
|
|
|
|
|
|
|
|
|
|
|
|
static bfd_boolean
|
|
|
|
|
|
mapping_symbol_for_insn (bfd_vma pc, struct disassemble_info *info,
|
|
|
|
|
|
enum map_type *map_symbol)
|
|
|
|
|
|
{
|
|
|
|
|
|
bfd_vma addr;
|
|
|
|
|
|
int n, start = 0;
|
|
|
|
|
|
bfd_boolean found = FALSE;
|
|
|
|
|
|
enum map_type type = MAP_ARM;
|
|
|
|
|
|
struct arm_private_data *private_data;
|
|
|
|
|
|
|
|
|
|
|
|
if (info->private_data == NULL || info->symtab_size == 0
|
|
|
|
|
|
|| bfd_asymbol_flavour (*info->symtab) != bfd_target_elf_flavour)
|
|
|
|
|
|
return FALSE;
|
|
|
|
|
|
|
|
|
|
|
|
private_data = info->private_data;
|
|
|
|
|
|
if (pc == 0)
|
|
|
|
|
|
start = 0;
|
|
|
|
|
|
else
|
|
|
|
|
|
start = private_data->last_mapping_sym;
|
|
|
|
|
|
|
|
|
|
|
|
start = (start == -1)? 0 : start;
|
|
|
|
|
|
addr = bfd_asymbol_value (info->symtab[start]);
|
|
|
|
|
|
|
|
|
|
|
|
if (pc >= addr)
|
|
|
|
|
|
{
|
|
|
|
|
|
if (get_map_sym_type (info, start, &type))
|
|
|
|
|
|
found = TRUE;
|
|
|
|
|
|
}
|
|
|
|
|
|
else
|
|
|
|
|
|
{
|
|
|
|
|
|
for (n = start - 1; n >= 0; n--)
|
|
|
|
|
|
{
|
|
|
|
|
|
if (get_map_sym_type (info, n, &type))
|
|
|
|
|
|
{
|
|
|
|
|
|
found = TRUE;
|
|
|
|
|
|
break;
|
|
|
|
|
|
}
|
|
|
|
|
|
}
|
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
/* No mapping symbols were found. A leading $d may be
|
|
|
|
|
|
omitted for sections which start with data; but for
|
|
|
|
|
|
compatibility with legacy and stripped binaries, only
|
|
|
|
|
|
assume the leading $d if there is at least one mapping
|
|
|
|
|
|
symbol in the file. */
|
|
|
|
|
|
if (!found && private_data->has_mapping_symbols == 1)
|
|
|
|
|
|
{
|
|
|
|
|
|
type = MAP_DATA;
|
|
|
|
|
|
found = TRUE;
|
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
*map_symbol = type;
|
|
|
|
|
|
return found;
|
|
|
|
|
|
}
|
|
|
|
|
|
|
2009-06-18 12:31:21 +02:00
|
|
|
|
/* Given a bfd_mach_arm_XXX value, this function fills in the fields
|
|
|
|
|
|
of the supplied arm_feature_set structure with bitmasks indicating
|
[ARM] Update bfd's Tag_CPU_arch knowledge
BFD's bfd_get_mach () function returns a bfd specific value representing
the architecture of the target which is populated from the Tag_CPU_arch
build attribute value of that target. Among other users of that
interfacem, objdump which uses it to print the architecture version of
the binary being examinated and to decide what instruction is available
if run with "-m arm" via its own mapping from bfd_mach_arm_X values to
feature bits available.
However, both BFD and objdump's most recent known architecture is
Armv5TE. When encountering a newer architecture bfd_get_mach will return
bfd_mach_arm_unknown. This is unfortunate since objdump uses that value
to allow all instructions on all architectures which is already what it
does by default, making the "-m arm" trick useless.
This patch updates BFD and objdump's knowledge of Arm architecture
versions up to the latest Armv8-M Baseline and Mainline, Armv8-R and
Armv8.4-A architectures. Since several architecture versions (eg. 8.X-A)
share the same Tag_CPU_arch build attribute value and
bfd_mach_arm values, the mapping from bfd machine value to feature bits
need to return the most featureful feature bits that would yield the
given bfd machine value otherwise some instruction would not disassemble
under "-m arm" mode. The patch rework that mapping to make this clearer
and simplify writing the mapping rules. In particular, for simplicity
all FPU instructions are allowed in all cases.
Finally, the patch also rewrite the cpu_arch_ver table in GAS to use the
TAG_CPU_ARCH_X macros rather than hardcode their value.
2018-07-02 Thomas Preud'homme <thomas.preudhomme@arm.com>
bfd/
* archures.c (bfd_mach_arm_5TEJ, bfd_mach_arm_6, bfd_mach_arm_6KZ,
bfd_mach_arm_6T2, bfd_mach_arm_6K, bfd_mach_arm_7, bfd_mach_arm_6M,
bfd_mach_arm_6SM, bfd_mach_arm_7EM, bfd_mach_arm_8, bfd_mach_arm_8R,
bfd_mach_arm_8M_BASE, bfd_mach_arm_8M_MAIN): Define.
* bfd-in2.h: Regenerate.
* cpu-arm.c (arch_info_struct): Add entries for above new
bfd_mach_arm values.
* elf32-arm.c (bfd_arm_get_mach_from_attributes): Add Tag_CPU_arch to
bfd_mach_arm mapping logic for pre Armv4 and Armv5TEJ and later
architectures. Force assert failure for any new Tag_CPU_arch value.
gas/
* config/tc-arm.c (cpu_arch_ver): Use symbolic TAG_CPU_ARCH macros
rather than hardcode their values.
ld/
* arm-dis.c (select_arm_features): Fix typo in heading comment. Allow
all FPU features and add mapping from new bfd_mach_arm values to
allowed CPU feature bits.
opcodes/
* testsuite/ld-arm/tls-descrelax-be8.d: Add architecture version in
expected result.
* testsuite/ld-arm/tls-descrelax-v7.d: Likewise.
* testsuite/ld-arm/tls-longplt-lib.d: Likewise.
* testsuite/ld-arm/tls-longplt.d: Likewise.
2018-07-02 12:22:20 +02:00
|
|
|
|
the supported base architectures and coprocessor extensions.
|
2009-06-18 12:31:21 +02:00
|
|
|
|
|
|
|
|
|
|
FIXME: This could more efficiently implemented as a constant array,
|
|
|
|
|
|
although it would also be less robust. */
|
|
|
|
|
|
|
|
|
|
|
|
static void
|
|
|
|
|
|
select_arm_features (unsigned long mach,
|
|
|
|
|
|
arm_feature_set * features)
|
|
|
|
|
|
{
|
[ARM] Update bfd's Tag_CPU_arch knowledge
BFD's bfd_get_mach () function returns a bfd specific value representing
the architecture of the target which is populated from the Tag_CPU_arch
build attribute value of that target. Among other users of that
interfacem, objdump which uses it to print the architecture version of
the binary being examinated and to decide what instruction is available
if run with "-m arm" via its own mapping from bfd_mach_arm_X values to
feature bits available.
However, both BFD and objdump's most recent known architecture is
Armv5TE. When encountering a newer architecture bfd_get_mach will return
bfd_mach_arm_unknown. This is unfortunate since objdump uses that value
to allow all instructions on all architectures which is already what it
does by default, making the "-m arm" trick useless.
This patch updates BFD and objdump's knowledge of Arm architecture
versions up to the latest Armv8-M Baseline and Mainline, Armv8-R and
Armv8.4-A architectures. Since several architecture versions (eg. 8.X-A)
share the same Tag_CPU_arch build attribute value and
bfd_mach_arm values, the mapping from bfd machine value to feature bits
need to return the most featureful feature bits that would yield the
given bfd machine value otherwise some instruction would not disassemble
under "-m arm" mode. The patch rework that mapping to make this clearer
and simplify writing the mapping rules. In particular, for simplicity
all FPU instructions are allowed in all cases.
Finally, the patch also rewrite the cpu_arch_ver table in GAS to use the
TAG_CPU_ARCH_X macros rather than hardcode their value.
2018-07-02 Thomas Preud'homme <thomas.preudhomme@arm.com>
bfd/
* archures.c (bfd_mach_arm_5TEJ, bfd_mach_arm_6, bfd_mach_arm_6KZ,
bfd_mach_arm_6T2, bfd_mach_arm_6K, bfd_mach_arm_7, bfd_mach_arm_6M,
bfd_mach_arm_6SM, bfd_mach_arm_7EM, bfd_mach_arm_8, bfd_mach_arm_8R,
bfd_mach_arm_8M_BASE, bfd_mach_arm_8M_MAIN): Define.
* bfd-in2.h: Regenerate.
* cpu-arm.c (arch_info_struct): Add entries for above new
bfd_mach_arm values.
* elf32-arm.c (bfd_arm_get_mach_from_attributes): Add Tag_CPU_arch to
bfd_mach_arm mapping logic for pre Armv4 and Armv5TEJ and later
architectures. Force assert failure for any new Tag_CPU_arch value.
gas/
* config/tc-arm.c (cpu_arch_ver): Use symbolic TAG_CPU_ARCH macros
rather than hardcode their values.
ld/
* arm-dis.c (select_arm_features): Fix typo in heading comment. Allow
all FPU features and add mapping from new bfd_mach_arm values to
allowed CPU feature bits.
opcodes/
* testsuite/ld-arm/tls-descrelax-be8.d: Add architecture version in
expected result.
* testsuite/ld-arm/tls-descrelax-v7.d: Likewise.
* testsuite/ld-arm/tls-longplt-lib.d: Likewise.
* testsuite/ld-arm/tls-longplt.d: Likewise.
2018-07-02 12:22:20 +02:00
|
|
|
|
arm_feature_set arch_fset;
|
|
|
|
|
|
const arm_feature_set fpu_any = FPU_ANY;
|
|
|
|
|
|
|
2015-06-02 13:24:24 +02:00
|
|
|
|
#undef ARM_SET_FEATURES
|
|
|
|
|
|
#define ARM_SET_FEATURES(FSET) \
|
|
|
|
|
|
{ \
|
|
|
|
|
|
const arm_feature_set fset = FSET; \
|
[ARM] Update bfd's Tag_CPU_arch knowledge
BFD's bfd_get_mach () function returns a bfd specific value representing
the architecture of the target which is populated from the Tag_CPU_arch
build attribute value of that target. Among other users of that
interfacem, objdump which uses it to print the architecture version of
the binary being examinated and to decide what instruction is available
if run with "-m arm" via its own mapping from bfd_mach_arm_X values to
feature bits available.
However, both BFD and objdump's most recent known architecture is
Armv5TE. When encountering a newer architecture bfd_get_mach will return
bfd_mach_arm_unknown. This is unfortunate since objdump uses that value
to allow all instructions on all architectures which is already what it
does by default, making the "-m arm" trick useless.
This patch updates BFD and objdump's knowledge of Arm architecture
versions up to the latest Armv8-M Baseline and Mainline, Armv8-R and
Armv8.4-A architectures. Since several architecture versions (eg. 8.X-A)
share the same Tag_CPU_arch build attribute value and
bfd_mach_arm values, the mapping from bfd machine value to feature bits
need to return the most featureful feature bits that would yield the
given bfd machine value otherwise some instruction would not disassemble
under "-m arm" mode. The patch rework that mapping to make this clearer
and simplify writing the mapping rules. In particular, for simplicity
all FPU instructions are allowed in all cases.
Finally, the patch also rewrite the cpu_arch_ver table in GAS to use the
TAG_CPU_ARCH_X macros rather than hardcode their value.
2018-07-02 Thomas Preud'homme <thomas.preudhomme@arm.com>
bfd/
* archures.c (bfd_mach_arm_5TEJ, bfd_mach_arm_6, bfd_mach_arm_6KZ,
bfd_mach_arm_6T2, bfd_mach_arm_6K, bfd_mach_arm_7, bfd_mach_arm_6M,
bfd_mach_arm_6SM, bfd_mach_arm_7EM, bfd_mach_arm_8, bfd_mach_arm_8R,
bfd_mach_arm_8M_BASE, bfd_mach_arm_8M_MAIN): Define.
* bfd-in2.h: Regenerate.
* cpu-arm.c (arch_info_struct): Add entries for above new
bfd_mach_arm values.
* elf32-arm.c (bfd_arm_get_mach_from_attributes): Add Tag_CPU_arch to
bfd_mach_arm mapping logic for pre Armv4 and Armv5TEJ and later
architectures. Force assert failure for any new Tag_CPU_arch value.
gas/
* config/tc-arm.c (cpu_arch_ver): Use symbolic TAG_CPU_ARCH macros
rather than hardcode their values.
ld/
* arm-dis.c (select_arm_features): Fix typo in heading comment. Allow
all FPU features and add mapping from new bfd_mach_arm values to
allowed CPU feature bits.
opcodes/
* testsuite/ld-arm/tls-descrelax-be8.d: Add architecture version in
expected result.
* testsuite/ld-arm/tls-descrelax-v7.d: Likewise.
* testsuite/ld-arm/tls-longplt-lib.d: Likewise.
* testsuite/ld-arm/tls-longplt.d: Likewise.
2018-07-02 12:22:20 +02:00
|
|
|
|
arch_fset = fset; \
|
2015-06-02 13:24:24 +02:00
|
|
|
|
}
|
2015-03-24 07:08:08 +01:00
|
|
|
|
|
[ARM] Update bfd's Tag_CPU_arch knowledge
BFD's bfd_get_mach () function returns a bfd specific value representing
the architecture of the target which is populated from the Tag_CPU_arch
build attribute value of that target. Among other users of that
interfacem, objdump which uses it to print the architecture version of
the binary being examinated and to decide what instruction is available
if run with "-m arm" via its own mapping from bfd_mach_arm_X values to
feature bits available.
However, both BFD and objdump's most recent known architecture is
Armv5TE. When encountering a newer architecture bfd_get_mach will return
bfd_mach_arm_unknown. This is unfortunate since objdump uses that value
to allow all instructions on all architectures which is already what it
does by default, making the "-m arm" trick useless.
This patch updates BFD and objdump's knowledge of Arm architecture
versions up to the latest Armv8-M Baseline and Mainline, Armv8-R and
Armv8.4-A architectures. Since several architecture versions (eg. 8.X-A)
share the same Tag_CPU_arch build attribute value and
bfd_mach_arm values, the mapping from bfd machine value to feature bits
need to return the most featureful feature bits that would yield the
given bfd machine value otherwise some instruction would not disassemble
under "-m arm" mode. The patch rework that mapping to make this clearer
and simplify writing the mapping rules. In particular, for simplicity
all FPU instructions are allowed in all cases.
Finally, the patch also rewrite the cpu_arch_ver table in GAS to use the
TAG_CPU_ARCH_X macros rather than hardcode their value.
2018-07-02 Thomas Preud'homme <thomas.preudhomme@arm.com>
bfd/
* archures.c (bfd_mach_arm_5TEJ, bfd_mach_arm_6, bfd_mach_arm_6KZ,
bfd_mach_arm_6T2, bfd_mach_arm_6K, bfd_mach_arm_7, bfd_mach_arm_6M,
bfd_mach_arm_6SM, bfd_mach_arm_7EM, bfd_mach_arm_8, bfd_mach_arm_8R,
bfd_mach_arm_8M_BASE, bfd_mach_arm_8M_MAIN): Define.
* bfd-in2.h: Regenerate.
* cpu-arm.c (arch_info_struct): Add entries for above new
bfd_mach_arm values.
* elf32-arm.c (bfd_arm_get_mach_from_attributes): Add Tag_CPU_arch to
bfd_mach_arm mapping logic for pre Armv4 and Armv5TEJ and later
architectures. Force assert failure for any new Tag_CPU_arch value.
gas/
* config/tc-arm.c (cpu_arch_ver): Use symbolic TAG_CPU_ARCH macros
rather than hardcode their values.
ld/
* arm-dis.c (select_arm_features): Fix typo in heading comment. Allow
all FPU features and add mapping from new bfd_mach_arm values to
allowed CPU feature bits.
opcodes/
* testsuite/ld-arm/tls-descrelax-be8.d: Add architecture version in
expected result.
* testsuite/ld-arm/tls-descrelax-v7.d: Likewise.
* testsuite/ld-arm/tls-longplt-lib.d: Likewise.
* testsuite/ld-arm/tls-longplt.d: Likewise.
2018-07-02 12:22:20 +02:00
|
|
|
|
/* When several architecture versions share the same bfd_mach_arm_XXX value
|
|
|
|
|
|
the most featureful is chosen. */
|
2009-06-18 12:31:21 +02:00
|
|
|
|
switch (mach)
|
|
|
|
|
|
{
|
[ARM] Update bfd's Tag_CPU_arch knowledge
BFD's bfd_get_mach () function returns a bfd specific value representing
the architecture of the target which is populated from the Tag_CPU_arch
build attribute value of that target. Among other users of that
interfacem, objdump which uses it to print the architecture version of
the binary being examinated and to decide what instruction is available
if run with "-m arm" via its own mapping from bfd_mach_arm_X values to
feature bits available.
However, both BFD and objdump's most recent known architecture is
Armv5TE. When encountering a newer architecture bfd_get_mach will return
bfd_mach_arm_unknown. This is unfortunate since objdump uses that value
to allow all instructions on all architectures which is already what it
does by default, making the "-m arm" trick useless.
This patch updates BFD and objdump's knowledge of Arm architecture
versions up to the latest Armv8-M Baseline and Mainline, Armv8-R and
Armv8.4-A architectures. Since several architecture versions (eg. 8.X-A)
share the same Tag_CPU_arch build attribute value and
bfd_mach_arm values, the mapping from bfd machine value to feature bits
need to return the most featureful feature bits that would yield the
given bfd machine value otherwise some instruction would not disassemble
under "-m arm" mode. The patch rework that mapping to make this clearer
and simplify writing the mapping rules. In particular, for simplicity
all FPU instructions are allowed in all cases.
Finally, the patch also rewrite the cpu_arch_ver table in GAS to use the
TAG_CPU_ARCH_X macros rather than hardcode their value.
2018-07-02 Thomas Preud'homme <thomas.preudhomme@arm.com>
bfd/
* archures.c (bfd_mach_arm_5TEJ, bfd_mach_arm_6, bfd_mach_arm_6KZ,
bfd_mach_arm_6T2, bfd_mach_arm_6K, bfd_mach_arm_7, bfd_mach_arm_6M,
bfd_mach_arm_6SM, bfd_mach_arm_7EM, bfd_mach_arm_8, bfd_mach_arm_8R,
bfd_mach_arm_8M_BASE, bfd_mach_arm_8M_MAIN): Define.
* bfd-in2.h: Regenerate.
* cpu-arm.c (arch_info_struct): Add entries for above new
bfd_mach_arm values.
* elf32-arm.c (bfd_arm_get_mach_from_attributes): Add Tag_CPU_arch to
bfd_mach_arm mapping logic for pre Armv4 and Armv5TEJ and later
architectures. Force assert failure for any new Tag_CPU_arch value.
gas/
* config/tc-arm.c (cpu_arch_ver): Use symbolic TAG_CPU_ARCH macros
rather than hardcode their values.
ld/
* arm-dis.c (select_arm_features): Fix typo in heading comment. Allow
all FPU features and add mapping from new bfd_mach_arm values to
allowed CPU feature bits.
opcodes/
* testsuite/ld-arm/tls-descrelax-be8.d: Add architecture version in
expected result.
* testsuite/ld-arm/tls-descrelax-v7.d: Likewise.
* testsuite/ld-arm/tls-longplt-lib.d: Likewise.
* testsuite/ld-arm/tls-longplt.d: Likewise.
2018-07-02 12:22:20 +02:00
|
|
|
|
case bfd_mach_arm_2: ARM_SET_FEATURES (ARM_ARCH_V2); break;
|
|
|
|
|
|
case bfd_mach_arm_2a: ARM_SET_FEATURES (ARM_ARCH_V2S); break;
|
|
|
|
|
|
case bfd_mach_arm_3: ARM_SET_FEATURES (ARM_ARCH_V3); break;
|
|
|
|
|
|
case bfd_mach_arm_3M: ARM_SET_FEATURES (ARM_ARCH_V3M); break;
|
|
|
|
|
|
case bfd_mach_arm_4: ARM_SET_FEATURES (ARM_ARCH_V4); break;
|
|
|
|
|
|
case bfd_mach_arm_4T: ARM_SET_FEATURES (ARM_ARCH_V4T); break;
|
|
|
|
|
|
case bfd_mach_arm_5: ARM_SET_FEATURES (ARM_ARCH_V5); break;
|
|
|
|
|
|
case bfd_mach_arm_5T: ARM_SET_FEATURES (ARM_ARCH_V5T); break;
|
|
|
|
|
|
case bfd_mach_arm_5TE: ARM_SET_FEATURES (ARM_ARCH_V5TE); break;
|
|
|
|
|
|
case bfd_mach_arm_XScale: ARM_SET_FEATURES (ARM_ARCH_XSCALE); break;
|
2015-06-02 13:24:24 +02:00
|
|
|
|
case bfd_mach_arm_ep9312:
|
[ARM] Update bfd's Tag_CPU_arch knowledge
BFD's bfd_get_mach () function returns a bfd specific value representing
the architecture of the target which is populated from the Tag_CPU_arch
build attribute value of that target. Among other users of that
interfacem, objdump which uses it to print the architecture version of
the binary being examinated and to decide what instruction is available
if run with "-m arm" via its own mapping from bfd_mach_arm_X values to
feature bits available.
However, both BFD and objdump's most recent known architecture is
Armv5TE. When encountering a newer architecture bfd_get_mach will return
bfd_mach_arm_unknown. This is unfortunate since objdump uses that value
to allow all instructions on all architectures which is already what it
does by default, making the "-m arm" trick useless.
This patch updates BFD and objdump's knowledge of Arm architecture
versions up to the latest Armv8-M Baseline and Mainline, Armv8-R and
Armv8.4-A architectures. Since several architecture versions (eg. 8.X-A)
share the same Tag_CPU_arch build attribute value and
bfd_mach_arm values, the mapping from bfd machine value to feature bits
need to return the most featureful feature bits that would yield the
given bfd machine value otherwise some instruction would not disassemble
under "-m arm" mode. The patch rework that mapping to make this clearer
and simplify writing the mapping rules. In particular, for simplicity
all FPU instructions are allowed in all cases.
Finally, the patch also rewrite the cpu_arch_ver table in GAS to use the
TAG_CPU_ARCH_X macros rather than hardcode their value.
2018-07-02 Thomas Preud'homme <thomas.preudhomme@arm.com>
bfd/
* archures.c (bfd_mach_arm_5TEJ, bfd_mach_arm_6, bfd_mach_arm_6KZ,
bfd_mach_arm_6T2, bfd_mach_arm_6K, bfd_mach_arm_7, bfd_mach_arm_6M,
bfd_mach_arm_6SM, bfd_mach_arm_7EM, bfd_mach_arm_8, bfd_mach_arm_8R,
bfd_mach_arm_8M_BASE, bfd_mach_arm_8M_MAIN): Define.
* bfd-in2.h: Regenerate.
* cpu-arm.c (arch_info_struct): Add entries for above new
bfd_mach_arm values.
* elf32-arm.c (bfd_arm_get_mach_from_attributes): Add Tag_CPU_arch to
bfd_mach_arm mapping logic for pre Armv4 and Armv5TEJ and later
architectures. Force assert failure for any new Tag_CPU_arch value.
gas/
* config/tc-arm.c (cpu_arch_ver): Use symbolic TAG_CPU_ARCH macros
rather than hardcode their values.
ld/
* arm-dis.c (select_arm_features): Fix typo in heading comment. Allow
all FPU features and add mapping from new bfd_mach_arm values to
allowed CPU feature bits.
opcodes/
* testsuite/ld-arm/tls-descrelax-be8.d: Add architecture version in
expected result.
* testsuite/ld-arm/tls-descrelax-v7.d: Likewise.
* testsuite/ld-arm/tls-longplt-lib.d: Likewise.
* testsuite/ld-arm/tls-longplt.d: Likewise.
2018-07-02 12:22:20 +02:00
|
|
|
|
ARM_SET_FEATURES (ARM_FEATURE_LOW (ARM_AEXT_V4T,
|
|
|
|
|
|
ARM_CEXT_MAVERICK | FPU_MAVERICK));
|
2015-06-02 13:24:24 +02:00
|
|
|
|
break;
|
[ARM] Update bfd's Tag_CPU_arch knowledge
BFD's bfd_get_mach () function returns a bfd specific value representing
the architecture of the target which is populated from the Tag_CPU_arch
build attribute value of that target. Among other users of that
interfacem, objdump which uses it to print the architecture version of
the binary being examinated and to decide what instruction is available
if run with "-m arm" via its own mapping from bfd_mach_arm_X values to
feature bits available.
However, both BFD and objdump's most recent known architecture is
Armv5TE. When encountering a newer architecture bfd_get_mach will return
bfd_mach_arm_unknown. This is unfortunate since objdump uses that value
to allow all instructions on all architectures which is already what it
does by default, making the "-m arm" trick useless.
This patch updates BFD and objdump's knowledge of Arm architecture
versions up to the latest Armv8-M Baseline and Mainline, Armv8-R and
Armv8.4-A architectures. Since several architecture versions (eg. 8.X-A)
share the same Tag_CPU_arch build attribute value and
bfd_mach_arm values, the mapping from bfd machine value to feature bits
need to return the most featureful feature bits that would yield the
given bfd machine value otherwise some instruction would not disassemble
under "-m arm" mode. The patch rework that mapping to make this clearer
and simplify writing the mapping rules. In particular, for simplicity
all FPU instructions are allowed in all cases.
Finally, the patch also rewrite the cpu_arch_ver table in GAS to use the
TAG_CPU_ARCH_X macros rather than hardcode their value.
2018-07-02 Thomas Preud'homme <thomas.preudhomme@arm.com>
bfd/
* archures.c (bfd_mach_arm_5TEJ, bfd_mach_arm_6, bfd_mach_arm_6KZ,
bfd_mach_arm_6T2, bfd_mach_arm_6K, bfd_mach_arm_7, bfd_mach_arm_6M,
bfd_mach_arm_6SM, bfd_mach_arm_7EM, bfd_mach_arm_8, bfd_mach_arm_8R,
bfd_mach_arm_8M_BASE, bfd_mach_arm_8M_MAIN): Define.
* bfd-in2.h: Regenerate.
* cpu-arm.c (arch_info_struct): Add entries for above new
bfd_mach_arm values.
* elf32-arm.c (bfd_arm_get_mach_from_attributes): Add Tag_CPU_arch to
bfd_mach_arm mapping logic for pre Armv4 and Armv5TEJ and later
architectures. Force assert failure for any new Tag_CPU_arch value.
gas/
* config/tc-arm.c (cpu_arch_ver): Use symbolic TAG_CPU_ARCH macros
rather than hardcode their values.
ld/
* arm-dis.c (select_arm_features): Fix typo in heading comment. Allow
all FPU features and add mapping from new bfd_mach_arm values to
allowed CPU feature bits.
opcodes/
* testsuite/ld-arm/tls-descrelax-be8.d: Add architecture version in
expected result.
* testsuite/ld-arm/tls-descrelax-v7.d: Likewise.
* testsuite/ld-arm/tls-longplt-lib.d: Likewise.
* testsuite/ld-arm/tls-longplt.d: Likewise.
2018-07-02 12:22:20 +02:00
|
|
|
|
case bfd_mach_arm_iWMMXt: ARM_SET_FEATURES (ARM_ARCH_IWMMXT); break;
|
|
|
|
|
|
case bfd_mach_arm_iWMMXt2: ARM_SET_FEATURES (ARM_ARCH_IWMMXT2); break;
|
|
|
|
|
|
case bfd_mach_arm_5TEJ: ARM_SET_FEATURES (ARM_ARCH_V5TEJ); break;
|
|
|
|
|
|
case bfd_mach_arm_6: ARM_SET_FEATURES (ARM_ARCH_V6); break;
|
|
|
|
|
|
case bfd_mach_arm_6KZ: ARM_SET_FEATURES (ARM_ARCH_V6KZ); break;
|
|
|
|
|
|
case bfd_mach_arm_6T2: ARM_SET_FEATURES (ARM_ARCH_V6KZT2); break;
|
|
|
|
|
|
case bfd_mach_arm_6K: ARM_SET_FEATURES (ARM_ARCH_V6K); break;
|
|
|
|
|
|
case bfd_mach_arm_7: ARM_SET_FEATURES (ARM_ARCH_V7VE); break;
|
|
|
|
|
|
case bfd_mach_arm_6M: ARM_SET_FEATURES (ARM_ARCH_V6M); break;
|
|
|
|
|
|
case bfd_mach_arm_6SM: ARM_SET_FEATURES (ARM_ARCH_V6SM); break;
|
|
|
|
|
|
case bfd_mach_arm_7EM: ARM_SET_FEATURES (ARM_ARCH_V7EM); break;
|
|
|
|
|
|
case bfd_mach_arm_8:
|
|
|
|
|
|
{
|
|
|
|
|
|
/* Add bits for extensions that Armv8.4-A recognizes. */
|
|
|
|
|
|
arm_feature_set armv8_4_ext_fset
|
|
|
|
|
|
= ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_FP16_FML);
|
|
|
|
|
|
ARM_SET_FEATURES (ARM_ARCH_V8_4A);
|
|
|
|
|
|
ARM_MERGE_FEATURE_SETS (arch_fset, arch_fset, armv8_4_ext_fset);
|
|
|
|
|
|
break;
|
|
|
|
|
|
}
|
|
|
|
|
|
case bfd_mach_arm_8R: ARM_SET_FEATURES (ARM_ARCH_V8R); break;
|
|
|
|
|
|
case bfd_mach_arm_8M_BASE: ARM_SET_FEATURES (ARM_ARCH_V8M_BASE); break;
|
|
|
|
|
|
case bfd_mach_arm_8M_MAIN: ARM_SET_FEATURES (ARM_ARCH_V8M_MAIN); break;
|
|
|
|
|
|
/* If the machine type is unknown allow all architecture types and all
|
|
|
|
|
|
extensions. */
|
|
|
|
|
|
case bfd_mach_arm_unknown: ARM_SET_FEATURES (ARM_FEATURE_ALL); break;
|
2009-06-18 12:31:21 +02:00
|
|
|
|
default:
|
|
|
|
|
|
abort ();
|
|
|
|
|
|
}
|
2015-06-02 13:24:24 +02:00
|
|
|
|
#undef ARM_SET_FEATURES
|
[ARM] Update bfd's Tag_CPU_arch knowledge
BFD's bfd_get_mach () function returns a bfd specific value representing
the architecture of the target which is populated from the Tag_CPU_arch
build attribute value of that target. Among other users of that
interfacem, objdump which uses it to print the architecture version of
the binary being examinated and to decide what instruction is available
if run with "-m arm" via its own mapping from bfd_mach_arm_X values to
feature bits available.
However, both BFD and objdump's most recent known architecture is
Armv5TE. When encountering a newer architecture bfd_get_mach will return
bfd_mach_arm_unknown. This is unfortunate since objdump uses that value
to allow all instructions on all architectures which is already what it
does by default, making the "-m arm" trick useless.
This patch updates BFD and objdump's knowledge of Arm architecture
versions up to the latest Armv8-M Baseline and Mainline, Armv8-R and
Armv8.4-A architectures. Since several architecture versions (eg. 8.X-A)
share the same Tag_CPU_arch build attribute value and
bfd_mach_arm values, the mapping from bfd machine value to feature bits
need to return the most featureful feature bits that would yield the
given bfd machine value otherwise some instruction would not disassemble
under "-m arm" mode. The patch rework that mapping to make this clearer
and simplify writing the mapping rules. In particular, for simplicity
all FPU instructions are allowed in all cases.
Finally, the patch also rewrite the cpu_arch_ver table in GAS to use the
TAG_CPU_ARCH_X macros rather than hardcode their value.
2018-07-02 Thomas Preud'homme <thomas.preudhomme@arm.com>
bfd/
* archures.c (bfd_mach_arm_5TEJ, bfd_mach_arm_6, bfd_mach_arm_6KZ,
bfd_mach_arm_6T2, bfd_mach_arm_6K, bfd_mach_arm_7, bfd_mach_arm_6M,
bfd_mach_arm_6SM, bfd_mach_arm_7EM, bfd_mach_arm_8, bfd_mach_arm_8R,
bfd_mach_arm_8M_BASE, bfd_mach_arm_8M_MAIN): Define.
* bfd-in2.h: Regenerate.
* cpu-arm.c (arch_info_struct): Add entries for above new
bfd_mach_arm values.
* elf32-arm.c (bfd_arm_get_mach_from_attributes): Add Tag_CPU_arch to
bfd_mach_arm mapping logic for pre Armv4 and Armv5TEJ and later
architectures. Force assert failure for any new Tag_CPU_arch value.
gas/
* config/tc-arm.c (cpu_arch_ver): Use symbolic TAG_CPU_ARCH macros
rather than hardcode their values.
ld/
* arm-dis.c (select_arm_features): Fix typo in heading comment. Allow
all FPU features and add mapping from new bfd_mach_arm values to
allowed CPU feature bits.
opcodes/
* testsuite/ld-arm/tls-descrelax-be8.d: Add architecture version in
expected result.
* testsuite/ld-arm/tls-descrelax-v7.d: Likewise.
* testsuite/ld-arm/tls-longplt-lib.d: Likewise.
* testsuite/ld-arm/tls-longplt.d: Likewise.
2018-07-02 12:22:20 +02:00
|
|
|
|
|
|
|
|
|
|
/* None of the feature bits related to -mfpu have an impact on Tag_CPU_arch
|
|
|
|
|
|
and thus on bfd_mach_arm_XXX value. Therefore for a given
|
|
|
|
|
|
bfd_mach_arm_XXX value all coprocessor feature bits should be allowed. */
|
|
|
|
|
|
ARM_MERGE_FEATURE_SETS (*features, arch_fset, fpu_any);
|
2009-06-18 12:31:21 +02:00
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
|
2000-01-27 23:17:12 +01:00
|
|
|
|
/* NOTE: There are no checks in these routines that
|
|
|
|
|
|
the relevant number of data bytes exist. */
|
2002-05-23 14:48:23 +02:00
|
|
|
|
|
2000-01-27 23:17:12 +01:00
|
|
|
|
static int
|
2005-06-08 00:16:52 +02:00
|
|
|
|
print_insn (bfd_vma pc, struct disassemble_info *info, bfd_boolean little)
|
1999-05-03 09:29:11 +02:00
|
|
|
|
{
|
include/elf:
* arm.h: Import complete list of official relocation names
and numbers from AAELF. Define FAKE_RELOCs for old names.
Remove a few old names no longer used anywhere.
bfd:
* elf32-arm.c: Wherever possible, use official reloc names
from AAELF.
(elf32_arm_howto_table, elf32_arm_tls_gd32_howto)
(elf32_arm_tls_ldo32_howto, elf32_arm_tls_ldm32_howto)
(elf32_arm_tls_le32_howto, elf32_arm_tls_ie32_howto)
(elf32_arm_vtinherit_howto, elf32_arm_vtentry_howto)
(elf32_arm_pc11_howto, elf32_arm_thm_pc9_howto, elf32_arm_got_prel)
(elf32_arm_r_howto): Replace with elf32_arm_howto_table_1,
elf32_arm_howto_table_2, and elf32_arm_howto_table_3.
Add many new relocations from AAELF.
(elf32_arm_howto_from_type): Update to match.
(elf32_arm_reloc_map): Add entries for R_ARM_THM_JUMP24,
R_ARM_THM_JUMP11, R_ARM_THM_JUMP19, R_ARM_THM_JUMP8,
R_ARM_THM_JUMP6, R_ARM_GNU_VTINHERIT, and R_ARM_GNU_VTENTRY.
(elf32_arm_reloc_type_lookup): Use elf32_arm_howto_from_type.
(elf32_arm_final_link_relocate): Add support for
R_ARM_THM_JUMP24, R_ARM_THM_JUMP19, R_ARM_THM_JUMP6. Remove
case entries redundant with default.
* reloc.c: Reorganize ARM relocations. Add Thumb
assembler-internal relocations BFD_RELOC_ARM_T32_OFFSET_U8,
BFD_RELOC_ARM_T32_OFFSET_IMM, BFD_RELOC_ARM_T32_IMMEDIATE.
Add visible relocations BFD_RELOC_THUMB_PCREL_BRANCH7,
BFD_RELOC_THUMB_BRANCH20, BFD_RELOC_THUMB_BRANCH25.
Delete unused relocations BFD_RELOC_ARM_GOT12, BFD_RELOC_ARM_COPY.
* bfd-in2.h, libbfd.h: Regenerate.
opcodes:
* arm-dis.c (thumb_opcodes): Add disassembly for V6T2 16-bit
instructions. Adjust disassembly of some opcodes to match
unified syntax.
(thumb32_opcodes): New table.
(print_insn_thumb): Rename print_insn_thumb16; don't handle
two-halfword branches here.
(print_insn_thumb32): New function.
(print_insn): Choose among print_insn_arm, print_insn_thumb16,
and print_insn_thumb32. Be consistent about order of
halfwords when printing 32-bit instructions.
gas:
* hash.c (hash_lookup): Add len parameter. All callers changed.
(hash_find_n): New interface.
* hash.h: Prototype hash_find_n.
* sb.c: Include as.h.
(scrub_from_sb, sb_to_scrub, scrub_position): New statics.
(sb_scrub_and_add_sb): New interface.
* sb.h: Prototype sb_scrub_and_add_sb.
* input-scrub.c (input_scrub_include_sb): Use sb_scrub_and_add_sb.
* config/tc-arm.h (TC_FORCE_RELOCATION_LOCAL): Remove
reference to BFD_RELOC_ARM_GOT12 which is never generated.
* config/tc-arm.c: Rewrite, adding Thumb-2 support.
gas/testsuite:
* gas/arm/arm.exp: Convert all existing "gas_test" tests to
"run_dump_test" tests. Run more tests unconditionally. Run new tests.
* gas/arm/arch4t.s, gas/arm/arch6zk.s, gas/arm/arm3.s, gas/arm/arm6.s
* gas/arm/arm7dm.s, gas/arm/bignum1.s, gas/arm/float.s
* gas/arm/immed.s, gas/arm/iwmmxt.s, gas/arm/offset.s, gas/arm/thumb.s:
Adjust to work as a dump test.
* gas/arm/arch4t.d, gas/arm/arch6zk.d, gas/arm/arm3.d, gas/arm/arm6.d
* gas/arm/arm7dm.d, gas/arm/bignum1.d, gas/arm/float.d
* gas/arm/immed.d, gas/arm/iwmmxt.d, gas/arm/offset.d, gas/arm/thumb.d:
New files.
* gas/arm/armv1-bad.l, gas/arm/armv1-bad.s: Remove tests for
diagnostics that don't happen in the first pass anymore.
* gas/arm/iwmmxt-bad.l, gas/arm/r15-bad.l, gas/arm/req.l
* gas/arm/vfp-bad.l:
Update expected diagnostics.
* gas/arm/pic.d: Update expected reloc name.
* gas/arm/thumbv6.d: CPY no longer appears in disassembly.
* gas/arm/r15-bad.s: Avoid two-argument mul.
* gas/arm/req.s: Adjust comments.
* gas/arm/maverick.d, gas/arm/maverick.s: Avoid inappropriate
use of PC.
* gas/arm/macro-1.d, gas/arm/macro1.s
* gas/arm/t16-bad.l, gas/arm/t16-bad.s
* gas/arm/tcompat.d, gas/arm/tcompat.s
* gas/arm/tcompat2.d, gas/arm/tcompat2.s
* gas/arm/thumb32.d, gas/arm/thumb32.s
New test pair.
ld/testsuite:
* ld-arm/mixed-app.d: Adjust expected disassembly a little.
2005-05-18 07:40:12 +02:00
|
|
|
|
unsigned char b[4];
|
|
|
|
|
|
long given;
|
|
|
|
|
|
int status;
|
2006-11-22 18:45:57 +01:00
|
|
|
|
int is_thumb = FALSE;
|
2010-01-29 17:47:55 +01:00
|
|
|
|
int is_data = FALSE;
|
2008-07-07 20:35:24 +02:00
|
|
|
|
int little_code;
|
2006-11-22 18:45:57 +01:00
|
|
|
|
unsigned int size = 4;
|
2005-06-08 00:16:52 +02:00
|
|
|
|
void (*printer) (bfd_vma, struct disassemble_info *, long);
|
2006-11-22 18:45:57 +01:00
|
|
|
|
bfd_boolean found = FALSE;
|
2010-01-29 17:47:55 +01:00
|
|
|
|
struct arm_private_data *private_data;
|
2000-01-27 23:17:12 +01:00
|
|
|
|
|
1999-06-16 04:24:36 +02:00
|
|
|
|
if (info->disassembler_options)
|
|
|
|
|
|
{
|
2017-02-28 19:32:07 +01:00
|
|
|
|
parse_arm_disassembler_options (info->disassembler_options);
|
2002-11-30 09:39:46 +01:00
|
|
|
|
|
2000-01-27 23:17:12 +01:00
|
|
|
|
/* To avoid repeated parsing of these options, we remove them here. */
|
1999-06-16 04:24:36 +02:00
|
|
|
|
info->disassembler_options = NULL;
|
|
|
|
|
|
}
|
2002-11-30 09:39:46 +01:00
|
|
|
|
|
2009-06-18 12:31:21 +02:00
|
|
|
|
/* PR 10288: Control which instructions will be disassembled. */
|
|
|
|
|
|
if (info->private_data == NULL)
|
|
|
|
|
|
{
|
2010-01-29 17:47:55 +01:00
|
|
|
|
static struct arm_private_data private;
|
2009-06-18 12:31:21 +02:00
|
|
|
|
|
|
|
|
|
|
if ((info->flags & USER_SPECIFIED_MACHINE_TYPE) == 0)
|
|
|
|
|
|
/* If the user did not use the -m command line switch then default to
|
|
|
|
|
|
disassembling all types of ARM instruction.
|
2015-08-12 13:45:07 +02:00
|
|
|
|
|
2009-06-18 12:31:21 +02:00
|
|
|
|
The info->mach value has to be ignored as this will be based on
|
|
|
|
|
|
the default archictecture for the target and/or hints in the notes
|
|
|
|
|
|
section, but it will never be greater than the current largest arm
|
|
|
|
|
|
machine value (iWMMXt2), which is only equivalent to the V5TE
|
|
|
|
|
|
architecture. ARM architectures have advanced beyond the machine
|
|
|
|
|
|
value encoding, and these newer architectures would be ignored if
|
|
|
|
|
|
the machine value was used.
|
|
|
|
|
|
|
|
|
|
|
|
Ie the -m switch is used to restrict which instructions will be
|
|
|
|
|
|
disassembled. If it is necessary to use the -m switch to tell
|
|
|
|
|
|
objdump that an ARM binary is being disassembled, eg because the
|
|
|
|
|
|
input is a raw binary file, but it is also desired to disassemble
|
|
|
|
|
|
all ARM instructions then use "-marm". This will select the
|
|
|
|
|
|
"unknown" arm architecture which is compatible with any ARM
|
|
|
|
|
|
instruction. */
|
|
|
|
|
|
info->mach = bfd_mach_arm_unknown;
|
|
|
|
|
|
|
|
|
|
|
|
/* Compute the architecture bitmask from the machine number.
|
|
|
|
|
|
Note: This assumes that the machine number will not change
|
|
|
|
|
|
during disassembly.... */
|
2010-01-29 17:47:55 +01:00
|
|
|
|
select_arm_features (info->mach, & private.features);
|
2009-06-18 12:31:21 +02:00
|
|
|
|
|
2010-01-29 17:47:55 +01:00
|
|
|
|
private.has_mapping_symbols = -1;
|
2011-04-08 13:42:19 +02:00
|
|
|
|
private.last_mapping_sym = -1;
|
|
|
|
|
|
private.last_mapping_addr = 0;
|
2010-01-29 17:47:55 +01:00
|
|
|
|
|
|
|
|
|
|
info->private_data = & private;
|
2009-06-18 12:31:21 +02:00
|
|
|
|
}
|
2010-01-29 17:47:55 +01:00
|
|
|
|
|
|
|
|
|
|
private_data = info->private_data;
|
|
|
|
|
|
|
2008-07-07 20:35:24 +02:00
|
|
|
|
/* Decide if our code is going to be little-endian, despite what the
|
|
|
|
|
|
function argument might say. */
|
|
|
|
|
|
little_code = ((info->endian_code == BFD_ENDIAN_LITTLE) || little);
|
|
|
|
|
|
|
2010-01-29 17:47:55 +01:00
|
|
|
|
/* For ELF, consult the symbol table to determine what kind of code
|
|
|
|
|
|
or data we have. */
|
2009-10-03 02:39:53 +02:00
|
|
|
|
if (info->symtab_size != 0
|
2006-11-22 18:45:57 +01:00
|
|
|
|
&& bfd_asymbol_flavour (*info->symtab) == bfd_target_elf_flavour)
|
|
|
|
|
|
{
|
|
|
|
|
|
bfd_vma addr;
|
2010-01-29 17:47:55 +01:00
|
|
|
|
int n, start;
|
2006-11-22 18:45:57 +01:00
|
|
|
|
int last_sym = -1;
|
2010-01-29 17:47:55 +01:00
|
|
|
|
enum map_type type = MAP_ARM;
|
2006-11-22 18:45:57 +01:00
|
|
|
|
|
|
|
|
|
|
/* Start scanning at the start of the function, or wherever
|
|
|
|
|
|
we finished last time. */
|
2012-05-11 11:41:21 +02:00
|
|
|
|
/* PR 14006. When the address is 0 we are either at the start of the
|
|
|
|
|
|
very first function, or else the first function in a new, unlinked
|
2016-06-30 17:03:07 +02:00
|
|
|
|
executable section (eg because of -ffunction-sections). Either way
|
2012-05-11 11:41:21 +02:00
|
|
|
|
start scanning from the beginning of the symbol table, not where we
|
|
|
|
|
|
left off last time. */
|
|
|
|
|
|
if (pc == 0)
|
|
|
|
|
|
start = 0;
|
|
|
|
|
|
else
|
|
|
|
|
|
{
|
|
|
|
|
|
start = info->symtab_pos + 1;
|
|
|
|
|
|
if (start < private_data->last_mapping_sym)
|
|
|
|
|
|
start = private_data->last_mapping_sym;
|
|
|
|
|
|
}
|
2010-01-29 17:47:55 +01:00
|
|
|
|
found = FALSE;
|
2006-11-22 18:45:57 +01:00
|
|
|
|
|
2010-01-29 17:47:55 +01:00
|
|
|
|
/* First, look for mapping symbols. */
|
|
|
|
|
|
if (private_data->has_mapping_symbols != 0)
|
2006-11-22 18:45:57 +01:00
|
|
|
|
{
|
2010-01-29 17:47:55 +01:00
|
|
|
|
/* Scan up to the location being disassembled. */
|
|
|
|
|
|
for (n = start; n < info->symtab_size; n++)
|
|
|
|
|
|
{
|
|
|
|
|
|
addr = bfd_asymbol_value (info->symtab[n]);
|
|
|
|
|
|
if (addr > pc)
|
|
|
|
|
|
break;
|
|
|
|
|
|
if (get_map_sym_type (info, n, &type))
|
|
|
|
|
|
{
|
|
|
|
|
|
last_sym = n;
|
|
|
|
|
|
found = TRUE;
|
|
|
|
|
|
}
|
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
if (!found)
|
|
|
|
|
|
{
|
|
|
|
|
|
/* No mapping symbol found at this address. Look backwards
|
2011-06-02 15:43:24 +02:00
|
|
|
|
for a preceding one. */
|
2010-01-29 17:47:55 +01:00
|
|
|
|
for (n = start - 1; n >= 0; n--)
|
|
|
|
|
|
{
|
|
|
|
|
|
if (get_map_sym_type (info, n, &type))
|
|
|
|
|
|
{
|
|
|
|
|
|
last_sym = n;
|
|
|
|
|
|
found = TRUE;
|
|
|
|
|
|
break;
|
|
|
|
|
|
}
|
|
|
|
|
|
}
|
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
if (found)
|
|
|
|
|
|
private_data->has_mapping_symbols = 1;
|
|
|
|
|
|
|
|
|
|
|
|
/* No mapping symbols were found. A leading $d may be
|
|
|
|
|
|
omitted for sections which start with data; but for
|
|
|
|
|
|
compatibility with legacy and stripped binaries, only
|
|
|
|
|
|
assume the leading $d if there is at least one mapping
|
|
|
|
|
|
symbol in the file. */
|
|
|
|
|
|
if (!found && private_data->has_mapping_symbols == -1)
|
2006-11-22 18:45:57 +01:00
|
|
|
|
{
|
2010-01-29 17:47:55 +01:00
|
|
|
|
/* Look for mapping symbols, in any section. */
|
|
|
|
|
|
for (n = 0; n < info->symtab_size; n++)
|
|
|
|
|
|
if (is_mapping_symbol (info, n, &type))
|
|
|
|
|
|
{
|
|
|
|
|
|
private_data->has_mapping_symbols = 1;
|
|
|
|
|
|
break;
|
|
|
|
|
|
}
|
|
|
|
|
|
if (private_data->has_mapping_symbols == -1)
|
|
|
|
|
|
private_data->has_mapping_symbols = 0;
|
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
if (!found && private_data->has_mapping_symbols == 1)
|
|
|
|
|
|
{
|
|
|
|
|
|
type = MAP_DATA;
|
2006-11-22 18:45:57 +01:00
|
|
|
|
found = TRUE;
|
|
|
|
|
|
}
|
|
|
|
|
|
}
|
|
|
|
|
|
|
2010-01-29 17:47:55 +01:00
|
|
|
|
/* Next search for function symbols to separate ARM from Thumb
|
|
|
|
|
|
in binaries without mapping symbols. */
|
2006-11-22 18:45:57 +01:00
|
|
|
|
if (!found)
|
|
|
|
|
|
{
|
2010-01-29 17:47:55 +01:00
|
|
|
|
/* Scan up to the location being disassembled. */
|
|
|
|
|
|
for (n = start; n < info->symtab_size; n++)
|
2006-11-22 18:45:57 +01:00
|
|
|
|
{
|
2010-01-29 17:47:55 +01:00
|
|
|
|
addr = bfd_asymbol_value (info->symtab[n]);
|
|
|
|
|
|
if (addr > pc)
|
|
|
|
|
|
break;
|
|
|
|
|
|
if (get_sym_code_type (info, n, &type))
|
2006-11-22 18:45:57 +01:00
|
|
|
|
{
|
|
|
|
|
|
last_sym = n;
|
|
|
|
|
|
found = TRUE;
|
2010-01-29 17:47:55 +01:00
|
|
|
|
}
|
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
if (!found)
|
|
|
|
|
|
{
|
|
|
|
|
|
/* No mapping symbol found at this address. Look backwards
|
2011-06-02 15:43:24 +02:00
|
|
|
|
for a preceding one. */
|
2010-01-29 17:47:55 +01:00
|
|
|
|
for (n = start - 1; n >= 0; n--)
|
|
|
|
|
|
{
|
|
|
|
|
|
if (get_sym_code_type (info, n, &type))
|
|
|
|
|
|
{
|
|
|
|
|
|
last_sym = n;
|
|
|
|
|
|
found = TRUE;
|
|
|
|
|
|
break;
|
|
|
|
|
|
}
|
2006-11-22 18:45:57 +01:00
|
|
|
|
}
|
|
|
|
|
|
}
|
|
|
|
|
|
}
|
|
|
|
|
|
|
2011-04-08 13:42:19 +02:00
|
|
|
|
private_data->last_mapping_sym = last_sym;
|
|
|
|
|
|
private_data->last_type = type;
|
|
|
|
|
|
is_thumb = (private_data->last_type == MAP_THUMB);
|
|
|
|
|
|
is_data = (private_data->last_type == MAP_DATA);
|
2002-11-30 09:39:46 +01:00
|
|
|
|
|
2006-11-22 18:45:57 +01:00
|
|
|
|
/* Look a little bit ahead to see if we should print out
|
|
|
|
|
|
two or four bytes of data. If there's a symbol,
|
|
|
|
|
|
mapping or otherwise, after two bytes then don't
|
|
|
|
|
|
print more. */
|
|
|
|
|
|
if (is_data)
|
|
|
|
|
|
{
|
|
|
|
|
|
size = 4 - (pc & 3);
|
|
|
|
|
|
for (n = last_sym + 1; n < info->symtab_size; n++)
|
|
|
|
|
|
{
|
|
|
|
|
|
addr = bfd_asymbol_value (info->symtab[n]);
|
2010-01-06 16:02:45 +01:00
|
|
|
|
if (addr > pc
|
|
|
|
|
|
&& (info->section == NULL
|
|
|
|
|
|
|| info->section == info->symtab[n]->section))
|
2006-11-22 18:45:57 +01:00
|
|
|
|
{
|
|
|
|
|
|
if (addr - pc < size)
|
|
|
|
|
|
size = addr - pc;
|
|
|
|
|
|
break;
|
|
|
|
|
|
}
|
|
|
|
|
|
}
|
|
|
|
|
|
/* If the next symbol is after three bytes, we need to
|
|
|
|
|
|
print only part of the data, so that we can use either
|
|
|
|
|
|
.byte or .short. */
|
|
|
|
|
|
if (size == 3)
|
|
|
|
|
|
size = (pc & 1) ? 1 : 2;
|
|
|
|
|
|
}
|
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
if (info->symbols != NULL)
|
1999-05-03 09:29:11 +02:00
|
|
|
|
{
|
1999-06-16 04:58:52 +02:00
|
|
|
|
if (bfd_asymbol_flavour (*info->symbols) == bfd_target_coff_flavour)
|
|
|
|
|
|
{
|
2000-01-27 21:05:32 +01:00
|
|
|
|
coff_symbol_type * cs;
|
2002-11-30 09:39:46 +01:00
|
|
|
|
|
1999-06-16 04:58:52 +02:00
|
|
|
|
cs = coffsymbol (*info->symbols);
|
|
|
|
|
|
is_thumb = ( cs->native->u.syment.n_sclass == C_THUMBEXT
|
|
|
|
|
|
|| cs->native->u.syment.n_sclass == C_THUMBSTAT
|
|
|
|
|
|
|| cs->native->u.syment.n_sclass == C_THUMBLABEL
|
|
|
|
|
|
|| cs->native->u.syment.n_sclass == C_THUMBEXTFUNC
|
|
|
|
|
|
|| cs->native->u.syment.n_sclass == C_THUMBSTATFUNC);
|
|
|
|
|
|
}
|
2006-11-22 18:45:57 +01:00
|
|
|
|
else if (bfd_asymbol_flavour (*info->symbols) == bfd_target_elf_flavour
|
|
|
|
|
|
&& !found)
|
1999-06-16 04:58:52 +02:00
|
|
|
|
{
|
2006-10-31 21:21:57 +01:00
|
|
|
|
/* If no mapping symbol has been found then fall back to the type
|
|
|
|
|
|
of the function symbol. */
|
2006-11-22 18:45:57 +01:00
|
|
|
|
elf_symbol_type * es;
|
|
|
|
|
|
unsigned int type;
|
2006-10-31 21:21:57 +01:00
|
|
|
|
|
2006-11-22 18:45:57 +01:00
|
|
|
|
es = *(elf_symbol_type **)(info->symbols);
|
|
|
|
|
|
type = ELF_ST_TYPE (es->internal_elf_sym.st_info);
|
2006-10-31 21:21:57 +01:00
|
|
|
|
|
2016-05-10 17:14:23 +02:00
|
|
|
|
is_thumb =
|
|
|
|
|
|
((ARM_GET_SYM_BRANCH_TYPE (es->internal_elf_sym.st_target_internal)
|
|
|
|
|
|
== ST_BRANCH_TO_THUMB) || type == STT_ARM_16BIT);
|
1999-06-16 04:58:52 +02:00
|
|
|
|
}
|
2015-11-20 17:24:52 +01:00
|
|
|
|
else if (bfd_asymbol_flavour (*info->symbols)
|
|
|
|
|
|
== bfd_target_mach_o_flavour)
|
|
|
|
|
|
{
|
|
|
|
|
|
bfd_mach_o_asymbol *asym = (bfd_mach_o_asymbol *)*info->symbols;
|
|
|
|
|
|
|
|
|
|
|
|
is_thumb = (asym->n_desc & BFD_MACH_O_N_ARM_THUMB_DEF);
|
|
|
|
|
|
}
|
1999-06-16 04:58:52 +02:00
|
|
|
|
}
|
2002-11-30 09:39:46 +01:00
|
|
|
|
|
2006-11-22 18:45:57 +01:00
|
|
|
|
if (force_thumb)
|
|
|
|
|
|
is_thumb = TRUE;
|
|
|
|
|
|
|
2009-04-01 17:45:13 +02:00
|
|
|
|
if (is_data)
|
|
|
|
|
|
info->display_endian = little ? BFD_ENDIAN_LITTLE : BFD_ENDIAN_BIG;
|
|
|
|
|
|
else
|
|
|
|
|
|
info->display_endian = little_code ? BFD_ENDIAN_LITTLE : BFD_ENDIAN_BIG;
|
|
|
|
|
|
|
include/elf:
* arm.h: Import complete list of official relocation names
and numbers from AAELF. Define FAKE_RELOCs for old names.
Remove a few old names no longer used anywhere.
bfd:
* elf32-arm.c: Wherever possible, use official reloc names
from AAELF.
(elf32_arm_howto_table, elf32_arm_tls_gd32_howto)
(elf32_arm_tls_ldo32_howto, elf32_arm_tls_ldm32_howto)
(elf32_arm_tls_le32_howto, elf32_arm_tls_ie32_howto)
(elf32_arm_vtinherit_howto, elf32_arm_vtentry_howto)
(elf32_arm_pc11_howto, elf32_arm_thm_pc9_howto, elf32_arm_got_prel)
(elf32_arm_r_howto): Replace with elf32_arm_howto_table_1,
elf32_arm_howto_table_2, and elf32_arm_howto_table_3.
Add many new relocations from AAELF.
(elf32_arm_howto_from_type): Update to match.
(elf32_arm_reloc_map): Add entries for R_ARM_THM_JUMP24,
R_ARM_THM_JUMP11, R_ARM_THM_JUMP19, R_ARM_THM_JUMP8,
R_ARM_THM_JUMP6, R_ARM_GNU_VTINHERIT, and R_ARM_GNU_VTENTRY.
(elf32_arm_reloc_type_lookup): Use elf32_arm_howto_from_type.
(elf32_arm_final_link_relocate): Add support for
R_ARM_THM_JUMP24, R_ARM_THM_JUMP19, R_ARM_THM_JUMP6. Remove
case entries redundant with default.
* reloc.c: Reorganize ARM relocations. Add Thumb
assembler-internal relocations BFD_RELOC_ARM_T32_OFFSET_U8,
BFD_RELOC_ARM_T32_OFFSET_IMM, BFD_RELOC_ARM_T32_IMMEDIATE.
Add visible relocations BFD_RELOC_THUMB_PCREL_BRANCH7,
BFD_RELOC_THUMB_BRANCH20, BFD_RELOC_THUMB_BRANCH25.
Delete unused relocations BFD_RELOC_ARM_GOT12, BFD_RELOC_ARM_COPY.
* bfd-in2.h, libbfd.h: Regenerate.
opcodes:
* arm-dis.c (thumb_opcodes): Add disassembly for V6T2 16-bit
instructions. Adjust disassembly of some opcodes to match
unified syntax.
(thumb32_opcodes): New table.
(print_insn_thumb): Rename print_insn_thumb16; don't handle
two-halfword branches here.
(print_insn_thumb32): New function.
(print_insn): Choose among print_insn_arm, print_insn_thumb16,
and print_insn_thumb32. Be consistent about order of
halfwords when printing 32-bit instructions.
gas:
* hash.c (hash_lookup): Add len parameter. All callers changed.
(hash_find_n): New interface.
* hash.h: Prototype hash_find_n.
* sb.c: Include as.h.
(scrub_from_sb, sb_to_scrub, scrub_position): New statics.
(sb_scrub_and_add_sb): New interface.
* sb.h: Prototype sb_scrub_and_add_sb.
* input-scrub.c (input_scrub_include_sb): Use sb_scrub_and_add_sb.
* config/tc-arm.h (TC_FORCE_RELOCATION_LOCAL): Remove
reference to BFD_RELOC_ARM_GOT12 which is never generated.
* config/tc-arm.c: Rewrite, adding Thumb-2 support.
gas/testsuite:
* gas/arm/arm.exp: Convert all existing "gas_test" tests to
"run_dump_test" tests. Run more tests unconditionally. Run new tests.
* gas/arm/arch4t.s, gas/arm/arch6zk.s, gas/arm/arm3.s, gas/arm/arm6.s
* gas/arm/arm7dm.s, gas/arm/bignum1.s, gas/arm/float.s
* gas/arm/immed.s, gas/arm/iwmmxt.s, gas/arm/offset.s, gas/arm/thumb.s:
Adjust to work as a dump test.
* gas/arm/arch4t.d, gas/arm/arch6zk.d, gas/arm/arm3.d, gas/arm/arm6.d
* gas/arm/arm7dm.d, gas/arm/bignum1.d, gas/arm/float.d
* gas/arm/immed.d, gas/arm/iwmmxt.d, gas/arm/offset.d, gas/arm/thumb.d:
New files.
* gas/arm/armv1-bad.l, gas/arm/armv1-bad.s: Remove tests for
diagnostics that don't happen in the first pass anymore.
* gas/arm/iwmmxt-bad.l, gas/arm/r15-bad.l, gas/arm/req.l
* gas/arm/vfp-bad.l:
Update expected diagnostics.
* gas/arm/pic.d: Update expected reloc name.
* gas/arm/thumbv6.d: CPY no longer appears in disassembly.
* gas/arm/r15-bad.s: Avoid two-argument mul.
* gas/arm/req.s: Adjust comments.
* gas/arm/maverick.d, gas/arm/maverick.s: Avoid inappropriate
use of PC.
* gas/arm/macro-1.d, gas/arm/macro1.s
* gas/arm/t16-bad.l, gas/arm/t16-bad.s
* gas/arm/tcompat.d, gas/arm/tcompat.s
* gas/arm/tcompat2.d, gas/arm/tcompat2.s
* gas/arm/thumb32.d, gas/arm/thumb32.s
New test pair.
ld/testsuite:
* ld-arm/mixed-app.d: Adjust expected disassembly a little.
2005-05-18 07:40:12 +02:00
|
|
|
|
info->bytes_per_line = 4;
|
1999-05-03 09:29:11 +02:00
|
|
|
|
|
2009-06-15 13:37:26 +02:00
|
|
|
|
/* PR 10263: Disassemble data if requested to do so by the user. */
|
|
|
|
|
|
if (is_data && ((info->flags & DISASSEMBLE_DATA) == 0))
|
2006-11-22 18:45:57 +01:00
|
|
|
|
{
|
|
|
|
|
|
int i;
|
|
|
|
|
|
|
2009-06-15 13:37:26 +02:00
|
|
|
|
/* Size was already set above. */
|
2006-11-22 18:45:57 +01:00
|
|
|
|
info->bytes_per_chunk = size;
|
|
|
|
|
|
printer = print_insn_data;
|
|
|
|
|
|
|
2009-06-30 13:57:05 +02:00
|
|
|
|
status = info->read_memory_func (pc, (bfd_byte *) b, size, info);
|
2006-11-22 18:45:57 +01:00
|
|
|
|
given = 0;
|
|
|
|
|
|
if (little)
|
|
|
|
|
|
for (i = size - 1; i >= 0; i--)
|
|
|
|
|
|
given = b[i] | (given << 8);
|
|
|
|
|
|
else
|
|
|
|
|
|
for (i = 0; i < (int) size; i++)
|
|
|
|
|
|
given = b[i] | (given << 8);
|
|
|
|
|
|
}
|
|
|
|
|
|
else if (!is_thumb)
|
1999-05-03 09:29:11 +02:00
|
|
|
|
{
|
include/elf:
* arm.h: Import complete list of official relocation names
and numbers from AAELF. Define FAKE_RELOCs for old names.
Remove a few old names no longer used anywhere.
bfd:
* elf32-arm.c: Wherever possible, use official reloc names
from AAELF.
(elf32_arm_howto_table, elf32_arm_tls_gd32_howto)
(elf32_arm_tls_ldo32_howto, elf32_arm_tls_ldm32_howto)
(elf32_arm_tls_le32_howto, elf32_arm_tls_ie32_howto)
(elf32_arm_vtinherit_howto, elf32_arm_vtentry_howto)
(elf32_arm_pc11_howto, elf32_arm_thm_pc9_howto, elf32_arm_got_prel)
(elf32_arm_r_howto): Replace with elf32_arm_howto_table_1,
elf32_arm_howto_table_2, and elf32_arm_howto_table_3.
Add many new relocations from AAELF.
(elf32_arm_howto_from_type): Update to match.
(elf32_arm_reloc_map): Add entries for R_ARM_THM_JUMP24,
R_ARM_THM_JUMP11, R_ARM_THM_JUMP19, R_ARM_THM_JUMP8,
R_ARM_THM_JUMP6, R_ARM_GNU_VTINHERIT, and R_ARM_GNU_VTENTRY.
(elf32_arm_reloc_type_lookup): Use elf32_arm_howto_from_type.
(elf32_arm_final_link_relocate): Add support for
R_ARM_THM_JUMP24, R_ARM_THM_JUMP19, R_ARM_THM_JUMP6. Remove
case entries redundant with default.
* reloc.c: Reorganize ARM relocations. Add Thumb
assembler-internal relocations BFD_RELOC_ARM_T32_OFFSET_U8,
BFD_RELOC_ARM_T32_OFFSET_IMM, BFD_RELOC_ARM_T32_IMMEDIATE.
Add visible relocations BFD_RELOC_THUMB_PCREL_BRANCH7,
BFD_RELOC_THUMB_BRANCH20, BFD_RELOC_THUMB_BRANCH25.
Delete unused relocations BFD_RELOC_ARM_GOT12, BFD_RELOC_ARM_COPY.
* bfd-in2.h, libbfd.h: Regenerate.
opcodes:
* arm-dis.c (thumb_opcodes): Add disassembly for V6T2 16-bit
instructions. Adjust disassembly of some opcodes to match
unified syntax.
(thumb32_opcodes): New table.
(print_insn_thumb): Rename print_insn_thumb16; don't handle
two-halfword branches here.
(print_insn_thumb32): New function.
(print_insn): Choose among print_insn_arm, print_insn_thumb16,
and print_insn_thumb32. Be consistent about order of
halfwords when printing 32-bit instructions.
gas:
* hash.c (hash_lookup): Add len parameter. All callers changed.
(hash_find_n): New interface.
* hash.h: Prototype hash_find_n.
* sb.c: Include as.h.
(scrub_from_sb, sb_to_scrub, scrub_position): New statics.
(sb_scrub_and_add_sb): New interface.
* sb.h: Prototype sb_scrub_and_add_sb.
* input-scrub.c (input_scrub_include_sb): Use sb_scrub_and_add_sb.
* config/tc-arm.h (TC_FORCE_RELOCATION_LOCAL): Remove
reference to BFD_RELOC_ARM_GOT12 which is never generated.
* config/tc-arm.c: Rewrite, adding Thumb-2 support.
gas/testsuite:
* gas/arm/arm.exp: Convert all existing "gas_test" tests to
"run_dump_test" tests. Run more tests unconditionally. Run new tests.
* gas/arm/arch4t.s, gas/arm/arch6zk.s, gas/arm/arm3.s, gas/arm/arm6.s
* gas/arm/arm7dm.s, gas/arm/bignum1.s, gas/arm/float.s
* gas/arm/immed.s, gas/arm/iwmmxt.s, gas/arm/offset.s, gas/arm/thumb.s:
Adjust to work as a dump test.
* gas/arm/arch4t.d, gas/arm/arch6zk.d, gas/arm/arm3.d, gas/arm/arm6.d
* gas/arm/arm7dm.d, gas/arm/bignum1.d, gas/arm/float.d
* gas/arm/immed.d, gas/arm/iwmmxt.d, gas/arm/offset.d, gas/arm/thumb.d:
New files.
* gas/arm/armv1-bad.l, gas/arm/armv1-bad.s: Remove tests for
diagnostics that don't happen in the first pass anymore.
* gas/arm/iwmmxt-bad.l, gas/arm/r15-bad.l, gas/arm/req.l
* gas/arm/vfp-bad.l:
Update expected diagnostics.
* gas/arm/pic.d: Update expected reloc name.
* gas/arm/thumbv6.d: CPY no longer appears in disassembly.
* gas/arm/r15-bad.s: Avoid two-argument mul.
* gas/arm/req.s: Adjust comments.
* gas/arm/maverick.d, gas/arm/maverick.s: Avoid inappropriate
use of PC.
* gas/arm/macro-1.d, gas/arm/macro1.s
* gas/arm/t16-bad.l, gas/arm/t16-bad.s
* gas/arm/tcompat.d, gas/arm/tcompat.s
* gas/arm/tcompat2.d, gas/arm/tcompat2.s
* gas/arm/thumb32.d, gas/arm/thumb32.s
New test pair.
ld/testsuite:
* ld-arm/mixed-app.d: Adjust expected disassembly a little.
2005-05-18 07:40:12 +02:00
|
|
|
|
/* In ARM mode endianness is a straightforward issue: the instruction
|
|
|
|
|
|
is four bytes long and is either ordered 0123 or 3210. */
|
|
|
|
|
|
printer = print_insn_arm;
|
|
|
|
|
|
info->bytes_per_chunk = 4;
|
2005-06-08 00:16:52 +02:00
|
|
|
|
size = 4;
|
include/elf:
* arm.h: Import complete list of official relocation names
and numbers from AAELF. Define FAKE_RELOCs for old names.
Remove a few old names no longer used anywhere.
bfd:
* elf32-arm.c: Wherever possible, use official reloc names
from AAELF.
(elf32_arm_howto_table, elf32_arm_tls_gd32_howto)
(elf32_arm_tls_ldo32_howto, elf32_arm_tls_ldm32_howto)
(elf32_arm_tls_le32_howto, elf32_arm_tls_ie32_howto)
(elf32_arm_vtinherit_howto, elf32_arm_vtentry_howto)
(elf32_arm_pc11_howto, elf32_arm_thm_pc9_howto, elf32_arm_got_prel)
(elf32_arm_r_howto): Replace with elf32_arm_howto_table_1,
elf32_arm_howto_table_2, and elf32_arm_howto_table_3.
Add many new relocations from AAELF.
(elf32_arm_howto_from_type): Update to match.
(elf32_arm_reloc_map): Add entries for R_ARM_THM_JUMP24,
R_ARM_THM_JUMP11, R_ARM_THM_JUMP19, R_ARM_THM_JUMP8,
R_ARM_THM_JUMP6, R_ARM_GNU_VTINHERIT, and R_ARM_GNU_VTENTRY.
(elf32_arm_reloc_type_lookup): Use elf32_arm_howto_from_type.
(elf32_arm_final_link_relocate): Add support for
R_ARM_THM_JUMP24, R_ARM_THM_JUMP19, R_ARM_THM_JUMP6. Remove
case entries redundant with default.
* reloc.c: Reorganize ARM relocations. Add Thumb
assembler-internal relocations BFD_RELOC_ARM_T32_OFFSET_U8,
BFD_RELOC_ARM_T32_OFFSET_IMM, BFD_RELOC_ARM_T32_IMMEDIATE.
Add visible relocations BFD_RELOC_THUMB_PCREL_BRANCH7,
BFD_RELOC_THUMB_BRANCH20, BFD_RELOC_THUMB_BRANCH25.
Delete unused relocations BFD_RELOC_ARM_GOT12, BFD_RELOC_ARM_COPY.
* bfd-in2.h, libbfd.h: Regenerate.
opcodes:
* arm-dis.c (thumb_opcodes): Add disassembly for V6T2 16-bit
instructions. Adjust disassembly of some opcodes to match
unified syntax.
(thumb32_opcodes): New table.
(print_insn_thumb): Rename print_insn_thumb16; don't handle
two-halfword branches here.
(print_insn_thumb32): New function.
(print_insn): Choose among print_insn_arm, print_insn_thumb16,
and print_insn_thumb32. Be consistent about order of
halfwords when printing 32-bit instructions.
gas:
* hash.c (hash_lookup): Add len parameter. All callers changed.
(hash_find_n): New interface.
* hash.h: Prototype hash_find_n.
* sb.c: Include as.h.
(scrub_from_sb, sb_to_scrub, scrub_position): New statics.
(sb_scrub_and_add_sb): New interface.
* sb.h: Prototype sb_scrub_and_add_sb.
* input-scrub.c (input_scrub_include_sb): Use sb_scrub_and_add_sb.
* config/tc-arm.h (TC_FORCE_RELOCATION_LOCAL): Remove
reference to BFD_RELOC_ARM_GOT12 which is never generated.
* config/tc-arm.c: Rewrite, adding Thumb-2 support.
gas/testsuite:
* gas/arm/arm.exp: Convert all existing "gas_test" tests to
"run_dump_test" tests. Run more tests unconditionally. Run new tests.
* gas/arm/arch4t.s, gas/arm/arch6zk.s, gas/arm/arm3.s, gas/arm/arm6.s
* gas/arm/arm7dm.s, gas/arm/bignum1.s, gas/arm/float.s
* gas/arm/immed.s, gas/arm/iwmmxt.s, gas/arm/offset.s, gas/arm/thumb.s:
Adjust to work as a dump test.
* gas/arm/arch4t.d, gas/arm/arch6zk.d, gas/arm/arm3.d, gas/arm/arm6.d
* gas/arm/arm7dm.d, gas/arm/bignum1.d, gas/arm/float.d
* gas/arm/immed.d, gas/arm/iwmmxt.d, gas/arm/offset.d, gas/arm/thumb.d:
New files.
* gas/arm/armv1-bad.l, gas/arm/armv1-bad.s: Remove tests for
diagnostics that don't happen in the first pass anymore.
* gas/arm/iwmmxt-bad.l, gas/arm/r15-bad.l, gas/arm/req.l
* gas/arm/vfp-bad.l:
Update expected diagnostics.
* gas/arm/pic.d: Update expected reloc name.
* gas/arm/thumbv6.d: CPY no longer appears in disassembly.
* gas/arm/r15-bad.s: Avoid two-argument mul.
* gas/arm/req.s: Adjust comments.
* gas/arm/maverick.d, gas/arm/maverick.s: Avoid inappropriate
use of PC.
* gas/arm/macro-1.d, gas/arm/macro1.s
* gas/arm/t16-bad.l, gas/arm/t16-bad.s
* gas/arm/tcompat.d, gas/arm/tcompat.s
* gas/arm/tcompat2.d, gas/arm/tcompat2.s
* gas/arm/thumb32.d, gas/arm/thumb32.s
New test pair.
ld/testsuite:
* ld-arm/mixed-app.d: Adjust expected disassembly a little.
2005-05-18 07:40:12 +02:00
|
|
|
|
|
2009-06-18 12:31:21 +02:00
|
|
|
|
status = info->read_memory_func (pc, (bfd_byte *) b, 4, info);
|
2008-07-07 20:35:24 +02:00
|
|
|
|
if (little_code)
|
include/elf:
* arm.h: Import complete list of official relocation names
and numbers from AAELF. Define FAKE_RELOCs for old names.
Remove a few old names no longer used anywhere.
bfd:
* elf32-arm.c: Wherever possible, use official reloc names
from AAELF.
(elf32_arm_howto_table, elf32_arm_tls_gd32_howto)
(elf32_arm_tls_ldo32_howto, elf32_arm_tls_ldm32_howto)
(elf32_arm_tls_le32_howto, elf32_arm_tls_ie32_howto)
(elf32_arm_vtinherit_howto, elf32_arm_vtentry_howto)
(elf32_arm_pc11_howto, elf32_arm_thm_pc9_howto, elf32_arm_got_prel)
(elf32_arm_r_howto): Replace with elf32_arm_howto_table_1,
elf32_arm_howto_table_2, and elf32_arm_howto_table_3.
Add many new relocations from AAELF.
(elf32_arm_howto_from_type): Update to match.
(elf32_arm_reloc_map): Add entries for R_ARM_THM_JUMP24,
R_ARM_THM_JUMP11, R_ARM_THM_JUMP19, R_ARM_THM_JUMP8,
R_ARM_THM_JUMP6, R_ARM_GNU_VTINHERIT, and R_ARM_GNU_VTENTRY.
(elf32_arm_reloc_type_lookup): Use elf32_arm_howto_from_type.
(elf32_arm_final_link_relocate): Add support for
R_ARM_THM_JUMP24, R_ARM_THM_JUMP19, R_ARM_THM_JUMP6. Remove
case entries redundant with default.
* reloc.c: Reorganize ARM relocations. Add Thumb
assembler-internal relocations BFD_RELOC_ARM_T32_OFFSET_U8,
BFD_RELOC_ARM_T32_OFFSET_IMM, BFD_RELOC_ARM_T32_IMMEDIATE.
Add visible relocations BFD_RELOC_THUMB_PCREL_BRANCH7,
BFD_RELOC_THUMB_BRANCH20, BFD_RELOC_THUMB_BRANCH25.
Delete unused relocations BFD_RELOC_ARM_GOT12, BFD_RELOC_ARM_COPY.
* bfd-in2.h, libbfd.h: Regenerate.
opcodes:
* arm-dis.c (thumb_opcodes): Add disassembly for V6T2 16-bit
instructions. Adjust disassembly of some opcodes to match
unified syntax.
(thumb32_opcodes): New table.
(print_insn_thumb): Rename print_insn_thumb16; don't handle
two-halfword branches here.
(print_insn_thumb32): New function.
(print_insn): Choose among print_insn_arm, print_insn_thumb16,
and print_insn_thumb32. Be consistent about order of
halfwords when printing 32-bit instructions.
gas:
* hash.c (hash_lookup): Add len parameter. All callers changed.
(hash_find_n): New interface.
* hash.h: Prototype hash_find_n.
* sb.c: Include as.h.
(scrub_from_sb, sb_to_scrub, scrub_position): New statics.
(sb_scrub_and_add_sb): New interface.
* sb.h: Prototype sb_scrub_and_add_sb.
* input-scrub.c (input_scrub_include_sb): Use sb_scrub_and_add_sb.
* config/tc-arm.h (TC_FORCE_RELOCATION_LOCAL): Remove
reference to BFD_RELOC_ARM_GOT12 which is never generated.
* config/tc-arm.c: Rewrite, adding Thumb-2 support.
gas/testsuite:
* gas/arm/arm.exp: Convert all existing "gas_test" tests to
"run_dump_test" tests. Run more tests unconditionally. Run new tests.
* gas/arm/arch4t.s, gas/arm/arch6zk.s, gas/arm/arm3.s, gas/arm/arm6.s
* gas/arm/arm7dm.s, gas/arm/bignum1.s, gas/arm/float.s
* gas/arm/immed.s, gas/arm/iwmmxt.s, gas/arm/offset.s, gas/arm/thumb.s:
Adjust to work as a dump test.
* gas/arm/arch4t.d, gas/arm/arch6zk.d, gas/arm/arm3.d, gas/arm/arm6.d
* gas/arm/arm7dm.d, gas/arm/bignum1.d, gas/arm/float.d
* gas/arm/immed.d, gas/arm/iwmmxt.d, gas/arm/offset.d, gas/arm/thumb.d:
New files.
* gas/arm/armv1-bad.l, gas/arm/armv1-bad.s: Remove tests for
diagnostics that don't happen in the first pass anymore.
* gas/arm/iwmmxt-bad.l, gas/arm/r15-bad.l, gas/arm/req.l
* gas/arm/vfp-bad.l:
Update expected diagnostics.
* gas/arm/pic.d: Update expected reloc name.
* gas/arm/thumbv6.d: CPY no longer appears in disassembly.
* gas/arm/r15-bad.s: Avoid two-argument mul.
* gas/arm/req.s: Adjust comments.
* gas/arm/maverick.d, gas/arm/maverick.s: Avoid inappropriate
use of PC.
* gas/arm/macro-1.d, gas/arm/macro1.s
* gas/arm/t16-bad.l, gas/arm/t16-bad.s
* gas/arm/tcompat.d, gas/arm/tcompat.s
* gas/arm/tcompat2.d, gas/arm/tcompat2.s
* gas/arm/thumb32.d, gas/arm/thumb32.s
New test pair.
ld/testsuite:
* ld-arm/mixed-app.d: Adjust expected disassembly a little.
2005-05-18 07:40:12 +02:00
|
|
|
|
given = (b[0]) | (b[1] << 8) | (b[2] << 16) | (b[3] << 24);
|
|
|
|
|
|
else
|
|
|
|
|
|
given = (b[3]) | (b[2] << 8) | (b[1] << 16) | (b[0] << 24);
|
1999-05-03 09:29:11 +02:00
|
|
|
|
}
|
2000-01-27 23:17:12 +01:00
|
|
|
|
else
|
1999-05-03 09:29:11 +02:00
|
|
|
|
{
|
include/elf:
* arm.h: Import complete list of official relocation names
and numbers from AAELF. Define FAKE_RELOCs for old names.
Remove a few old names no longer used anywhere.
bfd:
* elf32-arm.c: Wherever possible, use official reloc names
from AAELF.
(elf32_arm_howto_table, elf32_arm_tls_gd32_howto)
(elf32_arm_tls_ldo32_howto, elf32_arm_tls_ldm32_howto)
(elf32_arm_tls_le32_howto, elf32_arm_tls_ie32_howto)
(elf32_arm_vtinherit_howto, elf32_arm_vtentry_howto)
(elf32_arm_pc11_howto, elf32_arm_thm_pc9_howto, elf32_arm_got_prel)
(elf32_arm_r_howto): Replace with elf32_arm_howto_table_1,
elf32_arm_howto_table_2, and elf32_arm_howto_table_3.
Add many new relocations from AAELF.
(elf32_arm_howto_from_type): Update to match.
(elf32_arm_reloc_map): Add entries for R_ARM_THM_JUMP24,
R_ARM_THM_JUMP11, R_ARM_THM_JUMP19, R_ARM_THM_JUMP8,
R_ARM_THM_JUMP6, R_ARM_GNU_VTINHERIT, and R_ARM_GNU_VTENTRY.
(elf32_arm_reloc_type_lookup): Use elf32_arm_howto_from_type.
(elf32_arm_final_link_relocate): Add support for
R_ARM_THM_JUMP24, R_ARM_THM_JUMP19, R_ARM_THM_JUMP6. Remove
case entries redundant with default.
* reloc.c: Reorganize ARM relocations. Add Thumb
assembler-internal relocations BFD_RELOC_ARM_T32_OFFSET_U8,
BFD_RELOC_ARM_T32_OFFSET_IMM, BFD_RELOC_ARM_T32_IMMEDIATE.
Add visible relocations BFD_RELOC_THUMB_PCREL_BRANCH7,
BFD_RELOC_THUMB_BRANCH20, BFD_RELOC_THUMB_BRANCH25.
Delete unused relocations BFD_RELOC_ARM_GOT12, BFD_RELOC_ARM_COPY.
* bfd-in2.h, libbfd.h: Regenerate.
opcodes:
* arm-dis.c (thumb_opcodes): Add disassembly for V6T2 16-bit
instructions. Adjust disassembly of some opcodes to match
unified syntax.
(thumb32_opcodes): New table.
(print_insn_thumb): Rename print_insn_thumb16; don't handle
two-halfword branches here.
(print_insn_thumb32): New function.
(print_insn): Choose among print_insn_arm, print_insn_thumb16,
and print_insn_thumb32. Be consistent about order of
halfwords when printing 32-bit instructions.
gas:
* hash.c (hash_lookup): Add len parameter. All callers changed.
(hash_find_n): New interface.
* hash.h: Prototype hash_find_n.
* sb.c: Include as.h.
(scrub_from_sb, sb_to_scrub, scrub_position): New statics.
(sb_scrub_and_add_sb): New interface.
* sb.h: Prototype sb_scrub_and_add_sb.
* input-scrub.c (input_scrub_include_sb): Use sb_scrub_and_add_sb.
* config/tc-arm.h (TC_FORCE_RELOCATION_LOCAL): Remove
reference to BFD_RELOC_ARM_GOT12 which is never generated.
* config/tc-arm.c: Rewrite, adding Thumb-2 support.
gas/testsuite:
* gas/arm/arm.exp: Convert all existing "gas_test" tests to
"run_dump_test" tests. Run more tests unconditionally. Run new tests.
* gas/arm/arch4t.s, gas/arm/arch6zk.s, gas/arm/arm3.s, gas/arm/arm6.s
* gas/arm/arm7dm.s, gas/arm/bignum1.s, gas/arm/float.s
* gas/arm/immed.s, gas/arm/iwmmxt.s, gas/arm/offset.s, gas/arm/thumb.s:
Adjust to work as a dump test.
* gas/arm/arch4t.d, gas/arm/arch6zk.d, gas/arm/arm3.d, gas/arm/arm6.d
* gas/arm/arm7dm.d, gas/arm/bignum1.d, gas/arm/float.d
* gas/arm/immed.d, gas/arm/iwmmxt.d, gas/arm/offset.d, gas/arm/thumb.d:
New files.
* gas/arm/armv1-bad.l, gas/arm/armv1-bad.s: Remove tests for
diagnostics that don't happen in the first pass anymore.
* gas/arm/iwmmxt-bad.l, gas/arm/r15-bad.l, gas/arm/req.l
* gas/arm/vfp-bad.l:
Update expected diagnostics.
* gas/arm/pic.d: Update expected reloc name.
* gas/arm/thumbv6.d: CPY no longer appears in disassembly.
* gas/arm/r15-bad.s: Avoid two-argument mul.
* gas/arm/req.s: Adjust comments.
* gas/arm/maverick.d, gas/arm/maverick.s: Avoid inappropriate
use of PC.
* gas/arm/macro-1.d, gas/arm/macro1.s
* gas/arm/t16-bad.l, gas/arm/t16-bad.s
* gas/arm/tcompat.d, gas/arm/tcompat.s
* gas/arm/tcompat2.d, gas/arm/tcompat2.s
* gas/arm/thumb32.d, gas/arm/thumb32.s
New test pair.
ld/testsuite:
* ld-arm/mixed-app.d: Adjust expected disassembly a little.
2005-05-18 07:40:12 +02:00
|
|
|
|
/* In Thumb mode we have the additional wrinkle of two
|
|
|
|
|
|
instruction lengths. Fortunately, the bits that determine
|
|
|
|
|
|
the length of the current instruction are always to be found
|
|
|
|
|
|
in the first two bytes. */
|
2005-06-08 00:16:52 +02:00
|
|
|
|
printer = print_insn_thumb16;
|
include/elf:
* arm.h: Import complete list of official relocation names
and numbers from AAELF. Define FAKE_RELOCs for old names.
Remove a few old names no longer used anywhere.
bfd:
* elf32-arm.c: Wherever possible, use official reloc names
from AAELF.
(elf32_arm_howto_table, elf32_arm_tls_gd32_howto)
(elf32_arm_tls_ldo32_howto, elf32_arm_tls_ldm32_howto)
(elf32_arm_tls_le32_howto, elf32_arm_tls_ie32_howto)
(elf32_arm_vtinherit_howto, elf32_arm_vtentry_howto)
(elf32_arm_pc11_howto, elf32_arm_thm_pc9_howto, elf32_arm_got_prel)
(elf32_arm_r_howto): Replace with elf32_arm_howto_table_1,
elf32_arm_howto_table_2, and elf32_arm_howto_table_3.
Add many new relocations from AAELF.
(elf32_arm_howto_from_type): Update to match.
(elf32_arm_reloc_map): Add entries for R_ARM_THM_JUMP24,
R_ARM_THM_JUMP11, R_ARM_THM_JUMP19, R_ARM_THM_JUMP8,
R_ARM_THM_JUMP6, R_ARM_GNU_VTINHERIT, and R_ARM_GNU_VTENTRY.
(elf32_arm_reloc_type_lookup): Use elf32_arm_howto_from_type.
(elf32_arm_final_link_relocate): Add support for
R_ARM_THM_JUMP24, R_ARM_THM_JUMP19, R_ARM_THM_JUMP6. Remove
case entries redundant with default.
* reloc.c: Reorganize ARM relocations. Add Thumb
assembler-internal relocations BFD_RELOC_ARM_T32_OFFSET_U8,
BFD_RELOC_ARM_T32_OFFSET_IMM, BFD_RELOC_ARM_T32_IMMEDIATE.
Add visible relocations BFD_RELOC_THUMB_PCREL_BRANCH7,
BFD_RELOC_THUMB_BRANCH20, BFD_RELOC_THUMB_BRANCH25.
Delete unused relocations BFD_RELOC_ARM_GOT12, BFD_RELOC_ARM_COPY.
* bfd-in2.h, libbfd.h: Regenerate.
opcodes:
* arm-dis.c (thumb_opcodes): Add disassembly for V6T2 16-bit
instructions. Adjust disassembly of some opcodes to match
unified syntax.
(thumb32_opcodes): New table.
(print_insn_thumb): Rename print_insn_thumb16; don't handle
two-halfword branches here.
(print_insn_thumb32): New function.
(print_insn): Choose among print_insn_arm, print_insn_thumb16,
and print_insn_thumb32. Be consistent about order of
halfwords when printing 32-bit instructions.
gas:
* hash.c (hash_lookup): Add len parameter. All callers changed.
(hash_find_n): New interface.
* hash.h: Prototype hash_find_n.
* sb.c: Include as.h.
(scrub_from_sb, sb_to_scrub, scrub_position): New statics.
(sb_scrub_and_add_sb): New interface.
* sb.h: Prototype sb_scrub_and_add_sb.
* input-scrub.c (input_scrub_include_sb): Use sb_scrub_and_add_sb.
* config/tc-arm.h (TC_FORCE_RELOCATION_LOCAL): Remove
reference to BFD_RELOC_ARM_GOT12 which is never generated.
* config/tc-arm.c: Rewrite, adding Thumb-2 support.
gas/testsuite:
* gas/arm/arm.exp: Convert all existing "gas_test" tests to
"run_dump_test" tests. Run more tests unconditionally. Run new tests.
* gas/arm/arch4t.s, gas/arm/arch6zk.s, gas/arm/arm3.s, gas/arm/arm6.s
* gas/arm/arm7dm.s, gas/arm/bignum1.s, gas/arm/float.s
* gas/arm/immed.s, gas/arm/iwmmxt.s, gas/arm/offset.s, gas/arm/thumb.s:
Adjust to work as a dump test.
* gas/arm/arch4t.d, gas/arm/arch6zk.d, gas/arm/arm3.d, gas/arm/arm6.d
* gas/arm/arm7dm.d, gas/arm/bignum1.d, gas/arm/float.d
* gas/arm/immed.d, gas/arm/iwmmxt.d, gas/arm/offset.d, gas/arm/thumb.d:
New files.
* gas/arm/armv1-bad.l, gas/arm/armv1-bad.s: Remove tests for
diagnostics that don't happen in the first pass anymore.
* gas/arm/iwmmxt-bad.l, gas/arm/r15-bad.l, gas/arm/req.l
* gas/arm/vfp-bad.l:
Update expected diagnostics.
* gas/arm/pic.d: Update expected reloc name.
* gas/arm/thumbv6.d: CPY no longer appears in disassembly.
* gas/arm/r15-bad.s: Avoid two-argument mul.
* gas/arm/req.s: Adjust comments.
* gas/arm/maverick.d, gas/arm/maverick.s: Avoid inappropriate
use of PC.
* gas/arm/macro-1.d, gas/arm/macro1.s
* gas/arm/t16-bad.l, gas/arm/t16-bad.s
* gas/arm/tcompat.d, gas/arm/tcompat.s
* gas/arm/tcompat2.d, gas/arm/tcompat2.s
* gas/arm/thumb32.d, gas/arm/thumb32.s
New test pair.
ld/testsuite:
* ld-arm/mixed-app.d: Adjust expected disassembly a little.
2005-05-18 07:40:12 +02:00
|
|
|
|
info->bytes_per_chunk = 2;
|
2005-06-08 00:16:52 +02:00
|
|
|
|
size = 2;
|
|
|
|
|
|
|
2009-06-30 13:57:05 +02:00
|
|
|
|
status = info->read_memory_func (pc, (bfd_byte *) b, 2, info);
|
2008-07-07 20:35:24 +02:00
|
|
|
|
if (little_code)
|
2005-10-31 07:10:33 +01:00
|
|
|
|
given = (b[0]) | (b[1] << 8);
|
|
|
|
|
|
else
|
|
|
|
|
|
given = (b[1]) | (b[0] << 8);
|
|
|
|
|
|
|
include/elf:
* arm.h: Import complete list of official relocation names
and numbers from AAELF. Define FAKE_RELOCs for old names.
Remove a few old names no longer used anywhere.
bfd:
* elf32-arm.c: Wherever possible, use official reloc names
from AAELF.
(elf32_arm_howto_table, elf32_arm_tls_gd32_howto)
(elf32_arm_tls_ldo32_howto, elf32_arm_tls_ldm32_howto)
(elf32_arm_tls_le32_howto, elf32_arm_tls_ie32_howto)
(elf32_arm_vtinherit_howto, elf32_arm_vtentry_howto)
(elf32_arm_pc11_howto, elf32_arm_thm_pc9_howto, elf32_arm_got_prel)
(elf32_arm_r_howto): Replace with elf32_arm_howto_table_1,
elf32_arm_howto_table_2, and elf32_arm_howto_table_3.
Add many new relocations from AAELF.
(elf32_arm_howto_from_type): Update to match.
(elf32_arm_reloc_map): Add entries for R_ARM_THM_JUMP24,
R_ARM_THM_JUMP11, R_ARM_THM_JUMP19, R_ARM_THM_JUMP8,
R_ARM_THM_JUMP6, R_ARM_GNU_VTINHERIT, and R_ARM_GNU_VTENTRY.
(elf32_arm_reloc_type_lookup): Use elf32_arm_howto_from_type.
(elf32_arm_final_link_relocate): Add support for
R_ARM_THM_JUMP24, R_ARM_THM_JUMP19, R_ARM_THM_JUMP6. Remove
case entries redundant with default.
* reloc.c: Reorganize ARM relocations. Add Thumb
assembler-internal relocations BFD_RELOC_ARM_T32_OFFSET_U8,
BFD_RELOC_ARM_T32_OFFSET_IMM, BFD_RELOC_ARM_T32_IMMEDIATE.
Add visible relocations BFD_RELOC_THUMB_PCREL_BRANCH7,
BFD_RELOC_THUMB_BRANCH20, BFD_RELOC_THUMB_BRANCH25.
Delete unused relocations BFD_RELOC_ARM_GOT12, BFD_RELOC_ARM_COPY.
* bfd-in2.h, libbfd.h: Regenerate.
opcodes:
* arm-dis.c (thumb_opcodes): Add disassembly for V6T2 16-bit
instructions. Adjust disassembly of some opcodes to match
unified syntax.
(thumb32_opcodes): New table.
(print_insn_thumb): Rename print_insn_thumb16; don't handle
two-halfword branches here.
(print_insn_thumb32): New function.
(print_insn): Choose among print_insn_arm, print_insn_thumb16,
and print_insn_thumb32. Be consistent about order of
halfwords when printing 32-bit instructions.
gas:
* hash.c (hash_lookup): Add len parameter. All callers changed.
(hash_find_n): New interface.
* hash.h: Prototype hash_find_n.
* sb.c: Include as.h.
(scrub_from_sb, sb_to_scrub, scrub_position): New statics.
(sb_scrub_and_add_sb): New interface.
* sb.h: Prototype sb_scrub_and_add_sb.
* input-scrub.c (input_scrub_include_sb): Use sb_scrub_and_add_sb.
* config/tc-arm.h (TC_FORCE_RELOCATION_LOCAL): Remove
reference to BFD_RELOC_ARM_GOT12 which is never generated.
* config/tc-arm.c: Rewrite, adding Thumb-2 support.
gas/testsuite:
* gas/arm/arm.exp: Convert all existing "gas_test" tests to
"run_dump_test" tests. Run more tests unconditionally. Run new tests.
* gas/arm/arch4t.s, gas/arm/arch6zk.s, gas/arm/arm3.s, gas/arm/arm6.s
* gas/arm/arm7dm.s, gas/arm/bignum1.s, gas/arm/float.s
* gas/arm/immed.s, gas/arm/iwmmxt.s, gas/arm/offset.s, gas/arm/thumb.s:
Adjust to work as a dump test.
* gas/arm/arch4t.d, gas/arm/arch6zk.d, gas/arm/arm3.d, gas/arm/arm6.d
* gas/arm/arm7dm.d, gas/arm/bignum1.d, gas/arm/float.d
* gas/arm/immed.d, gas/arm/iwmmxt.d, gas/arm/offset.d, gas/arm/thumb.d:
New files.
* gas/arm/armv1-bad.l, gas/arm/armv1-bad.s: Remove tests for
diagnostics that don't happen in the first pass anymore.
* gas/arm/iwmmxt-bad.l, gas/arm/r15-bad.l, gas/arm/req.l
* gas/arm/vfp-bad.l:
Update expected diagnostics.
* gas/arm/pic.d: Update expected reloc name.
* gas/arm/thumbv6.d: CPY no longer appears in disassembly.
* gas/arm/r15-bad.s: Avoid two-argument mul.
* gas/arm/req.s: Adjust comments.
* gas/arm/maverick.d, gas/arm/maverick.s: Avoid inappropriate
use of PC.
* gas/arm/macro-1.d, gas/arm/macro1.s
* gas/arm/t16-bad.l, gas/arm/t16-bad.s
* gas/arm/tcompat.d, gas/arm/tcompat.s
* gas/arm/tcompat2.d, gas/arm/tcompat2.s
* gas/arm/thumb32.d, gas/arm/thumb32.s
New test pair.
ld/testsuite:
* ld-arm/mixed-app.d: Adjust expected disassembly a little.
2005-05-18 07:40:12 +02:00
|
|
|
|
if (!status)
|
1999-05-03 09:29:11 +02:00
|
|
|
|
{
|
include/elf:
* arm.h: Import complete list of official relocation names
and numbers from AAELF. Define FAKE_RELOCs for old names.
Remove a few old names no longer used anywhere.
bfd:
* elf32-arm.c: Wherever possible, use official reloc names
from AAELF.
(elf32_arm_howto_table, elf32_arm_tls_gd32_howto)
(elf32_arm_tls_ldo32_howto, elf32_arm_tls_ldm32_howto)
(elf32_arm_tls_le32_howto, elf32_arm_tls_ie32_howto)
(elf32_arm_vtinherit_howto, elf32_arm_vtentry_howto)
(elf32_arm_pc11_howto, elf32_arm_thm_pc9_howto, elf32_arm_got_prel)
(elf32_arm_r_howto): Replace with elf32_arm_howto_table_1,
elf32_arm_howto_table_2, and elf32_arm_howto_table_3.
Add many new relocations from AAELF.
(elf32_arm_howto_from_type): Update to match.
(elf32_arm_reloc_map): Add entries for R_ARM_THM_JUMP24,
R_ARM_THM_JUMP11, R_ARM_THM_JUMP19, R_ARM_THM_JUMP8,
R_ARM_THM_JUMP6, R_ARM_GNU_VTINHERIT, and R_ARM_GNU_VTENTRY.
(elf32_arm_reloc_type_lookup): Use elf32_arm_howto_from_type.
(elf32_arm_final_link_relocate): Add support for
R_ARM_THM_JUMP24, R_ARM_THM_JUMP19, R_ARM_THM_JUMP6. Remove
case entries redundant with default.
* reloc.c: Reorganize ARM relocations. Add Thumb
assembler-internal relocations BFD_RELOC_ARM_T32_OFFSET_U8,
BFD_RELOC_ARM_T32_OFFSET_IMM, BFD_RELOC_ARM_T32_IMMEDIATE.
Add visible relocations BFD_RELOC_THUMB_PCREL_BRANCH7,
BFD_RELOC_THUMB_BRANCH20, BFD_RELOC_THUMB_BRANCH25.
Delete unused relocations BFD_RELOC_ARM_GOT12, BFD_RELOC_ARM_COPY.
* bfd-in2.h, libbfd.h: Regenerate.
opcodes:
* arm-dis.c (thumb_opcodes): Add disassembly for V6T2 16-bit
instructions. Adjust disassembly of some opcodes to match
unified syntax.
(thumb32_opcodes): New table.
(print_insn_thumb): Rename print_insn_thumb16; don't handle
two-halfword branches here.
(print_insn_thumb32): New function.
(print_insn): Choose among print_insn_arm, print_insn_thumb16,
and print_insn_thumb32. Be consistent about order of
halfwords when printing 32-bit instructions.
gas:
* hash.c (hash_lookup): Add len parameter. All callers changed.
(hash_find_n): New interface.
* hash.h: Prototype hash_find_n.
* sb.c: Include as.h.
(scrub_from_sb, sb_to_scrub, scrub_position): New statics.
(sb_scrub_and_add_sb): New interface.
* sb.h: Prototype sb_scrub_and_add_sb.
* input-scrub.c (input_scrub_include_sb): Use sb_scrub_and_add_sb.
* config/tc-arm.h (TC_FORCE_RELOCATION_LOCAL): Remove
reference to BFD_RELOC_ARM_GOT12 which is never generated.
* config/tc-arm.c: Rewrite, adding Thumb-2 support.
gas/testsuite:
* gas/arm/arm.exp: Convert all existing "gas_test" tests to
"run_dump_test" tests. Run more tests unconditionally. Run new tests.
* gas/arm/arch4t.s, gas/arm/arch6zk.s, gas/arm/arm3.s, gas/arm/arm6.s
* gas/arm/arm7dm.s, gas/arm/bignum1.s, gas/arm/float.s
* gas/arm/immed.s, gas/arm/iwmmxt.s, gas/arm/offset.s, gas/arm/thumb.s:
Adjust to work as a dump test.
* gas/arm/arch4t.d, gas/arm/arch6zk.d, gas/arm/arm3.d, gas/arm/arm6.d
* gas/arm/arm7dm.d, gas/arm/bignum1.d, gas/arm/float.d
* gas/arm/immed.d, gas/arm/iwmmxt.d, gas/arm/offset.d, gas/arm/thumb.d:
New files.
* gas/arm/armv1-bad.l, gas/arm/armv1-bad.s: Remove tests for
diagnostics that don't happen in the first pass anymore.
* gas/arm/iwmmxt-bad.l, gas/arm/r15-bad.l, gas/arm/req.l
* gas/arm/vfp-bad.l:
Update expected diagnostics.
* gas/arm/pic.d: Update expected reloc name.
* gas/arm/thumbv6.d: CPY no longer appears in disassembly.
* gas/arm/r15-bad.s: Avoid two-argument mul.
* gas/arm/req.s: Adjust comments.
* gas/arm/maverick.d, gas/arm/maverick.s: Avoid inappropriate
use of PC.
* gas/arm/macro-1.d, gas/arm/macro1.s
* gas/arm/t16-bad.l, gas/arm/t16-bad.s
* gas/arm/tcompat.d, gas/arm/tcompat.s
* gas/arm/tcompat2.d, gas/arm/tcompat2.s
* gas/arm/thumb32.d, gas/arm/thumb32.s
New test pair.
ld/testsuite:
* ld-arm/mixed-app.d: Adjust expected disassembly a little.
2005-05-18 07:40:12 +02:00
|
|
|
|
/* These bit patterns signal a four-byte Thumb
|
|
|
|
|
|
instruction. */
|
|
|
|
|
|
if ((given & 0xF800) == 0xF800
|
|
|
|
|
|
|| (given & 0xF800) == 0xF000
|
|
|
|
|
|
|| (given & 0xF800) == 0xE800)
|
1999-05-03 09:29:11 +02:00
|
|
|
|
{
|
2009-06-18 12:31:21 +02:00
|
|
|
|
status = info->read_memory_func (pc + 2, (bfd_byte *) b, 2, info);
|
2008-07-07 20:35:24 +02:00
|
|
|
|
if (little_code)
|
include/elf:
* arm.h: Import complete list of official relocation names
and numbers from AAELF. Define FAKE_RELOCs for old names.
Remove a few old names no longer used anywhere.
bfd:
* elf32-arm.c: Wherever possible, use official reloc names
from AAELF.
(elf32_arm_howto_table, elf32_arm_tls_gd32_howto)
(elf32_arm_tls_ldo32_howto, elf32_arm_tls_ldm32_howto)
(elf32_arm_tls_le32_howto, elf32_arm_tls_ie32_howto)
(elf32_arm_vtinherit_howto, elf32_arm_vtentry_howto)
(elf32_arm_pc11_howto, elf32_arm_thm_pc9_howto, elf32_arm_got_prel)
(elf32_arm_r_howto): Replace with elf32_arm_howto_table_1,
elf32_arm_howto_table_2, and elf32_arm_howto_table_3.
Add many new relocations from AAELF.
(elf32_arm_howto_from_type): Update to match.
(elf32_arm_reloc_map): Add entries for R_ARM_THM_JUMP24,
R_ARM_THM_JUMP11, R_ARM_THM_JUMP19, R_ARM_THM_JUMP8,
R_ARM_THM_JUMP6, R_ARM_GNU_VTINHERIT, and R_ARM_GNU_VTENTRY.
(elf32_arm_reloc_type_lookup): Use elf32_arm_howto_from_type.
(elf32_arm_final_link_relocate): Add support for
R_ARM_THM_JUMP24, R_ARM_THM_JUMP19, R_ARM_THM_JUMP6. Remove
case entries redundant with default.
* reloc.c: Reorganize ARM relocations. Add Thumb
assembler-internal relocations BFD_RELOC_ARM_T32_OFFSET_U8,
BFD_RELOC_ARM_T32_OFFSET_IMM, BFD_RELOC_ARM_T32_IMMEDIATE.
Add visible relocations BFD_RELOC_THUMB_PCREL_BRANCH7,
BFD_RELOC_THUMB_BRANCH20, BFD_RELOC_THUMB_BRANCH25.
Delete unused relocations BFD_RELOC_ARM_GOT12, BFD_RELOC_ARM_COPY.
* bfd-in2.h, libbfd.h: Regenerate.
opcodes:
* arm-dis.c (thumb_opcodes): Add disassembly for V6T2 16-bit
instructions. Adjust disassembly of some opcodes to match
unified syntax.
(thumb32_opcodes): New table.
(print_insn_thumb): Rename print_insn_thumb16; don't handle
two-halfword branches here.
(print_insn_thumb32): New function.
(print_insn): Choose among print_insn_arm, print_insn_thumb16,
and print_insn_thumb32. Be consistent about order of
halfwords when printing 32-bit instructions.
gas:
* hash.c (hash_lookup): Add len parameter. All callers changed.
(hash_find_n): New interface.
* hash.h: Prototype hash_find_n.
* sb.c: Include as.h.
(scrub_from_sb, sb_to_scrub, scrub_position): New statics.
(sb_scrub_and_add_sb): New interface.
* sb.h: Prototype sb_scrub_and_add_sb.
* input-scrub.c (input_scrub_include_sb): Use sb_scrub_and_add_sb.
* config/tc-arm.h (TC_FORCE_RELOCATION_LOCAL): Remove
reference to BFD_RELOC_ARM_GOT12 which is never generated.
* config/tc-arm.c: Rewrite, adding Thumb-2 support.
gas/testsuite:
* gas/arm/arm.exp: Convert all existing "gas_test" tests to
"run_dump_test" tests. Run more tests unconditionally. Run new tests.
* gas/arm/arch4t.s, gas/arm/arch6zk.s, gas/arm/arm3.s, gas/arm/arm6.s
* gas/arm/arm7dm.s, gas/arm/bignum1.s, gas/arm/float.s
* gas/arm/immed.s, gas/arm/iwmmxt.s, gas/arm/offset.s, gas/arm/thumb.s:
Adjust to work as a dump test.
* gas/arm/arch4t.d, gas/arm/arch6zk.d, gas/arm/arm3.d, gas/arm/arm6.d
* gas/arm/arm7dm.d, gas/arm/bignum1.d, gas/arm/float.d
* gas/arm/immed.d, gas/arm/iwmmxt.d, gas/arm/offset.d, gas/arm/thumb.d:
New files.
* gas/arm/armv1-bad.l, gas/arm/armv1-bad.s: Remove tests for
diagnostics that don't happen in the first pass anymore.
* gas/arm/iwmmxt-bad.l, gas/arm/r15-bad.l, gas/arm/req.l
* gas/arm/vfp-bad.l:
Update expected diagnostics.
* gas/arm/pic.d: Update expected reloc name.
* gas/arm/thumbv6.d: CPY no longer appears in disassembly.
* gas/arm/r15-bad.s: Avoid two-argument mul.
* gas/arm/req.s: Adjust comments.
* gas/arm/maverick.d, gas/arm/maverick.s: Avoid inappropriate
use of PC.
* gas/arm/macro-1.d, gas/arm/macro1.s
* gas/arm/t16-bad.l, gas/arm/t16-bad.s
* gas/arm/tcompat.d, gas/arm/tcompat.s
* gas/arm/tcompat2.d, gas/arm/tcompat2.s
* gas/arm/thumb32.d, gas/arm/thumb32.s
New test pair.
ld/testsuite:
* ld-arm/mixed-app.d: Adjust expected disassembly a little.
2005-05-18 07:40:12 +02:00
|
|
|
|
given = (b[0]) | (b[1] << 8) | (given << 16);
|
bfd/
* elf32-arm.c (PLT_THUMB_STUB_SIZE): Define.
(elf32_arm_plt_thumb_stub): New.
(struct elf32_arm_link_hash_entry): Add plt_thumb_refcount
and plt_got_offset.
(elf32_arm_link_hash_traverse): Fix typo.
(elf32_arm_link_hash_table): Add obfd.
(elf32_arm_link_hash_newfunc): Initialize new fields.
(elf32_arm_copy_indirect_symbol): Copy plt_thumb_refcount.
(elf32_arm_link_hash_table_create): Initialize obfd.
(record_arm_to_thumb_glue): Mark the glue as a local ARM function.
(record_thumb_to_arm_glue): Mark the glue as a local Thumb function.
(bfd_elf32_arm_get_bfd_for_interworking): Verify that the
interworking BFD is not dynamic.
(bfd_elf32_arm_process_before_allocation): Handle R_ARM_PLT32. Do
not emit glue for PLT references.
(elf32_arm_final_link_relocate): Handle Thumb functions. Do not
emit glue for PLT references. Support the Thumb PLT prefix.
(elf32_arm_gc_sweep_hook): Handle R_ARM_THM_PC22 and
plt_thumb_refcount.
(elf32_arm_check_relocs): Likewise.
(elf32_arm_adjust_dynamic_symbol): Handle Thumb functions and
plt_thumb_refcount.
(allocate_dynrelocs): Handle Thumb PLT references.
(elf32_arm_finish_dynamic_symbol): Likewise.
(elf32_arm_symbol_processing): New function.
(elf_backend_symbol_processing): Define.
opcodes/
* arm-dis.c (WORD_ADDRESS): Define.
(print_insn): Use it. Correct big-endian end-of-section handling.
gas/testsuite/
* gas/arm/mapping.d: Expect F markers for Thumb code.
* gas/arm/unwind.d: Update big-endian pattern.
ld/
* emultempl/armelf.em (arm_elf_set_bfd_for_interworking): Don't use
a dynamic object for stubs.
ld/testsuite/
* ld-arm/mixed-app.d, ld-arm/mixed-app.r, ld-arm/mixed-app.s,
ld-arm/mixed-app.sym, ld-arm/mixed-lib.d, ld-arm/mixed-lib.r,
ld-arm/mixed-lib.s, ld-arm/mixed-lib.sym, ld-arm/arm-dyn.ld,
ld-arm/arm-lib.ld: New files.
* ld-arm/arm-app-abs32.d, ld-arm/arm-app-abs32.r, ld-arm/arm-app.d,
ld-arm/arm-app.r, ld-arm/arm-lib-plt32.d, ld-arm/arm-lib-plt32.r,
ld-arm/arm-lib.d, ld-arm/arm-lib.r, ld-arm/arm-static-app.d,
ld-arm/arm-static-app.r: Update for big-endian.
* ld-arm/arm-elf.exp: Run the new tests.
2004-11-17 18:50:28 +01:00
|
|
|
|
else
|
include/elf:
* arm.h: Import complete list of official relocation names
and numbers from AAELF. Define FAKE_RELOCs for old names.
Remove a few old names no longer used anywhere.
bfd:
* elf32-arm.c: Wherever possible, use official reloc names
from AAELF.
(elf32_arm_howto_table, elf32_arm_tls_gd32_howto)
(elf32_arm_tls_ldo32_howto, elf32_arm_tls_ldm32_howto)
(elf32_arm_tls_le32_howto, elf32_arm_tls_ie32_howto)
(elf32_arm_vtinherit_howto, elf32_arm_vtentry_howto)
(elf32_arm_pc11_howto, elf32_arm_thm_pc9_howto, elf32_arm_got_prel)
(elf32_arm_r_howto): Replace with elf32_arm_howto_table_1,
elf32_arm_howto_table_2, and elf32_arm_howto_table_3.
Add many new relocations from AAELF.
(elf32_arm_howto_from_type): Update to match.
(elf32_arm_reloc_map): Add entries for R_ARM_THM_JUMP24,
R_ARM_THM_JUMP11, R_ARM_THM_JUMP19, R_ARM_THM_JUMP8,
R_ARM_THM_JUMP6, R_ARM_GNU_VTINHERIT, and R_ARM_GNU_VTENTRY.
(elf32_arm_reloc_type_lookup): Use elf32_arm_howto_from_type.
(elf32_arm_final_link_relocate): Add support for
R_ARM_THM_JUMP24, R_ARM_THM_JUMP19, R_ARM_THM_JUMP6. Remove
case entries redundant with default.
* reloc.c: Reorganize ARM relocations. Add Thumb
assembler-internal relocations BFD_RELOC_ARM_T32_OFFSET_U8,
BFD_RELOC_ARM_T32_OFFSET_IMM, BFD_RELOC_ARM_T32_IMMEDIATE.
Add visible relocations BFD_RELOC_THUMB_PCREL_BRANCH7,
BFD_RELOC_THUMB_BRANCH20, BFD_RELOC_THUMB_BRANCH25.
Delete unused relocations BFD_RELOC_ARM_GOT12, BFD_RELOC_ARM_COPY.
* bfd-in2.h, libbfd.h: Regenerate.
opcodes:
* arm-dis.c (thumb_opcodes): Add disassembly for V6T2 16-bit
instructions. Adjust disassembly of some opcodes to match
unified syntax.
(thumb32_opcodes): New table.
(print_insn_thumb): Rename print_insn_thumb16; don't handle
two-halfword branches here.
(print_insn_thumb32): New function.
(print_insn): Choose among print_insn_arm, print_insn_thumb16,
and print_insn_thumb32. Be consistent about order of
halfwords when printing 32-bit instructions.
gas:
* hash.c (hash_lookup): Add len parameter. All callers changed.
(hash_find_n): New interface.
* hash.h: Prototype hash_find_n.
* sb.c: Include as.h.
(scrub_from_sb, sb_to_scrub, scrub_position): New statics.
(sb_scrub_and_add_sb): New interface.
* sb.h: Prototype sb_scrub_and_add_sb.
* input-scrub.c (input_scrub_include_sb): Use sb_scrub_and_add_sb.
* config/tc-arm.h (TC_FORCE_RELOCATION_LOCAL): Remove
reference to BFD_RELOC_ARM_GOT12 which is never generated.
* config/tc-arm.c: Rewrite, adding Thumb-2 support.
gas/testsuite:
* gas/arm/arm.exp: Convert all existing "gas_test" tests to
"run_dump_test" tests. Run more tests unconditionally. Run new tests.
* gas/arm/arch4t.s, gas/arm/arch6zk.s, gas/arm/arm3.s, gas/arm/arm6.s
* gas/arm/arm7dm.s, gas/arm/bignum1.s, gas/arm/float.s
* gas/arm/immed.s, gas/arm/iwmmxt.s, gas/arm/offset.s, gas/arm/thumb.s:
Adjust to work as a dump test.
* gas/arm/arch4t.d, gas/arm/arch6zk.d, gas/arm/arm3.d, gas/arm/arm6.d
* gas/arm/arm7dm.d, gas/arm/bignum1.d, gas/arm/float.d
* gas/arm/immed.d, gas/arm/iwmmxt.d, gas/arm/offset.d, gas/arm/thumb.d:
New files.
* gas/arm/armv1-bad.l, gas/arm/armv1-bad.s: Remove tests for
diagnostics that don't happen in the first pass anymore.
* gas/arm/iwmmxt-bad.l, gas/arm/r15-bad.l, gas/arm/req.l
* gas/arm/vfp-bad.l:
Update expected diagnostics.
* gas/arm/pic.d: Update expected reloc name.
* gas/arm/thumbv6.d: CPY no longer appears in disassembly.
* gas/arm/r15-bad.s: Avoid two-argument mul.
* gas/arm/req.s: Adjust comments.
* gas/arm/maverick.d, gas/arm/maverick.s: Avoid inappropriate
use of PC.
* gas/arm/macro-1.d, gas/arm/macro1.s
* gas/arm/t16-bad.l, gas/arm/t16-bad.s
* gas/arm/tcompat.d, gas/arm/tcompat.s
* gas/arm/tcompat2.d, gas/arm/tcompat2.s
* gas/arm/thumb32.d, gas/arm/thumb32.s
New test pair.
ld/testsuite:
* ld-arm/mixed-app.d: Adjust expected disassembly a little.
2005-05-18 07:40:12 +02:00
|
|
|
|
given = (b[1]) | (b[0] << 8) | (given << 16);
|
|
|
|
|
|
|
|
|
|
|
|
printer = print_insn_thumb32;
|
2005-06-08 00:16:52 +02:00
|
|
|
|
size = 4;
|
1999-05-03 09:29:11 +02:00
|
|
|
|
}
|
|
|
|
|
|
}
|
2006-06-07 16:08:19 +02:00
|
|
|
|
|
|
|
|
|
|
if (ifthen_address != pc)
|
2009-06-18 12:31:21 +02:00
|
|
|
|
find_ifthen_state (pc, info, little_code);
|
2006-06-07 16:08:19 +02:00
|
|
|
|
|
|
|
|
|
|
if (ifthen_state)
|
|
|
|
|
|
{
|
|
|
|
|
|
if ((ifthen_state & 0xf) == 0x8)
|
|
|
|
|
|
ifthen_next_state = 0;
|
|
|
|
|
|
else
|
|
|
|
|
|
ifthen_next_state = (ifthen_state & 0xe0)
|
|
|
|
|
|
| ((ifthen_state & 0xf) << 1);
|
|
|
|
|
|
}
|
1999-05-03 09:29:11 +02:00
|
|
|
|
}
|
2002-11-30 09:39:46 +01:00
|
|
|
|
|
include/elf:
* arm.h: Import complete list of official relocation names
and numbers from AAELF. Define FAKE_RELOCs for old names.
Remove a few old names no longer used anywhere.
bfd:
* elf32-arm.c: Wherever possible, use official reloc names
from AAELF.
(elf32_arm_howto_table, elf32_arm_tls_gd32_howto)
(elf32_arm_tls_ldo32_howto, elf32_arm_tls_ldm32_howto)
(elf32_arm_tls_le32_howto, elf32_arm_tls_ie32_howto)
(elf32_arm_vtinherit_howto, elf32_arm_vtentry_howto)
(elf32_arm_pc11_howto, elf32_arm_thm_pc9_howto, elf32_arm_got_prel)
(elf32_arm_r_howto): Replace with elf32_arm_howto_table_1,
elf32_arm_howto_table_2, and elf32_arm_howto_table_3.
Add many new relocations from AAELF.
(elf32_arm_howto_from_type): Update to match.
(elf32_arm_reloc_map): Add entries for R_ARM_THM_JUMP24,
R_ARM_THM_JUMP11, R_ARM_THM_JUMP19, R_ARM_THM_JUMP8,
R_ARM_THM_JUMP6, R_ARM_GNU_VTINHERIT, and R_ARM_GNU_VTENTRY.
(elf32_arm_reloc_type_lookup): Use elf32_arm_howto_from_type.
(elf32_arm_final_link_relocate): Add support for
R_ARM_THM_JUMP24, R_ARM_THM_JUMP19, R_ARM_THM_JUMP6. Remove
case entries redundant with default.
* reloc.c: Reorganize ARM relocations. Add Thumb
assembler-internal relocations BFD_RELOC_ARM_T32_OFFSET_U8,
BFD_RELOC_ARM_T32_OFFSET_IMM, BFD_RELOC_ARM_T32_IMMEDIATE.
Add visible relocations BFD_RELOC_THUMB_PCREL_BRANCH7,
BFD_RELOC_THUMB_BRANCH20, BFD_RELOC_THUMB_BRANCH25.
Delete unused relocations BFD_RELOC_ARM_GOT12, BFD_RELOC_ARM_COPY.
* bfd-in2.h, libbfd.h: Regenerate.
opcodes:
* arm-dis.c (thumb_opcodes): Add disassembly for V6T2 16-bit
instructions. Adjust disassembly of some opcodes to match
unified syntax.
(thumb32_opcodes): New table.
(print_insn_thumb): Rename print_insn_thumb16; don't handle
two-halfword branches here.
(print_insn_thumb32): New function.
(print_insn): Choose among print_insn_arm, print_insn_thumb16,
and print_insn_thumb32. Be consistent about order of
halfwords when printing 32-bit instructions.
gas:
* hash.c (hash_lookup): Add len parameter. All callers changed.
(hash_find_n): New interface.
* hash.h: Prototype hash_find_n.
* sb.c: Include as.h.
(scrub_from_sb, sb_to_scrub, scrub_position): New statics.
(sb_scrub_and_add_sb): New interface.
* sb.h: Prototype sb_scrub_and_add_sb.
* input-scrub.c (input_scrub_include_sb): Use sb_scrub_and_add_sb.
* config/tc-arm.h (TC_FORCE_RELOCATION_LOCAL): Remove
reference to BFD_RELOC_ARM_GOT12 which is never generated.
* config/tc-arm.c: Rewrite, adding Thumb-2 support.
gas/testsuite:
* gas/arm/arm.exp: Convert all existing "gas_test" tests to
"run_dump_test" tests. Run more tests unconditionally. Run new tests.
* gas/arm/arch4t.s, gas/arm/arch6zk.s, gas/arm/arm3.s, gas/arm/arm6.s
* gas/arm/arm7dm.s, gas/arm/bignum1.s, gas/arm/float.s
* gas/arm/immed.s, gas/arm/iwmmxt.s, gas/arm/offset.s, gas/arm/thumb.s:
Adjust to work as a dump test.
* gas/arm/arch4t.d, gas/arm/arch6zk.d, gas/arm/arm3.d, gas/arm/arm6.d
* gas/arm/arm7dm.d, gas/arm/bignum1.d, gas/arm/float.d
* gas/arm/immed.d, gas/arm/iwmmxt.d, gas/arm/offset.d, gas/arm/thumb.d:
New files.
* gas/arm/armv1-bad.l, gas/arm/armv1-bad.s: Remove tests for
diagnostics that don't happen in the first pass anymore.
* gas/arm/iwmmxt-bad.l, gas/arm/r15-bad.l, gas/arm/req.l
* gas/arm/vfp-bad.l:
Update expected diagnostics.
* gas/arm/pic.d: Update expected reloc name.
* gas/arm/thumbv6.d: CPY no longer appears in disassembly.
* gas/arm/r15-bad.s: Avoid two-argument mul.
* gas/arm/req.s: Adjust comments.
* gas/arm/maverick.d, gas/arm/maverick.s: Avoid inappropriate
use of PC.
* gas/arm/macro-1.d, gas/arm/macro1.s
* gas/arm/t16-bad.l, gas/arm/t16-bad.s
* gas/arm/tcompat.d, gas/arm/tcompat.s
* gas/arm/tcompat2.d, gas/arm/tcompat2.s
* gas/arm/thumb32.d, gas/arm/thumb32.s
New test pair.
ld/testsuite:
* ld-arm/mixed-app.d: Adjust expected disassembly a little.
2005-05-18 07:40:12 +02:00
|
|
|
|
if (status)
|
|
|
|
|
|
{
|
|
|
|
|
|
info->memory_error_func (status, pc, info);
|
|
|
|
|
|
return -1;
|
|
|
|
|
|
}
|
2001-01-09 21:29:48 +01:00
|
|
|
|
if (info->flags & INSN_HAS_RELOC)
|
|
|
|
|
|
/* If the instruction has a reloc associated with it, then
|
|
|
|
|
|
the offset field in the instruction will actually be the
|
|
|
|
|
|
addend for the reloc. (We are using REL type relocs).
|
|
|
|
|
|
In such cases, we can ignore the pc when computing
|
|
|
|
|
|
addresses, since the addend is not currently pc-relative. */
|
|
|
|
|
|
pc = 0;
|
2002-11-30 09:39:46 +01:00
|
|
|
|
|
2005-06-08 00:16:52 +02:00
|
|
|
|
printer (pc, info, given);
|
2006-06-07 16:08:19 +02:00
|
|
|
|
|
|
|
|
|
|
if (is_thumb)
|
|
|
|
|
|
{
|
|
|
|
|
|
ifthen_state = ifthen_next_state;
|
|
|
|
|
|
ifthen_address += size;
|
|
|
|
|
|
}
|
2005-06-08 00:16:52 +02:00
|
|
|
|
return size;
|
1999-05-03 09:29:11 +02:00
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
int
|
2005-06-08 00:16:52 +02:00
|
|
|
|
print_insn_big_arm (bfd_vma pc, struct disassemble_info *info)
|
1999-05-03 09:29:11 +02:00
|
|
|
|
{
|
2008-07-07 20:35:24 +02:00
|
|
|
|
/* Detect BE8-ness and record it in the disassembler info. */
|
|
|
|
|
|
if (info->flavour == bfd_target_elf_flavour
|
|
|
|
|
|
&& info->section != NULL
|
|
|
|
|
|
&& (elf_elfheader (info->section->owner)->e_flags & EF_ARM_BE8))
|
|
|
|
|
|
info->endian_code = BFD_ENDIAN_LITTLE;
|
|
|
|
|
|
|
2002-11-30 09:39:46 +01:00
|
|
|
|
return print_insn (pc, info, FALSE);
|
2000-01-27 23:17:12 +01:00
|
|
|
|
}
|
2000-01-03 21:50:57 +01:00
|
|
|
|
|
2000-01-27 23:17:12 +01:00
|
|
|
|
int
|
2005-06-08 00:16:52 +02:00
|
|
|
|
print_insn_little_arm (bfd_vma pc, struct disassemble_info *info)
|
2000-01-27 23:17:12 +01:00
|
|
|
|
{
|
2002-11-30 09:39:46 +01:00
|
|
|
|
return print_insn (pc, info, TRUE);
|
2000-01-27 23:17:12 +01:00
|
|
|
|
}
|
1999-05-03 09:29:11 +02:00
|
|
|
|
|
GDB PR tdep/8282: MIPS: Wire in `set disassembler-options'
Implement MIPS target support for passing options to the disassembler,
complementing commit 65b48a81404c ("GDB: Add support for the new
set/show disassembler-options commands.").
This includes options that expect an argument, so adjust the generic
code and data structures used so as to handle such options. So as to
give backends syntax flexibility no specific delimiter has been defined
to separate options from their respective arguments, so it has to be
included as the last character of the option name. Completion code
however has not been adjusted and consequently option arguments cannot
be completed at this time.
Also the MIPS target has non-empty defaults for the options, so that ABI
names for the general-purpose registers respect our `set mips abi ...'
setting rather than always being determined from the ELF headers of the
binary file selected. Handle these defaults as implicit options, never
shown to the user and always prepended to the user-specified options, so
that the latters can override the defaults.
The resulting output for the MIPS target is as follows:
(gdb) show disassembler-options
The current disassembler options are ''
The following disassembler options are supported for use with the
'set disassembler-options <option>[,<option>...]' command:
no-aliases Use canonical instruction forms.
msa Recognize MSA instructions.
virt Recognize the virtualization ASE instructions.
xpa Recognize the eXtended Physical Address (XPA) ASE
instructions.
ginv Recognize the Global INValidate (GINV) ASE instructions.
gpr-names=ABI Print GPR names according to specified ABI.
Default: based on binary being disassembled.
fpr-names=ABI Print FPR names according to specified ABI.
Default: numeric.
cp0-names=ARCH Print CP0 register names according to specified architecture.
Default: based on binary being disassembled.
hwr-names=ARCH Print HWR names according to specified architecture.
Default: based on binary being disassembled.
reg-names=ABI Print GPR and FPR names according to specified ABI.
reg-names=ARCH Print CP0 register and HWR names according to specified
architecture.
For the options above, the following values are supported for "ABI":
numeric 32 n32 64
For the options above, the following values are supported for "ARCH":
numeric r3000 r3900 r4000 r4010 vr4100 vr4111 vr4120 r4300 r4400 r4600
r4650 r5000 vr5400 vr5500 r5900 r6000 rm7000 rm9000 r8000 r10000 r12000
r14000 r16000 mips5 mips32 mips32r2 mips32r3 mips32r5 mips32r6 mips64
mips64r2 mips64r3 mips64r5 mips64r6 interaptiv-mr2 sb1 loongson2e
loongson2f loongson3a octeon octeon+ octeon2 octeon3 xlr xlp
(gdb)
which corresponds to what `objdump --help' used to print for the MIPS
target, with minor formatting changes, most notably option argument
lists being wrapped, but also the amount of white space separating
options from the respective descriptions. The relevant part the new
code is now also used by `objdump --help', which means these formatting
changes apply to both outputs, except for argument list wrapping, which
is GDB-specific.
This also adds a separating new line between the heading and option
lists where descriptions are provided, hence:
(gdb) set architecture s390:31-bit
(gdb) show disassembler-options
The current disassembler options are ''
The following disassembler options are supported for use with the
'set disassembler-options <option>[,<option>...]' command:
esa Disassemble in ESA architecture mode
zarch Disassemble in z/Architecture mode
insnlength Print unknown instructions according to length from first two bits
(gdb)
but:
(gdb) set architecture powerpc:common
(gdb) show disassembler-options
The current disassembler options are ''
The following disassembler options are supported for use with the
'set disassembler-options <option>[,<option>...]' command:
403, 405, 440, 464, 476, 601, 603, 604, 620, 7400, 7410, 7450, 7455, 750cl,
821, 850, 860, a2, altivec, any, booke, booke32, cell, com, e200z4, e300,
e500, e500mc, e500mc64, e5500, e6500, e500x2, efs, efs2, power4, power5,
power6, power7, power8, power9, ppc, ppc32, 32, ppc64, 64, ppc64bridge,
ppcps, pwr, pwr2, pwr4, pwr5, pwr5x, pwr6, pwr7, pwr8, pwr9, pwrx, raw, spe,
spe2, titan, vle, vsx
(gdb)
Existing affected target backends have been adjusted accordingly.
This has been verified manually with:
(gdb) set architecture arm
(gdb) set architecture powerpc:common
(gdb) set architecture s390:31-bit
to cause no issues with the `show disassembler-options' and `set
disassembler-options' commands. A test case for the MIPS target has
also been provided, covering the default settings with ABI overrides as
well as disassembler option overrides.
2018-07-02 Maciej W. Rozycki <macro@mips.com>
Simon Marchi <simon.marchi@polymtl.ca>
include/
PR tdep/8282
* dis-asm.h (disasm_option_arg_t): New typedef.
(disasm_options_and_args_t): Likewise.
(disasm_options_t): Add `arg' member, document members.
(disassembler_options_mips): New prototype.
(disassembler_options_arm, disassembler_options_powerpc)
(disassembler_options_s390): Update prototypes.
opcodes/
PR tdep/8282
* mips-dis.c (mips_option_arg_t): New enumeration.
(mips_options): New variable.
(disassembler_options_mips): New function.
(print_mips_disassembler_options): Reimplement in terms of
`disassembler_options_mips'.
* arm-dis.c (disassembler_options_arm): Adapt to using the
`disasm_options_and_args_t' structure.
* ppc-dis.c (disassembler_options_powerpc): Likewise.
* s390-dis.c (disassembler_options_s390): Likewise.
gdb/
PR tdep/8282
* disasm.h (gdb_disassembler): Add
`m_disassembler_options_holder'. member
* disasm.c (get_all_disassembler_options): New function.
(gdb_disassembler::gdb_disassembler): Use it.
(gdb_buffered_insn_length_init_dis): Likewise.
(gdb_buffered_insn_length): Adjust accordingly.
(set_disassembler_options): Handle options with arguments.
(show_disassembler_options_sfunc): Likewise. Add a leading new
line if showing options with descriptions.
(disassembler_options_completer): Adapt to using the
`disasm_options_and_args_t' structure.
* mips-tdep.c (mips_disassembler_options): New variable.
(mips_disassembler_options_o32): Likewise.
(mips_disassembler_options_n32): Likewise.
(mips_disassembler_options_n64): Likewise.
(gdb_print_insn_mips): Don't set `disassembler_options'.
(gdb_print_insn_mips_n32, gdb_print_insn_mips_n64): Remove
functions.
(mips_gdbarch_init): Always set `gdbarch_print_insn' to
`gdb_print_insn_mips'. Set `gdbarch_disassembler_options',
`gdbarch_disassembler_options_implicit' and
`gdbarch_valid_disassembler_options'.
* arm-tdep.c (_initialize_arm_tdep): Adapt to using the
`disasm_options_and_args_t' structure.
* gdbarch.sh (disassembler_options_implicit): New `gdbarch'
method.
(valid_disassembler_options): Switch from `disasm_options_t' to
the `disasm_options_and_args_t' structure.
* NEWS: Document `set disassembler-options' support for the MIPS
target.
* gdbarch.h: Regenerate.
* gdbarch.c: Regenerate.
gdb/doc/
PR tdep/8282
* gdb.texinfo (Source and Machine Code): Document `set
disassembler-options' support for the MIPS target.
gdb/testsuite/
PR tdep/8282
* gdb.arch/mips-disassembler-options.exp: New test.
* gdb.arch/mips-disassembler-options.s: New test source.
2018-07-03 00:57:21 +02:00
|
|
|
|
const disasm_options_and_args_t *
|
2017-02-28 19:32:07 +01:00
|
|
|
|
disassembler_options_arm (void)
|
|
|
|
|
|
{
|
GDB PR tdep/8282: MIPS: Wire in `set disassembler-options'
Implement MIPS target support for passing options to the disassembler,
complementing commit 65b48a81404c ("GDB: Add support for the new
set/show disassembler-options commands.").
This includes options that expect an argument, so adjust the generic
code and data structures used so as to handle such options. So as to
give backends syntax flexibility no specific delimiter has been defined
to separate options from their respective arguments, so it has to be
included as the last character of the option name. Completion code
however has not been adjusted and consequently option arguments cannot
be completed at this time.
Also the MIPS target has non-empty defaults for the options, so that ABI
names for the general-purpose registers respect our `set mips abi ...'
setting rather than always being determined from the ELF headers of the
binary file selected. Handle these defaults as implicit options, never
shown to the user and always prepended to the user-specified options, so
that the latters can override the defaults.
The resulting output for the MIPS target is as follows:
(gdb) show disassembler-options
The current disassembler options are ''
The following disassembler options are supported for use with the
'set disassembler-options <option>[,<option>...]' command:
no-aliases Use canonical instruction forms.
msa Recognize MSA instructions.
virt Recognize the virtualization ASE instructions.
xpa Recognize the eXtended Physical Address (XPA) ASE
instructions.
ginv Recognize the Global INValidate (GINV) ASE instructions.
gpr-names=ABI Print GPR names according to specified ABI.
Default: based on binary being disassembled.
fpr-names=ABI Print FPR names according to specified ABI.
Default: numeric.
cp0-names=ARCH Print CP0 register names according to specified architecture.
Default: based on binary being disassembled.
hwr-names=ARCH Print HWR names according to specified architecture.
Default: based on binary being disassembled.
reg-names=ABI Print GPR and FPR names according to specified ABI.
reg-names=ARCH Print CP0 register and HWR names according to specified
architecture.
For the options above, the following values are supported for "ABI":
numeric 32 n32 64
For the options above, the following values are supported for "ARCH":
numeric r3000 r3900 r4000 r4010 vr4100 vr4111 vr4120 r4300 r4400 r4600
r4650 r5000 vr5400 vr5500 r5900 r6000 rm7000 rm9000 r8000 r10000 r12000
r14000 r16000 mips5 mips32 mips32r2 mips32r3 mips32r5 mips32r6 mips64
mips64r2 mips64r3 mips64r5 mips64r6 interaptiv-mr2 sb1 loongson2e
loongson2f loongson3a octeon octeon+ octeon2 octeon3 xlr xlp
(gdb)
which corresponds to what `objdump --help' used to print for the MIPS
target, with minor formatting changes, most notably option argument
lists being wrapped, but also the amount of white space separating
options from the respective descriptions. The relevant part the new
code is now also used by `objdump --help', which means these formatting
changes apply to both outputs, except for argument list wrapping, which
is GDB-specific.
This also adds a separating new line between the heading and option
lists where descriptions are provided, hence:
(gdb) set architecture s390:31-bit
(gdb) show disassembler-options
The current disassembler options are ''
The following disassembler options are supported for use with the
'set disassembler-options <option>[,<option>...]' command:
esa Disassemble in ESA architecture mode
zarch Disassemble in z/Architecture mode
insnlength Print unknown instructions according to length from first two bits
(gdb)
but:
(gdb) set architecture powerpc:common
(gdb) show disassembler-options
The current disassembler options are ''
The following disassembler options are supported for use with the
'set disassembler-options <option>[,<option>...]' command:
403, 405, 440, 464, 476, 601, 603, 604, 620, 7400, 7410, 7450, 7455, 750cl,
821, 850, 860, a2, altivec, any, booke, booke32, cell, com, e200z4, e300,
e500, e500mc, e500mc64, e5500, e6500, e500x2, efs, efs2, power4, power5,
power6, power7, power8, power9, ppc, ppc32, 32, ppc64, 64, ppc64bridge,
ppcps, pwr, pwr2, pwr4, pwr5, pwr5x, pwr6, pwr7, pwr8, pwr9, pwrx, raw, spe,
spe2, titan, vle, vsx
(gdb)
Existing affected target backends have been adjusted accordingly.
This has been verified manually with:
(gdb) set architecture arm
(gdb) set architecture powerpc:common
(gdb) set architecture s390:31-bit
to cause no issues with the `show disassembler-options' and `set
disassembler-options' commands. A test case for the MIPS target has
also been provided, covering the default settings with ABI overrides as
well as disassembler option overrides.
2018-07-02 Maciej W. Rozycki <macro@mips.com>
Simon Marchi <simon.marchi@polymtl.ca>
include/
PR tdep/8282
* dis-asm.h (disasm_option_arg_t): New typedef.
(disasm_options_and_args_t): Likewise.
(disasm_options_t): Add `arg' member, document members.
(disassembler_options_mips): New prototype.
(disassembler_options_arm, disassembler_options_powerpc)
(disassembler_options_s390): Update prototypes.
opcodes/
PR tdep/8282
* mips-dis.c (mips_option_arg_t): New enumeration.
(mips_options): New variable.
(disassembler_options_mips): New function.
(print_mips_disassembler_options): Reimplement in terms of
`disassembler_options_mips'.
* arm-dis.c (disassembler_options_arm): Adapt to using the
`disasm_options_and_args_t' structure.
* ppc-dis.c (disassembler_options_powerpc): Likewise.
* s390-dis.c (disassembler_options_s390): Likewise.
gdb/
PR tdep/8282
* disasm.h (gdb_disassembler): Add
`m_disassembler_options_holder'. member
* disasm.c (get_all_disassembler_options): New function.
(gdb_disassembler::gdb_disassembler): Use it.
(gdb_buffered_insn_length_init_dis): Likewise.
(gdb_buffered_insn_length): Adjust accordingly.
(set_disassembler_options): Handle options with arguments.
(show_disassembler_options_sfunc): Likewise. Add a leading new
line if showing options with descriptions.
(disassembler_options_completer): Adapt to using the
`disasm_options_and_args_t' structure.
* mips-tdep.c (mips_disassembler_options): New variable.
(mips_disassembler_options_o32): Likewise.
(mips_disassembler_options_n32): Likewise.
(mips_disassembler_options_n64): Likewise.
(gdb_print_insn_mips): Don't set `disassembler_options'.
(gdb_print_insn_mips_n32, gdb_print_insn_mips_n64): Remove
functions.
(mips_gdbarch_init): Always set `gdbarch_print_insn' to
`gdb_print_insn_mips'. Set `gdbarch_disassembler_options',
`gdbarch_disassembler_options_implicit' and
`gdbarch_valid_disassembler_options'.
* arm-tdep.c (_initialize_arm_tdep): Adapt to using the
`disasm_options_and_args_t' structure.
* gdbarch.sh (disassembler_options_implicit): New `gdbarch'
method.
(valid_disassembler_options): Switch from `disasm_options_t' to
the `disasm_options_and_args_t' structure.
* NEWS: Document `set disassembler-options' support for the MIPS
target.
* gdbarch.h: Regenerate.
* gdbarch.c: Regenerate.
gdb/doc/
PR tdep/8282
* gdb.texinfo (Source and Machine Code): Document `set
disassembler-options' support for the MIPS target.
gdb/testsuite/
PR tdep/8282
* gdb.arch/mips-disassembler-options.exp: New test.
* gdb.arch/mips-disassembler-options.s: New test source.
2018-07-03 00:57:21 +02:00
|
|
|
|
static disasm_options_and_args_t *opts_and_args;
|
2017-02-28 19:32:07 +01:00
|
|
|
|
|
GDB PR tdep/8282: MIPS: Wire in `set disassembler-options'
Implement MIPS target support for passing options to the disassembler,
complementing commit 65b48a81404c ("GDB: Add support for the new
set/show disassembler-options commands.").
This includes options that expect an argument, so adjust the generic
code and data structures used so as to handle such options. So as to
give backends syntax flexibility no specific delimiter has been defined
to separate options from their respective arguments, so it has to be
included as the last character of the option name. Completion code
however has not been adjusted and consequently option arguments cannot
be completed at this time.
Also the MIPS target has non-empty defaults for the options, so that ABI
names for the general-purpose registers respect our `set mips abi ...'
setting rather than always being determined from the ELF headers of the
binary file selected. Handle these defaults as implicit options, never
shown to the user and always prepended to the user-specified options, so
that the latters can override the defaults.
The resulting output for the MIPS target is as follows:
(gdb) show disassembler-options
The current disassembler options are ''
The following disassembler options are supported for use with the
'set disassembler-options <option>[,<option>...]' command:
no-aliases Use canonical instruction forms.
msa Recognize MSA instructions.
virt Recognize the virtualization ASE instructions.
xpa Recognize the eXtended Physical Address (XPA) ASE
instructions.
ginv Recognize the Global INValidate (GINV) ASE instructions.
gpr-names=ABI Print GPR names according to specified ABI.
Default: based on binary being disassembled.
fpr-names=ABI Print FPR names according to specified ABI.
Default: numeric.
cp0-names=ARCH Print CP0 register names according to specified architecture.
Default: based on binary being disassembled.
hwr-names=ARCH Print HWR names according to specified architecture.
Default: based on binary being disassembled.
reg-names=ABI Print GPR and FPR names according to specified ABI.
reg-names=ARCH Print CP0 register and HWR names according to specified
architecture.
For the options above, the following values are supported for "ABI":
numeric 32 n32 64
For the options above, the following values are supported for "ARCH":
numeric r3000 r3900 r4000 r4010 vr4100 vr4111 vr4120 r4300 r4400 r4600
r4650 r5000 vr5400 vr5500 r5900 r6000 rm7000 rm9000 r8000 r10000 r12000
r14000 r16000 mips5 mips32 mips32r2 mips32r3 mips32r5 mips32r6 mips64
mips64r2 mips64r3 mips64r5 mips64r6 interaptiv-mr2 sb1 loongson2e
loongson2f loongson3a octeon octeon+ octeon2 octeon3 xlr xlp
(gdb)
which corresponds to what `objdump --help' used to print for the MIPS
target, with minor formatting changes, most notably option argument
lists being wrapped, but also the amount of white space separating
options from the respective descriptions. The relevant part the new
code is now also used by `objdump --help', which means these formatting
changes apply to both outputs, except for argument list wrapping, which
is GDB-specific.
This also adds a separating new line between the heading and option
lists where descriptions are provided, hence:
(gdb) set architecture s390:31-bit
(gdb) show disassembler-options
The current disassembler options are ''
The following disassembler options are supported for use with the
'set disassembler-options <option>[,<option>...]' command:
esa Disassemble in ESA architecture mode
zarch Disassemble in z/Architecture mode
insnlength Print unknown instructions according to length from first two bits
(gdb)
but:
(gdb) set architecture powerpc:common
(gdb) show disassembler-options
The current disassembler options are ''
The following disassembler options are supported for use with the
'set disassembler-options <option>[,<option>...]' command:
403, 405, 440, 464, 476, 601, 603, 604, 620, 7400, 7410, 7450, 7455, 750cl,
821, 850, 860, a2, altivec, any, booke, booke32, cell, com, e200z4, e300,
e500, e500mc, e500mc64, e5500, e6500, e500x2, efs, efs2, power4, power5,
power6, power7, power8, power9, ppc, ppc32, 32, ppc64, 64, ppc64bridge,
ppcps, pwr, pwr2, pwr4, pwr5, pwr5x, pwr6, pwr7, pwr8, pwr9, pwrx, raw, spe,
spe2, titan, vle, vsx
(gdb)
Existing affected target backends have been adjusted accordingly.
This has been verified manually with:
(gdb) set architecture arm
(gdb) set architecture powerpc:common
(gdb) set architecture s390:31-bit
to cause no issues with the `show disassembler-options' and `set
disassembler-options' commands. A test case for the MIPS target has
also been provided, covering the default settings with ABI overrides as
well as disassembler option overrides.
2018-07-02 Maciej W. Rozycki <macro@mips.com>
Simon Marchi <simon.marchi@polymtl.ca>
include/
PR tdep/8282
* dis-asm.h (disasm_option_arg_t): New typedef.
(disasm_options_and_args_t): Likewise.
(disasm_options_t): Add `arg' member, document members.
(disassembler_options_mips): New prototype.
(disassembler_options_arm, disassembler_options_powerpc)
(disassembler_options_s390): Update prototypes.
opcodes/
PR tdep/8282
* mips-dis.c (mips_option_arg_t): New enumeration.
(mips_options): New variable.
(disassembler_options_mips): New function.
(print_mips_disassembler_options): Reimplement in terms of
`disassembler_options_mips'.
* arm-dis.c (disassembler_options_arm): Adapt to using the
`disasm_options_and_args_t' structure.
* ppc-dis.c (disassembler_options_powerpc): Likewise.
* s390-dis.c (disassembler_options_s390): Likewise.
gdb/
PR tdep/8282
* disasm.h (gdb_disassembler): Add
`m_disassembler_options_holder'. member
* disasm.c (get_all_disassembler_options): New function.
(gdb_disassembler::gdb_disassembler): Use it.
(gdb_buffered_insn_length_init_dis): Likewise.
(gdb_buffered_insn_length): Adjust accordingly.
(set_disassembler_options): Handle options with arguments.
(show_disassembler_options_sfunc): Likewise. Add a leading new
line if showing options with descriptions.
(disassembler_options_completer): Adapt to using the
`disasm_options_and_args_t' structure.
* mips-tdep.c (mips_disassembler_options): New variable.
(mips_disassembler_options_o32): Likewise.
(mips_disassembler_options_n32): Likewise.
(mips_disassembler_options_n64): Likewise.
(gdb_print_insn_mips): Don't set `disassembler_options'.
(gdb_print_insn_mips_n32, gdb_print_insn_mips_n64): Remove
functions.
(mips_gdbarch_init): Always set `gdbarch_print_insn' to
`gdb_print_insn_mips'. Set `gdbarch_disassembler_options',
`gdbarch_disassembler_options_implicit' and
`gdbarch_valid_disassembler_options'.
* arm-tdep.c (_initialize_arm_tdep): Adapt to using the
`disasm_options_and_args_t' structure.
* gdbarch.sh (disassembler_options_implicit): New `gdbarch'
method.
(valid_disassembler_options): Switch from `disasm_options_t' to
the `disasm_options_and_args_t' structure.
* NEWS: Document `set disassembler-options' support for the MIPS
target.
* gdbarch.h: Regenerate.
* gdbarch.c: Regenerate.
gdb/doc/
PR tdep/8282
* gdb.texinfo (Source and Machine Code): Document `set
disassembler-options' support for the MIPS target.
gdb/testsuite/
PR tdep/8282
* gdb.arch/mips-disassembler-options.exp: New test.
* gdb.arch/mips-disassembler-options.s: New test source.
2018-07-03 00:57:21 +02:00
|
|
|
|
if (opts_and_args == NULL)
|
2017-02-28 19:32:07 +01:00
|
|
|
|
{
|
GDB PR tdep/8282: MIPS: Wire in `set disassembler-options'
Implement MIPS target support for passing options to the disassembler,
complementing commit 65b48a81404c ("GDB: Add support for the new
set/show disassembler-options commands.").
This includes options that expect an argument, so adjust the generic
code and data structures used so as to handle such options. So as to
give backends syntax flexibility no specific delimiter has been defined
to separate options from their respective arguments, so it has to be
included as the last character of the option name. Completion code
however has not been adjusted and consequently option arguments cannot
be completed at this time.
Also the MIPS target has non-empty defaults for the options, so that ABI
names for the general-purpose registers respect our `set mips abi ...'
setting rather than always being determined from the ELF headers of the
binary file selected. Handle these defaults as implicit options, never
shown to the user and always prepended to the user-specified options, so
that the latters can override the defaults.
The resulting output for the MIPS target is as follows:
(gdb) show disassembler-options
The current disassembler options are ''
The following disassembler options are supported for use with the
'set disassembler-options <option>[,<option>...]' command:
no-aliases Use canonical instruction forms.
msa Recognize MSA instructions.
virt Recognize the virtualization ASE instructions.
xpa Recognize the eXtended Physical Address (XPA) ASE
instructions.
ginv Recognize the Global INValidate (GINV) ASE instructions.
gpr-names=ABI Print GPR names according to specified ABI.
Default: based on binary being disassembled.
fpr-names=ABI Print FPR names according to specified ABI.
Default: numeric.
cp0-names=ARCH Print CP0 register names according to specified architecture.
Default: based on binary being disassembled.
hwr-names=ARCH Print HWR names according to specified architecture.
Default: based on binary being disassembled.
reg-names=ABI Print GPR and FPR names according to specified ABI.
reg-names=ARCH Print CP0 register and HWR names according to specified
architecture.
For the options above, the following values are supported for "ABI":
numeric 32 n32 64
For the options above, the following values are supported for "ARCH":
numeric r3000 r3900 r4000 r4010 vr4100 vr4111 vr4120 r4300 r4400 r4600
r4650 r5000 vr5400 vr5500 r5900 r6000 rm7000 rm9000 r8000 r10000 r12000
r14000 r16000 mips5 mips32 mips32r2 mips32r3 mips32r5 mips32r6 mips64
mips64r2 mips64r3 mips64r5 mips64r6 interaptiv-mr2 sb1 loongson2e
loongson2f loongson3a octeon octeon+ octeon2 octeon3 xlr xlp
(gdb)
which corresponds to what `objdump --help' used to print for the MIPS
target, with minor formatting changes, most notably option argument
lists being wrapped, but also the amount of white space separating
options from the respective descriptions. The relevant part the new
code is now also used by `objdump --help', which means these formatting
changes apply to both outputs, except for argument list wrapping, which
is GDB-specific.
This also adds a separating new line between the heading and option
lists where descriptions are provided, hence:
(gdb) set architecture s390:31-bit
(gdb) show disassembler-options
The current disassembler options are ''
The following disassembler options are supported for use with the
'set disassembler-options <option>[,<option>...]' command:
esa Disassemble in ESA architecture mode
zarch Disassemble in z/Architecture mode
insnlength Print unknown instructions according to length from first two bits
(gdb)
but:
(gdb) set architecture powerpc:common
(gdb) show disassembler-options
The current disassembler options are ''
The following disassembler options are supported for use with the
'set disassembler-options <option>[,<option>...]' command:
403, 405, 440, 464, 476, 601, 603, 604, 620, 7400, 7410, 7450, 7455, 750cl,
821, 850, 860, a2, altivec, any, booke, booke32, cell, com, e200z4, e300,
e500, e500mc, e500mc64, e5500, e6500, e500x2, efs, efs2, power4, power5,
power6, power7, power8, power9, ppc, ppc32, 32, ppc64, 64, ppc64bridge,
ppcps, pwr, pwr2, pwr4, pwr5, pwr5x, pwr6, pwr7, pwr8, pwr9, pwrx, raw, spe,
spe2, titan, vle, vsx
(gdb)
Existing affected target backends have been adjusted accordingly.
This has been verified manually with:
(gdb) set architecture arm
(gdb) set architecture powerpc:common
(gdb) set architecture s390:31-bit
to cause no issues with the `show disassembler-options' and `set
disassembler-options' commands. A test case for the MIPS target has
also been provided, covering the default settings with ABI overrides as
well as disassembler option overrides.
2018-07-02 Maciej W. Rozycki <macro@mips.com>
Simon Marchi <simon.marchi@polymtl.ca>
include/
PR tdep/8282
* dis-asm.h (disasm_option_arg_t): New typedef.
(disasm_options_and_args_t): Likewise.
(disasm_options_t): Add `arg' member, document members.
(disassembler_options_mips): New prototype.
(disassembler_options_arm, disassembler_options_powerpc)
(disassembler_options_s390): Update prototypes.
opcodes/
PR tdep/8282
* mips-dis.c (mips_option_arg_t): New enumeration.
(mips_options): New variable.
(disassembler_options_mips): New function.
(print_mips_disassembler_options): Reimplement in terms of
`disassembler_options_mips'.
* arm-dis.c (disassembler_options_arm): Adapt to using the
`disasm_options_and_args_t' structure.
* ppc-dis.c (disassembler_options_powerpc): Likewise.
* s390-dis.c (disassembler_options_s390): Likewise.
gdb/
PR tdep/8282
* disasm.h (gdb_disassembler): Add
`m_disassembler_options_holder'. member
* disasm.c (get_all_disassembler_options): New function.
(gdb_disassembler::gdb_disassembler): Use it.
(gdb_buffered_insn_length_init_dis): Likewise.
(gdb_buffered_insn_length): Adjust accordingly.
(set_disassembler_options): Handle options with arguments.
(show_disassembler_options_sfunc): Likewise. Add a leading new
line if showing options with descriptions.
(disassembler_options_completer): Adapt to using the
`disasm_options_and_args_t' structure.
* mips-tdep.c (mips_disassembler_options): New variable.
(mips_disassembler_options_o32): Likewise.
(mips_disassembler_options_n32): Likewise.
(mips_disassembler_options_n64): Likewise.
(gdb_print_insn_mips): Don't set `disassembler_options'.
(gdb_print_insn_mips_n32, gdb_print_insn_mips_n64): Remove
functions.
(mips_gdbarch_init): Always set `gdbarch_print_insn' to
`gdb_print_insn_mips'. Set `gdbarch_disassembler_options',
`gdbarch_disassembler_options_implicit' and
`gdbarch_valid_disassembler_options'.
* arm-tdep.c (_initialize_arm_tdep): Adapt to using the
`disasm_options_and_args_t' structure.
* gdbarch.sh (disassembler_options_implicit): New `gdbarch'
method.
(valid_disassembler_options): Switch from `disasm_options_t' to
the `disasm_options_and_args_t' structure.
* NEWS: Document `set disassembler-options' support for the MIPS
target.
* gdbarch.h: Regenerate.
* gdbarch.c: Regenerate.
gdb/doc/
PR tdep/8282
* gdb.texinfo (Source and Machine Code): Document `set
disassembler-options' support for the MIPS target.
gdb/testsuite/
PR tdep/8282
* gdb.arch/mips-disassembler-options.exp: New test.
* gdb.arch/mips-disassembler-options.s: New test source.
2018-07-03 00:57:21 +02:00
|
|
|
|
disasm_options_t *opts;
|
2017-02-28 19:32:07 +01:00
|
|
|
|
unsigned int i;
|
GDB PR tdep/8282: MIPS: Wire in `set disassembler-options'
Implement MIPS target support for passing options to the disassembler,
complementing commit 65b48a81404c ("GDB: Add support for the new
set/show disassembler-options commands.").
This includes options that expect an argument, so adjust the generic
code and data structures used so as to handle such options. So as to
give backends syntax flexibility no specific delimiter has been defined
to separate options from their respective arguments, so it has to be
included as the last character of the option name. Completion code
however has not been adjusted and consequently option arguments cannot
be completed at this time.
Also the MIPS target has non-empty defaults for the options, so that ABI
names for the general-purpose registers respect our `set mips abi ...'
setting rather than always being determined from the ELF headers of the
binary file selected. Handle these defaults as implicit options, never
shown to the user and always prepended to the user-specified options, so
that the latters can override the defaults.
The resulting output for the MIPS target is as follows:
(gdb) show disassembler-options
The current disassembler options are ''
The following disassembler options are supported for use with the
'set disassembler-options <option>[,<option>...]' command:
no-aliases Use canonical instruction forms.
msa Recognize MSA instructions.
virt Recognize the virtualization ASE instructions.
xpa Recognize the eXtended Physical Address (XPA) ASE
instructions.
ginv Recognize the Global INValidate (GINV) ASE instructions.
gpr-names=ABI Print GPR names according to specified ABI.
Default: based on binary being disassembled.
fpr-names=ABI Print FPR names according to specified ABI.
Default: numeric.
cp0-names=ARCH Print CP0 register names according to specified architecture.
Default: based on binary being disassembled.
hwr-names=ARCH Print HWR names according to specified architecture.
Default: based on binary being disassembled.
reg-names=ABI Print GPR and FPR names according to specified ABI.
reg-names=ARCH Print CP0 register and HWR names according to specified
architecture.
For the options above, the following values are supported for "ABI":
numeric 32 n32 64
For the options above, the following values are supported for "ARCH":
numeric r3000 r3900 r4000 r4010 vr4100 vr4111 vr4120 r4300 r4400 r4600
r4650 r5000 vr5400 vr5500 r5900 r6000 rm7000 rm9000 r8000 r10000 r12000
r14000 r16000 mips5 mips32 mips32r2 mips32r3 mips32r5 mips32r6 mips64
mips64r2 mips64r3 mips64r5 mips64r6 interaptiv-mr2 sb1 loongson2e
loongson2f loongson3a octeon octeon+ octeon2 octeon3 xlr xlp
(gdb)
which corresponds to what `objdump --help' used to print for the MIPS
target, with minor formatting changes, most notably option argument
lists being wrapped, but also the amount of white space separating
options from the respective descriptions. The relevant part the new
code is now also used by `objdump --help', which means these formatting
changes apply to both outputs, except for argument list wrapping, which
is GDB-specific.
This also adds a separating new line between the heading and option
lists where descriptions are provided, hence:
(gdb) set architecture s390:31-bit
(gdb) show disassembler-options
The current disassembler options are ''
The following disassembler options are supported for use with the
'set disassembler-options <option>[,<option>...]' command:
esa Disassemble in ESA architecture mode
zarch Disassemble in z/Architecture mode
insnlength Print unknown instructions according to length from first two bits
(gdb)
but:
(gdb) set architecture powerpc:common
(gdb) show disassembler-options
The current disassembler options are ''
The following disassembler options are supported for use with the
'set disassembler-options <option>[,<option>...]' command:
403, 405, 440, 464, 476, 601, 603, 604, 620, 7400, 7410, 7450, 7455, 750cl,
821, 850, 860, a2, altivec, any, booke, booke32, cell, com, e200z4, e300,
e500, e500mc, e500mc64, e5500, e6500, e500x2, efs, efs2, power4, power5,
power6, power7, power8, power9, ppc, ppc32, 32, ppc64, 64, ppc64bridge,
ppcps, pwr, pwr2, pwr4, pwr5, pwr5x, pwr6, pwr7, pwr8, pwr9, pwrx, raw, spe,
spe2, titan, vle, vsx
(gdb)
Existing affected target backends have been adjusted accordingly.
This has been verified manually with:
(gdb) set architecture arm
(gdb) set architecture powerpc:common
(gdb) set architecture s390:31-bit
to cause no issues with the `show disassembler-options' and `set
disassembler-options' commands. A test case for the MIPS target has
also been provided, covering the default settings with ABI overrides as
well as disassembler option overrides.
2018-07-02 Maciej W. Rozycki <macro@mips.com>
Simon Marchi <simon.marchi@polymtl.ca>
include/
PR tdep/8282
* dis-asm.h (disasm_option_arg_t): New typedef.
(disasm_options_and_args_t): Likewise.
(disasm_options_t): Add `arg' member, document members.
(disassembler_options_mips): New prototype.
(disassembler_options_arm, disassembler_options_powerpc)
(disassembler_options_s390): Update prototypes.
opcodes/
PR tdep/8282
* mips-dis.c (mips_option_arg_t): New enumeration.
(mips_options): New variable.
(disassembler_options_mips): New function.
(print_mips_disassembler_options): Reimplement in terms of
`disassembler_options_mips'.
* arm-dis.c (disassembler_options_arm): Adapt to using the
`disasm_options_and_args_t' structure.
* ppc-dis.c (disassembler_options_powerpc): Likewise.
* s390-dis.c (disassembler_options_s390): Likewise.
gdb/
PR tdep/8282
* disasm.h (gdb_disassembler): Add
`m_disassembler_options_holder'. member
* disasm.c (get_all_disassembler_options): New function.
(gdb_disassembler::gdb_disassembler): Use it.
(gdb_buffered_insn_length_init_dis): Likewise.
(gdb_buffered_insn_length): Adjust accordingly.
(set_disassembler_options): Handle options with arguments.
(show_disassembler_options_sfunc): Likewise. Add a leading new
line if showing options with descriptions.
(disassembler_options_completer): Adapt to using the
`disasm_options_and_args_t' structure.
* mips-tdep.c (mips_disassembler_options): New variable.
(mips_disassembler_options_o32): Likewise.
(mips_disassembler_options_n32): Likewise.
(mips_disassembler_options_n64): Likewise.
(gdb_print_insn_mips): Don't set `disassembler_options'.
(gdb_print_insn_mips_n32, gdb_print_insn_mips_n64): Remove
functions.
(mips_gdbarch_init): Always set `gdbarch_print_insn' to
`gdb_print_insn_mips'. Set `gdbarch_disassembler_options',
`gdbarch_disassembler_options_implicit' and
`gdbarch_valid_disassembler_options'.
* arm-tdep.c (_initialize_arm_tdep): Adapt to using the
`disasm_options_and_args_t' structure.
* gdbarch.sh (disassembler_options_implicit): New `gdbarch'
method.
(valid_disassembler_options): Switch from `disasm_options_t' to
the `disasm_options_and_args_t' structure.
* NEWS: Document `set disassembler-options' support for the MIPS
target.
* gdbarch.h: Regenerate.
* gdbarch.c: Regenerate.
gdb/doc/
PR tdep/8282
* gdb.texinfo (Source and Machine Code): Document `set
disassembler-options' support for the MIPS target.
gdb/testsuite/
PR tdep/8282
* gdb.arch/mips-disassembler-options.exp: New test.
* gdb.arch/mips-disassembler-options.s: New test source.
2018-07-03 00:57:21 +02:00
|
|
|
|
|
|
|
|
|
|
opts_and_args = XNEW (disasm_options_and_args_t);
|
|
|
|
|
|
opts_and_args->args = NULL;
|
|
|
|
|
|
|
|
|
|
|
|
opts = &opts_and_args->options;
|
2017-02-28 19:32:07 +01:00
|
|
|
|
opts->name = XNEWVEC (const char *, NUM_ARM_OPTIONS + 1);
|
|
|
|
|
|
opts->description = XNEWVEC (const char *, NUM_ARM_OPTIONS + 1);
|
GDB PR tdep/8282: MIPS: Wire in `set disassembler-options'
Implement MIPS target support for passing options to the disassembler,
complementing commit 65b48a81404c ("GDB: Add support for the new
set/show disassembler-options commands.").
This includes options that expect an argument, so adjust the generic
code and data structures used so as to handle such options. So as to
give backends syntax flexibility no specific delimiter has been defined
to separate options from their respective arguments, so it has to be
included as the last character of the option name. Completion code
however has not been adjusted and consequently option arguments cannot
be completed at this time.
Also the MIPS target has non-empty defaults for the options, so that ABI
names for the general-purpose registers respect our `set mips abi ...'
setting rather than always being determined from the ELF headers of the
binary file selected. Handle these defaults as implicit options, never
shown to the user and always prepended to the user-specified options, so
that the latters can override the defaults.
The resulting output for the MIPS target is as follows:
(gdb) show disassembler-options
The current disassembler options are ''
The following disassembler options are supported for use with the
'set disassembler-options <option>[,<option>...]' command:
no-aliases Use canonical instruction forms.
msa Recognize MSA instructions.
virt Recognize the virtualization ASE instructions.
xpa Recognize the eXtended Physical Address (XPA) ASE
instructions.
ginv Recognize the Global INValidate (GINV) ASE instructions.
gpr-names=ABI Print GPR names according to specified ABI.
Default: based on binary being disassembled.
fpr-names=ABI Print FPR names according to specified ABI.
Default: numeric.
cp0-names=ARCH Print CP0 register names according to specified architecture.
Default: based on binary being disassembled.
hwr-names=ARCH Print HWR names according to specified architecture.
Default: based on binary being disassembled.
reg-names=ABI Print GPR and FPR names according to specified ABI.
reg-names=ARCH Print CP0 register and HWR names according to specified
architecture.
For the options above, the following values are supported for "ABI":
numeric 32 n32 64
For the options above, the following values are supported for "ARCH":
numeric r3000 r3900 r4000 r4010 vr4100 vr4111 vr4120 r4300 r4400 r4600
r4650 r5000 vr5400 vr5500 r5900 r6000 rm7000 rm9000 r8000 r10000 r12000
r14000 r16000 mips5 mips32 mips32r2 mips32r3 mips32r5 mips32r6 mips64
mips64r2 mips64r3 mips64r5 mips64r6 interaptiv-mr2 sb1 loongson2e
loongson2f loongson3a octeon octeon+ octeon2 octeon3 xlr xlp
(gdb)
which corresponds to what `objdump --help' used to print for the MIPS
target, with minor formatting changes, most notably option argument
lists being wrapped, but also the amount of white space separating
options from the respective descriptions. The relevant part the new
code is now also used by `objdump --help', which means these formatting
changes apply to both outputs, except for argument list wrapping, which
is GDB-specific.
This also adds a separating new line between the heading and option
lists where descriptions are provided, hence:
(gdb) set architecture s390:31-bit
(gdb) show disassembler-options
The current disassembler options are ''
The following disassembler options are supported for use with the
'set disassembler-options <option>[,<option>...]' command:
esa Disassemble in ESA architecture mode
zarch Disassemble in z/Architecture mode
insnlength Print unknown instructions according to length from first two bits
(gdb)
but:
(gdb) set architecture powerpc:common
(gdb) show disassembler-options
The current disassembler options are ''
The following disassembler options are supported for use with the
'set disassembler-options <option>[,<option>...]' command:
403, 405, 440, 464, 476, 601, 603, 604, 620, 7400, 7410, 7450, 7455, 750cl,
821, 850, 860, a2, altivec, any, booke, booke32, cell, com, e200z4, e300,
e500, e500mc, e500mc64, e5500, e6500, e500x2, efs, efs2, power4, power5,
power6, power7, power8, power9, ppc, ppc32, 32, ppc64, 64, ppc64bridge,
ppcps, pwr, pwr2, pwr4, pwr5, pwr5x, pwr6, pwr7, pwr8, pwr9, pwrx, raw, spe,
spe2, titan, vle, vsx
(gdb)
Existing affected target backends have been adjusted accordingly.
This has been verified manually with:
(gdb) set architecture arm
(gdb) set architecture powerpc:common
(gdb) set architecture s390:31-bit
to cause no issues with the `show disassembler-options' and `set
disassembler-options' commands. A test case for the MIPS target has
also been provided, covering the default settings with ABI overrides as
well as disassembler option overrides.
2018-07-02 Maciej W. Rozycki <macro@mips.com>
Simon Marchi <simon.marchi@polymtl.ca>
include/
PR tdep/8282
* dis-asm.h (disasm_option_arg_t): New typedef.
(disasm_options_and_args_t): Likewise.
(disasm_options_t): Add `arg' member, document members.
(disassembler_options_mips): New prototype.
(disassembler_options_arm, disassembler_options_powerpc)
(disassembler_options_s390): Update prototypes.
opcodes/
PR tdep/8282
* mips-dis.c (mips_option_arg_t): New enumeration.
(mips_options): New variable.
(disassembler_options_mips): New function.
(print_mips_disassembler_options): Reimplement in terms of
`disassembler_options_mips'.
* arm-dis.c (disassembler_options_arm): Adapt to using the
`disasm_options_and_args_t' structure.
* ppc-dis.c (disassembler_options_powerpc): Likewise.
* s390-dis.c (disassembler_options_s390): Likewise.
gdb/
PR tdep/8282
* disasm.h (gdb_disassembler): Add
`m_disassembler_options_holder'. member
* disasm.c (get_all_disassembler_options): New function.
(gdb_disassembler::gdb_disassembler): Use it.
(gdb_buffered_insn_length_init_dis): Likewise.
(gdb_buffered_insn_length): Adjust accordingly.
(set_disassembler_options): Handle options with arguments.
(show_disassembler_options_sfunc): Likewise. Add a leading new
line if showing options with descriptions.
(disassembler_options_completer): Adapt to using the
`disasm_options_and_args_t' structure.
* mips-tdep.c (mips_disassembler_options): New variable.
(mips_disassembler_options_o32): Likewise.
(mips_disassembler_options_n32): Likewise.
(mips_disassembler_options_n64): Likewise.
(gdb_print_insn_mips): Don't set `disassembler_options'.
(gdb_print_insn_mips_n32, gdb_print_insn_mips_n64): Remove
functions.
(mips_gdbarch_init): Always set `gdbarch_print_insn' to
`gdb_print_insn_mips'. Set `gdbarch_disassembler_options',
`gdbarch_disassembler_options_implicit' and
`gdbarch_valid_disassembler_options'.
* arm-tdep.c (_initialize_arm_tdep): Adapt to using the
`disasm_options_and_args_t' structure.
* gdbarch.sh (disassembler_options_implicit): New `gdbarch'
method.
(valid_disassembler_options): Switch from `disasm_options_t' to
the `disasm_options_and_args_t' structure.
* NEWS: Document `set disassembler-options' support for the MIPS
target.
* gdbarch.h: Regenerate.
* gdbarch.c: Regenerate.
gdb/doc/
PR tdep/8282
* gdb.texinfo (Source and Machine Code): Document `set
disassembler-options' support for the MIPS target.
gdb/testsuite/
PR tdep/8282
* gdb.arch/mips-disassembler-options.exp: New test.
* gdb.arch/mips-disassembler-options.s: New test source.
2018-07-03 00:57:21 +02:00
|
|
|
|
opts->arg = NULL;
|
2017-02-28 19:32:07 +01:00
|
|
|
|
for (i = 0; i < NUM_ARM_OPTIONS; i++)
|
|
|
|
|
|
{
|
|
|
|
|
|
opts->name[i] = regnames[i].name;
|
|
|
|
|
|
if (regnames[i].description != NULL)
|
|
|
|
|
|
opts->description[i] = _(regnames[i].description);
|
|
|
|
|
|
else
|
|
|
|
|
|
opts->description[i] = NULL;
|
|
|
|
|
|
}
|
|
|
|
|
|
/* The array we return must be NULL terminated. */
|
|
|
|
|
|
opts->name[i] = NULL;
|
|
|
|
|
|
opts->description[i] = NULL;
|
|
|
|
|
|
}
|
|
|
|
|
|
|
GDB PR tdep/8282: MIPS: Wire in `set disassembler-options'
Implement MIPS target support for passing options to the disassembler,
complementing commit 65b48a81404c ("GDB: Add support for the new
set/show disassembler-options commands.").
This includes options that expect an argument, so adjust the generic
code and data structures used so as to handle such options. So as to
give backends syntax flexibility no specific delimiter has been defined
to separate options from their respective arguments, so it has to be
included as the last character of the option name. Completion code
however has not been adjusted and consequently option arguments cannot
be completed at this time.
Also the MIPS target has non-empty defaults for the options, so that ABI
names for the general-purpose registers respect our `set mips abi ...'
setting rather than always being determined from the ELF headers of the
binary file selected. Handle these defaults as implicit options, never
shown to the user and always prepended to the user-specified options, so
that the latters can override the defaults.
The resulting output for the MIPS target is as follows:
(gdb) show disassembler-options
The current disassembler options are ''
The following disassembler options are supported for use with the
'set disassembler-options <option>[,<option>...]' command:
no-aliases Use canonical instruction forms.
msa Recognize MSA instructions.
virt Recognize the virtualization ASE instructions.
xpa Recognize the eXtended Physical Address (XPA) ASE
instructions.
ginv Recognize the Global INValidate (GINV) ASE instructions.
gpr-names=ABI Print GPR names according to specified ABI.
Default: based on binary being disassembled.
fpr-names=ABI Print FPR names according to specified ABI.
Default: numeric.
cp0-names=ARCH Print CP0 register names according to specified architecture.
Default: based on binary being disassembled.
hwr-names=ARCH Print HWR names according to specified architecture.
Default: based on binary being disassembled.
reg-names=ABI Print GPR and FPR names according to specified ABI.
reg-names=ARCH Print CP0 register and HWR names according to specified
architecture.
For the options above, the following values are supported for "ABI":
numeric 32 n32 64
For the options above, the following values are supported for "ARCH":
numeric r3000 r3900 r4000 r4010 vr4100 vr4111 vr4120 r4300 r4400 r4600
r4650 r5000 vr5400 vr5500 r5900 r6000 rm7000 rm9000 r8000 r10000 r12000
r14000 r16000 mips5 mips32 mips32r2 mips32r3 mips32r5 mips32r6 mips64
mips64r2 mips64r3 mips64r5 mips64r6 interaptiv-mr2 sb1 loongson2e
loongson2f loongson3a octeon octeon+ octeon2 octeon3 xlr xlp
(gdb)
which corresponds to what `objdump --help' used to print for the MIPS
target, with minor formatting changes, most notably option argument
lists being wrapped, but also the amount of white space separating
options from the respective descriptions. The relevant part the new
code is now also used by `objdump --help', which means these formatting
changes apply to both outputs, except for argument list wrapping, which
is GDB-specific.
This also adds a separating new line between the heading and option
lists where descriptions are provided, hence:
(gdb) set architecture s390:31-bit
(gdb) show disassembler-options
The current disassembler options are ''
The following disassembler options are supported for use with the
'set disassembler-options <option>[,<option>...]' command:
esa Disassemble in ESA architecture mode
zarch Disassemble in z/Architecture mode
insnlength Print unknown instructions according to length from first two bits
(gdb)
but:
(gdb) set architecture powerpc:common
(gdb) show disassembler-options
The current disassembler options are ''
The following disassembler options are supported for use with the
'set disassembler-options <option>[,<option>...]' command:
403, 405, 440, 464, 476, 601, 603, 604, 620, 7400, 7410, 7450, 7455, 750cl,
821, 850, 860, a2, altivec, any, booke, booke32, cell, com, e200z4, e300,
e500, e500mc, e500mc64, e5500, e6500, e500x2, efs, efs2, power4, power5,
power6, power7, power8, power9, ppc, ppc32, 32, ppc64, 64, ppc64bridge,
ppcps, pwr, pwr2, pwr4, pwr5, pwr5x, pwr6, pwr7, pwr8, pwr9, pwrx, raw, spe,
spe2, titan, vle, vsx
(gdb)
Existing affected target backends have been adjusted accordingly.
This has been verified manually with:
(gdb) set architecture arm
(gdb) set architecture powerpc:common
(gdb) set architecture s390:31-bit
to cause no issues with the `show disassembler-options' and `set
disassembler-options' commands. A test case for the MIPS target has
also been provided, covering the default settings with ABI overrides as
well as disassembler option overrides.
2018-07-02 Maciej W. Rozycki <macro@mips.com>
Simon Marchi <simon.marchi@polymtl.ca>
include/
PR tdep/8282
* dis-asm.h (disasm_option_arg_t): New typedef.
(disasm_options_and_args_t): Likewise.
(disasm_options_t): Add `arg' member, document members.
(disassembler_options_mips): New prototype.
(disassembler_options_arm, disassembler_options_powerpc)
(disassembler_options_s390): Update prototypes.
opcodes/
PR tdep/8282
* mips-dis.c (mips_option_arg_t): New enumeration.
(mips_options): New variable.
(disassembler_options_mips): New function.
(print_mips_disassembler_options): Reimplement in terms of
`disassembler_options_mips'.
* arm-dis.c (disassembler_options_arm): Adapt to using the
`disasm_options_and_args_t' structure.
* ppc-dis.c (disassembler_options_powerpc): Likewise.
* s390-dis.c (disassembler_options_s390): Likewise.
gdb/
PR tdep/8282
* disasm.h (gdb_disassembler): Add
`m_disassembler_options_holder'. member
* disasm.c (get_all_disassembler_options): New function.
(gdb_disassembler::gdb_disassembler): Use it.
(gdb_buffered_insn_length_init_dis): Likewise.
(gdb_buffered_insn_length): Adjust accordingly.
(set_disassembler_options): Handle options with arguments.
(show_disassembler_options_sfunc): Likewise. Add a leading new
line if showing options with descriptions.
(disassembler_options_completer): Adapt to using the
`disasm_options_and_args_t' structure.
* mips-tdep.c (mips_disassembler_options): New variable.
(mips_disassembler_options_o32): Likewise.
(mips_disassembler_options_n32): Likewise.
(mips_disassembler_options_n64): Likewise.
(gdb_print_insn_mips): Don't set `disassembler_options'.
(gdb_print_insn_mips_n32, gdb_print_insn_mips_n64): Remove
functions.
(mips_gdbarch_init): Always set `gdbarch_print_insn' to
`gdb_print_insn_mips'. Set `gdbarch_disassembler_options',
`gdbarch_disassembler_options_implicit' and
`gdbarch_valid_disassembler_options'.
* arm-tdep.c (_initialize_arm_tdep): Adapt to using the
`disasm_options_and_args_t' structure.
* gdbarch.sh (disassembler_options_implicit): New `gdbarch'
method.
(valid_disassembler_options): Switch from `disasm_options_t' to
the `disasm_options_and_args_t' structure.
* NEWS: Document `set disassembler-options' support for the MIPS
target.
* gdbarch.h: Regenerate.
* gdbarch.c: Regenerate.
gdb/doc/
PR tdep/8282
* gdb.texinfo (Source and Machine Code): Document `set
disassembler-options' support for the MIPS target.
gdb/testsuite/
PR tdep/8282
* gdb.arch/mips-disassembler-options.exp: New test.
* gdb.arch/mips-disassembler-options.s: New test source.
2018-07-03 00:57:21 +02:00
|
|
|
|
return opts_and_args;
|
2017-02-28 19:32:07 +01:00
|
|
|
|
}
|
|
|
|
|
|
|
2000-01-27 23:17:12 +01:00
|
|
|
|
void
|
2005-06-08 00:16:52 +02:00
|
|
|
|
print_arm_disassembler_options (FILE *stream)
|
2000-01-27 23:17:12 +01:00
|
|
|
|
{
|
2017-02-28 19:32:07 +01:00
|
|
|
|
unsigned int i, max_len = 0;
|
2000-01-27 23:17:12 +01:00
|
|
|
|
fprintf (stream, _("\n\
|
|
|
|
|
|
The following ARM specific disassembler options are supported for use with\n\
|
|
|
|
|
|
the -M switch:\n"));
|
2002-11-30 09:39:46 +01:00
|
|
|
|
|
2017-02-28 19:32:07 +01:00
|
|
|
|
for (i = 0; i < NUM_ARM_OPTIONS; i++)
|
|
|
|
|
|
{
|
|
|
|
|
|
unsigned int len = strlen (regnames[i].name);
|
|
|
|
|
|
if (max_len < len)
|
|
|
|
|
|
max_len = len;
|
|
|
|
|
|
}
|
2000-01-27 23:17:12 +01:00
|
|
|
|
|
2017-02-28 19:32:07 +01:00
|
|
|
|
for (i = 0, max_len++; i < NUM_ARM_OPTIONS; i++)
|
|
|
|
|
|
fprintf (stream, " %s%*c %s\n",
|
|
|
|
|
|
regnames[i].name,
|
|
|
|
|
|
(int)(max_len - strlen (regnames[i].name)), ' ',
|
|
|
|
|
|
_(regnames[i].description));
|
1999-05-03 09:29:11 +02:00
|
|
|
|
}
|
