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Implement ARC NPS-400 Ultra Ip and Miscellaneous instructions. opcodes * arc-nps400-tbl.h: Add Ultra Ip and Miscellaneous instructions format. * arc-opc.c: Add defines. e.g. F_NJ, F_NM , F_NO_T, F_NPS_SR, F_NPS_M, F_NPS_CORE, F_NPS_ALL. (insert_nps_misc_imm_offset): New function. (extract_nps_misc imm_offset): New function. (arc_num_flag_operands): Add F_NJ, F_NM, F_NO_T. (arc_flag_special_cases): Add F_NJ, F_NM, F_NO_T. include * opcode/arc.h (insn_class_t): Add ULTRAIP and MISC class. gas * testsuite/gas/arc/nps400-12.s: New file. * testsuite/gas/arc/nps400-12.d: New file.
2017-03-27 12:14:30 +02:00
2017-03-27 Rinat Zelig <rinat@mellanox.com>
* testsuite/gas/arc/nps400-12.s: New file.
* testsuite/gas/arc/nps400-12.d: New file.
[GAS/ARM] Fix selected_cpu with default CPU and -mcpu When GAS is compiled with DEFAULT_CPU set and then run with a -mcpu or -march option, selected_cpu will be set to the default CPU. This means the -mcpu is ignored which is surprising behavior. This commit instead sets selected_cpu from the value passed to -mcpu/-march. 2017-03-24 Thomas preud'homme <thomas.preudhomme@arm.com> gas/ * config/tc-arm.: (md_begin): Set selected_cpu from *mcpu_cpu_opt when CPU_DEFAULT is defined.
2017-03-24 14:22:16 +01:00
2017-03-24 Thomas preud'homme <thomas.preudhomme@arm.com>
* config/tc-arm.: (md_begin): Set selected_cpu from *mcpu_cpu_opt when
CPU_DEFAULT is defined.
Sanitize RISC-V GAS help text, documentation It looks like I missed the GAS help text when going through all the documentation last time, so it printed some of the old-format (never upstream) arguments. I fixed this, and when I went to check doc/ I noticed it was missing the '-fpic'/'-fno-pic' options.
2017-03-21 16:36:44 +01:00
2017-03-21 Palmer Dabbbelt <palmer@dabbelt.com>
* config/tc-riscv.c (md_show_usage): Remode defuct -m32, -m64,
-msoft-float, -mhard-float, -mno-rvc, and -mrvc options; and don't
print an invalid default ISA string.
* doc/c-riscv.texi (OPTIONS): Add -fpic and -fno-pic options.
gas: xtensa: make trampolines relaxation work with jumps in slots other than 0 add_jump_to_trampoline assumes that jump instruction is in slot 0, when it's in other slot that results in fixup that references NULL symbol, which results in segfault later in xtensa_make_cached_fixup. Search for the non-NULL symbol in the tc_frag_data.slot_symbols and check that there's exactly one such slot. xtensa_relax_frag for RELAX_TRAMPOLINE reassigns fixup from the original instruction with jump to generated jump in the trampoline frag, but does not fix its fx_r_type or fx_size. That results in "undecodable fix" or "fixup not contained within frag" error messages during relaxation. Fix both these fields. gas/ 2017-03-22 Max Filippov <jcmvbkbc@gmail.com> * config/tc-xtensa.c (xtensa_relax_frag): Change fx_size of the reassigned fixup to size of jump instruction (3) and fx_r_type to BFD_RELOC_XTENSA_SLOT0_OP, as there's only one slot. (add_jump_to_trampoline): Search origfrag->tc_frag_data.slot_symbols for the slot with non-NULL symbol and use that slot instead of slot 0.
2017-03-22 18:19:14 +01:00
2017-03-22 Max Filippov <jcmvbkbc@gmail.com>
* config/tc-xtensa.c (xtensa_relax_frag): Change fx_size of the
reassigned fixup to size of jump instruction (3) and fx_r_type
to BFD_RELOC_XTENSA_SLOT0_OP, as there's only one slot.
(add_jump_to_trampoline): Search
origfrag->tc_frag_data.slot_symbols for the slot with non-NULL
symbol and use that slot instead of slot 0.
S/390: Remove vx2 facility flag This patch removes the vx2 facility flag. It will not be used by GCC and was a misnomer anyway. Committed to mainline and 2.28 branch. include/ChangeLog: 2017-03-21 Andreas Krebbel <krebbel@linux.vnet.ibm.com> * opcode/s390.h (S390_INSTR_FLAG_VX2): Remove. (S390_INSTR_FLAG_FACILITY_MASK): Adjust value. gas/ChangeLog: 2017-03-21 Andreas Krebbel <krebbel@linux.vnet.ibm.com> * config/tc-s390.c (s390_parse_cpu): Remove S390_INSTR_FLAG_VX2 from cpu_table. Remove vx2, and novx2 from cpu_flags. opcodes/ChangeLog: 2017-03-21 Andreas Krebbel <krebbel@linux.vnet.ibm.com> * s390-mkopc.c (main): Remove vx2 check. * s390-opc.txt: Remove vx2 instruction flags.
2017-03-21 14:21:02 +01:00
2017-03-21 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
* config/tc-s390.c (s390_parse_cpu): Remove S390_INSTR_FLAG_VX2
from cpu_table. Remove vx2, and novx2 from cpu_flags.
arc/nps400: Add cp16/cp32 instructions to opcodes library Instructions for loading or storing 16/32B data from one address type to another. gas/ChangeLog * testsuite/gas/arc/nps400-11.s: New file. * testsuite/gas/arc/nps400-11.d: New file. include/ChangeLog * opcode/arc.h (insn_class_t): Add DMA class. opcodes/ChangeLog * arc-nps400-tbl.h: Add cp32/cp16 instructions format. * arc-opc.c: Add F_NPS_NA, NPS_DMA_IMM_ENTRY, NPS_DMA_IMM_OFFSET. (insert_nps_imm_offset): New function. (extract_nps_imm_offset): New function. (insert_nps_imm_entry): New function. (extract_nps_imm_entry): New function.
2017-03-21 12:37:33 +01:00
2017-03-21 Rinat Zelig <rinat@mellanox.com>
* testsuite/gas/arc/nps400-11.s: New file.
* testsuite/gas/arc/nps400-11.d: New file.
Update descriptions of the .2byte, .4byte and .8byte directives. * doc/as.texinfo (2byte): Note that if no expressions are present the directive does nothing. Emphasize that the output is unaligned, and that this can have an effect on the relocations generated. (4byte): Simplify description. Refer back to the 2byte description. (8byte): Likewise.
2017-03-20 17:57:07 +01:00
2017-03-20 Nick Clifton <nickc@redhat.com>
* doc/as.texinfo (2byte): Note that if no expressions are present
the directive does nothing. Emphasize that the output is
unaligned, and that this can have an effect on the relocations
generated.
(4byte): Simplify description. Refer back to the 2byte
description.
(8byte): Likewise.
[arm] Document missing -mfpu entries. Nick pointed out that I hadn't documented the new -mfpu option neon-vfpv3 and mentioned that some others were missing. Having looked through the list only one (neon-fp16) really should be documented; the other two entries in the real table should not be documented as they are aliases kept for legacy compatibility reasons. This patch adds the missing entries and notes in the main table that the other two entries should not be documented. I've also fixed a small spelling error in the accompanying text. * config/tc-arm.c (arm_fpus): Note entires that should not be documented. * doc/c-arm.texi (-mfpu): Add missing FPU entries for neon-vfpv3 and neon-fp16. Fix spelling error.
2017-03-20 15:56:22 +01:00
2017-03-20 Richard Earnshaw <rearnsha@arm.com>
* config/tc-arm.c (arm_fpus): Note entires that should not be
documented.
* doc/c-arm.texi (-mfpu): Add missing FPU entries for neon-vfpv3 and
neon-fp16. Fix spelling error.
[arm] Add neon-vfp3 as an alias for neon to -mfpu. GCC recently added neon-vfpv3 as an alias for neon in -mfpu. This patch adds a similar alias in GAS. * config/tc-arm.c (arm_fpus): Add neon-vfpv3 as an alias for neon.
2017-03-20 11:03:15 +01:00
2017-03-20 Richard Earnshaw <rearnsha@arm.com>
* config/tc-arm.c (arm_fpus): Add neon-vfpv3 as an alias for neon.
gas/arc: Limit special handling of t/nt flag to ARCv2 In a later commit I'll be adding a new version of the ".nt" flag for an ARC700 extension (NPS400) which does not require this same special handling. In this commit I have restricted the special flag handling to only apply if we are assembling for ARCv2. This is a restructuring commit, and there should be no user visible changes after this commit. gas/ChangeLog: * config/tc-arc.c (assemble_insn): Only handle ".t" and ".nt" specially for ARCv2.
2017-03-16 11:05:22 +01:00
2017-03-16 Rinat Zelig <rinat@mellanox.com>
* config/tc-arc.c (assemble_insn): Only handle ".t" and ".nt"
specially for ARCv2.
RISC-V: Fix assembler for c.li, c.andi and c.addiw - They can accept 0 in imm field 2017-03-14 Kito Cheng <kito.cheng@gmail.com> * riscv-opc.c (riscv_opcodes> <c.li>: Use the 'o' immediate encoding. <c.andi>: Likewise. <c.addiw> Likewise.
2017-03-07 11:15:02 +01:00
2017-03-14 Kito Cheng <kito.cheng@gmail.com>
* config/tc-riscv.c (validate_riscv_insn): Add 'o' RVC immediate
encoding format, which can accept 0-valued immediates.
(riscv_ip): Likewise.
Fix building riscv targets with gcc v6.3.1 * config/tc-riscv.c (riscv_pre_output_hook): Fix compile time warning about discarding a const qualifier.
2017-03-15 10:19:42 +01:00
2017-03-15 Nick Clifton <nickc@redhat.com>
* config/tc-riscv.c (riscv_pre_output_hook): Fix compile time
warning about discarding a const qualifier.
RISC-V: Define DWARF2_USE_FIXED_ADVANCE_PC. gas/ChangeLog 2017-03-02 Kuan-Lin Chen <rufus@andestech.com> * config/tc-riscv.h (HWARD2_USE_FIXED_ADVANCE_PC): New define.
2017-03-02 07:54:32 +01:00
2017-03-02 Kuan-Lin Chen <rufus@andestech.com>
* config/tc-riscv.h (HWARD2_USE_FIXED_ADVANCE_PC): New define.
RISC-V: Fix DW_CFA_advance_loc relocation. gas/ChangeLog: 2017-03-02 Kuan-Lin Chen <rufus@andestech.com> * config/tc-riscv.c (md_apply_fix): Set fx_frag and fx_next->fx_frag for CFA_advance_loc relocations.
2017-02-10 07:58:52 +01:00
2017-03-02 Kuan-Lin Chen <rufus@andestech.com>
* config/tc-riscv.c (md_apply_fix): Set fx_frag and
fx_next->fx_frag for CFA_advance_loc relocations.
RISC-V: Fix the offset of CFA relocation. gas/ChangeLog: 2017-03-02 Kuan-Lin Chen <rufus@andestech.com> * config/tc-riscv.c (md_apply_fix): Compute the correct offsets for CFA relocations.
2017-02-02 08:27:18 +01:00
2017-03-02 Kuan-Lin Chen <rufus@andestech.com>
* config/tc-riscv.c (md_apply_fix): Compute the correct offsets
for CFA relocations.
Rename R_AARCH64_TLSDESC_LD64_LO12_NC to R_AARCH64_TLSDESC_LD64_LO12 and R_AARCH64_TLSDESC_ADD_LO12_NC to R_AARCH64_TLSDESC_ADD_LO12. PR binutils/21202 include * elf/aarch64.h (R_AARCH64_TLSDESC_LD64_LO12_NC): Rename to R_AARCH64_TLSDESC_LD64_LO12. (R_AARCH64_TLSDESC_ADD_LO12_NC): Rename to R_AARCH64_TLSDESC_ADD_LO12_NC. bfd * reloc.c (BFD_RELOC_AARCH64_TLSDESC_LD64_LO12_NC): Rename to BFD_RELOC_AARCH64_TLSDESC_LD64_LO12. (BFD_RELOC_AARCH64_TLSDESC_ADD_LO12_NC): Rename to BFD_RELOC_AARCH64_TLSDESC_ADD_LO12. * bfd-in2.h: Regenerate. * libbfd.h: Regenerate. * elfnn-aarch64.c (IS_AARCH64_TLS_RELAX_RELOC): Update reloc names. (IS_AARCH64_TLSDESC_RELOC): Likewise. (elfNN_aarch64_howto_table): Likewise. (aarch64_tls_transition_without_check): Likewise. (aarch64_reloc_got_type): Likewise. (elfNN_aarch64_final_link_relocate): Likewise. (elfNN_aarch64_tls_relax): Likewise. (elfNN_aarch64_relocate_section): Likewise. (elfNN_aarch64_gc_sweep_hook): Likewise. (elfNN_aarch64_check_relocs): Likewise. * elfxx-aarch64.c (_bfd_aarch64_elf_put_addend): Likewise. (_bfd_aarch64_elf_resolve_relocation): Likewise. gas * config/tc-aarch64.c (reloc_table): Rename BFD_RELOC_AARCH64_TLSDESC_LD64_LO12_NC to BFD_RELOC_AARCH64_TLSDESC_LD64_LO12. Rname BFD_RELOC_AARCH64_TLSDESC_ADD_LO12_NC to BFD_RELOC_AARCH64_TLSDESC_ADD_LO12. (md_apply_fix): Likewise. (aarch64_force_relocation): Likewise. * testsuite/gas/aarch64/tls.d: Update regexp. ld * testsuite/ld-aarch64/ifunc-5r-local.d: Update regexp.
2017-03-13 10:58:04 +01:00
2017-03-13 Nick Clifton <nickc@redhat.com>
PR binutils/21202
* config/tc-aarch64.c (reloc_table): Rename
BFD_RELOC_AARCH64_TLSDESC_LD64_LO12_NC to
BFD_RELOC_AARCH64_TLSDESC_LD64_LO12. Rname
BFD_RELOC_AARCH64_TLSDESC_ADD_LO12_NC to
BFD_RELOC_AARCH64_TLSDESC_ADD_LO12.
(md_apply_fix): Likewise.
(aarch64_force_relocation): Likewise.
* testsuite/gas/aarch64/tls.d: Update regexp.
Document that the .2byte and .4byte directives warn about overlarge values. * doc/as.texinfo (2byte): Tidy up wording. Add note that overlarge values will produce a warning message and be trunacted. (4byte): Likewise.
2017-03-10 16:42:04 +01:00
2017-03-10 Tobin C. Harding <me@tobin.cc>
Nick Clifton <nickc@redhat.com>
* doc/as.texinfo (2byte): Tidy up wording. Add note that
overlarge values will produce a warning message and be trunacted.
(4byte): Likewise.
X86: Add pseudo prefixes to control encoding Many x86 instructions have more than one encodings. Assembler picks the default one, usually the shortest one. Although the ".s", ".d8" and ".d32" suffixes can be used to swap register operands or specify displacement size, they aren't very flexible. This patch adds pseudo prefixes, {xxx}, to control instruction encoding. The available pseudo prefixes are {disp8}, {disp32}, {load}, {store}, {vex2}, {vex3} and {evex}. Pseudo prefixes are preferred over the ".s", ".d8" and ".d32" suffixes, which are deprecated. gas/ * config/tc-i386.c (_i386_insn): Add dir_encoding and vec_encoding. Remove swap_operand and need_vrex. (extra_symbol_chars): Add '}'. (md_begin): Mark '}' with LEX_BEGIN_NAME. Allow '}' in mnemonic. (build_vex_prefix): Don't use 2-byte VEX encoding with {vex3}. Check dir_encoding and load. (parse_insn): Check pseudo prefixes. Set dir_encoding. (VEX_check_operands): Likewise. (match_template): Check dir_encoding and load. (parse_real_register): Set vec_encoding instead of need_vrex. (parse_register): Likewise. * doc/c-i386.texi: Document {disp8}, {disp32}, {load}, {store}, {vex2}, {vex3} and {evex}. Remove ".s", ".d8" and ".d32" * testsuite/gas/i386/i386.exp: Run pseudos and x86-64-pseudos. * testsuite/gas/i386/pseudos.d: New file. * testsuite/gas/i386/pseudos.s: Likewise. * testsuite/gas/i386/x86-64-pseudos.d: Likewise. * testsuite/gas/i386/x86-64-pseudos.s: Likewise. opcodes/ * i386-gen.c (opcode_modifiers): Replace S with Load. * i386-opc.h (S): Removed. (Load): New. (i386_opcode_modifier): Replace s with load. * i386-opc.tbl: Add {disp8}, {disp32}, {swap}, {vex2}, {vex3} and {evex}. Replace S with Load. * i386-tbl.h: Regenerated.
2017-03-09 18:58:46 +01:00
2017-03-09 H.J. Lu <hongjiu.lu@intel.com>
* config/tc-i386.c (_i386_insn): Add dir_encoding and
vec_encoding. Remove swap_operand and need_vrex.
(extra_symbol_chars): Add '}'.
(md_begin): Mark '}' with LEX_BEGIN_NAME. Allow '}' in
mnemonic.
(build_vex_prefix): Don't use 2-byte VEX encoding with
{vex3}. Check dir_encoding and load.
(parse_insn): Check pseudo prefixes. Set dir_encoding.
(VEX_check_operands): Likewise.
(match_template): Check dir_encoding and load.
(parse_real_register): Set vec_encoding instead of need_vrex.
(parse_register): Likewise.
* doc/c-i386.texi: Document {disp8}, {disp32}, {load}, {store},
{vex2}, {vex3} and {evex}. Remove ".s", ".d8" and ".d32"
* testsuite/gas/i386/i386.exp: Run pseudos and x86-64-pseudos.
* testsuite/gas/i386/pseudos.d: New file.
* testsuite/gas/i386/pseudos.s: Likewise.
* testsuite/gas/i386/x86-64-pseudos.d: Likewise.
* testsuite/gas/i386/x86-64-pseudos.s: Likewise.
Update -maltivec and -mvsx options to only enable their oldest instructions. Currently, the -maltivec and -mvsx GAS options enable *all* of the altivec and vsx instructions respecitively that have ever been added. This is in constract to GCC's -maltivec and -mvsx options, which only enable the oldest (ie, first) set of altivec and vsx instructions. This patch changes GAS to mimic GCC's behaviour with respect to -maltivec and -mvsx and it solves a problem with trying to assemble the lxvx instruction which is different between POWER8 and POWER9. opcodes/ * ppc-dis.c (ppc_opts) <altivec>: Do not use PPC_OPCODE_ALTIVEC2; <vsx>: Do not use PPC_OPCODE_VSX3; gas/ * testsuite/gas/ppc/altivec2.d (as): Use the -mpower8 option. (objdump): Use the -Mpower8 option.
2017-03-09 03:49:03 +01:00
2017-03-08 Peter Bergner <bergner@vnet.ibm.com>
* testsuite/gas/ppc/altivec2.d (as): Use the -mpower8 option.
(objdump): Use the -Mpower8 option.
Add support for the new 'lnia' extended mnemonic. opcodes/ * ppc-opc.c (powerpc_opcodes) <lnia>: New extended mnemonic. gas/ * testsuite/gas/ppc/power9.d <lnia> New test. * testsuite/gas/ppc/power9.s: Likewise.
2017-03-08 21:00:42 +01:00
2017-03-08 Peter Bergner <bergner@vnet.ibm.com>
* testsuite/gas/ppc/power9.d <lnia> New test.
* testsuite/gas/ppc/power9.s: Likewise.
Correct @section placement for makeinfo 4.13 * doc/as.texinfo (2byte, 4byte, 8byte): Correct @section placement.
2017-03-07 10:09:32 +01:00
2017-03-07 Alan Modra <amodra@gmail.com>
* doc/as.texinfo (2byte, 4byte, 8byte): Correct @section placement.
Document .Nbyte assembler directives * doc/as.texinfo (2byte, 4byte, 8byte): Document. * doc/c-arm.texi (2byte, 4byte, 8byte): Omit if ELF.
2017-03-07 07:16:36 +01:00
2017-03-07 Tobin C. Harding <me@tobin.cc>
Alan Modra <amodra@gmail.com>
* doc/as.texinfo (2byte, 4byte, 8byte): Document.
* doc/c-arm.texi (2byte, 4byte, 8byte): Omit if ELF.
Add support for Intel CET instructions Support Intel Control-flow Enforcement Technology (CET) instructions: https://software.intel.com/sites/default/files/managed/4d/2a/control-flow-enforcement-technology-preview.pdf gas/ * config/tc-i386.c (cpu_arch): Add .cet. * doc/c-i386.texi: Document cet. * testsuite/gas/i386/cet-intel.d: New file. * testsuite/gas/i386/cet.d: Likewise. * testsuite/gas/i386/cet.s: Likewise. * testsuite/gas/i386/x86-64-cet-intel.d: Likewise. * testsuite/gas/i386/x86-64-cet.d: Likewise. * testsuite/gas/i386/x86-64-cet.s: Likewise. * testsuite/gas/i386/i386.exp: Run Intel CET tests. opcodes/ * i386-dis.c (REG_0F1E_MOD_3): New enum. (MOD_0F1E_PREFIX_1): Likewise. (MOD_0F38F5_PREFIX_2): Likewise. (MOD_0F38F6_PREFIX_0): Likewise. (RM_0F1E_MOD_3_REG_7): Likewise. (PREFIX_MOD_0_0F01_REG_5): Likewise. (PREFIX_MOD_3_0F01_REG_5_RM_1): Likewise. (PREFIX_MOD_3_0F01_REG_5_RM_2): Likewise. (PREFIX_0F1E): Likewise. (PREFIX_MOD_0_0FAE_REG_5): Likewise. (PREFIX_0F38F5): Likewise. (dis386_twobyte): Use PREFIX_0F1E. (reg_table): Add REG_0F1E_MOD_3. (prefix_table): Add PREFIX_MOD_0_0F01_REG_5, PREFIX_MOD_3_0F01_REG_5_RM_1, PREFIX_MOD_3_0F01_REG_5_RM_2, PREFIX_0F1E, PREFIX_MOD_0_0FAE_REG_5 and PREFIX_0F38F5. Update PREFIX_0FAE_REG_6 and PREFIX_0F38F6. (three_byte_table): Use PREFIX_0F38F5. (mod_table): Use PREFIX_MOD_0_0F01_REG_5, PREFIX_MOD_0_0FAE_REG_5. Add MOD_0F1E_PREFIX_1, MOD_0F38F5_PREFIX_2, MOD_0F38F6_PREFIX_0. (rm_table): Add MOD_0F38F5_PREFIX_2, MOD_0F38F6_PREFIX_0, RM_0F1E_MOD_3_REG_7. Use PREFIX_MOD_3_0F01_REG_5_RM_1 and PREFIX_MOD_3_0F01_REG_5_RM_2. * i386-gen.c (cpu_flag_init): Add CPU_CET_FLAGS. (cpu_flags): Add CpuCET. * i386-opc.h (CpuCET): New enum. (CpuUnused): Commented out. (i386_cpu_flags): Add cpucet. * i386-opc.tbl: Add Intel CET instructions. * i386-init.h: Regenerated. * i386-tbl.h: Likewise.
2017-03-07 00:26:37 +01:00
2017-03-06 H.J. Lu <hongjiu.lu@intel.com>
* config/tc-i386.c (cpu_arch): Add .cet.
* doc/c-i386.texi: Document cet.
* testsuite/gas/i386/cet-intel.d: New file.
* testsuite/gas/i386/cet.d: Likewise.
* testsuite/gas/i386/cet.s: Likewise.
* testsuite/gas/i386/x86-64-cet-intel.d: Likewise.
* testsuite/gas/i386/x86-64-cet.d: Likewise.
* testsuite/gas/i386/x86-64-cet.s: Likewise.
* testsuite/gas/i386/i386.exp: Run Intel CET tests.
Update x86-64-mpx-inval-2 test for COFF Assembler displays upper case hex numbers and we need to force a good alignment to avoid matching NOPs at the end. * testsuite/gas/i386/x86-64-mpx-inval-2.s: Force a good alignment. * testsuite/gas/i386/x86-64-mpx-inval-2.l: Expect [0-9A-F]+.
2017-03-07 00:00:52 +01:00
2017-03-06 H.J. Lu <hongjiu.lu@intel.com>
* testsuite/gas/i386/x86-64-mpx-inval-2.s: Force a good alignment.
* testsuite/gas/i386/x86-64-mpx-inval-2.l: Expect [0-9A-F]+.
dw2gencfi.c DWARF2_FDE_RELOC_SIZE Add asserts that reloc size matches encoding size, and tidy. * dw2gencfi.c (encoding_size): Return unsigned int. (emit_expr_encoded): Assert size matches reloc bitsize. (output_fde): Use unsigned for offset_size and addr_size. Set addr_size earlier and use in place of constant 4 and uses of DWARF2_FDE_RELOC_SIZE. Assert it matches reloc bitsize.
2017-03-05 13:55:16 +01:00
2017-03-06 Alan Modra <amodra@gmail.com>
* dw2gencfi.c (encoding_size): Return unsigned int.
(emit_expr_encoded): Assert size matches reloc bitsize.
(output_fde): Use unsigned for offset_size and addr_size. Set
addr_size earlier and use in place of constant 4 and uses of
DWARF2_FDE_RELOC_SIZE. Assert it matches reloc bitsize.
gas/dw2gencfi.c formatting * dw2gencfi.c: Wrap overlong lines. Add parens for emacs auto reformat. Formatting and whitespace fixes.
2017-03-05 13:25:29 +01:00
2017-03-06 Alan Modra <amodra@gmail.com>
* dw2gencfi.c: Wrap overlong lines. Add parens for emacs
auto reformat. Formatting and whitespace fixes.
gas: Emit name, comp_dir and producer strings in .debug_str. Putting the name, comp_dir and producer strings in the .debug_str section makes it possible to share them across CUs. This saves a small amount of space (about ~20K on a glibc libc.so.6 build with debuginfo). And makes it easier for tools like rpm debugedit to adjust the source paths when generating separate debuginfo files. gas/ * dwarf2dbg.c (out_debug_abbrev): Use DW_FORM_strp instead of DW_FORM_string for DW_AT_name, DW_AT_comp_dir and DW_AT_producer. (out_debug_info): Accept symbols to name, comp_dir and producer in the .debug_str section and emit those offsets not full strings. (out_debug_str): New function that outputs the strings for name, comp_dir and producer in .debug_str and generates symbols to those strings. (out_debug_line): Create a .debug_str section if necessary and call out_debug_str before calling out_debug_info. * testsuite/gas/aarch64/dwarf.d: Add extra section symbol to expected output.
2017-03-05 23:37:54 +01:00
2017-03-05 Mark Wielaard <mark@klomp.org>
* dwarf2dbg.c (out_debug_abbrev): Use DW_FORM_strp instead of
DW_FORM_string for DW_AT_name, DW_AT_comp_dir and DW_AT_producer.
(out_debug_info): Accept symbols to name, comp_dir and producer in
the .debug_str section and emit those offsets not full strings.
(out_debug_str): New function that outputs the strings for name,
comp_dir and producer in .debug_str and generates symbols to those
strings.
(out_debug_line): Create a .debug_str section if necessary and call
out_debug_str before calling out_debug_info.
* testsuite/gas/aarch64/dwarf.d: Add extra section symbol to expected
output.
GAS: Fix bogus "attempt to move .org backwards" relaxation errors Fix a commit 6afe8e98a664 ("internal error for backwards .org"), <https://www.sourceware.org/ml/binutils/2008-06/msg00212.html>, GAS regression that caused legitimate code to fail assembly with an "attempt to move .org backwards" error. For example with the `mips-linux' target we get: $ cat org.s .set mips16 la $2, foo .org 0x1000 .align 2 foo: .half 0 $ as -o org.o org.s org.s: Assembler messages: org.s:3: Error: attempt to move .org backwards $ where the location pointer is obviously not moved backwards with `.org'. The cause is positive `stretch' in relaxation due to a PC-relative ADDIU instruction (produced from the LA macro used) getting expanded from 2 to 4 bytes as `foo' is noticed to be out of range for the short encoding. This in turn triggers logic in `relax_segment' which concludes in the processing of an `rs_org' frag produced that the location pointer is moved backwards while in fact only the amount to space forward to the location requested has shrunk, resulting in a negative growth of the frag. Correct the bad logic then and instead verify that the fixed part of an `rs_org' frag has not overrun the location requested, as per the comment already included with the error message: /* Growth may be negative, but variable part of frag cannot have fewer than 0 chars. That is, we can't .org backwards. */ which accurately describes the regression scenario. Move the comment ahead the conditional noted, for clarity. Add generic and MIPS test cases for the `.org' pseudo-op, including the test case discussed though not integrated with the offending commit in particular, adjusted to work across all targets. gas/ * write.c (relax_segment) <rs_org>: Only bail out if the fixed part of the frag has overrun the location requested. * testsuite/gas/all/org-1.d: New test. * testsuite/gas/all/org-2.d: New test. * testsuite/gas/all/org-3.d: New test. * testsuite/gas/all/org-4.d: New test. * testsuite/gas/all/org-5.d: New test. * testsuite/gas/all/org-6.d: New test. * testsuite/gas/all/org-1.l: New stderr output. * testsuite/gas/all/org-2.l: New stderr output. * testsuite/gas/all/org-3.l: New stderr output. * testsuite/gas/all/org-1.s: New test source. * testsuite/gas/all/org-2.s: New test source. * testsuite/gas/all/org-3.s: New test source. * testsuite/gas/all/org-4.s: New test source. * testsuite/gas/all/org-5.s: New test source. * testsuite/gas/all/org-6.s: New test source. * testsuite/gas/all/gas.exp: Run the new tests. * testsuite/gas/mips/org-1.d: New test. * testsuite/gas/mips/org-2.d: New test. * testsuite/gas/mips/org-3.d: New test. * testsuite/gas/mips/org-4.d: New test. * testsuite/gas/mips/org-5.d: New test. * testsuite/gas/mips/org-6.d: New test. * testsuite/gas/mips/org-7.d: New test. * testsuite/gas/mips/org-8.d: New test. * testsuite/gas/mips/org-9.d: New test. * testsuite/gas/mips/org-10.d: New test. * testsuite/gas/mips/org-11.d: New test. * testsuite/gas/mips/org-12.d: New test. * testsuite/gas/mips/org-1.l: New stderr output. * testsuite/gas/mips/org-4.l: New stderr output. * testsuite/gas/mips/org-5.l: New stderr output. * testsuite/gas/mips/org-6.l: New stderr output. * testsuite/gas/mips/org-10.l: New stderr output. * testsuite/gas/mips/org-1.s: New test source. * testsuite/gas/mips/org-2.s: New test source. * testsuite/gas/mips/org-3.s: New test source. * testsuite/gas/mips/org-4.s: New test source. * testsuite/gas/mips/org-5.s: New test source. * testsuite/gas/mips/org-6.s: New test source. * testsuite/gas/mips/org-7.s: New test source. * testsuite/gas/mips/org-8.s: New test source. * testsuite/gas/mips/org-9.s: New test source. * testsuite/gas/mips/org-10.s: New test source. * testsuite/gas/mips/org-11.s: New test source. * testsuite/gas/mips/org-12.s: New test source. * testsuite/gas/mips/mips.exp: Run the new tests.
2017-03-02 02:24:15 +01:00
2017-03-02 Maciej W. Rozycki <macro@imgtec.com>
* write.c (relax_segment) <rs_org>: Only bail out if the fixed
part of the frag has overrun the location requested.
* testsuite/gas/all/org-1.d: New test.
* testsuite/gas/all/org-2.d: New test.
* testsuite/gas/all/org-3.d: New test.
* testsuite/gas/all/org-4.d: New test.
* testsuite/gas/all/org-5.d: New test.
* testsuite/gas/all/org-6.d: New test.
* testsuite/gas/all/org-1.l: New stderr output.
* testsuite/gas/all/org-2.l: New stderr output.
* testsuite/gas/all/org-3.l: New stderr output.
* testsuite/gas/all/org-1.s: New test source.
* testsuite/gas/all/org-2.s: New test source.
* testsuite/gas/all/org-3.s: New test source.
* testsuite/gas/all/org-4.s: New test source.
* testsuite/gas/all/org-5.s: New test source.
* testsuite/gas/all/org-6.s: New test source.
* testsuite/gas/all/gas.exp: Run the new tests.
* testsuite/gas/mips/org-1.d: New test.
* testsuite/gas/mips/org-2.d: New test.
* testsuite/gas/mips/org-3.d: New test.
* testsuite/gas/mips/org-4.d: New test.
* testsuite/gas/mips/org-5.d: New test.
* testsuite/gas/mips/org-6.d: New test.
* testsuite/gas/mips/org-7.d: New test.
* testsuite/gas/mips/org-8.d: New test.
* testsuite/gas/mips/org-9.d: New test.
* testsuite/gas/mips/org-10.d: New test.
* testsuite/gas/mips/org-11.d: New test.
* testsuite/gas/mips/org-12.d: New test.
* testsuite/gas/mips/org-1.l: New stderr output.
* testsuite/gas/mips/org-4.l: New stderr output.
* testsuite/gas/mips/org-5.l: New stderr output.
* testsuite/gas/mips/org-6.l: New stderr output.
* testsuite/gas/mips/org-10.l: New stderr output.
* testsuite/gas/mips/org-1.s: New test source.
* testsuite/gas/mips/org-2.s: New test source.
* testsuite/gas/mips/org-3.s: New test source.
* testsuite/gas/mips/org-4.s: New test source.
* testsuite/gas/mips/org-5.s: New test source.
* testsuite/gas/mips/org-6.s: New test source.
* testsuite/gas/mips/org-7.s: New test source.
* testsuite/gas/mips/org-8.s: New test source.
* testsuite/gas/mips/org-9.s: New test source.
* testsuite/gas/mips/org-10.s: New test source.
* testsuite/gas/mips/org-11.s: New test source.
* testsuite/gas/mips/org-12.s: New test source.
* testsuite/gas/mips/mips.exp: Run the new tests.
[AArch64] Document +rcpc weak release consistency extension gas/ * doc/c-aarch64.texi (AArch64 Extensions): Document rcpc.
2017-03-01 15:51:13 +01:00
2017-03-01 Szabolcs Nagy <szabolcs.nagy@arm.com>
* doc/c-aarch64.texi (AArch64 Extensions): Document rcpc.
x86: fix handling of 64-bit operand size VPCMPESTR{I,M} Just like REX.W affects operand size of the implicit rAX/rDX inputs to PCMPESTR{I,M}, VEX.W does for VPCMPESTR{I,M}. Allow Q or L suffixes on the instructions. Similarly the disassembler needs to be adjusted to no longer require VEX.W to be zero for the instructions to be valid, and to emit proper suffixes. Note, however, that this doesn't address the problem of there being no way to control (at least) {,E}VEX.W for 32- or 16-bit code. Nor does it address the problem of the many WIG instructions not getting properly disassembled when VEX.W=1.
2017-02-28 10:53:35 +01:00
2017-02-28 Jan Beulich <jbeulich@suse.com>
* testsuite/gas/i386/x86-64-avx.s: Add suffixed variants of
VPCMPESTR{I,M}.
* testsuite/gas/i386/x86-64-sse2avx.s: Likewise.
* testsuite/gas/i386/x86-64-sse4_2.s: Add suffixed variants
of PCMPESTR{I,M}.
* testsuite/gas/i386/ilp32/x86-64-avx-intel.d: Likewise.
* testsuite/gas/i386/ilp32/x86-64-avx.d: Likewise.
* testsuite/gas/i386/ilp32/x86-64-sse2avx.d: Likewise.
* testsuite/gas/i386/ilp32/x86-64-sse4_2-intel.d: Likewise.
* testsuite/gas/i386/ilp32/x86-64-sse4_2.d: Likewise.
* testsuite/gas/i386/x86-64-avx-intel.d: Likewise.
* testsuite/gas/i386/x86-64-avx.d: Likewise.
* testsuite/gas/i386/x86-64-sse2avx.d: Likewise.
* testsuite/gas/i386/x86-64-sse4_2-intel.d: Likewise.
* testsuite/gas/i386/x86-64-sse4_2.d: Likewise.
Nios2 dynobj handling fixes A number of places in elf32-nios.c created dynamic sections but didn't set the hash table dynobj. That meant we could have duplicate dynamic sections connected to a number of bfds, so size_dynamic_sections didn't properly discard or allocate contents. Also, the entire set of dynamic sections was created in check_relocs on seeing GOT relocs, when only .got related sections are needed, probably done to hide segfaults later in finish_dynamic_sections. The patch fixes these issues and makes the assembler emit errors when nios2 lacks the necessary pc-relative relocs for subtraction expressions, rather than silently generating bad code. eg. ld-elf/merge. I've also tidied uses of elf32_nios2_hash_table and elf_hash_table. bfd/ PR 20995 * elf32-nios2.c (nios2_elf32_relocate_section): Use htab rather than elf32_nios2_hash_table or elf_hash_table. (create_got_section): Likewise. (nios2_elf32_finish_dynamic_symbol): Likewise. (nios2_elf32_adjust_dynamic_symbol): Likewise. (nios2_elf32_size_dynamic_sections): Likewise. (nios2_elf32_check_relocs): Delete dynobj, sgot, and srelgot vars. Use htab equivalents directly instead. Don't create all dynamic sections on needing just the GOT. Use a goto rather than a fall-through with reloc test. Ensure htab->dynobj is set when making dynamic sreloc section. (nios2_elf32_finish_dynamic_sections): Delete dynobj, use htab equivalent directly instead. Don't segfault on looking for .dynamic when dynamic sections have not been created. Don't segfault on .got.plt being discarded. (nios2_elf32_size_dynamic_sections): Delete plt and got vars. Don't set "relocs" on .rela.plt. Do handle .sbss. Delete fixme and another not so relevant comment. (nios2_elf_add_symbol_hook): Delete dynobj var. If not already set, set hash table dynobj on creating .sbss. gas/ * config/tc-nios2.h (TC_FORCE_RELOCATION_SUB_LOCAL): Define. ld/ * testsuite/ld-elf/merge.d: xfail for nios.
2017-02-28 01:08:51 +01:00
2017-02-28 Alan Modra <amodra@gmail.com>
* config/tc-nios2.h (TC_FORCE_RELOCATION_SUB_LOCAL): Define.
PowerPC addpcis fix This came up because I was looking at ld/tmpdir/addpcis.o and noticed the odd addends on REL16DX_HA. They ought to both be -4. The error crept in due REL16DX_HA howto being pc-relative (as indeed it should be), and code at gas/write.c:1001 after this comment /* Make it pc-relative. If the back-end code has not selected a pc-relative reloc, cancel the adjustment we do later on all pc-relative relocs. */ *not* cancelling the pc-relative adjustment. So I've made a dummy non-relative split reloc so that the generic code handles this, rather than attempting to add hacks later in md_apply_fix which would not be very robust. Having the new internal reloc also makes it easy to support addpcis rx,sym@ha as an equivalent to addpcis rx,(sym-0f)@ha 0: The patch also fixes overflow checking, which must test whether the addi will overflow too since @l relocs don't have any overflow check. Lastly, since I was poking at md_apply_fix, I arranged to have the generic gas/write.c code emit errors for subtraction expressions where we lack reloc support. include/ * elf/ppc64.h (R_PPC64_16DX_HA): New. Expand fake reloc comment. * elf/ppc.h (R_PPC_16DX_HA): Likewise. bfd/ * reloc.c (BFD_RELOC_PPC_16DX_HA): New. * elf64-ppc.c (ppc64_elf_howto_raw <R_PPC64_16DX_HA>): New howto. (ppc64_elf_reloc_type_lookup): Translate new bfd reloc. (ppc64_elf_ha_reloc): Correct overflow test on REL16DX_HA. (ppc64_elf_relocate_section): Likewise. * elf32-ppc.c (ppc_elf_howto_raw <R_PPC_16DX_HA>): New howto. (ppc_elf_reloc_type_lookup): Translate new bfd reloc. (ppc_elf_check_relocs): Handle R_PPC_16DX_HA to pacify gcc. * libbfd.h: Regenerate. * bfd-in2.h: Regenerate. gas/ * config/tc-ppc.c (md_assemble): Use BFD_RELOC_PPC_16DX_HA for addpcis. (md_apply_fix): Remove fx_subsy check. Move code converting to pcrel reloc earlier and handle BFD_RELOC_PPC_16DX_HA. Remove code emiiting errors on seeing fx_pcrel set on unexpected relocs, as that is done now by the generic code via.. * config/tc-ppc.h (TC_FORCE_RELOCATION_SUB_LOCAL): ..this. Define. (TC_VALIDATE_FIX_SUB): Define. ld/ * testsuite/ld-powerpc/addpcis.d: Define ext1 and ext2 at limits of addpcis range.
2017-02-27 23:02:36 +01:00
2017-02-28 Alan Modra <amodra@gmail.com>
* config/tc-ppc.c (md_assemble): Use BFD_RELOC_PPC_16DX_HA for addpcis.
(md_apply_fix): Remove fx_subsy check. Move code converting to
pcrel reloc earlier and handle BFD_RELOC_PPC_16DX_HA. Remove code
emiiting errors on seeing fx_pcrel set on unexpected relocs, as
that is done now by the generic code via..
* config/tc-ppc.h (TC_FORCE_RELOCATION_SUB_LOCAL): ..this. Define.
(TC_VALIDATE_FIX_SUB): Define.
MIPS/BFD: Also handle `jalr $0, $25' with R_MIPS_JALR Interpret the `jalr $0, $25' instruction encoding with an R_MIPS_JALR relocation attached as an alias to `jr $25' and convert the jump to an equivalent branch where possible, consequently covering the MIPSr6 architecture for the purpose of this optimization too. bfd/ * elfxx-mips.c (mips_elf_perform_relocation): Also handle the `jalr $0, $25' instruction encoding. gas/ * testsuite/gas/mips/jalr4.s: Add `jalr $0, $25' instructions. * testsuite/gas/mips/jalr4.d: Adjust accordingly. Remove MIPSr6 encoding patterns. * testsuite/gas/mips/jalr4-n64.d: Likewise. * testsuite/gas/mips/mipsr6@jalr4.d: New test. * testsuite/gas/mips/mipsr6@jalr4-n32.d: New test. * testsuite/gas/mips/mipsr6@jalr4-n64.d: New test. ld/ * testsuite/ld-mips-elf/jalr4.dd: Adjust for `jalr $0, $25' instructions. * testsuite/ld-mips-elf/jalr4-r6.dd: New test. * testsuite/ld-mips-elf/mips-elf.exp: Run the new test.
2017-02-28 01:14:08 +01:00
2017-02-28 Maciej W. Rozycki <macro@imgtec.com>
* testsuite/gas/mips/jalr4.s: Add `jalr $0, $25' instructions.
* testsuite/gas/mips/jalr4.d: Adjust accordingly. Remove MIPSr6
encoding patterns.
* testsuite/gas/mips/jalr4-n64.d: Likewise.
* testsuite/gas/mips/mipsr6@jalr4.d: New test.
* testsuite/gas/mips/mipsr6@jalr4-n32.d: New test.
* testsuite/gas/mips/mipsr6@jalr4-n64.d: New test.
Testsuite fixes for hppa64-hpux HPUX has a different .comm syntax, and anything in the first column is a label. gas/ * testsuite/gas/elf/strtab.s: Don't put directives on first column or continuation with labels not in first column. ld/ * testsuite/ld-elf/elf.exp: Xfail pr20995 tests on hppa64-hpux. Set up HPUX defsym. Run pr14170 tests and build symbol3 objects, defining HPUX where necessary. Define HPUX for implib tests. * testsuite/ld-elf/comm-data4.d: Run for hpux. * testsuite/ld-elf/endsym.d: Likewise. * testsuite/ld-elf/linkoncerdiff.d: Likewise. * testsuite/ld-elf/comm-data4.s: Add alternate .comm when HPUX. * testsuite/ld-elf/comm-data5.s: Likewise. * testsuite/ld-elf/endsym.s: Likewise. * testsuite/ld-elf/pr14170c.s: Likewise. * testsuite/ld-elf/symbol3.s: Likewise. * testsuite/ld-elf/implib.s: Likewise. Don't start directives in first column. * testsuite/ld-elf/linkoncerdiff2.s: Don't use numeric labels. * testsuite/ld-elf/warn3.d: Run for hpux. * testsuite/ld-scripts/rgn-at10.d: Xfail for hpux. * testsuite/ld-scripts/rgn-at11.d: Likewise. * testsuite/ld-scripts/size-2.d: Remove xfail for hpux.
2017-02-24 14:32:27 +01:00
2017-02-25 Alan Modra <amodra@gmail.com>
* testsuite/gas/elf/strtab.s: Don't put directives on first
column or continuation with labels not in first column.
[AArch64] Additional SVE instructions This patch supports some additions to the SVE architecture prior to its public release. include/ * opcode/aarch64.h (AARCH64_OPND_SVE_ADDR_RI_S4x16) (AARCH64_OPND_SVE_IMM_ROT1, AARCH64_OPND_SVE_IMM_ROT2) (AARCH64_OPND_SVE_Zm3_INDEX, AARCH64_OPND_SVE_Zm3_22_INDEX) (AARCH64_OPND_SVE_Zm4_INDEX): New aarch64_opnds. opcodes/ * aarch64-tbl.h (OP_SVE_HMH, OP_SVE_VMU_HSD, OP_SVE_VMVU_HSD) (OP_SVE_VMVV_HSD, OP_SVE_VMVVU_HSD, OP_SVE_VM_HSD, OP_SVE_VUVV_HSD) (OP_SVE_VUV_HSD, OP_SVE_VU_HSD, OP_SVE_VVVU_H, OP_SVE_VVVU_S) (OP_SVE_VVVU_HSD, OP_SVE_VVV_D, OP_SVE_VVV_D_H, OP_SVE_VVV_H) (OP_SVE_VVV_HSD, OP_SVE_VVV_S, OP_SVE_VVV_S_B, OP_SVE_VVV_SD_BH) (OP_SVE_VV_BHSDQ, OP_SVE_VV_HSD, OP_SVE_VZVV_HSD, OP_SVE_VZV_HSD) (OP_SVE_V_HSD): New macros. (OP_SVE_VMU_SD, OP_SVE_VMVU_SD, OP_SVE_VM_SD, OP_SVE_VUVV_SD) (OP_SVE_VU_SD, OP_SVE_VVVU_SD, OP_SVE_VVV_SD, OP_SVE_VZVV_SD) (OP_SVE_VZV_SD, OP_SVE_V_SD): Delete. (aarch64_opcode_table): Add new SVE instructions. (aarch64_opcode_table): Use imm_rotate{1,2} instead of imm_rotate for rotation operands. Add new SVE operands. * aarch64-asm.h (ins_sve_addr_ri_s4): New inserter. (ins_sve_quad_index): Likewise. (ins_imm_rotate): Split into... (ins_imm_rotate1, ins_imm_rotate2): ...these two inserters. * aarch64-asm.c (aarch64_ins_imm_rotate): Split into... (aarch64_ins_imm_rotate1, aarch64_ins_imm_rotate2): ...these two functions. (aarch64_ins_sve_addr_ri_s4): New function. (aarch64_ins_sve_quad_index): Likewise. (do_misc_encoding): Handle "MOV Zn.Q, Qm". * aarch64-asm-2.c: Regenerate. * aarch64-dis.h (ext_sve_addr_ri_s4): New extractor. (ext_sve_quad_index): Likewise. (ext_imm_rotate): Split into... (ext_imm_rotate1, ext_imm_rotate2): ...these two extractors. * aarch64-dis.c (aarch64_ext_imm_rotate): Split into... (aarch64_ext_imm_rotate1, aarch64_ext_imm_rotate2): ...these two functions. (aarch64_ext_sve_addr_ri_s4): New function. (aarch64_ext_sve_quad_index): Likewise. (aarch64_ext_sve_index): Allow quad indices. (do_misc_decoding): Likewise. * aarch64-dis-2.c: Regenerate. * aarch64-opc.h (FLD_SVE_i3h, FLD_SVE_rot1, FLD_SVE_rot2): New aarch64_field_kinds. (OPD_F_OD_MASK): Widen by one bit. (OPD_F_NO_ZR): Bump accordingly. (get_operand_field_width): New function. * aarch64-opc.c (fields): Add new SVE fields. (operand_general_constraint_met_p): Handle new SVE operands. (aarch64_print_operand): Likewise. * aarch64-opc-2.c: Regenerate. gas/ * doc/c-aarch64.texi: Document that sve implies fp16, simd and compnum. * config/tc-aarch64.c (parse_vector_type_for_operand): Allow .q to be used with SVE registers. (parse_operands): Handle new SVE operands. (aarch64_features): Make "sve" require F16 rather than FP. Also require COMPNUM. * testsuite/gas/aarch64/sve.s: Add tests for new instructions. Include compnum tests. * testsuite/gas/aarch64/sve.d: Update accordingly. * testsuite/gas/aarch64/sve-invalid.s: Add tests for new instructions. * testsuite/gas/aarch64/sve-invalid.l: Update accordingly. Also update expected output for new FMOV and MOV alternatives.
2017-02-24 19:29:00 +01:00
2017-02-24 Richard Sandiford <richard.sandiford@arm.com>
* doc/c-aarch64.texi: Document that sve implies fp16, simd and compnum.
* config/tc-aarch64.c (parse_vector_type_for_operand): Allow .q
to be used with SVE registers.
(parse_operands): Handle new SVE operands.
(aarch64_features): Make "sve" require F16 rather than FP. Also
require COMPNUM.
* testsuite/gas/aarch64/sve.s: Add tests for new instructions.
Include compnum tests.
* testsuite/gas/aarch64/sve.d: Update accordingly.
* testsuite/gas/aarch64/sve-invalid.s: Add tests for new instructions.
* testsuite/gas/aarch64/sve-invalid.l: Update accordingly. Also
update expected output for new FMOV and MOV alternatives.
[AArch64] Add a "compnum" feature This patch adds a named "compnum" feature for the ARMv8.3-A FCADD and FCMLA extensions. include/ * opcode/aarch64.h (AARCH64_FEATURE_COMPNUM): New macro. (AARCH64_ARCH_V8_3): Include AARCH64_FEATURE_COMPNUM. opcodes/ * aarch64-tbl.h (aarch64_feature_simd_v8_3): Replace with... (aarch64_feature_compnum): ...this. (SIMD_V8_3): Replace with... (COMPNUM): ...this. (CNUM_INSN): New macro. (aarch64_opcode_table): Use it for the complex number instructions. gas/ * doc/c-aarch64.texi: Add a "compnum" entry. * config/tc-aarch64.c (aarch64_features): Likewise, * testsuite/gas/aarch64/advsimd-compnum.s: New test. * testsuite/gas/aarch64/advsimd-compnum.d: Likewise.
2017-02-24 19:27:26 +01:00
2017-02-24 Richard Sandiford <richard.sandiford@arm.com>
* doc/c-aarch64.texi: Add a "compnum" entry.
* config/tc-aarch64.c (aarch64_features): Likewise,
* testsuite/gas/aarch64/advsimd-compnum.s: New test.
* testsuite/gas/aarch64/advsimd-compnum.d: Likewise.
x86: also correctly support TEST opcode aliases Opcodes F6/1 and F7/1 are aliases of F6/0 and F7/0 in all modes. This complements commit 8b89fe14b5 ("X86: Decode opcode 0x82 as opcode 0x80 in 32-bit mode"), just that here 64-bit mode is also covered.
2017-02-24 10:04:26 +01:00
2017-02-24 Jan Beulich <jbeulich@suse.com>
* testsuite/gas/i386/opcode.s: Add alternative TEST forms.
* testsuite/gas/i386/x86-64-opcode.s: Likewise.
* testsuite/gas/i386/opcode.d: Adjust accordingly.
* testsuite/gas/i386/opcode-intel.d: Likewise.
* testsuite/gas/i386/x86-64-opcode.d: Likewise.
* testsuite/gas/i386/ilp32/x86-64-opcode.d: Likewise.
gas: test cases for the architecture level aware SPARC ASI work. gas/ChangeLog: Test cases for the architecture level aware SPARC ASI work. * gas/testsuite/gas/sparc/sparc.exp: 2 new tests * gas/testsuite/gas/sparc/asi-bump-warn.s: New test * gas/testsuite/gas/sparc/asi-bump-warn.l: Likewise * gas/testsuite/gas/sparc/asi-arch-error.s: Likewise * gas/testsuite/gas/sparc/asi-arch-error.l: Likewise
2017-02-24 09:23:50 +01:00
2017-02-24 Sheldon Lobo <sheldon.lobo@oracle.com>
Test cases for the architecture level aware SPARC ASI work.
* gas/testsuite/gas/sparc/sparc.exp: 2 new tests
* gas/testsuite/gas/sparc/asi-bump-warn.s: New test
* gas/testsuite/gas/sparc/asi-bump-warn.l: Likewise
* gas/testsuite/gas/sparc/asi-arch-error.s: Likewise
* gas/testsuite/gas/sparc/asi-arch-error.l: Likewise
MIPS/BFD: Discard ineligible JALR relocations right away Discard R_MIPS_JALR and R_MICROMIPS_JALR relocations associated with jumps that cannot be converted to an equivalent branch right away in `mips_elf_calculate_relocation' rather than letting them through to `mips_elf_perform_relocation'. This includes cross-mode jumps which need to flip the ISA bit or jumps to a misaligned location that cannot be encoded with a branch, in addition to preemptible symbol references already handled. Cross-mode jumps are actually already rejected as the conversion is made in `mips_elf_perform_relocation', so in this case this change only saves some processing. Jumps to a misaligned location are however converted, with bits causing misalignment lost, making resulting code functionally different even if the lone effect is avoiding an address error exception with an instruction fetch at the jump destination requested. Add test cases suitable, also including GAS verification to confirm that the JALR relocations explicitly requested have indeed been output in the intermediate objects used. bfd/ * elfxx-mips.c (mips_elf_calculate_relocation) <R_MIPS_JALR> <R_MICROMIPS_JALR>: Discard relocation if `cross_mode_jump_p' or misaligned. gas/ * testsuite/gas/mips/jalr4.d: New test. * testsuite/gas/mips/jalr4-n32.d: New test. * testsuite/gas/mips/jalr4-n64.d: New test. * testsuite/gas/mips/jalr4.s: New test source. * testsuite/gas/mips/mips.exp: Run the new tests. ld/ * testsuite/ld-mips-elf/jalr4.dd: New test. * testsuite/ld-mips-elf/mips-elf.exp: Run the new test.
2017-02-23 20:26:53 +01:00
2017-02-23 Maciej W. Rozycki <macro@imgtec.com>
* testsuite/gas/mips/jalr4.d: New test.
* testsuite/gas/mips/jalr4-n32.d: New test.
* testsuite/gas/mips/jalr4-n64.d: New test.
* testsuite/gas/mips/jalr4.s: New test source.
* testsuite/gas/mips/mips.exp: Run the new tests.
opcodes,gas: associate SPARC ASIs with an architecture level. With this change an architecture level bump due to assembly ASIs will show up as a warning/error depending on options passed to gas. Tested with sparc64-linux-gnu, and it does not introduce any regressions. gas/ChangeLog: Add support for associating SPARC ASIs with an architecture level. * config/tc-sparc.c (parse_sparc_asi): New encode SPARC ASIs. opcodes/ChangeLog: Add support for associating SPARC ASIs with an architecture level. * include/opcode/sparc.h (sparc_asi): New sparc_asi struct. * opcodes/sparc-opc.c (asi_table): Updated asi_table and encoding/ decoding of SPARC ASIs.
2017-02-23 16:49:37 +01:00
2017-02-23 Sheldon Lobo <sheldon.lobo@oracle.com>
Add support for associating SPARC ASIs with an architecture level.
* config/tc-sparc.c (parse_sparc_asi): New encode SPARC ASIs.
gas: slightly relax .startof.()/.sizeof.() testcase
2017-02-23 11:21:10 +01:00
2017-02-23 Jan Beulich <jbeulich@suse.com>
* testsuite/gas/all/err-sizeof.s: Don't use sums or differences
of symbols as expression.
2017-02-23 Jan Beulich <jbeulich@suse.com>
x86: extend 64-bit invalid MPX insn forms testcase
2017-02-23 11:00:44 +01:00
* gas/testsuite/gas/i386/x86-64-mpx-inval-2.d: Add 32- and 16-
bit GPR forms of BNDCL, BNDCU, and BNDCN. Add RSP-as-index
Intel syntax forms of BNDMK, BNDSTX, and BNDLDX.
* gas/testsuite/gas/i386/x86-64-mpx-inval-2.l: Adjust.
GAS: Consistently fix labels at the `.end' pseudo-op Fix a functional regression with the `.end' pseudo-op, introduced with commit ecb4347adecd ("Last take: approval for MIPS_STABS_ELF killing"), <https://sourceware.org/ml/binutils/2002-06/msg00443.html>, and commit dcd410fe1544 ("GNU as 2.14 on IRIX 6: crashes with shared libs"), <https://sourceware.org/ml/binutils/2003-07/msg00415.html>, which caused symbol values for labels placed between the end of a function's contents and its terminating `.end' followed by one of the alignment pseudo-ops to be different depending on whether either `-mdebug', or `-mno-pdr', or neither of the command-line options is in effect, be it implied or specified. Given debug-label-end.s as follows and the `mips-linux' target we have: $ cat debug-label-end.s .text .globl foo .globl bar .align 4, 0 .ent foo foo: nop .aent bar bar: .insn .end foo .align 4, 0 .space 16 .globl baz .ent baz baz: nop .end baz .align 4, 0 .space 16 $ as -o debug-label-end.o debug-label-end.s $ readelf -s debug-label-end.o | grep bar 9: 00000004 0 FUNC GLOBAL DEFAULT 1 bar $ as -mdebug -o debug-label-end.o debug-label-end.s $ readelf -s debug-label-end.o | grep bar 9: 00000010 0 FUNC GLOBAL DEFAULT 1 bar $ as -mno-pdr -o debug-label-end.o debug-label-end.s $ readelf -s debug-label-end.o | grep bar 8: 00000010 0 FUNC GLOBAL DEFAULT 1 bar $ The reason is the call to `md_flush_pending_output', which in the case of `mips*-*-*' targets expands to `mips_emit_delays', which in turn calls `mips_no_prev_insn', which calls `mips_clear_insn_labels', which clears the list of outstanding labels. That list is in turn consulted in `mips_align', called in the interpretation of alignment directives, and the labels adjusted to the current location. A call to `md_flush_pending_output' is only made from `s_mips_end' and then only if `-mpdr' is in effect, which is the default for `*-*-linux*' and some other `mips*-*-*' targets. A call to `md_flush_pending_output' is never made from `ecoff_directive_end', which is used in place of `s_mips_end' when `-mdebug' is in effect. Consequently if `-mno-pdr' or `-mdebug' is in effect the list of outstanding labels makes it through to any alignment directive that follows and the labels are differently interpreted depending on the command-lines options used. And we want code produced to be always the same. Call `md_flush_pending_output' unconditionally then in `s_mips_end' and add such a call from `ecoff_directive_end' as well, as long as the macro is defined. While `ecoff_directive_end' is shared among targets, the only one other than `mips*-*-*' actually using it is `alpha*-*-*' and it does not define `md_flush_pending_output'. So the semantics isn't going to change for it and neither it has to have its `s_alpha_end' updated or have code in `ecoff_directive_end' conditionalized. gas/ * ecoff.c (ecoff_directive_end) [md_flush_pending_output]: Call `md_flush_pending_output'. * config/tc-mips.c (s_mips_end) [md_flush_pending_output]: Call `md_flush_pending_output' unconditionally. * testsuite/gas/mips/debug-label-end-1.d: New test. * testsuite/gas/mips/debug-label-end-2.d: New test. * testsuite/gas/mips/debug-label-end-3.d: New test. * testsuite/gas/mips/debug-label-end.s: New test source. * testsuite/gas/mips/mips.exp: Run the new tests.
2017-02-17 21:30:55 +01:00
2017-02-22 Maciej W. Rozycki <macro@imgtec.com>
* ecoff.c (ecoff_directive_end) [md_flush_pending_output]: Call
`md_flush_pending_output'.
* config/tc-mips.c (s_mips_end) [md_flush_pending_output]: Call
`md_flush_pending_output' unconditionally.
* testsuite/gas/mips/debug-label-end-1.d: New test.
* testsuite/gas/mips/debug-label-end-2.d: New test.
* testsuite/gas/mips/debug-label-end-3.d: New test.
* testsuite/gas/mips/debug-label-end.s: New test source.
* testsuite/gas/mips/mips.exp: Run the new tests.
Fix gas/all/err-sizeof.s for cris*-*-*
2017-02-22 14:17:33 +01:00
2017-02-22 Hans-Peter Nilsson <hp@axis.com>
* testsuite/gas/all/err-sizeof.s: Include cris*-*-* in the list of
targets yielding an error message matching "too complex".
Skip ARM vcmp-noprefix-imm test on non-ELF targets
2017-02-22 12:57:49 +01:00
2017-02-22 Nick Clifton <nickc@redhat.com>
* testsuite/gas/arm/vcmp-noprefix-imm.d: Skip for non-ELF targets.
gas: require an operand to .startof.()/.sizeof.()
2017-02-22 10:37:52 +01:00
2017-02-21 Jan Beulich <jbeulich@suse.com>
* expr.c (operand): Handle missing operand to .startof.() and
.sizeof.().
* testsuite/gas/all/err-sizeof.s: New.
Downgrade powerpc register error to warning PR 21118 * NEWS: Revise powerpc register check. * config/tc-ppc.c (ppc_optimize_expr, md_assemble): Make "invalid register expression" a warning.
2017-02-20 02:36:52 +01:00
2017-02-20 Alan Modra <amodra@gmail.com>
PR 21118
* NEWS: Revise powerpc register check.
* config/tc-ppc.c (ppc_optimize_expr, md_assemble): Make "invalid
register expression" a warning.
GAS: Add ECOFF `.aent' pseudo-op support Implement the ECOFF `.aent' pseudo-op for ECOFF-style `.mdebug' section support with ELF objects and, for consistency, also with ECOFF objects. This is so that the same MIPS source can be assembled without and with `.mdebug' section generation enabled. Taking the `gas/testsuite/gas/mips/aent.s' test case source as an example and the `mips-linux' target we have: $ as -o aent.o aent.s $ as -mdebug -o aent.o aent.s aent.s: Assembler messages: aent.s:10: Error: unknown pseudo-op: `.aent' $ because for the !ECOFF_DEBUGGING case (which is the default) the pseudo-op is already handled by the MIPS backend with `s_mips_ent', however no handler is present for the opposite case. For the MIPS target this is a functional regression introduced with commit ecb4347adecd ("Last take: approval for MIPS_STABS_ELF killing"), <https://sourceware.org/ml/binutils/2002-06/msg00443.html>, where support for the `.mdebug' section was added along with its associated `-mdebug'/`-no-mdebug' command-line options, bringing an inconsistency between the assembly syntax supported for each of these options as far as the `.aent' pseudo-op is concerned. Assembly language documentation available describes the pseudo-op respectively as follows[1]: " .aent name, symno Sets an alternate entry point for the current procedure. Use this information when you want to generate information for the debugger. It must appear inside an .ent/.end pair." and[2]: " .aent name [,symno] Sets an alternate entry point for the current procedure. Use this information when you want to generate information for the debugger. This directive must appear between a pair of .ent and .end directives. (The optional symno is for compiler use only. It refers to a dense number in a .T file (symbol table).)" Copy the approach from `s_mips_ent' then and add `.aent' support to the `.ent' pseudo-op handler shared between the ELF and ECOFF object file format backends, by setting BSF_FUNCTION for the symbol requested. References: [1] "MIPSpro Assembly Language Programmer's Guide", Silicon Graphics, Inc., Document Number 007-2418-004, Section 8.1 "Op-Codes", p. 96 <http://techpubs.sgi.com/library/manuals/2000/007-2418-004/pdf/007-2418-004.pdf> [2] "Digital UNIX Assembly Language Programmer's Guide", Digital Equipment Corporation, Order Number: AA-PS31D-TE, March 1996, Chapter 5 "Assembler Directives", p. 5-2 <http://h41361.www4.hpe.com/docs/base_doc/DOCUMENTATION/V40G_PDF/APS31DTE.PDF> gas/ * ecoff.c (ecoff_directive_ent, add_procedure): Handle `.aent'. * config/obj-ecoff.c (obj_pseudo_table): Add "aent" entry. * config/obj-elf.c (ecoff_debug_pseudo_table): Likewise. * testsuite/gas/mips/aent-2.d: New test. * testsuite/gas/mips/aent-mdebug.d: New test. * testsuite/gas/mips/aent-mdebug-2.d: New test. * testsuite/gas/mips/mips.exp: Run the new tests.
2017-02-16 02:50:29 +01:00
2017-02-17 Maciej W. Rozycki <macro@imgtec.com>
* ecoff.c (ecoff_directive_ent, add_procedure): Handle `.aent'.
* config/obj-ecoff.c (obj_pseudo_table): Add "aent" entry.
* config/obj-elf.c (ecoff_debug_pseudo_table): Likewise.
* testsuite/gas/mips/aent-2.d: New test.
* testsuite/gas/mips/aent-mdebug.d: New test.
* testsuite/gas/mips/aent-mdebug-2.d: New test.
* testsuite/gas/mips/mips.exp: Run the new tests.
[AArch64] Add SVE system registers This patch adds the SVE-specific system registers. opcodes/ * aarch64-opc.c (aarch64_sys_regs): Add SVE registers. (aarch64_sys_reg_supported_p): Handle them. gas/ * testsuite/gas/aarch64/sve-sysreg.s, testsuite/gas/aarch64/sve-sysreg.d, testsuite/gas/aarch64/sve-sysreg-invalid.d, testsuite/gas/aarch64/sve-sysreg-invalid.l: New tests.
2017-02-15 17:54:21 +01:00
2017-02-15 Richard Sandiford <richard.sandiford@arm.com>
* testsuite/gas/aarch64/sve-sysreg.s,
testsuite/gas/aarch64/sve-sysreg.d,
testsuite/gas/aarch64/sve-sysreg-invalid.d,
testsuite/gas/aarch64/sve-sysreg-invalid.l: New tests.
[AArch64] Fix +sve documentation The documentation entry for the SVE feature incorrectly said that it was enabled by default for ARMv8-A or later. This patch fixes that and also mentions that +sve implies +simd. (It also implies +fp, but that follows by transitivity.) gas/ * doc/c-aarch64.texi: Fix sve entry.
2017-02-15 17:51:17 +01:00
2017-02-15 Richard Sandiford <richard.sandiford@arm.com>
* doc/c-aarch64.texi: Fix sve entry.
[ARC] Fix assembler relaxation. Fix assembler relaxation step for add, ld, mov, mpy and sub instructions. Add tests to it. gas/ 2017-02-15 Claudiu Zissulescu <claziss@synopsys.com> * config/tc-arc.c (md_convert_frag): Remove @pcl relocation information from input expression. (assemble_insn): Make sure pcrel is correctly set. (arc_pcrel_adjust): Compensate for PCL rounding. * testsuite/gas/arc/relax-add01.d: New file. * testsuite/gas/arc/relax-add01.s: Likewise. * testsuite/gas/arc/relax-add02.d: Likewise. * testsuite/gas/arc/relax-add02.s: Likewise. * testsuite/gas/arc/relax-add03.d: Likewise. * testsuite/gas/arc/relax-add03.s: Likewise. * testsuite/gas/arc/relax-add04.d: Likewise. * testsuite/gas/arc/relax-add04.s: Likewise. * testsuite/gas/arc/relax-ld01.d: Likewise. * testsuite/gas/arc/relax-ld01.s: Likewise. * testsuite/gas/arc/relax-ld02.d: Likewise. * testsuite/gas/arc/relax-ld02.s: Likewise. * testsuite/gas/arc/relax-mov01.d: Likewise. * testsuite/gas/arc/relax-mov01.s: Likewise. * testsuite/gas/arc/relax-mov02.d: Likewise. * testsuite/gas/arc/relax-mov02.s: Likewise. * testsuite/gas/arc/relax-mpy01.d: Likewise. * testsuite/gas/arc/relax-mpy01.s: Likewise. * testsuite/gas/arc/relax-sub01.d: Likewise. * testsuite/gas/arc/relax-sub01.s: Likewise. * testsuite/gas/arc/relax-sub02.d: Likewise. * testsuite/gas/arc/relax-sub02.s: Likewise. * testsuite/gas/arc/relax-sub03.d: Likewise. * testsuite/gas/arc/relax-sub03.s: Likewise. * testsuite/gas/arc/relax-sub04.d: Likewise. * testsuite/gas/arc/relax-sub04.s: Likewise. opcodes/ 2017-02-15 Claudiu Zissulescu <claziss@synopsys.com> * arc-opc.c (UIMM6_20R): Define. (SIMM12_20): Use above. (SIMM12_20R): Define. (SIMM3_5_S): Use above. (UIMM7_A32_11R_S): Define. (UIMM7_9_S): Use above. (UIMM3_13R_S): Define. (SIMM11_A32_7_S): Use above. (SIMM9_8R): Define. (UIMM10_A32_8_S): Use above. (UIMM8_8R_S): Define. (W6): Use above. (arc_relax_opcodes): Use all above defines.
2017-02-15 11:57:51 +01:00
2017-02-15 Claudiu Zissulescu <claziss@synopsys.com>
* config/tc-arc.c (md_convert_frag): Remove @pcl relocation
information from input expression.
(assemble_insn): Make sure pcrel is correctly set.
(arc_pcrel_adjust): Compensate for PCL rounding.
* testsuite/gas/arc/relax-add01.d: New file.
* testsuite/gas/arc/relax-add01.s: Likewise.
* testsuite/gas/arc/relax-add02.d: Likewise.
* testsuite/gas/arc/relax-add02.s: Likewise.
* testsuite/gas/arc/relax-add03.d: Likewise.
* testsuite/gas/arc/relax-add03.s: Likewise.
* testsuite/gas/arc/relax-add04.d: Likewise.
* testsuite/gas/arc/relax-add04.s: Likewise.
* testsuite/gas/arc/relax-ld01.d: Likewise.
* testsuite/gas/arc/relax-ld01.s: Likewise.
* testsuite/gas/arc/relax-ld02.d: Likewise.
* testsuite/gas/arc/relax-ld02.s: Likewise.
* testsuite/gas/arc/relax-mov01.d: Likewise.
* testsuite/gas/arc/relax-mov01.s: Likewise.
* testsuite/gas/arc/relax-mov02.d: Likewise.
* testsuite/gas/arc/relax-mov02.s: Likewise.
* testsuite/gas/arc/relax-mpy01.d: Likewise.
* testsuite/gas/arc/relax-mpy01.s: Likewise.
* testsuite/gas/arc/relax-sub01.d: Likewise.
* testsuite/gas/arc/relax-sub01.s: Likewise.
* testsuite/gas/arc/relax-sub02.d: Likewise.
* testsuite/gas/arc/relax-sub02.s: Likewise.
* testsuite/gas/arc/relax-sub03.d: Likewise.
* testsuite/gas/arc/relax-sub03.s: Likewise.
* testsuite/gas/arc/relax-sub04.d: Likewise.
* testsuite/gas/arc/relax-sub04.s: Likewise.
Distinguish some of the registers different on ARC700 and HS38 cpus opcodes * arc-regs.h: Distinguish some of the registers different on ARC700 and HS38 cpus. gas * testsuite/gas/arc/st.d: Update for 0xe having a name now
2017-02-15 09:52:53 +01:00
2017-02-09 Vineet Gupta <vgupta@synopsys.com>
* testsuite/gas/arc/st.d: Update for 0xe having a name now
PowerPC register expression checks This stops powerpc gas blithely accepting such nonsense as "addi %f4,%cr3,%r31". PR 21118 gas/ * NEWS: Mention powerpc register checks. * config/tc-ppc.c (struct pd_reg): Make value a short. Add flags. (pre_defined_registers): Delete fpscr and pmr entries. Set register type in flags. (cr_names): Set type in flags. (reg_name_search): Return pointer to struct pd_reg rather than value. (register_name): Adjust to suit. Set X_md from flags. (ppc_parse_name): Likewise. (ppc_optimize_expr): New function. (md_assemble): Verify expresion reg flags match operand. * config/tc-ppc.h (md_optimize_expr): Define. (ppc_optimize_expr): Declare. include/ * opcode/ppc.h (PPC_OPERAND_*): Reassign values, regs first. (PPC_OPERAND_SPR, PPC_OPERAND_GQR): Define. opcodes/ * ppc-opc.c (powerpc_operands): Flag SPR, SPRG and TBR entries with PPC_OPERAND_SPR. Flag PSQ and PSQM with PPC_OPERAND_GQR.
2017-02-14 11:08:21 +01:00
2017-02-14 Alan Modra <amodra@gmail.com>
PR 21118
* NEWS: Mention powerpc register checks.
* config/tc-ppc.c (struct pd_reg): Make value a short. Add flags.
(pre_defined_registers): Delete fpscr and pmr entries. Set
register type in flags.
(cr_names): Set type in flags.
(reg_name_search): Return pointer to struct pd_reg rather than value.
(register_name): Adjust to suit. Set X_md from flags.
(ppc_parse_name): Likewise.
(ppc_optimize_expr): New function.
(md_assemble): Verify expresion reg flags match operand.
* config/tc-ppc.h (md_optimize_expr): Define.
(ppc_optimize_expr): Declare.
Fix powerpc testsuite source errors PR 21118 work exposed these errors in the testsuite. * testsuite/gas/ppc/cell.s: Correct invalid registers. * testsuite/gas/ppc/vle-simple-1.s: Likewise. * testsuite/gas/ppc/vle-simple-2.s: Likewise.
2017-02-14 11:00:27 +01:00
2017-02-14 Alan Modra <amodra@gmail.com>
* testsuite/gas/ppc/cell.s: Correct invalid registers.
* testsuite/gas/ppc/vle-simple-1.s: Likewise.
* testsuite/gas/ppc/vle-simple-2.s: Likewise.
[ARM] Allow immediate without prefix in unified syntax for VCMP 2017-02-13 Thomas Preud'homme <thomas.preudhomme@arm.com> gas/ * config/tc-arm.c (parse_ifimm_zero): Make prefix optional in unified syntax. * testsuite/gas/arm/vcmp-noprefix-imm.d: New file. * testsuite/gas/arm/vcmp-noprefix-imm.s: New file.
2017-02-13 18:46:59 +01:00
2017-02-13 Thomas Preud'homme <thomas.preudhomme@arm.com>
* config/tc-arm.c (parse_ifimm_zero): Make prefix optional in unified
syntax.
* testsuite/gas/arm/vcmp-noprefix-imm.d: New file.
* testsuite/gas/arm/vcmp-noprefix-imm.s: New file.
POWER9 add scv/rfscv instruction support opcodes/ * ppc-opc.c (powerpc_opcodes) <scv, rfscv>: New mnemonics. gas/ * testsuite/gas/ppc/power9.d <scv, rfscv>: New tests.
2017-02-10 05:18:23 +01:00
2017-02-10 Nicholas Piggin <npiggin@gmail.com>
* testsuite/gas/ppc/power9.d <scv, rfscv>: New tests.
MIPS/GAS/doc: Include MIPS options in the man page Include the detailed MIPS option description in the man page along with other target descriptions and complementing the terse list earlier on. gas/ * doc/as.texinfo (Overview): Select MIPS options for man page inclusion.
2017-02-02 17:23:21 +01:00
2017-02-02 Maciej W. Rozycki <macro@imgtec.com>
* doc/as.texinfo (Overview): Select MIPS options for man page
inclusion.
MIPS: Add options to control branch ISA checks Complement commit 9d862524f6ae ("MIPS: Verify the ISA mode and alignment of branch and jump targets") and add GAS and LD options to control the checks for invalid branches between ISA modes introduced there, to help with some handwritten code lacking `.insn' annotation for labels used as branch targets and code produced by older versions of GCC which suffers from the issue with branches to code that has been optimized away, addressed with GCC commit 242424 ("MIPS/GCC: Mark trailing labels with `.insn'"), <https://gcc.gnu.org/ml/gcc-patches/2016-11/msg01061.html>. bfd/ * elfxx-mips.h (_bfd_mips_elf_insn32): Rename prototype to... (_bfd_mips_elf_linker_flags): ... this. Add another parameter. * elfxx-mips.c (mips_elf_link_hash_table): Add `ignore_branch_isa' member. (mips_elf_perform_relocation): Do not treat an ISA mode mismatch in branch relocation calculation as an error if `ignore_branch_isa' has been set. (_bfd_mips_elf_insn32): Rename to... (_bfd_mips_elf_linker_flags): ... this. Rename the `on' parameter to `insn32' and add an `ignore_branch_isa' parameter. Handle the new parameter. gas/ * config/tc-mips.c (mips_ignore_branch_isa): New variable. (options): Add OPTION_IGNORE_BRANCH_ISA and OPTION_NO_IGNORE_BRANCH_ISA enum values. (md_longopts): Add "mignore-branch-isa" and "mno-ignore-branch-isa" options. (md_parse_option): Handle OPTION_IGNORE_BRANCH_ISA and OPTION_NO_IGNORE_BRANCH_ISA. (fix_bad_cross_mode_branch_p): Return FALSE if `mips_ignore_branch_isa' has been set. (md_show_usage): Add `-mignore-branch-isa' and `-mno-ignore-branch-isa'. * doc/as.texinfo (Target MIPS options): Add `-mignore-branch-isa' and `-mno-ignore-branch-isa' options. (-mignore-branch-isa, -mno-ignore-branch-isa): New options. * doc/c-mips.texi (MIPS Options): Add `-mignore-branch-isa' and `-mno-ignore-branch-isa' options. * testsuite/gas/mips/branch-local-ignore-2.d: New test. * testsuite/gas/mips/branch-local-ignore-3.d: New test. * testsuite/gas/mips/branch-local-ignore-n32-2.d: New test. * testsuite/gas/mips/branch-local-ignore-n32-3.d: New test. * testsuite/gas/mips/branch-local-ignore-n64-2.d: New test. * testsuite/gas/mips/branch-local-ignore-n64-3.d: New test. * testsuite/gas/mips/mips.exp: Run the new tests. ld/ * emultempl/mipself.em (ignore_branch_isa): New variable. (mips_create_output_section_statements): Rename `_bfd_mips_elf_insn32' called to `_bfd_mips_elf_linker_flags', add `ignore_branch_isa' argument. (PARSE_AND_LIST_PROLOGUE): Add OPTION_IGNORE_BRANCH_ISA and OPTION_NO_IGNORE_BRANCH_ISA enum values. (PARSE_AND_LIST_LONGOPTS): Add "ignore-branch-isa" and "no-ignore-branch-isa" options. (PARSE_AND_LIST_OPTIONS): Add `--ignore-branch-isa' and `--no-ignore-branch-isa'. (PARSE_AND_LIST_ARGS_CASES): Handle OPTION_IGNORE_BRANCH_ISA and OPTION_NO_IGNORE_BRANCH_ISA. * ld.texinfo (Options specific to MIPS targets): Add `--ignore-branch-isa' and `--no-ignore-branch-isa' options. (ld and the MIPS family): Likewise. * testsuite/ld-mips-elf/bal-jalx-pic-ignore.d: New test. * testsuite/ld-mips-elf/bal-jalx-pic-ignore-n32.d: New test. * testsuite/ld-mips-elf/bal-jalx-pic-ignore-n64.d: New test. * testsuite/ld-mips-elf/unaligned-branch-ignore-2.d: New test. * testsuite/ld-mips-elf/unaligned-branch-ignore-r6-1: New test. * testsuite/ld-mips-elf/unaligned-branch-ignore-mips16: New test. * testsuite/ld-mips-elf/unaligned-branch-ignore-micromips: New test. * testsuite/ld-mips-elf/mips-elf.exp: Run the new tests.
2017-01-30 18:11:22 +01:00
2017-01-30 Maciej W. Rozycki <macro@imgtec.com>
* config/tc-mips.c (mips_ignore_branch_isa): New variable.
(options): Add OPTION_IGNORE_BRANCH_ISA and
OPTION_NO_IGNORE_BRANCH_ISA enum values.
(md_longopts): Add "mignore-branch-isa" and
"mno-ignore-branch-isa" options.
(md_parse_option): Handle OPTION_IGNORE_BRANCH_ISA and
OPTION_NO_IGNORE_BRANCH_ISA.
(fix_bad_cross_mode_branch_p): Return FALSE if
`mips_ignore_branch_isa' has been set.
(md_show_usage): Add `-mignore-branch-isa' and
`-mno-ignore-branch-isa'.
* doc/as.texinfo (Target MIPS options): Add
`-mignore-branch-isa' and `-mno-ignore-branch-isa' options.
(-mignore-branch-isa, -mno-ignore-branch-isa): New options.
* doc/c-mips.texi (MIPS Options): Add `-mignore-branch-isa' and
`-mno-ignore-branch-isa' options.
* testsuite/gas/mips/branch-local-ignore-2.d: New test.
* testsuite/gas/mips/branch-local-ignore-3.d: New test.
* testsuite/gas/mips/branch-local-ignore-n32-2.d: New test.
* testsuite/gas/mips/branch-local-ignore-n32-3.d: New test.
* testsuite/gas/mips/branch-local-ignore-n64-2.d: New test.
* testsuite/gas/mips/branch-local-ignore-n64-3.d: New test.
* testsuite/gas/mips/mips.exp: Run the new tests.
MIPS/GAS/testsuite: Convert branch local list tests to dump tests gas/ * testsuite/gas/mips/branch-local-2.d: New test. * testsuite/gas/mips/branch-local-3.d: New test. * testsuite/gas/mips/branch-local-n32-2.d: New test. * testsuite/gas/mips/branch-local-n32-3.d: New test. * testsuite/gas/mips/branch-local-n64-2.d: New test. * testsuite/gas/mips/branch-local-n64-3.d: New test. * testsuite/gas/mips/mips.exp: Fold corresponding list tests into the new tests.
2017-01-30 18:10:31 +01:00
2017-01-30 Maciej W. Rozycki <macro@imgtec.com>
* testsuite/gas/mips/branch-local-2.d: New test.
* testsuite/gas/mips/branch-local-3.d: New test.
* testsuite/gas/mips/branch-local-n32-2.d: New test.
* testsuite/gas/mips/branch-local-n32-3.d: New test.
* testsuite/gas/mips/branch-local-n64-2.d: New test.
* testsuite/gas/mips/branch-local-n64-3.d: New test.
* testsuite/gas/mips/mips.exp: Fold corresponding list tests
into the new tests.
Fix disassembling of TIC6X parallel instructions where the previous fetch packet ended with a 32-bit insn. PR 21056 opcodes * tic6x-dis.c (print_insn_tic6x): Correct displaying of parallel instructions when the previous fetch packet ends with a 32-bit instruction. gas * testsuite/gas/tic6x/insns16-parallel.s: New test case. * testsuite/gas/tic6x/insns16-parallel.d: New test driver.
2017-01-27 13:00:55 +01:00
2017-01-27 Alexis Deruell <alexis.deruelle@gmail.com>
PR 21056
* testsuite/gas/tic6x/insns16-parallel.s: New test case.
* testsuite/gas/tic6x/insns16-parallel.d: New test driver.
gas: Default to ELF for RTEMS targets * configure.tgt (aarch64*-*-rtems*): Remove. (bfin-*-rtems*): Likewise. (h8300-*-rtems*): Likewise. (i386-*-rtems*): Likewise. (m32c-*-rtems*): Likewise. (m32r-*-rtems*): Likewise. (m68k-*-rtems*): Likewise. (mips-*-rtems*): Likewise. (nios2-*-rtems*): Likewise. (ppc-*-rtems*): Likewise. (sh-*-rtems*): Likewise. (sparc64-*-rtems*): Likewise. (sparc-*-rtems*): Likewise. (*-*-rtems*) Use ELF format.
2017-01-25 08:24:47 +01:00
2017-01-25 Sebastian Huber <sebastian.huber@embedded-brains.de>
* configure.tgt (aarch64*-*-rtems*): Remove.
(bfin-*-rtems*): Likewise.
(h8300-*-rtems*): Likewise.
(i386-*-rtems*): Likewise.
(m32c-*-rtems*): Likewise.
(m32r-*-rtems*): Likewise.
(m68k-*-rtems*): Likewise.
(mips-*-rtems*): Likewise.
(nios2-*-rtems*): Likewise.
(ppc-*-rtems*): Likewise.
(sh-*-rtems*): Likewise.
(sparc64-*-rtems*): Likewise.
(sparc-*-rtems*): Likewise.
(*-*-rtems*) Use ELF format.
gas: Use ARM EABI for RTEMS * configure.tgt (arm-*-rtems*): Move to (arm-*-eabi*).
2017-01-25 08:23:44 +01:00
2017-01-25 Sebastian Huber <sebastian.huber@embedded-brains.de>
* configure.tgt (arm-*-rtems*): Move to (arm-*-eabi*).
Remove all RTEMS COFF targets bfd/ * config.bfd (*-*-rtemscoff*): Mark as removed. gas/ * configure.tgt (sh-*-rtemscoff*): Remove. ld/ * configure.tgt (h8300-*-rtemscoff*): Remove. (i960-*-rtems*): Likewise. (m68*-*-rtemscoff*): Likewise. (sh-*-rtemscoff*): Likewise.
2017-01-25 08:22:27 +01:00
2017-01-25 Sebastian Huber <sebastian.huber@embedded-brains.de>
* configure.tgt (sh-*-rtemscoff*): Remove.
RISC-V gas: Remove em=linux from configure.tgt The use of te-linux.h is unnecessary since the TE_LINUX define is unused and LOCAL_LABELS_FB is defined to 1 in tc-riscv.h as well. gas/ * configure.tgt (riscv*-*-*): Remove em=linux.
2017-01-19 09:10:51 +01:00
2017-01-24 Sebastian Huber <sebastian.huber@embedded-brains.de>
* configure.tgt (riscv*-*-*): Remove em=linux.
Fix spelling mistakes and typos in the GAS sources. PR gas/21072 * asintl.h: Fix spelling mistakes and typos. * atof-generic.c: Likewise. * bit_fix.h: Likewise. * config/atof-ieee.c: Likewise. * config/bfin-defs.h: Likewise. * config/bfin-parse.y: Likewise. * config/obj-coff-seh.h: Likewise. * config/obj-coff.c: Likewise. * config/obj-evax.c: Likewise. * config/obj-macho.c: Likewise. * config/rx-parse.y: Likewise. * config/tc-aarch64.c: Likewise. * config/tc-alpha.c: Likewise. * config/tc-arc.c: Likewise. * config/tc-arm.c: Likewise. * config/tc-avr.c: Likewise. * config/tc-bfin.c: Likewise. * config/tc-cr16.c: Likewise. * config/tc-cris.c: Likewise. * config/tc-crx.c: Likewise. * config/tc-d10v.c: Likewise. * config/tc-d30v.c: Likewise. * config/tc-dlx.c: Likewise. * config/tc-epiphany.c: Likewise. * config/tc-frv.c: Likewise. * config/tc-hppa.c: Likewise. * config/tc-i370.c: Likewise. * config/tc-i386-intel.c: Likewise. * config/tc-i386.c: Likewise. * config/tc-i960.c: Likewise. * config/tc-ia64.c: Likewise. * config/tc-m32r.c: Likewise. * config/tc-m68hc11.c: Likewise. * config/tc-m68k.c: Likewise. * config/tc-mcore.c: Likewise. * config/tc-mep.c: Likewise. * config/tc-mep.h: Likewise. * config/tc-metag.c: Likewise. * config/tc-microblaze.c: Likewise. * config/tc-mips.c: Likewise. * config/tc-mmix.c: Likewise. * config/tc-mn10200.c: Likewise. * config/tc-mn10300.c: Likewise. * config/tc-msp430.c: Likewise. * config/tc-msp430.h: Likewise. * config/tc-nds32.c: Likewise. * config/tc-nds32.h: Likewise. * config/tc-nios2.c: Likewise. * config/tc-nios2.h: Likewise. * config/tc-ns32k.c: Likewise. * config/tc-pdp11.c: Likewise. * config/tc-ppc.c: Likewise. * config/tc-pru.c: Likewise. * config/tc-rx.c: Likewise. * config/tc-s390.c: Likewise. * config/tc-score.c: Likewise. * config/tc-score7.c: Likewise. * config/tc-sh.c: Likewise. * config/tc-sh64.c: Likewise. * config/tc-sparc.c: Likewise. * config/tc-tic4x.c: Likewise. * config/tc-tic54x.c: Likewise. * config/tc-v850.c: Likewise. * config/tc-vax.c: Likewise. * config/tc-visium.c: Likewise. * config/tc-xgate.c: Likewise. * config/tc-xtensa.c: Likewise. * config/tc-z80.c: Likewise. * config/tc-z8k.c: Likewise. * config/te-vms.c: Likewise. * config/xtensa-relax.c: Likewise. * doc/as.texinfo: Likewise. * doc/c-arm.texi: Likewise. * doc/c-hppa.texi: Likewise. * doc/c-i370.texi: Likewise. * doc/c-i386.texi: Likewise. * doc/c-m32r.texi: Likewise. * doc/c-m68k.texi: Likewise. * doc/c-mmix.texi: Likewise. * doc/c-msp430.texi: Likewise. * doc/c-nds32.texi: Likewise. * doc/c-ns32k.texi: Likewise. * doc/c-riscv.texi: Likewise. * doc/c-rx.texi: Likewise. * doc/c-s390.texi: Likewise. * doc/c-tic6x.texi: Likewise. * doc/c-tilegx.texi: Likewise. * doc/c-tilepro.texi: Likewise. * doc/c-v850.texi: Likewise. * doc/c-xgate.texi: Likewise. * doc/c-xtensa.texi: Likewise. * dwarf2dbg.c: Likewise. * ecoff.c: Likewise. * itbl-ops.c: Likewise. * listing.c: Likewise. * macro.c: Likewise. * po/gas.pot: Likewise. * read.c: Likewise. * struc-symbol.h: Likewise. * symbols.h: Likewise. * testsuite/gas/arc/relocs-errors.err: Likewise. * write.c: Likewise.
2017-01-23 16:23:07 +01:00
2017-01-23 Sebastian Rasmussen <sebras@gmail.com>
PR gas/21072
* asintl.h: Fix spelling mistakes and typos.
* atof-generic.c: Likewise.
* bit_fix.h: Likewise.
* config/atof-ieee.c: Likewise.
* config/bfin-defs.h: Likewise.
* config/bfin-parse.y: Likewise.
* config/obj-coff-seh.h: Likewise.
* config/obj-coff.c: Likewise.
* config/obj-evax.c: Likewise.
* config/obj-macho.c: Likewise.
* config/rx-parse.y: Likewise.
* config/tc-aarch64.c: Likewise.
* config/tc-alpha.c: Likewise.
* config/tc-arc.c: Likewise.
* config/tc-arm.c: Likewise.
* config/tc-avr.c: Likewise.
* config/tc-bfin.c: Likewise.
* config/tc-cr16.c: Likewise.
* config/tc-cris.c: Likewise.
* config/tc-crx.c: Likewise.
* config/tc-d10v.c: Likewise.
* config/tc-d30v.c: Likewise.
* config/tc-dlx.c: Likewise.
* config/tc-epiphany.c: Likewise.
* config/tc-frv.c: Likewise.
* config/tc-hppa.c: Likewise.
* config/tc-i370.c: Likewise.
* config/tc-i386-intel.c: Likewise.
* config/tc-i386.c: Likewise.
* config/tc-i960.c: Likewise.
* config/tc-ia64.c: Likewise.
* config/tc-m32r.c: Likewise.
* config/tc-m68hc11.c: Likewise.
* config/tc-m68k.c: Likewise.
* config/tc-mcore.c: Likewise.
* config/tc-mep.c: Likewise.
* config/tc-mep.h: Likewise.
* config/tc-metag.c: Likewise.
* config/tc-microblaze.c: Likewise.
* config/tc-mips.c: Likewise.
* config/tc-mmix.c: Likewise.
* config/tc-mn10200.c: Likewise.
* config/tc-mn10300.c: Likewise.
* config/tc-msp430.c: Likewise.
* config/tc-msp430.h: Likewise.
* config/tc-nds32.c: Likewise.
* config/tc-nds32.h: Likewise.
* config/tc-nios2.c: Likewise.
* config/tc-nios2.h: Likewise.
* config/tc-ns32k.c: Likewise.
* config/tc-pdp11.c: Likewise.
* config/tc-ppc.c: Likewise.
* config/tc-pru.c: Likewise.
* config/tc-rx.c: Likewise.
* config/tc-s390.c: Likewise.
* config/tc-score.c: Likewise.
* config/tc-score7.c: Likewise.
* config/tc-sh.c: Likewise.
* config/tc-sh64.c: Likewise.
* config/tc-sparc.c: Likewise.
* config/tc-tic4x.c: Likewise.
* config/tc-tic54x.c: Likewise.
* config/tc-v850.c: Likewise.
* config/tc-vax.c: Likewise.
* config/tc-visium.c: Likewise.
* config/tc-xgate.c: Likewise.
* config/tc-xtensa.c: Likewise.
* config/tc-z80.c: Likewise.
* config/tc-z8k.c: Likewise.
* config/te-vms.c: Likewise.
* config/xtensa-relax.c: Likewise.
* doc/as.texinfo: Likewise.
* doc/c-arm.texi: Likewise.
* doc/c-hppa.texi: Likewise.
* doc/c-i370.texi: Likewise.
* doc/c-i386.texi: Likewise.
* doc/c-m32r.texi: Likewise.
* doc/c-m68k.texi: Likewise.
* doc/c-mmix.texi: Likewise.
* doc/c-msp430.texi: Likewise.
* doc/c-nds32.texi: Likewise.
* doc/c-ns32k.texi: Likewise.
* doc/c-riscv.texi: Likewise.
* doc/c-rx.texi: Likewise.
* doc/c-s390.texi: Likewise.
* doc/c-tic6x.texi: Likewise.
* doc/c-tilegx.texi: Likewise.
* doc/c-tilepro.texi: Likewise.
* doc/c-v850.texi: Likewise.
* doc/c-xgate.texi: Likewise.
* doc/c-xtensa.texi: Likewise.
* dwarf2dbg.c: Likewise.
* ecoff.c: Likewise.
* itbl-ops.c: Likewise.
* listing.c: Likewise.
* macro.c: Likewise.
* po/gas.pot: Likewise.
* read.c: Likewise.
* struc-symbol.h: Likewise.
* symbols.h: Likewise.
* testsuite/gas/arc/relocs-errors.err: Likewise.
* write.c: Likewise.
Updated Irish translation for ld and Swedish translation for gas.
2017-01-23 14:32:12 +01:00
2017-01-23 Nick Clifton <nickc@redhat.com>
* po/sv.po: Updated Swedish translation.
Fix potential array overrun in x86 assembler. * config/tc-i386.c (parse_operands): Check for operand overflow before setting the unspecified bit.
2017-01-20 11:32:25 +01:00
2017-01-20 Nick Clifton <nickc@redhat.com>
* config/tc-i386.c (parse_operands): Check for operand overflow
before setting the unspecified bit.
PR gas/20649: MIPS: Fix GOT16/LO16 reloc pairing with comdat sections Correct a regression from commit 8614eeee67f9 ("Traditional MIPS patches"), <https://sourceware.org/ml/binutils/2000-07/msg00018.html>, which caused symbols in linkonce or what is these days known as comdat sections to be treated as external for the purpose of PIC relocation generation even if their binding remains STB_LOCAL. This in turn disabled GOT16/LO16 relocation pairing with references to such symbols, as no complementing LO16 relocation is expected for external GOT16 references in the o32 ABI, which ultimately leads to link errors, e.g.: ld: comdat-reloc.o: Can't find matching LO16 reloc against `foo' for R_MIPS_GOT16 at 0x24 in section `.text.bar[bar]' as with the LD test case included with this change. Revert the special case for symbols in comdat sections then, making code actually match `adjust_reloc_syms' as indicated in its explanatory comment, and adjust calling code accordingly. Also bring back the corresponding description of what now is `s_is_linkonce', lost with commit 5f0fe04bc550 ("Improved MIPS16/MIPS32 code intermixing for gas."), <https://www.sourceware.org/ml/binutils/2006-07/msg00039.html>. gas/ PR gas/20649 * config/tc-mips.c (pic_need_relax): Don't check for linkonce symbols, remove the `segtype' parameter. (mips_frob_file, md_estimate_size_before_relax): Adjust accordingly. (s_is_linkonce): Add an explanatory comment. * testsuite/gas/mips/comdat-reloc.d: New test. * testsuite/gas/mips/comdat-reloc.s: New test source. * testsuite/gas/mips/mips.exp: Run the new test. ld/ PR gas/20649 * testsuite/ld-mips-elf/mips-elf.exp: Add PIC comdat GOT16/LO16 relocation pairing link test.
2017-01-18 19:18:21 +01:00
2017-01-18 Maciej W. Rozycki <macro@imgtec.com>
PR gas/20649
* config/tc-mips.c (pic_need_relax): Don't check for linkonce
symbols, remove the `segtype' parameter.
(mips_frob_file, md_estimate_size_before_relax): Adjust
accordingly.
(s_is_linkonce): Add an explanatory comment.
* testsuite/gas/mips/comdat-reloc.d: New test.
* testsuite/gas/mips/comdat-reloc.s: New test source.
* testsuite/gas/mips/mips.exp: Run the new test.
[ARM] Fix the decoding of indexed element VCMLA instruction Bit 24 of the indexed element vcmla decode mask was incorrectly left unset. This could cause incorrect disassembly of some currently undefined instructions as vcmla. Rotatation immediates were not printed correctly in the disassembly (could print 170 and 280 instead of 180 and 270). opcodes/ * arm-dis.c (coprocessor_opcodes): Fix vcmla mask and disassembly. gas/ * testsuite/gas/arm/armv8_3-a-simd.s: Add vcmla tests. * testsuite/gas/arm/armv8_3-a-simd.d: Update.
2017-01-18 18:08:34 +01:00
2017-01-18 Szabolcs Nagy <szabolcs.nagy@arm.com>
* testsuite/gas/arm/armv8_3-a-simd.s: Add vcmla tests.
* testsuite/gas/arm/armv8_3-a-simd.d: Update.
Add support for processing lex source files with flex v 2.6.3 PR 21059 binutils* arlex.l: Support processing with flex 2.6.3. * deflex.l: Likewise. gas * config/bfin-lex.l: Support processing with flex 2.6.3. * itbl-lex.l: Likewise.
2017-01-18 14:38:27 +01:00
2017-01-18 Bernhard Rosenkranzer <bero@lindev.ch>
PR 21059
* config/bfin-lex.l: Support processing with flex 2.6.3.
* itbl-lex.l: Likewise.
Catch gas exit-via-signal gas/ * as.h (gas_assert): Use abort. (as_assert): Remove. (signal_init): Declare. * as.c (main): Call signal_init. * messages.c: #include <signal.h> (as_assert): Delete. (as_abort): Allow NULL FILE. (signal_crash): New. (signal_init): Register fatal signal handlers. * configure.ac: Check for strsignal. * config.in: Rebuilt. * configure: Rebuilt.
2017-01-18 14:23:10 +01:00
2017-01-18 Nathan Sidwell <nathan@acm.org>
* as.h (gas_assert): Use abort.
(as_assert): Remove.
(signal_init): Declare.
* as.c (main): Call signal_init.
* messages.c: #include <signal.h>
(as_assert): Delete.
(as_abort): Allow NULL FILE.
(signal_crash): New.
(signal_init): Register fatal signal handlers.
* configure.ac: Check for strsignal.
* config.in: Rebuilt.
* configure: Rebuilt.
Updated Swedish translation for GAS.
2017-01-18 12:35:29 +01:00
2017-01-17 Nick Clifton <nickc@redhat.com>
Updated Swedish translations for GAS and LD subdirectories. gas * po/sv.po: Updated Swedish translation. ld * po/sv.po: Updated Swedish translation.
2017-01-16 11:59:23 +01:00
* po/sv.po: Updated Swedish translation.
Enable Intel AVX512_VPOPCNTDQ instructions gas/ 2017-01-12 Igor Tsimbalist <igor.v.tsimbalist@intel.com> * config/tc-i386.c (cpu_arch): Add .avx512_vpopcntdq. (cpu_noarch): Add noavx512_vpopcntdq. * doc/c-i386.texi: Document avx512_vpopcntdq, noavx512_vpopcntdq. * testsuite/gas/i386/i386.exp: Run AVX512_VPOPCNTDQ tests. * testsuite/gas/i386/avx512_vpopcntdqd-intel.d: New file. * testsuite/gas/i386/avx512_vpopcntdqd.d: Ditto. * testsuite/gas/i386/avx512_vpopcntdqd.s: Ditto. * testsuite/gas/i386/x86-64-avx512_vpopcntdqd-intel.d: Ditto. * testsuite/gas/i386/x86-64-avx512_vpopcntdqd.d: Ditto. * testsuite/gas/i386/x86-64-avx512_vpopcntdqd.s: Ditto. opcodes/ 2017-01-12 Igor Tsimbalist <igor.v.tsimbalist@intel.com> * i386-dis.c (enum): Add PREFIX_EVEX_0F3855, EVEX_W_0F3855_P_2. * i386-dis-evex.h (evex_table): Updated. * i386-gen.c (cpu_flag_init): Add CPU_AVX512_VPOPCNTDQ_FLAGS, CPU_ANY_AVX512_VPOPCNTDQ_FLAGS. Update CPU_ANY_AVX512F_FLAGS. (cpu_flags): Add CpuAVX512_VPOPCNTDQ. * i386-opc.h (enum): (AVX512_VPOPCNTDQ): New. (i386_cpu_flags): Add cpuavx512_vpopcntdq. * i386-opc.tbl: Add Intel AVX512_VPOPCNTDQ instructions. * i386-init.h: Regenerate. * i386-tbl.h: Ditto.
2017-01-12 17:42:17 +01:00
2017-01-12 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
* config/tc-i386.c (cpu_arch): Add .avx512_vpopcntdq.
(cpu_noarch): Add noavx512_vpopcntdq.
* doc/c-i386.texi: Document avx512_vpopcntdq, noavx512_vpopcntdq.
* testsuite/gas/i386/i386.exp: Run AVX512_VPOPCNTDQ tests.
* testsuite/gas/i386/avx512_vpopcntdqd-intel.d: New file.
* testsuite/gas/i386/avx512_vpopcntdqd.d: Ditto.
* testsuite/gas/i386/avx512_vpopcntdqd.s: Ditto.
* testsuite/gas/i386/x86-64-avx512_vpopcntdqd-intel.d: Ditto.
* testsuite/gas/i386/x86-64-avx512_vpopcntdqd.d: Ditto.
* testsuite/gas/i386/x86-64-avx512_vpopcntdqd.s: Ditto.
Prevent internal assembler errors if a stabs creation function builds an badly formatted input string. * read.c (temp_ilp): New function. Installs a temporary input line pointer. (restore_ilp): New function. Restores the original input line pointer. * read.h (temp_ilp): Prototype. (restore_ilp): Prototype. * stabs.c (dot_func_p): Use bfd_boolean type. (generate_asm_file): Use temp_ilp and restore_ilp. (stabs_generate_asm_lineno): Likewise. (stabs_generate_asm_endfunc): Likewise.
2017-01-12 15:56:13 +01:00
2017-01-12 Nick Clifton <nickc@redhat.com>
* read.c (temp_ilp): New function. Installs a temporary input
line pointer.
(restore_ilp): New function. Restores the original input line
pointer.
* read.h (temp_ilp): Prototype.
(restore_ilp): Prototype.
* stabs.c (dot_func_p): Use bfd_boolean type.
(generate_asm_file): Use temp_ilp and restore_ilp.
(stabs_generate_asm_lineno): Likewise.
(stabs_generate_asm_endfunc): Likewise.
Add support for x86/64 redox target. bfd * config.bfd: Add entries for i686-redox and x86_64-redox. gas * configure.tgt: Add entry for i386-redox. ld * configure.tgt: Add entries for x86-redox and x86_64-redox.
2017-01-11 16:05:53 +01:00
2017-01-11 Jeremy Soller <jackpot51@gmail.com>
* configure.tgt: Add entry for i386-redox.
Updated Swedish translations for GAS and LD
2017-01-10 12:28:36 +01:00
2017-01-10 Nick Clifton <nickc@redhat.com>
* po/sv.po: Updated Swedish translation.
Fix sleb128-8 regressions. gas/ * testsuite/gas/all/sleb128-8.d: Adjust test. * testsuite/gas/all/gas.exp (test_cond): Likewise.
2017-01-10 14:43:01 +01:00
2017-01-10 Tristan Gingold <gingold@adacore.com>
* testsuite/gas/all/sleb128-8.d: Adjust test.
* testsuite/gas/all/gas.exp (test_cond): Likewise.
This patch ensure same output for sleb128 with large number. gas/ * read.c (emit_leb128_expr): Extended unsigned big number for sleb128. * testsuite/gas/all/gas.exp (test_cond): Add sleb128-8 test. * testsuite/gas/all/sleb128.d: New test. * testsuite/gas/all/sleb128.s: New test source.
2017-01-09 15:50:32 +01:00
2017-01-10 Tristan Gingold <gingold@adacore.com>
* read.c (emit_leb128_expr): Extended unsigned big number for
sleb128.
* testsuite/gas/all/gas.exp (test_cond): Add sleb128-8 test.
* testsuite/gas/all/sleb128.d: New test.
* testsuite/gas/all/sleb128.s: New test source.
RISC-V/GAS: Support more relocs against constant addresses Previously, some pseudoinstructions like "call" only accepted symbolic addresses and rejected constant addresses with an esoteric internal error. This patch enables them by deferring application of constant relocations to md_apply_fix, rather than eagerly applying them during instruction assembly. gas/ChangeLog 2017-01-09 Andrew Waterman <andrew@sifive.com> * config/tc-riscv.c (append_insn): Don't eagerly apply relocations against constants. (md_apply_fix): Mark relocations against constants as "done."
2016-12-22 03:05:28 +01:00
2017-01-09 Andrew Waterman <andrew@sifive.com>
* config/tc-riscv.c (append_insn): Don't eagerly apply relocations
against constants.
(md_apply_fix): Mark relocations against constants as "done."
RISC-V/GAS: Improve handling of invalid relocs TLS relocs against constants previously segfaulted, and illegal symbol subtractions were silently ignored. The previous behavior was to segfault. gas/ChangeLog 2017-01-09 Andrew Waterman <andrew@sifive.com> * config/tc-riscv.c (md_apply_fix): Report TLS relocations against constants. Report disallowed symbol subtractions.
2016-12-21 21:47:13 +01:00
2017-01-09 Andrew Waterman <andrew@sifive.com>
* config/tc-riscv.c (append_insn): Don't eagerly apply relocations
against constants.
(md_apply_fix): Mark relocations against constants as "done."
Remove some custom sections from RISC-V's default linker scripts This was added so compressed loads could have smaller offsets for accessing the data section, but the result was that writable sections ended up in INITIAL_READONLY_SECTIONS. This is a bad idea. The fix is to just remove this micro-optimization. Thanks to Alan Morda for finding the problem! ld/ChangeLog 2017-01-09 Palmer Dabbelt <palmer@dabbelt.com> Kito Cheng <kito.cheng@gmail.com> * emulparams/elf32lriscv-defs.sh (INITIAL_READONLY_SECTIONS): Removed. (SDATA_START_SYMBOLS): Likewise.
2016-12-30 02:29:53 +01:00
2017-01-09 Palmer Dabbelt <palmer@dabbelt.com>
Kito Cheng <kito.cheng@gmail.com>
* emulparams/elf32lriscv-defs.sh (INITIAL_READONLY_SECTIONS):
Removed.
(SDATA_START_SYMBOLS): Likewise.
Add Swedish translation for GAS. * po/sv.po: New Swedish translation. * configure.ac (ALL_LINGUAS): Add sv. * configure: Regenerate.
2017-01-09 11:11:50 +01:00
2017-01-09 Nick Clifton <nickc@redhat.com>
* po/sv.po: New Swedish translation.
* configure.ac (ALL_LINGUAS): Add sv.
* configure: Regenerate.
RISC-V/GAS: Correct branch relaxation for weak symbols. * config/tc-riscv.c (relaxed_branch_length): Use the long sequence when the target is a weak symbol.
2017-01-09 10:22:33 +01:00
2017-01-09 Andrew Waterman <andrew@sifive.com>
* config/tc-riscv.c (relaxed_branch_length): Use the long
sequence when the target is a weak symbol.
[AArch64] Add separate feature flag for weaker release consistent load insns The weaker release consistency support of ARMv8.3-A is allowed as an optional extension for ARMv8.2-A, so separate command line option and feature flag is added: -march=armv8.2-a+rcpc turns LDAPR, LDAPRB, LDAPRH instructions on. opcodes/ * aarch64-tbl.h (RCPC, RCPC_INSN): Define. (aarch64_opcode_table): Use RCPC_INSN. include/ * opcode/aarch64.h (AARCH64_FEATURE_RCPC): Define. (AARCH64_ARCH_V8_3): Update. gas/ * config/tc-aarch64.c (aarch64_features): Add rcpc. * doc/c-aarch64.texi (AArch64 Extensions): Document rcpc. * testsuite/gas/aarch64/ldst-exclusive-armv8_3.d: Rename to ... * testsuite/gas/aarch64/ldst-rcpc.d: This. * testsuite/gas/aarch64/ldst-exclusive-armv8_3.s: Rename to ... * testsuite/gas/aarch64/ldst-rcpc.s: This. * testsuite/gas/aarch64/ldst-rcpc-armv8_2.d: New test.
2017-01-04 13:27:10 +01:00
2017-01-04 Szabolcs Nagy <szabolcs.nagy@arm.com>
* config/tc-aarch64.c (aarch64_features): Add rcpc.
* doc/c-aarch64.texi (AArch64 Extensions): Document rcpc.
* testsuite/gas/aarch64/ldst-exclusive-armv8_3.d: Rename to ...
* testsuite/gas/aarch64/ldst-rcpc.d: This.
* testsuite/gas/aarch64/ldst-exclusive-armv8_3.s: Rename to ...
* testsuite/gas/aarch64/ldst-rcpc.s: This.
* testsuite/gas/aarch64/ldst-rcpc-armv8_2.d: New test.
When configuring GAS treat as sparcv9 target the same way as a sparc64 target. PR gas/20992 * configure.tgt: Treat sparcv9 as sparc64.
2017-01-04 12:49:00 +01:00
2017-01-04 Norm Jacobs <norm.jacobs@oracle.com>
PR gas/20992
* configure.tgt: Treat sparcv9 as sparc64.
Add support for the Q extension to the RISCV ISA. gas * config/tc-riscv.c (riscv_set_arch): Whitelist the "q" ISA extension. (riscv_after_parse_args): Set FLOAT_ABI_QUAD when the Q ISA is enabled and no other ABI is specified. include * opcode/riscv-opc.h: Add support for the "q" ISA extension. opcodes * riscv-opc.c (riscv-opcodes): Add support for the "q" ISA extension. * riscv-opcodes/all-opcodes: Likewise.
2017-01-03 18:42:01 +01:00
2017-01-03 Kito Cheng <kito.cheng@gmail.com>
* config/tc-riscv.c (riscv_set_arch): Whitelist the "q" ISA
extension.
(riscv_after_parse_args): Set FLOAT_ABI_QUAD when the Q ISA is
enabled and no other ABI is specified.
Fix PRU GAS for 32-bit hosts The PRU GAS port I originally submitted does not build on 32bit hosts. This patch fixes it by aligning md_number_to_chars's definition with the global declaration in tc.h. Here is the original bug report I got: https://github.com/rcn-ee/repos/pull/23#issuecomment-269915175 * config/tc-pru.c (md_number_to_chars): Fix parameter to be valueT, as declared in tc.h. (md_apply_fix): Fix to work on 32-bit hosts. Signed-off-by: Dimitar Dimitrov <dimitar@dinux.eu>
2017-01-02 17:20:21 +01:00
2017-01-03 Dimitar Dimitrov <dimitar@dinux.eu>
* config/tc-pru.c (md_number_to_chars): Fix parameter to be
valueT, as declared in tc.h.
(md_apply_fix): Fix to work on 32-bit hosts.
Update year range in copyright notice of all files.
2017-01-02 04:36:43 +01:00
2017-01-02 Alan Modra <amodra@gmail.com>
Update year range in copyright notice of all files.
ChangeLog rotation
2017-01-02 04:25:05 +01:00
For older changes see ChangeLog-2016
New 2016 binutils ChangeLog files Note that this does not create bfd/doc/ChangeLog, */testsuite/ChangeLog and include/*/ChangeLog files.
2016-01-01 11:44:31 +01:00
ChangeLog rotation
2017-01-02 04:25:05 +01:00
Copyright (C) 2017 Free Software Foundation, Inc.
New 2016 binutils ChangeLog files Note that this does not create bfd/doc/ChangeLog, */testsuite/ChangeLog and include/*/ChangeLog files.
2016-01-01 11:44:31 +01:00
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