Andrew Sadek <andrew.sadek.se@gmail.com>
A new implemented feature in GCC Microblaze that allows Position
Independent Code to run using Data Text Relative addressing instead
of using Global Offset Table.
Its aim was to make 'PIC' more efficient and flexible as elf size
excess performance overhead were noticed when using GOT due to the
indirect addressing.
include/ChangeLog:
* bfdlink.h (Add flag): Add new flag @ 'bfd_link_info' struct.
* elf/microblaze.h (Add 3 new relocations):
R_MICROBLAZE_TEXTPCREL_64, R_MICROBLAZE_TEXTREL_64
and R_MICROBLAZE_TEXTREL_32_LO for relax function.
bfd/ChangeLog:
* bfd/reloc.c (2 new BFD relocations):
BFD_RELOC_MICROBLAZE_64_TEXTPCREL &
BFD_RELOC_MICROBLAZE_64_TEXTPCREL
* bfd/bfd-in2.h: Regenerate
* bfd/libbfd.h: Regenerate
* bfd/elf32-microblaze.c (Handle new relocs): define 'HOWTO' of 3
new relocs and handle them in both relocate and relax functions.
(microblaze_elf_reloc_type_lookup): add mapping between for new
bfd relocs.
(microblaze_elf_relocate_section): Handle new relocs in case of
elf relocation.
(microblaze_elf_relax_section): Handle new relocs for elf relaxation.
gas/ChangeLog:
* gas/config/tc-microblaze.c (Handle new relocs directives in
assembler): Handle new relocs from compiler output.
(imm_types): add new imm types for data text relative addressing
TEXT_OFFSET, TEXT_PC_OFFSET
(md_convert_frag): conversion for BFD_RELOC_MICROBLAZE_64_TEXTPCREL,
BFD_RELOC_MICROBLAZE_64_TEXTPCREL
(md_apply_fix): apply fix for BFD_RELOC_MICROBLAZE_64_TEXTPCREL,
BFD_RELOC_MICROBLAZE_64_TEXTPCREL
(md_estimate_size_before_relax): estimate size for
BFD_RELOC_MICROBLAZE_64_TEXTPCREL,
BFD_RELOC_MICROBLAZE_64_TEXTPCREL
(tc_gen_reloc): generate relocations for
BFD_RELOC_MICROBLAZE_64_TEXTPCREL,
BFD_RELOC_MICROBLAZE_64_TEXTPCREL
ld/ChangeLog:
* ld/lexsup.c (Add 2 ld options):
(ld_options): add disable-multiple-abs-defs @ 'ld_options' array
(parse_args): parse new option and pass flag to 'link_info' struct.
* ld/ldlex.h (Add enum): add new enum @ 'option_values' enum.
* ld/ld.texinfo (Add new option): Add description for
'disable-multiple-abs-defs'
* ld/main.c: Initialize flags with false @ 'main'. Handle
disable-multiple-abs-defs @ 'mutiple_definition'.
PR 23054
* cond.c (s_ifsef): Replace use of obstack_copy with obstack_alloc
followed by memcpy.
(s_if, s_ifb, s_ifc, s_ifeqs): Likewise.
* obj-elf.c (elf_adjust_symtab): Check for local symbols before
attempting to dereference the sy_next field of a symbol.
* stabs.c (get_stab_string_offset): Fail if there is no string
following the stab directive.
Since only the first 32 bits of input operand are used for tpause and
umwait, the REX.W bit is skipped. Both 32-bit registers and 64-bit
registers are allowed.
gas/
* testsuite/gas/i386/x86-64-waitpkg.s: Add 32-bit registers
tests for tpause and umwait.
* testsuite/gas/i386/x86-64-waitpkg-intel.d: Updated.
* testsuite/gas/i386/x86-64-waitpkg.d: Likewise.
opcodes/
* i386-dis.c (prefix_table): Replace Em with Edq on tpause and
umwait.
* i386-opc.tbl: Allow 32-bit registers for tpause and umwait in
64-bit mode.
* i386-tbl.h: Regenerated.
config/plugins.m4 has
if test "$plugins" = "yes"; then
AC_SEARCH_LIBS([dlopen], [dl])
fi
Plugin uses dlsym, but libasan.so only intercepts dlopen, not dlsym:
[hjl@gnu-tools-1 binutils-text]$ nm -D /lib64/libasan.so.4| grep " dl"
0000000000038580 W dlclose
U dl_iterate_phdr
000000000004dc50 W dlopen
U dlsym
U dlvsym
[hjl@gnu-tools-1 binutils-text]$
Testing dlopen for libdl leads to false negative when -fsanitize=address
is used. It results in link failure:
../bfd/.libs/libbfd.a(plugin.o): undefined reference to symbol 'dlsym@@GLIBC_2.16'
dlsym should be used to check if libdl is needed for plugin.
bfd/
PR gas/22318
* configure: Regenerated.
binutils/
PR gas/22318
* configure: Regenerated.
gas/
PR gas/22318
* configure: Regenerated.
gprof/
PR gas/22318
* configure: Regenerated.
ld/
PR gas/22318
* configure: Regenerated.
"vex" has many fields to control how to decode an instruction. Clear
all fields in "vex" before decoding an instruction to avoid using values
left from the previous instruction.
gas/
PR binutils/23025
* testsuite/gas/i386/prefix.s: Add tests for vcvtpd2dq with
VEX and EVEX prefixes.
* testsuite/gas/i386/prefix.d: Updated.
opcodes/
PR binutils/23025
* i386-dis.c (get_valid_dis386): Don't set vex.prefix nor vex.w
to 0.
(print_insn): Clear vex instead of vex.evex.
This patch adds the following relocation support into binutils gas.
BFD_RELOC_AARCH64_TLSLE_LDST16_TPREL_LO12,
BFD_RELOC_AARCH64_TLSLE_LDST16_TPREL_LO12_NC,
BFD_RELOC_AARCH64_TLSLE_LDST32_TPREL_LO12,
BFD_RELOC_AARCH64_TLSLE_LDST32_TPREL_LO12_NC,
BFD_RELOC_AARCH64_TLSLE_LDST64_TPREL_LO12,
BFD_RELOC_AARCH64_TLSLE_LDST64_TPREL_LO12_NC,
BFD_RELOC_AARCH64_TLSLE_LDST8_TPREL_LO12,
BFD_RELOC_AARCH64_TLSLE_LDST8_TPREL_LO12_NC.
Those relocations includes both ip64 and ilp32 variant.
It again can be inferred from other information.
The vpopcntd templates all need to have Dword added to their memory
operands; the lack thereof was actually a bug preventing certain Intel
syntax code to assemble, so test cases get extended.
In the course of folding their patterns (possible now that the pointless
and partly even bogus VecESize are no longer in the way) I've noticed
that vcvt*2usi, other than their vcvt*2si counterparts, don't allow for
any suffixes. As that is supposedly intentional, make the disassembler
consistently omit suffixes for all to-scalar-int conversion insns.
Since they're shorter to encode, the 0xa0...0xa3 encodings are preferred
for moves between accumulator and absolute address outside of 64-bit
mode. With HLE release semantics this encoding is unsupported though,
with the assembler raising an error. The operation is valid though, we
merely need to pick the longer encoding in that case.
The wrong placement of the Load attribute in the templates prevented
this from working. The disassembler also didn't handle this consistently
with other similar dual-encoding insns.
While many templates allowing multiple suitably matching XMM/YMM/ZMM
operand sizes can be folded, a few need to be split in order to not
wrongly accept "xmmword ptr" operands when only XMM registers are
permitted (and memory operands are more narrow). Add a test case
validating this.
Since the addition of pseudo prefixes changed how the scrubber treats
'{', we need to explicitly strip whitespace in check_VecOperations ().
* config/tc-i386.c (check_VecOperations): Strip whitespace.
* testsuite/gas/i386/optimize-1.s: Add whitespaces before
{%k7} and {z},
* testsuite/gas/i386/x86-64-optimize-2.s: Likewise.
We can optimize AVX512 instructions with EVEX128 only if AVX512VL is
enabled:
1. Instruction is an AVX512VL instruction. Or
2. AVX512VL is enabled explicitly by -march=+avx512vl/".arch .avx512vl".
We should optimize EVEX instructions with EVEX128 encoding when pseudo
{evex} prefix is used.
* config/tc-i386.c (set_cpu_arch): Set cpu_arch_isa_flags.
(md_parse_option): Likewise.
(optimize_encoding): Check i.tm.cpu_flags and cpu_arch_isa_flags
for cpuavx512vl instead of cpu_arch_flags. Optimize EVEX with
EVEX128 when EVEX encoding is required.
* testsuite/gas/i386/i386.exp: Run optimize-4, optimize-5,
x86-64-optimize-5 and x86-64-optimize-6.
* testsuite/gas/i386/optimize-1.d: Updated.
* testsuite/gas/i386/x86-64-optimize-2.d: Likewise.
* testsuite/gas/i386/optimize-4.d: New file.
* testsuite/gas/i386/optimize-4.s: Likewise.
* testsuite/gas/i386/optimize-5.d: Likewise.
* testsuite/gas/i386/optimize-5.s: Likewise.
* testsuite/gas/i386/x86-64-optimize-5.d: Likewise.
* testsuite/gas/i386/x86-64-optimize-5.s: Likewise.
* testsuite/gas/i386/x86-64-optimize-6.d: Likewise.
* testsuite/gas/i386/x86-64-optimize-6.s: Likewise.
"clr reg" is an alias of "xor reg, reg". We can encode "clr reg64" as
"xor reg32, reg32".
gas/
* config/tc-i386.c (optimize_encoding): Also encode "clr reg64"
as "xor reg32, reg32".
* testsuite/gas/i386/x86-64-optimize-1.s: Add "clr reg64" tests.
* testsuite/gas/i386/x86-64-optimize-1.d: Updated.
opcodes/
* i386-opc.tbl: Add Optimize to clr.
* i386-tbl.h: Regenerated.
The differences between some of the register and memory forms of the
same insn often don't really require the templates to be separate. For
example, Disp8MemShift is simply irrelevant to register forms. Fold
these as far as possible, and also fold register-only forms. Further
folding is possible, but needs other prereq work done first.
A note regarding EVEXDYN: This is intended to be used only when no other
properties of the template would make is_evex_encoding() return true. In
all "normal" cases I think it is preferable to omit this indicator, to
keep the table half way readable.
Their memory forms were bogusly using VexLWP instead of VexNDD. Adjust
VexNDD handling to cope with these, allowing their register and memory
forms to be folded.
They aren't really useful (anymore?): The conflicting operand size check
isn't applicable to any insn validly using respective memory operand
sizes (and if they're used wrongly, another error would result), and the
logic in process_suffix() can be easily changed to work without them.
While re-structuring conditionals in process_suffix() also drop the
CMPXCHG8B special case in favor of a NoRex64 attribute in the opcode
table.
Some BMI/BMI2 insns allow their middle operands to be a memory one. In
such a case, matching register types between operands 0 and 1 as well as
1 and 2 won't help - operands 0 and 2 also need to be checked.
Make more obvious what the success and failure paths are, and in
particular that what used to be at the "skip" label can't be reached
by what used to be straight line code.
Just like for the AVX/AES and AVX/PCLMUL combinations, AVX/GFN,
AVX512F/GFNI, AVX512F/VAES, and AVX512F/PCLMUL need special handling to
deal with the pair of required checks specified in the templates.
fsub/fsubr/fsubp/fsubrp as well as fdiv/fdivr/fdivp/fdivrp disassembly
should match (a) the Intel SDM and (b) respective input fed to gas (both
of course with the exception of when we intentionally convert bogus
insns, accompanied by a warning).
Drop "second": For one there's no other source register (the other
source operand is in memory), and in Intel syntax such numbering would
also be wrong.
Take the opportunity and also
- properly place declarations ahead of statements
- use %u format for unsigned int arguments
- fix indentation
This requires a change to ModR/M handling: Recording of displacement
types must not discard operand size information. Change the respective
code to alter only .disp<N>.
Oops, not tested well enough. -mpower9 sets all the PPC_OPCODE_POWERn
for n <= 9.
* config/tc-ppc.c (ppc_handle_align): Correct last patch. Really
don't emit a group terminating nop for power9. Simplify cpu
tests.
Power9 doesn't have a group terminating nop, so we may as well emit a
normal nop for power9. Not that it matters a great deal, I believe
ori 2,2,0 will be treated exactly as ori 0,0,0 by the hardware.
* config/tc-ppc.c (ppc_handle_align): Don't emit a group
terminating nop for power9.
xcoff (32-bit) objdump accepted but ignored -M options unless
-mpowerpc was also given. This patch fixes that, leaving the default
as -Mpwr for xcoff. I've also enabled more tests for xcoff targets.
binutils/
* configure.ac: Add objdump_private_desc_xcoff for rs6000.
* configure: Regenerate.
gas/
* testsuite/gas/ppc/aix.exp: Run for rs6000 too.
* testsuite/gas/ppc/ppc.exp: Run more tests for non-ELF targets.
* testsuite/gas/ppc/machine.d: Don't run for PE targets.
opcodes/
* disassemble.c (disassembler): Use bfd_arch_powerpc entry for
bfd_arch_rs6000.
* disassemble.h (print_insn_rs6000): Delete.
* ppc-dis.c (powerpc_init_dialect): Handle rs6000.
(disassemble_init_powerpc): Call powerpc_init_dialect for rs6000.
(print_insn_rs6000): Delete.
Commit 4d354d8b89 introduced a NULL
pointer dereference by replacing a pointer assignment by a pointer
dereference assignment without adding a NULL pointer check. This patch
fixes it.
2018-03-02 Thomas Preud'homme <thomas.preudhomme@arm.com>
gas/
* config/tc-arm.c (md_begin): Add NULL pointer check before
dereferencing march_ext_opt.
I've always found the code in ARM backend of gas to control what
CPU/architecture and FPU are selected by the user and to support
autodetection of features complex and confusing. Chief among the
issues I have with that code is the lack of comments to explain
the meaning of the various variables. This patch addresses that
and much more:
- add comments to explain meaning of all arm_feature_set variables
- keep track of currently selected CPU, extensions and FPU in a separate
set of new variables
- make naming of variable more consistent
- remove dead code
- simplify handling of extensions
The overall approach is as follows:
* restrict m*_opt variable to hold the feature bits of the
corresponding mcpu/march/mfpu command-line options
* record selected CPU, extensions and FPU in new selected_* during
md_begin
* whenever a .cpu/.arch/.arch_extension/.fpu directive is met, update
the corresponding selected_* variables (eg. selected_arch, then
selected_cpu for a .cpu or .arch directive) and then finally
cpu_variant from them
* pass extension feature set pointer by value to arm_parse_extension
since it's only ever called from arm_parse_cpu and arm_parse_arch
which allocate the extension feature set themselves
* likewise, remove allocation from s_arm_arch_extension since the use
of arm_feature_set structure for selected_ext rather than a pointer
alleviate the need for it
* in autodetection mode, only set all CPU fits in cpu_variant but leave
selected_cpu* variables unset
* in md_begin, remove dead "else if" to set a default FPU when no FPU
was selected. Setting a default FPU based on CPU as did the code
before it turn dead should be based on the default FPU field of the
CPU and architecture table as will be done in a separate patch. Logic
is wrong anyway since it sets VFP2 as default FPU for Armv6-M and
Armv7-M
Hopefully that should be enough to understand the change but if not feel
free to ask questions about the patch. While I believe the new code is
easier to understand, it remains complex and the old one was even more
complex so the change is difficult to understand.
2018-03-01 Thomas Preud'homme <thomas.preudhomme@arm.com>
gas/
* config/tc-arm.c (cpu_variant, arm_arch_used, thumb_arch_used,
legacy_cpu, legacy_fpu, mcpu_cpu_opt, dyn_mcpu_ext_opt,
mcpu_fpu_opt, march_cpu_opt, dyn_march_ext_opt, march_fpu_opt,
mfpu_opt, object_arch, selected_cpu): Comment meaning of variables.
(dyn_mcpu_ext_opt): Also rename into ...
(mcpu_ext_opt): This.
(dyn_march_ext_opt): Also rename into ...
(march_ext_opt): This.
(object_arch): Also rename into ...
(selected_object_arch): This and make it a plain arm_feature_set
structure.
(selected_arch, selected_ext, selected_fpu): New static variables.
(mark_feature_used): Fix comments, feature is marked as used iff it is
currently allowed.
(do_bx): Adapt to change in name and type of object_arch.
(md_begin): Set selected_arch rather than mcpu_cpu_opt, selected_ext
rather than dyn_mcpu_ext_opt and selected_fpu rather than mfpu_opt.
Remove dead code to set default FPU if architecture version is greater
than 5. Set all CPU bits of cpu_variant directly in autodection
leaving mcpu_cpu_opt, selected_arch and selected_cpu unset.
(arm_parse_extension): Take extension feature set pointer parameter by
value rather than by pointer. Remove allocation code. Adapt code
accordingly.
(arm_parse_cpu): Adapt to variable renaming and changes in
arm_parse_extension () signature.
(arm_parse_arch): Likewise.
(aeabi_set_public_attributes): Also set selected_arch and selected_ext
in addition to selected_cpu. Set flags_arch and flags_ext from them
instead of selected_cpu. Adapt to variables renaming and type change.
(arm_md_post_relax): Adapt to variable renaming.
(s_arm_cpu): Set selcted_cpu_cpu and selected_ext instead of
mcpu_cpu_opt and dyn_mcpu_ext_opt. Set selected_cpu from them and
cpu_variant from selected_cpu and selected_fpu.
(s_arm_arch): Likewise.
(s_arm_object_arch): Adapt to variable renaming.
(s_arm_arch_extension): Use ARM_CPU_IS_ANY instead of checking feature
set against arm_any. Check selected_arch rather than *mcpu_cpu_opt.
Set selected_ext rather than *dyn_mcpu_ext_opt and remove allocation
code.
(s_arm_fpu): Set selected_fpu instead of mfpu_opt. Set all CPU feature
bits if in autodetection mode.
On x86, some instructions have alternate shorter encodings:
1. When the upper 32 bits of destination registers of
andq $imm31, %r64
testq $imm31, %r64
xorq %r64, %r64
subq %r64, %r64
known to be zero, we can encode them without the REX_W bit:
andl $imm31, %r32
testl $imm31, %r32
xorl %r32, %r32
subl %r32, %r32
This optimization is enabled with -O, -O2 and -Os.
2. Since 0xb0 mov with 32-bit destination registers zero-extends 32-bit
immediate to 64-bit destination register, we can use it to encode 64-bit
mov with 32-bit immediates. This optimization is enabled with -O, -O2
and -Os.
3. Since the upper bits of destination registers of VEX128 and EVEX128
instructions are extended to zero, if all bits of destination registers
of AVX256 or AVX512 instructions are zero, we can use VEX128 or EVEX128
encoding to encode AVX256 or AVX512 instructions. When 2 source
registers are identical, AVX256 and AVX512 andn and xor instructions:
VOP %reg, %reg, %dest_reg
can be encoded with
VOP128 %reg, %reg, %dest_reg
This optimization is enabled with -O2 and -Os.
4. 16-bit, 32-bit and 64-bit register tests with immediate may be
encoded as 8-bit register test with immediate. This optimization is
enabled with -Os.
This patch does:
1. Add {nooptimize} pseudo prefix to disable instruction size
optimization.
2. Add optimize to i386_opcode_modifier to tell assembler that encoding
of an instruction may be optimized.
gas/
PR gas/22871
* NEWS: Mention -O[2|s].
* config/tc-i386.c (_i386_insn): Add no_optimize.
(optimize): New.
(optimize_for_space): Likewise.
(fits_in_imm7): New function.
(fits_in_imm31): Likewise.
(optimize_encoding): Likewise.
(md_assemble): Call optimize_encoding to optimize encoding.
(parse_insn): Handle {nooptimize}.
(md_shortopts): Append "O::".
(md_parse_option): Handle -On.
* doc/c-i386.texi: Document -O0, -O, -O1, -O2 and -Os as well
as {nooptimize}.
* testsuite/gas/cfi/cfi-x86_64.d: Pass -O0 to assembler.
* testsuite/gas/i386/ilp32/cfi/cfi-x86_64.d: Likewise.
* testsuite/gas/i386/i386.exp: Run optimize-1, optimize-2,
optimize-3, x86-64-optimize-1, x86-64-optimize-2,
x86-64-optimize-3 and x86-64-optimize-4.
* testsuite/gas/i386/optimize-1.d: New file.
* testsuite/gas/i386/optimize-1.s: Likewise.
* testsuite/gas/i386/optimize-2.d: Likewise.
* testsuite/gas/i386/optimize-2.s: Likewise.
* testsuite/gas/i386/optimize-3.d: Likewise.
* testsuite/gas/i386/optimize-3.s: Likewise.
* testsuite/gas/i386/x86-64-optimize-1.s: Likewise.
* testsuite/gas/i386/x86-64-optimize-1.d: Likewise.
* testsuite/gas/i386/x86-64-optimize-2.d: Likewise.
* testsuite/gas/i386/x86-64-optimize-2.s: Likewise.
* testsuite/gas/i386/x86-64-optimize-3.d: Likewise.
* testsuite/gas/i386/x86-64-optimize-3.s: Likewise.
* testsuite/gas/i386/x86-64-optimize-4.d: Likewise.
* testsuite/gas/i386/x86-64-optimize-4.s: Likewise.
opcodes/
PR gas/22871
* i386-gen.c (opcode_modifiers): Add Optimize.
* i386-opc.h (Optimize): New enum.
(i386_opcode_modifier): Add optimize.
* i386-opc.tbl: Add "Optimize" to "mov $imm, reg",
"sub reg, reg/mem", "test $imm, acc", "test $imm, reg/mem",
"and $imm, acc", "and $imm, reg/mem", "xor reg, reg/mem",
"movq $imm, reg" and AVX256 and AVX512 versions of vandnps,
vandnpd, vpandn, vpandnd, vpandnq, vxorps, vxorpd, vpxor,
vpxord and vpxorq.
* i386-tbl.h: Regenerated.
This patch makes GAS emit a warning when trying to assemble the Armv8.2
FP16 instructions VMOVX and VINS with condition codes. The Armv8-A
Reference Manual specifies these instructions without conditional codes
and says that if they are found in an IT block that they are CONSTRAINED
UNPREDICABLE.
gas/ChangeLog:
2018-02-22 Andre Vieira <andre.simoesdiasvieira@arm.com>
* config/tc-arm.c (do_neon_movhf): If conditional error out when in arm
mode and emit warning in thumb mode.
* testsuite/gas/arm/armv8-2-fp16-scalar-bad.s: Add new tests.
* testsuite/gas/arm/armv8-2-fp16-scalar-bad.l: Idem.
Add {rex} pseudo prefix to generate a REX byte for integer and legacy
vector instructions if possible. Note that this differs from the rex
prefix which generates REX prefix unconditionally.
gas/
* config/tc-i386.c (_i386_insn): Add rex_encoding.
(md_assemble): When i.rex_encoding is true, generate a REX byte
if possible.
(parse_insn): Set i.rex_encoding for {rex}.
* doc/c-i386.texi: Document {rex}.
* testsuite/gas/i386/x86-64-pseudos.s: Add {rex} tests.
* testsuite/gas/i386/x86-64-pseudos.d: Updated.
opcodes/
* i386-opc.tbl: Add {rex},
* i386-tbl.h: Regenerated.
Add a pair of MIPS16 branch tests to verify correct R_MIPS16_PC16_S1
relocation generation for cross-section references in a single source.
This complements commit c9775dde32 ("MIPS16: Add R_MIPS16_PC16_S1
branch relocation support").
gas/
* testsuite/gas/mips/mips16-branch-reloc-4.d: New test.
* testsuite/gas/mips/mips16-branch-reloc-5.d: New test.
* testsuite/gas/mips/mips16-branch-reloc-4.s: New test source.
* testsuite/gas/mips/mips16-branch-reloc-5.s: New test source.
* testsuite/gas/mips/mips.exp: Run the new tests.
Literal movement code may grow auto litpool so big that it won't be
possible to jump around it. Limit the size of auto litpools by 1/2 of
the jump range.
gas/
2018-02-20 Max Filippov <jcmvbkbc@gmail.com>
* config/tc-xtensa.c (struct litpool_frag): Add new field
literal_count.
(MAX_AUTO_POOL_LITERALS, MAX_EXPLICIT_POOL_LITERALS)
(MAX_POOL_LITERALS): New macro definitions.
(auto_litpool_limit): Initialize to 0.
(md_parse_option): Set auto_litpool_limit in the presence of
--auto-litpools option.
(xtensa_maybe_create_literal_pool_frag): Zero-initialize
literal_count field.
(xg_find_litpool): New function. Make sure that found literal
pool size is within the limit.
(xtensa_move_literals): Extract literal pool search code into
the new function.
* testsuite/gas/xtensa/all.exp: Add auto-litpools-2 test.
* testsuite/gas/xtensa/auto-litpools-2.d: New file.
* testsuite/gas/xtensa/auto-litpools-2.s: New file.
* testsuite/gas/xtensa/auto-litpools.d: Fix up changed
addresses.
* testsuite/gas/xtensa/auto-litpools.s: Change literal value so
that objdump doesn't get out of sync.
Documentation for .arch_extension says it accepts the same architectural
extensions as those accepted by -mcpu. Given the name and the fact that
-march for obvious reason also accept the same extensions, I believe
it's worth mentioning that it accepts the same extensions as both
-march and -mcpu. This commit addresses that.
2018-02-20 Thomas Preud'homme <thomas.preudhomme@arm.com>
gas/
* doc/c-arm.texi (.arch_extension): Mention extensions it accepts are
also the same as -march.
Implement the '.nop SIZE[, CONTROL]' assembler directive, which emits
SIZE bytes filled with no-op instructions. SIZE is absolute expression.
The optional CONTROL byte controls how no-op instructions should be
generated. If the comma and @var{control} are omitted, CONTROL is
assumed to be zero.
For Intel 80386 and AMD x86-64 targets, CONTROL byte specifies the size
limit of a single no-op instruction. The valid values of CONTROL byte
are between 0 and 8 for 16-bit mode, between 0 and 10 for 32-bit mode,
between 0 and 11 for 64-bit mode. When 0 is used, the no-op size limit
is set to the maximum supported size.
2 new relax states, rs_space_nop and rs_fill_nop, are added to enum
_relax_state, which are similar to rs_space and rs_fill, respectively,
but they fill with no-op instructions, instead of a single byte. A
target backend must override the default md_generate_nops to generate
proper no-op instructions. Otherwise, an error of unimplemented .nop
directive will be issued whenever .nop directive is used.
* NEWS: Mention .nop directive.
* as.h (_relax_state): Add rs_space_nop and rs_fill_nop.
* read.c (potable): Add .nop.
(s_nop): New function.
* read.h (s_nop): New prototype.
* write.c (cvt_frag_to_fill): Handle rs_space_nop and
rs_fill_nop.
(md_generate_nops): New function.
(relax_segment): Likewise.
(write_contents): Use md_generate_nops for rs_fill_nop.
* config/tc-i386.c (alt64_11): New.
(alt64_patt): Likewise.
(md_convert_frag): Handle rs_space_nop.
(i386_output_nops): New function.
(i386_generate_nops): Likewise.
(i386_align_code): Call i386_output_nops.
* config/tc-i386.h (i386_generate_nops): New.
(md_generate_nops): Likewise.
* doc/as.texinfo: Document .nop directive.
* testsuite/gas/i386/i386.exp: Run .nop directive tests.
* testsuite/gas/i386/nop-1.d: New file.
* testsuite/gas/i386/nop-1.s: Likewise.
* testsuite/gas/i386/nop-2.d: Likewise.
* testsuite/gas/i386/nop-2.s: Likewise.
* testsuite/gas/i386/nop-3.d: Likewise.
* testsuite/gas/i386/nop-3.s: Likewise.
* testsuite/gas/i386/nop-4.d: Likewise.
* testsuite/gas/i386/nop-4.s: Likewise.
* testsuite/gas/i386/nop-5.d: Likewise.
* testsuite/gas/i386/nop-5.s: Likewise.
* testsuite/gas/i386/nop-6.d: Likewise.
* testsuite/gas/i386/nop-6.s: Likewise.
* testsuite/gas/i386/nop-bad-1.l: Likewise.
* testsuite/gas/i386/nop-bad-1.s: Likewise.
* testsuite/gas/i386/x86-64-nop-1.d: Likewise.
* testsuite/gas/i386/x86-64-nop-2.d: Likewise.
* testsuite/gas/i386/x86-64-nop-3.d: Likewise.
* testsuite/gas/i386/x86-64-nop-4.d: Likewise.
* testsuite/gas/i386/x86-64-nop-5.d: Likewise.
* testsuite/gas/i386/x86-64-nop-6.d: Likewise.
The build attribute number for Armv8.4-A is currently incorrectly set to that of Armv8-M.
This patch fixes that by setting it as part of the Armv8-A family and adds a test for it.
gas/
2018-02-15 Tamar Christina <tamar.christina@arm.com>
* config/tc-arm.c (cpu_arch_ver): Renumber ARM_ARCH_V8_4A.
* testsuite/gas/arm/attr-march-armv8_4-a.d: New.
For jumps requiring multiple trampolines trampoline placement code may
place multiple sequential trampolines into the same frag. Don't do that.
gas/
2018-02-13 Max Filippov <jcmvbkbc@gmail.com>
* config/tc-xtensa.c (xg_find_best_trampoline): Skip trampoline
frag that contains source address.
PR 22773
* config/tc-arm.c (md_apply_fix): Test Rn field of Thumb ORR
instruction before assuming that it is a MOV instruction.
* testsuite/gas/arm/pr22773.s: New test.
* testsuite/gas/arm/pr22773.d: New test driver.
* testsuite/gas/arm/pr22773.l: New expected output.
Since there is no need to prepare for PLT branch on x86-64, generate
R_X86_64_PLT32, instead of R_X86_64_PC32, if possible, which can be
used as a marker for 32-bit PC-relative branches.
To compile Linux kernel, this patch:
From: "H.J. Lu" <hjl.tools@gmail.com>
Subject: [PATCH] x86: Treat R_X86_64_PLT32 as R_X86_64_PC32
On i386, there are 2 types of PLTs, PIC and non-PIC. PIE and shared
objects must use PIC PLT. To use PIC PLT, you need to load
_GLOBAL_OFFSET_TABLE_ into EBX first. There is no need for that on
x86-64 since x86-64 uses PC-relative PLT.
On x86-64, for 32-bit PC-relative branches, we can generate PLT32
relocation, instead of PC32 relocation, which can also be used as
a marker for 32-bit PC-relative branches. Linker can always reduce
PLT32 relocation to PC32 if function is defined locally. Local
functions should use PC32 relocation. As far as Linux kernel is
concerned, R_X86_64_PLT32 can be treated the same as R_X86_64_PC32
since Linux kernel doesn't use PLT.
is needed. It is available on hjl/plt32/master branch at
https://github.com/hjl-tools/linux
bfd/
PR gas/22791
* elf64-x86-64.c (is_32bit_relative_branch): Removed.
(elf_x86_64_relocate_section): Check PIC relocations in PIE.
Remove is_32bit_relative_branch usage. Disallow PC32 reloc
against protected function in shared object.
gas/
PR gas/22791
* config/tc-i386.c (need_plt32_p): New function.
(output_jump): Generate BFD_RELOC_X86_64_PLT32 if possible.
(md_estimate_size_before_relax): Likewise.
* testsuite/gas/i386/reloc64.d: Updated.
* testsuite/gas/i386/x86-64-jump.d: Likewise.
* testsuite/gas/i386/x86-64-mpx-branch-1.d: Likewise.
* testsuite/gas/i386/x86-64-mpx-branch-2.d: Likewise.
* testsuite/gas/i386/x86-64-relax-2.d: Likewise.
* testsuite/gas/i386/x86-64-relax-3.d: Likewise.
* testsuite/gas/i386/ilp32/reloc64.d: Likewise.
* testsuite/gas/i386/ilp32/x86-64-branch.d: Likewise.
ld/
PR gas/22791
* testsuite/ld-x86-64/mpx1c.rd: Updated.
* testsuite/ld-x86-64/pr22791-1.err: New file.
* testsuite/ld-x86-64/pr22791-1a.c: Likewise.
* testsuite/ld-x86-64/pr22791-1b.s: Likewise.
* testsuite/ld-x86-64/pr22791-2.rd: Likewise.
* testsuite/ld-x86-64/pr22791-2a.s: Likewise.
* testsuite/ld-x86-64/pr22791-2b.c: Likewise.
* testsuite/ld-x86-64/pr22791-2c.s: Likewise.
* testsuite/ld-x86-64/x86-64.exp: Run PR ld/22791 tests.
Correct a duplicate `Loongson-3A tests' GAS test name introduced with
commit 9867540240 ("Add Loongson3A specific instructions"),
<https://sourceware.org/ml/binutils/2010-12/msg00447.html>, shared
between gas/testsuite/gas/mips/loongson-3a.d and
gas/testsuite/gas/mips/loongson-3a-2.d.
gas/
* testsuite/gas/mips/loongson-3a-2.d: Rename test.
Correct a commit 2d6dda7161 ("MIPS/BFD: Correctly report unsupported
`.reginfo' section size") issue and avoid a GAS test failure:
regexp_diff match failure
regexp "^.*: Incorrect `\.reginfo' section size; expected 24, got 28$"
line "../as-new: dump.o: Incorrect `.reginfo' section size; expected 24, got 32"
FAIL: MIPS assembled .reginfo section size (n32)
on MIPS targets other than bare-metal ones. The reason for this failure
is section padding to alignment, done in `size_seg'. For n32 `.reginfo'
the section alignment is set to 3, and therefore the section is padded
to a multiple of 8, except for bare-metal targets, for which padding is
unconditionally disabled in `md_section_align'.
Use `--no-pad-sections' then to disable padding for all targets, so that
the size of `.reginfo' is always the same, matching the message pattern.
gas/
* testsuite/gas/mips/reginfo-2-n32.d: Add `--no-pad-sections' to
`as' flags.
The instruction encoding for the MIPS r6 sigrie instruction seems to be
incorrect. It's currently 0x4170xxxx (which overlaps with ei, di, evp,
and dvp), but should be 0x0417xxxx. See ISA reference[1][2].
References:
[1] "MIPS Architecture for Programmers Volume II-A: The MIPS32
Instruction Set Manual", Imagination Technologies, Inc., Document
Number: MD00086, Revision 6.06, December 15, 2016, Table A.4 "MIPS32
REGIMM Encoding of rt Field", p. 452
[2] "MIPS Architecture For Programmers Volume II-A: The MIPS64
Instruction Set Reference Manual", Imagination Technologies, Inc.,
Document Number: MD00087, Revision 6.06, December 15, 2016, Table
A.4 "MIPS64 REGIMM Encoding of rt Field", p. 581
opcodes/
* mips-opc.c (mips_builtin_opcodes): Correct "sigrie" encoding.
gas/
* testsuite/gas/mips/r6.d: Update for "sigrie" encoding fix.
* testsuite/gas/mips/r6-n32.d: Likewise.
* testsuite/gas/mips/r6-n64.d: Likewise.
Checks for insn alignment were hopelessly confused when misaligned
data starts a new frag. The real-world testcase happened to run out
of frag space in the middle of emitting a trace-back table via
something like:
.byte 0 /* VERSION=0 */
.byte 9 /* LANG=C++ */
.byte 34 /* Bits on: has_tboff, fp_present */
.byte 64 /* Bits on: name_present */
.byte 128 /* Bits on: stores_bc, FP_SAVED=0 */
.byte 0 /* Bits on: GP_SAVED=0 */
.byte 2 /* FIXEDPARMS=2 */
.byte 1 /* FLOATPARMS=0, parmsonstk */
.long 0
.long 768 /* tb_offset: 0x300 */
.hword 45 /* Function name length: 45 */
.long 0x334e5a5f
.long 0x31766f70
.long 0x65744932
.long 0x69746172
.long 0x7a5f6e6f
.long 0x64504533
.long 0x5f534e50
.long 0x72463431
.long 0x61746361
.long 0x74535f6c
.long 0x74637572
.byte 0x45
.byte 0
The trigger being those misaligned .long's output for the function
name. A most horrible way to output a string, especially considering
endian issues..
PR 22819
* config/tc-ppc.c (md_assemble): Rewrite insn alignment checking.
(ppc_frag_check): Likewise.
* testsuite/gas/ppc/misalign.d,
* testsuite/gas/ppc/misalign.l,
* testsuite/gas/ppc/misalign.s: New test.
* testsuite/gas/ppc/misalign2.d,
* testsuite/gas/ppc/misalign2.s: New test.
* testsuite/gas/ppc/ppc.exp: Run them.
Correct a commit f0531ed6a4 ("Compress loads/stores with implicit 0
offset.") regression and remove a `-Wshadow' compilation error:
cc1: warnings being treated as errors
.../gas/config/tc-riscv.c: In function 'riscv_handle_implicit_zero_offset':
.../gas/config/tc-riscv.c:1194: error: declaration of 'expr' shadows a global declaration
.../gas/expr.h:180: error: shadowed declaration is here
make[4]: *** [tc-riscv.o] Error 1
which for versions of GCC before 4.8 prevents GAS for RISC-V targets
from being built. See also GCC PR c/53066.
gas/
* config/tc-riscv.c (riscv_handle_implicit_zero_offset): Rename
`expr' parameter to `ep'.
Report an error when an unsupported `.reginfo' section size is found in
`_bfd_mips_elf_section_processing', removing an assertion that triggers
at elfxx-mips.c:7105 in GAS when assembling input like:
.section .reginfo
.word 0xdeadbeef
and in `objcopy --rename-section' when renaming an incorrectly sized
section to `.reginfo'.
bfd/
* elfxx-mips.c (_bfd_mips_elf_section_processing): For
SHT_MIPS_REGINFO sections don't assert the correct size and
report an error instead.
binutils/
* testsuite/binutils-all/mips/mips-reginfo.d: New test.
* testsuite/binutils-all/mips/mips-reginfo-n32.d: New test.
* testsuite/binutils-all/mips/mips-reginfo.s: New test source.
* testsuite/binutils-all/mips/mips.exp: Run the new tests.
gas/
* testsuite/gas/mips/reginfo-2.d: New test.
* testsuite/gas/mips/reginfo-2-n32.d: New test.
* testsuite/gas/mips/reginfo-2.l: New test stderr output.
* testsuite/gas/mips/reginfo-2.s: New test source.
* testsuite/gas/mips/mips.exp: Run the new tests.
The PR22714 testcase is such that the input buffer processed by
do_scrub_chars ends on this line
1: bug "Returning to usermode but unexpected PSR bits set?", \@
right at the backslash. (The line is part of a macro definition.)
The next input buffer then starts with '@' which starts a comment on
ARM, and the check for \@ fails due to to == tostart. Now it would be
possible to simply access to[-1] in this particular case, but that's
ugly, and to be absolutely safe from people deliberately trying to
crash gas we'd need the read.c:read_a_source_file buffer passed to
do_scrub_chars to have a single byte pad at the start.
PR 22714
* app.c (last_char): New static var.
(struct app_save): Add last_char field.
(app_push, app_pop): Handle it.
(do_scrub_chars): Use last_char in test for "\@". Set last_char.
The .dc.a directive has wrong size (32 bits) on SPARC 64-bit because
the assembler sets the correct BFD architecture only at the very end
of the processing and it's too late for the directive. It's fixed by
defining TARGET_MACH and making it return a sensible default value.
gas/
* config/tc-sparc.h (sparc_mach): Declare.
(TARGET_MACH): Define to above.
* config/tc-sparc.c (sparc_mach): New function.
(sparc_md_end): Minor tweak.
ld/
* testsuite/ld-elf/pr22450.d: Remove reference to SPARC64.
Michael Eager
Igor Tsimbalist
Nick Clifton
Alan Modra
H.J. Lu
John Darrington
Peter Bergner
Renlin Li
Jan Beulich
Jim Wilson
Thomas Preud'homme
Maciej W. Rozycki
Kuan-Lin Chen
Andre Simoes Dias Vieira
A. Wilcox
Max Filippov
Tamar Christina
Henry Wong
Eric Botcazou