gettext("") returns the header entry with meta information, not the
empty string.
* config/tc-arm.c (reg_expected_msgs[REG_TYPE_RNB]): Don't use
N_() on empty string.
CSRRW and CSRRWI always write CSR. CSRRS, CSRRC, CSRRSI and CSRRCI write CSR
when RS1 isn't zero. The CSR is read only if the [11:10] bits of CSR address
is 0x3. The read-only CSR can not be written by the CSR instructions.
gas/
* config/tc-riscv.c (riscv_ip): New boolean insn_with_csr to indicate
we are assembling instruction with CSR. Call riscv_csr_read_only_check
after parsing all arguments.
(enum csr_insn_type): New enum is used to classify the CSR instruction.
(riscv_csr_insn_type, riscv_csr_read_only_check): New functions. These
are used to check if we write a read-only CSR by the CSR instruction.
* testsuite/gas/riscv/priv-reg-fail-read-only-01.s: New testcase. Test
all CSR for the read-only CSR checking.
* testsuite/gas/riscv/priv-reg-fail-read-only-01.d: Likewise.
* testsuite/gas/riscv/priv-reg-fail-read-only-01.l: Likewise.
* testsuite/gas/riscv/priv-reg-fail-read-only-02.s: New testcase. Test
all CSR instructions for the read-only CSR checking.
* testsuite/gas/riscv/priv-reg-fail-read-only-02.d: Likewise.
* testsuite/gas/riscv/priv-reg-fail-read-only-02.l: Likewise.
Add new .option `csr-check/no-csr-check` and GAS option `-mcsr-check
/-mno-csr-check` to enbale/disable the CSR checking. Disable the CSR
checking by default.
gas/
* config/tc-riscv.c: Add new .option and GAS options to enbale/disable
the CSR checking. We disable the CSR checking by default.
(reg_lookup_internal): Check the `riscv_opts.csr_check`
before we doing the CSR checking.
* doc/c-riscv.texi: Add description for the new .option and assembler
options.
* testsuite/gas/riscv/priv-reg-fail-fext.d: Add `-mcsr-check` to enable
the CSR checking.
* testsuite/gas/riscv/priv-reg-fail-rv32-only.d: Likewise.
According to the riscv privilege spec, some CSR are only valid when rv32 or
the specific extension is set. We extend the DECLARE_CSR and DECLARE_CSR_ALIAS
to record more informaton we need, and then check whether the CSR is valid
according to these information. We report warning message when the CSR is
invalid, so we have a choice between error and warning by --fatal-warnings
option. Also, a --no-warn/-W option is used to turn the warnings off, if
people don't want the warnings.
gas/
* config/tc-riscv.c (enum riscv_csr_class): New enum. Used to decide
whether or not this CSR is legal in the current ISA string.
(struct riscv_csr_extra): New structure to hold all extra information
of CSR.
(riscv_init_csr_hash): New function. According to the DECLARE_CSR and
DECLARE_CSR_ALIAS, insert CSR extra information into csr_extra_hash.
Call hash_reg_name to insert CSR address into reg_names_hash.
(md_begin): Call riscv_init_csr_hashes for each DECLARE_CSR.
(reg_csr_lookup_internal, riscv_csr_class_check): New functions.
Decide whether the CSR is valid according to the csr_extra_hash.
(init_opcode_hash): Update 'if (hash_error != NULL)' as hash_error is
not a boolean. This is same as riscv_init_csr_hash, so keep the
consistent usage.
* testsuite/gas/riscv/csr-dw-regnums.d: Add -march=rv32if option.
* testsuite/gas/riscv/priv-reg.d: Add f-ext by -march option.
* testsuite/gas/riscv/priv-reg-fail-fext.d: New testcase. The source
file is `priv-reg.s`, and the ISA is rv32i without f-ext, so the
f-ext CSR are not allowed.
* testsuite/gas/riscv/priv-reg-fail-fext.l: Likewise.
* testsuite/gas/riscv/priv-reg-fail-rv32-only.d: New testcase. The
source file is `priv-reg.s`, and the ISA is rv64if, so the
rv32-only CSR are not allowed.
* testsuite/gas/riscv/priv-reg-fail-rv32-only.l: Likewise.
include/
* opcode/riscv-opc.h: Extend DECLARE_CSR and DECLARE_CSR_ALIAS to
record riscv_csr_class.
opcodes/
* riscv-dis.c (print_insn_args): Updated since the DECLARE_CSR is changed.
gdb/
* riscv-tdep.c: Updated since the DECLARE_CSR is changed.
* riscv-tdep.h: Likewise.
* features/riscv/rebuild-csr-xml.sh: Generate the 64bit-csr.xml without
rv32-only CSR.
* features/riscv/64bit-csr.xml: Regernated.
binutils/
* dwarf.c: Updated since the DECLARE_CSR is changed.
This allows pdp11 to handle 32-bit fixups that can be applied by gas,
and improves the error message emitted when the required reloc isn't
available.
* config/tc-pdp11.c (md_apply_fix): Handle BFD_RELOC_32.
(tc_gen_reloc): Only give a BAD_CASE assertion on pcrel relocs.
This patch fixes an ancient wart in aout support, in that text and
data section sizes are rounded up for alignment rather that just the
corresponding header sizes. Changing section sizes could conceivably
result in buffer overflows if section contents were held in memory.
Also, keeping the original section sizes allows this PR to be fixed
nicely.
bfd/
PR 25569
* aoutx.h (adjust_o_magic, adjust_z_magic, adjust_n_magic): Use
"text", "data" and "bss" section pointer vars. Don't update
section size, just exec header sizes.
(adjust_sizes_and_vmas): Don't update text section size. Set
initial exec header a_text. Print exec headers sizes.
* pdp11.c (adjust_o_magic, adjust_z_magic, adjust_n_magic),
(adjust_sizes_and_vmas): Similarly. Formatting.
(final_link): Correct final file extension.
gas/
PR 25569
* config/obj-aout.c (obj_aout_frob_file_before_fix): Don't loop
on section size adjustment, instead perform another write if
exec header size is larger than section size.
* config/tc-i386.c (output_insn): Mark cvtpi2ps and cvtpi2pd
with GNU_PROPERTY_X86_FEATURE_2_MMX.
* testsuite/gas/i386/i386.exp: Run property-3 and
x86-64-property-3.
* testsuite/gas/i386/property-3.d: New file.
* testsuite/gas/i386/property-3.s: Likewise.
* testsuite/gas/i386/x86-64-property-3.d: Likewise.
AMD ABM has 2 instructions: popcnt and lzcnt. ABM CPUID feature bit has
been reused for lzcnt and a POPCNT CPUID feature bit is added for popcnt
which used to be the part of SSE4.2. This patch removes CpuABM and adds
CpuPOPCNT. It changes ABM to enable both lzcnt and popcnt, changes SSE4.2
to also enable popcnt.
gas/
* config/tc-i386.c (cpu_arch): Add .popcnt.
* doc/c-i386.texi: Remove abm and .abm. Add popcnt and .popcnt.
Add a tab before @samp{.sse4a}.
opcodes/
* i386-gen.c (cpu_flag_init): Replace CpuABM with
CpuLZCNT|CpuPOPCNT. Add CpuPOPCNT to CPU_SSE4_2_FLAGS. Add
CPU_POPCNT_FLAGS.
(cpu_flags): Remove CpuABM. Add CpuPOPCNT.
* i386-opc.h (CpuABM): Removed.
(CpuPOPCNT): New.
(i386_cpu_flags): Remove cpuabm. Add cpupopcnt.
* i386-opc.tbl: Replace CpuABM|CpuSSE4_2 with CpuPOPCNT on
popcnt. Remove CpuABM from lzcnt.
* i386-init.h: Regenerated.
* i386-tbl.h: Likewise.
There's no need to have separate Cpu64 and CpuNo64 templates: There
already is special logic handling the attribute, and all that's needed
is rejecting 16-bit address registers in 64-bit mode. Suppress suffix
guessing and group all involved logic together, outside of suffix
processing (arguably it doesn't even belong in process_suffix()).
Also, since no AddrPrefixOpReg template permits any suffixes, move the
No_*Suf specifiers for them to a central place. Along with this drop
the no longer relevant NoRex64 from there.
Generally, the documentation doesn't allow for any explicit operands
to be specified with MONITOR/MWAIT. To permit the more legible
overriding of the address size via specifying operands, the option is
being retained even in Intel mode, but operand swapping is being
suppressed by this patch. This is both because it makes no sense here
(all of the operands are inputs) and because, as a result, old gcc
(prior to 4.8) actually expects it this way with -mintel-syntax (and
hence gets fixed by this change rather than, as claimed by a reply in
the bug report, broken).
Conversions which shrink element size and which have a memory source
can't be disambiguated between their 128- and 256-bit variants by
looking at the register operand. "operand size mismatch", however, is a
pretty misleading diagnostic. Generalize the logic introduced for
VFPCLASSP{S,D} such that, with suitable similar adjustments to the
respective templates, it'll cover these cases too.
For VCVTNEPS2BF16 also fold the two previously separate AVX512VL
templates to achieve the intended effect. This is then also accompanied
by a respective addition to the inval-avx512f testcase.
commit 7deea9aad8 changed nosse4 to include CpuSSE4a. But AMD SSE4a is
a superset of SSE3 and Intel SSE4 is a superset of SSSE3. Disable Intel
SSE4 shouldn't disable AMD SSE4a. This patch restores nosse4. It also
adds .sse4a and nosse4a.
gas/
* config/tc-i386.c (cpu_arch): Add .sse4a and nosse4a. Restore
nosse4.
* doc/c-i386.texi: Document sse4a and nosse4a.
opcodes/
* i386-gen.c (cpu_flag_init): Add CPU_ANY_SSE4A_FLAGS. Remove
CPU_ANY_SSE4_FLAGS.
For these to get treatment consistent with other operand size checking
the special logic shouldn't live in md_assemble(), but process_suffix().
And there's more logic involved than simply zapping the suffix.
Note however that MOVS[BW]* and MOVZ[BW]* still won't be fully
consistent, due to the objection to fold MOVS* templates just like was
done for MOVZ* in c07315e0c6 ("x86: allow suffix-less movzw and 64-bit
movzb").
Note further that it is against my own intentions to have MOVSX/MOVZX
silently default to a byte source in AT&T mode. This should happen only
when the destination register is a 16-bit one. In all other cases there
is an ambiguity, and the user should be warned. But it was explicitly
requested for this to be done in a way inconsistent with everything
else.
Note finally that the assembler change points out (and this patch fixes)
a wrong Intel syntax test introduced by bc31405ebb ("x86-64: Properly
encode and decode movsxd"): When source code specifies a 16-bit
destination register, disassembly expectations shouldn't have been to
find a 32-bit one.
Since we already suppress the prefix altogether when it's the default
one for the chosen addressing mode, let's do so also when instruction
prefix and override specified with the memory operand match. (Note that
insn prefix specified segment overrides never get discarded.)
For one both possible forms should be warned about. And then, to guard
against future surprises, qualify the original opcode check by excluding
VEX/EVEX-like templates.
Since PLT entry isn't needed for branch to local symbol, we can resolve
R_386_PLT32/R_X86_64_PLT32 relocation aganst local symbol to section,
similar to R_386_PC32/R_X86_64_PC32.
2020-02-13 Fangrui Song <maskray@google.com>
H.J. Lu <hongjiu.lu@intel.com>
PR gas/25551
* config/tc-i386.c (tc_i386_fix_adjustable): Don't check
BFD_RELOC_386_PLT32 nor BFD_RELOC_X86_64_PLT32.
* testsuite/gas/i386/i386.exp: Run relax-5 and x86-64-relax-4.
* testsuite/gas/i386/relax-5.d: New file.
* testsuite/gas/i386/relax-5.s: Likewise.
* testsuite/gas/i386/x86-64-relax-4.d: Likewise.
* testsuite/gas/i386/x86-64-relax-4.s: Likewise.
With AVX512VL disabled (e.g. when writing code for the Knights family
of processors) these insns aren't ambiguous when used with a memory
source, and hence should be accepted without suffix or operand size
specifier. When AVX512VL is enabled, to be consistent with this as
well as other ambiguous operand size handling it would seem better to
just warn about the ambiguity in AT&T mode, and still default to 512-bit
operands (on the assumption that the code may have been written without
AVX512VL in mind yet), but it was requested to leave AT&T syntax mode
alone here.
AMD and Intel differ in their handling of far indirect branches as well
as LFS/LGS/LSS: AMD CPUs ignore REX.W while Intel ones honors it. (Note
how the latter three were hybrids so far, while far branches were fully
AMD-like.)
Along the lines of be4c5e58bd ("x86: Always disallow double word suffix
with word general register") also adjust check_{byte,word}_reg(), to make
overall behavior consistent again in this regard.
The diagnostics issued by check_*_reg() are pretty AT&T-centric. Re-use
logic already used for SIMD memory operand size checking also for ones
where GPRs would alternatively also be allowed. (There's certainly room
for further improvement here.)
My previous patch introduced the use of a C99 feature. C99 standard is
not required for gas, so this feature should be removed.
Committed as obvious.
gas/ChangeLog:
2020-02-11 Matthew Malcomson <matthew.malcomson@arm.com>
* config/tc-arm.c (vcx_handle_register_arguments): Remove `for`
loop initial declaration.
Here we implement the custom datapath extensions for MVE.
This required the following changes:
- Adding a new register argument type (that takes either an MVE vector or
a Neon S or D register).
- Adding two new immediate operands types (0-127 and 0-4095).
- Using the Neon type machinery to distinguish between instruction
types. This required the introduction of new neon shapes to account
for the coprocessor operands to these instructions.
- Adding a new disassembly character to `print_insn_cde` to handle the
new register types.
Specification can be found at
https://developer.arm.com/docs/ddi0607/latest
Successfully regression tested on arm-none-eabi, and arm-wince-pe.
gas/ChangeLog:
2020-02-10 Matthew Malcomson <matthew.malcomson@arm.com>
* config/tc-arm.c (NEON_MAX_TYPE_ELS): Increment to account for
instructions that can have 5 arguments.
(enum operand_parse_code): Add new operands.
(parse_operands): Account for new operands.
(S5): New macro.
(enum neon_shape_el): Introduce P suffixes for coprocessor.
(neon_select_shape): Account for P suffix.
(LOW1): Move macro to global position.
(HI4): Move macro to global position.
(vcx_assign_vec_d): New.
(vcx_assign_vec_m): New.
(vcx_assign_vec_n): New.
(enum vcx_reg_type): New.
(vcx_get_reg_type): New.
(vcx_size_pos): New.
(vcx_vec_pos): New.
(vcx_handle_shape): New.
(vcx_ensure_register_in_range): New.
(vcx_handle_register_arguments): New.
(vcx_handle_insn_block): New.
(vcx_handle_common_checks): New.
(do_vcx1): New.
(do_vcx2): New.
(do_vcx3): New.
* testsuite/gas/arm/cde-missing-fp.d: New test.
* testsuite/gas/arm/cde-missing-fp.l: New test.
* testsuite/gas/arm/cde-missing-mve.d: New test.
* testsuite/gas/arm/cde-missing-mve.l: New test.
* testsuite/gas/arm/cde-mve-or-neon.d: New test.
* testsuite/gas/arm/cde-mve-or-neon.s: New test.
* testsuite/gas/arm/cde-mve.s: New test.
* testsuite/gas/arm/cde-warnings.l:
* testsuite/gas/arm/cde-warnings.s:
* testsuite/gas/arm/cde.d:
* testsuite/gas/arm/cde.s:
opcodes/ChangeLog:
2020-02-10 Matthew Malcomson <matthew.malcomson@arm.com>
* arm-dis.c (print_insn_cde): Define 'V' parse character.
(cde_opcodes): Add VCX* instructions.
This patch is part of a series that adds support for the Armv8.m
ARMv8.m Custom Datapath Extension to binutils.
This patch introduces the Custom Instructions Class 1/2/3 (Single/
Dual, Accumulator/Non-accumulator varianats) to the arm backend.
The following Custom Instructions are added: cx1, cx1a,
cx1d, cx1da, cx2, cx2a, cx2d, cx2da, cx3, cx3a, cx3d, cx3da.
Specification can be found at
https://developer.arm.com/docs/ddi0607/latest
This patch distinguishes between enabling CDE for different coprocessor
numbers by defining multiple architecture flags. This means that the
parsing of the architecture extension flags is kept entirely in the
existing code path.
We introduce a new IT block state to indicate the behaviour of these
instructions. This new state allows being used in an IT block or
outside an IT block, but does not allow the instruction to be used
inside a VPT block.
We need this since the CX*A instruction versions can be used in IT
blocks, but they aren't to have the conditional suffixes on them. Hence
we need to mark an instruction as allowed in either position.
We also need a new flag to objdump, in order to determine whether to
disassemble an instruction as CDE related or not.
Successfully regression tested on arm-none-eabi, and arm-wince-pe.
gas/ChangeLog:
2020-02-10 Stam Markianos-Wright <stam.markianos-wright@arm.com>
Matthew Malcomson <matthew.malcomson@arm.com>
* config/tc-arm.c (arm_ext_cde*): New feature sets for each
CDE coprocessor that can be enabled.
(enum pred_instruction_type): New pred type.
(BAD_NO_VPT): New error message.
(BAD_CDE): New error message.
(BAD_CDE_COPROC): New error message.
(enum operand_parse_code): Add new immediate operands.
(parse_operands): Account for new immediate operands.
(check_cde_operand): New.
(cde_coproc_enabled): New.
(cde_coproc_pos): New.
(cde_handle_coproc): New.
(cxn_handle_predication): New.
(do_custom_instruction_1): New.
(do_custom_instruction_2): New.
(do_custom_instruction_3): New.
(do_cx1): New.
(do_cx1a): New.
(do_cx1d): New.
(do_cx1da): New.
(do_cx2): New.
(do_cx2a): New.
(do_cx2d): New.
(do_cx2da): New.
(do_cx3): New.
(do_cx3a): New.
(do_cx3d): New.
(do_cx3da): New.
(handle_pred_state): Define new IT block behaviour.
(insns): Add newn CX*{,d}{,a} instructions.
(CDE_EXTENSIONS,armv8m_main_ext_table,armv8_1m_main_ext_table):
Define new cdecp extension strings.
* doc/c-arm.texi: Document new cdecp extension arguments.
* testsuite/gas/arm/cde-scalar.d: New test.
* testsuite/gas/arm/cde-scalar.s: New test.
* testsuite/gas/arm/cde-warnings.d: New test.
* testsuite/gas/arm/cde-warnings.l: New test.
* testsuite/gas/arm/cde-warnings.s: New test.
* testsuite/gas/arm/cde.d: New test.
* testsuite/gas/arm/cde.s: New test.
include/ChangeLog:
2020-02-10 Stam Markianos-Wright <stam.markianos-wright@arm.com>
Matthew Malcomson <matthew.malcomson@arm.com>
* opcode/arm.h (ARM_EXT2_CDE): New extension macro.
(ARM_EXT2_CDE0): New extension macro.
(ARM_EXT2_CDE1): New extension macro.
(ARM_EXT2_CDE2): New extension macro.
(ARM_EXT2_CDE3): New extension macro.
(ARM_EXT2_CDE4): New extension macro.
(ARM_EXT2_CDE5): New extension macro.
(ARM_EXT2_CDE6): New extension macro.
(ARM_EXT2_CDE7): New extension macro.
opcodes/ChangeLog:
2020-02-10 Stam Markianos-Wright <stam.markianos-wright@arm.com>
Matthew Malcomson <matthew.malcomson@arm.com>
* arm-dis.c (struct cdeopcode32): New.
(CDE_OPCODE): New macro.
(cde_opcodes): New disassembly table.
(regnames): New option to table.
(cde_coprocs): New global variable.
(print_insn_cde): New
(print_insn_thumb32): Use print_insn_cde.
(parse_arm_disassembler_options): Parse coprocN args.
Commit d835a58baa disabled sysenter/sysenter in 64-bit mode by
default. By default, assembler should accept common, Intel64 only
and AMD64 ISAs since there are no conflicts.
gas/
PR gas/25516
* config/tc-i386.c (intel64): Renamed to ...
(isa64): This.
(match_template): Accept Intel64 only instruction by default.
(i386_displacement): Updated.
(md_parse_option): Updated.
* c-i386.texi: Update -mamd64/-mintel64 documentation.
* testsuite/gas/i386/i386.exp: Run x86-64-sysenter. Pass
-mamd64 to x86-64-sysenter-amd.
* testsuite/gas/i386/x86-64-sysenter.d: New file.
opcodes/
PR gas/25516
* i386-gen.c (opcode_modifiers): Replace AMD64 and Intel64
with ISA64.
* i386-opc.h (AMD64): Removed.
(Intel64): Likewose.
(AMD64): New.
(INTEL64): Likewise.
(INTEL64ONLY): Likewise.
(i386_opcode_modifier): Replace amd64 and intel64 with isa64.
* i386-opc.tbl (Amd64): New.
(Intel64): Likewise.
(Intel64Only): Likewise.
Replace AMD64 with Amd64. Update sysenter/sysenter with
Cpu64 and Intel64Only. Remove AMD64 from sysenter/sysenter.
* i386-tbl.h: Regenerated.
* config/obj-elf.c (obj_elf_change_section): Error for section
type, attr or entsize changes in assembly.
* testsuite/gas/elf/elf.exp: Pass -Z to gas for section5 test.
* testsuite/gas/elf/section5.l: Update.
PR 25469
bfd * archures.c: Add GBZ80 and Z80N machine values.
* reloc.c: Add BFD_RELOC_Z80_16_BE.
* coff-z80.c: Add support for new reloc.
* coffcode.h: Add support for new machine values.
* cpu-z80.c: Add support for new machine names.
* elf32-z80.c: Add support for new reloc.
* bfd-in2.h: Regenerate.
* libbfd.h: Regenerate.
binutils* readelf.c (get_machine_flags): Add support for Z80N machine
number.
gas * config/tc-z80.c: Add -gbz80 command line option to generate code
for the GameBoy Z80. Add support for generating DWARF.
* config/tc-z80.h: Add support for DWARF debug information
generation.
* doc/c-z80.texi: Document new command line option.
* testsuite/gas/z80/gbz80_all.d: New file.
* testsuite/gas/z80/gbz80_all.s: New file.
* testsuite/gas/z80/z80.exp: Run the new tests.
* testsuite/gas/z80/z80n_all.d: New file.
* testsuite/gas/z80/z80n_all.s: New file.
* testsuite/gas/z80/z80n_reloc.d: New file.
include * coff/internal.h (R_IMM16BE): Define.
* elf/z80.h (EF_Z80_MACH_Z80N): Define.
(R_Z80_16_BE): New reloc.
ld * emulparams/elf32z80.sh: Use z80 emulation.
* emultempl/z80.em: Make generic to both COFF and ELF Z80 emulations.
* emultempl/z80elf.em: Delete.
* testsuite/ld-elf/pr22450.d: Expect to fail for the Z80.
* testsuite/ld-elf/sec64k.exp: Fix Z80 assembly.
* testsuite/ld-unique/pr21529.s: Avoid register name conflict.
* testsuite/ld-unique/unique.s: Likewise.
* testsuite/ld-unique/unique_empty.s: Likewise.
* testsuite/ld-unique/unique_shared.s: Likewise.
* testsuite/ld-unique/unique.d: Updated expected output.
* testsuite/ld-z80/arch_z80n.d: New file.
* testsuite/ld-z80/comb_arch_z80_z80n.d: New file.
* testsuite/ld-z80/labels.s: Add more labels.
* testsuite/ld-z80/relocs.s: Add more reloc tests.
* testsuite/ld-z80/relocs_f_z80n.d: New file
opcodes * z80-dis.c: Add support for GBZ80 opcodes.
As shown in
https://sourceware.org/bugzilla/show_bug.cgi?id=25490
--gc-sections will silently remove __patchable_function_entries section
and generate corrupt result. This patch adds the section flag 'o' to
.section directive:
.section __patchable_function_entries,"awo",@progbits,foo
.section __patchable_function_entries,"awoG",@progbits,foo,foo,comdat
.section __patchable_function_entries,"awo",@progbits,bar,unique,4
.section __patchable_function_entries,"awoG",@progbits,foo,foo,comdat,unique,1
which specifies the symbol name which the section references. Assmebler
will set its elf_linked_to_section to a local section where the symbol
is defined.
Linker is updated to call mark_hook if gc_mark of any of its linked-to
sections is set after all sections, except for backend specific ones,
have been garbage collected.
bfd/
PR gas/25381
* bfd-in2.h: Regenerated.
* elflink.c (_bfd_elf_gc_mark_extra_sections): Call mark_hook
on section if gc_mark of any of its linked-to sections is set
and don't set gc_mark again.
* section.c (asection): Add linked_to_symbol_name to map_head
union.
gas/
PR gas/25381
* config/obj-elf.c (get_section): Also check
linked_to_symbol_name.
(obj_elf_change_section): Also set map_head.linked_to_symbol_name.
(obj_elf_parse_section_letters): Handle the 'o' flag.
(build_group_lists): Renamed to ...
(build_additional_section_info): This. Set elf_linked_to_section
from map_head.linked_to_symbol_name.
(elf_adjust_symtab): Updated.
* config/obj-elf.h (elf_section_match): Add linked_to_symbol_name.
* doc/as.texi: Document the 'o' flag.
* testsuite/gas/elf/elf.exp: Run PR gas/25381 tests.
* testsuite/gas/elf/section18.d: New file.
* testsuite/gas/elf/section18.s: Likewise.
* testsuite/gas/elf/section19.d: Likewise.
* testsuite/gas/elf/section19.s: Likewise.
* testsuite/gas/elf/section20.d: Likewise.
* testsuite/gas/elf/section20.s: Likewise.
* testsuite/gas/elf/section21.d: Likewise.
* testsuite/gas/elf/section21.l: Likewise.
* testsuite/gas/elf/section21.s: Likewise.
ld/
PR ld/24526
PR ld/25021
PR ld/25490
* testsuite/ld-elf/elf.exp: Run PR ld/25490 tests.
* testsuite/ld-elf/pr24526.d: New file.
* testsuite/ld-elf/pr24526.s: Likewise.
* testsuite/ld-elf/pr25021.d: Likewise.
* testsuite/ld-elf/pr25021.s: Likewise.
* testsuite/ld-elf/pr25490-2-16.rd: Likewise.
* testsuite/ld-elf/pr25490-2-32.rd: Likewise.
* testsuite/ld-elf/pr25490-2-64.rd: Likewise.
* testsuite/ld-elf/pr25490-2.s: Likewise.
* testsuite/ld-elf/pr25490-3-16.rd: Likewise.
* testsuite/ld-elf/pr25490-3-32.rd: Likewise.
* testsuite/ld-elf/pr25490-3-64.rd: Likewise.
* testsuite/ld-elf/pr25490-3.s: Likewise.
* testsuite/ld-elf/pr25490-4-16.rd: Likewise.
* testsuite/ld-elf/pr25490-4-32.rd: Likewise.
* testsuite/ld-elf/pr25490-4-64.rd: Likewise.
* testsuite/ld-elf/pr25490-4.s: Likewise.
* testsuite/ld-elf/pr25490-5-16.rd: Likewise.
* testsuite/ld-elf/pr25490-5-32.rd: Likewise.
* testsuite/ld-elf/pr25490-5-64.rd: Likewise.
* testsuite/ld-elf/pr25490-5.s: Likewise.
* testsuite/ld-elf/pr25490-6-16.rd: Likewise.
* testsuite/ld-elf/pr25490-6-32.rd: Likewise.
* testsuite/ld-elf/pr25490-6-64.rd: Likewise.
* testsuite/ld-elf/pr25490-6.s: Likewise.
Clang's integrated assembler supports multiple section with the same
name:
.section .text,"ax",@progbits,unique,1
nop
.section .text,"ax",@progbits,unique,2
nop
"unique,N" assigns the number, N, as the section ID, to a section. The
valid values of the section ID are between 0 and 4294967295. It can be
used to distinguish different sections with the same section name.
This is useful with -fno-unique-section-names -ffunction-sections.
-ffunction-sections by default generates .text.foo, .text.bar, etc.
Using the same string can save lots of space in .strtab.
This patch adds section_id to bfd_section and reuses the linker
internal bit in BFD section flags, SEC_LINKER_CREATED, for assmebler
internal use to mark valid section_id. It also updates objdump to
compare section pointers if 2 sections comes from the same file since
2 different sections can have the same section name.
bfd/
PR gas/25380
* bfd-in2.h: Regenerated.
* ecoff.c (bfd_debug_section): Add section_id.
* section.c (bfd_section): Add section_id.
(SEC_ASSEMBLER_SECTION_ID): New.
(BFD_FAKE_SECTION): Add section_id.
binutils/
PR gas/25380
* objdump.c (sym_ok): Return FALSE if 2 sections are in the
same file with different section pointers.
gas/
PR gas/25380
* config/obj-elf.c (section_match): Removed.
(get_section): Also match SEC_ASSEMBLER_SECTION_ID and
section_id.
(obj_elf_change_section): Replace info and group_name arguments
with match_p. Also update the section ID and flags from match_p.
(obj_elf_section): Handle "unique,N". Update call to
obj_elf_change_section.
* config/obj-elf.h (elf_section_match): New.
(obj_elf_change_section): Updated.
* config/tc-arm.c (start_unwind_section): Update call to
obj_elf_change_section.
* config/tc-ia64.c (obj_elf_vms_common): Likewise.
* config/tc-microblaze.c (microblaze_s_data): Likewise.
(microblaze_s_sdata): Likewise.
(microblaze_s_rdata): Likewise.
(microblaze_s_bss): Likewise.
* config/tc-mips.c (s_change_section): Likewise.
* config/tc-msp430.c (msp430_profiler): Likewise.
* config/tc-rx.c (parse_rx_section): Likewise.
* config/tc-tic6x.c (tic6x_start_unwind_section): Likewise.
* doc/as.texi: Document "unique,N" in .section directive.
* testsuite/gas/elf/elf.exp: Run "unique,N" tests.
* testsuite/gas/elf/section15.d: New file.
* testsuite/gas/elf/section15.s: Likewise.
* testsuite/gas/elf/section16.s: Likewise.
* testsuite/gas/elf/section16a.d: Likewise.
* testsuite/gas/elf/section16b.d: Likewise.
* testsuite/gas/elf/section17.d: Likewise.
* testsuite/gas/elf/section17.l: Likewise.
* testsuite/gas/elf/section17.s: Likewise.
* testsuite/gas/i386/unique.d: Likewise.
* testsuite/gas/i386/unique.s: Likewise.
* testsuite/gas/i386/x86-64-unique.d: Likewise.
* testsuite/gas/i386/i386.exp: Run unique and x86-64-unique.
ld/
PR gas/25380
* testsuite/ld-i386/pr22001-1c.S: Use "unique,N" in .section
directives.
* testsuite/ld-i386/tls-gd1.S: Likewise.
* testsuite/ld-x86-64/pr21481b.S: Likewise.
The nios2 ABI documentation lists %gotoff as assembler syntax for the
R_NIOS2_GOTOFF relocation, used to represent a 32-bit GOT-relative offset
in data sections. This was previously unimplemented in GAS.
2020-01-31 Sandra Loosemore <sandra@codesourcery.com>
gas/
* config/tc-nios2.c (nios2_cons): Handle %gotoff as well as
%tls_ldo.
We noticed +mve was not enabling DSP instructions as it should, reported in PR
25472.
The MVE architecture extension for Armv8.1-M Mainline implies DSP extensions.
This patch reflects that in the '+mve' command line option.
gas/ChangeLog:
2020-01-31 Andre Vieira <andre.simoesdiasvieira@arm.com>
PR gas/25472
* config/tc-arm.c (armv8m_main_ext_table): Refactored +dsp adding.
(armv8_1m_main_ext_table): Refactored +dsp adding and enabled dsp for
+mve.
* testsuite/gas/arm/mve_dsp.d: New test.
This patch adds support for assembly instructions vldmia, vldmdb, vstmia
and vstmdb in MVE. This instructions are already supported for Armv8-M
Floating-point Extension.
gas/ChangeLog:
2020-01-31 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
* config/tc-arm.c (fldmias): Moved inside "THUMB_VARIANT & arm_ext_v6t2"
to support VLDMIA instruction for MVE.
(fldmdbs): Moved inside "THUMB_VARIANT & arm_ext_v6t2" to support VLDMDB
instruction for MVE.
(fstmias): Moved inside "THUMB_VARIANT & arm_ext_v6t2" to support VSTMIA
instruction for MVE.
(fstmdbs): Moved inside "THUMB_VARIANT & arm_ext_v6t2" to support VSTMDB
instruction for MVE.
* testsuite/gas/arm/mve-ldst.d: New test.
* testsuite/gas/arm/mve-ldst.s: Likewise.
Comparison of i.tm.base_opcode against particular but not sufficiently
specific values needs to be accompanied by other qualification. Exclude
VEX and alike encodings here, and also exclude all forms of prefixes
explicitly specified in the opcodes table. While using @GOT with such
insns may not be very useful, it also isn't with e.g. ADC and SBB, yet
these get explicitly listed in comments as supported.
Other than near returns these default to 32-bit operand size, and hence
it isn't really unlikely that 64-bit forms are meant. Hence these should
have disambiguating suffixes. In Intel mode, however, don't error in
these cases unconditionally - MASM accepts these without suffix _and_
without warning.
- 64-bit CALL permitting just a single operand size doesn't need it.
- FLDENV et al should never have had it.
It remains suspicious that a number of 64-bit only insns continue to
have the attribute, despite this being intended for .code16gcc handling
only.
movsxd is a 64-bit only instruction. It supports both 16-bit and 32-bit
destination registers. Its AT&T mnemonic is movslq which only supports
64-bit destination register. There is also a discrepancy between AMD64
and Intel64 on movsxd with 16-bit destination register. AMD64 supports
32-bit source operand and Intel64 supports 16-bit source operand.
This patch updates movsxd encoding and decoding to alow 16-bit and 32-bit
destination registers. It also handles movsxd with 16-bit destination
register for AMD64 and Intel 64.
gas/
PR binutils/25445
* config/tc-i386.c (check_long_reg): Also convert to QWORD for
movsxd.
* doc/c-i386.texi: Add a node for AMD64 vs. Intel64 ISA
differences. Document movslq and movsxd.
* testsuite/gas/i386/i386.exp: Run PR binutils/25445 tests.
* testsuite/gas/i386/x86-64-movsxd-intel.d: New file.
* testsuite/gas/i386/x86-64-movsxd-intel64-intel.d: Likewise.
* testsuite/gas/i386/x86-64-movsxd-intel64-inval.l: Likewise.
* testsuite/gas/i386/x86-64-movsxd-intel64-inval.s: Likewise.
* testsuite/gas/i386/x86-64-movsxd-intel64.d: Likewise.
* testsuite/gas/i386/x86-64-movsxd-intel64.s: Likewise.
* testsuite/gas/i386/x86-64-movsxd-inval.l: Likewise.
* testsuite/gas/i386/x86-64-movsxd-inval.s: Likewise.
* testsuite/gas/i386/x86-64-movsxd.d: Likewise.
* testsuite/gas/i386/x86-64-movsxd.s: Likewise.
opcodes/
PR binutils/25445
* i386-dis.c (MOVSXD_Fixup): New function.
(movsxd_mode): New enum.
(x86_64_table): Use MOVSXD_Fixup and movsxd_mode on movsxd.
(intel_operand_size): Handle movsxd_mode.
(OP_E_register): Likewise.
(OP_G): Likewise.
* i386-opc.tbl: Remove Rex64 and allow 32-bit destination
register on movsxd. Add movsxd with 16-bit destination register
for AMD64 and Intel64 ISAs.
* i386-tbl.h: Regenerated.
In 64-bit mode, double word suffix in mnemonic with word general register
is disallowed. Otherwise, assembler gives a warning:
$ cat /tmp/x.s
movl %ax, %bx
movl %ds, %ax
movl %ax, %cs
$ gcc -c /tmp/x.s
/tmp/x.s: Assembler messages:
/tmp/x.s:1: Error: incorrect register `%bx' used with `l' suffix
/tmp/x.s:2: Error: incorrect register `%ax' used with `l' suffix
/tmp/x.s:3: Error: incorrect register `%ax' used with `l' suffix
$ gcc -c /tmp/x.s -m32
/tmp/x.s: Assembler messages:
/tmp/x.s: Assembler messages:
/tmp/x.s:1: Warning: using `%ebx' instead of `%bx' due to `l' suffix
/tmp/x.s:1: Warning: using `%eax' instead of `%ax' due to `l' suffix
/tmp/x.s:2: Warning: using `%eax' instead of `%ax' due to `l' suffix
/tmp/x.s:3: Warning: using `%eax' instead of `%ax' due to `l' suffix
This patch makes it a hard error in all modes. Now we get:
$ gcc -c /tmp/x.s -m32
/tmp/x.s: Assembler messages:
/tmp/x.s:1: Error: incorrect register `%bx' used with `l' suffix
/tmp/x.s:2: Error: incorrect register `%ax' used with `l' suffix
/tmp/x.s:3: Error: incorrect register `%ax' used with `l' suffix
PR gas/25438
* config/tc-i386.c (check_long_reg): Always disallow double word
suffix in mnemonic with word general register.
* testsuite/gas/i386/general.s: Replace word general register
with double word general register for movl.
* testsuite/gas/i386/inval.s: Add tests for movl with word general
register.
* testsuite/gas/i386/general.l: Updated.
* testsuite/gas/i386/inval.l: Likewise.
This implements register saving and restoring in the __tls_get_addr
call stub, so that when glibc supports the optimized tls call stub gcc
can generate code that assumes only r0, r12 and of course r3 are
changed on a __tls_get_addr call. When gcc expects __tls_get_addr
calls to preserve registers the call will be to __tls_get_addr_desc,
which will be translated by the linker to a call to __tls_get_addr_opt.
bfd/
* elf64-ppc.h (struct ppc64_elf_params): Add no_tls_get_addr_regsave.
* elf64-ppc.c (struct ppc_link_hash_table): Add tga_desc and
tga_desc_fd.
(is_tls_get_addr): Match tga_desc and tga_desc_df too.
(STDU_R1_0R1, ADDI_R1_R1): Define.
(tls_get_addr_prologue, tls_get_addr_epilogue): New functions.
(ppc64_elf_tls_setup): Set up tga_desc and tga_desc_fd. Indirect
tga_desc_fd to opt_fd, and tga_desc to opt. Set
no_tls_get_addr_regsave.
(branch_reloc_hash_match): Add hash3 and hash4.
(ppc64_elf_tls_optimize): Handle tga_desc_fd and tga_desc too.
(ppc64_elf_size_dynamic_sections): Likewise.
(ppc64_elf_relocate_section): Likewise.
(plt_stub_size, build_plt_stub): Likewise. Size regsave
__tls_get_addr stub.
(build_tls_get_addr_stub): Build regsave __tls_get_addr stub and
eh_frame.
(ppc_size_one_stub): Handle tga_desc_fd and tga_desc too. Size
eh_frame for regsave __tls_get_addr.
gas/
* config/tc-ppc.c (parse_tls_arg): Handle tls arg for
__tls_get_addr_desc and __tls_get_addr_opt.
ld/
* emultempl/ppc64elf.em (ppc64_opt, PARSE_AND_LIST_LONGOPTS),
(PARSE_AND_LIST_OPTIONS, PARSE_AND_LIST_ARGS_CASES): Support
--tls-get-addr-regsave and --no-tls-get-addr-regsave.
(params): Init new field.
* ld.texi (--tls-get-addr-regsave, --no-tls-get-addr-regsave):
Document.
* testsuite/ld-powerpc/tlsdesc.s,
* testsuite/ld-powerpc/tlsdesc.d,
* testsuite/ld-powerpc/tlsdesc.wf,
* testsuite/ld-powerpc/tlsdesc2.d,
* testsuite/ld-powerpc/tlsdesc2.wf,
* testsuite/ld-powerpc/tlsexenors.d,
* testsuite/ld-powerpc/tlsexenors.r,
* testsuite/ld-powerpc/tlsexers.d,
* testsuite/ld-powerpc/tlsexers.r,
* testsuite/ld-powerpc/tlsexetocnors.d,
* testsuite/ld-powerpc/tlsexetocrs.d,
* testsuite/ld-powerpc/tlsexetocrs.r,
* testsuite/ld-powerpc/tlsopt6.d,
* testsuite/ld-powerpc/tlsopt6.wf: New.
* testsuite/ld-powerpc/powerpc.exp: Run new tests.
There's no need (anymore?) to heavily special case this - just make
generic logic consider only its first operand, and deal with the case
of an 'l' suffix not being allowed in a pattern.
Commit b76bc5d54e ("x86: don't default variable shift count insns to
8-bit operand size") pointed out a very bad case, but the underlying
problem is, as mentioned on various occasions, much larger: Silently
selecting a (nowhere documented afaict) certain default operand size
when there's no "sizing" suffix and no suitable register operand(s) is
simply dangerous (for the programmer to make mistakes).
While in Intel syntax mode such mistakes already lead to an error (which
is going to remain that way), AT&T syntax mode now gains warnings in
such cases by default, which can be suppressed or promoted to an error
if so desired by the programmer. Furthermore at least general purpose
insns now consistently have a default applied (alongside the warning
emission), rather than accepting some and refusing others.
No warnings are (as before) to be generated for "DefaultSize" insns as
well as ones acting on selector and other fixed-width values. For
SYSRET, however, the DefaultSize needs to be dropped - it had been
wrongly put there in the first place, as it's unrelated to .code16gcc
(no stack accesses involved).
As set forth as a prereq when I first mentioned this intended change a
few years back, Linux as well as gcc have meanwhile been patched to
avoid (emission of) ambiguous operands (and hence triggering of the new
warning).
Note that I think that in 64-bit mode IRET and far RET would better get
a diagnostic too, as it's reasonably likely that a suffix-less instance
really is meant to be a 64-bit one. But I guess I better make this a
separate follow-on patch.
Note further that floating point operations with integer operands are an
exception for now: They continue to use short (16-bit) operands by
default even in 32- and 64-bit modes.
Finally note that while {,V}PCMPESTR{I,M} would, strictly speaking, also
need to be diagnosed, with their 64-bit forms not being very useful I
think it is better to continue to avoid warning about them (by way of
them carrying IgnoreSize attributes).
This patch moves MVE feature bits into the CORE_HIGH section. This makes sure
.fpu and -mfpu does not reset the bits set by MVE. This is important because
.fpu has no option to "set" these same bits and thus, mimic'ing GCC, we choose
to define MVE as an architecture extension rather than put it together with
other the legacy fpu features.
This will enable the following behavior:
.arch armv8.1-m.main
.arch mve
.fpu fpv5-sp-d16 #does not disable mve.
vadd.i32 q0, q1, q2
This patch also makes sure MVE is not taken into account during auto-detect.
This was already the case, but because we moved the MVE bits to the
architecture feature space we must make sure ARM_ANY does not include MVE.
gas/ChangeLog:
2020-01-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
PR 25376
* config/tc-arm.c (mve_ext, mve_fp_ext): Use CORE_HIGH.
(armv8_1m_main_ext_table): Use CORE_HIGH for mve.
* testsuite/arm/armv8_1-m-fpu-mve-1.s: New.
* testsuite/arm/armv8_1-m-fpu-mve-1.d: New.
* testsuite/arm/armv8_1-m-fpu-mve-2.s: New.
* testsuite/arm/armv8_1-m-fpu-mve-2.d: New.
include/ChangeLog:
2020-01-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
PR 25376
* opcodes/arm.h (FPU_MVE, FPU_MVE_FPU): Move these features to...
(ARM_EXT2_MVE, ARM_EXT2_MVE_FP): ... the CORE_HIGH space.
(ARM_ANY): Redefine to not include any MVE bits.
(ARM_FEATURE_ALL): Removed.
opcodes/ChangeLog:
2020-01-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
PR 25376
* opcodes/arm-dis.c (coprocessor_opcodes): Use CORE_HIGH for MVE bits.
(neon_opcodes): Likewise.
(select_arm_features): Make sure we enable MVE bits when selecting
armv8.1-m.main. Make sure we do not enable MVE bits when not selecting
any architecture.
gas/ChangeLog:
2020-01-15 Jozef Lawrynowicz <jozef.l@mittosystems.com>
* config/tc-msp430.c (CHECK_RELOC_MSP430): Always generate 430X
relocations when the target is 430X, except when extracting part of an
expression.
(msp430_srcoperand): Adjust comment.
Initialize the expp member of the msp430_operand_s struct as
appropriate.
(msp430_dstoperand): Likewise.
* testsuite/gas/msp430/msp430.exp: Run new test.
* testsuite/gas/msp430/reloc-lo-430x.d: New test.
* testsuite/gas/msp430/reloc-lo-430x.s: New test.
include/ChangeLog:
2020-01-15 Jozef Lawrynowicz <jozef.l@mittosystems.com>
* opcode/msp430.h (enum msp430_expp_e): New.
(struct msp430_operand_s): Add expp member to struct.
ld/ChangeLog:
2020-01-15 Jozef Lawrynowicz <jozef.l@mittosystems.com>
* testsuite/ld-msp430-elf/msp430-elf.exp: Run new test.
* testsuite/ld-msp430-elf/reloc-lo-430x.s: New test.
PR 25377
gas * config/tc-z80.c: Add support for half precision, single
precision and double precision floating point values.
* config/tc-z80.h b/gas/config/tc-z80.h: Disable string escapes.
* doc/as.texi: Add new z80 command line options.
* doc/c-z80.texi: Document new z80 command line options.
* testsuite/gas/z80/ez80_pref_dis.s: New test.
* testsuite/gas/z80/ez80_pref_dis.d: New test driver.
* testsuite/gas/z80/z80.exp: Run the new test.
* testsuite/gas/z80/fp_math48.d: Use correct command line option.
* testsuite/gas/z80/fp_zeda32.d: Likewise.
* testsuite/gas/z80/strings.d: Update expected output.
opcodes * z80-dis.c (suffix): Use .db instruction to generate double
prefix.
There are no instructions under these matrix multiply extensions that
can be used without having SVE enabled.
Since these extensions require SVE, we make that explicit in the options
table.
Tested on aarch64-none-elf without regressions.
gas/ChangeLog:
2020-01-13 Matthew Malcomson <matthew.malcomson@arm.com>
* config/tc-aarch64.c (f64mm, f32mm): Add sve as a feature
dependency.
Don't do that. Especially don't use shift counts that assume the type
being shifted is 32 bits when the type is long/unsigned long. Also
reverts part of a change I made on 2019-12-11 to tic4x_print_register
that on closer inspection turns out to be unnecessary.
include/
* opcode/tic4x.h (EXTR): Delete.
(EXTRU, EXTRS, INSERTU, INSERTS): Rewrite without zero/sign
extension using shifts. Do trim INSERTU value to specified bitfield.
opcodes/
* tic4x-dis.c (tic4x_print_register): Remove dead code.
gas/
* config/tc-tic4x.c (tic4x_operands_match): Correct tic3x trap
insertion.
Checking just the base opcode without also checking this isn't a VEX
encoding, and without there being other insn properties avoiding a match
once respective VEX/XOP/EXEX-encoded insns would appear, is at least
dangerous. Add respective checks. At the same time there's no real need
to check the extension opcode to be None for the 0xA8 form - there's
nothing it can be confused with, and non-VEX-and-alike forms also can't
appear.
Commit ac0ab1842d ("i386: Also check R12-R15 registers when optimizing
testq to testb") didn't go quite far enough: In order to avoid confusing
other code registers would better be converted to byte ones uniformly.
PR 14891
* config/obj-elf.c (obj_elf_section): Fail if the section name is
already defined as a different symbol type.
* testsuite/gas/elf/pr14891.s: New test source file.
* testsuite/gas/elf/pr14891.d: New test driver.
* testsuite/gas/elf/pr14891.s: New test expected error output.
* testsuite/gas/elf/elf.exp: Run the new test.
The fix is the additional ARRAY_SIZE test, the rest just tidies
variable types rather than adding a cast to avoid warnings.
opcodes/
* z8k-dis.c: Include libiberty.h
(instr_data_s): Make max_fetched unsigned.
(z8k_lookup_instr): Make nibl_index and tabl_index unsigned.
Don't exceed byte_info bounds.
(output_instr): Make num_bytes unsigned.
(unpack_instr): Likewise for nibl_count and loop.
* z8kgen.c (gas <opcode_entry_type>): Make noperands, length and
idx unsigned.
* z8k-opc.h: Regenerate.
gas/
* config/tc-z8k.c (md_begin): Make idx unsigned.
(get_specific): Likewise for this_index.
We use gas' expression function to parse the operands of an
instruction in a generic way. There are situations when we have labels
and registers having the same name as well as the substraction sign
doesn't always stands for the arithmetical operation but for the
register range (e.g. enter instruction). This patch improves parsing
symbols found in a instruction operand, cleans up code and avoids
using default or undefined variables.
gas/
xxxx-xx-xx Claudiu Zissulescu <claziss@synopsys.com>
* config/tc-arc.c (parse_reloc_symbol): New function.
(tokenize_arguments): Clean up, use parse_reloc_symbol function.
(md_operand): Set X_md to absent.
(arc_parse_name): Check for X_md.
PR 25224
bfd * Makefile.am: Add z80-elf target support.
* configure.ac: Likewise.
* targets.c: Likewise.
* config.bfd: Add z80-elf target support and new arches: ez80 and z180.
* elf32-z80.c: New file.
* archures.c: Add new z80 architectures: eZ80 and Z180.
* coffcode.h: Likewise.
* cpu-z80.c: Likewise.
* bfd-in2.h: Likewise plus additional Z80 relocations.
* coff-z80.c: Add new relocations for Z80 target and local label check.
gas * config/tc-z80.c: Add new architectures: Z180 and eZ80. Add support
for assembler code generated by SDCC. Add new relocation types. Add
z80-elf target support.
* config/tc-z80.h: Add z80-elf target support. Enable dollar local
labels. Local labels starts from ".L".
* testsuite/gas/all/fwdexp.d: Fix failure due to symbol conflict.
* testsuite/gas/all/fwdexp.s: Likewise.
* testsuite/gas/z80/suffix.d: Fix failure on ELF target.
* testsuite/gas/z80/z80.exp: Add new tests
* testsuite/gas/z80/dollar.d: New file.
* testsuite/gas/z80/dollar.s: New file.
* testsuite/gas/z80/ez80_adl_all.d: New file.
* testsuite/gas/z80/ez80_adl_all.s: New file.
* testsuite/gas/z80/ez80_adl_suf.d: New file.
* testsuite/gas/z80/ez80_isuf.s: New file.
* testsuite/gas/z80/ez80_z80_all.d: New file.
* testsuite/gas/z80/ez80_z80_all.s: New file.
* testsuite/gas/z80/ez80_z80_suf.d: New file.
* testsuite/gas/z80/r800_extra.d: New file.
* testsuite/gas/z80/r800_extra.s: New file.
* testsuite/gas/z80/r800_ii8.d: New file.
* testsuite/gas/z80/r800_z80_doc.d: New file.
* testsuite/gas/z80/z180.d: New file.
* testsuite/gas/z80/z180.s: New file.
* testsuite/gas/z80/z180_z80_doc.d: New file.
* testsuite/gas/z80/z80_doc.d: New file.
* testsuite/gas/z80/z80_doc.s: New file.
* testsuite/gas/z80/z80_ii8.d: New file.
* testsuite/gas/z80/z80_ii8.s: New file.
* testsuite/gas/z80/z80_in_f_c.d: New file.
* testsuite/gas/z80/z80_in_f_c.s: New file.
* testsuite/gas/z80/z80_op_ii_ld.d: New file.
* testsuite/gas/z80/z80_op_ii_ld.s: New file.
* testsuite/gas/z80/z80_out_c_0.d: New file.
* testsuite/gas/z80/z80_out_c_0.s: New file.
* testsuite/gas/z80/z80_reloc.d: New file.
* testsuite/gas/z80/z80_reloc.s: New file.
* testsuite/gas/z80/z80_sli.d: New file.
* testsuite/gas/z80/z80_sli.s: New file.
ld * Makefile.am: Add new target z80-elf
* configure.tgt: Likewise.
* emultempl/z80.em: Add support for eZ80 and Z180 architectures.
* emulparams/elf32z80.sh: New file.
* emultempl/z80elf.em: Likewise.
* testsuite/ld-z80/arch_ez80_adl.d: Likewise.
* testsuite/ld-z80/arch_ez80_z80.d: Likewise.
* testsuite/ld-z80/arch_r800.d: Likewise.
* testsuite/ld-z80/arch_z180.d: Likewise.
* testsuite/ld-z80/arch_z80.d: Likewise.
* testsuite/ld-z80/comb_arch_ez80_z80.d: Likewise.
* testsuite/ld-z80/comb_arch_z180.d: Likewise.
* testsuite/ld-z80/labels.s: Likewise.
* testsuite/ld-z80/relocs.s: Likewise.
* testsuite/ld-z80/relocs_b_ez80.d: Likewise.
* testsuite/ld-z80/relocs_b_z80.d: Likewise.
* testsuite/ld-z80/relocs_f_z80.d: Likewise.
* testsuite/ld-z80/z80.exp: Likewise.
opcodes * z80-dis.c: Add support for eZ80 and Z80 instructions.
There's no reason to not also issue them in Intel syntax mode, and it
can be quite helpful to mention the actual insn (after all there can be
multiple on a single line).
First and foremost REX must come last. Next JumpInterSegment branches
can't possibly have a REX prefix, as they're consistently CpuNo64. And
finally make BND prefix handling in output_branch() consistent with that
of other prefixes in the same function, and make its placement among
prefixes consistent with output_jump() (which, oddly enough, still isn't
the supposedly canonical order specified by the *_PREFIX definitions).
The expectation of x86-64-branch-3 for "call" / "jmp" with an obvious
direct destination to translate to an indirect _far_ branch is plain
wrong. The operand size prefix should have no effect at all on the
interpretation of the operand. The main underlying issue here is that
the Intel64 templates of the direct branches don't include Disp16, yet
various assumptions exist that it would always be there when there's
also Disp32/Disp32S, toggled by the operand size prefix (which is
being ignored by direct branches in Intel64 mode).
Along these lines it was also wrong to base the displacement width
decision solely on the operand size prefix: REX.W cancels this effect
and hence needs taking into consideration, too.
A disassembler change is needed here as well: XBEGIN was wrongly treated
the same as direct CALL/JMP, which isn't the case - the operand size
prefix does affect displacement size there, it's merely ignored when it
comes to updating [ER]IP.
In memory operand addressing, which forms of displacement are permitted
besides Disp8 is pretty clearly limited
- outside of 64-bit mode, Disp16 or Disp32 only, depending on address
size (MPX being special in not allowing Disp16),
- in 64-bit mode, Disp32s or Disp64 without address size override, and
solely Disp32 with one.
Adjust assembler and i386-gen to match this, observing that templates
already get adjusted before trying to match them against input depending
on the presence of an address size prefix.
This adjustment logic gets extended to all cases, as certain DispNN
values should also be dropped when there's no such prefix. In fact
behavior of the assembler, perhaps besides the exact diagnostics wording,
should not differ between there being templates applicable to 64-bit and
non-64-bit at the same time, or there being fully separate sets of
templates, with their DispNN settings already reduced accordingly.
This adjustment logic further gets guarded such that there wouldn't be
and Disp<N> conversion based on address size prefix when this prefix
doesn't control the width of the displacement (on branches other than
absolute ones).
These adjustments then also allow folding two MOV templates, which had
been split between 64-bit and non-64-bits variants so far.
Once in this area also
- drop the bogus DispNN from JumpByte templates, leaving just the
correct Disp8 there (compensated by i386_finalize_displacement()
now setting Disp8 on their operands),
- add the missing Disp32S to XBEGIN.
Note that the changes make it necessary to temporarily mark a test as
XFAIL; this will get taken care of by a subsequent patch. The failing
parts are entirely bogus and will get replaced.
Similar to SP, BP, SI and DI registers, R12-R15 registers must use REX
prefix for the low byte register when optimizing
test $imm7, %r64/%r32/%r16 -> test $imm7, %r8
PR gas/25274
* config/tc-i386.c (optimize_encoding): Also check R12-R15
registers for "test $imm7, %r64/%r32/%r16 -> test $imm7, %r8"
optimization.
* testsuite/gas/i386/x86-64-optimize-3.s: Add tests for test
with r12.
* testsuite/gas/i386/x86-64-optimize-3.d: Updated.
* testsuite/gas/i386/x86-64-optimize-3b.d: Likewise.
Add 3 command-line options to align branches within a fixed boundary
with segment prefixes or NOPs:
1. -malign-branch-boundary=NUM aligns branches within NUM byte boundary.
2. -malign-branch=TYPE[+TYPE...] specifies types of branches to align.
The supported branches are:
a. Conditional jump.
b. Fused conditional jump.
c. Unconditional jump.
d. Call.
e. Ret.
f. Indirect jump and call.
3. -malign-branch-prefix-size=NUM aligns branches with NUM segment
prefixes per instruction.
3 new rs_machine_dependent frag types are added:
1. BRANCH_PADDING. The variable size frag to insert NOP before branch.
2. BRANCH_PREFIX. The variable size frag to insert segment prefixes to
an instruction. The choices of prefixes are:
a. Use the existing segment prefix if there is one.
b. Use CS segment prefix in 64-bit mode.
c. In 32-bit mode, use SS segment prefix with ESP/EBP base register
and use DS segment prefix without ESP/EBP base register.
3. FUSED_JCC_PADDING. The variable size frag to insert NOP before fused
conditional jump.
The new rs_machine_dependent frags aren't inserted if the previous item
is a prefix or a constant directive, which may be used to hardcode an
instruction, since there is no clear instruction boundary. Segment
prefixes and NOP padding are disabled before relaxable TLS relocations
and tls_get_addr calls to keep TLS instruction sequence unchanged.
md_estimate_size_before_relax() and i386_generic_table_relax_frag() are
used to handled BRANCH_PADDING, BRANCH_PREFIX and FUSED_JCC_PADDING frags.
i386_generic_table_relax_frag() grows or shrinks sizes of segment prefix
and NOP to align the next branch frag:
1. First try to add segment prefixes to instructions before a branch.
2. If there is no sufficient room to add segment prefixes, NOP will be
inserted before a branch.
* config/tc-i386.c (_i386_insn): Add has_gotpc_tls_reloc.
(tls_get_addr): New.
(last_insn): New.
(align_branch_power): New.
(align_branch_kind): New.
(align_branch_bit): New.
(align_branch): New.
(MAX_FUSED_JCC_PADDING_SIZE): New.
(align_branch_prefix_size): New.
(BRANCH_PADDING): New.
(BRANCH_PREFIX): New.
(FUSED_JCC_PADDING): New.
(i386_generate_nops): Support BRANCH_PADDING and FUSED_JCC_PADDING.
(md_begin): Abort if align_branch_prefix_size <
MAX_FUSED_JCC_PADDING_SIZE.
(md_assemble): Set last_insn.
(maybe_fused_with_jcc_p): New.
(add_fused_jcc_padding_frag_p): New.
(add_branch_prefix_frag_p): New.
(add_branch_padding_frag_p): New.
(output_insn): Generate a BRANCH_PADDING, FUSED_JCC_PADDING or
BRANCH_PREFIX frag and terminate each frag to align branches.
(output_disp): Set i.has_gotpc_tls_reloc to TRUE for GOTPC and
relaxable TLS relocations.
(output_imm): Likewise.
(i386_next_non_empty_frag): New.
(i386_next_jcc_frag): New.
(i386_classify_machine_dependent_frag): New.
(i386_branch_padding_size): New.
(i386_generic_table_relax_frag): New.
(md_estimate_size_before_relax): Handle COND_JUMP_PADDING,
FUSED_JCC_PADDING and COND_JUMP_PREFIX frags.
(md_convert_frag): Handle BRANCH_PADDING, BRANCH_PREFIX and
FUSED_JCC_PADDING frags.
(OPTION_MALIGN_BRANCH_BOUNDARY): New.
(OPTION_MALIGN_BRANCH_PREFIX_SIZE): New.
(OPTION_MALIGN_BRANCH): New.
(md_longopts): Add -malign-branch-boundary=,
-malign-branch-prefix-size= and -malign-branch=.
(md_parse_option): Handle -malign-branch-boundary=,
-malign-branch-prefix-size= and -malign-branch=.
(md_show_usage): Display -malign-branch-boundary=,
-malign-branch-prefix-size= and -malign-branch=.
(i386_target_format): Set tls_get_addr.
(i386_cons_align): New.
* config/tc-i386.h (i386_cons_align): New.
(md_cons_align): New.
(i386_generic_table_relax_frag): New.
(md_generic_table_relax_frag): New.
(i386_tc_frag_data): Add u, padding_address, length,
max_prefix_length, prefix_length, default_prefix, cmp_size,
classified and branch_type.
(TC_FRAG_INIT): Initialize u, padding_address, length,
max_prefix_length, prefix_length, default_prefix, cmp_size,
classified and branch_type.
* doc/c-i386.texi: Document -malign-branch-boundary=,
-malign-branch= and -malign-branch-prefix-size=.
This started out as fixing decode_16, which used a char to index a 256
byte decodings array. When char is signed that could result in an out
of bounds array access. The rest of the patch is for consistency and
just general cleanup.
* config/obj-evax.c (crc32, encode_32, encode_16, decode_16):
Remove unnecessary prototypes.
(number_of_codings): Delete, use ARRAY_SIZE instead throughout.
(codings, decodings): Make arrays of unsigned char.
(crc32): Use unsigned variables. Delete unnecessary mask.
(encode_32, encode_16): Return unsigned char*, and make static
buffer an unsigned char array.
(decode_16): Make arg an unsigned char*. Remove useless casts.
(shorten_identifier): Use unsigned char crc_chars.
(is_truncated_identifier): Make ptr an unsigned char*.
In ("x86: extend SSE check to PCLMULQDQ, AES, and GFNI insns") I went
both a little too far and not quite far enough:
- GFNI insns also have AVX512 variants, which also shouldn't get
diagnosed,
- SSE4a insns should get diagnosed just like SSE4.x ones,
- SHA insns should get diagnosed just like PCLMULQDQ or AES ones.
This patch fixes .arch_extension behaviour.
Currently, context table for '.arch_extension' is only set while
"-march" processing, but it is not set while .arch processing,
so following code is rejected
.syntax unified
.thumb
.arch armv8.1-m.main
.arch_extension mve.fp
unless -march=armv8.1-m.main is given.
Committing on behalf of Vladimir Murzin
gas/ChangeLog:
2019-12-10 Vladimir Murzin <vladimir.murzin@arm.com>
* config/tc-arm.c (s_arm_arch): Set selected_ctx_ext_table.
* testsuite/gas/arm/mve-arch-ext.s: New.
* testsuite/gas/arm/mve-arch-ext.d: New.
This is an alias of "qword ptr", commonly used with MMX insns.
At this occasion also test (alongside the newly supported "mmword")
- "zmmword" used as expression,
- PADDB with "oword ptr" (aliasing "xmmword ptr").
Commit dc2be329b9 ("i386: Only check suffix in instruction mnemonic")
broke rejecting of these for floating point insns. Fix this by setting
the "byte" operand attribute, which will now (again) cause an error.
Furthermore the diagnostic for the "far ptr" case in general and for the
"near ptr" case in the non-float cases became "invalid instruction
suffix" instead of the intended "operand size mismatch". Fix this by
also setting the "tbyte" operand attribute (no insn template accepts
both byte and tbyte operands).
There are extremely few insns accepting "tbyte ptr" operand, so the
"tbyte" operand flag checking done by match_operand_size() is already
sufficient; the setting of the suffix has become meaningless anyway
with dc2be329b9 ("i386: Only check suffix in instruction mnemonic").
Fold the code with that setting the "byte" operand flag to force an
error (no insn at all accepts both "byte ptr" and tbyte ptr" operands,
except for AnySize ones where the two (conflicting) recorded types
don't matter (operand_size_match() doesn't call match_operand_size() in
this case).
No floating point insn accepts an "fword ptr" operand, so the "fword"
operand flag checking done by match_mem_size() is already sufficient;
the setting of the suffix has become meaningless anyway with
dc2be329b9 ("i386: Only check suffix in instruction mnemonic").
LDS et al don't accept "word ptr" operands anyway, as per their insn
templates. Hence there's no need to special case this here; the check
has become dysfunctional anyway by dc2be329b9 ("i386: Only check
suffix in instruction mnemonic").
This, at the assembler level, is just a "brace" feature covering both
AES and SHA2. Hence there's no need for it to have a separate feature
flag, freeing up a bit for future re-use. Along these lines there are
also a number of dead definitions/variables in the opcode table file.
SHA2 is a prereq to SHA3, not part of it aiui. Hence disabling the
latter should not also disable the former.
In the course of adding respective tests also do away with the
duplication of crypto.d's contents in crypto-directive.d.
Since we accept these without suffix / operand size specifier, we should
also do so with one. (The fact that we unilaterally accept these, other
than far branches, rather than limiting them to Intel64 mode, will be
taken care of later on.)
Also take the opportunity and make sure "lfs <reg>, tbyte ptr <mem>"
et al get rejected outside of 64-bit mode. This became broken by
dc2be329b9 ("i386: Only check suffix in instruction mnemonic").
Furthermore cover lgdt et al in the Intel syntax handling as well, which
continued to work after said commit just by coincidence.
While dc2be329b9 ("i386: Only check suffix in instruction mnemonic")
has made the assembler accept these in the first place (they were wrongly
rejected before), the generated code was still wrong in that it lacked
an operand size override. (In 64-bit code, other than in 16- and 32-bit
ones, CALL and JMP with memory operands are all entirely unambiguous: No
operand size can have two meanings.)
While segment registers are registers, their use doesn't allow sizing
of insns without suffix / explicit operand size specifier. Prevent
PUSH and POP of segment registers from entering that path, instead
allowing them to observe the stackop_size setting just like other
PUSH/POP and alike do.
Insns permitting only GPR operands (and hence implicit sizing when
there's no suffix) don't ever have their DefaultSize attribute
inspected, so it shouldn't be there in the first place.
Additionally XBEGIN is like JMP, not CALL, and hence shouldn't be
converted to 32-bit operand size in .code16gcc mode. While the same is
true for SYSRET, it permitting more than one suffix makes it FLDENV-
like, and hence rather than dropping the attribute, for now add it to
the exclusion list to avoid it getting an operand size prefix emitted
in .code16gcc mode. (This will be dealt with later, perhaps together
with FLDENV and friends.)
The flag controlling the default DWARF CIE version to produce now
starts with the value -1. This can be modified with the command line
flag as before, but after command line flag processing, in
md_after_parse_args targets can, if the global still has the value -1,
override this value. This gives a target specific default.
If a CIE version is not select either by command line flag, or a
target specific default, then some new code in dwarf2_init now select
a global default. This remains as version 1 to match previous
behaviour.
This RISC-V has a target specific default of version provided, this
make the return column uleb128, which means we can use all DWARF
registers include CSRs.
I chose to switch to version 3 rather than version 4 as this is most
similar to the global default (version 1). Switching to version 4
adds additional columns to the CIE header.
gas/ChangeLog:
* as.c (flag_dwarf_cie_version): Change initial value to -1, and
update comment.
* config/tc-riscv.c (riscv_after_parse_args): Set
flag_dwarf_cie_version if it has not already been set.
* dwarf2dbg.c (dwarf2_init): Initialise flag_dwarf_cie_version if
needed.
* testsuite/gas/riscv/default-cie-version.d: New file.
* testsuite/gas/riscv/default-cie-version.s: New file.
ld/ChangeLog:
* testsuite/ld-elf/eh5.d: Accept version 3 DWARF CIE.
Change-Id: Ibbfe8f0979fba480bf0a359978b09d2b3055555e
This commit gives DWARF register numbers to the RISC-V CSRs inline
with the RISC-V ELF specification here:
https://github.com/riscv/riscv-elf-psabi-doc/blob/master/riscv-elf.md
The CSRs are defined being numbered from 4096 to 8191.
This adds support to the assembler, required in order to reference
CSRs in, for example .cfi directives.
I have then extended dwarf.c in order to support printing CSR names in
the dumped DWARF output. As the CSR name space is quite large and
only sparsely populated, I have provided a new function to perform
RISC-V DWARF register name lookup which uses a switch statement rather
than the table base approach that other architectures use.
Any CSR that does not have a known name will return a name based on
'csr%d' with the %d being replaced by the offset of the CSR from 4096.
gas/ChangeLog:
* config/tc-riscv.c (tc_riscv_regname_to_dw2regnum): Lookup CSR
names too.
* testsuite/gas/riscv/csr-dw-regnums.d: New file.
* testsuite/gas/riscv/csr-dw-regnums.s: New file.
binutils/ChangeLog:
* dwarf.c (regname_internal_riscv): New function.
(init_dwarf_regnames_riscv): Use new function.
Change-Id: I3f70bc24fa8b3c75744e6775eeeb87db70c7ecfb
We build a hash table of all register classes and numbers. The hash
key is the register name and the hash value is the class and number
encoded into a single value, which is of type 'void *'.
When we pull the values out of the hash we cast them to be a pointer
to a structure, however, we never access the fields of that structure,
we just decode the register class and number from the pointer value
itself.
This commit removes the structure and treats the encoded class and
number as a 'void *' during hash lookup.
gas/ChangeLog:
* config/tc-riscv.c (struct regname): Delete.
(hash_reg_names): Handle value as 'void *'.
Change-Id: Ie7d8f46ca3798f56f4af94395279de684f87f9cc
psb CYSNC was not finding that CSYNC was a correct spelling.
The problem was upper case version was being put in the
wrong hashtable. This fixes the problem by using the
correct hashtable.
Also adds testcases for the upper case versions.
* config/tc-aarch64.c (md_begin): Use correct
hash table for uppercase version of hint.
* testsuite/gas/aarch64/system-2.s: Extend psb case to uppercase.
* testsuite/gas/aarch64/system-2.d: Update.
Change-Id: If43f8b85cacd24840d596c3092b0345e5f212766
This patch changes the CRC extension to use the core feature bits instead
of the coproc/fpu feature bits.
CRC is not an fpu feature and it causes issues with the new fpu reset
patch (f439988037). CRC can be set using
the '.arch_extension' directive, which sets bits in the coproc bitfield. When
a '.fpu' directive is encountered, the CRC feature bit gets removed and
there is no way to set it back using '.fpu'.
With this patch, CRC will be marked in the feature core bits, which prevents
it from getting removed when setting/changing the fpu options.
gas/ChangeLog:
* config/tc-arm.c (arm_ext_crc): New.
(crc_ext_armv8): Remove.
(insns): Rename crc_ext_armv8 to arm_ext_crc.
(arm_cpus): Replace CRC_EXT_ARMV8 with ARM_EXT2_CRC.
(armv8a_ext_table, armv8r_ext_table,
arm_option_extension_value_table): Redefine the crc
extension in terms of ARM_EXT2_CRC.
* gas/testsuite/gas/arm/crc-ext.s: New.
* gas/testsuite/gas/arm/crc-ext.d: New.
include/ChangeLog:
* opcode/arm.h (ARM_EXT2_CRC): New extension feature
to replace CRC_EXT_ARMV8.
(CRC_EXT_ARMV8): Remove and mark bit as unused.
(ARM_ARCH_V8A_CRC, ARM_ARCH_V8_1A, ARM_ARCH_V8_2A,
ARM_ARCH_V8_3A, ARM_ARCH_V8_4A, ARM_ARCH_V8_5A,
ARM_ARCH_V8_6A): Redefine using ARM_EXT2_CRC instead of
CRC_EXT_ARMV8.
opcodes/ChangeLog:
* opcodes/arm-dis.c (arm_opcodes, thumb32_opcodes):
Change the coproc CRC conditions to use the extension
feature set, second word, base on ARM_EXT2_CRC.
... instead of an operand one. Which operand it applies to can be
determined from other operand properties, but as it turns out the only
place it is actually used at doesn't even need further qualification.
This patch enables a few instructions for Armv8.1-M MVE. Currently VLDM,
VSTM, VSTR, VLDR, VPUSH and VPOP are enabled only when the Armv8-M
Floating-point Extension is enabled. According to the ARMv8.1-M ARM,
section A.1.4.2[1], they can be enabled by having "Armv8-M Floating-point
Extension and/or Armv8.1-M MVE".
[1]https://developer.arm.com/docs/ddi0553/bh/armv81-m-architecture-reference-manual
2019-11-12 Mihail Ionescu <mihail.ionescu@arm.com>
* config/tc-arm.c (do_vfp_nsyn_push): Move in order to enable it for
both fpu_vfp_ext_v1xd and mve_ext and add call to the aliased vstm
instruction for mve_ext.
(do_vfp_nsyn_pop): Move in order to enable it for both
fpu_vfp_ext_v1xd and mve_ext and add call to the aliased vldm
instruction for mve_ext.
(do_neon_ldm_stm): Add fpu_vfp_ext_v1 and mve_ext checks.
(insns): Enable vldm, vldmia, vldmdb, vstm, vstmia, vstmdb, vpop,
vpush, and fldd, fstd, flds, fsts for arm_ext_v6t2 instead
of fpu_vfp_ext_v1xd.
* testsuite/gas/arm/v8_1m-mve.s: New.
* testsuite/gas/arm/v8_1m-mve.d: New.
Alan Modra
Nelson Chu
Sergey Belyashov
H.J. Lu
Jan Beulich
Matthew Malcomson
Gitea
Sandra Loosemore
Andre Vieira
Nick Clifton
Srinath Parvathaneni
Jozef Lawrynowicz
Claudiu Zissulescu
Szabolcs Nagy
Andrew Burgess
Andrew Pinski
Mihail Ionescu