Commit Graph

2450 Commits

Author SHA1 Message Date
Phil Blundell
60391a255b Add markers for 2.33 branch to NEWS and ChangeLog files. 2019-09-09 10:27:40 +01:00
Claudiu Zissulescu
cd18a823d1 [ARC] [COMMITTED] Fix FASTMATH field.
Move FASTMATH to the right enum.

2019-08-30  Claudiu Zissulescu <claziss@gmail.com>

        * opcode/arc.h (FASTMATH): Move it from insn_class_t to
        insn_subclass_t enum.
2019-08-30 11:31:19 +03:00
Alan Modra
baf46cd780 ARM CMSE symbols
This patch removes use of st_target_internal to cache the result of
comparing symbol names against CMSE_PREFIX.  The problem with setting
a bit in st_target_internal in swap_symbol_in is that calling
bfd_elf_sym_name from swap_symbol_in requires symtab_hdr, and you
don't know for sure whether swap_symbol_in is operating on dynsyms
(and thus elf_tdata (abfd)->dynsymtab_hdr should be used) or on the
normal symtab (thus elf_tdata (abfd)->symtab_hdr).  You can make an
educated guess based on abfd->flags & DYNAMIC but that relies on
knowing a lot about calls to bfd_elf_get_elf_syms, and is fragile in
the face of possible future changes.

include/
	* elf/arm.h (ARM_GET_SYM_CMSE_SPCL, ARM_SET_SYM_CMSE_SPCL): Delete.
bfd/
	* elf32-arm.c (cmse_scan): Don't use ARM_GET_SYM_CMSE_SPCL,
	instead recognize CMSE_PREFIX in symbol name.
	(elf32_arm_gc_mark_extra_sections): Likewise.
	(elf32_arm_filter_cmse_symbols): Don't test ARM_GET_SYM_CMSE_SPCL.
	(elf32_arm_swap_symbol_in): Don't invoke ARM_SET_SYM_CMSE_SPCL.
2019-08-22 14:14:23 +09:30
Mihailo Stojanovic
f16a9783c5 Add support for a MIPS specific .MIPS.xhash section.
This patch is a reimplementation of [1] which was submitted in 2015 by
Neil Schellenberger. Copyright issue was sorted out [2] last year.
It proposed a new section (.gnu.xhash) and related dynamic tag
(DT_GNU_XHASH). The new section would be virtually identical to the
existing .gnu.hash except for the translation table (xlat) which would
contain correct MIPS .dynsym indexes corresponding to the hashvals in
chains. This is because MIPS ABI imposes a different ordering on the
dynsyms than the one expected by the .gnu.hash section. Another addition
would be a leading word (ngnusyms) which would contain the number of
entries in the translation table.

  In this patch, the new section name and dynamic tag are changed to
reflect the fact that the section should be treated as MIPS-specific
(.MIPS.xhash and DT_MIPS_XHASH).

  This patch addresses the alignment issue as reported in [3], which is
caused by the leading word added to the .MIPS.xhash section. Leading word
is removed in this patch, and the number of entries in the translation
table is now calculated using DT_MIPS_SYMTABNO dynamic tag (this is
addressed by the corresponding glibc patch).

  Suggestions on coding style in [4] were taken into account. Existing
GNU hash testcase was covered, and another one was added in the MIPS
part of the testsuite.

  The other major change is reserving MIPS ABI version 5 for .MIPS.xhash,
marking the need of support for .MIPS.xhash in the dynamic linker (again,
addressed in the corresponding glibc patch). This is something which I
am not sure of, especially after reading [5]. I am confused on whether
this ABI version is reserved for IFUNC, or it can be used for this
purpose.

Already mentioned glibc patch is submitted at:
https://sourceware.org/ml/libc-alpha/2019-06/msg00456.html

[1] https://sourceware.org/ml/binutils/2015-10/msg00057.html
[2] https://sourceware.org/ml/binutils/2018-03/msg00025.html
[3] https://sourceware.org/ml/binutils/2016-01/msg00006.html
[4] https://sourceware.org/ml/binutils/2016-02/msg00097.html
[5] https://sourceware.org/ml/libc-alpha/2016-12/msg00853.html

ld      * emulparams/elf32bmip.sh: Add .MIPS.xhash section.
        * emulparams/elf32bmipn32-defs.sh: Add .MIPS.xhash section.
        * emulparams/elf64bmip-defs.sh: Add .MIPS.xhash section.
        * emultempl/mipself.em: Remove mips_after_parse function.
        * testsuite/ld-elf/hash.d: Update comment.
        * testsuite/ld-mips-elf/hash1.d: New test.
        * testsuite/ld-mips-elf/hash1.s: Ditto.
        * testsuite/ld-mips-elf/hash1a.d: Remove.
        * testsuite/ld-mips-elf/hash1b.d: Ditto.
        * testsuite/ld-mips-elf/hash1c.d: Ditto
        * testsuite/ld-mips-elf/hash2.d: New test.
        * testsuite/ld-mips-elf/mips-elf.exp: New tests.
        * testsuite/ld-mips-elf/start.s: New test.

bfd     * elf-bfd.h (struct elf_backend_data): New members.
        * elflink.c (_bfd_elf_link_create_dynamic_sections): Create
        .gnu.hash section if necessary.
        (struct collect_gnu_hash_codes): New member.
        (elf_gnu_hash_process_symidx): New function name.
        (elf_renumber_gnu_hash_syms): Ignore local and undefined
        symbols. Record xlat location for every symbol which should have
        a .MIPS.xhash entry.
        (bfd_elf_size_dynamic_sections): Add DT_GNU_HASH dynamic tag to
        dynamic section if necessary.
        (GNU_HASH_SECTION_NAME): New define.
        (bfd_elf_size_dynsym_hash_dynstr): Get .MIPS.xhash section.
        Update the section size info.
        * elfxx-mips.c (struct mips_elf_hash_sort_data): New members.
        (struct mips_elf_link_hash_entry): New member.
        (mips_elf_link_hash_newfunc): Initialize .MIPS.xhash translation
        table location.
        (mips_elf_sort_hash_table): Initialize the pointer to the
        .MIPS.xhash section.
        (mips_elf_sort_hash_table_f): Populate the .MIPS.xhash
        translation table entry with the symbol dynindx.
        (_bfd_mips_elf_section_from_shdr): Add SHT_MIPS_XHASH.
        (_bfd_mips_elf_fake_sections): Initialize .MIPS.xhash section
        info.
        (_bfd_mips_elf_create_dynamic_sections): Create .MIPS.xhash
        section.
        (_bfd_mips_elf_size_dynamic_sections): Add DT_MIPS_XHASH tag to
        dynamic section.
        (_bfd_mips_elf_finish_synamic_sections): Add DT_MIPS_XHASH.
        (_bfd_mips_elf_final_write_processing): Set .MIPS.xhash section
        sh_link info.
        (_bfd_mips_elf_get_target_dtag): Get DT_MIPS_XHASH tag.
        (MIPS_LIBC_ABI_XHASH): New ABI version enum value.
        (_bfd_mips_post_process_headers): Mark the ABI version as
        MIPS_LIBC_ABI_XHASH if there exists a .MIPS.xhash section,
        but not a .hash section.
        (_bfd_mips_elf_record_xhash_symbol): New function. Record a
        position in the translation table, associated with the hash
        entry.
        * elfxx-mips.h (literal_reloc_p): Define
        elf_backend_record_xhash_symbol backend hook.
        * elfxx-target.h: Initialize elf_backend_record_xhash_symbol
        backend hook.

include * elf/mips.h (SHT_GNU_XHASH): New define.
        (DT_GNU_XHASH): New define.

binutils * readelf.c (get_mips_dynamic_type): Return MIPS_XHASH dynamic type.
        (get_mips_section_type_name): Return MI{S_XHASH name string.
        (dynamic_section_mips_val): Initialize the .MIPS.xhash dynamic
        info.
        (process_symbol_table): Initialize the .MIPS.xhash section
        pointer. Adjust the readelf output to support the new section.
        (process_object): Set the .MIPS.xhash dynamic info to zero.
2019-08-09 11:06:37 +01:00
Yoshinori Sato
7b1dd70105 Update the handling of shift rotate and load/store multiple instructions in the H8300 assembler.
incldue	* opcode/h8300.h (EXPAND_UNOP_EXTENDED_B): Add MODEL.
	(EXPAND_UNOP_EXTENDED_W): Likewise.
	(EXPAND_UNOP_EXTENDED_L): Likewise.
	(struct h8_opcode h8_opcodes): Likewise.
	(struct h8_opcode h8_opcodes): tas / ldm / stm supported H8S or
	later.
2019-08-08 13:59:17 +01:00
Claudiu Zissulescu
7e126ba31a [ARC] Update ARC opcode table
Update ARC opcode table by cleaning up invalid instructions, and fixing wrong encodings.

opcodes/
xxxx-xx-xx  Claudiu Zissulescu  <claziss@synopsys.com>

	* arc-ext-tbl.h (bspeek): Remove it, added to main table.
	(bspop): Likewise.
	(modapp): Likewise.
	* arc-opc.c (RAD_CHK): Add.
	* arc-tbl.h: Regenerate.

include/
xxxx-xx-xx  Claudiu Zissulescu  <claziss@synopsys.com>

	* include/opcode/arc.h (FASTMATH): Add.
	(SWITCH): Likewise.
2019-07-24 16:46:01 +03:00
Alan Modra
7137a1ed0a PT_GNU_MBIND section mapping
* elf/internal.h (ELF_SECTION_IN_SEGMENT_1): Exclude non-alloc
	sections in GNU_MBIND segments.
2019-07-24 16:12:01 +09:30
Omar Majid
1dd1bc4daf Allow objdump to recognise the System.Runtime.dll files that get shipped with .NET Core 2.1.
include	* coff/i386.h (IMAGE_FILE_MACHINE_NATIVE_APPLE_OVERRIDE): Define.
	(IMAGE_FILE_MACHINE_NATIVE_FREEBSD_OVERRIDE): Define.
	(IMAGE_FILE_MACHINE_NATIVE_LINUX_OVERRIDE): Define.
	(IMAGE_FILE_MACHINE_NATIVE_NETBSD_OVERRIDE): Define.
	(I386_APPLE_MAGIC): Define.
	(I386_FREEBSD_MAGIC): Define.
	(I386_LINUX_MAGIC): Define.
	(I386_NETBSD_MAGIC): Define.
	(I386BADMAG): Extend macro to allow new magic numbers.
	* coff/x86_64.h (IMAGE_FILE_MACHINE_NATIVE_APPLE_OVERRIDE): Define.
	(IMAGE_FILE_MACHINE_NATIVE_FREEBSD_OVERRIDE): Define.
	(IMAGE_FILE_MACHINE_NATIVE_LINUX_OVERRIDE): Define.
	(IMAGE_FILE_MACHINE_NATIVE_NETBSD_OVERRIDE): Define.
	(AMD64_APPLE_MAGIC): Define.
	(AMD64_FREEBSD_MAGIC): Define.
	(AMD64_LINUX_MAGIC): Define.
	(AMD64_NETBSD_MAGIC): Define.
	(AMD64BADMAG): Extend macro to allow new magic numbers.

bfd	* coffcode.h (coff_set_arch_mach_hook): Handle I386_APPLE_MAGIC,
	I386_FREEBSD_MAGIC, I386_LINUX_MAGIC, I386_NETBSD_MAGIC,
	AMD64_APPLE_MAGIC, AMD64_FREEBSD_MAGIC, AMD64_LINUX_MAGIC,
	AMD64_NETBSD_MAGIC.
	* peXXigen.c: Add comment about source of .NET magic numbers.

binutils* Makefile.am (AUTOMAKE_OPTIONS): Add subdir-objects
	(GENTESTDLLSPROG): Define.
	(TEST_PROGS): Add GENTESTDLLSPROG.
	* Makefile.in: Regenerate.
	* testsuite/binutils-all/objdump.exp
	(test_objdump_dotnet_assemblies): New proc.
	Run the new proc.
	* testsuite/gentestdlls.c: New source file.
2019-07-23 09:44:57 +01:00
Alan Modra
c213164ad2 [PowerPC64] pc-relative TLS relocations
This patch supports using pcrel instructions in TLS code sequences.  A
number of new relocations are needed, gas operand modifiers to
generate those relocations, and new TLS optimisation.  For
optimisation it turns out that the new pcrel GD and LD sequences can
be distinguished from the non-pcrel GD and LD sequences by there being
different relocations on the new sequence.  The final "add ra,rb,13"
on IE sequences similarly needs a new relocation, or as I chose, a
modification of R_PPC64_TLS.  On pcrel IE code, the R_PPC64_TLS points
one byte into the "add" instruction rather than being on the
instruction boundary.

GD:
 pla 3,z@got@tlsgd@pcrel	  # R_PPC64_GOT_TLSGD34
 bl __tls_get_addr@notoc(z@tlsgd) # R_PPC64_TLSGD and R_PPC64_REL24_NOTOC
  edited to IE
   pld 3,z@got@tprel@pcrel
   add 3,3,13
  edited to LE
   paddi 3,13,z@tprel
   nop

LD:
 pla 3,z@got@tlsld@pcrel	  # R_PPC64_GOT_TLSLD34
 bl __tls_get_addr@notoc(z@tlsld) # R_PPC64_TLSLD and R_PPC64_REL24_NOTOC
 ..
 paddi 9,3,z2@dtprel
 pld 10,z3@got@dtprel@pcrel
 add 10,10,3
  edited to LE
   paddi 3,13,0x1000
   nop

IE:
 pld 9,z@got@tprel@pcrel	  # R_PPC64_GOT_TPREL34
 add 3,9,z@tls@pcrel		  # R_PPC64_TLS at insn+1
 ldx 4,9,z@tls@pcrel
 lwax 5,9,z@tls@pcrel
 stdx 5,9,z@tls@pcrel
  edited to LE
  paddi 9,13,z@tprel
  nop
  ld 4,0(9)
  lwa 5,0(9)
  std 5,0(9)

LE:
 paddi 10,13,z@tprel

include/
	* elf/ppc64.h (R_PPC64_TPREL34, R_PPC64_DTPREL34),
	(R_PPC64_GOT_TLSGD34, R_PPC64_GOT_TLSLD34),
	(R_PPC64_GOT_TPREL34, R_PPC64_GOT_DTPREL34): Define.
	(IS_PPC64_TLS_RELOC): Include new tls relocs.
bfd/
	* reloc.c (BFD_RELOC_PPC64_TPREL34, BFD_RELOC_PPC64_DTPREL34),
	(BFD_RELOC_PPC64_GOT_TLSGD34, BFD_RELOC_PPC64_GOT_TLSLD34),
	(BFD_RELOC_PPC64_GOT_TPREL34, BFD_RELOC_PPC64_GOT_DTPREL34),
	(BFD_RELOC_PPC64_TLS_PCREL): New pcrel tls relocs.
	* elf64-ppc.c (ppc64_elf_howto_raw): Add howtos for pcrel tls relocs.
	(ppc64_elf_reloc_type_lookup): Translate pcrel tls relocs.
	(must_be_dyn_reloc, dec_dynrel_count): Add R_PPC64_TPREL64.
	(ppc64_elf_check_relocs): Support pcrel tls relocs.
	(ppc64_elf_tls_optimize, ppc64_elf_relocate_section): Likewise.
	* bfd-in2.h: Regenerate.
	* libbfd.h: Regenerate.
gas/
	* config/tc-ppc.c (ppc_elf_suffix): Map "tls@pcrel", "got@tlsgd@pcrel",
	"got@tlsld@pcrel", "got@tprel@pcrel", and "got@dtprel@pcrel".
	(fixup_size, md_assemble): Handle pcrel tls relocs.
	(ppc_force_relocation, ppc_fix_adjustable): Likewise.
	(md_apply_fix, tc_gen_reloc): Likewise.
ld/
	* testsuite/ld-powerpc/tlsgd.d,
	* testsuite/ld-powerpc/tlsgd.s,
	* testsuite/ld-powerpc/tlsie.d,
	* testsuite/ld-powerpc/tlsie.s,
	* testsuite/ld-powerpc/tlsld.d,
	* testsuite/ld-powerpc/tlsld.s: New tests.
	* testsuite/ld-powerpc/powerpc.exp: Run them.
2019-07-19 18:01:25 +09:30
Nick Alcock
12a0b67d28 libctf: introduce ctf_func_type_{info,args}, ctf_type_aname_raw
The first two of these allow you to get function type info and args out
of the types section give a type ID: astonishingly, this was missing
from libctf before now: so even though types of kind CTF_K_FUNCTION were
supported, you couldn't find out anything about them.  (The existing
ctf_func_info and ctf_func_args only allow you to get info about
functions in the function section, i.e. given symbol table indexes, not
type IDs.)

The second of these allows you to get the raw undecorated name out of
the CTF section (strdupped for safety) without traversing subtypes to
build a full C identifier out of it.  It's useful for things that are
already tracking the type kind etc and just need an unadorned name.

include/
	* ctf-api.h (ECTF_NOTFUNC): Fix description.
	(ctf_func_type_info): New.
	(ctf_func_type_args): Likewise.
libctf/
	* ctf-types.c (ctf_type_aname_raw): New.
	(ctf_func_type_info): Likewise.
	(ctf_func_type_args): Likewise.
	* ctf-error.c (_ctf_errlist): Fix description.
2019-07-18 20:53:57 +01:00
Jan Beulich
21df382b91 x86: fold SReg{2,3}
They're the only exception to there generally being no mix of register
kinds possible in an insn operand template, and there being two bits per
operand for their representation is also quite wasteful, considering the
low number of uses.  Fold both bits and deal with the little bit of
fallout.

Also take the liberty and drop dead code trying to set REX_B: No segment
register has RegRex set on it.

Additionally I was quite surprised that PUSH/POP with the permitted
segment registers is not covered by the test cases.  Add the missing
pieces.
2019-07-16 09:30:29 +02:00
Matthew Malcomson
41be57caf3 [gas][aarch64][SVE2] Fix pmull{t,b} requirement on SVE2-AES
I had mistakenly given all variants of the new SVE2 instructions
pmull{t,b} a dependency on the feature +sve2-aes.

Only the variant specifying .Q -> .D  sizes should have that
restriction.

This patch fixes that mistake and updates the testsuite to have extra
tests (matching the given set of tests per line in aarch64-tbl.h that
the rest of the SVE2 tests follow).

We also add a line in the documentation of the command line to clarify
how to enable `pmull{t,b}` of this larger size.  This is needed because
all other instructions gated under the `sve2-aes` architecture extension
are marked in the instruction documentation by an `HaveSVE2AES` check
while pmull{t,b} is gated under the `HaveSVE2PMULL128` check.

Regtested targeting aarch64-linux.

gas/ChangeLog:

2019-07-01  Matthew Malcomson  <matthew.malcomson@arm.com>

	* testsuite/gas/aarch64/illegal-sve2-aes.d: Update tests.
	* testsuite/gas/aarch64/illegal-sve2.l: Update tests.
	* doc/c-aarch64.texi: Add special note of pmull{t,b}
	instructions under the sve2-aes architecture extension.
	* testsuite/gas/aarch64/illegal-sve2.s: Add small size
	pmull{t,b} instructions.
	* testsuite/gas/aarch64/sve2.d: Add small size pmull{t,b}
	disassembly.
	* testsuite/gas/aarch64/sve2.s: Add small size pmull{t,b}
	instructions.

include/ChangeLog:

2019-07-01  Matthew Malcomson  <matthew.malcomson@arm.com>

	* opcode/aarch64.h (enum aarch64_insn_class): sve_size_013
	renamed to sve_size_13.

opcodes/ChangeLog:

2019-07-01  Matthew Malcomson  <matthew.malcomson@arm.com>

	* aarch64-asm.c (aarch64_encode_variant_using_iclass): Use new
	sve_size_13 icode to account for variant behaviour of
	pmull{t,b}.
	* aarch64-dis-2.c: Regenerate.
	* aarch64-dis.c (aarch64_decode_variant_using_iclass): Use new
	sve_size_13 icode to account for variant behaviour of
	pmull{t,b}.
	* aarch64-tbl.h (OP_SVE_VVV_HD_BS): Add new qualifier.
	(OP_SVE_VVV_Q_D): Add new qualifier.
	(OP_SVE_VVV_QHD_DBS): Remove now unused qualifier.
	(struct aarch64_opcode): Split pmull{t,b} into those requiring
	AES and those not.
2019-07-01 15:17:22 +01:00
Nick Alcock
7cee18263c libctf: endianness fixes
Testing of the first code to generate CTF_K_SLICEs on big-endian
revealed a bunch of new problems in this area.  Most importantly, the
trick we did earlier to avoid wasting two bytes on padding in the
ctf_slice_t is best avoided: because it leads to the whole file after
that point no longer being naturally aligned, all multibyte accesses
from then on must use memmove() to avoid unaligned access on platforms
where that is fatal.  In future, this is planned, but for now we are
still doing direct access in many places, so we must revert to making
ctf_slice_t properly aligned for storage in an array.

Rather than wasting bytes on padding, we boost the size of cts_offset
and cts_bits.  This is still a waste of space (we cannot have offsets or
bits in bitfields > 256) but it cannot be avoided for now, and slices
are not so common that this will be a serious problem.

A possibly-worse endianness problem fixed at the same time involves
a codepath used only for foreign-endian, uncompressed CTF files, where
we were not copying the actual CTF data into the buffer, leading to
libctf reading only zeroes (or, possibly, uninitialized garbage).

Finally, when we read in a CTF file, we copy the header and work from
the copy.  We were flipping the endianness of the header copy, and of
the body of the file buffer, but not of the header in the file buffer
itself: so if we write the file back out again we end up with an
unreadable frankenfile with header and body of different endiannesses.
Fix by flipping both copies of the header.

include/
	* ctf.h (ctf_slice_t): Make cts_offset and cts_bits unsigned
	short, so following structures are properly aligned.

libctf/
	* ctf-open.c (get_vbytes_common): Return the new slice size.
	(ctf_bufopen): Flip the endianness of the CTF-section header copy.
	Remember to copy in the CTF data when opening an uncompressed
	foreign-endian CTF file.  Prune useless variable manipulation.
2019-06-21 13:04:02 +01:00
Szabolcs Nagy
e30d1fa1bf Add R_AARCH64_P32_MOVW_PREL_* ELF32 relocs
These ilp32 relocations were missing for some reason.

bfd/ChangeLog:

	* elfnn-aarch64.c: Enable MOVW_PREL relocs for ELF32.

include/ChangeLog:

	* elf/aarch64.h (R_AARCH64_P32_MOVW_PREL_G0): Define.
	(R_AARCH64_P32_MOVW_PREL_G0_NC): Define.
	(R_AARCH64_P32_MOVW_PREL_G1): Define.

ld/ChangeLog:

	* testsuite/ld-aarch64/aarch64-elf.exp: Add emit-relocs-22 and -23.
	* testsuite/ld-aarch64/emit-relocs-22.d: New test.
	* testsuite/ld-aarch64/emit-relocs-22.s: New test.
	* testsuite/ld-aarch64/emit-relocs-23.d: New test.
	* testsuite/ld-aarch64/emit-relocs-23.s: New test.
2019-06-14 12:02:19 +01:00
Nick Alcock
a610aa4f9c libctf: fix the type of ctf_enum.cte_value
This stops the file format from depending on the size of the host int.
(It does mean that we cannot encode enums with a value > 2^32 on
platforms with an int > 2^32: this will be fixed in the next format
revision.)

include/
	* ctf.h (ctf_enum.cte_value): Fix type to int32_t.
2019-06-04 17:05:08 +01:00
Jose E. Marchesi
a0486bac41 libctf: fix a number of build problems found on Solaris and NetBSD
- Use of nonportable <endian.h>
- Use of qsort_r
- Use of zlib without appropriate magic to pull in the binutils zlib
- Use of off64_t without checking (fixed by dropping the unused fields
  that need off64_t entirely)
- signedness problems due to long being too short a type on 32-bit
  platforms: ctf_id_t is now 'unsigned long', and CTF_ERR must be
  used only for functions that return ctf_id_t
- One lingering use of bzero() and of <sys/errno.h>

All fixed, using code from gnulib where possible.

Relatedly, set cts_size in a couple of places it was missed
(string table and symbol table loading upon ctf_bfdopen()).

binutils/
	* objdump.c (make_ctfsect): Drop cts_type, cts_flags, and
	cts_offset.
	* readelf.c (shdr_to_ctf_sect): Likewise.
include/
	* ctf-api.h (ctf_sect_t): Drop cts_type, cts_flags, and cts_offset.
	(ctf_id_t): This is now an unsigned type.
	(CTF_ERR): Cast it to ctf_id_t.  Note that it should only be used
	for ctf_id_t-returning functions.
libctf/
	* Makefile.am (ZLIB): New.
	(ZLIBINC): Likewise.
	(AM_CFLAGS): Use them.
	(libctf_a_LIBADD): New, for LIBOBJS.
	* configure.ac: Check for zlib, endian.h, and qsort_r.
	* ctf-endian.h: New, providing htole64 and le64toh.
	* swap.h: Code style fixes.
	(bswap_identity_64): New.
	* qsort_r.c: New, from gnulib (with one added #include).
	* ctf-decls.h: New, providing a conditional qsort_r declaration,
	and unconditional definitions of MIN and MAX.
	* ctf-impl.h: Use it.  Do not use <sys/errno.h>.
	(ctf_set_errno): Now returns unsigned long.
	* ctf-util.c (ctf_set_errno): Adjust here too.
	* ctf-archive.c: Use ctf-endian.h.
	(ctf_arc_open_by_offset): Use memset, not bzero.  Drop cts_type,
	cts_flags and cts_offset.
	(ctf_arc_write): Drop debugging dependent on the size of off_t.
	* ctf-create.c: Provide a definition of roundup if not defined.
	(ctf_create): Drop cts_type, cts_flags and cts_offset.
	(ctf_add_reftype): Do not check if type IDs are below zero.
	(ctf_add_slice): Likewise.
	(ctf_add_typedef): Likewise.
	(ctf_add_member_offset): Cast error-returning ssize_t's to size_t
	when known error-free.  Drop CTF_ERR usage for functions returning
	int.
	(ctf_add_member_encoded): Drop CTF_ERR usage for functions returning
	int.
	(ctf_add_variable): Likewise.
	(enumcmp): Likewise.
	(enumadd): Likewise.
	(membcmp): Likewise.
	(ctf_add_type): Likewise.  Cast error-returning ssize_t's to size_t
	when known error-free.
	* ctf-dump.c (ctf_is_slice): Drop CTF_ERR usage for functions
	returning int: use CTF_ERR for functions returning ctf_type_id.
	(ctf_dump_label): Likewise.
	(ctf_dump_objts): Likewise.
	* ctf-labels.c (ctf_label_topmost): Likewise.
	(ctf_label_iter): Likewise.
	(ctf_label_info): Likewise.
	* ctf-lookup.c (ctf_func_args): Likewise.
	* ctf-open.c (upgrade_types): Cast to size_t where appropriate.
	(ctf_bufopen): Likewise.  Use zlib types as needed.
	* ctf-types.c (ctf_member_iter): Drop CTF_ERR usage for functions
	returning int.
	(ctf_enum_iter): Likewise.
	(ctf_type_size): Likewise.
	(ctf_type_align): Likewise.  Cast to size_t where appropriate.
	(ctf_type_kind_unsliced): Likewise.
	(ctf_type_kind): Likewise.
	(ctf_type_encoding): Likewise.
	(ctf_member_info): Likewise.
	(ctf_array_info): Likewise.
	(ctf_enum_value): Likewise.
	(ctf_type_rvisit): Likewise.
	* ctf-open-bfd.c (ctf_bfdopen): Drop cts_type, cts_flags and
	cts_offset.
	(ctf_simple_open): Likewise.
	(ctf_bfdopen_ctfsect): Likewise.  Set cts_size properly.
	* Makefile.in: Regenerate.
	* aclocal.m4: Likewise.
	* config.h: Likewise.
	* configure: Likewise.
2019-05-31 11:10:51 +02:00
Nick Alcock
a30b3e182a libctf: debug dumping
This introduces ctf_dump(), an iterator which returns a series of
strings, each representing a debugging dump of one item from a given
section in the CTF file.  The items may be multiline: a callback is
provided to allow the caller to decorate each line as they desire before
the line is returned.

libctf/
	* ctf-dump.c: New.

include/
	* ctf-api.h (ctf_dump_decorate_f): New.
	(ctf_dump_state_t): new.
	(ctf_dump): New.
2019-05-28 17:09:37 +01:00
Nick Alcock
6dbf2b7340 libctf: labels
This facility allows you to associate regions of type IDs with *labels*,
a labelled tiling of the type ID space. You can use these to define
CTF containers with distinct parents for distinct ranges of the ID
space, or to assist with parallelization of CTF processing, or for any
other purpose you can think of.

Notably absent from here (though declared in the API header) is any way
to define new labels: this will probably be introduced soon, as part of
the linker deduplication work.  (One existed in the past, but was deeply
tied to the Solaris CTF file generator and had to be torn out.)

libctf/
	* ctf-labels.c: New.
include/
	* ctf-api.h (ctf_label_f): New.
	(ctf_label_set): New.
	(ctf_label_get): New.
	(ctf_label_topmost): New.
	(ctf_label_info): New.
	(ctf_label_iter): New.
2019-05-28 17:09:30 +01:00
Nick Alcock
6c33b742ce libctf: library version enforcement
This old Solaris standard allows callers to specify that they are
expecting one particular API and/or CTF file format from the library.

libctf/
	* ctf-impl.h (_libctf_version): New declaration.
	* ctf-subr.c (_libctf_version): Define it.
	(ctf_version): New.

include/
	* ctf-api.h (ctf_version): New.
2019-05-28 17:08:29 +01:00
Nick Alcock
b437bfe0f4 libctf: lookups by name and symbol
These functions allow you to look up types given a name in a simple
subset of C declarator syntax (no function pointers), to look up the
types of variables given a name, and to look up the types of data
objects and the type signatures of functions given symbol table offsets.

(Despite its name, one function in this commit, ctf_lookup_symbol_name(),
is for the internal use of libctf only, and does not appear in any
public header files.)

libctf/
	* ctf-lookup.c (isqualifier): New.
	(ctf_lookup_by_name): Likewise.
	(struct ctf_lookup_var_key): Likewise.
	(ctf_lookup_var): Likewise.
	(ctf_lookup_variable): Likewise.
	(ctf_lookup_symbol_name): Likewise.
	(ctf_lookup_by_symbol): Likewise.
	(ctf_func_info): Likewise.
	(ctf_func_args): Likewise.

include/
	* ctf-api.h (ctf_func_info): New.
	(ctf_func_args): Likewise.
	(ctf_lookup_by_symbol): Likewise.
	(ctf_lookup_by_symbol): Likewise.
	(ctf_lookup_variable): Likewise.
2019-05-28 17:08:19 +01:00
Nick Alcock
316afdb130 libctf: core type lookup
Finally we get to the functions used to actually look up and enumerate
properties of types in a container (names, sizes, members, what type a
pointer or cv-qual references, determination of whether two types are
assignment-compatible, etc).

With a very few exceptions these do not work for types newly added via
ctf_add_*(): they only work on types in read-only containers, or types
added before the most recent call to ctf_update().

This also adds support for lookup of "variables" (string -> type ID
mappings) and for generation of C type names corresponding to a type ID.

libctf/
	* ctf-decl.c: New file.
	* ctf-types.c: Likewise.
	* ctf-impl.h: New declarations.

include/
	* ctf-api.h (ctf_visit_f): New definition.
	(ctf_member_f): Likewise.
	(ctf_enum_f): Likewise.
	(ctf_variable_f): Likewise.
	(ctf_type_f): Likewise.
	(ctf_type_isparent): Likewise.
	(ctf_type_ischild): Likewise.
	(ctf_type_resolve): Likewise.
	(ctf_type_aname): Likewise.
	(ctf_type_lname): Likewise.
	(ctf_type_name): Likewise.
	(ctf_type_sizee): Likewise.
	(ctf_type_align): Likewise.
	(ctf_type_kind): Likewise.
	(ctf_type_reference): Likewise.
	(ctf_type_pointer): Likewise.
	(ctf_type_encoding): Likewise.
	(ctf_type_visit): Likewise.
	(ctf_type_cmp): Likewise.
	(ctf_type_compat): Likewise.
	(ctf_member_info): Likewise.
	(ctf_array_info): Likewise.
	(ctf_enum_name): Likewise.
	(ctf_enum_value): Likewise.
	(ctf_member_iter): Likewise.
	(ctf_enum_iter): Likewise.
	(ctf_type_iter): Likewise.
	(ctf_variable_iter): Likewise.
2019-05-28 17:08:14 +01:00
Nick Alcock
143dce8481 libctf: ELF file opening via BFD
These functions let you open an ELF file with a customarily-named CTF
section in it, automatically opening the CTF file or archive and
associating the symbol and string tables in the ELF file with the CTF
container, so that you can look up the types of symbols in the ELF file
via ctf_lookup_by_symbol(), and so that strings can be shared between
the ELF file and CTF container, to save space.

It uses BFD machinery to do so.  This has now been lightly tested and
seems to work.  In particular, if you already have a bfd you can pass
it in to ctf_bfdopen(), and if you want a bfd made for you you can
call ctf_open() or ctf_fdopen(), optionally specifying a target (or
try once without a target and then again with one if you get
ECTF_BFD_AMBIGUOUS back).

We use a forward declaration for the struct bfd in ctf-api.h, so that
ctf-api.h users are not required to pull in <bfd.h>.  (This is mostly
for the sake of readelf.)

libctf/
	* ctf-open-bfd.c: New file.
	* ctf-open.c (ctf_close): New.
	* ctf-impl.h: Include bfd.h.
	(ctf_file): New members ctf_data_mmapped, ctf_data_mmapped_len.
	(ctf_archive_internal): New members ctfi_abfd, ctfi_data,
	ctfi_bfd_close.
	(ctf_bfdopen_ctfsect): New declaration.
	(_CTF_SECTION): likewise.

include/
	* ctf-api.h (struct bfd): New forward.
	(ctf_fdopen): New.
	(ctf_bfdopen): Likewise.
	(ctf_open): Likewise.
	(ctf_arc_open): Likewise.
2019-05-28 17:08:08 +01:00
Nick Alcock
9402cc593f libctf: mmappable archives
If you need to store a large number of CTF containers somewhere, this
provides a dedicated facility for doing so: an mmappable archive format
like a very simple tar or ar without all the system-dependent format
horrors or need for heavy file copying, with built-in compression of
files above a particular size threshold.

libctf automatically mmap()s uncompressed elements of these archives, or
uncompresses them, as needed.  (If the platform does not support mmap(),
copying into dynamically-allocated buffers is used.)

Archive iteration operations are partitioned into raw and non-raw
forms. Raw operations pass thhe raw archive contents to the callback:
non-raw forms open each member with ctf_bufopen() and pass the resulting
ctf_file_t to the iterator instead.  This lets you manipulate the raw
data in the archive, or the contents interpreted as a CTF file, as
needed.

It is not yet known whether we will store CTF archives in a linked ELF
object in one of these (akin to debugdata) or whether they'll get one
section per TU plus one parent container for types shared between them.
(In the case of ELF objects with very large numbers of TUs, an archive
of all of them would seem preferable, so we might just use an archive,
and add lzma support so you can assume that .gnu_debugdata and .ctf are
compressed using the same algorithm if both are present.)

To make usage easier, the ctf_archive_t is not the on-disk
representation but an abstraction over both ctf_file_t's and archives of
many ctf_file_t's: users see both CTF archives and raw CTF files as
ctf_archive_t's upon opening, the only difference being that a raw CTF
file has only a single "archive member", named ".ctf" (the default if a
null pointer is passed in as the name).  The next commit will make use
of this facility, in addition to providing the public interface to
actually open archives.  (In the future, it should be possible to have
all CTF sections in an ELF file appear as an "archive" in the same
fashion.)

This machinery is also used to allow library-internal creators of
ctf_archive_t's (such as the next commit) to stash away an ELF string
and symbol table, so that all opens of members in a given archive will
use them.  This lets CTF archives exploit the ELF string and symbol
table just like raw CTF files can.

(All this leads to somewhat confusing type naming.  The ctf_archive_t is
a typedef for the opaque internal type, struct ctf_archive_internal: the
non-internal "struct ctf_archive" is the on-disk structure meant for
other libraries manipulating CTF files.  It is probably clearest to use
the struct name for struct ctf_archive_internal inside the program, and
the typedef names outside.)

libctf/
	* ctf-archive.c: New.
	* ctf-impl.h (ctf_archive_internal): New type.
	(ctf_arc_open_internal): New declaration.
	(ctf_arc_bufopen): Likewise.
	(ctf_arc_close_internal): Likewise.
include/
	* ctf.h (CTFA_MAGIC): New.
	(struct ctf_archive): New.
	(struct ctf_archive_modent): Likewise.
	* ctf-api.h (ctf_archive_member_f): New.
	(ctf_archive_raw_member_f): Likewise.
	(ctf_arc_write): Likewise.
	(ctf_arc_close): Likewise.
	(ctf_arc_open_by_name): Likewise.
	(ctf_archive_iter): Likewise.
	(ctf_archive_raw_iter): Likewise.
	(ctf_get_arc): Likewise.
2019-05-28 17:07:55 +01:00
Nick Alcock
72f3392127 libctf: opening
This fills in the other half of the opening/creation puzzle: opening of
already-existing CTF files.  Such files are always read-only: if you
want to add to a CTF file opened with one of the opening functions in
this file, use ctf_add_type(), in a later commit, to copy appropriate
types into a newly ctf_create()d, writable container.

The lowest-level opening functions are in here: ctf_bufopen(), which
takes ctf_sect_t structures akin to ELF section headers, and
ctf_simple_open(), which can be used if you don't have an entire ELF
section header to work from.  Both will malloc() new space for the
buffers only if necessary, will mmap() directly from the file if
requested, and will mprotect() it afterwards to prevent accidental
corruption of the types. These functions are also used by ctf_update()
when converting types in a writable container into read-only types that
can be looked up using the lookup functions (in later commits).

The files are always of the native endianness of the system that created
them: at read time, the endianness of the header magic number is used to
determine whether or not the file needs byte-swapping, and the entire
thing is aggressively byte-swapped.

The agggressive nature of this swapping avoids complicating the rest of
the code with endianness conversions, while the native endianness
introduces no byte-swapping overhead in the common case. (The
endianness-independence code is also much newer than everything else in
this file, and deserves closer scrutiny.)

The accessors at the top of the file are there to transparently support
older versions of the CTF file format, allowing translation from older
formats that have different sizes for the structures in ctf.h:
currently, these older formats are intermingled with the newer ones in
ctf.h: they will probably migrate to a compatibility header in time, to
ease readability.  The ctf_set_base() function is split out for the same
reason: when conversion code to a newer format is written, it would need
to malloc() new storage for the entire ctf_file_t if a file format
change causes it to grow, and for that we need ctf_set_base() to be a
separate function.

One pair of linked data structures supported by this file has no
creation code in libctf yet: the data and function object sections read
by init_symtab(). These will probably arrive soon, when the linker comes
to need them. (init_symtab() has hardly been changed since 2009, but if
any code in libctf has rotted over time, this will.)

A few simple accessors are also present that can even be called on
read-only containers because they don't actually modify them, since the
relevant things are not stored in the container but merely change its
operation: ctf_setmodel(), which lets you specify whether a container is
LP64 or not (used to statically determine the sizes of a few types),
ctf_import(), which is the only way to associate a parent container with
a child container, and ctf_setspecific(), which lets the caller
associate an arbitrary pointer with the CTF container for any use. If
the user doesn't call these functions correctly, libctf will misbehave:
this is particularly important for ctf_import(), since a container built
against a given parent container will not be able to resolve types that
depend on types in the parent unless it is ctf_import()ed with a parent
container with the same set of types at the same IDs, or a superset.

Possible future extensions (also noted in the ctf-hash.c file) include
storing a count of things so that we don't need to do one pass over the
CTF file counting everything, and computing a perfect hash at CTF
creation time in some compact form, storing it in the CTF file, and
using it to hash things so we don't need to do a second pass over the
entire CTF file to set up the hashes used to go from names to type IDs.
(There are multiple such hashes, one for each C type namespace: types,
enums, structs, and unions.)

libctf/
	* ctf-open.c: New file.
	* swap.h: Likewise.
include/
	* ctf-api.h (ctf_file_close): New declaration.
	(ctf_getdatasect): Likewise.
	(ctf_parent_file): Likewise.
	(ctf_parent_name): Likewise.
	(ctf_parent_name_set): Likewise.
	(ctf_import): Likewise.
	(ctf_setmodel): Likewise.
	(ctf_getmodel): Likewise.
	(ctf_setspecific): Likewise.
	(ctf_getspecific): Likewise.
2019-05-28 17:07:46 +01:00
Nick Alcock
47d546f427 libctf: creation functions
The CTF creation process looks roughly like (error handling elided):

int err;
ctf_file_t *foo = ctf_create (&err);

ctf_id_t type = ctf_add_THING (foo, ...);
ctf_update (foo);
ctf_*write (...);

Some ctf_add_THING functions accept other type IDs as arguments,
depending on the type: cv-quals, pointers, and structure and union
members all take other types as arguments.  So do 'slices', which
let you take an existing integral type and recast it as a type
with a different bitness or offset within a byte, for bitfields.
One class of THING is not a type: "variables", which are mappings
of names (in the internal string table) to types.  These are mostly
useful when encoding variables that do not appear in a symbol table
but which some external user has some other way to figure out the
address of at runtime (dynamic symbol lookup or querying a VM
interpreter or something).

You can snapshot the creation process at any point: rolling back to a
snapshot deletes all types and variables added since that point.

You can make arbitrary type queries on the CTF container during the
creation process, but you must call ctf_update() first, which
translates the growing dynamic container into a static one (this uses
the CTF opening machinery, added in a later commit), which is quite
expensive.  This function must also be called after adding types
and before writing the container out.

Because addition of types involves looking up existing types, we add a
little of the type lookup machinery here, as well: only enough to
look up types in dynamic containers under construction.

libctf/
	* ctf-create.c: New file.
	* ctf-lookup.c: New file.

include/
	* ctf-api.h (zlib.h): New include.
	(ctf_sect_t): New.
	(ctf_sect_names_t): Likewise.
	(ctf_encoding_t): Likewise.
	(ctf_membinfo_t): Likewise.
	(ctf_arinfo_t): Likewise.
	(ctf_funcinfo_t): Likewise.
	(ctf_lblinfo_t): Likewise.
	(ctf_snapshot_id_t): Likewise.
	(CTF_FUNC_VARARG): Likewise.
	(ctf_simple_open): Likewise.
	(ctf_bufopen): Likewise.
	(ctf_create): Likewise.
	(ctf_add_array): Likewise.
	(ctf_add_const): Likewise.
	(ctf_add_enum_encoded): Likewise.
	(ctf_add_enum): Likewise.
	(ctf_add_float): Likewise.
	(ctf_add_forward): Likewise.
	(ctf_add_function): Likewise.
	(ctf_add_integer): Likewise.
	(ctf_add_slice): Likewise.
	(ctf_add_pointer): Likewise.
	(ctf_add_type): Likewise.
	(ctf_add_typedef): Likewise.
	(ctf_add_restrict): Likewise.
	(ctf_add_struct): Likewise.
	(ctf_add_union): Likewise.
	(ctf_add_struct_sized): Likewise.
	(ctf_add_union_sized): Likewise.
	(ctf_add_volatile): Likewise.
	(ctf_add_enumerator): Likewise.
	(ctf_add_member): Likewise.
	(ctf_add_member_offset): Likewise.
	(ctf_add_member_encoded): Likewise.
	(ctf_add_variable): Likewise.
	(ctf_set_array): Likewise.
	(ctf_update): Likewise.
	(ctf_snapshot): Likewise.
	(ctf_rollback): Likewise.
	(ctf_discard): Likewise.
	(ctf_write): Likewise.
	(ctf_gzwrite): Likewise.
	(ctf_compress_write): Likewise.
2019-05-28 17:07:40 +01:00
Nick Alcock
479604f44f libctf: error handling
CTF functions return zero on success or an extended errno value which
can be translated into a string via the functions in this commit.

The errno numbers start at -CTF_BASE.

libctf/
	* ctf-error.c: New file.

include/
	* ctf-api.h (ctf_errno): New declaration.
	(ctf_errmsg): Likewise.
2019-05-28 17:07:24 +01:00
Nick Alcock
60da9d9559 libctf: lowest-level memory allocation and debug-dumping wrappers
The memory-allocation wrappers are simple things to allow malloc
interposition: they are only used inconsistently at present, usually
where malloc debugging was required in the past.

These provide a default implementation that is environment-variable
triggered (initialized on the first call to the libctf creation and
file-opening functions, the first functions people will use), and
a ctf_setdebug()/ctf_getdebug() pair that allows the caller to
explicitly turn debugging off and on.  If ctf_setdebug() is called,
the automatic setting from an environment variable is skipped.

libctf/
	* ctf-impl.h: New file.
	* ctf-subr.c: New file.

include/
	* ctf-api.h (ctf_setdebug): New.
	(ctf_getdebug): Likewise.
2019-05-28 17:07:15 +01:00
Nick Alcock
2e94b05630 include: new header ctf-api.h
This non-installed header is the means by which libctf consumers
communicate with libctf.

This header will be extended in subsequent commits.

include/
	* ctf-api.h: New file.
2019-05-28 17:07:11 +01:00
Nick Alcock
fceac76e64 include: new header ctf.h: file format description
The data structures and macros in this header can be used, if desired,
to access or create CTF files directly, without going through libctf,
though this should rarely be necessary in practice.

libctf relies on this header as its description of the CTF file format.

include/
	* ctf.h: New file.
2019-05-28 17:06:55 +01:00
Szabolcs Nagy
2301ed1c9a aarch64: add STO_AARCH64_VARIANT_PCS and DT_AARCH64_VARIANT_PCS
The bottom 2 bits of st_other are used for visibility, the top 6 bits are
de facto reserved for processor specific use.  This patch defines a
bits to mark function symbols that follow a variant procedure call standard
with different register usage convention.

A dynamic tag is also defined that marks modules with R_<CLS>_JUMP_SLOT
relocations referencing symbols marked with STO_AARCH64_VARIANT_PCS.
This can be used by dynamic linkers that support lazy binding to decide
what registers need to be preserved during symbol resolution.

binutils/ChangeLog:

	* readelf.c (get_aarch64_dynamic_type): Handle DT_AARCH64_VARIANT_PCS.
	(get_aarch64_symbol_other): New, handles STO_AARCH64_VARIANT_PCS.
	(get_symbol_other): Call get_aarch64_symbol_other.

include/ChangeLog:

	* elf/aarch64.h (DT_AARCH64_VARIANT_PCS): Define.
	(STO_AARCH64_VARIANT_PCS): Define.
2019-05-24 15:05:57 +01:00
Alan Modra
5663e32184 PowerPC relocations for prefix insns
include/
	* elf/ppc64.h (R_PPC64_PLTSEQ_NOTOC, R_PPC64_PLTCALL_NOTOC),
	(R_PPC64_PCREL_OPT, R_PPC64_D34, R_PPC64_D34_LO, R_PPC64_D34_HI30),
	(R_PPC64_D34_HA30, R_PPC64_PCREL34, R_PPC64_GOT_PCREL34),
	(R_PPC64_PLT_PCREL34, R_PPC64_PLT_PCREL34_NOTOC),
	(R_PPC64_ADDR16_HIGHER34, R_PPC64_ADDR16_HIGHERA34),
	(R_PPC64_ADDR16_HIGHEST34, R_PPC64_ADDR16_HIGHESTA34),
	(R_PPC64_REL16_HIGHER34, R_PPC64_REL16_HIGHERA34),
	(R_PPC64_REL16_HIGHEST34, R_PPC64_REL16_HIGHESTA34),
	(R_PPC64_D28, R_PPC64_PCREL28): Define.
bfd/
	* reloc.c (BFD_RELOC_PPC64_D34, BFD_RELOC_PPC64_D34_LO),
	(BFD_RELOC_PPC64_D34_HI30, BFD_RELOC_PPC64_D34_HA30),
	(BFD_RELOC_PPC64_PCREL34, BFD_RELOC_PPC64_GOT_PCREL34),
	(BFD_RELOC_PPC64_PLT_PCREL34),
	(BFD_RELOC_PPC64_ADDR16_HIGHER34, BFD_RELOC_PPC64_ADDR16_HIGHERA34),
	(BFD_RELOC_PPC64_ADDR16_HIGHEST34, BFD_RELOC_PPC64_ADDR16_HIGHESTA34),
	(BFD_RELOC_PPC64_REL16_HIGHER34, BFD_RELOC_PPC64_REL16_HIGHERA34),
	(BFD_RELOC_PPC64_REL16_HIGHEST34, BFD_RELOC_PPC64_REL16_HIGHESTA34),
	(BFD_RELOC_PPC64_D28, BFD_RELOC_PPC64_PCREL28): New reloc enums.
	* elf64-ppc.c (PNOP): Define.
	(ppc64_elf_howto_raw): Add reloc howtos for new relocations.
	(ppc64_elf_reloc_type_lookup): Translate new bfd reloc numbers.
	(ppc64_elf_ha_reloc): Adjust addend for highera34 and highesta34
	relocs.
	(ppc64_elf_prefix_reloc): New function.
	(struct ppc_link_hash_table): Add notoc_plt.
	(is_branch_reloc): Add R_PPC64_PLTCALL_NOTOC.
	(is_plt_seq_reloc): Add R_PPC64_PLT_PCREL34,
	R_PPC64_PLT_PCREL34_NOTOC, and R_PPC64_PLTSEQ_NOTOC.
	(ppc64_elf_check_relocs): Handle pcrel got and plt relocs.  Set
	has_pltcall for section on seeing R_PPC64_PLTCALL_NOTOC.  Handle
	possible need for dynamic relocs on non-pcrel powerxx relocs.
	(dec_dynrel_count): Handle non-pcrel powerxx relocs.
	(ppc64_elf_inline_plt): Handle R_PPC64_PLTCALL_NOTOC.
	(toc_adjusting_stub_needed): Likewise.
	(ppc64_elf_tls_optimize): Handle R_PPC64_PLTSEQ_NOTOC.
	(ppc64_elf_relocate_section): Handle new powerxx relocs.
	* bfd-in2.h: Regenerate.
	* libbfd.h: Regenerate.
gas/
	* config/tc-ppc.c (ppc_elf_suffix): Support @pcrel, @got@pcrel,
	@plt@pcrel, @higher34, @highera34, @highest34, and @highesta34.
	(fixup_size): Handle new powerxx relocs.
	(md_assemble): Warn for @pcrel on non-prefix insns.
	Accept @l, @h and @ha on prefix insns, and infer reloc without
	any @ suffix.  Translate powerxx relocs to suit DQ and DS field
	instructions.  Include operand tests as well as opcode test to
	translate BFD_RELOC_HI16_S to BFD_RELOC_PPC_16DX_HA.
	(ppc_fix_adjustable): Return false for pcrel GOT and PLT relocs.
	(md_apply_fix): Handle new powerxx relocs.
	* config/tc-ppc.h (TC_FORCE_RELOCATION_SUB_LOCAL): Accept
	BFD_RELOC_PPC64_ADDR16_HIGHER34, BFD_RELOC_PPC64_ADDR16_HIGHERA34,
	BFD_RELOC_PPC64_ADDR16_HIGHEST34, BFD_RELOC_PPC64_ADDR16_HIGHESTA34,
	BFD_RELOC_PPC64_D34, and BFD_RELOC_PPC64_D28.
	* testsuite/gas/ppc/prefix-reloc.d,
	* testsuite/gas/ppc/prefix-reloc.s: New test.
	* testsuite/gas/ppc/ppc.exp: Run it.
2019-05-24 10:27:49 +09:30
Peter Bergner
dd7efa7915 PowerPC add initial -mfuture instruction support
This patch adds initial 64-bit insn assembler/disassembler support.
The only instruction added is "pnop" along with the automatic aligning
of prefix instruction so they do not cross 64-byte boundaries.

include/
	* dis-asm.h (WIDE_OUTPUT): Define.
	* opcode/ppc.h (prefix_opcodes, prefix_num_opcodes): Declare.
	(PPC_OPCODE_POWERXX, PPC_GET_PREFIX, PPC_GET_SUFFIX),
	(PPC_PREFIX_P, PPC_PREFIX_SEG): Define.
opcodes/
	* ppc-dis.c (ppc_opts): Add "future" entry.
	(PREFIX_OPCD_SEGS): Define.
	(prefix_opcd_indices): New array.
	(disassemble_init_powerpc): Initialize prefix_opcd_indices.
	(lookup_prefix): New function.
	(print_insn_powerpc): Handle 64-bit prefix instructions.
	* ppc-opc.c (PREFIX_OP, PREFIX_FORM, SUFFIX_MASK, PREFIX_MASK),
	(PMRR, POWERXX): Define.
	(prefix_opcodes): New instruction table.
	(prefix_num_opcodes): New constant.
binutils/
	* objdump.c (disassemble_bytes): Set WIDE_OUTPUT in flags.
gas/
	* config/tc-ppc.c (ppc_setup_opcodes): Handle prefix_opcodes.
	(struct insn_label_list): New.
	(insn_labels, free_insn_labels): New variables.
	(ppc_record_label, ppc_clear_labels, ppc_start_line_hook): New funcs.
	(ppc_frob_label, ppc_new_dot_label): Move functions earlier in file
	and call ppc_record_label.
	(md_assemble): Handle 64-bit prefix instructions.  Align labels
	that are on the same line as a prefix instruction.
	* config/tc-ppc.h (tc_frob_label, ppc_frob_label): Move to
	later in the file.
	(md_start_line_hook): Define.
	(ppc_start_line_hook): Declare.
	* testsuite/gas/ppc/prefix-align.d,
	* testsuite/gas/ppc/prefix-align.s: New test.
	* testsuite/gas/ppc/ppc.exp: Run new test.
2019-05-24 10:24:45 +09:30
Jose E. Marchesi
8ebe621240 include: add elf/bpf.h
This patch adds a header file with BPF-specific ELF definitions.  In
particular, the architecture relocations.

include/ChangeLog:

2019-05-23  Jose E. Marchesi  <jose.marchesi@oracle.com>

	* elf/bpf.h: New file.
2019-05-23 19:32:58 +02:00
Andre Vieira
a7ad558c37 [PATCH 1/57][Arm][GAS]: Add support for +mve and +mve.fp
bfd/ChangeLog:
2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>

	* elf32-arm.c (elf32_arm_merge_eabi_attributes): Add case for Tag_MVE_arch.

binutils/ChangeLog:
2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>

	* readelf.c (arm_attr_tag_MVE_arch): New array for Tag_MVE_arch values.
	(arm_attr_public_tag arm_attr_public_tags): Add case for Tag_MVE_arch.

elfcpp/ChangeLog:
2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>

	* arm.h (Tag_MVE_arch): Define new enum value.

gas/ChangeLog:
2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>

	* config/tc-arm.c (mve_ext, mve_fp_ext): New features.
	(armv8_1m_main_ext_table): Add new extensions.
	(aeabi_set_public_attributes): Translate new features to new build attributes.
	(arm_convert_symbolic_attribute): Add Tag_MVE_arch.
	* doc/c-arm.texi: Document new extensions and new build attribute.

include/ChangeLog:
2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>

	* elf/arm.h (Tag_MVE_arch): Define new enum value.
	* opcode/arm.h (FPU_MVE, FPU_MVE_FP): New MACROs for new features.
2019-05-16 16:17:21 +01:00
Matthew Malcomson
28ed815ad2 [binutils][aarch64] New SVE_SHLIMM_UNPRED_22 operand.
New operand describes a shift-left immediate encoded in bits
22:20-19:18-16 where UInt(bits) - esize == shift.
This operand is useful for instructions like sshllb.

gas/ChangeLog:

2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>

	* config/tc-aarch64.c (parse_operands): Handle new SVE_SHLIMM_UNPRED_22
	operand.

include/ChangeLog:

2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>

	* opcode/aarch64.h (enum aarch64_opnd): New SVE_SHLIMM_UNPRED_22
	operand.

opcodes/ChangeLog:

2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>

	* aarch64-asm-2.c: Regenerated.
	* aarch64-dis-2.c: Regenerated.
	* aarch64-opc-2.c: Regenerated.
	* aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
	for SVE_SHLIMM_UNPRED_22.
	(aarch64_print_operand): Add printing for SVE_SHLIMM_UNPRED_22.
	* aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_SHLIMM_UNPRED_22
	operand.
2019-05-09 10:29:27 +01:00
Matthew Malcomson
fd1dc4a0c1 [binutils][aarch64] New sve_size_tsz_bhs iclass.
Add sve_size_tsz_bhs iclass needed for sqxtnb and similar instructions.
This iclass encodes one of three variants by the most significant bit
set in a 3-bit value where only one bit may be set.

include/ChangeLog:

2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>

	* opcode/aarch64.h (enum aarch64_insn_class): Add sve_size_tsz_bhs
	iclass.

opcodes/ChangeLog:

2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>

	* aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
	sve_size_tsz_bhs iclass encode.
	* aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
	sve_size_tsz_bhs iclass decode.
2019-05-09 10:29:26 +01:00
Matthew Malcomson
31e36ab341 [binutils][aarch64] New SVE_Zm4_11_INDEX operand.
This includes defining a new single bit field SVE_i2h at position 20.
SVE_Zm4_11_INDEX handles indexed Zn registers where the index is encoded
in bits 20:11 and the register is chosed from range z0-z15 in bits 19-16.

gas/ChangeLog:

2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>

	* config/tc-aarch64.c (parse_operands): Handle new SVE_Zm4_11_INDEX
	operand.

include/ChangeLog:

2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>

	* opcode/aarch64.h (enum aarch64_opnd): New SVE_Zm4_11_INDEX operand.

opcodes/ChangeLog:

2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>

	* aarch64-asm-2.c: Regenerated.
	* aarch64-dis-2.c: Regenerated.
	* aarch64-opc-2.c: Regenerated.
	* aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
	for SVE_Zm4_11_INDEX.
	(aarch64_print_operand): Add printing for SVE_Zm4_11_INDEX.
	(fields): Handle SVE_i2h field.
	* aarch64-opc.h (enum aarch64_field_kind): New SVE_i2h field.
	* aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_Zm4_11_INDEX operand.
2019-05-09 10:29:24 +01:00
Matthew Malcomson
1be5f94f9c [binutils][aarch64] New sve_shift_tsz_bhsd iclass.
This new iclass encodes the variant by which is the most significant bit
used of bits 23-22:20-19, where those bits are usually part of a
given constant operand.

include/ChangeLog:

2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>

	* opcode/aarch64.h (enum aarch64_insn_class): Add sve_shift_tsz_bhsd
	iclass.

opcodes/ChangeLog:

2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>

	* aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
	sve_shift_tsz_bhsd iclass encode.
	* aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
	sve_shift_tsz_bhsd iclass decode.
2019-05-09 10:29:23 +01:00
Matthew Malcomson
3c17238bc9 [binutils][aarch64] New SVE_SHRIMM_UNPRED_22 operand.
Include a new iclass to extract the variant from the most significant 3
bits of this operand.

Instructions such as rshrnb include a constant shift amount as an
operand, where the most significant three bits of this operand determine
what size elements the instruction is operating on.

The new SVE_SHRIMM_UNPRED_22 operand denotes this constant encoded in
bits 22:20-19:18-16 while the new sve_shift_tsz_hsd iclass denotes that
the SVE qualifier is encoded in bits 22:20-19.

gas/ChangeLog:

2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>

	* config/tc-aarch64.c (parse_operands): Handle new SVE_SHRIMM_UNPRED_22
	operand.

include/ChangeLog:

2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>

	* opcode/aarch64.h (enum aarch64_opnd): New SVE_SHRIMM_UNPRED_22
	operand.
	(enum aarch64_insn_class): Add sve_shift_tsz_hsd iclass.

opcodes/ChangeLog:

2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>

	* aarch64-asm-2.c: Regenerated.
	* aarch64-dis-2.c: Regenerated.
	* aarch64-opc-2.c: Regenerated.
	* aarch64-asm.c (aarch64_ins_sve_shrimm):
	(aarch64_encode_variant_using_iclass): Handle
	sve_shift_tsz_hsd iclass encode.
	* aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
	sve_shift_tsz_hsd iclass decode.
	* aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
	for SVE_SHRIMM_UNPRED_22.
	(aarch64_print_operand): Add printing for SVE_SHRIMM_UNPRED_22.
	* aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_SHRIMM_UNPRED_22
	operand.
2019-05-09 10:29:22 +01:00
Matthew Malcomson
cd50a87ae2 [binutils][aarch64] New sve_size_013 iclass.
Add sve_size_013 instruction class

This new iclass handles instructions such as pmullb whose size specifier
can only be encoded as 0, 1, or 3.

include/ChangeLog:

2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>

	* opcode/aarch64.h (enum aarch64_insn_class): Add sve_size_013 iclass.

opcodes/ChangeLog:

2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>

	* aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
	sve_size_013 iclass encode.
	* aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
	sve_size_013 iclass decode.
2019-05-09 10:29:21 +01:00
Matthew Malcomson
3c705960ca [binutils][aarch64] New sve_size_bh iclass.
Add new iclass sve_size_bh to handle instructions that have two variants
encoded with the SVE_sz field.
This iclass behaves the same as the sve_size_sd iclass, but it has a
nicer name for those instructions that choose between variants using the
"B" and "H" size qualifiers.

include/ChangeLog:

2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>

	* opcode/aarch64.h (enum aarch64_insn_class): Add sve_size_bh iclass.

opcodes/ChangeLog:

2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>

	* aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
	sve_size_bh iclass encode.
	* aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
	sve_size_bh iclass decode.
2019-05-09 10:29:20 +01:00
Matthew Malcomson
0a57e14ffa [binutils][aarch64] New sve_size_sd2 iclass.
Define new sve_size_sd2 iclass to distinguish between the two variants
of ldnt1sb and ldnt1sh.

include/ChangeLog:

2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>

	* opcode/aarch64.h (enum aarch64_insn_class): Add sve_size_sd2 iclass.

opcodes/ChangeLog:

2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>

	* aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
	sve_size_sd2 iclass encode.
	* aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
	sve_size_sd2 iclass decode.
	* aarch64-opc.c (fields): Handle SVE_sz2 field.
	* aarch64-opc.h (enum aarch64_field_kind): New SVE_sz2 field.
2019-05-09 10:29:19 +01:00
Matthew Malcomson
c469c86473 [binutils][aarch64] New SVE_ADDR_ZX operand.
Add AARCH64_OPND_SVE_ADDR_ZX operand that allows a vector of addresses
in a Zn register, offset by an Xm register.
This is used with scatter/gather SVE2 instructions.

gas/ChangeLog:

2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>

	* config/tc-aarch64.c (REG_ZR): Macro specifying zero register.
	(parse_address_main): Account for new addressing mode [Zn.S, Xm].
	(parse_operands): Handle new SVE_ADDR_ZX operand.

include/ChangeLog:

2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>

	* opcode/aarch64.h (enum aarch64_opnd): New SVE_ADDR_ZX operand.

opcodes/ChangeLog:

2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>

	* aarch64-asm-2.c: Regenerated.
	* aarch64-dis-2.c: Regenerated.
	* aarch64-opc-2.c: Regenerated.
	* aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
	for SVE_ADDR_ZX.
	(aarch64_print_operand): Add printing for SVE_ADDR_ZX.
	* aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_ADDR_ZX operand.
2019-05-09 10:29:18 +01:00
Matthew Malcomson
116adc2747 [binutils][aarch64] New SVE_Zm3_11_INDEX operand.
Introduce new operand SVE_Zm3_11_INDEX that indicates a register between
z0-z7 stored in bits 18-16 and an index stored in bits 20-19:11.

gas/ChangeLog:

2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>

	* config/tc-aarch64.c (parse_operands): Handle new SVE_Zm3_11_INDEX
	operand.

include/ChangeLog:

2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>

	* opcode/aarch64.h (enum aarch64_opnd): New SVE_Zm3_11_INDEX operand.

opcodes/ChangeLog:

2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>

	* aarch64-asm-2.c: Regenerated.
	* aarch64-dis-2.c: Regenerated.
	* aarch64-opc-2.c: Regenerated.
	* aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
	for SVE_Zm3_11_INDEX.
	(aarch64_print_operand): Add printing for SVE_Zm3_11_INDEX.
	(fields): Handle SVE_i3l and SVE_i3h2 fields.
	* aarch64-opc.h (enum aarch64_field_kind): New SVE_i3l and SVE_i3h2
	fields.
	* aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_Zm3_11_INDEX operand.
2019-05-09 10:29:17 +01:00
Matthew Malcomson
3bd82c86f0 [binutils][aarch64] New iclass sve_size_hsd2.
Add "sve_size_hsd2" iclass decode that uses the new FLD_SVE_size field
value to determine the variant of an instruction.

include/ChangeLog:

2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>

	* opcode/aarch64.h (enum aarch64_insn_class): Add sve_size_hsd2 iclass.

opcodes/ChangeLog:

2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>

	* aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
	sve_size_hsd2 iclass encode.
	* aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
	sve_size_hsd2 iclass decode.
	* aarch64-opc.c (fields): Handle SVE_size field.
	* aarch64-opc.h (enum aarch64_field_kind): New SVE_size field.
2019-05-09 10:29:16 +01:00
Matthew Malcomson
adccc50753 [binutils][aarch64] Introduce SVE_IMM_ROT3 operand.
New operand AARCH64_OPND_SVE_IMM_ROT3 handles a single bit rotate
operand encoded at bit position 10.

gas/ChangeLog:

2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>

	* config/tc-aarch64.c (parse_operands): Handle new SVE_IMM_ROT3 operand.

include/ChangeLog:

2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>

	* opcode/aarch64.h (enum aarch64_opnd): New SVE_IMM_ROT3 operand.

opcodes/ChangeLog:

2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>

	* aarch64-asm-2.c: Regenerated.
	* aarch64-dis-2.c: Regenerated.
	* aarch64-opc-2.c: Regenerated.
	* aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
	for SVE_IMM_ROT3.
	(aarch64_print_operand): Add printing for SVE_IMM_ROT3.
	(fields): Handle SVE_rot3 field.
	* aarch64-opc.h (enum aarch64_field_kind): New SVE_rot3 field.
	* aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_IMM_ROT3 operand.
2019-05-09 10:29:15 +01:00
Matthew Malcomson
7ce2460a77 [binutils][aarch64] SVE2 feature extension flags.
Include all feature flag macros.

The "sve2" extension that enables the core sve2 instructions.
This also enables the sve extension, since sve is a requirement of sve2.

Extra optional sve2 features are the bitperm, sm4, aes, and sha3 extensions.
These are all given extra feature flags, "bitperm", "sve2-sm4",
"sve2-aes", and "sve2-sha3" respectively.
The sm4, aes, and sha3 extensions are explicitly marked as sve2
extensions to distinguish them from the corresponding NEON extensions.

Rather than continue extending the current feature flag numbers, I used
some bits that have been skipped.

gas/ChangeLog:

2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>

	* config/tc-aarch64.c: Add command line architecture feature flags
	"sve2", "sve2-sm4", "sve2-aes", "sve2-sha3", "bitperm".
	* doc/c-aarch64.texi: Document new architecture feature flags.

include/ChangeLog:

2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>

	* opcode/aarch64.h (AARCH64_FEATURE_SVE2
	AARCH64_FEATURE_SVE2_AES, AARCH64_FEATURE_SVE2_BITPERM,
	AARCH64_FEATURE_SVE2_SM4, AARCH64_FEATURE_SVE2_SHA3): New
	feature macros.

opcodes/ChangeLog:

2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>

	* aarch64-tbl.h
	(aarch64_feature_sve2, aarch64_feature_sve2aes,
	aarch64_feature_sve2sha3, aarch64_feature_sve2sm4,
	aarch64_feature_sve2bitperm): New feature sets.
	(SVE2, SVE2_AES, SVE2_SHA3, SVE2_SM4, SVE2_BITPERM): New macros
	for feature set addresses.
	(SVE2_INSN, SVE2_INSNC, SVE2AES_INSN, SVE2SHA3_INSN,
	SVE2SM4_INSN, SVE2SM4_INSNC, SVE2BITPERM_INSN): New macros.
2019-05-09 10:29:12 +01:00
Faraz Shahbazker
41cee0897b Add load-link, store-conditional paired EVA instructions
Add paired load-link and store-conditional instructions to the
EVA ASE for MIPS32R6[1].  These instructions are optional within
the EVA ASE.  Their presence is indicated by the XNP bit in the
Config5 register.

[1] "MIPS Architecture for Programmers Volume II-A: The MIPS32
     Instruction Set Manual", Imagination Technologies Ltd., Document
     Number: MD00086, Revision 6.06, December 15, 2016, Section 3.2
     "Alphabetical List of Instructions", pp. 230-231, pp. 357-360.

gas/
	* config/tc-mips.c (mips_set_ase): Handle ASE_EVA_R6.
	(macro) <M_LLWPE_AB, M_SCWPE_AB>: New cases.
	(mips_after_parse_args): Translate EVA to EVA_R6.
	* testsuite/gas/mips/ase-errors-1.s: Add new instructions.
	* testsuite/gas/mips/eva.s: Likewise.
	* testsuite/gas/mips/ase-errors-1.l: Check errors for
	 new instructions.
	* testsuite/gas/mips/mipsr6@eva.d: Check new test cases.

include/
	* opcode/mips.h (ASE_EVA_R6): New macro.
	(M_LLWPE_AB, M_SCWPE_AB): New enum values.

opcodes/
	* mips-dis.c (mips_calculate_combination_ases): Add ISA
	argument and set ASE_EVA_R6 appropriately.
	(set_default_mips_dis_options): Pass ISA to above.
	(parse_mips_dis_option): Likewise.
	* mips-opc.c (EVAR6): New macro.
	(mips_builtin_opcodes): Add llwpe, scwpe.

Derived from patch authored by Andrew Bennett <andrew.bennett@imgtec.com>
2019-05-06 06:43:32 -07:00
Sudakshina Das
b83b4b1382 [BINUTILS, AArch64] Enable Transactional Memory Extension
This patch enables the new Transactional Memory Extension added recently
as part of Arm's new architecture technologies.

We introduce a new optional extension "tme" to enable this. The following
instructions are part of the extension:
   * tstart <Xt>
   * ttest <Xt>
   * tcommit
   * tcancel #<imm>
The ISA for the above can be found here:
https://developer.arm.com/docs/ddi0602/latest/base-instructions-alphabetic-order

*** gas/ChangeLog ***

2019-05-01  Sudakshina Das  <sudi.das@arm.com>

	* config/tc-aarch64.c (parse_operands): Add case for
	AARCH64_OPND_TME_UIMM16.
	(aarch64_features): Add "tme".
	* doc/c-aarch64.texi: Document the same.
	* testsuite/gas/aarch64/tme-invalid.d: New test.
	* testsuite/gas/aarch64/tme-invalid.l: New test.
	* testsuite/gas/aarch64/tme-invalid.s: New test.
	* testsuite/gas/aarch64/tme.d: New test.
	* testsuite/gas/aarch64/tme.s: New test.

*** include/ChangeLog ***

2019-05-01  Sudakshina Das  <sudi.das@arm.com>

	* opcode/aarch64.h (AARCH64_FEATURE_TME): New.
	(enum aarch64_opnd): Add AARCH64_OPND_TME_UIMM16.

*** opcodes/ChangeLog ***

2019-05-01  Sudakshina Das  <sudi.das@arm.com>

	* aarch64-asm-2.c: Regenerated.
	* aarch64-dis-2.c: Regenerated.
	* aarch64-opc-2.c: Regenerated.
	* aarch64-opc.c (operand_general_constraint_met_p): Add case for
	AARCH64_OPND_TME_UIMM16.
	(aarch64_print_operand): Likewise.
	* aarch64-tbl.h (QL_IMM_NIL): New.
	(TME): New.
	(_TME_INSN): New.
	(struct aarch64_opcode): Add tstart, tcommit, ttest and tcancel.
2019-05-01 17:14:01 +01:00
Andrew Bennett
a45328b93b [MIPS] Add load-link, store-conditional paired instructions
Add several baseline MIPS32R6[1] and MIPS64R6[2] instructions
that were omitted from the initial spec.  These instructions
are optional in implementations but not associated with any
ASE or pseudo-ASE.  Their presence is indicated by the XNP bit
in the Config5 register.

[1] "MIPS Architecture for Programmers Volume II-A: The MIPS32
     Instruction Set Manual", Imagination Technologies Ltd., Document
     Number: MD00086, Revision 6.06, December 15, 2016, Section 3.2
     "Alphabetical List of Instructions", pp. 228-229, pp. 354-357.

[2] "MIPS Architecture for Programmers Volume II-A: The MIPS64
     Instruction Set Manual", Imagination Technologies Ltd., Document
     Number: MD00087, Revision 6.06, December 15, 2016, Section 3.2
     "Alphabetical List of Instructions", pp. 289-290 and pp. 458-460.

gas/
	* config/tc-mips.c (macro) <M_LLWP_AB, M_LLDP_AB, M_SCWP_AB,
	M_SCDP_AB>: New cases and expansions for paired instructions.
	* testsuite/gas/mips/llpscp-32.s: New test source.
	* testsuite/gas/mips/llpscp-64.s: Likewise.
	* testsuite/gas/mips/llpscp-32.d: New test.
	* testsuite/gas/mips/llpscp-64.d: Likewise.
	* testsuite/gas/mips/mips.exp: Run the new tests.
	* testsuite/gas/mips/r6.s: Add new instructions to test source.
	* testsuite/gas/mips/r6-64.s: Likewise.
	* testsuite/gas/mips/r6-64-n32.d: Check new instructions.
	* testsuite/gas/mips/r6-64-n64.d: Likewise.
	* testsuite/gas/mips/r6-n32.d: Likewise.
	* testsuite/gas/mips/r6-n64.d: Likwwise.
	* testsuite/gas/mips/r6.d: Likewise.

include/
	* opcode/mips.h (M_LLWP_AB, M_LLDP_AB): New enum values.
	(M_SCWP_AB, M_SCDP_AB): Likewise.

opcodes/
	* mips-opc.c (mips_builtin_opcodes): Add llwp, lldp, scwp, scdp.
2019-04-26 18:28:05 -07:00