(MIPS_MACH_HAS_MULT_HILO_HAZARD, MIPS_MACH_HAS_DIV_HILO_HAZARD): New.
* mips.igen (check_mt_hilo, check_mult_hilo, check_div_hilo): Provide
separate implementations for mipsIV and mipsV. Use new macros to
determine whether the restrictions apply.
* mips.igen (check_mf_cycles, check_mt_hilo, check_mf_hilo)
(check_mult_hilo): Improve comments.
(check_div_hilo): Likewise. Also, fork off a new version
to handle mips32/mips64 (since there are no hazards to check
in MIPS32/MIPS64).
* mips.igen (do_load_double, do_store_double): New functions.
(LDC1, SDC1): Rename to...
(LDC1b, SDC1b): respectively.
(LDC1a, SDC1a): New instructions for MIPS II and MIPS32 support.
* mdmx.c (SD_): Delete.
(Unpredictable): Re-define, for now, to directly invoke
unpredictable_action().
(mdmx_acc_op): Fix error in .ob immediate handling.
Ed Satterthwaite <ehs@broadcom.com>
* mips3d.igen: New file which contains MIPS-3D ASE instructions.
* Makefile.in (IGEN_INCLUDE): Add mips3d.igen.
* mips.igen: Include mips3d.igen.
(mips3d): New model name for MIPS-3D ASE instructions.
(CVT.W.fmt): Don't use this instruction for word (source) format
instructions.
* cp1.c (fp_binary_r, fp_add_r, fp_mul_r, fpu_inv1, fpu_inv1_32)
(fpu_inv1_64, fp_recip1, fp_recip2, fpu_inv_sqrt1, fpu_inv_sqrt1_32)
(fpu_inv_sqrt1_64, fp_rsqrt1, fp_rsqrt2): New functions.
(NR_FRAC_GUARD, IMPLICIT_1): New macros.
* sim-main.h (fmt_pw, CompareAbs, AddR, MultiplyR, Recip1, Recip2)
(RSquareRoot1, RSquareRoot2): New macros.
(fp_add_r, fp_mul_r, fp_recip1, fp_recip2, fp_rsqrt1)
(fp_rsqrt2): New functions.
* configure.in: Add MIPS-3D support to mipsisa64 simulator.
* configure: Regenerate.
* cp1.c (FP_PS_upper, FP_PS_lower, FP_PS_cat, FPQNaN_PS): New macros.
(value_fpr, store_fpr, fp_cmp, fp_unary, fp_binary, fp_mac)
(fp_inv_sqrt, fpu_format_name): Add paired-single support.
(convert): Note that this function is not used for paired-single
format conversions.
(ps_lower, ps_upper, pack_ps, convert_ps): New functions.
* mips.igen (FMT, MOVtf.fmt): Add paired-single support.
(check_fmt_p): Enable paired-single support.
(ALNV.PS, CVT.PS.S, CVT.S.PL, CVT.S.PU, PLL.PS, PLU.PS, PUL.PS)
(PUU.PS): New instructions.
(CVT.S.fmt): Don't use this instruction for paired-single format
destinations.
* sim-main.h (FP_formats): New value 'fmt_ps.'
(ps_lower, ps_upper, pack_ps, convert_ps): New prototypes.
(PSLower, PSUpper, PackPS, ConvertPS): New macros.
* mips.igen (MOVN, MOVZ): Trace result.
(TNEI): Print "tnei" as the opcode name in traces.
(CEIL.W): Add disassembly string for traces.
(RSQRT.fmt): Make location of disassembly string consistent
with other instructions.
Ed Satterthwaite <ehs@broadcom.com>
* cp1.c: Fix more comment spelling and formatting.
(value_fcr, store_fcr): Use fenr_FS rather than hard-coding value.
(denorm_mode): New function.
(fpu_unary, fpu_binary): Round results after operation, collect
status from rounding operations, and update the FCSR.
(convert): Collect status from integer conversions and rounding
operations, and update the FCSR. Adjust NaN values that result
from conversions. Convert to use sim_io_eprintf rather than
fprintf, and remove some debugging code.
* cp1.h (fenr_FS): New define.
* sim-main.h (FGRIDX): Remove, replace all uses with...
(FGR_BASE): New macro.
(FP0_REGNUM, FCRCS_REGNUM, FCRIR_REGNUM): New macros.
(_sim_cpu): Move 'fgr' member to be right before 'fpr_state' member.
(NR_FGR, FGR): Likewise.
* interp.c: Replace all uses of FGRIDX with FGR_BASE.
* mips.igen: Likewise.
* sim-main.h (Nan, Infinity, Less, Equal, AbsoluteValue, Negate)
(Add, Sub, Multiply, Divide, Recip, SquareRoot): Move lower in
file, remove PARAMS from prototypes.
(value_fpr, store_fpr, convert): Likewise. Use SIM_STATE to provide
simulator state arguments.
(ValueFPR, StoreFPR, Convert): Move lower in file. Use SIM_ARGS to
pass simulator state arguments.
* cp1.c (SD): Redefine as CPU_STATE(cpu).
(store_fpr, convert): Remove 'sd' argument.
(value_fpr): Likewise. Convert to use 'SD' instead.
Ed Satterthwaite <ehs@broadcom.com>
* configure.in (mipsisa64sb1*-*-*): New target for supporting
Broadcom SiByte SB-1 processor configurations.
* configure: Regenerate.
* sb1.igen: New file.
* mips.igen: Include sb1.igen.
(sb1): New model.
* Makefile.in (IGEN_INCLUDE): Add sb1.igen.
* mdmx.igen: Add "sb1" model to all appropriate functions and
instructions.
* mdmx.c (AbsDiffOB, AvgOB, AccAbsDiffOB): New functions.
(ob_func, ob_acc): Reference the above.
(qh_acc): Adjust to keep the same size as ob_acc.
* sim-main.h (status_SBX, MX_VECT_ABSD, MX_VECT_AVG, MX_AbsDiff)
(MX_Avg, MX_VECT_ABSDA, MX_AbsDiffC): New macros.
2002-05-01 Chris Demetriou <cgd@broadcom.com>
* callback.c: Use 'deprecated' rather than 'depreciated.'
[ igen/ChangeLog ]
2002-05-01 Chris Demetriou <cgd@broadcom.com>
* igen.c: Use 'deprecated' rather than 'depreciated.'
[ mips/ChangeLog ]
2002-05-01 Chris Demetriou <cgd@broadcom.com>
* interp.c: Use 'deprecated' rather than 'depreciated.'
* sim-main.h: Likewise.
* cp1.c (store_fpr): Remove #ifdef'd out call to UndefinedResult
which wouldn't compile anyway.
* sim-main.h (unpredictable_action): New function prototype.
(Unpredictable): Define to call igen function unpredictable().
(NotWordValue): New macro to call igen function not_word_value().
(UndefinedResult): Remove.
* interp.c (undefined_result): Remove.
(unpredictable_action): New function.
* mips.igen (not_word_value, unpredictable): New functions.
(ADD, ADDI, do_addiu, do_addu, BGEZAL, BGEZALL, BLTZAL, BLTZALL)
(CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, do_mult, do_multu)
(do_sra, do_srav, do_srl, do_srlv, SUB, do_subu): Invoke
NotWordValue() to check for unpredictable inputs, then
Unpredictable() to handle them.
* cp1.c (fpu_format_name): New function to replace...
(DOFMT): This. Delete, and update all callers.
(fpu_rounding_mode_name): New function to replace...
(RMMODE): This. Delete, and update all callers.
* interp.c: Move FPU support routines from here to...
* cp1.c: Here. New file.
* Makefile.in (SIM_OBJS): Add cp1.o to object list.
(cp1.o): New target.
* configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets.
* mips.igen (mips32, mips64): New models, add to all instructions
and functions as appropriate.
(loadstore_ea, check_u64): New variant for model mips64.
(check_fmt_p): New variant for models mipsV and mips64, remove
mipsV model marking fro other variant.
(SLL) Rename to...
(SLLa) this.
(CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions
for mips32 and mips64.
(DCLO, DCLZ): New instructions for mips64.
* mips.igen (BREAK, LUI, ORI, SYSCALL, XORI): Print
immediate or code as a hex value with the "%#lx" format.
(ANDI): Likewise, and fix printed instruction name.
* sim-main.h (status_UX, status_SX, status_KX, status_TS)
(status_PX, status_MX, status_CU0, status_CU1, status_CU2)
(status_CU3): New definitions.
* sim-main.h (ExceptionCause): Add new values for MIPS32
and MIPS64: MDMX, MCheck, CacheErr. Update comments
for DebugBreakPoint and NMIReset to note their status in
MIPS32 and MIPS64.
(SignalExceptionMDMX, SignalExceptionWatch, SignalExceptionMCheck)
(SignalExceptionCacheErr): New exception macros.
* mips.igen (check_fpu): Enable check for coprocessor 1 usability.
* sim-main.h (COP_Usable): Define, but for now coprocessor 1
is always enabled.
(SignalExceptionCoProcessorUnusable): Take as argument the
unusable coprocessor number.
* mips.igen (check_fmt, check_fmt_p): New functions to check
whether specific floating point formats are usable.
(ABS.fmt, ADD.fmt, CEIL.L.fmt, CEIL.W, DIV.fmt, FLOOR.L.fmt)
(FLOOR.W.fmt, MOV.fmt, MUL.fmt, NEG.fmt, RECIP.fmt, ROUND.L.fmt)
(ROUND.W.fmt, RSQRT.fmt, SQRT.fmt, SUB.fmt, TRUNC.L.fmt, TRUNC.W):
Use the new functions.
(do_c_cond_fmt): Remove format checks...
(C.cond.fmta, C.cond.fmtb): And move them into all callers.
* mips.igen (loadstore_ea): New function to do effective
address calculations.
(do_load, do_load_left, do_load_right, LL, LDD, PREF, do_store,
do_store_left, do_store_right, SC, SCD, PREFX, SWC1, SWXC1,
CACHE): Use loadstore_ea to do effective address computations.
* mips.igen (PREFX): Tweak instruction opcode fields (i.e.,
add a comma) so that it more closely match the MIPS ISA
documentation opcode partitioning.
(PREF): Put useful names on opcode fields, and include
instruction-printing string.
* mips.igen (check_u64): New function which in the future will
check whether 64-bit instructions are usable and signal an
exception if not. Currently a no-op.
(DADD, DADDI, DADDIU, DADDU, DDIV, DDIVU, DMULT, DMULTU, DSLL,
DSLL32, DSLLV, DSRA, DSRA32, DSRAV, DSRL, DSRL32, DSRLV, DSUB,
DSUBU, LD, LDL, LDR, LLD, LWU, SCD, SD, SDL, SDR, DMxC1, LDXC1,
LWXC1, SDXC1, SWXC1, DMFC0, DMTC0): Use check_u64.
* mips.igen (check_fpu): New function which in the future will
check whether FPU instructions are usable and signal an exception
if not. Currently a no-op.
(ABS.fmt, ADD.fmt, BC1a, BC1b, C.cond.fmta, C.cond.fmtb,
CEIL.L.fmt, CEIL.W, CxC1, CVT.D.fmt, CVT.L.fmt, CVT.S.fmt,
CVT.W.fmt, DIV.fmt, DMxC1, DMxC1, FLOOR.L.fmt, FLOOR.W.fmt, LDC1,
LDXC1, LWC1, LWXC1, MADD.D, MADD.S, MxC1, MOV.fmt, MOVtf,
MOVtf.fmt, MOVN.fmt, MOVZ.fmt, MSUB.D, MSUB.S, MUL.fmt, NEG.fmt,
NMADD.D, NMADD.S, NMSUB.D, NMSUB.S, RECIP.fmt, ROUND.L.fmt,
ROUND.W.fmt, RSQRT.fmt, SDC1, SDXC1, SQRT.fmt, SUB.fmt, SWC1,
SWXC1, TRUNC.L.fmt, TRUNC.W): Use check_fpu.
* mips.igen (do_load_left, do_load_right): Move to be immediately
following do_load.
(do_store_left, do_store_right): Move to be immediately following
do_store.
* mips.igen: Add some additional comments about supported
models, and about which instructions go where.
(BC1b, MFC0, MTC0, RFE): Sort supported models in the same
order as is used in the rest of the file.
* mips.igen (ADD, ADDI, DADDI, DSUB, SUB): Add comment
indicating that ALU32_END or ALU64_END are there to check
for overflow.
(DADD): Likewise, but also remove previous comment about
overflow checking.
* mips.igen (ADDI): Print immediate value.
(BREAK): Print code.
(DADDIU, DSRAV, DSRLV): Print correct instruction name.
(SLL): Print "nop" specially, and don't run the code
that does the shift for the "nop" case.
PENDING_FILL. Use PENDING_SCHED directly to handle the pending
set of the FCSR.
* sim-main.h (COCIDX): Remove definition; this isn't supported by
PENDING_FILL, and you can get the intended effect gracefully by
calling PENDING_SCHED directly.
2000-10-19 Frank Ch. Eigler <fche@redhat.com>
On advice from Chris G. Demetriou <cgd@sibyte.com>:
* sim-main.h (GPR_CLEAR): Remove unused alternative macro.
* merge from internal repo -> sourceware
2000-03-02 Frank Ch. Eigler <fche@redhat.com>
* configure: Regenerated.
Tue Feb 8 18:35:01 2000 Donald Lindsay <dlindsay@hound.cygnus.com>
* interp.c, mips.igen: all 5 DEADC0DE situations now have sim_io_eprintf
calls, conditional on the simulator being in verbose mode.
1999-02-05 Frank Ch. Eigler <fche@cygnus.com>
* dv-tx3904sio.c (tx3904sio_tickle): After a polled I/O from the
CPU, start periodic background I/O polls.
(tx3904sio_poll): New function: periodic I/O poller.
[ChangeLog]
1998-12-30 Frank Ch. Eigler <fche@cygnus.com>
* mips.igen (BREAK): Call signal_exception instead of sim_engine_halt.
start-sanitize-sky
* interp.c (signal_exception): Call SIM_CPU_EXCEPTION_TRIGGER hook.
Call sim_engine_halt on BreakPoint.
end-sanitize-sky
[ChangeLog.sky]
1998-12-30 Frank Ch. Eigler <fche@cygnus.com>
* sky-gdb.c (sky_sim_engine_halt): Do not set CIA here.
1998-12-29 Frank Ch. Eigler <fche@cygnus.com>
* interp.c (sim_open): Allocate jm3904 memory in smaller chunks.
(load_word): Call SIM_CORE_SIGNAL hook on error.
(signal_exception): Call SIM_CPU_EXCEPTION_TRIGGER hook before
starting. For exception dispatching, pass PC instead of NULL_CIA.
(decode_coproc): Use COP0_BADVADDR to store faulting address.
* sim-main.h (COP0_BADVADDR): Define.
(SIM_CORE_SIGNAL): Define hook to call mips_core_signal.
(SIM_CPU_EXCEPTION*): Define hooks to call mips_cpu_exception*().
(_sim_cpu): Add exc_* fields to store register value snapshots.
* mips.igen (*): Replace memory-related SignalException* calls
with references to SIM_CORE_SIGNAL hook.
* dv-tx3904irc.c (tx3904irc_port_event): printf format warning
fix.
* sim-main.c (*): Minor warning cleanups.
Set mips_fpu, and mips_fpu_bitsize.
Set sim_gen, and sim_igen_machine.
* configure: Rebuild.
* mips.igen (BC1): Renamed to BC1a and BC1b to avoid conflicts.
* sim-main.h (SizeFGR): Handle TARGET_ENABLE_FR.
1998-12-10 Frank Ch. Eigler <fche@cygnus.com>
* dv-tx3904sio.c (tx3904sio_io_read_buffer): Endianness fixes.
(tx3904sio_tickle): fflush after a stdout character output.
v850/simops.c, d10v/simops.c, v850/Makefile.in, d10v/Makefile.in:
Include targ-vals.h instead of syscall.h. Replace SYS_* with
TARGET_SYS_*. Add dependency.
z8k/support.c: Include <errno.h>
v850/simops.c: Replace long with portable signed32.
mips/interp.c: Make sim_monitor global - needed by sky.
Fri Sep 4 10:37:57 1998 Frank Ch. Eigler <fche@cygnus.com>
* r5900.igen (mtsab): Correct typo in input register.
* sim-main.h (TMP_*): New macros for accessing local 128-bit
temporary for multimedia instructions.
* r5900.igen (*): Convert most instructions to use new TMP
macros to store output result during computation.
Chris Demetriou
Richard Sandiford
Ian Lance Taylor
Andrew Cagney
Michael Snyder
Alexandre Oliva
Fred Fish
Jim Blandy
Ben Elliston
Frank Ch. Eigler
Nick Clifton
Jason Molenda
Stan Shebs
Gavin Romig-Koch
Jeff Law
Doug Evans
Ron Unrau