Commit Graph

7625 Commits

Author SHA1 Message Date
Alan Modra 87c69f9732 Rename PowerPC64 pcrel GOT TLS relocations
These relocations should have had REL in their names, to reflect the
fact that they are pc-relative.  Fix that now by adding _PCREL.
I've added some back-compatibility code to support anyone using
.reloc with the old relocations.

include/
	* elf/ppc64.h (elf_ppc64_reloc_type): Rename
	R_PPC64_GOT_TLSGD34 to R_PPC64_GOT_TLSGD_PCREL34,
	R_PPC64_GOT_TLSLD34 to R_PPC64_GOT_TLSLD_PCREL34,
	R_PPC64_GOT_TPREL34 to R_PPC64_GOT_TPREL_PCREL34, and
	R_PPC64_GOT_DTPREL34 to R_PPC64_GOT_DTPREL_PCREL34.
bfd/
	* reloc.c: Rename
	BFD_RELOC_PPC64_GOT_TLSGD34 to BFD_RELOC_PPC64_GOT_TLSGD_PCREL34,
	BFD_RELOC_PPC64_GOT_TLSLD34 to BFD_RELOC_PPC64_GOT_TLSLD_PCREL34,
	BFD_RELOC_PPC64_GOT_TPREL34 to BFD_RELOC_PPC64_GOT_TPREL_PCREL34,
	BFD_RELOC_PPC64_GOT_DTPREL34 to BFD_RELOC_PPC64_GOT_DTPREL_PCREL34.
	* elf64-ppc.c: Update throughout for reloc renaming.
	(ppc64_elf_reloc_name_lookup): Handle old reloc names.
	* libbfd.h: Regenerate.
	* bfd-in2.h: Regenerate.
gas/
	* config/tc-ppc.c: Update throughout for reloc renaming.
elfcpp/
	* powerpc.h: Rename
	R_PPC64_GOT_TLSGD34 to R_PPC64_GOT_TLSGD_PCREL34,
	R_PPC64_GOT_TLSLD34 to R_PPC64_GOT_TLSLD_PCREL34,
	R_PPC64_GOT_TPREL34 to R_PPC64_GOT_TPREL_PCREL34, and
	R_PPC64_GOT_DTPREL34 to R_PPC64_GOT_DTPREL_PCREL34.
gold/
	* powerpc.cc: Update throughout for reloc renaming.
2020-06-06 14:44:32 +09:30
Jose E. Marchesi f1919c56e1 gas: avoid GCC 10 warning stringop-overflow in tc-bpf.c
The GAS struct frag ends with a field `fr_literal' whose purpose is to
mark the begining of the frag's data:

struct frag {
  ...
  /* Data begins here.  */
  char fr_literal[1];
};

The code in gas/config/tc-bpf.c recently committed:

where = fixP->fx_frag->fr_literal + fixP->fx_where;
where[1] = target_big_endian ? 0x01 : 0x10;

triggers the stringop-overflow warning in GCC 10+, since the compiler
assumes the size of the modified buffer is 1 byte.  This patch
slightly modifies the code to make tc-bpf.c buildable with GCC 10+.

2020-06-05  Jose E. Marchesi  <jose.marchesi@oracle.com>

	* config/tc-bpf.c (md_apply_fix): Avoid GCC 10 warning
	stringop-overflow.
2020-06-05 16:23:30 +02:00
Nelson Chu 3fc6c3dc2a RISC-V: Don't generate the ELF privilege attributes when no CSR are used.
gas/
	* config/tc-riscv.c (explicit_csr): New static boolean.
	Used to indicate CSR are explictly used.
	(riscv_ip): Set explicit_csr to TRUE if any CSR is used.
	(riscv_write_out_attrs): If we already have set elf priv
	attributes, then generate them.  Otherwise, don't generate
	them when no CSR are used.

	* testsuite/gas/riscv/attribute-01.d: Remove the priv attributes.
	* testsuite/gas/riscv/attribute-02.d: Likewise.
	* testsuite/gas/riscv/attribute-03.d: Likewise.
	* testsuite/gas/riscv/attribute-04.d: Likewise.
	* testsuite/gas/riscv/attribute-05.d: Likewise.
	* testsuite/gas/riscv/attribute-06.d: Likewise.
	* testsuite/gas/riscv/attribute-07.d: Likewise.
	* testsuite/gas/riscv/attribute-08.d: Likewise.
	* testsuite/gas/riscv/attribute-09.d: Likewise.
	* testsuite/gas/riscv/attribute-10.d: Likewise.
	* testsuite/gas/riscv/attribute-unknown.d: Likewise.
	* testsuite/gas/riscv/attribute-11.s: New testcase.
	* testsuite/gas/riscv/attribute-11.d: New testcase.  The CSR is
	used, so we should output the ELF priv attributes.
	* testsuite/gas/riscv/attribute-12.d: New testcase.  The CSR is
	used, so output the priv attributes according to the -mpriv-spec.
	* testsuite/gas/riscv/attribute-13.d: New testcase.  The CSR isn't
	used, so ignore the -mpriv-spec setting.

	ld/
	* testsuite/ld-riscv-elf/attr-merge-arch-01.d: Likewise.
	* testsuite/ld-riscv-elf/attr-merge-arch-02.d: Likewise.
	* testsuite/ld-riscv-elf/attr-merge-arch-03.d: Likewise.
	* testsuite/ld-riscv-elf/attr-merge-stack-align.d: Likewise.
	* testsuite/ld-riscv-elf/attr-merge-strict-align-01.d: Likewise.
	* testsuite/ld-riscv-elf/attr-merge-strict-align-02.d: Likewise.
	* testsuite/ld-riscv-elf/attr-merge-strict-align-03.d: Likewise.
	* testsuite/ld-riscv-elf/attr-merge-strict-align-04.d: Likewise.
	* testsuite/ld-riscv-elf/attr-merge-strict-align-05.d: Likewise.
	* testsuite/ld-riscv-elf/call-relax.d: Add -mno-arch-attr.
2020-06-05 12:14:44 +08:00
H.J. Lu d413a6233a gas: Fix ip2k-elf and xstormy16-elf build
Fix ip2k-elf and xstormy16-elf build due to

commit e9bffec9af
Author: Jose E. Marchesi <jose.marchesi@oracle.com>
Date:   Thu Jun 4 16:15:53 2020 +0200

    opcodes: discriminate endianness and insn-endianness in CGEN ports

	* config/tc-ip2k. (ip2k_apply_fix): Pass endianness to
	cgen_get_insn_value.
	* config/tc-xstormy16.c (xstormy16_md_apply_fix): Pass
	endianness to cgen_get_insn_value and cgen_put_insn_value.
2020-06-04 11:15:06 -07:00
Jose E. Marchesi 7d8b91fda9 gas: simplify code in tc-bpf.c:md_apply_fix
2020-06-04  Jose E. Marchesi  <jose.marchesi@oracle.com>

	* config/tc-bpf.c (md_apply_fix): Simplify and avoid using
	cgen_put_insn_value.
2020-06-04 16:34:16 +02:00
Jose E. Marchesi d8740be159 cpu,gas,opcodes: remove no longer needed workaround from the BPF port
cpu/ChangeLog:

2020-06-02  Jose E. Marchesi  <jose.marchesi@oracle.com>

	* bpf.cpu (define-bpf-isa): Set base-insn-bitsize to 64.
	* bpf.opc (bpf_print_insn): Do not set endian_code here.

gas/ChangeLog:

2020-06-04  Jose E. Marchesi  <jose.marchesi@oracle.com>

	* config/tc-bpf.c (md_begin): Pass CGEN_CPU_OPEN_INSN_ENDIAN to
	bpf_cgen_cpu_open.
	(md_assemble): Remove no longer needed hack.

opcodes/ChangeLog:

2020-06-04  Jose E. Marchesi  <jose.marchesi@oracle.com>

	* disassemble.c (disassemble_init_for_target): Set endian_code for
	bpf targets.
	* bpf-desc.c: Regenerate.
	* bpf-opc.c: Likewise.
	* bpf-dis.c: Likewise.
2020-06-04 16:17:42 +02:00
Jose E. Marchesi e9bffec9af opcodes: discriminate endianness and insn-endianness in CGEN ports
The CGEN support code in opcodes accesses instruction contents using a
couple of functions defined in cgen-opc.c: cgen_get_insn_value and
cgen_put_insn_value.  These functions use the "instruction endianness"
in the CPU description to order the read/written bytes.

The process of writing an instruction to the object file is:

  a) cgen_put_insn_value        ;; Writes out the opcodes.
  b) ARCH_cgen_insert_operand
       insert_normal
         insert_1
           cgen_put_insn_value  ;; Writes out the bytes of the
                                ;; operand.

Likewise, the process of reading an instruction from the object file
is:

  a) cgen_get_insn_value        ;; Reads the opcodes.
  b) ARCH_cgen_extract_operand
       extract_normal
         extract_1
           cgen_get_insn_value  ;; Reads in the bytes of the
                                ;; operand.

As can be seen above, cgen_{get,put}_insn_value are used to both
process the instruction opcodes (the constant fields conforming the
base instruction) and also the values of the instruction operands,
such as immediates.

This is problematic for architectures in which the endianness of
instructions is different to the endianness of data.  An example is
BPF, where instructions are always encoded big-endian but the data may
be either big or little.

This patch changes the cgen_{get,put}_insn_value functions in order to
get an extra argument with the endianness to use, and adapts the
existin callers to these functions in order to provide cd->endian or
cd->insn_endian, whatever appropriate.  Callers like extract_1 and
insert_1 pass cd->endian (since they are reading/writing operand
values) while callers reading/writing the base instruction pass
cd->insn_endian instead.

A few little adjustments have been needed in some existing CGEN based
ports:
* The BPF assembler uses cgen_put_insn_value.  It has been adapted to
  pass the new endian argument.
* The mep port has code in mep.opc that uses cgen_{get,put}_insn_value.
  It has been adapted to pass the new endianargument.  Ditto for a
  call in the assembler.

Tested with --enable-targets=all.
Regested in all supported targets.
No regressions.

include/ChangeLog:

2020-06-04  Jose E. Marchesi  <jose.marchesi@oracle.com>

	* opcode/cgen.h: Get an `endian' argument in both
	cgen_get_insn_value and cgen_put_insn_value.

opcodes/ChangeLog:

2020-06-04  Jose E. Marchesi  <jose.marchesi@oracle.com>

	* cgen-opc.c (cgen_get_insn_value): Get an `endian' argument.
	(cgen_put_insn_value): Likewise.
	(cgen_lookup_insn): Pass endianness to cgen_{get,put}_insn_value.
	* cgen-dis.in (print_insn): Likewise.
	* cgen-ibld.in (insert_1): Likewise.
	(insert_1): Likewise.
	(insert_insn_normal): Likewise.
	(extract_1): Likewise.
	* bpf-dis.c: Regenerate.
	* bpf-ibld.c: Likewise.
	* bpf-ibld.c: Likewise.
	* cgen-dis.in: Likewise.
	* cgen-ibld.in: Likewise.
	* cgen-opc.c: Likewise.
	* epiphany-dis.c: Likewise.
	* epiphany-ibld.c: Likewise.
	* fr30-dis.c: Likewise.
	* fr30-ibld.c: Likewise.
	* frv-dis.c: Likewise.
	* frv-ibld.c: Likewise.
	* ip2k-dis.c: Likewise.
	* ip2k-ibld.c: Likewise.
	* iq2000-dis.c: Likewise.
	* iq2000-ibld.c: Likewise.
	* lm32-dis.c: Likewise.
	* lm32-ibld.c: Likewise.
	* m32c-dis.c: Likewise.
	* m32c-ibld.c: Likewise.
	* m32r-dis.c: Likewise.
	* m32r-ibld.c: Likewise.
	* mep-dis.c: Likewise.
	* mep-ibld.c: Likewise.
	* mt-dis.c: Likewise.
	* mt-ibld.c: Likewise.
	* or1k-dis.c: Likewise.
	* or1k-ibld.c: Likewise.
	* xc16x-dis.c: Likewise.
	* xc16x-ibld.c: Likewise.
	* xstormy16-dis.c: Likewise.
	* xstormy16-ibld.c: Likewise.

gas/ChangeLog:

2020-06-04  Jose E. Marchesi  <jose.marchesi@oracle.com>

	* cgen.c (gas_cgen_finish_insn): Pass the endianness to
	cgen_put_insn_value.
	(gas_cgen_md_apply_fix): Likewise.
	(gas_cgen_md_apply_fix): Likewise.
	* config/tc-bpf.c (md_apply_fix): Pass data endianness to
	cgen_put_insn_value.
	* config/tc-mep.c (mep_check_ivc2_scheduling): Pass endianness to
	cgen_put_insn_value.

cpu/ChangeLog:

2020-06-02  Jose E. Marchesi  <jose.marchesi@oracle.com>

	* mep.opc (print_slot_insn): Pass the insn endianness to
	cgen_get_insn_value.
2020-06-04 16:17:42 +02:00
Alan Modra 1cf67587a0 tcl global directive outside proc body does nothing (gas)
* testsuite/config/default.exp: Remove global directive outside
	proc body.
	* testsuite/gas/mep/complex-relocs.exp: Likewise.
	* testsuite/gas/microblaze/relax_size.exp: Likewise.
	* testsuite/gas/microblaze/reloc_sym.exp: Likewise.
	* testsuite/gas/mt/relocs.exp: Likewise.
	* testsuite/gas/rx/rx.exp: Likewise.
2020-06-04 16:11:38 +09:30
Stephen Casner 338d56a848 * gas/doc/c-riscv.texi (RISC-V-Options): Fix non-ASCII apostrophe. 2020-06-03 13:42:54 -07:00
Jim Wilson bb7322c671 RISC-V: Fix minor bugs in .insn docs.
This fixes some minor bugs in the docs for the .insn directive pointed out
by Frédéric Pétrot, and I added a few more cleanups since I was changing
the docs.

	gas/
	PR 26051
	* doc/c-riscv.texi (RISC-V-Formats): Add missing I format using
	simm12(rs1).  Correct S format to use simm12(rs1).  Drop SB and B
	formats using simm12(rs1).  Correct SB and B to use rs1 and rs2.
	Move B before SB.  Move J before UJ.
2020-06-02 18:37:09 -07:00
Alex Coplan c39c821c1d gas: Fix checking for backwards .org with negative offset
This patch fixes internal errors in (at least) arm and aarch64 GAS
when assembling code that attempts a negative .org.  The bug appears
to be a regression introduced in binutils-2.29 by commit 9875b36538.

	* write.c (relax_segment): Fix handling of negative offset when
	relaxing an rs_org frag.
	* testsuite/gas/aarch64/org-neg.d: New test.
	* testsuite/gas/aarch64/org-neg.l: Error output for test.
	* testsuite/gas/aarch64/org-neg.s: Input for test.
	* testsuite/gas/arm/org-neg.d: New test.
	* testsuite/gas/arm/org-neg.l: Error output for test.
	* testsuite/gas/arm/org-neg.s: Input for test.
2020-06-02 00:10:40 +09:30
Stephen Casner 66e3eb08a5 Fix all unexpected failures in gas testsuite for pdp11-aout.
These failures were caused by the PDP11's mix of little-endian octets
in shorts but shorts in big endian order for long or quad so regexps
did not match.  Also tests used addresses as values in .long which
required BRD_RELOC_32 that was not implemented.

* gas/config/tc-pdp11.c (md_number_to_chars): Implement .quad
* gas/testsuite/gas/all/gas.exp: Select alternate test scripts for
pdp11, skip octa test completely.
* gas/testsuite/gas/all/eqv-dot-pdp11.s: Identical to eqv-dot.s
* gas/testsuite/gas/all/eqv-dot-pdp11.d: Match different octet order.
* gas/testsuite/gas/all/cond-pdp11.l: Match different octet order.

* bfd/pdp11.c: Implement BRD_RELOC_32 to relocate the low 16 bits of
addreses in .long (used in testsuites) and .stab values.
2020-05-28 10:11:59 -07:00
Nick Clifton 9e85f042a6 [PATCH] gas: Fix comment on definition of frag_grow()
* frags.c (frag_grow): Fix comment.
2020-05-28 14:30:34 +01:00
Stephen Casner 1c912705af Fix PR gas/26001 (pdp11-*-*)
PR gas/26001
* gas/config/tc-pdp11.c (parse_reg): Distinguish register names from
symbols that begin with a register name.
* gas/testsuite/gas/pdp11/pdp11.exp: Add test of such symbols.
* gas/testsuite/gas/pdp11/pr26001.s: Likewise.
* gas/testsuite/gas/pdp11/pr26001.d: Likewise.
2020-05-27 18:40:38 -07:00
Simon Cook 5c5055683b RISC-V: Fix missing initialization of riscv_csr_extra structs
The next pointer of struct riscv_csr_extra was not always initilized
to NULL or a valid pointer, causing the assembler to attempt to read
through an uninitialized pointer on startup.

gas/ChangeLog:

        * config/tc-riscv.c (riscv_init_csr_hash): NULL initilize next
        pointer when creating struct riscv_csr_extra.
2020-05-27 16:38:37 -07:00
H.J. Lu 3c73074034 gas: Adjust x86 tests for PECOFF
* testsuite/gas/i386/align-branch-9.d: Updated for PECOFF.
	* testsuite/gas/i386/inval-avx512f.s: Add .p2align for PECOFF.
	* testsuite/gas/i386/inval-avx512f.l: Updated.
2020-05-26 14:18:08 -07:00
Stefan Schulze Frielinghaus 57b179405a ChangeLog entries for f687f5f563 2020-05-26 18:35:51 +02:00
H.J. Lu e3fed0f2fe tc-xgate.c: Replace R_XGATE_PCREL_X with BFD_RELOC_XGATE_PCREL_X
Replace R_XGATE_PCREL_X with BFD_RELOC_XGATE_PCREL_X to silence GCC 10
warning:

gas/config/tc-xgate.c:1339:5: error: implicit conversion from ‘enum elf_xgate_reloc_type’ to ‘bfd_reloc_code_real_type’ {aka ‘enum bfd_reloc_code_real’} [-Werror=enum-conversion]
 1339 |     R_XGATE_PCREL_9);
      |     ^~~~~~~~~~~~~~~

	PR gas/26044
	* config/tc-xgate.c (md_apply_fix): Check BFD_RELOC_XGATE_PCREL_X
	instead of R_XGATE_PCREL_X.
	(xgate_parse_operand): Replace R_XGATE_PCREL_X with
	BFD_RELOC_XGATE_PCREL_X.
2020-05-26 09:34:18 -07:00
H.J. Lu 8bbc5da5ee gas: Silence GCC 10 warning on tc-visium.c
PR gas/26044
	* config/tc-visium.c (md_convert_frag): Replace fragP->fr_literal
	with &fragP->fr_literal[0].
2020-05-26 07:54:05 -07:00
H.J. Lu c4612b92e3 gas: Silence GCC 10 warning tc-vax.c
PR gas/26044
	* config/tc-vax.c (md_estimate_size_before_relax): Replace
	fragP->fr_literal with &fragP->fr_literal[0].
	(md_convert_frag): Likewise.
2020-05-26 07:41:07 -07:00
H.J. Lu 70b1b570bf gas: Silence GCC 10 warning on tc-v850.c
PR gas/26044
	* config/tc-v850.c (md_convert_frag): Replace fragP->fr_literal
	with &fragP->fr_literal[0].
2020-05-26 06:56:18 -07:00
H.J. Lu e67e940f5d gas: Silence GCC 10 warning on tc-crx.c
opcode/crx.h has

typedef enum
  {
    ...
    MAX_REG
  }
reg;

typedef enum
  {
    c0 = MAX_REG,
  }
copreg;

tc-crx.c has

static int
getreg_image (reg r)
{
  ...
 /* Check whether the register is in registers table.  */
  if (r < MAX_REG)
    rreg = &crx_regtab[r];
  /* Check whether the register is in coprocessor registers table.  */
  else if (r < (int) MAX_COPREG)
    rreg = &crx_copregtab[r-MAX_REG];
}

Change getreg_image's argument type to int and replace fragP->fr_literal
with &fragP->fr_literal[0] to silence GCC 10 warning.

	PR gas/26044
	* config/tc-crx.c (getreg_image): Change argument type to int.
	(md_convert_frag): Replace fragP->fr_literal with
	&fragP->fr_literal[0].
2020-05-26 06:53:36 -07:00
H.J. Lu a05e3e2039 tc-score.c: Replace overlapping sprintf with memmove
Fix GCC 10 warning:

gas/config/tc-score.c:4575:6: error: ‘sprintf’ argument 3 may overlap destination object ‘keep_data’ [-Werror=restrict]
 4575 |      sprintf (append_str, "bne %s", keep_data);
      |      ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~

	PR gas/26044
	* onfig/tc-score.c (s3_do_macro_bcmp): Replace overlapping
	sprintf with memmove.
2020-05-26 06:12:37 -07:00
H.J. Lu c6412eeea9 gas: Silence GCC 10 warning on tc-mcore.c
* config/tc-mcore.c (md_convert_frag): Replace fragP->fr_literal
	with &fragP->fr_literal[0].
2020-05-25 19:39:13 -07:00
H.J. Lu 9fcc34577e tc-cr16.c: Use memmove to concatenate 2 overlapping strings
PR gas/26041
	* config/tc-cr16.c (md_assemble): Use memmove to concatenate
	2 overlapping strings.
2020-05-25 19:39:13 -07:00
H.J. Lu 6c115e16ca gas: Silence GCC 10 warning on tc-cr16.c
* config/tc-cr16.c (md_convert_frag): Replace fragP->fr_literal
	with &fragP->fr_literal[0].
2020-05-25 16:19:49 -07:00
H.J. Lu a39d29cda1 gas: Update fr_literal access in frag for GCC 10
When access fr_literal in

struct frag {
  ...
  /* Data begins here.  */
  char fr_literal[1];
};

with

char *buf = fragp->fr_fix + fragp->fr_literal;

GCC 10 gave

gas/config/tc-csky.c: In function ‘md_convert_frag’:
gas/config/tc-csky.c:4507:9: error: writing 1 byte into a region of size 0 [-Werror=stringop-overflow=]
 4507 |  buf[1] = BYTE_1 (CSKYV1_INST_SUBI | (7 << 4));
      |         ^

Change

  char *buf = fragp->fr_fix + fragp->fr_literal;

to

  char *buf = fragp->fr_fix + &fragp->fr_literal[0];

to silence GCC 10 warning.

	* config/tc-csky.c (md_convert_frag): Replace fragp->fr_literal
	with &fragp->fr_literal[0].
	* config/tc-microblaze.c (md_apply_fix): Likewise.
	* config/tc-sh.c (md_convert_frag): Likewise.
2020-05-25 04:51:17 -07:00
Jim Wilson 72393fd103 RISC-V: Gas inserts cfa relocs in wrong section.
The frag code makes a distinction between inserting frags before the frag
chains are chained together and afterward.  After chaining, we need to set
now_seg before creating the frag.  tc-xtensa.c has a function called
fix_new_exp_in_seg that handles this right, but switches segments twice each
time it is called.  In this case, we can inline it and pull the save and
restore out of the loop to get better code.

	gas/
	PR 26025
	* config/tc-riscv.c (riscv_pre_output_hook): Change s type from const
	asection to segT.  New locals seg and subseg.  Call subseg_set before
	fix_new_exp.  Call subseg_set after loop to restore original values.
2020-05-24 16:42:21 -07:00
Alan Modra 9fbb53c7c8 Replace "if (x) free (x)" with "free (x)", gas
* atof-generic.c: Replace "if (x) free (x)" with "free (x)"
	throughout.
	* config/obj-elf.c: Likewise.
	* config/tc-aarch64.c: Likewise.
	* config/tc-arm.c: Likewise.
	* config/tc-m68k.c: Likewise.
	* config/tc-nios2.c: Likewise.
	* config/tc-tic30.c: Likewise.
	* ecoff.c: Likewise.
	* read.c: Likewise.
	* stabs.c: Likewise.
	* symbols.c: Likewise.
	* testsuite/gas/all/test-gen.c: Likewise.
2020-05-21 10:45:33 +09:30
Nelson Chu 8f595e9b4f [PATCH v2 0/9] RISC-V: Support version controling for ISA standard extensions and CSR
1. Remove the -mriscv-isa-version and --with-riscv-isa-version options.
We can still use -march to choose the version for each extensions, so there is
no need to add these.

2. Change the arguments of options from [1p9|1p9p1|...] to [1.9|1.9.1|...].
Unlike the architecture string has specified by spec, ther is no need to do
the same thing for options.

3. Spilt the patches to reduce the burdens of review.

[PATCH 3/7] RISC-V: Support new GAS options and configure options to set ISA versions
to
[PATCH v2 3/9] RISC-V: Support GAS option -misa-spec to set ISA versions
[PATCH v2 4/9] RISC-V: Support configure options to set ISA versions by default.

[PATCH 4/7] RISC-V: Support version checking for CSR according to privilege version.
to
[PATCH v2 5/9] RISC-V: Support version checking for CSR according to privilege spec version.
[PATCH v2 6/9] RISC-V: Support configure option to choose the privilege spec version.

4. Use enum class rather than string to compare the choosen ISA spec in opcodes/riscv-opc.c.
The behavior is same as comparing the choosen privilege spec.

include	* opcode/riscv.h: Include "bfd.h" to support bfd_boolean.
	(enum riscv_isa_spec_class): New enum class.  All supported ISA spec
	belong to one of the class
	(struct riscv_ext_version): New structure holds version information
	for the specific ISA.
	* opcode/riscv-opc.h (DECLARE_CSR): There are two version information,
	define_version and abort_version.  The define_version means which
	privilege spec is started to define the CSR, and the abort_version
	means which privilege spec is started to abort the CSR.  If the CSR is
	valid for the newest spec, then the abort_version should be
	PRIV_SPEC_CLASS_DRAFT.
	(DECLARE_CSR_ALIAS): Same as DECLARE_CSR, but only for the obselete CSR.
	* opcode/riscv.h (enum riscv_priv_spec_class): New enum class.  Define
	the current supported privilege spec versions.
	(struct riscv_csr_extra): Add new fields to store more information
	about the CSR.  We use these information to find the suitable CSR
	address when user choosing a specific privilege spec.

binutils * dwarf.c: Updated since DECLARE_CSR is changed.

opcodes	* riscv-opc.c (riscv_ext_version_table): The table used to store
	all information about the supported spec and the corresponding ISA
	versions.  Currently, only Zicsr is supported to verify the
	correctness of Z sub extension settings.  Others will be supported
	in the future patches.
	(struct isa_spec_t, isa_specs): List for all supported ISA spec
	classes and the corresponding strings.
	(riscv_get_isa_spec_class): New function.  Get the corresponding ISA
	spec class by giving a ISA spec string.
	* riscv-opc.c (struct priv_spec_t): New structure.
	(struct priv_spec_t priv_specs): List for all supported privilege spec
	classes and the corresponding strings.
	(riscv_get_priv_spec_class): New function.  Get the corresponding
	privilege spec class by giving a spec string.
	(riscv_get_priv_spec_name): New function.  Get the corresponding
	privilege spec string by giving a CSR version class.
	* riscv-dis.c: Updated since DECLARE_CSR is changed.
	* riscv-dis.c: Add new disassembler option -Mpriv-spec to dump the CSR
	according to the chosen version.  Build a hash table riscv_csr_hash to
	store the valid CSR for the chosen pirv verison.  Dump the direct
	CSR address rather than it's name if it is invalid.
	(parse_riscv_dis_option_without_args): New function.  Parse the options
	without arguments.
	(parse_riscv_dis_option): Call parse_riscv_dis_option_without_args to
	parse the options without arguments first, and then handle the options
	with arguments.  Add the new option -Mpriv-spec, which has argument.
	* riscv-dis.c (print_riscv_disassembler_options): Add description
	about the new OBJDUMP option.

ld	* testsuite/ld-riscv-elf/attr-merge-arch-01.d: Updated
        priv attributes according to the -mpriv-spec option.
	* testsuite/ld-riscv-elf/attr-merge-arch-02.d: Likewise.
	* testsuite/ld-riscv-elf/attr-merge-arch-03.d: Likewise.
	* testsuite/ld-riscv-elf/attr-merge-priv-spec-a.s: Likewise.
	* testsuite/ld-riscv-elf/attr-merge-priv-spec-b.s: Likewise.
	* testsuite/ld-riscv-elf/attr-merge-priv-spec.d: Likewise.
	* testsuite/ld-riscv-elf/attr-merge-stack-align.d: Likewise.
	* testsuite/ld-riscv-elf/attr-merge-strict-align-01.d: Likewise.
	* testsuite/ld-riscv-elf/attr-merge-strict-align-02.d: Likewise.
	* testsuite/ld-riscv-elf/attr-merge-strict-align-03.d: Likewise.
	* testsuite/ld-riscv-elf/attr-merge-strict-align-04.d: Likewise.
	* testsuite/ld-riscv-elf/attr-merge-strict-align-05.d: Likewise.

bfd 	* elfxx-riscv.h (riscv_parse_subset_t): Add new callback function
	get_default_version.  It is used to find the default version for
	the specific extension.
	* elfxx-riscv.c (riscv_parsing_subset_version): Remove the parameters
	default_major_version and default_minor_version.  Add new bfd_boolean
	parameter *use_default_version.  Set it to TRUE if we need to call
	the callback rps->get_default_version to find the default version.
	(riscv_parse_std_ext): Call rps->get_default_version if we fail to find
	the default version in riscv_parsing_subset_version, and then call
	riscv_add_subset to add the subset into subset list.
	(riscv_parse_prefixed_ext): Likewise.
	(riscv_std_z_ext_strtab): Support Zicsr extensions.
	* elfnn-riscv.c (riscv_merge_std_ext): Use strcasecmp to compare the
	strings rather than characters.
	riscv_merge_arch_attr_info): The callback function get_default_version
	is only needed for assembler, so set it to NULL int the linker.
	* elfxx-riscv.c (riscv_estimate_digit): Remove the static.
	* elfxx-riscv.h: Updated.

gas	* testsuite/gas/riscv/priv-reg-fail-read-only-01.s: Updated.
	* config/tc-riscv.c (default_arch_with_ext, default_isa_spec):
	Static variables which are used to set the ISA extensions. You can
	use -march (or ELF build attributes) and -misa-spec to set them,
	respectively.
	(ext_version_hash): The hash table used to handle the extensions
	with versions.
	(init_ext_version_hash): Initialize the ext_version_hash according
	to riscv_ext_version_table.
	(riscv_get_default_ext_version): The callback function of
	riscv_parse_subset_t.  According to the choosed ISA spec,
	get the default version for the specific extension.
	(riscv_set_arch): Set the callback function.
	(enum options, struct option md_longopts): Add new option -misa-spec.
	(md_parse_option): Do not call riscv_set_arch for -march.  We will
	call it later in riscv_after_parse_args.  Call riscv_get_isa_spec_class
	to set default_isa_spec class.
	(riscv_after_parse_args): Call init_ext_version_hash to initialize the
	ext_version_hash, and then call riscv_set_arch to set the architecture
	with versions according to default_arch_with_ext.
	* testsuite/gas/riscv/attribute-02.d: Set 0p0 as default version for
	x extensions.
	* testsuite/gas/riscv/attribute-03.d: Likewise.
	* testsuite/gas/riscv/attribute-09.d: New testcase.  For i-ext, we
	already set it's version to 2p1 by march, so no need to use the default
	2p2 version.  For m-ext, we do not set the version by -march and ELF arch
	attribute, so set the default 2p0 to it.  For zicsr, it is not defined in
	ISA spec 2p2, so set 0p0 to it.
	* testsuite/gas/riscv/attribute-10.d: New testcase.  The version of
	zicsr is 2p0 according to ISA spec 20191213.
	* config/tc-riscv.c (DEFAULT_RISCV_ARCH_WITH_EXT)
	(DEFAULT_RISCV_ISA_SPEC): Default configure option settings.
	You can set them by configure options --with-arch and
	--with-isa-spec, respectively.
	(riscv_set_default_isa_spec): New function used to set the
	default ISA spec.
	(md_parse_option): Call riscv_set_default_isa_spec rather than
	call riscv_get_isa_spec_class directly.
	(riscv_after_parse_args): If the -isa-spec is not set, then we
	set the default ISA spec according to DEFAULT_RISCV_ISA_SPEC by
	calling riscv_set_default_isa_spec.
	* testsuite/gas/riscv/attribute-01.d: Add -misa-spec=2.2, since
	the --with-isa-spec may be set to different ISA spec.
	* testsuite/gas/riscv/attribute-02.d: Likewise.
	* testsuite/gas/riscv/attribute-03.d: Likewise.
	* testsuite/gas/riscv/attribute-04.d: Likewise.
	* testsuite/gas/riscv/attribute-05.d: Likewise.
	* testsuite/gas/riscv/attribute-06.d: Likewise.
	* testsuite/gas/riscv/attribute-07.d: Likewise.
	* configure.ac: Add configure options, --with-arch and
	--with-isa-spec.
	* configure: Regenerated.
	* config.in: Regenerated.
	* config/tc-riscv.c (default_priv_spec): Static variable which is
	used to check if the CSR is valid for the chosen privilege spec. You
	can use -mpriv-spec to set it.
	(enum reg_class): We now get the CSR address from csr_extra_hash rather
	than reg_names_hash.  Therefore, move RCLASS_CSR behind RCLASS_MAX.
	(riscv_init_csr_hashes): Only need to initialize one hash table
	csr_extra_hash.
	(riscv_csr_class_check): Change the return type to void.  Don't check
	the ISA dependency if -mcsr-check isn't set.
	(riscv_csr_version_check): New function.  Check and find the CSR address
	from csr_extra_hash, according to default_priv_spec.  Report warning
	for the invalid CSR if -mcsr-check is set.
	(reg_csr_lookup_internal): Updated.
	(reg_lookup_internal): Likewise.
	(md_begin): Updated since DECLARE_CSR and DECLARE_CSR_ALIAS are changed.
	(enum options, struct option md_longopts): Add new GAS option -mpriv-spec.
	(md_parse_option): Call riscv_set_default_priv_version to set
	default_priv_spec.
	(riscv_after_parse_args): If -mpriv-spec isn't set, then set the default
	privilege spec to the newest one.
	(enum riscv_csr_class, struct riscv_csr_extra): Move them to
	include/opcode/riscv.h.
	* testsuite/gas/riscv/priv-reg-fail-fext.d: This test case just want
	to check the ISA dependency for CSR, so fix the spec version by adding
	-mpriv-spec=1.11.
	* testsuite/gas/riscv/priv-reg-fail-fext.l: Likewise.  There are some
	version warnings for the test case.
	* gas/testsuite/gas/riscv/priv-reg-fail-read-only-01.d: Likewise.
	* gas/testsuite/gas/riscv/priv-reg-fail-read-only-01.l: Likewise.
	* gas/testsuite/gas/riscv/priv-reg-fail-read-only-02.d: Likewise.
	* gas/testsuite/gas/riscv/priv-reg-fail-rv32-only.d: Likewise.
	* gas/testsuite/gas/riscv/priv-reg-fail-rv32-only.l: Likewise.
	* gas/testsuite/gas/riscv/priv-reg-fail-version-1p9.d: New test case.
	Check whether the CSR is valid when privilege version 1.9 is choosed.
	* gas/testsuite/gas/riscv/priv-reg-fail-version-1p9.l: Likewise.
	* gas/testsuite/gas/riscv/priv-reg-fail-version-1p9p1.d: New test case.
	Check whether the CSR is valid when privilege version 1.9.1 is choosed.
	* gas/testsuite/gas/riscv/priv-reg-fail-version-1p9p1.l: Likewise.
	* gas/testsuite/gas/riscv/priv-reg-fail-version-1p10.d: New test case.
	Check whether the CSR is valid when privilege version 1.10 is choosed.
	* gas/testsuite/gas/riscv/priv-reg-fail-version-1p10.l: Likewise.
	* gas/testsuite/gas/riscv/priv-reg-fail-version-1p11.d: New test case.
	Check whether the CSR is valid when privilege version 1.11 is choosed.
	* gas/testsuite/gas/riscv/priv-reg-fail-version-1p11.l: Likewise.
	* config/tc-riscv.c (DEFAULT_RISCV_ISA_SPEC): Default configure option
	setting.  You can set it by configure option --with-priv-spec.
	(riscv_set_default_priv_spec): New function used to set the default
	privilege spec.
	(md_parse_option): Call riscv_set_default_priv_spec rather than
	call riscv_get_priv_spec_class directly.
	(riscv_after_parse_args): If -mpriv-spec isn't set, then we set the
	default privilege spec according to DEFAULT_RISCV_PRIV_SPEC by
	calling riscv_set_default_priv_spec.
	* testsuite/gas/riscv/csr-dw-regnums.d: Add -mpriv-spec=1.11, since
	the --with-priv-spec may be set to different privilege spec.
	* testsuite/gas/riscv/priv-reg.d: Likewise.
	* configure.ac: Add configure option --with-priv-spec.
	* configure: Regenerated.
	* config.in: Regenerated.
	* config/tc-riscv.c (explicit_attr): Rename explicit_arch_attr to
	explicit_attr.  Set it to TRUE if any ELF attribute is found.
	(riscv_set_default_priv_spec): Try to set the default_priv_spec if
	the priv attributes are set.
	(md_assemble): Set the default_priv_spec according to the priv
	attributes when we start to assemble instruction.
	(riscv_write_out_attrs): Rename riscv_write_out_arch_attr to
	riscv_write_out_attrs.  Update the arch and priv attributes.  If we
	don't set the corresponding ELF attributes, then try to output the
	default ones.
	(riscv_set_public_attributes): If any ELF attribute or -march-attr
	options is set (explicit_attr is TRUE), then call riscv_write_out_attrs
	to update the arch and priv attributes.
	(s_riscv_attribute): Make sure all arch and priv attributes are set
	before any instruction.
	* testsuite/gas/riscv/attribute-01.d: Update the priv attributes if any
	ELF attribute or -march-attr is set.  If the priv attributes are not
	set, then try to update them by the default setting (-mpriv-spec or
	--with-priv-spec).
	* testsuite/gas/riscv/attribute-02.d: Likewise.
	* testsuite/gas/riscv/attribute-03.d: Likewise.
	* testsuite/gas/riscv/attribute-04.d: Likewise.
	* testsuite/gas/riscv/attribute-06.d: Likewise.
	* testsuite/gas/riscv/attribute-07.d: Likewise.
	* testsuite/gas/riscv/attribute-08.d: Likewise.
	* testsuite/gas/riscv/attribute-09.d: Likewise.
	* testsuite/gas/riscv/attribute-10.d: Likewise.
	* testsuite/gas/riscv/attribute-unknown.d: Likewise.
	* testsuite/gas/riscv/attribute-05.d: Likewise.  Also, the priv spec
	set by priv attributes must be supported.
	* testsuite/gas/riscv/attribute-05.s: Likewise.
	* testsuite/gas/riscv/priv-reg-fail-version-1p9.d: Likewise.  Updated
	priv attributes according to the -mpriv-spec option.
	* testsuite/gas/riscv/priv-reg-fail-version-1p9p1.d: Likewise.
	* testsuite/gas/riscv/priv-reg-fail-version-1p10.d: Likewise.
	* testsuite/gas/riscv/priv-reg-fail-version-1p11.d: Likewise.
	* testsuite/gas/riscv/priv-reg.d: Removed.
	* testsuite/gas/riscv/priv-reg-version-1p9.d: New test case.  Dump the
	CSR according to the priv spec 1.9.
	* testsuite/gas/riscv/priv-reg-version-1p9p1.d: New test case.  Dump the
	CSR according to the priv spec 1.9.1.
	* testsuite/gas/riscv/priv-reg-version-1p10.d: New test case.  Dump the
	CSR according to the priv spec 1.10.
	* testsuite/gas/riscv/priv-reg-version-1p11.d: New test case.  Dump the
	CSR according to the priv spec 1.11.
	* config/tc-riscv.c (md_show_usage): Add descriptions about
	the new GAS options.
	* doc/c-riscv.texi: Likewise.
2020-05-20 17:22:48 +01:00
Peter Bergner 3d205eb448 Power10 dcbf, sync, and wait extensions.
opcodes/
	* ppc-opc.c (insert_ls, extract_ls): Handle 3-bit L fields and new
	WC values on POWER10 sync, dcbf  and wait instructions.
	(insert_pl, extract_pl): New functions.
	(L2OPT, LS, WC): Use insert_ls and extract_ls.
	(LS3): New , 3-bit L for sync.
	(LS3, L3OPT): New, 3-bit L for sync and dcbf.
	(SC2, PL): New, 2-bit SC and PL for sync and wait.
	(XWCPL_MASK, XL3RT_MASK, XSYNCLS_MASK): New instruction masks.
	(XOPL3, XWCPL, XSYNCLS): New opcode macros.
	(powerpc_opcodes) <dcbflp, dcbfps, dcbstps pause_short, phwsync,
	plwsync, stcisync, stncisync, stsync, waitrsv>: New extended mnemonics.
	<wait>: Enable PL operand on POWER10.
	<dcbf>: Enable L3OPT operand on POWER10.
	<sync>: Enable SC2 operand on POWER10.

gas/
	* testsuite/gas/ppc/power9.s <dcbf, dcbfl, dcbflp>: Add tests.
	* testsuite/gas/ppc/power9.d: Likewise.
	* testsuite/gas/ppc/power10.s <dcbf, dcbfps, dcbstps, hwsync, lwsync,
	pause_short, phwsync, plwsync, ptesync, stcisync, stncisync, stsync,
	sync, wait, waitrsv>: Add tests.
	* testsuite/gas/ppc/power10.d: Likewise.
2020-05-19 18:09:51 -05:00
Alexander Fedotov 164446e04c Fix the ARM assembler to generate a Realtime profile for armv8-r.
PR 25992
gas	* config/tc-arm.c : Add arm_ext_v8r feature.
	(it_fsm_post_encode): Check arm_ext_v8r feature.
	(get_aeabi_cpu_arch_from_fset): Check arm_ext_v8r feature.

include	* opcode/arm.h (ARM_EXT2_V8R): Define. Modified ARM_AEXT2_V8R.
2020-05-19 12:45:42 +01:00
Alan Modra 69f57659c3 Use bfd_get_filename throughout gas
* write.c (write_contents): Use bfd_get_filename rather than
	accessing bfd->filename directly.  Use bfd_section_name rather
	than accessing section->name directly.
2020-05-19 12:55:27 +09:30
Alan Modra 0e1d094e96 Clear all local_symbol.lsy_flags
* symbols.c (local_symbol_make): Init all of lsy_flags.
2020-05-19 10:51:04 +09:30
Alan Modra d402189f2f Re: Fix tight loop on recursively-defined symbols
sy_resolving ought to not be set for a struct local_symbol, but it is
apparent from local_symbol_make that the field is not initialised.

	* symbols.c (resolve_symbol_value): Invoke LOCAL_SYMBOL_CHECK
	before looking at add_symbol->sy_flags.sy_resolving.
2020-05-18 13:46:27 +09:30
liuhongt 503648e41e Don't handle lret/iret when -mlfence-before-ret=[or|not|shl|yes] since they are invalid in SGX enclaves.
gas/ChangeLog
	* gas/config/tc-i386.c: Not handle lret/iret.
	* gas/testsuite/gas/i386/lfence-ret-a.d: Adjust testcase.
	* gas/testsuite/gas/i386/lfence-ret-b.d: Ditto.
	* gas/testsuite/gas/i386/lfence-ret-c.d: Ditto.
	* gas/testsuite/gas/i386/lfence-ret-d.d: Ditto.
	* gas/testsuite/gas/i386/lfence-ret.s: Ditto.
	* gas/testsuite/gas/i386/x86-64-lfence-ret-a.d: Ditto.
	* gas/testsuite/gas/i386/x86-64-lfence-ret-b.d: Ditto.
	* gas/testsuite/gas/i386/x86-64-lfence-ret-c.d: Ditto.
	* gas/testsuite/gas/i386/x86-64-lfence-ret-d.d: Ditto.
	* gas/testsuite/gas/i386/x86-64-lfence-ret-e.d: Ditto.
	* gas/testsuite/gas/i386/x86-64-lfence-ret.s: Ditto.
	* gas/testsuite/gas/i386/x86-64-lfence-ret.e: Deleted.
2020-05-18 10:23:59 +08:00
Alan Modra 2a50b40146 Fix tight loop on recursively-defined symbols
This patch fixes a bug in GAS where the assembler enters a tight loop
when attempting to resolve recursively-defined symbols, e.g. when
trying to assemble "a=a".

This is a regression introduced between binutils 2.32 and 2.33,
by commit 1903f1385b

	* symbols.c (struct local_symbol): Update comment.
	(resolve_symbol_value): For resolved symbols equated to other
	symbols, verify that the referenced symbol is not a local_symbol
	before accessing sy_value.  Don't leave symbol loops during
	finalize_syms resolution.
	* testsuite/gas/all/assign-bad-recursive.d: New test.
	* testsuite/gas/all/assign-bad-recursive.l: Error output for test.
	* testsuite/gas/all/assign-bad-recursive.s: Assembly for test.
	* testsuite/gas/all/gas.exp: Run it.
2020-05-15 18:21:07 +09:30
Nick Clifton 9d95b8e9d6 Update Swedish translation for the gas sub-directory and a new Serbian translation for the gold sub-directory. 2020-05-14 11:26:26 +01:00
Alan Modra 3b646889b0 Power10 VSX scalar min-max-compare quad precision operations
opcodes/
	* ppc-opc (powerpc_opcodes): Add xscmpeqqp, xscmpgeqp, xscmpgtqp,
	xsmaxcqp, xsmincqp.
gas/
	* testsuite/gas/ppc/scalarquad.d,
	* testsuite/gas/ppc/scalarquad.s: New test.
	* testsuite/gas/ppc/ppc.exp: Run it.
2020-05-11 21:08:38 +09:30
Alan Modra 9cc4ce8831 Power10 VSX load/store rightmost element operations
opcodes/
	* ppc-opc.c (powerpc_opcodes): Add lxvrbx, lxvrhx, lxvrwx, lxvrdx,
	stxvrbx, stxvrhx, stxvrwx, stxvrdx.
gas/
	* testsuite/gas/ppc/rightmost.d,
	* testsuite/gas/ppc/rightmost.s: New test.
	* testsuite/gas/ppc/ppc.exp: Run it.
2020-05-11 21:08:37 +09:30
Alan Modra 5d57bc3ff9 Power10 test lsb by byte operation
opcodes/
	* ppc-opc.c (powerpc_opcodes): Add xvtlsbb.
gas/
	* testsuite/gas/ppc/xvtlsbb.d,
	* testsuite/gas/ppc/xvtlsbb.s: New test.
	* testsuite/gas/ppc/ppc.exp: Run it.
2020-05-11 21:08:37 +09:30
Alan Modra 66ef5847c3 Power10 string operations
opcodes/
	* ppc-opc.c (powerpc_opcodes): Add vstribl, vstribr, vstrihl, vstrihr,
	vclrlb, vclrrb, vstribl., vstribr., vstrihl., vstrihr..
gas/
	* testsuite/gas/ppc/stringop.d,
	* testsuite/gas/ppc/stringop.s: New test.
	* testsuite/gas/ppc/ppc.exp: Run it.
2020-05-11 21:08:37 +09:30
Peter Bergner 4f3e9537c4 Power10 Set boolean extension
opcodes/
	* ppc-opc.c (powerpc_opcodes) <setbc, setbcr, setnbc, setnbcr>: New
	mnemonics.
gas/
	* testsuite/gas/ppc/set_bool.d,
	* testsuite/gas/ppc/set_bool.s: New test.
	* testsuite/gas/ppc/ppc.exp: Run it.
2020-05-11 21:08:37 +09:30
Alan Modra ec40e91c77 Power10 bit manipulation operations
opcodes/
	* ppc-opc.c (UIM8, P_U8XX4_MASK): Define.
	(powerpc_opcodes): Add vgnb, vcfuged, vpextd, vpdepd, vclzdm,
	vctzdm, cntlzdm, pdepd, pextd, cfuged, cnttzdm.
	(prefix_opcodes): Add xxeval.
gas/
	* testsuite/gas/ppc/bitmanip.d,
	* testsuite/gas/ppc/bitmanip.s: New test.
	* testsuite/gas/ppc/ppc.exp: Run it.
2020-05-11 21:08:37 +09:30
Alan Modra d7e97a765e Power10 VSX PCV generate operations
opcodes/
	* ppc-opc.c (powerpc_opcodes): Add xxgenpcvbm, xxgenpcvhm,
	xxgenpcvwm, xxgenpcvdm.
gas/
	* testsuite/gas/ppc/genpcv.d,
	* testsuite/gas/ppc/genpcv.s: New test.
	* testsuite/gas/ppc/ppc.exp: Run it.
2020-05-11 21:08:37 +09:30
Alan Modra fdefed7c26 Power10 VSX Mask Manipulation Operations
opcodes/
	* ppc-opc.c (MP, VXVAM_MASK): Define.
	(VXVAPS_MASK): Use VXVA_MASK.
	(powerpc_opcodes): Add mtvsrbmi, vexpandbm, vexpandhm, vexpandwm,
	vexpanddm, vexpandqm, vextractbm, vextracthm, vextractwm,
	vextractdm, vextractqm, mtvsrbm, mtvsrhm, mtvsrwm, mtvsrdm, mtvsrqm,
	vcntmbb, vcntmbh, vcntmbw, vcntmbd.
gas/
	* testsuite/gas/ppc/maskmanip.d,
	* testsuite/gas/ppc/maskmanip.s: New test.
	* testsuite/gas/ppc/ppc.exp: Run it.
2020-05-11 21:08:37 +09:30
Alan Modra aa3c112fab Power10 Reduced precision outer product operations
include/
	* opcode/ppc.h (PPC_OPERAND_ACC): Define.  Renumber following
	PPC_OPERAND defines.
opcodes/
	* ppc-opc.c (insert_xa6a, extract_xa6a, insert_xb6a, extract_xb6a):
	New functions.
	(powerpc_operands): Define ACC, PMSK8, PMSK4, PMSK2, XMSK, YMSK,
	YMSK2, XA6a, XA6ap, XB6a entries.
	(PMMIRR, P_X_MASK, P_XX1_MASK, P_GER_MASK): Define
	(P_GER2_MASK, P_GER4_MASK, P_GER8_MASK, P_GER64_MASK): Define.
	(PPCVSX4): Define.
	(powerpc_opcodes): Add xxmfacc, xxmtacc, xxsetaccz,
	xvi8ger4pp, xvi8ger4, xvf16ger2pp, xvf16ger2, xvf32gerpp, xvf32ger,
	xvi4ger8pp, xvi4ger8, xvi16ger2spp, xvi16ger2s, xvbf16ger2pp,
	xvbf16ger2, xvf64gerpp, xvf64ger, xvi16ger2, xvf16ger2np,
	xvf32gernp, xvi8ger4spp, xvi16ger2pp, xvbf16ger2np, xvf64gernp,
	xvf16ger2pn, xvf32gerpn, xvbf16ger2pn, xvf64gerpn, xvf16ger2nn,
	xvf32gernn, xvbf16ger2nn, xvf64gernn, xvcvbf16sp, xvcvspbf16.
	(prefix_opcodes): Add pmxvi8ger4pp, pmxvi8ger4, pmxvf16ger2pp,
	pmxvf16ger2, pmxvf32gerpp, pmxvf32ger, pmxvi4ger8pp, pmxvi4ger8,
	pmxvi16ger2spp, pmxvi16ger2s, pmxvbf16ger2pp, pmxvbf16ger2,
	pmxvf64gerpp, pmxvf64ger, pmxvi16ger2, pmxvf16ger2np, pmxvf32gernp,
	pmxvi8ger4spp, pmxvi16ger2pp, pmxvbf16ger2np, pmxvf64gernp,
	pmxvf16ger2pn, pmxvf32gerpn, pmxvbf16ger2pn, pmxvf64gerpn,
	pmxvf16ger2nn, pmxvf32gernn, pmxvbf16ger2nn, pmxvf64gernn.
gas/
	* config/tc-ppc.c (pre_defined_registers): Add accumulators.
	(md_assemble): Check acc specified in correct operand.
	* testsuite/gas/ppc/outerprod.d,
	* testsuite/gas/ppc/outerprod.s,
	* testsuite/gas/ppc/vsx4.d,
	* testsuite/gas/ppc/vsx4.s: New tests.
	* testsuite/gas/ppc/ppc.exp: Run them.
2020-05-11 21:08:37 +09:30
Alan Modra 6edbfd3beb Power10 SIMD permute class operations
opcodes/
	* ppc-opc.c (insert_imm32, extract_imm32): New functions.
	(insert_xts, extract_xts): New functions.
	(IMM32, UIM3, IX, UIM5, SH3, XTS, P8RR): Define.
	(P_XX4_MASK, P_UXX4_MASK, VSOP, P_VS_MASK, P_VSI_MASK): Define.
	(VXRC_MASK, VXSH_MASK): Define.
	(powerpc_opcodes): Add vinsbvlx, vsldbi, vextdubvlx, vextdubvrx,
	vextduhvlx, vextduhvrx, vextduwvlx, vextduwvrx, vextddvlx,
	vextddvrx, vinshvlx, vinswvlx, vinsw, vinsbvrx, vinshvrx,
	vinswvrx, vinsd, vinsblx, vsrdbi, vinshlx, vinswlx, vinsdlx,
	vinsbrx, vinshrx, vinswrx, vinsdrx, lxvkq.
	(prefix_opcodes): Add xxsplti32dx, xxspltidp, xxspltiw, xxblendvb,
	xxblendvh, xxblendvw, xxblendvd, xxpermx.
gas/
	* testsuite/gas/ppc/simd_perm.d,
	* testsuite/gas/ppc/simd_perm.s: New test.
	* testsuite/gas/ppc/ppc.exp: Run it.
2020-05-11 21:08:37 +09:30
Alan Modra c7d7aea2f5 Power10 128-bit binary integer operations
opcodes/
	* ppc-opc.c (powerpc_opcodes): Add vrlq, vdivuq, vmsumcud, vrlqmi,
	vmuloud, vcmpuq, vslq, vdivsq, vcmpsq, vrlqnm, vcmpequq, vmulosd,
	vsrq, vdiveuq, vcmpgtuq, vmuleud, vsraq, vdivesq, vcmpgtsq, vmulesd,
	vcmpequq., vextsd2q, vmoduq, vcmpgtuq., vmodsq, vcmpgtsq., xscvqpuqz,
	xscvuqqp, xscvqpsqz, xscvsqqp, dcffixqq, dctfixqq.
gas/
	* testsuite/gas/ppc/int128.d,
	* testsuite/gas/ppc/int128.s: New test.
	* testsuite/gas/ppc/ppc.exp: Run it.
2020-05-11 21:08:37 +09:30
Alan Modra 94ba9882d5 Power10 VSX 32-byte storage access
bfd/
	* elf64-ppc.c (xlate_pcrel_opt): Handle lxvp and stxvp.
opcodes/
	* ppc-opc.c (insert_xtp, extract_xtp): New functions.
	(XTP, DQXP, DQXP_MASK): Define.
	(powerpc_opcodes): Add lxvp, stxvp, lxvpx, stxvpx.
	(prefix_opcodes): Add plxvp and pstxvp.
gas/
	* testsuite/gas/ppc/vsx_32byte.d,
	* testsuite/gas/ppc/vsx_32byte.s: New test.
	* testsuite/gas/ppc/ppc.exp: Run it.
ld/
	* testsuite/ld-powerpc/pcrelopt.s: Add lxvp and stxvp.
	* testsuite/ld-powerpc/pcrelopt.d: Update.
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