This patch adds initial 64-bit insn assembler/disassembler support.
The only instruction added is "pnop" along with the automatic aligning
of prefix instruction so they do not cross 64-byte boundaries.
include/
* dis-asm.h (WIDE_OUTPUT): Define.
* opcode/ppc.h (prefix_opcodes, prefix_num_opcodes): Declare.
(PPC_OPCODE_POWERXX, PPC_GET_PREFIX, PPC_GET_SUFFIX),
(PPC_PREFIX_P, PPC_PREFIX_SEG): Define.
opcodes/
* ppc-dis.c (ppc_opts): Add "future" entry.
(PREFIX_OPCD_SEGS): Define.
(prefix_opcd_indices): New array.
(disassemble_init_powerpc): Initialize prefix_opcd_indices.
(lookup_prefix): New function.
(print_insn_powerpc): Handle 64-bit prefix instructions.
* ppc-opc.c (PREFIX_OP, PREFIX_FORM, SUFFIX_MASK, PREFIX_MASK),
(PMRR, POWERXX): Define.
(prefix_opcodes): New instruction table.
(prefix_num_opcodes): New constant.
binutils/
* objdump.c (disassemble_bytes): Set WIDE_OUTPUT in flags.
gas/
* config/tc-ppc.c (ppc_setup_opcodes): Handle prefix_opcodes.
(struct insn_label_list): New.
(insn_labels, free_insn_labels): New variables.
(ppc_record_label, ppc_clear_labels, ppc_start_line_hook): New funcs.
(ppc_frob_label, ppc_new_dot_label): Move functions earlier in file
and call ppc_record_label.
(md_assemble): Handle 64-bit prefix instructions. Align labels
that are on the same line as a prefix instruction.
* config/tc-ppc.h (tc_frob_label, ppc_frob_label): Move to
later in the file.
(md_start_line_hook): Define.
(ppc_start_line_hook): Declare.
* testsuite/gas/ppc/prefix-align.d,
* testsuite/gas/ppc/prefix-align.s: New test.
* testsuite/gas/ppc/ppc.exp: Run new test.
The AArch64 disassembler has an optimization that it uses to reduce the amount
it has to search for mapping symbols during disassembly. This optimization
assumes that sections are listed in the section header in monotonic increasing
VMAs. However this is not a requirement for the ELF specification.
Because of this when such "out of order" sections occur the disassembler would
pick the wrong mapping symbol to disassemble the section with.
This fixes it by explicitly passing along the stop offset for the current
disassembly glob and when this changes compared to the previous one we've seen
the optimization won't be performed. In effect this restarts the search from
a well defined starting point. Usually the symbol's address.
The existing stop_vma can't be used for this as it is allowed to be unset and
setting this unconditionally would change the semantics of this field.
binutils/ChangeLog:
* objdump.c (disassemble_bytes): Pass stop_offset.
* testsuite/binutils-all/aarch64/out-of-order.T: New test.
* testsuite/binutils-all/aarch64/out-of-order.d: New test.
* testsuite/binutils-all/aarch64/out-of-order.s: New test.
include/ChangeLog:
* dis-asm.h (struct disassemble_info): Add stop_offset.
opcodes/ChangeLog:
* aarch64-dis.c (last_stop_offset): New.
(print_insn_aarch64): Use stop_offset.
Include <string.h> to dis-asm.h to get strchr declaration
include/Changelog:
2019-01-11 Pavel I. Kryukov <kryukov@frtk.ru>
* dis-asm.h: include <string.h>
The RISC-V assembler generates fake labels with the name '.L0 ' as
part of the debug information (see
gas/config/tc-riscv.h:FAKE_LABEL_NAME).
The problem is that currently, when disassembling an object file, the
output looks like this (this is an example from the GDB testsuite, but
is pretty representative of anything with debug information):
000000000000001e <main>:
1e: 7179 addi sp,sp,-48
20: f406 sd ra,40(sp)
22: f022 sd s0,32(sp)
24: 1800 addi s0,sp,48
0000000000000026 <.L0 >:
26: 87aa mv a5,a0
28: feb43023 sd a1,-32(s0)
2c: fcc43c23 sd a2,-40(s0)
30: fef42623 sw a5,-20(s0)
0000000000000034 <.L0 >:
34: fec42783 lw a5,-20(s0)
38: 0007871b sext.w a4,a5
3c: 678d lui a5,0x3
3e: 03978793 addi a5,a5,57 # 3039 <.LASF30+0x2a9d>
42: 02f71463 bne a4,a5,6a <.L0 >
0000000000000046 <.L0 >:
46: 000007b7 lui a5,0x0
4a: 0007b783 ld a5,0(a5) # 0 <need_malloc>
4e: 6f9c ld a5,24(a5)
0000000000000050 <.L0 >:
50: 86be mv a3,a5
52: 466d li a2,27
54: 4585 li a1,1
56: 000007b7 lui a5,0x0
5a: 00078513 mv a0,a5
5e: 00000097 auipc ra,0x0
62: 000080e7 jalr ra # 5e <.L0 +0xe>
0000000000000066 <.L0 >:
66: 4785 li a5,1
68: a869 j 102 <.L0 >
000000000000006a <.L0 >:
6a: 000007b7 lui a5,0x0
6e: 00078513 mv a0,a5
72: 00000097 auipc ra,0x0
76: 000080e7 jalr ra # 72 <.L0 +0x8>
The frequent repeated '.L0 ' labels are pointless, as they are
non-unique there's no way to match a use of '.L0 ' to its appearence
in the output, so we'd be better off just not printing it at all.
That's what this patch does by defining a 'symbol_is_valid' method for
RISC-V. With this commit, the same disassembly now looks like this:
000000000000001e <main>:
1e: 7179 addi sp,sp,-48
20: f406 sd ra,40(sp)
22: f022 sd s0,32(sp)
24: 1800 addi s0,sp,48
26: 87aa mv a5,a0
28: feb43023 sd a1,-32(s0)
2c: fcc43c23 sd a2,-40(s0)
30: fef42623 sw a5,-20(s0)
34: fec42783 lw a5,-20(s0)
38: 0007871b sext.w a4,a5
3c: 678d lui a5,0x3
3e: 03978793 addi a5,a5,57 # 3039 <.LASF30+0x2a9d>
42: 02f71463 bne a4,a5,6a <.L4>
46: 000007b7 lui a5,0x0
4a: 0007b783 ld a5,0(a5) # 0 <need_malloc>
4e: 6f9c ld a5,24(a5)
50: 86be mv a3,a5
52: 466d li a2,27
54: 4585 li a1,1
56: 000007b7 lui a5,0x0
5a: 00078513 mv a0,a5
5e: 00000097 auipc ra,0x0
62: 000080e7 jalr ra # 5e <main+0x40>
66: 4785 li a5,1
68: a869 j 102 <.L5>
000000000000006a <.L4>:
6a: 000007b7 lui a5,0x0
6e: 00078513 mv a0,a5
72: 00000097 auipc ra,0x0
76: 000080e7 jalr ra # 72 <.L4+0x8>
In order to share the fake label between the assembler and the
libopcodes library, I've added some new defines RISCV_FAKE_LABEL_NAME
and RISCV_FAKE_LABEL_CHAR in include/opcode/riscv.h. I could have
just moved FAKE_LABEL_NAME to the include file, however, I thnk this
would be confusing, someone working on the assembler would likely not
expect to find FAKE_LABEL_NAME defined outside of the assembler source
tree. By introducing the RISCV_FAKE_LABEL_* defines I can leave the
assembler standard FAKE_LABEL_ defines in the assembler source, but
still share the RISCV_FAKE_LABEL_* with libopcodes.
gas/ChangeLog:
* config/tc-riscv.h (FAKE_LABEL_NAME): Define as
RISCV_FAKE_LABEL_NAME.
(FAKE_LABEL_CHAR): Define as RISCV_FAKE_LABEL_CHAR.
include/ChangeLog:
* dis-asm.h (riscv_symbol_is_valid): Declare.
* opcode/riscv.h (RISCV_FAKE_LABEL_NAME): Define.
(RISCV_FAKE_LABEL_CHAR): Define.
opcodes/ChangeLog:
* disassembler.c (disassemble_init_for_target): Add RISC-V
initialisation.
* riscv-dis.c (riscv_symbol_is_valid): New function.
We have not only removed all unsupported and obsolete code, but also supported lost of new features,
including better link-time relaxations and TLS implementations. Besides, the files generated by the
newly assembler and linker usually get higher performance and more optimized code size.
ld * emultempl/nds32elf.em (hyper_relax): New variable.
(nds32_elf_create_output_section_statements):
the parameters of bfd_elf32_nds32_set_target_option
(PARSE_AND_LIST_PROLOGUE, PARSE_AND_LIST_OPTIONS,
PARSE_AND_LIST_ARGS_CASES): Add new option --mhyper-relax.
* emultempl/nds32elf.em (nds32_elf_after_open): Updated.
* emultempl/nds32elf.em (tls_desc_trampoline): New variable.
* (nds32_elf_create_output_section_statements): Updated.
* (nds32_elf_after_parse): Disable relaxations when PIC is enable.
* (PARSE_AND_LIST_PROLOGUE, PARSE_AND_LIST_OPTIONS,
PARSE_AND_LIST_ARGS_CASES): Add new option --m[no-]tlsdesc-trampoline.
include * elf/nds32.h: Remove the unused target features.
* dis-asm.h (disassemble_init_nds32): Declared.
* elf/nds32.h (E_NDS32_NULL): Removed.
(E_NDS32_HAS_DSP_INST, E_NDS32_HAS_ZOL): New.
* opcode/nds32.h: Ident.
(N32_SUB6, INSN_LW): New macros.
(enum n32_opcodes): Updated.
* elf/nds32.h: Doc fixes.
* elf/nds32.h: Add R_NDS32_LSI.
* elf/nds32.h: Add new relocations for TLS.
gas * config/tc-nds32.c: Remove the unused target features.
(nds32_relax_relocs, md_pseudo_table, nds32_elf_record_fixup_exp,
nds32_set_elf_flags_by_insn, nds32_insert_relax_entry,
nds32_apply_fix): Likewise.
(nds32_no_ex9_begin): Removed.
* config/tc-nds32.c (add_mapping_symbol_for_align,
make_mapping_symbol, add_mapping_symbol): New functions.
* config/tc-nds32.h (enum mstate): New.
(nds32_segment_info_type): Likewise.
* configure.ac (--enable-dsp-ext, --enable-zol-ext): New options.
* config.in: Regenerated.
* configure: Regenerated.
* config/tc-nds32.c (nds32_dx_regs):
Set the value according to the configuration.
(nds32_perf_ext, nds32_perf_ext2, nds32_string_ext, nds32_audio_ext):
Likewise.
(nds32_dsp_ext): New variable. Set the value according to the
configuration.
(nds32_zol_ext): Likewise.
(asm_desc, nds32_pseudo_opcode_table): Make them static.
(nds32_set_elf_flags_by_insn): Updated.
(nds32_check_insn_available): Updated.
(nds32_str_tolower): New function.
* config/tc-nds32.c (relax_table): Updated.
(md_begin): Updated.
(md_assemble): Use XNEW macro to allocate space for `insn.info',
and then remember to free it.
(md_section_align): Cast (-1) to ValueT.
(nds32_get_align): Cast (~0U) to addressT.
(nds32_relax_branch_instructions): Updated.
(md_convert_frag): Add new local variable `final_r_type'.
(invalid_prev_frag): Add new bfd_boolean parameter `relax'.
All callers changed.
* config/tc-nds32.c (struct nds32_relocs_pattern): Add `insn' field.
(struct nds32_hint_map): Add `option_list' field.
(struct suffix_name, suffix_table): Remove the unused `pic' field.
(do_pseudo_b, do_pseudo_bal): Remove the suffix checking.
(do_pseudo_la_internal, do_pseudo_pushpopm): Indent.
(relax_hint_bias, relax_hint_id_current): New static variables.
(reset_bias, relax_hint_begin): New variables.
(nds_itoa): New function.
(CLEAN_REG, GET_OPCODE): New macros.
(struct relax_hint_id): New.
(nds32_relax_hint): For .relax_hint directive, we can use `begin'
and `end' to mark the relax pattern without giving exactly id number.
(nds32_elf_append_relax_relocs): Handle the case that the .relax_hint
directives are attached to pseudo instruction.
(nds32_elf_save_pseudo_pattern): Change the second parameter from
instruction's opcode to byte code.
(nds32_elf_build_relax_relation): Add new bfd_boolean parameter
`pseudo_hint'.
(nds32_lookup_pseudo_opcode): Fix the overflow issue.
(enum nds32_insn_type): Add N32_RELAX_ALU1 and N32_RELAX_16BIT.
(nds32_elf_record_fixup_exp, relax_ls_table, hint_map,
nds32_find_reloc_table, nds32_match_hint_insn, nds32_parse_name):
Updated.
* config/tc-nds32.h (MAX_RELAX_NUM): Extend it to 6.
(enum nds32_relax_hint_type): Merge NDS32_RELAX_HINT_LA and
NDS32_RELAX_HINT_LS into NDS32_RELAX_HINT_LALS. Add
NDS32_RELAX_HINT_LA_PLT, NDS32_RELAX_HINT_LA_GOT and
NDS32_RELAX_HINT_LA_GOTOFF.
* config/tc-nds32.h (relax_ls_table): Add floating load/store
to gp relax pattern.
(hint_map, nds32_find_reloc_table): Likewise.
* configure.ac: Define NDS32_LINUX_TOOLCHAIN.
* configure: Regenerated.
* config.in: Regenerated.
* config/tc-nds32.h (enum nds32_ramp): Updated.
(enum nds32_relax_hint_type): Likewise.
* config/tc-nds32.c: Include "errno.h" and "limits.h".
(relax_ls_table): Add TLS relax patterns.
(nds32_elf_append_relax_relocs): Attach BFD_RELOC_NDS32_GROUP on
each instructions of TLS patterns.
(nds32_elf_record_fixup_exp): Updated.
(nds32_apply_fix): Likewise.
(suffix_table): Add TLSDESC suffix.
binutils* testsuite/binutils-all/objcopy.exp: Set the unsupported reloc number
from 215 to 255 for NDS32.
bfd * elf32-nds32.c (nds32_elf_relax_loadstore):
Remove the unused target features.
(bfd_elf32_nds32_set_target_option): Remove the unused parameters.
(nds32_elf_relax_piclo12, nds32_elf_relax_letlslo12,
nds32_elf_relax_letlsadd, nds32_elf_relax_letlsls,
nds32_elf_relax_pltgot_suff, nds32_elf_relax_got_suff
nds32_elf_relax_gotoff_suff, calculate_plt_memory_address,
calculate_plt_offset, calculate_got_memory_address,
nds32_elf_check_dup_relocs): Removed.
All callers changed.
* elf32-nds32.h: Remove the unused macros and defines.
(elf_nds32_link_hash_table): Remove the unused variable.
(bfd_elf32_nds32_set_target_option): Update prototype.
(nds32_elf_ex9_init): Removed.
* elf32-nds32.c (nds32_convert_32_to_16): Updated.
* elf32-nds32.c (HOWTO2, HOWTO3): Define new HOWTO macros
to initialize array nds32_elf_howto_table in any order
without lots of EMPTY_HOWTO.
(nds32_reloc_map): Updated.
* reloc.c: Add BFD_RELOC_NDS32_LSI.
* bfd-in2.h: Regenerated.
* bfd/libbfd.h: Regenerated.
* elf32-nds32.c (nds32_elf_relax_howto_table): Add R_NDS32_LSI.
(nds32_reloc_map): Likewise.
(nds32_elf_relax_flsi): New function.
(nds32_elf_relax_section): Support floating load/store relaxation.
* elf32-nds32.c (NDS32_GUARD_SEC_P, elf32_nds32_local_gp_offset):
New macro.
(struct elf_nds32_link_hash_entry): New `offset_to_gp' field.
(struct elf_nds32_obj_tdata): New `offset_to_gp' and `hdr_size' fields.
(elf32_nds32_allocate_local_sym_info, nds32_elf_relax_guard,
nds32_elf_is_target_special_symbol, nds32_elf_maybe_function_sym):
New functions.
(nds32_info_to_howto_rel): Add BFD_ASSERT.
(bfd_elf32_bfd_reloc_type_table_lookup, nds32_elf_link_hash_newfunc,
nds32_elf_link_hash_table_create, nds32_elf_relocate_section,
nds32_elf_relax_loadstore, nds32_elf_relax_lo12, nds32_relax_adjust_label,
bfd_elf32_nds32_set_target_option, nds32_fag_mark_relax): Updated.
(nds32_elf_final_sda_base): Improve it to find the better gp value.
(insert_nds32_elf_blank): Must consider `len' when inserting blanks.
* elf32-nds32.h (bfd_elf32_nds32_set_target_option): Update prototype.
(struct elf_nds32_link_hash_table): Add new variable `hyper_relax'.
* elf32-nds32.c (elf32_nds32_allocate_dynrelocs): New function.
(create_got_section): Likewise.
(allocate_dynrelocs, nds32_elf_size_dynamic_sections,
nds32_elf_relocate_section, nds32_elf_finish_dynamic_symbol): Updated.
(nds32_elf_check_relocs): Fix the issue that the shared library may
has TEXTREL entry in the dynamic section.
(nds32_elf_create_dynamic_sections): Enable to call readonly_dynrelocs
since the TEXTREL issue is fixed in the nds32_elf_check_relocs.
(nds32_elf_finish_dynamic_sections): Update and add DT_RELASZ
dynamic entry.
(calculate_offset): Remove the unused parameter `pic_ext_target' and
related codes.
All callers changed.
(elf_backend_dtrel_excludes_plt): Disable it temporarily since it
will cause some errors for our test cases.
* elf32-nds32.c (nds32_elf_merge_private_bfd_data): Allow to link the
generic object.
* reloc.c: Add TLS relocations.
* libbfd.h: Regenerated.
* bfd-in2.h: Regenerated.
* elf32-nds32.h (struct section_id_list_t): New.
(elf32_nds32_lookup_section_id, elf32_nds32_check_relax_group,
elf32_nds32_unify_relax_group, nds32_elf_unify_tls_model):
New prototypes.
(elf32_nds32_compute_jump_table_size, elf32_nds32_local_tlsdesc_gotent):
New macro.
(nds32_insertion_sort, bfd_elf32_nds32_set_target_option,
elf_nds32_link_hash_table): Updated.
* elf32-nds32.c (enum elf_nds32_tls_type): New.
(struct elf32_nds32_relax_group_t, struct relax_group_list_t): New.
(elf32_nds32_add_dynreloc, patch_tls_desc_to_ie, get_tls_type,
fls, ones32, list_insert, list_insert_sibling, dump_chain,
elf32_nds32_check_relax_group, elf32_nds32_lookup_section_id,
elf32_nds32_unify_relax_group, nds32_elf_unify_tls_model): New functions.
(elf_nds32_obj_tdata): Add new fields.
(elf32_nds32_relax_group_ptr, nds32_elf_local_tlsdesc_gotent): New macros.
(nds32_elf_howto_table): Add TLS relocations.
(nds32_reloc_map): Likewise.
(nds32_elf_copy_indirect_symbol, nds32_elf_size_dynamic_sections,
nds32_elf_finish_dynamic_symbol, elf32_nds32_allocate_local_sym_info,
nds32_elf_relocate_section, bfd_elf32_nds32_set_target_option,
nds32_elf_check_relocs, allocate_dynrelocs): Updated.
(nds32_elf_relax_section): Call nds32_elf_unify_tls_model.
(dtpoff_base): Rename it to `gottpof' and then update it.
opcodes * nds32-asm.c (operand_fields): Remove the unused fields.
(nds32_opcodes): Remove the unused instructions.
* nds32-dis.c (nds32_ex9_info): Removed.
(nds32_parse_opcode): Updated.
(print_insn_nds32): Likewise.
* nds32-asm.c (config.h, stdlib.h, string.h): New includes.
(LEX_SET_FIELD, LEX_GET_FIELD): Update defines.
(nds32_asm_init, build_operand_hash_table, build_keyword_hash_table,
build_opcode_hash_table): New functions.
(nds32_keyword_table, nds32_keyword_count_table, nds32_field_table,
nds32_opcode_table): New.
(hw_ktabs): Declare it to a pointer rather than an array.
(build_hash_table): Removed.
* nds32-asm.h (enum): Add SYN_INPUT, SYN_OUTPUT, SYN_LOPT,
SYN_ROPT and upadte HW_GPR and HW_INT.
* nds32-dis.c (keywords): Remove const.
(match_field): New function.
(nds32_parse_opcode): Updated.
* disassemble.c (disassemble_init_for_target):
Add disassemble_init_nds32.
* nds32-dis.c (eum map_type): New.
(nds32_private_data): Likewise.
(get_mapping_symbol_type, is_mapping_symbol, nds32_symbol_is_valid,
nds32_add_opcode_hash_table, disassemble_init_nds32): New functions.
(print_insn_nds32): Updated.
* nds32-asm.c (parse_aext_reg): Add new parameter.
(parse_re, parse_re2, parse_aext_reg): Only reduced registers
are allowed to use.
All callers changed.
* nds32-asm.c (keyword_usr, keyword_sr): Updated.
(operand_fields): Add new fields.
(nds32_opcodes): Add new instructions.
(keyword_aridxi_mx): New keyword.
* nds32-asm.h (enum): Add NASM_ATTR_DSP_ISAEXT, HW_AEXT_ARIDXI_MX
and NASM_ATTR_ZOL.
(ALU2_1, ALU2_2, ALU2_3): New macros.
* nds32-dis.c (nds32_filter_unknown_insn): Updated.
This patch series is a new binutils port for C-SKY processors, including support for both the V1 and V2 processor variants. V1 is derived from the MCore architecture while V2 is substantially different, with mixed 16- and 32-bit instructions, a larger register set, a different (but overlapping) ABI, etc. There is support for bare-metal ELF targets and Linux with both glibc and uClibc.
This code is being contributed jointly by C-SKY Microsystems and Mentor Graphics. C-SKY is responsible for the technical content and has proposed Lifang Xia and Yunhai Shang as port maintainers. (Note that C-SKY does have a corporate copyright assignment on file with the FSF.) Mentor Graphics' role has been cleaning up the code, adding documentation and additional test cases, etc, to address issues we anticipated reviewers would complain about.
bfd * Makefile.am (ALL_MACHINES, ALL_MACHINES_CFILES): Add C-SKY.
(BFD32_BACKENDS, BFD_BACKENDS_CFILES): Likewise.
* Makefile.in: Regenerated.
* archures.c (enum bfd_architecture): Add bfd_arch_csky and
related bfd_mach defines.
(bfd_csky_arch): Declare.
(bfd_archures_list): Add C-SKY.
* bfd-in.h (elf32_csky_build_stubs): Declare.
(elf32_csky_size_stubs): Declare.
(elf32_csky_next_input_section: Declare.
(elf32_csky_setup_section_lists): Declare.
* bfd-in2.h: Regenerated.
* config.bfd: Add C-SKY.
* configure.ac: Likewise.
* configure: Regenerated.
* cpu-csky.c: New file.
* elf-bfd.h (enum elf_target_id): Add C-SKY.
* elf32-csky.c: New file.
* libbfd.h: Regenerated.
* reloc.c: Add C-SKY relocations.
* targets.c (csky_elf32_be_vec, csky_elf32_le_vec): Declare.
(_bfd_target_vector): Add C-SKY target vector entries.
binutils* readelf.c: Include elf/csky.h.
(guess_is_rela): Handle EM_CSKY.
(dump_relocations): Likewise.
(get_machine_name): Likewise.
(is_32bit_abs_reloc): Likewise.
include * dis-asm.h (csky_symbol_is_valid): Declare.
* opcode/csky.h: New file.
opcodes * Makefile.am (TARGET_LIBOPCODES_CFILES): Add csky-dis.c.
* Makefile.in: Regenerated.
* configure.ac: Add C-SKY.
* configure: Regenerated.
* csky-dis.c: New file.
* csky-opc.h: New file.
* disassemble.c (ARCH_csky): Define.
(disassembler, disassemble_init_for_target): Add case for ARCH_csky.
* disassemble.h (print_insn_csky, csky_get_disassembler): Declare.
gas * Makefile.am (TARGET_CPU_CFILES): Add entry for C-SKY.
(TARGET_CPU_HFILES, TARGET_ENV_HFILES): Likewise.
* Makefile.in: Regenerated.
* config/tc-csky.c: New file.
* config/tc-csky.h: New file.
* config/te-csky_abiv1.h: New file.
* config/te-csky_abiv1_linux.h: New file.
* config/te-csky_abiv2.h: New file.
* config/te-csky_abiv2_linux.h: New file.
* configure.tgt: Add C-SKY.
* doc/Makefile.am (CPU_DOCS): Add entry for C-SKY.
* doc/Makefile.in: Regenerated.
* doc/all.texi: Set CSKY feature.
* doc/as.texi (Overview): Add C-SKY options.
(Machine Dependencies): Likewise.
* doc/c-csky.texi: New file.
* testsuite/gas/csky/*: New test cases.
ld * Makefile.am (ALL_EMULATION_SOURCES): Add C-SKY emulations.
(ecskyelf.c, ecskyelf_linux.c): New rules.
* Makefile.in: Regenerated.
* configure.tgt: Add C-SKY.
* emulparams/cskyelf.sh: New file.
* emulparams/cskyelf_linux.sh: New file.
* emultempl/cskyelf.em: New file.
* gen-doc.texi: Add C-SKY.
* ld.texi: Likewise.
(Options specific to C-SKY targets): New section.
* testsuite/ld-csky/*: New tests.
Implement MIPS target support for passing options to the disassembler,
complementing commit 65b48a8140 ("GDB: Add support for the new
set/show disassembler-options commands.").
This includes options that expect an argument, so adjust the generic
code and data structures used so as to handle such options. So as to
give backends syntax flexibility no specific delimiter has been defined
to separate options from their respective arguments, so it has to be
included as the last character of the option name. Completion code
however has not been adjusted and consequently option arguments cannot
be completed at this time.
Also the MIPS target has non-empty defaults for the options, so that ABI
names for the general-purpose registers respect our `set mips abi ...'
setting rather than always being determined from the ELF headers of the
binary file selected. Handle these defaults as implicit options, never
shown to the user and always prepended to the user-specified options, so
that the latters can override the defaults.
The resulting output for the MIPS target is as follows:
(gdb) show disassembler-options
The current disassembler options are ''
The following disassembler options are supported for use with the
'set disassembler-options <option>[,<option>...]' command:
no-aliases Use canonical instruction forms.
msa Recognize MSA instructions.
virt Recognize the virtualization ASE instructions.
xpa Recognize the eXtended Physical Address (XPA) ASE
instructions.
ginv Recognize the Global INValidate (GINV) ASE instructions.
gpr-names=ABI Print GPR names according to specified ABI.
Default: based on binary being disassembled.
fpr-names=ABI Print FPR names according to specified ABI.
Default: numeric.
cp0-names=ARCH Print CP0 register names according to specified architecture.
Default: based on binary being disassembled.
hwr-names=ARCH Print HWR names according to specified architecture.
Default: based on binary being disassembled.
reg-names=ABI Print GPR and FPR names according to specified ABI.
reg-names=ARCH Print CP0 register and HWR names according to specified
architecture.
For the options above, the following values are supported for "ABI":
numeric 32 n32 64
For the options above, the following values are supported for "ARCH":
numeric r3000 r3900 r4000 r4010 vr4100 vr4111 vr4120 r4300 r4400 r4600
r4650 r5000 vr5400 vr5500 r5900 r6000 rm7000 rm9000 r8000 r10000 r12000
r14000 r16000 mips5 mips32 mips32r2 mips32r3 mips32r5 mips32r6 mips64
mips64r2 mips64r3 mips64r5 mips64r6 interaptiv-mr2 sb1 loongson2e
loongson2f loongson3a octeon octeon+ octeon2 octeon3 xlr xlp
(gdb)
which corresponds to what `objdump --help' used to print for the MIPS
target, with minor formatting changes, most notably option argument
lists being wrapped, but also the amount of white space separating
options from the respective descriptions. The relevant part the new
code is now also used by `objdump --help', which means these formatting
changes apply to both outputs, except for argument list wrapping, which
is GDB-specific.
This also adds a separating new line between the heading and option
lists where descriptions are provided, hence:
(gdb) set architecture s390:31-bit
(gdb) show disassembler-options
The current disassembler options are ''
The following disassembler options are supported for use with the
'set disassembler-options <option>[,<option>...]' command:
esa Disassemble in ESA architecture mode
zarch Disassemble in z/Architecture mode
insnlength Print unknown instructions according to length from first two bits
(gdb)
but:
(gdb) set architecture powerpc:common
(gdb) show disassembler-options
The current disassembler options are ''
The following disassembler options are supported for use with the
'set disassembler-options <option>[,<option>...]' command:
403, 405, 440, 464, 476, 601, 603, 604, 620, 7400, 7410, 7450, 7455, 750cl,
821, 850, 860, a2, altivec, any, booke, booke32, cell, com, e200z4, e300,
e500, e500mc, e500mc64, e5500, e6500, e500x2, efs, efs2, power4, power5,
power6, power7, power8, power9, ppc, ppc32, 32, ppc64, 64, ppc64bridge,
ppcps, pwr, pwr2, pwr4, pwr5, pwr5x, pwr6, pwr7, pwr8, pwr9, pwrx, raw, spe,
spe2, titan, vle, vsx
(gdb)
Existing affected target backends have been adjusted accordingly.
This has been verified manually with:
(gdb) set architecture arm
(gdb) set architecture powerpc:common
(gdb) set architecture s390:31-bit
to cause no issues with the `show disassembler-options' and `set
disassembler-options' commands. A test case for the MIPS target has
also been provided, covering the default settings with ABI overrides as
well as disassembler option overrides.
2018-07-02 Maciej W. Rozycki <macro@mips.com>
Simon Marchi <simon.marchi@polymtl.ca>
include/
PR tdep/8282
* dis-asm.h (disasm_option_arg_t): New typedef.
(disasm_options_and_args_t): Likewise.
(disasm_options_t): Add `arg' member, document members.
(disassembler_options_mips): New prototype.
(disassembler_options_arm, disassembler_options_powerpc)
(disassembler_options_s390): Update prototypes.
opcodes/
PR tdep/8282
* mips-dis.c (mips_option_arg_t): New enumeration.
(mips_options): New variable.
(disassembler_options_mips): New function.
(print_mips_disassembler_options): Reimplement in terms of
`disassembler_options_mips'.
* arm-dis.c (disassembler_options_arm): Adapt to using the
`disasm_options_and_args_t' structure.
* ppc-dis.c (disassembler_options_powerpc): Likewise.
* s390-dis.c (disassembler_options_s390): Likewise.
gdb/
PR tdep/8282
* disasm.h (gdb_disassembler): Add
`m_disassembler_options_holder'. member
* disasm.c (get_all_disassembler_options): New function.
(gdb_disassembler::gdb_disassembler): Use it.
(gdb_buffered_insn_length_init_dis): Likewise.
(gdb_buffered_insn_length): Adjust accordingly.
(set_disassembler_options): Handle options with arguments.
(show_disassembler_options_sfunc): Likewise. Add a leading new
line if showing options with descriptions.
(disassembler_options_completer): Adapt to using the
`disasm_options_and_args_t' structure.
* mips-tdep.c (mips_disassembler_options): New variable.
(mips_disassembler_options_o32): Likewise.
(mips_disassembler_options_n32): Likewise.
(mips_disassembler_options_n64): Likewise.
(gdb_print_insn_mips): Don't set `disassembler_options'.
(gdb_print_insn_mips_n32, gdb_print_insn_mips_n64): Remove
functions.
(mips_gdbarch_init): Always set `gdbarch_print_insn' to
`gdb_print_insn_mips'. Set `gdbarch_disassembler_options',
`gdbarch_disassembler_options_implicit' and
`gdbarch_valid_disassembler_options'.
* arm-tdep.c (_initialize_arm_tdep): Adapt to using the
`disasm_options_and_args_t' structure.
* gdbarch.sh (disassembler_options_implicit): New `gdbarch'
method.
(valid_disassembler_options): Switch from `disasm_options_t' to
the `disasm_options_and_args_t' structure.
* NEWS: Document `set disassembler-options' support for the MIPS
target.
* gdbarch.h: Regenerate.
* gdbarch.c: Regenerate.
gdb/doc/
PR tdep/8282
* gdb.texinfo (Source and Machine Code): Document `set
disassembler-options' support for the MIPS target.
gdb/testsuite/
PR tdep/8282
* gdb.arch/mips-disassembler-options.exp: New test.
* gdb.arch/mips-disassembler-options.s: New test source.
When elf section size is beyond unsigned int max value, objdump fails
to disassemble from that section. Ex on PowerPC,
$ objdump -h /proc/kcore
Idx Name Size VMA
4 load2 100000000 c000000000000000
Here, size of load2 section is 0x100000000. Also note that, 0xc00....
address range is kernel space for PowerPC. Now let's try to disassemble
do_sys_open() using /proc/kcore.
$ cat /proc/kallsyms | grep -A1 -w do_sys_open
c00000000036c000 T do_sys_open
c00000000036c2d0 T SyS_open
Before patch:
$ objdump -d --start-address=0xc00000000036c000 --stop-address=0xc00000000036c2d0 /proc/kcore
/proc/kcore: file format elf64-powerpcle
Disassembly of section load2:
c00000000036c000 <load2+0x36c000>:
c00000000036c000: Address 0xc00000000036c000 is out of bounds.
Fix this by changing type of 'buffer_length' from unsigned int to
size_t. After patch:
$ objdump -d --start-address=0xc00000000036c000 --stop-address=0xc00000000036c2d0 /proc/kcore
/proc/kcore: file format elf64-powerpcle
Disassembly of section load2:
c00000000036c000 <load2+0x36c000>:
c00000000036c000: fc 00 4c 3c addis r2,r12,252
c00000000036c004: 00 53 42 38 addi r2,r2,21248
c00000000036c008: a6 02 08 7c mflr r0
include/
* dis-asm.h (struct disassemble_info): Change type of buffer_length
field to size_t.
opcodes/
* dis-buf.c (buffer_read_memory): Change type of end_addr_offset,
max_addr_offset and octets variables to size_t.
This is a follow-up to
[PATCH 0/6] Unify the disassembler selection in gdb and objdump
https://sourceware.org/ml/binutils/2017-05/msg00192.html
that is, opcodes is able to select the right disassembler, so gdb
doesn't have to select them. Instead, gdb can just use
default_print_insn. As a result, these print_insn_XXX are not used
out of opcodes, so this patch also moves their declarations from
include/dis-asm.h to opcodes/disassemble.h. With this change,
GDB doesn't use any print_insn_XXX directly any more.
gdb:
2017-06-14 Yao Qi <yao.qi@linaro.org>
* aarch64-tdep.c (aarch64_gdb_print_insn): Call
default_print_insn instead of print_insn_aarch64.
* arm-tdep.c (gdb_print_insn_arm): Call
default_print_insn instead of print_insn_big_arm
and print_insn_little_arm.
* i386-tdep.c (i386_print_insn): Call default_print_insn
instead of print_insn_i386.
* ia64-tdep.c (ia64_print_insn): Call
default_print_insn instead of print_insn_ia64.
* mips-tdep.c (gdb_print_insn_mips): Call
default_print_insn instead of print_insn_big_mips
and print_insn_little_mips.
* spu-tdep.c (gdb_print_insn_spu): Call default_print_insn
instead of print_insn_spu.
include:
2017-06-14 Yao Qi <yao.qi@linaro.org>
* dis-asm.h (print_insn_aarch64): Move it to opcodes/disassemble.h.
(print_insn_big_arm, print_insn_big_mips): Likewise.
(print_insn_i386, print_insn_ia64): Likewise.
(print_insn_little_arm, print_insn_little_mips): Likewise.
(print_insn_spu): Likewise.
opcodes:
2017-06-14 Yao Qi <yao.qi@linaro.org>
* aarch64-dis.c: Include disassemble.h instead of dis-asm.h.
* arm-dis.c: Likewise.
* ia64-dis.c: Likewise.
* mips-dis.c: Likewise.
* spu-dis.c: Likewise.
* disassemble.h (print_insn_aarch64): New declaration, moved from
include/dis-asm.h.
(print_insn_big_arm, print_insn_big_mips): Likewise.
(print_insn_i386, print_insn_ia64): Likewise.
(print_insn_little_arm, print_insn_little_mips): Likewise.
Nowadays, opcodes/disassemble.c:disassembler selects the proper
disassembler according to ABFD only. However, it actually
selects disassemblers according to arch, mach, endianess, and
abfd. This patch adds them to the parameters of disassembler,
so that its caller can still select disassemblers in case that
abfd is NULL (a typical case in GDB).
There isn't any functionality change.
binutils:
2017-05-24 Yao Qi <yao.qi@linaro.org>
* objdump.c (disassemble_data): Caller update.
include:
2017-05-24 Yao Qi <yao.qi@linaro.org>
* dis-asm.h (disassembler): Update declaration.
opcodes:
2017-05-24 Yao Qi <yao.qi@linaro.org>
* disassemble.c (disassembler): Add arguments a, big and mach.
Use them.
sim/common:
2017-05-24 Yao Qi <yao.qi@linaro.org>
* sim-trace.c (trace_disasm): Caller update.
include * dis-asm.h: Add prototypes for wasm32 disassembler.
opcodes * Makefile.am: Add wasm32-dis.c.
* configure.ac: Add wasm32-dis.c to wasm32 target.
* disassemble.c: Add wasm32 disassembler code.
* wasm32-dis.c: New file.
* Makefile.in: Regenerate.
* configure: Regenerate.
* po/POTFILES.in: Regenerate.
* po/opcodes.pot: Regenerate.
gas * testsuite/gas/wasm32/allinsn.d: Adjust test for disassembler
changes.
* testsuite/gas/wasm32/disass.d: New test.
* testsuite/gas/wasm32/disass.s: New test.
* testsuite/gas/wasm32/disass-2.d: New test.
* testsuite/gas/wasm32/disass-2.s: New test.
* testsuite/gas/wasm32/reloc.d: Adjust test for changed reloc
names.
* testsuite/gas/wasm32/reloc.s: Update test for changed assembler
syntax.
* testsuite/gas/wasm32/wasm32.exp: Run new tests. Expect allinsn
test to succeed.
The memory disassemble_info::disassembler_options points to is always
owned by the client. I.e., that field is an non-owning, observing
pointer. Thus const makes sense.
Are the include/ and opcodes/ bits OK?
Tested on x86_64 Fedora 23, built with --enable-targets=all.
include/ChangeLog:
2017-04-05 Pedro Alves <palves@redhat.com>
* dis-asm.h (disassemble_info) <disassembler_options>: Now a
"const char *".
(next_disassembler_option): Constify.
opcodes/ChangeLog:
2017-04-05 Pedro Alves <palves@redhat.com>
* arc-dis.c (parse_option, parse_disassembler_options): Constify.
* arm-dis.c (parse_arm_disassembler_options): Constify.
* ppc-dis.c (powerpc_init_dialect): Constify local.
* vax-dis.c (parse_disassembler_options): Constify.
gdb/ChangeLog:
2017-04-05 Pedro Alves <palves@redhat.com>
* arm-tdep.c (show_disassembly_style_sfunc): Constify local.
* disasm.c (set_disassembler_options): Constify local.
* i386-tdep.c (i386_print_insn): Remove cast and FIXME comment.
This commit adds support to GDB so that it can modify the disassembler-options
value that is passed to the disassembler, similar to objdump's -M option.
Currently, the only supported targets are ARM, PowerPC and S/390, but
adding support for a new target(s) is not difficult.
include/
* dis-asm.h (disasm_options_t): New typedef.
(parse_arm_disassembler_option): Remove prototype.
(set_arm_regname_option): Likewise.
(get_arm_regnames): Likewise.
(get_arm_regname_num_options): Likewise.
(disassemble_init_s390): New prototype.
(disassembler_options_powerpc): Likewise.
(disassembler_options_arm): Likewise.
(disassembler_options_s390): Likewise.
(remove_whitespace_and_extra_commas): Likewise.
(disassembler_options_cmp): Likewise.
(next_disassembler_option): New inline function.
(FOR_EACH_DISASSEMBLER_OPTION): New macro.
opcodes/
* disassemble.c Include "safe-ctype.h".
(disassemble_init_for_target): Handle s390 init.
(remove_whitespace_and_extra_commas): New function.
(disassembler_options_cmp): Likewise.
* arm-dis.c: Include "libiberty.h".
(NUM_ELEM): Delete.
(regnames): Use long disassembler style names.
Add force-thumb and no-force-thumb options.
(NUM_ARM_REGNAMES): Rename from this...
(NUM_ARM_OPTIONS): ...to this. Use ARRAY_SIZE.
(get_arm_regname_num_options): Delete.
(set_arm_regname_option): Likewise.
(get_arm_regnames): Likewise.
(parse_disassembler_options): Likewise.
(parse_arm_disassembler_option): Rename from this...
(parse_arm_disassembler_options): ...to this. Make static.
Use new FOR_EACH_DISASSEMBLER_OPTION macro to scan over options.
(print_insn): Use parse_arm_disassembler_options.
(disassembler_options_arm): New function.
(print_arm_disassembler_options): Handle updated regnames.
* ppc-dis.c: Include "libiberty.h".
(ppc_opts): Add "32" and "64" entries.
(ppc_parse_cpu): Use ARRAY_SIZE and disassembler_options_cmp.
(powerpc_init_dialect): Add break to switch statement.
Use new FOR_EACH_DISASSEMBLER_OPTION macro.
(disassembler_options_powerpc): New function.
(print_ppc_disassembler_options): Use ARRAY_SIZE.
Remove printing of "32" and "64".
* s390-dis.c: Include "libiberty.h".
(init_flag): Remove unneeded variable.
(struct s390_options_t): New structure type.
(options): New structure.
(init_disasm): Rename from this...
(disassemble_init_s390): ...to this. Add initializations for
current_arch_mask and option_use_insn_len_bits_p. Remove init_flag.
(print_insn_s390): Delete call to init_disasm.
(disassembler_options_s390): New function.
(print_s390_disassembler_options): Print using information from
struct 'options'.
* po/opcodes.pot: Regenerate.
binutils/
* objdump.c (main): Use remove_whitespace_and_extra_commas.
gdb/
* NEWS: Mention new set/show disassembler-options commands.
* doc/gdb.texinfo: Document new set/show disassembler-options commands.
* disasm.c: Include "arch-utils.h", "gdbcmd.h" and "safe-ctype.h".
(prospective_options): New static variable.
(gdb_disassembler::gdb_disassembler): Initialize
m_di.disassembler_options.
(gdb_buffered_insn_length_init_dis): Initilize di->disassembler_options.
(get_disassembler_options): New function.
(set_disassembler_options): Likewise.
(set_disassembler_options_sfunc): Likewise.
(show_disassembler_options_sfunc): Likewise.
(disassembler_options_completer): Likewise.
(_initialize_disasm): Likewise.
* disasm.h (get_disassembler_options): New prototype.
(set_disassembler_options): Likewise.
* gdbarch.sh (gdbarch_disassembler_options): New variable.
(gdbarch_verify_disassembler_options): Likewise.
* gdbarch.c: Regenerate.
* gdbarch.h: Likewise.
* arm-tdep.c (num_disassembly_options): Delete.
(set_disassembly_style): Likewise.
(arm_disassembler_options): New static variable.
(set_disassembly_style_sfunc): Convert short style name into long
option name. Call set_disassembler_options.
(show_disassembly_style_sfunc): New function.
(arm_gdbarch_init): Call set_gdbarch_disassembler_options and
set_gdbarch_verify_disassembler_options.
(_initialize_arm_tdep): Delete regnames variable and update callers.
(arm_disassembler_options): Initialize.
(disasm_options): New variable.
(num_disassembly_options): Rename from this...
(num_disassembly_styles): ...to this. Compute by scanning through
disasm_options.
(valid_disassembly_styles): Initialize using disasm_options.
Remove calls to parse_arm_disassembler_option, get_arm_regnames and
set_arm_regname_option.
Pass show_disassembly_style_sfunc to the "disassembler" setshow command.
* rs6000-tdep.c (powerpc_disassembler_options): New static variable.
(rs6000_gdbarch_init): Call set_gdbarch_disassembler_options and
set_gdbarch_verify_disassembler_options.
* s390-tdep.c (s390_disassembler_options): New static variable.
(s390_gdbarch_init):all set_gdbarch_disassembler_options and
set_gdbarch_verify_disassembler_options.
gdb/testsuite/
* gdb.arch/powerpc-power.exp: Delete test.
* gdb.arch/powerpc-power.s: Likewise.
* gdb.disasm/disassembler-options.exp: New test.
* gdb.arch/powerpc-altivec.exp: Likewise.
* gdb.arch/powerpc-altivec.s: Likewise.
* gdb.arch/powerpc-altivec2.exp: Likewise.
* gdb.arch/powerpc-altivec2.s: Likewise.
* gdb.arch/powerpc-altivec3.exp: Likewise.
* gdb.arch/powerpc-altivec3.s: Likewise.
* gdb.arch/powerpc-power7.exp: Likewise.
* gdb.arch/powerpc-power7.s: Likewise.
* gdb.arch/powerpc-power8.exp: Likewise.
* gdb.arch/powerpc-power8.s: Likewise.
* gdb.arch/powerpc-power9.exp: Likewise.
* gdb.arch/powerpc-power9.s: Likewise.
* gdb.arch/powerpc-vsx.exp: Likewise.
* gdb.arch/powerpc-vsx.s: Likewise.
* gdb.arch/powerpc-vsx2.exp: Likewise.
* gdb.arch/powerpc-vsx2.s: Likewise.
* gdb.arch/powerpc-vsx3.exp: Likewise.
* gdb.arch/powerpc-vsx3.s: Likewise.
* gdb.arch/arm-disassembler-options.exp: Likewise.
* gdb.arch/powerpc-disassembler-options.exp: Likewise.
* gdb.arch/s390-disassembler-options.exp: Likewise.
include * dis-asm.h (struct disassemble_info): Add stop_vma field.
binuti * objdump.c (disassemble_bytes): Set the stop_vma field in the
disassemble_info structure when disassembling code sections with
-d.
* doc/binutils.texi (objdump): Document the discrepancy between -d
and -D.
opcodes * dis-buf.c (buffer_read_memory): Fail is stop_vma is set and the
requested region lies beyond it.
* bfin-dis.c (print_insn_bfin): Ignore sysop instructions when
looking for 32-bit insns.
* mcore-dis.c (print_insn_mcore): Disable stop_vma when reading
data.
* sh-dis.c (print_insn_sh): Likewise.
* tic6x-dis.c (print_insn_tic6x): Disable stop_vma when reading
blocks of instructions.
* vax-dis.c (print_insn_vax): Check that the requested address
does not clash with the stop_vma.
tests * gas/arm/backslash-at.s: Add extra .byte directives so that the
foo symbol does not appear to point half way through an
instruction.
* gas/arm/backslash-at.d: Update expected disassembly.
* gas/i386/ilp32/x86-64-opcode-inval-intel.d: Likewise.
* gas/i386/ilp32/x86-64-opcode-inval.d: Likewise.
* gas/i386/x86-64-opcode-inval-intel.d: Likewise.
* gas/i386/x86-64-opcode-inval.d: Likewise.
* metag.h: New file.
* dis-asm.h (print_insn_metag): New declaration.
* metag.h: New file.
* Makefile.am: Add Meta.
* Makefile.in: Regenerate.
* configure: Regenerate.
* configure.in: Add Meta.
* disassemble.c: Add Meta support.
* metag-dis.c: New file.
* Makefile.am: Add Meta.
* Makefile.in: Regenerate.
* archures.c (bfd_mach_metag): New.
* bfd-in2.h: Regenerate.
* config.bfd: Add Meta.
* configure: Regenerate.
* configure.in: Add Meta.
* cpu-metag.c: New file.
* elf-bfd.h: Add Meta.
* elf32-metag.c: New file.
* elf32-metag.h: New file.
* libbfd.h: Regenerate.
* reloc.c: Add Meta relocations.
* targets.c: Add Meta.
* Makefile.am: Add Meta.
* Makefile.in: Regenerate.
* config/tc-metag.c: New file.
* config/tc-metag.h: New file.
* configure.tgt: Add Meta.
* doc/Makefile.am: Add Meta.
* doc/Makefile.in: Regenerate.
* doc/all.texi: Add Meta.
* doc/as.texiinfo: Document Meta options.
* doc/c-metag.texi: New file.
* gas/metag/labelarithmetic.d: New file.
* gas/metag/labelarithmetic.s: New file.
* gas/metag/metacore12.d: New file.
* gas/metag/metacore12.s: New file.
* gas/metag/metacore21-invalid.l: New file.
* gas/metag/metacore21-invalid.s: New file.
* gas/metag/metacore21.d: New file.
* gas/metag/metacore21.s: New file.
* gas/metag/metacore21ext.d: New file.
* gas/metag/metacore21ext.s: New file.
* gas/metag/metadsp21-invalid.l: New file.
* gas/metag/metadsp21-invalid.s: New file.
* gas/metag/metadsp21.d: New file.
* gas/metag/metadsp21.s: New file.
* gas/metag/metadsp21ext.d: New file.
* gas/metag/metadsp21ext.s: New file.
* gas/metag/metafpu21.d: New file.
* gas/metag/metafpu21.s: New file.
* gas/metag/metafpu21ext.d: New file.
* gas/metag/metafpu21ext.s: New file.
* gas/metag/metag.exp: New file.
* gas/metag/tls.d: New file.
* gas/metag/tls.s: New file.
* Makefile.am: Add Meta.
* Makefile.in: Regenerate.
* configure.tgt: Add Meta.
* emulparams/elf32metag.sh: New file.
* emultempl/metagelf.em: New file.
* ld-elf/merge.d: Mark Meta as xfail.
* ld-gc/start.d: Skip this test on Meta.
* ld-gc/personality.d: Skip this test on Meta.
* ld-metag/external.s: New file.
* ld-metag/metag.exp: New file.
* ld-metag/pcrel.d: New file.
* ld-metag/pcrel.s: New file.
* ld-metag/shared.d: New file.
* ld-metag/shared.r: New file.
* ld-metag/shared.s: New file.
* ld-metag/stub.d: New file.
* ld-metag/stub.s: New file.
* ld-metag/stub_pic_app.d: New file.
* ld-metag/stub_pic_app.r: New file.
* ld-metag/stub_pic_app.s: New file.
* ld-metag/stub_pic_shared.d: New file.
* ld-metag/stub_pic_shared.s: New file.
* ld-metag/stub_shared.d: New file.
* ld-metag/stub_shared.r: New file.
* ld-metag/stub_shared.s: New file.
* binutils/readelf.c: (guess_is_rela): Add EM_METAG.
(dump_relocations): Add EM_METAG.
(get_machine_name): Correct case for Meta.
(is_32bit_abs_reloc): Add support for Meta ADDR32 reloc.
(is_none_reloc): Add support for Meta NONE reloc.
Alan Modra
Peter Bergner
Tamar Christina
Павел Крюков
Andrew Burgess
John Darrington
Nick Clifton
Andrew Jenner
Maciej W. Rozycki
Francois H. Theron
Ravi Bangoria
Yao Qi
Pip Cet
Pedro Alves
Peter Bergner
Dimitar Dimitrov
Claudiu Zissulescu
DJ Delorie
Eric Botcazou
Christian Svensson
Kuan-Lin Chen
Sandra Loosemore
Joseph Myers