Not much to see here, just reduce the number of calls to S_GET_VALUE
and symbol_symbolS in the comparison functions.
* config/tc-xtensa.c (xg_order_trampoline_chain_entry): Don't
call S_GET_VALUE multiple times for a symbol. Rearrange code
so it is obvious what is the primary sort key.
(xg_order_trampoline_chain): Similarly.
Also fixes m68hc1x printf arguments which would have bombed when
compiling on a 32-bit host with --enable-64-bit-bfd.
bfd/
PR 24955
* elf32-arm.c (set_cmse_veneer_addr_from_implib): Use bfd_malloc
rather than xmalloc.
* elf32-m68hc1x.c (reloc_warning): New function.
(elf32_m68hc11_relocate_section): Use it here. Cast bfd_vma values
corresponding to %lx in format strings.
* elf32-nds32.c (nds32_insertion_sort): Use a stack temporary.
gas/
* config/tc-nds32.c (nds32_set_section_relocs): Use relocs and n
parameters rather than equivalent sec->orelocation and
sec->reloc_count. Don't sort for n <= 1. Tidy.
PR 25041
opcodes * avr-dis.c (avr_operand): Fix construction of address for lds/sts
instructions.
gas * testsuite/gas/avr/pr25041.s: New test.
* testsuite/gas/avr/pr25041.d: New test driver.
So far z15 was identified as arch13. After the machine has been
announced we can now add the real name.
gas/ChangeLog:
2019-10-08 Andreas Krebbel <krebbel@linux.ibm.com>
* config/tc-s390.c (s390_parse_cpu): Add z15 as alternate CPU
name.
* doc/as.texi: Add z15 to CPU string list.
* doc/c-s390.texi: Likewise.
opcodes/ChangeLog:
2019-10-08 Andreas Krebbel <krebbel@linux.ibm.com>
* s390-mkopc.c (main): Enable z15 as CPU string in the opcode
table.
This functionality will generate a new GNU object attribute for the "data region"
has been added. This object attribute is used
mark whether the compiler has generated code assuming that data could be in the
upper or lower memory regions.
Code which assumes data is always in the lower memory region is incompatible
with code which uses the full memory range for data.
The patch also adds a new assembler directive ".mspabi_attribute" to handle the
existing MSPABI object attributes. GCC will now emit both .gnu_attribute and
.mspabi_attribute directives to indicate what options the source file was
compiled with.
The assembler will now check the values set in these directives against the
options that the it has been invoked with. If there is a discrepancy, the
assembler will exit with an error.
bfd * elf32-msp430.c (elf32_msp430_merge_mspabi_attributes): Rename to..
(elf32_msp430_merge_msp430_attributes): Add support for merging the GNU
object attribute for data region.
binutils* readelf.c (display_msp430_gnu_attribute): New.
(process_arch_specific): Use msp430 specific handler for GNU
attributes.
gas * config/tc-msp430.c (md_parse_option): Set lower_data_region_only to
FALSE if the data region is set to "upper", "either" or "none".
(msp430_object_attribute): New.
(md_pseudo_table): Handle .mspabi_attribute and .gnu_attribute.
(msp430_md_end): Replace hard-coded attribute values with enums.
Handle data region object attribute.
* doc/as.texi: Document MSP430 Data Region object attribute.
* doc/c-msp430.texi: Document the .mspabi_attribute directive.
* testsuite/gas/msp430/attr-430-small-bad.d: New test.
* testsuite/gas/msp430/attr-430-small-bad.l: New test.
* testsuite/gas/msp430/attr-430-small-good.d: New test.
* testsuite/gas/msp430/attr-430-small.s: New test.
* testsuite/gas/msp430/attr-430x-large-any-bad.d: New test.
* testsuite/gas/msp430/attr-430x-large-any-bad.l: New test.
* testsuite/gas/msp430/attr-430x-large-any-good.d: New test.
* testsuite/gas/msp430/attr-430x-large-any.s: New test.
* testsuite/gas/msp430/attr-430x-large-lower-bad.d: New test.
* testsuite/gas/msp430/attr-430x-large-lower-bad.l: New test.
* testsuite/gas/msp430/attr-430x-large-lower-good.d: New test.
* testsuite/gas/msp430/attr-430x-large-lower.s: New test.
* testsuite/gas/msp430/msp430.exp: Run new tests.
include * elf/msp430.h: Add enums for MSPABI and GNU object attribute tag names
and values.
ld * testsuite/ld-msp430-elf/attr-gnu-main.s: New test.
* testsuite/ld-msp430-elf/attr-gnu-obj.s: New test.
* testsuite/ld-msp430-elf/attr-gnu-region-lower-upper.d: New test.
* testsuite/ld-msp430-elf/attr-gnu-region-lower.d: New test.
* testsuite/ld-msp430-elf/attr-gnu-region-upper.d: New test.
* testsuite/ld-msp430-elf/msp430-elf.exp: Run new tests.
First and foremost the EsSeg attribute was misplaced for CMPSD. Then
both it and MOVSD were lacking Dword on both of their operands.
Finally string insns with multiple operands and requiring use of ES:
had the wrong operand number reported in the diagnostic.
The fix for PR12848 introduced an off by one error in the mask, this corrected
the negative overflows but not the positive overflows. As a result the
conditional branch instructions accepted a too wide positive immediate which
resulted in it corrupting the instruction during encoding.
The relocation I believe has been incorrectly named, to be consistent with the
other relocations it should have been named BRANCH21 which is why the masks for
it are confusing.
I've replaced the masks with a function out_of_range_p which should make it
harder to make such mistakes.
The mask for BL/BLX on Armv6t+ is also wrong, the extended range is 25-bits
and so the mask should be checking for 24-bits for positive overflow.
gas/ChangeLog:
PR gas/24991
* config/tc-arm.c (out_of_range_p): New.
(md_apply_fix): Use it in BFD_RELOC_THUMB_PCREL_BRANCH9,
BFD_RELOC_THUMB_PCREL_BRANCH12, BFD_RELOC_THUMB_PCREL_BRANCH20,
BFD_RELOC_THUMB_PCREL_BRANCH23, BFD_RELOC_THUMB_PCREL_BRANCH25
* testsuite/gas/arm/pr24991.d: New test.
* testsuite/gas/arm/pr24991.l: New test.
* testsuite/gas/arm/pr24991.s: New test.
This patch modifies assembler to accept the equivalent sized floating
and signless datatypes for VLDR instruction but as alias for the unsigned version.
gas/ChangeLog:
2019-09-23 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
* config/tc-arm.c (do_mve_vstr_vldr_RQ): Modify function to allow float
* and signless datatypes for few cases of VLDR instruction.
* testsuite/gas/arm/mve-vldr-bad-3.l: Modify.
* testsuite/gas/arm/mve-vldr-bad-3.s: Likewise.
* testsuite/gas/arm/mve-vstrldr-1.d: Likewise.
* testsuite/gas/arm/mve-vstrldr-1.s: Likewise.
bfd/
* bfd-in.h: Move arm declaraions..
* cpu-arm.h: ..to here, new file..
* coff-arm.h: ..and here, new file..
* elf32-arm.h: ..and here, new file.
* cpu-arm.c: Include cpu-arm.h.
* coff-arm.c: Include cpu-arm.h and coff-arm.h.
* elf32-arm.c: Include cpu-arm.h and elf32-arm.h.
* pe-arm.c: Move function rename defines later.
* pe-arm-wince.c: Likewise and include sysdep.h and bfd.h early.
* bfd-in2.h: Regenerate.
gas/
* config/tc-arm.c: Include cpu-arm.h.
ld/
* emultempl/armelf.em: Include elf32-arm.h.
* emultempl/pe.em: Move func defines later and include coff-arm.h.
This one exposed a bug in tic6x gas, found with inline function
parameter type checking. struct bfd_section and struct bfd_symbol
both have a flags field, so bfd_is_com_section (symbol) compiled OK
when bfd_is_com_section was a macro but didn't special case common
symbols.
bfd/
* bfd-in.h (bfd_section_name, bfd_section_size, bfd_section_vma),
(bfd_section_lma, bfd_section_alignment, bfd_section_flags),
(bfd_section_userdata, bfd_is_com_section, discarded_section),
(bfd_get_section_limit_octets, bfd_get_section_limit): Delete macros.
* bfd.c (bfd_get_section_limit_octets, bfd_get_section_limit),
(bfd_section_list_remove, bfd_section_list_append),
(bfd_section_list_prepend, bfd_section_list_insert_after),
(bfd_section_list_insert_before, bfd_section_removed_from_list):
New inline functions.
* section.c (bfd_is_und_section, bfd_is_abs_section),
(bfd_is_ind_section, bfd_is_const_section, bfd_section_list_remove),
(bfd_section_list_append, bfd_section_list_prepend),
(bfd_section_list_insert_after, bfd_section_list_insert_before),
(bfd_section_removed_from_list): Delete macros.
(bfd_section_name, bfd_section_size, bfd_section_vma),
(bfd_section_lma, bfd_section_alignment, bfd_section_flags),
(bfd_section_userdata, bfd_is_com_section, bfd_is_und_section),
(bfd_is_abs_section, bfd_is_ind_section, bfd_is_const_section),
(discarded_section): New inline functions.
* bfd-in2.h: Regenerate.
gas/
* config/tc-tic6x.c (tc_gen_reloc): Correct common symbol check.
ld/
* emultempl/xtensaelf.em (xtensa_get_section_deps): Comment.
Use bfd_section_userdata.
(xtensa_set_section_deps): Use bfd_set_section_userdata.
* ldlang.c (lang_output_section_get): Use bfd_section_userdata.
(sort_def_symbol): Likewise, and bfd_set_section_userdata.
(init_os): Use bfd_set_section_userdata.
(print_all_symbols): Use bfd_section_userdata.
* ldlang.h (get_userdata): Delete.
Commit 21df382b91 ("x86: fold SReg{2,3}") went too far: Folding 64-bit
PUSH/POP templates into non-64-bit ones isn't correct, due to the
different operand widths, and hence suffixes permitted. Restore the
separate templates.
Add tests of PUSH/POP with q suffix and %fs/%gs operands to the
testsuite. While doing so also add PUSHF/POPF ones _without_ suffix.
These NEWS entries had been missed when the instructions were added.
gas/ChangeLog:
2019-09-19 Matthew Malcomson <matthew.malcomson@arm.com>
* NEWS: Add SVE2 and TME entries.
I get some spurious changes when running autoconf/automake for various
projects in the tree. This is likely because they were generated using
distro-patched tools last time.
I ran `autoreconf -f` in the various automake projects of the
binutils-gdb tree, and this is the result. The tools I am using have
been compiled from source, from the upstream release.
bfd/ChangeLog:
* Makefile.in: Re-generate.
* configure: Re-generate.
* doc/Makefile.in: Re-generate.
binutils/ChangeLog:
* Makefile.in: Re-generate.
* configure: Re-generate.
* doc/Makefile.in: Re-generate.
gas/ChangeLog:
* Makefile.in: Re-generate.
* configure: Re-generate.
* doc/Makefile.in: Re-generate.
gold/ChangeLog:
* testsuite/Makefile.in: Re-generate.
gprof/ChangeLog:
* Makefile.in: Re-generate.
* configure: Re-generate.
ld/ChangeLog:
* Makefile.in: Re-generate.
* configure: Re-generate.
opcodes/ChangeLog:
* Makefile.in: Re-generate.
* configure: Re-generate.
Generalize opcode arch dependencies so that we can support the
overlapping B extension Zb* subsets.
2019-09-17 Maxim Blinov <maxim.blinov@embecosm.com>
gas/
* config/tc-riscv.c (riscv_multi_subset_supports): Handle
insn_class enum rather than subset char string.
(riscv_ip): Update call to riscv_multi_subset_supports.
include/
* opcode/riscv.h (riscv_insn_class): New enum.
* opcode/riscv.h (struct riscv_opcode): Change
subset field to insn_class field.
opcodes/
* riscv-opc.c (riscv_opcodes): Change subset field
to insn_class field for all instructions.
(riscv_insn_types): Likewise.
This patch adds support for MVE VCTP instruction in assembler.
gas ChangeLog:
2019-09-10 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
* config/tc-arm.c (M_MNEM_vctp): Add new Mnemonic.
(do_mve_vctp): Add function to encode VCTP instruction.
* testsuite/gas/arm/mve-vctp-bad.d: New test.
* testsuite/gas/arm/mve-vctp-bad.l: Likewise.
* testsuite/gas/arm/mve-vctp-bad.s: Likewise.
* testsuite/gas/arm/mve-vctp.d: Likewise.
* testsuite/gas/arm/mve-vctp.s: Likewise.
This patch make changes to the assembler to encode MVE VMOV instruction "a" same as "b".
a: VMOV<c><q> <Dd>, <Dm>
b: VMOV<c><q>.F64 <Dd>, <Dm>
gas/ChangeLog:
2019-08-30 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
* config/tc-arm.c (do_neon_mov): Modify "if" statement.
* testsuite/gas/arm/mve-vmov-bad-3.d: New test.
* testsuite/gas/arm/mve-vmov-bad-3.l: Likewise.
* testsuite/gas/arm/mve-vmov-bad-3.s: Likewise.
gas * config/tc-arm.c (parse_neon_mov): Add check to accept vector
register to both the arguments in VMOV instruction.
* testsuite/gas/arm/mve-vmov-1.d: Modify.
* testsuite/gas/arm/mve-vmov-1.s: Likewise.
* testsuite/gas/arm/mve-vorr.d: Likewise.
opcodes * arm-dis.c (mve_opcodes): Add entry for MVE_VMOV_VEC_TO_VEC.
(is_mve_undefined): Add case for MVE_VMOV_VEC_TO_VEC.
(print_insn_mve): Add condition to check Qm==Qn of VORR instruction.
li is a pseudo instruction in RISC-V, it might expand to more than one
instructions if the immediate value can't fit addi or lui, but the
assembler will always using 4-byte instructions during expansion.
For example:
li a0, 0x12345001
will expand into
12345537 lui a0,0x12345
00150513 addi a0,a0,1
but addi could be compress into
0505 addi a0,a0,1
It because load_const use macro_build to emit instructions,
and macro_build call append_insn, and expect it will compress
it if possible, but the fact is append_insn never compress anything,
So this patch redirect the li expansion flow to normal instruction
emission flow via md_assemble, added md_assemblef as an wrapper for
that for easier emit instruction with printf-style argument to build
instruction.
gas/ChangeLog:
* tc-riscv.c (md_assemblef): New.
(load_const) Use md_assemblef instead of macro_build to emit
instructions.
* testsuite/gas/riscv/li32.d: New.
* testsuite/gas/riscv/li32.s: Ditto.
* testsuite/gas/riscv/li64.d: Ditto.
* testsuite/gas/riscv/li64.s: Ditto.
This patch adds support for following CPUs:
Cortex-M35P, Cortex-A77, Cortex-A76AE.
Related specifications can be found at https://developer.arm.com/ip-products/processors.
gas/ChangeLog:
* config/tc-arm.c: New entries for Cortex-M35P, Cortex-A77,
and Cortex-A76AE.
* doc/c-arm.texi: Document new processors.
* testsuite/gas/arm/cpu-cortex-a76ae.d: New test.
* testsuite/gas/arm/cpu-cortex-a77.d: New test.
* testsuite/gas/arm/cpu-cortex-m35p.d: New test.
bfd/ChangeLog:
* cpu-arm.c: New entries for Cortex-M35P, Cortex-A77, Cortex-A76AE.
* atof-generic.c (atof_generic): Do not ignore leading zeros if
they appear after a decimal point.
* testsuite/gas/all/float.s: Extend test to include a number with
a leading decimal point followed by several zeroes.
* testsuite/gas/i386/fp.s: Likewise.
* testsuite/gas/i386/fp.d: Update expected output.
The syntax of the directive is:
.float16 <0-n decimal numbers>
e.g.
.float16 0.5
.float16 10.2, NaN, 452.09
The floats will always be encoded using the binary16 format as described in the
IEEE 754-2008 standard. There is no need to support Arm's alternative half-precision
format since AArch64 only supports the IEEE format.
gas * config/tc-aarch64.c: Add float16 directive and add "Hh" to
acceptable float characters.
* doc/c-aarch64.texi: Documentation for float16 directive.
* testsuite/gas/aarch64/float16-be.d: New test.
* testsuite/gas/aarch64/float16-le.d: New test.
* testsuite/gas/aarch64/float16.s: New test.
* NEWS: Add NEWS entry.
Related specifications can be found at
https://developer.arm.com/ip-products/processors.
gas * NEWS: Mention the Arm and AArch64 new processors.
* config/tc-aarch64.c: New entries for Cortex-A34, Cortex-A65,
Cortex-A77, cortex-A65AE, and Cortex-A76AE.
* doc/c-aarch64.texi: Document new CPUs.
* testsuite/gas/aarch64/cpu-cortex-a34.d: New test.
* testsuite/gas/aarch64/cpu-cortex-a65.d: New test.
* testsuite/gas/aarch64/cpu-cortex-a65ae.d: New test.
* testsuite/gas/aarch64/cpu-cortex-a76ae.d: New test.
* testsuite/gas/aarch64/cpu-cortex-a77.d: New test.
* testsuite/gas/aarch64/nop-asm.s: New test.
bfd * cpu-aarch64.c: New entries for Cortex-A34, Cortex-A65,
Cortex-A77, cortex-A65AE, and Cortex-A76AE.
gas/
* config/tc-mips.c (mips_move_labels): Retain ISA mode bit
when moving labels in text segments.
(mips_align): Indicate text mode when aligning labels in
text segments.
* gas/testsuite/gas/mips/insn-isa-mode.d: New test.
* gas/testsuite/gas/mips/insn-isa-mode.s: New test source.
* gas/testsuite/gas/mips/mips.exp: Run the new test.
The tests were failing due to md_atof trying to do word-wise endian
switching on the float16 (for little-endian targets sometimes
multi word values have their word order changed).
However since a float16 is only 1 word wide, it would end up writing
incorrect data, as you cannot switch the word order of just one word.
* config/tc-arm.c (md_atof): Add precision check. Formatting.
This is a change to the first published specifications [1][a] but since there is no hardware
out there that uses the old instructions we do not want to support the old variant.
This changes are done based on the latest published specifications [1][b].
[1] https://developer.arm.com/architectures/cpu-architecture/m-profile/docs/ddi0553/latest/armv81-m-architecture-reference-manual
[a] version bf
[b] version bh
gas * config/tc-arm.c (enum operand_parse_code): Add the entry OP_I48_I64.
(po_imm1_or_imm2_or_fail): Marco to check the immediate is either of
48 or 64.
(parse_operands): Add case OP_I48_I64.
(do_mve_scalar_shift1): Add function to encode the MVE shift
instructions with 4 arguments.
* testsuite/gas/arm/mve-shift-bad.l: Modify.
* testsuite/gas/arm/mve-shift-bad.s: Likewise.
* testsuite/gas/arm/mve-shift.d: Likewise.
* testsuite/gas/arm/mve-shift.s: Likewise.
opcodes * arm-dis.c (struct mopcode32 mve_opcodes): Modify the mask for
cases MVE_SQRSHRL and MVE_UQRSHLL.
(print_insn_mve): Add case for specifier 'k' to check
specific bit of the instruction.
Half precision floating point numbers will be encoded using the IEEE 754
half precision floating point format - 16 bits in total, 1 for sign, 5
for exponent and 10 bits of mantissa.
This patch implements the float16 directive for both the IEEE 754 format
and the Arm alternative format for the Arm backend.
The syntax of the directive is:
.float16 <0-n decimal numbers>
e.g.
.float16 12.0
.float16 0.23, 433.1, 0.06
The Arm alternative format is almost identical to the IEEE 754 format,
except that it doesn't encode for NaNs or Infinity (instead an exponent
of 0x1F represents a normalized number in the range 65536 to 131008).
The alternative format is documented in the reference manual:
https://static.docs.arm.com/ddi0487/db/DDI0487D_b_armv8_arm.pdf?_ga=2.72318806.49764181.1561632697-999473562.1560847439
Which format is used is controlled by the .float16_format <format>
directive, where if <format> = ieee, then use the IEEE 754
half-precision format else if <format> = alternative, then use the
Arm alternative format
Or the format can be set on the command line via the -mfp16-format
option that has a similar syntax. -mfp16-format=<ieee|alternative>.
This also fixes the format and it cannot be changed by any directives.
Once the format has been set (either by the command line option or a directive) it cannot be changed,
and any attempts to change it (i.e. with the float16_format directive) will result in a warning and the
line being ignored.
For ELF targets the appropriate EABI attribute will be written out at the end of assembling
if the format has been explicitly specified. If no format has been explicitly specified then no
EABI attributes will be written.
If the format is not explicitly specified then any float16 directives are encoding using the IEEE 754-2008
format by default until the format is fixed or changed with the float16_format directive.
gas * config/tc-arm.c (enum fp_16bit_format): Add enum to represent the 2 float16 encodings.
(md_atof): Set precision for float16 type.
(arm_is_largest_exponent_ok): Check for whether to encode with the IEEE or alternative
format.
(set_fp16_format): Parse a float16_format directive.
(arm_parse_fp16_opt): Parse the fp16-format command line option.
(aeabi_set_public_attributes): For ELF encode the FP16 format EABI attribute.
* config/tc-arm.h (TC_LARGEST_EXPONENT_IS_NORMAL): Macro that expands to
arm_is_largest_exponent_ok.
(arm_is_largest_exponent_ok): Add prototype for arm_is_largest_exponent_ok function.
* doc/c-arm.texi: Add documentation for .float16, .float16_format and -mfp16-format=
* testsuite/gas/arm/float16-bad.d: New test.
* testsuite/gas/arm/float16-bad.l: New test.
* testsuite/gas/arm/float16-bad.s: New test.
* testsuite/gas/arm/float16-be.d: New test.
* testsuite/gas/arm/float16-format-bad.d: New test.
* testsuite/gas/arm/float16-format-bad.l: New test.
* testsuite/gas/arm/float16-format-bad.s: New test.
* testsuite/gas/arm/float16-format-opt-bad.d: New test.
* testsuite/gas/arm/float16-format-opt-bad.l: New test.
* testsuite/gas/arm/float16-le.d: New test.
* testsuite/gas/arm/float16.s: New test.
* testsuite/gas/arm/float16-eabi-alternative-format.d: New test.
* testsuite/gas/arm/float16-eabi-ieee-format.d: New test.
* testsuite/gas/arm/float16-eabi-no-format.d: New test.
* testsuite/gas/arm/float16-eabi.s: New test.
* config/atof-ieee.c (H_PRECISION): Macro for precision of float16
type.
(atof_ieee): Set precision and exponent bits for encoding float16
types.
(gen_to_words): NaN and Infinity encoding for float16.
(ieee_md_atof): Set precision for encoding float16 type.
In order to be able to add/remove insns to/from the middle of these
tests, generalize the patterns for the symbol reference comments of RIP-
relative operands.
Previously GAS would accept .u32, .u16 and .u8 suffixes to the VQ(R)DMLAH and VQ(R)DMLASH
instructions, however the Armv8.1-M Mainline specification states that these functions only
have signed variations (.s32, .s16 and .s8 suffixes).
This is documented here:
https://static.docs.arm.com/ddi0553/bh/DDI0553B_h_armv8m_arm.pdf?_ga=2.143079093.1892401233.1563295591-999473562.1560847439#page=1183
gas * config/tc-arm.c (do_mve_vqdmlah): Use N_S_32 macro.
(do_neon_qrdmlah): Use N_S_32 macro.
* testsuite/gas/arm/mve-vqdmlah-bad.d: New test.
* testsuite/gas/arm/mve-vqdmlah-bad.l: New test.
* testsuite/gas/arm/mve-vqdmlah-bad.s: New test.
* testsuite/gas/arm/mve-vqdmlah.d: Remove unsigned instruction tests.
* testsuite/gas/arm/mve-vqdmlah.s: Remove unsigned instruction tests.
* testsuite/gas/arm/mve-vqdmlash-bad.d: New test.
* testsuite/gas/arm/mve-vqdmlash-bad.l: New test.
* testsuite/gas/arm/mve-vqdmlash-bad.s: New test.
* testsuite/gas/arm/mve-vqdmlash.d: Remove unsigned instruction tests.
* testsuite/gas/arm/mve-vqdmlash.s: Remove unsigned instruction tests.
opcodes * arm-dis.c: Only accept signed variants of VQ(R)DMLAH and VQ(R)DMLASH
instructions.
New instruction are added, and some of them are overlapping. Update
disassembler to correctly recognize them. Introduce nps400 option.
opcodes/
xxxx-xx-xx Claudiu Zissulescu <claziss@synopsys.com>
* arc-dis.c (skip_this_opcode): Check also for 0x07 major opcodes,
and MPY class instructions.
(parse_option): Add nps400 option.
(print_arc_disassembler_options): Add nps400 info.
gas/
xxxx-xx-xx Claudiu Zissulescu <claziss@synopsys.com>
* testsuite/gas/arc/nps400-6.d: Update test.
