2010-09-27 15:33:00 +02:00
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2010-09-27 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
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* s390-dis.c (print_insn_s390): Pick instruction with most
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specific mask.
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* s390-opc.c: Add unused bits to the insn mask.
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* s390-opc.txt: Reorder some instructions to prefer more recent
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versions.
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2010-09-27 11:47:05 +02:00
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2010-09-27 Tejas Belagod <tejas.belagod@arm.com>
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* arm_dis.c (print_insn_coprocessor): Apply off-by-alignment
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correction to unaligned PCs while printing comment.
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2010-09-23 17:52:19 +02:00
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2010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
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* arm-dis.c (arm_opcodes): Add Virtualiztion Extensions support.
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(thumb32_opcodes): Likewise.
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(banked_regname): New function.
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(print_insn_arm): Add Virtualization Extensions support.
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(print_insn_thumb32): Likewise.
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2010-09-23 17:37:45 +02:00
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2010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
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* arm-dis.c (arm_opcodes): Support disassembly of UDIV and SDIV in
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ARM state.
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2010-09-23 17:26:24 +02:00
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2010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
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* arm-dis.c (arm_opcodes): SMC implies Security Extensions.
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(thumb32_opcodes): Likewise.
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2010-09-23 17:18:19 +02:00
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2010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
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* arm-dis.c (arm_opcodes): Add support for pldw.
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(thumb32_opcodes): Likewise.
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2010-09-22 23:55:17 +02:00
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2010-09-22 Robin Getz <robin.getz@analog.com>
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* bfin-dis.c (fmtconst): Cast address to 32bits.
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2010-09-22 23:54:33 +02:00
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2010-09-22 Mike Frysinger <vapier@gentoo.org>
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* bfin-dis.c (decode_REGMV_0): Rewrite valid combo checks.
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2010-09-22 23:53:46 +02:00
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2010-09-22 Robin Getz <robin.getz@analog.com>
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* bfin-dis.c (decode_ProgCtrl_0): Check for parallel insns.
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Reject P6/P7 to TESTSET.
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(decode_PushPopReg_0): Check for parallel insns. Reject pushing
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SP onto the stack.
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(decode_PushPopMultiple_0): Check for parallel insns. Make sure
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P/D fields match all the time.
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(decode_CCflag_0): Check for parallel insns. Verify x/y fields
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are 0 for accumulator compares.
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(decode_CC2stat_0): Check for parallel insns. Reject CC<op>CC.
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(decode_CaCTRL_0, decode_ccMV_0, decode_CC2dreg_0, decode_BRCC_0,
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decode_UJUMP_0, decode_LOGI2op_0, decode_COMPI2opD_0,
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decode_COMPI2opP_0, decode_LoopSetup_0, decode_LDIMMhalf_0,
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decode_CALLa_0, decode_linkage_0, decode_pseudoDEBUG_0,
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decode_pseudoOChar_0, decode_pseudodbg_assert_0): Check for parallel
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insns.
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(decode_dagMODim_0): Verify br field for IREG ops.
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(decode_LDST_0): Reject preg load into same preg.
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(_print_insn_bfin): Handle returns for ILLEGAL decodes.
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(print_insn_bfin): Likewise.
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2010-09-22 23:53:14 +02:00
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2010-09-22 Mike Frysinger <vapier@gentoo.org>
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* bfin-dis.c (decode_PushPopMultiple_0): Return 0 when pr > 5.
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2010-09-22 23:41:39 +02:00
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2010-09-22 Robin Getz <robin.getz@analog.com>
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* bfin-dis.c (decode_dsp32shiftimm_0): Add missing "S" flag.
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2010-09-22 23:39:08 +02:00
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2010-09-22 Mike Frysinger <vapier@gentoo.org>
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* bfin-dis.c (decode_CC2stat_0): Decode all ASTAT bits.
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2010-09-22 23:38:20 +02:00
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2010-09-22 Robin Getz <robin.getz@analog.com>
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* bfin-dis.c (IS_DREG, IS_PREG, IS_GENREG, IS_DAGREG): Reject
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register values greater than 8.
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(IS_RESERVEDREG, allreg, mostreg): New helpers.
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(decode_ProgCtrl_0): Call IS_DREG/IS_PREG as appropriate.
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(decode_PushPopReg_0): Call mostreg/allreg as appropriate.
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(decode_CC2dreg_0): Check valid CC register number.
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2010-09-22 23:26:13 +02:00
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2010-09-22 Robin Getz <robin.getz@analog.com>
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* bfin-dis.c (decode_pseudoDEBUG_0): Add space after DBG.
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2010-09-22 23:05:03 +02:00
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2010-09-22 Robin Getz <robin.getz@analog.com>
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* bfin-dis.c (machine_registers): Add AC0_COPY, V_COPY, and RND_MOD.
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(reg_names): Likewise.
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(decode_statbits): Likewise; while reformatting to make manageable.
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2010-09-22 22:59:00 +02:00
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2010-09-22 Mike Frysinger <vapier@gentoo.org>
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* bfin-dis.c (decode_pseudoDEBUG_0): Add space after OUTC.
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(decode_pseudoOChar_0): New function.
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(_print_insn_bfin): Remove #if 0 and call new decode_pseudoOChar_0.
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2010-09-22 22:37:25 +02:00
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2010-09-22 Robin Getz <robin.getz@analog.com>
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* bfin-dis.c (decode_dsp32shift_0): Decode sub opcodes 2/2 as
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LSHIFT instead of SHIFT.
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2010-09-22 22:32:40 +02:00
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2010-09-22 Mike Frysinger <vapier@gentoo.org>
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* bfin-dis.c (constant_formats): Constify the whole structure.
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(fmtconst): Add const to return value.
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(reg_names): Mark const.
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(decode_multfunc): Mark s0/s1 as const.
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(decode_macfunc): Mark a/sop as const.
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2010-09-17 12:13:41 +02:00
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2010-09-17 Tejas Belagod <tejas.belagod@arm.com>
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* arm_dis.c (coprocessor_opcodes): Add MRC entry for APSR_nzcv.
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2010-09-15 01:49:04 +02:00
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2010-09-14 Maciej W. Rozycki <macro@codesourcery.com>
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* mips-opc.c (mips_builtin_opcodes): Add "sync_acquire",
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"sync_mb", "sync_release", "sync_rmb" and "sync_wmb".
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2010-09-10 15:00:54 +02:00
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2010-09-10 Pierre Muller <muller@ics.u-strasbg.fr>
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* src/opcodes/dlx-dis.c (print_insn_dlx): Use dlx_insn type for
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dlx_insn_type array.
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2010-08-31 23:56:57 +02:00
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2010-08-31 H.J. Lu <hongjiu.lu@intel.com>
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PR binutils/11960
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* i386-dis.c (sIv): New.
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(dis386): Replace Iq with sIv on "pushT".
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(reg_table): Replace T with {T|} on callT, JcallT, jmpT and JjmpT.
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(x86_64_table): Replace {T|}/{P|} with P.
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(putop): Add 'w' to 'T'/'P' if needed for Intel syntax.
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(OP_sI): Update v_mode. Remove w_mode.
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2010-08-27 15:59:55 +02:00
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2010-08-27 Nathan Froyd <froydnj@codesourcery.com>
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* ppc-opc.c (powerpc_opcodes) [lswx,lswi,stswx,stswi]: Deprecate
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on E500 and E500MC.
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2010-08-17 22:37:26 +02:00
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2010-08-17 H.J. Lu <hongjiu.lu@intel.com>
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* i386-dis.c (reg_table): Replace Eb with Mb on prefetch and
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prefetchw.
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2010-08-06 20:22:50 +02:00
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2010-08-06 Quentin Neill <quentin.neill@amd.com>
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* i386-gen.c (cpu_flag_init): Define CpuNop extension flag, add
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to processor flags for PENTIUMPRO processors and later.
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* i386-opc.h (enum): Add CpuNop.
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(i386_cpu_flags): Add cpunop bit.
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* i386-opc.tbl: Change nop cpu_flags.
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* i386-init.h: Regenerated.
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* i386-tbl.h: Likewise.
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2010-08-06 18:33:43 +02:00
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2010-08-06 Quentin Neill <quentin.neill@amd.com>
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* i386-opc.h (enum): Fix typos in comments.
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2010-08-06 05:59:49 +02:00
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2010-08-06 Alan Modra <amodra@gmail.com>
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* disassemble.c: Formatting.
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(disassemble_init_for_target <ARCH_m32c>): Comment on endian.
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2010-08-06 03:03:17 +02:00
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2010-08-05 H.J. Lu <hongjiu.lu@intel.com>
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* i386-opc.tbl: Add Cpu186 to ud1/ud2/ud2a/ud2b.
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* i386-tbl.h: Regenerated.
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2010-08-06 02:52:57 +02:00
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2010-08-05 H.J. Lu <hongjiu.lu@intel.com>
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* i386-dis.c (dis386_twobyte): Replace ud2a/ud2b with ud2/ud1.
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* i386-opc.tbl: Add ud1. Remove Cpu686 from ud2/ud2a/ud2b.
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* i386-tbl.h: Regenerated.
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[include/opcode]
* rx.h (RX_Operand_Type): Add TwoReg.
(RX_Opcode_ID): Remove ediv and ediv2.
[opcodes]
* rx-decode.opc (SRR): New.
(rx_decode_opcode): Use it for movbi and movbir. Decode NOP2 (mov
r0,r0) and NOP3 (max r0,r0) special cases.
* rx-decode.c: Regenerate.
[sim/rx]
* rx.c (decode_cache_base): New.
(id_names): Remove ediv and edivu.
(optype_names): Add TwoReg.
(maybe_get_mem_page): New.
(rx_get_byte): Call it.
(get_op): Add TwoReg support.
(put_op): Likewise.
(PD, PS, PS2, GD, GS, GS2, DSZ, SSZ, S2SZ, US1, US2, OM): "opcode"
is a pointer now.
(DO_RETURN): New. We use longjmp to return an exception result.
(decode_opcode): Make opcode a pointer to the decode cache. Save
decoded opcode information and re-use. Call DO_RETURN instead of
return throughout. Remove ediv and edivu.
* mem.c (ptdc): New. Adds decode cache.
(rx_mem_ptr): Support it.
(rx_mem_decode_cache): New.
* mem.h (enum mem_ptr_action): add MPA_DECODE_CACHE.
(rx_mem_decode_cache): Declare.
* gdb-if.c (sim_resume): Add decode_opcode's setjmp logic here...
* main.c (main): ...and here. Use a fast loop if neither trace
nor disassemble is given.
* cpu.h (RX_MAKE_STEPPED, RX_MAKE_HIT_BREAK, RX_MAKE_EXITED,
RX_MAKE_STOPPED, RX_EXITED, RX_STOPPED): Adjust so that 0 is not a
valid code for anything.
2010-07-29 20:41:28 +02:00
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|
2010-07-29 DJ Delorie <dj@redhat.com>
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* rx-decode.opc (SRR): New.
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|
(rx_decode_opcode): Use it for movbi and movbir. Decode NOP2 (mov
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|
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r0,r0) and NOP3 (max r0,r0) special cases.
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|
* rx-decode.c: Regenerate.
|
2010-08-06 05:59:49 +02:00
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|
2010-07-28 23:54:34 +02:00
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|
2010-07-28 H.J. Lu <hongjiu.lu@intel.com>
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|
* i386-dis.c: Add 0F to VEX opcode enums.
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|
2010-07-28 02:36:46 +02:00
|
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|
|
2010-07-27 DJ Delorie <dj@redhat.com>
|
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|
|
* rx-decode.opc (store_flags): Remove, replace with F_* macros.
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|
(rx_decode_opcode): Likewise.
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|
|
* rx-decode.c: Regenerate.
|
|
|
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|
|
|
2010-07-23 16:52:54 +02:00
|
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|
|
2010-07-23 Naveen.H.S <naveen.S@kpitcummins.com>
|
|
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|
|
|
Ina Pandit <ina.pandit@kpitcummins.com>
|
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|
|
* v850-dis.c (v850_sreg_names): Updated structure for system
|
|
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|
|
registers.
|
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|
|
(float_cc_names): new structure for condition codes.
|
|
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|
|
(print_value): Update the function that prints value.
|
|
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|
|
(get_operand_value): New function to get the operand value.
|
|
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|
|
(disassemble): Updated to handle the disassembly of instructions.
|
|
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|
|
(print_insn_v850): Updated function to print instruction for different
|
|
|
|
|
|
families.
|
|
|
|
|
|
* opcodes/v850-opc.c (v850_msg_is_out_of_range, insert_i5div1,
|
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|
|
|
extract_i5div1, insert_i5div2, extract_i5div2, insert_i5div3,
|
|
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|
|
extract_i5div3, insert_d5_4, extract_d5_4, extract_d8_6,
|
|
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|
|
insert_d8_7, extract_d8_7, insert_v8, extract_v8, insert_u16_loop,
|
|
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|
|
extract_u16_loop, insert_d16_15, extract_d16_15, insert_d16_16,
|
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|
|
extract_d16_16, nsert_d17_16, extract_d17_16, insert_d22,
|
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|
extract_d22, insert_d23, extract_d23, insert_i9, extract_i9,
|
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|
|
insert_u9, extract_u9, extract_spe, insert_r4, extract_r4): New.
|
|
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|
|
(insert_d8_7, insert_d5_4, insert_i5div): Remove.
|
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|
|
(v850_operands): Update with the relocation name. Also update
|
|
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|
|
the instructions with specific set of processors.
|
|
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|
|
2010-07-09 00:40:28 +02:00
|
|
|
|
2010-07-08 Tejas Belagod <tejas.belagod@arm.com>
|
|
|
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|
|
|
|
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|
|
* arm-dis.c (print_insn_arm): Add cases for printing more
|
|
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symbolic operands.
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(print_insn_thumb32): Likewise.
|
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2010-07-06 02:06:04 +02:00
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2010-07-06 Maciej W. Rozycki <macro@codesourcery.com>
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* mips-dis.c (print_insn_mips): Correct branch instruction type
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determination.
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2010-07-06 02:02:46 +02:00
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2010-07-06 Maciej W. Rozycki <macro@codesourcery.com>
|
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* mips-dis.c (print_mips16_insn_arg): Remove branch instruction
|
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type and delay slot determination.
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(print_insn_mips16): Extend branch instruction type and delay
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slot determination to cover all instructions.
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* mips16-opc.c (BR): Remove macro.
|
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|
(UBR, CBR): New macros.
|
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|
(mips16_opcodes): Update branch annotation for "b", "beqz",
|
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|
"bnez", "bteqz" and "btnez". Add branch annotation for "jalrc"
|
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and "jrc".
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2010-07-05 19:14:22 +02:00
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2010-07-05 H.J. Lu <hongjiu.lu@intel.com>
|
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|
AVX Programming Reference (June, 2010)
|
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* i386-dis.c (mod_table): Replace rdrnd with rdrand.
|
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* i386-opc.tbl: Likewise.
|
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* i386-tbl.h: Regenerated.
|
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2010-07-05 18:40:32 +02:00
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2010-07-05 H.J. Lu <hongjiu.lu@intel.com>
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* i386-opc.h (CpuFSGSBase): Fix a typo in comments.
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2010-07-03 10:27:23 +02:00
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2010-07-03 Andreas Schwab <schwab@linux-m68k.org>
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* ppc-dis.c (powerpc_init_dialect): Cast PPC_OPCODE_xxx to
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ppc_cpu_t before inverting.
|
2010-07-03 10:29:51 +02:00
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(ppc_parse_cpu): Likewise.
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(print_insn_powerpc): Likewise.
|
2010-07-03 10:27:23 +02:00
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2010-07-03 08:51:56 +02:00
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2010-07-03 Alan Modra <amodra@gmail.com>
|
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* ppc-dis.c (ppc_opts, powerpc_init_dialect): Remove old opcode flags.
|
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|
* ppc-opc.c (PPC32, POWER32, COM32, CLASSIC): Delete.
|
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(PPC64, MFDEC2): Update.
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(NON32, NO371): Define.
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(powerpc_opcode): Update to not use old opcode flags, and avoid
|
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-m601 duplicates.
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2010-07-03 06:09:56 +02:00
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2010-07-03 DJ Delorie <dj@delorie.com>
|
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* m32c-ibld.c: Regenerate.
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2010-07-03 05:33:17 +02:00
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2010-07-03 Alan Modra <amodra@gmail.com>
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* ppc-opc.c (PWR2COM): Define.
|
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(PPCPWR2): Add PPC_OPCODE_COMMON.
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(powerpc_opcodes): Add "subc", "subco", "subco.", "fcir", "fcir.",
|
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"fcirz", "fcirz." to -mcom opcodes. Remove "mfsri", "dclst",
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"rac" from -mcom.
|
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|
Support AVX Programming Reference (June, 2010)
gas/
2010-07-01 H.J. Lu <hongjiu.lu@intel.com>
AVX Programming Reference (June, 2010)
* config/tc-i386.c (cpu_arch): Add .xsaveopt, .fsgsbase, .rdrnd
and .f16c.
* doc/c-i386.texi: Document xsaveopt, fsgsbase, rdrnd and f16c.
gas/testsuite/
2010-07-01 H.J. Lu <hongjiu.lu@intel.com>
AVX Programming Reference (June, 2010)
* gas/i386/arch-10.s: Add xsaveopt.
* gas/i386/x86-64-arch-2.s: Likwise.
* gas/i386/arch-10.d: Updated.
* gas/i386/arch-10-1.l: Likewise.
* gas/i386/arch-10-2.l: Likewise.
* gas/i386/arch-10-3.l: Likewise.
* gas/i386/arch-10-4.l: Likewise.
* gas/i386/x86-64-arch-2.d: Likewise.
* gas/i386/f16c-intel.d: New.
* gas/i386/f16c.d: Likewise.
* gas/i386/f16c.s: Likewise.
* gas/i386/fsgs-intel.d: Likewise.
* gas/i386/fsgs.d: Likewise.
* gas/i386/fsgs.s: Likewise.
* gas/i386/rdrnd-intel.d: Likewise.
* gas/i386/rdrnd.d: Likewise.
* gas/i386/rdrnd.s: Likewise.
* gas/i386/x86-64-f16c-intel.d: Likewise.
* gas/i386/x86-64-f16c.d: Likewise.
* gas/i386/x86-64-f16c.s: Likewise.
* gas/i386/x86-64-fsgs-intel.d: Likewise.
* gas/i386/x86-64-fsgs.d: Likewise.
* gas/i386/x86-64-fsgs.s: Likewise.
* gas/i386/x86-64-rdrnd-intel.d: Likewise.
* gas/i386/x86-64-rdrnd.d: Likewise.
* gas/i386/x86-64-rdrnd.s: Likewise.
* gas/i386/i386.exp: Run f16c, f16c-intel, fsgs, fsgs-intel,
rdrnd, rdrnd-intel, x86-64-f16c, x86-64-f16c-intel, x86-64-fsgs,
x86-64-fsgs-intel, x86-64-rdrnd, x86-64-rdrnd-intel.
* gas/i386/x86-64-xsave.s: Add tests for xsaveopt64.
* gas/i386/x86-64-xsave-intel.d: Updated.
* gas/i386/x86-64-xsave.d: Likewise.
opcodes/
2010-07-01 H.J. Lu <hongjiu.lu@intel.com>
AVX Programming Reference (June, 2010)
* i386-dis.c (PREFIX_0FAE_REG_0): New.
(PREFIX_0FAE_REG_1): Likewise.
(PREFIX_0FAE_REG_2): Likewise.
(PREFIX_0FAE_REG_3): Likewise.
(PREFIX_VEX_3813): Likewise.
(PREFIX_VEX_3A1D): Likewise.
(prefix_table): Add PREFIX_0FAE_REG_0, PREFIX_0FAE_REG_1,
PREFIX_0FAE_REG_2, PREFIX_0FAE_REG_3, PREFIX_VEX_3813 and
PREFIX_VEX_3A1D.
(vex_table): Add PREFIX_VEX_3813 and PREFIX_VEX_3A1D.
(mod_table): Add PREFIX_0FAE_REG_0, PREFIX_0FAE_REG_1,
PREFIX_0FAE_REG_2, PREFIX_0FAE_REG_3 xsaveopt and rdrnd.
* i386-gen.c (cpu_flag_init): Add CPU_XSAVEOPT_FLAGS,
CPU_FSGSBASE_FLAGS, CPU_RDRND_FLAGS and CPU_F16C_FLAGS.
(cpu_flags): Add CpuXsaveopt, CpuFSGSBase, CpuRdRnd and CpuF16C.
* i386-opc.h (CpuXsaveopt): New.
(CpuFSGSBase):Likewise.
(CpuRdRnd): Likewise.
(CpuF16C): Likewise.
(i386_cpu_flags): Add cpuxsaveopt, cpufsgsbase, cpurdrnd and
cpuf16c.
* i386-opc.tbl: Add xsaveopt, rdfsbase, rdgsbase, rdrnd,
wrfsbase, wrgsbase, vcvtph2ps and vcvtps2ph.
2010-07-01 23:55:02 +02:00
|
|
|
|
2010-07-01 H.J. Lu <hongjiu.lu@intel.com>
|
|
|
|
|
|
|
|
|
|
|
|
AVX Programming Reference (June, 2010)
|
|
|
|
|
|
* i386-dis.c (PREFIX_0FAE_REG_0): New.
|
|
|
|
|
|
(PREFIX_0FAE_REG_1): Likewise.
|
|
|
|
|
|
(PREFIX_0FAE_REG_2): Likewise.
|
|
|
|
|
|
(PREFIX_0FAE_REG_3): Likewise.
|
|
|
|
|
|
(PREFIX_VEX_3813): Likewise.
|
|
|
|
|
|
(PREFIX_VEX_3A1D): Likewise.
|
|
|
|
|
|
(prefix_table): Add PREFIX_0FAE_REG_0, PREFIX_0FAE_REG_1,
|
|
|
|
|
|
PREFIX_0FAE_REG_2, PREFIX_0FAE_REG_3, PREFIX_VEX_3813 and
|
|
|
|
|
|
PREFIX_VEX_3A1D.
|
|
|
|
|
|
(vex_table): Add PREFIX_VEX_3813 and PREFIX_VEX_3A1D.
|
|
|
|
|
|
(mod_table): Add PREFIX_0FAE_REG_0, PREFIX_0FAE_REG_1,
|
|
|
|
|
|
PREFIX_0FAE_REG_2, PREFIX_0FAE_REG_3 xsaveopt and rdrnd.
|
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|
|
|
|
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|
|
* i386-gen.c (cpu_flag_init): Add CPU_XSAVEOPT_FLAGS,
|
|
|
|
|
|
CPU_FSGSBASE_FLAGS, CPU_RDRND_FLAGS and CPU_F16C_FLAGS.
|
|
|
|
|
|
(cpu_flags): Add CpuXsaveopt, CpuFSGSBase, CpuRdRnd and CpuF16C.
|
|
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|
|
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|
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|
|
* i386-opc.h (CpuXsaveopt): New.
|
2010-07-05 18:40:32 +02:00
|
|
|
|
(CpuFSGSBase): Likewise.
|
Support AVX Programming Reference (June, 2010)
gas/
2010-07-01 H.J. Lu <hongjiu.lu@intel.com>
AVX Programming Reference (June, 2010)
* config/tc-i386.c (cpu_arch): Add .xsaveopt, .fsgsbase, .rdrnd
and .f16c.
* doc/c-i386.texi: Document xsaveopt, fsgsbase, rdrnd and f16c.
gas/testsuite/
2010-07-01 H.J. Lu <hongjiu.lu@intel.com>
AVX Programming Reference (June, 2010)
* gas/i386/arch-10.s: Add xsaveopt.
* gas/i386/x86-64-arch-2.s: Likwise.
* gas/i386/arch-10.d: Updated.
* gas/i386/arch-10-1.l: Likewise.
* gas/i386/arch-10-2.l: Likewise.
* gas/i386/arch-10-3.l: Likewise.
* gas/i386/arch-10-4.l: Likewise.
* gas/i386/x86-64-arch-2.d: Likewise.
* gas/i386/f16c-intel.d: New.
* gas/i386/f16c.d: Likewise.
* gas/i386/f16c.s: Likewise.
* gas/i386/fsgs-intel.d: Likewise.
* gas/i386/fsgs.d: Likewise.
* gas/i386/fsgs.s: Likewise.
* gas/i386/rdrnd-intel.d: Likewise.
* gas/i386/rdrnd.d: Likewise.
* gas/i386/rdrnd.s: Likewise.
* gas/i386/x86-64-f16c-intel.d: Likewise.
* gas/i386/x86-64-f16c.d: Likewise.
* gas/i386/x86-64-f16c.s: Likewise.
* gas/i386/x86-64-fsgs-intel.d: Likewise.
* gas/i386/x86-64-fsgs.d: Likewise.
* gas/i386/x86-64-fsgs.s: Likewise.
* gas/i386/x86-64-rdrnd-intel.d: Likewise.
* gas/i386/x86-64-rdrnd.d: Likewise.
* gas/i386/x86-64-rdrnd.s: Likewise.
* gas/i386/i386.exp: Run f16c, f16c-intel, fsgs, fsgs-intel,
rdrnd, rdrnd-intel, x86-64-f16c, x86-64-f16c-intel, x86-64-fsgs,
x86-64-fsgs-intel, x86-64-rdrnd, x86-64-rdrnd-intel.
* gas/i386/x86-64-xsave.s: Add tests for xsaveopt64.
* gas/i386/x86-64-xsave-intel.d: Updated.
* gas/i386/x86-64-xsave.d: Likewise.
opcodes/
2010-07-01 H.J. Lu <hongjiu.lu@intel.com>
AVX Programming Reference (June, 2010)
* i386-dis.c (PREFIX_0FAE_REG_0): New.
(PREFIX_0FAE_REG_1): Likewise.
(PREFIX_0FAE_REG_2): Likewise.
(PREFIX_0FAE_REG_3): Likewise.
(PREFIX_VEX_3813): Likewise.
(PREFIX_VEX_3A1D): Likewise.
(prefix_table): Add PREFIX_0FAE_REG_0, PREFIX_0FAE_REG_1,
PREFIX_0FAE_REG_2, PREFIX_0FAE_REG_3, PREFIX_VEX_3813 and
PREFIX_VEX_3A1D.
(vex_table): Add PREFIX_VEX_3813 and PREFIX_VEX_3A1D.
(mod_table): Add PREFIX_0FAE_REG_0, PREFIX_0FAE_REG_1,
PREFIX_0FAE_REG_2, PREFIX_0FAE_REG_3 xsaveopt and rdrnd.
* i386-gen.c (cpu_flag_init): Add CPU_XSAVEOPT_FLAGS,
CPU_FSGSBASE_FLAGS, CPU_RDRND_FLAGS and CPU_F16C_FLAGS.
(cpu_flags): Add CpuXsaveopt, CpuFSGSBase, CpuRdRnd and CpuF16C.
* i386-opc.h (CpuXsaveopt): New.
(CpuFSGSBase):Likewise.
(CpuRdRnd): Likewise.
(CpuF16C): Likewise.
(i386_cpu_flags): Add cpuxsaveopt, cpufsgsbase, cpurdrnd and
cpuf16c.
* i386-opc.tbl: Add xsaveopt, rdfsbase, rdgsbase, rdrnd,
wrfsbase, wrgsbase, vcvtph2ps and vcvtps2ph.
2010-07-01 23:55:02 +02:00
|
|
|
|
(CpuRdRnd): Likewise.
|
|
|
|
|
|
(CpuF16C): Likewise.
|
|
|
|
|
|
(i386_cpu_flags): Add cpuxsaveopt, cpufsgsbase, cpurdrnd and
|
|
|
|
|
|
cpuf16c.
|
|
|
|
|
|
|
|
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|
|
* i386-opc.tbl: Add xsaveopt, rdfsbase, rdgsbase, rdrnd,
|
|
|
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|
|
wrfsbase, wrgsbase, vcvtph2ps and vcvtps2ph.
|
2010-07-01 23:57:04 +02:00
|
|
|
|
* i386-init.h: Regenerated.
|
|
|
|
|
|
* i386-tbl.h: Likewise.
|
Support AVX Programming Reference (June, 2010)
gas/
2010-07-01 H.J. Lu <hongjiu.lu@intel.com>
AVX Programming Reference (June, 2010)
* config/tc-i386.c (cpu_arch): Add .xsaveopt, .fsgsbase, .rdrnd
and .f16c.
* doc/c-i386.texi: Document xsaveopt, fsgsbase, rdrnd and f16c.
gas/testsuite/
2010-07-01 H.J. Lu <hongjiu.lu@intel.com>
AVX Programming Reference (June, 2010)
* gas/i386/arch-10.s: Add xsaveopt.
* gas/i386/x86-64-arch-2.s: Likwise.
* gas/i386/arch-10.d: Updated.
* gas/i386/arch-10-1.l: Likewise.
* gas/i386/arch-10-2.l: Likewise.
* gas/i386/arch-10-3.l: Likewise.
* gas/i386/arch-10-4.l: Likewise.
* gas/i386/x86-64-arch-2.d: Likewise.
* gas/i386/f16c-intel.d: New.
* gas/i386/f16c.d: Likewise.
* gas/i386/f16c.s: Likewise.
* gas/i386/fsgs-intel.d: Likewise.
* gas/i386/fsgs.d: Likewise.
* gas/i386/fsgs.s: Likewise.
* gas/i386/rdrnd-intel.d: Likewise.
* gas/i386/rdrnd.d: Likewise.
* gas/i386/rdrnd.s: Likewise.
* gas/i386/x86-64-f16c-intel.d: Likewise.
* gas/i386/x86-64-f16c.d: Likewise.
* gas/i386/x86-64-f16c.s: Likewise.
* gas/i386/x86-64-fsgs-intel.d: Likewise.
* gas/i386/x86-64-fsgs.d: Likewise.
* gas/i386/x86-64-fsgs.s: Likewise.
* gas/i386/x86-64-rdrnd-intel.d: Likewise.
* gas/i386/x86-64-rdrnd.d: Likewise.
* gas/i386/x86-64-rdrnd.s: Likewise.
* gas/i386/i386.exp: Run f16c, f16c-intel, fsgs, fsgs-intel,
rdrnd, rdrnd-intel, x86-64-f16c, x86-64-f16c-intel, x86-64-fsgs,
x86-64-fsgs-intel, x86-64-rdrnd, x86-64-rdrnd-intel.
* gas/i386/x86-64-xsave.s: Add tests for xsaveopt64.
* gas/i386/x86-64-xsave-intel.d: Updated.
* gas/i386/x86-64-xsave.d: Likewise.
opcodes/
2010-07-01 H.J. Lu <hongjiu.lu@intel.com>
AVX Programming Reference (June, 2010)
* i386-dis.c (PREFIX_0FAE_REG_0): New.
(PREFIX_0FAE_REG_1): Likewise.
(PREFIX_0FAE_REG_2): Likewise.
(PREFIX_0FAE_REG_3): Likewise.
(PREFIX_VEX_3813): Likewise.
(PREFIX_VEX_3A1D): Likewise.
(prefix_table): Add PREFIX_0FAE_REG_0, PREFIX_0FAE_REG_1,
PREFIX_0FAE_REG_2, PREFIX_0FAE_REG_3, PREFIX_VEX_3813 and
PREFIX_VEX_3A1D.
(vex_table): Add PREFIX_VEX_3813 and PREFIX_VEX_3A1D.
(mod_table): Add PREFIX_0FAE_REG_0, PREFIX_0FAE_REG_1,
PREFIX_0FAE_REG_2, PREFIX_0FAE_REG_3 xsaveopt and rdrnd.
* i386-gen.c (cpu_flag_init): Add CPU_XSAVEOPT_FLAGS,
CPU_FSGSBASE_FLAGS, CPU_RDRND_FLAGS and CPU_F16C_FLAGS.
(cpu_flags): Add CpuXsaveopt, CpuFSGSBase, CpuRdRnd and CpuF16C.
* i386-opc.h (CpuXsaveopt): New.
(CpuFSGSBase):Likewise.
(CpuRdRnd): Likewise.
(CpuF16C): Likewise.
(i386_cpu_flags): Add cpuxsaveopt, cpufsgsbase, cpurdrnd and
cpuf16c.
* i386-opc.tbl: Add xsaveopt, rdfsbase, rdgsbase, rdrnd,
wrfsbase, wrgsbase, vcvtph2ps and vcvtps2ph.
2010-07-01 23:55:02 +02:00
|
|
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|
|
2010-07-01 04:29:12 +02:00
|
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|
|
2010-07-01 Sebastian Andrzej Siewior <bigeasy@linutronix.de>
|
|
|
|
|
|
|
|
|
|
|
|
* ppc-opc.c (powerpc_opcodes): Revert deprecation of mfocrf, mtcrf
|
|
|
|
|
|
and mtocrf on EFS.
|
|
|
|
|
|
|
2010-06-29 06:17:34 +02:00
|
|
|
|
2010-06-29 Alan Modra <amodra@gmail.com>
|
|
|
|
|
|
|
|
|
|
|
|
* maxq-dis.c: Delete file.
|
|
|
|
|
|
* Makefile.am: Remove references to maxq.
|
|
|
|
|
|
* configure.in: Likewise.
|
|
|
|
|
|
* disassemble.c: Likewise.
|
|
|
|
|
|
* Makefile.in: Regenerate.
|
|
|
|
|
|
* configure: Regenerate.
|
|
|
|
|
|
* po/POTFILES.in: Regenerate.
|
|
|
|
|
|
|
2010-06-28 16:41:59 +02:00
|
|
|
|
2010-06-29 Alan Modra <amodra@gmail.com>
|
|
|
|
|
|
|
|
|
|
|
|
* mep-dis.c: Regenerate.
|
|
|
|
|
|
|
2010-06-28 11:10:25 +02:00
|
|
|
|
2010-06-28 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
|
|
|
|
|
|
|
|
|
|
|
|
* arm-disc.c (parse_insn_neon): Fix Neon alignment syntax.
|
|
|
|
|
|
|
2010-06-27 06:07:55 +02:00
|
|
|
|
2010-06-27 Alan Modra <amodra@gmail.com>
|
|
|
|
|
|
|
|
|
|
|
|
* arc-dis.c (arc_sprintf): Delete set but unused variables.
|
|
|
|
|
|
(decodeInstr): Likewise.
|
|
|
|
|
|
* dlx-dis.c (print_insn_dlx): Likewise.
|
|
|
|
|
|
* h8300-dis.c (bfd_h8_disassemble_init): Likewise.
|
|
|
|
|
|
* maxq-dis.c (check_move, print_insn): Likewise.
|
|
|
|
|
|
* mep-dis.c (mep_examine_ivc2_insns): Likewise.
|
|
|
|
|
|
* msp430-dis.c (msp430_branchinstr): Likewise.
|
|
|
|
|
|
* bfin-dis.c (_print_insn_bfin): Avoid set but unused warning.
|
|
|
|
|
|
* cgen-asm.in (parse_insn_normal, _cgen_assemble_insn): Likewise.
|
|
|
|
|
|
* sparc-dis.c (print_insn_sparc): Likewise.
|
|
|
|
|
|
* fr30-asm.c: Regenerate.
|
|
|
|
|
|
* frv-asm.c: Regenerate.
|
|
|
|
|
|
* ip2k-asm.c: Regenerate.
|
|
|
|
|
|
* iq2000-asm.c: Regenerate.
|
|
|
|
|
|
* lm32-asm.c: Regenerate.
|
|
|
|
|
|
* m32c-asm.c: Regenerate.
|
|
|
|
|
|
* m32r-asm.c: Regenerate.
|
|
|
|
|
|
* mep-asm.c: Regenerate.
|
|
|
|
|
|
* mt-asm.c: Regenerate.
|
|
|
|
|
|
* openrisc-asm.c: Regenerate.
|
|
|
|
|
|
* xc16x-asm.c: Regenerate.
|
|
|
|
|
|
* xstormy16-asm.c: Regenerate.
|
|
|
|
|
|
|
2010-06-16 18:27:37 +02:00
|
|
|
|
2010-06-16 Vincent Rivière <vincent.riviere@freesbee.fr>
|
|
|
|
|
|
|
|
|
|
|
|
PR gas/11673
|
|
|
|
|
|
* m68k-opc.c (m68k_opcodes): Remove move.l for isab and later.
|
|
|
|
|
|
|
2010-06-16 17:12:51 +02:00
|
|
|
|
2010-06-16 Vincent Rivière <vincent.riviere@freesbee.fr>
|
|
|
|
|
|
|
|
|
|
|
|
PR binutils/11676
|
|
|
|
|
|
* m68k-dis.c (print_insn_arg): Prefix float constants with #0e.
|
|
|
|
|
|
|
2010-06-14 16:48:05 +02:00
|
|
|
|
2010-06-14 Sebastian Andrzej Siewior <bigeasy@linutronix.de>
|
|
|
|
|
|
|
|
|
|
|
|
* ppc-dis.c (ppc_opts): Remove PPC_OPCODE_E500MC from e500 and
|
|
|
|
|
|
e500x2. Add PPC_OPCODE_E500 to e500 and e500x2
|
|
|
|
|
|
* ppc-opc.c (powerpc_opcodes): Deprecate all opcodes on EFS which
|
|
|
|
|
|
touch floating point regs and are enabled by COM, PPC or PPCCOM.
|
|
|
|
|
|
Treat sync as msync on e500. Treat eieio as mbar 1 on e500.
|
|
|
|
|
|
Treat lwsync as msync on e500.
|
|
|
|
|
|
|
2010-06-07 12:43:52 +02:00
|
|
|
|
2010-06-07 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
|
|
|
|
|
|
|
|
|
|
|
|
* arm-dis.c (thumb-opcodes): Add disassembly for movs.
|
|
|
|
|
|
|
2010-05-28 18:04:21 +02:00
|
|
|
|
2010-05-28 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
|
|
|
|
|
|
|
2010-06-14 16:48:05 +02:00
|
|
|
|
* arm-dis.c (print_insn_neon): Ensure disassembly of Neon
|
2010-05-28 18:04:21 +02:00
|
|
|
|
constants is the same on 32-bit and 64-bit hosts.
|
|
|
|
|
|
|
2010-05-27 12:45:52 +02:00
|
|
|
|
2010-05-27 Jason Duerstock <jason.duerstock+binutils@gmail.com>
|
2010-05-27 12:43:27 +02:00
|
|
|
|
|
|
|
|
|
|
* m68k-dis.c (print_insn_m68k): Emit undefined instructions as
|
|
|
|
|
|
.short directives so that they can be reassembled.
|
|
|
|
|
|
|
2010-05-26 23:49:30 +02:00
|
|
|
|
2010-05-26 Catherine Moore <clm@codesourcery.com>
|
|
|
|
|
|
David Ung <davidu@mips.com>
|
|
|
|
|
|
|
|
|
|
|
|
* mips-opc.c: Change membership to I1 for instructions ssnop and
|
|
|
|
|
|
ehb.
|
|
|
|
|
|
|
2010-05-26 18:08:23 +02:00
|
|
|
|
2010-05-26 H.J. Lu <hongjiu.lu@intel.com>
|
|
|
|
|
|
|
|
|
|
|
|
* i386-dis.c (sib): New.
|
|
|
|
|
|
(get_sib): Likewise.
|
|
|
|
|
|
(print_insn): Call get_sib.
|
|
|
|
|
|
OP_E_memory): Use sib.
|
|
|
|
|
|
|
2010-05-26 14:59:56 +02:00
|
|
|
|
2010-05-26 Catherine Moore <clm@codesoourcery.com>
|
|
|
|
|
|
|
|
|
|
|
|
* mips-dis.c (mips_arch): Remove INSN_MIPS16.
|
|
|
|
|
|
* mips-opc.c (I16): Remove.
|
|
|
|
|
|
(mips_builtin_op): Reclassify jalx.
|
|
|
|
|
|
|
2010-05-19 05:44:36 +02:00
|
|
|
|
2010-05-19 Alan Modra <amodra@gmail.com>
|
|
|
|
|
|
|
|
|
|
|
|
* ppc-opc.c (powerpc_opcodes): Enable divdeu, devweu, divde,
|
|
|
|
|
|
divwe, divdeuo, divweuo, divdeo, divweo for A2. Add icswepx.
|
|
|
|
|
|
|
2010-05-13 08:30:09 +02:00
|
|
|
|
2010-05-13 Alan Modra <amodra@gmail.com>
|
|
|
|
|
|
|
|
|
|
|
|
* ppc-opc.c (powerpc_opcodes): Correct wclr encoding.
|
|
|
|
|
|
|
2010-05-11 19:36:33 +02:00
|
|
|
|
2010-05-11 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
|
|
|
|
|
|
|
|
|
|
|
|
* arm-dis.c (thumb_opcodes): Update ldmia entry to use new %W
|
|
|
|
|
|
format.
|
|
|
|
|
|
(print_insn_thumb16): Add support for new %W format.
|
|
|
|
|
|
|
2010-05-07 14:28:50 +02:00
|
|
|
|
2010-05-07 Tristan Gingold <gingold@adacore.com>
|
|
|
|
|
|
|
|
|
|
|
|
* Makefile.in: Regenerate with automake 1.11.1.
|
|
|
|
|
|
* aclocal.m4: Ditto.
|
|
|
|
|
|
|
2010-05-05 17:28:26 +02:00
|
|
|
|
2010-05-05 Nick Clifton <nickc@redhat.com>
|
|
|
|
|
|
|
|
|
|
|
|
* po/es.po: Updated Spanish translation.
|
|
|
|
|
|
|
2010-04-22 16:37:16 +02:00
|
|
|
|
2010-04-22 Nick Clifton <nickc@redhat.com>
|
|
|
|
|
|
|
|
|
|
|
|
* po/opcodes.pot: Updated by the Translation project.
|
|
|
|
|
|
* po/vi.po: Updated Vietnamese translation.
|
|
|
|
|
|
|
2010-04-16 23:35:24 +02:00
|
|
|
|
2010-04-16 H.J. Lu <hongjiu.lu@intel.com>
|
|
|
|
|
|
|
|
|
|
|
|
* i386-dis.c (get_valid_dis386): Return bad_opcode on unknown
|
|
|
|
|
|
bits in opcode.
|
|
|
|
|
|
|
2010-04-09 16:40:18 +02:00
|
|
|
|
2010-04-09 Nick Clifton <nickc@redhat.com>
|
|
|
|
|
|
|
|
|
|
|
|
* i386-dis.c (print_insn): Remove unused variable op.
|
|
|
|
|
|
(OP_sI): Remove unused variable mask.
|
|
|
|
|
|
|
2010-04-07 09:20:51 +02:00
|
|
|
|
2010-04-07 Alan Modra <amodra@gmail.com>
|
|
|
|
|
|
|
|
|
|
|
|
* configure: Regenerate.
|
|
|
|
|
|
|
2010-04-06 18:04:34 +02:00
|
|
|
|
2010-04-06 Peter Bergner <bergner@vnet.ibm.com>
|
|
|
|
|
|
|
|
|
|
|
|
* ppc-opc.c (RBOPT): New define.
|
|
|
|
|
|
("dccci"): Enable for PPCA2. Make operands optional.
|
|
|
|
|
|
("iccci"): Likewise. Do not deprecate for PPC476.
|
|
|
|
|
|
|
2010-04-06 17:41:43 +02:00
|
|
|
|
2010-04-02 Masaki Muranaka <monaka@monami-software.com>
|
|
|
|
|
|
|
|
|
|
|
|
* cr16-opc.c (cr16_instruction): Fix typo in comment.
|
|
|
|
|
|
|
bfd:
* Makefile.am (ALL_MACHINES): Add cpu-tic6x.lo.
(ALL_MACHINES_CFILES): Add cpu-tic6x.c.
(BFD32_BACKENDS): Add elf32-tic6x.lo.
(BFD32_BACKENDS_CFILES): Add elf32-tic6x.c.
* Makefile.in: Regenerate.
* archures.c (bfd_arch_tic6x, bfd_tic6x_arch): New.
(bfd_archures_list): Update.
* config.bfd (tic6x-*-elf): New.
* configure.in (bfd_elf32_tic6x_be_vec, bfd_elf32_tic6x_le_vec):
New.
* configure: Regenerate.
* cpu-tic6x.c, elf32-tic6x.c: New.
* reloc.c (BFD_RELOC_C6000_PCR_S21, BFD_RELOC_C6000_PCR_S12,
BFD_RELOC_C6000_PCR_S10, BFD_RELOC_C6000_PCR_S7,
BFD_RELOC_C6000_ABS_S16, BFD_RELOC_C6000_ABS_L16,
BFD_RELOC_C6000_ABS_H16, BFD_RELOC_C6000_SBR_U15_B,
BFD_RELOC_C6000_SBR_U15_H, BFD_RELOC_C6000_SBR_U15_W,
BFD_RELOC_C6000_SBR_S16, BFD_RELOC_C6000_SBR_L16_B,
BFD_RELOC_C6000_SBR_L16_H, BFD_RELOC_C6000_SBR_L16_W,
BFD_RELOC_C6000_SBR_H16_B, BFD_RELOC_C6000_SBR_H16_H,
BFD_RELOC_C6000_SBR_H16_W, BFD_RELOC_C6000_SBR_GOT_U15_W,
BFD_RELOC_C6000_SBR_GOT_L16_W, BFD_RELOC_C6000_SBR_GOT_H16_W,
BFD_RELOC_C6000_DSBT_INDEX, BFD_RELOC_C6000_PREL31,
BFD_RELOC_C6000_COPY, BFD_RELOC_C6000_ALIGN,
BFD_RELOC_C6000_FPHEAD, BFD_RELOC_C6000_NOCMP): New.
* targets.c (bfd_elf32_tic6x_be_vec, bfd_elf32_tic6x_le_vec): New.
(_bfd_target_vector): Update.
* bfd-in2.h, libbfd.h: Regenerate.
binutils:
* MAINTAINERS: Add self as TI C6X maintainer.
* NEWS: Add news entry for TI C6X support.
* readelf.c: Include elf/tic6x.h.
(guess_is_rela): Handle EM_TI_C6000.
(dump_relocations): Likewise.
(get_tic6x_dynamic_type): New.
(get_dynamic_type): Call it.
(get_machine_flags): Handle EF_C6000_REL.
(get_osabi_name): Handle machine-specific values only for relevant
machines. Handle C6X values.
(get_tic6x_segment_type): New.
(get_segment_type): Call it.
(get_tic6x_section_type_name): New.
(get_section_type_name): Call it.
(is_32bit_abs_reloc, is_16bit_abs_reloc, is_none_reloc): Handle
EM_TI_C6000.
gas:
* Makefile.am (TARGET_CPU_CFILES): Add config/tc-tic6x.c.
(TARGET_CPU_HFILES): Add config/tc-tic6x.h.
* Makefile.in: Regenerate.
* NEWS: Add news entry for TI C6X support.
* app.c (do_scrub_chars): Handle "||^" for TI C6X. Handle
TC_PREDICATE_START_CHAR and TC_PREDICATE_END_CHAR. Keep spaces in
operands if TC_KEEP_OPERAND_SPACES.
* configure.tgt (tic6x-*-*): New.
* config/tc-ia64.h (TC_PREDICATE_START_CHAR,
TC_PREDICATE_END_CHAR): Define.
* config/tc-tic6x.c, config/tc-tic6x.h: New.
* doc/Makefile.am (CPU_DOCS): Add c-tic6x.texi.
* doc/Makefile.in: Regenerate.
* doc/all.texi (TIC6X): Define.
* doc/as.texinfo: Add TI C6X documentation. Include c-tic6x.texi.
* doc/c-tic6x.texi: New.
gas/testsuite:
* gas/tic6x: New directory and testcases.
include:
* dis-asm.h (print_insn_tic6x): Declare.
include/elf:
* common.h (ELFOSABI_C6000_ELFABI, ELFOSABI_C6000_LINUX): Define.
* tic6x.h: New.
include/opcode:
* tic6x-control-registers.h, tic6x-insn-formats.h,
tic6x-opcode-table.h, tic6x.h: New.
ld:
* Makefile.am (ALL_EMULATIONS): Add eelf32_tic6x_be.o and
eelf32_tic6x_le.o.
(eelf32_tic6x_be.c, eelf32_tic6x_le.c): New.
* NEWS: Add news entry for TI C6X support.
* configure.tgt (tic6x-*-*): New.
* emulparams/elf32_tic6x_be.sh, emulparams/elf32_tic6x_le.sh: New.
ld/testsuite:
* ld-elf/flags1.d, ld-elf/merge.d: XFAIL for tic6x-*-*.
* ld-elf/sec-to-seg.exp: Set B_test_same_seg to 0 for tic6x-*-*.
* ld-tic6x: New directory and testcases.
opcodes:
* Makefile.am (TARGET_LIBOPCODES_CFILES): Add tic6x-dis.c.
* Makefile.in: Regenerate.
* configure.in (bfd_tic6x_arch): New.
* configure: Regenerate.
* disassemble.c (ARCH_tic6x): Define if ARCH_all.
(disassembler): Handle TI C6X.
* tic6x-dis.c: New.
2010-03-25 22:12:36 +01:00
|
|
|
|
2010-03-25 Joseph Myers <joseph@codesourcery.com>
|
|
|
|
|
|
|
|
|
|
|
|
* Makefile.am (TARGET_LIBOPCODES_CFILES): Add tic6x-dis.c.
|
|
|
|
|
|
* Makefile.in: Regenerate.
|
|
|
|
|
|
* configure.in (bfd_tic6x_arch): New.
|
|
|
|
|
|
* configure: Regenerate.
|
|
|
|
|
|
* disassemble.c (ARCH_tic6x): Define if ARCH_all.
|
|
|
|
|
|
(disassembler): Handle TI C6X.
|
|
|
|
|
|
* tic6x-dis.c: New.
|
|
|
|
|
|
|
2010-03-24 06:16:29 +01:00
|
|
|
|
2010-03-24 Mike Frysinger <vapier@gentoo.org>
|
|
|
|
|
|
|
|
|
|
|
|
* bfin-dis.c (decode_regs_hi): Change REG_LH2 typo to REG_MH2.
|
|
|
|
|
|
|
2010-03-23 16:59:45 +01:00
|
|
|
|
2010-03-23 Joseph Myers <joseph@codesourcery.com>
|
|
|
|
|
|
|
|
|
|
|
|
* dis-buf.c (buffer_read_memory): Give error for reading just
|
|
|
|
|
|
before the start of memory.
|
|
|
|
|
|
|
2010-03-23 03:56:24 +01:00
|
|
|
|
2010-03-22 Sebastian Pop <sebastian.pop@amd.com>
|
|
|
|
|
|
Quentin Neill <quentin.neill@amd.com>
|
|
|
|
|
|
|
|
|
|
|
|
* i386-dis.c (OP_LWP_I): Removed.
|
|
|
|
|
|
(reg_table): Do not use OP_LWP_I, use Iq.
|
|
|
|
|
|
(OP_LWPCB_E): Remove use of names16.
|
|
|
|
|
|
(OP_LWP_E): Same.
|
|
|
|
|
|
* i386-opc.tbl: Removed 16bit LWP insns. 32bit LWP insns
|
|
|
|
|
|
should not set the Vex.length bit.
|
|
|
|
|
|
* i386-tbl.h: Regenerated.
|
|
|
|
|
|
|
2010-02-25 02:00:13 +01:00
|
|
|
|
2010-02-25 Edmar Wienskoski <edmar@freescale.com>
|
|
|
|
|
|
|
|
|
|
|
|
* ppc-dis.c (ppc_opts): Add PPC_OPCODE_E500MC for "e500mc64".
|
|
|
|
|
|
|
2010-02-24 16:11:44 +01:00
|
|
|
|
2010-02-24 Nick Clifton <nickc@redhat.com>
|
|
|
|
|
|
|
|
|
|
|
|
PR binutils/6773
|
|
|
|
|
|
* arm-dis.c (arm_opcodes): Replace <prefix>addsubx with
|
|
|
|
|
|
<prefix>asx. Replace <prefix>subaddx with <prefix>sax.
|
|
|
|
|
|
(thumb32_opcodes): Likewise.
|
|
|
|
|
|
|
2010-02-15 11:09:39 +01:00
|
|
|
|
2010-02-15 Nick Clifton <nickc@redhat.com>
|
|
|
|
|
|
|
|
|
|
|
|
* po/vi.po: Updated Vietnamese translation.
|
|
|
|
|
|
|
2010-02-13 05:38:57 +01:00
|
|
|
|
2010-02-12 Doug Evans <dje@sebabeach.org>
|
|
|
|
|
|
|
|
|
|
|
|
* lm32-opinst.c: Regenerate.
|
|
|
|
|
|
|
* fr30-desc.c, * fr30-desc.h, * fr30-opc.c,
* frv-desc.c, * frv-desc.h, * frv-opc.c,
* ip2k-desc.c, * ip2k-desc.h, * ip2k-opc.c,
* iq2000-desc.c, * iq2000-desc.h, * iq2000-opc.c,
* lm32-desc.c, * lm32-desc.h, * lm32-opc.c, * lm32-opinst.c,
* m32c-desc.c, * m32c-desc.h, * m32c-opc.c,
* m32r-desc.c, * m32r-desc.h, * m32r-opc.c, * m32r-opinst.c,
* mep-desc.c, * mep-desc.h, * mep-opc.c,
* mt-desc.c, * mt-desc.h, * mt-opc.c,
* openrisc-desc.c, * openrisc-desc.h, * openrisc-opc.c,
* xc16x-desc.c, * xc16x-desc.h, * xc16x-opc.c,
* xstormy16-desc.c, * xstormy16-desc.h, * xstormy16-opc.c: Regenerate.
2010-02-12 04:25:49 +01:00
|
|
|
|
2010-02-11 Doug Evans <dje@sebabeach.org>
|
|
|
|
|
|
|
* cgen-dis.in (print_normal): Delete CGEN_PRINT_NORMAL.
(print_address): Delete CGEN_PRINT_ADDRESS.
* fr30-dis.c, * frv-dis.c, * ip2k-dis.c, * iq2000-dis.c,
* lm32-dis.c, * m32c-dis.c, * m32r-desc.c, * m32r-desc.h,
* m32r-dis.c, * mep-dis.c, * mt-dis.c, * openrisc-dis.c,
* xc16x-dis.c, * xstormy16-dis.c: Regenerate.
2010-02-12 05:42:28 +01:00
|
|
|
|
* cgen-dis.in (print_normal): Delete CGEN_PRINT_NORMAL.
|
|
|
|
|
|
(print_address): Delete CGEN_PRINT_ADDRESS.
|
|
|
|
|
|
* fr30-dis.c, * frv-dis.c, * ip2k-dis.c, * iq2000-dis.c,
|
|
|
|
|
|
* lm32-dis.c, * m32c-dis.c, * m32r-desc.c, * m32r-desc.h,
|
|
|
|
|
|
* m32r-dis.c, * mep-dis.c, * mt-dis.c, * openrisc-dis.c,
|
|
|
|
|
|
* xc16x-dis.c, * xstormy16-dis.c: Regenerate.
|
|
|
|
|
|
|
* fr30-desc.c, * fr30-desc.h, * fr30-opc.c,
* frv-desc.c, * frv-desc.h, * frv-opc.c,
* ip2k-desc.c, * ip2k-desc.h, * ip2k-opc.c,
* iq2000-desc.c, * iq2000-desc.h, * iq2000-opc.c,
* lm32-desc.c, * lm32-desc.h, * lm32-opc.c, * lm32-opinst.c,
* m32c-desc.c, * m32c-desc.h, * m32c-opc.c,
* m32r-desc.c, * m32r-desc.h, * m32r-opc.c, * m32r-opinst.c,
* mep-desc.c, * mep-desc.h, * mep-opc.c,
* mt-desc.c, * mt-desc.h, * mt-opc.c,
* openrisc-desc.c, * openrisc-desc.h, * openrisc-opc.c,
* xc16x-desc.c, * xc16x-desc.h, * xc16x-opc.c,
* xstormy16-desc.c, * xstormy16-desc.h, * xstormy16-opc.c: Regenerate.
2010-02-12 04:25:49 +01:00
|
|
|
|
* fr30-desc.c, * fr30-desc.h, * fr30-opc.c,
|
|
|
|
|
|
* frv-desc.c, * frv-desc.h, * frv-opc.c,
|
|
|
|
|
|
* ip2k-desc.c, * ip2k-desc.h, * ip2k-opc.c,
|
|
|
|
|
|
* iq2000-desc.c, * iq2000-desc.h, * iq2000-opc.c,
|
|
|
|
|
|
* lm32-desc.c, * lm32-desc.h, * lm32-opc.c, * lm32-opinst.c,
|
|
|
|
|
|
* m32c-desc.c, * m32c-desc.h, * m32c-opc.c,
|
|
|
|
|
|
* m32r-desc.c, * m32r-desc.h, * m32r-opc.c, * m32r-opinst.c,
|
|
|
|
|
|
* mep-desc.c, * mep-desc.h, * mep-opc.c,
|
|
|
|
|
|
* mt-desc.c, * mt-desc.h, * mt-opc.c,
|
|
|
|
|
|
* openrisc-desc.c, * openrisc-desc.h, * openrisc-opc.c,
|
|
|
|
|
|
* xc16x-desc.c, * xc16x-desc.h, * xc16x-opc.c,
|
|
|
|
|
|
* xstormy16-desc.c, * xstormy16-desc.h, * xstormy16-opc.c: Regenerate.
|
|
|
|
|
|
|
2010-02-11 14:41:19 +01:00
|
|
|
|
2010-02-11 H.J. Lu <hongjiu.lu@intel.com>
|
|
|
|
|
|
|
|
|
|
|
|
* i386-dis.c: Update copyright.
|
|
|
|
|
|
* i386-gen.c: Likewise.
|
|
|
|
|
|
* i386-opc.h: Likewise.
|
|
|
|
|
|
* i386-opc.tbl: Likewise.
|
|
|
|
|
|
|
2010-02-11 06:06:14 +01:00
|
|
|
|
2010-02-10 Quentin Neill <quentin.neill@amd.com>
|
|
|
|
|
|
Sebastian Pop <sebastian.pop@amd.com>
|
|
|
|
|
|
|
|
|
|
|
|
* i386-dis.c (OP_EX_VexImmW): Reintroduced
|
|
|
|
|
|
function to handle 5th imm8 operand.
|
|
|
|
|
|
(PREFIX_VEX_3A48): Added.
|
|
|
|
|
|
(PREFIX_VEX_3A49): Added.
|
|
|
|
|
|
(VEX_W_3A48_P_2): Added.
|
|
|
|
|
|
(VEX_W_3A49_P_2): Added.
|
|
|
|
|
|
(prefix table): Added entries for PREFIX_VEX_3A48
|
|
|
|
|
|
and PREFIX_VEX_3A49.
|
|
|
|
|
|
(vex table): Added entries for VEX_W_3A48_P_2 and
|
|
|
|
|
|
and VEX_W_3A49_P_2.
|
|
|
|
|
|
* i386-gen.c (operand_type_init): Added OPERAND_TYPE_VEC_IMM4
|
|
|
|
|
|
for Vec_Imm4 operands.
|
|
|
|
|
|
* i386-opc.h (enum): Added Vec_Imm4.
|
|
|
|
|
|
(i386_operand_type): Added vec_imm4.
|
|
|
|
|
|
* i386-opc.tbl: Add entries for vpermilp[ds].
|
|
|
|
|
|
* i386-init.h: Regenerated.
|
|
|
|
|
|
* i386-tbl.h: Regenerated.
|
|
|
|
|
|
|
2010-02-10 20:59:07 +01:00
|
|
|
|
2010-02-10 Richard Sandiford <r.sandiford@uk.ibm.com>
|
|
|
|
|
|
|
|
|
|
|
|
* ppc-dis.c (ppc_opts): Add "pwr4", "pwr5", "pwr5x", "pwr6"
|
|
|
|
|
|
and "pwr7". Move "a2" into alphabetical order.
|
|
|
|
|
|
|
2010-02-08 02:59:38 +01:00
|
|
|
|
2010-02-08 Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
|
|
|
|
|
|
|
|
|
|
|
|
* ppc-dis.c (ppc_opts): Add titan entry.
|
|
|
|
|
|
* ppc-opc.c (TITAN, MULHW): Define.
|
|
|
|
|
|
(powerpc_opcodes): Support AppliedMicro Titan core (APM83xxx).
|
|
|
|
|
|
|
2010-02-03 21:36:14 +01:00
|
|
|
|
2010-02-03 Quentin Neill <quentin.neill@amd.com>
|
|
|
|
|
|
|
|
|
|
|
|
* i386-gen.c (cpu_flag_init): Rename CPU_AMDFAM15_FLAGS
|
|
|
|
|
|
to CPU_BDVER1_FLAGS
|
|
|
|
|
|
* i386-init.h: Regenerated.
|
|
|
|
|
|
|
2010-02-03 13:47:06 +01:00
|
|
|
|
2010-02-03 Anthony Green <green@moxielogic.com>
|
|
|
|
|
|
|
|
|
|
|
|
* moxie-opc.c (moxie_form1_opc_info): Move "nop" from 0x00 to
|
|
|
|
|
|
0x0f, and make 0x00 an illegal instruction.
|
|
|
|
|
|
|
2010-01-29 17:47:55 +01:00
|
|
|
|
2010-01-29 Daniel Jacobowitz <dan@codesourcery.com>
|
|
|
|
|
|
|
|
|
|
|
|
* opcodes/arm-dis.c (struct arm_private_data): New.
|
|
|
|
|
|
(print_insn_coprocessor, print_insn_arm): Update to use struct
|
|
|
|
|
|
arm_private_data.
|
|
|
|
|
|
(is_mapping_symbol, get_map_sym_type): New functions.
|
|
|
|
|
|
(get_sym_code_type): Check the symbol's section. Do not check
|
|
|
|
|
|
mapping symbols.
|
|
|
|
|
|
(print_insn): Default to disassembling ARM mode code. Check
|
|
|
|
|
|
for mapping symbols separately from other symbols. Use
|
|
|
|
|
|
struct arm_private_data.
|
|
|
|
|
|
|
Allow VL=1 on scalar FMA instructions.
gas/testsuite/
2010-01-28 H.J. Lu <hongjiu.lu@intel.com>
* gas/i386/fma-scalar-intel.d: New.
* gas/i386/fma-scalar.d: Likewise.
* gas/i386/fma-scalar.s: Likewise.
* gas/i386/x86-64-fma-scalar-intel.d: Likewise.
* gas/i386/x86-64-fma-scalar.d: Likewise.
* gas/i386/x86-64-fma-scalar.s: Likewise.
* gas/i386/i386.exp: Run fma-scalar, fma-scalar-intel,
x86-64-fma-scalar and x86-64-fma-scalar-intel.
opcodes/
2010-01-28 H.J. Lu <hongjiu.lu@intel.com>
* i386-dis.c (EXVexWdqScalar): New.
(vex_scalar_w_dq_mode): Likewise.
(prefix_table): Update entries for PREFIX_VEX_3899,
PREFIX_VEX_389B, PREFIX_VEX_389D, PREFIX_VEX_389F,
PREFIX_VEX_38A9, PREFIX_VEX_38AB, PREFIX_VEX_38AD,
PREFIX_VEX_38AF, PREFIX_VEX_38B9, PREFIX_VEX_38BB,
PREFIX_VEX_38BD and PREFIX_VEX_38BF.
(intel_operand_size): Handle vex_scalar_w_dq_mode.
(OP_EX): Likewise.
2010-01-28 16:33:23 +01:00
|
|
|
|
2010-01-28 H.J. Lu <hongjiu.lu@intel.com>
|
|
|
|
|
|
|
|
|
|
|
|
* i386-dis.c (EXVexWdqScalar): New.
|
|
|
|
|
|
(vex_scalar_w_dq_mode): Likewise.
|
|
|
|
|
|
(prefix_table): Update entries for PREFIX_VEX_3899,
|
|
|
|
|
|
PREFIX_VEX_389B, PREFIX_VEX_389D, PREFIX_VEX_389F,
|
|
|
|
|
|
PREFIX_VEX_38A9, PREFIX_VEX_38AB, PREFIX_VEX_38AD,
|
|
|
|
|
|
PREFIX_VEX_38AF, PREFIX_VEX_38B9, PREFIX_VEX_38BB,
|
|
|
|
|
|
PREFIX_VEX_38BD and PREFIX_VEX_38BF.
|
|
|
|
|
|
(intel_operand_size): Handle vex_scalar_w_dq_mode.
|
|
|
|
|
|
(OP_EX): Likewise.
|
|
|
|
|
|
|
Allow VL=1 on AVX scalar instructions.
gas/
2010-01-27 H.J. Lu <hongjiu.lu@intel.com>
* config/tc-i386.c (avxscalar): New.
(OPTION_MAVXSCALAR): Likewise.
(build_vex_prefix): Select vector_length for scalar instructions
based on avxscalar.
(md_longopts): Add OPTION_MAVXSCALAR.
(md_parse_option): Handle OPTION_MAVXSCALAR.
(md_show_usage): Add -mavxscalar=.
* doc/c-i386.texi: Document -mavxscalar=.
gas/testsuite/
2010-01-27 H.J. Lu <hongjiu.lu@intel.com>
* gas/i386/avx-scalar-intel.d: New.
* gas/i386/avx-scalar.d: Likewise.
* gas/i386/avx-scalar.s: Likewise.
* gas/i386/x86-64-avx-scalar-intel.d: Likewise.
* gas/i386/x86-64-avx-scalar.d: Likewise.
* gas/i386/x86-64-avx-scalar.s: Likewise.
* gas/i386/i386.exp: Run avx-scalar, avx-scalar-intel,
x86-64-avx-scalar and x86-64-avx-scalar-intel.
opcodes/
2010-01-27 H.J. Lu <hongjiu.lu@intel.com>
* i386-dis.c (XMScalar): New.
(EXdScalar): Likewise.
(EXqScalar): Likewise.
(EXqScalarS): Likewise.
(VexScalar): Likewise.
(EXdVexScalarS): Likewise.
(EXqVexScalarS): Likewise.
(XMVexScalar): Likewise.
(scalar_mode): Likewise.
(d_scalar_mode): Likewise.
(d_scalar_swap_mode): Likewise.
(q_scalar_mode): Likewise.
(q_scalar_swap_mode): Likewise.
(vex_scalar_mode): Likewise.
(vex_len_table): Duplcate entries for VEX_LEN_10_P_1,
VEX_LEN_10_P_3, VEX_LEN_11_P_1, VEX_LEN_11_P_3, VEX_LEN_2A_P_1,
VEX_LEN_2A_P_3, VEX_LEN_2C_P_3, VEX_LEN_2D_P_1, VEX_LEN_2E_P_0,
VEX_LEN_2E_P_2, VEX_LEN_2F_P_2, VEX_LEN_51_P_1, VEX_LEN_51_P_3,
VEX_LEN_52_P_1, VEX_LEN_53_P_1, VEX_LEN_58_P_1, VEX_LEN_58_P_3,
VEX_LEN_59_P_1, VEX_LEN_5A_P_1, VEX_LEN_5A_P_3, VEX_LEN_5C_P_1,
VEX_LEN_5C_P_3, VEX_LEN_5D_P_1, VEX_LEN_5D_P_3, VEX_LEN_5E_P_1,
VEX_LEN_5E_P_3, VEX_LEN_5F_P_1, VEX_LEN_5F_P_3, VEX_LEN_6E_P_2,
VEX_LEN_7E_P_1, VEX_LEN_7E_P_2, VEX_LEN_D6_P_2, VEX_LEN_C2_P_1,
VEX_LEN_C2_P_3, VEX_LEN_3A0A_P_2 and VEX_LEN_3A0B_P_2.
(vex_w_table): Update entries for VEX_W_10_P_1, VEX_W_10_P_3,
VEX_W_11_P_1, VEX_W_11_P_3, VEX_W_2E_P_0, VEX_W_2E_P_2,
VEX_W_2F_P_0, VEX_W_2F_P_2, VEX_W_51_P_1, VEX_W_51_P_3,
VEX_W_52_P_1, VEX_W_53_P_1, VEX_W_58_P_1, VEX_W_58_P_3,
VEX_W_59_P_1, VEX_W_59_P_3, VEX_W_5A_P_1, VEX_W_5A_P_3,
VEX_W_5C_P_1, VEX_W_5C_P_3, VEX_W_5D_P_1, VEX_W_5D_P_3,
VEX_W_5E_P_1, VEX_W_5E_P_3, VEX_W_5F_P_1, VEX_W_5F_P_3,
VEX_W_7E_P_1, VEX_W_D6_P_2 VEX_W_C2_P_1, VEX_W_C2_P_3,
VEX_W_3A0A_P_2 and VEX_W_3A0B_P_2.
(intel_operand_size): Handle d_scalar_mode, d_scalar_swap_mode,
q_scalar_mode, q_scalar_swap_mode.
(OP_XMM): Handle scalar_mode.
(OP_EX): Handle d_scalar_mode, d_scalar_swap_mode, q_scalar_mode
and q_scalar_swap_mode.
(OP_VEX): Handle vex_scalar_mode.
2010-01-27 15:34:40 +01:00
|
|
|
|
2010-01-27 H.J. Lu <hongjiu.lu@intel.com>
|
|
|
|
|
|
|
|
|
|
|
|
* i386-dis.c (XMScalar): New.
|
|
|
|
|
|
(EXdScalar): Likewise.
|
|
|
|
|
|
(EXqScalar): Likewise.
|
|
|
|
|
|
(EXqScalarS): Likewise.
|
|
|
|
|
|
(VexScalar): Likewise.
|
|
|
|
|
|
(EXdVexScalarS): Likewise.
|
|
|
|
|
|
(EXqVexScalarS): Likewise.
|
|
|
|
|
|
(XMVexScalar): Likewise.
|
|
|
|
|
|
(scalar_mode): Likewise.
|
|
|
|
|
|
(d_scalar_mode): Likewise.
|
|
|
|
|
|
(d_scalar_swap_mode): Likewise.
|
|
|
|
|
|
(q_scalar_mode): Likewise.
|
|
|
|
|
|
(q_scalar_swap_mode): Likewise.
|
|
|
|
|
|
(vex_scalar_mode): Likewise.
|
|
|
|
|
|
(vex_len_table): Duplcate entries for VEX_LEN_10_P_1,
|
|
|
|
|
|
VEX_LEN_10_P_3, VEX_LEN_11_P_1, VEX_LEN_11_P_3, VEX_LEN_2A_P_1,
|
|
|
|
|
|
VEX_LEN_2A_P_3, VEX_LEN_2C_P_3, VEX_LEN_2D_P_1, VEX_LEN_2E_P_0,
|
|
|
|
|
|
VEX_LEN_2E_P_2, VEX_LEN_2F_P_2, VEX_LEN_51_P_1, VEX_LEN_51_P_3,
|
|
|
|
|
|
VEX_LEN_52_P_1, VEX_LEN_53_P_1, VEX_LEN_58_P_1, VEX_LEN_58_P_3,
|
|
|
|
|
|
VEX_LEN_59_P_1, VEX_LEN_5A_P_1, VEX_LEN_5A_P_3, VEX_LEN_5C_P_1,
|
|
|
|
|
|
VEX_LEN_5C_P_3, VEX_LEN_5D_P_1, VEX_LEN_5D_P_3, VEX_LEN_5E_P_1,
|
|
|
|
|
|
VEX_LEN_5E_P_3, VEX_LEN_5F_P_1, VEX_LEN_5F_P_3, VEX_LEN_6E_P_2,
|
|
|
|
|
|
VEX_LEN_7E_P_1, VEX_LEN_7E_P_2, VEX_LEN_D6_P_2, VEX_LEN_C2_P_1,
|
|
|
|
|
|
VEX_LEN_C2_P_3, VEX_LEN_3A0A_P_2 and VEX_LEN_3A0B_P_2.
|
|
|
|
|
|
(vex_w_table): Update entries for VEX_W_10_P_1, VEX_W_10_P_3,
|
|
|
|
|
|
VEX_W_11_P_1, VEX_W_11_P_3, VEX_W_2E_P_0, VEX_W_2E_P_2,
|
|
|
|
|
|
VEX_W_2F_P_0, VEX_W_2F_P_2, VEX_W_51_P_1, VEX_W_51_P_3,
|
|
|
|
|
|
VEX_W_52_P_1, VEX_W_53_P_1, VEX_W_58_P_1, VEX_W_58_P_3,
|
|
|
|
|
|
VEX_W_59_P_1, VEX_W_59_P_3, VEX_W_5A_P_1, VEX_W_5A_P_3,
|
|
|
|
|
|
VEX_W_5C_P_1, VEX_W_5C_P_3, VEX_W_5D_P_1, VEX_W_5D_P_3,
|
|
|
|
|
|
VEX_W_5E_P_1, VEX_W_5E_P_3, VEX_W_5F_P_1, VEX_W_5F_P_3,
|
|
|
|
|
|
VEX_W_7E_P_1, VEX_W_D6_P_2 VEX_W_C2_P_1, VEX_W_C2_P_3,
|
|
|
|
|
|
VEX_W_3A0A_P_2 and VEX_W_3A0B_P_2.
|
|
|
|
|
|
(intel_operand_size): Handle d_scalar_mode, d_scalar_swap_mode,
|
|
|
|
|
|
q_scalar_mode, q_scalar_swap_mode.
|
|
|
|
|
|
(OP_XMM): Handle scalar_mode.
|
|
|
|
|
|
(OP_EX): Handle d_scalar_mode, d_scalar_swap_mode, q_scalar_mode
|
|
|
|
|
|
and q_scalar_swap_mode.
|
|
|
|
|
|
(OP_VEX): Handle vex_scalar_mode.
|
|
|
|
|
|
|
2010-01-25 00:22:43 +01:00
|
|
|
|
2010-01-24 H.J. Lu <hongjiu.lu@intel.com>
|
|
|
|
|
|
|
|
|
|
|
|
* i386-dis.c (prefix_table): Remove trailing { Bad_Opcode }.
|
|
|
|
|
|
|
2010-01-24 22:35:13 +01:00
|
|
|
|
2010-01-24 H.J. Lu <hongjiu.lu@intel.com>
|
|
|
|
|
|
|
|
|
|
|
|
* i386-dis.c (vex_len_table): Remove trailing { Bad_Opcode }.
|
|
|
|
|
|
|
2010-01-24 21:39:40 +01:00
|
|
|
|
2010-01-24 H.J. Lu <hongjiu.lu@intel.com>
|
|
|
|
|
|
|
|
|
|
|
|
* i386-dis.c (prefix_table): Remove trailing { Bad_Opcode }.
|
|
|
|
|
|
|
2010-01-24 19:24:23 +01:00
|
|
|
|
2010-01-24 H.J. Lu <hongjiu.lu@intel.com>
|
|
|
|
|
|
|
|
|
|
|
|
* i386-dis.c (Bad_Opcode): New.
|
|
|
|
|
|
(bad_opcode): Likewise.
|
|
|
|
|
|
(dis386): Replace { "(bad)", { XX } } with { Bad_Opcode }.
|
|
|
|
|
|
(dis386_twobyte): Likewise.
|
|
|
|
|
|
(reg_table): Likewise.
|
|
|
|
|
|
(prefix_table): Likewise.
|
|
|
|
|
|
(x86_64_table): Likewise.
|
|
|
|
|
|
(vex_len_table): Likewise.
|
|
|
|
|
|
(vex_w_table): Likewise.
|
|
|
|
|
|
(mod_table): Likewise.
|
|
|
|
|
|
(rm_table): Likewise.
|
|
|
|
|
|
(float_reg): Likewise.
|
|
|
|
|
|
(reg_table): Remove trailing "(bad)" entries.
|
|
|
|
|
|
(prefix_table): Likewise.
|
|
|
|
|
|
(x86_64_table): Likewise.
|
|
|
|
|
|
(vex_len_table): Likewise.
|
|
|
|
|
|
(vex_w_table): Likewise.
|
|
|
|
|
|
(mod_table): Likewise.
|
|
|
|
|
|
(rm_table): Likewise.
|
|
|
|
|
|
(get_valid_dis386): Handle bytemode 0.
|
|
|
|
|
|
|
2010-01-24 01:59:13 +01:00
|
|
|
|
2010-01-23 H.J. Lu <hongjiu.lu@intel.com>
|
|
|
|
|
|
|
|
|
|
|
|
* i386-opc.h (VEXScalar): New.
|
|
|
|
|
|
|
|
|
|
|
|
* i386-opc.tbl: Replace "Vex" with "Vex=3" on AVX scalar
|
|
|
|
|
|
instructions.
|
|
|
|
|
|
* i386-tbl.h: Regenerated.
|
|
|
|
|
|
|
2010-01-21 18:32:32 +01:00
|
|
|
|
2010-01-21 H.J. Lu <hongjiu.lu@intel.com>
|
2010-01-21 18:30:14 +01:00
|
|
|
|
|
|
|
|
|
|
* i386-dis.c (mod_table): Use FXSAVE on xsave and xrstor.
|
|
|
|
|
|
|
|
|
|
|
|
* i386-opc.tbl: Add xsave64 and xrstor64.
|
|
|
|
|
|
* i386-tbl.h: Regenerated.
|
|
|
|
|
|
|
2010-01-20 11:54:03 +01:00
|
|
|
|
2010-01-20 Nick Clifton <nickc@redhat.com>
|
|
|
|
|
|
|
|
|
|
|
|
PR 11170
|
|
|
|
|
|
* arm-dis.c (print_arm_address): Do not ignore negative bit in PC
|
|
|
|
|
|
based post-indexed addressing.
|
|
|
|
|
|
|
2010-01-15 22:24:13 +01:00
|
|
|
|
2010-01-15 Sebastian Pop <sebastian.pop@amd.com>
|
|
|
|
|
|
|
|
|
|
|
|
* i386-opc.tbl: Support all the possible aliases for VPCOM* insns.
|
|
|
|
|
|
* i386-tbl.h: Regenerated.
|
|
|
|
|
|
|
2010-01-14 20:35:36 +01:00
|
|
|
|
2010-01-14 H.J. Lu <hongjiu.lu@intel.com>
|
|
|
|
|
|
|
|
|
|
|
|
* i386-opc.h (VexVVVV): Replace VEX.DNS with VEX.NDS in
|
|
|
|
|
|
comments.
|
|
|
|
|
|
|
2010-01-14 18:29:18 +01:00
|
|
|
|
2010-01-14 H.J. Lu <hongjiu.lu@intel.com>
|
|
|
|
|
|
|
|
|
|
|
|
* i386-dis.c (names_mm): New.
|
|
|
|
|
|
(intel_names_mm): Likewise.
|
|
|
|
|
|
(att_names_mm): Likewise.
|
|
|
|
|
|
(names_xmm): Likewise.
|
|
|
|
|
|
(intel_names_xmm): Likewise.
|
|
|
|
|
|
(att_names_xmm): Likewise.
|
|
|
|
|
|
(names_ymm): Likewise.
|
|
|
|
|
|
(intel_names_ymm): Likewise.
|
|
|
|
|
|
(att_names_ymm): Likewise.
|
|
|
|
|
|
(print_insn): Set names_mm, names_xmm and names_ymm.
|
|
|
|
|
|
(OP_MMX): Use names_mm, names_xmm and names_ymm.
|
|
|
|
|
|
(OP_XMM): Likewise.
|
|
|
|
|
|
(OP_EM): Likewise.
|
|
|
|
|
|
(OP_EMC): Likewise.
|
|
|
|
|
|
(OP_MXC): Likewise.
|
|
|
|
|
|
(OP_EX): Likewise.
|
|
|
|
|
|
(XMM_Fixup): Likewise.
|
|
|
|
|
|
(OP_VEX): Likewise.
|
|
|
|
|
|
(OP_EX_VexReg): Likewise.
|
|
|
|
|
|
(OP_Vex_2src): Likewise.
|
|
|
|
|
|
(OP_Vex_2src_1): Likewise.
|
|
|
|
|
|
(OP_Vex_2src_2): Likewise.
|
|
|
|
|
|
(OP_REG_VexI4): Likewise.
|
|
|
|
|
|
|
2010-01-13 17:06:12 +01:00
|
|
|
|
2010-01-13 H.J. Lu <hongjiu.lu@intel.com>
|
|
|
|
|
|
|
|
|
|
|
|
* i386-dis.c (print_insn): Update comments.
|
|
|
|
|
|
|
2010-01-13 05:03:20 +01:00
|
|
|
|
2010-01-12 H.J. Lu <hongjiu.lu@intel.com>
|
|
|
|
|
|
|
|
|
|
|
|
* i386-dis.c (rex_original): Removed.
|
|
|
|
|
|
(ckprefix): Remove rex_original.
|
|
|
|
|
|
(print_insn): Update comments.
|
|
|
|
|
|
|
2010-01-09 22:11:44 +01:00
|
|
|
|
2010-01-09 Ralf Wildenhues <Ralf.Wildenhues@gmx.de>
|
|
|
|
|
|
|
|
|
|
|
|
* Makefile.in: Regenerate.
|
|
|
|
|
|
* configure: Regenerate.
|
|
|
|
|
|
|
* cgen-ibld.in (insert_normal, extract_normal): Minor cleanup.
* fr30-ibld.c, * frv-ibld.c, * ip2k-ibld.c, * iq2000-ibld.c,
* lm32-ibld.c, * m32c-ibld.c, * m32r-ibld.c, * mep-ibld.c,
* mt-ibld.c, * openrisc-ibld.c, * xc16x-ibld.c,
* xstormy16-ibld.c: Regenerate.
2010-01-07 19:05:45 +01:00
|
|
|
|
2010-01-07 Doug Evans <dje@sebabeach.org>
|
|
|
|
|
|
|
|
|
|
|
|
* cgen-ibld.in (insert_normal, extract_normal): Minor cleanup.
|
|
|
|
|
|
* fr30-ibld.c, * frv-ibld.c, * ip2k-ibld.c, * iq2000-ibld.c,
|
|
|
|
|
|
* lm32-ibld.c, * m32c-ibld.c, * m32r-ibld.c, * mep-ibld.c,
|
|
|
|
|
|
* mt-ibld.c, * openrisc-ibld.c, * xc16x-ibld.c,
|
|
|
|
|
|
* xstormy16-ibld.c: Regenerate.
|
|
|
|
|
|
|
2010-01-06 23:52:47 +01:00
|
|
|
|
2010-01-06 Quentin Neill <quentin.neill@amd.com>
|
|
|
|
|
|
|
|
|
|
|
|
* i386-gen.c (cpu_flag_init): Add new CPU_AMDFAM15_FLAGS.
|
|
|
|
|
|
* i386-init.h: Regenerated.
|
|
|
|
|
|
|
2010-01-06 16:02:45 +01:00
|
|
|
|
2010-01-06 Daniel Gutson <dgutson@codesourcery.com>
|
|
|
|
|
|
|
|
|
|
|
|
* arm-dis.c (print_insn): Fixed search for next symbol and data
|
|
|
|
|
|
dumping condition, and the initial mapping symbol state.
|
|
|
|
|
|
|
cpu/
* m32c.cpu (f-dsp-32-u24): Fix mode of extract handler.
(f-dsp-40-u20, f-dsp-40-u24): Ditto.
opcodes/
* cgen-ibld.in: #include "cgen/basic-modes.h".
* fr30-ibld.c, * frv-ibld.c, * ip2k-ibld.c, * iq2000-ibld.c,
* lm32-ibld.c, * m32c-ibld.c, * m32r-ibld.c, * mep-ibld.c,
* mt-ibld.c, * openrisc-ibld.c, * xc16x-ibld.c,
* xstormy16-ibld.c: Regenerate.
2010-01-06 06:30:19 +01:00
|
|
|
|
2010-01-05 Doug Evans <dje@sebabeach.org>
|
|
|
|
|
|
|
|
|
|
|
|
* cgen-ibld.in: #include "cgen/basic-modes.h".
|
|
|
|
|
|
* fr30-ibld.c, * frv-ibld.c, * ip2k-ibld.c, * iq2000-ibld.c,
|
|
|
|
|
|
* lm32-ibld.c, * m32c-ibld.c, * m32r-ibld.c, * mep-ibld.c,
|
|
|
|
|
|
* mt-ibld.c, * openrisc-ibld.c, * xc16x-ibld.c,
|
|
|
|
|
|
* xstormy16-ibld.c: Regenerate.
|
|
|
|
|
|
|
2010-01-04 11:18:32 +01:00
|
|
|
|
2010-01-04 Nick Clifton <nickc@redhat.com>
|
|
|
|
|
|
|
|
|
|
|
|
PR 11123
|
|
|
|
|
|
* arm-dis.c (print_insn_coprocessor): Initialise value.
|
|
|
|
|
|
|
2010-01-04 03:32:56 +01:00
|
|
|
|
2010-01-04 Edmar Wienskoski <edmar@freescale.com>
|
|
|
|
|
|
|
|
|
|
|
|
* ppc-dis.c (ppc_opts): Add entry for "e500mc64".
|
|
|
|
|
|
|
* cgen-asm.in: Update copyright year.
* cgen-dis.in: Update copyright year.
* cgen-ibld.in: Update copyright year.
* fr30-asm.c, * fr30-desc.c, * fr30-desc.h, * fr30-dis.c,
* fr30-ibld.c, * fr30-opc.c, * fr30-opc.h, * frv-asm.c, * frv-desc.c,
* frv-desc.h, * frv-dis.c, * frv-ibld.c, * frv-opc.c, * frv-opc.h,
* ip2k-asm.c, * ip2k-desc.c, * ip2k-desc.h, * ip2k-dis.c,
* ip2k-ibld.c, * ip2k-opc.c, * ip2k-opc.h, * iq2000-asm.c,
* iq2000-desc.c, * iq2000-desc.h, * iq2000-dis.c, * iq2000-ibld.c,
* iq2000-opc.c, * iq2000-opc.h, * lm32-asm.c, * lm32-desc.c,
* lm32-desc.h, * lm32-dis.c, * lm32-ibld.c, * lm32-opc.c, * lm32-opc.h,
* lm32-opinst.c, * m32c-asm.c, * m32c-desc.c, * m32c-desc.h,
* m32c-dis.c, * m32c-ibld.c, * m32c-opc.c, * m32c-opc.h, * m32r-asm.c,
* m32r-desc.c, * m32r-desc.h, * m32r-dis.c, * m32r-ibld.c,
* m32r-opc.c, * m32r-opc.h, * m32r-opinst.c, * mep-asm.c, * mep-desc.c,
* mep-desc.h, * mep-dis.c, * mep-ibld.c, * mep-opc.c, * mep-opc.h,
* mt-asm.c, * mt-desc.c, * mt-desc.h, * mt-dis.c, * mt-ibld.c,
* mt-opc.c, * mt-opc.h, * openrisc-asm.c, * openrisc-desc.c,
* openrisc-desc.h, * openrisc-dis.c, * openrisc-ibld.c,
* openrisc-opc.c, * openrisc-opc.h, * xc16x-asm.c, * xc16x-desc.c,
* xc16x-desc.h, * xc16x-dis.c, * xc16x-ibld.c, * xc16x-opc.c,
* xc16x-opc.h, * xstormy16-asm.c, * xstormy16-desc.c,
* xstormy16-desc.h, * xstormy16-dis.c, * xstormy16-ibld.c,
* xstormy16-opc.c, * xstormy16-opc.h: Regenerate.
2010-01-02 19:50:59 +01:00
|
|
|
|
2010-01-02 Doug Evans <dje@sebabeach.org>
|
|
|
|
|
|
|
|
|
|
|
|
* cgen-asm.in: Update copyright year.
|
|
|
|
|
|
* cgen-dis.in: Update copyright year.
|
|
|
|
|
|
* cgen-ibld.in: Update copyright year.
|
|
|
|
|
|
* fr30-asm.c, * fr30-desc.c, * fr30-desc.h, * fr30-dis.c,
|
|
|
|
|
|
* fr30-ibld.c, * fr30-opc.c, * fr30-opc.h, * frv-asm.c, * frv-desc.c,
|
|
|
|
|
|
* frv-desc.h, * frv-dis.c, * frv-ibld.c, * frv-opc.c, * frv-opc.h,
|
|
|
|
|
|
* ip2k-asm.c, * ip2k-desc.c, * ip2k-desc.h, * ip2k-dis.c,
|
|
|
|
|
|
* ip2k-ibld.c, * ip2k-opc.c, * ip2k-opc.h, * iq2000-asm.c,
|
|
|
|
|
|
* iq2000-desc.c, * iq2000-desc.h, * iq2000-dis.c, * iq2000-ibld.c,
|
|
|
|
|
|
* iq2000-opc.c, * iq2000-opc.h, * lm32-asm.c, * lm32-desc.c,
|
|
|
|
|
|
* lm32-desc.h, * lm32-dis.c, * lm32-ibld.c, * lm32-opc.c, * lm32-opc.h,
|
|
|
|
|
|
* lm32-opinst.c, * m32c-asm.c, * m32c-desc.c, * m32c-desc.h,
|
|
|
|
|
|
* m32c-dis.c, * m32c-ibld.c, * m32c-opc.c, * m32c-opc.h, * m32r-asm.c,
|
|
|
|
|
|
* m32r-desc.c, * m32r-desc.h, * m32r-dis.c, * m32r-ibld.c,
|
|
|
|
|
|
* m32r-opc.c, * m32r-opc.h, * m32r-opinst.c, * mep-asm.c, * mep-desc.c,
|
|
|
|
|
|
* mep-desc.h, * mep-dis.c, * mep-ibld.c, * mep-opc.c, * mep-opc.h,
|
|
|
|
|
|
* mt-asm.c, * mt-desc.c, * mt-desc.h, * mt-dis.c, * mt-ibld.c,
|
|
|
|
|
|
* mt-opc.c, * mt-opc.h, * openrisc-asm.c, * openrisc-desc.c,
|
|
|
|
|
|
* openrisc-desc.h, * openrisc-dis.c, * openrisc-ibld.c,
|
|
|
|
|
|
* openrisc-opc.c, * openrisc-opc.h, * xc16x-asm.c, * xc16x-desc.c,
|
|
|
|
|
|
* xc16x-desc.h, * xc16x-dis.c, * xc16x-ibld.c, * xc16x-opc.c,
|
|
|
|
|
|
* xc16x-opc.h, * xstormy16-asm.c, * xstormy16-desc.c,
|
|
|
|
|
|
* xstormy16-desc.h, * xstormy16-dis.c, * xstormy16-ibld.c,
|
|
|
|
|
|
* xstormy16-opc.c, * xstormy16-opc.h: Regenerate.
|
2009-12-19 19:36:27 +01:00
|
|
|
|
|
2010-01-01 19:06:10 +01:00
|
|
|
|
For older changes see ChangeLog-2009
|
1999-05-03 09:29:11 +02:00
|
|
|
|
|
|
|
|
|
|
Local Variables:
|
2001-01-11 20:01:42 +01:00
|
|
|
|
mode: change-log
|
|
|
|
|
|
left-margin: 8
|
|
|
|
|
|
fill-column: 74
|
1999-05-03 09:29:11 +02:00
|
|
|
|
version-control: never
|
|
|
|
|
|
End:
|