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1153 Commits

Author SHA1 Message Date
H.J. Lu
eec0f4ca4c 2006-11-09 H.J. Lu <hongjiu.lu@intel.com> 
* i386-dis.c (twobyte_uses_SSE_prefix): Renamed to ...
	(twobyte_uses_DATA_prefix): This.
	(twobyte_uses_REPNZ_prefix): New.
	(twobyte_uses_REPZ_prefix): Likewise.
	(threebyte_0x38_uses_DATA_prefix): Likewise.
	(threebyte_0x38_uses_REPNZ_prefix): Likewise.
	(threebyte_0x38_uses_REPZ_prefix): Likewise.
	(threebyte_0x3a_uses_DATA_prefix): Likewise.
	(threebyte_0x3a_uses_REPNZ_prefix): Likewise.
	(threebyte_0x3a_uses_REPZ_prefix): Likewise.
	(print_insn): Updated checking usages of DATA/REPNZ/REPZ
	prefixes.
 2006-11-10 02:13:40 +00:00
Alan Modra
a9353e608e * ppc-opc.c: Restore COM to mfcr wrongly removed 2003-07-04. 2006-11-06 00:46:07 +00:00
Nick Clifton
06d2da930d * tc-score.c (do16_rdrs): Handle not! instruction especially. 
* score-opc.h (score_opcodes): Delete modifier '0x'.
* gas/score/rD_rA.d: Correct not! and not.c instruction disassembly.
* gas/score/b.d: Correct b! and b instruction disassembly.
 2006-11-01 10:29:49 +00:00
Paul Brook
2087ad8497 2006-10-30 Paul Brook <paul@codesourcery.com> 
binutils/
	* objdump.c (disassemble_section): Set info->symtab_pos.
	(disassemble_data): Set info->symtab and info->symtab_size.

	include/
	* dis-asm.h (disassemble_info): Add symtab, symtab_pos and
	symtab_size.

	opcodes/
	* arm-dis.c (last_is_thumb, last_mapping_sym, last_mapping_addr): New.
	(get_sym_code_type): New function.
	(print_insn): Search for mapping symbols.
 2006-10-31 20:21:57 +00:00
Nick Clifton
b138abaa40 * tc-score.c (data_op2): Check invalid operands. 
(my_get_expression): Const operand of some instructions can not be symbol in assembly.
  (get_insn_class_from_type): Handle instruction type Insn_internal.
  (do_macro_ldst_label): Modify inst.type.
  (Insn_PIC): Delete.
* score-inst.h (enum score_insn_type): Add Insn_internal.
* tc-score.c (data_op2): The immediate value in lw is 15 bit signed.
* score-dis.c (print_insn): Correct the error code to print correct PCE instruction disassembly.
 2006-10-31 09:54:41 +00:00
Peter Bergner
702f0fb48f 2006-10-26 Ben Elliston <bje@au.ibm.com> 
Anton Blanchard  <anton@samba.org>
	    Peter Bergner  <bergner@vnet.ibm.com>

	* ppc-opc.c (A_L, DCM, DGM, TE, RMC, R, SP, S, SH16, XRT_L, EH,
	AFRALFRC_MASK, Z, ZRC, Z_MASK, XLRT_MASK, XEH_MASK): Define.
	(POWER6): Define.
	(powerpc_opcodes): Extend "lwarx", "ldarx", "dcbf", "fres", "fres.",
	"frsqrtes", "frsqrtes." "fre", "fre.", "frsqrte" and "frsqrte.".
	Add "doze", "nap", "sleep", "rvwinkle", "dcbfl", "prtyw", "prtyd",
	"mfcfar", "cmpb", "lfdpx", "stfdpx", "mtcfar", "mffgpr", "mftgpr",
	"lwzcix", "lhzcix", "lbzcix", "ldcix", "lfiwax", "stwcix", "sthcix",
	"stbcix", "stdcix", "lfdp", "dadd", "dadd.", "dqua", "dqua.", "dmul",
	"dmul.", "drrnd", "drrnd.", "dscli", "dscli.", "dquai", "dquai.",
	"dscri", "dscri.", "drintx", "drintx.", "dcmpo", "dtstex", "dtstdc",
	"dtstdg", "dtstsf", "drintn", "drintn.", "dctdp", "dctdp.", "dctfix",
	"dctfix.", "ddedpd", "ddedpd.", "dxex", "dxex.", "dsub", "dsub.",
	"ddiv", "ddiv.", "dcmpu", "drsp", "drsp.", "dcffix", "dcffix.",
	"denbcd", "denbcd.", "diex", "diex.", "stfdp", "daddq", "daddq.",
	"dquaq", "dquaq.", "fcpsgn", "fcpsgn.", "dmulq", "dmulq.",
	"drrndq", "drrndq.", "dscliq", "dscliq.", "dquaiq", "dquaiq.",
	"dscriq", "dscriq.", "drintxq", "drintxq.", "dcmpoq", "dtstexq",
	"dtstdcq", "dtstdgq", "dtstsfq", "drintnq", "drintnq.",
	"dctqpq", "dctqpq.", "dctfixq", "dctfixq.", "ddedpdq", "ddedpdq.",
	"dxexq", "dxexq.", "dsubq", "dsubq.", "ddivq", "ddivq.", "dcmpuq",
	"drdpq", "drdpq.", "dcffixq", "dcffixq.", "denbcdq", "denbcdq.",
	"diexq" and "diexq." opcodes.
 2006-10-26 17:37:26 +00:00
Daniel Jacobowitz
a3202ebb06 * h8300-dis.c (bfd_h8_disassemble): Add missing consts. 2006-10-26 15:37:21 +00:00
Alan Modra
e9f5312993 New Cell SPU port. 2006-10-25 06:49:21 +00:00
Alan Modra
ede602d7c8 Add powerpc cell support. 2006-10-24 01:27:29 +00:00
Michael Meissner
7918206c55 Fix AMDFAM10 POPCNT instruction 2006-10-23 22:53:29 +00:00
Andrew Stubbs
f3b8f6287b 2006-10-20 Andrew Stubbs <andrew.stubbs@st.com> 
opcodes/

	* sh-dis.c (print_insn_sh): Remove 0x from output to prevent GDB
	duplicating it.

gas/testsuite/

	* gas/sh/pcrel-coff.d: Update patterns (remove 0x on addresses).
	* gas/sh/pcrel-hms.d: Likewise.
	* gas/sh/pcrel.d: Likewise.
	* gas/sh/pcrel2.d: Likewise.
	* gas/sh/pic.d: Likewise.
	* gas/sh/tlsd.d: Likewise.
	* gas/sh/tlsdnopic.d: Likewise.
	* gas/sh/tlsdpic.d: Likewise.
 2006-10-20 14:47:05 +00:00
Dave Brolley
d3f1a42773 2006-10-18 Dave Brolley <brolley@redhat.com> 
* configure.in (BFD_MACHINES): Add cgen-bitset.lo for bfd_sh_arch.
        * configure: Regenerated.
 2006-10-18 18:18:26 +00:00
Alan Modra
3bb0c887b3 Regenerate. 2006-09-29 08:05:35 +00:00
Joseph Myers
2d447fcaa9 bfd/ 
2006-09-26  Mark Shinwell  <shinwell@codesourcery.com>
            Joseph Myers  <joseph@codesourcery.com>
            Ian Lance Taylor  <ian@wasabisystems.com>
            Ben Elliston  <bje@wasabisystems.com>

	* archures.c: Add definition for bfd_mach_arm_iWMMXt2.
	* cpu-arm.c (processors): Add bfd_mach_arm_iWMMXt2.
	(arch_info_struct, bfd_arm_update_notes): Likewise.
	(architectures): Likewise.
	(bfd_arm_merge_machines): Check for iWMMXt2.
	* bfd-in2.h: Rebuild.

gas/
2006-09-26  Mark Shinwell  <shinwell@codesourcery.com>
            Joseph Myers  <joseph@codesourcery.com>
            Ian Lance Taylor  <ian@wasabisystems.com>
            Ben Elliston  <bje@wasabisystems.com>

	* config/tc-arm.c (arm_cext_iwmmxt2): New.
	(enum operand_parse_code): New code OP_RIWR_I32z.
	(parse_operands): Handle OP_RIWR_I32z.
	(do_iwmmxt_wmerge): New function.
	(do_iwmmxt_wldstd): Handle iwmmxt2 case where second operand is
	a register.
	(do_iwmmxt_wrwrwr_or_imm5): New function.
	(insns): Mark instructions as RIWR_I32z as appropriate.
	Also add torvsc<b,h,w>, wabs<b,h,w>, wabsdiff<b,h,w>,
	waddbhus<l,m>, waddhc, waddwc, waddsubhx, wavg4{r}, wmaddu{x,n},
	wmadds{x,n}, wmerge, wmiaxy{n}, wmiawxy{n}, wmul<sm,um>{r},
	wmulw<um,sm,l>{r}, wqmiaxy{n}, wqmulm{r}, wqmulwm{r}, wsubaddhx.
	(md_begin): Handle IWMMXT2.
	(arm_cpus): Add iwmmxt2.
	(arm_extensions): Likewise.
	(arm_archs): Likewise.

gas/testsuite/
2006-09-26  Mark Shinwell  <shinwell@codesourcery.com>
            Joseph Myers  <joseph@codesourcery.com>
            Ian Lance Taylor  <ian@wasabisystems.com>
            Ben Elliston  <bje@wasabisystems.com>

	* gas/arm/iwmmxt2.s: New file.
	* gas/arm/iwmmxt2.d: New file.

include/opcode/
2006-09-26  Mark Shinwell  <shinwell@codesourcery.com>
            Joseph Myers  <joseph@codesourcery.com>
            Ian Lance Taylor  <ian@wasabisystems.com>
            Ben Elliston  <bje@wasabisystems.com>

	* arm.h (ARM_CEXT_IWMMXT2, ARM_ARCH_IWMMXT2): Define.

opcodes/
2006-09-26  Mark Shinwell  <shinwell@codesourcery.com>
            Joseph Myers  <joseph@codesourcery.com>
            Ian Lance Taylor  <ian@wasabisystems.com>
            Ben Elliston  <bje@wasabisystems.com>

	* arm-dis.c (coprocessor_opcodes): The X-qualifier to WMADD may
	only be used with the default multiply-add operation, so if N is
	set, don't bother printing X.  Add new iwmmxt instructions.
	(IWMMXT_INSN_COUNT): Update.
	(iwmmxt_wwssnames): Qualify "wwss" names at index 2, 6, 10 and 14
	with a 'c' suffix.
	(print_insn_coprocessor): Check for iWMMXt2.  Handle format
	specifiers 'r', 'i'.
 2006-09-26 12:04:45 +00:00
H.J. Lu
c4b5fff932 2006-09-24 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com> 
PR binutils/3100
	* i386-dis.c (prefix_user_table): Fix the second operand of
	maskmovdqu instruction to allow only %xmm register instead of
	both %xmm register and memory.
 2006-09-24 17:25:47 +00:00
H.J. Lu
a7a8d8e58e Add PR binutils/3000 to its entry. 2006-09-24 17:13:59 +00:00
H.J. Lu
539e75adb5 gas/ 
2006-09-23  H.J. Lu  <hongjiu.lu@intel.com>

	PR binutils/3235
	* config/tc-i386.c (match_template): Check address size prefix
	to turn Disp64/Disp32/Disp16 operand into Disp32/Disp16/Disp32
	operand.

gas/testsuite/

2006-09-23  H.J. Lu  <hongjiu.lu@intel.com>

	PR binutils/3235
	* gas/i386/addr16.d: New file.
	* gas/i386/addr16.s: Likewise.
	* gas/i386/addr32.d: Likewise.
	* gas/i386/addr32.s: Likewise.

	* gas/i386/i386.exp: Add "addr16" and "addr32".

	* gas/i386/x86-64-addr32.s: Add tests for "add32 mov".
	* gas/i386/x86-64-addr32.d: Updated.

opcodes/

2006-09-23  H.J. Lu  <hongjiu.lu@intel.com>

	PR binutils/3235
	* i386-dis.c (OP_OFF64): Get 32bit offset if there is an
	address size prefix.
 2006-09-23 23:10:14 +00:00
Nick Clifton
1c0d3aa6ae Add support for Score target. 2006-09-16 23:51:50 +00:00
Nick Clifton
0112cd268b * bfd-in.h (STRING_AND_COMMA): New macro. Takes one constant string as its 
argument and emits the string followed by a comma and then the length of
  the string.
  (CONST_STRNEQ): New macro.  Checks to see if a variable string has a constant
  string as its initial characters.
  (CONST_STRNCPY): New macro.  Copies a constant string to the start of a
  variable string.
* bfd-in2.h: Regenerate.
* <remainign files>: Make use of the new macros.
 2006-09-16 18:12:17 +00:00
Paul Brook
428e3f1f4e 2006-09-04 Paul Brook <paul@codesourcery.com> 
gas/
	* config/tc-arm.c (do_neon_dyadic_if_i): Remove.
	(do_neon_dyadic_if_i_d): Avoid setting U bit.
	(do_neon_mac_maybe_scalar): Ditto.
	(do_neon_dyadic_narrow): Force operand type to NT_integer.
	(insns): Remove out of date comments.

	gas/testsuite/
	* gas/arm/neon-cov.s: Test .u and .s aliases for .i suffixes.
	* gas/arm/neon-cov.d: Adjust expected output.

	opcodes/
	* arm-dis.c (neon_opcode): Fix suffix on VMOVN.
 2006-09-05 14:07:22 +00:00
H.J. Lu
96fbad7318 2006-08-23 H.J. Lu <hongjiu.lu@intel.com> 
* i386-dis.c (three_byte_table): Expand to 256 elements.
 2006-08-23 14:48:49 +00:00
Michael Meissner
4d9567e059 Fix bug 3000 2006-08-14 23:45:59 +00:00
Richard Sandiford
777b13b958 opcodes/ 
* m68k-opc.c (m68k_opcodes): Fix operand specificer in the Coldfire
	"fdaddl" entry.

gas/testsuite/
	* gas/m68k/mcf-fpu.s: Add tests for all addressing modes.
	* gas/m68k/mcf-fpu.d: Update accordingly.
 2006-07-29 08:55:38 +00:00
Paul Brook
401a54cf6e 2006-07-19 Paul Brook <paul@codesourcery.com> 
gas/
	* config/tc-arm.c (insns): Fix rbit Arm opcode.
	gas/testsuite/
	* gas/arm/archv6t2.d: Adjust expected output for rbit.
	opcodes/
	* armd-dis.c (arm_opcodes): Fix rbit opcode.
 2006-07-19 12:53:33 +00:00
H.J. Lu
2b516b7297 gas/testsuite/ 
2006-07-18  H.J. Lu  <hongjiu.lu@intel.com>

	* gas/i386/opcode.s: Add sldt, smsw and str.
	* gas/i386/x86-64-opcode.s: Likewise.

	* gas/i386/opcode.d: Updated.
	* gas/i386/x86-64-opcode.d: Likewise.

opcodes/

2006-07-18  H.J. Lu  <hongjiu.lu@intel.com>

	* i386-dis.c (grps): Change "sldtQ", "strQ" and "smswQ" to
	"sldt", "str" and "smsw".
 2006-07-18 20:25:41 +00:00
H.J. Lu
10505f38ce Add missing ChangeLog entry. 2006-07-15 16:58:36 +00:00
H.J. Lu
a6bd098c72 2006-07-15 H.J. Lu <hongjiu.lu@intel.com> 
PR binutils/2829
	* i386-dis.c (GRP11_C6): NEW.
	(GRP11_C7): Likewise.
	(GRP12): Updated.
	(GRP13): Likewise.
	(GRP14): Likewise.
	(GRP15): Likewise.
	(GRP16): Likewise.
	(GRPAMD): Likewise.
	(GRPPADLCK1): Likewise.
	(GRPPADLCK2): Likewise.
	(dis386): Use GRP11_C6 and GRP11_C7 for entres 0xc6 and 0xc7,
	respectively.
	(grps): Add entries for GRP11_C6 and GRP11_C7.
 2006-07-15 16:33:24 +00:00
Michael Meissner
050dfa73de Add amdfam10 instructions 2006-07-13 22:25:48 +00:00
Julian Brown
e8b42ce4f8 * arm-dis.c (coprocessor): Alter fmsrr disassembly syntax. 2006-07-05 17:08:47 +00:00
H.J. Lu
1596541188 gas/testsuite/ 
2006-06-12  H.J. Lu  <hongjiu.lu@intel.com>

	* gas/i386/i386.exp: Run nops and x86-64-nops.

	* gas/i386/nops.d: New file.
	* gas/i386/nops.s: Likewise.
	* gas/i386/x86-64-nops.d: Likewise.
	* gas/i386/x86-64-nops.s: Likewise.

include/opcode/

2006-06-12  H.J. Lu  <hongjiu.lu@intel.com>

	* i386.h (i386_optab): Add "nop" with memory reference.

opcodes/

2006-06-12  H.J. Lu  <hongjiu.lu@intel.com>

	* i386-dis.c (dis386_twobyte): Use "nopQ" for 0x1f.
	(twobyte_has_modrm): Set 1 for 0x1f.
 2006-06-12 18:59:37 +00:00
H.J. Lu
46e883c5a9 gas/ 
2006-06-12  H.J. Lu  <hongjiu.lu@intel.com>

	* config/tc-i386.c (process_suffix): Don't add rex64 for
	"xchg %rax,%rax".

gas/testsuite/

2006-06-12  H.J. Lu  <hongjiu.lu@intel.com>

	* gas/i386/opcode.s: Add "xchg %ax,%ax".
	* gas/i386/opcode.d: Updated.

	* gas/i386/x86-64-opcode.s: Add xchg %ax,%ax, xchg %eax,%eax,
	xchg %rax,%rax, rex64 xchg %rax,%rax and xchg %rax,%r8.
	* gas/i386/x86-64-opcode.d: Updated.

include/opcode/

2006-06-12  H.J. Lu  <hongjiu.lu@intel.com>

	* i386.h (i386_optab): Update comment for 64bit NOP.

opcodes/

2006-06-12  H.J. Lu  <hongjiu.lu@intel.com>

	* i386-dis.c (NOP_Fixup): Removed.
	(NOP_Fixup1): New.
	(NOP_Fixup2): Likewise.
	(dis386): Use NOP_Fixup1 and NOP_Fixup2 on 0x90.
 2006-06-12 18:55:44 +00:00
Julian Brown
4e9d3b813b * arm-dis.c (print_insn_neon): Disassemble 32-bit immediates as signed 
on 64-bit hosts.
 2006-06-12 15:31:28 +00:00
H.J. Lu
b3882df925 2006-06-10 H.J. Lu <hongjiu.lu@intel.com> 
* i386.c (GRP10): Renamed to ...
	(GRP12): This.
	(GRP11): Renamed to ...
	(GRP13): This.
	(GRP12): Renamed to ...
	(GRP14): This.
	(GRP13): Renamed to ...
	(GRP15): This.
	(GRP14): Renamed to ...
	(GRP16): This.
	(dis386_twobyte): Updated.
	(grps): Likewise.
 2006-06-10 18:20:39 +00:00
Nick Clifton
5f4df3dd7b Updated Finnish translation 2006-06-09 13:40:51 +00:00
Joseph Myers
6648b7cff9 bfd/doc: 
* bfd.texinfo: Remove local @tex code.

bfd:
	* po/Make-in (pdf, ps): New dummy targets.

binutils:
	* po/Make-in (pdf, ps): New dummy targets.

gas:
	* po/Make-in (pdf, ps): New dummy targets.

gprof:
	* po/Make-in (pdf, ps): New dummy targets.

ld:
	* po/Make-in (pdf, ps): New dummy targets.

opcodes:
	* po/Make-in (pdf, ps): New dummy targets.
 2006-06-07 15:38:01 +00:00
Paul Brook
c22aaad1c7 2006-06-06 Paul Brook <paul@codesourcery.com> 
opcodes/
	* arm-dis.c (coprocessor_opcodes): Add %c to unconditional arm
	instructions.
	(neon_opcodes): Add conditional execution specifiers.
	(thumb_opcodes): Ditto.
	(thumb32_opcodes): Ditto.
	(arm_conditional): Change 0xe to "al" and add "" to end.
	(ifthen_state, ifthen_next_state, ifthen_address): New.
	(IFTHEN_COND): Define.
	(print_insn_coprocessor, print_insn_neon): Print thumb conditions.
	(print_insn_arm): Change %c to use new values of arm_conditional.
	(print_insn_thumb16): Print thumb conditions.  Add %I.
	(print_insn_thumb32): Print thumb conditions.
	(find_ifthen_state): New function.
	(print_insn): Track IT block state.
gas/testsuite/
	* gas/arm/thumb2_bcond.d: Update expected output.
	* gas/arm/thumb32.d: Ditto.
	* gas/arm/vfp1_t2.d: Ditto.
	* gas/arm/vfp1xD_t2.d: Ditto.
binutils/testsuite/
	* binutils-all/arm/objdump.exp: New file.
	* binutils-all/arm/thumb2-cond.s: New test.
 2006-06-07 14:08:19 +00:00
Alan Modra
9622b051cf include/opcode/ 
* ppc.h (PPC_OPCODE_POWER6): Define.
	Adjust whitespace.
gas/
	* config/tc-ppc.c (parse_cpu): Handle "-mpower6".
	(md_show_usage): Document it.
	(ppc_setup_opcodes): Test power6 opcode flag bits.
	* doc/c-ppc.texi (PowerPC-Opts): Document "-mpower6".
opcodes/
	* ppc-dis.c (powerpc_dialect): Handle power6 option.
	(print_ppc_disassembler_options): Mention power6.
 2006-06-07 05:23:59 +00:00
Thiemo Seufer
65263ce323 [ gas/ChangeLog ] 
* config/tc-mips.c (ISA_SUPPORTS_DSP64): New macro.
	(CPU_HAS_MIPS3D, CPU_HAS_MDMX, CPU_HAS_DSP, CPU_HAS_MT): Delete.
	(macro_build): Update comment.
	(mips_ip): Allow DSP64 instructions for MIPS64R2.
	(mips_after_parse_args): Remove uses of CPU_HAS_MIPS3D and
	CPU_HAS_MDMX.
	(mips_cpu_info): Fix formatting. Add MIPS_CPU_ASE_MIPS3D and
	MIPS_CPU_ASE_MDMX flags for sb1.

	[ gas/testsuite/ChangeLog ]
	* gas/mips/mips64-dsp.s, gas/mips/mips64-dsp.d: New DSP64 tests.
	* gas/mips/mips.exp: Run DSP64 tests.

	[ opcodes/ChangeLog ]
	* mips-dis.c: Disassemble DSP64 instructions for MIPS64R2.
	* mips-opc.c: Add DSP64 instructions.
 2006-06-06 10:49:48 +00:00
Alan Modra
92ce91bb61 * m68hc11-dis.c (print_insn): Warning fix. 2006-06-06 02:48:34 +00:00
Daniel Jacobowitz
4cfe2c59ff bfd/, binutils/, gas/, gprof/, ld/, opcodes/ 
* po/Make-in (top_builddir): Define.
 2006-06-05 14:04:05 +00:00
Alan Modra
7ff1a5b533 * Makefile.am: Run "make dep-am". 
* Makefile.in: Regenerate.
	* config.in: Regenerate.
 2006-06-05 12:28:18 +00:00
Daniel Jacobowitz
20e95c23ab Configury changes: update src repository (binutils, gdb, and rda) to use 
config/gettext-sister.m4 instead of the old gettext.m4.  Regenerate all
affected autotools files.  Include intl in gdb releases again.
 2006-05-31 15:14:46 +00:00
Nick Clifton
eebf07fbf5 Update Spanish translation 2006-05-30 11:01:59 +00:00
Richard Sandiford
a596001ece include/opcodes/ 
* m68k.h (mcf_mask): Define.

opcodes/
	* m68k-opc.c (m68k_opcodes): Fix the masks of the Coldfire fmovemd
	and fmovem entries.  Put register list entries before immediate
	mask entries.  Use "l" rather than "L" in the fmovem entries.
	* m68k-dis.c (match_insn_m68k): Remove the PRIV argument and work it
	out from INFO.
	(m68k_scan_mask): New function, split out from...
	(print_insn_m68k): ...here.  If no architecture has been set,
	first try printing an m680x0 instruction, then try a Coldfire one.

gas/testsuite/
	* gas/m68k/mcf-fpu.s: Add fmovemd and fmovem instructions.
	* gas/m68k/mcf-fpu.d: Adjust accordingly.
 2006-05-25 08:09:03 +00:00
Nick Clifton
4a4d496a37 Updated Vietnamese and Irish translations 2006-05-24 07:54:45 +00:00
Nick Clifton
a854efa328 * crx-dis.c (EXTRACT): Make macro work on 64-bit hosts. 2006-05-22 08:40:09 +00:00
Nick Clifton
0bd7906139 Updated Dutch translation 2006-05-22 08:33:35 +00:00
Nick Clifton
7ff7c29e1f Remove ChangeLog entries, since the template files were already up to date. 2006-05-22 08:30:57 +00:00
Nick Clifton
5002adadc5 Update translation templates 2006-05-22 08:25:15 +00:00
Alan Modra
00988f494c * avr-dis.c: Formatting fix. 2006-05-17 23:44:58 +00:00
Thiemo Seufer
9b3f89ee00 [ gas/ChangeLog ] 
* config/tc-mips.c (macro_build): Test for currently active
	mips16 option.
	(mips16_ip): Reject invalid opcodes.

	[ opcodes/ChangeLog ]
	* mips16-opc.c (I1, I32, I64): New shortcut defines.
	(mips16_opcodes): Change membership of instructions to their
	lowest baseline ISA.

	[ gas/testsuite/ChangeLog ]
	* gas/mips/mips.exp: Run new tests.
	* gas/mips/mips16e.s, gas/mips/mips16e.d, gas/mips/mips16e-64.s,
	gas/mips/mips16e-64.d, gas/mips/mips16e-64.l: New tests.
 2006-05-14 15:35:22 +00:00
H.J. Lu
cb6d34334f gas/testsuite/ 
2006-05-09  H.J. Lu  <hongjiu.lu@intel.com>

	* gas/i386/i386.exp: Run x86-64-gidt.

	* gas/i386/x86-64-gidt.d: New file.
	* gas/i386/x86-64-gidt.s: Likewise.

opcodes/

2006-05-09  H.J. Lu  <hongjiu.lu@intel.com>

	* i386-dis.c (grps): Update sgdt/sidt for 64bit.
 2006-05-09 16:05:40 +00:00
Julian Brown
1f3c39b9e6 * arm-dis.c (coprocessor_opcodes): Don't interpret fldmx/fstmx as 
vldm/vstm.
 2006-05-05 18:56:01 +00:00
Thiemo Seufer
d43b4baf07 [ gas/ChangeLog ] 
* config/tc-mips.c (macro_build): Add case 'k' to handle cache
	instruction.
	(macro): Add new case M_CACHE_AB.

	[ opcodes/ChangeLog ]
	* mips-opc.c: Add macro for cache instruction.

	[ include/opcode/ChangeLog ]
	* mips.h (enum): Add macro M_CACHE_AB.
 2006-05-05 15:41:23 +00:00
Thiemo Seufer
39a7806dae [ gas/testsuite/ChangeLog ] 
2006-05-04  Thiemo Seufer  <ths@mips.com>
            Nigel Stephens  <nigel@mips.com>

        * gas/mips/mips.exp: Run mips32-dsp tests only for mips32r2.
        * gas/mips/set-arch.d: Adjust according to opcode table changes.

[ include/opcode/ChangeLog ]
2006-05-04  Thiemo Seufer  <ths@mips.com>
            Nigel Stephens  <nigel@mips.com>
            David Ung  <davidu@mips.com>

        * mips.h: Add INSN_SMARTMIPS define.

[ opcodes/ChangeLog ]
2006-05-04  Thiemo Seufer  <ths@mips.com>
            Nigel Stephens  <nigel@mips.com>
            David Ung  <davidu@mips.com>

        * mips-dis.c (mips_arch_choices): Add smartmips instruction
        decoding to MIPS32 and MIPS32R2.  Limit DSP decoding to release
        2 ISAs.  Add MIPS3D decoding to MIPS32R2.  Add MT decoding to
        MIPS64R2.
        * mips-opc.c: fix random typos in comments.
        (INSN_SMARTMIPS): New defines.
        (mips_builtin_opcodes): Add paired single support for MIPS32R2.
        Move bc3f, bc3fl, bc3t, bc3tl downwards.  Move flushi, flushd,
        flushid, wb upwards.  Move cfc3, ctc3 downwards.  Rework the
        FP_S and FP_D flags to denote single and double register
        accesses separately.  Move dmfc3, dmtc3, mfc3, mtc3 downwards.
        Allow jr.hb and jalr.hb for release 1 ISAs.  Allow luxc1, suxc1
        for MIPS32R2.  Add SmartMIPS instructions.  Add two-argument
        variants of bc2f, bc2fl, bc2t, bc2tl.  Add mfhc2, mthc2 to
        release 2 ISAs.
        * mips16-opc.c (mips16_opcodes): Add sdbbp instruction.
 2006-05-04 10:47:05 +00:00
Thiemo Seufer
104b4fab38 2006-05-03 Thiemo Seufer <ths@mips.com> 
[ opcodes/ChangeLog ]
        * mips-opc.c (mips_builtin_opcodes): Fix mftr argument order.

        [ gas/testsuite/ChangeLog ]
        * gas/mips/mips32-mt.d: Fix mftr argument order.
 2006-05-03 20:59:20 +00:00
Thiemo Seufer
022fac6d2a * mips-dis.c (print_insn_args): Force mips16 to odd addresses. 
(print_mips16_insn_arg): Force mips16 to odd addresses.
 2006-05-02 11:12:41 +00:00
Thiemo Seufer
9bcd4f993c [ gas/ChangeLog ] 
2006-04-30  Thiemo Seufer  <ths@mips.com>
            David Ung  <davidu@mips.com>

        * config/tc-mips.c (validate_mips_insn): Handling of udi cases.
        (mips_immed): New table that records various handling of udi
        instruction patterns.
        (mips_ip): Adds udi handling.

[ include/opcode/ChangeLog ]
2006-04-30  Thiemo Seufer  <ths@mips.com>
            David Ung  <davidu@mips.com>

        * mips.h: Defines udi bits and masks.  Add description of
        characters which may appear in the args field of udi
        instructions.

[ opcodes/ChangeLog ]
2006-04-30  Thiemo Seufer  <ths@mips.com>
            David Ung  <davidu@mips.com>

        * mips-opc.c (mips_builtin_opcodes): Add udi instructions
        "udi0" to "udi15".
        * mips-dis.c (print_insn_args): Adds udi argument handling.
 2006-04-30 18:34:39 +00:00
Jim Wilson
f095b97b59 Fix buglet noticed while looking at PR 1298. 
* m68k-dis.c (match_insn_m68k): Restore fprintf_func before printing
error message.
 2006-04-29 03:11:31 +00:00
Thiemo Seufer
bdb09db1cf Don't mis-spell your boss' name... 2006-04-28 13:38:49 +00:00
Thiemo Seufer
59c455b37c [ opcodes/ChangeLog ] 
2006-04-28  Thiemo Seufer  <ths@mips.com>
            David Ung  <davidu@mips.com>
            Nigel Stevens  <nigel@mips.com>

	* mips-dis.c (mips_cp0sel_names_mips3264r2): Add MT register
        names.

[ gas/testsuite/ChangeLog ]
2006-04-28  Thiemo Seufer  <ths@mips.com>
            David Ung  <davidu@mips.com>
            Nigel Stevens  <nigel@mips.com>

	* gas/mips/cp0sel-names-mips32r2.d,
	gas/mips/cp0sel-names-mips64r2.d: Update for MT register names.
 2006-04-28 13:17:00 +00:00
Thiemo Seufer
cc0ca239ed * mips-dis.c (print_insn_args): Add mips_opcode argument. 
(print_insn_mips):  Adjust print_insn_args call.
 2006-04-28 12:59:30 +00:00
Thiemo Seufer
0d09bfe6d3 * mips-dis.c (print_insn_args): Print $fcc only for FP 
instructions, use $cc elsewise.
 2006-04-28 12:19:31 +00:00
Thiemo Seufer
654c225a6d * opcodes/mips-dis.c (mips16_to_32_reg_map, mips16_reg_names): 
Map MIPS16 registers to O32 names.
	(print_mips16_insn_arg): Use mips16_reg_names.
 2006-04-28 11:42:28 +00:00
Julian Brown
0dbde4cf38 * arm-dis.c (print_insn_neon): Disassemble floating-point constant 
VMOV.
 2006-04-26 16:02:07 +00:00
Julian Brown
16980d0b05 * opcodes/arm-dis.c (coprocessor_opcodes): Add %A, %B, %k, convert 
%<code>[zy] into %[zy]<code>.  Expand meaning of %<bitfield>['`?].
	Add unified load/store instruction names.
	(neon_opcode_table): New.
	(arm_opcodes): Expand meaning of %<bitfield>['`?].
	(arm_decode_bitfield): New.
	(print_insn_coprocessor): Add pc argument. Add %A & %B specifiers.
	Use arm_decode_bitfield and adjust numeric specifiers. Adjust %z & %y.
	(print_insn_neon): New.
	(print_insn_arm): Adjust print_insn_coprocessor call. Call
	print_insn_neon. Use arm_decode_bitfield and adjust numeric specifiers.
	(print_insn_thumb32): Likewise.
 2006-04-26 15:40:55 +00:00
Alan Modra
ec3fcc5688 * Makefile.am: Run "make dep-am". 
* Makefile.in: Regenerate.
 2006-04-19 12:10:21 +00:00
Alan Modra
7c6646cd4b * avr-dis.c (avr_operand): Warning fix. 2006-04-19 02:15:05 +00:00
Alan Modra
241a6c40c8 bfd/ 
* warning.m4 (--enable-werror, -build-warnings): Format help messages.
	* configure: Regenerate.
binutils/
	* configure: Regenerate.
gas/
	* configure.in (--enable-targets): Indent help message.
	* configure: Regenerate.
gprof/
	* configure: Regenerate.
ld/
	* configure: Regenerate.
opcodes/
	* configure: Regenerate.
 2006-04-19 02:06:15 +00:00
Daniel Jacobowitz
e740356690 Update POTFILES.in. 2006-04-16 18:25:11 +00:00
Nick Clifton
52f16a0ef4 PR binutils/2454 
* avr-dis.c (avr_operand): Arrange for a comment to appear before the symolic
form of an address, so that the output of objdump -d can be reassembled.
 2006-04-12 13:09:10 +00:00
DJ Delorie
e78efa90d6 * m32c.opc (parse_unsigned_bitbase): Take a new parameter which 
decides if this function accepts symbolic constants or not.
(parse_signed_bitbase): Likewise.
(parse_unsigned_bitbase8): Pass the new parameter.
(parse_unsigned_bitbase11): Likewise.
(parse_unsigned_bitbase16): Likewise.
(parse_unsigned_bitbase19): Likewise.
(parse_unsigned_bitbase27): Likewise.
(parse_signed_bitbase8): Likewise.
(parse_signed_bitbase11): Likewise.
(parse_signed_bitbase19): Likewise.
* m32c-asm.c: Regenerate.
 2006-04-10 21:19:14 +00:00
Carlos O'Donell
108a6f8eb4 2006-04-06 Carlos O'Donell <carlos@codesourcery.com> 
* Makefile.tpl: Add install-html target.
	* Makefile.def: Add install-html target.
	* Makefile.in: Regenerate.
	* configure.in: Add --with-datarootdir, --with-docdir,
	and --with-htmldir options.
	* configure: Regenerate.

bfd/

2006-04-06  Carlos O'Donell  <carlos@codesourcery.com>

	* po/Make-in: Add install-html target.
	* Makefile.am: Rename docdir to bfddocdir. Add datarootdir, docdir
	htmldir. Add install-html and install-html-recursive targets.
	* Makefile.in: Regenerate.
	* configure.in: AC_SUBST for datarootdir, docdir and htmldir.
	* configure: Regenerate.

bfd/doc/

2006-04-06  Carlos O'Donell  <carlos@codesourcery.com>

	* Makefile.am: Add install-html and install-html-am targets.
	Define datarootdir, docdir and htmldir.
	* Makefile.in: Regenerate.

binutils/

2006-04-06  Carlos O'Donell  <carlos@codesourcery.com>

	* po/Make-in: Add install-html target.
	* Makefile.am: Add install-html and install-html-recursive targets.
	* Makefile.in: Regenerate.
	* configure.in: AC_SUBST datarootdir, docdir and htmldir.
	* configure: Regenerate.
	* doc/Makefile.am: Add install-html and install-html-am targets.
	* doc/Makefile.in: Regenerate.

etc/

2006-04-06  Carlos O'Donell  <carlos@codesourcery.com>

	* Makefile.in: Add install-html target. Add htmldir,
	docdir and datarootdir.
	* configure.texi: Document install-html target.
	* configure.in: AC_SUBST datarootdir, docdir, htmldir.
	* configure: Regenerate.

gas/

2006-04-06  Carlos O'Donell  <carlos@codesourcery.com>

	* po/Make-in: Add install-html target.
	* Makefile.am: Add install-html and install-html-recursive targets.
	* Makefile.in: Regenerate.
	* configure.in: AC_SUBST datarootdir, docdir, htmldir.
	* configure: Regenerate.
	* doc/Makefile.am: Add install-html and install-html-am targets.
	* doc/Makefile.in: Regenerate.

gprof/

2006-04-06  Carlos O'Donell  <carlos@codesourcery.com>

	* po/Make-in: Add install-html target.
	* Makefile.am: Add install-html, install-html-am and
	install-html-recursive targets.
	* Makefile.in: Regenerate.
	* configure.in: AC_SUBST datarootdir, docdir, htmldir.
	* configure: Regenerate.

intl/

2006-04-06  Carlos O'Donell  <carlos@codesourcery.com>

	* intl/Makefile.in: Add html info and dvi and install-html to .PHONY
	Add install-html target.

ld/

2006-04-06  Carlos O'Donell  <carlos@codesourcery.com>

	* Makefile.am: Add install-html, install-html-am, and
	install-html-recursive targets.
	* Makefile.in: Regenerate.
	* configure.in: AC_SUBST datarootdir, docdir, htmldir.
	* configure: Regenerate.
	* po/Make-in: Add install-html target.

opcodes/

2006-04-06  Carlos O'Donell  <carlos@codesourcery.com>

	* Makefile.am: Add install-html target.
	* Makefile.in: Regenerate.
 2006-04-06 21:49:35 +00:00
Nick Clifton
a135cb2ce1 Updated Vietnamese translation. 2006-04-06 10:09:41 +00:00
Alan Modra
47426b4127 * pdp11-opc.c (pdp11_opcodes): Fix opcode for SEC instruction. 2006-03-31 11:43:14 +00:00
Bernd Schmidt
331f1cbe1c * bfin-dis.c (decode_dsp32shiftimm_0): Simplify and correct the 
logic to identify halfword shifts.
 2006-03-16 19:09:48 +00:00
Paul Brook
c16d2bf065 2006-03-16 Paul Brook <paul@codesourcery.com> 
gas/
	* config/tc-arm.c (insns): Add "svc".
gas/testsuite/
	* gas/arm/svc.d: New test.
	* gas/arm/svc.s: New test.
	* gas/arm/inst.d: Accept svc mnemonic.
	* gas/arm/thumb.d: Ditto.
	* gas/arm/wince_inst.d: Ditto.
opcodes/
	* arm-dis.c (arm_opcodes): Rename swi to svc.
	(thumb_opcodes): Ditto.
 2006-03-16 15:08:48 +00:00
DJ Delorie
5398310abc * m32c-asm.c: Regenerate. 
* m32c-desc.c: Likewise.
* m32c-desc.h: Likewise.
* m32c-dis.c: Likewise.
* m32c-ibld.c: Likewise.
* m32c-opc.c: Likewise.
* m32c-opc.h: Likewise.
 2006-03-14 04:23:52 +00:00
DJ Delorie
5348b81e4c i* m32c-desc.c: Regenerate. 
* m32c-opc.c: Likewise.
* m32c-opc.h: Likewise.
 2006-03-14 00:30:59 +00:00
DJ Delorie
253d272cfc * m32c.cpu (mul.l): New. 
(mulu.l): New.
* m32c-desc.c: Regenerate with mul.l, mulu.l.
* m32c-opc.c: Likewise.
* m32c-opc.h: Likewise.
 2006-03-11 02:23:19 +00:00
Nick Clifton
f530741d16 Update Swedish translations 2006-03-09 17:28:11 +00:00
H.J. Lu
35c52694b9 gas/testsuite/ 
2006-03-07  H.J. Lu  <hongjiu.lu@intel.com>

	PR binutils/2428
	* gas/i386/i386.exp: Add rep, rep-suffix, x86-64-rep and
	x86-64-rep-suffix.

	* gas/i386/naked.d: Replace repz with rep.
	* gas/i386/x86_64.d: Likewise.

	* gas/i386/rep-suffix.d: New file.
	* gas/i386/rep-suffix.s: Likewise.
	* gas/i386/rep.d: Likewise.
	* gas/i386/rep.s: Likewise.
	* gas/i386/x86-64-rep-suffix.d: Likewise.
	* gas/i386/x86-64-rep-suffix.s: Likewise.
	* gas/i386/x86-64-rep.d: Likewise.
	* gas/i386/x86-64-rep.s: Likewise.

opcodes/

2006-03-07  H.J. Lu  <hongjiu.lu@intel.com>

	PR binutils/2428
	* i386-dis.c (REP_Fixup): New function.
	(AL): Remove duplicate.
	(Xbr): New.
	(Xvr): Likewise.
	(Ybr): Likewise.
	(Yvr): Likewise.
	(indirDXr): Likewise.
	(ALr): Likewise.
	(eAXr): Likewise.
	(dis386): Updated entries of ins, outs, movs, lods and stos.
 2006-03-07 20:18:06 +00:00
Nick Clifton
ed963e2de8 * cgen-ibld.in (insert_normal): Cope with attempts to insert a signed 32-bit 
value into an unsigned 32-bit field when the host is a 64-bit machine.
 2006-03-05 08:38:53 +00:00
Nick Clifton
c7d41dc5a0 Fix parseing functions to return an error message if the parse failed 2006-03-03 15:57:43 +00:00
Carlos O'Donell
f7d9e5c379 bfd/doc/ 
2006-10-14  Carlos O'Donell  <carlos@codesourcery.com>

       * Makefile.am: Add html target.
       * Makefile.in: Regenerate.

bfd/
2006-10-14  Carlos O'Donell  <carlos@codesourcery.com>

       * po/Make-in: Add html target.

binutils/
2006-10-14  Carlos O'Donell  <carlos@codesourcery.com>

       * po/Make-in: Add html target.

gas/
2006-10-14  Carlos O'Donell  <carlos@codesourcery.com>

       * doc/Makefile.am: Add html target.
       * doc/Makefile.in: Regenerate.
       * po/Make-in: Add html target.

gprof/
2006-10-14  Carlos O'Donell  <carlos@codesourcery.com>

       * po/Make-in: Add html target.

ld/
2006-10-14  Carlos O'Donell  <carlos@codesourcery.com>

       * Makefile.am: Add html target.
       * Makefile.in: Regenerate.
       * po/Make-in: Add html target.

opcodes/
2006-10-14  Carlos O'Donell  <carlos@codesourcery.com>

       * po/Make-in: Add html target.

etc/
2006-10-14  Carlos O'Donell  <carlos@codesourcery.com>

       * Makefile.in: TEXI2HTML uses makeinfo. Define
       HTMLFILES. Add html targets.
       * configure.texi: Use ifnottex. Add alternative
       image format specifier as jpg.
       * standards.texi: Use ifnottex.

intl/
2006-10-14  Carlos O'Donell  <carlos@codesourcery.com>

       * intl/Makefile.in: Add html target.
 2006-02-27 16:26:26 +00:00
H.J. Lu
331d2d0d9c gas/ 
2006-02-27  H.J. Lu <hongjiu.lu@intel.com>

	* gas/config/tc-i386.c (output_insn): Support Intel Merom New
	Instructions.

	* gas/config/tc-i386.h (CpuMNI): New.
	(CpuUnknownFlags): Add CpuMNI.

gas/testsuite/

2006-02-27  H.J. Lu <hongjiu.lu@intel.com>

	* gas/i386/i386.exp: Add merom and x86-64-merom.

	* gas/i386/merom.d: New file.
	* gas/i386/merom.s: Likewise.
	* gas/i386/x86-64-merom.d: Likewise.
	* gas/i386/x86-64-merom.s: Likewise.

include/opcode/

2006-02-27  H.J. Lu <hongjiu.lu@intel.com>

	* i386.h (i386_optab): Support Intel Merom New Instructions.

opcodes/

2006-02-27  H.J. Lu <hongjiu.lu@intel.com>

	* i386-dis.c (IS_3BYTE_OPCODE): New for 3-byte opcodes used by
	Intel Merom New Instructions.
	(THREE_BYTE_0): Likewise.
	(THREE_BYTE_1): Likewise.
	(three_byte_table): Likewise.
	(dis386_twobyte): Use THREE_BYTE_0 for entry 0x38. Use
	THREE_BYTE_1 for entry 0x3a.
	(twobyte_has_modrm): Updated.
	(twobyte_uses_SSE_prefix): Likewise.
	(print_insn): Handle 3-byte opcodes used by Intel Merom New
	Instructions.
 2006-02-27 15:35:37 +00:00
David S. Miller
ff3f9d5b2a 2006-02-24 David S. Miller <davem@sunset.davemloft.net> 
* sparc-dis.c (v9_priv_reg_names): Add "gl" entry.
	(v9_hpriv_reg_names): New table.
	(print_insn_sparc): Allow values up to 16 for '?' and '!'.
	New cases '$' and '%' for read/write hyperprivileged register.
	* sparc-opc.c (sparc_opcodes): Add new entries for UA2005
	window handling and rdhpr/wrhpr instructions.
 2006-02-25 01:33:24 +00:00
DJ Delorie
6772dd07c4 [include/elf] 
* m32c.h: Add relax relocs.

[cpu]
	* m32c.cpu (RL_TYPE): New attribute, with macros.
	(Lab-8-24): Add RELAX.
	(unary-insn-defn-g, binary-arith-imm-dst-defn,
	binary-arith-imm4-dst-defn): Add 1ADDR attribute.
	(binary-arith-src-dst-defn): Add 2ADDR attribute.
	(jcnd16-5, jcnd16, jcnd32, jmp16.s, jmp16.b, jmp16.w, jmp16.a,
	jmp32.s, jmp32.b, jmp32.w, jmp32.a, jsr16.w, jsr16.a): Add JUMP
	attribute.
	(jsri16, jsri32): Add 1ADDR attribute.
	(jsr32.w, jsr32.a): Add JUMP attribute.

[opcodes]
	* m32c-desc.c: Regenerate with linker relaxation attributes.
	* m32c-desc.h: Likewise.
	* m32c-dis.c: Likewise.
	* m32c-opc.c: Likewise.

[gas]
	* config/tc-m32c.h (md_apply_fix): Define to m32c_apply_fix.
	(tc_gen_reloc): Don't define.
	* config/tc-m32c.c (rl_for, relaxable): New convenience macros.
	(OPTION_LINKRELAX): New.
	(md_longopts): Add it.
	(m32c_relax): New.
	(md_parse_options): Set it.
	(md_assemble): Emit relaxation relocs as needed.
	(md_convert_frag): Emit relaxation relocs as needed.
	(md_cgen_lookup_reloc): Add LAB_8_8 and LAB_8_16.
	(m32c_apply_fix): New.
	(tc_gen_reloc): New.
	(m32c_force_relocation): Force out jump relocs when relaxing.
	(m32c_fix_adjustable): Return false if relaxing.

[bfd]
	* elf32-m32c.c (m32c_elf_howto_table): Add relaxation relocs.
	(m32c_elf_relocate_section): Don't relocate them.
	(compare_reloc): New.
	(relax_reloc): Remove.
	(m32c_offset_for_reloc): New.
	(m16c_addr_encodings): New.
	(m16c_jmpaddr_encodings): New.
	(m32c_addr_encodings): New.
	(m32c_elf_relax_section): Relax jumps and address displacements.
	(m32c_elf_relax_delete_bytes): Adjust for internal syms.  Fix up
	short jumps.

	* reloc.c: Add m32c relax relocs.
	* libbfd.h: Regenerate.
 2006-02-24 22:10:36 +00:00
Paul Brook
62b3e31101 2006-02-24 Paul Brook <paul@codesourcery.com> 
gas/
	* config/arm/tc-arm.c (arm_ext_v6_notm, arm_ext_div, arm_ext_v7,
	arm_ext_v7a, arm_ext_v7r, arm_ext_v7m): New variables.
	(struct asm_barrier_opt): Define.
	(arm_v7m_psr_hsh, arm_barrier_opt_hsh): New variables.
	(parse_psr): Accept V7M psr names.
	(parse_barrier): New function.
	(enum operand_parse_code): Add OP_oBARRIER.
	(parse_operands): Implement OP_oBARRIER.
	(do_barrier): New function.
	(do_dbg, do_pli, do_t_barrier, do_t_dbg, do_t_div): New functions.
	(do_t_cpsi): Add V7M restrictions.
	(do_t_mrs, do_t_msr): Validate V7M variants.
	(md_assemble): Check for NULL variants.
	(v7m_psrs, barrier_opt_names): New tables.
	(insns): Add V7 instructions.  Mark V6 instructions absent from V7M.
	(md_begin): Initialize arm_v7m_psr_hsh and arm_barrier_opt_hsh.
	(arm_cpu_option_table): Add Cortex-M3, R4 and A8.
	(arm_arch_option_table): Add armv7, armv7a, armv7r and armv7m.
	(struct cpu_arch_ver_table): Define.
	(cpu_arch_ver): New.
	(aeabi_set_public_attributes): Use cpu_arch_ver.  Set
	Tag_CPU_arch_profile.
	* doc/c-arm.texi: Document new cpu and arch options.
gas/testsuite/
	* gas/arm/thumb32.d: Fix expected msr and mrs output.
	* gas/arm/arch7.d: New test.
	* gas/arm/arch7.s: New test.
	* gas/arm/arch7m-bad.l: New test.
	* gas/arm/arch7m-bad.d: New test.
	* gas/arm/arch7m-bad.s: New test.
include/opcode/
	* arm.h: Add V7 feature bits.
opcodes/
	* arm-dis.c (arm_opcodes): Add V7 instructions.
	(thumb32_opcodes): Ditto.  Handle V7M MSR/MRS variants.
	(print_arm_address): New function.
	(print_insn_arm): Use it.  Add 'P' and 'U' cases.
	(psr_name): New function.
	(print_insn_thumb32): Add 'U', 'C' and 'D' cases.
 2006-02-24 15:36:36 +00:00
H.J. Lu
59cf82fe74 bfd/ 
2006-02-23  H.J. Lu  <hongjiu.lu@intel.com>

	* cpu-ia64-opc.c (ins_immu5b): New.
	(ext_immu5b): Likewise.
	(elf64_ia64_operands): Add IMMU5b.

gas/

2006-02-23  H.J. Lu  <hongjiu.lu@intel.com>

	* config/tc-ia64.c (operand_match): Handle IA64_OPND_IMMU5b.

gas/testsuite/

2006-02-23  H.J. Lu  <hongjiu.lu@intel.com>

	* gas/ia64/opc-i.s: Add tests for tf.
	* gas/ia64/pseudo.s: Likewise.
	* gas/ia64/opc-i.d: Updated.
	* gas/ia64/pseudo.d: Likewise.

include/opcode/

2006-02-23  H.J. Lu  <hongjiu.lu@intel.com>

	* ia64.h (ia64_opnd): Add IA64_OPND_IMMU5b.

opcodes/

2006-02-23  H.J. Lu  <hongjiu.lu@intel.com>

	* ia64-opc-i.c (bXc): New.
	(mXc): Likewise.
	(OpX2TaTbYaXcC): Likewise.
	(TF). Likewise.
	(TFCM). Likewise.
	(ia64_opcodes_i): Add instructions for tf.

	* ia64-opc.h (IMMU5b): New.

	* ia64-asmtab.c: Regenerated.
 2006-02-23 21:36:18 +00:00
H.J. Lu
19a7219fd1 Update copyright years. 2006-02-23 14:49:32 +00:00
H.J. Lu
7f3dfb9cf7 gas/ 
2006-02-22  H.J. Lu  <hongjiu.lu@intel.com>

	* config/tc-ia64.c (specify_resource): Add the rule 17 from
	SDM 2.2.

gas/testsuite/

2006-02-22  H.J. Lu  <hongjiu.lu@intel.com>

	* gas/ia64/dv-raw-err.s: Add check for vmsw.0.
	* gas/ia64/dv-raw-err.l: Updated.

	* gas/ia64/opc-b.s: Add vmsw.0 and vmsw.1.
	* gas/ia64/opc-b.d: Updated.

opcodes/

2006-02-22  H.J. Lu  <hongjiu.lu@intel.com>

	* ia64-gen.c (lookup_regindex): Handle ".vm".
	(print_dependency_table): Handle '\"'.

	* ia64-ic.tbl: Updated from SDM 2.2.
	* ia64-raw.tbl: Likewise.
	* ia64-waw.tbl: Likewise.
	* ia64-asmtab.c: Regenerated.

	* ia64-opc-b.c (ia64_opcodes_b): Add vmsw.0 and vmsw.1.
 2006-02-23 00:17:24 +00:00
Nick Clifton
d70c5fc7c5 Add support for the Infineon XC16X. 2006-02-17 14:36:28 +00:00
H.J. Lu
a1cfb73ee0 gas/testsuite/ 
2006-02-11  H.J. Lu  <hongjiu.lu@intel.com>

	* gas/i386/i386.exp: Add "x86-64-drx" and "x86-64-drx-suffix".

	* gas/i386/x86-64-crx-suffix.d: Minor update.

	* gas/i386/x86-64-drx-suffix.d: New file.
	* gas/i386/x86-64-drx.d: Likewise.
	* gas/i386/x86-64-drx.s: Likewise.

opcodes/

2006-02-11  H.J. Lu  <hongjiu.lu@intel.com>

	* i386-dis.c (dis386_twobyte): Use "movZ" for debug register
	moves.
 2006-02-11 18:08:35 +00:00
H.J. Lu
6dd5059a06 gas/testsuite/ 
2006-02-11  H.J. Lu  <hongjiu.lu@intel.com>

	* gas/i386/i386.exp: Add "x86-64-crx" and "x86-64-crx-suffix".

	* gas/i386/x86-64-crx-suffix.d: New file.
	* gas/i386/x86-64-crx.d: Likewise.
	* gas/i386/x86-64-crx.s: Likewise.

opcodes/

2006-02-11  H.J. Lu  <hongjiu.lu@intel.com>

	* i386-dis.c ('Z'): Add a new macro.
	(dis386_twobyte): Use "movZ" for control register moves.
 2006-02-11 17:00:59 +00:00
Nick Clifton
8536c657ff Fix %hi() operator for 64-bit hosts. 2006-02-10 12:05:12 +00:00
Nathan Sidwell
266abb8f72 * bfd/archures.c (bfd_mach_mcf5200, bfd_mach_mcf5206e, 
bfd_mach_mcf5307, bfd_mach_mcf5407, bfd_mach_mcf528x,
	bfd_mach_mcfv4e, bfd_mach_mcf521x, bfd_mach_mcf5249,
	bfd_mach_mcf547x, bfd_mach_mcf548x): Remove.
	(bfd_mach_mcf_isa_a, bfd_mach_mcf_isa_a_div,
	bfd_mach_mcf_isa_a_div_mac, bfd_mach_mcf_isa_a_div_emac,
	bfd_mach_mcf_isa_aplus, bfd_mach_mcf_isa_aplus_mac,
	bfd_mach_mcf_isa_aplus_emac, bfd_mach_mcf_isa_aplus_usp,
	bfd_mach_mcf_isa_aplus_usp_mac, bfd_mach_mcf_isa_aplus_usp_emac,
	bfd_mach_mcf_isa_b, bfd_mach_mcf_isa_b_mac, bfd_mach_mcf_isa_b_emac,
	bfd_mach_mcf_isa_b_usp_float, bfd_mach_mcf_isa_b_usp_float_mac,
	bfd_mach_mcf_isa_b_usp_float_emac): New.
	(bfd_default_scan): Update coldfire mapping.
	* bfd/bfd-in.h (bfd_m68k_mach_to_features,
	bfd_m68k_features_to_mach): Declare.
	* bfd/bfd-in2.h: Rebuilt.
	* bfd/cpu-m68k.c (arch_info_struct): Add new coldfire machines,
	adjust legacy names.
	(m68k_arch_features): New.
	(bfd_m68k_mach_to_features,
	bfd_m68k_features_to_mach): Define.
	* bfd/elf32-m68k.c (elf32_m68k_object_p): New.
	(elf32_m68k_merge_private_bfd_data): Merge the CF EF flags.
	(elf32_m68k_print_private_bfd_data): Print the CF EF flags.
	(elf_backend_object_p): Define.
	* bfd/ieee.c (ieee_write_processor): Update coldfire machines.
	* bfd/libbfd.h: Rebuilt.

	* gas/config/tc-m68k.c (mcf5208_control_regs, mcf5213_control_regs,
	mcf5329_control_regs): New.
	(not_current_architecture, selected_arch, selected_cpu): New.
	(m68k_archs, m68k_extensions): New.
	(archs): Renamed to ...
	(m68k_cpus): ... here.  Adjust.
	(n_arches): Remove.
	(md_pseudo_table): Add arch and cpu directives.
	(find_cf_chip, m68k_ip): Adjust table scanning.
	(no_68851, no_68881): Remove.
	(md_assemble): Lazily initialize.
	(select_control_regs): Adjust cpu names. Add 5208, 5213, 5329.
	(md_init_after_args): Move functionality to m68k_init_arch.
	(mri_chip): Adjust table scanning.
	(md_parse_option): Reimplement 'm' processing to add -march & -mcpu
	options with saner parsing.
	(m68k_lookup_cpu, m68k_set_arch, m68k_set_cpu, m68k_set_extension,
	m68k_init_arch): New.
	(s_m68k_cpu, s_m68k_arch): New.
	(md_show_usage): Adjust.
	(m68k_elf_final_processing): Set CF EF flags.
	* gas/config/tc-m68k.h (m68k_init_after_args): Remove.
	(tc_init_after_args): Remove.
	* gas/doc/c-m68k.texi (M68K-Opts): Document -march, -mcpu options.
	(M68k-Directives): Document .arch and .cpu directives.

	* gas/testsuite/gas/m68k/all.exp: Add arch-cpu-1 test.
	* gas/testsuite/gas/m68k/arch-cpu-1.[sd]: New.

	* include/elf/m68k.h (EF_CPU32, EF_M68000, EF_CFV4E): Rename to ...
	(EF_M68K_CPU32, EF_M68K_M68000, EF_M68K_CFV4E): ... here.
	(EF_M68K_ISA_MASK, EF_M68K_ISA_A, EF_M68K_M68K_ISA_A_PLUS,
	EF_M68K_ISA_B, EF_M68K_HW_DIV, EF_M68K_MAC_MASK, EF_M68K_MAC,
	EF_M68K_EMAC, EF_M68K_USP, EF_M68K_FLOAT): New.

	* include/opcode/m68k.h (m68008, m68ec030, m68882): Remove.
	(m68k_mask): New.
	(cpu_m68k, cpu_cf): New.
	(mcf5200, mcf5206e, mcf521x, mcf5249, mcf528x, mcf5307, mcf5407,
	mcf5470, mcf5480): Rename to cpu_<foo>. Add m680x0 variants.

	* opcodes/m68k-dis.c (print_insn_m68k): Use
	bfd_m68k_mach_to_features.

	* binutils/readelf.c (get_machine_flags): Add logic for EF_M68K flags.
 2006-02-07 19:01:10 +00:00
David Ung
f1a64f4922 * mips-opc.c: Add I33 masks to these MIPS32R2 instructions: prefx, 
ceil.l.d, ceil.l.s, cvt.d.l, cvt.l.d, cvt.l.s, cvt.s.l, floor.l.d,
floor.l.s, ldxc1, lwxc1, madd.d, madd.s, msub.d, msub.s, nmadd.d,
nmadd.s, nmsub.d, nmsub.s, recip.d, recip.s, round.l.d, rsqrt.d,
rsqrt.s, sdxc1, swxc1, trunc.l.d, trunc.l.s.
 2006-01-26 15:14:57 +00:00
Arnold Metselaar
9e919b5f1d fixes related to indexed operands 2006-01-18 13:48:46 +00:00
Arnold Metselaar
c9021189f6 Use unsigned char to hold data to be disassembled. 2006-01-17 21:15:56 +00:00
Andreas Schwab
d99b646536 PR binutils/1486 
binutils/:
	* configure.in: Don't define DISASSEMBLER_NEEDS_RELOCS.
	* configure: Regenerate.
	* objdump.c (struct objdump_disasm_info): Don't check for
	DISASSEMBLER_NEEDS_RELOCS.
	(objdump_print_addr): Likewise.
	(disassemble_bytes): Check disassembler_needs_relocs from
	disassemble_info at run-time instead of DISASSEMBLER_NEEDS_RELOCS
	at compile-time.
	(disassemble_section): Likewise.
	(disassemble_data): Initialize it.

include/:
	* dis-asm.h (struct disassemble_info): Add
	disassembler_needs_relocs.

objdump/:
	* disassemble.c (disassemble_init_for_target): Set
	disassembler_needs_relocs for bfd_arch_arm.
 2006-01-17 17:39:20 +00:00
Alan Modra
e88d958a4f split changelogs 2006-01-16 23:15:07 +00:00
Paul Brook
c2fe93275a 2006-01-16 Paul Brook <paul@codesourcery.com> 
opcodes/
	* m68k-opc.c(m68k_opcodes): Fix opcodes for ColdFire f?abss,
	f?add?, and f?sub? instructions.

gas/testsuite/
	* gas/m68k/all.exp: Add mcf-fpu.
	* gas/m68k/mcf-fpu.d: New file.
	* gas/m68k/mcf-fpu.s: New file.
 2006-01-16 16:23:30 +00:00
Nick Clifton
32fba81dfe Add new Chinese (simplified) translation 2006-01-16 16:15:17 +00:00
Paul Brook
1b3a26b59c 2006-01-05 Paul Brook <paul@codesourcery.com> 
* m68k-opc.c (m68k_opcodes): Add missing ColdFire fdsqrtd entry.
 2006-01-15 16:35:21 +00:00
DJ Delorie
db313fa614 * m32c-desc.c: Regenerate. 
* m32c-opc.c: Regenerate.
* m32c-opc.h: Regenerate.
 2006-01-06 23:25:36 +00:00
DJ Delorie
54d46aca35 * cgen-ibld.in (extract_normal): Avoid memory range errors. 
* m32c-ibld.c: Regenerated.
 2006-01-03 22:06:18 +00:00
Alan Modra
c85a332d60 * Makefile.am: Run "make dep-am". 
* Makefile.in: Regenerate.
	* po/POTFILES.in: Regenerate.
 2005-12-27 01:20:06 +00:00
Nick Clifton
54758c3e39 Fix PicoJava opcodes 2005-12-22 17:09:39 +00:00
Nathan Sidwell
d031aafbfe Second part of ms1 to mt renaming. 
* bfd/archures.c (bfd_arch_mt): Renamed.
	(bfd_mt_arch): Renamed.
	(bfd_archures_list): Adjusted.
	* bfd/bfd-in2.h: Rebuilt.
	* bfd/config.bfd (mt): Remove special case targ_archs.
	(mt-*-elf): Rename bfd_elf32_mt_vec.
	* bfd/configure: Rebuilt.
	* bfd/configure.in (bfd_elf32_mt_vec): Renamed.
	(selarchs) Remove mt special case.
	* bfd/cpu-mt.c (arch_info_struct): Adjust.
	(bfd_mt_arch): Renamed, adjust.
	* bfd/elf32-mt.c (mt_reloc_type_lookup, mt_info_to_howto_rela,
	mt_elf_relocate_hi16, mt_final_link_relocate, mt_relocate_section,
	mt_elf_howto_table): Renamed, adjusted.
	(mt_elf_gc_mark_hook, mt_elf_gc_sweep_hook, mt_elf_check_relocs,
	elf32_mt_machine, mt_elf_object_p, mt_elf_set_private_flags,
	mt_elf_copy_private_bfd_data, mt_elf_merge_private_bfd_data,
	mt_elf_print_private_bfd_data): Renamed, adjusted.
	(TARGET_BIG_SYM, TARGET_BIG_NAME, ELF_ARCH, ELF_MACHINE_CODE,
	ELF_MAXPAGESIZE, elf_info_to_howto, elf_backend_relocate_section,
	bfd_elf32_bfd_reloc_type_lookup, elf_backend_gc_mark_hook,
	elf_backend_gc_sweep_hook, elf_backend_check_relocs,
	eld_backend_object_p, bfd_elf32_bfd_set_private_flags,
	bfd_elf32_bfd_copy_private_bfd_data,
	bfd_elf32_bfd_merge_private_bfd_data,
	bfd_elf32_bfd_print_private_bfd_data): Adjusted.
	* bfd/libbfd.h: Regenerated.
	* bfd/reloc.c (BFD_RELOC_MT_PC16, BFD_RELOC_MT_HI16,
	BFD_RELOC_MT_LO16, BFD_RELOC_MT_GNU_VTINHERIT,
	BFD_RELOC_MT_GNU_VTENTRY, BFD_RELOC_MT_PCINSN8): Renamed.
	* bfd/targets.c (bfd_elf32_mt_vec): Renamed.
	(_bfd_target_vector): Adjusted.
	* binutils/readelf.c (guess_is_rela): Use EM_MT.
	(dump_relocations, get_machine_name): Adjust.

	* cpu/mt.cpu (define-arch, define-isa): Set name to mt.
	(define-mach): Adjust.
	* cpu/mt.opc (CGEN_ASM_HASH): Update.
	(mt_asm_hash, mt_cgen_insn_supported): Renamed.
	(parse_loopsize, parse_imm16): Adjust.

	* gas/configure: Rebuilt.
	* gas/configure.in (mt): Remove special case.
	* gas/config/tc-mt.c (opcodes/mt-desc.h, opcodes/mt-opc.h): Change
	#includes.
	(mt_insn, mt_mach, mt_mach_bitmask, mt_flags, mt_architectures):
	Rename, adjust.
	(md_parse_option, md_show_usage, md_begin, md_assemble,
	md_cgen_lookup_reloc, md_atof): Adjust.
	(mt_force_relocation, mt_apply_fix, mt_fix_adjustable): Rename, adjust.
	* gas/config/tc-mt.h (TC_MT): Rename.
	(LISTING_HEADER, TARGET_ARCH, TARGET_FORMAT): Adjust.
	(md_apply_fix): Adjust.
	(mt_apply_fix, mt_fix_adjustable, mt_force_relocation): Rename.
	(TC_FORCE_RELOCATION, tc_fix_adjustable): Adjust.

	* gdb/mt-tdep.c (mt_arch_constants, mt_gdb_regnums): Rename, adjust.
	(mt_register_name, mt_register_type, mt_register_reggroup_p,
	mt_return_value, mt_skip_prologue, mt_breapoint_from_pc,
	mt_pseudo_register_read, mt_pseudo_register_write, mt_frame_align,
	mt_registers_info, mt_push_dummy_call, mt_unwind_cache,
	mt_frame_unwind_cache, mt_unwind_pc, mt_unwind_dummy_id,
	mt_frame_this_id, mt_frame_prev_register, mt_frame_base_address,
	mt_frame_unwind, mt_frame_sniffer, mt_frame_base, mt_gdbarch_init,
	_initialize_mt_tdep): Rename & adjust.

	* include/dis-asm.h (print_insn_mt): Renamed.

	* include/elf/common.h (EM_MT): Renamed.
	* include/elf/mt.h: Rename relocs, cpu & other defines.

	* ld/emulparams/elf32mt.sh (ARCH, OUTPUT_FORMAT): Adjust.

	* opcodes/Makefile.am (HFILES, CFILES, ALL_MACHINES): Adjust.
	(stamp-mt): Adjust rule.
	(mt-asm.lo, mt-desc.lo, mt-dis.lo, mt-ibld.lo, mt-opc.lo): Rename &
	adjust.
	* opcodes/Makefile.in: Rebuilt.
	* opcodes/configure: Rebuilt.
	* opcodes/configure.in (bfd_mt_arch): Rename & adjust.
	* opcodes/disassemble.c (ARCH_mt): Renamed.
	(disassembler): Adjust.
	* opcodes/mt-asm.c: Renamed, rebuilt.
	* opcodes/mt-desc.c: Renamed, rebuilt.
	* opcodes/mt-desc.h: Renamed, rebuilt.
	* opcodes/mt-dis.c: Renamed, rebuilt.
	* opcodes/mt-ibld.c: Renamed, rebuilt.
	* opcodes/mt-opc.c: Renamed, rebuilt.
	* opcodes/mt-opc.h: Renamed, rebuilt.

	* sid/Makefile.in: Rebuilt.
	* sid/aclocal.m4: Rebuilt.
	* sid/configure: Rebuilt.
	* sid/sid.spec: Adjust.
	* sid/bsp/Makefile.am: Adjust.
	* sid/bsp/Makefile.in: Rebuilt.
	* sid/bsp/aclocal.m4: Rebuilt.
	* sid/bsp/configrun-sid.in: Adjust.
	* sid/bsp/pregen/Makefile.in: Rebuilt.
	* sid/bsp/pregen/mt-gdb.conf: Renamed & rebuilt.
	* sid/bsp/pregen/mt-gloss.conf: Renamed & rebuilt.
	* sid/bsp/pregen/pregen-configs.in: Adjust.
	* sid/component/aclocal.m4: Rebuilt.
	* sid/component/configure: Rebuilt.
	* sid/component/tconfig.in: Adjust.
	* sid/component/bochs/aclocal.m4: Rebuilt.
	* sid/component/cache/Makefile.in: Rebuilt.
	* sid/component/cgen-cpu/Makefile.in: Rebuilt.
	* sid/component/cgen-cpu/aclocal.m4: Rebuilt.
	* sid/component/cgen-cpu/compCGEN.cxx: Adjust.
	* sid/component/cgen-cpu/configure: Rebuilt.
	* sid/component/cgen-cpu/configure.in: Rebult.
	* sid/component/cgen-cpu/mt/Makefile.am: Adjust.
	* sid/component/cgen-cpu/mt/Makefile.in: Rebuilt.
	* sid/component/cgen-cpu/mt/hw-cpu-mt.txt: Adjust.
	* sid/component/cgen-cpu/mt/mt-cpu.h: Rebuilt.
	* sid/component/cgen-cpu/mt/mt-decode.cxx: Rebuilt.
	* sid/component/cgen-cpu/mt/mt-decode.h: Rebuilt.
	* sid/component/cgen-cpu/mt/mt-defs.h: Rebuilt.
	* sid/component/cgen-cpu/mt/mt-desc.h: Rebuilt.
	* sid/component/cgen-cpu/mt/mt-sem.cxx: Rebuilt.
	* sid/component/cgen-cpu/mt/mt-write.cxx: Rebuilt.
	* sid/component/cgen-cpu/mt/mt.cxx: Adjust.
	* sid/component/cgen-cpu/mt/mt.h: Adjust.
	* sid/component/consoles/Makefile.in: Rebuilt.
	* sid/component/families/aclocal.m4: Rebuilt.
	* sid/component/families/configure: Rebuilt.
	* sid/component/gdb/Makefile.in: Rebuilt.
	* sid/component/gloss/Makefile.in: Rebuilt.
	* sid/component/glue/Makefile.in: Rebuilt.
	* sid/component/ide/Makefile.in: Rebuilt.
	* sid/component/interrupt/Makefile.in: Rebuilt.
	* sid/component/lcd/Makefile.in: Rebuilt.
	* sid/component/lcd/testsuite/Makefile.in: Rebuilt.
	* sid/component/loader/Makefile.am: Rebuilt.
	* sid/component/loader/Makefile.in: Rebuilt.
	* sid/component/mapper/Makefile.in: Rebuilt.
	* sid/component/mapper/testsuite/Makefile.in: Rebuilt.
	* sid/component/memory/Makefile.in: Rebuilt.
	* sid/component/mmu/Makefile.in: Rebuilt.
	* sid/component/parport/Makefile.in: Rebuilt.
	* sid/component/profiling/Makefile.in: Rebuilt.
	* sid/component/rtc/Makefile.in: Rebuilt.
	* sid/component/sched/Makefile.in: Rebuilt.
	* sid/component/testsuite/Makefile.in: Rebuilt.
	* sid/component/timers/aclocal.m4: Rebuilt.
	* sid/component/timers/configure: Rebuilt.
	* sid/component/uart/Makefile.in: Rebuilt.
	* sid/component/uart/testsuite/Makefile.in: Rebuilt.
	* sid/config/config.sub: Adjust.
	* sid/config/info.tcl.in: Adjust.
	* sid/config/sidtargets.m4: Adjust.
	* sid/doc/Makefile.in: Rebuilt.
	* sid/main/dynamic/Makefile.am: Rebuilt.
	* sid/main/dynamic/Makefile.in: Rebuilt.
	* sid/main/dynamic/aclocal.m4: Rebuilt.
	* sid/main/dynamic/configure: Rebuilt.
 2005-12-16 10:23:12 +00:00
DJ Delorie
eda87aba05 * m32c.cpu (jsri): Fix order so register names aren't treated as 
symbols.
(indexb, indexbd, indexbs, indexl, indexld, indexls, indexw,
indexwd, indexws): Fix encodings.

* m32c-desc.c: Regenerate.
* m32c-opc.c: Regenerate.
* m32c-opc.h: Regenerate.
 2005-12-14 03:30:07 +00:00
Nathan Sidwell
4970f871a7 Rename ms1 to mt, part 1 
* config.sub: Replace ms1 arch with mt.  Allow ms1 as alias.
	* configure.in: Replace ms1 arch with mt.
	* configure: Rebuilt.

	* bfd/Makefile.am (ALL_MACHINES, ALL_MACHINES_CFILES,
	BFD32_BACKENDS, BFD32_BACKENDS_CFILES): Replace ms1 with mt.
	(cpu_mt.lo, elf32-mt.lo): Update target and dependency names.
	* bfd/Makefile.in: Rebuilt.
	* bfd/config.bfd: Replace ms1 arch with mt.
	* bfd/configure.in: Replace ms1 files with mt files.
	* bfd/configure: Rebuilt.
	* bfd/elf32-mt.c: Renamed from elf32-ms1.c.  Update include files.
	* bfd/cpu-mt.c: Renamed from cpu-ms1.c.

	* cpu/mt.cpu: Rename from ms1.cpu.
	* cpu/mt.opc: Rename from ms1.opc.

	* binutils/Makefile.am: Replace ms1 files with mt files.
	* binutils/Makefile.in: Rebuilt.
	* binutils/readelf.c (elf/mt.h): Adjust #include.

	* gas/configure.in: Replace ms1 arch with mt arch.
	* gas/configure: Rebuilt.
	* gas/configure.tgt: Replace ms1 arch with mt arch.
	* gas/config/tc-mt.c: Renamed from tc-ms1.c: Update include files.

	* gas/doc/Makefile.am (CPU_DOCS): Replace ms1 files with mt files.
	* gas/doc/Makefile.in: Rebuilt.

	* gas/testsuite/gas/mt: Renamed from ms1 dir.  Update file names as
	needed.
	* gas/testsuite/gas/mt/errors.exp: Replace ms1 arch with mt arch.
	* gas/testsuite/gas/mt/mt.exp: Replace ms1 arch with mt arch.
	* gas/testsuite/gas/mt/relocs.exp: Replace ms1 arch with mt arch.

	* gdb/configure.tgt: Replace ms1 arch with mt arch.
	* gdb/config/mt: Renamed from ms1 dir.  Update file names as needed.
	* gdb/config/mt/mt.mt (TDEPFILES): Replace ms1 file with mt file.

	* include/elf/mt.h: Renamed from ms1.h

	* ld/Makefile.am (ALL_EMULATIONS): Replace ms1 files with mt files.
	(eelf32mt.c): Update target name and dependencies.
	* ld/Makefile.in: Rebuilt.
	* ld/configure.tgt: Replace ms1 arch with mt arch.
	* ld/emulparams/elf32mt.sh: Renamed from elf32ms1.sh. Update
	comment.

	* libgloss/configure.in: Replace ms1 arch with mt arch.
	* libgloss/configure: Rebuilt.
	* libgloss/mt: Renamed from ms1 dir.

	* newlib/configure.host: Replace ms1 arch with mt arch.
	* newlib/libc/machine/mt: Renamed from ms1 dir.

	* opcodes/Makefile.am (CLEANFILES, CGEN_CPUS, MT_DEPS): Replace ms1
	with mt.
	* opcodes/Makefile.in: Rebuilt.
	* opcodes/configure.in: Replace ms1 files with mt files.
	* opcodes/configure: Rebuilt.

	* sid/component/cgen-cpu/mt: Renamed from ms1 dir.  Update file
	names as appropriate.
	* sid/component/cgen-cpu/mt/Makefile.am: Replace ms1 files with mt
	files.
	* sid/component/cgen-cpu/mt/Makefile.in: Rebuilt.
 2005-12-12 11:25:08 +00:00
Jan Beulich
272c92178a opcodes/ 
2005-12-08  Jan Beulich  <jbeulich@novell.com>

	* i386-dis.c (MAXLEN): Reduce to architectural limit.
	(fetch_data): Check for sufficient buffer size.
 2005-12-08 15:21:05 +00:00
Jan Beulich
422673a90b opcodes/ 
2005-12-08  Jan Beulich  <jbeulich@novell.com>

	* i386-dis.c (OP_ST): Remove prefix in Intel mode.
 2005-12-08 11:28:11 +00:00
Alan Modra
6e50d963b0 * i386-dis.c (dofloat): Handle %rip-relative floating point addressing. 2005-12-08 09:59:40 +00:00
Hans-Peter Nilsson
cf54500c3c * cris-opc.c (cris_opcodes) <"move" "s,P">: Define using 
MOVE_M_TO_PREG_OPCODE and MOVE_M_TO_PREG_ZBITS instead of constants.
 2005-12-07 12:56:13 +00:00
H.J. Lu
cb712a9ecd gas/ 
2005-12-06  H.J. Lu  <hongjiu.lu@intel.com>

	PR gas/1874
	* config/tc-i386.c (match_template): Handle monitor.
	(process_suffix): Likewise.

gas/testsuite/

2005-12-06  H.J. Lu  <hongjiu.lu@intel.com>

	PR gas/1874
	* gas/i386/i386.exp: Add x86-64-prescott for 64bit.

	* gas/i386/prescott.s: Test address size override for monitor.
	* gas/i386/prescott.d: Updated.

	* gas/i386/x86-64-prescott.d: New file.
	* gas/i386/x86-64-prescott.s: Likewise.

include/opcode/

2005-12-06  H.J. Lu  <hongjiu.lu@intel.com>

	PR gas/1874
	* i386.h (i386_optab): Add 64bit support for monitor and mwait.

opcodes/

2005-12-06  H.J. Lu  <hongjiu.lu@intel.com>

	PR gas/1874
	* i386-dis.c (address_mode): New enum type.
	(address_mode): New variable.
	(mode_64bit): Removed.
	(ckprefix): Updated to check address_mode instead of mode_64bit.
	(prefix_name): Likewise.
	(print_insn): Likewise.
	(putop): Likewise.
	(print_operand_value): Likewise.
	(intel_operand_size): Likewise.
	(OP_E): Likewise.
	(OP_G): Likewise.
	(set_op): Likewise.
	(OP_REG): Likewise.
	(OP_I): Likewise.
	(OP_I64): Likewise.
	(OP_OFF): Likewise.
	(OP_OFF64): Likewise.
	(ptr_reg): Likewise.
	(OP_C): Likewise.
	(SVME_Fixup): Likewise.
	(print_insn): Set address_mode.
	(PNI_Fixup): Add 64bit and address size override support for
	monitor and mwait.
 2005-12-06 12:40:57 +00:00
Hans-Peter Nilsson
cdedc9f07f * cris-dis.c (bytes_to_skip): Handle new parameter prefix_matchedp. 
(print_with_operands): Check for prefix when [PC+] is seen.
 2005-12-05 23:27:01 +00:00
Dave Brolley
3609e0feb6 2005-12-02 Dave Brolley <brolley@redhat.com> 
* configure.in (cgen_files): Add cgen-bitset.lo.
        (ta): Add cgen-bitset.lo when arch==bfd_cris_arch.
        * Makefile.am (CFILES): Add cgen-bitset.c.
        (ALL_MACHINES): Add cgen-bitset.lo.
        (cgen-bitset.lo): New target.
        * cgen-opc.c (cgen_bitset_create, cgen_bitset_init, cgen_bitset_clear)
        (cgen_bitset_add, cgen_bitset_set, cgen_bitset_contains)
        (cgen_bitset_compare, cgen_bitset_intersect_p, cgen_bitset_copy)
        (cgen_bitset_union): Moved from here ...
        * cgen-bitset.c: ... to here. New file.
        * Makefile.in: Regenerated.
        * configure: Regenerated.
 2005-12-02 20:09:42 +00:00
Jim Wilson
aa2273ba99 Fix 32-bit host/target --enable-targets=all build failure from Doug Evans. 
* ia64-gen.c (_opcode_int64_low, _opcode_int64_high,
opcode_fprintf_vma): New.
(print_main_table): New opcode_fprintf_vma instead of fprintf_vma.
 2005-11-23 04:58:37 +00:00
Alan Modra
ce7a772b48 * ppc-opc.c (powerpc_opcodes): Add frin,friz,frip,frim. Correct 
frsqrtes.
 2005-11-15 21:33:04 +00:00
Thiemo Seufer
0499d65b9b * mips.h: Assign 'm'/'M' codes to MIPS16e save/restore 
instructions.  Define MIPS16_ALL_ARGS and MIPS16_ALL_STATICS for
        save/restore encoding of the args field.

        * mips16-opc.c: Add MIPS16e save/restore opcodes.
        * mips-dis.c (print_mips16_insn_arg): Handle printing of 'm'/'M'
        codes for save/restore.

        * config/tc-mips.c (mips16_ip): Add handling of 'm' and 'M' codes
        for the MIPS16e save/restore instructions.

        * gas/mips/mips.exp: Run new save/restore tests.
        * gas/testsuite/gas/mips/mips16e-save.s: New test for generating
        different styles of save/restore instructions.
        * gas/testsuite/gas/mips/mips16e-save.d: New.
 2005-11-14 02:25:39 +00:00
Andreas Schwab
dc82c973b3 * m68k-dis.c (print_insn_m68k): Only match FPU insns with 
coprocessor ID 1.
 2005-11-10 14:32:28 +00:00
Nick Clifton
dbb33a874e * m32c-desc.c: Regenerated. 2005-11-08 16:16:47 +00:00
Nathan Sidwell
6f84a2a649 bfd: 
Add ms2.
	* archures.c (bfd_mach_ms2): Define.
	* cpu-ms1.c (arch_info_struct): Add ms2 stanza.
	* elf32-ms1.c (elf32_ms1_machine): Add ms2 case.
	(ms1_elf_merge_private_bfd_data): Remove unused variables.  Add
	correct merging logic, with workaround.
	(ms1_elf_print_private_bfd_data): Add ms2 case.
	* reloc.c (BFD_RELOC_MS1_PCINSN8): Add ms2 specific reloc.
	* libbfd.h: Regenerated.
	* bfd-in2.h: Regenerated.

cpu:
	Add ms2
	* ms1.cpu (ms2, ms2bf): New architecture variant, cpu, machine and
	model.
	(f-uu8, f-uu1, f-imm16l, f-loopo, f-cb1sel, f-cb2sel, f-cb1incr,
	f-cb2incr, f-rc3): New fields.
	(LOOP): New instruction.
	(JAL-HAZARD): New hazard.
	(imm16o, loopsize, imm16l, rc3, cb1sel, cb2sel, cb1incr, cb2incr):
	New operands.
	(mul, muli, dbnz, iflush): Enable for ms2
	(jal, reti): Has JAL-HAZARD.
	(ldctxt, ldfb, stfb): Only ms1.
	(fbcb): Only ms1,ms1-003.
	(wfbinc, mefbinc, wfbincr, mwfbincr, fbcbincs, mfbcbincs,
	fbcbincrs, mfbcbincrs): Enable for ms2.
	(loop, loopu, dfbc, dwfb, fbwfb, dfbr): New ms2 insns.
	* ms1.opc (parse_loopsize): New.
	(parse_imm16): hi16/lo16 relocs are applicable to IMM16L.
	(print_pcrel): New.

gas:
	Add ms2.
	* config/tc-ms1.c (ms1_mach_bitmask): Initialize to MS1.
	(ms1_architectures): Add ms2.
	(md_parse_option): Add ms2.
	(md_show_usage): Add ms2.
	(md_assemble): Add JAL_HAZARD detection logic.
	(md_cgen_lookup_reloc): Add MS1_OPERAND_LOOPSIZE case.
	* doc/c-ms1.texi: New.
	* doc/all.texi: Add MS1.
	* doc/Makefile.am (CPU_DOCS): Add c-ms1.texi.
	* doc/Makefile.in: Rebuilt.
	* doc/Makefile: Rebuilt.

gas/testsuite:
	Add ms2.
	* gas/ms1/allinsn.d: Adjust pcrel disassembly.
	* gas/ms1/errors.exp: Fix target triplet.
	* gas/ms1/ms1-16-003.d: Adjust pcrel disassembly.
	* gas/ms1/ms1-16-003.s: Tweak label.
	* gas/ms1/ms1.exp: Adjust target triplet.  Add ms2 test.
	* gas/ms1/ms2.d, gas/ms1/ms2.s: New.
	* gas/ms1/relocs.d: Adjust expected machine name and pcrel
	disassembly.
	* gas/ms1/relocs.exp: Adjust target triplet.

include:
	Add ms2.
	* elf/ms1.h (EF_MS1_CPU_MS2): New.


opcodes:
	Add ms2.
	* ms1-asm.c, ms1-desc.c, ms1-desc.h, ms1-dis.c, ms1-ibld.c,
	ms1-opc.c, ms1-opc.h: Regenerated.
 2005-11-08 11:15:13 +00:00
Steve Ellcey
a541e3cedd * configure: Regenerate after modifying bfd/warning.m4. 2005-11-07 22:21:48 +00:00
Alan Modra
3e7d61b225 * i386-dis.c (ckprefix): Handle rex on fwait. Don't print 
ignored rex prefixes here.
	(print_insn): Instead, handle them similarly to fwait followed
	by non-fp insns.
 2005-11-07 00:19:12 +00:00
H.J. Lu
a92e0d0a05 2005-11-02 H.J. Lu <hongjiu.lu@intel.com> 
* iq2000-desc.c: Regenerated.
	* iq2000-desc.h: Likewise.
	* iq2000-dis.c: Likewise.
	* iq2000-opc.c: Likewise.
 2005-11-02 16:58:31 +00:00
Paul Brook
36b0c57df5 2005-11-02 Paul Brook <paul@codesourcery.com> 
* arm-dis.c (print_insn_thumb32): Word align blx target address.
 2005-11-02 16:53:11 +00:00
Alan Modra
9a2ff3f50c * arm-dis.c (print_insn): Warning fix. 2005-10-31 06:10:33 +00:00
H.J. Lu
9e5169a8fa ld/ 
binutils/
opcodes/

2005-10-30  H.J. Lu  <hongjiu.lu@intel.com>

	* Makefile.am: Run "make dep-am".
	* Makefile.in: Regenerated.

	* dep-in.sed: Replace " ./" with " ".
 2005-10-30 17:40:28 +00:00
Dave Brolley
fb53f5a81a 2005-10-28 Dave Brolley <brolley@redhat.com> 
* All CGEN-generated sources: Regenerate.

        Contribute the following changes:
        2005-09-19  Dave Brolley  <brolley@redhat.com>

        * disassemble.c (disassemble_init_for_target): Add 'break' to case for
        bfd_arch_tic4x. Use cgen_bitset_create and cgen_bitset_set for
        bfd_arch_m32c case.

        2005-02-16  Dave Brolley  <brolley@redhat.com>

        * cgen-dis.in: Rename CGEN_ISA_MASK to CGEN_BITSET. Rename
        cgen_isa_mask_* to cgen_bitset_*.
        * cgen-opc.c: Likewise.

        2003-11-28  Richard Sandiford  <rsandifo@redhat.com>

        * cgen-dis.in (print_insn_@arch@): Fix comparison with cached isas.
        * *-dis.c: Regenerate.

        2003-06-05  DJ Delorie  <dj@redhat.com>

        * cgen-dis.in (print_insn_@arch@): Copy prev_isas, don't assign
        it, as it may point to a reused buffer. Set prev_isas when we
        change cpus.

        2002-12-13  Dave Brolley  <brolley@redhat.com>

        * cgen-opc.c (cgen_isa_mask_create): New support function for
        CGEN_ISA_MASK.
        (cgen_isa_mask_init): Ditto.
        (cgen_isa_mask_clear): Ditto.
        (cgen_isa_mask_add): Ditto.
        (cgen_isa_mask_set): Ditto.
        (cgen_isa_supported): Ditto.
        (cgen_isa_mask_compare): Ditto.
        (cgen_isa_mask_intersection): Ditto.
        (cgen_isa_mask_copy): Ditto.
        (cgen_isa_mask_combine): Ditto.
        * cgen-dis.in (libiberty.h): #include it.
        (isas): Renamed from 'isa' and now (CGEN_ISA_MASK *).
        (print_insn_@arch@): Use CGEN_ISA_MASK and support functions.
        * Makefile.am (CGENDEPS): Add utils-cgen.scm and attrs.scm.
        * Makefile.in: Regenerated.
 2005-10-28 19:49:22 +00:00
DJ Delorie
c6552317c1 * m32c.cpu (Imm-8-s4n, Imm-12-s4n): New. 
(arith-jnz16-imm4-dst-defn, arith-jnz32-imm4-dst-defn,
arith-jnz-imm4-dst-mach, arith-jnz-imm4-dst): Keep track of which
imm operand is needed.
(adjnz, sbjnz): Pass the right operands.
(unary-insn-defn, unary16-defn, unary32-defn, unary-insn-mach,
unary-insn): Add -g variants for opcodes that need to support :G.
(not.BW:G, push.BW:G): Call it.
(stzx16-imm8-imm8-dsp8sb, stzx16-imm8-imm8-dsp8fb,
stzx16-imm8-imm8-abs16): Fix operand typos.
* m32c.opc (m32c_asm_hash): Support bnCND.
(parse_signed4n, print_signed4n): New.

* m32c-asm.c: Regenerate.
* m32c-desc.c: Regenerate.
* m32c-desc.h: Regenerate.
* m32c-dis.c: Regenerate.
* m32c-ibld.c: Regenerate.
* m32c-opc.c: Regenerate.
* m32c-opc.h: Regenerate.
 2005-10-27 23:54:17 +00:00
DJ Delorie
f75eb1c004 * m32c.cpu (f-dsp-8-s24, Dsp-8-s24): New. 
(mov-dspsp-dst-defn, mov-src-dspsp-defn, mov16-dspsp-dst-defn,
mov16-src-dspsp-defn, mov32-dspsp-dst-defn, mov32-src-dspsp-defn):
dsp8[sp] is signed.
(mov.WL:S #imm,A0/A1): dsp24 is signed (i.e. -0x800000..0xffffff).
(mov.BW:S r0,r1): Fix typo r1l->r1.
(tst): Allow :G suffix.
* m32c.opc (parse_signed24): New, for -0x800000..0xffffff.

* m32c-asm.c: Regenerate.
* m32c-desc.c: Regenerate.
* m32c-desc.h: Regenerate.
* m32c-dis.c: Regenerate.
* m32c-ibld.c: Regenerate.
* m32c-opc.c: Regenerate.
* m32c-opc.h: Regenerate.
 2005-10-26 14:59:12 +00:00
Paul Brook
f1022c90ad 2005-10-26 Paul Brook <paul@codesourcery.com> 
gas/
	* config/tc-arm.c (insns): Correct "sel" entry.
gas/testsuite/
	* gas/arm/archv6.d: Adjust expected output.
opcodes/
	* arm-dis.c (arm_opcodes): Correct "sel" entry.
 2005-10-26 14:09:29 +00:00
Alan Modra
e277c00b2d * m32r.opc (parse_hi16): Do not assume a 32-bit host word size. 2005-10-26 07:49:05 +00:00
DJ Delorie
92e0a9414c * m32c.cpu (add16-bQ-sp,add16-wQ-sp): Fix to allow either width by 
making one a macro of the other.

* m32c-asm.c: Regenerate.
* m32c-desc.c: Regenerate.
* m32c-desc.h: Regenerate.
* m32c-dis.c: Regenerate.
* m32c-ibld.c: Regenerate.
* m32c-opc.c: Regenerate.
* m32c-opc.h: Regenerate.
 2005-10-25 18:52:02 +00:00
Nick Clifton
3c9b82baee Add support for the Z80 processor family 2005-10-25 17:40:19 +00:00
Alan Modra
3caac5b897 Regenerate 2005-10-25 02:20:17 +00:00
Jan Beulich
6a2375c6b2 include/opcode/ 
2005-10-24  Jan Beulich  <jbeulich@novell.com>

	* ia64.h (enum ia64_opnd): Move memory operand out of set of
	indirect operands.

bfd/
2005-10-24  Jan Beulich  <jbeulich@novell.com>

	* cpu-ia64-opc.c (elf64_ia64_operands): Move memory operand out of
	set of indirect operands.

gas/
2005-10-24  Jan Beulich  <jbeulich@novell.com>

	* config/tc-ia64.c (enum reg_symbol): Delete IND_MEM.
	(dot_rot): Change type of num_* variables. Check for positive count.
	(ia64_optimize_expr): Re-structure.
	(md_operand): Check for general register.

gas/testsuite/
2005-10-24  Jan Beulich  <jbeulich@novell.com>

	* gas/ia64/index.[sl]: New.
	* gas/ia64/rotX.[sl]: New.
	* gas/ia64/ia64.exp: Run new tests.

opcodes/
2005-10-24  Jan Beulich  <jbeulich@novell.com>

	* ia64-asmtab.c: Regenerate.
 2005-10-24 07:42:50 +00:00
DJ Delorie
a1a280bb84 [cpu] 
* m32c.cpu (lde, ste): Add dsp[a0] and [a1a] addressing.
(indexb, indexbd, indexbs, indexw, indexwd, indexws, indexl,
indexld, indexls): .w variants have `1' bit.
(rot32.b): QI, not SI.
(rot32.w): HI, not SI.
(xchg16): HI for .w variant.

[opcodes]
* m32c-asm.c: Regenerate.
* m32c-desc.c: Regenerate.
* m32c-desc.h: Regenerate.
* m32c-dis.c: Regenerate.
* m32c-ibld.c: Regenerate.
* m32c-opc.c: Regenerate.
* m32c-opc.h: Regenerate.
 2005-10-22 00:03:13 +00:00
Nick Clifton
b7d4853035 bfin-dis.c: Tidy up code, removing redundant constructs. 2005-10-21 16:28:18 +00:00
Martin Schwidefsky
8dd744b6c0 * s390-opc.txt: Add unnormalized hfp multiply and multiply-and-add 
instructions.
 2005-10-19 15:05:10 +00:00
Nick Clifton
e74eb924c2 * m32r.opc (parse_slo16): Fix bad application of previous patch. 2005-10-19 14:44:17 +00:00
Jie Zhang
471e4e36fc * bfin-dis.c (print_insn_bfin): Do proper endian transform when 
reading instruction from memory.
 2005-10-18 16:39:41 +00:00
Nick Clifton
5e03663f3d m32r.opc (parse_slo16): Better version of previous patch. 2005-10-18 07:53:17 +00:00
Nick Clifton
ab7c9a26e5 m32r.opc (parse_slo16): Do not assume a 32-bit host word size. 2005-10-14 08:33:27 +00:00
Richard Earnshaw
19590ef7f6 2005-10-08 James Lemke <jim@wasabisystems.com> 
* arm-dis.c (coprocessor_opcodes): Fix mask for various Maverick CDP
	operations.
 2005-10-08 14:52:07 +00:00
Daniel Jacobowitz
6edfbbad08 bfd/ 
* elf32-arm.c (elf32_arm_check_relocs): Avoid aliasing warnings from
	GCC.
	(elf32_arm_size_dynamic_sections): Likewise.
	* ecofflink.c (bfd_ecoff_debug_one_external): Likewise.
	* elf32-hppa.c (elf32_hppa_check_relocs): Likewise.
	* elf32-m32r.c (m32r_elf_check_relocs): Likewise.
	* elf32-m68k.c (elf_m68k_check_relocs): Likewise.
	* elf32-ppc.c (ppc_elf_check_relocs): Likewise.
	* elf32-s390.c (elf_s390_check_relocs): Likewise.
	(elf_s390_size_dynamic_sections): Likewise.
	* elf32-sh.c (sh_elf_check_relocs): Likewise.
	* elf64-ppc.c (ppc64_elf_check_relocs, dec_dynrel_count)
	(ppc64_elf_size_dynamic_sections): Likewise.
	* elf64-s390.c (elf_s390_check_relocs): Likewise.
	(elf_s390_size_dynamic_sections): Likewise.
	* elfxx-mips.c (_bfd_mips_elf_finish_dynamic_sections): Likewise.
	* elfxx-sparc.c (_bfd_sparc_elf_check_relocs): Likewise.
	(_bfd_sparc_elf_size_dynamic_sections): Likewise.
	* ieee.c (ieee_slurp_section_data): Likewise.
	* oasys.c (oasys_slurp_section_data): Likewise.
opcodes/
	* ppc-dis.c (struct dis_private): Remove.
	(powerpc_dialect): Avoid aliasing warnings.
	(print_insn_big_powerpc, print_insn_little_powerpc): Likewise.
 2005-10-06 19:21:14 +00:00
Nick Clifton
095f284399 oops - delayed commit for addtion of Irish translation for gprof and opcodes 2005-10-03 10:52:38 +00:00