Add nps400 to the list of acceptable values for the -mcpu command line
switch, and to the .cpu directive.
I've added an extra cross reference from -mcpu to .cpu to improve
navigation of the documentation.
gas/ChangeLog:
* doc/c-arc.texi (ARC Options): Add nps400 to list of valus for
-mcpu. Add cross reference to .cpu directive from -mcpu option.
(ARC Directives): Add NPS400 to .cpu directive list.
The RAS extension was introduced as part of the ARMv8.2 architecture
where it is a required feature. It is also available as an optional
feature for ARMv8 and ARMv8.1. In binutils, the RAS extension is
currently enabled by default for -march=armv8.2-a but is not available
for -march=armv8 or -march=armv8.1-a.
This patch adds the feature extension '+ras' to enable the RAS extension
for ARMv8 and ARMv8.1, it is disabled by default.
gas/
2016-04-20 Matthew Wahab <matthew.wahab@arm.com>
* config/tc-aarch64.c (aarch64_features): Add "ras".
* doc/c-aarch64.texi (AArch64 Extensions): Add "ras".
* testsuite/gas/aarch64/armv8-ras-1.d: New.
* testsuite/gas/aarch64/armv8-ras-1.s: New.
* testsuite/gas/aarch64/illegal-ras-1.d: New.
* testsuite/gas/aarch64/illegal-ras-1.s: New.
Change-Id: I824fb9bc8cf846bcc03aa17a726efb1350d78b9d
This reverts commit 9a452709fe.
This change was committed as obvious, but it has been rightly been
pointed out to me that this change is not obvious, and as such I am
reverting it.
gas/ChangeLog:
Revert prevous change.
* config/tc-arc.c (arc_option): Make .cpu directive
case-sensitive again.
Presumably this was supposed to be regname[sizeof (regname) - 1] but was typoed
to regname[sizeof (rename) - 1]. However that should be unnecessary because
sprintf should null terminate. As is this assignment is invalid ISO C because
rename refers to the function rename (), and sizeof on functions is undefined.
In GNU C C the size of functions is 1 so the expression is the same as
regname[0]. The following call to sprintf () clearly will over right that, so
the statement either has no effect or is invalid. Given that it seems safe to
just remove it. While we are there correct the size of regname, and switch
from snprintf to sprintf since we know the exact length of the result.
gas/ChangeLog:
2016-04-15 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
* config/tc-mips.c (md_begin): Remove useless assignment.
They are only used in one file, so we might as well restrict there scope to
that file, and theoretically this might slightly improve compilers ability to
optimize usage of these variables.
gas/ChangeLog:
2016-04-14 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
* config/tc-nios2.c (nios2_as_options): Make file static.
* config/tc-ppc.c (toc_reloc_ypes): Likewise.
* config/tc-sparc.c (native_op_table): Likewise.
Add support for arc/nps400 cmem instructions, these load and store
instructions are hard-wired to access "0x57f00000 + 16-bit-offset".
Supporting this relocation required some additions to the arc relocation
handling in the bfd library, as well as the standard changes required to
add a new relocation type.
There's a test of the new instructions in the assembler, and a test of
the relocation in the linker.
bfd/ChangeLog:
* reloc.c: Add BFD_RELOC_ARC_NPS_CMEM16 entry.
* bfd-in2.h: Regenerate.
* libbfd.h: Regenerate.
* elf32-arc.c: Add 'opcode/arc.h' include.
(struct arc_relocation_data): Add symbol_name.
(arc_special_overflow_checks): New function.
(arc_do_relocation): Use arc_special_overflow_checks, reindent as
required, add an extra comment.
(elf_arc_relocate_section): Setup symbol_name in reloc_data.
gas/ChangeLog:
* testsuite/gas/arc/nps400-3.d: New file.
* testsuite/gas/arc/nps400-3.s: New file.
include/ChangeLog:
* elf/arc-reloc.def: Add ARC_NPS_CMEM16 reloc.
* opcode/arc.h (NPS_CMEM_HIGH_VALUE): Define.
ld/ChangeLog:
* testsuite/ld-arc/arc.exp: New file.
* testsuite/ld-arc/nps-1.s: New file.
* testsuite/ld-arc/nps-1a.d: New file.
* testsuite/ld-arc/nps-1b.d: New file.
* testsuite/ld-arc/nps-1b.err: New file.
opcodes/ChangeLog:
* arc-nps400-tbl.h: Add xldb, xldw, xld, xstb, xstw, and xst
instructions.
* arc-opc.c (insert_nps_cmem_uimm16): New function.
(extract_nps_cmem_uimm16): New function.
(arc_operands): Add NPS_XLDST_UIMM16 operand.
We were running a slightly different set of assembler tests on big and
little endian arc targets. This commit unifies the set of tests run.
gas/ChangeLog:
* testsuite/gas/arc/add_s-err.s: Update target pattern.
* testsuite/gas/arc/warn.s: Likewise.
* testsuite/gas/elf/elf.exp: Run test for arc.
PR target/19938
bfd * elf-bbfd.h (struct elf_backend_data): New field:
elf_strtab_flags.
New field: elf_backend_set_special_section_info_and_link
* elfxx-target.h (elf_backend_strtab_flags): Define if not already
defined.
(elf_backend_set_special_section_info_and_link): Define if not
already defined.
(elfNN_bed): Use elf_backend_set_special_section_info_and_link and
elf_backend_strtab_flags macros to initialise fields in structure.
* elf.c (_bfd_elf_make_section_from_shdr): Check for SHF_STRINGS
being set even if SHF_MERGE is not set.
(elf_fake_sections): Likewise.
(section_match): New function. Matches two ELF sections based
upon fixed characteristics.
(find_link): New function. Locates a section in a BFD that
matches a section in a different BFD.
(_bfd_elf_copy_private_bfd_data): Copy the sh_info and sh_link
fields of reserved sections.
(bfd_elf_compute_section_file_positions): Set the flags for the
.shstrtab section based upon the elf_strtab_flags field in the
elf_backend_data structure.
(swap_out_syms): Likewise for the .strtab section.
* elflink.c (bfd_elf_final_link): Set the flags for the
.strtab section based upon the elf_strtab_flags field in the
elf_backend_data structure.
* elf32-i386.c (elf32_i386_set_special_info_link): New function.
(elf_backend_strtab_flags): Set to SHF_STRINGS for Solaris
targets.
(elf_backend_set_special_section_info_and_link): Define for
Solaris targets.
* elf32-sparc.c: Likewise.
* elf64-x86-64.c: Likewise.
binutils* testsuite/binutils-all/i386/compressed-1b.d: Allow for the
string sections possibly having the SHF_STRINGS flag bit set.
* testsuite/binutils-all/i386/compressed-1c.d: Likewise.
* testsuite/binutils-all/readelf.s: Likewise.
* testsuite/binutils-all/readelf.s-64: Likewise.
* testsuite/binutils-all/x86-64/compressed-1b.d: Likewise.
* testsuite/binutils-all/x86-64/compressed-1c.d: Likewise.
gas * testsuite/gas/i386/ilp32/x86-64-unwind.d: Allow for the string
sections possibly having the SHF_STRINGS flag bit set.
* testsuite/gas/i386/x86-64-unwind.d: Likewise.
gas/
2016-04-12 Claudiu Zissulescu <claziss@synopsys.com>
* config/tc-arc.c (mach_type_specified_p): Change type to
bfd_boolean.
(arc_option): Set private flags when parsing cpu pseudo-op.
(md_parse_option): Set mach_type_specified_p to TRUE.
PR target/19937
opcode * v850-opc.c (v850_opcodes): Correct masks for long versions of
the LD.B and LD.BU instructions.
gas * testsuite/gas/v850/pr19937.s: New test.
* testsuite/gas/v850/pr19937.d: New test control file.
* testsuite/gas/v850/basic.exp: Run the new test.
Weak symbols can be preempted at link time so always choose the longer
sequence in branch relaxation, according to the relaxation level chosen,
so that any symbol finally used as the branch target is reachable.
2016-04-13 Maciej W. Rozycki <macro@imgtec.com>
Andrew Bennett <andrew.bennett@imgtec.com>
gas/
* config/tc-mips.c (relaxed_branch_length): Use the long
sequence where the target is a weak symbol.
(relaxed_micromips_32bit_branch_length): Likewise.
(relaxed_micromips_16bit_branch_length): Likewise.
* testsuite/gas/mips/branch-weak-1.d: New test.
* testsuite/gas/mips/branch-weak-2.d: New test.
* testsuite/gas/mips/branch-weak-3.d: New test.
* testsuite/gas/mips/branch-weak-4.d: New test.
* testsuite/gas/mips/branch-weak-5.d: New test.
* testsuite/gas/mips/branch-weak.l: New stderr output.
* testsuite/gas/mips/branch-weak.s: New test source.
* testsuite/gas/mips/mips.exp: Run the new tests.
Where branch relaxation is enabled emit the long sequence for branches
whose distance cannot be determined, i.e. to symbols that are undefined
or in a different segment. These symbols are only resolved at link time
and therefore the longer sequence ensures the branch target is in range,
which cannot be guaranteed with a direct branch.
This is the opposite to the current implementation, originally proposed
here: <https://sourceware.org/ml/binutils/2002-09/msg00218.html>. The
proposal was then extensively discussed before the final version was
posted here: <https://sourceware.org/ml/binutils/2002-10/msg00191.html>
and eventually committed:
commit 4a6a3df43d
Author: Alexandre Oliva <aoliva@redhat.com>
Date: Sat Oct 12 05:23:33 2002 +0000
The case considered here was not commented in the review however and the
original version remains. With branch relaxation enabled it makes more
sense to do it consistently, so that all code impure with respect to
branch distances can be linked. Direct branches are still produced for
the cases concerned where branch relaxation is disabled, which is the
default.
gas/
* config/tc-mips.c (relaxed_branch_length): Use the long
sequence where the distance cannot be determined.
(relaxed_micromips_32bit_branch_length): Likewise.
* testsuite/gas/mips/branch-extern-1.d: New test.
* testsuite/gas/mips/branch-extern-2.d: New test.
* testsuite/gas/mips/branch-extern-3.d: New test.
* testsuite/gas/mips/branch-extern-4.d: New test.
* testsuite/gas/mips/branch-extern.l: New stderr output.
* testsuite/gas/mips/branch-extern.s: New test source.
* testsuite/gas/mips/branch-section-1.d: New test.
* testsuite/gas/mips/branch-section-2.d: New test.
* testsuite/gas/mips/branch-section-3.d: New test.
* testsuite/gas/mips/branch-section-4.d: New test.
* testsuite/gas/mips/branch-section.l: New stderr output.
* testsuite/gas/mips/branch-section.s: New test source.
* testsuite/gas/mips/mips.exp: Run the new tests.
gas/
* config/tc-mips.c (s_option): Sanitize `.option picX'
pseudo-op.
* testsuite/gas/mips/option-pic-1.d: New test.
* testsuite/gas/mips/option-pic-2.l: New list test.
* testsuite/gas/mips/option-pic-1.s: New test source.
* testsuite/gas/mips/option-pic-2.s: New test source.
* testsuite/gas/mips/mips.exp: Run the new tests.
gas/
* config/tc-mips.c (s_option): Reject `.option picX' if VxWorks
PIC.
* testsuite/gas/mips/option-pic-vxworks-1.l: New list test.
* testsuite/gas/mips/option-pic-vxworks-2.l: New list test.
* testsuite/gas/mips/option-pic-vxworks-1.s: New test source.
* testsuite/gas/mips/option-pic-vxworks-2.s: New test source.
* testsuite/gas/mips/mips.exp: Run the new tests.
Add some new control instructions to the opcodes library, and a new test
for these new instructions to the assembler. The new instructions use
an instruction flag longer than any seen before (on arc), and so the max
flag length is extended to accommodate this.
gas/ChangeLog:
* config/tc-arc.h (MAX_FLAG_NAME_LENGTH): Increase to 7.
* testsuite/gas/arc/nps400-2.d: New file.
* testsuite/gas/arc/nps400-2.s: New file.
opcodes/ChangeLog:
* arc-nps400-tbl.h: Add schd, sync, and hwschd instructions.
* arc-opc.c (arc_flag_operands): Add new flags.
(arc_flag_classes): Add new classes.
This commit completes support for having multiple instructions with the
same mnemonic in non-contiguous blocks within the arc_opcodes table.
The commit adds an iterator mechanism for the arc_opcode_hash_entry
structure, which is then used in find_opcode_match to consider all
arc_opcode entries with the same mnemonic, even when these instructions
are stored in non-contiguous blocks.
I extend the comment on the arc_opcodes table to discuss how entries
within the table are organised, and to mention how instructions can be
split into multiple groups if needed, but that the table is still
searched in table order.
There should be no user visible changes after this commit.
gas/ChangeLog:
* config/tc-arc.c (struct arc_opcode_hash_entry_iterator): New
structure.
(arc_opcode_hash_entry_iterator_init): New function.
(arc_opcode_hash_entry_iterator_next): New function.
(find_opcode_match): Iterate over all arc_opcode entries
referenced by the arc_opcode_hash_entry passed in as a parameter.
opcodes/ChangeLog:
* arc-opc.c (arc_opcodes): Extend comment to discus table layout.
Building on earlier commits, this commit moves along support for having
multiple arc_opcode entries in the arc_opcodes table that have the same
mnemonic (name) field, but are not stored in a contiguous block in the
table.
In this commit we support looking up the arc_opcode_hash_entry from the
hash table, and passing this along to the find_opcode_match function,
which then finds the specific arc_opcode that we're assembling. We
still don't actually support the multiple chains of arc_opcode entries
in this commit, but the limitation is now isolated to the
find_opcode_match function.
There is no user visible change after this commit.
gas/ChangeLog:
* config/tc-arc.c (arc_find_opcode): Now returns
arc_opcode_hash_entry pointer.
(find_opcode_match): Update argument type, extract arc_opcode from
incoming arc_opcode_hash_entry.
(find_special_case_pseudo): Update return type.
(find_special_case_flag): Update return type.
(find_special_case): Update return type.
(assemble_tokens): Lookup arc_opcode_hash_entry based on
instruction mnemonic, then use find_opcode_match to identify
specific arc_opcode.
The arc assembler builds a hash table to hold references to arc_opcode
entries in the arc_opcodes table. This hash assumes that each mnemonic
will always appear in a contiguous blocks within the arc_opcodes table;
all ADD instruction will be together, all AND instructions will likewise
be together and so on.
The problem with this is that as different variations of arc are added,
then it is often more convenient to split instructions apart, so all the
base ADD instructions are together, but, variants of ADD specific to one
variation of arc are grouped with other instructions specific to that
arc variant. The current data structures don't support splitting the
instructions in this way.
This commit is a first step towards addressing this limitation. In this
commit the hash table that currently holds arc_opcode pointers directly,
instead holds a pointer to a new, intermediate, data structure. This
new data structure holds the pointer to the arc_opcode. In this way, we
can, in the future support having the intermediate structure hold
multiple pointers to different arc_opcode groups.
There should be no visible functional change after this commit.
gas/ChangeLog:
* config/tc-arc.c (struct arc_opcode_hash_entry): New structure.
(arc_find_opcode): New function.
(find_special_case_pseudo): Use arc_find_opcode.
(find_special_case_flag): Likewise.
(assemble_tokens): Likewise.
(md_begin): Build hash using struct arc_opcode_hash_entry.
An upcoming commit will add a new arc instruction flag that uses
characters that have never appeared in an arc instruction flag before.
Currently the assembler is very conservative about which characters can
or cannot appear in an instruction flag.
This commit relaxes these constraints a little. After this commit all
alpha-numeric characters are now allowed into instruction flags. This
complete set is not required for the upcoming change, however, having
this slightly larger set does not impact the assemblers ability to
correctly parse input, but does make it easier to add new flag to the
instruction table.
gas/ChangeLog:
* config/tc-arc.c (tokenize_flags): Allow greater range of
characters into flag names.
The preprocess_operands function changes the incoming list of assembler
tokens based on the assumption that the first arc_operand found will be
the same instruction class as all of the arc_operands for the same
mnemonic.
Though this assumption is probably fine, removing this assumption, and
pushing the token change down into assemble_tokens makes the code no
more complex, and might even be easier to follow.
There should be no user visible changes after this commit.
gas/ChangeLog:
* config/tc-arc.c (find_opcode_match): Handle O_symbol case, add
new de_fault label.
(preprocess_operands): Delete.
(assemble_tokens): Remove call to preprocess_operands.
PR gas/19910
* config/tc-sparc.c (sparc_ip): Report an error if the expression
inside a %-macro could not be fully parsed.
* expr.c (integer_constant): Accept and ignore U suffixes to
integers.
(operand): When a missing closing parenthesis is encountered,
report the character that was found instead.
* testsuite/gas/mips/tls-ill.l: Update expected error message.
* testsuite/gas/sparc/pr19910-1.d: New test driver.
* testsuite/gas/sparc/pr19910-1.s: New test.
* testsuite/gas/sparc/pr19910-2.l: Expected error output.
* testsuite/gas/sparc/pr19910-2.s: New test.
* testsuite/gas/sparc/sparc.exp: Run the new tests.
* config/tc-msp430.c (msp430_operands): Check for a NOP preceding
an EINT instruction. Warn/fix as necessary.
* testsuite/gas/msp430/bad.s: Add test of EINT without preceding NOP.
* testsuite/gas/msp430/bad.l: Update expected messages.
In tc-arc.h we redefine constants that are also defined in the
include/opcode/arc.h header file. The problem is that changing one
without changing the other resulting in strange crashes.
We could comment both locations to stress the importance of remembering
to update the other location too, or we could just include the
opcode/arc.h header file into the assembler.
Given that other targets include their opcode/ARCH.h header file, and
only having a single definition, where possible, is usually the safest
solution, that's what I switch too with this commit.
gas/ChangeLog:
* config/tc-arc.h: Include 'opcode/arc.h'.
(MAX_INSN_ARGS): Delete.
(MAX_INSN_FLGS): Delete.
Providing declarations in tc.h points out that alpha wasn't properly marking
FLT_CHARS as const. We can also get rid of the confusing redefinition of
X_CHARS to mmix_x_chars. Finally we can get rid of some now redundant
declarations of these constants.
gas/ChangeLog:
2016-04-03 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
* config/tc-alpha.c: Const qualify FLT_CHARS.
* config/atof-ieee.c: Remove declarations of FLT_CHARS and EXP_CHARS.
* config/tc-cris.h: Likewise.
* expr.c: Likewise.
* config/tc-mmix.c (md_atof): Adjust comment.
* config/tc-mmix.h: Stop defining FLT_CHARS and EXP_CHARS as macros.
* tc.h: Declare FLT_CHARS and EXP_CHARS.
It needs a few more things to be const now.
gas/ChangeLog:
2016-04-03 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
* config/tc-score.c (s3_gen_reloc): Add const qualifiers.
* config/tc-score7.c (s7_gen_reloc): Likewise.
It is only ever assigned values in the enum, and it is passed to functions that
expect the argument's type to be the enum.
gas/ChangeLog:
2016-04-03 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
* config/tc-arm.c (do_t_branch): Change the type of reloc to
bfd_reloc_code_real_type.
Its not used for anything outside of md_assemble () so it doesn't need to be
extern. While we are there we can replace free () and xmalloc () with
XRESIZEVEC which should be faster.
gas/ChangeLog:
2016-04-03 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
* config/bfin-parse.y (current_inputline): Remove definition.
* config/tc-bfin.c (md_assemble): Simplify use of current_inputline.
Instead of canonicalizing the argument we can just use a case insensitive
compare.
gas/ChangeLog:
2016-04-03 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
* config/tc-avr.c (md_parse_option): Use strcasecmp () to compare
strings.
Small spelling mistake in a #define, fixed in this commit.
gas/ChangeLog:
* config/tc-arc.h (MAX_FLAG_NAME_LENGHT): Rename to...
(MAX_FLAG_NAME_LENGTH): ...this.
(struct arc_flags): Update to use MAX_FLAG_NAME_LENGTH.
* config/tc-arc.c (tokenize_flags): Likewise.
Xtensa uses it in several macros passing it a literal string, so its convenient
for the argument type to be const char *. However some of the code in
symbols.c seems to assume tc_canonicalize_symbol_name () will return a non
const pointer, and some other target's implementations even modify the
argument, so it seems best to return a char * which means casting away const on
the argument when we return it instead of another string.
gas/ChangeLog:
2016-03-31 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
* config/tc-xtensa.c (struct rename_section_struct): Make old_name
const.
(xtensa_section_rename): Make argument type const char *.
* config/tc-xtensa.h (xtensa_section_rename): Adjust.
parse_ldconst () takes a char ** as a in / out argument, and sometimes points
args[0] to a constant string. Then in some cases after parse_ldconst ()
returns md_assemble () twiddles the contents of arg[0]. So it seems like
it would take some work to avoid these casts, and its not really clear
that work is worth it.
gas/ChangeLog:
2016-03-31 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
* config/tc-i960.c (parse_ldconst): Cast to char * when assigning to
args[0].
For these targets its not clear how md_assemble can usefully be split up so
that part can take const char *. There is also a fair number of targets that
need md_assemble () to take a char *, so we can't easily make the argument
const. So since there isn't many callers it seems easiest to just add a couple
of casts.
gas/ChangeLog:
2016-03-31 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
* config/tc-m32c.c (m32c_md_end): cast the argument to md_assemble to
char *.
(m32c_indirect_operand): Likewise.
* config/tc-nds32.c (do_pseudo_b): Likewise.
(do_pseudo_bal): Likewise.
(do_pseudo_ls_bhw): Likewise.
get_symbol_name () returns a char * in a out arg, which means we need to cast
to assign a literal to the variable passed to get_symbol_name (). It seems
like better APIs than get_symbol_name () could be provided, but that seems like
a fair amount of work so just casting seems to be the betterthing to do for
now.
gas/ChangeLog:
2016-03-31 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
* config/tc-ia64.c (md_assemble): Add temporary variable to pass to
get_symbol_name ().
* config/tc-sparc.c (s_register): Cast a literal to char * in
assignment.
various places either directly or indirectly set input_line_pointer to point at
a literal. Currently lots of places modify the string input_line_pointer
points at, so making it const isn't easy. Since most if not all of these
places assign to input_line_pointer to parse an expression it would probably be
best to add ways to generate and deal with expressions that doesn't involve
parsing strings, but for now adding some casts seems easiest.
gas/ChangeLog:
2016-03-31 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
* config/tc-i960.c (parse_expr): Cast to char * when assigning to
input_line_pointer.
* config/tc-m32r.c (expand_debug_syms): Likewise.
* config/tc-msp430.c (msp430_dstoperand): Likewise.
* config/tc-z80.c (md_begin): Likewise.
* stabs.c (stabs_generate_asm_func): Likewise.
these places define char arrays containing values greater than 0x80 which
doesn't fit in an 8 bit signed char, but does fit in an unsigned one.
gas/ChangeLog:
2016-03-31 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
* config/tc-aarch64.c (aarch64_handle_align): Make the type of some
variables unsigned char[].
* config/tc-alpha.c (alpha_handle_align): Likewise.
* config/tc-arm.c (arm_handle_align): Likewise.
* config/tc-z80.c: Likewise.
This name describes what the variable means slightly better, and the enum with
two values that is only used for this one variable is kind of silly.
gas/ChangeLog:
2016-03-25 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
* as.c (parse_args): Adjust.
* as.h (flag_size_check): Rename to flag_allow_nonconst_size.
* config/obj-elf.c (elf_frob_symbol): Adjust.
In the SPARC V9 (and later) versions of the SPARC specification, the
section C.1.1 "Register Names" specifies that:
"asr_reg. An asr_reg is an Ancillary State Register name. It may have
one of the following values:
%asr16-%asr31"
The rationale of having this restriction was that the registers from 16
to 31 are reserved to implementations, and are therefore "non-V9". It
also assumes that the existing ASR registers in the range 0..31 will
have their own names such as %y, that can be used to access such
registers.
However, this is problematic. When a new ASR register is introduced,
such as %mcdper a.k.a. %asr14, it is useful to be able to use %asr14 in
order to not depend on the latest version of the assembler.
The Solaris assembler is lax and allows to assembly instructions
referring to %asr0 to %asr31. This patch makes the GNU assembler to
mimic that behavior.
gas/ChangeLog:
2016-03-24 Jose E. Marchesi <jose.marchesi@oracle.com>
* config/tc-sparc.c (sparc_ip): Remove the V9 restriction on ASR
registers to be in the 16..31 range.
frag_var () assigns its last argument to frag::fr_opcode, and it turns out
some targets modify the string that points to. However it appears niether the
generic code or the microblaze code modifies what fr_opcode points to, so this
code should be safe. So we unfortunately need to cast to char * when passing
an argument to frag_var () but otherwise microblaze can itself point to these
strings with const char *.
gas/ChangeLog:
2016-03-24 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
* config/tc-microblaze.c (md_assemble): Cast opc to char * when calling
frag_var ().
I'm not sure the string it returns is particularly useful, or better than the
string returned by other atof implementations on failure, but given the others
return a localized string it seems like this one should too.
gas/ChangeLog:
2016-03-24 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
* config/tc-visium.c (md_atof): Localize the string returned on
failure.
if the condition is true then we know that str already points to a'\0' in the
string passed to the function. Since we know the latter part of the function
doesn't modify that string, and str already points to a null byte there's no
point in changing str to point to a literal empty string.
gas/ChangeLog:
2016-03-22 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
* config/tc-pdp11.c (md_assemble): Remove useless if and assignment to
str.
This lets us avoid assigning a literal to a char *, and perhaps more
importantly makes it clearer what is going on here.
gas/ChangeLog:
2016-03-22 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
* config/tc-sparc.c (sparc_regname_to_dw2regnum): Replace strchr ()
call with a switch.
This increases consistancy of how we allocate memory, and always casting the
result to the proper type. It also helps make sure we get any use of sizeof on
the result type correct.
gas/ChangeLog:
2016-03-22 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
* listing.c (listing_message): Use XNEW style allocation macros.
* read.c (read_a_source_file): Likewise.
(read_symbol_name): Likewise.
(s_mri_common): Likewise.
(assign_symbol): Likewise.
(s_reloc): Likewise.
(emit_expr_with_reloc): Likewise.
(s_incbin): Likewise.
(s_include): Likewise.
* sb.c (sb_build): Likewise.
(sb_check): Likewise.
One of the tic54x testcases looks for a section alignment of 1. After
9136aa49 the alignment became 0. While it happens that an alignment
of 0 is treated as an alignment of 1, there is no reason to not apply
the explicit alignment.
* write.c (record_alignment): Revert 2016-02-18 change.
bfd * warning.m4 (GCC_WARN_CFLAGS): Only add -Wstack-usage if using a
sufficiently recent version of GCC.
* configure: Regenerate.
others * configure: Regenerate.
Adds the first few nps400 instructions.
gas/ChangeLog:
* testsuite/gas/arc/nps400-0.d: New file.
* testsuite/gas/arc/nps400-0.s: New file.
* testsuite/gas/arc/nps400-1.d: New file.
* testsuite/gas/arc/nps400-1.s: New file.
include/ChangeLog:
* opcodes/arc.h (insn_class_t): Add BITOP type.
opcodes/ChangeLog:
* arc-nps400-tbl.h: New file.
* arc-opc.c: Add top level comment.
(insert_nps_3bit_dst): New function.
(extract_nps_3bit_dst): New function.
(insert_nps_3bit_src2): New function.
(extract_nps_3bit_src2): New function.
(insert_nps_bitop_size): New function.
(extract_nps_bitop_size): New function.
(arc_flag_operands): Add nps400 entries.
(arc_flag_classes): Add nps400 entries.
(arc_operands): Add nps400 entries.
(arc_opcodes): Add nps400 include.
When parsing the operand instruction flags we don't currently detect the
case where multiple flags are provided from the same class set, these
will be accepted and the bit values merged together, resulting in the
wrong instruction being assembled. For example:
adc.n.eq r0,r0,r2
Will assemble without error, yet, upon disassembly, the instruction will
actually be:
adc.c r0,r0,r2
In a later commit the concept of required flags will be introduced.
Required flags are just like normal instruction flags, except that they
must be present for the instruction to match. Adding this will allow
for simpler instructions in the instruction table, and allow for more
sharing of operand extraction and insertion functions.
To solve both of the above issues (multiple flags being invalid, and
required flags), this commit reworks the flag class mechanism.
Currently the flag class is never used. Each instruction can reference
multiple flag classes, each flag class has a class type and a set of
flags. However, at present, the class type is never used. The current
values identify the type of instruction that the flag will be used in,
but this is not required information.
Instead, this commit discards the old flag classes, and introduces 3 new
classes. The first F_CLASS_NONE, is just a NULL marker value, and is
only used in the NULL marker flag class. The other two flag classes are
F_FLAG_OPTIONAL, and F_FLAG_REQUIRED.
The class F_FLAG_OPTIONAL has the property that at most one of the flags
in the flag set for that class must be present in the instruction. The
"at most" one means that no flags being present is fine.
The class F_FLAG_REQUIRED is not currently used, but will be soon. With
this class, exactly one of the flags from this class must be present in
the instruction. If the flag class contains a single flag, then of
course that flag must be present. However, if the flag class contained
two or more, then one, and only one of them must be present.
gas/ChangeLog:
* config/tc-arc.c (find_opcode_match): Move lnflg, and i
declarations to start of block. Reset code on all flags before
attempting to match them. Handle multiple hits on the same flag.
Handle flag class.
* testsuite/gas/arc/asm-errors.d: New file.
* testsuite/gas/arc/asm-errors.err: New file.
* testsuite/gas/arc/asm-errors.s: New file.
include/ChangeLog:
* opcode/arc.h (flag_class_t): Remove all old flag classes, add 3
new classes instead.
opcodes/ChangeLog:
* arc-opc.c (arc_flag_classes): Convert all flag classes to use
the new class enum values.
This commit introduces the nps400 machine type as a variant of arc.
There's a new flag in the assembler to select this machine type. All
other changes are just adding handling of the new machine type into the
relevant places.
The nps400 is an arc700 variant with some vendor specific instructions
added into the instruction set. This commit does not add any of the new
instructions, this is just laying the groundwork for future commits.
However, in preparation for these new instructions a new opcode define for
nps400 has been added to include/opcode/arc.h, this new opcode define is
used in the assembler and disassembler along with the existing define
for arc700 such that when assembling and disassembling for nps400 the
user will have access to all arc700 instructions and all the nps400
vendor extension instructions.
bfd/ChangeLog:
* archures.c (bfd_mach_arc_nps400): Define.
* bfd-in2.h: Regenerate.
* cpu-arc.c (arch_info_struct): New entry for nps400, renumber
some existing entries to make space.
* elf32-arc.c (arc_elf_object_p): Add nps400 case.
(arc_elf_final_write_processing): Likewise.
binutils/ChangeLog:
* readelf.c (decode_ARC_machine_flags): Handle nps400.
gas/ChangeLog:
* config/tc-arc.c (cpu_types): Add nps400 entry.
(check_zol): Handle nps400.
include/ChangeLog:
* elf/arc.h (E_ARC_MACH_NPS400): Define.
* opcode/arc.h (ARC_OPCODE_NPS400): Define.
opcodes/ChangeLog:
* arc-dis.c (print_insn_arc): Handle nps400.
The constant EF_ARC_CPU_GENERIC is defined in the include/elf/arc.h
file, and is used in a few places in binutils, however, this constant
should never make it into the elf header flags; we always set a valid
cpu type in the assembler, which should then be copied over during
linking.
There are some non-gnu arc compilers that don't write an architecture
type into the e_flags field, instead leaving the field as 0, which is
the EF_ARC_CPU_GENERIC value. This non-gnu compiler uses the machine
type to distinguish between the old and newer arc architectures, setting
the machine type to EM_ARC_COMPACT for old arc600, arc601, and arc700
architectures, while using EM_ARC_COMPACT2 for newer arcem and archs
architectures.
Previously when displaying the machine flags for an older EM_ARC_COMPACT
machine, if the e_flags had not been filled in, then we relied on the
default case statement to display the message "Generic ARCompact", while
in the EM_ARC_COMPACT2 case we specifically handled EF_ARC_CPU_GENERIC
to print "ARC Generic", leaving the default case to print a message
about unrecognised cpu flag.
After this commit EF_ARC_CPU_GENERIC has been removed, for both machine
types EM_ARC_COMPACT and EM_ARC_COMPACT2 we now rely on the default case
statement to handle the situation where the e_flags has not been filled
in. The message displayed is now "Unknown ARCompact" (for older arc
architectures) and "Unknown ARC" (for the newer architectures). The
switch from "Generic" to "Unknown" in the message string is for clarity,
calling the file "Generic" can give the impression that the file is
compiled for a common sub-set of the architectures, and would therefore
run on any type of machine (or at least any type of new or old machine
depending on if the machine type is ARC or ARCv2). However, this was
not what "Generic" meant, it really meant "Unknown", so that's what we
now say.
As part of the merging of the readelf flag reading code, I have unified
the strings used in displaying the ELF ABI. This means that for older
arc machines (arc600, arc601, and arc700) the string used for the
original ABI, and ABIv2 have changed, the current ABIv3 remains the
same. For the newer architectures (arcem and archs) the abi strings
remain unchanged in all cases.
bfd/ChangeLog:
* elf32-arc.c (arc_elf_print_private_bfd_data): Remove use of
EF_ARC_CPU_GENERIC.
(arc_elf_final_write_processing): Don't bother setting cpu field
in e_flags, this will have been set elsewhere.
binutils/ChangeLog:
* readelf.c (get_machine_flags): Move arc processing into...
(decode_ARC_machine_flags): ... new function. Remove use of
EF_ARC_CPU_GENERIC, change default case from "generic arc" to
"unknown arc". Merged ABI printing between two machine types.
gas/ChangeLog:
* config/tc-arc.c (arc_select_cpu): Remove use of
EF_ARC_CPU_GENERIC.
include/ChangeLog:
* elf/arc.h (EF_ARC_CPU_GENERIC): Delete. Update related comment.
This commit restructures the selection of the default cpu/mach so that
the choice is made from md_begin (if the user has not provided a command
line choice). This will reduce the amount of change needed in a later
patch.
At the request of Synopsys, the default architecture changes to ARC700
from this commit, previously the default was a non-existent
super-architecture that contained all instructions from all arc
variants. There's some clean up associated with removing the default
merged architecture, and a small test fix now that the default is
ARC700.
binutils/ChangeLog:
* testsuite/binutils-all/objdump.exp (cpus_expected): Add ARC700
to the architecture list.
gas/ChangeLog:
* config/tc-arc.c (arc_target): Delay initialisation until
arc_select_cpu.
(arc_target_name): Likewise.
(arc_features): Likewise.
(arc_mach_type): Likewise.
(cpu_types): Remove "all" entry.
(arc_select_cpu): New function, most of the content is from...
(md_parse_option): ... here. Call new arc_select_cpu.
(md_begin): Call arc_select_cpu if needed, default is now arc700.
include/ChangeLog:
* opcode/arc.h (ARC_OPCODE_BASE): Delete.
opcodes/ChangeLog:
* arc-opc.c (BASE): Delete.
The inline-data test checks the specific bytes laid down by the
assembler, and so relies on the endianness of the target. I could
change the expected results to be endian agnostic, however, I worried
that a bug in the assembler that gets the endianness wrong would then
slip through. Instead I add a new test for big-endian arc, and restrict
the existing test to little-endian arc.
gas/ChangeLog:
* testsuite/gas/arc/inline-data-1.d: Add target restriction.
* testsuite/gas/arc/inline-data-2.d: New file.
char can be a signed type, and some of the values in these arrays are greater
than 0x80 which means they are outside of the range a signed char can store.
Fortunately it seems most compilers handle this in the obvious way by storing
the same bits as a negative number, but this is wierd and easily fixed.
gas/ChangeLog:
2016-03-20 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
* tc-i386.c (f32_1): Change type to unsigned char[].
(f32_2): Likewise.
(f32_3): Likewise.
(f32_4): Likewise.
(f32_5): Likewise.
(f32_6): Likewise.
(f32_7): Likewise.
(f32_8): Likewise.
(f32_9): Likewise.
(f32_10): Likewise.
(f32_11): Likewise.
(f32_12): Likewise.
(f32_13): Likewise.
(f32_14): Likewise.
(f16_3): Likewise.
(f16_4): Likewise.
(f16_5): Likewise.
(f16_6): Likewise.
(f16_7): Likewise.
(f16_8): Likewise.
(jump_31): Likewise.
(f32_patt): Likewise.
(f16_patt): Likewise.
(alt_3): Likewise.
(alt_4): Likewise.
(alt_5): Likewise.
(alt_6): Likewise.
(alt_7): Likewise.
(alt_8): Likewise.
(alt_9): Likewise.
(alt_10): Likewise.
(alt_patt): Likewise.
PR target/19721
opcodes * aarch64-tbl.h (aarch64_opcode_table): Fix type of second operand
of MOV insn that aliases an ORR insn.
gas * testsuite/gas/aarch64/pr19721.s: New test source file.
* testsuite/gas/aarch64/pr19721.d: New test driver file.
gas * doc/as.texinfo: Place the target specific command line options
into their own man page section.
etc * texi2pod.pl: Add TARGET to the list of recognised man page
sections.
gas/
* config/tc-arm.c (N_S_32): New.
(N_F_16_32): Likewise.
(N_SUF_32): Support N_F16.
(N_IF_32): Likewise.
(neon_dyadic_misc): Likewise.
(do_neon_cmp): Likewise.
(do_neon_cmp_inv): Likewise.
(do_neon_mul): Likewise.
(do_neon_fcmp_absolute): Likewise.
(do_neon_step): Likewise.
(do_neon_abs_neg): Likewise.
(CVT_FLAVOR_VAR): Likewise.
(do_neon_cvt_1): Likewise.
(do_neon_recip_est): Likewise.
(do_vmaxnm): Likewise.
(do_vrint_1): Likewise.
(neon_check_type): Check architecture support for FP16 extension.
(insns): Update comments.
* testsuite/gas/arm/armv8-2-fp16-simd.s: New test source.
* testsuite/gas/arm/armv8-2-fp16-simd.d: New testcase for arm mode.
* testsuite/gas/arm/armv8-2-fp16-simd-thumb.d: Likewise for thumb mode.
* testsuite/gas/arm/armv8-2-fp16-simd-warning.d: New rejection test for
arm mode.
* testsuite/gas/arm/armv8-2-fp16-simd-warning-thumb.d: Likewise for
thumb mode.
* testsuite/gas/arm/armv8-2-fp16-simd-warning.l: New expected rejection
error file.
opcode/
* arm-dis.c (neon_opcodes): Support new FP16 instructions.
* read.c (emit_expr_with_reloc): Add code check a bignum with
nbytes == 1.
* config/rx/rx-parse.y (rx_intop): Accept bignum values for sizes
other than 32-bits.
* testsuite/gas/elf/bignum.s: New test source file.
* testsuite/gas/elf/bignum.d: New test driver file.
* testsuite/gas/elf/elf.exp: Run the new test.
gcc 4.7 complains about variables that shadow function names, which now happens
in tc-arm.c because there is a global function do_align (), and local variables
do_align. The simplest fix for this seems to be to rename those variables to
do_alignment.
gas/ChangeLog:
2016-03-09 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
* config/tc-arm.c (neon_alignment_bit): Rename do_align to
do_alignment.
(do_neon_ld_st_lane): Likewise.
(do_neon_ld_dup): Likewise.
bfd/
2016-03-08 Cupertino Miranda <Cupertino.Miranda@synopsys.com>
Andrew Burgess <andrew.burgess@embecosm.com>
* elf32-arc.c (arc_bfd_get_32): Becomes an alias for bfd_get_32.
(arc_bfd_put_32): Becomes an alias for bfd_put_32.
(arc_elf_howto_init): Added assert to validate relocations.
(get_middle_endian_relocation): Delete.
(middle_endian_convert): New function.
(ME): Redefine, now does nothing.
(IS_ME): New define.
(arc_do_relocation): Extend the attached 'ARC_RELOC_HOWTO'
definition to call middle_endian_convert. Add a new local
variable and make use of this throughout. Added call to
arc_bfd_get_8 and arc_bfd_put_8 for 8 bit relocations.
gas/
2016-03-08 Andrew Burgess <andrew.burgess@embecosm.com>
* testsuite/gas/arc/inline-data-1.d: New file.
* testsuite/gas/arc/inline-data-1.s: New file.
include/
2016-03-08 Cupertino Miranda <Cupertino.Miranda@synopsys.com>
Andrew Burgess <andrew.burgess@embecosm.com>
* elf/arc-reloc.def: Add a call to ME within the formula for each
relocation that requires middle-endian correction.
bfd/
2016-02-29 Cupertino Miranda <Cupertino.Miranda@synopsys.com>
* elf32-arc.c (arc_elf_final_write_processing): Add condition to
the flag change.
(elf_arc_relocate_section): Fixes and conditions to support PIE.
Assert for code sections dynamic relocs.
gas/
2016-02-29 Claudiu Zissulescu <Claudiu.Zissulescu@synopsys.com>
* config/tc-arc.c: Enable code density instructions for ARC EM.
ld/
2016-02-29 Cupertino Miranda <Cupertino.Miranda@synopsys.com>
* scripttempl/arclinux.sc: Force .tdata and .tbss to always be
generated.
Some gas tests are excluded for arc targets using the pattern arc-*-*,
however this only covers little endian arc targets. This commit extends
the patter to cover big endian arc targets, the pattern is now arc*-*-*.
gas/ChangeLog:
* testsuite/gas/all/gas.exp: Change target pattern to cover
arceb-*.
* testsuite/gas/all/redef3.d: Likewise.
* testsuite/gas/elf/elf.exp: Likewise.
opcodes/
2016-02-24 Renlin Li <renlin.li@arm.com>
* arm-dis.c (print_insn_coprocessor): Check co-processor number for
cpd/cpd2, mcr/mcr2, mrc/mrc2, ldc/ldc2, stc/stc2.
gas/
2016-02-24 Renlin Li <renlin.li@arm.com>
* testsuite/gas/arm/copro.s: Use coprocessor other than 10, 11.
* testsuite/gas/arm/copro.d: Update.
There is no need to set BFD compression bits for each section. We
should just set it once in write_object_file.
* write.c (compress_debug): Move BFD compression bits setting
to ...
(write_object_file): Here.
Increment register number by 16 if RegVRex is set.
* config/tc-i386.c (register_number): Check RegVRex.
* testsuite/gas/i386/x86-64-avx512f.s: Add a test for vgatherqpd
with %zmm19 and %zmm3.
* testsuite/gas/i386/x86-64-avx512f-intel.d: Updated.
* testsuite/gas/i386/x86-64-avx512f.d: Likewise.
* symbols.c (decode_local_label_name): Make type a const char *.
* listing.c (print_source): Make type of p const char *.
(print_line): Make type of string const char *.
(buffer_line): Return const char *.
(title): Make type const char *.
(subtitle): Likewise.
(listing_listing): Make type of p const char *.
* messages.c (as_internal_value_out_of_range): Make type of prefix
const char *.
* stabs.c (s_stab_generic): make type of stab_secname, stabstr_secname
and string const char *.
* read.c (_bfd_rel): Make type of name const char *.
* app.c (out_string): Change type to const char *.
(struct app_save::out_string): Likewise.
gas * read.c (finish_bundle): Avoid recording a negative alignment.
(do_align): Use unsigned values for n, len and max. Only create
a frag if the alignment requirement is greater than the minimum
byte alignment. Avoid recording a negative alignment.
(s_align): Use unsigned values where appropriate.
(bss_alloc): Use an unsigned value for the alignment.
(sizeof_sleb128): Add a comment noting that we encode one octet
per byte, regardless of the value of OCTETS_PER_BYTE_POWER.
(emit_leb129_expr): Abort if the emitted encoding was longer than
expected.
* read.h (output_leb128): Update prototype.
(sizeof_leb128): Update prototype.
(bss_alloc): Update prototype.
* write.c (record_alignment): Use an unsigned value for the
alignment. Do not record alignments less than the minimum
alignment for a byte.
* write.h (record_alignment): Update prototype.
Despite the documentation and the comment in xtensa_move_literals, in
the presence of --text-section-literals and --auto-litpools literals are
moved from the separate literal sections into .init and .fini, because
the check in the xtensa_move_literals is incorrect.
This moving was broken with introduction of auto litpools: some literals
now may be lost. This happens because literal frags emitted from .init
and .fini are not closed when new .literal_position marks new literal
pool. Then frag_align(2, 0, 0) changes type of the last literal frag to
rs_align. rs_align frags are skipped in the xtensa_move_literals. As a
result fixups against such literals are not moved out of .init.literal/
.fini.literal sections producing the following assembler error:
test.S: Warning: fixes not all moved from .init.literal
test.S: Internal error!
Fix check for .init.literal/.fini.literal in the xtensa_move_literals
and don't let it move literals from there in the presence of
--text-section-literals or --auto-litpools.
2016-02-17 Max Filippov <jcmvbkbc@gmail.com>
gas/
* config/tc-xtensa.c (xtensa_move_literals): Fix check for
.init.literal/.fini.literal section name.
* testsuite/gas/xtensa/all.exp: Add init-fini-literals to the
list of xtensa tests.
* testsuite/gas/xtensa/init-fini-literals.d: New file:
init-fini-literals test result patterns.
* testsuite/gas/xtensa/init-fini-literals.s: New file:
init-fini-literals test.
In AArch64 gas, register name or string starts with valid register name
is not allowed as symbol name for mov[z,k,n] instruction.
This patch removes the restriction.
gas/
PR gas/19620
* config/tc-aarch64.c (parse_half): Remove restrictions on symbol name.
* testsuite/gas/aarch64/movw_label.d: New.
* testsuite/gas/aarch64/movw_label.s: New.
gas * doc/as.texinfo (.section): Document that numeric values can now
be used for the flags and type fields of the ELF target's .section
directive. Add notes about the restrictions on setting flags and
types.
* config/obj-elf.c (obj_elf_change_section): Allow known sections
to be given processor specific section types. Allow processor and
application specific flags of a section to be set after
definition.
(obj_elf_parse_section_letters): Handle parsing numeric values.
(obj_elf_section_type): Handle parsing numeric values.
(obj_elf_section): Allow numeric type values.
* config/obj-elf.h (obj_elf_change_section): Update prototype.
* testsuite/gas/elf/section10.d: New test.
* testsuite/gas/elf/section10.s: Source file for new test.
* testsuite/gas/elf/elf.exp: Run the new test.
* testsuite/gas/i386/ilp32/x86-64-unwind.d: Remove dependency upon
the description of the flags produced by readelf.
* testsuite/gas/tic6x/scomm-directive-4.d: Likewise.
* NEWS: Mention the new feature.
bfd * elf-bfd.h (struct bfd_elf_special_section): Use unsigned values
for length and type fields. Use a signed value for the
suffix_length field.
binutils* readelf.c (get_section_type_name): Add hex prefix to offsets
printed for LOPROC and LOOS values. Ensure that a result is
always returned for the V850 target, even when an unrecognised
processor specific value is encountered.
(process_section_headers): Display key values in the order in
which they appear to the user. Add the "C (compressed)" value to
the list.
ld * testsuite/ld-i386/pr12718.d: Remove dependency upon the
description of the flags produced by readelf.
* testsuite/ld-i386/pr12921.d: Likewise.
* testsuite/ld-i386/tlsbin-nacl.rd: Likewise.
* testsuite/ld-i386/tlsbin.rd: Likewise.
* testsuite/ld-i386/tlsbindesc-nacl.rd: Likewise.
* testsuite/ld-i386/tlsbindesc.rd: Likewise.
* testsuite/ld-i386/tlsdesc-nacl.rd: Likewise.
* testsuite/ld-i386/tlsdesc.rd: Likewise.
* testsuite/ld-i386/tlsgdesc-nacl.rd: Likewise.
* testsuite/ld-i386/tlsgdesc.rd: Likewise.
* testsuite/ld-i386/tlsnopic-nacl.rd: Likewise.
* testsuite/ld-i386/tlsnopic.rd: Likewise.
* testsuite/ld-i386/tlspic-nacl.rd: Likewise.
* testsuite/ld-i386/tlspic.rd: Likewise.
* testsuite/ld-s390/tlsbin.rd: Likewise.
* testsuite/ld-s390/tlsbin_64.rd: Likewise.
* testsuite/ld-s390/tlspic.rd: Likewise.
* testsuite/ld-s390/tlspic_64.rd: Likewise.
* testsuite/ld-sh/tlsbin-2.d: Likewise.
* testsuite/ld-sh/tlspic-2.d: Likewise.
* testsuite/ld-tic6x/common.d: Likewise.
* testsuite/ld-tic6x/shlib-1.rd: Likewise.
* testsuite/ld-tic6x/shlib-1b.rd: Likewise.
* testsuite/ld-tic6x/shlib-1r.rd: Likewise.
* testsuite/ld-tic6x/shlib-1rb.rd: Likewise.
* testsuite/ld-tic6x/shlib-app-1.rd: Likewise.
* testsuite/ld-tic6x/shlib-app-1b.rd: Likewise.
* testsuite/ld-tic6x/shlib-app-1r.rd: Likewise.
* testsuite/ld-tic6x/shlib-app-1rb.rd: Likewise.
* testsuite/ld-tic6x/shlib-noindex.rd: Likewise.
* testsuite/ld-tic6x/static-app-1.rd: Likewise.
* testsuite/ld-tic6x/static-app-1b.rd: Likewise.
* testsuite/ld-tic6x/static-app-1r.rd: Likewise.
* testsuite/ld-tic6x/static-app-1rb.rd: Likewise.
* testsuite/ld-x86-64/ilp32-4-nacl.d: Likewise.
* testsuite/ld-x86-64/ilp32-4.d: Likewise.
* testsuite/ld-x86-64/pr12718.d: Likewise.
* testsuite/ld-x86-64/pr12921.d: Likewise.
* testsuite/ld-x86-64/split-by-file-nacl.rd: Likewise.
* testsuite/ld-x86-64/split-by-file.rd: Likewise.
* testsuite/ld-x86-64/tlsbin-nacl.rd: Likewise.
* testsuite/ld-x86-64/tlsbin.rd: Likewise.
* testsuite/ld-x86-64/tlsbindesc-nacl.rd: Likewise.
* testsuite/ld-x86-64/tlsbindesc.rd: Likewise.
* testsuite/ld-x86-64/tlsdesc-nacl.rd: Likewise.
* testsuite/ld-x86-64/tlsdesc.rd: Likewise.
* testsuite/ld-x86-64/tlsgdesc-nacl.rd: Likewise.
* testsuite/ld-x86-64/tlsgdesc.rd: Likewise.
* testsuite/ld-x86-64/tlspic-nacl.rd: Likewise.
* testsuite/ld-x86-64/tlspic.rd: Likewise.
* testsuite/ld-xtensa/tlsbin.rd: Likewise.
* testsuite/ld-xtensa/tlspic.rd: Likewise.
PR gas/19614
* dw2gencfi.c (cfi_sections_set): Delay setting this variable
until it is actually used.
(cfi_set_sections): Set cfi_sections_set to true.
(dot_cfi_startproc): Likewise.
(dot_cfi_endproc): Likewise.
(dot_cfi_fde_data): Likewise.
(cfi_finish): Likewise.
(dot_cfi_sections): Do not set cfi_sections_set.
* doc/as.texinfo (.cfi_sections): Note that targets can provide
their own cfi section name. Also note that the directive can be
reissued provided that CFI generation has not started.
* testsuite/gas/mips/compact-eh-err2.s: Add .cfi_startproc and
.cfi_endproc directives so that the redefinition of .cfi_sections
will trigger the generation of the error message.
* testsuite/gas/mips/compact-eh-err2.l: Update expected line
number of error message.
PR target/19561
opcdoe * msp430-dis.c (print_insn_msp430): Add a special case for
decoding an RRC instruction with the ZC bit set in the extension
word.
include * opcode/msp430.h (IGNORE_CARRY_BIT): New define.
(RRUX): Synthesise using case 2 rather than 7.
gas * config/tc-msp430.c (msp430_operands): Remove case 7. Use case 2
to handle encoding of RRUX instruction.
* testsuite/gas/msp430/msp430x.s: Add more tests of the extended
shift instructions.
* testsuite/gas/msp430/msp430x.d: Update expected disassembly.
Change 1058c7532d "Use signed data type for R_XTENSA_DIFF* relocation
offsets." changed signedness of BFD_RELOC_XTENSA_DIFF* relocations
substituted for BFD_RELOC_*. This made it impossible to encode arbitrary
8-, 16- and 32-bit values, which broke e.g. debug info encoding by .loc
directive. Revert this part and add test.
gas/
2016-02-03 Max Filippov <jcmvbkbc@gmail.com>
* config/tc-xtensa.c (md_apply_fix): Mark BFD_RELOC_XTENSA_DIFF*
substitutions for BFD_RELOC_* as unsigned.
* gas/testsuite/gas/xtensa/all.exp: Add loc to list of xtensa
tests.
* gas/testsuite/gas/xtensa/loc.d: New file: loc test result
patterns.
* gas/testsuite/gas/xtensa/loc.s: New file: loc test.
This change makes gas's notion of the msp430 dwarf2 address size match
that of gcc and gdb. This is needed so that the format of addresses
generated for DW_LNE_set_address in .debug_line will match the address
size for the compilation unit.
In gcc/config/msp430/msp430.h, it's set to 4:
#define DWARF2_ADDR_SIZE 4
Likewise in gdb/msp430-tdep.c:
set_gdbarch_dwarf2_addr_size (gdbarch, 4);
(As far as I can tell, however, GDB doesn't use this value when decoding
.debug_line. Instead, GDB uses the Pointer Size from the compilation
unit.)
readelf is able to seamlessly handle mismatches between these various
sizes by using the size of the DW_LNE_set_address instruction to
determine the address size. Another way to fix this problem is to
make GDB behave in a similar manner. In my opinion, GDB should detect
and inform the user about these mismatches; it's not clear to me if
it's correct for GDB to go ahead and read the address anyway when a
size mismatch is detected.
Without this change, addresses in .debug_line are encoded in two bytes
for some multilibs. When GDB reads the address for
DW_LNE_set_address, it uses the pointer size provided by the CU. When
these values don't match, GDB reads the wrong number of bytes. In the
cases that I've looked at, GDB is reading 4 bytes from a 2 byte
container, which results in a garbage address. GDB discards lines
which have a bogus address; the end result is that GDB records no line
number information for CUs which have a mismatch between the address
size (from the CU) and the format of the address used by
DW_LNE_set_address.
gas/ChangeLog:
* config/tc-msp430.h (DWARF2_ADDR_SIZE): Set to 4.
Basic all instructions assembler test, auto-generated by CGEN, then
fixed by hand for some cases where CGEN had generated invalid
instruction operands.
gas/ChangeLog:
* testsuite/gas/ip2k/allinsn.d: New file.
* testsuite/gas/ip2k/allinsn.s: New file.
* testsuite/gas/ip2k/ip2k-allinsn.exp: New file.
In commit 02a79b89fd some of the load
instructions with a zero offset (where the offset is not mentioned) were
marked as NO-DIS, meaning that the disassembler must display the offset,
even though it is zero.
This change seems a little strange to me as it was only applied to some
loads, not all, and the same change was not applied to the stores.
However, I'm reluctant to revert a specific change to the assembler,
when the output is obviously correct. With this commit then I simply
bring the expected assembler test results into line with what is
actually produced.
gas/ChangeLog:
* testsuite/gas/epiphany/addr-syntax.d: Add explicit 0 offset to
some load instructions.
* testsuite/gas/epiphany/allinsn.d: Likewise.
* testsuite/gas/epiphany/regression.d: Likewise.
In commit 02a79b89fd all instruction
aliases that have a '.l' suffix were marked as NO-DIS, so the
disassembler will not display them, in preference to the instruction
without the suffix. However, the gas testsuite was not updated at the
time, this commit fixes that oversight.
gas/ChangeLog:
* testsuite/gas/epiphany/addr-syntax.d: Remove unneeded '.l'
suffixes from instruction mnemonics in expected output.
* testsuite/gas/epiphany/allinsn.d: Likewise.
* testsuite/gas/epiphany/regression.d: Likewise.
* testsuite/gas/epiphany/sample.d: Likewise.
In commit 02a79b89fd the register aliases
sb, sl, and ip were made less preferred than r9, r10, and r12, however,
the expected test results were not updated. This commit fixes this
oversight and updates the test results.
gas/ChangeLog:
* testsuite/gas/epiphany/addr-syntax.d: Update expected register
names.
* testsuite/gas/epiphany/allinsn.d: Likewise.
* testsuite/gas/epiphany/sample.d: Likewise.
Always set the bytes_per_line field (of struct disassemble_info) to the
same constant value, this is inline with the advice contained within
include/dis-asm.h.
Setting this field to a constant value will cause the disassembler
output to be better aligned.
cpu/ChangeLog:
* epiphany.opc (epiphany_print_insn): Set info->bytes_per_line to
a constant to better align disassembler output.
opcodes/ChangeLog:
* epiphany-dis.c: Regenerated from latest cpu files.
gas/ChangeLog:
* testsuite/gas/epiphany/sample.d: Update expected output.
Use OPTION_MXXX for -mxxx option in x86 assembler.
* config/tc-i386.c (OPTION_OMIT_LOCK_PREFIX): Renamed to ...
(OPTION_MOMIT_LOCK_PREFIX): This.
(md_longopts): Updated.
(md_parse_option): Likewise.
In the instruction to write to the ARMv8.2 PSTATE field UAO,
MSR UAO, #<imm>, the immediate should be either 0 or 1 but GAS accepts
any unsigned 4-bit integer.
This patch implements the constraint on the immediate, generating an
error if the immediate operand is invalid, and adds tests for the
illegal forms.
opcodes/
2016-01-20 Matthew Wahab <matthew.wahab@arm.com>
* aarch64-opc.c (operand_general_constraint_met_p): Check validity
of MSR UAO immediate operand.
gas/
2016-01-20 Matthew Wahab <matthew.wahab@arm.com>
* testsuite/gas/aarch64/armv8_2-a-illegal.d: New.
* testsuite/gas/aarch64/armv8_2-a-illegal.l: New.
* testsuite/gas/aarch64/armv8_2-a-illegal.s: New.
Change-Id: Ibdec4967c00b1ef3be9dbc43d23b2c70d1a0b28c
bfd/ChangeLog:
* elf32-arm.c ((elf32_arm_special_sections): Remove catch of noread
section using '.text.noread' pattern.
gas/ChangeLog:
* config/obj-elf.c (obj_elf_change_section) : Allow arm section with
SHF_ARM_NOREAD section flag.
* config/tc-arm.h (md_elf_section_letter) : Implement this hook to
handle letter 'y'.
(arm_elf_section_letter) : Declare it.
* config/tc-arm.c (arm_elf_section_letter): Handle letter 'y' to set
SHF_ARM_NOREAD section flag.
* doc/c-arm.texi (ARM section attribute 'y'): Document it.
gas/testsuite/ChangeLog:
* gas/arm/section-execute-only.s: New test case.
* gas/arm/section-execute-only.d: Expected output.
ld/testsuite/ChangeLog:
* ld-arm/thumb1-noread-not-present-mixing-two-section.s: Add 'y'
attribute usage.
* ld-arm/thumb1-noread-present-one-section.s: Likewise.
* ld-arm/thumb1-noread-present-two-section.s: Likewise.
* ld-arm/thumb1-input-section-flag-match.s: Likewise.
binutils/ChangeLog:
* readelf.c (get_elf_section_flags): Display y letter for section
with SHF_ARM_NOREAD section flag in readelf section output.
(process_section_headers): Add y letter in readelf section output
key mapping for ARM architecture.
The POOL48A major opcode was defined in early revisions of the 64-bit
microMIPS ISA, has never been implemented, and was removed before the
64-bit microMIPS ISA specification[1] has been finalized.
This complements commit a6c7053929 ("MIPS/opcodes: Remove microMIPS
48-bit LI instruction").
References:
[1] "MIPS Architecture for Programmers, Volume II-B: The microMIPS64
Instruction Set", MIPS Technologies, Inc., Document Number: MD00594,
Revision 3.06, October 17, 2012, Table 6.2 "microMIPS64 Encoding of
Major Opcode Field", p. 578
gas/
* config/tc-mips.c (micromips_insn_length): Remove the mention
of 48-bit microMIPS instructions.
gdb/
* mips-tdep.c (mips_insn_size): Remove 48-bit microMIPS
instruction support.
(micromips_next_pc): Likewise.
(micromips_scan_prologue): Likewise.
(micromips_deal_with_atomic_sequence): Likewise.
(micromips_stack_frame_destroyed_p): Likewise.
(mips_breakpoint_from_pc): Likewise.
opcodes/
* mips-dis.c (print_insn_micromips): Remove 48-bit microMIPS
instruction support.
Oddly, config.sub converts a duple ending in -elf for these target to
-unknown-none, which means they aren't seen as elf targets by
binutils. So, counter that. This exposes a number of testsuite
issues (ones you would have seen if configuring with a full triple,
say m68hc11-unknown-elf).
binutils/
* testsuite/lib/binutils-common.exp (is_elf_format): Return true
for m68hc11/12 and xgate triples.
gas/
* testsuite/gas/cfi/cfi.exp: Exclude m68hc11/12 from m68k test.
ld/
* testsuite/lib/ld-lib.exp (check_shared_lib_support): Exclude xgate.
* testsuite/ld-elf/endsym.d: xfail m68hc11/12 and xgate.
* testsuite/ld-elf/pr14156a.d: Likewise.
* testsuite/ld-elf/pr14926.d: Don't run for m68hc11/12 and xgate.
* testsuite/ld-elf/sec64k.exp: Likewise.
* rl78-decode.opc (rl78_decode_opcode): Add 's' operand to movw
instructions that can support stack pointer operations.
* rl78-decode.c: Regenerate.
* rl78-dis.c: Fix display of stack pointer in MOVW based
instructions.
* testsuite/gas/rl78/sp-relative-movw.s: New test.
* testsuite/gas/rl78/sp-relative-movw.d: Expected disassembly.
* testsuite/gas/rl78/rl78.exp: Run the new test.
Some of the RAS system registers added to binutils as part of the ARMv8.2
support are missing the feature checks to warn when they aren't
supported by the target.
This patch adds the missing feature checks with a test to check that
the correct warnings are given for all the ARMv8.2 system registers.
gas/
2016-01-14 Matthew Wahab <matthew.wahab@arm.com>
* testsuite/gas/aarch64/illegal-sysreg-2.l: New.
* testsuite/gas/aarch64/illegal-sysreg-2.d: New.
opcodes/
2016-01-14 Matthew Wahab <matthew.wahab@arm.com>
* aarch64-opc.c (aarch64_sys_reg_supported_p): Merge conditionals
testing for RAS support. Add checks for erxfr_el1, erxctlr_el1,
erxtatus_el1 and erxaddr_el1.
Change-Id: I66b590ea49c1eb6b0e5c93e0dc2bc9c4e79a52fe
Fix:
cc1: warnings being treated as errors
.../gas/config/tc-nios2.c: In function 'output_movia':
.../gas/config/tc-nios2.c:3474: warning: 'code' may be used uninitialized in this function
make[4]: *** [tc-nios2.o] Error 1
seen with GCC 4.1.2 and 4.4.7.
gas/
* config/tc-nios2.c (output_movia): Preset `code' to 0.
The ARMv8.2 architecture includes the RAS extension which adds an
instruction, ESB, and a number of coprocessor registers. This patch adds
the instruction to binutils, making it available when -march=armv8.2-a
is selected. It also adds tests for the instruction and for the
coprocessor registers.
gas/
2016-01-12 Matthew Wahab <matthew.wahab@arm.com>
* config/tc-arm.c (arm_ext_v8_2): New.
(insns): Add "esb".
* testsuite/gas/arm/armv8_2-a.d: New.
* testsuite/gas/arm/armv8_2-a.s: New.
opcodes/
2016-01-12 Matthew Wahab <matthew.wahab@arm.com>
* arm-dis.c (arm_opcodes): Add "esb".
(thumb_opcodes): Likewise.
Change-Id: I67f3d70789db78d1c66a56c4994675f99ac15e34
For ISA_B/C only the combination #,d(An) is allowed in addition to the
ISA_A combinations for move.b and move.w (and pc-relative is never
allowed as destination).
opcodes/
PR gas/13050
* m68k-opc.c (moveb, movew): For ISA_B/C only allow #,d(An) in
addition to ISA_A.
gas/
PR gas/13050
* testsuite/gas/m68k/all.exp: Add tests p13050-1 and p13050-2.
* testsuite/gas/m68k/p13050-1.s: New file.
* testsuite/gas/m68k/p13050-2.d: New file.
* testsuite/gas/m68k/p13050-2.s: New file.
The convention within for relocation names is that they start with the
string "R_", however, this is not so for ARC for the display names of
relocations, however, internally, the names for the relocations types do
have the 'R_' prefix. I suspect that the missing 'R_' on the output
strings was an oversight, as I can't see any comment to the contrary.
To bring ARC into line with other targets, this commit adds the 'R_'
prefix to the output strings used for relocation names, and updates all
of the assembler tests where this was exposed.
bfd/ChangeLog:
* elf32-arc.c (reloc_type_to_name): Change ARC_RELOC_HOWTO to
place 'R_' before the reloc name returned.
(elf_arc_howto_table): Change ARC_RELOC_HOWTO to place 'R_' before
the relocation string.
gas/ChangeLog:
* testsuite/gas/arc/adc.d: Add 'R_' prefix to relocation names.
* testsuite/gas/arc/add.d: Likewise.
* testsuite/gas/arc/and.d: Likewise.
* testsuite/gas/arc/asl.d: Likewise.
* testsuite/gas/arc/asr.d: Likewise.
* testsuite/gas/arc/bic.d: Likewise.
* testsuite/gas/arc/extb.d: Likewise.
* testsuite/gas/arc/extw.d: Likewise.
* testsuite/gas/arc/j.d: Likewise.
* testsuite/gas/arc/jl.d: Likewise.
* testsuite/gas/arc/ld2.d: Likewise.
* testsuite/gas/arc/lsr.d: Likewise.
* testsuite/gas/arc/mov.d: Likewise.
* testsuite/gas/arc/or.d: Likewise.
* testsuite/gas/arc/pcl-relocs.d: Likewise.
* testsuite/gas/arc/pcrel-relocs.d: Likewise.
* testsuite/gas/arc/pic-relocs.d: Likewise.
* testsuite/gas/arc/plt-relocs.d: Likewise.
* testsuite/gas/arc/rlc.d: Likewise.
* testsuite/gas/arc/ror.d: Likewise.
* testsuite/gas/arc/rrc.d: Likewise.
* testsuite/gas/arc/sbc.d: Likewise.
* testsuite/gas/arc/sda-relocs.d: Likewise.
* testsuite/gas/arc/sda-relocs2.d: Likewise.
* testsuite/gas/arc/sexb.d: Likewise.
* testsuite/gas/arc/sexw.d: Likewise.
* testsuite/gas/arc/st.d: Likewise.
* testsuite/gas/arc/sub.d: Likewise.
* testsuite/gas/arc/tls-relocs.d: Likewise.
* testsuite/gas/arc/xor.d: Likewise.
Trevor Saunders
Andrew Burgess
Matthew Wahab
Martin Galvan
H.J. Lu
Alan Modra
Nick Clifton
Claudiu Zissulescu
Maciej W. Rozycki
James Greenhalgh
Jiong Wang
Jose E. Marchesi
Trevor Saunders
Ulrich Drepper
Mickael Guene
Thomas Preud'homme
Joel Sherrill
Renlin Li
Kyrylo Tkachov
Dan Gisselquist
Max Filippov
Vinay Kumar G
Kevin Buettner
Loria
Andrew Senkevich
Catherine Moore
Yoshinori Sato
Peter Bergner
Andreas Schwab