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binutils-gdb/opcodes
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Jim Wilson 1080bf78c0 RISC-V: Accept version, supervisor ext and more than one NSE for -march. 
This patch moves all -march parsing logic into bfd, because we will use this
code in ELF attributes.

	bfd/
	* elfxx-riscv.h (RISCV_DONT_CARE_VERSION): New macro.
	(struct riscv_subset_t): New structure.
	(riscv_subset_t): New typedef.
	(riscv_subset_list_t): New structure.
	(riscv_release_subset_list): New prototype.
	(riscv_add_subset): Likewise.
	(riscv_lookup_subset): Likewise.
	(riscv_lookup_subset_version): Likewise.
	(riscv_release_subset_list): Likewise.
	* elfxx-riscv.c: Include safe-ctype.h.
	(riscv_parsing_subset_version): New function.
	(riscv_supported_std_ext): Likewise.
	(riscv_parse_std_ext): Likewise.
	(riscv_parse_sv_or_non_std_ext): Likewise.
	(riscv_parse_subset): Likewise.
	(riscv_add_subset): Likewise.
	(riscv_lookup_subset): Likewise.
	(riscv_lookup_subset_version): Likewise.
	(riscv_release_subset_list): Likewise.
	gas/
	* config/tc-riscv.c: Include elfxx-riscv.h.
	(struct riscv_subset): Removed.
	(riscv_subsets): Change type to riscv_subset_list_t.
	(riscv_subset_supports): Removed argument: xlen_required and move
	logic into libbfd.
	(riscv_multi_subset_supports): Removed argument: xlen_required.
	(riscv_clear_subsets): Removed.
	(riscv_add_subset): Ditto.
	(riscv_set_arch): Extract parsing logic into libbfd.
	(riscv_ip): Update argument for riscv_multi_subset_supports and
	riscv_subset_supports. Update riscv_subsets due to struct definition
	changed.
	(riscv_after_parse_args): Update riscv_subsets due to struct
	definition changed, update and argument for riscv_subset_supports.
	* testsuite/gas/riscv/empty.s: New.
	* testsuite/gas/riscv/march-fail-rv32ef.d: Likewise.
	* testsuite/gas/riscv/march-fail-rv32ef.l: Likewise.
	* testsuite/gas/riscv/march-fail-rv32i.d: Likewise.
	* testsuite/gas/riscv/march-fail-rv32i.l: Likewise.
	* testsuite/gas/riscv/march-fail-rv32iam.d: Likewise.
	* testsuite/gas/riscv/march-fail-rv32iam.l: Likewise.
	* testsuite/gas/riscv/march-fail-rv32ic.d: Likewise.
	* testsuite/gas/riscv/march-fail-rv32ic.l: Likewise.
	* testsuite/gas/riscv/march-fail-rv32icx2p.d: Likewise.
	* testsuite/gas/riscv/march-fail-rv32icx2p.l: Likewise.
	* testsuite/gas/riscv/march-fail-rv32imc.d: Likewise.
	* testsuite/gas/riscv/march-fail-rv32imc.l: Likewise.
	* testsuite/gas/riscv/march-fail-rv64I.d: Likewise.
	* testsuite/gas/riscv/march-fail-rv64I.l: Likewise.
	* testsuite/gas/riscv/march-fail-rv64e.d: Likewise.
	* testsuite/gas/riscv/march-fail-rv64e.l: Likewise.
	* testsuite/gas/riscv/march-ok-g2.d: Likewise.
	* testsuite/gas/riscv/march-ok-g2p0.d: Likewise.
	* testsuite/gas/riscv/march-ok-i2p0.d: Likewise.
	* testsuite/gas/riscv/march-ok-nse-with-version.: Likewise.d
	* testsuite/gas/riscv/march-ok-s-with-version.d: Likewise.
	* testsuite/gas/riscv/march-ok-s.d: Likewise.
	* testsuite/gas/riscv/march-ok-sx.d: Likewise.
	* testsuite/gas/riscv/march-ok-two-nse.d: Likewise.
	* testsuite/gas/riscv/march-ok-g2_p1.d: Likewise.
	* testsuite/gas/riscv/march-ok-i2p0m2_a2f2.d: Likewise.
	include/
	* opcode/riscv.h (riscv_opcode): Change type of xlen_requirement to
	unsigned.
	opcodes/
	* riscv-opc.c: Change the type of xlen, because type of
	xlen_requirement changed.
 		2018-12-03 14:05:17 -08:00
..
po csky regen 2018-08-01 10:32:56 +09:30
.gitignore
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ChangeLog RISC-V: Accept version, supervisor ext and more than one NSE for -march. 2018-12-03 14:05:17 -08:00
ChangeLog-0001
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ChangeLog-0203
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ChangeLog-2004
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ChangeLog-2005
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ChangeLog-2006
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ChangeLog-2007
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ChangeLog-2008
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ChangeLog-2009
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ChangeLog-2010
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ChangeLog-2011
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ChangeLog-2012
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ChangeLog-2013
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ChangeLog-2014
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ChangeLog-2015
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ChangeLog-2016
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ChangeLog-2017
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ChangeLog-9297
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ChangeLog-9899
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MAINTAINERS
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Makefile.am csky-opc.h: Initialize fields of last array elements 2018-09-21 10:27:49 -04:00
Makefile.in csky-opc.h: Initialize fields of last array elements 2018-09-21 10:27:49 -04:00
aarch64-asm-2.c [BINUTILS, AARCH64, 6/8] Add Tag getting instruction in Memory Tagging Extension 2018-11-12 13:20:58 +00:00
aarch64-asm.c [BINUTILS, AARCH64, 6/8] Add Tag getting instruction in Memory Tagging Extension 2018-11-12 13:20:58 +00:00
aarch64-asm.h [BINUTILS, AARCH64, 6/8] Add Tag getting instruction in Memory Tagging Extension 2018-11-12 13:20:58 +00:00
aarch64-dis-2.c [BINUTILS, AARCH64, 6/8] Add Tag getting instruction in Memory Tagging Extension 2018-11-12 13:20:58 +00:00
aarch64-dis.c [BINUTILS, AARCH64, 6/8] Add Tag getting instruction in Memory Tagging Extension 2018-11-12 13:20:58 +00:00
aarch64-dis.h [BINUTILS, AARCH64, 6/8] Add Tag getting instruction in Memory Tagging Extension 2018-11-12 13:20:58 +00:00
aarch64-gen.c
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aarch64-opc-2.c [BINUTILS, AARCH64, 6/8] Add Tag getting instruction in Memory Tagging Extension 2018-11-12 13:20:58 +00:00
aarch64-opc.c [BINUTILS, AARCH64, 8/8] Add data cache instructions for Memory Tagging Extension 2018-11-12 13:29:38 +00:00
aarch64-opc.h [BINUTILS, AARCH64, 2/8] Add Tag generation instructions in Memory Tagging Extension 2018-11-12 12:59:22 +00:00
aarch64-tbl.h [aarch64] - Only use MOV for disassembly when shifter op is LSL #0 2018-12-03 17:34:33 +00:00
aclocal.m4 csky-opc.h: Initialize fields of last array elements 2018-09-21 10:27:49 -04:00
alpha-dis.c
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alpha-opc.c
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arc-dis.c
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arc-dis.h
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arc-ext-tbl.h
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arc-ext.c
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arc-ext.h
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arc-fxi.h
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arc-nps400-tbl.h ARC: Fix build errors with large constants and C89 2018-09-20 15:49:00 +01:00
arc-opc.c [ARC] Fix decoding of w6 signed short immediate. 2018-07-23 11:09:43 +02:00
arc-regs.h [ARC] Update handling AUX-registers. 2018-08-06 16:41:32 +03:00
arc-tbl.h [ARC] Allow vewt instruction for ARC EM family. 2018-07-23 11:09:43 +02:00
arm-dis.c [BINUTILS, ARM] Add Armv8.5-A to select_arm_features and update macros. 2018-11-06 12:13:45 +00:00
avr-dis.c
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bfin-dis.c
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cgen-asm.c
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cgen-asm.in
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cgen-bitset.c
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cgen-dis.c
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cgen-dis.in
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cgen-ibld.in
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cgen-opc.c
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cgen.sh
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config.in
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configure csky-opc.h: Initialize fields of last array elements 2018-09-21 10:27:49 -04:00
configure.ac csky-opc.h: Initialize fields of last array elements 2018-09-21 10:27:49 -04:00
configure.com
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cr16-dis.c
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cr16-opc.c
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cris-dis.c
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cris-opc.c
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crx-dis.c
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crx-opc.c
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csky-dis.c Add support for the C_SKY series of processors. 2018-07-30 12:24:14 +01:00
csky-opc.h csky-opc.h: Initialize fields of last array elements 2018-09-21 10:27:49 -04:00
d10v-dis.c
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d10v-opc.c
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d30v-dis.c
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d30v-opc.c
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dep-in.sed
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dis-buf.c
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dis-init.c
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disassemble.c Andes Technology has good news for you, we plan to update the nds32 port of binutils on upstream! 2018-09-20 13:32:58 +01:00
disassemble.h Add support for the C_SKY series of processors. 2018-07-30 12:24:14 +01:00
dlx-dis.c
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epiphany-asm.c
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epiphany-desc.c
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epiphany-desc.h
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epiphany-dis.c
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epiphany-ibld.c
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epiphany-opc.c
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epiphany-opc.h
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fr30-asm.c
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fr30-desc.c
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fr30-desc.h
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fr30-dis.c
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fr30-ibld.c
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fr30-opc.c
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fr30-opc.h
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frv-asm.c
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frv-desc.c
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frv-desc.h
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frv-dis.c
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frv-ibld.c
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frv-opc.c
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frv-opc.h
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ft32-dis.c
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ft32-opc.c
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h8300-dis.c
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hppa-dis.c
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i386-dis-evex.h x86: correctly handle VPBROADCASTD with EVEX.W set outside of 64-bit mode 2018-11-06 11:45:49 +01:00
i386-dis.c x86: correctly handle VMOVD with EVEX.W set outside of 64-bit mode 2018-11-06 11:45:11 +01:00
i386-gen.c x86: fold Size{16,32,64} template attributes 2018-10-10 08:41:52 +02:00
i386-init.h x86: Add CpuCMOV and CpuFXSR 2018-08-11 14:37:32 -07:00
i386-opc.c
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i386-opc.h x86: fold Size{16,32,64} template attributes 2018-10-10 08:41:52 +02:00
i386-opc.tbl x86: adjust {,E}VEX.W handling for PEXTR* / PINSR* 2018-11-06 11:43:55 +01:00
i386-reg.tbl x86: fold RegEip/RegRip and RegEiz/RegRiz 2018-08-06 08:34:36 +02:00
i386-tbl.h x86: adjust {,E}VEX.W handling for PEXTR* / PINSR* 2018-11-06 11:43:55 +01:00
ia64-asmtab.c
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ia64-asmtab.h
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ia64-dis.c
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ia64-gen.c
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ia64-ic.tbl
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ia64-opc-a.c
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ia64-opc-b.c
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ia64-opc-d.c
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ia64-opc-f.c
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ia64-opc-i.c
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ia64-opc-m.c
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ia64-opc-x.c
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ia64-opc.c
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ia64-opc.h
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ia64-raw.tbl
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ia64-war.tbl
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ia64-waw.tbl
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ip2k-asm.c
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ip2k-desc.c
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ip2k-desc.h
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ip2k-dis.c
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ip2k-ibld.c
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ip2k-opc.c
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ip2k-opc.h
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iq2000-asm.c
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iq2000-desc.c
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iq2000-desc.h
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iq2000-dis.c
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iq2000-ibld.c
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iq2000-opc.c
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iq2000-opc.h
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lm32-asm.c
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lm32-desc.c
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lm32-desc.h
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lm32-dis.c
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lm32-ibld.c
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lm32-opc.c
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lm32-opc.h
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lm32-opinst.c
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m32c-asm.c
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m32c-desc.c
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m32c-desc.h
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m32c-dis.c
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m32c-ibld.c
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m32c-opc.c
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m32c-opc.h
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m32r-asm.c
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m32r-desc.c
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m32r-desc.h
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m32r-dis.c
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m32r-ibld.c
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m32r-opc.c
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m32r-opc.h
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m32r-opinst.c
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m68hc11-dis.c
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m68hc11-opc.c
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m68k-dis.c
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m68k-opc.c
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m10200-dis.c
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m10200-opc.c
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m10300-dis.c
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m10300-opc.c
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makefile.vms
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mcore-dis.c
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mcore-opc.h
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mep-asm.c
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mep-desc.c
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mep-desc.h
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mep-dis.c
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mep-ibld.c
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mep-opc.c
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mep-opc.h
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metag-dis.c
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microblaze-dis.c
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microblaze-dis.h
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microblaze-opc.h
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microblaze-opcm.h
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micromips-opc.c
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mips-dis.c [MIPS] Add Loongson 2K1000 proccessor support. 2018-08-29 20:55:25 +08:00
mips-formats.h
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mips-opc.c [MIPS] Add Loongson 3A1000 proccessor support. 2018-08-29 20:32:30 +08:00
mips16-opc.c
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mmix-dis.c
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mmix-opc.c
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moxie-dis.c
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moxie-opc.c
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msp430-decode.c
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msp430-decode.opc
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msp430-dis.c
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mt-asm.c
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mt-desc.c
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mt-desc.h
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mt-dis.c
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mt-ibld.c
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mt-opc.c
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mt-opc.h
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nds32-asm.c Andes Technology has good news for you, we plan to update the nds32 port of binutils on upstream! 2018-09-20 13:32:58 +01:00
nds32-asm.h Andes Technology has good news for you, we plan to update the nds32 port of binutils on upstream! 2018-09-20 13:32:58 +01:00
nds32-dis.c Andes Technology has good news for you, we plan to update the nds32 port of binutils on upstream! 2018-09-20 13:32:58 +01:00
nds32-opc.h
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nfp-dis.c opcodes/nfp: Fix disassembly of crc[] with swapped operands. 2018-11-13 15:33:21 +02:00
nios2-dis.c Fix incorrect extraction of signed constants in nios2 disassembler. 2018-09-23 12:31:23 -07:00
nios2-opc.c
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ns32k-dis.c
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opc2c.c
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opintl.h
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or1k-asm.c or1k: Add the l.adrp insn and supporting relocations 2018-10-05 11:41:41 +09:00
or1k-desc.c or1k: Add the l.muld, l.muldu, l.macu, l.msbu insns 2018-10-05 11:41:42 +09:00
or1k-desc.h or1k: Add the l.muld, l.muldu, l.macu, l.msbu insns 2018-10-05 11:41:42 +09:00
or1k-dis.c or1k: Add the l.adrp insn and supporting relocations 2018-10-05 11:41:41 +09:00
or1k-ibld.c or1k: Add the l.adrp insn and supporting relocations 2018-10-05 11:41:41 +09:00
or1k-opc.c or1k: Add the l.muld, l.muldu, l.macu, l.msbu insns 2018-10-05 11:41:42 +09:00
or1k-opc.h or1k: Add the l.muld, l.muldu, l.macu, l.msbu insns 2018-10-05 11:41:42 +09:00
or1k-opinst.c or1k: Add the l.muld, l.muldu, l.macu, l.msbu insns 2018-10-05 11:41:42 +09:00
pdp11-dis.c
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pdp11-opc.c
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pj-dis.c
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pj-opc.c
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ppc-dis.c Use operand->extract to provide defaults for optional PowerPC operands 2018-08-21 16:05:36 +09:30
ppc-opc.c PowerPC instruction mask checks 2018-11-06 21:17:28 +10:30
pru-dis.c
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pru-opc.c
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riscv-dis.c RISC-V: Accept version, supervisor ext and more than one NSE for -march. 2018-12-03 14:05:17 -08:00
riscv-opc.c RISC-V: Add missing c.unimp instruction. 2018-11-29 13:10:38 -08:00
rl78-decode.c
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rl78-decode.opc
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rl78-dis.c
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rx-decode.c
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rx-decode.opc
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rx-dis.c
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s12z-dis.c S12Z opcodes: Fix bug disassembling certain shift instructions. 2018-11-21 21:34:47 +01:00
s390-dis.c
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s390-mkopc.c
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s390-opc.c
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s390-opc.txt S/390: Support vector alignment hints 2018-10-23 18:13:01 +02:00
score-dis.c
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score-opc.h
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score7-dis.c
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sh-dis.c
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sh-opc.h Tidy bit twiddling 2018-08-20 09:54:20 +09:30
sparc-dis.c
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sparc-opc.c sparc/leon: add support for partial write psr instruction 2018-08-29 20:52:28 +02:00
spu-dis.c
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spu-opc.c
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stamp-h.in
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sysdep.h
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tic4x-dis.c
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tic6x-dis.c
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tic30-dis.c
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tic54x-dis.c
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tic54x-opc.c
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tic80-dis.c
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tic80-opc.c
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tilegx-dis.c
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tilegx-opc.c
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tilepro-dis.c
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tilepro-opc.c
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v850-dis.c
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v850-opc.c
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vax-dis.c
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visium-dis.c
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visium-opc.c
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wasm32-dis.c
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xc16x-asm.c
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xc16x-desc.c
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xc16x-desc.h
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xc16x-dis.c
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xc16x-ibld.c
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xc16x-opc.c
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xc16x-opc.h
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xgate-dis.c
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xgate-opc.c
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xstormy16-asm.c
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xstormy16-desc.c
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xstormy16-desc.h
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xstormy16-dis.c
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xstormy16-ibld.c
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xstormy16-opc.c
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xstormy16-opc.h
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xtensa-dis.c
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z8k-dis.c
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z8k-opc.h
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z8kgen.c
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z80-dis.c
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