2005-04-05 13:26:48 +02:00
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;;- Machine description for Blackfin for GNU compiler
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2022-01-03 10:42:10 +01:00
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;; Copyright (C) 2005-2022 Free Software Foundation, Inc.
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2005-04-05 13:26:48 +02:00
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;; Contributed by Analog Devices.
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;; This file is part of GCC.
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;; GCC is free software; you can redistribute it and/or modify it
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;; under the terms of the GNU General Public License as published
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host-hpux.c: Change copyright header to refer to version 3 of the GNU General Public License...
* config/host-hpux.c: Change copyright header to refer to version 3 of the GNU
General Public License and to point readers at the COPYING3 file and the FSF's
license web page.
* config/alpha/predicates.md, config/alpha/vms-ld.c,
config/alpha/linux.h, config/alpha/alpha.opt,
config/alpha/linux-elf.h, config/alpha/vms.h, config/alpha/elf.h,
config/alpha/vms-unwind.h, config/alpha/ev4.md,
config/alpha/ev6.md, config/alpha/alpha.c, config/alpha/vms-cc.c,
config/alpha/alpha.h, config/alpha/sync.md,
config/alpha/openbsd.h, config/alpha/alpha.md,
config/alpha/alpha-modes.def, config/alpha/ev5.md,
config/alpha/alpha-protos.h, config/alpha/freebsd.h,
config/alpha/osf5.h, config/alpha/netbsd.h, config/alpha/vms64.h,
config/alpha/constraints.md, config/alpha/osf.h,
config/alpha/xm-vms.h, config/alpha/unicosmk.h, config/linux.h,
config/frv/predicates.md, config/frv/frv.h, config/frv/linux.h,
config/frv/frv.md, config/frv/frv.opt, config/frv/frv-modes.def,
config/frv/frv-asm.h, config/frv/frv-protos.h,
config/frv/frv-abi.h, config/frv/frv.c, config/s390/tpf.h,
config/s390/s390.c, config/s390/predicates.md, config/s390/s390.h,
config/s390/linux.h, config/s390/tpf.md, config/s390/tpf.opt,
config/s390/2064.md, config/s390/2084.md, config/s390/s390.md,
config/s390/s390.opt, config/s390/s390-modes.def,
config/s390/fixdfdi.h, config/s390/constraints.md,
config/s390/s390-protos.h, config/s390/s390x.h, config/elfos.h,
config/dbxcoff.h, config/m32c/predicates.md, config/m32c/cond.md,
config/m32c/m32c.c, config/m32c/minmax.md, config/m32c/blkmov.md,
config/m32c/m32c-pragma.c, config/m32c/m32c.h,
config/m32c/prologue.md, config/m32c/m32c.abi,
config/m32c/muldiv.md, config/m32c/bitops.md, config/m32c/mov.md,
config/m32c/addsub.md, config/m32c/m32c.md, config/m32c/m32c.opt,
config/m32c/t-m32c, config/m32c/m32c-modes.def,
config/m32c/jump.md, config/m32c/shift.md,
config/m32c/m32c-protos.h, config/libgloss.h,
config/spu/spu-protos.h, config/spu/predicates.md,
config/spu/spu-builtins.h, config/spu/spu.c,
config/spu/spu-builtins.def, config/spu/spu-builtins.md,
config/spu/spu.h, config/spu/spu-elf.h, config/spu/constraints.md,
config/spu/spu.md, config/spu/spu-c.c, config/spu/spu.opt,
config/spu/spu-modes.def, config/spu/t-spu-elf, config/interix.h,
config/sparc/hypersparc.md, config/sparc/predicates.md,
config/sparc/linux.h, config/sparc/sp64-elf.h,
config/sparc/supersparc.md, config/sparc/cypress.md,
config/sparc/openbsd1-64.h, config/sparc/openbsd64.h,
config/sparc/niagara.md, config/sparc/sparc.md,
config/sparc/long-double-switch.opt, config/sparc/ultra3.md,
config/sparc/sparc.opt, config/sparc/sync.md,
config/sparc/sp-elf.h, config/sparc/sparc-protos.h,
config/sparc/ultra1_2.md, config/sparc/biarch64.h,
config/sparc/sparc.c, config/sparc/little-endian.opt,
config/sparc/sysv4-only.h, config/sparc/sparc.h,
config/sparc/linux64.h, config/sparc/freebsd.h,
config/sparc/sol2.h, config/sparc/rtemself.h,
config/sparc/netbsd-elf.h, config/sparc/vxworks.h,
config/sparc/sparc-modes.def, config/sparc/sparclet.md,
config/sparc/sysv4.h, config/vx-common.h, config/netbsd-aout.h,
config/flat.h, config/m32r/m32r.md, config/m32r/predicates.md,
config/m32r/little.h, config/m32r/m32r.c, config/m32r/m32r.opt,
config/m32r/linux.h, config/m32r/constraints.md,
config/m32r/m32r.h, config/m32r/m32r-protos.h, config/vxworks.opt,
config/darwin-c.c, config/darwin.opt, config/i386/i386.h,
config/i386/cygming.h, config/i386/linux.h, config/i386/cygwin.h,
config/i386/i386.md, config/i386/netware-crt0.c,
config/i386/sco5.h, config/i386/mmx.md, config/i386/vx-common.h,
config/i386/kaos-i386.h, config/i386/winnt-stubs.c,
config/i386/netbsd64.h, config/i386/djgpp.h, config/i386/gas.h,
config/i386/sol2.h, config/i386/constraints.md,
config/i386/netware-libgcc.c, config/i386/sysv5.h,
config/i386/predicates.md, config/i386/geode.md,
config/i386/x86-64.h, config/i386/kfreebsd-gnu.h,
config/i386/freebsd64.h, config/i386/vxworksae.h,
config/i386/pentium.md, config/i386/lynx.h, config/i386/i386elf.h,
config/i386/rtemself.h, config/i386/netbsd-elf.h,
config/i386/ppro.md, config/i386/k6.md, config/i386/netware.c,
config/i386/netware.h, config/i386/i386-modes.def,
config/i386/sysv4-cpp.h, config/i386/i386-interix.h,
config/i386/cygwin1.c, config/i386/djgpp.opt, config/i386/uwin.h,
config/i386/unix.h, config/i386/ptx4-i.h, config/i386/xm-djgpp.h,
config/i386/att.h, config/i386/winnt.c, config/i386/beos-elf.h,
config/i386/sol2-10.h, config/i386/darwin64.h, config/i386/sse.md,
config/i386/i386.opt, config/i386/bsd.h, config/i386/cygming.opt,
config/i386/xm-mingw32.h, config/i386/linux64.h,
config/i386/openbsdelf.h, config/i386/xm-cygwin.h,
config/i386/sco5.opt, config/i386/darwin.h, config/i386/mingw32.h,
config/i386/winnt-cxx.c, config/i386/i386-interix3.h,
config/i386/nwld.c, config/i386/nwld.h, config/i386/host-cygwin.c,
config/i386/cygwin2.c, config/i386/i386-protos.h,
config/i386/sync.md, config/i386/openbsd.h,
config/i386/host-mingw32.c, config/i386/i386-aout.h,
config/i386/nto.h, config/i386/biarch64.h,
config/i386/i386-coff.h, config/i386/freebsd.h,
config/i386/driver-i386.c, config/i386/knetbsd-gnu.h,
config/i386/host-i386-darwin.c, config/i386/vxworks.h,
config/i386/crtdll.h, config/i386/i386.c, config/i386/sysv4.h,
config/darwin-protos.h, config/linux.opt, config/sol2.c,
config/sol2.h, config/sh/symbian.c, config/sh/sh-protos.h,
config/sh/linux.h, config/sh/elf.h, config/sh/superh.h,
config/sh/sh4.md, config/sh/coff.h, config/sh/newlib.h,
config/sh/embed-elf.h, config/sh/symbian-pre.h, config/sh/rtems.h,
config/sh/kaos-sh.h, config/sh/sh4a.md, config/sh/constraints.md,
config/sh/sh64.h, config/sh/sh.opt, config/sh/symbian-post.h,
config/sh/sh-c.c, config/sh/predicates.md, config/sh/sh.c,
config/sh/sh.h, config/sh/shmedia.md, config/sh/sh-modes.def,
config/sh/little.h, config/sh/sh1.md, config/sh/sh4-300.md,
config/sh/superh64.h, config/sh/rtemself.h,
config/sh/netbsd-elf.h, config/sh/sh.md, config/sh/vxworks.h,
config/usegas.h, config/svr3.h, config/pdp11/pdp11-protos.h,
config/pdp11/2bsd.h, config/pdp11/pdp11.md, config/pdp11/pdp11.c,
config/pdp11/pdp11.opt, config/pdp11/pdp11-modes.def,
config/pdp11/pdp11.h, config/avr/rtems.h, config/avr/avr-protos.h,
config/avr/predicates.md, config/avr/constraints.md,
config/avr/avr.md, config/avr/avr.c, config/avr/avr.opt,
config/avr/avr.h, config/sol2-protos.h, config/dbxelf.h,
config/lynx.opt, config/crx/crx.h, config/crx/crx-protos.h,
config/crx/crx.md, config/crx/crx.c, config/crx/crx.opt,
config/c4x/c4x-c.c, config/c4x/c4x.c, config/c4x/c4x.opt,
config/c4x/c4x-modes.def, config/c4x/rtems.h,
config/c4x/predicates.md, config/c4x/c4x.h,
config/c4x/c4x-protos.h, config/c4x/c4x.md, config/kfreebsd-gnu.h,
config/xtensa/predicates.md, config/xtensa/xtensa.c,
config/xtensa/linux.h, config/xtensa/xtensa.h,
config/xtensa/elf.h, config/xtensa/xtensa.md,
config/xtensa/xtensa.opt, config/xtensa/constraints.md,
config/xtensa/xtensa-protos.h, config/dbx.h,
config/stormy16/predicates.md, config/stormy16/stormy16.md,
config/stormy16/stormy16.c, config/stormy16/stormy16.opt,
config/stormy16/stormy16.h, config/stormy16/stormy16-protos.h,
config/host-solaris.c, config/fr30/fr30.h,
config/fr30/predicates.md, config/fr30/fr30-protos.h,
config/fr30/fr30.md, config/fr30/fr30.c, config/fr30/fr30.opt,
config/vxworksae.h, config/sol2-c.c, config/lynx.h,
config/m68hc11/m68hc11-protos.h, config/m68hc11/predicates.md,
config/m68hc11/m68hc11.md, config/m68hc11/m68hc11.c,
config/m68hc11/m68hc11.opt, config/m68hc11/m68hc11.h,
config/m68hc11/m68hc12.h, config/openbsd-oldgas.h,
config/host-linux.c, config/interix3.h, config/cris/cris.c,
config/cris/predicates.md, config/cris/linux.h,
config/cris/cris.h, config/cris/aout.h, config/cris/cris.md,
config/cris/linux.opt, config/cris/cris.opt, config/cris/elf.opt,
config/cris/aout.opt, config/cris/cris-protos.h,
config/vxworks-dummy.h, config/netbsd.h, config/netbsd-elf.h,
config/iq2000/iq2000.h, config/iq2000/predicates.md,
config/iq2000/iq2000-protos.h, config/iq2000/iq2000.md,
config/iq2000/iq2000.c, config/iq2000/iq2000.opt,
config/host-darwin.c, config/mt/mt.md, config/mt/mt.c,
config/mt/mt.opt, config/mt/t-mt, config/mt/mt.h,
config/mt/mt-protos.h, config/svr4.h, config/host-darwin.h,
config/chorus.h, config/mn10300/mn10300.c,
config/mn10300/mn10300.opt, config/mn10300/predicates.md,
config/mn10300/mn10300.h, config/mn10300/linux.h,
config/mn10300/constraints.md, config/mn10300/mn10300-protos.h,
config/mn10300/mn10300.md, config/ia64/predicates.md,
config/ia64/itanium1.md, config/ia64/unwind-ia64.h,
config/ia64/ia64-c.c, config/ia64/sync.md, config/ia64/ia64.c,
config/ia64/itanium2.md, config/ia64/ia64.h, config/ia64/vect.md,
config/ia64/freebsd.h, config/ia64/ia64.md,
config/ia64/ia64-modes.def, config/ia64/constraints.md,
config/ia64/hpux.h, config/ia64/ia64-protos.h, config/windiss.h,
config/gofast.h, config/rtems.h, config/sol2-10.h,
config/m68k/predicates.md, config/m68k/m68k.md,
config/m68k/linux.h, config/m68k/m68k-modes.def,
config/m68k/print-sysroot-suffix.sh, config/m68k/m68k-protos.h,
config/m68k/coff.h, config/m68k/m68k-none.h, config/m68k/ieee.opt,
config/m68k/openbsd.h, config/m68k/m68k-aout.h,
config/m68k/m68k.opt, config/m68k/m68020-elf.h,
config/m68k/m68kelf.h, config/m68k/m68k-devices.def,
config/m68k/uclinux-oldabi.h, config/m68k/m68k.c,
config/m68k/constraints.md, config/m68k/rtemself.h,
config/m68k/netbsd-elf.h, config/m68k/m68k.h,
config/m68k/uclinux.h, config/rs6000/power4.md,
config/rs6000/host-darwin.c, config/rs6000/6xx.md,
config/rs6000/linux.h, config/rs6000/eabi.h,
config/rs6000/aix41.opt, config/rs6000/xcoff.h,
config/rs6000/secureplt.h, config/rs6000/linuxspe.h,
config/rs6000/eabialtivec.h, config/rs6000/8540.md,
config/rs6000/darwin8.h, config/rs6000/kaos-ppc.h,
config/rs6000/windiss.h, config/rs6000/603.md,
config/rs6000/aix41.h, config/rs6000/cell.md,
config/rs6000/mpc.md, config/rs6000/aix43.h, config/rs6000/beos.h,
config/rs6000/gnu.h, config/rs6000/rtems.h, config/rs6000/aix.opt,
config/rs6000/darwin.md, config/rs6000/darwin64.h,
config/rs6000/default64.h, config/rs6000/7xx.md,
config/rs6000/darwin.opt, config/rs6000/spe.md,
config/rs6000/rs6000.opt, config/rs6000/rs6000-c.c,
config/rs6000/rios2.md, config/rs6000/linuxaltivec.h,
config/rs6000/7450.md, config/rs6000/linux64.h,
config/rs6000/constraints.md, config/rs6000/440.md,
config/rs6000/darwin.h, config/rs6000/host-ppc64-darwin.c,
config/rs6000/rs6000.c, config/rs6000/aix52.h,
config/rs6000/rs6000.h, config/rs6000/power6.md,
config/rs6000/predicates.md, config/rs6000/altivec.md,
config/rs6000/aix64.opt, config/rs6000/rios1.md,
config/rs6000/rs6000-modes.def, config/rs6000/rs64.md,
config/rs6000/eabisim.h, config/rs6000/sysv4le.h,
config/rs6000/darwin7.h, config/rs6000/dfp.md,
config/rs6000/linux64.opt, config/rs6000/sync.md,
config/rs6000/vxworksae.h, config/rs6000/power5.md,
config/rs6000/lynx.h, config/rs6000/biarch64.h,
config/rs6000/rs6000.md, config/rs6000/sysv4.opt,
config/rs6000/eabispe.h, config/rs6000/e500.h,
config/rs6000/freebsd.h, config/rs6000/rs6000-protos.h,
config/rs6000/netbsd.h, config/rs6000/e500-double.h,
config/rs6000/aix.h, config/rs6000/vxworks.h,
config/rs6000/40x.md, config/rs6000/aix51.h,
config/rs6000/sysv4.h, config/arc/arc-protos.h, config/arc/arc.md,
config/arc/arc.c, config/arc/arc.opt, config/arc/arc-modes.def,
config/arc/arc.h, config/mcore/mcore-elf.h,
config/mcore/mcore-protos.h, config/mcore/predicates.md,
config/mcore/mcore.md, config/mcore/mcore.c,
config/mcore/mcore.opt, config/mcore/mcore.h,
config/mcore/mcore-pe.h, config/darwin.c, config/freebsd-nthr.h,
config/score/predicates.md, config/score/score-version.h,
config/score/score-protos.h, config/score/misc.md,
config/score/elf.h, config/score/score.c, config/score/mac.md,
config/score/score7.md, config/score/score.h,
config/score/score-conv.h, config/score/score-mdaux.c,
config/score/score.md, config/score/score.opt,
config/score/score-modes.def, config/score/score-mdaux.h,
config/score/mul-div.S, config/arm/uclinux-elf.h,
config/arm/semi.h, config/arm/ecos-elf.h, config/arm/arm1020e.md,
config/arm/symbian.h, config/arm/linux-elf.h,
config/arm/arm1026ejs.md, config/arm/arm1136jfs.md,
config/arm/elf.h, config/arm/aout.h, config/arm/arm.c,
config/arm/thumb2.md, config/arm/vec-common.md, config/arm/coff.h,
config/arm/strongarm-pe.h, config/arm/arm.h,
config/arm/cortex-a8-neon.md, config/arm/semiaof.h,
config/arm/cortex-a8.md, config/arm/uclinux-eabi.h,
config/arm/arm-modes.def, config/arm/linux-eabi.h,
config/arm/rtems-elf.h, config/arm/neon-schedgen.ml,
config/arm/arm-cores.def, config/arm/arm-protos.h,
config/arm/vfp.md, config/arm/aof.h, config/arm/linux-gas.h,
config/arm/wince-pe.h, config/arm/neon.md,
config/arm/constraints.md, config/arm/neon.ml,
config/arm/xscale-elf.h, config/arm/strongarm-coff.h,
config/arm/arm.opt, config/arm/arm926ejs.md,
config/arm/predicates.md, config/arm/iwmmxt.md,
config/arm/arm_neon.h, config/arm/unknown-elf.h,
config/arm/kaos-arm.h, config/arm/bpabi.h, config/arm/pe.opt,
config/arm/neon-testgen.ml, config/arm/arm.md,
config/arm/xscale-coff.h, config/arm/pe.c,
config/arm/arm-generic.md, config/arm/pe.h,
config/arm/kaos-strongarm.h, config/arm/freebsd.h,
config/arm/neon-docgen.ml, config/arm/netbsd.h, config/arm/fpa.md,
config/arm/strongarm-elf.h, config/arm/cirrus.md,
config/arm/netbsd-elf.h, config/arm/vxworks.h,
config/arm/neon-gen.ml, config/kaos.h, config/darwin-driver.c,
config/pa/predicates.md, config/pa/pa64-hpux.h,
config/pa/pa-hpux.opt, config/pa/som.h, config/pa/pa-hpux1010.opt,
config/pa/pa-hpux1111.opt, config/pa/pa-pro-end.h,
config/pa/elf.h, config/pa/fptr.c, config/pa/pa64-linux.h,
config/pa/pa.md, config/pa/pa.opt, config/pa/pa-hpux.h,
config/pa/pa-hpux10.h, config/pa/pa-hpux11.h,
config/pa/pa-hpux1010.h, config/pa/pa-protos.h,
config/pa/pa-osf.h, config/pa/pa-hpux1111.h, config/pa/pa-64.h,
config/pa/milli64.S, config/pa/pa.c, config/pa/pa-linux.h,
config/pa/pa.h, config/pa/pa32-linux.h, config/pa/pa64-hpux.opt,
config/pa/pa64-regs.h, config/pa/pa-modes.def,
config/pa/constraints.md, config/darwin9.h, config/mips/4100.md,
config/mips/linux.h, config/mips/elfoabi.h, config/mips/elf.h,
config/mips/sdb.h, config/mips/windiss.h, config/mips/rtems.h,
config/mips/3000.md, config/mips/iris5.h, config/mips/5000.md,
config/mips/7000.md, config/mips/9000.md, config/mips/4600.md,
config/mips/linux64.h, config/mips/elforion.h,
config/mips/constraints.md, config/mips/generic.md,
config/mips/predicates.md, config/mips/4300.md,
config/mips/mips-ps-3d.md, config/mips/iris.h, config/mips/24k.md,
config/mips/mips.md, config/mips/mips.opt, config/mips/4k.md,
config/mips/5k.md, config/mips/vr4120-div.S,
config/mips/openbsd.h, config/mips/iris6.h, config/mips/4000.md,
config/mips/mips-protos.h, config/mips/6000.md,
config/mips/mips.c, config/mips/mips.h, config/mips/r3900.h,
config/mips/74k.md, config/mips/netbsd.h, config/mips/vxworks.h,
config/mips/mips-modes.def, config/mips/vr.h,
config/soft-fp/t-softfp, config/openbsd.h, config/ptx4.h,
config/freebsd-spec.h, config/vax/vax.c, config/vax/openbsd.h,
config/vax/vax.h, config/vax/elf.h, config/vax/vax.md,
config/vax/bsd.h, config/vax/vax.opt, config/vax/vax-modes.def,
config/vax/openbsd1.h, config/vax/netbsd.h,
config/vax/vax-protos.h, config/vax/netbsd-elf.h,
config/vax/vaxv.h, config/vax/ultrix.h, config/freebsd.h,
config/h8300/rtems.h, config/h8300/predicates.md,
config/h8300/h8300.c, config/h8300/h8300.h, config/h8300/elf.h,
config/h8300/h8300.md, config/h8300/h8300.opt,
config/h8300/coff.h, config/h8300/h8300-protos.h,
config/v850/v850.md, config/v850/predicates.md,
config/v850/v850-c.c, config/v850/v850.c, config/v850/v850.opt,
config/v850/v850.h, config/v850/v850-protos.h, config/vxworks.c,
config/knetbsd-gnu.h, config/sol2-6.h, config/vxworks.h,
config/mmix/mmix.h, config/mmix/predicates.md,
config/mmix/mmix-protos.h, config/mmix/mmix.md,
config/mmix/mmix.c, config/mmix/mmix.opt,
config/mmix/mmix-modes.def, config/bfin/bfin.opt,
config/bfin/rtems.h, config/bfin/bfin-modes.def,
config/bfin/predicates.md, config/bfin/bfin-protos.h,
config/bfin/bfin.c, config/bfin/bfin.h, config/bfin/bfin.md: Likewise.
From-SVN: r127157
2007-08-02 12:49:31 +02:00
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;; by the Free Software Foundation; either version 3, or (at your
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2005-04-05 13:26:48 +02:00
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;; option) any later version.
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;; GCC is distributed in the hope that it will be useful, but WITHOUT
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;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
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;; License for more details.
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;; You should have received a copy of the GNU General Public License
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host-hpux.c: Change copyright header to refer to version 3 of the GNU General Public License...
* config/host-hpux.c: Change copyright header to refer to version 3 of the GNU
General Public License and to point readers at the COPYING3 file and the FSF's
license web page.
* config/alpha/predicates.md, config/alpha/vms-ld.c,
config/alpha/linux.h, config/alpha/alpha.opt,
config/alpha/linux-elf.h, config/alpha/vms.h, config/alpha/elf.h,
config/alpha/vms-unwind.h, config/alpha/ev4.md,
config/alpha/ev6.md, config/alpha/alpha.c, config/alpha/vms-cc.c,
config/alpha/alpha.h, config/alpha/sync.md,
config/alpha/openbsd.h, config/alpha/alpha.md,
config/alpha/alpha-modes.def, config/alpha/ev5.md,
config/alpha/alpha-protos.h, config/alpha/freebsd.h,
config/alpha/osf5.h, config/alpha/netbsd.h, config/alpha/vms64.h,
config/alpha/constraints.md, config/alpha/osf.h,
config/alpha/xm-vms.h, config/alpha/unicosmk.h, config/linux.h,
config/frv/predicates.md, config/frv/frv.h, config/frv/linux.h,
config/frv/frv.md, config/frv/frv.opt, config/frv/frv-modes.def,
config/frv/frv-asm.h, config/frv/frv-protos.h,
config/frv/frv-abi.h, config/frv/frv.c, config/s390/tpf.h,
config/s390/s390.c, config/s390/predicates.md, config/s390/s390.h,
config/s390/linux.h, config/s390/tpf.md, config/s390/tpf.opt,
config/s390/2064.md, config/s390/2084.md, config/s390/s390.md,
config/s390/s390.opt, config/s390/s390-modes.def,
config/s390/fixdfdi.h, config/s390/constraints.md,
config/s390/s390-protos.h, config/s390/s390x.h, config/elfos.h,
config/dbxcoff.h, config/m32c/predicates.md, config/m32c/cond.md,
config/m32c/m32c.c, config/m32c/minmax.md, config/m32c/blkmov.md,
config/m32c/m32c-pragma.c, config/m32c/m32c.h,
config/m32c/prologue.md, config/m32c/m32c.abi,
config/m32c/muldiv.md, config/m32c/bitops.md, config/m32c/mov.md,
config/m32c/addsub.md, config/m32c/m32c.md, config/m32c/m32c.opt,
config/m32c/t-m32c, config/m32c/m32c-modes.def,
config/m32c/jump.md, config/m32c/shift.md,
config/m32c/m32c-protos.h, config/libgloss.h,
config/spu/spu-protos.h, config/spu/predicates.md,
config/spu/spu-builtins.h, config/spu/spu.c,
config/spu/spu-builtins.def, config/spu/spu-builtins.md,
config/spu/spu.h, config/spu/spu-elf.h, config/spu/constraints.md,
config/spu/spu.md, config/spu/spu-c.c, config/spu/spu.opt,
config/spu/spu-modes.def, config/spu/t-spu-elf, config/interix.h,
config/sparc/hypersparc.md, config/sparc/predicates.md,
config/sparc/linux.h, config/sparc/sp64-elf.h,
config/sparc/supersparc.md, config/sparc/cypress.md,
config/sparc/openbsd1-64.h, config/sparc/openbsd64.h,
config/sparc/niagara.md, config/sparc/sparc.md,
config/sparc/long-double-switch.opt, config/sparc/ultra3.md,
config/sparc/sparc.opt, config/sparc/sync.md,
config/sparc/sp-elf.h, config/sparc/sparc-protos.h,
config/sparc/ultra1_2.md, config/sparc/biarch64.h,
config/sparc/sparc.c, config/sparc/little-endian.opt,
config/sparc/sysv4-only.h, config/sparc/sparc.h,
config/sparc/linux64.h, config/sparc/freebsd.h,
config/sparc/sol2.h, config/sparc/rtemself.h,
config/sparc/netbsd-elf.h, config/sparc/vxworks.h,
config/sparc/sparc-modes.def, config/sparc/sparclet.md,
config/sparc/sysv4.h, config/vx-common.h, config/netbsd-aout.h,
config/flat.h, config/m32r/m32r.md, config/m32r/predicates.md,
config/m32r/little.h, config/m32r/m32r.c, config/m32r/m32r.opt,
config/m32r/linux.h, config/m32r/constraints.md,
config/m32r/m32r.h, config/m32r/m32r-protos.h, config/vxworks.opt,
config/darwin-c.c, config/darwin.opt, config/i386/i386.h,
config/i386/cygming.h, config/i386/linux.h, config/i386/cygwin.h,
config/i386/i386.md, config/i386/netware-crt0.c,
config/i386/sco5.h, config/i386/mmx.md, config/i386/vx-common.h,
config/i386/kaos-i386.h, config/i386/winnt-stubs.c,
config/i386/netbsd64.h, config/i386/djgpp.h, config/i386/gas.h,
config/i386/sol2.h, config/i386/constraints.md,
config/i386/netware-libgcc.c, config/i386/sysv5.h,
config/i386/predicates.md, config/i386/geode.md,
config/i386/x86-64.h, config/i386/kfreebsd-gnu.h,
config/i386/freebsd64.h, config/i386/vxworksae.h,
config/i386/pentium.md, config/i386/lynx.h, config/i386/i386elf.h,
config/i386/rtemself.h, config/i386/netbsd-elf.h,
config/i386/ppro.md, config/i386/k6.md, config/i386/netware.c,
config/i386/netware.h, config/i386/i386-modes.def,
config/i386/sysv4-cpp.h, config/i386/i386-interix.h,
config/i386/cygwin1.c, config/i386/djgpp.opt, config/i386/uwin.h,
config/i386/unix.h, config/i386/ptx4-i.h, config/i386/xm-djgpp.h,
config/i386/att.h, config/i386/winnt.c, config/i386/beos-elf.h,
config/i386/sol2-10.h, config/i386/darwin64.h, config/i386/sse.md,
config/i386/i386.opt, config/i386/bsd.h, config/i386/cygming.opt,
config/i386/xm-mingw32.h, config/i386/linux64.h,
config/i386/openbsdelf.h, config/i386/xm-cygwin.h,
config/i386/sco5.opt, config/i386/darwin.h, config/i386/mingw32.h,
config/i386/winnt-cxx.c, config/i386/i386-interix3.h,
config/i386/nwld.c, config/i386/nwld.h, config/i386/host-cygwin.c,
config/i386/cygwin2.c, config/i386/i386-protos.h,
config/i386/sync.md, config/i386/openbsd.h,
config/i386/host-mingw32.c, config/i386/i386-aout.h,
config/i386/nto.h, config/i386/biarch64.h,
config/i386/i386-coff.h, config/i386/freebsd.h,
config/i386/driver-i386.c, config/i386/knetbsd-gnu.h,
config/i386/host-i386-darwin.c, config/i386/vxworks.h,
config/i386/crtdll.h, config/i386/i386.c, config/i386/sysv4.h,
config/darwin-protos.h, config/linux.opt, config/sol2.c,
config/sol2.h, config/sh/symbian.c, config/sh/sh-protos.h,
config/sh/linux.h, config/sh/elf.h, config/sh/superh.h,
config/sh/sh4.md, config/sh/coff.h, config/sh/newlib.h,
config/sh/embed-elf.h, config/sh/symbian-pre.h, config/sh/rtems.h,
config/sh/kaos-sh.h, config/sh/sh4a.md, config/sh/constraints.md,
config/sh/sh64.h, config/sh/sh.opt, config/sh/symbian-post.h,
config/sh/sh-c.c, config/sh/predicates.md, config/sh/sh.c,
config/sh/sh.h, config/sh/shmedia.md, config/sh/sh-modes.def,
config/sh/little.h, config/sh/sh1.md, config/sh/sh4-300.md,
config/sh/superh64.h, config/sh/rtemself.h,
config/sh/netbsd-elf.h, config/sh/sh.md, config/sh/vxworks.h,
config/usegas.h, config/svr3.h, config/pdp11/pdp11-protos.h,
config/pdp11/2bsd.h, config/pdp11/pdp11.md, config/pdp11/pdp11.c,
config/pdp11/pdp11.opt, config/pdp11/pdp11-modes.def,
config/pdp11/pdp11.h, config/avr/rtems.h, config/avr/avr-protos.h,
config/avr/predicates.md, config/avr/constraints.md,
config/avr/avr.md, config/avr/avr.c, config/avr/avr.opt,
config/avr/avr.h, config/sol2-protos.h, config/dbxelf.h,
config/lynx.opt, config/crx/crx.h, config/crx/crx-protos.h,
config/crx/crx.md, config/crx/crx.c, config/crx/crx.opt,
config/c4x/c4x-c.c, config/c4x/c4x.c, config/c4x/c4x.opt,
config/c4x/c4x-modes.def, config/c4x/rtems.h,
config/c4x/predicates.md, config/c4x/c4x.h,
config/c4x/c4x-protos.h, config/c4x/c4x.md, config/kfreebsd-gnu.h,
config/xtensa/predicates.md, config/xtensa/xtensa.c,
config/xtensa/linux.h, config/xtensa/xtensa.h,
config/xtensa/elf.h, config/xtensa/xtensa.md,
config/xtensa/xtensa.opt, config/xtensa/constraints.md,
config/xtensa/xtensa-protos.h, config/dbx.h,
config/stormy16/predicates.md, config/stormy16/stormy16.md,
config/stormy16/stormy16.c, config/stormy16/stormy16.opt,
config/stormy16/stormy16.h, config/stormy16/stormy16-protos.h,
config/host-solaris.c, config/fr30/fr30.h,
config/fr30/predicates.md, config/fr30/fr30-protos.h,
config/fr30/fr30.md, config/fr30/fr30.c, config/fr30/fr30.opt,
config/vxworksae.h, config/sol2-c.c, config/lynx.h,
config/m68hc11/m68hc11-protos.h, config/m68hc11/predicates.md,
config/m68hc11/m68hc11.md, config/m68hc11/m68hc11.c,
config/m68hc11/m68hc11.opt, config/m68hc11/m68hc11.h,
config/m68hc11/m68hc12.h, config/openbsd-oldgas.h,
config/host-linux.c, config/interix3.h, config/cris/cris.c,
config/cris/predicates.md, config/cris/linux.h,
config/cris/cris.h, config/cris/aout.h, config/cris/cris.md,
config/cris/linux.opt, config/cris/cris.opt, config/cris/elf.opt,
config/cris/aout.opt, config/cris/cris-protos.h,
config/vxworks-dummy.h, config/netbsd.h, config/netbsd-elf.h,
config/iq2000/iq2000.h, config/iq2000/predicates.md,
config/iq2000/iq2000-protos.h, config/iq2000/iq2000.md,
config/iq2000/iq2000.c, config/iq2000/iq2000.opt,
config/host-darwin.c, config/mt/mt.md, config/mt/mt.c,
config/mt/mt.opt, config/mt/t-mt, config/mt/mt.h,
config/mt/mt-protos.h, config/svr4.h, config/host-darwin.h,
config/chorus.h, config/mn10300/mn10300.c,
config/mn10300/mn10300.opt, config/mn10300/predicates.md,
config/mn10300/mn10300.h, config/mn10300/linux.h,
config/mn10300/constraints.md, config/mn10300/mn10300-protos.h,
config/mn10300/mn10300.md, config/ia64/predicates.md,
config/ia64/itanium1.md, config/ia64/unwind-ia64.h,
config/ia64/ia64-c.c, config/ia64/sync.md, config/ia64/ia64.c,
config/ia64/itanium2.md, config/ia64/ia64.h, config/ia64/vect.md,
config/ia64/freebsd.h, config/ia64/ia64.md,
config/ia64/ia64-modes.def, config/ia64/constraints.md,
config/ia64/hpux.h, config/ia64/ia64-protos.h, config/windiss.h,
config/gofast.h, config/rtems.h, config/sol2-10.h,
config/m68k/predicates.md, config/m68k/m68k.md,
config/m68k/linux.h, config/m68k/m68k-modes.def,
config/m68k/print-sysroot-suffix.sh, config/m68k/m68k-protos.h,
config/m68k/coff.h, config/m68k/m68k-none.h, config/m68k/ieee.opt,
config/m68k/openbsd.h, config/m68k/m68k-aout.h,
config/m68k/m68k.opt, config/m68k/m68020-elf.h,
config/m68k/m68kelf.h, config/m68k/m68k-devices.def,
config/m68k/uclinux-oldabi.h, config/m68k/m68k.c,
config/m68k/constraints.md, config/m68k/rtemself.h,
config/m68k/netbsd-elf.h, config/m68k/m68k.h,
config/m68k/uclinux.h, config/rs6000/power4.md,
config/rs6000/host-darwin.c, config/rs6000/6xx.md,
config/rs6000/linux.h, config/rs6000/eabi.h,
config/rs6000/aix41.opt, config/rs6000/xcoff.h,
config/rs6000/secureplt.h, config/rs6000/linuxspe.h,
config/rs6000/eabialtivec.h, config/rs6000/8540.md,
config/rs6000/darwin8.h, config/rs6000/kaos-ppc.h,
config/rs6000/windiss.h, config/rs6000/603.md,
config/rs6000/aix41.h, config/rs6000/cell.md,
config/rs6000/mpc.md, config/rs6000/aix43.h, config/rs6000/beos.h,
config/rs6000/gnu.h, config/rs6000/rtems.h, config/rs6000/aix.opt,
config/rs6000/darwin.md, config/rs6000/darwin64.h,
config/rs6000/default64.h, config/rs6000/7xx.md,
config/rs6000/darwin.opt, config/rs6000/spe.md,
config/rs6000/rs6000.opt, config/rs6000/rs6000-c.c,
config/rs6000/rios2.md, config/rs6000/linuxaltivec.h,
config/rs6000/7450.md, config/rs6000/linux64.h,
config/rs6000/constraints.md, config/rs6000/440.md,
config/rs6000/darwin.h, config/rs6000/host-ppc64-darwin.c,
config/rs6000/rs6000.c, config/rs6000/aix52.h,
config/rs6000/rs6000.h, config/rs6000/power6.md,
config/rs6000/predicates.md, config/rs6000/altivec.md,
config/rs6000/aix64.opt, config/rs6000/rios1.md,
config/rs6000/rs6000-modes.def, config/rs6000/rs64.md,
config/rs6000/eabisim.h, config/rs6000/sysv4le.h,
config/rs6000/darwin7.h, config/rs6000/dfp.md,
config/rs6000/linux64.opt, config/rs6000/sync.md,
config/rs6000/vxworksae.h, config/rs6000/power5.md,
config/rs6000/lynx.h, config/rs6000/biarch64.h,
config/rs6000/rs6000.md, config/rs6000/sysv4.opt,
config/rs6000/eabispe.h, config/rs6000/e500.h,
config/rs6000/freebsd.h, config/rs6000/rs6000-protos.h,
config/rs6000/netbsd.h, config/rs6000/e500-double.h,
config/rs6000/aix.h, config/rs6000/vxworks.h,
config/rs6000/40x.md, config/rs6000/aix51.h,
config/rs6000/sysv4.h, config/arc/arc-protos.h, config/arc/arc.md,
config/arc/arc.c, config/arc/arc.opt, config/arc/arc-modes.def,
config/arc/arc.h, config/mcore/mcore-elf.h,
config/mcore/mcore-protos.h, config/mcore/predicates.md,
config/mcore/mcore.md, config/mcore/mcore.c,
config/mcore/mcore.opt, config/mcore/mcore.h,
config/mcore/mcore-pe.h, config/darwin.c, config/freebsd-nthr.h,
config/score/predicates.md, config/score/score-version.h,
config/score/score-protos.h, config/score/misc.md,
config/score/elf.h, config/score/score.c, config/score/mac.md,
config/score/score7.md, config/score/score.h,
config/score/score-conv.h, config/score/score-mdaux.c,
config/score/score.md, config/score/score.opt,
config/score/score-modes.def, config/score/score-mdaux.h,
config/score/mul-div.S, config/arm/uclinux-elf.h,
config/arm/semi.h, config/arm/ecos-elf.h, config/arm/arm1020e.md,
config/arm/symbian.h, config/arm/linux-elf.h,
config/arm/arm1026ejs.md, config/arm/arm1136jfs.md,
config/arm/elf.h, config/arm/aout.h, config/arm/arm.c,
config/arm/thumb2.md, config/arm/vec-common.md, config/arm/coff.h,
config/arm/strongarm-pe.h, config/arm/arm.h,
config/arm/cortex-a8-neon.md, config/arm/semiaof.h,
config/arm/cortex-a8.md, config/arm/uclinux-eabi.h,
config/arm/arm-modes.def, config/arm/linux-eabi.h,
config/arm/rtems-elf.h, config/arm/neon-schedgen.ml,
config/arm/arm-cores.def, config/arm/arm-protos.h,
config/arm/vfp.md, config/arm/aof.h, config/arm/linux-gas.h,
config/arm/wince-pe.h, config/arm/neon.md,
config/arm/constraints.md, config/arm/neon.ml,
config/arm/xscale-elf.h, config/arm/strongarm-coff.h,
config/arm/arm.opt, config/arm/arm926ejs.md,
config/arm/predicates.md, config/arm/iwmmxt.md,
config/arm/arm_neon.h, config/arm/unknown-elf.h,
config/arm/kaos-arm.h, config/arm/bpabi.h, config/arm/pe.opt,
config/arm/neon-testgen.ml, config/arm/arm.md,
config/arm/xscale-coff.h, config/arm/pe.c,
config/arm/arm-generic.md, config/arm/pe.h,
config/arm/kaos-strongarm.h, config/arm/freebsd.h,
config/arm/neon-docgen.ml, config/arm/netbsd.h, config/arm/fpa.md,
config/arm/strongarm-elf.h, config/arm/cirrus.md,
config/arm/netbsd-elf.h, config/arm/vxworks.h,
config/arm/neon-gen.ml, config/kaos.h, config/darwin-driver.c,
config/pa/predicates.md, config/pa/pa64-hpux.h,
config/pa/pa-hpux.opt, config/pa/som.h, config/pa/pa-hpux1010.opt,
config/pa/pa-hpux1111.opt, config/pa/pa-pro-end.h,
config/pa/elf.h, config/pa/fptr.c, config/pa/pa64-linux.h,
config/pa/pa.md, config/pa/pa.opt, config/pa/pa-hpux.h,
config/pa/pa-hpux10.h, config/pa/pa-hpux11.h,
config/pa/pa-hpux1010.h, config/pa/pa-protos.h,
config/pa/pa-osf.h, config/pa/pa-hpux1111.h, config/pa/pa-64.h,
config/pa/milli64.S, config/pa/pa.c, config/pa/pa-linux.h,
config/pa/pa.h, config/pa/pa32-linux.h, config/pa/pa64-hpux.opt,
config/pa/pa64-regs.h, config/pa/pa-modes.def,
config/pa/constraints.md, config/darwin9.h, config/mips/4100.md,
config/mips/linux.h, config/mips/elfoabi.h, config/mips/elf.h,
config/mips/sdb.h, config/mips/windiss.h, config/mips/rtems.h,
config/mips/3000.md, config/mips/iris5.h, config/mips/5000.md,
config/mips/7000.md, config/mips/9000.md, config/mips/4600.md,
config/mips/linux64.h, config/mips/elforion.h,
config/mips/constraints.md, config/mips/generic.md,
config/mips/predicates.md, config/mips/4300.md,
config/mips/mips-ps-3d.md, config/mips/iris.h, config/mips/24k.md,
config/mips/mips.md, config/mips/mips.opt, config/mips/4k.md,
config/mips/5k.md, config/mips/vr4120-div.S,
config/mips/openbsd.h, config/mips/iris6.h, config/mips/4000.md,
config/mips/mips-protos.h, config/mips/6000.md,
config/mips/mips.c, config/mips/mips.h, config/mips/r3900.h,
config/mips/74k.md, config/mips/netbsd.h, config/mips/vxworks.h,
config/mips/mips-modes.def, config/mips/vr.h,
config/soft-fp/t-softfp, config/openbsd.h, config/ptx4.h,
config/freebsd-spec.h, config/vax/vax.c, config/vax/openbsd.h,
config/vax/vax.h, config/vax/elf.h, config/vax/vax.md,
config/vax/bsd.h, config/vax/vax.opt, config/vax/vax-modes.def,
config/vax/openbsd1.h, config/vax/netbsd.h,
config/vax/vax-protos.h, config/vax/netbsd-elf.h,
config/vax/vaxv.h, config/vax/ultrix.h, config/freebsd.h,
config/h8300/rtems.h, config/h8300/predicates.md,
config/h8300/h8300.c, config/h8300/h8300.h, config/h8300/elf.h,
config/h8300/h8300.md, config/h8300/h8300.opt,
config/h8300/coff.h, config/h8300/h8300-protos.h,
config/v850/v850.md, config/v850/predicates.md,
config/v850/v850-c.c, config/v850/v850.c, config/v850/v850.opt,
config/v850/v850.h, config/v850/v850-protos.h, config/vxworks.c,
config/knetbsd-gnu.h, config/sol2-6.h, config/vxworks.h,
config/mmix/mmix.h, config/mmix/predicates.md,
config/mmix/mmix-protos.h, config/mmix/mmix.md,
config/mmix/mmix.c, config/mmix/mmix.opt,
config/mmix/mmix-modes.def, config/bfin/bfin.opt,
config/bfin/rtems.h, config/bfin/bfin-modes.def,
config/bfin/predicates.md, config/bfin/bfin-protos.h,
config/bfin/bfin.c, config/bfin/bfin.h, config/bfin/bfin.md: Likewise.
From-SVN: r127157
2007-08-02 12:49:31 +02:00
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;; along with GCC; see the file COPYING3. If not see
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;; <http://www.gnu.org/licenses/>.
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2005-04-05 13:26:48 +02:00
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; operand punctuation marks:
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;
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; X -- integer value printed as log2
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; Y -- integer value printed as log2(~value) - for bitclear
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; h -- print half word register, low part
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; d -- print half word register, high part
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; D -- print operand as dregs pairs
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; w -- print operand as accumulator register word (a0w, a1w)
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; H -- high part of double mode operand
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; T -- byte register representation Oct. 02 2001
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; constant operand classes
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;
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; J 2**N 5bit imm scaled
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; Ks7 -64 .. 63 signed 7bit imm
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; Ku5 0..31 unsigned 5bit imm
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; Ks4 -8 .. 7 signed 4bit imm
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; Ks3 -4 .. 3 signed 3bit imm
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; Ku3 0 .. 7 unsigned 3bit imm
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; Pn 0, 1, 2 constants 0, 1 or 2, corresponding to n
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;
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; register operands
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; d (r0..r7)
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; a (p0..p5,fp,sp)
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; e (a0, a1)
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; b (i0..i3)
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; f (m0..m3)
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2006-06-18 12:30:23 +02:00
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; v (b0..b3)
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; c (i0..i3,m0..m3) CIRCREGS
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; C (CC) CCREGS
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bfin-protos.h (bfin_hardware_loop): Declare.
* config/bfin/bfin-protos.h (bfin_hardware_loop): Declare.
* config/bfin/bfin.c (basic-block.h): Include.
(struct machine_function): New.
(bfin_init_machine_status): New.
(override_options): Initialize init_machine_status.
(bfin_hardware_loop): New.
(MAX_LOOP_DEPTH, MAX_LOOP_LENGTH): Define.
(DEF_VEC_P (loop_info)): New.
(DEF_VEC_ALLOC_P (loop_info,heap)): New.
(struct loop_info): New.
(loop_info): New typedef.
(struct loop_work): New.
(loop_work): New typedef.
(DEF_VEC_O (loop_work)): New.
(DEF_VEC_ALLOC_O (loop_work,heap)): New.
(bfin_dump_loops): New.
(bfin_bb_in_loop): New.
(bfin_scan_loop): New.
(bfin_optimize_loop): New.
(bfin_reorg_loops): New.
(bfin_reorg): Use bfin_reorg_loops.
* config/bfin/bfin.h (FIRST_PSEUDO_REGISTER): Adjust for adding
loop registers.
(I_REGNO_P): Simplify.
(DP_REGNO_P, DPREG_P): New macros.
(REGISTER_NAMES, FIXED_REGISTERS, CALL_USED_REGISTERS,
REG_ALLOC_ORDER): Add LT0, LT1, LC0, LC1, LB0, LB1.
(enum reg_class, REG_CLASS_NAMES, REG_CLASS_CONTENTS):
Add LT_REGS, LC_REGS, LB_REGS.
(REG_CLASS_FROM_LETTER): Add 't' for LT_REGS, 'k' for LC_REGS,
'l' for LB_REGS.
(REGNO_REG_CLASS): Deal with loop registers.
* config/bfin/bfin.md: Add comment for 't', 'k', 'l' constraint
letters.
(REG_LT0, REG_LT1, REG_LC0, REG_LC1, REG_LB0, REG_LB1):
New constants for loop registers.
(UNSPEC_LSETUP_END): New.
(seq_insns): New define_attr. Set it for appropriate insns.
(movsi_insn): Add alternatives for move from/to
loop count registers.
(doloop_end): New define_expand.
(loop_end): New define_insn.
(define_split for bad doloop_end): New.
(lsetup_with_autoinit): New define_insn.
(lsetup_without_autoinit): New define_insn.
(rep_movsi, rep_movhi): Clobber LT1, LC1, LB1.
* config/bfin/predicates.md (lc_register_operand): New.
(lt_register_operand): New.
(lb_register_operand): New.
(nondp_register_operand): New.
(nondp_reg_or_memory_operand): New.
* doc/md.texi: Document Blackfin new 't', 'k', 'l' constraint letters.
From-SVN: r114274
2006-05-31 18:46:15 +02:00
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; t (lt0,lt1)
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; k (lc0,lc1)
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2006-06-18 12:30:23 +02:00
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; u (lb0,lb1)
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2005-04-05 13:26:48 +02:00
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;
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;; Define constants for hard registers.
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(define_constants
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[(REG_R0 0)
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(REG_R1 1)
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(REG_R2 2)
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(REG_R3 3)
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(REG_R4 4)
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(REG_R5 5)
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(REG_R6 6)
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(REG_R7 7)
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(REG_P0 8)
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(REG_P1 9)
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(REG_P2 10)
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(REG_P3 11)
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(REG_P4 12)
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(REG_P5 13)
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(REG_P6 14)
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(REG_P7 15)
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(REG_SP 14)
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(REG_FP 15)
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(REG_I0 16)
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2005-11-12 17:08:35 +01:00
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(REG_I1 17)
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(REG_I2 18)
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(REG_I3 19)
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(REG_B0 20)
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(REG_B1 21)
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(REG_B2 22)
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(REG_B3 23)
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(REG_L0 24)
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(REG_L1 25)
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(REG_L2 26)
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2005-04-05 13:26:48 +02:00
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(REG_L3 27)
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(REG_M0 28)
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(REG_M1 29)
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(REG_M2 30)
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(REG_M3 31)
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(REG_A0 32)
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(REG_A1 33)
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(REG_CC 34)
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(REG_RETS 35)
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(REG_RETI 36)
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(REG_RETX 37)
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(REG_RETN 38)
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(REG_RETE 39)
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(REG_ASTAT 40)
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(REG_SEQSTAT 41)
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(REG_USP 42)
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bfin-protos.h (bfin_hardware_loop): Declare.
* config/bfin/bfin-protos.h (bfin_hardware_loop): Declare.
* config/bfin/bfin.c (basic-block.h): Include.
(struct machine_function): New.
(bfin_init_machine_status): New.
(override_options): Initialize init_machine_status.
(bfin_hardware_loop): New.
(MAX_LOOP_DEPTH, MAX_LOOP_LENGTH): Define.
(DEF_VEC_P (loop_info)): New.
(DEF_VEC_ALLOC_P (loop_info,heap)): New.
(struct loop_info): New.
(loop_info): New typedef.
(struct loop_work): New.
(loop_work): New typedef.
(DEF_VEC_O (loop_work)): New.
(DEF_VEC_ALLOC_O (loop_work,heap)): New.
(bfin_dump_loops): New.
(bfin_bb_in_loop): New.
(bfin_scan_loop): New.
(bfin_optimize_loop): New.
(bfin_reorg_loops): New.
(bfin_reorg): Use bfin_reorg_loops.
* config/bfin/bfin.h (FIRST_PSEUDO_REGISTER): Adjust for adding
loop registers.
(I_REGNO_P): Simplify.
(DP_REGNO_P, DPREG_P): New macros.
(REGISTER_NAMES, FIXED_REGISTERS, CALL_USED_REGISTERS,
REG_ALLOC_ORDER): Add LT0, LT1, LC0, LC1, LB0, LB1.
(enum reg_class, REG_CLASS_NAMES, REG_CLASS_CONTENTS):
Add LT_REGS, LC_REGS, LB_REGS.
(REG_CLASS_FROM_LETTER): Add 't' for LT_REGS, 'k' for LC_REGS,
'l' for LB_REGS.
(REGNO_REG_CLASS): Deal with loop registers.
* config/bfin/bfin.md: Add comment for 't', 'k', 'l' constraint
letters.
(REG_LT0, REG_LT1, REG_LC0, REG_LC1, REG_LB0, REG_LB1):
New constants for loop registers.
(UNSPEC_LSETUP_END): New.
(seq_insns): New define_attr. Set it for appropriate insns.
(movsi_insn): Add alternatives for move from/to
loop count registers.
(doloop_end): New define_expand.
(loop_end): New define_insn.
(define_split for bad doloop_end): New.
(lsetup_with_autoinit): New define_insn.
(lsetup_without_autoinit): New define_insn.
(rep_movsi, rep_movhi): Clobber LT1, LC1, LB1.
* config/bfin/predicates.md (lc_register_operand): New.
(lt_register_operand): New.
(lb_register_operand): New.
(nondp_register_operand): New.
(nondp_reg_or_memory_operand): New.
* doc/md.texi: Document Blackfin new 't', 'k', 'l' constraint letters.
From-SVN: r114274
2006-05-31 18:46:15 +02:00
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(REG_ARGP 43)
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(REG_LT0 44)
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(REG_LT1 45)
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(REG_LC0 46)
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(REG_LC1 47)
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(REG_LB0 48)
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(REG_LB1 49)])
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2005-04-05 13:26:48 +02:00
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;; Constants used in UNSPECs and UNSPEC_VOLATILEs.
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(define_constants
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[(UNSPEC_CBRANCH_TAKEN 0)
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(UNSPEC_CBRANCH_NOPS 1)
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(UNSPEC_RETURN 2)
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(UNSPEC_MOVE_PIC 3)
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(UNSPEC_LIBRARY_OFFSET 4)
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genmodes.c (make_vector_mode): Allow making VECTOR_MODE_INT of a MODE_PARTIAL_INT mode.
* genmodes.c (make_vector_mode): Allow making VECTOR_MODE_INT of a
MODE_PARTIAL_INT mode.
* config/bfin/bfin-modes.def: Add V2PDI and V2SI.
* config/bfin/bfin.c (print_operand): Add macflag and mac/msu modifiers
for CONST_INTs.
(hard_regno_mode_ok): V2PDImode is ok for accumulators.
* config/bfin/bfin.h (CLASS_MAX_NREGS, HARD_REGNO_NREGS): Handle
V2PDImode.
* config/bfin/predicates.md (const01_operand, vec_shift_operand):
New predicates.
* config/bfin/bfin.md (UNSPEC_MUL_WITH_FLAG, UNSPEC_MAC_WITH_FLAG):
New constants.
(MACFLAG_NONE, MACFLAG_T, MACFLAG_FU, MACFLAG_TFU, MACFLAG_IS,
MACFLAG_IU, MACFLAG_W32, MACFLAG_M, MACFLAG_S2RND, MACFLAG_ISS2,
MACFLAG_IH): Likewise.
(movstricthi_1): Renamed from "*movstricthi".
(load_accumulator, load_accumulator_pair, movsi_insv, insv,
ssaddsi3, sssubsi3, ssnegsi2, signbitssi2, smaxhi3, sminhi3,
abshi2, neghi2, ssneghi2, signbitshi2, movhi_low2high,
movhi_high2high, movhi_low2low, movhi_high2low, movhiv2hi_low,
movhiv2hi_high, composev2hi, movv2hi_hi, movv2hi_hi_low,
movv2hi_hi_high, ssaddhi3, sssubhi3, ssaddv2hi3, sssubv2hi3,
addsubv2hi3, subaddv2hi3, ssaddsubv2hi3, sssubaddv2hi3,
sublohiv2hi3, subhilov2hi3, sssublohiv2hi3, sssubhilov2hi3,
addlohiv2hi3, addhilov2hi3, ssaddlohiv2hi3, ssaddhilov2hi3,
mulhisi_ll, mulhisi_lh, mulhisi_hl, mulhisi_hh, ssnegv2hi2,
ssashiftv2hi3, ssashifthi3, lshiftv2hi3, lshifthi3, packv2hi,
flag_mulhi, flag_mulhisi_parts, flag_machi, flag_machi_acconly,
flag_macinithi, flag_macinit1hi, flag_mulv2hi, flag_mulv2hi_parts,
flag_macv2hi_parts, flag_macv2hi_parts_acconly,
flag_macinitv2hi_parts, flag_macinit1v2hi_parts): New patterns.
From-SVN: r113245
2006-04-25 13:49:27 +02:00
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(UNSPEC_PUSH_MULTIPLE 5)
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;; Multiply or MAC with extra CONST_INT operand specifying the macflag
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(UNSPEC_MUL_WITH_FLAG 6)
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bfin.opt (mfdpic): New option.
* config/bfin/bfin.opt (mfdpic): New option.
* config/bfin/t-bfin-elf (EXTRA_PARTS): Add crtbeginS.o and crtendS.o.
(EXTRA_MULTILIB_PARTS): Likewise.
(CRTSTUFF_T_CFLAGS, TARGET_LIBGCC2_CFLAGS): Use -fpic.
(MULTILIB_OPTIONS, MULTILIB_EXCEPTIONS): Build one extra -mfdpic
multilib.
* config/bfin/elf.h (STARTFILE_SPEC): Don't link in crt0.o if -shared.
(CRT_CALL_STATIC_FUNCTION): New.
* config/bfin/uclinux.h (STARTFILE_SPEC): Don't link in crt0.o if
-shared.
(CRT_CALL_STATIC_FUNCTION): New.
* config/bfin/bfin.c (legitimize_pic_address): Now static. Handle
FD-PIC moves.
(n_pregs_to_save): PIC register doesn't need to be saved with FD-PIC.
(print_operand): Handle UNSPEC_MOVE_FDPIC and UNSPEC_FUNCDESC_GOT17M4.
(initialize_trampoline): Changed to handle FD-PIC code generation.
(expand_move): If TARGET_FDPIC, use emit_pic_move as needed.
(bfin_expand_call): Generate FD-PIC calls if TARGET_FDPIC.
(override_options): Disallow -mid-shared-library -mfdpic combination.
Can't do unaligned ops if FD-PIC.
Turn off flag_pic if trying to generate non-id-shared-library
non-fdpic code, since it's not supported.
(bfin_assemble_integer): New function.
(TARGET_ASM_INTEGER): Define.
* config/bfin/crti.s (__init, __fini): Save P3 on the stack if
__BFIN_FDPIC__.
* config/bfin/crtn.s: Restore them.
* config/bfin/bfin.h (TARGET_CPU_CPP_BUILTINS): Define __BFIN_FDPIC__
if TARGET_FDPIC.
(DRIVER_SELF_SPECS, SUBTARGET_DRIVER_SELF_SPECS,
LINK_GCC_C_SEQUENCE_SPEC, ASM_SPEC, LINK_SPEC): New macros.
(FDPIC_FPTR_REGNO, FDPIC_REGNO, OUR_FDPIC_REG): New macros.
(TRAMPOLINE_SIZE, TRAMPOLINE_TEMPLATE): Adjust for FD-PIC.
(CONDITIONAL_REGISTER_USAGE): If TARGET_FDPIC, FDPIC_REGNO is
call-used.
(enum reg_class, REG_CLASS_CONTENTS, REG_CLASS_NAMES): Add
FDPIC_REGS and FDPIC_FPTR_REGS.
(REG_CLASS_FROM_LETTER): Use 'Z' and 'Y' for them.
* config/bfin/bfin.md (UNSPEC_MOVE_FDPIC, UNSPEC_FUNCDESC_GOT17M4,
UNSPEC_VOLATILE_LOAD_FUNCDESC): New constants.
(load_funcdescsi): New pattern.
(call_symbol_fdpic, sibcall_symbol_fdpic, call_value_symbol_fdpic,
sibcall_value_symbol_fdpic, call_insn_fdpic, sibcall_insn_fdpic,
call_value_insn_fdpic, sibcall_value_insn_fdpic): New patterns.
From-SVN: r114199
2006-05-29 16:11:07 +02:00
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(UNSPEC_MAC_WITH_FLAG 7)
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(UNSPEC_MOVE_FDPIC 8)
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bfin-protos.h (bfin_hardware_loop): Declare.
* config/bfin/bfin-protos.h (bfin_hardware_loop): Declare.
* config/bfin/bfin.c (basic-block.h): Include.
(struct machine_function): New.
(bfin_init_machine_status): New.
(override_options): Initialize init_machine_status.
(bfin_hardware_loop): New.
(MAX_LOOP_DEPTH, MAX_LOOP_LENGTH): Define.
(DEF_VEC_P (loop_info)): New.
(DEF_VEC_ALLOC_P (loop_info,heap)): New.
(struct loop_info): New.
(loop_info): New typedef.
(struct loop_work): New.
(loop_work): New typedef.
(DEF_VEC_O (loop_work)): New.
(DEF_VEC_ALLOC_O (loop_work,heap)): New.
(bfin_dump_loops): New.
(bfin_bb_in_loop): New.
(bfin_scan_loop): New.
(bfin_optimize_loop): New.
(bfin_reorg_loops): New.
(bfin_reorg): Use bfin_reorg_loops.
* config/bfin/bfin.h (FIRST_PSEUDO_REGISTER): Adjust for adding
loop registers.
(I_REGNO_P): Simplify.
(DP_REGNO_P, DPREG_P): New macros.
(REGISTER_NAMES, FIXED_REGISTERS, CALL_USED_REGISTERS,
REG_ALLOC_ORDER): Add LT0, LT1, LC0, LC1, LB0, LB1.
(enum reg_class, REG_CLASS_NAMES, REG_CLASS_CONTENTS):
Add LT_REGS, LC_REGS, LB_REGS.
(REG_CLASS_FROM_LETTER): Add 't' for LT_REGS, 'k' for LC_REGS,
'l' for LB_REGS.
(REGNO_REG_CLASS): Deal with loop registers.
* config/bfin/bfin.md: Add comment for 't', 'k', 'l' constraint
letters.
(REG_LT0, REG_LT1, REG_LC0, REG_LC1, REG_LB0, REG_LB1):
New constants for loop registers.
(UNSPEC_LSETUP_END): New.
(seq_insns): New define_attr. Set it for appropriate insns.
(movsi_insn): Add alternatives for move from/to
loop count registers.
(doloop_end): New define_expand.
(loop_end): New define_insn.
(define_split for bad doloop_end): New.
(lsetup_with_autoinit): New define_insn.
(lsetup_without_autoinit): New define_insn.
(rep_movsi, rep_movhi): Clobber LT1, LC1, LB1.
* config/bfin/predicates.md (lc_register_operand): New.
(lt_register_operand): New.
(lb_register_operand): New.
(nondp_register_operand): New.
(nondp_reg_or_memory_operand): New.
* doc/md.texi: Document Blackfin new 't', 'k', 'l' constraint letters.
From-SVN: r114274
2006-05-31 18:46:15 +02:00
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(UNSPEC_FUNCDESC_GOT17M4 9)
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rtlanal.c (note_uses): Deal with SEQUENCEs.
* rtlanal.c (note_uses): Deal with SEQUENCEs.
* config/bfin/bfin.c: Include "timevar.h".
(bfin_flag_schedule_insns2, splitting_for_sched,
bfin_flag_var_tracking): New variables.
(print_operand): Handle '%!'.
(override_options): Disable normal sched2 pass, instead set
bfin_flag_schedule_insns2 for reorg to handle it.
(output_file_start): Likewise for var-tracking.
(bfin_optimize_loop): Take some care not to stumble over SEQUENCEs.
(gen_one_bundle, bfin_gen_bundles, type_for_anomaly, trapping_loads_p):
New functions.
(bfin_reorg): Do second scheduling pass here, and call
bfin_gen_bundles. Use type_for_anomaly and trapping_loads_p instead
of examining insns directly. If bfin_flag_var_tracking, call
var-tracking pass when done with everything else.
* config/bfin/bfin.h (PRINT_OPERAND_PUNCT_VALID_P): '!' is valid.
* config/bfin/bfin.md (UNSPEC_32BIT): New constant.
(movsi_insn32): New pattern, with two new splits to create it
before the final scheduling pass.
(neghi2): Not a dsp32 insn, rather alu0.
(movbi, pushsi_insn, popsi_insn, movsi_insn, movv2hi_insn, movhi_insn,
movqi_insn, movsf_insn, movsi_insv, extendhisi2, zero_extendhisi2,
extendqihi2, extendqisi2, zero_extendqihi2, zero_extendqisi2,
mulhisi3, umulhisi3, ssadsi3, sssubsi3, smaxsi3, sminsi3, abssi2,
ssnegsi2, signbitssi2, smaxhi3, sminhi3, abshi2, ssneghi2, signbitshi2,
movhi_low2high, movhi_high2high, movhi_low2low, movhi_high2low,
movhiv2hi_low, movhiv2hi_high, composev2hi, packv2hi, movv2hi_hi,
ssaddhi3, sssubhi3, addv2hi3, ssaddv2hi3, subv2hi3, sssubv2hi3,
addsubv2hi3, subaddv2hi3, ssaddsubv2hi3, sssubaddv2hi3, sublohiv2hi3,
subhilov2hi3, sssublohiv2hi3, sssubhilov2hi3, addlohiv2hi3,
addhilov2hi3, ssaddlohiv2hi3, ssaddhilov2hi3, sminv2hi3, smaxv2hi3,
flag_mulhi, flag_mulhisi, flag_mulhisi_parts, flag_machi,
flag_machi_acconly, flag_macinithi, flag_macinit1hi, mulv2hi3,
flag_mulv2hi, flag_mulv2hi_parts, flag_macv2hi_parts,
flag_macv2hi_parts_acconly, flag_macinitv2hi_parts,
flag_macinit1v2hi_parts, mulhisi_ll, mulhisi_lh, mulhisi_hl,
mulhisi_hh, ssnegv2hi2, absv2hi2, ssashiftv2hi3, ssashifthi3,
lshiftv2hi3, lshifthi3): Use '%!' to terminate all dsp32/load/store
variants instead of ';'.
(ror_one, rol_one): Likewise. Make them dsp32 insns.
(ashlsi3_insn, ashrsi3, lshrsi3): Add dsp32 variants.
(align8, align16, align24): Now named patterns; also using '%!'.
(mnop): New insn.
From-SVN: r119534
2006-12-05 09:49:56 +01:00
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|
|
(UNSPEC_LSETUP_END 10)
|
2007-02-04 17:40:30 +01:00
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|
;; Distinguish a 32-bit version of an insn from a 16-bit version.
|
2007-06-12 16:35:13 +02:00
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|
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|
(UNSPEC_32BIT 11)
|
From Jie Zhang:
* config/bfin/bfin.c (enum bfin_builtins): Add BFIN_BUILTIN_ONES,
BFIN_BUILTIN_CPLX_MUL_16_S40, BFIN_BUILTIN_CPLX_MAC_16_S40,
BFIN_BUILTIN_CPLX_MSU_16_S40, and BFIN_BUILTIN_CPLX_SQU.
(bfin_init_builtins): Initialize __builtin_bfin_ones,
__builtin_bfin_min_fr1x16, __builtin_bfin_max_fr1x16,
__builtin_bfin_min_fr1x32, __builtin_bfin_max_fr1x32,
__builtin_bfin_cmplx_add, __builtin_bfin_cmplx_sub,
__builtin_bfin_cmplx_mul_s40, __builtin_bfin_cmplx_mac_s40,
__builtin_bfin_cmplx_msu_s40 and __builtin_bfin_csqu_fr16.
(bdesc_1arg): Add __builtin_bfin_ones.
(bfin_expand_builtin): Expand __builtin_bfin_cmplx_mul_s40,
__builtin_bfin_cmplx_mac_s40, __builtin_bfin_cmplx_msu_s40,
and __builtin_bfin_csqu_fr16.
* config/bfin/bfin.md (UNSPEC_ONES): New constant.
(ones): New define_insn.
(ssaddhi3_parts): New define_insn.
(sssubhi3_parts): New define_insn.
(flag_mulhi_parts): New define_insn.
From-SVN: r128475
2007-09-13 20:27:28 +02:00
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(UNSPEC_NOP 12)
|
2021-10-18 12:56:56 +02:00
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(UNSPEC_ATOMIC 13)])
|
2005-04-05 13:26:48 +02:00
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(define_constants
|
cfgcleanup.c (try_crossjump_to_edge): Only skip past NOTE_INSN_BASIC_BLOCK.
* cfgcleanup.c (try_crossjump_to_edge): Only skip past
NOTE_INSN_BASIC_BLOCK.
* cfglayout.c (duplicate_insn_chain): Copy epilogue insn marks.
Duplicate NOTE_INSN_EPILOGUE_BEG notes.
* cfgrtl.c (can_delete_note_p): Allow NOTE_INSN_EPILOGUE_BEG
to be deleted.
* dwarf2out.c (struct cfa_loc): Change indirect field to bitfield,
add in_use field.
(add_cfi): Disable check redefining cfa away from drap.
(lookup_cfa_1): Add remember argument; handle remember/restore.
(lookup_cfa): Pass remember argument.
(cfa_remember): New.
(compute_barrier_args_size_1): Remove sibcall check.
(dwarf2out_frame_debug_def_cfa): New.
(dwarf2out_frame_debug_adjust_cfa): New.
(dwarf2out_frame_debug_cfa_offset): New.
(dwarf2out_frame_debug_cfa_register): New.
(dwarf2out_frame_debug_cfa_restore): New.
(dwarf2out_frame_debug): Handle REG_CFA_* notes.
(dwarf2out_begin_epilogue): New.
(dwarf2out_frame_debug_restore_state): New.
(dw_cfi_oprnd1_desc): Handle DW_CFA_remember_state,
DW_CFA_restore_state.
(output_cfi_directive): Likewise.
(convert_cfa_to_fb_loc_list): Likewise.
(dw_cfi_oprnd1_desc): Handle DW_CFA_restore.
* dwarf2out.h: Update.
* emit-rtl.c (try_split): Don't split RTX_FRAME_RELATED_P.
(copy_insn_1): Early out for null.
* final.c (final_scan_insn): Call dwarf2out_begin_epilogue
and dwarf2out_frame_debug_restore_state.
* function.c (prologue, epilogue, sibcall_epilogue): Remove.
(prologue_insn_hash, epilogue_insn_hash): New.
(free_after_compilation): Adjust freeing accordingly.
(record_insns): Create hash table if needed; push insns into
hash instead of array.
(maybe_copy_epilogue_insn): New.
(contains): Search hash table instead of array.
(sibcall_epilogue_contains): Remove.
(thread_prologue_and_epilogue_insns): Split eh_return insns
and mark them as epilogues.
(reposition_prologue_and_epilogue_notes): Rewrite epilogue
scanning in terms of basic blocks.
* insn-notes.def (CFA_RESTORE_STATE): New.
* jump.c (returnjump_p_1): Accept EH_RETURN.
(eh_returnjump_p_1, eh_returnjump_p): New.
* reg-notes.def (CFA_DEF_CFA, CFA_ADJUST_CFA, CFA_OFFSET,
CFA_REGISTER, CFA_RESTORE): New.
* rtl.def (EH_RETURN): New.
* rtl.h (eh_returnjump_p, maybe_copy_epilogue_insn): Declare.
* config/bfin/bfin.md (UNSPEC_VOLATILE_EH_RETURN): Remove.
(eh_return_internal): Use eh_return rtx; split w/ epilogue.
* config/i386/i386.c (gen_push): Update cfa state.
(pro_epilogue_adjust_stack): Add set_cfa argument. When true,
add a CFA_ADJUST_CFA note.
(ix86_dwarf_handle_frame_unspec): Remove.
(ix86_expand_prologue): Update cfa state.
(ix86_emit_restore_reg_using_pop): New.
(ix86_emit_restore_regs_using_pop): New.
(ix86_emit_leave): New.
(ix86_emit_restore_regs_using_mov): Add CFA_RESTORE notes.
(ix86_expand_epilogue): Add notes for unwinding the epilogue.
* config/i386/i386.h (struct machine_cfa_state): New.
(ix86_cfa_state): New.
* config/i386/i386.md (UNSPEC_EH_RETURN): Remove.
(eh_return_internal): Merge from eh_return_<mode>,
use eh_return rtx, split w/ epilogue.
From-SVN: r147995
2009-05-30 02:33:46 +02:00
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[(UNSPEC_VOLATILE_CSYNC 1)
|
bfin.opt (mfdpic): New option.
* config/bfin/bfin.opt (mfdpic): New option.
* config/bfin/t-bfin-elf (EXTRA_PARTS): Add crtbeginS.o and crtendS.o.
(EXTRA_MULTILIB_PARTS): Likewise.
(CRTSTUFF_T_CFLAGS, TARGET_LIBGCC2_CFLAGS): Use -fpic.
(MULTILIB_OPTIONS, MULTILIB_EXCEPTIONS): Build one extra -mfdpic
multilib.
* config/bfin/elf.h (STARTFILE_SPEC): Don't link in crt0.o if -shared.
(CRT_CALL_STATIC_FUNCTION): New.
* config/bfin/uclinux.h (STARTFILE_SPEC): Don't link in crt0.o if
-shared.
(CRT_CALL_STATIC_FUNCTION): New.
* config/bfin/bfin.c (legitimize_pic_address): Now static. Handle
FD-PIC moves.
(n_pregs_to_save): PIC register doesn't need to be saved with FD-PIC.
(print_operand): Handle UNSPEC_MOVE_FDPIC and UNSPEC_FUNCDESC_GOT17M4.
(initialize_trampoline): Changed to handle FD-PIC code generation.
(expand_move): If TARGET_FDPIC, use emit_pic_move as needed.
(bfin_expand_call): Generate FD-PIC calls if TARGET_FDPIC.
(override_options): Disallow -mid-shared-library -mfdpic combination.
Can't do unaligned ops if FD-PIC.
Turn off flag_pic if trying to generate non-id-shared-library
non-fdpic code, since it's not supported.
(bfin_assemble_integer): New function.
(TARGET_ASM_INTEGER): Define.
* config/bfin/crti.s (__init, __fini): Save P3 on the stack if
__BFIN_FDPIC__.
* config/bfin/crtn.s: Restore them.
* config/bfin/bfin.h (TARGET_CPU_CPP_BUILTINS): Define __BFIN_FDPIC__
if TARGET_FDPIC.
(DRIVER_SELF_SPECS, SUBTARGET_DRIVER_SELF_SPECS,
LINK_GCC_C_SEQUENCE_SPEC, ASM_SPEC, LINK_SPEC): New macros.
(FDPIC_FPTR_REGNO, FDPIC_REGNO, OUR_FDPIC_REG): New macros.
(TRAMPOLINE_SIZE, TRAMPOLINE_TEMPLATE): Adjust for FD-PIC.
(CONDITIONAL_REGISTER_USAGE): If TARGET_FDPIC, FDPIC_REGNO is
call-used.
(enum reg_class, REG_CLASS_CONTENTS, REG_CLASS_NAMES): Add
FDPIC_REGS and FDPIC_FPTR_REGS.
(REG_CLASS_FROM_LETTER): Use 'Z' and 'Y' for them.
* config/bfin/bfin.md (UNSPEC_MOVE_FDPIC, UNSPEC_FUNCDESC_GOT17M4,
UNSPEC_VOLATILE_LOAD_FUNCDESC): New constants.
(load_funcdescsi): New pattern.
(call_symbol_fdpic, sibcall_symbol_fdpic, call_value_symbol_fdpic,
sibcall_value_symbol_fdpic, call_insn_fdpic, sibcall_insn_fdpic,
call_value_insn_fdpic, sibcall_value_insn_fdpic): New patterns.
From-SVN: r114199
2006-05-29 16:11:07 +02:00
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(UNSPEC_VOLATILE_SSYNC 2)
|
2007-06-13 19:41:07 +02:00
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(UNSPEC_VOLATILE_LOAD_FUNCDESC 3)
|
2008-10-29 17:37:22 +01:00
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(UNSPEC_VOLATILE_STORE_EH_HANDLER 4)
|
2009-09-07 20:06:51 +02:00
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(UNSPEC_VOLATILE_DUMMY 5)
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(UNSPEC_VOLATILE_STALL 6)])
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2005-04-05 13:26:48 +02:00
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genmodes.c (make_vector_mode): Allow making VECTOR_MODE_INT of a MODE_PARTIAL_INT mode.
* genmodes.c (make_vector_mode): Allow making VECTOR_MODE_INT of a
MODE_PARTIAL_INT mode.
* config/bfin/bfin-modes.def: Add V2PDI and V2SI.
* config/bfin/bfin.c (print_operand): Add macflag and mac/msu modifiers
for CONST_INTs.
(hard_regno_mode_ok): V2PDImode is ok for accumulators.
* config/bfin/bfin.h (CLASS_MAX_NREGS, HARD_REGNO_NREGS): Handle
V2PDImode.
* config/bfin/predicates.md (const01_operand, vec_shift_operand):
New predicates.
* config/bfin/bfin.md (UNSPEC_MUL_WITH_FLAG, UNSPEC_MAC_WITH_FLAG):
New constants.
(MACFLAG_NONE, MACFLAG_T, MACFLAG_FU, MACFLAG_TFU, MACFLAG_IS,
MACFLAG_IU, MACFLAG_W32, MACFLAG_M, MACFLAG_S2RND, MACFLAG_ISS2,
MACFLAG_IH): Likewise.
(movstricthi_1): Renamed from "*movstricthi".
(load_accumulator, load_accumulator_pair, movsi_insv, insv,
ssaddsi3, sssubsi3, ssnegsi2, signbitssi2, smaxhi3, sminhi3,
abshi2, neghi2, ssneghi2, signbitshi2, movhi_low2high,
movhi_high2high, movhi_low2low, movhi_high2low, movhiv2hi_low,
movhiv2hi_high, composev2hi, movv2hi_hi, movv2hi_hi_low,
movv2hi_hi_high, ssaddhi3, sssubhi3, ssaddv2hi3, sssubv2hi3,
addsubv2hi3, subaddv2hi3, ssaddsubv2hi3, sssubaddv2hi3,
sublohiv2hi3, subhilov2hi3, sssublohiv2hi3, sssubhilov2hi3,
addlohiv2hi3, addhilov2hi3, ssaddlohiv2hi3, ssaddhilov2hi3,
mulhisi_ll, mulhisi_lh, mulhisi_hl, mulhisi_hh, ssnegv2hi2,
ssashiftv2hi3, ssashifthi3, lshiftv2hi3, lshifthi3, packv2hi,
flag_mulhi, flag_mulhisi_parts, flag_machi, flag_machi_acconly,
flag_macinithi, flag_macinit1hi, flag_mulv2hi, flag_mulv2hi_parts,
flag_macv2hi_parts, flag_macv2hi_parts_acconly,
flag_macinitv2hi_parts, flag_macinit1v2hi_parts): New patterns.
From-SVN: r113245
2006-04-25 13:49:27 +02:00
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(define_constants
|
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[(MACFLAG_NONE 0)
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(MACFLAG_T 1)
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(MACFLAG_FU 2)
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(MACFLAG_TFU 3)
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(MACFLAG_IS 4)
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(MACFLAG_IU 5)
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(MACFLAG_W32 6)
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(MACFLAG_M 7)
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2007-04-12 15:03:17 +02:00
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(MACFLAG_IS_M 8)
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(MACFLAG_S2RND 9)
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(MACFLAG_ISS2 10)
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(MACFLAG_IH 11)])
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genmodes.c (make_vector_mode): Allow making VECTOR_MODE_INT of a MODE_PARTIAL_INT mode.
* genmodes.c (make_vector_mode): Allow making VECTOR_MODE_INT of a
MODE_PARTIAL_INT mode.
* config/bfin/bfin-modes.def: Add V2PDI and V2SI.
* config/bfin/bfin.c (print_operand): Add macflag and mac/msu modifiers
for CONST_INTs.
(hard_regno_mode_ok): V2PDImode is ok for accumulators.
* config/bfin/bfin.h (CLASS_MAX_NREGS, HARD_REGNO_NREGS): Handle
V2PDImode.
* config/bfin/predicates.md (const01_operand, vec_shift_operand):
New predicates.
* config/bfin/bfin.md (UNSPEC_MUL_WITH_FLAG, UNSPEC_MAC_WITH_FLAG):
New constants.
(MACFLAG_NONE, MACFLAG_T, MACFLAG_FU, MACFLAG_TFU, MACFLAG_IS,
MACFLAG_IU, MACFLAG_W32, MACFLAG_M, MACFLAG_S2RND, MACFLAG_ISS2,
MACFLAG_IH): Likewise.
(movstricthi_1): Renamed from "*movstricthi".
(load_accumulator, load_accumulator_pair, movsi_insv, insv,
ssaddsi3, sssubsi3, ssnegsi2, signbitssi2, smaxhi3, sminhi3,
abshi2, neghi2, ssneghi2, signbitshi2, movhi_low2high,
movhi_high2high, movhi_low2low, movhi_high2low, movhiv2hi_low,
movhiv2hi_high, composev2hi, movv2hi_hi, movv2hi_hi_low,
movv2hi_hi_high, ssaddhi3, sssubhi3, ssaddv2hi3, sssubv2hi3,
addsubv2hi3, subaddv2hi3, ssaddsubv2hi3, sssubaddv2hi3,
sublohiv2hi3, subhilov2hi3, sssublohiv2hi3, sssubhilov2hi3,
addlohiv2hi3, addhilov2hi3, ssaddlohiv2hi3, ssaddhilov2hi3,
mulhisi_ll, mulhisi_lh, mulhisi_hl, mulhisi_hh, ssnegv2hi2,
ssashiftv2hi3, ssashifthi3, lshiftv2hi3, lshifthi3, packv2hi,
flag_mulhi, flag_mulhisi_parts, flag_machi, flag_machi_acconly,
flag_macinithi, flag_macinit1hi, flag_mulv2hi, flag_mulv2hi_parts,
flag_macv2hi_parts, flag_macv2hi_parts_acconly,
flag_macinitv2hi_parts, flag_macinit1v2hi_parts): New patterns.
From-SVN: r113245
2006-04-25 13:49:27 +02:00
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2005-04-05 13:26:48 +02:00
|
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(define_attr "type"
|
From Jie Zhang <jie.zhang@analog.com>:
* config/bfin/predicates.md (p_register_operand): New
predicate.
(dp_register_operand): New predicate.
* config/bfin/bfin-protos.h (WA_05000074): Define.
(ENABLE_WA_05000074): Define.
* config/bfin/bfin.c (bfin_cpus[]): Add WA_05000074 for
all cpus.
(bfin_gen_bundles): Put dsp32shiftimm instruction in slot[0].
* config/bfin/bfin.md (define_attr type): Add dsp32shiftimm.
(define_attr addrtype): Allow load/store register to be
P register.
(define_attr storereg): New.
(define_cpu_unit anomaly_05000074): New.
(define_insn_reservation dsp32shiftimm): New.
(define_insn_reservation dsp32shiftimm_anomaly_05000074): New.
(define_insn_reservation loadp): Cannot use slot2.
(define_insn_reservation loadsp): Cannot use slot2.
(define_insn_reservation storep): Cannot use slot2. Does not
apply when working around 05000074.
(define_insn_reservation storep_anomaly_05000074): New.
(define_insn_reservation storei): Does not apply when working
around 05000074.
(define_insn_reservation storei_anomaly_05000074): New.
(define_attr length): Add dsp32shiftimm case.
(define_insn movsi_insn32, movsi_insv, ashlsi3_insn, ashrsi3,
ror_one, rol_one, lshrsi3, lshrpdi3, ashrpdi3, movhiv2hi_low,
movhiv2hi_high, composev2hi, packv2hi, movv2hi_hi,
ssashiftv2hi3, ssashifthi3, ssashiftsi3, lshiftv2hi3, lshifthi3):
Set type as dsp32shiftimm for dsp32shiftimm alternatives.
From-SVN: r151490
2009-09-07 23:40:23 +02:00
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"move,movcc,mvi,mcld,mcst,dsp32,dsp32shiftimm,mult,alu0,shft,brcc,br,call,misc,sync,compare,dummy,stall"
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2005-04-05 13:26:48 +02:00
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(const_string "misc"))
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2009-09-07 20:06:51 +02:00
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(define_attr "addrtype" "32bit,preg,spreg,ireg"
|
predicates.md (d_register_operand, [...]): New predicates.
* config/bfin/predicates.md (d_register_operand, mem_p_address_operand,
mem_i_address_operand): New predicates.
* config/bfin/bfin.c (bfin_issue_rate): New function.
(TARGET_SCHED_ISSUE_RATE): New macro.
* config/bfin/bfin.md (addrtype): New attribute.
(slot0, slot1, slot2, store, pregs): New cpu_units.
(core): Now a define_reservation.
(alu): Remove some insn types from this reservation.
(dsp32, load32, loadp, loadi, store32, storep, storei, multi): New
insn reservations.
(dummy reservation): Don't trigger for mcld insns.
(absence_sets): Two new absence sets to enforce slot ordering.
(popsi_insn): Set addrtype.
From-SVN: r119090
2006-11-22 15:12:46 +01:00
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|
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|
(cond [(and (eq_attr "type" "mcld")
|
From Jie Zhang <jie.zhang@analog.com>:
* config/bfin/predicates.md (p_register_operand): New
predicate.
(dp_register_operand): New predicate.
* config/bfin/bfin-protos.h (WA_05000074): Define.
(ENABLE_WA_05000074): Define.
* config/bfin/bfin.c (bfin_cpus[]): Add WA_05000074 for
all cpus.
(bfin_gen_bundles): Put dsp32shiftimm instruction in slot[0].
* config/bfin/bfin.md (define_attr type): Add dsp32shiftimm.
(define_attr addrtype): Allow load/store register to be
P register.
(define_attr storereg): New.
(define_cpu_unit anomaly_05000074): New.
(define_insn_reservation dsp32shiftimm): New.
(define_insn_reservation dsp32shiftimm_anomaly_05000074): New.
(define_insn_reservation loadp): Cannot use slot2.
(define_insn_reservation loadsp): Cannot use slot2.
(define_insn_reservation storep): Cannot use slot2. Does not
apply when working around 05000074.
(define_insn_reservation storep_anomaly_05000074): New.
(define_insn_reservation storei): Does not apply when working
around 05000074.
(define_insn_reservation storei_anomaly_05000074): New.
(define_attr length): Add dsp32shiftimm case.
(define_insn movsi_insn32, movsi_insv, ashlsi3_insn, ashrsi3,
ror_one, rol_one, lshrsi3, lshrpdi3, ashrpdi3, movhiv2hi_low,
movhiv2hi_high, composev2hi, packv2hi, movv2hi_hi,
ssashiftv2hi3, ssashifthi3, ssashiftsi3, lshiftv2hi3, lshifthi3):
Set type as dsp32shiftimm for dsp32shiftimm alternatives.
From-SVN: r151490
2009-09-07 23:40:23 +02:00
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|
(and (match_operand 0 "dp_register_operand" "")
|
predicates.md (d_register_operand, [...]): New predicates.
* config/bfin/predicates.md (d_register_operand, mem_p_address_operand,
mem_i_address_operand): New predicates.
* config/bfin/bfin.c (bfin_issue_rate): New function.
(TARGET_SCHED_ISSUE_RATE): New macro.
* config/bfin/bfin.md (addrtype): New attribute.
(slot0, slot1, slot2, store, pregs): New cpu_units.
(core): Now a define_reservation.
(alu): Remove some insn types from this reservation.
(dsp32, load32, loadp, loadi, store32, storep, storei, multi): New
insn reservations.
(dummy reservation): Don't trigger for mcld insns.
(absence_sets): Two new absence sets to enforce slot ordering.
(popsi_insn): Set addrtype.
From-SVN: r119090
2006-11-22 15:12:46 +01:00
|
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(match_operand 1 "mem_p_address_operand" "")))
|
|
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(const_string "preg")
|
2009-09-07 20:06:51 +02:00
|
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(and (eq_attr "type" "mcld")
|
From Jie Zhang <jie.zhang@analog.com>:
* config/bfin/predicates.md (p_register_operand): New
predicate.
(dp_register_operand): New predicate.
* config/bfin/bfin-protos.h (WA_05000074): Define.
(ENABLE_WA_05000074): Define.
* config/bfin/bfin.c (bfin_cpus[]): Add WA_05000074 for
all cpus.
(bfin_gen_bundles): Put dsp32shiftimm instruction in slot[0].
* config/bfin/bfin.md (define_attr type): Add dsp32shiftimm.
(define_attr addrtype): Allow load/store register to be
P register.
(define_attr storereg): New.
(define_cpu_unit anomaly_05000074): New.
(define_insn_reservation dsp32shiftimm): New.
(define_insn_reservation dsp32shiftimm_anomaly_05000074): New.
(define_insn_reservation loadp): Cannot use slot2.
(define_insn_reservation loadsp): Cannot use slot2.
(define_insn_reservation storep): Cannot use slot2. Does not
apply when working around 05000074.
(define_insn_reservation storep_anomaly_05000074): New.
(define_insn_reservation storei): Does not apply when working
around 05000074.
(define_insn_reservation storei_anomaly_05000074): New.
(define_attr length): Add dsp32shiftimm case.
(define_insn movsi_insn32, movsi_insv, ashlsi3_insn, ashrsi3,
ror_one, rol_one, lshrsi3, lshrpdi3, ashrpdi3, movhiv2hi_low,
movhiv2hi_high, composev2hi, packv2hi, movv2hi_hi,
ssashiftv2hi3, ssashifthi3, ssashiftsi3, lshiftv2hi3, lshifthi3):
Set type as dsp32shiftimm for dsp32shiftimm alternatives.
From-SVN: r151490
2009-09-07 23:40:23 +02:00
|
|
|
|
(and (match_operand 0 "dp_register_operand" "")
|
2009-09-07 20:06:51 +02:00
|
|
|
|
(match_operand 1 "mem_spfp_address_operand" "")))
|
|
|
|
|
(const_string "spreg")
|
predicates.md (d_register_operand, [...]): New predicates.
* config/bfin/predicates.md (d_register_operand, mem_p_address_operand,
mem_i_address_operand): New predicates.
* config/bfin/bfin.c (bfin_issue_rate): New function.
(TARGET_SCHED_ISSUE_RATE): New macro.
* config/bfin/bfin.md (addrtype): New attribute.
(slot0, slot1, slot2, store, pregs): New cpu_units.
(core): Now a define_reservation.
(alu): Remove some insn types from this reservation.
(dsp32, load32, loadp, loadi, store32, storep, storei, multi): New
insn reservations.
(dummy reservation): Don't trigger for mcld insns.
(absence_sets): Two new absence sets to enforce slot ordering.
(popsi_insn): Set addrtype.
From-SVN: r119090
2006-11-22 15:12:46 +01:00
|
|
|
|
(and (eq_attr "type" "mcld")
|
From Jie Zhang <jie.zhang@analog.com>:
* config/bfin/predicates.md (p_register_operand): New
predicate.
(dp_register_operand): New predicate.
* config/bfin/bfin-protos.h (WA_05000074): Define.
(ENABLE_WA_05000074): Define.
* config/bfin/bfin.c (bfin_cpus[]): Add WA_05000074 for
all cpus.
(bfin_gen_bundles): Put dsp32shiftimm instruction in slot[0].
* config/bfin/bfin.md (define_attr type): Add dsp32shiftimm.
(define_attr addrtype): Allow load/store register to be
P register.
(define_attr storereg): New.
(define_cpu_unit anomaly_05000074): New.
(define_insn_reservation dsp32shiftimm): New.
(define_insn_reservation dsp32shiftimm_anomaly_05000074): New.
(define_insn_reservation loadp): Cannot use slot2.
(define_insn_reservation loadsp): Cannot use slot2.
(define_insn_reservation storep): Cannot use slot2. Does not
apply when working around 05000074.
(define_insn_reservation storep_anomaly_05000074): New.
(define_insn_reservation storei): Does not apply when working
around 05000074.
(define_insn_reservation storei_anomaly_05000074): New.
(define_attr length): Add dsp32shiftimm case.
(define_insn movsi_insn32, movsi_insv, ashlsi3_insn, ashrsi3,
ror_one, rol_one, lshrsi3, lshrpdi3, ashrpdi3, movhiv2hi_low,
movhiv2hi_high, composev2hi, packv2hi, movv2hi_hi,
ssashiftv2hi3, ssashifthi3, ssashiftsi3, lshiftv2hi3, lshifthi3):
Set type as dsp32shiftimm for dsp32shiftimm alternatives.
From-SVN: r151490
2009-09-07 23:40:23 +02:00
|
|
|
|
(and (match_operand 0 "dp_register_operand" "")
|
predicates.md (d_register_operand, [...]): New predicates.
* config/bfin/predicates.md (d_register_operand, mem_p_address_operand,
mem_i_address_operand): New predicates.
* config/bfin/bfin.c (bfin_issue_rate): New function.
(TARGET_SCHED_ISSUE_RATE): New macro.
* config/bfin/bfin.md (addrtype): New attribute.
(slot0, slot1, slot2, store, pregs): New cpu_units.
(core): Now a define_reservation.
(alu): Remove some insn types from this reservation.
(dsp32, load32, loadp, loadi, store32, storep, storei, multi): New
insn reservations.
(dummy reservation): Don't trigger for mcld insns.
(absence_sets): Two new absence sets to enforce slot ordering.
(popsi_insn): Set addrtype.
From-SVN: r119090
2006-11-22 15:12:46 +01:00
|
|
|
|
(match_operand 1 "mem_i_address_operand" "")))
|
|
|
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|
(const_string "ireg")
|
|
|
|
|
(and (eq_attr "type" "mcst")
|
From Jie Zhang <jie.zhang@analog.com>:
* config/bfin/predicates.md (p_register_operand): New
predicate.
(dp_register_operand): New predicate.
* config/bfin/bfin-protos.h (WA_05000074): Define.
(ENABLE_WA_05000074): Define.
* config/bfin/bfin.c (bfin_cpus[]): Add WA_05000074 for
all cpus.
(bfin_gen_bundles): Put dsp32shiftimm instruction in slot[0].
* config/bfin/bfin.md (define_attr type): Add dsp32shiftimm.
(define_attr addrtype): Allow load/store register to be
P register.
(define_attr storereg): New.
(define_cpu_unit anomaly_05000074): New.
(define_insn_reservation dsp32shiftimm): New.
(define_insn_reservation dsp32shiftimm_anomaly_05000074): New.
(define_insn_reservation loadp): Cannot use slot2.
(define_insn_reservation loadsp): Cannot use slot2.
(define_insn_reservation storep): Cannot use slot2. Does not
apply when working around 05000074.
(define_insn_reservation storep_anomaly_05000074): New.
(define_insn_reservation storei): Does not apply when working
around 05000074.
(define_insn_reservation storei_anomaly_05000074): New.
(define_attr length): Add dsp32shiftimm case.
(define_insn movsi_insn32, movsi_insv, ashlsi3_insn, ashrsi3,
ror_one, rol_one, lshrsi3, lshrpdi3, ashrpdi3, movhiv2hi_low,
movhiv2hi_high, composev2hi, packv2hi, movv2hi_hi,
ssashiftv2hi3, ssashifthi3, ssashiftsi3, lshiftv2hi3, lshifthi3):
Set type as dsp32shiftimm for dsp32shiftimm alternatives.
From-SVN: r151490
2009-09-07 23:40:23 +02:00
|
|
|
|
(and (match_operand 1 "dp_register_operand" "")
|
predicates.md (d_register_operand, [...]): New predicates.
* config/bfin/predicates.md (d_register_operand, mem_p_address_operand,
mem_i_address_operand): New predicates.
* config/bfin/bfin.c (bfin_issue_rate): New function.
(TARGET_SCHED_ISSUE_RATE): New macro.
* config/bfin/bfin.md (addrtype): New attribute.
(slot0, slot1, slot2, store, pregs): New cpu_units.
(core): Now a define_reservation.
(alu): Remove some insn types from this reservation.
(dsp32, load32, loadp, loadi, store32, storep, storei, multi): New
insn reservations.
(dummy reservation): Don't trigger for mcld insns.
(absence_sets): Two new absence sets to enforce slot ordering.
(popsi_insn): Set addrtype.
From-SVN: r119090
2006-11-22 15:12:46 +01:00
|
|
|
|
(match_operand 0 "mem_p_address_operand" "")))
|
|
|
|
|
(const_string "preg")
|
2009-09-07 20:06:51 +02:00
|
|
|
|
(and (eq_attr "type" "mcst")
|
From Jie Zhang <jie.zhang@analog.com>:
* config/bfin/predicates.md (p_register_operand): New
predicate.
(dp_register_operand): New predicate.
* config/bfin/bfin-protos.h (WA_05000074): Define.
(ENABLE_WA_05000074): Define.
* config/bfin/bfin.c (bfin_cpus[]): Add WA_05000074 for
all cpus.
(bfin_gen_bundles): Put dsp32shiftimm instruction in slot[0].
* config/bfin/bfin.md (define_attr type): Add dsp32shiftimm.
(define_attr addrtype): Allow load/store register to be
P register.
(define_attr storereg): New.
(define_cpu_unit anomaly_05000074): New.
(define_insn_reservation dsp32shiftimm): New.
(define_insn_reservation dsp32shiftimm_anomaly_05000074): New.
(define_insn_reservation loadp): Cannot use slot2.
(define_insn_reservation loadsp): Cannot use slot2.
(define_insn_reservation storep): Cannot use slot2. Does not
apply when working around 05000074.
(define_insn_reservation storep_anomaly_05000074): New.
(define_insn_reservation storei): Does not apply when working
around 05000074.
(define_insn_reservation storei_anomaly_05000074): New.
(define_attr length): Add dsp32shiftimm case.
(define_insn movsi_insn32, movsi_insv, ashlsi3_insn, ashrsi3,
ror_one, rol_one, lshrsi3, lshrpdi3, ashrpdi3, movhiv2hi_low,
movhiv2hi_high, composev2hi, packv2hi, movv2hi_hi,
ssashiftv2hi3, ssashifthi3, ssashiftsi3, lshiftv2hi3, lshifthi3):
Set type as dsp32shiftimm for dsp32shiftimm alternatives.
From-SVN: r151490
2009-09-07 23:40:23 +02:00
|
|
|
|
(and (match_operand 1 "dp_register_operand" "")
|
2009-09-07 20:06:51 +02:00
|
|
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(match_operand 0 "mem_spfp_address_operand" "")))
|
|
|
|
|
(const_string "spreg")
|
predicates.md (d_register_operand, [...]): New predicates.
* config/bfin/predicates.md (d_register_operand, mem_p_address_operand,
mem_i_address_operand): New predicates.
* config/bfin/bfin.c (bfin_issue_rate): New function.
(TARGET_SCHED_ISSUE_RATE): New macro.
* config/bfin/bfin.md (addrtype): New attribute.
(slot0, slot1, slot2, store, pregs): New cpu_units.
(core): Now a define_reservation.
(alu): Remove some insn types from this reservation.
(dsp32, load32, loadp, loadi, store32, storep, storei, multi): New
insn reservations.
(dummy reservation): Don't trigger for mcld insns.
(absence_sets): Two new absence sets to enforce slot ordering.
(popsi_insn): Set addrtype.
From-SVN: r119090
2006-11-22 15:12:46 +01:00
|
|
|
|
(and (eq_attr "type" "mcst")
|
From Jie Zhang <jie.zhang@analog.com>:
* config/bfin/predicates.md (p_register_operand): New
predicate.
(dp_register_operand): New predicate.
* config/bfin/bfin-protos.h (WA_05000074): Define.
(ENABLE_WA_05000074): Define.
* config/bfin/bfin.c (bfin_cpus[]): Add WA_05000074 for
all cpus.
(bfin_gen_bundles): Put dsp32shiftimm instruction in slot[0].
* config/bfin/bfin.md (define_attr type): Add dsp32shiftimm.
(define_attr addrtype): Allow load/store register to be
P register.
(define_attr storereg): New.
(define_cpu_unit anomaly_05000074): New.
(define_insn_reservation dsp32shiftimm): New.
(define_insn_reservation dsp32shiftimm_anomaly_05000074): New.
(define_insn_reservation loadp): Cannot use slot2.
(define_insn_reservation loadsp): Cannot use slot2.
(define_insn_reservation storep): Cannot use slot2. Does not
apply when working around 05000074.
(define_insn_reservation storep_anomaly_05000074): New.
(define_insn_reservation storei): Does not apply when working
around 05000074.
(define_insn_reservation storei_anomaly_05000074): New.
(define_attr length): Add dsp32shiftimm case.
(define_insn movsi_insn32, movsi_insv, ashlsi3_insn, ashrsi3,
ror_one, rol_one, lshrsi3, lshrpdi3, ashrpdi3, movhiv2hi_low,
movhiv2hi_high, composev2hi, packv2hi, movv2hi_hi,
ssashiftv2hi3, ssashifthi3, ssashiftsi3, lshiftv2hi3, lshifthi3):
Set type as dsp32shiftimm for dsp32shiftimm alternatives.
From-SVN: r151490
2009-09-07 23:40:23 +02:00
|
|
|
|
(and (match_operand 1 "dp_register_operand" "")
|
predicates.md (d_register_operand, [...]): New predicates.
* config/bfin/predicates.md (d_register_operand, mem_p_address_operand,
mem_i_address_operand): New predicates.
* config/bfin/bfin.c (bfin_issue_rate): New function.
(TARGET_SCHED_ISSUE_RATE): New macro.
* config/bfin/bfin.md (addrtype): New attribute.
(slot0, slot1, slot2, store, pregs): New cpu_units.
(core): Now a define_reservation.
(alu): Remove some insn types from this reservation.
(dsp32, load32, loadp, loadi, store32, storep, storei, multi): New
insn reservations.
(dummy reservation): Don't trigger for mcld insns.
(absence_sets): Two new absence sets to enforce slot ordering.
(popsi_insn): Set addrtype.
From-SVN: r119090
2006-11-22 15:12:46 +01:00
|
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|
(match_operand 0 "mem_i_address_operand" "")))
|
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(const_string "ireg")]
|
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(const_string "32bit")))
|
|
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|
|
|
From Jie Zhang <jie.zhang@analog.com>:
* config/bfin/predicates.md (p_register_operand): New
predicate.
(dp_register_operand): New predicate.
* config/bfin/bfin-protos.h (WA_05000074): Define.
(ENABLE_WA_05000074): Define.
* config/bfin/bfin.c (bfin_cpus[]): Add WA_05000074 for
all cpus.
(bfin_gen_bundles): Put dsp32shiftimm instruction in slot[0].
* config/bfin/bfin.md (define_attr type): Add dsp32shiftimm.
(define_attr addrtype): Allow load/store register to be
P register.
(define_attr storereg): New.
(define_cpu_unit anomaly_05000074): New.
(define_insn_reservation dsp32shiftimm): New.
(define_insn_reservation dsp32shiftimm_anomaly_05000074): New.
(define_insn_reservation loadp): Cannot use slot2.
(define_insn_reservation loadsp): Cannot use slot2.
(define_insn_reservation storep): Cannot use slot2. Does not
apply when working around 05000074.
(define_insn_reservation storep_anomaly_05000074): New.
(define_insn_reservation storei): Does not apply when working
around 05000074.
(define_insn_reservation storei_anomaly_05000074): New.
(define_attr length): Add dsp32shiftimm case.
(define_insn movsi_insn32, movsi_insv, ashlsi3_insn, ashrsi3,
ror_one, rol_one, lshrsi3, lshrpdi3, ashrpdi3, movhiv2hi_low,
movhiv2hi_high, composev2hi, packv2hi, movv2hi_hi,
ssashiftv2hi3, ssashifthi3, ssashiftsi3, lshiftv2hi3, lshifthi3):
Set type as dsp32shiftimm for dsp32shiftimm alternatives.
From-SVN: r151490
2009-09-07 23:40:23 +02:00
|
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(define_attr "storereg" "preg,other"
|
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(cond [(and (eq_attr "type" "mcst")
|
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(match_operand 1 "p_register_operand" ""))
|
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(const_string "preg")]
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(const_string "other")))
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2005-04-05 13:26:48 +02:00
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;; Scheduling definitions
|
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(define_automaton "bfin")
|
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|
predicates.md (d_register_operand, [...]): New predicates.
* config/bfin/predicates.md (d_register_operand, mem_p_address_operand,
mem_i_address_operand): New predicates.
* config/bfin/bfin.c (bfin_issue_rate): New function.
(TARGET_SCHED_ISSUE_RATE): New macro.
* config/bfin/bfin.md (addrtype): New attribute.
(slot0, slot1, slot2, store, pregs): New cpu_units.
(core): Now a define_reservation.
(alu): Remove some insn types from this reservation.
(dsp32, load32, loadp, loadi, store32, storep, storei, multi): New
insn reservations.
(dummy reservation): Don't trigger for mcld insns.
(absence_sets): Two new absence sets to enforce slot ordering.
(popsi_insn): Set addrtype.
From-SVN: r119090
2006-11-22 15:12:46 +01:00
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(define_cpu_unit "slot0" "bfin")
|
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(define_cpu_unit "slot1" "bfin")
|
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(define_cpu_unit "slot2" "bfin")
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;; Three units used to enforce parallel issue restrictions:
|
2007-02-04 17:40:30 +01:00
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;; only one of the 16-bit slots can use a P register in an address,
|
predicates.md (d_register_operand, [...]): New predicates.
* config/bfin/predicates.md (d_register_operand, mem_p_address_operand,
mem_i_address_operand): New predicates.
* config/bfin/bfin.c (bfin_issue_rate): New function.
(TARGET_SCHED_ISSUE_RATE): New macro.
* config/bfin/bfin.md (addrtype): New attribute.
(slot0, slot1, slot2, store, pregs): New cpu_units.
(core): Now a define_reservation.
(alu): Remove some insn types from this reservation.
(dsp32, load32, loadp, loadi, store32, storep, storei, multi): New
insn reservations.
(dummy reservation): Don't trigger for mcld insns.
(absence_sets): Two new absence sets to enforce slot ordering.
(popsi_insn): Set addrtype.
From-SVN: r119090
2006-11-22 15:12:46 +01:00
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;; and only one them can be a store.
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(define_cpu_unit "store" "bfin")
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(define_cpu_unit "pregs" "bfin")
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2009-09-07 20:06:51 +02:00
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;; A dummy unit used to delay scheduling of loads after a conditional
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;; branch.
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(define_cpu_unit "load" "bfin")
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|
From Jie Zhang <jie.zhang@analog.com>:
* config/bfin/predicates.md (p_register_operand): New
predicate.
(dp_register_operand): New predicate.
* config/bfin/bfin-protos.h (WA_05000074): Define.
(ENABLE_WA_05000074): Define.
* config/bfin/bfin.c (bfin_cpus[]): Add WA_05000074 for
all cpus.
(bfin_gen_bundles): Put dsp32shiftimm instruction in slot[0].
* config/bfin/bfin.md (define_attr type): Add dsp32shiftimm.
(define_attr addrtype): Allow load/store register to be
P register.
(define_attr storereg): New.
(define_cpu_unit anomaly_05000074): New.
(define_insn_reservation dsp32shiftimm): New.
(define_insn_reservation dsp32shiftimm_anomaly_05000074): New.
(define_insn_reservation loadp): Cannot use slot2.
(define_insn_reservation loadsp): Cannot use slot2.
(define_insn_reservation storep): Cannot use slot2. Does not
apply when working around 05000074.
(define_insn_reservation storep_anomaly_05000074): New.
(define_insn_reservation storei): Does not apply when working
around 05000074.
(define_insn_reservation storei_anomaly_05000074): New.
(define_attr length): Add dsp32shiftimm case.
(define_insn movsi_insn32, movsi_insv, ashlsi3_insn, ashrsi3,
ror_one, rol_one, lshrsi3, lshrpdi3, ashrpdi3, movhiv2hi_low,
movhiv2hi_high, composev2hi, packv2hi, movv2hi_hi,
ssashiftv2hi3, ssashifthi3, ssashiftsi3, lshiftv2hi3, lshifthi3):
Set type as dsp32shiftimm for dsp32shiftimm alternatives.
From-SVN: r151490
2009-09-07 23:40:23 +02:00
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;; A logical unit used to work around anomaly 05000074.
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(define_cpu_unit "anomaly_05000074" "bfin")
|
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predicates.md (d_register_operand, [...]): New predicates.
* config/bfin/predicates.md (d_register_operand, mem_p_address_operand,
mem_i_address_operand): New predicates.
* config/bfin/bfin.c (bfin_issue_rate): New function.
(TARGET_SCHED_ISSUE_RATE): New macro.
* config/bfin/bfin.md (addrtype): New attribute.
(slot0, slot1, slot2, store, pregs): New cpu_units.
(core): Now a define_reservation.
(alu): Remove some insn types from this reservation.
(dsp32, load32, loadp, loadi, store32, storep, storei, multi): New
insn reservations.
(dummy reservation): Don't trigger for mcld insns.
(absence_sets): Two new absence sets to enforce slot ordering.
(popsi_insn): Set addrtype.
From-SVN: r119090
2006-11-22 15:12:46 +01:00
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(define_reservation "core" "slot0+slot1+slot2")
|
2005-04-05 13:26:48 +02:00
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(define_insn_reservation "alu" 1
|
2006-12-08 13:42:44 +01:00
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(eq_attr "type" "move,movcc,mvi,alu0,shft,brcc,br,call,misc,sync,compare")
|
2005-04-05 13:26:48 +02:00
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"core")
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(define_insn_reservation "imul" 3
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(eq_attr "type" "mult")
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"core*3")
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predicates.md (d_register_operand, [...]): New predicates.
* config/bfin/predicates.md (d_register_operand, mem_p_address_operand,
mem_i_address_operand): New predicates.
* config/bfin/bfin.c (bfin_issue_rate): New function.
(TARGET_SCHED_ISSUE_RATE): New macro.
* config/bfin/bfin.md (addrtype): New attribute.
(slot0, slot1, slot2, store, pregs): New cpu_units.
(core): Now a define_reservation.
(alu): Remove some insn types from this reservation.
(dsp32, load32, loadp, loadi, store32, storep, storei, multi): New
insn reservations.
(dummy reservation): Don't trigger for mcld insns.
(absence_sets): Two new absence sets to enforce slot ordering.
(popsi_insn): Set addrtype.
From-SVN: r119090
2006-11-22 15:12:46 +01:00
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|
(define_insn_reservation "dsp32" 1
|
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(eq_attr "type" "dsp32")
|
|
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|
"slot0")
|
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|
|
|
From Jie Zhang <jie.zhang@analog.com>:
* config/bfin/predicates.md (p_register_operand): New
predicate.
(dp_register_operand): New predicate.
* config/bfin/bfin-protos.h (WA_05000074): Define.
(ENABLE_WA_05000074): Define.
* config/bfin/bfin.c (bfin_cpus[]): Add WA_05000074 for
all cpus.
(bfin_gen_bundles): Put dsp32shiftimm instruction in slot[0].
* config/bfin/bfin.md (define_attr type): Add dsp32shiftimm.
(define_attr addrtype): Allow load/store register to be
P register.
(define_attr storereg): New.
(define_cpu_unit anomaly_05000074): New.
(define_insn_reservation dsp32shiftimm): New.
(define_insn_reservation dsp32shiftimm_anomaly_05000074): New.
(define_insn_reservation loadp): Cannot use slot2.
(define_insn_reservation loadsp): Cannot use slot2.
(define_insn_reservation storep): Cannot use slot2. Does not
apply when working around 05000074.
(define_insn_reservation storep_anomaly_05000074): New.
(define_insn_reservation storei): Does not apply when working
around 05000074.
(define_insn_reservation storei_anomaly_05000074): New.
(define_attr length): Add dsp32shiftimm case.
(define_insn movsi_insn32, movsi_insv, ashlsi3_insn, ashrsi3,
ror_one, rol_one, lshrsi3, lshrpdi3, ashrpdi3, movhiv2hi_low,
movhiv2hi_high, composev2hi, packv2hi, movv2hi_hi,
ssashiftv2hi3, ssashifthi3, ssashiftsi3, lshiftv2hi3, lshifthi3):
Set type as dsp32shiftimm for dsp32shiftimm alternatives.
From-SVN: r151490
2009-09-07 23:40:23 +02:00
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(define_insn_reservation "dsp32shiftimm" 1
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(and (eq_attr "type" "dsp32shiftimm")
|
2011-09-14 23:15:09 +02:00
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(not (match_test "ENABLE_WA_05000074")))
|
From Jie Zhang <jie.zhang@analog.com>:
* config/bfin/predicates.md (p_register_operand): New
predicate.
(dp_register_operand): New predicate.
* config/bfin/bfin-protos.h (WA_05000074): Define.
(ENABLE_WA_05000074): Define.
* config/bfin/bfin.c (bfin_cpus[]): Add WA_05000074 for
all cpus.
(bfin_gen_bundles): Put dsp32shiftimm instruction in slot[0].
* config/bfin/bfin.md (define_attr type): Add dsp32shiftimm.
(define_attr addrtype): Allow load/store register to be
P register.
(define_attr storereg): New.
(define_cpu_unit anomaly_05000074): New.
(define_insn_reservation dsp32shiftimm): New.
(define_insn_reservation dsp32shiftimm_anomaly_05000074): New.
(define_insn_reservation loadp): Cannot use slot2.
(define_insn_reservation loadsp): Cannot use slot2.
(define_insn_reservation storep): Cannot use slot2. Does not
apply when working around 05000074.
(define_insn_reservation storep_anomaly_05000074): New.
(define_insn_reservation storei): Does not apply when working
around 05000074.
(define_insn_reservation storei_anomaly_05000074): New.
(define_attr length): Add dsp32shiftimm case.
(define_insn movsi_insn32, movsi_insv, ashlsi3_insn, ashrsi3,
ror_one, rol_one, lshrsi3, lshrpdi3, ashrpdi3, movhiv2hi_low,
movhiv2hi_high, composev2hi, packv2hi, movv2hi_hi,
ssashiftv2hi3, ssashifthi3, ssashiftsi3, lshiftv2hi3, lshifthi3):
Set type as dsp32shiftimm for dsp32shiftimm alternatives.
From-SVN: r151490
2009-09-07 23:40:23 +02:00
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"slot0")
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(define_insn_reservation "dsp32shiftimm_anomaly_05000074" 1
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(and (eq_attr "type" "dsp32shiftimm")
|
2011-09-14 23:15:09 +02:00
|
|
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|
(match_test "ENABLE_WA_05000074"))
|
From Jie Zhang <jie.zhang@analog.com>:
* config/bfin/predicates.md (p_register_operand): New
predicate.
(dp_register_operand): New predicate.
* config/bfin/bfin-protos.h (WA_05000074): Define.
(ENABLE_WA_05000074): Define.
* config/bfin/bfin.c (bfin_cpus[]): Add WA_05000074 for
all cpus.
(bfin_gen_bundles): Put dsp32shiftimm instruction in slot[0].
* config/bfin/bfin.md (define_attr type): Add dsp32shiftimm.
(define_attr addrtype): Allow load/store register to be
P register.
(define_attr storereg): New.
(define_cpu_unit anomaly_05000074): New.
(define_insn_reservation dsp32shiftimm): New.
(define_insn_reservation dsp32shiftimm_anomaly_05000074): New.
(define_insn_reservation loadp): Cannot use slot2.
(define_insn_reservation loadsp): Cannot use slot2.
(define_insn_reservation storep): Cannot use slot2. Does not
apply when working around 05000074.
(define_insn_reservation storep_anomaly_05000074): New.
(define_insn_reservation storei): Does not apply when working
around 05000074.
(define_insn_reservation storei_anomaly_05000074): New.
(define_attr length): Add dsp32shiftimm case.
(define_insn movsi_insn32, movsi_insv, ashlsi3_insn, ashrsi3,
ror_one, rol_one, lshrsi3, lshrpdi3, ashrpdi3, movhiv2hi_low,
movhiv2hi_high, composev2hi, packv2hi, movv2hi_hi,
ssashiftv2hi3, ssashifthi3, ssashiftsi3, lshiftv2hi3, lshifthi3):
Set type as dsp32shiftimm for dsp32shiftimm alternatives.
From-SVN: r151490
2009-09-07 23:40:23 +02:00
|
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|
"slot0+anomaly_05000074")
|
|
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|
predicates.md (d_register_operand, [...]): New predicates.
* config/bfin/predicates.md (d_register_operand, mem_p_address_operand,
mem_i_address_operand): New predicates.
* config/bfin/bfin.c (bfin_issue_rate): New function.
(TARGET_SCHED_ISSUE_RATE): New macro.
* config/bfin/bfin.md (addrtype): New attribute.
(slot0, slot1, slot2, store, pregs): New cpu_units.
(core): Now a define_reservation.
(alu): Remove some insn types from this reservation.
(dsp32, load32, loadp, loadi, store32, storep, storei, multi): New
insn reservations.
(dummy reservation): Don't trigger for mcld insns.
(absence_sets): Two new absence sets to enforce slot ordering.
(popsi_insn): Set addrtype.
From-SVN: r119090
2006-11-22 15:12:46 +01:00
|
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(define_insn_reservation "load32" 1
|
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(and (not (eq_attr "seq_insns" "multi"))
|
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(and (eq_attr "type" "mcld") (eq_attr "addrtype" "32bit")))
|
2009-09-07 20:06:51 +02:00
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|
"core+load")
|
predicates.md (d_register_operand, [...]): New predicates.
* config/bfin/predicates.md (d_register_operand, mem_p_address_operand,
mem_i_address_operand): New predicates.
* config/bfin/bfin.c (bfin_issue_rate): New function.
(TARGET_SCHED_ISSUE_RATE): New macro.
* config/bfin/bfin.md (addrtype): New attribute.
(slot0, slot1, slot2, store, pregs): New cpu_units.
(core): Now a define_reservation.
(alu): Remove some insn types from this reservation.
(dsp32, load32, loadp, loadi, store32, storep, storei, multi): New
insn reservations.
(dummy reservation): Don't trigger for mcld insns.
(absence_sets): Two new absence sets to enforce slot ordering.
(popsi_insn): Set addrtype.
From-SVN: r119090
2006-11-22 15:12:46 +01:00
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(define_insn_reservation "loadp" 1
|
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(and (not (eq_attr "seq_insns" "multi"))
|
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(and (eq_attr "type" "mcld") (eq_attr "addrtype" "preg")))
|
From Jie Zhang <jie.zhang@analog.com>:
* config/bfin/predicates.md (p_register_operand): New
predicate.
(dp_register_operand): New predicate.
* config/bfin/bfin-protos.h (WA_05000074): Define.
(ENABLE_WA_05000074): Define.
* config/bfin/bfin.c (bfin_cpus[]): Add WA_05000074 for
all cpus.
(bfin_gen_bundles): Put dsp32shiftimm instruction in slot[0].
* config/bfin/bfin.md (define_attr type): Add dsp32shiftimm.
(define_attr addrtype): Allow load/store register to be
P register.
(define_attr storereg): New.
(define_cpu_unit anomaly_05000074): New.
(define_insn_reservation dsp32shiftimm): New.
(define_insn_reservation dsp32shiftimm_anomaly_05000074): New.
(define_insn_reservation loadp): Cannot use slot2.
(define_insn_reservation loadsp): Cannot use slot2.
(define_insn_reservation storep): Cannot use slot2. Does not
apply when working around 05000074.
(define_insn_reservation storep_anomaly_05000074): New.
(define_insn_reservation storei): Does not apply when working
around 05000074.
(define_insn_reservation storei_anomaly_05000074): New.
(define_attr length): Add dsp32shiftimm case.
(define_insn movsi_insn32, movsi_insv, ashlsi3_insn, ashrsi3,
ror_one, rol_one, lshrsi3, lshrpdi3, ashrpdi3, movhiv2hi_low,
movhiv2hi_high, composev2hi, packv2hi, movv2hi_hi,
ssashiftv2hi3, ssashifthi3, ssashiftsi3, lshiftv2hi3, lshifthi3):
Set type as dsp32shiftimm for dsp32shiftimm alternatives.
From-SVN: r151490
2009-09-07 23:40:23 +02:00
|
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|
"slot1+pregs+load")
|
2009-09-07 20:06:51 +02:00
|
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(define_insn_reservation "loadsp" 1
|
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(and (not (eq_attr "seq_insns" "multi"))
|
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|
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|
(and (eq_attr "type" "mcld") (eq_attr "addrtype" "spreg")))
|
From Jie Zhang <jie.zhang@analog.com>:
* config/bfin/predicates.md (p_register_operand): New
predicate.
(dp_register_operand): New predicate.
* config/bfin/bfin-protos.h (WA_05000074): Define.
(ENABLE_WA_05000074): Define.
* config/bfin/bfin.c (bfin_cpus[]): Add WA_05000074 for
all cpus.
(bfin_gen_bundles): Put dsp32shiftimm instruction in slot[0].
* config/bfin/bfin.md (define_attr type): Add dsp32shiftimm.
(define_attr addrtype): Allow load/store register to be
P register.
(define_attr storereg): New.
(define_cpu_unit anomaly_05000074): New.
(define_insn_reservation dsp32shiftimm): New.
(define_insn_reservation dsp32shiftimm_anomaly_05000074): New.
(define_insn_reservation loadp): Cannot use slot2.
(define_insn_reservation loadsp): Cannot use slot2.
(define_insn_reservation storep): Cannot use slot2. Does not
apply when working around 05000074.
(define_insn_reservation storep_anomaly_05000074): New.
(define_insn_reservation storei): Does not apply when working
around 05000074.
(define_insn_reservation storei_anomaly_05000074): New.
(define_attr length): Add dsp32shiftimm case.
(define_insn movsi_insn32, movsi_insv, ashlsi3_insn, ashrsi3,
ror_one, rol_one, lshrsi3, lshrpdi3, ashrpdi3, movhiv2hi_low,
movhiv2hi_high, composev2hi, packv2hi, movv2hi_hi,
ssashiftv2hi3, ssashifthi3, ssashiftsi3, lshiftv2hi3, lshifthi3):
Set type as dsp32shiftimm for dsp32shiftimm alternatives.
From-SVN: r151490
2009-09-07 23:40:23 +02:00
|
|
|
|
"slot1+pregs")
|
predicates.md (d_register_operand, [...]): New predicates.
* config/bfin/predicates.md (d_register_operand, mem_p_address_operand,
mem_i_address_operand): New predicates.
* config/bfin/bfin.c (bfin_issue_rate): New function.
(TARGET_SCHED_ISSUE_RATE): New macro.
* config/bfin/bfin.md (addrtype): New attribute.
(slot0, slot1, slot2, store, pregs): New cpu_units.
(core): Now a define_reservation.
(alu): Remove some insn types from this reservation.
(dsp32, load32, loadp, loadi, store32, storep, storei, multi): New
insn reservations.
(dummy reservation): Don't trigger for mcld insns.
(absence_sets): Two new absence sets to enforce slot ordering.
(popsi_insn): Set addrtype.
From-SVN: r119090
2006-11-22 15:12:46 +01:00
|
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(define_insn_reservation "loadi" 1
|
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(and (not (eq_attr "seq_insns" "multi"))
|
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(and (eq_attr "type" "mcld") (eq_attr "addrtype" "ireg")))
|
2009-09-07 20:06:51 +02:00
|
|
|
|
"(slot1|slot2)+load")
|
predicates.md (d_register_operand, [...]): New predicates.
* config/bfin/predicates.md (d_register_operand, mem_p_address_operand,
mem_i_address_operand): New predicates.
* config/bfin/bfin.c (bfin_issue_rate): New function.
(TARGET_SCHED_ISSUE_RATE): New macro.
* config/bfin/bfin.md (addrtype): New attribute.
(slot0, slot1, slot2, store, pregs): New cpu_units.
(core): Now a define_reservation.
(alu): Remove some insn types from this reservation.
(dsp32, load32, loadp, loadi, store32, storep, storei, multi): New
insn reservations.
(dummy reservation): Don't trigger for mcld insns.
(absence_sets): Two new absence sets to enforce slot ordering.
(popsi_insn): Set addrtype.
From-SVN: r119090
2006-11-22 15:12:46 +01:00
|
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(define_insn_reservation "store32" 1
|
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(and (not (eq_attr "seq_insns" "multi"))
|
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(and (eq_attr "type" "mcst") (eq_attr "addrtype" "32bit")))
|
2005-04-05 13:26:48 +02:00
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"core")
|
|
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|
predicates.md (d_register_operand, [...]): New predicates.
* config/bfin/predicates.md (d_register_operand, mem_p_address_operand,
mem_i_address_operand): New predicates.
* config/bfin/bfin.c (bfin_issue_rate): New function.
(TARGET_SCHED_ISSUE_RATE): New macro.
* config/bfin/bfin.md (addrtype): New attribute.
(slot0, slot1, slot2, store, pregs): New cpu_units.
(core): Now a define_reservation.
(alu): Remove some insn types from this reservation.
(dsp32, load32, loadp, loadi, store32, storep, storei, multi): New
insn reservations.
(dummy reservation): Don't trigger for mcld insns.
(absence_sets): Two new absence sets to enforce slot ordering.
(popsi_insn): Set addrtype.
From-SVN: r119090
2006-11-22 15:12:46 +01:00
|
|
|
|
(define_insn_reservation "storep" 1
|
From Jie Zhang <jie.zhang@analog.com>:
* config/bfin/predicates.md (p_register_operand): New
predicate.
(dp_register_operand): New predicate.
* config/bfin/bfin-protos.h (WA_05000074): Define.
(ENABLE_WA_05000074): Define.
* config/bfin/bfin.c (bfin_cpus[]): Add WA_05000074 for
all cpus.
(bfin_gen_bundles): Put dsp32shiftimm instruction in slot[0].
* config/bfin/bfin.md (define_attr type): Add dsp32shiftimm.
(define_attr addrtype): Allow load/store register to be
P register.
(define_attr storereg): New.
(define_cpu_unit anomaly_05000074): New.
(define_insn_reservation dsp32shiftimm): New.
(define_insn_reservation dsp32shiftimm_anomaly_05000074): New.
(define_insn_reservation loadp): Cannot use slot2.
(define_insn_reservation loadsp): Cannot use slot2.
(define_insn_reservation storep): Cannot use slot2. Does not
apply when working around 05000074.
(define_insn_reservation storep_anomaly_05000074): New.
(define_insn_reservation storei): Does not apply when working
around 05000074.
(define_insn_reservation storei_anomaly_05000074): New.
(define_attr length): Add dsp32shiftimm case.
(define_insn movsi_insn32, movsi_insv, ashlsi3_insn, ashrsi3,
ror_one, rol_one, lshrsi3, lshrpdi3, ashrpdi3, movhiv2hi_low,
movhiv2hi_high, composev2hi, packv2hi, movv2hi_hi,
ssashiftv2hi3, ssashifthi3, ssashiftsi3, lshiftv2hi3, lshifthi3):
Set type as dsp32shiftimm for dsp32shiftimm alternatives.
From-SVN: r151490
2009-09-07 23:40:23 +02:00
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(and (and (not (eq_attr "seq_insns" "multi"))
|
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(and (eq_attr "type" "mcst")
|
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|
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(ior (eq_attr "addrtype" "preg")
|
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(eq_attr "addrtype" "spreg"))))
|
2011-09-14 23:15:09 +02:00
|
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|
(ior (not (match_test "ENABLE_WA_05000074"))
|
From Jie Zhang <jie.zhang@analog.com>:
* config/bfin/predicates.md (p_register_operand): New
predicate.
(dp_register_operand): New predicate.
* config/bfin/bfin-protos.h (WA_05000074): Define.
(ENABLE_WA_05000074): Define.
* config/bfin/bfin.c (bfin_cpus[]): Add WA_05000074 for
all cpus.
(bfin_gen_bundles): Put dsp32shiftimm instruction in slot[0].
* config/bfin/bfin.md (define_attr type): Add dsp32shiftimm.
(define_attr addrtype): Allow load/store register to be
P register.
(define_attr storereg): New.
(define_cpu_unit anomaly_05000074): New.
(define_insn_reservation dsp32shiftimm): New.
(define_insn_reservation dsp32shiftimm_anomaly_05000074): New.
(define_insn_reservation loadp): Cannot use slot2.
(define_insn_reservation loadsp): Cannot use slot2.
(define_insn_reservation storep): Cannot use slot2. Does not
apply when working around 05000074.
(define_insn_reservation storep_anomaly_05000074): New.
(define_insn_reservation storei): Does not apply when working
around 05000074.
(define_insn_reservation storei_anomaly_05000074): New.
(define_attr length): Add dsp32shiftimm case.
(define_insn movsi_insn32, movsi_insv, ashlsi3_insn, ashrsi3,
ror_one, rol_one, lshrsi3, lshrpdi3, ashrpdi3, movhiv2hi_low,
movhiv2hi_high, composev2hi, packv2hi, movv2hi_hi,
ssashiftv2hi3, ssashifthi3, ssashiftsi3, lshiftv2hi3, lshifthi3):
Set type as dsp32shiftimm for dsp32shiftimm alternatives.
From-SVN: r151490
2009-09-07 23:40:23 +02:00
|
|
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(eq_attr "storereg" "other")))
|
|
|
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"slot1+pregs+store")
|
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(define_insn_reservation "storep_anomaly_05000074" 1
|
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(and (and (not (eq_attr "seq_insns" "multi"))
|
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(and (eq_attr "type" "mcst")
|
|
|
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(ior (eq_attr "addrtype" "preg")
|
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(eq_attr "addrtype" "spreg"))))
|
2011-09-14 23:15:09 +02:00
|
|
|
|
(and (match_test "ENABLE_WA_05000074")
|
From Jie Zhang <jie.zhang@analog.com>:
* config/bfin/predicates.md (p_register_operand): New
predicate.
(dp_register_operand): New predicate.
* config/bfin/bfin-protos.h (WA_05000074): Define.
(ENABLE_WA_05000074): Define.
* config/bfin/bfin.c (bfin_cpus[]): Add WA_05000074 for
all cpus.
(bfin_gen_bundles): Put dsp32shiftimm instruction in slot[0].
* config/bfin/bfin.md (define_attr type): Add dsp32shiftimm.
(define_attr addrtype): Allow load/store register to be
P register.
(define_attr storereg): New.
(define_cpu_unit anomaly_05000074): New.
(define_insn_reservation dsp32shiftimm): New.
(define_insn_reservation dsp32shiftimm_anomaly_05000074): New.
(define_insn_reservation loadp): Cannot use slot2.
(define_insn_reservation loadsp): Cannot use slot2.
(define_insn_reservation storep): Cannot use slot2. Does not
apply when working around 05000074.
(define_insn_reservation storep_anomaly_05000074): New.
(define_insn_reservation storei): Does not apply when working
around 05000074.
(define_insn_reservation storei_anomaly_05000074): New.
(define_attr length): Add dsp32shiftimm case.
(define_insn movsi_insn32, movsi_insv, ashlsi3_insn, ashrsi3,
ror_one, rol_one, lshrsi3, lshrpdi3, ashrpdi3, movhiv2hi_low,
movhiv2hi_high, composev2hi, packv2hi, movv2hi_hi,
ssashiftv2hi3, ssashifthi3, ssashiftsi3, lshiftv2hi3, lshifthi3):
Set type as dsp32shiftimm for dsp32shiftimm alternatives.
From-SVN: r151490
2009-09-07 23:40:23 +02:00
|
|
|
|
(eq_attr "storereg" "preg")))
|
|
|
|
|
"slot1+anomaly_05000074+pregs+store")
|
predicates.md (d_register_operand, [...]): New predicates.
* config/bfin/predicates.md (d_register_operand, mem_p_address_operand,
mem_i_address_operand): New predicates.
* config/bfin/bfin.c (bfin_issue_rate): New function.
(TARGET_SCHED_ISSUE_RATE): New macro.
* config/bfin/bfin.md (addrtype): New attribute.
(slot0, slot1, slot2, store, pregs): New cpu_units.
(core): Now a define_reservation.
(alu): Remove some insn types from this reservation.
(dsp32, load32, loadp, loadi, store32, storep, storei, multi): New
insn reservations.
(dummy reservation): Don't trigger for mcld insns.
(absence_sets): Two new absence sets to enforce slot ordering.
(popsi_insn): Set addrtype.
From-SVN: r119090
2006-11-22 15:12:46 +01:00
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(define_insn_reservation "storei" 1
|
From Jie Zhang <jie.zhang@analog.com>:
* config/bfin/predicates.md (p_register_operand): New
predicate.
(dp_register_operand): New predicate.
* config/bfin/bfin-protos.h (WA_05000074): Define.
(ENABLE_WA_05000074): Define.
* config/bfin/bfin.c (bfin_cpus[]): Add WA_05000074 for
all cpus.
(bfin_gen_bundles): Put dsp32shiftimm instruction in slot[0].
* config/bfin/bfin.md (define_attr type): Add dsp32shiftimm.
(define_attr addrtype): Allow load/store register to be
P register.
(define_attr storereg): New.
(define_cpu_unit anomaly_05000074): New.
(define_insn_reservation dsp32shiftimm): New.
(define_insn_reservation dsp32shiftimm_anomaly_05000074): New.
(define_insn_reservation loadp): Cannot use slot2.
(define_insn_reservation loadsp): Cannot use slot2.
(define_insn_reservation storep): Cannot use slot2. Does not
apply when working around 05000074.
(define_insn_reservation storep_anomaly_05000074): New.
(define_insn_reservation storei): Does not apply when working
around 05000074.
(define_insn_reservation storei_anomaly_05000074): New.
(define_attr length): Add dsp32shiftimm case.
(define_insn movsi_insn32, movsi_insv, ashlsi3_insn, ashrsi3,
ror_one, rol_one, lshrsi3, lshrpdi3, ashrpdi3, movhiv2hi_low,
movhiv2hi_high, composev2hi, packv2hi, movv2hi_hi,
ssashiftv2hi3, ssashifthi3, ssashiftsi3, lshiftv2hi3, lshifthi3):
Set type as dsp32shiftimm for dsp32shiftimm alternatives.
From-SVN: r151490
2009-09-07 23:40:23 +02:00
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(and (and (not (eq_attr "seq_insns" "multi"))
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(and (eq_attr "type" "mcst") (eq_attr "addrtype" "ireg")))
|
2011-09-14 23:15:09 +02:00
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(ior (not (match_test "ENABLE_WA_05000074"))
|
From Jie Zhang <jie.zhang@analog.com>:
* config/bfin/predicates.md (p_register_operand): New
predicate.
(dp_register_operand): New predicate.
* config/bfin/bfin-protos.h (WA_05000074): Define.
(ENABLE_WA_05000074): Define.
* config/bfin/bfin.c (bfin_cpus[]): Add WA_05000074 for
all cpus.
(bfin_gen_bundles): Put dsp32shiftimm instruction in slot[0].
* config/bfin/bfin.md (define_attr type): Add dsp32shiftimm.
(define_attr addrtype): Allow load/store register to be
P register.
(define_attr storereg): New.
(define_cpu_unit anomaly_05000074): New.
(define_insn_reservation dsp32shiftimm): New.
(define_insn_reservation dsp32shiftimm_anomaly_05000074): New.
(define_insn_reservation loadp): Cannot use slot2.
(define_insn_reservation loadsp): Cannot use slot2.
(define_insn_reservation storep): Cannot use slot2. Does not
apply when working around 05000074.
(define_insn_reservation storep_anomaly_05000074): New.
(define_insn_reservation storei): Does not apply when working
around 05000074.
(define_insn_reservation storei_anomaly_05000074): New.
(define_attr length): Add dsp32shiftimm case.
(define_insn movsi_insn32, movsi_insv, ashlsi3_insn, ashrsi3,
ror_one, rol_one, lshrsi3, lshrpdi3, ashrpdi3, movhiv2hi_low,
movhiv2hi_high, composev2hi, packv2hi, movv2hi_hi,
ssashiftv2hi3, ssashifthi3, ssashiftsi3, lshiftv2hi3, lshifthi3):
Set type as dsp32shiftimm for dsp32shiftimm alternatives.
From-SVN: r151490
2009-09-07 23:40:23 +02:00
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(eq_attr "storereg" "other")))
|
predicates.md (d_register_operand, [...]): New predicates.
* config/bfin/predicates.md (d_register_operand, mem_p_address_operand,
mem_i_address_operand): New predicates.
* config/bfin/bfin.c (bfin_issue_rate): New function.
(TARGET_SCHED_ISSUE_RATE): New macro.
* config/bfin/bfin.md (addrtype): New attribute.
(slot0, slot1, slot2, store, pregs): New cpu_units.
(core): Now a define_reservation.
(alu): Remove some insn types from this reservation.
(dsp32, load32, loadp, loadi, store32, storep, storei, multi): New
insn reservations.
(dummy reservation): Don't trigger for mcld insns.
(absence_sets): Two new absence sets to enforce slot ordering.
(popsi_insn): Set addrtype.
From-SVN: r119090
2006-11-22 15:12:46 +01:00
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"(slot1|slot2)+store")
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|
From Jie Zhang <jie.zhang@analog.com>:
* config/bfin/predicates.md (p_register_operand): New
predicate.
(dp_register_operand): New predicate.
* config/bfin/bfin-protos.h (WA_05000074): Define.
(ENABLE_WA_05000074): Define.
* config/bfin/bfin.c (bfin_cpus[]): Add WA_05000074 for
all cpus.
(bfin_gen_bundles): Put dsp32shiftimm instruction in slot[0].
* config/bfin/bfin.md (define_attr type): Add dsp32shiftimm.
(define_attr addrtype): Allow load/store register to be
P register.
(define_attr storereg): New.
(define_cpu_unit anomaly_05000074): New.
(define_insn_reservation dsp32shiftimm): New.
(define_insn_reservation dsp32shiftimm_anomaly_05000074): New.
(define_insn_reservation loadp): Cannot use slot2.
(define_insn_reservation loadsp): Cannot use slot2.
(define_insn_reservation storep): Cannot use slot2. Does not
apply when working around 05000074.
(define_insn_reservation storep_anomaly_05000074): New.
(define_insn_reservation storei): Does not apply when working
around 05000074.
(define_insn_reservation storei_anomaly_05000074): New.
(define_attr length): Add dsp32shiftimm case.
(define_insn movsi_insn32, movsi_insv, ashlsi3_insn, ashrsi3,
ror_one, rol_one, lshrsi3, lshrpdi3, ashrpdi3, movhiv2hi_low,
movhiv2hi_high, composev2hi, packv2hi, movv2hi_hi,
ssashiftv2hi3, ssashifthi3, ssashiftsi3, lshiftv2hi3, lshifthi3):
Set type as dsp32shiftimm for dsp32shiftimm alternatives.
From-SVN: r151490
2009-09-07 23:40:23 +02:00
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(define_insn_reservation "storei_anomaly_05000074" 1
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(and (and (not (eq_attr "seq_insns" "multi"))
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(and (eq_attr "type" "mcst") (eq_attr "addrtype" "ireg")))
|
2011-09-14 23:15:09 +02:00
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(and (match_test "ENABLE_WA_05000074")
|
From Jie Zhang <jie.zhang@analog.com>:
* config/bfin/predicates.md (p_register_operand): New
predicate.
(dp_register_operand): New predicate.
* config/bfin/bfin-protos.h (WA_05000074): Define.
(ENABLE_WA_05000074): Define.
* config/bfin/bfin.c (bfin_cpus[]): Add WA_05000074 for
all cpus.
(bfin_gen_bundles): Put dsp32shiftimm instruction in slot[0].
* config/bfin/bfin.md (define_attr type): Add dsp32shiftimm.
(define_attr addrtype): Allow load/store register to be
P register.
(define_attr storereg): New.
(define_cpu_unit anomaly_05000074): New.
(define_insn_reservation dsp32shiftimm): New.
(define_insn_reservation dsp32shiftimm_anomaly_05000074): New.
(define_insn_reservation loadp): Cannot use slot2.
(define_insn_reservation loadsp): Cannot use slot2.
(define_insn_reservation storep): Cannot use slot2. Does not
apply when working around 05000074.
(define_insn_reservation storep_anomaly_05000074): New.
(define_insn_reservation storei): Does not apply when working
around 05000074.
(define_insn_reservation storei_anomaly_05000074): New.
(define_attr length): Add dsp32shiftimm case.
(define_insn movsi_insn32, movsi_insv, ashlsi3_insn, ashrsi3,
ror_one, rol_one, lshrsi3, lshrpdi3, ashrpdi3, movhiv2hi_low,
movhiv2hi_high, composev2hi, packv2hi, movv2hi_hi,
ssashiftv2hi3, ssashifthi3, ssashiftsi3, lshiftv2hi3, lshifthi3):
Set type as dsp32shiftimm for dsp32shiftimm alternatives.
From-SVN: r151490
2009-09-07 23:40:23 +02:00
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(eq_attr "storereg" "preg")))
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"((slot1+anomaly_05000074)|slot2)+store")
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predicates.md (d_register_operand, [...]): New predicates.
* config/bfin/predicates.md (d_register_operand, mem_p_address_operand,
mem_i_address_operand): New predicates.
* config/bfin/bfin.c (bfin_issue_rate): New function.
(TARGET_SCHED_ISSUE_RATE): New macro.
* config/bfin/bfin.md (addrtype): New attribute.
(slot0, slot1, slot2, store, pregs): New cpu_units.
(core): Now a define_reservation.
(alu): Remove some insn types from this reservation.
(dsp32, load32, loadp, loadi, store32, storep, storei, multi): New
insn reservations.
(dummy reservation): Don't trigger for mcld insns.
(absence_sets): Two new absence sets to enforce slot ordering.
(popsi_insn): Set addrtype.
From-SVN: r119090
2006-11-22 15:12:46 +01:00
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(define_insn_reservation "multi" 2
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(eq_attr "seq_insns" "multi")
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"core")
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2009-09-07 20:06:51 +02:00
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(define_insn_reservation "load_stall1" 1
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(and (eq_attr "type" "stall")
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(match_operand 0 "const1_operand" ""))
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"core+load*2")
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(define_insn_reservation "load_stall3" 1
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(and (eq_attr "type" "stall")
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(match_operand 0 "const3_operand" ""))
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"core+load*4")
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predicates.md (d_register_operand, [...]): New predicates.
* config/bfin/predicates.md (d_register_operand, mem_p_address_operand,
mem_i_address_operand): New predicates.
* config/bfin/bfin.c (bfin_issue_rate): New function.
(TARGET_SCHED_ISSUE_RATE): New macro.
* config/bfin/bfin.md (addrtype): New attribute.
(slot0, slot1, slot2, store, pregs): New cpu_units.
(core): Now a define_reservation.
(alu): Remove some insn types from this reservation.
(dsp32, load32, loadp, loadi, store32, storep, storei, multi): New
insn reservations.
(dummy reservation): Don't trigger for mcld insns.
(absence_sets): Two new absence sets to enforce slot ordering.
(popsi_insn): Set addrtype.
From-SVN: r119090
2006-11-22 15:12:46 +01:00
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(absence_set "slot0" "slot1,slot2")
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(absence_set "slot1" "slot2")
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2005-04-05 13:26:48 +02:00
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;; Make sure genautomata knows about the maximum latency that can be produced
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;; by the adjust_cost function.
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(define_insn_reservation "dummy" 5
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predicates.md (d_register_operand, [...]): New predicates.
* config/bfin/predicates.md (d_register_operand, mem_p_address_operand,
mem_i_address_operand): New predicates.
* config/bfin/bfin.c (bfin_issue_rate): New function.
(TARGET_SCHED_ISSUE_RATE): New macro.
* config/bfin/bfin.md (addrtype): New attribute.
(slot0, slot1, slot2, store, pregs): New cpu_units.
(core): Now a define_reservation.
(alu): Remove some insn types from this reservation.
(dsp32, load32, loadp, loadi, store32, storep, storei, multi): New
insn reservations.
(dummy reservation): Don't trigger for mcld insns.
(absence_sets): Two new absence sets to enforce slot ordering.
(popsi_insn): Set addrtype.
From-SVN: r119090
2006-11-22 15:12:46 +01:00
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(eq_attr "type" "dummy")
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2005-04-05 13:26:48 +02:00
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"core")
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;; Operand and operator predicates
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(include "predicates.md")
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constraints.md: New file.
* config/bfin/constraints.md: New file.
* config/bfin/bfin.md: Include it.
(adddi3): Use satisfies_constraint functions instead of the old macros.
* config/bfin/bfin.h (REG_CLASS_FROM_LETTER, CONSTRAINT_LEN,
CONST_18UBIT_IMM_P, CONST_16BIT_IMM_P, CONST_16UBIT_IMM_P,
CONST_7BIT_IMM_P, CONST_7NBIT_IMM_P, CONST_5UBIT_IMM_P,
CONST_4BIT_IMM_P, CONST_4UBIT_IMM_P, CONST_3BIT_IMM_P,
CONST_3UBIT_IMM_P, CONST_OK_FOR_K, CONST_OK_FOR_P, CONST_OK_FOR_M,
CONST_OK_FOR_CONSTRAINT_P, CONST_DOUBLE_OK_FOR_LETTER,
EXTRA_CONSTRAINT): Delete.
* config/bfin/predicates.md (highbits_operand, reg_or_7bit_operand,
reg_or_neg7bit_operand): Use satisfies_constraint functions instead
of the old macros.
* config/bfin/bfin.c: Include "tm-constrs.h".
(bfin_secondary_reload, split_load_immediate, bfin_rtx_costs):
Use satisfies_constraint functions instead of the old macros.
* doc/md.texi (Blackfin Constraints): Update file name reference.
From-SVN: r134198
2008-04-11 16:40:55 +02:00
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(include "constraints.md")
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2005-04-05 13:26:48 +02:00
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;;; FRIO branches have been optimized for code density
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;;; this comes at a slight cost of complexity when
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;;; a compiler needs to generate branches in the general
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;;; case. In order to generate the correct branching
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;;; mechanisms the compiler needs keep track of instruction
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;;; lengths. The follow table describes how to count instructions
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;;; for the FRIO architecture.
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;;;
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;;; unconditional br are 12-bit imm pcrelative branches *2
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;;; conditional br are 10-bit imm pcrelative branches *2
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;;; brcc 10-bit:
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;;; 1024 10-bit imm *2 is 2048 (-1024..1022)
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;;; br 12-bit :
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;;; 4096 12-bit imm *2 is 8192 (-4096..4094)
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;;; NOTE : For brcc we generate instructions such as
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;;; if cc jmp; jump.[sl] offset
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;;; offset of jump.[sl] is from the jump instruction but
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;;; gcc calculates length from the if cc jmp instruction
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2005-05-19 10:42:26 +02:00
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;;; furthermore gcc takes the end address of the branch instruction
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;;; as (pc) for a forward branch
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;;; hence our range is (-4094, 4092) instead of (-4096, 4094) for a br
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2005-04-05 13:26:48 +02:00
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;;;
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;;; The way the (pc) rtx works in these calculations is somewhat odd;
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;;; for backward branches it's the address of the current instruction,
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;;; for forward branches it's the previously known address of the following
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;;; instruction - we have to take this into account by reducing the range
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;;; for a forward branch.
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;; Lengths for type "mvi" insns are always defined by the instructions
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;; themselves.
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(define_attr "length" ""
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(cond [(eq_attr "type" "mcld")
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(if_then_else (match_operand 1 "effective_address_32bit_p" "")
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(const_int 4) (const_int 2))
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(eq_attr "type" "mcst")
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(if_then_else (match_operand 0 "effective_address_32bit_p" "")
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(const_int 4) (const_int 2))
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(eq_attr "type" "move") (const_int 2)
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(eq_attr "type" "dsp32") (const_int 4)
|
From Jie Zhang <jie.zhang@analog.com>:
* config/bfin/predicates.md (p_register_operand): New
predicate.
(dp_register_operand): New predicate.
* config/bfin/bfin-protos.h (WA_05000074): Define.
(ENABLE_WA_05000074): Define.
* config/bfin/bfin.c (bfin_cpus[]): Add WA_05000074 for
all cpus.
(bfin_gen_bundles): Put dsp32shiftimm instruction in slot[0].
* config/bfin/bfin.md (define_attr type): Add dsp32shiftimm.
(define_attr addrtype): Allow load/store register to be
P register.
(define_attr storereg): New.
(define_cpu_unit anomaly_05000074): New.
(define_insn_reservation dsp32shiftimm): New.
(define_insn_reservation dsp32shiftimm_anomaly_05000074): New.
(define_insn_reservation loadp): Cannot use slot2.
(define_insn_reservation loadsp): Cannot use slot2.
(define_insn_reservation storep): Cannot use slot2. Does not
apply when working around 05000074.
(define_insn_reservation storep_anomaly_05000074): New.
(define_insn_reservation storei): Does not apply when working
around 05000074.
(define_insn_reservation storei_anomaly_05000074): New.
(define_attr length): Add dsp32shiftimm case.
(define_insn movsi_insn32, movsi_insv, ashlsi3_insn, ashrsi3,
ror_one, rol_one, lshrsi3, lshrpdi3, ashrpdi3, movhiv2hi_low,
movhiv2hi_high, composev2hi, packv2hi, movv2hi_hi,
ssashiftv2hi3, ssashifthi3, ssashiftsi3, lshiftv2hi3, lshifthi3):
Set type as dsp32shiftimm for dsp32shiftimm alternatives.
From-SVN: r151490
2009-09-07 23:40:23 +02:00
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(eq_attr "type" "dsp32shiftimm") (const_int 4)
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2005-04-05 13:26:48 +02:00
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(eq_attr "type" "call") (const_int 4)
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(eq_attr "type" "br")
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(if_then_else (and
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(le (minus (match_dup 0) (pc)) (const_int 4092))
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(ge (minus (match_dup 0) (pc)) (const_int -4096)))
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(const_int 2)
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(const_int 4))
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(eq_attr "type" "brcc")
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(cond [(and
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(le (minus (match_dup 3) (pc)) (const_int 1020))
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(ge (minus (match_dup 3) (pc)) (const_int -1024)))
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(const_int 2)
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(and
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2005-05-19 10:42:26 +02:00
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(le (minus (match_dup 3) (pc)) (const_int 4092))
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2005-04-05 13:26:48 +02:00
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(ge (minus (match_dup 3) (pc)) (const_int -4094)))
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(const_int 4)]
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(const_int 6))
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]
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(const_int 2)))
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bfin-protos.h (bfin_hardware_loop): Declare.
* config/bfin/bfin-protos.h (bfin_hardware_loop): Declare.
* config/bfin/bfin.c (basic-block.h): Include.
(struct machine_function): New.
(bfin_init_machine_status): New.
(override_options): Initialize init_machine_status.
(bfin_hardware_loop): New.
(MAX_LOOP_DEPTH, MAX_LOOP_LENGTH): Define.
(DEF_VEC_P (loop_info)): New.
(DEF_VEC_ALLOC_P (loop_info,heap)): New.
(struct loop_info): New.
(loop_info): New typedef.
(struct loop_work): New.
(loop_work): New typedef.
(DEF_VEC_O (loop_work)): New.
(DEF_VEC_ALLOC_O (loop_work,heap)): New.
(bfin_dump_loops): New.
(bfin_bb_in_loop): New.
(bfin_scan_loop): New.
(bfin_optimize_loop): New.
(bfin_reorg_loops): New.
(bfin_reorg): Use bfin_reorg_loops.
* config/bfin/bfin.h (FIRST_PSEUDO_REGISTER): Adjust for adding
loop registers.
(I_REGNO_P): Simplify.
(DP_REGNO_P, DPREG_P): New macros.
(REGISTER_NAMES, FIXED_REGISTERS, CALL_USED_REGISTERS,
REG_ALLOC_ORDER): Add LT0, LT1, LC0, LC1, LB0, LB1.
(enum reg_class, REG_CLASS_NAMES, REG_CLASS_CONTENTS):
Add LT_REGS, LC_REGS, LB_REGS.
(REG_CLASS_FROM_LETTER): Add 't' for LT_REGS, 'k' for LC_REGS,
'l' for LB_REGS.
(REGNO_REG_CLASS): Deal with loop registers.
* config/bfin/bfin.md: Add comment for 't', 'k', 'l' constraint
letters.
(REG_LT0, REG_LT1, REG_LC0, REG_LC1, REG_LB0, REG_LB1):
New constants for loop registers.
(UNSPEC_LSETUP_END): New.
(seq_insns): New define_attr. Set it for appropriate insns.
(movsi_insn): Add alternatives for move from/to
loop count registers.
(doloop_end): New define_expand.
(loop_end): New define_insn.
(define_split for bad doloop_end): New.
(lsetup_with_autoinit): New define_insn.
(lsetup_without_autoinit): New define_insn.
(rep_movsi, rep_movhi): Clobber LT1, LC1, LB1.
* config/bfin/predicates.md (lc_register_operand): New.
(lt_register_operand): New.
(lb_register_operand): New.
(nondp_register_operand): New.
(nondp_reg_or_memory_operand): New.
* doc/md.texi: Document Blackfin new 't', 'k', 'l' constraint letters.
From-SVN: r114274
2006-05-31 18:46:15 +02:00
|
|
|
|
;; Classify the insns into those that are one instruction and those that
|
|
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|
|
;; are more than one in sequence.
|
|
|
|
|
(define_attr "seq_insns" "single,multi"
|
|
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|
(const_string "single"))
|
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|
2007-09-19 17:13:18 +02:00
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|
;; Describe a user's asm statement.
|
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|
(define_asm_attributes
|
|
|
|
|
[(set_attr "type" "misc")
|
|
|
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(set_attr "seq_insns" "multi")
|
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(set_attr "length" "4")])
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|
2005-04-05 13:26:48 +02:00
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;; Conditional moves
|
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|
2011-05-03 18:50:30 +02:00
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(define_mode_iterator CCMOV [QI HI SI])
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(define_expand "mov<mode>cc"
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[(set (match_operand:CCMOV 0 "register_operand" "")
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(if_then_else:CCMOV (match_operand 1 "comparison_operator" "")
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(match_operand:CCMOV 2 "register_operand" "")
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|
(match_operand:CCMOV 3 "register_operand" "")))]
|
2005-04-05 13:26:48 +02:00
|
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|
""
|
|
|
|
|
{
|
2011-05-03 18:50:30 +02:00
|
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|
operands[1] = bfin_gen_compare (operands[1], <MODE>mode);
|
2005-04-05 13:26:48 +02:00
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|
|
})
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|
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|
|
2011-05-03 18:50:30 +02:00
|
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|
|
(define_insn "*mov<mode>cc_insn1"
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[(set (match_operand:CCMOV 0 "register_operand" "=da,da,da")
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(if_then_else:CCMOV
|
2006-02-21 16:32:21 +01:00
|
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|
|
(eq:BI (match_operand:BI 3 "register_operand" "C,C,C")
|
2005-04-05 13:26:48 +02:00
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(const_int 0))
|
2011-05-03 18:50:30 +02:00
|
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(match_operand:CCMOV 1 "register_operand" "da,0,da")
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(match_operand:CCMOV 2 "register_operand" "0,da,da")))]
|
2005-04-05 13:26:48 +02:00
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|
""
|
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|
"@
|
2011-05-03 18:50:30 +02:00
|
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|
|
if !cc %0 = %1;
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|
|
if cc %0 = %2;
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if !cc %0 = %1; if cc %0 = %2;"
|
2005-04-05 13:26:48 +02:00
|
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|
|
[(set_attr "length" "2,2,4")
|
2006-12-08 13:42:44 +01:00
|
|
|
|
(set_attr "type" "movcc")
|
bfin-protos.h (bfin_hardware_loop): Declare.
* config/bfin/bfin-protos.h (bfin_hardware_loop): Declare.
* config/bfin/bfin.c (basic-block.h): Include.
(struct machine_function): New.
(bfin_init_machine_status): New.
(override_options): Initialize init_machine_status.
(bfin_hardware_loop): New.
(MAX_LOOP_DEPTH, MAX_LOOP_LENGTH): Define.
(DEF_VEC_P (loop_info)): New.
(DEF_VEC_ALLOC_P (loop_info,heap)): New.
(struct loop_info): New.
(loop_info): New typedef.
(struct loop_work): New.
(loop_work): New typedef.
(DEF_VEC_O (loop_work)): New.
(DEF_VEC_ALLOC_O (loop_work,heap)): New.
(bfin_dump_loops): New.
(bfin_bb_in_loop): New.
(bfin_scan_loop): New.
(bfin_optimize_loop): New.
(bfin_reorg_loops): New.
(bfin_reorg): Use bfin_reorg_loops.
* config/bfin/bfin.h (FIRST_PSEUDO_REGISTER): Adjust for adding
loop registers.
(I_REGNO_P): Simplify.
(DP_REGNO_P, DPREG_P): New macros.
(REGISTER_NAMES, FIXED_REGISTERS, CALL_USED_REGISTERS,
REG_ALLOC_ORDER): Add LT0, LT1, LC0, LC1, LB0, LB1.
(enum reg_class, REG_CLASS_NAMES, REG_CLASS_CONTENTS):
Add LT_REGS, LC_REGS, LB_REGS.
(REG_CLASS_FROM_LETTER): Add 't' for LT_REGS, 'k' for LC_REGS,
'l' for LB_REGS.
(REGNO_REG_CLASS): Deal with loop registers.
* config/bfin/bfin.md: Add comment for 't', 'k', 'l' constraint
letters.
(REG_LT0, REG_LT1, REG_LC0, REG_LC1, REG_LB0, REG_LB1):
New constants for loop registers.
(UNSPEC_LSETUP_END): New.
(seq_insns): New define_attr. Set it for appropriate insns.
(movsi_insn): Add alternatives for move from/to
loop count registers.
(doloop_end): New define_expand.
(loop_end): New define_insn.
(define_split for bad doloop_end): New.
(lsetup_with_autoinit): New define_insn.
(lsetup_without_autoinit): New define_insn.
(rep_movsi, rep_movhi): Clobber LT1, LC1, LB1.
* config/bfin/predicates.md (lc_register_operand): New.
(lt_register_operand): New.
(lb_register_operand): New.
(nondp_register_operand): New.
(nondp_reg_or_memory_operand): New.
* doc/md.texi: Document Blackfin new 't', 'k', 'l' constraint letters.
From-SVN: r114274
2006-05-31 18:46:15 +02:00
|
|
|
|
(set_attr "seq_insns" "*,*,multi")])
|
2005-04-05 13:26:48 +02:00
|
|
|
|
|
2011-05-03 18:50:30 +02:00
|
|
|
|
(define_insn "*mov<mode>cc_insn2"
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|
|
|
|
[(set (match_operand:CCMOV 0 "register_operand" "=da,da,da")
|
|
|
|
|
(if_then_else:CCMOV
|
2006-02-21 16:32:21 +01:00
|
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|
|
(ne:BI (match_operand:BI 3 "register_operand" "C,C,C")
|
2005-04-05 13:26:48 +02:00
|
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|
|
(const_int 0))
|
2011-05-03 18:50:30 +02:00
|
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|
|
(match_operand:CCMOV 1 "register_operand" "0,da,da")
|
|
|
|
|
(match_operand:CCMOV 2 "register_operand" "da,0,da")))]
|
2005-04-05 13:26:48 +02:00
|
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|
|
""
|
|
|
|
|
"@
|
2011-05-03 18:50:30 +02:00
|
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|
|
if !cc %0 = %2;
|
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|
|
|
if cc %0 = %1;
|
|
|
|
|
if cc %0 = %1; if !cc %0 = %2;"
|
2005-04-05 13:26:48 +02:00
|
|
|
|
[(set_attr "length" "2,2,4")
|
2006-12-08 13:42:44 +01:00
|
|
|
|
(set_attr "type" "movcc")
|
bfin-protos.h (bfin_hardware_loop): Declare.
* config/bfin/bfin-protos.h (bfin_hardware_loop): Declare.
* config/bfin/bfin.c (basic-block.h): Include.
(struct machine_function): New.
(bfin_init_machine_status): New.
(override_options): Initialize init_machine_status.
(bfin_hardware_loop): New.
(MAX_LOOP_DEPTH, MAX_LOOP_LENGTH): Define.
(DEF_VEC_P (loop_info)): New.
(DEF_VEC_ALLOC_P (loop_info,heap)): New.
(struct loop_info): New.
(loop_info): New typedef.
(struct loop_work): New.
(loop_work): New typedef.
(DEF_VEC_O (loop_work)): New.
(DEF_VEC_ALLOC_O (loop_work,heap)): New.
(bfin_dump_loops): New.
(bfin_bb_in_loop): New.
(bfin_scan_loop): New.
(bfin_optimize_loop): New.
(bfin_reorg_loops): New.
(bfin_reorg): Use bfin_reorg_loops.
* config/bfin/bfin.h (FIRST_PSEUDO_REGISTER): Adjust for adding
loop registers.
(I_REGNO_P): Simplify.
(DP_REGNO_P, DPREG_P): New macros.
(REGISTER_NAMES, FIXED_REGISTERS, CALL_USED_REGISTERS,
REG_ALLOC_ORDER): Add LT0, LT1, LC0, LC1, LB0, LB1.
(enum reg_class, REG_CLASS_NAMES, REG_CLASS_CONTENTS):
Add LT_REGS, LC_REGS, LB_REGS.
(REG_CLASS_FROM_LETTER): Add 't' for LT_REGS, 'k' for LC_REGS,
'l' for LB_REGS.
(REGNO_REG_CLASS): Deal with loop registers.
* config/bfin/bfin.md: Add comment for 't', 'k', 'l' constraint
letters.
(REG_LT0, REG_LT1, REG_LC0, REG_LC1, REG_LB0, REG_LB1):
New constants for loop registers.
(UNSPEC_LSETUP_END): New.
(seq_insns): New define_attr. Set it for appropriate insns.
(movsi_insn): Add alternatives for move from/to
loop count registers.
(doloop_end): New define_expand.
(loop_end): New define_insn.
(define_split for bad doloop_end): New.
(lsetup_with_autoinit): New define_insn.
(lsetup_without_autoinit): New define_insn.
(rep_movsi, rep_movhi): Clobber LT1, LC1, LB1.
* config/bfin/predicates.md (lc_register_operand): New.
(lt_register_operand): New.
(lb_register_operand): New.
(nondp_register_operand): New.
(nondp_reg_or_memory_operand): New.
* doc/md.texi: Document Blackfin new 't', 'k', 'l' constraint letters.
From-SVN: r114274
2006-05-31 18:46:15 +02:00
|
|
|
|
(set_attr "seq_insns" "*,*,multi")])
|
2005-04-05 13:26:48 +02:00
|
|
|
|
|
|
|
|
|
;; Insns to load HIGH and LO_SUM
|
|
|
|
|
|
|
|
|
|
(define_insn "movsi_high"
|
|
|
|
|
[(set (match_operand:SI 0 "register_operand" "=x")
|
|
|
|
|
(high:SI (match_operand:SI 1 "immediate_operand" "i")))]
|
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|
"reload_completed"
|
|
|
|
|
"%d0 = %d1;"
|
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|
|
|
[(set_attr "type" "mvi")
|
|
|
|
|
(set_attr "length" "4")])
|
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|
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|
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|
|
(define_insn "movstricthi_high"
|
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|
|
[(set (match_operand:SI 0 "register_operand" "+x")
|
|
|
|
|
(ior:SI (and:SI (match_dup 0) (const_int 65535))
|
|
|
|
|
(match_operand:SI 1 "immediate_operand" "i")))]
|
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|
|
|
"reload_completed"
|
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|
|
|
"%d0 = %d1;"
|
|
|
|
|
[(set_attr "type" "mvi")
|
|
|
|
|
(set_attr "length" "4")])
|
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|
|
|
|
|
|
|
|
(define_insn "movsi_low"
|
|
|
|
|
[(set (match_operand:SI 0 "register_operand" "=x")
|
|
|
|
|
(lo_sum:SI (match_operand:SI 1 "register_operand" "0")
|
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|
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|
(match_operand:SI 2 "immediate_operand" "i")))]
|
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|
|
"reload_completed"
|
|
|
|
|
"%h0 = %h2;"
|
|
|
|
|
[(set_attr "type" "mvi")
|
|
|
|
|
(set_attr "length" "4")])
|
|
|
|
|
|
|
|
|
|
(define_insn "movsi_high_pic"
|
|
|
|
|
[(set (match_operand:SI 0 "register_operand" "=x")
|
|
|
|
|
(high:SI (unspec:SI [(match_operand:SI 1 "" "")]
|
|
|
|
|
UNSPEC_MOVE_PIC)))]
|
|
|
|
|
""
|
|
|
|
|
"%d0 = %1@GOT_LOW;"
|
|
|
|
|
[(set_attr "type" "mvi")
|
|
|
|
|
(set_attr "length" "4")])
|
|
|
|
|
|
|
|
|
|
(define_insn "movsi_low_pic"
|
|
|
|
|
[(set (match_operand:SI 0 "register_operand" "=x")
|
|
|
|
|
(lo_sum:SI (match_operand:SI 1 "register_operand" "0")
|
|
|
|
|
(unspec:SI [(match_operand:SI 2 "" "")]
|
|
|
|
|
UNSPEC_MOVE_PIC)))]
|
|
|
|
|
""
|
|
|
|
|
"%h0 = %h2@GOT_HIGH;"
|
|
|
|
|
[(set_attr "type" "mvi")
|
|
|
|
|
(set_attr "length" "4")])
|
|
|
|
|
|
|
|
|
|
;;; Move instructions
|
|
|
|
|
|
|
|
|
|
(define_insn_and_split "movdi_insn"
|
|
|
|
|
[(set (match_operand:DI 0 "nonimmediate_operand" "=x,mx,r")
|
|
|
|
|
(match_operand:DI 1 "general_operand" "iFx,r,mx"))]
|
2007-06-11 13:29:00 +02:00
|
|
|
|
"GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) == REG"
|
2005-04-05 13:26:48 +02:00
|
|
|
|
"#"
|
|
|
|
|
"reload_completed"
|
|
|
|
|
[(set (match_dup 2) (match_dup 3))
|
|
|
|
|
(set (match_dup 4) (match_dup 5))]
|
|
|
|
|
{
|
|
|
|
|
rtx lo_half[2], hi_half[2];
|
|
|
|
|
split_di (operands, 2, lo_half, hi_half);
|
|
|
|
|
|
|
|
|
|
if (reg_overlap_mentioned_p (lo_half[0], hi_half[1]))
|
|
|
|
|
{
|
|
|
|
|
operands[2] = hi_half[0];
|
|
|
|
|
operands[3] = hi_half[1];
|
|
|
|
|
operands[4] = lo_half[0];
|
|
|
|
|
operands[5] = lo_half[1];
|
|
|
|
|
}
|
|
|
|
|
else
|
|
|
|
|
{
|
|
|
|
|
operands[2] = lo_half[0];
|
|
|
|
|
operands[3] = lo_half[1];
|
|
|
|
|
operands[4] = hi_half[0];
|
|
|
|
|
operands[5] = hi_half[1];
|
|
|
|
|
}
|
|
|
|
|
})
|
|
|
|
|
|
|
|
|
|
(define_insn "movbi"
|
2008-10-29 17:37:22 +01:00
|
|
|
|
[(set (match_operand:BI 0 "nonimmediate_operand" "=x,x,d,md,C,d,C,P1")
|
|
|
|
|
(match_operand:BI 1 "general_operand" "x,xKs3,md,d,d,C,P0,P1"))]
|
2005-04-05 13:26:48 +02:00
|
|
|
|
|
|
|
|
|
""
|
|
|
|
|
"@
|
|
|
|
|
%0 = %1;
|
|
|
|
|
%0 = %1 (X);
|
rtlanal.c (note_uses): Deal with SEQUENCEs.
* rtlanal.c (note_uses): Deal with SEQUENCEs.
* config/bfin/bfin.c: Include "timevar.h".
(bfin_flag_schedule_insns2, splitting_for_sched,
bfin_flag_var_tracking): New variables.
(print_operand): Handle '%!'.
(override_options): Disable normal sched2 pass, instead set
bfin_flag_schedule_insns2 for reorg to handle it.
(output_file_start): Likewise for var-tracking.
(bfin_optimize_loop): Take some care not to stumble over SEQUENCEs.
(gen_one_bundle, bfin_gen_bundles, type_for_anomaly, trapping_loads_p):
New functions.
(bfin_reorg): Do second scheduling pass here, and call
bfin_gen_bundles. Use type_for_anomaly and trapping_loads_p instead
of examining insns directly. If bfin_flag_var_tracking, call
var-tracking pass when done with everything else.
* config/bfin/bfin.h (PRINT_OPERAND_PUNCT_VALID_P): '!' is valid.
* config/bfin/bfin.md (UNSPEC_32BIT): New constant.
(movsi_insn32): New pattern, with two new splits to create it
before the final scheduling pass.
(neghi2): Not a dsp32 insn, rather alu0.
(movbi, pushsi_insn, popsi_insn, movsi_insn, movv2hi_insn, movhi_insn,
movqi_insn, movsf_insn, movsi_insv, extendhisi2, zero_extendhisi2,
extendqihi2, extendqisi2, zero_extendqihi2, zero_extendqisi2,
mulhisi3, umulhisi3, ssadsi3, sssubsi3, smaxsi3, sminsi3, abssi2,
ssnegsi2, signbitssi2, smaxhi3, sminhi3, abshi2, ssneghi2, signbitshi2,
movhi_low2high, movhi_high2high, movhi_low2low, movhi_high2low,
movhiv2hi_low, movhiv2hi_high, composev2hi, packv2hi, movv2hi_hi,
ssaddhi3, sssubhi3, addv2hi3, ssaddv2hi3, subv2hi3, sssubv2hi3,
addsubv2hi3, subaddv2hi3, ssaddsubv2hi3, sssubaddv2hi3, sublohiv2hi3,
subhilov2hi3, sssublohiv2hi3, sssubhilov2hi3, addlohiv2hi3,
addhilov2hi3, ssaddlohiv2hi3, ssaddhilov2hi3, sminv2hi3, smaxv2hi3,
flag_mulhi, flag_mulhisi, flag_mulhisi_parts, flag_machi,
flag_machi_acconly, flag_macinithi, flag_macinit1hi, mulv2hi3,
flag_mulv2hi, flag_mulv2hi_parts, flag_macv2hi_parts,
flag_macv2hi_parts_acconly, flag_macinitv2hi_parts,
flag_macinit1v2hi_parts, mulhisi_ll, mulhisi_lh, mulhisi_hl,
mulhisi_hh, ssnegv2hi2, absv2hi2, ssashiftv2hi3, ssashifthi3,
lshiftv2hi3, lshifthi3): Use '%!' to terminate all dsp32/load/store
variants instead of ';'.
(ror_one, rol_one): Likewise. Make them dsp32 insns.
(ashlsi3_insn, ashrsi3, lshrsi3): Add dsp32 variants.
(align8, align16, align24): Now named patterns; also using '%!'.
(mnop): New insn.
From-SVN: r119534
2006-12-05 09:49:56 +01:00
|
|
|
|
%0 = B %1 (Z)%!
|
2006-02-21 16:32:21 +01:00
|
|
|
|
B %0 = %1;
|
2005-04-05 13:26:48 +02:00
|
|
|
|
CC = %1;
|
bfin.md (ror_one, [...]): New patterns.
* config/bfin/bfin.md (ror_one, rol_one, ashrdi3, ashldi3, lshrdi3):
New patterns.
(movbi): Add alternative to set CC to zero.
(compare_eq, compare_ne, compare_le, compare_lt, compare_leu,
compare_ltu): Now named patterns.
From-SVN: r101320
2005-06-25 13:52:32 +02:00
|
|
|
|
%0 = CC;
|
2008-10-29 17:37:22 +01:00
|
|
|
|
CC = R0 < R0;
|
|
|
|
|
CC = R0 == R0;"
|
|
|
|
|
[(set_attr "type" "move,mvi,mcld,mcst,compare,compare,compare,compare")
|
|
|
|
|
(set_attr "length" "2,2,*,*,2,2,2,2")
|
|
|
|
|
(set_attr "seq_insns" "*,*,*,*,*,*,*,*")])
|
2005-04-05 13:26:48 +02:00
|
|
|
|
|
|
|
|
|
(define_insn "movpdi"
|
|
|
|
|
[(set (match_operand:PDI 0 "nonimmediate_operand" "=e,<,e")
|
|
|
|
|
(match_operand:PDI 1 "general_operand" " e,e,>"))]
|
|
|
|
|
""
|
|
|
|
|
"@
|
|
|
|
|
%0 = %1;
|
|
|
|
|
%0 = %x1; %0 = %w1;
|
|
|
|
|
%w0 = %1; %x0 = %1;"
|
bfin-protos.h (bfin_hardware_loop): Declare.
* config/bfin/bfin-protos.h (bfin_hardware_loop): Declare.
* config/bfin/bfin.c (basic-block.h): Include.
(struct machine_function): New.
(bfin_init_machine_status): New.
(override_options): Initialize init_machine_status.
(bfin_hardware_loop): New.
(MAX_LOOP_DEPTH, MAX_LOOP_LENGTH): Define.
(DEF_VEC_P (loop_info)): New.
(DEF_VEC_ALLOC_P (loop_info,heap)): New.
(struct loop_info): New.
(loop_info): New typedef.
(struct loop_work): New.
(loop_work): New typedef.
(DEF_VEC_O (loop_work)): New.
(DEF_VEC_ALLOC_O (loop_work,heap)): New.
(bfin_dump_loops): New.
(bfin_bb_in_loop): New.
(bfin_scan_loop): New.
(bfin_optimize_loop): New.
(bfin_reorg_loops): New.
(bfin_reorg): Use bfin_reorg_loops.
* config/bfin/bfin.h (FIRST_PSEUDO_REGISTER): Adjust for adding
loop registers.
(I_REGNO_P): Simplify.
(DP_REGNO_P, DPREG_P): New macros.
(REGISTER_NAMES, FIXED_REGISTERS, CALL_USED_REGISTERS,
REG_ALLOC_ORDER): Add LT0, LT1, LC0, LC1, LB0, LB1.
(enum reg_class, REG_CLASS_NAMES, REG_CLASS_CONTENTS):
Add LT_REGS, LC_REGS, LB_REGS.
(REG_CLASS_FROM_LETTER): Add 't' for LT_REGS, 'k' for LC_REGS,
'l' for LB_REGS.
(REGNO_REG_CLASS): Deal with loop registers.
* config/bfin/bfin.md: Add comment for 't', 'k', 'l' constraint
letters.
(REG_LT0, REG_LT1, REG_LC0, REG_LC1, REG_LB0, REG_LB1):
New constants for loop registers.
(UNSPEC_LSETUP_END): New.
(seq_insns): New define_attr. Set it for appropriate insns.
(movsi_insn): Add alternatives for move from/to
loop count registers.
(doloop_end): New define_expand.
(loop_end): New define_insn.
(define_split for bad doloop_end): New.
(lsetup_with_autoinit): New define_insn.
(lsetup_without_autoinit): New define_insn.
(rep_movsi, rep_movhi): Clobber LT1, LC1, LB1.
* config/bfin/predicates.md (lc_register_operand): New.
(lt_register_operand): New.
(lb_register_operand): New.
(nondp_register_operand): New.
(nondp_reg_or_memory_operand): New.
* doc/md.texi: Document Blackfin new 't', 'k', 'l' constraint letters.
From-SVN: r114274
2006-05-31 18:46:15 +02:00
|
|
|
|
[(set_attr "type" "move,mcst,mcld")
|
2019-03-24 20:25:49 +01:00
|
|
|
|
(set_attr "length" "4,*,*")
|
bfin-protos.h (bfin_hardware_loop): Declare.
* config/bfin/bfin-protos.h (bfin_hardware_loop): Declare.
* config/bfin/bfin.c (basic-block.h): Include.
(struct machine_function): New.
(bfin_init_machine_status): New.
(override_options): Initialize init_machine_status.
(bfin_hardware_loop): New.
(MAX_LOOP_DEPTH, MAX_LOOP_LENGTH): Define.
(DEF_VEC_P (loop_info)): New.
(DEF_VEC_ALLOC_P (loop_info,heap)): New.
(struct loop_info): New.
(loop_info): New typedef.
(struct loop_work): New.
(loop_work): New typedef.
(DEF_VEC_O (loop_work)): New.
(DEF_VEC_ALLOC_O (loop_work,heap)): New.
(bfin_dump_loops): New.
(bfin_bb_in_loop): New.
(bfin_scan_loop): New.
(bfin_optimize_loop): New.
(bfin_reorg_loops): New.
(bfin_reorg): Use bfin_reorg_loops.
* config/bfin/bfin.h (FIRST_PSEUDO_REGISTER): Adjust for adding
loop registers.
(I_REGNO_P): Simplify.
(DP_REGNO_P, DPREG_P): New macros.
(REGISTER_NAMES, FIXED_REGISTERS, CALL_USED_REGISTERS,
REG_ALLOC_ORDER): Add LT0, LT1, LC0, LC1, LB0, LB1.
(enum reg_class, REG_CLASS_NAMES, REG_CLASS_CONTENTS):
Add LT_REGS, LC_REGS, LB_REGS.
(REG_CLASS_FROM_LETTER): Add 't' for LT_REGS, 'k' for LC_REGS,
'l' for LB_REGS.
(REGNO_REG_CLASS): Deal with loop registers.
* config/bfin/bfin.md: Add comment for 't', 'k', 'l' constraint
letters.
(REG_LT0, REG_LT1, REG_LC0, REG_LC1, REG_LB0, REG_LB1):
New constants for loop registers.
(UNSPEC_LSETUP_END): New.
(seq_insns): New define_attr. Set it for appropriate insns.
(movsi_insn): Add alternatives for move from/to
loop count registers.
(doloop_end): New define_expand.
(loop_end): New define_insn.
(define_split for bad doloop_end): New.
(lsetup_with_autoinit): New define_insn.
(lsetup_without_autoinit): New define_insn.
(rep_movsi, rep_movhi): Clobber LT1, LC1, LB1.
* config/bfin/predicates.md (lc_register_operand): New.
(lt_register_operand): New.
(lb_register_operand): New.
(nondp_register_operand): New.
(nondp_reg_or_memory_operand): New.
* doc/md.texi: Document Blackfin new 't', 'k', 'l' constraint letters.
From-SVN: r114274
2006-05-31 18:46:15 +02:00
|
|
|
|
(set_attr "seq_insns" "*,multi,multi")])
|
2005-04-05 13:26:48 +02:00
|
|
|
|
|
genmodes.c (make_vector_mode): Allow making VECTOR_MODE_INT of a MODE_PARTIAL_INT mode.
* genmodes.c (make_vector_mode): Allow making VECTOR_MODE_INT of a
MODE_PARTIAL_INT mode.
* config/bfin/bfin-modes.def: Add V2PDI and V2SI.
* config/bfin/bfin.c (print_operand): Add macflag and mac/msu modifiers
for CONST_INTs.
(hard_regno_mode_ok): V2PDImode is ok for accumulators.
* config/bfin/bfin.h (CLASS_MAX_NREGS, HARD_REGNO_NREGS): Handle
V2PDImode.
* config/bfin/predicates.md (const01_operand, vec_shift_operand):
New predicates.
* config/bfin/bfin.md (UNSPEC_MUL_WITH_FLAG, UNSPEC_MAC_WITH_FLAG):
New constants.
(MACFLAG_NONE, MACFLAG_T, MACFLAG_FU, MACFLAG_TFU, MACFLAG_IS,
MACFLAG_IU, MACFLAG_W32, MACFLAG_M, MACFLAG_S2RND, MACFLAG_ISS2,
MACFLAG_IH): Likewise.
(movstricthi_1): Renamed from "*movstricthi".
(load_accumulator, load_accumulator_pair, movsi_insv, insv,
ssaddsi3, sssubsi3, ssnegsi2, signbitssi2, smaxhi3, sminhi3,
abshi2, neghi2, ssneghi2, signbitshi2, movhi_low2high,
movhi_high2high, movhi_low2low, movhi_high2low, movhiv2hi_low,
movhiv2hi_high, composev2hi, movv2hi_hi, movv2hi_hi_low,
movv2hi_hi_high, ssaddhi3, sssubhi3, ssaddv2hi3, sssubv2hi3,
addsubv2hi3, subaddv2hi3, ssaddsubv2hi3, sssubaddv2hi3,
sublohiv2hi3, subhilov2hi3, sssublohiv2hi3, sssubhilov2hi3,
addlohiv2hi3, addhilov2hi3, ssaddlohiv2hi3, ssaddhilov2hi3,
mulhisi_ll, mulhisi_lh, mulhisi_hl, mulhisi_hh, ssnegv2hi2,
ssashiftv2hi3, ssashifthi3, lshiftv2hi3, lshifthi3, packv2hi,
flag_mulhi, flag_mulhisi_parts, flag_machi, flag_machi_acconly,
flag_macinithi, flag_macinit1hi, flag_mulv2hi, flag_mulv2hi_parts,
flag_macv2hi_parts, flag_macv2hi_parts_acconly,
flag_macinitv2hi_parts, flag_macinit1v2hi_parts): New patterns.
From-SVN: r113245
2006-04-25 13:49:27 +02:00
|
|
|
|
(define_insn "load_accumulator"
|
|
|
|
|
[(set (match_operand:PDI 0 "register_operand" "=e")
|
|
|
|
|
(sign_extend:PDI (match_operand:SI 1 "register_operand" "d")))]
|
|
|
|
|
""
|
|
|
|
|
"%0 = %1;"
|
|
|
|
|
[(set_attr "type" "move")])
|
|
|
|
|
|
|
|
|
|
(define_insn_and_split "load_accumulator_pair"
|
|
|
|
|
[(set (match_operand:V2PDI 0 "register_operand" "=e")
|
|
|
|
|
(sign_extend:V2PDI (vec_concat:V2SI
|
|
|
|
|
(match_operand:SI 1 "register_operand" "d")
|
|
|
|
|
(match_operand:SI 2 "register_operand" "d"))))]
|
|
|
|
|
""
|
|
|
|
|
"#"
|
|
|
|
|
"reload_completed"
|
|
|
|
|
[(set (match_dup 3) (sign_extend:PDI (match_dup 1)))
|
|
|
|
|
(set (match_dup 4) (sign_extend:PDI (match_dup 2)))]
|
|
|
|
|
{
|
|
|
|
|
operands[3] = gen_rtx_REG (PDImode, REGNO (operands[0]));
|
|
|
|
|
operands[4] = gen_rtx_REG (PDImode, REGNO (operands[0]) + 1);
|
|
|
|
|
})
|
|
|
|
|
|
2005-04-05 13:26:48 +02:00
|
|
|
|
(define_insn "*pushsi_insn"
|
|
|
|
|
[(set (mem:SI (pre_dec:SI (reg:SI REG_SP)))
|
|
|
|
|
(match_operand:SI 0 "register_operand" "xy"))]
|
|
|
|
|
""
|
|
|
|
|
"[--SP] = %0;"
|
|
|
|
|
[(set_attr "type" "mcst")
|
2006-12-01 18:53:42 +01:00
|
|
|
|
(set_attr "addrtype" "32bit")
|
2005-04-05 13:26:48 +02:00
|
|
|
|
(set_attr "length" "2")])
|
|
|
|
|
|
|
|
|
|
(define_insn "*popsi_insn"
|
2006-12-01 18:53:42 +01:00
|
|
|
|
[(set (match_operand:SI 0 "register_operand" "=d,xy")
|
2005-04-05 13:26:48 +02:00
|
|
|
|
(mem:SI (post_inc:SI (reg:SI REG_SP))))]
|
|
|
|
|
""
|
rtlanal.c (note_uses): Deal with SEQUENCEs.
* rtlanal.c (note_uses): Deal with SEQUENCEs.
* config/bfin/bfin.c: Include "timevar.h".
(bfin_flag_schedule_insns2, splitting_for_sched,
bfin_flag_var_tracking): New variables.
(print_operand): Handle '%!'.
(override_options): Disable normal sched2 pass, instead set
bfin_flag_schedule_insns2 for reorg to handle it.
(output_file_start): Likewise for var-tracking.
(bfin_optimize_loop): Take some care not to stumble over SEQUENCEs.
(gen_one_bundle, bfin_gen_bundles, type_for_anomaly, trapping_loads_p):
New functions.
(bfin_reorg): Do second scheduling pass here, and call
bfin_gen_bundles. Use type_for_anomaly and trapping_loads_p instead
of examining insns directly. If bfin_flag_var_tracking, call
var-tracking pass when done with everything else.
* config/bfin/bfin.h (PRINT_OPERAND_PUNCT_VALID_P): '!' is valid.
* config/bfin/bfin.md (UNSPEC_32BIT): New constant.
(movsi_insn32): New pattern, with two new splits to create it
before the final scheduling pass.
(neghi2): Not a dsp32 insn, rather alu0.
(movbi, pushsi_insn, popsi_insn, movsi_insn, movv2hi_insn, movhi_insn,
movqi_insn, movsf_insn, movsi_insv, extendhisi2, zero_extendhisi2,
extendqihi2, extendqisi2, zero_extendqihi2, zero_extendqisi2,
mulhisi3, umulhisi3, ssadsi3, sssubsi3, smaxsi3, sminsi3, abssi2,
ssnegsi2, signbitssi2, smaxhi3, sminhi3, abshi2, ssneghi2, signbitshi2,
movhi_low2high, movhi_high2high, movhi_low2low, movhi_high2low,
movhiv2hi_low, movhiv2hi_high, composev2hi, packv2hi, movv2hi_hi,
ssaddhi3, sssubhi3, addv2hi3, ssaddv2hi3, subv2hi3, sssubv2hi3,
addsubv2hi3, subaddv2hi3, ssaddsubv2hi3, sssubaddv2hi3, sublohiv2hi3,
subhilov2hi3, sssublohiv2hi3, sssubhilov2hi3, addlohiv2hi3,
addhilov2hi3, ssaddlohiv2hi3, ssaddhilov2hi3, sminv2hi3, smaxv2hi3,
flag_mulhi, flag_mulhisi, flag_mulhisi_parts, flag_machi,
flag_machi_acconly, flag_macinithi, flag_macinit1hi, mulv2hi3,
flag_mulv2hi, flag_mulv2hi_parts, flag_macv2hi_parts,
flag_macv2hi_parts_acconly, flag_macinitv2hi_parts,
flag_macinit1v2hi_parts, mulhisi_ll, mulhisi_lh, mulhisi_hl,
mulhisi_hh, ssnegv2hi2, absv2hi2, ssashiftv2hi3, ssashifthi3,
lshiftv2hi3, lshifthi3): Use '%!' to terminate all dsp32/load/store
variants instead of ';'.
(ror_one, rol_one): Likewise. Make them dsp32 insns.
(ashlsi3_insn, ashrsi3, lshrsi3): Add dsp32 variants.
(align8, align16, align24): Now named patterns; also using '%!'.
(mnop): New insn.
From-SVN: r119534
2006-12-05 09:49:56 +01:00
|
|
|
|
"%0 = [SP++]%!"
|
2005-04-05 13:26:48 +02:00
|
|
|
|
[(set_attr "type" "mcld")
|
2006-12-01 18:53:42 +01:00
|
|
|
|
(set_attr "addrtype" "preg,32bit")
|
2005-04-05 13:26:48 +02:00
|
|
|
|
(set_attr "length" "2")])
|
|
|
|
|
|
|
|
|
|
;; The first alternative is used to make reload choose a limited register
|
|
|
|
|
;; class when faced with a movsi_insn that had its input operand replaced
|
|
|
|
|
;; with a PLUS. We generally require fewer secondary reloads this way.
|
|
|
|
|
|
bfin-protos.h (bfin_hardware_loop): Declare.
* config/bfin/bfin-protos.h (bfin_hardware_loop): Declare.
* config/bfin/bfin.c (basic-block.h): Include.
(struct machine_function): New.
(bfin_init_machine_status): New.
(override_options): Initialize init_machine_status.
(bfin_hardware_loop): New.
(MAX_LOOP_DEPTH, MAX_LOOP_LENGTH): Define.
(DEF_VEC_P (loop_info)): New.
(DEF_VEC_ALLOC_P (loop_info,heap)): New.
(struct loop_info): New.
(loop_info): New typedef.
(struct loop_work): New.
(loop_work): New typedef.
(DEF_VEC_O (loop_work)): New.
(DEF_VEC_ALLOC_O (loop_work,heap)): New.
(bfin_dump_loops): New.
(bfin_bb_in_loop): New.
(bfin_scan_loop): New.
(bfin_optimize_loop): New.
(bfin_reorg_loops): New.
(bfin_reorg): Use bfin_reorg_loops.
* config/bfin/bfin.h (FIRST_PSEUDO_REGISTER): Adjust for adding
loop registers.
(I_REGNO_P): Simplify.
(DP_REGNO_P, DPREG_P): New macros.
(REGISTER_NAMES, FIXED_REGISTERS, CALL_USED_REGISTERS,
REG_ALLOC_ORDER): Add LT0, LT1, LC0, LC1, LB0, LB1.
(enum reg_class, REG_CLASS_NAMES, REG_CLASS_CONTENTS):
Add LT_REGS, LC_REGS, LB_REGS.
(REG_CLASS_FROM_LETTER): Add 't' for LT_REGS, 'k' for LC_REGS,
'l' for LB_REGS.
(REGNO_REG_CLASS): Deal with loop registers.
* config/bfin/bfin.md: Add comment for 't', 'k', 'l' constraint
letters.
(REG_LT0, REG_LT1, REG_LC0, REG_LC1, REG_LB0, REG_LB1):
New constants for loop registers.
(UNSPEC_LSETUP_END): New.
(seq_insns): New define_attr. Set it for appropriate insns.
(movsi_insn): Add alternatives for move from/to
loop count registers.
(doloop_end): New define_expand.
(loop_end): New define_insn.
(define_split for bad doloop_end): New.
(lsetup_with_autoinit): New define_insn.
(lsetup_without_autoinit): New define_insn.
(rep_movsi, rep_movhi): Clobber LT1, LC1, LB1.
* config/bfin/predicates.md (lc_register_operand): New.
(lt_register_operand): New.
(lb_register_operand): New.
(nondp_register_operand): New.
(nondp_reg_or_memory_operand): New.
* doc/md.texi: Document Blackfin new 't', 'k', 'l' constraint letters.
From-SVN: r114274
2006-05-31 18:46:15 +02:00
|
|
|
|
(define_insn "*movsi_insn"
|
2009-04-29 16:13:30 +02:00
|
|
|
|
[(set (match_operand:SI 0 "nonimmediate_operand" "=da,x,da,y,da,x,x,x,da,mr")
|
|
|
|
|
(match_operand:SI 1 "general_operand" "da,x,y,da,xKs7,xKsh,xKuh,ix,mr,da"))]
|
2007-06-11 13:29:00 +02:00
|
|
|
|
"GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) == REG"
|
bfin-protos.h (bfin_hardware_loop): Declare.
* config/bfin/bfin-protos.h (bfin_hardware_loop): Declare.
* config/bfin/bfin.c (basic-block.h): Include.
(struct machine_function): New.
(bfin_init_machine_status): New.
(override_options): Initialize init_machine_status.
(bfin_hardware_loop): New.
(MAX_LOOP_DEPTH, MAX_LOOP_LENGTH): Define.
(DEF_VEC_P (loop_info)): New.
(DEF_VEC_ALLOC_P (loop_info,heap)): New.
(struct loop_info): New.
(loop_info): New typedef.
(struct loop_work): New.
(loop_work): New typedef.
(DEF_VEC_O (loop_work)): New.
(DEF_VEC_ALLOC_O (loop_work,heap)): New.
(bfin_dump_loops): New.
(bfin_bb_in_loop): New.
(bfin_scan_loop): New.
(bfin_optimize_loop): New.
(bfin_reorg_loops): New.
(bfin_reorg): Use bfin_reorg_loops.
* config/bfin/bfin.h (FIRST_PSEUDO_REGISTER): Adjust for adding
loop registers.
(I_REGNO_P): Simplify.
(DP_REGNO_P, DPREG_P): New macros.
(REGISTER_NAMES, FIXED_REGISTERS, CALL_USED_REGISTERS,
REG_ALLOC_ORDER): Add LT0, LT1, LC0, LC1, LB0, LB1.
(enum reg_class, REG_CLASS_NAMES, REG_CLASS_CONTENTS):
Add LT_REGS, LC_REGS, LB_REGS.
(REG_CLASS_FROM_LETTER): Add 't' for LT_REGS, 'k' for LC_REGS,
'l' for LB_REGS.
(REGNO_REG_CLASS): Deal with loop registers.
* config/bfin/bfin.md: Add comment for 't', 'k', 'l' constraint
letters.
(REG_LT0, REG_LT1, REG_LC0, REG_LC1, REG_LB0, REG_LB1):
New constants for loop registers.
(UNSPEC_LSETUP_END): New.
(seq_insns): New define_attr. Set it for appropriate insns.
(movsi_insn): Add alternatives for move from/to
loop count registers.
(doloop_end): New define_expand.
(loop_end): New define_insn.
(define_split for bad doloop_end): New.
(lsetup_with_autoinit): New define_insn.
(lsetup_without_autoinit): New define_insn.
(rep_movsi, rep_movhi): Clobber LT1, LC1, LB1.
* config/bfin/predicates.md (lc_register_operand): New.
(lt_register_operand): New.
(lb_register_operand): New.
(nondp_register_operand): New.
(nondp_reg_or_memory_operand): New.
* doc/md.texi: Document Blackfin new 't', 'k', 'l' constraint letters.
From-SVN: r114274
2006-05-31 18:46:15 +02:00
|
|
|
|
"@
|
2009-04-29 16:13:30 +02:00
|
|
|
|
%0 = %1;
|
|
|
|
|
%0 = %1;
|
2005-04-05 13:26:48 +02:00
|
|
|
|
%0 = %1;
|
|
|
|
|
%0 = %1;
|
|
|
|
|
%0 = %1 (X);
|
|
|
|
|
%0 = %1 (X);
|
|
|
|
|
%0 = %1 (Z);
|
|
|
|
|
#
|
rtlanal.c (note_uses): Deal with SEQUENCEs.
* rtlanal.c (note_uses): Deal with SEQUENCEs.
* config/bfin/bfin.c: Include "timevar.h".
(bfin_flag_schedule_insns2, splitting_for_sched,
bfin_flag_var_tracking): New variables.
(print_operand): Handle '%!'.
(override_options): Disable normal sched2 pass, instead set
bfin_flag_schedule_insns2 for reorg to handle it.
(output_file_start): Likewise for var-tracking.
(bfin_optimize_loop): Take some care not to stumble over SEQUENCEs.
(gen_one_bundle, bfin_gen_bundles, type_for_anomaly, trapping_loads_p):
New functions.
(bfin_reorg): Do second scheduling pass here, and call
bfin_gen_bundles. Use type_for_anomaly and trapping_loads_p instead
of examining insns directly. If bfin_flag_var_tracking, call
var-tracking pass when done with everything else.
* config/bfin/bfin.h (PRINT_OPERAND_PUNCT_VALID_P): '!' is valid.
* config/bfin/bfin.md (UNSPEC_32BIT): New constant.
(movsi_insn32): New pattern, with two new splits to create it
before the final scheduling pass.
(neghi2): Not a dsp32 insn, rather alu0.
(movbi, pushsi_insn, popsi_insn, movsi_insn, movv2hi_insn, movhi_insn,
movqi_insn, movsf_insn, movsi_insv, extendhisi2, zero_extendhisi2,
extendqihi2, extendqisi2, zero_extendqihi2, zero_extendqisi2,
mulhisi3, umulhisi3, ssadsi3, sssubsi3, smaxsi3, sminsi3, abssi2,
ssnegsi2, signbitssi2, smaxhi3, sminhi3, abshi2, ssneghi2, signbitshi2,
movhi_low2high, movhi_high2high, movhi_low2low, movhi_high2low,
movhiv2hi_low, movhiv2hi_high, composev2hi, packv2hi, movv2hi_hi,
ssaddhi3, sssubhi3, addv2hi3, ssaddv2hi3, subv2hi3, sssubv2hi3,
addsubv2hi3, subaddv2hi3, ssaddsubv2hi3, sssubaddv2hi3, sublohiv2hi3,
subhilov2hi3, sssublohiv2hi3, sssubhilov2hi3, addlohiv2hi3,
addhilov2hi3, ssaddlohiv2hi3, ssaddhilov2hi3, sminv2hi3, smaxv2hi3,
flag_mulhi, flag_mulhisi, flag_mulhisi_parts, flag_machi,
flag_machi_acconly, flag_macinithi, flag_macinit1hi, mulv2hi3,
flag_mulv2hi, flag_mulv2hi_parts, flag_macv2hi_parts,
flag_macv2hi_parts_acconly, flag_macinitv2hi_parts,
flag_macinit1v2hi_parts, mulhisi_ll, mulhisi_lh, mulhisi_hl,
mulhisi_hh, ssnegv2hi2, absv2hi2, ssashiftv2hi3, ssashifthi3,
lshiftv2hi3, lshifthi3): Use '%!' to terminate all dsp32/load/store
variants instead of ';'.
(ror_one, rol_one): Likewise. Make them dsp32 insns.
(ashlsi3_insn, ashrsi3, lshrsi3): Add dsp32 variants.
(align8, align16, align24): Now named patterns; also using '%!'.
(mnop): New insn.
From-SVN: r119534
2006-12-05 09:49:56 +01:00
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|
|
|
%0 = %1%!
|
|
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%0 = %1%!"
|
2009-04-29 16:13:30 +02:00
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|
[(set_attr "type" "move,move,move,move,mvi,mvi,mvi,*,mcld,mcst")
|
|
|
|
|
(set_attr "length" "2,2,2,2,2,4,4,*,*,*")])
|
2005-04-05 13:26:48 +02:00
|
|
|
|
|
rtlanal.c (note_uses): Deal with SEQUENCEs.
* rtlanal.c (note_uses): Deal with SEQUENCEs.
* config/bfin/bfin.c: Include "timevar.h".
(bfin_flag_schedule_insns2, splitting_for_sched,
bfin_flag_var_tracking): New variables.
(print_operand): Handle '%!'.
(override_options): Disable normal sched2 pass, instead set
bfin_flag_schedule_insns2 for reorg to handle it.
(output_file_start): Likewise for var-tracking.
(bfin_optimize_loop): Take some care not to stumble over SEQUENCEs.
(gen_one_bundle, bfin_gen_bundles, type_for_anomaly, trapping_loads_p):
New functions.
(bfin_reorg): Do second scheduling pass here, and call
bfin_gen_bundles. Use type_for_anomaly and trapping_loads_p instead
of examining insns directly. If bfin_flag_var_tracking, call
var-tracking pass when done with everything else.
* config/bfin/bfin.h (PRINT_OPERAND_PUNCT_VALID_P): '!' is valid.
* config/bfin/bfin.md (UNSPEC_32BIT): New constant.
(movsi_insn32): New pattern, with two new splits to create it
before the final scheduling pass.
(neghi2): Not a dsp32 insn, rather alu0.
(movbi, pushsi_insn, popsi_insn, movsi_insn, movv2hi_insn, movhi_insn,
movqi_insn, movsf_insn, movsi_insv, extendhisi2, zero_extendhisi2,
extendqihi2, extendqisi2, zero_extendqihi2, zero_extendqisi2,
mulhisi3, umulhisi3, ssadsi3, sssubsi3, smaxsi3, sminsi3, abssi2,
ssnegsi2, signbitssi2, smaxhi3, sminhi3, abshi2, ssneghi2, signbitshi2,
movhi_low2high, movhi_high2high, movhi_low2low, movhi_high2low,
movhiv2hi_low, movhiv2hi_high, composev2hi, packv2hi, movv2hi_hi,
ssaddhi3, sssubhi3, addv2hi3, ssaddv2hi3, subv2hi3, sssubv2hi3,
addsubv2hi3, subaddv2hi3, ssaddsubv2hi3, sssubaddv2hi3, sublohiv2hi3,
subhilov2hi3, sssublohiv2hi3, sssubhilov2hi3, addlohiv2hi3,
addhilov2hi3, ssaddlohiv2hi3, ssaddhilov2hi3, sminv2hi3, smaxv2hi3,
flag_mulhi, flag_mulhisi, flag_mulhisi_parts, flag_machi,
flag_machi_acconly, flag_macinithi, flag_macinit1hi, mulv2hi3,
flag_mulv2hi, flag_mulv2hi_parts, flag_macv2hi_parts,
flag_macv2hi_parts_acconly, flag_macinitv2hi_parts,
flag_macinit1v2hi_parts, mulhisi_ll, mulhisi_lh, mulhisi_hl,
mulhisi_hh, ssnegv2hi2, absv2hi2, ssashiftv2hi3, ssashifthi3,
lshiftv2hi3, lshifthi3): Use '%!' to terminate all dsp32/load/store
variants instead of ';'.
(ror_one, rol_one): Likewise. Make them dsp32 insns.
(ashlsi3_insn, ashrsi3, lshrsi3): Add dsp32 variants.
(align8, align16, align24): Now named patterns; also using '%!'.
(mnop): New insn.
From-SVN: r119534
2006-12-05 09:49:56 +01:00
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|
(define_insn "*movsi_insn32"
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[(set (match_operand:SI 0 "register_operand" "=d,d")
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(unspec:SI [(match_operand:SI 1 "nonmemory_operand" "d,P0")] UNSPEC_32BIT))]
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""
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"@
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%0 = ROT %1 BY 0%!
|
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%0 = %0 -|- %0%!"
|
From Jie Zhang <jie.zhang@analog.com>:
* config/bfin/predicates.md (p_register_operand): New
predicate.
(dp_register_operand): New predicate.
* config/bfin/bfin-protos.h (WA_05000074): Define.
(ENABLE_WA_05000074): Define.
* config/bfin/bfin.c (bfin_cpus[]): Add WA_05000074 for
all cpus.
(bfin_gen_bundles): Put dsp32shiftimm instruction in slot[0].
* config/bfin/bfin.md (define_attr type): Add dsp32shiftimm.
(define_attr addrtype): Allow load/store register to be
P register.
(define_attr storereg): New.
(define_cpu_unit anomaly_05000074): New.
(define_insn_reservation dsp32shiftimm): New.
(define_insn_reservation dsp32shiftimm_anomaly_05000074): New.
(define_insn_reservation loadp): Cannot use slot2.
(define_insn_reservation loadsp): Cannot use slot2.
(define_insn_reservation storep): Cannot use slot2. Does not
apply when working around 05000074.
(define_insn_reservation storep_anomaly_05000074): New.
(define_insn_reservation storei): Does not apply when working
around 05000074.
(define_insn_reservation storei_anomaly_05000074): New.
(define_attr length): Add dsp32shiftimm case.
(define_insn movsi_insn32, movsi_insv, ashlsi3_insn, ashrsi3,
ror_one, rol_one, lshrsi3, lshrpdi3, ashrpdi3, movhiv2hi_low,
movhiv2hi_high, composev2hi, packv2hi, movv2hi_hi,
ssashiftv2hi3, ssashifthi3, ssashiftsi3, lshiftv2hi3, lshifthi3):
Set type as dsp32shiftimm for dsp32shiftimm alternatives.
From-SVN: r151490
2009-09-07 23:40:23 +02:00
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[(set_attr "type" "dsp32shiftimm,dsp32")])
|
rtlanal.c (note_uses): Deal with SEQUENCEs.
* rtlanal.c (note_uses): Deal with SEQUENCEs.
* config/bfin/bfin.c: Include "timevar.h".
(bfin_flag_schedule_insns2, splitting_for_sched,
bfin_flag_var_tracking): New variables.
(print_operand): Handle '%!'.
(override_options): Disable normal sched2 pass, instead set
bfin_flag_schedule_insns2 for reorg to handle it.
(output_file_start): Likewise for var-tracking.
(bfin_optimize_loop): Take some care not to stumble over SEQUENCEs.
(gen_one_bundle, bfin_gen_bundles, type_for_anomaly, trapping_loads_p):
New functions.
(bfin_reorg): Do second scheduling pass here, and call
bfin_gen_bundles. Use type_for_anomaly and trapping_loads_p instead
of examining insns directly. If bfin_flag_var_tracking, call
var-tracking pass when done with everything else.
* config/bfin/bfin.h (PRINT_OPERAND_PUNCT_VALID_P): '!' is valid.
* config/bfin/bfin.md (UNSPEC_32BIT): New constant.
(movsi_insn32): New pattern, with two new splits to create it
before the final scheduling pass.
(neghi2): Not a dsp32 insn, rather alu0.
(movbi, pushsi_insn, popsi_insn, movsi_insn, movv2hi_insn, movhi_insn,
movqi_insn, movsf_insn, movsi_insv, extendhisi2, zero_extendhisi2,
extendqihi2, extendqisi2, zero_extendqihi2, zero_extendqisi2,
mulhisi3, umulhisi3, ssadsi3, sssubsi3, smaxsi3, sminsi3, abssi2,
ssnegsi2, signbitssi2, smaxhi3, sminhi3, abshi2, ssneghi2, signbitshi2,
movhi_low2high, movhi_high2high, movhi_low2low, movhi_high2low,
movhiv2hi_low, movhiv2hi_high, composev2hi, packv2hi, movv2hi_hi,
ssaddhi3, sssubhi3, addv2hi3, ssaddv2hi3, subv2hi3, sssubv2hi3,
addsubv2hi3, subaddv2hi3, ssaddsubv2hi3, sssubaddv2hi3, sublohiv2hi3,
subhilov2hi3, sssublohiv2hi3, sssubhilov2hi3, addlohiv2hi3,
addhilov2hi3, ssaddlohiv2hi3, ssaddhilov2hi3, sminv2hi3, smaxv2hi3,
flag_mulhi, flag_mulhisi, flag_mulhisi_parts, flag_machi,
flag_machi_acconly, flag_macinithi, flag_macinit1hi, mulv2hi3,
flag_mulv2hi, flag_mulv2hi_parts, flag_macv2hi_parts,
flag_macv2hi_parts_acconly, flag_macinitv2hi_parts,
flag_macinit1v2hi_parts, mulhisi_ll, mulhisi_lh, mulhisi_hl,
mulhisi_hh, ssnegv2hi2, absv2hi2, ssashiftv2hi3, ssashifthi3,
lshiftv2hi3, lshifthi3): Use '%!' to terminate all dsp32/load/store
variants instead of ';'.
(ror_one, rol_one): Likewise. Make them dsp32 insns.
(ashlsi3_insn, ashrsi3, lshrsi3): Add dsp32 variants.
(align8, align16, align24): Now named patterns; also using '%!'.
(mnop): New insn.
From-SVN: r119534
2006-12-05 09:49:56 +01:00
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(define_split
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[(set (match_operand:SI 0 "d_register_operand" "")
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(const_int 0))]
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"splitting_for_sched && !optimize_size"
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[(set (match_dup 0) (unspec:SI [(const_int 0)] UNSPEC_32BIT))])
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(define_split
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[(set (match_operand:SI 0 "d_register_operand" "")
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(match_operand:SI 1 "d_register_operand" ""))]
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"splitting_for_sched && !optimize_size"
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[(set (match_dup 0) (unspec:SI [(match_dup 1)] UNSPEC_32BIT))])
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genmodes.c (make_vector_mode): Allow making VECTOR_MODE_INT of a MODE_PARTIAL_INT mode.
* genmodes.c (make_vector_mode): Allow making VECTOR_MODE_INT of a
MODE_PARTIAL_INT mode.
* config/bfin/bfin-modes.def: Add V2PDI and V2SI.
* config/bfin/bfin.c (print_operand): Add macflag and mac/msu modifiers
for CONST_INTs.
(hard_regno_mode_ok): V2PDImode is ok for accumulators.
* config/bfin/bfin.h (CLASS_MAX_NREGS, HARD_REGNO_NREGS): Handle
V2PDImode.
* config/bfin/predicates.md (const01_operand, vec_shift_operand):
New predicates.
* config/bfin/bfin.md (UNSPEC_MUL_WITH_FLAG, UNSPEC_MAC_WITH_FLAG):
New constants.
(MACFLAG_NONE, MACFLAG_T, MACFLAG_FU, MACFLAG_TFU, MACFLAG_IS,
MACFLAG_IU, MACFLAG_W32, MACFLAG_M, MACFLAG_S2RND, MACFLAG_ISS2,
MACFLAG_IH): Likewise.
(movstricthi_1): Renamed from "*movstricthi".
(load_accumulator, load_accumulator_pair, movsi_insv, insv,
ssaddsi3, sssubsi3, ssnegsi2, signbitssi2, smaxhi3, sminhi3,
abshi2, neghi2, ssneghi2, signbitshi2, movhi_low2high,
movhi_high2high, movhi_low2low, movhi_high2low, movhiv2hi_low,
movhiv2hi_high, composev2hi, movv2hi_hi, movv2hi_hi_low,
movv2hi_hi_high, ssaddhi3, sssubhi3, ssaddv2hi3, sssubv2hi3,
addsubv2hi3, subaddv2hi3, ssaddsubv2hi3, sssubaddv2hi3,
sublohiv2hi3, subhilov2hi3, sssublohiv2hi3, sssubhilov2hi3,
addlohiv2hi3, addhilov2hi3, ssaddlohiv2hi3, ssaddhilov2hi3,
mulhisi_ll, mulhisi_lh, mulhisi_hl, mulhisi_hh, ssnegv2hi2,
ssashiftv2hi3, ssashifthi3, lshiftv2hi3, lshifthi3, packv2hi,
flag_mulhi, flag_mulhisi_parts, flag_machi, flag_machi_acconly,
flag_macinithi, flag_macinit1hi, flag_mulv2hi, flag_mulv2hi_parts,
flag_macv2hi_parts, flag_macv2hi_parts_acconly,
flag_macinitv2hi_parts, flag_macinit1v2hi_parts): New patterns.
From-SVN: r113245
2006-04-25 13:49:27 +02:00
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(define_insn_and_split "*movv2hi_insn"
|
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[(set (match_operand:V2HI 0 "nonimmediate_operand" "=da,da,d,dm")
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(match_operand:V2HI 1 "general_operand" "i,di,md,d"))]
|
2005-04-05 13:26:48 +02:00
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2007-06-11 13:29:00 +02:00
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"GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) == REG"
|
genmodes.c (make_vector_mode): Allow making VECTOR_MODE_INT of a MODE_PARTIAL_INT mode.
* genmodes.c (make_vector_mode): Allow making VECTOR_MODE_INT of a
MODE_PARTIAL_INT mode.
* config/bfin/bfin-modes.def: Add V2PDI and V2SI.
* config/bfin/bfin.c (print_operand): Add macflag and mac/msu modifiers
for CONST_INTs.
(hard_regno_mode_ok): V2PDImode is ok for accumulators.
* config/bfin/bfin.h (CLASS_MAX_NREGS, HARD_REGNO_NREGS): Handle
V2PDImode.
* config/bfin/predicates.md (const01_operand, vec_shift_operand):
New predicates.
* config/bfin/bfin.md (UNSPEC_MUL_WITH_FLAG, UNSPEC_MAC_WITH_FLAG):
New constants.
(MACFLAG_NONE, MACFLAG_T, MACFLAG_FU, MACFLAG_TFU, MACFLAG_IS,
MACFLAG_IU, MACFLAG_W32, MACFLAG_M, MACFLAG_S2RND, MACFLAG_ISS2,
MACFLAG_IH): Likewise.
(movstricthi_1): Renamed from "*movstricthi".
(load_accumulator, load_accumulator_pair, movsi_insv, insv,
ssaddsi3, sssubsi3, ssnegsi2, signbitssi2, smaxhi3, sminhi3,
abshi2, neghi2, ssneghi2, signbitshi2, movhi_low2high,
movhi_high2high, movhi_low2low, movhi_high2low, movhiv2hi_low,
movhiv2hi_high, composev2hi, movv2hi_hi, movv2hi_hi_low,
movv2hi_hi_high, ssaddhi3, sssubhi3, ssaddv2hi3, sssubv2hi3,
addsubv2hi3, subaddv2hi3, ssaddsubv2hi3, sssubaddv2hi3,
sublohiv2hi3, subhilov2hi3, sssublohiv2hi3, sssubhilov2hi3,
addlohiv2hi3, addhilov2hi3, ssaddlohiv2hi3, ssaddhilov2hi3,
mulhisi_ll, mulhisi_lh, mulhisi_hl, mulhisi_hh, ssnegv2hi2,
ssashiftv2hi3, ssashifthi3, lshiftv2hi3, lshifthi3, packv2hi,
flag_mulhi, flag_mulhisi_parts, flag_machi, flag_machi_acconly,
flag_macinithi, flag_macinit1hi, flag_mulv2hi, flag_mulv2hi_parts,
flag_macv2hi_parts, flag_macv2hi_parts_acconly,
flag_macinitv2hi_parts, flag_macinit1v2hi_parts): New patterns.
From-SVN: r113245
2006-04-25 13:49:27 +02:00
|
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"@
|
|
|
|
|
#
|
|
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|
%0 = %1;
|
rtlanal.c (note_uses): Deal with SEQUENCEs.
* rtlanal.c (note_uses): Deal with SEQUENCEs.
* config/bfin/bfin.c: Include "timevar.h".
(bfin_flag_schedule_insns2, splitting_for_sched,
bfin_flag_var_tracking): New variables.
(print_operand): Handle '%!'.
(override_options): Disable normal sched2 pass, instead set
bfin_flag_schedule_insns2 for reorg to handle it.
(output_file_start): Likewise for var-tracking.
(bfin_optimize_loop): Take some care not to stumble over SEQUENCEs.
(gen_one_bundle, bfin_gen_bundles, type_for_anomaly, trapping_loads_p):
New functions.
(bfin_reorg): Do second scheduling pass here, and call
bfin_gen_bundles. Use type_for_anomaly and trapping_loads_p instead
of examining insns directly. If bfin_flag_var_tracking, call
var-tracking pass when done with everything else.
* config/bfin/bfin.h (PRINT_OPERAND_PUNCT_VALID_P): '!' is valid.
* config/bfin/bfin.md (UNSPEC_32BIT): New constant.
(movsi_insn32): New pattern, with two new splits to create it
before the final scheduling pass.
(neghi2): Not a dsp32 insn, rather alu0.
(movbi, pushsi_insn, popsi_insn, movsi_insn, movv2hi_insn, movhi_insn,
movqi_insn, movsf_insn, movsi_insv, extendhisi2, zero_extendhisi2,
extendqihi2, extendqisi2, zero_extendqihi2, zero_extendqisi2,
mulhisi3, umulhisi3, ssadsi3, sssubsi3, smaxsi3, sminsi3, abssi2,
ssnegsi2, signbitssi2, smaxhi3, sminhi3, abshi2, ssneghi2, signbitshi2,
movhi_low2high, movhi_high2high, movhi_low2low, movhi_high2low,
movhiv2hi_low, movhiv2hi_high, composev2hi, packv2hi, movv2hi_hi,
ssaddhi3, sssubhi3, addv2hi3, ssaddv2hi3, subv2hi3, sssubv2hi3,
addsubv2hi3, subaddv2hi3, ssaddsubv2hi3, sssubaddv2hi3, sublohiv2hi3,
subhilov2hi3, sssublohiv2hi3, sssubhilov2hi3, addlohiv2hi3,
addhilov2hi3, ssaddlohiv2hi3, ssaddhilov2hi3, sminv2hi3, smaxv2hi3,
flag_mulhi, flag_mulhisi, flag_mulhisi_parts, flag_machi,
flag_machi_acconly, flag_macinithi, flag_macinit1hi, mulv2hi3,
flag_mulv2hi, flag_mulv2hi_parts, flag_macv2hi_parts,
flag_macv2hi_parts_acconly, flag_macinitv2hi_parts,
flag_macinit1v2hi_parts, mulhisi_ll, mulhisi_lh, mulhisi_hl,
mulhisi_hh, ssnegv2hi2, absv2hi2, ssashiftv2hi3, ssashifthi3,
lshiftv2hi3, lshifthi3): Use '%!' to terminate all dsp32/load/store
variants instead of ';'.
(ror_one, rol_one): Likewise. Make them dsp32 insns.
(ashlsi3_insn, ashrsi3, lshrsi3): Add dsp32 variants.
(align8, align16, align24): Now named patterns; also using '%!'.
(mnop): New insn.
From-SVN: r119534
2006-12-05 09:49:56 +01:00
|
|
|
|
%0 = %1%!
|
|
|
|
|
%0 = %1%!"
|
genmodes.c (make_vector_mode): Allow making VECTOR_MODE_INT of a MODE_PARTIAL_INT mode.
* genmodes.c (make_vector_mode): Allow making VECTOR_MODE_INT of a
MODE_PARTIAL_INT mode.
* config/bfin/bfin-modes.def: Add V2PDI and V2SI.
* config/bfin/bfin.c (print_operand): Add macflag and mac/msu modifiers
for CONST_INTs.
(hard_regno_mode_ok): V2PDImode is ok for accumulators.
* config/bfin/bfin.h (CLASS_MAX_NREGS, HARD_REGNO_NREGS): Handle
V2PDImode.
* config/bfin/predicates.md (const01_operand, vec_shift_operand):
New predicates.
* config/bfin/bfin.md (UNSPEC_MUL_WITH_FLAG, UNSPEC_MAC_WITH_FLAG):
New constants.
(MACFLAG_NONE, MACFLAG_T, MACFLAG_FU, MACFLAG_TFU, MACFLAG_IS,
MACFLAG_IU, MACFLAG_W32, MACFLAG_M, MACFLAG_S2RND, MACFLAG_ISS2,
MACFLAG_IH): Likewise.
(movstricthi_1): Renamed from "*movstricthi".
(load_accumulator, load_accumulator_pair, movsi_insv, insv,
ssaddsi3, sssubsi3, ssnegsi2, signbitssi2, smaxhi3, sminhi3,
abshi2, neghi2, ssneghi2, signbitshi2, movhi_low2high,
movhi_high2high, movhi_low2low, movhi_high2low, movhiv2hi_low,
movhiv2hi_high, composev2hi, movv2hi_hi, movv2hi_hi_low,
movv2hi_hi_high, ssaddhi3, sssubhi3, ssaddv2hi3, sssubv2hi3,
addsubv2hi3, subaddv2hi3, ssaddsubv2hi3, sssubaddv2hi3,
sublohiv2hi3, subhilov2hi3, sssublohiv2hi3, sssubhilov2hi3,
addlohiv2hi3, addhilov2hi3, ssaddlohiv2hi3, ssaddhilov2hi3,
mulhisi_ll, mulhisi_lh, mulhisi_hl, mulhisi_hh, ssnegv2hi2,
ssashiftv2hi3, ssashifthi3, lshiftv2hi3, lshifthi3, packv2hi,
flag_mulhi, flag_mulhisi_parts, flag_machi, flag_machi_acconly,
flag_macinithi, flag_macinit1hi, flag_mulv2hi, flag_mulv2hi_parts,
flag_macv2hi_parts, flag_macv2hi_parts_acconly,
flag_macinitv2hi_parts, flag_macinit1v2hi_parts): New patterns.
From-SVN: r113245
2006-04-25 13:49:27 +02:00
|
|
|
|
"reload_completed && GET_CODE (operands[1]) == CONST_VECTOR"
|
|
|
|
|
[(set (match_dup 0) (high:SI (match_dup 2)))
|
|
|
|
|
(set (match_dup 0) (lo_sum:SI (match_dup 0) (match_dup 3)))]
|
|
|
|
|
{
|
|
|
|
|
HOST_WIDE_INT intval = INTVAL (XVECEXP (operands[1], 0, 1)) << 16;
|
|
|
|
|
intval |= INTVAL (XVECEXP (operands[1], 0, 0)) & 0xFFFF;
|
2006-05-04 13:03:41 +02:00
|
|
|
|
|
genmodes.c (make_vector_mode): Allow making VECTOR_MODE_INT of a MODE_PARTIAL_INT mode.
* genmodes.c (make_vector_mode): Allow making VECTOR_MODE_INT of a
MODE_PARTIAL_INT mode.
* config/bfin/bfin-modes.def: Add V2PDI and V2SI.
* config/bfin/bfin.c (print_operand): Add macflag and mac/msu modifiers
for CONST_INTs.
(hard_regno_mode_ok): V2PDImode is ok for accumulators.
* config/bfin/bfin.h (CLASS_MAX_NREGS, HARD_REGNO_NREGS): Handle
V2PDImode.
* config/bfin/predicates.md (const01_operand, vec_shift_operand):
New predicates.
* config/bfin/bfin.md (UNSPEC_MUL_WITH_FLAG, UNSPEC_MAC_WITH_FLAG):
New constants.
(MACFLAG_NONE, MACFLAG_T, MACFLAG_FU, MACFLAG_TFU, MACFLAG_IS,
MACFLAG_IU, MACFLAG_W32, MACFLAG_M, MACFLAG_S2RND, MACFLAG_ISS2,
MACFLAG_IH): Likewise.
(movstricthi_1): Renamed from "*movstricthi".
(load_accumulator, load_accumulator_pair, movsi_insv, insv,
ssaddsi3, sssubsi3, ssnegsi2, signbitssi2, smaxhi3, sminhi3,
abshi2, neghi2, ssneghi2, signbitshi2, movhi_low2high,
movhi_high2high, movhi_low2low, movhi_high2low, movhiv2hi_low,
movhiv2hi_high, composev2hi, movv2hi_hi, movv2hi_hi_low,
movv2hi_hi_high, ssaddhi3, sssubhi3, ssaddv2hi3, sssubv2hi3,
addsubv2hi3, subaddv2hi3, ssaddsubv2hi3, sssubaddv2hi3,
sublohiv2hi3, subhilov2hi3, sssublohiv2hi3, sssubhilov2hi3,
addlohiv2hi3, addhilov2hi3, ssaddlohiv2hi3, ssaddhilov2hi3,
mulhisi_ll, mulhisi_lh, mulhisi_hl, mulhisi_hh, ssnegv2hi2,
ssashiftv2hi3, ssashifthi3, lshiftv2hi3, lshifthi3, packv2hi,
flag_mulhi, flag_mulhisi_parts, flag_machi, flag_machi_acconly,
flag_macinithi, flag_macinit1hi, flag_mulv2hi, flag_mulv2hi_parts,
flag_macv2hi_parts, flag_macv2hi_parts_acconly,
flag_macinitv2hi_parts, flag_macinit1v2hi_parts): New patterns.
From-SVN: r113245
2006-04-25 13:49:27 +02:00
|
|
|
|
operands[0] = gen_rtx_REG (SImode, REGNO (operands[0]));
|
|
|
|
|
operands[2] = operands[3] = GEN_INT (trunc_int_for_mode (intval, SImode));
|
|
|
|
|
}
|
|
|
|
|
[(set_attr "type" "move,move,mcld,mcst")
|
|
|
|
|
(set_attr "length" "2,2,*,*")])
|
2005-04-05 13:26:48 +02:00
|
|
|
|
|
|
|
|
|
(define_insn "*movhi_insn"
|
|
|
|
|
[(set (match_operand:HI 0 "nonimmediate_operand" "=x,da,x,d,mr")
|
|
|
|
|
(match_operand:HI 1 "general_operand" "x,xKs7,xKsh,mr,d"))]
|
2007-06-11 13:29:00 +02:00
|
|
|
|
"GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) == REG"
|
bfin-protos.h (bfin_dsp_memref_p): Declare.
* config/bfin/bfin-protos.h (bfin_dsp_memref_p): Declare.
* config/bfin/bfin.c (bfin_dsp_memref_p): New function.
(bfin_valid_reg_p): Test for pseudos explicitly and use only
REGNO_MODE_CODE_OK_FOR_BASE_P. New args MODE and OUTER_CODE; all
callers changed.
* config/bfin/bfin.h (PREG_P): Use P_REGNO_P.
(IREG_P, P_REGNO_P, I_REGNO_P): New macros.
(enum reg_class, REG_CLASS_CONTENTS): Add IPREGS.
(BASE_REG_CLASS, REG_OK_FOR_BASE_P, REG_OK_FOR_INDEX_P,
REGNO_OK_FOR_BASE_STRICT_P, REGNO_OK_FOR_BASE_NONSTRICT_P): Delete
macros.
(IREG_POSSIBLE_P, MODE_CODE_BASE_REG_CLASS,
REGNO_MODE_CODE_OK_FOR_BASE_P): New macros.
(REGNO_REG_CLASS): ARGP is in PREGS.
* config/bfin/bfin.md (movhi_insn): Allow for addresses containing
IREGS.
(zero_extendhisi2, extendhisi2): Likewise; changed to define_and_split
to deal with those addresses.
* addresses.h: New file.
* caller-save.c: Include "addresses.h".
(init_caller_save): Use new base_reg_class function.
* rtl-factoring.c: Include "addresses.h".
(recompute_gain_for_pattern_seq): Use new function ok_for_base_p_1.
* recog.c: Include "addresses.h".
(preprocess_constraints): Use new base_reg_class function.
* regrename.c: Include "addresses.h".
(scan_rtx_address): Use new regno_ok_for_base_p and base_reg_class
functions. Keep track of a new var INDEX_CODE to compute valid
classes.
(replace_oldest_value_addr): Likewise.
(replace_oldest_value_mem): Use base_reg_class.
* reload.c: Include "addresses.h".
(REGNO_MODE_OK_FOR_BASE_P, REG_MODE_OK_FOR_BASE_P): Delete macros.
(find_reloads): Use new base_reg_class function.
(find_reloads_address): Likewise; also use regno_ok_for_base_p.
(find_reloads_address_1): Likewise. New args OUTER_CODE and INDEX_CODE;
all callers and prototype changed.
* reload1.c: Include "addresses.h".
(maybe_fix_stack_asms): Use base_reg_class.
* regclass.c: Include "addresses.h".
(ok_for_index_p_nonstrict, ok_for_base_p_nonstrict): New functions.
(init_reg_autoinc): Use new base_reg_class function.
(record_reg_classes): Likewise.
(record_address_regs): Delete arg CLASS; add args CONTEXT, MODE,
OUTER_CODE and INDEX_CODE. All callers and prototype changed.
Use new args to compute necessary class.
* Makefile.in (regclass.o, reload.o, reload1.o, caller-save.o, recog.o,
regrename.o, rtl-factoring.o): Update dependencies.
* doc/tm.texi (MODE_CODE_BASE_REG_CLASS): Document.
(REGNO_MODE_CODE_OK_FOR_BASE_P): Likewise.
(REG_OK_FOR_BASE_P, REG_MODE_OK_FOR_BASE_P, REG_MODE_OK_FOR_REG_BASE_P,
REG_OK_FOR_INDEX_P): Delete documentation.
From-SVN: r112248
2006-03-21 14:07:33 +01:00
|
|
|
|
{
|
|
|
|
|
static const char *templates[] = {
|
|
|
|
|
"%0 = %1;",
|
|
|
|
|
"%0 = %1 (X);",
|
|
|
|
|
"%0 = %1 (X);",
|
rtlanal.c (note_uses): Deal with SEQUENCEs.
* rtlanal.c (note_uses): Deal with SEQUENCEs.
* config/bfin/bfin.c: Include "timevar.h".
(bfin_flag_schedule_insns2, splitting_for_sched,
bfin_flag_var_tracking): New variables.
(print_operand): Handle '%!'.
(override_options): Disable normal sched2 pass, instead set
bfin_flag_schedule_insns2 for reorg to handle it.
(output_file_start): Likewise for var-tracking.
(bfin_optimize_loop): Take some care not to stumble over SEQUENCEs.
(gen_one_bundle, bfin_gen_bundles, type_for_anomaly, trapping_loads_p):
New functions.
(bfin_reorg): Do second scheduling pass here, and call
bfin_gen_bundles. Use type_for_anomaly and trapping_loads_p instead
of examining insns directly. If bfin_flag_var_tracking, call
var-tracking pass when done with everything else.
* config/bfin/bfin.h (PRINT_OPERAND_PUNCT_VALID_P): '!' is valid.
* config/bfin/bfin.md (UNSPEC_32BIT): New constant.
(movsi_insn32): New pattern, with two new splits to create it
before the final scheduling pass.
(neghi2): Not a dsp32 insn, rather alu0.
(movbi, pushsi_insn, popsi_insn, movsi_insn, movv2hi_insn, movhi_insn,
movqi_insn, movsf_insn, movsi_insv, extendhisi2, zero_extendhisi2,
extendqihi2, extendqisi2, zero_extendqihi2, zero_extendqisi2,
mulhisi3, umulhisi3, ssadsi3, sssubsi3, smaxsi3, sminsi3, abssi2,
ssnegsi2, signbitssi2, smaxhi3, sminhi3, abshi2, ssneghi2, signbitshi2,
movhi_low2high, movhi_high2high, movhi_low2low, movhi_high2low,
movhiv2hi_low, movhiv2hi_high, composev2hi, packv2hi, movv2hi_hi,
ssaddhi3, sssubhi3, addv2hi3, ssaddv2hi3, subv2hi3, sssubv2hi3,
addsubv2hi3, subaddv2hi3, ssaddsubv2hi3, sssubaddv2hi3, sublohiv2hi3,
subhilov2hi3, sssublohiv2hi3, sssubhilov2hi3, addlohiv2hi3,
addhilov2hi3, ssaddlohiv2hi3, ssaddhilov2hi3, sminv2hi3, smaxv2hi3,
flag_mulhi, flag_mulhisi, flag_mulhisi_parts, flag_machi,
flag_machi_acconly, flag_macinithi, flag_macinit1hi, mulv2hi3,
flag_mulv2hi, flag_mulv2hi_parts, flag_macv2hi_parts,
flag_macv2hi_parts_acconly, flag_macinitv2hi_parts,
flag_macinit1v2hi_parts, mulhisi_ll, mulhisi_lh, mulhisi_hl,
mulhisi_hh, ssnegv2hi2, absv2hi2, ssashiftv2hi3, ssashifthi3,
lshiftv2hi3, lshifthi3): Use '%!' to terminate all dsp32/load/store
variants instead of ';'.
(ror_one, rol_one): Likewise. Make them dsp32 insns.
(ashlsi3_insn, ashrsi3, lshrsi3): Add dsp32 variants.
(align8, align16, align24): Now named patterns; also using '%!'.
(mnop): New insn.
From-SVN: r119534
2006-12-05 09:49:56 +01:00
|
|
|
|
"%0 = W %1 (X)%!",
|
|
|
|
|
"W %0 = %1%!",
|
|
|
|
|
"%h0 = W %1%!",
|
|
|
|
|
"W %0 = %h1%!"
|
bfin-protos.h (bfin_dsp_memref_p): Declare.
* config/bfin/bfin-protos.h (bfin_dsp_memref_p): Declare.
* config/bfin/bfin.c (bfin_dsp_memref_p): New function.
(bfin_valid_reg_p): Test for pseudos explicitly and use only
REGNO_MODE_CODE_OK_FOR_BASE_P. New args MODE and OUTER_CODE; all
callers changed.
* config/bfin/bfin.h (PREG_P): Use P_REGNO_P.
(IREG_P, P_REGNO_P, I_REGNO_P): New macros.
(enum reg_class, REG_CLASS_CONTENTS): Add IPREGS.
(BASE_REG_CLASS, REG_OK_FOR_BASE_P, REG_OK_FOR_INDEX_P,
REGNO_OK_FOR_BASE_STRICT_P, REGNO_OK_FOR_BASE_NONSTRICT_P): Delete
macros.
(IREG_POSSIBLE_P, MODE_CODE_BASE_REG_CLASS,
REGNO_MODE_CODE_OK_FOR_BASE_P): New macros.
(REGNO_REG_CLASS): ARGP is in PREGS.
* config/bfin/bfin.md (movhi_insn): Allow for addresses containing
IREGS.
(zero_extendhisi2, extendhisi2): Likewise; changed to define_and_split
to deal with those addresses.
* addresses.h: New file.
* caller-save.c: Include "addresses.h".
(init_caller_save): Use new base_reg_class function.
* rtl-factoring.c: Include "addresses.h".
(recompute_gain_for_pattern_seq): Use new function ok_for_base_p_1.
* recog.c: Include "addresses.h".
(preprocess_constraints): Use new base_reg_class function.
* regrename.c: Include "addresses.h".
(scan_rtx_address): Use new regno_ok_for_base_p and base_reg_class
functions. Keep track of a new var INDEX_CODE to compute valid
classes.
(replace_oldest_value_addr): Likewise.
(replace_oldest_value_mem): Use base_reg_class.
* reload.c: Include "addresses.h".
(REGNO_MODE_OK_FOR_BASE_P, REG_MODE_OK_FOR_BASE_P): Delete macros.
(find_reloads): Use new base_reg_class function.
(find_reloads_address): Likewise; also use regno_ok_for_base_p.
(find_reloads_address_1): Likewise. New args OUTER_CODE and INDEX_CODE;
all callers and prototype changed.
* reload1.c: Include "addresses.h".
(maybe_fix_stack_asms): Use base_reg_class.
* regclass.c: Include "addresses.h".
(ok_for_index_p_nonstrict, ok_for_base_p_nonstrict): New functions.
(init_reg_autoinc): Use new base_reg_class function.
(record_reg_classes): Likewise.
(record_address_regs): Delete arg CLASS; add args CONTEXT, MODE,
OUTER_CODE and INDEX_CODE. All callers and prototype changed.
Use new args to compute necessary class.
* Makefile.in (regclass.o, reload.o, reload1.o, caller-save.o, recog.o,
regrename.o, rtl-factoring.o): Update dependencies.
* doc/tm.texi (MODE_CODE_BASE_REG_CLASS): Document.
(REGNO_MODE_CODE_OK_FOR_BASE_P): Likewise.
(REG_OK_FOR_BASE_P, REG_MODE_OK_FOR_BASE_P, REG_MODE_OK_FOR_REG_BASE_P,
REG_OK_FOR_INDEX_P): Delete documentation.
From-SVN: r112248
2006-03-21 14:07:33 +01:00
|
|
|
|
};
|
|
|
|
|
int alt = which_alternative;
|
|
|
|
|
rtx mem = (MEM_P (operands[0]) ? operands[0]
|
|
|
|
|
: MEM_P (operands[1]) ? operands[1] : NULL_RTX);
|
|
|
|
|
if (mem && bfin_dsp_memref_p (mem))
|
|
|
|
|
alt += 2;
|
|
|
|
|
return templates[alt];
|
|
|
|
|
}
|
2005-04-05 13:26:48 +02:00
|
|
|
|
[(set_attr "type" "move,mvi,mvi,mcld,mcst")
|
|
|
|
|
(set_attr "length" "2,2,4,*,*")])
|
|
|
|
|
|
|
|
|
|
(define_insn "*movqi_insn"
|
|
|
|
|
[(set (match_operand:QI 0 "nonimmediate_operand" "=x,da,x,d,mr")
|
|
|
|
|
(match_operand:QI 1 "general_operand" "x,xKs7,xKsh,mr,d"))]
|
2007-06-11 13:29:00 +02:00
|
|
|
|
"GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) == REG"
|
2005-04-05 13:26:48 +02:00
|
|
|
|
"@
|
|
|
|
|
%0 = %1;
|
|
|
|
|
%0 = %1 (X);
|
|
|
|
|
%0 = %1 (X);
|
rtlanal.c (note_uses): Deal with SEQUENCEs.
* rtlanal.c (note_uses): Deal with SEQUENCEs.
* config/bfin/bfin.c: Include "timevar.h".
(bfin_flag_schedule_insns2, splitting_for_sched,
bfin_flag_var_tracking): New variables.
(print_operand): Handle '%!'.
(override_options): Disable normal sched2 pass, instead set
bfin_flag_schedule_insns2 for reorg to handle it.
(output_file_start): Likewise for var-tracking.
(bfin_optimize_loop): Take some care not to stumble over SEQUENCEs.
(gen_one_bundle, bfin_gen_bundles, type_for_anomaly, trapping_loads_p):
New functions.
(bfin_reorg): Do second scheduling pass here, and call
bfin_gen_bundles. Use type_for_anomaly and trapping_loads_p instead
of examining insns directly. If bfin_flag_var_tracking, call
var-tracking pass when done with everything else.
* config/bfin/bfin.h (PRINT_OPERAND_PUNCT_VALID_P): '!' is valid.
* config/bfin/bfin.md (UNSPEC_32BIT): New constant.
(movsi_insn32): New pattern, with two new splits to create it
before the final scheduling pass.
(neghi2): Not a dsp32 insn, rather alu0.
(movbi, pushsi_insn, popsi_insn, movsi_insn, movv2hi_insn, movhi_insn,
movqi_insn, movsf_insn, movsi_insv, extendhisi2, zero_extendhisi2,
extendqihi2, extendqisi2, zero_extendqihi2, zero_extendqisi2,
mulhisi3, umulhisi3, ssadsi3, sssubsi3, smaxsi3, sminsi3, abssi2,
ssnegsi2, signbitssi2, smaxhi3, sminhi3, abshi2, ssneghi2, signbitshi2,
movhi_low2high, movhi_high2high, movhi_low2low, movhi_high2low,
movhiv2hi_low, movhiv2hi_high, composev2hi, packv2hi, movv2hi_hi,
ssaddhi3, sssubhi3, addv2hi3, ssaddv2hi3, subv2hi3, sssubv2hi3,
addsubv2hi3, subaddv2hi3, ssaddsubv2hi3, sssubaddv2hi3, sublohiv2hi3,
subhilov2hi3, sssublohiv2hi3, sssubhilov2hi3, addlohiv2hi3,
addhilov2hi3, ssaddlohiv2hi3, ssaddhilov2hi3, sminv2hi3, smaxv2hi3,
flag_mulhi, flag_mulhisi, flag_mulhisi_parts, flag_machi,
flag_machi_acconly, flag_macinithi, flag_macinit1hi, mulv2hi3,
flag_mulv2hi, flag_mulv2hi_parts, flag_macv2hi_parts,
flag_macv2hi_parts_acconly, flag_macinitv2hi_parts,
flag_macinit1v2hi_parts, mulhisi_ll, mulhisi_lh, mulhisi_hl,
mulhisi_hh, ssnegv2hi2, absv2hi2, ssashiftv2hi3, ssashifthi3,
lshiftv2hi3, lshifthi3): Use '%!' to terminate all dsp32/load/store
variants instead of ';'.
(ror_one, rol_one): Likewise. Make them dsp32 insns.
(ashlsi3_insn, ashrsi3, lshrsi3): Add dsp32 variants.
(align8, align16, align24): Now named patterns; also using '%!'.
(mnop): New insn.
From-SVN: r119534
2006-12-05 09:49:56 +01:00
|
|
|
|
%0 = B %1 (X)%!
|
|
|
|
|
B %0 = %1%!"
|
2005-04-05 13:26:48 +02:00
|
|
|
|
[(set_attr "type" "move,mvi,mvi,mcld,mcst")
|
|
|
|
|
(set_attr "length" "2,2,4,*,*")])
|
|
|
|
|
|
|
|
|
|
(define_insn "*movsf_insn"
|
|
|
|
|
[(set (match_operand:SF 0 "nonimmediate_operand" "=x,x,da,mr")
|
|
|
|
|
(match_operand:SF 1 "general_operand" "x,Fx,mr,da"))]
|
2007-06-11 13:29:00 +02:00
|
|
|
|
"GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) == REG"
|
2005-04-05 13:26:48 +02:00
|
|
|
|
"@
|
|
|
|
|
%0 = %1;
|
|
|
|
|
#
|
rtlanal.c (note_uses): Deal with SEQUENCEs.
* rtlanal.c (note_uses): Deal with SEQUENCEs.
* config/bfin/bfin.c: Include "timevar.h".
(bfin_flag_schedule_insns2, splitting_for_sched,
bfin_flag_var_tracking): New variables.
(print_operand): Handle '%!'.
(override_options): Disable normal sched2 pass, instead set
bfin_flag_schedule_insns2 for reorg to handle it.
(output_file_start): Likewise for var-tracking.
(bfin_optimize_loop): Take some care not to stumble over SEQUENCEs.
(gen_one_bundle, bfin_gen_bundles, type_for_anomaly, trapping_loads_p):
New functions.
(bfin_reorg): Do second scheduling pass here, and call
bfin_gen_bundles. Use type_for_anomaly and trapping_loads_p instead
of examining insns directly. If bfin_flag_var_tracking, call
var-tracking pass when done with everything else.
* config/bfin/bfin.h (PRINT_OPERAND_PUNCT_VALID_P): '!' is valid.
* config/bfin/bfin.md (UNSPEC_32BIT): New constant.
(movsi_insn32): New pattern, with two new splits to create it
before the final scheduling pass.
(neghi2): Not a dsp32 insn, rather alu0.
(movbi, pushsi_insn, popsi_insn, movsi_insn, movv2hi_insn, movhi_insn,
movqi_insn, movsf_insn, movsi_insv, extendhisi2, zero_extendhisi2,
extendqihi2, extendqisi2, zero_extendqihi2, zero_extendqisi2,
mulhisi3, umulhisi3, ssadsi3, sssubsi3, smaxsi3, sminsi3, abssi2,
ssnegsi2, signbitssi2, smaxhi3, sminhi3, abshi2, ssneghi2, signbitshi2,
movhi_low2high, movhi_high2high, movhi_low2low, movhi_high2low,
movhiv2hi_low, movhiv2hi_high, composev2hi, packv2hi, movv2hi_hi,
ssaddhi3, sssubhi3, addv2hi3, ssaddv2hi3, subv2hi3, sssubv2hi3,
addsubv2hi3, subaddv2hi3, ssaddsubv2hi3, sssubaddv2hi3, sublohiv2hi3,
subhilov2hi3, sssublohiv2hi3, sssubhilov2hi3, addlohiv2hi3,
addhilov2hi3, ssaddlohiv2hi3, ssaddhilov2hi3, sminv2hi3, smaxv2hi3,
flag_mulhi, flag_mulhisi, flag_mulhisi_parts, flag_machi,
flag_machi_acconly, flag_macinithi, flag_macinit1hi, mulv2hi3,
flag_mulv2hi, flag_mulv2hi_parts, flag_macv2hi_parts,
flag_macv2hi_parts_acconly, flag_macinitv2hi_parts,
flag_macinit1v2hi_parts, mulhisi_ll, mulhisi_lh, mulhisi_hl,
mulhisi_hh, ssnegv2hi2, absv2hi2, ssashiftv2hi3, ssashifthi3,
lshiftv2hi3, lshifthi3): Use '%!' to terminate all dsp32/load/store
variants instead of ';'.
(ror_one, rol_one): Likewise. Make them dsp32 insns.
(ashlsi3_insn, ashrsi3, lshrsi3): Add dsp32 variants.
(align8, align16, align24): Now named patterns; also using '%!'.
(mnop): New insn.
From-SVN: r119534
2006-12-05 09:49:56 +01:00
|
|
|
|
%0 = %1%!
|
|
|
|
|
%0 = %1%!"
|
2005-04-05 13:26:48 +02:00
|
|
|
|
[(set_attr "type" "move,*,mcld,mcst")])
|
|
|
|
|
|
|
|
|
|
(define_insn_and_split "movdf_insn"
|
|
|
|
|
[(set (match_operand:DF 0 "nonimmediate_operand" "=x,mx,r")
|
|
|
|
|
(match_operand:DF 1 "general_operand" "iFx,r,mx"))]
|
2007-06-11 13:29:00 +02:00
|
|
|
|
"GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) == REG"
|
2005-04-05 13:26:48 +02:00
|
|
|
|
"#"
|
|
|
|
|
"reload_completed"
|
|
|
|
|
[(set (match_dup 2) (match_dup 3))
|
|
|
|
|
(set (match_dup 4) (match_dup 5))]
|
|
|
|
|
{
|
|
|
|
|
rtx lo_half[2], hi_half[2];
|
|
|
|
|
split_di (operands, 2, lo_half, hi_half);
|
|
|
|
|
|
|
|
|
|
if (reg_overlap_mentioned_p (lo_half[0], hi_half[1]))
|
|
|
|
|
{
|
|
|
|
|
operands[2] = hi_half[0];
|
|
|
|
|
operands[3] = hi_half[1];
|
|
|
|
|
operands[4] = lo_half[0];
|
|
|
|
|
operands[5] = lo_half[1];
|
|
|
|
|
}
|
|
|
|
|
else
|
|
|
|
|
{
|
|
|
|
|
operands[2] = lo_half[0];
|
|
|
|
|
operands[3] = lo_half[1];
|
|
|
|
|
operands[4] = hi_half[0];
|
|
|
|
|
operands[5] = hi_half[1];
|
|
|
|
|
}
|
|
|
|
|
})
|
|
|
|
|
|
genmodes.c (make_vector_mode): Allow making VECTOR_MODE_INT of a MODE_PARTIAL_INT mode.
* genmodes.c (make_vector_mode): Allow making VECTOR_MODE_INT of a
MODE_PARTIAL_INT mode.
* config/bfin/bfin-modes.def: Add V2PDI and V2SI.
* config/bfin/bfin.c (print_operand): Add macflag and mac/msu modifiers
for CONST_INTs.
(hard_regno_mode_ok): V2PDImode is ok for accumulators.
* config/bfin/bfin.h (CLASS_MAX_NREGS, HARD_REGNO_NREGS): Handle
V2PDImode.
* config/bfin/predicates.md (const01_operand, vec_shift_operand):
New predicates.
* config/bfin/bfin.md (UNSPEC_MUL_WITH_FLAG, UNSPEC_MAC_WITH_FLAG):
New constants.
(MACFLAG_NONE, MACFLAG_T, MACFLAG_FU, MACFLAG_TFU, MACFLAG_IS,
MACFLAG_IU, MACFLAG_W32, MACFLAG_M, MACFLAG_S2RND, MACFLAG_ISS2,
MACFLAG_IH): Likewise.
(movstricthi_1): Renamed from "*movstricthi".
(load_accumulator, load_accumulator_pair, movsi_insv, insv,
ssaddsi3, sssubsi3, ssnegsi2, signbitssi2, smaxhi3, sminhi3,
abshi2, neghi2, ssneghi2, signbitshi2, movhi_low2high,
movhi_high2high, movhi_low2low, movhi_high2low, movhiv2hi_low,
movhiv2hi_high, composev2hi, movv2hi_hi, movv2hi_hi_low,
movv2hi_hi_high, ssaddhi3, sssubhi3, ssaddv2hi3, sssubv2hi3,
addsubv2hi3, subaddv2hi3, ssaddsubv2hi3, sssubaddv2hi3,
sublohiv2hi3, subhilov2hi3, sssublohiv2hi3, sssubhilov2hi3,
addlohiv2hi3, addhilov2hi3, ssaddlohiv2hi3, ssaddhilov2hi3,
mulhisi_ll, mulhisi_lh, mulhisi_hl, mulhisi_hh, ssnegv2hi2,
ssashiftv2hi3, ssashifthi3, lshiftv2hi3, lshifthi3, packv2hi,
flag_mulhi, flag_mulhisi_parts, flag_machi, flag_machi_acconly,
flag_macinithi, flag_macinit1hi, flag_mulv2hi, flag_mulv2hi_parts,
flag_macv2hi_parts, flag_macv2hi_parts_acconly,
flag_macinitv2hi_parts, flag_macinit1v2hi_parts): New patterns.
From-SVN: r113245
2006-04-25 13:49:27 +02:00
|
|
|
|
;; Storing halfwords.
|
|
|
|
|
(define_insn "*movsi_insv"
|
|
|
|
|
[(set (zero_extract:SI (match_operand 0 "register_operand" "+d,x")
|
|
|
|
|
(const_int 16)
|
|
|
|
|
(const_int 16))
|
|
|
|
|
(match_operand:SI 1 "nonmemory_operand" "d,n"))]
|
|
|
|
|
""
|
|
|
|
|
"@
|
rtlanal.c (note_uses): Deal with SEQUENCEs.
* rtlanal.c (note_uses): Deal with SEQUENCEs.
* config/bfin/bfin.c: Include "timevar.h".
(bfin_flag_schedule_insns2, splitting_for_sched,
bfin_flag_var_tracking): New variables.
(print_operand): Handle '%!'.
(override_options): Disable normal sched2 pass, instead set
bfin_flag_schedule_insns2 for reorg to handle it.
(output_file_start): Likewise for var-tracking.
(bfin_optimize_loop): Take some care not to stumble over SEQUENCEs.
(gen_one_bundle, bfin_gen_bundles, type_for_anomaly, trapping_loads_p):
New functions.
(bfin_reorg): Do second scheduling pass here, and call
bfin_gen_bundles. Use type_for_anomaly and trapping_loads_p instead
of examining insns directly. If bfin_flag_var_tracking, call
var-tracking pass when done with everything else.
* config/bfin/bfin.h (PRINT_OPERAND_PUNCT_VALID_P): '!' is valid.
* config/bfin/bfin.md (UNSPEC_32BIT): New constant.
(movsi_insn32): New pattern, with two new splits to create it
before the final scheduling pass.
(neghi2): Not a dsp32 insn, rather alu0.
(movbi, pushsi_insn, popsi_insn, movsi_insn, movv2hi_insn, movhi_insn,
movqi_insn, movsf_insn, movsi_insv, extendhisi2, zero_extendhisi2,
extendqihi2, extendqisi2, zero_extendqihi2, zero_extendqisi2,
mulhisi3, umulhisi3, ssadsi3, sssubsi3, smaxsi3, sminsi3, abssi2,
ssnegsi2, signbitssi2, smaxhi3, sminhi3, abshi2, ssneghi2, signbitshi2,
movhi_low2high, movhi_high2high, movhi_low2low, movhi_high2low,
movhiv2hi_low, movhiv2hi_high, composev2hi, packv2hi, movv2hi_hi,
ssaddhi3, sssubhi3, addv2hi3, ssaddv2hi3, subv2hi3, sssubv2hi3,
addsubv2hi3, subaddv2hi3, ssaddsubv2hi3, sssubaddv2hi3, sublohiv2hi3,
subhilov2hi3, sssublohiv2hi3, sssubhilov2hi3, addlohiv2hi3,
addhilov2hi3, ssaddlohiv2hi3, ssaddhilov2hi3, sminv2hi3, smaxv2hi3,
flag_mulhi, flag_mulhisi, flag_mulhisi_parts, flag_machi,
flag_machi_acconly, flag_macinithi, flag_macinit1hi, mulv2hi3,
flag_mulv2hi, flag_mulv2hi_parts, flag_macv2hi_parts,
flag_macv2hi_parts_acconly, flag_macinitv2hi_parts,
flag_macinit1v2hi_parts, mulhisi_ll, mulhisi_lh, mulhisi_hl,
mulhisi_hh, ssnegv2hi2, absv2hi2, ssashiftv2hi3, ssashifthi3,
lshiftv2hi3, lshifthi3): Use '%!' to terminate all dsp32/load/store
variants instead of ';'.
(ror_one, rol_one): Likewise. Make them dsp32 insns.
(ashlsi3_insn, ashrsi3, lshrsi3): Add dsp32 variants.
(align8, align16, align24): Now named patterns; also using '%!'.
(mnop): New insn.
From-SVN: r119534
2006-12-05 09:49:56 +01:00
|
|
|
|
%d0 = %h1 << 0%!
|
genmodes.c (make_vector_mode): Allow making VECTOR_MODE_INT of a MODE_PARTIAL_INT mode.
* genmodes.c (make_vector_mode): Allow making VECTOR_MODE_INT of a
MODE_PARTIAL_INT mode.
* config/bfin/bfin-modes.def: Add V2PDI and V2SI.
* config/bfin/bfin.c (print_operand): Add macflag and mac/msu modifiers
for CONST_INTs.
(hard_regno_mode_ok): V2PDImode is ok for accumulators.
* config/bfin/bfin.h (CLASS_MAX_NREGS, HARD_REGNO_NREGS): Handle
V2PDImode.
* config/bfin/predicates.md (const01_operand, vec_shift_operand):
New predicates.
* config/bfin/bfin.md (UNSPEC_MUL_WITH_FLAG, UNSPEC_MAC_WITH_FLAG):
New constants.
(MACFLAG_NONE, MACFLAG_T, MACFLAG_FU, MACFLAG_TFU, MACFLAG_IS,
MACFLAG_IU, MACFLAG_W32, MACFLAG_M, MACFLAG_S2RND, MACFLAG_ISS2,
MACFLAG_IH): Likewise.
(movstricthi_1): Renamed from "*movstricthi".
(load_accumulator, load_accumulator_pair, movsi_insv, insv,
ssaddsi3, sssubsi3, ssnegsi2, signbitssi2, smaxhi3, sminhi3,
abshi2, neghi2, ssneghi2, signbitshi2, movhi_low2high,
movhi_high2high, movhi_low2low, movhi_high2low, movhiv2hi_low,
movhiv2hi_high, composev2hi, movv2hi_hi, movv2hi_hi_low,
movv2hi_hi_high, ssaddhi3, sssubhi3, ssaddv2hi3, sssubv2hi3,
addsubv2hi3, subaddv2hi3, ssaddsubv2hi3, sssubaddv2hi3,
sublohiv2hi3, subhilov2hi3, sssublohiv2hi3, sssubhilov2hi3,
addlohiv2hi3, addhilov2hi3, ssaddlohiv2hi3, ssaddhilov2hi3,
mulhisi_ll, mulhisi_lh, mulhisi_hl, mulhisi_hh, ssnegv2hi2,
ssashiftv2hi3, ssashifthi3, lshiftv2hi3, lshifthi3, packv2hi,
flag_mulhi, flag_mulhisi_parts, flag_machi, flag_machi_acconly,
flag_macinithi, flag_macinit1hi, flag_mulv2hi, flag_mulv2hi_parts,
flag_macv2hi_parts, flag_macv2hi_parts_acconly,
flag_macinitv2hi_parts, flag_macinit1v2hi_parts): New patterns.
From-SVN: r113245
2006-04-25 13:49:27 +02:00
|
|
|
|
%d0 = %1;"
|
2020-03-11 05:16:19 +01:00
|
|
|
|
[(set_attr "type" "dsp32shiftimm,mvi")
|
|
|
|
|
(set_attr "length" "*,4")])
|
genmodes.c (make_vector_mode): Allow making VECTOR_MODE_INT of a MODE_PARTIAL_INT mode.
* genmodes.c (make_vector_mode): Allow making VECTOR_MODE_INT of a
MODE_PARTIAL_INT mode.
* config/bfin/bfin-modes.def: Add V2PDI and V2SI.
* config/bfin/bfin.c (print_operand): Add macflag and mac/msu modifiers
for CONST_INTs.
(hard_regno_mode_ok): V2PDImode is ok for accumulators.
* config/bfin/bfin.h (CLASS_MAX_NREGS, HARD_REGNO_NREGS): Handle
V2PDImode.
* config/bfin/predicates.md (const01_operand, vec_shift_operand):
New predicates.
* config/bfin/bfin.md (UNSPEC_MUL_WITH_FLAG, UNSPEC_MAC_WITH_FLAG):
New constants.
(MACFLAG_NONE, MACFLAG_T, MACFLAG_FU, MACFLAG_TFU, MACFLAG_IS,
MACFLAG_IU, MACFLAG_W32, MACFLAG_M, MACFLAG_S2RND, MACFLAG_ISS2,
MACFLAG_IH): Likewise.
(movstricthi_1): Renamed from "*movstricthi".
(load_accumulator, load_accumulator_pair, movsi_insv, insv,
ssaddsi3, sssubsi3, ssnegsi2, signbitssi2, smaxhi3, sminhi3,
abshi2, neghi2, ssneghi2, signbitshi2, movhi_low2high,
movhi_high2high, movhi_low2low, movhi_high2low, movhiv2hi_low,
movhiv2hi_high, composev2hi, movv2hi_hi, movv2hi_hi_low,
movv2hi_hi_high, ssaddhi3, sssubhi3, ssaddv2hi3, sssubv2hi3,
addsubv2hi3, subaddv2hi3, ssaddsubv2hi3, sssubaddv2hi3,
sublohiv2hi3, subhilov2hi3, sssublohiv2hi3, sssubhilov2hi3,
addlohiv2hi3, addhilov2hi3, ssaddlohiv2hi3, ssaddhilov2hi3,
mulhisi_ll, mulhisi_lh, mulhisi_hl, mulhisi_hh, ssnegv2hi2,
ssashiftv2hi3, ssashifthi3, lshiftv2hi3, lshifthi3, packv2hi,
flag_mulhi, flag_mulhisi_parts, flag_machi, flag_machi_acconly,
flag_macinithi, flag_macinit1hi, flag_mulv2hi, flag_mulv2hi_parts,
flag_macv2hi_parts, flag_macv2hi_parts_acconly,
flag_macinitv2hi_parts, flag_macinit1v2hi_parts): New patterns.
From-SVN: r113245
2006-04-25 13:49:27 +02:00
|
|
|
|
|
|
|
|
|
(define_expand "insv"
|
|
|
|
|
[(set (zero_extract:SI (match_operand:SI 0 "register_operand" "")
|
|
|
|
|
(match_operand:SI 1 "immediate_operand" "")
|
|
|
|
|
(match_operand:SI 2 "immediate_operand" ""))
|
|
|
|
|
(match_operand:SI 3 "nonmemory_operand" ""))]
|
|
|
|
|
""
|
|
|
|
|
{
|
|
|
|
|
if (INTVAL (operands[1]) != 16 || INTVAL (operands[2]) != 16)
|
|
|
|
|
FAIL;
|
|
|
|
|
|
|
|
|
|
/* From mips.md: insert_bit_field doesn't verify that our source
|
|
|
|
|
matches the predicate, so check it again here. */
|
|
|
|
|
if (! register_operand (operands[0], VOIDmode))
|
|
|
|
|
FAIL;
|
|
|
|
|
})
|
|
|
|
|
|
2005-04-05 13:26:48 +02:00
|
|
|
|
;; This is the main "hook" for PIC code. When generating
|
|
|
|
|
;; PIC, movsi is responsible for determining when the source address
|
|
|
|
|
;; needs PIC relocation and appropriately calling legitimize_pic_address
|
|
|
|
|
;; to perform the actual relocation.
|
|
|
|
|
|
|
|
|
|
(define_expand "movsi"
|
|
|
|
|
[(set (match_operand:SI 0 "nonimmediate_operand" "")
|
|
|
|
|
(match_operand:SI 1 "general_operand" ""))]
|
|
|
|
|
""
|
2006-11-20 13:22:25 +01:00
|
|
|
|
{
|
|
|
|
|
if (expand_move (operands, SImode))
|
|
|
|
|
DONE;
|
|
|
|
|
})
|
2005-04-05 13:26:48 +02:00
|
|
|
|
|
|
|
|
|
(define_expand "movv2hi"
|
|
|
|
|
[(set (match_operand:V2HI 0 "nonimmediate_operand" "")
|
|
|
|
|
(match_operand:V2HI 1 "general_operand" ""))]
|
|
|
|
|
""
|
|
|
|
|
"expand_move (operands, V2HImode);")
|
|
|
|
|
|
|
|
|
|
(define_expand "movdi"
|
|
|
|
|
[(set (match_operand:DI 0 "nonimmediate_operand" "")
|
|
|
|
|
(match_operand:DI 1 "general_operand" ""))]
|
|
|
|
|
""
|
|
|
|
|
"expand_move (operands, DImode);")
|
|
|
|
|
|
|
|
|
|
(define_expand "movsf"
|
|
|
|
|
[(set (match_operand:SF 0 "nonimmediate_operand" "")
|
|
|
|
|
(match_operand:SF 1 "general_operand" ""))]
|
|
|
|
|
""
|
|
|
|
|
"expand_move (operands, SFmode);")
|
|
|
|
|
|
|
|
|
|
(define_expand "movdf"
|
|
|
|
|
[(set (match_operand:DF 0 "nonimmediate_operand" "")
|
|
|
|
|
(match_operand:DF 1 "general_operand" ""))]
|
|
|
|
|
""
|
|
|
|
|
"expand_move (operands, DFmode);")
|
|
|
|
|
|
|
|
|
|
(define_expand "movhi"
|
|
|
|
|
[(set (match_operand:HI 0 "nonimmediate_operand" "")
|
|
|
|
|
(match_operand:HI 1 "general_operand" ""))]
|
|
|
|
|
""
|
|
|
|
|
"expand_move (operands, HImode);")
|
|
|
|
|
|
|
|
|
|
(define_expand "movqi"
|
|
|
|
|
[(set (match_operand:QI 0 "nonimmediate_operand" "")
|
|
|
|
|
(match_operand:QI 1 "general_operand" ""))]
|
|
|
|
|
""
|
|
|
|
|
" expand_move (operands, QImode); ")
|
|
|
|
|
|
|
|
|
|
;; Some define_splits to break up SI/SFmode loads of immediate constants.
|
|
|
|
|
|
|
|
|
|
(define_split
|
|
|
|
|
[(set (match_operand:SI 0 "register_operand" "")
|
|
|
|
|
(match_operand:SI 1 "symbolic_or_const_operand" ""))]
|
|
|
|
|
"reload_completed
|
|
|
|
|
/* Always split symbolic operands; split integer constants that are
|
|
|
|
|
too large for a single instruction. */
|
|
|
|
|
&& (GET_CODE (operands[1]) != CONST_INT
|
|
|
|
|
|| (INTVAL (operands[1]) < -32768
|
|
|
|
|
|| INTVAL (operands[1]) >= 65536
|
|
|
|
|
|| (INTVAL (operands[1]) >= 32768 && PREG_P (operands[0]))))"
|
|
|
|
|
[(set (match_dup 0) (high:SI (match_dup 1)))
|
|
|
|
|
(set (match_dup 0) (lo_sum:SI (match_dup 0) (match_dup 1)))]
|
|
|
|
|
{
|
|
|
|
|
if (GET_CODE (operands[1]) == CONST_INT
|
|
|
|
|
&& split_load_immediate (operands))
|
|
|
|
|
DONE;
|
|
|
|
|
/* ??? Do something about TARGET_LOW_64K. */
|
|
|
|
|
})
|
|
|
|
|
|
|
|
|
|
(define_split
|
|
|
|
|
[(set (match_operand:SF 0 "register_operand" "")
|
|
|
|
|
(match_operand:SF 1 "immediate_operand" ""))]
|
|
|
|
|
"reload_completed"
|
|
|
|
|
[(set (match_dup 2) (high:SI (match_dup 3)))
|
|
|
|
|
(set (match_dup 2) (lo_sum:SI (match_dup 2) (match_dup 3)))]
|
|
|
|
|
{
|
|
|
|
|
long values;
|
|
|
|
|
|
bfin.c (emit_link_insn, [...]): Use gcc_assert or gcc_unreachable as appropriate.
* config/bfin/bfin.c (emit_link_insn, effective_address_32bit_p,
print_address_operand, print_operand, legitimize_pic_address,
asm_conditional_branch, bfin_gen_compare, output_push_multiple,
output_pop_multiple): Use gcc_assert or gcc_unreachable as
appropriate.
* config/bfin/bfin.md (movsf splitter, beq, bne): Likewise.
Co-Authored-By: Bernd Schmidt <bernd.schmidt@analog.com>
From-SVN: r99096
2005-05-02 16:29:44 +02:00
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gcc_assert (GET_CODE (operands[1]) == CONST_DOUBLE);
|
2005-04-05 13:26:48 +02:00
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|
Remove REAL_VALUE_FROM_CONST_DOUBLE
To maintain symmetry after the previous removal of
CONST_DOUBLE_FROM_REAL_VALUE, this patch also gets rid of
REAL_VALUE_FROM_CONST_DOUBLE. All the macro did was copy the
contents of CONST_DOUBLE_REAL_VALUE into a temporary real_value
structure. In many cases there was no need for this temporary
and we could simply use the CONST_DOUBLE_REAL_VALUE directly.
For that reason this patch is less automatic than the others.
Bootstrapped & regression-tested on x86_64-linux-gnu. Also tested by
building one target per CPU directory and checking that there were
no new warnings and no changes in testsuite output at -O2.
gcc/
* real.h (REAL_VALUE_FROM_CONST_DOUBLE): Delete.
* config/aarch64/aarch64.c (aarch64_float_const_zero_rtx_p)
(aarch64_print_operand, aarch64_float_const_representable_p)
(aarch64_output_simd_mov_immediate): Use CONST_DOUBLE_REAL_VALUE
instead of REAL_VALUE_FROM_CONST_DOUBLE.
* config/arc/arc.c (arc_print_operand): Likewise.
* config/arm/arm.c (arm_const_double_rtx, vfp3_const_double_index)
(neon_valid_immediate, arm_print_operand, arm_emit_fp16_const)
(vfp3_const_double_for_fract_bits, vfp3_const_double_for_bits):
Likewise.
* config/arm/arm.md (*arm32_movhf, consttable_4, consttable_8)
(consttable_16): Likewise.
* config/arm/vfp.md (*movhf_vfp_neon, *movhf_vfp): Likewise.
* config/avr/avr.c (avr_print_operand): Likewise.
* config/bfin/bfin.md: Likewise (in a define_split).
* config/c6x/c6x.md: Likewise (in a define_split).
* config/cr16/cr16.c (cr16_const_double_ok): Likewise.
(cr16_print_operand): Likewise.
* config/cris/cris.c (cris_print_operand): Likewise.
* config/epiphany/epiphany.c (epiphany_print_operand): Likewise.
* config/fr30/fr30.c (fr30_print_operand): Likewise.
(fr30_const_double_is_zero): Likewise.
* config/frv/frv.c (frv_print_operand, output_move_single): Likewise.
* config/frv/frv.md: Likewise (in a define_split).
* config/frv/predicates.md (int_2word_operand): Likewise.
* config/h8300/h8300.c (h8300_print_operand): Likewise.
* config/i386/i386.c (standard_80387_constant_p): Likewise.
(ix86_print_operand, ix86_split_to_parts): Likewise.
* config/i386/i386.md: Likewise (in a define_split).
* config/ia64/ia64.c (ia64_split_tmode, ia64_print_operand): Likewise.
* config/iq2000/iq2000.md (movsf_lo_sum, movsf_high): Likewise.
* config/m32r/m32r.c (easy_df_const, m32r_print_operand): Likewise.
* config/m68k/m68k.c (handle_move_double, standard_68881_constant_p)
(print_operand): Likewise.
* config/m68k/m68k.md (movsf_cf_hard, movdf_cf_hard): Likewise.
* config/mep/mep.md: Likewise (in define_split).
* config/microblaze/microblaze.c (microblaze_const_double_ok)
(print_operand): Likewise.
* config/mips/mips.md (consttable_float): Likewise.
* config/mmix/mmix.c (mmix_intval): Likewise.
* config/mn10300/mn10300.c (mn10300_print_operand): Likewise.
* config/nvptx/nvptx.c (nvptx_print_operand): Likewise.
* config/pa/pa.c (pa_singlemove_string): Likewise.
* config/pdp11/pdp11.c (pdp11_expand_operands): Likewise.
(pdp11_asm_print_operand, legitimate_const_double_p): Likewise.
* config/rs6000/rs6000.c (num_insns_constant, rs6000_emit_cmove)
(output_toc): Likewise.
* config/rs6000/rs6000.md: Likewise (in define_splits).
* config/rx/rx.c (rx_print_operand): Likewise.
* config/s390/s390.c (s390_output_pool_entry): Likewise.
* config/sh/sh.c (fp_zero_operand, fp_one_operand): Likewise.
* config/sh/sh.md (consttable_sf, consttable_df): Likewise
(and also in define_splits).
* config/sparc/sparc.c (fp_sethi_p, fp_mov_p): Likewise.
(fp_high_losum_p): Likewise.
* config/sparc/sparc.md (*movsf_insn, *movsf_lo_sum): Likewise.
(*movsf_high): Likewise.
* config/spu/spu.c (const_double_to_hwint): Likewise.
* config/v850/v850.c (const_double_split): Likewise.
* config/vax/vax.c (vax_float_literal): Likewise.
* config/visium/visium.c (visium_expand_copysign): Likewise.
* config/visium/visium.md: Likewise (in define_split).
* config/xtensa/predicates.md (const_float_1_operand): Likewise.
* config/xtensa/xtensa.c (print_operand): Likewise.
(xtensa_output_literal): Likewise.
* cprop.c (implicit_set_cond_p): Likewise.
* dwarf2out.c (insert_float): Likewise.
* expmed.c (expand_mult, make_tree): Likewise.
* expr.c (compress_float_constant): Likewise.
* rtlanal.c (split_double): Likewise.
* simplify-rtx.c (avoid_constant_pool_reference): Likewise.
(simplify_const_unary_operation, simplify_binary_operation_1)
(simplify_const_binary_operation): Likewise.
(simplify_const_relational_operation): Likewise.
* varasm.c (output_constant_pool_2): Likewise.
From-SVN: r228478
2015-10-05 13:37:49 +02:00
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REAL_VALUE_TO_TARGET_SINGLE (*CONST_DOUBLE_REAL_VALUE (operands[1]), values);
|
2005-04-05 13:26:48 +02:00
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operands[2] = gen_rtx_REG (SImode, true_regnum (operands[0]));
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operands[3] = GEN_INT (trunc_int_for_mode (values, SImode));
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if (values >= -32768 && values < 65536)
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{
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emit_move_insn (operands[2], operands[3]);
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DONE;
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}
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if (split_load_immediate (operands + 2))
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DONE;
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})
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;; Sadly, this can't be a proper named movstrict pattern, since the compiler
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;; expects to be able to use registers for operand 1.
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;; Note that the asm instruction is defined by the manual to take an unsigned
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;; constant, but it doesn't matter to the assembler, and the compiler only
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;; deals with sign-extended constants. Hence "Ksh".
|
genmodes.c (make_vector_mode): Allow making VECTOR_MODE_INT of a MODE_PARTIAL_INT mode.
* genmodes.c (make_vector_mode): Allow making VECTOR_MODE_INT of a
MODE_PARTIAL_INT mode.
* config/bfin/bfin-modes.def: Add V2PDI and V2SI.
* config/bfin/bfin.c (print_operand): Add macflag and mac/msu modifiers
for CONST_INTs.
(hard_regno_mode_ok): V2PDImode is ok for accumulators.
* config/bfin/bfin.h (CLASS_MAX_NREGS, HARD_REGNO_NREGS): Handle
V2PDImode.
* config/bfin/predicates.md (const01_operand, vec_shift_operand):
New predicates.
* config/bfin/bfin.md (UNSPEC_MUL_WITH_FLAG, UNSPEC_MAC_WITH_FLAG):
New constants.
(MACFLAG_NONE, MACFLAG_T, MACFLAG_FU, MACFLAG_TFU, MACFLAG_IS,
MACFLAG_IU, MACFLAG_W32, MACFLAG_M, MACFLAG_S2RND, MACFLAG_ISS2,
MACFLAG_IH): Likewise.
(movstricthi_1): Renamed from "*movstricthi".
(load_accumulator, load_accumulator_pair, movsi_insv, insv,
ssaddsi3, sssubsi3, ssnegsi2, signbitssi2, smaxhi3, sminhi3,
abshi2, neghi2, ssneghi2, signbitshi2, movhi_low2high,
movhi_high2high, movhi_low2low, movhi_high2low, movhiv2hi_low,
movhiv2hi_high, composev2hi, movv2hi_hi, movv2hi_hi_low,
movv2hi_hi_high, ssaddhi3, sssubhi3, ssaddv2hi3, sssubv2hi3,
addsubv2hi3, subaddv2hi3, ssaddsubv2hi3, sssubaddv2hi3,
sublohiv2hi3, subhilov2hi3, sssublohiv2hi3, sssubhilov2hi3,
addlohiv2hi3, addhilov2hi3, ssaddlohiv2hi3, ssaddhilov2hi3,
mulhisi_ll, mulhisi_lh, mulhisi_hl, mulhisi_hh, ssnegv2hi2,
ssashiftv2hi3, ssashifthi3, lshiftv2hi3, lshifthi3, packv2hi,
flag_mulhi, flag_mulhisi_parts, flag_machi, flag_machi_acconly,
flag_macinithi, flag_macinit1hi, flag_mulv2hi, flag_mulv2hi_parts,
flag_macv2hi_parts, flag_macv2hi_parts_acconly,
flag_macinitv2hi_parts, flag_macinit1v2hi_parts): New patterns.
From-SVN: r113245
2006-04-25 13:49:27 +02:00
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(define_insn "movstricthi_1"
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2005-04-05 13:26:48 +02:00
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[(set (strict_low_part (match_operand:HI 0 "register_operand" "+x"))
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(match_operand:HI 1 "immediate_operand" "Ksh"))]
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""
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"%h0 = %1;"
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[(set_attr "type" "mvi")
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(set_attr "length" "4")])
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;; Sign and zero extensions
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bfin-protos.h (bfin_dsp_memref_p): Declare.
* config/bfin/bfin-protos.h (bfin_dsp_memref_p): Declare.
* config/bfin/bfin.c (bfin_dsp_memref_p): New function.
(bfin_valid_reg_p): Test for pseudos explicitly and use only
REGNO_MODE_CODE_OK_FOR_BASE_P. New args MODE and OUTER_CODE; all
callers changed.
* config/bfin/bfin.h (PREG_P): Use P_REGNO_P.
(IREG_P, P_REGNO_P, I_REGNO_P): New macros.
(enum reg_class, REG_CLASS_CONTENTS): Add IPREGS.
(BASE_REG_CLASS, REG_OK_FOR_BASE_P, REG_OK_FOR_INDEX_P,
REGNO_OK_FOR_BASE_STRICT_P, REGNO_OK_FOR_BASE_NONSTRICT_P): Delete
macros.
(IREG_POSSIBLE_P, MODE_CODE_BASE_REG_CLASS,
REGNO_MODE_CODE_OK_FOR_BASE_P): New macros.
(REGNO_REG_CLASS): ARGP is in PREGS.
* config/bfin/bfin.md (movhi_insn): Allow for addresses containing
IREGS.
(zero_extendhisi2, extendhisi2): Likewise; changed to define_and_split
to deal with those addresses.
* addresses.h: New file.
* caller-save.c: Include "addresses.h".
(init_caller_save): Use new base_reg_class function.
* rtl-factoring.c: Include "addresses.h".
(recompute_gain_for_pattern_seq): Use new function ok_for_base_p_1.
* recog.c: Include "addresses.h".
(preprocess_constraints): Use new base_reg_class function.
* regrename.c: Include "addresses.h".
(scan_rtx_address): Use new regno_ok_for_base_p and base_reg_class
functions. Keep track of a new var INDEX_CODE to compute valid
classes.
(replace_oldest_value_addr): Likewise.
(replace_oldest_value_mem): Use base_reg_class.
* reload.c: Include "addresses.h".
(REGNO_MODE_OK_FOR_BASE_P, REG_MODE_OK_FOR_BASE_P): Delete macros.
(find_reloads): Use new base_reg_class function.
(find_reloads_address): Likewise; also use regno_ok_for_base_p.
(find_reloads_address_1): Likewise. New args OUTER_CODE and INDEX_CODE;
all callers and prototype changed.
* reload1.c: Include "addresses.h".
(maybe_fix_stack_asms): Use base_reg_class.
* regclass.c: Include "addresses.h".
(ok_for_index_p_nonstrict, ok_for_base_p_nonstrict): New functions.
(init_reg_autoinc): Use new base_reg_class function.
(record_reg_classes): Likewise.
(record_address_regs): Delete arg CLASS; add args CONTEXT, MODE,
OUTER_CODE and INDEX_CODE. All callers and prototype changed.
Use new args to compute necessary class.
* Makefile.in (regclass.o, reload.o, reload1.o, caller-save.o, recog.o,
regrename.o, rtl-factoring.o): Update dependencies.
* doc/tm.texi (MODE_CODE_BASE_REG_CLASS): Document.
(REGNO_MODE_CODE_OK_FOR_BASE_P): Likewise.
(REG_OK_FOR_BASE_P, REG_MODE_OK_FOR_BASE_P, REG_MODE_OK_FOR_REG_BASE_P,
REG_OK_FOR_INDEX_P): Delete documentation.
From-SVN: r112248
2006-03-21 14:07:33 +01:00
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(define_insn_and_split "extendhisi2"
|
2005-04-05 13:26:48 +02:00
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[(set (match_operand:SI 0 "register_operand" "=d, d")
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(sign_extend:SI (match_operand:HI 1 "nonimmediate_operand" "d, m")))]
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""
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"@
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%0 = %h1 (X);
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rtlanal.c (note_uses): Deal with SEQUENCEs.
* rtlanal.c (note_uses): Deal with SEQUENCEs.
* config/bfin/bfin.c: Include "timevar.h".
(bfin_flag_schedule_insns2, splitting_for_sched,
bfin_flag_var_tracking): New variables.
(print_operand): Handle '%!'.
(override_options): Disable normal sched2 pass, instead set
bfin_flag_schedule_insns2 for reorg to handle it.
(output_file_start): Likewise for var-tracking.
(bfin_optimize_loop): Take some care not to stumble over SEQUENCEs.
(gen_one_bundle, bfin_gen_bundles, type_for_anomaly, trapping_loads_p):
New functions.
(bfin_reorg): Do second scheduling pass here, and call
bfin_gen_bundles. Use type_for_anomaly and trapping_loads_p instead
of examining insns directly. If bfin_flag_var_tracking, call
var-tracking pass when done with everything else.
* config/bfin/bfin.h (PRINT_OPERAND_PUNCT_VALID_P): '!' is valid.
* config/bfin/bfin.md (UNSPEC_32BIT): New constant.
(movsi_insn32): New pattern, with two new splits to create it
before the final scheduling pass.
(neghi2): Not a dsp32 insn, rather alu0.
(movbi, pushsi_insn, popsi_insn, movsi_insn, movv2hi_insn, movhi_insn,
movqi_insn, movsf_insn, movsi_insv, extendhisi2, zero_extendhisi2,
extendqihi2, extendqisi2, zero_extendqihi2, zero_extendqisi2,
mulhisi3, umulhisi3, ssadsi3, sssubsi3, smaxsi3, sminsi3, abssi2,
ssnegsi2, signbitssi2, smaxhi3, sminhi3, abshi2, ssneghi2, signbitshi2,
movhi_low2high, movhi_high2high, movhi_low2low, movhi_high2low,
movhiv2hi_low, movhiv2hi_high, composev2hi, packv2hi, movv2hi_hi,
ssaddhi3, sssubhi3, addv2hi3, ssaddv2hi3, subv2hi3, sssubv2hi3,
addsubv2hi3, subaddv2hi3, ssaddsubv2hi3, sssubaddv2hi3, sublohiv2hi3,
subhilov2hi3, sssublohiv2hi3, sssubhilov2hi3, addlohiv2hi3,
addhilov2hi3, ssaddlohiv2hi3, ssaddhilov2hi3, sminv2hi3, smaxv2hi3,
flag_mulhi, flag_mulhisi, flag_mulhisi_parts, flag_machi,
flag_machi_acconly, flag_macinithi, flag_macinit1hi, mulv2hi3,
flag_mulv2hi, flag_mulv2hi_parts, flag_macv2hi_parts,
flag_macv2hi_parts_acconly, flag_macinitv2hi_parts,
flag_macinit1v2hi_parts, mulhisi_ll, mulhisi_lh, mulhisi_hl,
mulhisi_hh, ssnegv2hi2, absv2hi2, ssashiftv2hi3, ssashifthi3,
lshiftv2hi3, lshifthi3): Use '%!' to terminate all dsp32/load/store
variants instead of ';'.
(ror_one, rol_one): Likewise. Make them dsp32 insns.
(ashlsi3_insn, ashrsi3, lshrsi3): Add dsp32 variants.
(align8, align16, align24): Now named patterns; also using '%!'.
(mnop): New insn.
From-SVN: r119534
2006-12-05 09:49:56 +01:00
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%0 = W %h1 (X)%!"
|
bfin-protos.h (bfin_dsp_memref_p): Declare.
* config/bfin/bfin-protos.h (bfin_dsp_memref_p): Declare.
* config/bfin/bfin.c (bfin_dsp_memref_p): New function.
(bfin_valid_reg_p): Test for pseudos explicitly and use only
REGNO_MODE_CODE_OK_FOR_BASE_P. New args MODE and OUTER_CODE; all
callers changed.
* config/bfin/bfin.h (PREG_P): Use P_REGNO_P.
(IREG_P, P_REGNO_P, I_REGNO_P): New macros.
(enum reg_class, REG_CLASS_CONTENTS): Add IPREGS.
(BASE_REG_CLASS, REG_OK_FOR_BASE_P, REG_OK_FOR_INDEX_P,
REGNO_OK_FOR_BASE_STRICT_P, REGNO_OK_FOR_BASE_NONSTRICT_P): Delete
macros.
(IREG_POSSIBLE_P, MODE_CODE_BASE_REG_CLASS,
REGNO_MODE_CODE_OK_FOR_BASE_P): New macros.
(REGNO_REG_CLASS): ARGP is in PREGS.
* config/bfin/bfin.md (movhi_insn): Allow for addresses containing
IREGS.
(zero_extendhisi2, extendhisi2): Likewise; changed to define_and_split
to deal with those addresses.
* addresses.h: New file.
* caller-save.c: Include "addresses.h".
(init_caller_save): Use new base_reg_class function.
* rtl-factoring.c: Include "addresses.h".
(recompute_gain_for_pattern_seq): Use new function ok_for_base_p_1.
* recog.c: Include "addresses.h".
(preprocess_constraints): Use new base_reg_class function.
* regrename.c: Include "addresses.h".
(scan_rtx_address): Use new regno_ok_for_base_p and base_reg_class
functions. Keep track of a new var INDEX_CODE to compute valid
classes.
(replace_oldest_value_addr): Likewise.
(replace_oldest_value_mem): Use base_reg_class.
* reload.c: Include "addresses.h".
(REGNO_MODE_OK_FOR_BASE_P, REG_MODE_OK_FOR_BASE_P): Delete macros.
(find_reloads): Use new base_reg_class function.
(find_reloads_address): Likewise; also use regno_ok_for_base_p.
(find_reloads_address_1): Likewise. New args OUTER_CODE and INDEX_CODE;
all callers and prototype changed.
* reload1.c: Include "addresses.h".
(maybe_fix_stack_asms): Use base_reg_class.
* regclass.c: Include "addresses.h".
(ok_for_index_p_nonstrict, ok_for_base_p_nonstrict): New functions.
(init_reg_autoinc): Use new base_reg_class function.
(record_reg_classes): Likewise.
(record_address_regs): Delete arg CLASS; add args CONTEXT, MODE,
OUTER_CODE and INDEX_CODE. All callers and prototype changed.
Use new args to compute necessary class.
* Makefile.in (regclass.o, reload.o, reload1.o, caller-save.o, recog.o,
regrename.o, rtl-factoring.o): Update dependencies.
* doc/tm.texi (MODE_CODE_BASE_REG_CLASS): Document.
(REGNO_MODE_CODE_OK_FOR_BASE_P): Likewise.
(REG_OK_FOR_BASE_P, REG_MODE_OK_FOR_BASE_P, REG_MODE_OK_FOR_REG_BASE_P,
REG_OK_FOR_INDEX_P): Delete documentation.
From-SVN: r112248
2006-03-21 14:07:33 +01:00
|
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"reload_completed && bfin_dsp_memref_p (operands[1])"
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[(set (match_dup 2) (match_dup 1))
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(set (match_dup 0) (sign_extend:SI (match_dup 2)))]
|
|
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|
|
{
|
|
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|
operands[2] = gen_lowpart (HImode, operands[0]);
|
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|
}
|
2005-04-05 13:26:48 +02:00
|
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|
[(set_attr "type" "alu0,mcld")])
|
|
|
|
|
|
bfin-protos.h (bfin_dsp_memref_p): Declare.
* config/bfin/bfin-protos.h (bfin_dsp_memref_p): Declare.
* config/bfin/bfin.c (bfin_dsp_memref_p): New function.
(bfin_valid_reg_p): Test for pseudos explicitly and use only
REGNO_MODE_CODE_OK_FOR_BASE_P. New args MODE and OUTER_CODE; all
callers changed.
* config/bfin/bfin.h (PREG_P): Use P_REGNO_P.
(IREG_P, P_REGNO_P, I_REGNO_P): New macros.
(enum reg_class, REG_CLASS_CONTENTS): Add IPREGS.
(BASE_REG_CLASS, REG_OK_FOR_BASE_P, REG_OK_FOR_INDEX_P,
REGNO_OK_FOR_BASE_STRICT_P, REGNO_OK_FOR_BASE_NONSTRICT_P): Delete
macros.
(IREG_POSSIBLE_P, MODE_CODE_BASE_REG_CLASS,
REGNO_MODE_CODE_OK_FOR_BASE_P): New macros.
(REGNO_REG_CLASS): ARGP is in PREGS.
* config/bfin/bfin.md (movhi_insn): Allow for addresses containing
IREGS.
(zero_extendhisi2, extendhisi2): Likewise; changed to define_and_split
to deal with those addresses.
* addresses.h: New file.
* caller-save.c: Include "addresses.h".
(init_caller_save): Use new base_reg_class function.
* rtl-factoring.c: Include "addresses.h".
(recompute_gain_for_pattern_seq): Use new function ok_for_base_p_1.
* recog.c: Include "addresses.h".
(preprocess_constraints): Use new base_reg_class function.
* regrename.c: Include "addresses.h".
(scan_rtx_address): Use new regno_ok_for_base_p and base_reg_class
functions. Keep track of a new var INDEX_CODE to compute valid
classes.
(replace_oldest_value_addr): Likewise.
(replace_oldest_value_mem): Use base_reg_class.
* reload.c: Include "addresses.h".
(REGNO_MODE_OK_FOR_BASE_P, REG_MODE_OK_FOR_BASE_P): Delete macros.
(find_reloads): Use new base_reg_class function.
(find_reloads_address): Likewise; also use regno_ok_for_base_p.
(find_reloads_address_1): Likewise. New args OUTER_CODE and INDEX_CODE;
all callers and prototype changed.
* reload1.c: Include "addresses.h".
(maybe_fix_stack_asms): Use base_reg_class.
* regclass.c: Include "addresses.h".
(ok_for_index_p_nonstrict, ok_for_base_p_nonstrict): New functions.
(init_reg_autoinc): Use new base_reg_class function.
(record_reg_classes): Likewise.
(record_address_regs): Delete arg CLASS; add args CONTEXT, MODE,
OUTER_CODE and INDEX_CODE. All callers and prototype changed.
Use new args to compute necessary class.
* Makefile.in (regclass.o, reload.o, reload1.o, caller-save.o, recog.o,
regrename.o, rtl-factoring.o): Update dependencies.
* doc/tm.texi (MODE_CODE_BASE_REG_CLASS): Document.
(REGNO_MODE_CODE_OK_FOR_BASE_P): Likewise.
(REG_OK_FOR_BASE_P, REG_MODE_OK_FOR_BASE_P, REG_MODE_OK_FOR_REG_BASE_P,
REG_OK_FOR_INDEX_P): Delete documentation.
From-SVN: r112248
2006-03-21 14:07:33 +01:00
|
|
|
|
(define_insn_and_split "zero_extendhisi2"
|
2005-04-05 13:26:48 +02:00
|
|
|
|
[(set (match_operand:SI 0 "register_operand" "=d, d")
|
|
|
|
|
(zero_extend:SI (match_operand:HI 1 "nonimmediate_operand" "d, m")))]
|
|
|
|
|
""
|
|
|
|
|
"@
|
|
|
|
|
%0 = %h1 (Z);
|
rtlanal.c (note_uses): Deal with SEQUENCEs.
* rtlanal.c (note_uses): Deal with SEQUENCEs.
* config/bfin/bfin.c: Include "timevar.h".
(bfin_flag_schedule_insns2, splitting_for_sched,
bfin_flag_var_tracking): New variables.
(print_operand): Handle '%!'.
(override_options): Disable normal sched2 pass, instead set
bfin_flag_schedule_insns2 for reorg to handle it.
(output_file_start): Likewise for var-tracking.
(bfin_optimize_loop): Take some care not to stumble over SEQUENCEs.
(gen_one_bundle, bfin_gen_bundles, type_for_anomaly, trapping_loads_p):
New functions.
(bfin_reorg): Do second scheduling pass here, and call
bfin_gen_bundles. Use type_for_anomaly and trapping_loads_p instead
of examining insns directly. If bfin_flag_var_tracking, call
var-tracking pass when done with everything else.
* config/bfin/bfin.h (PRINT_OPERAND_PUNCT_VALID_P): '!' is valid.
* config/bfin/bfin.md (UNSPEC_32BIT): New constant.
(movsi_insn32): New pattern, with two new splits to create it
before the final scheduling pass.
(neghi2): Not a dsp32 insn, rather alu0.
(movbi, pushsi_insn, popsi_insn, movsi_insn, movv2hi_insn, movhi_insn,
movqi_insn, movsf_insn, movsi_insv, extendhisi2, zero_extendhisi2,
extendqihi2, extendqisi2, zero_extendqihi2, zero_extendqisi2,
mulhisi3, umulhisi3, ssadsi3, sssubsi3, smaxsi3, sminsi3, abssi2,
ssnegsi2, signbitssi2, smaxhi3, sminhi3, abshi2, ssneghi2, signbitshi2,
movhi_low2high, movhi_high2high, movhi_low2low, movhi_high2low,
movhiv2hi_low, movhiv2hi_high, composev2hi, packv2hi, movv2hi_hi,
ssaddhi3, sssubhi3, addv2hi3, ssaddv2hi3, subv2hi3, sssubv2hi3,
addsubv2hi3, subaddv2hi3, ssaddsubv2hi3, sssubaddv2hi3, sublohiv2hi3,
subhilov2hi3, sssublohiv2hi3, sssubhilov2hi3, addlohiv2hi3,
addhilov2hi3, ssaddlohiv2hi3, ssaddhilov2hi3, sminv2hi3, smaxv2hi3,
flag_mulhi, flag_mulhisi, flag_mulhisi_parts, flag_machi,
flag_machi_acconly, flag_macinithi, flag_macinit1hi, mulv2hi3,
flag_mulv2hi, flag_mulv2hi_parts, flag_macv2hi_parts,
flag_macv2hi_parts_acconly, flag_macinitv2hi_parts,
flag_macinit1v2hi_parts, mulhisi_ll, mulhisi_lh, mulhisi_hl,
mulhisi_hh, ssnegv2hi2, absv2hi2, ssashiftv2hi3, ssashifthi3,
lshiftv2hi3, lshifthi3): Use '%!' to terminate all dsp32/load/store
variants instead of ';'.
(ror_one, rol_one): Likewise. Make them dsp32 insns.
(ashlsi3_insn, ashrsi3, lshrsi3): Add dsp32 variants.
(align8, align16, align24): Now named patterns; also using '%!'.
(mnop): New insn.
From-SVN: r119534
2006-12-05 09:49:56 +01:00
|
|
|
|
%0 = W %h1 (Z)%!"
|
bfin-protos.h (bfin_dsp_memref_p): Declare.
* config/bfin/bfin-protos.h (bfin_dsp_memref_p): Declare.
* config/bfin/bfin.c (bfin_dsp_memref_p): New function.
(bfin_valid_reg_p): Test for pseudos explicitly and use only
REGNO_MODE_CODE_OK_FOR_BASE_P. New args MODE and OUTER_CODE; all
callers changed.
* config/bfin/bfin.h (PREG_P): Use P_REGNO_P.
(IREG_P, P_REGNO_P, I_REGNO_P): New macros.
(enum reg_class, REG_CLASS_CONTENTS): Add IPREGS.
(BASE_REG_CLASS, REG_OK_FOR_BASE_P, REG_OK_FOR_INDEX_P,
REGNO_OK_FOR_BASE_STRICT_P, REGNO_OK_FOR_BASE_NONSTRICT_P): Delete
macros.
(IREG_POSSIBLE_P, MODE_CODE_BASE_REG_CLASS,
REGNO_MODE_CODE_OK_FOR_BASE_P): New macros.
(REGNO_REG_CLASS): ARGP is in PREGS.
* config/bfin/bfin.md (movhi_insn): Allow for addresses containing
IREGS.
(zero_extendhisi2, extendhisi2): Likewise; changed to define_and_split
to deal with those addresses.
* addresses.h: New file.
* caller-save.c: Include "addresses.h".
(init_caller_save): Use new base_reg_class function.
* rtl-factoring.c: Include "addresses.h".
(recompute_gain_for_pattern_seq): Use new function ok_for_base_p_1.
* recog.c: Include "addresses.h".
(preprocess_constraints): Use new base_reg_class function.
* regrename.c: Include "addresses.h".
(scan_rtx_address): Use new regno_ok_for_base_p and base_reg_class
functions. Keep track of a new var INDEX_CODE to compute valid
classes.
(replace_oldest_value_addr): Likewise.
(replace_oldest_value_mem): Use base_reg_class.
* reload.c: Include "addresses.h".
(REGNO_MODE_OK_FOR_BASE_P, REG_MODE_OK_FOR_BASE_P): Delete macros.
(find_reloads): Use new base_reg_class function.
(find_reloads_address): Likewise; also use regno_ok_for_base_p.
(find_reloads_address_1): Likewise. New args OUTER_CODE and INDEX_CODE;
all callers and prototype changed.
* reload1.c: Include "addresses.h".
(maybe_fix_stack_asms): Use base_reg_class.
* regclass.c: Include "addresses.h".
(ok_for_index_p_nonstrict, ok_for_base_p_nonstrict): New functions.
(init_reg_autoinc): Use new base_reg_class function.
(record_reg_classes): Likewise.
(record_address_regs): Delete arg CLASS; add args CONTEXT, MODE,
OUTER_CODE and INDEX_CODE. All callers and prototype changed.
Use new args to compute necessary class.
* Makefile.in (regclass.o, reload.o, reload1.o, caller-save.o, recog.o,
regrename.o, rtl-factoring.o): Update dependencies.
* doc/tm.texi (MODE_CODE_BASE_REG_CLASS): Document.
(REGNO_MODE_CODE_OK_FOR_BASE_P): Likewise.
(REG_OK_FOR_BASE_P, REG_MODE_OK_FOR_BASE_P, REG_MODE_OK_FOR_REG_BASE_P,
REG_OK_FOR_INDEX_P): Delete documentation.
From-SVN: r112248
2006-03-21 14:07:33 +01:00
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|
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"reload_completed && bfin_dsp_memref_p (operands[1])"
|
|
|
|
|
[(set (match_dup 2) (match_dup 1))
|
|
|
|
|
(set (match_dup 0) (zero_extend:SI (match_dup 2)))]
|
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{
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|
operands[2] = gen_lowpart (HImode, operands[0]);
|
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}
|
2005-04-05 13:26:48 +02:00
|
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[(set_attr "type" "alu0,mcld")])
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(define_insn "zero_extendbisi2"
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[(set (match_operand:SI 0 "register_operand" "=d")
|
|
|
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|
(zero_extend:SI (match_operand:BI 1 "nonimmediate_operand" "C")))]
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""
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"%0 = %1;"
|
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[(set_attr "type" "compare")])
|
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|
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|
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|
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(define_insn "extendqihi2"
|
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[(set (match_operand:HI 0 "register_operand" "=d, d")
|
|
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(sign_extend:HI (match_operand:QI 1 "nonimmediate_operand" "m, d")))]
|
|
|
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|
""
|
|
|
|
|
"@
|
rtlanal.c (note_uses): Deal with SEQUENCEs.
* rtlanal.c (note_uses): Deal with SEQUENCEs.
* config/bfin/bfin.c: Include "timevar.h".
(bfin_flag_schedule_insns2, splitting_for_sched,
bfin_flag_var_tracking): New variables.
(print_operand): Handle '%!'.
(override_options): Disable normal sched2 pass, instead set
bfin_flag_schedule_insns2 for reorg to handle it.
(output_file_start): Likewise for var-tracking.
(bfin_optimize_loop): Take some care not to stumble over SEQUENCEs.
(gen_one_bundle, bfin_gen_bundles, type_for_anomaly, trapping_loads_p):
New functions.
(bfin_reorg): Do second scheduling pass here, and call
bfin_gen_bundles. Use type_for_anomaly and trapping_loads_p instead
of examining insns directly. If bfin_flag_var_tracking, call
var-tracking pass when done with everything else.
* config/bfin/bfin.h (PRINT_OPERAND_PUNCT_VALID_P): '!' is valid.
* config/bfin/bfin.md (UNSPEC_32BIT): New constant.
(movsi_insn32): New pattern, with two new splits to create it
before the final scheduling pass.
(neghi2): Not a dsp32 insn, rather alu0.
(movbi, pushsi_insn, popsi_insn, movsi_insn, movv2hi_insn, movhi_insn,
movqi_insn, movsf_insn, movsi_insv, extendhisi2, zero_extendhisi2,
extendqihi2, extendqisi2, zero_extendqihi2, zero_extendqisi2,
mulhisi3, umulhisi3, ssadsi3, sssubsi3, smaxsi3, sminsi3, abssi2,
ssnegsi2, signbitssi2, smaxhi3, sminhi3, abshi2, ssneghi2, signbitshi2,
movhi_low2high, movhi_high2high, movhi_low2low, movhi_high2low,
movhiv2hi_low, movhiv2hi_high, composev2hi, packv2hi, movv2hi_hi,
ssaddhi3, sssubhi3, addv2hi3, ssaddv2hi3, subv2hi3, sssubv2hi3,
addsubv2hi3, subaddv2hi3, ssaddsubv2hi3, sssubaddv2hi3, sublohiv2hi3,
subhilov2hi3, sssublohiv2hi3, sssubhilov2hi3, addlohiv2hi3,
addhilov2hi3, ssaddlohiv2hi3, ssaddhilov2hi3, sminv2hi3, smaxv2hi3,
flag_mulhi, flag_mulhisi, flag_mulhisi_parts, flag_machi,
flag_machi_acconly, flag_macinithi, flag_macinit1hi, mulv2hi3,
flag_mulv2hi, flag_mulv2hi_parts, flag_macv2hi_parts,
flag_macv2hi_parts_acconly, flag_macinitv2hi_parts,
flag_macinit1v2hi_parts, mulhisi_ll, mulhisi_lh, mulhisi_hl,
mulhisi_hh, ssnegv2hi2, absv2hi2, ssashiftv2hi3, ssashifthi3,
lshiftv2hi3, lshifthi3): Use '%!' to terminate all dsp32/load/store
variants instead of ';'.
(ror_one, rol_one): Likewise. Make them dsp32 insns.
(ashlsi3_insn, ashrsi3, lshrsi3): Add dsp32 variants.
(align8, align16, align24): Now named patterns; also using '%!'.
(mnop): New insn.
From-SVN: r119534
2006-12-05 09:49:56 +01:00
|
|
|
|
%0 = B %1 (X)%!
|
2005-04-05 13:26:48 +02:00
|
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|
|
%0 = %T1 (X);"
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|
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[(set_attr "type" "mcld,alu0")])
|
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|
|
|
|
|
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(define_insn "extendqisi2"
|
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[(set (match_operand:SI 0 "register_operand" "=d, d")
|
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(sign_extend:SI (match_operand:QI 1 "nonimmediate_operand" "m, d")))]
|
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""
|
|
|
|
|
"@
|
rtlanal.c (note_uses): Deal with SEQUENCEs.
* rtlanal.c (note_uses): Deal with SEQUENCEs.
* config/bfin/bfin.c: Include "timevar.h".
(bfin_flag_schedule_insns2, splitting_for_sched,
bfin_flag_var_tracking): New variables.
(print_operand): Handle '%!'.
(override_options): Disable normal sched2 pass, instead set
bfin_flag_schedule_insns2 for reorg to handle it.
(output_file_start): Likewise for var-tracking.
(bfin_optimize_loop): Take some care not to stumble over SEQUENCEs.
(gen_one_bundle, bfin_gen_bundles, type_for_anomaly, trapping_loads_p):
New functions.
(bfin_reorg): Do second scheduling pass here, and call
bfin_gen_bundles. Use type_for_anomaly and trapping_loads_p instead
of examining insns directly. If bfin_flag_var_tracking, call
var-tracking pass when done with everything else.
* config/bfin/bfin.h (PRINT_OPERAND_PUNCT_VALID_P): '!' is valid.
* config/bfin/bfin.md (UNSPEC_32BIT): New constant.
(movsi_insn32): New pattern, with two new splits to create it
before the final scheduling pass.
(neghi2): Not a dsp32 insn, rather alu0.
(movbi, pushsi_insn, popsi_insn, movsi_insn, movv2hi_insn, movhi_insn,
movqi_insn, movsf_insn, movsi_insv, extendhisi2, zero_extendhisi2,
extendqihi2, extendqisi2, zero_extendqihi2, zero_extendqisi2,
mulhisi3, umulhisi3, ssadsi3, sssubsi3, smaxsi3, sminsi3, abssi2,
ssnegsi2, signbitssi2, smaxhi3, sminhi3, abshi2, ssneghi2, signbitshi2,
movhi_low2high, movhi_high2high, movhi_low2low, movhi_high2low,
movhiv2hi_low, movhiv2hi_high, composev2hi, packv2hi, movv2hi_hi,
ssaddhi3, sssubhi3, addv2hi3, ssaddv2hi3, subv2hi3, sssubv2hi3,
addsubv2hi3, subaddv2hi3, ssaddsubv2hi3, sssubaddv2hi3, sublohiv2hi3,
subhilov2hi3, sssublohiv2hi3, sssubhilov2hi3, addlohiv2hi3,
addhilov2hi3, ssaddlohiv2hi3, ssaddhilov2hi3, sminv2hi3, smaxv2hi3,
flag_mulhi, flag_mulhisi, flag_mulhisi_parts, flag_machi,
flag_machi_acconly, flag_macinithi, flag_macinit1hi, mulv2hi3,
flag_mulv2hi, flag_mulv2hi_parts, flag_macv2hi_parts,
flag_macv2hi_parts_acconly, flag_macinitv2hi_parts,
flag_macinit1v2hi_parts, mulhisi_ll, mulhisi_lh, mulhisi_hl,
mulhisi_hh, ssnegv2hi2, absv2hi2, ssashiftv2hi3, ssashifthi3,
lshiftv2hi3, lshifthi3): Use '%!' to terminate all dsp32/load/store
variants instead of ';'.
(ror_one, rol_one): Likewise. Make them dsp32 insns.
(ashlsi3_insn, ashrsi3, lshrsi3): Add dsp32 variants.
(align8, align16, align24): Now named patterns; also using '%!'.
(mnop): New insn.
From-SVN: r119534
2006-12-05 09:49:56 +01:00
|
|
|
|
%0 = B %1 (X)%!
|
2005-04-05 13:26:48 +02:00
|
|
|
|
%0 = %T1 (X);"
|
|
|
|
|
[(set_attr "type" "mcld,alu0")])
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
(define_insn "zero_extendqihi2"
|
|
|
|
|
[(set (match_operand:HI 0 "register_operand" "=d, d")
|
|
|
|
|
(zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "m, d")))]
|
|
|
|
|
""
|
|
|
|
|
"@
|
rtlanal.c (note_uses): Deal with SEQUENCEs.
* rtlanal.c (note_uses): Deal with SEQUENCEs.
* config/bfin/bfin.c: Include "timevar.h".
(bfin_flag_schedule_insns2, splitting_for_sched,
bfin_flag_var_tracking): New variables.
(print_operand): Handle '%!'.
(override_options): Disable normal sched2 pass, instead set
bfin_flag_schedule_insns2 for reorg to handle it.
(output_file_start): Likewise for var-tracking.
(bfin_optimize_loop): Take some care not to stumble over SEQUENCEs.
(gen_one_bundle, bfin_gen_bundles, type_for_anomaly, trapping_loads_p):
New functions.
(bfin_reorg): Do second scheduling pass here, and call
bfin_gen_bundles. Use type_for_anomaly and trapping_loads_p instead
of examining insns directly. If bfin_flag_var_tracking, call
var-tracking pass when done with everything else.
* config/bfin/bfin.h (PRINT_OPERAND_PUNCT_VALID_P): '!' is valid.
* config/bfin/bfin.md (UNSPEC_32BIT): New constant.
(movsi_insn32): New pattern, with two new splits to create it
before the final scheduling pass.
(neghi2): Not a dsp32 insn, rather alu0.
(movbi, pushsi_insn, popsi_insn, movsi_insn, movv2hi_insn, movhi_insn,
movqi_insn, movsf_insn, movsi_insv, extendhisi2, zero_extendhisi2,
extendqihi2, extendqisi2, zero_extendqihi2, zero_extendqisi2,
mulhisi3, umulhisi3, ssadsi3, sssubsi3, smaxsi3, sminsi3, abssi2,
ssnegsi2, signbitssi2, smaxhi3, sminhi3, abshi2, ssneghi2, signbitshi2,
movhi_low2high, movhi_high2high, movhi_low2low, movhi_high2low,
movhiv2hi_low, movhiv2hi_high, composev2hi, packv2hi, movv2hi_hi,
ssaddhi3, sssubhi3, addv2hi3, ssaddv2hi3, subv2hi3, sssubv2hi3,
addsubv2hi3, subaddv2hi3, ssaddsubv2hi3, sssubaddv2hi3, sublohiv2hi3,
subhilov2hi3, sssublohiv2hi3, sssubhilov2hi3, addlohiv2hi3,
addhilov2hi3, ssaddlohiv2hi3, ssaddhilov2hi3, sminv2hi3, smaxv2hi3,
flag_mulhi, flag_mulhisi, flag_mulhisi_parts, flag_machi,
flag_machi_acconly, flag_macinithi, flag_macinit1hi, mulv2hi3,
flag_mulv2hi, flag_mulv2hi_parts, flag_macv2hi_parts,
flag_macv2hi_parts_acconly, flag_macinitv2hi_parts,
flag_macinit1v2hi_parts, mulhisi_ll, mulhisi_lh, mulhisi_hl,
mulhisi_hh, ssnegv2hi2, absv2hi2, ssashiftv2hi3, ssashifthi3,
lshiftv2hi3, lshifthi3): Use '%!' to terminate all dsp32/load/store
variants instead of ';'.
(ror_one, rol_one): Likewise. Make them dsp32 insns.
(ashlsi3_insn, ashrsi3, lshrsi3): Add dsp32 variants.
(align8, align16, align24): Now named patterns; also using '%!'.
(mnop): New insn.
From-SVN: r119534
2006-12-05 09:49:56 +01:00
|
|
|
|
%0 = B %1 (Z)%!
|
2005-04-05 13:26:48 +02:00
|
|
|
|
%0 = %T1 (Z);"
|
|
|
|
|
[(set_attr "type" "mcld,alu0")])
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
(define_insn "zero_extendqisi2"
|
|
|
|
|
[(set (match_operand:SI 0 "register_operand" "=d, d")
|
|
|
|
|
(zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "m, d")))]
|
|
|
|
|
""
|
|
|
|
|
"@
|
rtlanal.c (note_uses): Deal with SEQUENCEs.
* rtlanal.c (note_uses): Deal with SEQUENCEs.
* config/bfin/bfin.c: Include "timevar.h".
(bfin_flag_schedule_insns2, splitting_for_sched,
bfin_flag_var_tracking): New variables.
(print_operand): Handle '%!'.
(override_options): Disable normal sched2 pass, instead set
bfin_flag_schedule_insns2 for reorg to handle it.
(output_file_start): Likewise for var-tracking.
(bfin_optimize_loop): Take some care not to stumble over SEQUENCEs.
(gen_one_bundle, bfin_gen_bundles, type_for_anomaly, trapping_loads_p):
New functions.
(bfin_reorg): Do second scheduling pass here, and call
bfin_gen_bundles. Use type_for_anomaly and trapping_loads_p instead
of examining insns directly. If bfin_flag_var_tracking, call
var-tracking pass when done with everything else.
* config/bfin/bfin.h (PRINT_OPERAND_PUNCT_VALID_P): '!' is valid.
* config/bfin/bfin.md (UNSPEC_32BIT): New constant.
(movsi_insn32): New pattern, with two new splits to create it
before the final scheduling pass.
(neghi2): Not a dsp32 insn, rather alu0.
(movbi, pushsi_insn, popsi_insn, movsi_insn, movv2hi_insn, movhi_insn,
movqi_insn, movsf_insn, movsi_insv, extendhisi2, zero_extendhisi2,
extendqihi2, extendqisi2, zero_extendqihi2, zero_extendqisi2,
mulhisi3, umulhisi3, ssadsi3, sssubsi3, smaxsi3, sminsi3, abssi2,
ssnegsi2, signbitssi2, smaxhi3, sminhi3, abshi2, ssneghi2, signbitshi2,
movhi_low2high, movhi_high2high, movhi_low2low, movhi_high2low,
movhiv2hi_low, movhiv2hi_high, composev2hi, packv2hi, movv2hi_hi,
ssaddhi3, sssubhi3, addv2hi3, ssaddv2hi3, subv2hi3, sssubv2hi3,
addsubv2hi3, subaddv2hi3, ssaddsubv2hi3, sssubaddv2hi3, sublohiv2hi3,
subhilov2hi3, sssublohiv2hi3, sssubhilov2hi3, addlohiv2hi3,
addhilov2hi3, ssaddlohiv2hi3, ssaddhilov2hi3, sminv2hi3, smaxv2hi3,
flag_mulhi, flag_mulhisi, flag_mulhisi_parts, flag_machi,
flag_machi_acconly, flag_macinithi, flag_macinit1hi, mulv2hi3,
flag_mulv2hi, flag_mulv2hi_parts, flag_macv2hi_parts,
flag_macv2hi_parts_acconly, flag_macinitv2hi_parts,
flag_macinit1v2hi_parts, mulhisi_ll, mulhisi_lh, mulhisi_hl,
mulhisi_hh, ssnegv2hi2, absv2hi2, ssashiftv2hi3, ssashifthi3,
lshiftv2hi3, lshifthi3): Use '%!' to terminate all dsp32/load/store
variants instead of ';'.
(ror_one, rol_one): Likewise. Make them dsp32 insns.
(ashlsi3_insn, ashrsi3, lshrsi3): Add dsp32 variants.
(align8, align16, align24): Now named patterns; also using '%!'.
(mnop): New insn.
From-SVN: r119534
2006-12-05 09:49:56 +01:00
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%0 = B %1 (Z)%!
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2005-04-05 13:26:48 +02:00
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%0 = %T1 (Z);"
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[(set_attr "type" "mcld,alu0")])
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;; DImode logical operations
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|
md.texi (Iterators): Renamed from Macros.
* doc/md.texi (Iterators): Renamed from Macros. All contents
changed to reflect rename of respectively define_code_macro and
define_mode_macro to define_code_iterator and define_mode_iterator.
(Mode Iterators, Code Iterators): Similar.
* read-rtl.c (struct iterator_group, struct iterator_traverse_data)
(uses_mode_iterator_p, apply_mode_iterator, uses_code_iterator_p)
(apply_iterator_to_string, uses_iterator_p, apply_iterator_traverse)
(initialize_iterators, find_iterator, check_code_iterator)
(map_attr_string, apply_mode_maps, apply_iterator_to_rtx, add_mapping)
(read_mapping, read_rtx_1): Similar.
* config/alpha/sync.md, config/alpha/alpha.md, config/frv/frv.md,
config/s390/s390.md, config/m32c/blkmov.md, config/m32c/m32c.md,
config/spu/spu.md, config/sparc/sparc.md, config/sparc/sync.md,
config/i386/i386.md, config/i386/mmx.md, config/i386/sse.md,
config/i386/sync.md, config/crx/crx.md, config/xtensa/xtensa.md,
config/cris/cris.c, config/cris/cris.md, config/ia64/sync.md,
config/ia64/div.md, config/ia64/vect.md, config/ia64/ia64.md,
config/m68k/m68k.md, config/rs6000/spe.md, config/rs6000/altivec.md,
config/rs6000/sync.md, config/rs6000/rs6000.md,
config/arm/vec-common.md, config/arm/neon.md, config/arm/iwmmxt.md,
config/arm/arm.md, config/mips/mips-dsp.md, config/mips/mips.md,
config/vax/vax.md, config/bfin/bfin.md: Similar.
From-SVN: r127715
2007-08-22 22:32:18 +02:00
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(define_code_iterator any_logical [and ior xor])
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2005-04-05 13:26:48 +02:00
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(define_code_attr optab [(and "and")
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(ior "ior")
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(xor "xor")])
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(define_code_attr op [(and "&")
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(ior "|")
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(xor "^")])
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(define_code_attr high_result [(and "0")
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(ior "%H1")
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(xor "%H1")])
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bfin.md (<optab>di3): Now a define_expand which expands logical operations piecewise.
* config/bfin/bfin.md (<optab>di3): Now a define_expand which expands
logical operations piecewise.
(<optab>di_zesidi_di, <optab>di_sesidi_di, negdi2, one_cmpldi2,
zero_extendsidi2, subdi_di_zesidi, subdi_zesidi_di, subdi_di_sesidi,
subdi_sesidi_di): Delete.
(add_with_carry): Produce carry in CC instead of a DREG to shorten
the generated sequence. Allow three-reg add in constraints. Rewrite
the rtl expression for carry to avoid zero_extend of a constant.
(sub_with_carry): New pattern.
(adddi3, subdi3): Change into define_expand. For subtract, generate a
different sequence not involving jumps.
(notbi): Now a named pattern.
From-SVN: r124414
2007-05-04 13:00:00 +02:00
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;; Keep this pattern around to avoid generating NO_CONFLICT blocks.
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(define_expand "<optab>di3"
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2005-04-05 13:26:48 +02:00
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[(set (match_operand:DI 0 "register_operand" "=d")
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(any_logical:DI (match_operand:DI 1 "register_operand" "0")
|
bfin.md (<optab>di3): Now a define_expand which expands logical operations piecewise.
* config/bfin/bfin.md (<optab>di3): Now a define_expand which expands
logical operations piecewise.
(<optab>di_zesidi_di, <optab>di_sesidi_di, negdi2, one_cmpldi2,
zero_extendsidi2, subdi_di_zesidi, subdi_zesidi_di, subdi_di_sesidi,
subdi_sesidi_di): Delete.
(add_with_carry): Produce carry in CC instead of a DREG to shorten
the generated sequence. Allow three-reg add in constraints. Rewrite
the rtl expression for carry to avoid zero_extend of a constant.
(sub_with_carry): New pattern.
(adddi3, subdi3): Change into define_expand. For subtract, generate a
different sequence not involving jumps.
(notbi): Now a named pattern.
From-SVN: r124414
2007-05-04 13:00:00 +02:00
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(match_operand:DI 2 "general_operand" "d")))]
|
2005-04-05 13:26:48 +02:00
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""
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{
|
bfin.md (<optab>di3): Now a define_expand which expands logical operations piecewise.
* config/bfin/bfin.md (<optab>di3): Now a define_expand which expands
logical operations piecewise.
(<optab>di_zesidi_di, <optab>di_sesidi_di, negdi2, one_cmpldi2,
zero_extendsidi2, subdi_di_zesidi, subdi_zesidi_di, subdi_di_sesidi,
subdi_sesidi_di): Delete.
(add_with_carry): Produce carry in CC instead of a DREG to shorten
the generated sequence. Allow three-reg add in constraints. Rewrite
the rtl expression for carry to avoid zero_extend of a constant.
(sub_with_carry): New pattern.
(adddi3, subdi3): Change into define_expand. For subtract, generate a
different sequence not involving jumps.
(notbi): Now a named pattern.
From-SVN: r124414
2007-05-04 13:00:00 +02:00
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rtx hi_half[3], lo_half[3];
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enum insn_code icode = CODE_FOR_<optab>si3;
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if (!reg_overlap_mentioned_p (operands[0], operands[1])
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&& !reg_overlap_mentioned_p (operands[0], operands[2]))
|
rtl.h (emit_clobber, [...]): Declare.
gcc/
* rtl.h (emit_clobber, gen_clobber, emit_use, gen_use): Declare.
* emit-rtl.c (emit_clobber, gen_clobber, emit_use, gen_use): New
functions. Do not emit uses and clobbers of CONCATs; individually
use and clobber their operands.
* builtins.c (expand_builtin_setjmp_receiver): Use emit_clobber,
gen_clobber, emit_use and gen_use.
(expand_builtin_longjmp, expand_builtin_nonlocal_goto): Likewise.
(expand_builtin_return): Likewise.
* cfgbuild.c (count_basic_blocks): Likewise.
* cfgrtl.c (rtl_flow_call_edges_add): Likewise.
* explow.c (emit_stack_restore): Likewise.
* expmed.c (extract_bit_field_1): Likewise.
* expr.c (convert_move, emit_move_complex_parts): Likewise.
(emit_move_multi_word, store_constructor): Likewise.
* function.c (do_clobber_return_reg, do_use_return_reg): Likewise.
(thread_prologue_and_epilogue_insns): Likewise.
* lower-subreg.c (resolve_simple_move): Likewise.
* optabs.c (widen_operand, expand_binop): Likewise.
(expand_doubleword_bswap, emit_no_conflict_block): Likewise.
* reload.c (find_reloads): Likewise.
* reload1.c (eliminate_regs_in_insn): Likewise.
* stmt.c (expand_nl_goto_receiver): Likewise.
* config/alpha/alpha.md (builtin_longjmp): Likewise.
* config/arc/arc.md (*movdi_insn, *movdf_insn): Likewise.
* config/arm/arm.c (arm_load_pic_register): Likewise.
(thumb1_expand_epilogue, thumb_set_return_address): Likewise.
* config/arm/arm.md (untyped_return): Likewise.
* config/arm/linux-elf.h (PROFILE_HOOK): Likewise.
* config/avr/avr.c (expand_prologue): Likewise.
* config/bfin/bfin.c (do_unlink): Likewise.
* config/bfin/bfin.md (<optab>di3, adddi3, subdi3): Likewise.
* config/cris/cris.c (cris_expand_prologue): Likewise.
* config/darwin.c (machopic_indirect_data_reference): Likewise.
(machopic_legitimize_pic_address): Likewise.
* config/frv/frv.c (frv_frame_access, frv_expand_epilogue): Likewise.
(frv_ifcvt_modify_insn, frv_expand_mdpackh_builtin): Likewise.
* config/i386/i386.c (ix86_expand_vector_move_misalign): Likewise.
(ix86_expand_convert_uns_didf_sse): Likewise.
(ix86_expand_vector_init_general): Likewise.
* config/ia64/ia64.md (eh_epilogue): Likewise.
* config/iq2000/iq2000.c (iq2000_expand_epilogue): Likewise.
* config/m32c/m32c.c (m32c_emit_eh_epilogue): Likewise.
* config/m32r/m32r.c (m32r_reload_lr): Likewise.
(config/iq2000/iq2000.c): Likewise.
* config/mips/mips.md (fixuns_truncdfsi2): Likewise.
(fixuns_truncdfdi2, fixuns_truncsfsi2, fixuns_truncsfdi2): Likewise.
(builtin_longjmp): Likewise.
* config/mn10300/mn10300.md (call, call_value): Likewise.
* config/pa/pa.md (nonlocal_goto, nonlocal_longjmp): Likewise.
* config/pdp11/pdp11.md (abshi2): Likewise.
* config/rs6000/rs6000.c (rs6000_emit_move): Likewise.
* config/s390/s390.c (s390_emit_prologue): Likewise.
* config/s390/s390.md (movmem_long, setmem_long): Likewise.
(cmpmem_long, extendsidi2, zero_extendsidi2, udivmoddi4): Likewise.
(builtin_setjmp_receiver, restore_stack_nonlocal): Likewise.
* config/sh/sh.c (prepare_move_operands): Likewise.
(output_stack_adjust, sh_expand_epilogue): Likewise.
(sh_set_return_address, sh_expand_t_scc): Likewise.
* config/sparc/sparc.c (load_pic_register): Likewise.
* config/sparc/sparc.md (untyped_return, nonlocal_goto): Likewise.
* config/spu/spu.c (spu_expand_epilogue): Likewise.
* config/v850/v850.c (expand_epilogue): Likewise.
From-SVN: r136251
2008-06-01 11:47:28 +02:00
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emit_clobber (operands[0]);
|
bfin.md (<optab>di3): Now a define_expand which expands logical operations piecewise.
* config/bfin/bfin.md (<optab>di3): Now a define_expand which expands
logical operations piecewise.
(<optab>di_zesidi_di, <optab>di_sesidi_di, negdi2, one_cmpldi2,
zero_extendsidi2, subdi_di_zesidi, subdi_zesidi_di, subdi_di_sesidi,
subdi_sesidi_di): Delete.
(add_with_carry): Produce carry in CC instead of a DREG to shorten
the generated sequence. Allow three-reg add in constraints. Rewrite
the rtl expression for carry to avoid zero_extend of a constant.
(sub_with_carry): New pattern.
(adddi3, subdi3): Change into define_expand. For subtract, generate a
different sequence not involving jumps.
(notbi): Now a named pattern.
From-SVN: r124414
2007-05-04 13:00:00 +02:00
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split_di (operands, 3, lo_half, hi_half);
|
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if (!(*insn_data[icode].operand[2].predicate) (lo_half[2], SImode))
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lo_half[2] = force_reg (SImode, lo_half[2]);
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emit_insn (GEN_FCN (icode) (lo_half[0], lo_half[1], lo_half[2]));
|
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if (!(*insn_data[icode].operand[2].predicate) (hi_half[2], SImode))
|
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hi_half[2] = force_reg (SImode, hi_half[2]);
|
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emit_insn (GEN_FCN (icode) (hi_half[0], hi_half[1], hi_half[2]));
|
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DONE;
|
2005-04-05 13:26:48 +02:00
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})
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(define_insn "zero_extendqidi2"
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[(set (match_operand:DI 0 "register_operand" "=d")
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(zero_extend:DI (match_operand:QI 1 "register_operand" "d")))]
|
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""
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"%0 = %T1 (Z);\\n\\t%H0 = 0;"
|
bfin-protos.h (bfin_hardware_loop): Declare.
* config/bfin/bfin-protos.h (bfin_hardware_loop): Declare.
* config/bfin/bfin.c (basic-block.h): Include.
(struct machine_function): New.
(bfin_init_machine_status): New.
(override_options): Initialize init_machine_status.
(bfin_hardware_loop): New.
(MAX_LOOP_DEPTH, MAX_LOOP_LENGTH): Define.
(DEF_VEC_P (loop_info)): New.
(DEF_VEC_ALLOC_P (loop_info,heap)): New.
(struct loop_info): New.
(loop_info): New typedef.
(struct loop_work): New.
(loop_work): New typedef.
(DEF_VEC_O (loop_work)): New.
(DEF_VEC_ALLOC_O (loop_work,heap)): New.
(bfin_dump_loops): New.
(bfin_bb_in_loop): New.
(bfin_scan_loop): New.
(bfin_optimize_loop): New.
(bfin_reorg_loops): New.
(bfin_reorg): Use bfin_reorg_loops.
* config/bfin/bfin.h (FIRST_PSEUDO_REGISTER): Adjust for adding
loop registers.
(I_REGNO_P): Simplify.
(DP_REGNO_P, DPREG_P): New macros.
(REGISTER_NAMES, FIXED_REGISTERS, CALL_USED_REGISTERS,
REG_ALLOC_ORDER): Add LT0, LT1, LC0, LC1, LB0, LB1.
(enum reg_class, REG_CLASS_NAMES, REG_CLASS_CONTENTS):
Add LT_REGS, LC_REGS, LB_REGS.
(REG_CLASS_FROM_LETTER): Add 't' for LT_REGS, 'k' for LC_REGS,
'l' for LB_REGS.
(REGNO_REG_CLASS): Deal with loop registers.
* config/bfin/bfin.md: Add comment for 't', 'k', 'l' constraint
letters.
(REG_LT0, REG_LT1, REG_LC0, REG_LC1, REG_LB0, REG_LB1):
New constants for loop registers.
(UNSPEC_LSETUP_END): New.
(seq_insns): New define_attr. Set it for appropriate insns.
(movsi_insn): Add alternatives for move from/to
loop count registers.
(doloop_end): New define_expand.
(loop_end): New define_insn.
(define_split for bad doloop_end): New.
(lsetup_with_autoinit): New define_insn.
(lsetup_without_autoinit): New define_insn.
(rep_movsi, rep_movhi): Clobber LT1, LC1, LB1.
* config/bfin/predicates.md (lc_register_operand): New.
(lt_register_operand): New.
(lb_register_operand): New.
(nondp_register_operand): New.
(nondp_reg_or_memory_operand): New.
* doc/md.texi: Document Blackfin new 't', 'k', 'l' constraint letters.
From-SVN: r114274
2006-05-31 18:46:15 +02:00
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[(set_attr "length" "4")
|
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(set_attr "seq_insns" "multi")])
|
2005-04-05 13:26:48 +02:00
|
|
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|
|
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|
|
(define_insn "zero_extendhidi2"
|
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|
[(set (match_operand:DI 0 "register_operand" "=d")
|
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|
|
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(zero_extend:DI (match_operand:HI 1 "register_operand" "d")))]
|
|
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|
""
|
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|
|
"%0 = %h1 (Z);\\n\\t%H0 = 0;"
|
bfin-protos.h (bfin_hardware_loop): Declare.
* config/bfin/bfin-protos.h (bfin_hardware_loop): Declare.
* config/bfin/bfin.c (basic-block.h): Include.
(struct machine_function): New.
(bfin_init_machine_status): New.
(override_options): Initialize init_machine_status.
(bfin_hardware_loop): New.
(MAX_LOOP_DEPTH, MAX_LOOP_LENGTH): Define.
(DEF_VEC_P (loop_info)): New.
(DEF_VEC_ALLOC_P (loop_info,heap)): New.
(struct loop_info): New.
(loop_info): New typedef.
(struct loop_work): New.
(loop_work): New typedef.
(DEF_VEC_O (loop_work)): New.
(DEF_VEC_ALLOC_O (loop_work,heap)): New.
(bfin_dump_loops): New.
(bfin_bb_in_loop): New.
(bfin_scan_loop): New.
(bfin_optimize_loop): New.
(bfin_reorg_loops): New.
(bfin_reorg): Use bfin_reorg_loops.
* config/bfin/bfin.h (FIRST_PSEUDO_REGISTER): Adjust for adding
loop registers.
(I_REGNO_P): Simplify.
(DP_REGNO_P, DPREG_P): New macros.
(REGISTER_NAMES, FIXED_REGISTERS, CALL_USED_REGISTERS,
REG_ALLOC_ORDER): Add LT0, LT1, LC0, LC1, LB0, LB1.
(enum reg_class, REG_CLASS_NAMES, REG_CLASS_CONTENTS):
Add LT_REGS, LC_REGS, LB_REGS.
(REG_CLASS_FROM_LETTER): Add 't' for LT_REGS, 'k' for LC_REGS,
'l' for LB_REGS.
(REGNO_REG_CLASS): Deal with loop registers.
* config/bfin/bfin.md: Add comment for 't', 'k', 'l' constraint
letters.
(REG_LT0, REG_LT1, REG_LC0, REG_LC1, REG_LB0, REG_LB1):
New constants for loop registers.
(UNSPEC_LSETUP_END): New.
(seq_insns): New define_attr. Set it for appropriate insns.
(movsi_insn): Add alternatives for move from/to
loop count registers.
(doloop_end): New define_expand.
(loop_end): New define_insn.
(define_split for bad doloop_end): New.
(lsetup_with_autoinit): New define_insn.
(lsetup_without_autoinit): New define_insn.
(rep_movsi, rep_movhi): Clobber LT1, LC1, LB1.
* config/bfin/predicates.md (lc_register_operand): New.
(lt_register_operand): New.
(lb_register_operand): New.
(nondp_register_operand): New.
(nondp_reg_or_memory_operand): New.
* doc/md.texi: Document Blackfin new 't', 'k', 'l' constraint letters.
From-SVN: r114274
2006-05-31 18:46:15 +02:00
|
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[(set_attr "length" "4")
|
|
|
|
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(set_attr "seq_insns" "multi")])
|
2005-04-05 13:26:48 +02:00
|
|
|
|
|
|
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|
|
(define_insn_and_split "extendsidi2"
|
|
|
|
|
[(set (match_operand:DI 0 "register_operand" "=d")
|
|
|
|
|
(sign_extend:DI (match_operand:SI 1 "register_operand" "d")))]
|
|
|
|
|
""
|
|
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"#"
|
|
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"reload_completed"
|
|
|
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|
[(set (match_dup 3) (match_dup 1))
|
|
|
|
|
(set (match_dup 3) (ashiftrt:SI (match_dup 3) (const_int 31)))]
|
|
|
|
|
{
|
|
|
|
|
split_di (operands, 1, operands + 2, operands + 3);
|
|
|
|
|
if (REGNO (operands[0]) != REGNO (operands[1]))
|
|
|
|
|
emit_move_insn (operands[2], operands[1]);
|
|
|
|
|
})
|
|
|
|
|
|
|
|
|
|
(define_insn_and_split "extendqidi2"
|
|
|
|
|
[(set (match_operand:DI 0 "register_operand" "=d")
|
|
|
|
|
(sign_extend:DI (match_operand:QI 1 "register_operand" "d")))]
|
|
|
|
|
""
|
|
|
|
|
"#"
|
|
|
|
|
"reload_completed"
|
|
|
|
|
[(set (match_dup 2) (sign_extend:SI (match_dup 1)))
|
|
|
|
|
(set (match_dup 3) (sign_extend:SI (match_dup 1)))
|
|
|
|
|
(set (match_dup 3) (ashiftrt:SI (match_dup 3) (const_int 31)))]
|
|
|
|
|
{
|
|
|
|
|
split_di (operands, 1, operands + 2, operands + 3);
|
|
|
|
|
})
|
|
|
|
|
|
|
|
|
|
(define_insn_and_split "extendhidi2"
|
|
|
|
|
[(set (match_operand:DI 0 "register_operand" "=d")
|
|
|
|
|
(sign_extend:DI (match_operand:HI 1 "register_operand" "d")))]
|
|
|
|
|
""
|
|
|
|
|
"#"
|
|
|
|
|
"reload_completed"
|
|
|
|
|
[(set (match_dup 2) (sign_extend:SI (match_dup 1)))
|
|
|
|
|
(set (match_dup 3) (sign_extend:SI (match_dup 1)))
|
|
|
|
|
(set (match_dup 3) (ashiftrt:SI (match_dup 3) (const_int 31)))]
|
|
|
|
|
{
|
|
|
|
|
split_di (operands, 1, operands + 2, operands + 3);
|
|
|
|
|
})
|
|
|
|
|
|
|
|
|
|
;; DImode arithmetic operations
|
|
|
|
|
|
bfin.h (enum reg_class, [...]): Add D0REGS through D7REGS.
* config/bfin/bfin.h (enum reg_class, REG_CLASS_NAMES,
REG_CLASS_CONTENTS): Add D0REGS through D7REGS.
(CONSTRAINT_LEN): Add entry for 'q'.
(REG_CLASS_FROM_CONSTRAINT): Renamed from REG_CLASS_FROM_LETTER.
Add 'q' constraints.
(REGNO_REG_CLASS): For R0 through R7, return corresponding regclass.
(CLASS_LIKELY_SPILLED_P): True for R0, R1 and R2.
* config/bfin/bfin.md (add_with_carry): New pattern.
(s_or_u, su_optab, su_modifier): New code macros/attrs.
(<su_optab>hisi_ll, <su_optab>hisi_lh, <su_optab>hisi_hl,
<su_optab>hisi_hh): Renamed from mulhisi_xx patterns; macroized to
support unsigned multiplies too. Removed incorrect commutativity from
operand 1 constraint where appropriate.
(usmulhisi_ull, usmulhisi_ulh, usmulhisi_uhl, usmulhisi_uhh): New
patterns.
(<su_optab>hisi_ll_lh, <su_optab>hisi_ll_hl, <su_optab>hisi_ll_hh,
<su_optab>hisi_lh_hl, <su_optab>hisi_lh_hh, <su_optab>hisi_hl_hh):
New patterns.
(usmulhisi_ll_lul, usmulhisi_ll_luh, usmulhisi_ll_hul,
usmulhisi_ll_huh, usmulhisi_lh_lul, usmulhisi_lh_luh, usmulhisi_lh_hul,
usmulhisi_lh_huh, usmulhisi_hl_lul, usmulhisi_hl_luh, usmulhisi_hl_hul,
usmulhisi_hl_huh, usmulhisi_hh_lul, usmulhisi_hh_luh, usmulhisi_hh_hul,
usmulhisi_hh_huh): New patterns.
From-SVN: r122373
2007-02-27 14:44:10 +01:00
|
|
|
|
(define_insn "add_with_carry"
|
|
|
|
|
[(set (match_operand:SI 0 "register_operand" "=d,d")
|
bfin.md (<optab>di3): Now a define_expand which expands logical operations piecewise.
* config/bfin/bfin.md (<optab>di3): Now a define_expand which expands
logical operations piecewise.
(<optab>di_zesidi_di, <optab>di_sesidi_di, negdi2, one_cmpldi2,
zero_extendsidi2, subdi_di_zesidi, subdi_zesidi_di, subdi_di_sesidi,
subdi_sesidi_di): Delete.
(add_with_carry): Produce carry in CC instead of a DREG to shorten
the generated sequence. Allow three-reg add in constraints. Rewrite
the rtl expression for carry to avoid zero_extend of a constant.
(sub_with_carry): New pattern.
(adddi3, subdi3): Change into define_expand. For subtract, generate a
different sequence not involving jumps.
(notbi): Now a named pattern.
From-SVN: r124414
2007-05-04 13:00:00 +02:00
|
|
|
|
(plus:SI (match_operand:SI 1 "register_operand" "%0,d")
|
bfin.h (enum reg_class, [...]): Add D0REGS through D7REGS.
* config/bfin/bfin.h (enum reg_class, REG_CLASS_NAMES,
REG_CLASS_CONTENTS): Add D0REGS through D7REGS.
(CONSTRAINT_LEN): Add entry for 'q'.
(REG_CLASS_FROM_CONSTRAINT): Renamed from REG_CLASS_FROM_LETTER.
Add 'q' constraints.
(REGNO_REG_CLASS): For R0 through R7, return corresponding regclass.
(CLASS_LIKELY_SPILLED_P): True for R0, R1 and R2.
* config/bfin/bfin.md (add_with_carry): New pattern.
(s_or_u, su_optab, su_modifier): New code macros/attrs.
(<su_optab>hisi_ll, <su_optab>hisi_lh, <su_optab>hisi_hl,
<su_optab>hisi_hh): Renamed from mulhisi_xx patterns; macroized to
support unsigned multiplies too. Removed incorrect commutativity from
operand 1 constraint where appropriate.
(usmulhisi_ull, usmulhisi_ulh, usmulhisi_uhl, usmulhisi_uhh): New
patterns.
(<su_optab>hisi_ll_lh, <su_optab>hisi_ll_hl, <su_optab>hisi_ll_hh,
<su_optab>hisi_lh_hl, <su_optab>hisi_lh_hh, <su_optab>hisi_hl_hh):
New patterns.
(usmulhisi_ll_lul, usmulhisi_ll_luh, usmulhisi_ll_hul,
usmulhisi_ll_huh, usmulhisi_lh_lul, usmulhisi_lh_luh, usmulhisi_lh_hul,
usmulhisi_lh_huh, usmulhisi_hl_lul, usmulhisi_hl_luh, usmulhisi_hl_hul,
usmulhisi_hl_huh, usmulhisi_hh_lul, usmulhisi_hh_luh, usmulhisi_hh_hul,
usmulhisi_hh_huh): New patterns.
From-SVN: r122373
2007-02-27 14:44:10 +01:00
|
|
|
|
(match_operand:SI 2 "nonmemory_operand" "Ks7,d")))
|
bfin.md (<optab>di3): Now a define_expand which expands logical operations piecewise.
* config/bfin/bfin.md (<optab>di3): Now a define_expand which expands
logical operations piecewise.
(<optab>di_zesidi_di, <optab>di_sesidi_di, negdi2, one_cmpldi2,
zero_extendsidi2, subdi_di_zesidi, subdi_zesidi_di, subdi_di_sesidi,
subdi_sesidi_di): Delete.
(add_with_carry): Produce carry in CC instead of a DREG to shorten
the generated sequence. Allow three-reg add in constraints. Rewrite
the rtl expression for carry to avoid zero_extend of a constant.
(sub_with_carry): New pattern.
(adddi3, subdi3): Change into define_expand. For subtract, generate a
different sequence not involving jumps.
(notbi): Now a named pattern.
From-SVN: r124414
2007-05-04 13:00:00 +02:00
|
|
|
|
(set (match_operand:BI 3 "register_operand" "=C,C")
|
|
|
|
|
(ltu:BI (not:SI (match_dup 1)) (match_dup 2)))]
|
bfin.h (enum reg_class, [...]): Add D0REGS through D7REGS.
* config/bfin/bfin.h (enum reg_class, REG_CLASS_NAMES,
REG_CLASS_CONTENTS): Add D0REGS through D7REGS.
(CONSTRAINT_LEN): Add entry for 'q'.
(REG_CLASS_FROM_CONSTRAINT): Renamed from REG_CLASS_FROM_LETTER.
Add 'q' constraints.
(REGNO_REG_CLASS): For R0 through R7, return corresponding regclass.
(CLASS_LIKELY_SPILLED_P): True for R0, R1 and R2.
* config/bfin/bfin.md (add_with_carry): New pattern.
(s_or_u, su_optab, su_modifier): New code macros/attrs.
(<su_optab>hisi_ll, <su_optab>hisi_lh, <su_optab>hisi_hl,
<su_optab>hisi_hh): Renamed from mulhisi_xx patterns; macroized to
support unsigned multiplies too. Removed incorrect commutativity from
operand 1 constraint where appropriate.
(usmulhisi_ull, usmulhisi_ulh, usmulhisi_uhl, usmulhisi_uhh): New
patterns.
(<su_optab>hisi_ll_lh, <su_optab>hisi_ll_hl, <su_optab>hisi_ll_hh,
<su_optab>hisi_lh_hl, <su_optab>hisi_lh_hh, <su_optab>hisi_hl_hh):
New patterns.
(usmulhisi_ll_lul, usmulhisi_ll_luh, usmulhisi_ll_hul,
usmulhisi_ll_huh, usmulhisi_lh_lul, usmulhisi_lh_luh, usmulhisi_lh_hul,
usmulhisi_lh_huh, usmulhisi_hl_lul, usmulhisi_hl_luh, usmulhisi_hl_hul,
usmulhisi_hl_huh, usmulhisi_hh_lul, usmulhisi_hh_luh, usmulhisi_hh_hul,
usmulhisi_hh_huh): New patterns.
From-SVN: r122373
2007-02-27 14:44:10 +01:00
|
|
|
|
""
|
|
|
|
|
"@
|
bfin.md (<optab>di3): Now a define_expand which expands logical operations piecewise.
* config/bfin/bfin.md (<optab>di3): Now a define_expand which expands
logical operations piecewise.
(<optab>di_zesidi_di, <optab>di_sesidi_di, negdi2, one_cmpldi2,
zero_extendsidi2, subdi_di_zesidi, subdi_zesidi_di, subdi_di_sesidi,
subdi_sesidi_di): Delete.
(add_with_carry): Produce carry in CC instead of a DREG to shorten
the generated sequence. Allow three-reg add in constraints. Rewrite
the rtl expression for carry to avoid zero_extend of a constant.
(sub_with_carry): New pattern.
(adddi3, subdi3): Change into define_expand. For subtract, generate a
different sequence not involving jumps.
(notbi): Now a named pattern.
From-SVN: r124414
2007-05-04 13:00:00 +02:00
|
|
|
|
%0 += %2; cc = ac0;
|
|
|
|
|
%0 = %1 + %2; cc = ac0;"
|
bfin.h (enum reg_class, [...]): Add D0REGS through D7REGS.
* config/bfin/bfin.h (enum reg_class, REG_CLASS_NAMES,
REG_CLASS_CONTENTS): Add D0REGS through D7REGS.
(CONSTRAINT_LEN): Add entry for 'q'.
(REG_CLASS_FROM_CONSTRAINT): Renamed from REG_CLASS_FROM_LETTER.
Add 'q' constraints.
(REGNO_REG_CLASS): For R0 through R7, return corresponding regclass.
(CLASS_LIKELY_SPILLED_P): True for R0, R1 and R2.
* config/bfin/bfin.md (add_with_carry): New pattern.
(s_or_u, su_optab, su_modifier): New code macros/attrs.
(<su_optab>hisi_ll, <su_optab>hisi_lh, <su_optab>hisi_hl,
<su_optab>hisi_hh): Renamed from mulhisi_xx patterns; macroized to
support unsigned multiplies too. Removed incorrect commutativity from
operand 1 constraint where appropriate.
(usmulhisi_ull, usmulhisi_ulh, usmulhisi_uhl, usmulhisi_uhh): New
patterns.
(<su_optab>hisi_ll_lh, <su_optab>hisi_ll_hl, <su_optab>hisi_ll_hh,
<su_optab>hisi_lh_hl, <su_optab>hisi_lh_hh, <su_optab>hisi_hl_hh):
New patterns.
(usmulhisi_ll_lul, usmulhisi_ll_luh, usmulhisi_ll_hul,
usmulhisi_ll_huh, usmulhisi_lh_lul, usmulhisi_lh_luh, usmulhisi_lh_hul,
usmulhisi_lh_huh, usmulhisi_hl_lul, usmulhisi_hl_luh, usmulhisi_hl_hul,
usmulhisi_hl_huh, usmulhisi_hh_lul, usmulhisi_hh_luh, usmulhisi_hh_hul,
usmulhisi_hh_huh): New patterns.
From-SVN: r122373
2007-02-27 14:44:10 +01:00
|
|
|
|
[(set_attr "type" "alu0")
|
bfin.md (<optab>di3): Now a define_expand which expands logical operations piecewise.
* config/bfin/bfin.md (<optab>di3): Now a define_expand which expands
logical operations piecewise.
(<optab>di_zesidi_di, <optab>di_sesidi_di, negdi2, one_cmpldi2,
zero_extendsidi2, subdi_di_zesidi, subdi_zesidi_di, subdi_di_sesidi,
subdi_sesidi_di): Delete.
(add_with_carry): Produce carry in CC instead of a DREG to shorten
the generated sequence. Allow three-reg add in constraints. Rewrite
the rtl expression for carry to avoid zero_extend of a constant.
(sub_with_carry): New pattern.
(adddi3, subdi3): Change into define_expand. For subtract, generate a
different sequence not involving jumps.
(notbi): Now a named pattern.
From-SVN: r124414
2007-05-04 13:00:00 +02:00
|
|
|
|
(set_attr "length" "4")
|
bfin.h (enum reg_class, [...]): Add D0REGS through D7REGS.
* config/bfin/bfin.h (enum reg_class, REG_CLASS_NAMES,
REG_CLASS_CONTENTS): Add D0REGS through D7REGS.
(CONSTRAINT_LEN): Add entry for 'q'.
(REG_CLASS_FROM_CONSTRAINT): Renamed from REG_CLASS_FROM_LETTER.
Add 'q' constraints.
(REGNO_REG_CLASS): For R0 through R7, return corresponding regclass.
(CLASS_LIKELY_SPILLED_P): True for R0, R1 and R2.
* config/bfin/bfin.md (add_with_carry): New pattern.
(s_or_u, su_optab, su_modifier): New code macros/attrs.
(<su_optab>hisi_ll, <su_optab>hisi_lh, <su_optab>hisi_hl,
<su_optab>hisi_hh): Renamed from mulhisi_xx patterns; macroized to
support unsigned multiplies too. Removed incorrect commutativity from
operand 1 constraint where appropriate.
(usmulhisi_ull, usmulhisi_ulh, usmulhisi_uhl, usmulhisi_uhh): New
patterns.
(<su_optab>hisi_ll_lh, <su_optab>hisi_ll_hl, <su_optab>hisi_ll_hh,
<su_optab>hisi_lh_hl, <su_optab>hisi_lh_hh, <su_optab>hisi_hl_hh):
New patterns.
(usmulhisi_ll_lul, usmulhisi_ll_luh, usmulhisi_ll_hul,
usmulhisi_ll_huh, usmulhisi_lh_lul, usmulhisi_lh_luh, usmulhisi_lh_hul,
usmulhisi_lh_huh, usmulhisi_hl_lul, usmulhisi_hl_luh, usmulhisi_hl_hul,
usmulhisi_hl_huh, usmulhisi_hh_lul, usmulhisi_hh_luh, usmulhisi_hh_hul,
usmulhisi_hh_huh): New patterns.
From-SVN: r122373
2007-02-27 14:44:10 +01:00
|
|
|
|
(set_attr "seq_insns" "multi")])
|
|
|
|
|
|
bfin.md (<optab>di3): Now a define_expand which expands logical operations piecewise.
* config/bfin/bfin.md (<optab>di3): Now a define_expand which expands
logical operations piecewise.
(<optab>di_zesidi_di, <optab>di_sesidi_di, negdi2, one_cmpldi2,
zero_extendsidi2, subdi_di_zesidi, subdi_zesidi_di, subdi_di_sesidi,
subdi_sesidi_di): Delete.
(add_with_carry): Produce carry in CC instead of a DREG to shorten
the generated sequence. Allow three-reg add in constraints. Rewrite
the rtl expression for carry to avoid zero_extend of a constant.
(sub_with_carry): New pattern.
(adddi3, subdi3): Change into define_expand. For subtract, generate a
different sequence not involving jumps.
(notbi): Now a named pattern.
From-SVN: r124414
2007-05-04 13:00:00 +02:00
|
|
|
|
(define_insn "sub_with_carry"
|
|
|
|
|
[(set (match_operand:SI 0 "register_operand" "=d")
|
|
|
|
|
(minus:SI (match_operand:SI 1 "register_operand" "%d")
|
|
|
|
|
(match_operand:SI 2 "nonmemory_operand" "d")))
|
|
|
|
|
(set (match_operand:BI 3 "register_operand" "=C")
|
|
|
|
|
(leu:BI (match_dup 2) (match_dup 1)))]
|
2005-04-05 13:26:48 +02:00
|
|
|
|
""
|
bfin.md (<optab>di3): Now a define_expand which expands logical operations piecewise.
* config/bfin/bfin.md (<optab>di3): Now a define_expand which expands
logical operations piecewise.
(<optab>di_zesidi_di, <optab>di_sesidi_di, negdi2, one_cmpldi2,
zero_extendsidi2, subdi_di_zesidi, subdi_zesidi_di, subdi_di_sesidi,
subdi_sesidi_di): Delete.
(add_with_carry): Produce carry in CC instead of a DREG to shorten
the generated sequence. Allow three-reg add in constraints. Rewrite
the rtl expression for carry to avoid zero_extend of a constant.
(sub_with_carry): New pattern.
(adddi3, subdi3): Change into define_expand. For subtract, generate a
different sequence not involving jumps.
(notbi): Now a named pattern.
From-SVN: r124414
2007-05-04 13:00:00 +02:00
|
|
|
|
"%0 = %1 - %2; cc = ac0;"
|
2005-04-05 13:26:48 +02:00
|
|
|
|
[(set_attr "type" "alu0")
|
bfin.md (<optab>di3): Now a define_expand which expands logical operations piecewise.
* config/bfin/bfin.md (<optab>di3): Now a define_expand which expands
logical operations piecewise.
(<optab>di_zesidi_di, <optab>di_sesidi_di, negdi2, one_cmpldi2,
zero_extendsidi2, subdi_di_zesidi, subdi_zesidi_di, subdi_di_sesidi,
subdi_sesidi_di): Delete.
(add_with_carry): Produce carry in CC instead of a DREG to shorten
the generated sequence. Allow three-reg add in constraints. Rewrite
the rtl expression for carry to avoid zero_extend of a constant.
(sub_with_carry): New pattern.
(adddi3, subdi3): Change into define_expand. For subtract, generate a
different sequence not involving jumps.
(notbi): Now a named pattern.
From-SVN: r124414
2007-05-04 13:00:00 +02:00
|
|
|
|
(set_attr "length" "4")
|
bfin-protos.h (bfin_hardware_loop): Declare.
* config/bfin/bfin-protos.h (bfin_hardware_loop): Declare.
* config/bfin/bfin.c (basic-block.h): Include.
(struct machine_function): New.
(bfin_init_machine_status): New.
(override_options): Initialize init_machine_status.
(bfin_hardware_loop): New.
(MAX_LOOP_DEPTH, MAX_LOOP_LENGTH): Define.
(DEF_VEC_P (loop_info)): New.
(DEF_VEC_ALLOC_P (loop_info,heap)): New.
(struct loop_info): New.
(loop_info): New typedef.
(struct loop_work): New.
(loop_work): New typedef.
(DEF_VEC_O (loop_work)): New.
(DEF_VEC_ALLOC_O (loop_work,heap)): New.
(bfin_dump_loops): New.
(bfin_bb_in_loop): New.
(bfin_scan_loop): New.
(bfin_optimize_loop): New.
(bfin_reorg_loops): New.
(bfin_reorg): Use bfin_reorg_loops.
* config/bfin/bfin.h (FIRST_PSEUDO_REGISTER): Adjust for adding
loop registers.
(I_REGNO_P): Simplify.
(DP_REGNO_P, DPREG_P): New macros.
(REGISTER_NAMES, FIXED_REGISTERS, CALL_USED_REGISTERS,
REG_ALLOC_ORDER): Add LT0, LT1, LC0, LC1, LB0, LB1.
(enum reg_class, REG_CLASS_NAMES, REG_CLASS_CONTENTS):
Add LT_REGS, LC_REGS, LB_REGS.
(REG_CLASS_FROM_LETTER): Add 't' for LT_REGS, 'k' for LC_REGS,
'l' for LB_REGS.
(REGNO_REG_CLASS): Deal with loop registers.
* config/bfin/bfin.md: Add comment for 't', 'k', 'l' constraint
letters.
(REG_LT0, REG_LT1, REG_LC0, REG_LC1, REG_LB0, REG_LB1):
New constants for loop registers.
(UNSPEC_LSETUP_END): New.
(seq_insns): New define_attr. Set it for appropriate insns.
(movsi_insn): Add alternatives for move from/to
loop count registers.
(doloop_end): New define_expand.
(loop_end): New define_insn.
(define_split for bad doloop_end): New.
(lsetup_with_autoinit): New define_insn.
(lsetup_without_autoinit): New define_insn.
(rep_movsi, rep_movhi): Clobber LT1, LC1, LB1.
* config/bfin/predicates.md (lc_register_operand): New.
(lt_register_operand): New.
(lb_register_operand): New.
(nondp_register_operand): New.
(nondp_reg_or_memory_operand): New.
* doc/md.texi: Document Blackfin new 't', 'k', 'l' constraint letters.
From-SVN: r114274
2006-05-31 18:46:15 +02:00
|
|
|
|
(set_attr "seq_insns" "multi")])
|
2005-04-05 13:26:48 +02:00
|
|
|
|
|
bfin.md (<optab>di3): Now a define_expand which expands logical operations piecewise.
* config/bfin/bfin.md (<optab>di3): Now a define_expand which expands
logical operations piecewise.
(<optab>di_zesidi_di, <optab>di_sesidi_di, negdi2, one_cmpldi2,
zero_extendsidi2, subdi_di_zesidi, subdi_zesidi_di, subdi_di_sesidi,
subdi_sesidi_di): Delete.
(add_with_carry): Produce carry in CC instead of a DREG to shorten
the generated sequence. Allow three-reg add in constraints. Rewrite
the rtl expression for carry to avoid zero_extend of a constant.
(sub_with_carry): New pattern.
(adddi3, subdi3): Change into define_expand. For subtract, generate a
different sequence not involving jumps.
(notbi): Now a named pattern.
From-SVN: r124414
2007-05-04 13:00:00 +02:00
|
|
|
|
(define_expand "adddi3"
|
|
|
|
|
[(set (match_operand:DI 0 "register_operand" "")
|
|
|
|
|
(plus:DI (match_operand:DI 1 "register_operand" "")
|
|
|
|
|
(match_operand:DI 2 "nonmemory_operand" "")))
|
|
|
|
|
(clobber (match_scratch:SI 3 ""))
|
2005-04-05 13:26:48 +02:00
|
|
|
|
(clobber (reg:CC 34))]
|
|
|
|
|
""
|
bfin.md (<optab>di3): Now a define_expand which expands logical operations piecewise.
* config/bfin/bfin.md (<optab>di3): Now a define_expand which expands
logical operations piecewise.
(<optab>di_zesidi_di, <optab>di_sesidi_di, negdi2, one_cmpldi2,
zero_extendsidi2, subdi_di_zesidi, subdi_zesidi_di, subdi_di_sesidi,
subdi_sesidi_di): Delete.
(add_with_carry): Produce carry in CC instead of a DREG to shorten
the generated sequence. Allow three-reg add in constraints. Rewrite
the rtl expression for carry to avoid zero_extend of a constant.
(sub_with_carry): New pattern.
(adddi3, subdi3): Change into define_expand. For subtract, generate a
different sequence not involving jumps.
(notbi): Now a named pattern.
From-SVN: r124414
2007-05-04 13:00:00 +02:00
|
|
|
|
{
|
|
|
|
|
rtx xops[8];
|
|
|
|
|
xops[0] = gen_lowpart (SImode, operands[0]);
|
|
|
|
|
xops[1] = simplify_gen_subreg (SImode, operands[0], DImode, 4);
|
|
|
|
|
xops[2] = gen_lowpart (SImode, operands[1]);
|
|
|
|
|
xops[3] = simplify_gen_subreg (SImode, operands[1], DImode, 4);
|
|
|
|
|
xops[4] = gen_lowpart (SImode, operands[2]);
|
|
|
|
|
xops[5] = simplify_gen_subreg (SImode, operands[2], DImode, 4);
|
|
|
|
|
xops[6] = gen_reg_rtx (SImode);
|
|
|
|
|
xops[7] = gen_rtx_REG (BImode, REG_CC);
|
|
|
|
|
if (!register_operand (xops[4], SImode)
|
|
|
|
|
&& (GET_CODE (xops[4]) != CONST_INT
|
constraints.md: New file.
* config/bfin/constraints.md: New file.
* config/bfin/bfin.md: Include it.
(adddi3): Use satisfies_constraint functions instead of the old macros.
* config/bfin/bfin.h (REG_CLASS_FROM_LETTER, CONSTRAINT_LEN,
CONST_18UBIT_IMM_P, CONST_16BIT_IMM_P, CONST_16UBIT_IMM_P,
CONST_7BIT_IMM_P, CONST_7NBIT_IMM_P, CONST_5UBIT_IMM_P,
CONST_4BIT_IMM_P, CONST_4UBIT_IMM_P, CONST_3BIT_IMM_P,
CONST_3UBIT_IMM_P, CONST_OK_FOR_K, CONST_OK_FOR_P, CONST_OK_FOR_M,
CONST_OK_FOR_CONSTRAINT_P, CONST_DOUBLE_OK_FOR_LETTER,
EXTRA_CONSTRAINT): Delete.
* config/bfin/predicates.md (highbits_operand, reg_or_7bit_operand,
reg_or_neg7bit_operand): Use satisfies_constraint functions instead
of the old macros.
* config/bfin/bfin.c: Include "tm-constrs.h".
(bfin_secondary_reload, split_load_immediate, bfin_rtx_costs):
Use satisfies_constraint functions instead of the old macros.
* doc/md.texi (Blackfin Constraints): Update file name reference.
From-SVN: r134198
2008-04-11 16:40:55 +02:00
|
|
|
|
|| !satisfies_constraint_Ks7 (xops[4])))
|
bfin.md (<optab>di3): Now a define_expand which expands logical operations piecewise.
* config/bfin/bfin.md (<optab>di3): Now a define_expand which expands
logical operations piecewise.
(<optab>di_zesidi_di, <optab>di_sesidi_di, negdi2, one_cmpldi2,
zero_extendsidi2, subdi_di_zesidi, subdi_zesidi_di, subdi_di_sesidi,
subdi_sesidi_di): Delete.
(add_with_carry): Produce carry in CC instead of a DREG to shorten
the generated sequence. Allow three-reg add in constraints. Rewrite
the rtl expression for carry to avoid zero_extend of a constant.
(sub_with_carry): New pattern.
(adddi3, subdi3): Change into define_expand. For subtract, generate a
different sequence not involving jumps.
(notbi): Now a named pattern.
From-SVN: r124414
2007-05-04 13:00:00 +02:00
|
|
|
|
xops[4] = force_reg (SImode, xops[4]);
|
|
|
|
|
if (!reg_overlap_mentioned_p (operands[0], operands[1])
|
|
|
|
|
&& !reg_overlap_mentioned_p (operands[0], operands[2]))
|
rtl.h (emit_clobber, [...]): Declare.
gcc/
* rtl.h (emit_clobber, gen_clobber, emit_use, gen_use): Declare.
* emit-rtl.c (emit_clobber, gen_clobber, emit_use, gen_use): New
functions. Do not emit uses and clobbers of CONCATs; individually
use and clobber their operands.
* builtins.c (expand_builtin_setjmp_receiver): Use emit_clobber,
gen_clobber, emit_use and gen_use.
(expand_builtin_longjmp, expand_builtin_nonlocal_goto): Likewise.
(expand_builtin_return): Likewise.
* cfgbuild.c (count_basic_blocks): Likewise.
* cfgrtl.c (rtl_flow_call_edges_add): Likewise.
* explow.c (emit_stack_restore): Likewise.
* expmed.c (extract_bit_field_1): Likewise.
* expr.c (convert_move, emit_move_complex_parts): Likewise.
(emit_move_multi_word, store_constructor): Likewise.
* function.c (do_clobber_return_reg, do_use_return_reg): Likewise.
(thread_prologue_and_epilogue_insns): Likewise.
* lower-subreg.c (resolve_simple_move): Likewise.
* optabs.c (widen_operand, expand_binop): Likewise.
(expand_doubleword_bswap, emit_no_conflict_block): Likewise.
* reload.c (find_reloads): Likewise.
* reload1.c (eliminate_regs_in_insn): Likewise.
* stmt.c (expand_nl_goto_receiver): Likewise.
* config/alpha/alpha.md (builtin_longjmp): Likewise.
* config/arc/arc.md (*movdi_insn, *movdf_insn): Likewise.
* config/arm/arm.c (arm_load_pic_register): Likewise.
(thumb1_expand_epilogue, thumb_set_return_address): Likewise.
* config/arm/arm.md (untyped_return): Likewise.
* config/arm/linux-elf.h (PROFILE_HOOK): Likewise.
* config/avr/avr.c (expand_prologue): Likewise.
* config/bfin/bfin.c (do_unlink): Likewise.
* config/bfin/bfin.md (<optab>di3, adddi3, subdi3): Likewise.
* config/cris/cris.c (cris_expand_prologue): Likewise.
* config/darwin.c (machopic_indirect_data_reference): Likewise.
(machopic_legitimize_pic_address): Likewise.
* config/frv/frv.c (frv_frame_access, frv_expand_epilogue): Likewise.
(frv_ifcvt_modify_insn, frv_expand_mdpackh_builtin): Likewise.
* config/i386/i386.c (ix86_expand_vector_move_misalign): Likewise.
(ix86_expand_convert_uns_didf_sse): Likewise.
(ix86_expand_vector_init_general): Likewise.
* config/ia64/ia64.md (eh_epilogue): Likewise.
* config/iq2000/iq2000.c (iq2000_expand_epilogue): Likewise.
* config/m32c/m32c.c (m32c_emit_eh_epilogue): Likewise.
* config/m32r/m32r.c (m32r_reload_lr): Likewise.
(config/iq2000/iq2000.c): Likewise.
* config/mips/mips.md (fixuns_truncdfsi2): Likewise.
(fixuns_truncdfdi2, fixuns_truncsfsi2, fixuns_truncsfdi2): Likewise.
(builtin_longjmp): Likewise.
* config/mn10300/mn10300.md (call, call_value): Likewise.
* config/pa/pa.md (nonlocal_goto, nonlocal_longjmp): Likewise.
* config/pdp11/pdp11.md (abshi2): Likewise.
* config/rs6000/rs6000.c (rs6000_emit_move): Likewise.
* config/s390/s390.c (s390_emit_prologue): Likewise.
* config/s390/s390.md (movmem_long, setmem_long): Likewise.
(cmpmem_long, extendsidi2, zero_extendsidi2, udivmoddi4): Likewise.
(builtin_setjmp_receiver, restore_stack_nonlocal): Likewise.
* config/sh/sh.c (prepare_move_operands): Likewise.
(output_stack_adjust, sh_expand_epilogue): Likewise.
(sh_set_return_address, sh_expand_t_scc): Likewise.
* config/sparc/sparc.c (load_pic_register): Likewise.
* config/sparc/sparc.md (untyped_return, nonlocal_goto): Likewise.
* config/spu/spu.c (spu_expand_epilogue): Likewise.
* config/v850/v850.c (expand_epilogue): Likewise.
From-SVN: r136251
2008-06-01 11:47:28 +02:00
|
|
|
|
emit_clobber (operands[0]);
|
bfin.md (<optab>di3): Now a define_expand which expands logical operations piecewise.
* config/bfin/bfin.md (<optab>di3): Now a define_expand which expands
logical operations piecewise.
(<optab>di_zesidi_di, <optab>di_sesidi_di, negdi2, one_cmpldi2,
zero_extendsidi2, subdi_di_zesidi, subdi_zesidi_di, subdi_di_sesidi,
subdi_sesidi_di): Delete.
(add_with_carry): Produce carry in CC instead of a DREG to shorten
the generated sequence. Allow three-reg add in constraints. Rewrite
the rtl expression for carry to avoid zero_extend of a constant.
(sub_with_carry): New pattern.
(adddi3, subdi3): Change into define_expand. For subtract, generate a
different sequence not involving jumps.
(notbi): Now a named pattern.
From-SVN: r124414
2007-05-04 13:00:00 +02:00
|
|
|
|
emit_insn (gen_add_with_carry (xops[0], xops[2], xops[4], xops[7]));
|
|
|
|
|
emit_insn (gen_movbisi (xops[6], xops[7]));
|
|
|
|
|
if (!register_operand (xops[5], SImode)
|
|
|
|
|
&& (GET_CODE (xops[5]) != CONST_INT
|
constraints.md: New file.
* config/bfin/constraints.md: New file.
* config/bfin/bfin.md: Include it.
(adddi3): Use satisfies_constraint functions instead of the old macros.
* config/bfin/bfin.h (REG_CLASS_FROM_LETTER, CONSTRAINT_LEN,
CONST_18UBIT_IMM_P, CONST_16BIT_IMM_P, CONST_16UBIT_IMM_P,
CONST_7BIT_IMM_P, CONST_7NBIT_IMM_P, CONST_5UBIT_IMM_P,
CONST_4BIT_IMM_P, CONST_4UBIT_IMM_P, CONST_3BIT_IMM_P,
CONST_3UBIT_IMM_P, CONST_OK_FOR_K, CONST_OK_FOR_P, CONST_OK_FOR_M,
CONST_OK_FOR_CONSTRAINT_P, CONST_DOUBLE_OK_FOR_LETTER,
EXTRA_CONSTRAINT): Delete.
* config/bfin/predicates.md (highbits_operand, reg_or_7bit_operand,
reg_or_neg7bit_operand): Use satisfies_constraint functions instead
of the old macros.
* config/bfin/bfin.c: Include "tm-constrs.h".
(bfin_secondary_reload, split_load_immediate, bfin_rtx_costs):
Use satisfies_constraint functions instead of the old macros.
* doc/md.texi (Blackfin Constraints): Update file name reference.
From-SVN: r134198
2008-04-11 16:40:55 +02:00
|
|
|
|
|| !satisfies_constraint_Ks7 (xops[5])))
|
bfin.md (<optab>di3): Now a define_expand which expands logical operations piecewise.
* config/bfin/bfin.md (<optab>di3): Now a define_expand which expands
logical operations piecewise.
(<optab>di_zesidi_di, <optab>di_sesidi_di, negdi2, one_cmpldi2,
zero_extendsidi2, subdi_di_zesidi, subdi_zesidi_di, subdi_di_sesidi,
subdi_sesidi_di): Delete.
(add_with_carry): Produce carry in CC instead of a DREG to shorten
the generated sequence. Allow three-reg add in constraints. Rewrite
the rtl expression for carry to avoid zero_extend of a constant.
(sub_with_carry): New pattern.
(adddi3, subdi3): Change into define_expand. For subtract, generate a
different sequence not involving jumps.
(notbi): Now a named pattern.
From-SVN: r124414
2007-05-04 13:00:00 +02:00
|
|
|
|
xops[5] = force_reg (SImode, xops[5]);
|
|
|
|
|
if (xops[5] != const0_rtx)
|
|
|
|
|
emit_insn (gen_addsi3 (xops[1], xops[3], xops[5]));
|
|
|
|
|
else
|
|
|
|
|
emit_move_insn (xops[1], xops[3]);
|
|
|
|
|
emit_insn (gen_addsi3 (xops[1], xops[1], xops[6]));
|
|
|
|
|
DONE;
|
|
|
|
|
})
|
2005-04-05 13:26:48 +02:00
|
|
|
|
|
bfin.md (<optab>di3): Now a define_expand which expands logical operations piecewise.
* config/bfin/bfin.md (<optab>di3): Now a define_expand which expands
logical operations piecewise.
(<optab>di_zesidi_di, <optab>di_sesidi_di, negdi2, one_cmpldi2,
zero_extendsidi2, subdi_di_zesidi, subdi_zesidi_di, subdi_di_sesidi,
subdi_sesidi_di): Delete.
(add_with_carry): Produce carry in CC instead of a DREG to shorten
the generated sequence. Allow three-reg add in constraints. Rewrite
the rtl expression for carry to avoid zero_extend of a constant.
(sub_with_carry): New pattern.
(adddi3, subdi3): Change into define_expand. For subtract, generate a
different sequence not involving jumps.
(notbi): Now a named pattern.
From-SVN: r124414
2007-05-04 13:00:00 +02:00
|
|
|
|
(define_expand "subdi3"
|
|
|
|
|
[(set (match_operand:DI 0 "register_operand" "")
|
|
|
|
|
(minus:DI (match_operand:DI 1 "register_operand" "")
|
|
|
|
|
(match_operand:DI 2 "register_operand" "")))
|
2005-04-05 13:26:48 +02:00
|
|
|
|
(clobber (reg:CC 34))]
|
|
|
|
|
""
|
bfin.md (<optab>di3): Now a define_expand which expands logical operations piecewise.
* config/bfin/bfin.md (<optab>di3): Now a define_expand which expands
logical operations piecewise.
(<optab>di_zesidi_di, <optab>di_sesidi_di, negdi2, one_cmpldi2,
zero_extendsidi2, subdi_di_zesidi, subdi_zesidi_di, subdi_di_sesidi,
subdi_sesidi_di): Delete.
(add_with_carry): Produce carry in CC instead of a DREG to shorten
the generated sequence. Allow three-reg add in constraints. Rewrite
the rtl expression for carry to avoid zero_extend of a constant.
(sub_with_carry): New pattern.
(adddi3, subdi3): Change into define_expand. For subtract, generate a
different sequence not involving jumps.
(notbi): Now a named pattern.
From-SVN: r124414
2007-05-04 13:00:00 +02:00
|
|
|
|
{
|
|
|
|
|
rtx xops[8];
|
|
|
|
|
xops[0] = gen_lowpart (SImode, operands[0]);
|
|
|
|
|
xops[1] = simplify_gen_subreg (SImode, operands[0], DImode, 4);
|
|
|
|
|
xops[2] = gen_lowpart (SImode, operands[1]);
|
|
|
|
|
xops[3] = simplify_gen_subreg (SImode, operands[1], DImode, 4);
|
|
|
|
|
xops[4] = gen_lowpart (SImode, operands[2]);
|
|
|
|
|
xops[5] = simplify_gen_subreg (SImode, operands[2], DImode, 4);
|
|
|
|
|
xops[6] = gen_reg_rtx (SImode);
|
|
|
|
|
xops[7] = gen_rtx_REG (BImode, REG_CC);
|
|
|
|
|
if (!reg_overlap_mentioned_p (operands[0], operands[1])
|
|
|
|
|
&& !reg_overlap_mentioned_p (operands[0], operands[2]))
|
rtl.h (emit_clobber, [...]): Declare.
gcc/
* rtl.h (emit_clobber, gen_clobber, emit_use, gen_use): Declare.
* emit-rtl.c (emit_clobber, gen_clobber, emit_use, gen_use): New
functions. Do not emit uses and clobbers of CONCATs; individually
use and clobber their operands.
* builtins.c (expand_builtin_setjmp_receiver): Use emit_clobber,
gen_clobber, emit_use and gen_use.
(expand_builtin_longjmp, expand_builtin_nonlocal_goto): Likewise.
(expand_builtin_return): Likewise.
* cfgbuild.c (count_basic_blocks): Likewise.
* cfgrtl.c (rtl_flow_call_edges_add): Likewise.
* explow.c (emit_stack_restore): Likewise.
* expmed.c (extract_bit_field_1): Likewise.
* expr.c (convert_move, emit_move_complex_parts): Likewise.
(emit_move_multi_word, store_constructor): Likewise.
* function.c (do_clobber_return_reg, do_use_return_reg): Likewise.
(thread_prologue_and_epilogue_insns): Likewise.
* lower-subreg.c (resolve_simple_move): Likewise.
* optabs.c (widen_operand, expand_binop): Likewise.
(expand_doubleword_bswap, emit_no_conflict_block): Likewise.
* reload.c (find_reloads): Likewise.
* reload1.c (eliminate_regs_in_insn): Likewise.
* stmt.c (expand_nl_goto_receiver): Likewise.
* config/alpha/alpha.md (builtin_longjmp): Likewise.
* config/arc/arc.md (*movdi_insn, *movdf_insn): Likewise.
* config/arm/arm.c (arm_load_pic_register): Likewise.
(thumb1_expand_epilogue, thumb_set_return_address): Likewise.
* config/arm/arm.md (untyped_return): Likewise.
* config/arm/linux-elf.h (PROFILE_HOOK): Likewise.
* config/avr/avr.c (expand_prologue): Likewise.
* config/bfin/bfin.c (do_unlink): Likewise.
* config/bfin/bfin.md (<optab>di3, adddi3, subdi3): Likewise.
* config/cris/cris.c (cris_expand_prologue): Likewise.
* config/darwin.c (machopic_indirect_data_reference): Likewise.
(machopic_legitimize_pic_address): Likewise.
* config/frv/frv.c (frv_frame_access, frv_expand_epilogue): Likewise.
(frv_ifcvt_modify_insn, frv_expand_mdpackh_builtin): Likewise.
* config/i386/i386.c (ix86_expand_vector_move_misalign): Likewise.
(ix86_expand_convert_uns_didf_sse): Likewise.
(ix86_expand_vector_init_general): Likewise.
* config/ia64/ia64.md (eh_epilogue): Likewise.
* config/iq2000/iq2000.c (iq2000_expand_epilogue): Likewise.
* config/m32c/m32c.c (m32c_emit_eh_epilogue): Likewise.
* config/m32r/m32r.c (m32r_reload_lr): Likewise.
(config/iq2000/iq2000.c): Likewise.
* config/mips/mips.md (fixuns_truncdfsi2): Likewise.
(fixuns_truncdfdi2, fixuns_truncsfsi2, fixuns_truncsfdi2): Likewise.
(builtin_longjmp): Likewise.
* config/mn10300/mn10300.md (call, call_value): Likewise.
* config/pa/pa.md (nonlocal_goto, nonlocal_longjmp): Likewise.
* config/pdp11/pdp11.md (abshi2): Likewise.
* config/rs6000/rs6000.c (rs6000_emit_move): Likewise.
* config/s390/s390.c (s390_emit_prologue): Likewise.
* config/s390/s390.md (movmem_long, setmem_long): Likewise.
(cmpmem_long, extendsidi2, zero_extendsidi2, udivmoddi4): Likewise.
(builtin_setjmp_receiver, restore_stack_nonlocal): Likewise.
* config/sh/sh.c (prepare_move_operands): Likewise.
(output_stack_adjust, sh_expand_epilogue): Likewise.
(sh_set_return_address, sh_expand_t_scc): Likewise.
* config/sparc/sparc.c (load_pic_register): Likewise.
* config/sparc/sparc.md (untyped_return, nonlocal_goto): Likewise.
* config/spu/spu.c (spu_expand_epilogue): Likewise.
* config/v850/v850.c (expand_epilogue): Likewise.
From-SVN: r136251
2008-06-01 11:47:28 +02:00
|
|
|
|
emit_clobber (operands[0]);
|
bfin.md (<optab>di3): Now a define_expand which expands logical operations piecewise.
* config/bfin/bfin.md (<optab>di3): Now a define_expand which expands
logical operations piecewise.
(<optab>di_zesidi_di, <optab>di_sesidi_di, negdi2, one_cmpldi2,
zero_extendsidi2, subdi_di_zesidi, subdi_zesidi_di, subdi_di_sesidi,
subdi_sesidi_di): Delete.
(add_with_carry): Produce carry in CC instead of a DREG to shorten
the generated sequence. Allow three-reg add in constraints. Rewrite
the rtl expression for carry to avoid zero_extend of a constant.
(sub_with_carry): New pattern.
(adddi3, subdi3): Change into define_expand. For subtract, generate a
different sequence not involving jumps.
(notbi): Now a named pattern.
From-SVN: r124414
2007-05-04 13:00:00 +02:00
|
|
|
|
emit_insn (gen_sub_with_carry (xops[0], xops[2], xops[4], xops[7]));
|
|
|
|
|
emit_insn (gen_notbi (xops[7], xops[7]));
|
|
|
|
|
emit_insn (gen_movbisi (xops[6], xops[7]));
|
|
|
|
|
emit_insn (gen_subsi3 (xops[1], xops[3], xops[5]));
|
|
|
|
|
emit_insn (gen_subsi3 (xops[1], xops[1], xops[6]));
|
|
|
|
|
DONE;
|
|
|
|
|
})
|
2005-04-05 13:26:48 +02:00
|
|
|
|
|
|
|
|
|
;; Combined shift/add instructions
|
|
|
|
|
|
|
|
|
|
(define_insn ""
|
|
|
|
|
[(set (match_operand:SI 0 "register_operand" "=a,d")
|
|
|
|
|
(ashift:SI (plus:SI (match_operand:SI 1 "register_operand" "%0,0")
|
|
|
|
|
(match_operand:SI 2 "register_operand" "a,d"))
|
|
|
|
|
(match_operand:SI 3 "pos_scale_operand" "P1P2,P1P2")))]
|
|
|
|
|
""
|
|
|
|
|
"%0 = (%0 + %2) << %3;" /* "shadd %0,%2,%3;" */
|
|
|
|
|
[(set_attr "type" "alu0")])
|
|
|
|
|
|
|
|
|
|
(define_insn ""
|
|
|
|
|
[(set (match_operand:SI 0 "register_operand" "=a")
|
|
|
|
|
(plus:SI (match_operand:SI 1 "register_operand" "a")
|
|
|
|
|
(mult:SI (match_operand:SI 2 "register_operand" "a")
|
|
|
|
|
(match_operand:SI 3 "scale_by_operand" "i"))))]
|
|
|
|
|
""
|
|
|
|
|
"%0 = %1 + (%2 << %X3);"
|
|
|
|
|
[(set_attr "type" "alu0")])
|
|
|
|
|
|
|
|
|
|
(define_insn ""
|
|
|
|
|
[(set (match_operand:SI 0 "register_operand" "=a")
|
|
|
|
|
(plus:SI (match_operand:SI 1 "register_operand" "a")
|
|
|
|
|
(ashift:SI (match_operand:SI 2 "register_operand" "a")
|
|
|
|
|
(match_operand:SI 3 "pos_scale_operand" "i"))))]
|
|
|
|
|
""
|
|
|
|
|
"%0 = %1 + (%2 << %3);"
|
|
|
|
|
[(set_attr "type" "alu0")])
|
|
|
|
|
|
|
|
|
|
(define_insn ""
|
|
|
|
|
[(set (match_operand:SI 0 "register_operand" "=a")
|
|
|
|
|
(plus:SI (mult:SI (match_operand:SI 1 "register_operand" "a")
|
|
|
|
|
(match_operand:SI 2 "scale_by_operand" "i"))
|
|
|
|
|
(match_operand:SI 3 "register_operand" "a")))]
|
|
|
|
|
""
|
|
|
|
|
"%0 = %3 + (%1 << %X2);"
|
|
|
|
|
[(set_attr "type" "alu0")])
|
|
|
|
|
|
|
|
|
|
(define_insn ""
|
|
|
|
|
[(set (match_operand:SI 0 "register_operand" "=a")
|
|
|
|
|
(plus:SI (ashift:SI (match_operand:SI 1 "register_operand" "a")
|
|
|
|
|
(match_operand:SI 2 "pos_scale_operand" "i"))
|
|
|
|
|
(match_operand:SI 3 "register_operand" "a")))]
|
|
|
|
|
""
|
|
|
|
|
"%0 = %3 + (%1 << %2);"
|
|
|
|
|
[(set_attr "type" "alu0")])
|
|
|
|
|
|
|
|
|
|
(define_insn "mulhisi3"
|
|
|
|
|
[(set (match_operand:SI 0 "register_operand" "=d")
|
|
|
|
|
(mult:SI (sign_extend:SI (match_operand:HI 1 "register_operand" "%d"))
|
|
|
|
|
(sign_extend:SI (match_operand:HI 2 "register_operand" "d"))))]
|
|
|
|
|
""
|
rtlanal.c (note_uses): Deal with SEQUENCEs.
* rtlanal.c (note_uses): Deal with SEQUENCEs.
* config/bfin/bfin.c: Include "timevar.h".
(bfin_flag_schedule_insns2, splitting_for_sched,
bfin_flag_var_tracking): New variables.
(print_operand): Handle '%!'.
(override_options): Disable normal sched2 pass, instead set
bfin_flag_schedule_insns2 for reorg to handle it.
(output_file_start): Likewise for var-tracking.
(bfin_optimize_loop): Take some care not to stumble over SEQUENCEs.
(gen_one_bundle, bfin_gen_bundles, type_for_anomaly, trapping_loads_p):
New functions.
(bfin_reorg): Do second scheduling pass here, and call
bfin_gen_bundles. Use type_for_anomaly and trapping_loads_p instead
of examining insns directly. If bfin_flag_var_tracking, call
var-tracking pass when done with everything else.
* config/bfin/bfin.h (PRINT_OPERAND_PUNCT_VALID_P): '!' is valid.
* config/bfin/bfin.md (UNSPEC_32BIT): New constant.
(movsi_insn32): New pattern, with two new splits to create it
before the final scheduling pass.
(neghi2): Not a dsp32 insn, rather alu0.
(movbi, pushsi_insn, popsi_insn, movsi_insn, movv2hi_insn, movhi_insn,
movqi_insn, movsf_insn, movsi_insv, extendhisi2, zero_extendhisi2,
extendqihi2, extendqisi2, zero_extendqihi2, zero_extendqisi2,
mulhisi3, umulhisi3, ssadsi3, sssubsi3, smaxsi3, sminsi3, abssi2,
ssnegsi2, signbitssi2, smaxhi3, sminhi3, abshi2, ssneghi2, signbitshi2,
movhi_low2high, movhi_high2high, movhi_low2low, movhi_high2low,
movhiv2hi_low, movhiv2hi_high, composev2hi, packv2hi, movv2hi_hi,
ssaddhi3, sssubhi3, addv2hi3, ssaddv2hi3, subv2hi3, sssubv2hi3,
addsubv2hi3, subaddv2hi3, ssaddsubv2hi3, sssubaddv2hi3, sublohiv2hi3,
subhilov2hi3, sssublohiv2hi3, sssubhilov2hi3, addlohiv2hi3,
addhilov2hi3, ssaddlohiv2hi3, ssaddhilov2hi3, sminv2hi3, smaxv2hi3,
flag_mulhi, flag_mulhisi, flag_mulhisi_parts, flag_machi,
flag_machi_acconly, flag_macinithi, flag_macinit1hi, mulv2hi3,
flag_mulv2hi, flag_mulv2hi_parts, flag_macv2hi_parts,
flag_macv2hi_parts_acconly, flag_macinitv2hi_parts,
flag_macinit1v2hi_parts, mulhisi_ll, mulhisi_lh, mulhisi_hl,
mulhisi_hh, ssnegv2hi2, absv2hi2, ssashiftv2hi3, ssashifthi3,
lshiftv2hi3, lshifthi3): Use '%!' to terminate all dsp32/load/store
variants instead of ';'.
(ror_one, rol_one): Likewise. Make them dsp32 insns.
(ashlsi3_insn, ashrsi3, lshrsi3): Add dsp32 variants.
(align8, align16, align24): Now named patterns; also using '%!'.
(mnop): New insn.
From-SVN: r119534
2006-12-05 09:49:56 +01:00
|
|
|
|
"%0 = %h1 * %h2 (IS)%!"
|
2005-04-05 13:26:48 +02:00
|
|
|
|
[(set_attr "type" "dsp32")])
|
|
|
|
|
|
|
|
|
|
(define_insn "umulhisi3"
|
|
|
|
|
[(set (match_operand:SI 0 "register_operand" "=d")
|
|
|
|
|
(mult:SI (zero_extend:SI (match_operand:HI 1 "register_operand" "%d"))
|
|
|
|
|
(zero_extend:SI (match_operand:HI 2 "register_operand" "d"))))]
|
|
|
|
|
""
|
rtlanal.c (note_uses): Deal with SEQUENCEs.
* rtlanal.c (note_uses): Deal with SEQUENCEs.
* config/bfin/bfin.c: Include "timevar.h".
(bfin_flag_schedule_insns2, splitting_for_sched,
bfin_flag_var_tracking): New variables.
(print_operand): Handle '%!'.
(override_options): Disable normal sched2 pass, instead set
bfin_flag_schedule_insns2 for reorg to handle it.
(output_file_start): Likewise for var-tracking.
(bfin_optimize_loop): Take some care not to stumble over SEQUENCEs.
(gen_one_bundle, bfin_gen_bundles, type_for_anomaly, trapping_loads_p):
New functions.
(bfin_reorg): Do second scheduling pass here, and call
bfin_gen_bundles. Use type_for_anomaly and trapping_loads_p instead
of examining insns directly. If bfin_flag_var_tracking, call
var-tracking pass when done with everything else.
* config/bfin/bfin.h (PRINT_OPERAND_PUNCT_VALID_P): '!' is valid.
* config/bfin/bfin.md (UNSPEC_32BIT): New constant.
(movsi_insn32): New pattern, with two new splits to create it
before the final scheduling pass.
(neghi2): Not a dsp32 insn, rather alu0.
(movbi, pushsi_insn, popsi_insn, movsi_insn, movv2hi_insn, movhi_insn,
movqi_insn, movsf_insn, movsi_insv, extendhisi2, zero_extendhisi2,
extendqihi2, extendqisi2, zero_extendqihi2, zero_extendqisi2,
mulhisi3, umulhisi3, ssadsi3, sssubsi3, smaxsi3, sminsi3, abssi2,
ssnegsi2, signbitssi2, smaxhi3, sminhi3, abshi2, ssneghi2, signbitshi2,
movhi_low2high, movhi_high2high, movhi_low2low, movhi_high2low,
movhiv2hi_low, movhiv2hi_high, composev2hi, packv2hi, movv2hi_hi,
ssaddhi3, sssubhi3, addv2hi3, ssaddv2hi3, subv2hi3, sssubv2hi3,
addsubv2hi3, subaddv2hi3, ssaddsubv2hi3, sssubaddv2hi3, sublohiv2hi3,
subhilov2hi3, sssublohiv2hi3, sssubhilov2hi3, addlohiv2hi3,
addhilov2hi3, ssaddlohiv2hi3, ssaddhilov2hi3, sminv2hi3, smaxv2hi3,
flag_mulhi, flag_mulhisi, flag_mulhisi_parts, flag_machi,
flag_machi_acconly, flag_macinithi, flag_macinit1hi, mulv2hi3,
flag_mulv2hi, flag_mulv2hi_parts, flag_macv2hi_parts,
flag_macv2hi_parts_acconly, flag_macinitv2hi_parts,
flag_macinit1v2hi_parts, mulhisi_ll, mulhisi_lh, mulhisi_hl,
mulhisi_hh, ssnegv2hi2, absv2hi2, ssashiftv2hi3, ssashifthi3,
lshiftv2hi3, lshifthi3): Use '%!' to terminate all dsp32/load/store
variants instead of ';'.
(ror_one, rol_one): Likewise. Make them dsp32 insns.
(ashlsi3_insn, ashrsi3, lshrsi3): Add dsp32 variants.
(align8, align16, align24): Now named patterns; also using '%!'.
(mnop): New insn.
From-SVN: r119534
2006-12-05 09:49:56 +01:00
|
|
|
|
"%0 = %h1 * %h2 (FU)%!"
|
2005-04-05 13:26:48 +02:00
|
|
|
|
[(set_attr "type" "dsp32")])
|
|
|
|
|
|
2005-11-20 19:49:18 +01:00
|
|
|
|
(define_insn "usmulhisi3"
|
|
|
|
|
[(set (match_operand:SI 0 "register_operand" "=W")
|
|
|
|
|
(mult:SI (zero_extend:SI (match_operand:HI 1 "register_operand" "W"))
|
|
|
|
|
(sign_extend:SI (match_operand:HI 2 "register_operand" "W"))))]
|
|
|
|
|
""
|
rtlanal.c (note_uses): Deal with SEQUENCEs.
* rtlanal.c (note_uses): Deal with SEQUENCEs.
* config/bfin/bfin.c: Include "timevar.h".
(bfin_flag_schedule_insns2, splitting_for_sched,
bfin_flag_var_tracking): New variables.
(print_operand): Handle '%!'.
(override_options): Disable normal sched2 pass, instead set
bfin_flag_schedule_insns2 for reorg to handle it.
(output_file_start): Likewise for var-tracking.
(bfin_optimize_loop): Take some care not to stumble over SEQUENCEs.
(gen_one_bundle, bfin_gen_bundles, type_for_anomaly, trapping_loads_p):
New functions.
(bfin_reorg): Do second scheduling pass here, and call
bfin_gen_bundles. Use type_for_anomaly and trapping_loads_p instead
of examining insns directly. If bfin_flag_var_tracking, call
var-tracking pass when done with everything else.
* config/bfin/bfin.h (PRINT_OPERAND_PUNCT_VALID_P): '!' is valid.
* config/bfin/bfin.md (UNSPEC_32BIT): New constant.
(movsi_insn32): New pattern, with two new splits to create it
before the final scheduling pass.
(neghi2): Not a dsp32 insn, rather alu0.
(movbi, pushsi_insn, popsi_insn, movsi_insn, movv2hi_insn, movhi_insn,
movqi_insn, movsf_insn, movsi_insv, extendhisi2, zero_extendhisi2,
extendqihi2, extendqisi2, zero_extendqihi2, zero_extendqisi2,
mulhisi3, umulhisi3, ssadsi3, sssubsi3, smaxsi3, sminsi3, abssi2,
ssnegsi2, signbitssi2, smaxhi3, sminhi3, abshi2, ssneghi2, signbitshi2,
movhi_low2high, movhi_high2high, movhi_low2low, movhi_high2low,
movhiv2hi_low, movhiv2hi_high, composev2hi, packv2hi, movv2hi_hi,
ssaddhi3, sssubhi3, addv2hi3, ssaddv2hi3, subv2hi3, sssubv2hi3,
addsubv2hi3, subaddv2hi3, ssaddsubv2hi3, sssubaddv2hi3, sublohiv2hi3,
subhilov2hi3, sssublohiv2hi3, sssubhilov2hi3, addlohiv2hi3,
addhilov2hi3, ssaddlohiv2hi3, ssaddhilov2hi3, sminv2hi3, smaxv2hi3,
flag_mulhi, flag_mulhisi, flag_mulhisi_parts, flag_machi,
flag_machi_acconly, flag_macinithi, flag_macinit1hi, mulv2hi3,
flag_mulv2hi, flag_mulv2hi_parts, flag_macv2hi_parts,
flag_macv2hi_parts_acconly, flag_macinitv2hi_parts,
flag_macinit1v2hi_parts, mulhisi_ll, mulhisi_lh, mulhisi_hl,
mulhisi_hh, ssnegv2hi2, absv2hi2, ssashiftv2hi3, ssashifthi3,
lshiftv2hi3, lshifthi3): Use '%!' to terminate all dsp32/load/store
variants instead of ';'.
(ror_one, rol_one): Likewise. Make them dsp32 insns.
(ashlsi3_insn, ashrsi3, lshrsi3): Add dsp32 variants.
(align8, align16, align24): Now named patterns; also using '%!'.
(mnop): New insn.
From-SVN: r119534
2006-12-05 09:49:56 +01:00
|
|
|
|
"%0 = %h2 * %h1 (IS,M)%!"
|
2005-11-20 19:49:18 +01:00
|
|
|
|
[(set_attr "type" "dsp32")])
|
|
|
|
|
|
2011-05-04 13:14:54 +02:00
|
|
|
|
;; The alternative involving IREGS requires that the corresponding L register
|
|
|
|
|
;; is zero.
|
2005-04-05 13:26:48 +02:00
|
|
|
|
|
|
|
|
|
(define_insn "addsi3"
|
2011-05-04 13:14:54 +02:00
|
|
|
|
[(set (match_operand:SI 0 "register_operand" "=ad,a,d,b")
|
|
|
|
|
(plus:SI (match_operand:SI 1 "register_operand" "%0, a,d,0")
|
|
|
|
|
(match_operand:SI 2 "reg_or_7bit_operand" "Ks7, a,d,fP2P4")))]
|
2005-04-05 13:26:48 +02:00
|
|
|
|
""
|
|
|
|
|
"@
|
|
|
|
|
%0 += %2;
|
|
|
|
|
%0 = %1 + %2;
|
2011-05-04 13:14:54 +02:00
|
|
|
|
%0 = %1 + %2;
|
|
|
|
|
%0 += %2;"
|
2005-04-05 13:26:48 +02:00
|
|
|
|
[(set_attr "type" "alu0")
|
2011-05-04 13:14:54 +02:00
|
|
|
|
(set_attr "length" "2,2,2,2")])
|
2005-04-05 13:26:48 +02:00
|
|
|
|
|
genmodes.c (make_vector_mode): Allow making VECTOR_MODE_INT of a MODE_PARTIAL_INT mode.
* genmodes.c (make_vector_mode): Allow making VECTOR_MODE_INT of a
MODE_PARTIAL_INT mode.
* config/bfin/bfin-modes.def: Add V2PDI and V2SI.
* config/bfin/bfin.c (print_operand): Add macflag and mac/msu modifiers
for CONST_INTs.
(hard_regno_mode_ok): V2PDImode is ok for accumulators.
* config/bfin/bfin.h (CLASS_MAX_NREGS, HARD_REGNO_NREGS): Handle
V2PDImode.
* config/bfin/predicates.md (const01_operand, vec_shift_operand):
New predicates.
* config/bfin/bfin.md (UNSPEC_MUL_WITH_FLAG, UNSPEC_MAC_WITH_FLAG):
New constants.
(MACFLAG_NONE, MACFLAG_T, MACFLAG_FU, MACFLAG_TFU, MACFLAG_IS,
MACFLAG_IU, MACFLAG_W32, MACFLAG_M, MACFLAG_S2RND, MACFLAG_ISS2,
MACFLAG_IH): Likewise.
(movstricthi_1): Renamed from "*movstricthi".
(load_accumulator, load_accumulator_pair, movsi_insv, insv,
ssaddsi3, sssubsi3, ssnegsi2, signbitssi2, smaxhi3, sminhi3,
abshi2, neghi2, ssneghi2, signbitshi2, movhi_low2high,
movhi_high2high, movhi_low2low, movhi_high2low, movhiv2hi_low,
movhiv2hi_high, composev2hi, movv2hi_hi, movv2hi_hi_low,
movv2hi_hi_high, ssaddhi3, sssubhi3, ssaddv2hi3, sssubv2hi3,
addsubv2hi3, subaddv2hi3, ssaddsubv2hi3, sssubaddv2hi3,
sublohiv2hi3, subhilov2hi3, sssublohiv2hi3, sssubhilov2hi3,
addlohiv2hi3, addhilov2hi3, ssaddlohiv2hi3, ssaddhilov2hi3,
mulhisi_ll, mulhisi_lh, mulhisi_hl, mulhisi_hh, ssnegv2hi2,
ssashiftv2hi3, ssashifthi3, lshiftv2hi3, lshifthi3, packv2hi,
flag_mulhi, flag_mulhisi_parts, flag_machi, flag_machi_acconly,
flag_macinithi, flag_macinit1hi, flag_mulv2hi, flag_mulv2hi_parts,
flag_macv2hi_parts, flag_macv2hi_parts_acconly,
flag_macinitv2hi_parts, flag_macinit1v2hi_parts): New patterns.
From-SVN: r113245
2006-04-25 13:49:27 +02:00
|
|
|
|
(define_insn "ssaddsi3"
|
|
|
|
|
[(set (match_operand:SI 0 "register_operand" "=d")
|
|
|
|
|
(ss_plus:SI (match_operand:SI 1 "register_operand" "d")
|
|
|
|
|
(match_operand:SI 2 "register_operand" "d")))]
|
|
|
|
|
""
|
rtlanal.c (note_uses): Deal with SEQUENCEs.
* rtlanal.c (note_uses): Deal with SEQUENCEs.
* config/bfin/bfin.c: Include "timevar.h".
(bfin_flag_schedule_insns2, splitting_for_sched,
bfin_flag_var_tracking): New variables.
(print_operand): Handle '%!'.
(override_options): Disable normal sched2 pass, instead set
bfin_flag_schedule_insns2 for reorg to handle it.
(output_file_start): Likewise for var-tracking.
(bfin_optimize_loop): Take some care not to stumble over SEQUENCEs.
(gen_one_bundle, bfin_gen_bundles, type_for_anomaly, trapping_loads_p):
New functions.
(bfin_reorg): Do second scheduling pass here, and call
bfin_gen_bundles. Use type_for_anomaly and trapping_loads_p instead
of examining insns directly. If bfin_flag_var_tracking, call
var-tracking pass when done with everything else.
* config/bfin/bfin.h (PRINT_OPERAND_PUNCT_VALID_P): '!' is valid.
* config/bfin/bfin.md (UNSPEC_32BIT): New constant.
(movsi_insn32): New pattern, with two new splits to create it
before the final scheduling pass.
(neghi2): Not a dsp32 insn, rather alu0.
(movbi, pushsi_insn, popsi_insn, movsi_insn, movv2hi_insn, movhi_insn,
movqi_insn, movsf_insn, movsi_insv, extendhisi2, zero_extendhisi2,
extendqihi2, extendqisi2, zero_extendqihi2, zero_extendqisi2,
mulhisi3, umulhisi3, ssadsi3, sssubsi3, smaxsi3, sminsi3, abssi2,
ssnegsi2, signbitssi2, smaxhi3, sminhi3, abshi2, ssneghi2, signbitshi2,
movhi_low2high, movhi_high2high, movhi_low2low, movhi_high2low,
movhiv2hi_low, movhiv2hi_high, composev2hi, packv2hi, movv2hi_hi,
ssaddhi3, sssubhi3, addv2hi3, ssaddv2hi3, subv2hi3, sssubv2hi3,
addsubv2hi3, subaddv2hi3, ssaddsubv2hi3, sssubaddv2hi3, sublohiv2hi3,
subhilov2hi3, sssublohiv2hi3, sssubhilov2hi3, addlohiv2hi3,
addhilov2hi3, ssaddlohiv2hi3, ssaddhilov2hi3, sminv2hi3, smaxv2hi3,
flag_mulhi, flag_mulhisi, flag_mulhisi_parts, flag_machi,
flag_machi_acconly, flag_macinithi, flag_macinit1hi, mulv2hi3,
flag_mulv2hi, flag_mulv2hi_parts, flag_macv2hi_parts,
flag_macv2hi_parts_acconly, flag_macinitv2hi_parts,
flag_macinit1v2hi_parts, mulhisi_ll, mulhisi_lh, mulhisi_hl,
mulhisi_hh, ssnegv2hi2, absv2hi2, ssashiftv2hi3, ssashifthi3,
lshiftv2hi3, lshifthi3): Use '%!' to terminate all dsp32/load/store
variants instead of ';'.
(ror_one, rol_one): Likewise. Make them dsp32 insns.
(ashlsi3_insn, ashrsi3, lshrsi3): Add dsp32 variants.
(align8, align16, align24): Now named patterns; also using '%!'.
(mnop): New insn.
From-SVN: r119534
2006-12-05 09:49:56 +01:00
|
|
|
|
"%0 = %1 + %2 (S)%!"
|
genmodes.c (make_vector_mode): Allow making VECTOR_MODE_INT of a MODE_PARTIAL_INT mode.
* genmodes.c (make_vector_mode): Allow making VECTOR_MODE_INT of a
MODE_PARTIAL_INT mode.
* config/bfin/bfin-modes.def: Add V2PDI and V2SI.
* config/bfin/bfin.c (print_operand): Add macflag and mac/msu modifiers
for CONST_INTs.
(hard_regno_mode_ok): V2PDImode is ok for accumulators.
* config/bfin/bfin.h (CLASS_MAX_NREGS, HARD_REGNO_NREGS): Handle
V2PDImode.
* config/bfin/predicates.md (const01_operand, vec_shift_operand):
New predicates.
* config/bfin/bfin.md (UNSPEC_MUL_WITH_FLAG, UNSPEC_MAC_WITH_FLAG):
New constants.
(MACFLAG_NONE, MACFLAG_T, MACFLAG_FU, MACFLAG_TFU, MACFLAG_IS,
MACFLAG_IU, MACFLAG_W32, MACFLAG_M, MACFLAG_S2RND, MACFLAG_ISS2,
MACFLAG_IH): Likewise.
(movstricthi_1): Renamed from "*movstricthi".
(load_accumulator, load_accumulator_pair, movsi_insv, insv,
ssaddsi3, sssubsi3, ssnegsi2, signbitssi2, smaxhi3, sminhi3,
abshi2, neghi2, ssneghi2, signbitshi2, movhi_low2high,
movhi_high2high, movhi_low2low, movhi_high2low, movhiv2hi_low,
movhiv2hi_high, composev2hi, movv2hi_hi, movv2hi_hi_low,
movv2hi_hi_high, ssaddhi3, sssubhi3, ssaddv2hi3, sssubv2hi3,
addsubv2hi3, subaddv2hi3, ssaddsubv2hi3, sssubaddv2hi3,
sublohiv2hi3, subhilov2hi3, sssublohiv2hi3, sssubhilov2hi3,
addlohiv2hi3, addhilov2hi3, ssaddlohiv2hi3, ssaddhilov2hi3,
mulhisi_ll, mulhisi_lh, mulhisi_hl, mulhisi_hh, ssnegv2hi2,
ssashiftv2hi3, ssashifthi3, lshiftv2hi3, lshifthi3, packv2hi,
flag_mulhi, flag_mulhisi_parts, flag_machi, flag_machi_acconly,
flag_macinithi, flag_macinit1hi, flag_mulv2hi, flag_mulv2hi_parts,
flag_macv2hi_parts, flag_macv2hi_parts_acconly,
flag_macinitv2hi_parts, flag_macinit1v2hi_parts): New patterns.
From-SVN: r113245
2006-04-25 13:49:27 +02:00
|
|
|
|
[(set_attr "type" "dsp32")])
|
|
|
|
|
|
2006-10-05 12:46:41 +02:00
|
|
|
|
(define_insn "subsi3"
|
2005-04-05 13:26:48 +02:00
|
|
|
|
[(set (match_operand:SI 0 "register_operand" "=da,d,a")
|
|
|
|
|
(minus:SI (match_operand:SI 1 "register_operand" "0,d,0")
|
2006-10-05 12:46:41 +02:00
|
|
|
|
(match_operand:SI 2 "reg_or_neg7bit_operand" "KN7,d,a")))]
|
|
|
|
|
""
|
2005-04-05 13:26:48 +02:00
|
|
|
|
{
|
|
|
|
|
static const char *const strings_subsi3[] = {
|
|
|
|
|
"%0 += -%2;",
|
|
|
|
|
"%0 = %1 - %2;",
|
|
|
|
|
"%0 -= %2;",
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
if (CONSTANT_P (operands[2]) && INTVAL (operands[2]) < 0) {
|
|
|
|
|
rtx tmp_op = operands[2];
|
|
|
|
|
operands[2] = GEN_INT (-INTVAL (operands[2]));
|
|
|
|
|
output_asm_insn ("%0 += %2;", operands);
|
|
|
|
|
operands[2] = tmp_op;
|
|
|
|
|
return "";
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
return strings_subsi3[which_alternative];
|
|
|
|
|
}
|
|
|
|
|
[(set_attr "type" "alu0")])
|
|
|
|
|
|
genmodes.c (make_vector_mode): Allow making VECTOR_MODE_INT of a MODE_PARTIAL_INT mode.
* genmodes.c (make_vector_mode): Allow making VECTOR_MODE_INT of a
MODE_PARTIAL_INT mode.
* config/bfin/bfin-modes.def: Add V2PDI and V2SI.
* config/bfin/bfin.c (print_operand): Add macflag and mac/msu modifiers
for CONST_INTs.
(hard_regno_mode_ok): V2PDImode is ok for accumulators.
* config/bfin/bfin.h (CLASS_MAX_NREGS, HARD_REGNO_NREGS): Handle
V2PDImode.
* config/bfin/predicates.md (const01_operand, vec_shift_operand):
New predicates.
* config/bfin/bfin.md (UNSPEC_MUL_WITH_FLAG, UNSPEC_MAC_WITH_FLAG):
New constants.
(MACFLAG_NONE, MACFLAG_T, MACFLAG_FU, MACFLAG_TFU, MACFLAG_IS,
MACFLAG_IU, MACFLAG_W32, MACFLAG_M, MACFLAG_S2RND, MACFLAG_ISS2,
MACFLAG_IH): Likewise.
(movstricthi_1): Renamed from "*movstricthi".
(load_accumulator, load_accumulator_pair, movsi_insv, insv,
ssaddsi3, sssubsi3, ssnegsi2, signbitssi2, smaxhi3, sminhi3,
abshi2, neghi2, ssneghi2, signbitshi2, movhi_low2high,
movhi_high2high, movhi_low2low, movhi_high2low, movhiv2hi_low,
movhiv2hi_high, composev2hi, movv2hi_hi, movv2hi_hi_low,
movv2hi_hi_high, ssaddhi3, sssubhi3, ssaddv2hi3, sssubv2hi3,
addsubv2hi3, subaddv2hi3, ssaddsubv2hi3, sssubaddv2hi3,
sublohiv2hi3, subhilov2hi3, sssublohiv2hi3, sssubhilov2hi3,
addlohiv2hi3, addhilov2hi3, ssaddlohiv2hi3, ssaddhilov2hi3,
mulhisi_ll, mulhisi_lh, mulhisi_hl, mulhisi_hh, ssnegv2hi2,
ssashiftv2hi3, ssashifthi3, lshiftv2hi3, lshifthi3, packv2hi,
flag_mulhi, flag_mulhisi_parts, flag_machi, flag_machi_acconly,
flag_macinithi, flag_macinit1hi, flag_mulv2hi, flag_mulv2hi_parts,
flag_macv2hi_parts, flag_macv2hi_parts_acconly,
flag_macinitv2hi_parts, flag_macinit1v2hi_parts): New patterns.
From-SVN: r113245
2006-04-25 13:49:27 +02:00
|
|
|
|
(define_insn "sssubsi3"
|
|
|
|
|
[(set (match_operand:SI 0 "register_operand" "=d")
|
|
|
|
|
(ss_minus:SI (match_operand:SI 1 "register_operand" "d")
|
|
|
|
|
(match_operand:SI 2 "register_operand" "d")))]
|
|
|
|
|
""
|
rtlanal.c (note_uses): Deal with SEQUENCEs.
* rtlanal.c (note_uses): Deal with SEQUENCEs.
* config/bfin/bfin.c: Include "timevar.h".
(bfin_flag_schedule_insns2, splitting_for_sched,
bfin_flag_var_tracking): New variables.
(print_operand): Handle '%!'.
(override_options): Disable normal sched2 pass, instead set
bfin_flag_schedule_insns2 for reorg to handle it.
(output_file_start): Likewise for var-tracking.
(bfin_optimize_loop): Take some care not to stumble over SEQUENCEs.
(gen_one_bundle, bfin_gen_bundles, type_for_anomaly, trapping_loads_p):
New functions.
(bfin_reorg): Do second scheduling pass here, and call
bfin_gen_bundles. Use type_for_anomaly and trapping_loads_p instead
of examining insns directly. If bfin_flag_var_tracking, call
var-tracking pass when done with everything else.
* config/bfin/bfin.h (PRINT_OPERAND_PUNCT_VALID_P): '!' is valid.
* config/bfin/bfin.md (UNSPEC_32BIT): New constant.
(movsi_insn32): New pattern, with two new splits to create it
before the final scheduling pass.
(neghi2): Not a dsp32 insn, rather alu0.
(movbi, pushsi_insn, popsi_insn, movsi_insn, movv2hi_insn, movhi_insn,
movqi_insn, movsf_insn, movsi_insv, extendhisi2, zero_extendhisi2,
extendqihi2, extendqisi2, zero_extendqihi2, zero_extendqisi2,
mulhisi3, umulhisi3, ssadsi3, sssubsi3, smaxsi3, sminsi3, abssi2,
ssnegsi2, signbitssi2, smaxhi3, sminhi3, abshi2, ssneghi2, signbitshi2,
movhi_low2high, movhi_high2high, movhi_low2low, movhi_high2low,
movhiv2hi_low, movhiv2hi_high, composev2hi, packv2hi, movv2hi_hi,
ssaddhi3, sssubhi3, addv2hi3, ssaddv2hi3, subv2hi3, sssubv2hi3,
addsubv2hi3, subaddv2hi3, ssaddsubv2hi3, sssubaddv2hi3, sublohiv2hi3,
subhilov2hi3, sssublohiv2hi3, sssubhilov2hi3, addlohiv2hi3,
addhilov2hi3, ssaddlohiv2hi3, ssaddhilov2hi3, sminv2hi3, smaxv2hi3,
flag_mulhi, flag_mulhisi, flag_mulhisi_parts, flag_machi,
flag_machi_acconly, flag_macinithi, flag_macinit1hi, mulv2hi3,
flag_mulv2hi, flag_mulv2hi_parts, flag_macv2hi_parts,
flag_macv2hi_parts_acconly, flag_macinitv2hi_parts,
flag_macinit1v2hi_parts, mulhisi_ll, mulhisi_lh, mulhisi_hl,
mulhisi_hh, ssnegv2hi2, absv2hi2, ssashiftv2hi3, ssashifthi3,
lshiftv2hi3, lshifthi3): Use '%!' to terminate all dsp32/load/store
variants instead of ';'.
(ror_one, rol_one): Likewise. Make them dsp32 insns.
(ashlsi3_insn, ashrsi3, lshrsi3): Add dsp32 variants.
(align8, align16, align24): Now named patterns; also using '%!'.
(mnop): New insn.
From-SVN: r119534
2006-12-05 09:49:56 +01:00
|
|
|
|
"%0 = %1 - %2 (S)%!"
|
genmodes.c (make_vector_mode): Allow making VECTOR_MODE_INT of a MODE_PARTIAL_INT mode.
* genmodes.c (make_vector_mode): Allow making VECTOR_MODE_INT of a
MODE_PARTIAL_INT mode.
* config/bfin/bfin-modes.def: Add V2PDI and V2SI.
* config/bfin/bfin.c (print_operand): Add macflag and mac/msu modifiers
for CONST_INTs.
(hard_regno_mode_ok): V2PDImode is ok for accumulators.
* config/bfin/bfin.h (CLASS_MAX_NREGS, HARD_REGNO_NREGS): Handle
V2PDImode.
* config/bfin/predicates.md (const01_operand, vec_shift_operand):
New predicates.
* config/bfin/bfin.md (UNSPEC_MUL_WITH_FLAG, UNSPEC_MAC_WITH_FLAG):
New constants.
(MACFLAG_NONE, MACFLAG_T, MACFLAG_FU, MACFLAG_TFU, MACFLAG_IS,
MACFLAG_IU, MACFLAG_W32, MACFLAG_M, MACFLAG_S2RND, MACFLAG_ISS2,
MACFLAG_IH): Likewise.
(movstricthi_1): Renamed from "*movstricthi".
(load_accumulator, load_accumulator_pair, movsi_insv, insv,
ssaddsi3, sssubsi3, ssnegsi2, signbitssi2, smaxhi3, sminhi3,
abshi2, neghi2, ssneghi2, signbitshi2, movhi_low2high,
movhi_high2high, movhi_low2low, movhi_high2low, movhiv2hi_low,
movhiv2hi_high, composev2hi, movv2hi_hi, movv2hi_hi_low,
movv2hi_hi_high, ssaddhi3, sssubhi3, ssaddv2hi3, sssubv2hi3,
addsubv2hi3, subaddv2hi3, ssaddsubv2hi3, sssubaddv2hi3,
sublohiv2hi3, subhilov2hi3, sssublohiv2hi3, sssubhilov2hi3,
addlohiv2hi3, addhilov2hi3, ssaddlohiv2hi3, ssaddhilov2hi3,
mulhisi_ll, mulhisi_lh, mulhisi_hl, mulhisi_hh, ssnegv2hi2,
ssashiftv2hi3, ssashifthi3, lshiftv2hi3, lshifthi3, packv2hi,
flag_mulhi, flag_mulhisi_parts, flag_machi, flag_machi_acconly,
flag_macinithi, flag_macinit1hi, flag_mulv2hi, flag_mulv2hi_parts,
flag_macv2hi_parts, flag_macv2hi_parts_acconly,
flag_macinitv2hi_parts, flag_macinit1v2hi_parts): New patterns.
From-SVN: r113245
2006-04-25 13:49:27 +02:00
|
|
|
|
[(set_attr "type" "dsp32")])
|
|
|
|
|
|
2007-04-12 15:03:17 +02:00
|
|
|
|
;; Accumulator addition
|
|
|
|
|
|
2007-05-03 15:17:51 +02:00
|
|
|
|
(define_insn "addpdi3"
|
|
|
|
|
[(set (match_operand:PDI 0 "register_operand" "=A")
|
|
|
|
|
(ss_plus:PDI (match_operand:PDI 1 "register_operand" "%0")
|
|
|
|
|
(match_operand:PDI 2 "nonmemory_operand" "B")))]
|
|
|
|
|
""
|
|
|
|
|
"A0 += A1%!"
|
|
|
|
|
[(set_attr "type" "dsp32")])
|
|
|
|
|
|
2007-04-12 15:03:17 +02:00
|
|
|
|
(define_insn "sum_of_accumulators"
|
|
|
|
|
[(set (match_operand:SI 0 "register_operand" "=d")
|
|
|
|
|
(ss_truncate:SI
|
|
|
|
|
(ss_plus:PDI (match_operand:PDI 2 "register_operand" "1")
|
|
|
|
|
(match_operand:PDI 3 "register_operand" "B"))))
|
|
|
|
|
(set (match_operand:PDI 1 "register_operand" "=A")
|
|
|
|
|
(ss_plus:PDI (match_dup 2) (match_dup 3)))]
|
|
|
|
|
""
|
|
|
|
|
"%0 = (A0 += A1)%!"
|
|
|
|
|
[(set_attr "type" "dsp32")])
|
|
|
|
|
|
2007-05-03 15:17:51 +02:00
|
|
|
|
(define_insn "us_truncpdisi2"
|
|
|
|
|
[(set (match_operand:SI 0 "register_operand" "=D,W")
|
|
|
|
|
(us_truncate:SI (match_operand:PDI 1 "register_operand" "A,B")))]
|
|
|
|
|
""
|
|
|
|
|
"%0 = %1 (FU)%!"
|
|
|
|
|
[(set_attr "type" "dsp32")])
|
|
|
|
|
|
2005-04-05 13:26:48 +02:00
|
|
|
|
;; Bit test instructions
|
|
|
|
|
|
|
|
|
|
(define_insn "*not_bittst"
|
2006-02-21 16:32:21 +01:00
|
|
|
|
[(set (match_operand:BI 0 "register_operand" "=C")
|
2005-04-05 13:26:48 +02:00
|
|
|
|
(eq:BI (zero_extract:SI (match_operand:SI 1 "register_operand" "d")
|
|
|
|
|
(const_int 1)
|
|
|
|
|
(match_operand:SI 2 "immediate_operand" "Ku5"))
|
|
|
|
|
(const_int 0)))]
|
|
|
|
|
""
|
|
|
|
|
"cc = !BITTST (%1,%2);"
|
|
|
|
|
[(set_attr "type" "alu0")])
|
|
|
|
|
|
|
|
|
|
(define_insn "*bittst"
|
2006-02-21 16:32:21 +01:00
|
|
|
|
[(set (match_operand:BI 0 "register_operand" "=C")
|
2005-04-05 13:26:48 +02:00
|
|
|
|
(ne:BI (zero_extract:SI (match_operand:SI 1 "register_operand" "d")
|
|
|
|
|
(const_int 1)
|
|
|
|
|
(match_operand:SI 2 "immediate_operand" "Ku5"))
|
|
|
|
|
(const_int 0)))]
|
|
|
|
|
""
|
|
|
|
|
"cc = BITTST (%1,%2);"
|
|
|
|
|
[(set_attr "type" "alu0")])
|
|
|
|
|
|
|
|
|
|
(define_insn_and_split "*bit_extract"
|
|
|
|
|
[(set (match_operand:SI 0 "register_operand" "=d")
|
|
|
|
|
(zero_extract:SI (match_operand:SI 1 "register_operand" "d")
|
|
|
|
|
(const_int 1)
|
|
|
|
|
(match_operand:SI 2 "immediate_operand" "Ku5")))
|
|
|
|
|
(clobber (reg:BI REG_CC))]
|
|
|
|
|
""
|
|
|
|
|
"#"
|
|
|
|
|
""
|
|
|
|
|
[(set (reg:BI REG_CC)
|
|
|
|
|
(ne:BI (zero_extract:SI (match_dup 1) (const_int 1) (match_dup 2))
|
|
|
|
|
(const_int 0)))
|
|
|
|
|
(set (match_dup 0)
|
|
|
|
|
(ne:SI (reg:BI REG_CC) (const_int 0)))])
|
|
|
|
|
|
|
|
|
|
(define_insn_and_split "*not_bit_extract"
|
|
|
|
|
[(set (match_operand:SI 0 "register_operand" "=d")
|
|
|
|
|
(zero_extract:SI (not:SI (match_operand:SI 1 "register_operand" "d"))
|
|
|
|
|
(const_int 1)
|
|
|
|
|
(match_operand:SI 2 "immediate_operand" "Ku5")))
|
|
|
|
|
(clobber (reg:BI REG_CC))]
|
|
|
|
|
""
|
|
|
|
|
"#"
|
|
|
|
|
""
|
|
|
|
|
[(set (reg:BI REG_CC)
|
|
|
|
|
(eq:BI (zero_extract:SI (match_dup 1) (const_int 1) (match_dup 2))
|
|
|
|
|
(const_int 0)))
|
|
|
|
|
(set (match_dup 0)
|
|
|
|
|
(ne:SI (reg:BI REG_CC) (const_int 0)))])
|
|
|
|
|
|
|
|
|
|
(define_insn "*andsi_insn"
|
|
|
|
|
[(set (match_operand:SI 0 "register_operand" "=d,d,d,d")
|
|
|
|
|
(and:SI (match_operand:SI 1 "register_operand" "%0,d,d,d")
|
|
|
|
|
(match_operand:SI 2 "rhs_andsi3_operand" "L,M1,M2,d")))]
|
|
|
|
|
""
|
|
|
|
|
"@
|
|
|
|
|
BITCLR (%0,%Y2);
|
|
|
|
|
%0 = %T1 (Z);
|
|
|
|
|
%0 = %h1 (Z);
|
|
|
|
|
%0 = %1 & %2;"
|
|
|
|
|
[(set_attr "type" "alu0")])
|
|
|
|
|
|
|
|
|
|
(define_expand "andsi3"
|
|
|
|
|
[(set (match_operand:SI 0 "register_operand" "")
|
|
|
|
|
(and:SI (match_operand:SI 1 "register_operand" "")
|
|
|
|
|
(match_operand:SI 2 "general_operand" "")))]
|
|
|
|
|
""
|
|
|
|
|
{
|
|
|
|
|
if (highbits_operand (operands[2], SImode))
|
|
|
|
|
{
|
|
|
|
|
operands[2] = GEN_INT (exact_log2 (-INTVAL (operands[2])));
|
|
|
|
|
emit_insn (gen_ashrsi3 (operands[0], operands[1], operands[2]));
|
|
|
|
|
emit_insn (gen_ashlsi3 (operands[0], operands[0], operands[2]));
|
|
|
|
|
DONE;
|
|
|
|
|
}
|
|
|
|
|
if (! rhs_andsi3_operand (operands[2], SImode))
|
|
|
|
|
operands[2] = force_reg (SImode, operands[2]);
|
|
|
|
|
})
|
|
|
|
|
|
|
|
|
|
(define_insn "iorsi3"
|
|
|
|
|
[(set (match_operand:SI 0 "register_operand" "=d,d")
|
|
|
|
|
(ior:SI (match_operand:SI 1 "register_operand" "%0,d")
|
|
|
|
|
(match_operand:SI 2 "regorlog2_operand" "J,d")))]
|
|
|
|
|
""
|
|
|
|
|
"@
|
|
|
|
|
BITSET (%0, %X2);
|
|
|
|
|
%0 = %1 | %2;"
|
|
|
|
|
[(set_attr "type" "alu0")])
|
|
|
|
|
|
|
|
|
|
(define_insn "xorsi3"
|
|
|
|
|
[(set (match_operand:SI 0 "register_operand" "=d,d")
|
|
|
|
|
(xor:SI (match_operand:SI 1 "register_operand" "%0,d")
|
|
|
|
|
(match_operand:SI 2 "regorlog2_operand" "J,d")))]
|
|
|
|
|
""
|
|
|
|
|
"@
|
|
|
|
|
BITTGL (%0, %X2);
|
|
|
|
|
%0 = %1 ^ %2;"
|
|
|
|
|
[(set_attr "type" "alu0")])
|
|
|
|
|
|
From Jie Zhang:
* config/bfin/bfin.c (enum bfin_builtins): Add BFIN_BUILTIN_ONES,
BFIN_BUILTIN_CPLX_MUL_16_S40, BFIN_BUILTIN_CPLX_MAC_16_S40,
BFIN_BUILTIN_CPLX_MSU_16_S40, and BFIN_BUILTIN_CPLX_SQU.
(bfin_init_builtins): Initialize __builtin_bfin_ones,
__builtin_bfin_min_fr1x16, __builtin_bfin_max_fr1x16,
__builtin_bfin_min_fr1x32, __builtin_bfin_max_fr1x32,
__builtin_bfin_cmplx_add, __builtin_bfin_cmplx_sub,
__builtin_bfin_cmplx_mul_s40, __builtin_bfin_cmplx_mac_s40,
__builtin_bfin_cmplx_msu_s40 and __builtin_bfin_csqu_fr16.
(bdesc_1arg): Add __builtin_bfin_ones.
(bfin_expand_builtin): Expand __builtin_bfin_cmplx_mul_s40,
__builtin_bfin_cmplx_mac_s40, __builtin_bfin_cmplx_msu_s40,
and __builtin_bfin_csqu_fr16.
* config/bfin/bfin.md (UNSPEC_ONES): New constant.
(ones): New define_insn.
(ssaddhi3_parts): New define_insn.
(sssubhi3_parts): New define_insn.
(flag_mulhi_parts): New define_insn.
From-SVN: r128475
2007-09-13 20:27:28 +02:00
|
|
|
|
(define_insn "ones"
|
|
|
|
|
[(set (match_operand:HI 0 "register_operand" "=d")
|
2021-10-18 12:56:56 +02:00
|
|
|
|
(truncate:HI
|
|
|
|
|
(popcount:SI (match_operand:SI 1 "register_operand" "d"))))]
|
From Jie Zhang:
* config/bfin/bfin.c (enum bfin_builtins): Add BFIN_BUILTIN_ONES,
BFIN_BUILTIN_CPLX_MUL_16_S40, BFIN_BUILTIN_CPLX_MAC_16_S40,
BFIN_BUILTIN_CPLX_MSU_16_S40, and BFIN_BUILTIN_CPLX_SQU.
(bfin_init_builtins): Initialize __builtin_bfin_ones,
__builtin_bfin_min_fr1x16, __builtin_bfin_max_fr1x16,
__builtin_bfin_min_fr1x32, __builtin_bfin_max_fr1x32,
__builtin_bfin_cmplx_add, __builtin_bfin_cmplx_sub,
__builtin_bfin_cmplx_mul_s40, __builtin_bfin_cmplx_mac_s40,
__builtin_bfin_cmplx_msu_s40 and __builtin_bfin_csqu_fr16.
(bdesc_1arg): Add __builtin_bfin_ones.
(bfin_expand_builtin): Expand __builtin_bfin_cmplx_mul_s40,
__builtin_bfin_cmplx_mac_s40, __builtin_bfin_cmplx_msu_s40,
and __builtin_bfin_csqu_fr16.
* config/bfin/bfin.md (UNSPEC_ONES): New constant.
(ones): New define_insn.
(ssaddhi3_parts): New define_insn.
(sssubhi3_parts): New define_insn.
(flag_mulhi_parts): New define_insn.
From-SVN: r128475
2007-09-13 20:27:28 +02:00
|
|
|
|
""
|
|
|
|
|
"%h0 = ONES %1;"
|
|
|
|
|
[(set_attr "type" "alu0")])
|
|
|
|
|
|
2021-10-18 12:56:56 +02:00
|
|
|
|
(define_expand "popcountsi2"
|
|
|
|
|
[(set (match_dup 2)
|
|
|
|
|
(truncate:HI (popcount:SI (match_operand:SI 1 "register_operand" ""))))
|
|
|
|
|
(set (match_operand:SI 0 "register_operand")
|
|
|
|
|
(zero_extend:SI (match_dup 2)))]
|
|
|
|
|
""
|
|
|
|
|
{
|
|
|
|
|
operands[2] = gen_reg_rtx (HImode);
|
|
|
|
|
})
|
|
|
|
|
|
|
|
|
|
(define_expand "popcounthi2"
|
|
|
|
|
[(set (match_dup 2)
|
|
|
|
|
(zero_extend:SI (match_operand:HI 1 "register_operand" "")))
|
|
|
|
|
(set (match_operand:HI 0 "register_operand")
|
|
|
|
|
(truncate:HI (popcount:SI (match_dup 2))))]
|
|
|
|
|
""
|
|
|
|
|
{
|
|
|
|
|
operands[2] = gen_reg_rtx (SImode);
|
|
|
|
|
})
|
|
|
|
|
|
2005-04-05 13:26:48 +02:00
|
|
|
|
(define_insn "smaxsi3"
|
|
|
|
|
[(set (match_operand:SI 0 "register_operand" "=d")
|
|
|
|
|
(smax:SI (match_operand:SI 1 "register_operand" "d")
|
|
|
|
|
(match_operand:SI 2 "register_operand" "d")))]
|
|
|
|
|
""
|
rtlanal.c (note_uses): Deal with SEQUENCEs.
* rtlanal.c (note_uses): Deal with SEQUENCEs.
* config/bfin/bfin.c: Include "timevar.h".
(bfin_flag_schedule_insns2, splitting_for_sched,
bfin_flag_var_tracking): New variables.
(print_operand): Handle '%!'.
(override_options): Disable normal sched2 pass, instead set
bfin_flag_schedule_insns2 for reorg to handle it.
(output_file_start): Likewise for var-tracking.
(bfin_optimize_loop): Take some care not to stumble over SEQUENCEs.
(gen_one_bundle, bfin_gen_bundles, type_for_anomaly, trapping_loads_p):
New functions.
(bfin_reorg): Do second scheduling pass here, and call
bfin_gen_bundles. Use type_for_anomaly and trapping_loads_p instead
of examining insns directly. If bfin_flag_var_tracking, call
var-tracking pass when done with everything else.
* config/bfin/bfin.h (PRINT_OPERAND_PUNCT_VALID_P): '!' is valid.
* config/bfin/bfin.md (UNSPEC_32BIT): New constant.
(movsi_insn32): New pattern, with two new splits to create it
before the final scheduling pass.
(neghi2): Not a dsp32 insn, rather alu0.
(movbi, pushsi_insn, popsi_insn, movsi_insn, movv2hi_insn, movhi_insn,
movqi_insn, movsf_insn, movsi_insv, extendhisi2, zero_extendhisi2,
extendqihi2, extendqisi2, zero_extendqihi2, zero_extendqisi2,
mulhisi3, umulhisi3, ssadsi3, sssubsi3, smaxsi3, sminsi3, abssi2,
ssnegsi2, signbitssi2, smaxhi3, sminhi3, abshi2, ssneghi2, signbitshi2,
movhi_low2high, movhi_high2high, movhi_low2low, movhi_high2low,
movhiv2hi_low, movhiv2hi_high, composev2hi, packv2hi, movv2hi_hi,
ssaddhi3, sssubhi3, addv2hi3, ssaddv2hi3, subv2hi3, sssubv2hi3,
addsubv2hi3, subaddv2hi3, ssaddsubv2hi3, sssubaddv2hi3, sublohiv2hi3,
subhilov2hi3, sssublohiv2hi3, sssubhilov2hi3, addlohiv2hi3,
addhilov2hi3, ssaddlohiv2hi3, ssaddhilov2hi3, sminv2hi3, smaxv2hi3,
flag_mulhi, flag_mulhisi, flag_mulhisi_parts, flag_machi,
flag_machi_acconly, flag_macinithi, flag_macinit1hi, mulv2hi3,
flag_mulv2hi, flag_mulv2hi_parts, flag_macv2hi_parts,
flag_macv2hi_parts_acconly, flag_macinitv2hi_parts,
flag_macinit1v2hi_parts, mulhisi_ll, mulhisi_lh, mulhisi_hl,
mulhisi_hh, ssnegv2hi2, absv2hi2, ssashiftv2hi3, ssashifthi3,
lshiftv2hi3, lshifthi3): Use '%!' to terminate all dsp32/load/store
variants instead of ';'.
(ror_one, rol_one): Likewise. Make them dsp32 insns.
(ashlsi3_insn, ashrsi3, lshrsi3): Add dsp32 variants.
(align8, align16, align24): Now named patterns; also using '%!'.
(mnop): New insn.
From-SVN: r119534
2006-12-05 09:49:56 +01:00
|
|
|
|
"%0 = max(%1,%2)%!"
|
2005-04-05 13:26:48 +02:00
|
|
|
|
[(set_attr "type" "dsp32")])
|
|
|
|
|
|
|
|
|
|
(define_insn "sminsi3"
|
|
|
|
|
[(set (match_operand:SI 0 "register_operand" "=d")
|
|
|
|
|
(smin:SI (match_operand:SI 1 "register_operand" "d")
|
|
|
|
|
(match_operand:SI 2 "register_operand" "d")))]
|
|
|
|
|
""
|
rtlanal.c (note_uses): Deal with SEQUENCEs.
* rtlanal.c (note_uses): Deal with SEQUENCEs.
* config/bfin/bfin.c: Include "timevar.h".
(bfin_flag_schedule_insns2, splitting_for_sched,
bfin_flag_var_tracking): New variables.
(print_operand): Handle '%!'.
(override_options): Disable normal sched2 pass, instead set
bfin_flag_schedule_insns2 for reorg to handle it.
(output_file_start): Likewise for var-tracking.
(bfin_optimize_loop): Take some care not to stumble over SEQUENCEs.
(gen_one_bundle, bfin_gen_bundles, type_for_anomaly, trapping_loads_p):
New functions.
(bfin_reorg): Do second scheduling pass here, and call
bfin_gen_bundles. Use type_for_anomaly and trapping_loads_p instead
of examining insns directly. If bfin_flag_var_tracking, call
var-tracking pass when done with everything else.
* config/bfin/bfin.h (PRINT_OPERAND_PUNCT_VALID_P): '!' is valid.
* config/bfin/bfin.md (UNSPEC_32BIT): New constant.
(movsi_insn32): New pattern, with two new splits to create it
before the final scheduling pass.
(neghi2): Not a dsp32 insn, rather alu0.
(movbi, pushsi_insn, popsi_insn, movsi_insn, movv2hi_insn, movhi_insn,
movqi_insn, movsf_insn, movsi_insv, extendhisi2, zero_extendhisi2,
extendqihi2, extendqisi2, zero_extendqihi2, zero_extendqisi2,
mulhisi3, umulhisi3, ssadsi3, sssubsi3, smaxsi3, sminsi3, abssi2,
ssnegsi2, signbitssi2, smaxhi3, sminhi3, abshi2, ssneghi2, signbitshi2,
movhi_low2high, movhi_high2high, movhi_low2low, movhi_high2low,
movhiv2hi_low, movhiv2hi_high, composev2hi, packv2hi, movv2hi_hi,
ssaddhi3, sssubhi3, addv2hi3, ssaddv2hi3, subv2hi3, sssubv2hi3,
addsubv2hi3, subaddv2hi3, ssaddsubv2hi3, sssubaddv2hi3, sublohiv2hi3,
subhilov2hi3, sssublohiv2hi3, sssubhilov2hi3, addlohiv2hi3,
addhilov2hi3, ssaddlohiv2hi3, ssaddhilov2hi3, sminv2hi3, smaxv2hi3,
flag_mulhi, flag_mulhisi, flag_mulhisi_parts, flag_machi,
flag_machi_acconly, flag_macinithi, flag_macinit1hi, mulv2hi3,
flag_mulv2hi, flag_mulv2hi_parts, flag_macv2hi_parts,
flag_macv2hi_parts_acconly, flag_macinitv2hi_parts,
flag_macinit1v2hi_parts, mulhisi_ll, mulhisi_lh, mulhisi_hl,
mulhisi_hh, ssnegv2hi2, absv2hi2, ssashiftv2hi3, ssashifthi3,
lshiftv2hi3, lshifthi3): Use '%!' to terminate all dsp32/load/store
variants instead of ';'.
(ror_one, rol_one): Likewise. Make them dsp32 insns.
(ashlsi3_insn, ashrsi3, lshrsi3): Add dsp32 variants.
(align8, align16, align24): Now named patterns; also using '%!'.
(mnop): New insn.
From-SVN: r119534
2006-12-05 09:49:56 +01:00
|
|
|
|
"%0 = min(%1,%2)%!"
|
2005-04-05 13:26:48 +02:00
|
|
|
|
[(set_attr "type" "dsp32")])
|
|
|
|
|
|
|
|
|
|
(define_insn "abssi2"
|
|
|
|
|
[(set (match_operand:SI 0 "register_operand" "=d")
|
genmodes.c (make_vector_mode): Allow making VECTOR_MODE_INT of a MODE_PARTIAL_INT mode.
* genmodes.c (make_vector_mode): Allow making VECTOR_MODE_INT of a
MODE_PARTIAL_INT mode.
* config/bfin/bfin-modes.def: Add V2PDI and V2SI.
* config/bfin/bfin.c (print_operand): Add macflag and mac/msu modifiers
for CONST_INTs.
(hard_regno_mode_ok): V2PDImode is ok for accumulators.
* config/bfin/bfin.h (CLASS_MAX_NREGS, HARD_REGNO_NREGS): Handle
V2PDImode.
* config/bfin/predicates.md (const01_operand, vec_shift_operand):
New predicates.
* config/bfin/bfin.md (UNSPEC_MUL_WITH_FLAG, UNSPEC_MAC_WITH_FLAG):
New constants.
(MACFLAG_NONE, MACFLAG_T, MACFLAG_FU, MACFLAG_TFU, MACFLAG_IS,
MACFLAG_IU, MACFLAG_W32, MACFLAG_M, MACFLAG_S2RND, MACFLAG_ISS2,
MACFLAG_IH): Likewise.
(movstricthi_1): Renamed from "*movstricthi".
(load_accumulator, load_accumulator_pair, movsi_insv, insv,
ssaddsi3, sssubsi3, ssnegsi2, signbitssi2, smaxhi3, sminhi3,
abshi2, neghi2, ssneghi2, signbitshi2, movhi_low2high,
movhi_high2high, movhi_low2low, movhi_high2low, movhiv2hi_low,
movhiv2hi_high, composev2hi, movv2hi_hi, movv2hi_hi_low,
movv2hi_hi_high, ssaddhi3, sssubhi3, ssaddv2hi3, sssubv2hi3,
addsubv2hi3, subaddv2hi3, ssaddsubv2hi3, sssubaddv2hi3,
sublohiv2hi3, subhilov2hi3, sssublohiv2hi3, sssubhilov2hi3,
addlohiv2hi3, addhilov2hi3, ssaddlohiv2hi3, ssaddhilov2hi3,
mulhisi_ll, mulhisi_lh, mulhisi_hl, mulhisi_hh, ssnegv2hi2,
ssashiftv2hi3, ssashifthi3, lshiftv2hi3, lshifthi3, packv2hi,
flag_mulhi, flag_mulhisi_parts, flag_machi, flag_machi_acconly,
flag_macinithi, flag_macinit1hi, flag_mulv2hi, flag_mulv2hi_parts,
flag_macv2hi_parts, flag_macv2hi_parts_acconly,
flag_macinitv2hi_parts, flag_macinit1v2hi_parts): New patterns.
From-SVN: r113245
2006-04-25 13:49:27 +02:00
|
|
|
|
(abs:SI (match_operand:SI 1 "register_operand" "d")))]
|
2005-04-05 13:26:48 +02:00
|
|
|
|
""
|
rtlanal.c (note_uses): Deal with SEQUENCEs.
* rtlanal.c (note_uses): Deal with SEQUENCEs.
* config/bfin/bfin.c: Include "timevar.h".
(bfin_flag_schedule_insns2, splitting_for_sched,
bfin_flag_var_tracking): New variables.
(print_operand): Handle '%!'.
(override_options): Disable normal sched2 pass, instead set
bfin_flag_schedule_insns2 for reorg to handle it.
(output_file_start): Likewise for var-tracking.
(bfin_optimize_loop): Take some care not to stumble over SEQUENCEs.
(gen_one_bundle, bfin_gen_bundles, type_for_anomaly, trapping_loads_p):
New functions.
(bfin_reorg): Do second scheduling pass here, and call
bfin_gen_bundles. Use type_for_anomaly and trapping_loads_p instead
of examining insns directly. If bfin_flag_var_tracking, call
var-tracking pass when done with everything else.
* config/bfin/bfin.h (PRINT_OPERAND_PUNCT_VALID_P): '!' is valid.
* config/bfin/bfin.md (UNSPEC_32BIT): New constant.
(movsi_insn32): New pattern, with two new splits to create it
before the final scheduling pass.
(neghi2): Not a dsp32 insn, rather alu0.
(movbi, pushsi_insn, popsi_insn, movsi_insn, movv2hi_insn, movhi_insn,
movqi_insn, movsf_insn, movsi_insv, extendhisi2, zero_extendhisi2,
extendqihi2, extendqisi2, zero_extendqihi2, zero_extendqisi2,
mulhisi3, umulhisi3, ssadsi3, sssubsi3, smaxsi3, sminsi3, abssi2,
ssnegsi2, signbitssi2, smaxhi3, sminhi3, abshi2, ssneghi2, signbitshi2,
movhi_low2high, movhi_high2high, movhi_low2low, movhi_high2low,
movhiv2hi_low, movhiv2hi_high, composev2hi, packv2hi, movv2hi_hi,
ssaddhi3, sssubhi3, addv2hi3, ssaddv2hi3, subv2hi3, sssubv2hi3,
addsubv2hi3, subaddv2hi3, ssaddsubv2hi3, sssubaddv2hi3, sublohiv2hi3,
subhilov2hi3, sssublohiv2hi3, sssubhilov2hi3, addlohiv2hi3,
addhilov2hi3, ssaddlohiv2hi3, ssaddhilov2hi3, sminv2hi3, smaxv2hi3,
flag_mulhi, flag_mulhisi, flag_mulhisi_parts, flag_machi,
flag_machi_acconly, flag_macinithi, flag_macinit1hi, mulv2hi3,
flag_mulv2hi, flag_mulv2hi_parts, flag_macv2hi_parts,
flag_macv2hi_parts_acconly, flag_macinitv2hi_parts,
flag_macinit1v2hi_parts, mulhisi_ll, mulhisi_lh, mulhisi_hl,
mulhisi_hh, ssnegv2hi2, absv2hi2, ssashiftv2hi3, ssashifthi3,
lshiftv2hi3, lshifthi3): Use '%!' to terminate all dsp32/load/store
variants instead of ';'.
(ror_one, rol_one): Likewise. Make them dsp32 insns.
(ashlsi3_insn, ashrsi3, lshrsi3): Add dsp32 variants.
(align8, align16, align24): Now named patterns; also using '%!'.
(mnop): New insn.
From-SVN: r119534
2006-12-05 09:49:56 +01:00
|
|
|
|
"%0 = abs %1%!"
|
2005-04-05 13:26:48 +02:00
|
|
|
|
[(set_attr "type" "dsp32")])
|
|
|
|
|
|
rtl.def (SS_ABS): New code.
* rtl.def (SS_ABS): New code.
* config/bfin/bfin.c (print_operand): New modifier 'v'.
(enum bfin_builtins): Add BFIN_BUILTIN_SUM_2X16, BFIN_BUILTIN_ABS_1x32,
BFIN_BUILTIN_ROUND_1x32, BFIN_BUILTIN_MULT_1x32x32,
BFIN_BUILTIN_MULT_1x32x32NS, BFIN_BUILTIN_SSASHIFT_1x32.
(bfin_init_builtins): Define them.
(bdesc_1arg, bdesc_2arg): Add some of them here, ...
(bfin_expand_builtin): ... and handle the others here.
* config/bfin/bfin.md (ssabssi2, ssroundsi2, ssashiftsi3,
flag_mul_macv2hi_parts_acconly_andcc0): New patterns.
(ss_absv2hi2): Renamed from absv2hi; use ss_abs code.
(ssashiftv2hi3, ssashifthi3, lshiftv2hi3, lshifthi3): Shift count
operand is only HImode.
From-SVN: r124280
2007-04-29 15:22:04 +02:00
|
|
|
|
(define_insn "ssabssi2"
|
|
|
|
|
[(set (match_operand:SI 0 "register_operand" "=d")
|
|
|
|
|
(ss_abs:SI (match_operand:SI 1 "register_operand" "d")))]
|
|
|
|
|
""
|
|
|
|
|
"%0 = abs %1%!"
|
|
|
|
|
[(set_attr "type" "dsp32")])
|
|
|
|
|
|
2005-04-05 13:26:48 +02:00
|
|
|
|
(define_insn "negsi2"
|
|
|
|
|
[(set (match_operand:SI 0 "register_operand" "=d")
|
genmodes.c (make_vector_mode): Allow making VECTOR_MODE_INT of a MODE_PARTIAL_INT mode.
* genmodes.c (make_vector_mode): Allow making VECTOR_MODE_INT of a
MODE_PARTIAL_INT mode.
* config/bfin/bfin-modes.def: Add V2PDI and V2SI.
* config/bfin/bfin.c (print_operand): Add macflag and mac/msu modifiers
for CONST_INTs.
(hard_regno_mode_ok): V2PDImode is ok for accumulators.
* config/bfin/bfin.h (CLASS_MAX_NREGS, HARD_REGNO_NREGS): Handle
V2PDImode.
* config/bfin/predicates.md (const01_operand, vec_shift_operand):
New predicates.
* config/bfin/bfin.md (UNSPEC_MUL_WITH_FLAG, UNSPEC_MAC_WITH_FLAG):
New constants.
(MACFLAG_NONE, MACFLAG_T, MACFLAG_FU, MACFLAG_TFU, MACFLAG_IS,
MACFLAG_IU, MACFLAG_W32, MACFLAG_M, MACFLAG_S2RND, MACFLAG_ISS2,
MACFLAG_IH): Likewise.
(movstricthi_1): Renamed from "*movstricthi".
(load_accumulator, load_accumulator_pair, movsi_insv, insv,
ssaddsi3, sssubsi3, ssnegsi2, signbitssi2, smaxhi3, sminhi3,
abshi2, neghi2, ssneghi2, signbitshi2, movhi_low2high,
movhi_high2high, movhi_low2low, movhi_high2low, movhiv2hi_low,
movhiv2hi_high, composev2hi, movv2hi_hi, movv2hi_hi_low,
movv2hi_hi_high, ssaddhi3, sssubhi3, ssaddv2hi3, sssubv2hi3,
addsubv2hi3, subaddv2hi3, ssaddsubv2hi3, sssubaddv2hi3,
sublohiv2hi3, subhilov2hi3, sssublohiv2hi3, sssubhilov2hi3,
addlohiv2hi3, addhilov2hi3, ssaddlohiv2hi3, ssaddhilov2hi3,
mulhisi_ll, mulhisi_lh, mulhisi_hl, mulhisi_hh, ssnegv2hi2,
ssashiftv2hi3, ssashifthi3, lshiftv2hi3, lshifthi3, packv2hi,
flag_mulhi, flag_mulhisi_parts, flag_machi, flag_machi_acconly,
flag_macinithi, flag_macinit1hi, flag_mulv2hi, flag_mulv2hi_parts,
flag_macv2hi_parts, flag_macv2hi_parts_acconly,
flag_macinitv2hi_parts, flag_macinit1v2hi_parts): New patterns.
From-SVN: r113245
2006-04-25 13:49:27 +02:00
|
|
|
|
(neg:SI (match_operand:SI 1 "register_operand" "d")))]
|
2005-04-05 13:26:48 +02:00
|
|
|
|
""
|
genmodes.c (make_vector_mode): Allow making VECTOR_MODE_INT of a MODE_PARTIAL_INT mode.
* genmodes.c (make_vector_mode): Allow making VECTOR_MODE_INT of a
MODE_PARTIAL_INT mode.
* config/bfin/bfin-modes.def: Add V2PDI and V2SI.
* config/bfin/bfin.c (print_operand): Add macflag and mac/msu modifiers
for CONST_INTs.
(hard_regno_mode_ok): V2PDImode is ok for accumulators.
* config/bfin/bfin.h (CLASS_MAX_NREGS, HARD_REGNO_NREGS): Handle
V2PDImode.
* config/bfin/predicates.md (const01_operand, vec_shift_operand):
New predicates.
* config/bfin/bfin.md (UNSPEC_MUL_WITH_FLAG, UNSPEC_MAC_WITH_FLAG):
New constants.
(MACFLAG_NONE, MACFLAG_T, MACFLAG_FU, MACFLAG_TFU, MACFLAG_IS,
MACFLAG_IU, MACFLAG_W32, MACFLAG_M, MACFLAG_S2RND, MACFLAG_ISS2,
MACFLAG_IH): Likewise.
(movstricthi_1): Renamed from "*movstricthi".
(load_accumulator, load_accumulator_pair, movsi_insv, insv,
ssaddsi3, sssubsi3, ssnegsi2, signbitssi2, smaxhi3, sminhi3,
abshi2, neghi2, ssneghi2, signbitshi2, movhi_low2high,
movhi_high2high, movhi_low2low, movhi_high2low, movhiv2hi_low,
movhiv2hi_high, composev2hi, movv2hi_hi, movv2hi_hi_low,
movv2hi_hi_high, ssaddhi3, sssubhi3, ssaddv2hi3, sssubv2hi3,
addsubv2hi3, subaddv2hi3, ssaddsubv2hi3, sssubaddv2hi3,
sublohiv2hi3, subhilov2hi3, sssublohiv2hi3, sssubhilov2hi3,
addlohiv2hi3, addhilov2hi3, ssaddlohiv2hi3, ssaddhilov2hi3,
mulhisi_ll, mulhisi_lh, mulhisi_hl, mulhisi_hh, ssnegv2hi2,
ssashiftv2hi3, ssashifthi3, lshiftv2hi3, lshifthi3, packv2hi,
flag_mulhi, flag_mulhisi_parts, flag_machi, flag_machi_acconly,
flag_macinithi, flag_macinit1hi, flag_mulv2hi, flag_mulv2hi_parts,
flag_macv2hi_parts, flag_macv2hi_parts_acconly,
flag_macinitv2hi_parts, flag_macinit1v2hi_parts): New patterns.
From-SVN: r113245
2006-04-25 13:49:27 +02:00
|
|
|
|
"%0 = -%1;"
|
2005-04-05 13:26:48 +02:00
|
|
|
|
[(set_attr "type" "alu0")])
|
|
|
|
|
|
genmodes.c (make_vector_mode): Allow making VECTOR_MODE_INT of a MODE_PARTIAL_INT mode.
* genmodes.c (make_vector_mode): Allow making VECTOR_MODE_INT of a
MODE_PARTIAL_INT mode.
* config/bfin/bfin-modes.def: Add V2PDI and V2SI.
* config/bfin/bfin.c (print_operand): Add macflag and mac/msu modifiers
for CONST_INTs.
(hard_regno_mode_ok): V2PDImode is ok for accumulators.
* config/bfin/bfin.h (CLASS_MAX_NREGS, HARD_REGNO_NREGS): Handle
V2PDImode.
* config/bfin/predicates.md (const01_operand, vec_shift_operand):
New predicates.
* config/bfin/bfin.md (UNSPEC_MUL_WITH_FLAG, UNSPEC_MAC_WITH_FLAG):
New constants.
(MACFLAG_NONE, MACFLAG_T, MACFLAG_FU, MACFLAG_TFU, MACFLAG_IS,
MACFLAG_IU, MACFLAG_W32, MACFLAG_M, MACFLAG_S2RND, MACFLAG_ISS2,
MACFLAG_IH): Likewise.
(movstricthi_1): Renamed from "*movstricthi".
(load_accumulator, load_accumulator_pair, movsi_insv, insv,
ssaddsi3, sssubsi3, ssnegsi2, signbitssi2, smaxhi3, sminhi3,
abshi2, neghi2, ssneghi2, signbitshi2, movhi_low2high,
movhi_high2high, movhi_low2low, movhi_high2low, movhiv2hi_low,
movhiv2hi_high, composev2hi, movv2hi_hi, movv2hi_hi_low,
movv2hi_hi_high, ssaddhi3, sssubhi3, ssaddv2hi3, sssubv2hi3,
addsubv2hi3, subaddv2hi3, ssaddsubv2hi3, sssubaddv2hi3,
sublohiv2hi3, subhilov2hi3, sssublohiv2hi3, sssubhilov2hi3,
addlohiv2hi3, addhilov2hi3, ssaddlohiv2hi3, ssaddhilov2hi3,
mulhisi_ll, mulhisi_lh, mulhisi_hl, mulhisi_hh, ssnegv2hi2,
ssashiftv2hi3, ssashifthi3, lshiftv2hi3, lshifthi3, packv2hi,
flag_mulhi, flag_mulhisi_parts, flag_machi, flag_machi_acconly,
flag_macinithi, flag_macinit1hi, flag_mulv2hi, flag_mulv2hi_parts,
flag_macv2hi_parts, flag_macv2hi_parts_acconly,
flag_macinitv2hi_parts, flag_macinit1v2hi_parts): New patterns.
From-SVN: r113245
2006-04-25 13:49:27 +02:00
|
|
|
|
(define_insn "ssnegsi2"
|
|
|
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|
[(set (match_operand:SI 0 "register_operand" "=d")
|
|
|
|
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(ss_neg:SI (match_operand:SI 1 "register_operand" "d")))]
|
|
|
|
|
""
|
rtlanal.c (note_uses): Deal with SEQUENCEs.
* rtlanal.c (note_uses): Deal with SEQUENCEs.
* config/bfin/bfin.c: Include "timevar.h".
(bfin_flag_schedule_insns2, splitting_for_sched,
bfin_flag_var_tracking): New variables.
(print_operand): Handle '%!'.
(override_options): Disable normal sched2 pass, instead set
bfin_flag_schedule_insns2 for reorg to handle it.
(output_file_start): Likewise for var-tracking.
(bfin_optimize_loop): Take some care not to stumble over SEQUENCEs.
(gen_one_bundle, bfin_gen_bundles, type_for_anomaly, trapping_loads_p):
New functions.
(bfin_reorg): Do second scheduling pass here, and call
bfin_gen_bundles. Use type_for_anomaly and trapping_loads_p instead
of examining insns directly. If bfin_flag_var_tracking, call
var-tracking pass when done with everything else.
* config/bfin/bfin.h (PRINT_OPERAND_PUNCT_VALID_P): '!' is valid.
* config/bfin/bfin.md (UNSPEC_32BIT): New constant.
(movsi_insn32): New pattern, with two new splits to create it
before the final scheduling pass.
(neghi2): Not a dsp32 insn, rather alu0.
(movbi, pushsi_insn, popsi_insn, movsi_insn, movv2hi_insn, movhi_insn,
movqi_insn, movsf_insn, movsi_insv, extendhisi2, zero_extendhisi2,
extendqihi2, extendqisi2, zero_extendqihi2, zero_extendqisi2,
mulhisi3, umulhisi3, ssadsi3, sssubsi3, smaxsi3, sminsi3, abssi2,
ssnegsi2, signbitssi2, smaxhi3, sminhi3, abshi2, ssneghi2, signbitshi2,
movhi_low2high, movhi_high2high, movhi_low2low, movhi_high2low,
movhiv2hi_low, movhiv2hi_high, composev2hi, packv2hi, movv2hi_hi,
ssaddhi3, sssubhi3, addv2hi3, ssaddv2hi3, subv2hi3, sssubv2hi3,
addsubv2hi3, subaddv2hi3, ssaddsubv2hi3, sssubaddv2hi3, sublohiv2hi3,
subhilov2hi3, sssublohiv2hi3, sssubhilov2hi3, addlohiv2hi3,
addhilov2hi3, ssaddlohiv2hi3, ssaddhilov2hi3, sminv2hi3, smaxv2hi3,
flag_mulhi, flag_mulhisi, flag_mulhisi_parts, flag_machi,
flag_machi_acconly, flag_macinithi, flag_macinit1hi, mulv2hi3,
flag_mulv2hi, flag_mulv2hi_parts, flag_macv2hi_parts,
flag_macv2hi_parts_acconly, flag_macinitv2hi_parts,
flag_macinit1v2hi_parts, mulhisi_ll, mulhisi_lh, mulhisi_hl,
mulhisi_hh, ssnegv2hi2, absv2hi2, ssashiftv2hi3, ssashifthi3,
lshiftv2hi3, lshifthi3): Use '%!' to terminate all dsp32/load/store
variants instead of ';'.
(ror_one, rol_one): Likewise. Make them dsp32 insns.
(ashlsi3_insn, ashrsi3, lshrsi3): Add dsp32 variants.
(align8, align16, align24): Now named patterns; also using '%!'.
(mnop): New insn.
From-SVN: r119534
2006-12-05 09:49:56 +01:00
|
|
|
|
"%0 = -%1 (S)%!"
|
genmodes.c (make_vector_mode): Allow making VECTOR_MODE_INT of a MODE_PARTIAL_INT mode.
* genmodes.c (make_vector_mode): Allow making VECTOR_MODE_INT of a
MODE_PARTIAL_INT mode.
* config/bfin/bfin-modes.def: Add V2PDI and V2SI.
* config/bfin/bfin.c (print_operand): Add macflag and mac/msu modifiers
for CONST_INTs.
(hard_regno_mode_ok): V2PDImode is ok for accumulators.
* config/bfin/bfin.h (CLASS_MAX_NREGS, HARD_REGNO_NREGS): Handle
V2PDImode.
* config/bfin/predicates.md (const01_operand, vec_shift_operand):
New predicates.
* config/bfin/bfin.md (UNSPEC_MUL_WITH_FLAG, UNSPEC_MAC_WITH_FLAG):
New constants.
(MACFLAG_NONE, MACFLAG_T, MACFLAG_FU, MACFLAG_TFU, MACFLAG_IS,
MACFLAG_IU, MACFLAG_W32, MACFLAG_M, MACFLAG_S2RND, MACFLAG_ISS2,
MACFLAG_IH): Likewise.
(movstricthi_1): Renamed from "*movstricthi".
(load_accumulator, load_accumulator_pair, movsi_insv, insv,
ssaddsi3, sssubsi3, ssnegsi2, signbitssi2, smaxhi3, sminhi3,
abshi2, neghi2, ssneghi2, signbitshi2, movhi_low2high,
movhi_high2high, movhi_low2low, movhi_high2low, movhiv2hi_low,
movhiv2hi_high, composev2hi, movv2hi_hi, movv2hi_hi_low,
movv2hi_hi_high, ssaddhi3, sssubhi3, ssaddv2hi3, sssubv2hi3,
addsubv2hi3, subaddv2hi3, ssaddsubv2hi3, sssubaddv2hi3,
sublohiv2hi3, subhilov2hi3, sssublohiv2hi3, sssubhilov2hi3,
addlohiv2hi3, addhilov2hi3, ssaddlohiv2hi3, ssaddhilov2hi3,
mulhisi_ll, mulhisi_lh, mulhisi_hl, mulhisi_hh, ssnegv2hi2,
ssashiftv2hi3, ssashifthi3, lshiftv2hi3, lshifthi3, packv2hi,
flag_mulhi, flag_mulhisi_parts, flag_machi, flag_machi_acconly,
flag_macinithi, flag_macinit1hi, flag_mulv2hi, flag_mulv2hi_parts,
flag_macv2hi_parts, flag_macv2hi_parts_acconly,
flag_macinitv2hi_parts, flag_macinit1v2hi_parts): New patterns.
From-SVN: r113245
2006-04-25 13:49:27 +02:00
|
|
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[(set_attr "type" "dsp32")])
|
|
|
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|
2005-04-05 13:26:48 +02:00
|
|
|
|
(define_insn "one_cmplsi2"
|
|
|
|
|
[(set (match_operand:SI 0 "register_operand" "=d")
|
genmodes.c (make_vector_mode): Allow making VECTOR_MODE_INT of a MODE_PARTIAL_INT mode.
* genmodes.c (make_vector_mode): Allow making VECTOR_MODE_INT of a
MODE_PARTIAL_INT mode.
* config/bfin/bfin-modes.def: Add V2PDI and V2SI.
* config/bfin/bfin.c (print_operand): Add macflag and mac/msu modifiers
for CONST_INTs.
(hard_regno_mode_ok): V2PDImode is ok for accumulators.
* config/bfin/bfin.h (CLASS_MAX_NREGS, HARD_REGNO_NREGS): Handle
V2PDImode.
* config/bfin/predicates.md (const01_operand, vec_shift_operand):
New predicates.
* config/bfin/bfin.md (UNSPEC_MUL_WITH_FLAG, UNSPEC_MAC_WITH_FLAG):
New constants.
(MACFLAG_NONE, MACFLAG_T, MACFLAG_FU, MACFLAG_TFU, MACFLAG_IS,
MACFLAG_IU, MACFLAG_W32, MACFLAG_M, MACFLAG_S2RND, MACFLAG_ISS2,
MACFLAG_IH): Likewise.
(movstricthi_1): Renamed from "*movstricthi".
(load_accumulator, load_accumulator_pair, movsi_insv, insv,
ssaddsi3, sssubsi3, ssnegsi2, signbitssi2, smaxhi3, sminhi3,
abshi2, neghi2, ssneghi2, signbitshi2, movhi_low2high,
movhi_high2high, movhi_low2low, movhi_high2low, movhiv2hi_low,
movhiv2hi_high, composev2hi, movv2hi_hi, movv2hi_hi_low,
movv2hi_hi_high, ssaddhi3, sssubhi3, ssaddv2hi3, sssubv2hi3,
addsubv2hi3, subaddv2hi3, ssaddsubv2hi3, sssubaddv2hi3,
sublohiv2hi3, subhilov2hi3, sssublohiv2hi3, sssubhilov2hi3,
addlohiv2hi3, addhilov2hi3, ssaddlohiv2hi3, ssaddhilov2hi3,
mulhisi_ll, mulhisi_lh, mulhisi_hl, mulhisi_hh, ssnegv2hi2,
ssashiftv2hi3, ssashifthi3, lshiftv2hi3, lshifthi3, packv2hi,
flag_mulhi, flag_mulhisi_parts, flag_machi, flag_machi_acconly,
flag_macinithi, flag_macinit1hi, flag_mulv2hi, flag_mulv2hi_parts,
flag_macv2hi_parts, flag_macv2hi_parts_acconly,
flag_macinitv2hi_parts, flag_macinit1v2hi_parts): New patterns.
From-SVN: r113245
2006-04-25 13:49:27 +02:00
|
|
|
|
(not:SI (match_operand:SI 1 "register_operand" "d")))]
|
2005-04-05 13:26:48 +02:00
|
|
|
|
""
|
genmodes.c (make_vector_mode): Allow making VECTOR_MODE_INT of a MODE_PARTIAL_INT mode.
* genmodes.c (make_vector_mode): Allow making VECTOR_MODE_INT of a
MODE_PARTIAL_INT mode.
* config/bfin/bfin-modes.def: Add V2PDI and V2SI.
* config/bfin/bfin.c (print_operand): Add macflag and mac/msu modifiers
for CONST_INTs.
(hard_regno_mode_ok): V2PDImode is ok for accumulators.
* config/bfin/bfin.h (CLASS_MAX_NREGS, HARD_REGNO_NREGS): Handle
V2PDImode.
* config/bfin/predicates.md (const01_operand, vec_shift_operand):
New predicates.
* config/bfin/bfin.md (UNSPEC_MUL_WITH_FLAG, UNSPEC_MAC_WITH_FLAG):
New constants.
(MACFLAG_NONE, MACFLAG_T, MACFLAG_FU, MACFLAG_TFU, MACFLAG_IS,
MACFLAG_IU, MACFLAG_W32, MACFLAG_M, MACFLAG_S2RND, MACFLAG_ISS2,
MACFLAG_IH): Likewise.
(movstricthi_1): Renamed from "*movstricthi".
(load_accumulator, load_accumulator_pair, movsi_insv, insv,
ssaddsi3, sssubsi3, ssnegsi2, signbitssi2, smaxhi3, sminhi3,
abshi2, neghi2, ssneghi2, signbitshi2, movhi_low2high,
movhi_high2high, movhi_low2low, movhi_high2low, movhiv2hi_low,
movhiv2hi_high, composev2hi, movv2hi_hi, movv2hi_hi_low,
movv2hi_hi_high, ssaddhi3, sssubhi3, ssaddv2hi3, sssubv2hi3,
addsubv2hi3, subaddv2hi3, ssaddsubv2hi3, sssubaddv2hi3,
sublohiv2hi3, subhilov2hi3, sssublohiv2hi3, sssubhilov2hi3,
addlohiv2hi3, addhilov2hi3, ssaddlohiv2hi3, ssaddhilov2hi3,
mulhisi_ll, mulhisi_lh, mulhisi_hl, mulhisi_hh, ssnegv2hi2,
ssashiftv2hi3, ssashifthi3, lshiftv2hi3, lshifthi3, packv2hi,
flag_mulhi, flag_mulhisi_parts, flag_machi, flag_machi_acconly,
flag_macinithi, flag_macinit1hi, flag_mulv2hi, flag_mulv2hi_parts,
flag_macv2hi_parts, flag_macv2hi_parts_acconly,
flag_macinitv2hi_parts, flag_macinit1v2hi_parts): New patterns.
From-SVN: r113245
2006-04-25 13:49:27 +02:00
|
|
|
|
"%0 = ~%1;"
|
2005-04-05 13:26:48 +02:00
|
|
|
|
[(set_attr "type" "alu0")])
|
|
|
|
|
|
Makefile.in (lib2funcs): Add _clrsbsi2 and _clrsbdi2.
libgcc/
* Makefile.in (lib2funcs): Add _clrsbsi2 and _clrsbdi2.
* libgcc-std.ver.in (GCC_4.7.0): New section.
gcc/
* doc/extend.texi (__builtin_clrsb, __builtin_clrsbl,
__builtin_clrsbll): Document.
* doc/rtl.texi (clrsb): New entry.
* optabs.c (widen_leading): Renamed from widen_clz. New argument
UNOPTAB. All callers changed. Use UNOPTAB instead of clz_optab.
(expand_unop): Handle clrsb_optab.
(init_optabs): Initialize it.
* optabs.h (enum optab_index): New entry OTI_clrsb.
(clrsb_optab): Define.
* genopinit.c (optabs): Add an entry for it.
* builtins.c (expand_builtin): Handle clrsb builtin functions.
* builtins.def (BUILT_IN_CLRSB, BUILT_IN_CLRSBIMAX, BUILT_IN_CLRSBL,
BUILT_IN_CLRSBLL): New.
* rtl.def (CLRSB): New code.
* dwarf2out.c (mem_loc_descriptor): Handle it.
* simplify-rtx.c (simplify_const_unary_operation): Likewise.
Use op_mode rather than mode when optimizing ffs, clz, ctz, parity
and popcount.
* libgcc2.c (__clrsbSI2, __clrsbDI2): New functions.
* libgcc2.h (__clrsbSI2, __clrsbDI2): Define and declare.
(__ctzDI2): Move declaration.
* config/bfin/bfin.md (clrsbsi2): New expander.
(signbitssi2): Use the CLRSB rtx.
(clrsbhi2): Renamed from signbitshi2. Use the CLRSB rtx.
* config/bfin/bfin.c (bdesc_1arg): Changed accordingly.
gcc/testsuite/
* gcc.c-torture/excute/builtin-bitops-1.c (MAKE_FUNS): Make
my_clrsb test functions.
(main): Test clrsb.
* gcc.dg/builtin-protos-1.c (test_s, test_u, test_sl, test_ul,
test_sll, test_ull): Add clrsb tests.
* gcc.dg/torture/builtin-attr-1.c: Add tests for clrsb, clrsbl,
clrsbll.
From-SVN: r175261
2011-06-21 16:16:39 +02:00
|
|
|
|
(define_expand "clrsbsi2"
|
|
|
|
|
[(set (match_dup 2)
|
re PR middle-end/50161 (wrong code with -fno-tree-ter and __builtin_popcountl)
PR middle-end/50161
* simplify-rtx.c (simplify_const_unary_operation): If
op is CONST_INT, don't look at op_mode, but use instead
mode.
* optabs.c (add_equal_note): For FFS, CLZ, CTZ,
CLRSB, POPCOUNT, PARITY and BSWAP use operand mode for
operation and TRUNCATE/ZERO_EXTEND if needed.
* doc/rtl.texi (ffs, clrsb, clz, ctz, popcount, parity, bswap):
Document that operand mode must be same as operation mode,
or VOIDmode.
* config/avr/avr.md (paritysi2, *parityqihi2.libgcc,
*paritysihi2.libgcc, popcountsi2, *popcountsi2.libgcc,
*popcountqihi2.libgcc, clzsi2, *clzsihi2.libgcc, ctzsi2,
*ctzsihi2.libgcc, ffssi2, *ffssihi2.libgcc): For unary ops
use the mode of operand for the operation and add truncate
or zero_extend around if needed.
* config/c6x/c6x.md (ctzdi2): Likewise.
* config/bfin/bfin.md (clrsbsi2, signbitssi2): Likewise.
* gcc.dg/pr50161.c: New test.
From-SVN: r177991
2011-08-23 17:51:45 +02:00
|
|
|
|
(truncate:HI (clrsb:SI (match_operand:SI 1 "register_operand" "d"))))
|
Makefile.in (lib2funcs): Add _clrsbsi2 and _clrsbdi2.
libgcc/
* Makefile.in (lib2funcs): Add _clrsbsi2 and _clrsbdi2.
* libgcc-std.ver.in (GCC_4.7.0): New section.
gcc/
* doc/extend.texi (__builtin_clrsb, __builtin_clrsbl,
__builtin_clrsbll): Document.
* doc/rtl.texi (clrsb): New entry.
* optabs.c (widen_leading): Renamed from widen_clz. New argument
UNOPTAB. All callers changed. Use UNOPTAB instead of clz_optab.
(expand_unop): Handle clrsb_optab.
(init_optabs): Initialize it.
* optabs.h (enum optab_index): New entry OTI_clrsb.
(clrsb_optab): Define.
* genopinit.c (optabs): Add an entry for it.
* builtins.c (expand_builtin): Handle clrsb builtin functions.
* builtins.def (BUILT_IN_CLRSB, BUILT_IN_CLRSBIMAX, BUILT_IN_CLRSBL,
BUILT_IN_CLRSBLL): New.
* rtl.def (CLRSB): New code.
* dwarf2out.c (mem_loc_descriptor): Handle it.
* simplify-rtx.c (simplify_const_unary_operation): Likewise.
Use op_mode rather than mode when optimizing ffs, clz, ctz, parity
and popcount.
* libgcc2.c (__clrsbSI2, __clrsbDI2): New functions.
* libgcc2.h (__clrsbSI2, __clrsbDI2): Define and declare.
(__ctzDI2): Move declaration.
* config/bfin/bfin.md (clrsbsi2): New expander.
(signbitssi2): Use the CLRSB rtx.
(clrsbhi2): Renamed from signbitshi2. Use the CLRSB rtx.
* config/bfin/bfin.c (bdesc_1arg): Changed accordingly.
gcc/testsuite/
* gcc.c-torture/excute/builtin-bitops-1.c (MAKE_FUNS): Make
my_clrsb test functions.
(main): Test clrsb.
* gcc.dg/builtin-protos-1.c (test_s, test_u, test_sl, test_ul,
test_sll, test_ull): Add clrsb tests.
* gcc.dg/torture/builtin-attr-1.c: Add tests for clrsb, clrsbl,
clrsbll.
From-SVN: r175261
2011-06-21 16:16:39 +02:00
|
|
|
|
(set (match_operand:SI 0 "register_operand")
|
|
|
|
|
(zero_extend:SI (match_dup 2)))]
|
|
|
|
|
""
|
|
|
|
|
{
|
|
|
|
|
operands[2] = gen_reg_rtx (HImode);
|
|
|
|
|
})
|
|
|
|
|
|
genmodes.c (make_vector_mode): Allow making VECTOR_MODE_INT of a MODE_PARTIAL_INT mode.
* genmodes.c (make_vector_mode): Allow making VECTOR_MODE_INT of a
MODE_PARTIAL_INT mode.
* config/bfin/bfin-modes.def: Add V2PDI and V2SI.
* config/bfin/bfin.c (print_operand): Add macflag and mac/msu modifiers
for CONST_INTs.
(hard_regno_mode_ok): V2PDImode is ok for accumulators.
* config/bfin/bfin.h (CLASS_MAX_NREGS, HARD_REGNO_NREGS): Handle
V2PDImode.
* config/bfin/predicates.md (const01_operand, vec_shift_operand):
New predicates.
* config/bfin/bfin.md (UNSPEC_MUL_WITH_FLAG, UNSPEC_MAC_WITH_FLAG):
New constants.
(MACFLAG_NONE, MACFLAG_T, MACFLAG_FU, MACFLAG_TFU, MACFLAG_IS,
MACFLAG_IU, MACFLAG_W32, MACFLAG_M, MACFLAG_S2RND, MACFLAG_ISS2,
MACFLAG_IH): Likewise.
(movstricthi_1): Renamed from "*movstricthi".
(load_accumulator, load_accumulator_pair, movsi_insv, insv,
ssaddsi3, sssubsi3, ssnegsi2, signbitssi2, smaxhi3, sminhi3,
abshi2, neghi2, ssneghi2, signbitshi2, movhi_low2high,
movhi_high2high, movhi_low2low, movhi_high2low, movhiv2hi_low,
movhiv2hi_high, composev2hi, movv2hi_hi, movv2hi_hi_low,
movv2hi_hi_high, ssaddhi3, sssubhi3, ssaddv2hi3, sssubv2hi3,
addsubv2hi3, subaddv2hi3, ssaddsubv2hi3, sssubaddv2hi3,
sublohiv2hi3, subhilov2hi3, sssublohiv2hi3, sssubhilov2hi3,
addlohiv2hi3, addhilov2hi3, ssaddlohiv2hi3, ssaddhilov2hi3,
mulhisi_ll, mulhisi_lh, mulhisi_hl, mulhisi_hh, ssnegv2hi2,
ssashiftv2hi3, ssashifthi3, lshiftv2hi3, lshifthi3, packv2hi,
flag_mulhi, flag_mulhisi_parts, flag_machi, flag_machi_acconly,
flag_macinithi, flag_macinit1hi, flag_mulv2hi, flag_mulv2hi_parts,
flag_macv2hi_parts, flag_macv2hi_parts_acconly,
flag_macinitv2hi_parts, flag_macinit1v2hi_parts): New patterns.
From-SVN: r113245
2006-04-25 13:49:27 +02:00
|
|
|
|
(define_insn "signbitssi2"
|
|
|
|
|
[(set (match_operand:HI 0 "register_operand" "=d")
|
re PR middle-end/50161 (wrong code with -fno-tree-ter and __builtin_popcountl)
PR middle-end/50161
* simplify-rtx.c (simplify_const_unary_operation): If
op is CONST_INT, don't look at op_mode, but use instead
mode.
* optabs.c (add_equal_note): For FFS, CLZ, CTZ,
CLRSB, POPCOUNT, PARITY and BSWAP use operand mode for
operation and TRUNCATE/ZERO_EXTEND if needed.
* doc/rtl.texi (ffs, clrsb, clz, ctz, popcount, parity, bswap):
Document that operand mode must be same as operation mode,
or VOIDmode.
* config/avr/avr.md (paritysi2, *parityqihi2.libgcc,
*paritysihi2.libgcc, popcountsi2, *popcountsi2.libgcc,
*popcountqihi2.libgcc, clzsi2, *clzsihi2.libgcc, ctzsi2,
*ctzsihi2.libgcc, ffssi2, *ffssihi2.libgcc): For unary ops
use the mode of operand for the operation and add truncate
or zero_extend around if needed.
* config/c6x/c6x.md (ctzdi2): Likewise.
* config/bfin/bfin.md (clrsbsi2, signbitssi2): Likewise.
* gcc.dg/pr50161.c: New test.
From-SVN: r177991
2011-08-23 17:51:45 +02:00
|
|
|
|
(truncate:HI (clrsb:SI (match_operand:SI 1 "register_operand" "d"))))]
|
genmodes.c (make_vector_mode): Allow making VECTOR_MODE_INT of a MODE_PARTIAL_INT mode.
* genmodes.c (make_vector_mode): Allow making VECTOR_MODE_INT of a
MODE_PARTIAL_INT mode.
* config/bfin/bfin-modes.def: Add V2PDI and V2SI.
* config/bfin/bfin.c (print_operand): Add macflag and mac/msu modifiers
for CONST_INTs.
(hard_regno_mode_ok): V2PDImode is ok for accumulators.
* config/bfin/bfin.h (CLASS_MAX_NREGS, HARD_REGNO_NREGS): Handle
V2PDImode.
* config/bfin/predicates.md (const01_operand, vec_shift_operand):
New predicates.
* config/bfin/bfin.md (UNSPEC_MUL_WITH_FLAG, UNSPEC_MAC_WITH_FLAG):
New constants.
(MACFLAG_NONE, MACFLAG_T, MACFLAG_FU, MACFLAG_TFU, MACFLAG_IS,
MACFLAG_IU, MACFLAG_W32, MACFLAG_M, MACFLAG_S2RND, MACFLAG_ISS2,
MACFLAG_IH): Likewise.
(movstricthi_1): Renamed from "*movstricthi".
(load_accumulator, load_accumulator_pair, movsi_insv, insv,
ssaddsi3, sssubsi3, ssnegsi2, signbitssi2, smaxhi3, sminhi3,
abshi2, neghi2, ssneghi2, signbitshi2, movhi_low2high,
movhi_high2high, movhi_low2low, movhi_high2low, movhiv2hi_low,
movhiv2hi_high, composev2hi, movv2hi_hi, movv2hi_hi_low,
movv2hi_hi_high, ssaddhi3, sssubhi3, ssaddv2hi3, sssubv2hi3,
addsubv2hi3, subaddv2hi3, ssaddsubv2hi3, sssubaddv2hi3,
sublohiv2hi3, subhilov2hi3, sssublohiv2hi3, sssubhilov2hi3,
addlohiv2hi3, addhilov2hi3, ssaddlohiv2hi3, ssaddhilov2hi3,
mulhisi_ll, mulhisi_lh, mulhisi_hl, mulhisi_hh, ssnegv2hi2,
ssashiftv2hi3, ssashifthi3, lshiftv2hi3, lshifthi3, packv2hi,
flag_mulhi, flag_mulhisi_parts, flag_machi, flag_machi_acconly,
flag_macinithi, flag_macinit1hi, flag_mulv2hi, flag_mulv2hi_parts,
flag_macv2hi_parts, flag_macv2hi_parts_acconly,
flag_macinitv2hi_parts, flag_macinit1v2hi_parts): New patterns.
From-SVN: r113245
2006-04-25 13:49:27 +02:00
|
|
|
|
""
|
rtlanal.c (note_uses): Deal with SEQUENCEs.
* rtlanal.c (note_uses): Deal with SEQUENCEs.
* config/bfin/bfin.c: Include "timevar.h".
(bfin_flag_schedule_insns2, splitting_for_sched,
bfin_flag_var_tracking): New variables.
(print_operand): Handle '%!'.
(override_options): Disable normal sched2 pass, instead set
bfin_flag_schedule_insns2 for reorg to handle it.
(output_file_start): Likewise for var-tracking.
(bfin_optimize_loop): Take some care not to stumble over SEQUENCEs.
(gen_one_bundle, bfin_gen_bundles, type_for_anomaly, trapping_loads_p):
New functions.
(bfin_reorg): Do second scheduling pass here, and call
bfin_gen_bundles. Use type_for_anomaly and trapping_loads_p instead
of examining insns directly. If bfin_flag_var_tracking, call
var-tracking pass when done with everything else.
* config/bfin/bfin.h (PRINT_OPERAND_PUNCT_VALID_P): '!' is valid.
* config/bfin/bfin.md (UNSPEC_32BIT): New constant.
(movsi_insn32): New pattern, with two new splits to create it
before the final scheduling pass.
(neghi2): Not a dsp32 insn, rather alu0.
(movbi, pushsi_insn, popsi_insn, movsi_insn, movv2hi_insn, movhi_insn,
movqi_insn, movsf_insn, movsi_insv, extendhisi2, zero_extendhisi2,
extendqihi2, extendqisi2, zero_extendqihi2, zero_extendqisi2,
mulhisi3, umulhisi3, ssadsi3, sssubsi3, smaxsi3, sminsi3, abssi2,
ssnegsi2, signbitssi2, smaxhi3, sminhi3, abshi2, ssneghi2, signbitshi2,
movhi_low2high, movhi_high2high, movhi_low2low, movhi_high2low,
movhiv2hi_low, movhiv2hi_high, composev2hi, packv2hi, movv2hi_hi,
ssaddhi3, sssubhi3, addv2hi3, ssaddv2hi3, subv2hi3, sssubv2hi3,
addsubv2hi3, subaddv2hi3, ssaddsubv2hi3, sssubaddv2hi3, sublohiv2hi3,
subhilov2hi3, sssublohiv2hi3, sssubhilov2hi3, addlohiv2hi3,
addhilov2hi3, ssaddlohiv2hi3, ssaddhilov2hi3, sminv2hi3, smaxv2hi3,
flag_mulhi, flag_mulhisi, flag_mulhisi_parts, flag_machi,
flag_machi_acconly, flag_macinithi, flag_macinit1hi, mulv2hi3,
flag_mulv2hi, flag_mulv2hi_parts, flag_macv2hi_parts,
flag_macv2hi_parts_acconly, flag_macinitv2hi_parts,
flag_macinit1v2hi_parts, mulhisi_ll, mulhisi_lh, mulhisi_hl,
mulhisi_hh, ssnegv2hi2, absv2hi2, ssashiftv2hi3, ssashifthi3,
lshiftv2hi3, lshifthi3): Use '%!' to terminate all dsp32/load/store
variants instead of ';'.
(ror_one, rol_one): Likewise. Make them dsp32 insns.
(ashlsi3_insn, ashrsi3, lshrsi3): Add dsp32 variants.
(align8, align16, align24): Now named patterns; also using '%!'.
(mnop): New insn.
From-SVN: r119534
2006-12-05 09:49:56 +01:00
|
|
|
|
"%h0 = signbits %1%!"
|
genmodes.c (make_vector_mode): Allow making VECTOR_MODE_INT of a MODE_PARTIAL_INT mode.
* genmodes.c (make_vector_mode): Allow making VECTOR_MODE_INT of a
MODE_PARTIAL_INT mode.
* config/bfin/bfin-modes.def: Add V2PDI and V2SI.
* config/bfin/bfin.c (print_operand): Add macflag and mac/msu modifiers
for CONST_INTs.
(hard_regno_mode_ok): V2PDImode is ok for accumulators.
* config/bfin/bfin.h (CLASS_MAX_NREGS, HARD_REGNO_NREGS): Handle
V2PDImode.
* config/bfin/predicates.md (const01_operand, vec_shift_operand):
New predicates.
* config/bfin/bfin.md (UNSPEC_MUL_WITH_FLAG, UNSPEC_MAC_WITH_FLAG):
New constants.
(MACFLAG_NONE, MACFLAG_T, MACFLAG_FU, MACFLAG_TFU, MACFLAG_IS,
MACFLAG_IU, MACFLAG_W32, MACFLAG_M, MACFLAG_S2RND, MACFLAG_ISS2,
MACFLAG_IH): Likewise.
(movstricthi_1): Renamed from "*movstricthi".
(load_accumulator, load_accumulator_pair, movsi_insv, insv,
ssaddsi3, sssubsi3, ssnegsi2, signbitssi2, smaxhi3, sminhi3,
abshi2, neghi2, ssneghi2, signbitshi2, movhi_low2high,
movhi_high2high, movhi_low2low, movhi_high2low, movhiv2hi_low,
movhiv2hi_high, composev2hi, movv2hi_hi, movv2hi_hi_low,
movv2hi_hi_high, ssaddhi3, sssubhi3, ssaddv2hi3, sssubv2hi3,
addsubv2hi3, subaddv2hi3, ssaddsubv2hi3, sssubaddv2hi3,
sublohiv2hi3, subhilov2hi3, sssublohiv2hi3, sssubhilov2hi3,
addlohiv2hi3, addhilov2hi3, ssaddlohiv2hi3, ssaddhilov2hi3,
mulhisi_ll, mulhisi_lh, mulhisi_hl, mulhisi_hh, ssnegv2hi2,
ssashiftv2hi3, ssashifthi3, lshiftv2hi3, lshifthi3, packv2hi,
flag_mulhi, flag_mulhisi_parts, flag_machi, flag_machi_acconly,
flag_macinithi, flag_macinit1hi, flag_mulv2hi, flag_mulv2hi_parts,
flag_macv2hi_parts, flag_macv2hi_parts_acconly,
flag_macinitv2hi_parts, flag_macinit1v2hi_parts): New patterns.
From-SVN: r113245
2006-04-25 13:49:27 +02:00
|
|
|
|
[(set_attr "type" "dsp32")])
|
|
|
|
|
|
rtl.def (SS_ABS): New code.
* rtl.def (SS_ABS): New code.
* config/bfin/bfin.c (print_operand): New modifier 'v'.
(enum bfin_builtins): Add BFIN_BUILTIN_SUM_2X16, BFIN_BUILTIN_ABS_1x32,
BFIN_BUILTIN_ROUND_1x32, BFIN_BUILTIN_MULT_1x32x32,
BFIN_BUILTIN_MULT_1x32x32NS, BFIN_BUILTIN_SSASHIFT_1x32.
(bfin_init_builtins): Define them.
(bdesc_1arg, bdesc_2arg): Add some of them here, ...
(bfin_expand_builtin): ... and handle the others here.
* config/bfin/bfin.md (ssabssi2, ssroundsi2, ssashiftsi3,
flag_mul_macv2hi_parts_acconly_andcc0): New patterns.
(ss_absv2hi2): Renamed from absv2hi; use ss_abs code.
(ssashiftv2hi3, ssashifthi3, lshiftv2hi3, lshifthi3): Shift count
operand is only HImode.
From-SVN: r124280
2007-04-29 15:22:04 +02:00
|
|
|
|
(define_insn "ssroundsi2"
|
|
|
|
|
[(set (match_operand:HI 0 "register_operand" "=d")
|
|
|
|
|
(truncate:HI
|
|
|
|
|
(lshiftrt:SI (ss_plus:SI (match_operand:SI 1 "register_operand" "d")
|
|
|
|
|
(const_int 32768))
|
|
|
|
|
(const_int 16))))]
|
|
|
|
|
""
|
|
|
|
|
"%h0 = %1 (RND)%!"
|
|
|
|
|
[(set_attr "type" "dsp32")])
|
|
|
|
|
|
genmodes.c (make_vector_mode): Allow making VECTOR_MODE_INT of a MODE_PARTIAL_INT mode.
* genmodes.c (make_vector_mode): Allow making VECTOR_MODE_INT of a
MODE_PARTIAL_INT mode.
* config/bfin/bfin-modes.def: Add V2PDI and V2SI.
* config/bfin/bfin.c (print_operand): Add macflag and mac/msu modifiers
for CONST_INTs.
(hard_regno_mode_ok): V2PDImode is ok for accumulators.
* config/bfin/bfin.h (CLASS_MAX_NREGS, HARD_REGNO_NREGS): Handle
V2PDImode.
* config/bfin/predicates.md (const01_operand, vec_shift_operand):
New predicates.
* config/bfin/bfin.md (UNSPEC_MUL_WITH_FLAG, UNSPEC_MAC_WITH_FLAG):
New constants.
(MACFLAG_NONE, MACFLAG_T, MACFLAG_FU, MACFLAG_TFU, MACFLAG_IS,
MACFLAG_IU, MACFLAG_W32, MACFLAG_M, MACFLAG_S2RND, MACFLAG_ISS2,
MACFLAG_IH): Likewise.
(movstricthi_1): Renamed from "*movstricthi".
(load_accumulator, load_accumulator_pair, movsi_insv, insv,
ssaddsi3, sssubsi3, ssnegsi2, signbitssi2, smaxhi3, sminhi3,
abshi2, neghi2, ssneghi2, signbitshi2, movhi_low2high,
movhi_high2high, movhi_low2low, movhi_high2low, movhiv2hi_low,
movhiv2hi_high, composev2hi, movv2hi_hi, movv2hi_hi_low,
movv2hi_hi_high, ssaddhi3, sssubhi3, ssaddv2hi3, sssubv2hi3,
addsubv2hi3, subaddv2hi3, ssaddsubv2hi3, sssubaddv2hi3,
sublohiv2hi3, subhilov2hi3, sssublohiv2hi3, sssubhilov2hi3,
addlohiv2hi3, addhilov2hi3, ssaddlohiv2hi3, ssaddhilov2hi3,
mulhisi_ll, mulhisi_lh, mulhisi_hl, mulhisi_hh, ssnegv2hi2,
ssashiftv2hi3, ssashifthi3, lshiftv2hi3, lshifthi3, packv2hi,
flag_mulhi, flag_mulhisi_parts, flag_machi, flag_machi_acconly,
flag_macinithi, flag_macinit1hi, flag_mulv2hi, flag_mulv2hi_parts,
flag_macv2hi_parts, flag_macv2hi_parts_acconly,
flag_macinitv2hi_parts, flag_macinit1v2hi_parts): New patterns.
From-SVN: r113245
2006-04-25 13:49:27 +02:00
|
|
|
|
(define_insn "smaxhi3"
|
|
|
|
|
[(set (match_operand:HI 0 "register_operand" "=d")
|
|
|
|
|
(smax:HI (match_operand:HI 1 "register_operand" "d")
|
|
|
|
|
(match_operand:HI 2 "register_operand" "d")))]
|
|
|
|
|
""
|
rtlanal.c (note_uses): Deal with SEQUENCEs.
* rtlanal.c (note_uses): Deal with SEQUENCEs.
* config/bfin/bfin.c: Include "timevar.h".
(bfin_flag_schedule_insns2, splitting_for_sched,
bfin_flag_var_tracking): New variables.
(print_operand): Handle '%!'.
(override_options): Disable normal sched2 pass, instead set
bfin_flag_schedule_insns2 for reorg to handle it.
(output_file_start): Likewise for var-tracking.
(bfin_optimize_loop): Take some care not to stumble over SEQUENCEs.
(gen_one_bundle, bfin_gen_bundles, type_for_anomaly, trapping_loads_p):
New functions.
(bfin_reorg): Do second scheduling pass here, and call
bfin_gen_bundles. Use type_for_anomaly and trapping_loads_p instead
of examining insns directly. If bfin_flag_var_tracking, call
var-tracking pass when done with everything else.
* config/bfin/bfin.h (PRINT_OPERAND_PUNCT_VALID_P): '!' is valid.
* config/bfin/bfin.md (UNSPEC_32BIT): New constant.
(movsi_insn32): New pattern, with two new splits to create it
before the final scheduling pass.
(neghi2): Not a dsp32 insn, rather alu0.
(movbi, pushsi_insn, popsi_insn, movsi_insn, movv2hi_insn, movhi_insn,
movqi_insn, movsf_insn, movsi_insv, extendhisi2, zero_extendhisi2,
extendqihi2, extendqisi2, zero_extendqihi2, zero_extendqisi2,
mulhisi3, umulhisi3, ssadsi3, sssubsi3, smaxsi3, sminsi3, abssi2,
ssnegsi2, signbitssi2, smaxhi3, sminhi3, abshi2, ssneghi2, signbitshi2,
movhi_low2high, movhi_high2high, movhi_low2low, movhi_high2low,
movhiv2hi_low, movhiv2hi_high, composev2hi, packv2hi, movv2hi_hi,
ssaddhi3, sssubhi3, addv2hi3, ssaddv2hi3, subv2hi3, sssubv2hi3,
addsubv2hi3, subaddv2hi3, ssaddsubv2hi3, sssubaddv2hi3, sublohiv2hi3,
subhilov2hi3, sssublohiv2hi3, sssubhilov2hi3, addlohiv2hi3,
addhilov2hi3, ssaddlohiv2hi3, ssaddhilov2hi3, sminv2hi3, smaxv2hi3,
flag_mulhi, flag_mulhisi, flag_mulhisi_parts, flag_machi,
flag_machi_acconly, flag_macinithi, flag_macinit1hi, mulv2hi3,
flag_mulv2hi, flag_mulv2hi_parts, flag_macv2hi_parts,
flag_macv2hi_parts_acconly, flag_macinitv2hi_parts,
flag_macinit1v2hi_parts, mulhisi_ll, mulhisi_lh, mulhisi_hl,
mulhisi_hh, ssnegv2hi2, absv2hi2, ssashiftv2hi3, ssashifthi3,
lshiftv2hi3, lshifthi3): Use '%!' to terminate all dsp32/load/store
variants instead of ';'.
(ror_one, rol_one): Likewise. Make them dsp32 insns.
(ashlsi3_insn, ashrsi3, lshrsi3): Add dsp32 variants.
(align8, align16, align24): Now named patterns; also using '%!'.
(mnop): New insn.
From-SVN: r119534
2006-12-05 09:49:56 +01:00
|
|
|
|
"%0 = max(%1,%2) (V)%!"
|
genmodes.c (make_vector_mode): Allow making VECTOR_MODE_INT of a MODE_PARTIAL_INT mode.
* genmodes.c (make_vector_mode): Allow making VECTOR_MODE_INT of a
MODE_PARTIAL_INT mode.
* config/bfin/bfin-modes.def: Add V2PDI and V2SI.
* config/bfin/bfin.c (print_operand): Add macflag and mac/msu modifiers
for CONST_INTs.
(hard_regno_mode_ok): V2PDImode is ok for accumulators.
* config/bfin/bfin.h (CLASS_MAX_NREGS, HARD_REGNO_NREGS): Handle
V2PDImode.
* config/bfin/predicates.md (const01_operand, vec_shift_operand):
New predicates.
* config/bfin/bfin.md (UNSPEC_MUL_WITH_FLAG, UNSPEC_MAC_WITH_FLAG):
New constants.
(MACFLAG_NONE, MACFLAG_T, MACFLAG_FU, MACFLAG_TFU, MACFLAG_IS,
MACFLAG_IU, MACFLAG_W32, MACFLAG_M, MACFLAG_S2RND, MACFLAG_ISS2,
MACFLAG_IH): Likewise.
(movstricthi_1): Renamed from "*movstricthi".
(load_accumulator, load_accumulator_pair, movsi_insv, insv,
ssaddsi3, sssubsi3, ssnegsi2, signbitssi2, smaxhi3, sminhi3,
abshi2, neghi2, ssneghi2, signbitshi2, movhi_low2high,
movhi_high2high, movhi_low2low, movhi_high2low, movhiv2hi_low,
movhiv2hi_high, composev2hi, movv2hi_hi, movv2hi_hi_low,
movv2hi_hi_high, ssaddhi3, sssubhi3, ssaddv2hi3, sssubv2hi3,
addsubv2hi3, subaddv2hi3, ssaddsubv2hi3, sssubaddv2hi3,
sublohiv2hi3, subhilov2hi3, sssublohiv2hi3, sssubhilov2hi3,
addlohiv2hi3, addhilov2hi3, ssaddlohiv2hi3, ssaddhilov2hi3,
mulhisi_ll, mulhisi_lh, mulhisi_hl, mulhisi_hh, ssnegv2hi2,
ssashiftv2hi3, ssashifthi3, lshiftv2hi3, lshifthi3, packv2hi,
flag_mulhi, flag_mulhisi_parts, flag_machi, flag_machi_acconly,
flag_macinithi, flag_macinit1hi, flag_mulv2hi, flag_mulv2hi_parts,
flag_macv2hi_parts, flag_macv2hi_parts_acconly,
flag_macinitv2hi_parts, flag_macinit1v2hi_parts): New patterns.
From-SVN: r113245
2006-04-25 13:49:27 +02:00
|
|
|
|
[(set_attr "type" "dsp32")])
|
|
|
|
|
|
|
|
|
|
(define_insn "sminhi3"
|
|
|
|
|
[(set (match_operand:HI 0 "register_operand" "=d")
|
|
|
|
|
(smin:HI (match_operand:HI 1 "register_operand" "d")
|
|
|
|
|
(match_operand:HI 2 "register_operand" "d")))]
|
|
|
|
|
""
|
rtlanal.c (note_uses): Deal with SEQUENCEs.
* rtlanal.c (note_uses): Deal with SEQUENCEs.
* config/bfin/bfin.c: Include "timevar.h".
(bfin_flag_schedule_insns2, splitting_for_sched,
bfin_flag_var_tracking): New variables.
(print_operand): Handle '%!'.
(override_options): Disable normal sched2 pass, instead set
bfin_flag_schedule_insns2 for reorg to handle it.
(output_file_start): Likewise for var-tracking.
(bfin_optimize_loop): Take some care not to stumble over SEQUENCEs.
(gen_one_bundle, bfin_gen_bundles, type_for_anomaly, trapping_loads_p):
New functions.
(bfin_reorg): Do second scheduling pass here, and call
bfin_gen_bundles. Use type_for_anomaly and trapping_loads_p instead
of examining insns directly. If bfin_flag_var_tracking, call
var-tracking pass when done with everything else.
* config/bfin/bfin.h (PRINT_OPERAND_PUNCT_VALID_P): '!' is valid.
* config/bfin/bfin.md (UNSPEC_32BIT): New constant.
(movsi_insn32): New pattern, with two new splits to create it
before the final scheduling pass.
(neghi2): Not a dsp32 insn, rather alu0.
(movbi, pushsi_insn, popsi_insn, movsi_insn, movv2hi_insn, movhi_insn,
movqi_insn, movsf_insn, movsi_insv, extendhisi2, zero_extendhisi2,
extendqihi2, extendqisi2, zero_extendqihi2, zero_extendqisi2,
mulhisi3, umulhisi3, ssadsi3, sssubsi3, smaxsi3, sminsi3, abssi2,
ssnegsi2, signbitssi2, smaxhi3, sminhi3, abshi2, ssneghi2, signbitshi2,
movhi_low2high, movhi_high2high, movhi_low2low, movhi_high2low,
movhiv2hi_low, movhiv2hi_high, composev2hi, packv2hi, movv2hi_hi,
ssaddhi3, sssubhi3, addv2hi3, ssaddv2hi3, subv2hi3, sssubv2hi3,
addsubv2hi3, subaddv2hi3, ssaddsubv2hi3, sssubaddv2hi3, sublohiv2hi3,
subhilov2hi3, sssublohiv2hi3, sssubhilov2hi3, addlohiv2hi3,
addhilov2hi3, ssaddlohiv2hi3, ssaddhilov2hi3, sminv2hi3, smaxv2hi3,
flag_mulhi, flag_mulhisi, flag_mulhisi_parts, flag_machi,
flag_machi_acconly, flag_macinithi, flag_macinit1hi, mulv2hi3,
flag_mulv2hi, flag_mulv2hi_parts, flag_macv2hi_parts,
flag_macv2hi_parts_acconly, flag_macinitv2hi_parts,
flag_macinit1v2hi_parts, mulhisi_ll, mulhisi_lh, mulhisi_hl,
mulhisi_hh, ssnegv2hi2, absv2hi2, ssashiftv2hi3, ssashifthi3,
lshiftv2hi3, lshifthi3): Use '%!' to terminate all dsp32/load/store
variants instead of ';'.
(ror_one, rol_one): Likewise. Make them dsp32 insns.
(ashlsi3_insn, ashrsi3, lshrsi3): Add dsp32 variants.
(align8, align16, align24): Now named patterns; also using '%!'.
(mnop): New insn.
From-SVN: r119534
2006-12-05 09:49:56 +01:00
|
|
|
|
"%0 = min(%1,%2) (V)%!"
|
genmodes.c (make_vector_mode): Allow making VECTOR_MODE_INT of a MODE_PARTIAL_INT mode.
* genmodes.c (make_vector_mode): Allow making VECTOR_MODE_INT of a
MODE_PARTIAL_INT mode.
* config/bfin/bfin-modes.def: Add V2PDI and V2SI.
* config/bfin/bfin.c (print_operand): Add macflag and mac/msu modifiers
for CONST_INTs.
(hard_regno_mode_ok): V2PDImode is ok for accumulators.
* config/bfin/bfin.h (CLASS_MAX_NREGS, HARD_REGNO_NREGS): Handle
V2PDImode.
* config/bfin/predicates.md (const01_operand, vec_shift_operand):
New predicates.
* config/bfin/bfin.md (UNSPEC_MUL_WITH_FLAG, UNSPEC_MAC_WITH_FLAG):
New constants.
(MACFLAG_NONE, MACFLAG_T, MACFLAG_FU, MACFLAG_TFU, MACFLAG_IS,
MACFLAG_IU, MACFLAG_W32, MACFLAG_M, MACFLAG_S2RND, MACFLAG_ISS2,
MACFLAG_IH): Likewise.
(movstricthi_1): Renamed from "*movstricthi".
(load_accumulator, load_accumulator_pair, movsi_insv, insv,
ssaddsi3, sssubsi3, ssnegsi2, signbitssi2, smaxhi3, sminhi3,
abshi2, neghi2, ssneghi2, signbitshi2, movhi_low2high,
movhi_high2high, movhi_low2low, movhi_high2low, movhiv2hi_low,
movhiv2hi_high, composev2hi, movv2hi_hi, movv2hi_hi_low,
movv2hi_hi_high, ssaddhi3, sssubhi3, ssaddv2hi3, sssubv2hi3,
addsubv2hi3, subaddv2hi3, ssaddsubv2hi3, sssubaddv2hi3,
sublohiv2hi3, subhilov2hi3, sssublohiv2hi3, sssubhilov2hi3,
addlohiv2hi3, addhilov2hi3, ssaddlohiv2hi3, ssaddhilov2hi3,
mulhisi_ll, mulhisi_lh, mulhisi_hl, mulhisi_hh, ssnegv2hi2,
ssashiftv2hi3, ssashifthi3, lshiftv2hi3, lshifthi3, packv2hi,
flag_mulhi, flag_mulhisi_parts, flag_machi, flag_machi_acconly,
flag_macinithi, flag_macinit1hi, flag_mulv2hi, flag_mulv2hi_parts,
flag_macv2hi_parts, flag_macv2hi_parts_acconly,
flag_macinitv2hi_parts, flag_macinit1v2hi_parts): New patterns.
From-SVN: r113245
2006-04-25 13:49:27 +02:00
|
|
|
|
[(set_attr "type" "dsp32")])
|
|
|
|
|
|
|
|
|
|
(define_insn "abshi2"
|
|
|
|
|
[(set (match_operand:HI 0 "register_operand" "=d")
|
|
|
|
|
(abs:HI (match_operand:HI 1 "register_operand" "d")))]
|
|
|
|
|
""
|
rtlanal.c (note_uses): Deal with SEQUENCEs.
* rtlanal.c (note_uses): Deal with SEQUENCEs.
* config/bfin/bfin.c: Include "timevar.h".
(bfin_flag_schedule_insns2, splitting_for_sched,
bfin_flag_var_tracking): New variables.
(print_operand): Handle '%!'.
(override_options): Disable normal sched2 pass, instead set
bfin_flag_schedule_insns2 for reorg to handle it.
(output_file_start): Likewise for var-tracking.
(bfin_optimize_loop): Take some care not to stumble over SEQUENCEs.
(gen_one_bundle, bfin_gen_bundles, type_for_anomaly, trapping_loads_p):
New functions.
(bfin_reorg): Do second scheduling pass here, and call
bfin_gen_bundles. Use type_for_anomaly and trapping_loads_p instead
of examining insns directly. If bfin_flag_var_tracking, call
var-tracking pass when done with everything else.
* config/bfin/bfin.h (PRINT_OPERAND_PUNCT_VALID_P): '!' is valid.
* config/bfin/bfin.md (UNSPEC_32BIT): New constant.
(movsi_insn32): New pattern, with two new splits to create it
before the final scheduling pass.
(neghi2): Not a dsp32 insn, rather alu0.
(movbi, pushsi_insn, popsi_insn, movsi_insn, movv2hi_insn, movhi_insn,
movqi_insn, movsf_insn, movsi_insv, extendhisi2, zero_extendhisi2,
extendqihi2, extendqisi2, zero_extendqihi2, zero_extendqisi2,
mulhisi3, umulhisi3, ssadsi3, sssubsi3, smaxsi3, sminsi3, abssi2,
ssnegsi2, signbitssi2, smaxhi3, sminhi3, abshi2, ssneghi2, signbitshi2,
movhi_low2high, movhi_high2high, movhi_low2low, movhi_high2low,
movhiv2hi_low, movhiv2hi_high, composev2hi, packv2hi, movv2hi_hi,
ssaddhi3, sssubhi3, addv2hi3, ssaddv2hi3, subv2hi3, sssubv2hi3,
addsubv2hi3, subaddv2hi3, ssaddsubv2hi3, sssubaddv2hi3, sublohiv2hi3,
subhilov2hi3, sssublohiv2hi3, sssubhilov2hi3, addlohiv2hi3,
addhilov2hi3, ssaddlohiv2hi3, ssaddhilov2hi3, sminv2hi3, smaxv2hi3,
flag_mulhi, flag_mulhisi, flag_mulhisi_parts, flag_machi,
flag_machi_acconly, flag_macinithi, flag_macinit1hi, mulv2hi3,
flag_mulv2hi, flag_mulv2hi_parts, flag_macv2hi_parts,
flag_macv2hi_parts_acconly, flag_macinitv2hi_parts,
flag_macinit1v2hi_parts, mulhisi_ll, mulhisi_lh, mulhisi_hl,
mulhisi_hh, ssnegv2hi2, absv2hi2, ssashiftv2hi3, ssashifthi3,
lshiftv2hi3, lshifthi3): Use '%!' to terminate all dsp32/load/store
variants instead of ';'.
(ror_one, rol_one): Likewise. Make them dsp32 insns.
(ashlsi3_insn, ashrsi3, lshrsi3): Add dsp32 variants.
(align8, align16, align24): Now named patterns; also using '%!'.
(mnop): New insn.
From-SVN: r119534
2006-12-05 09:49:56 +01:00
|
|
|
|
"%0 = abs %1 (V)%!"
|
genmodes.c (make_vector_mode): Allow making VECTOR_MODE_INT of a MODE_PARTIAL_INT mode.
* genmodes.c (make_vector_mode): Allow making VECTOR_MODE_INT of a
MODE_PARTIAL_INT mode.
* config/bfin/bfin-modes.def: Add V2PDI and V2SI.
* config/bfin/bfin.c (print_operand): Add macflag and mac/msu modifiers
for CONST_INTs.
(hard_regno_mode_ok): V2PDImode is ok for accumulators.
* config/bfin/bfin.h (CLASS_MAX_NREGS, HARD_REGNO_NREGS): Handle
V2PDImode.
* config/bfin/predicates.md (const01_operand, vec_shift_operand):
New predicates.
* config/bfin/bfin.md (UNSPEC_MUL_WITH_FLAG, UNSPEC_MAC_WITH_FLAG):
New constants.
(MACFLAG_NONE, MACFLAG_T, MACFLAG_FU, MACFLAG_TFU, MACFLAG_IS,
MACFLAG_IU, MACFLAG_W32, MACFLAG_M, MACFLAG_S2RND, MACFLAG_ISS2,
MACFLAG_IH): Likewise.
(movstricthi_1): Renamed from "*movstricthi".
(load_accumulator, load_accumulator_pair, movsi_insv, insv,
ssaddsi3, sssubsi3, ssnegsi2, signbitssi2, smaxhi3, sminhi3,
abshi2, neghi2, ssneghi2, signbitshi2, movhi_low2high,
movhi_high2high, movhi_low2low, movhi_high2low, movhiv2hi_low,
movhiv2hi_high, composev2hi, movv2hi_hi, movv2hi_hi_low,
movv2hi_hi_high, ssaddhi3, sssubhi3, ssaddv2hi3, sssubv2hi3,
addsubv2hi3, subaddv2hi3, ssaddsubv2hi3, sssubaddv2hi3,
sublohiv2hi3, subhilov2hi3, sssublohiv2hi3, sssubhilov2hi3,
addlohiv2hi3, addhilov2hi3, ssaddlohiv2hi3, ssaddhilov2hi3,
mulhisi_ll, mulhisi_lh, mulhisi_hl, mulhisi_hh, ssnegv2hi2,
ssashiftv2hi3, ssashifthi3, lshiftv2hi3, lshifthi3, packv2hi,
flag_mulhi, flag_mulhisi_parts, flag_machi, flag_machi_acconly,
flag_macinithi, flag_macinit1hi, flag_mulv2hi, flag_mulv2hi_parts,
flag_macv2hi_parts, flag_macv2hi_parts_acconly,
flag_macinitv2hi_parts, flag_macinit1v2hi_parts): New patterns.
From-SVN: r113245
2006-04-25 13:49:27 +02:00
|
|
|
|
[(set_attr "type" "dsp32")])
|
|
|
|
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|
|
|
|
|
(define_insn "neghi2"
|
|
|
|
|
[(set (match_operand:HI 0 "register_operand" "=d")
|
|
|
|
|
(neg:HI (match_operand:HI 1 "register_operand" "d")))]
|
|
|
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|
""
|
|
|
|
|
"%0 = -%1;"
|
rtlanal.c (note_uses): Deal with SEQUENCEs.
* rtlanal.c (note_uses): Deal with SEQUENCEs.
* config/bfin/bfin.c: Include "timevar.h".
(bfin_flag_schedule_insns2, splitting_for_sched,
bfin_flag_var_tracking): New variables.
(print_operand): Handle '%!'.
(override_options): Disable normal sched2 pass, instead set
bfin_flag_schedule_insns2 for reorg to handle it.
(output_file_start): Likewise for var-tracking.
(bfin_optimize_loop): Take some care not to stumble over SEQUENCEs.
(gen_one_bundle, bfin_gen_bundles, type_for_anomaly, trapping_loads_p):
New functions.
(bfin_reorg): Do second scheduling pass here, and call
bfin_gen_bundles. Use type_for_anomaly and trapping_loads_p instead
of examining insns directly. If bfin_flag_var_tracking, call
var-tracking pass when done with everything else.
* config/bfin/bfin.h (PRINT_OPERAND_PUNCT_VALID_P): '!' is valid.
* config/bfin/bfin.md (UNSPEC_32BIT): New constant.
(movsi_insn32): New pattern, with two new splits to create it
before the final scheduling pass.
(neghi2): Not a dsp32 insn, rather alu0.
(movbi, pushsi_insn, popsi_insn, movsi_insn, movv2hi_insn, movhi_insn,
movqi_insn, movsf_insn, movsi_insv, extendhisi2, zero_extendhisi2,
extendqihi2, extendqisi2, zero_extendqihi2, zero_extendqisi2,
mulhisi3, umulhisi3, ssadsi3, sssubsi3, smaxsi3, sminsi3, abssi2,
ssnegsi2, signbitssi2, smaxhi3, sminhi3, abshi2, ssneghi2, signbitshi2,
movhi_low2high, movhi_high2high, movhi_low2low, movhi_high2low,
movhiv2hi_low, movhiv2hi_high, composev2hi, packv2hi, movv2hi_hi,
ssaddhi3, sssubhi3, addv2hi3, ssaddv2hi3, subv2hi3, sssubv2hi3,
addsubv2hi3, subaddv2hi3, ssaddsubv2hi3, sssubaddv2hi3, sublohiv2hi3,
subhilov2hi3, sssublohiv2hi3, sssubhilov2hi3, addlohiv2hi3,
addhilov2hi3, ssaddlohiv2hi3, ssaddhilov2hi3, sminv2hi3, smaxv2hi3,
flag_mulhi, flag_mulhisi, flag_mulhisi_parts, flag_machi,
flag_machi_acconly, flag_macinithi, flag_macinit1hi, mulv2hi3,
flag_mulv2hi, flag_mulv2hi_parts, flag_macv2hi_parts,
flag_macv2hi_parts_acconly, flag_macinitv2hi_parts,
flag_macinit1v2hi_parts, mulhisi_ll, mulhisi_lh, mulhisi_hl,
mulhisi_hh, ssnegv2hi2, absv2hi2, ssashiftv2hi3, ssashifthi3,
lshiftv2hi3, lshifthi3): Use '%!' to terminate all dsp32/load/store
variants instead of ';'.
(ror_one, rol_one): Likewise. Make them dsp32 insns.
(ashlsi3_insn, ashrsi3, lshrsi3): Add dsp32 variants.
(align8, align16, align24): Now named patterns; also using '%!'.
(mnop): New insn.
From-SVN: r119534
2006-12-05 09:49:56 +01:00
|
|
|
|
[(set_attr "type" "alu0")])
|
genmodes.c (make_vector_mode): Allow making VECTOR_MODE_INT of a MODE_PARTIAL_INT mode.
* genmodes.c (make_vector_mode): Allow making VECTOR_MODE_INT of a
MODE_PARTIAL_INT mode.
* config/bfin/bfin-modes.def: Add V2PDI and V2SI.
* config/bfin/bfin.c (print_operand): Add macflag and mac/msu modifiers
for CONST_INTs.
(hard_regno_mode_ok): V2PDImode is ok for accumulators.
* config/bfin/bfin.h (CLASS_MAX_NREGS, HARD_REGNO_NREGS): Handle
V2PDImode.
* config/bfin/predicates.md (const01_operand, vec_shift_operand):
New predicates.
* config/bfin/bfin.md (UNSPEC_MUL_WITH_FLAG, UNSPEC_MAC_WITH_FLAG):
New constants.
(MACFLAG_NONE, MACFLAG_T, MACFLAG_FU, MACFLAG_TFU, MACFLAG_IS,
MACFLAG_IU, MACFLAG_W32, MACFLAG_M, MACFLAG_S2RND, MACFLAG_ISS2,
MACFLAG_IH): Likewise.
(movstricthi_1): Renamed from "*movstricthi".
(load_accumulator, load_accumulator_pair, movsi_insv, insv,
ssaddsi3, sssubsi3, ssnegsi2, signbitssi2, smaxhi3, sminhi3,
abshi2, neghi2, ssneghi2, signbitshi2, movhi_low2high,
movhi_high2high, movhi_low2low, movhi_high2low, movhiv2hi_low,
movhiv2hi_high, composev2hi, movv2hi_hi, movv2hi_hi_low,
movv2hi_hi_high, ssaddhi3, sssubhi3, ssaddv2hi3, sssubv2hi3,
addsubv2hi3, subaddv2hi3, ssaddsubv2hi3, sssubaddv2hi3,
sublohiv2hi3, subhilov2hi3, sssublohiv2hi3, sssubhilov2hi3,
addlohiv2hi3, addhilov2hi3, ssaddlohiv2hi3, ssaddhilov2hi3,
mulhisi_ll, mulhisi_lh, mulhisi_hl, mulhisi_hh, ssnegv2hi2,
ssashiftv2hi3, ssashifthi3, lshiftv2hi3, lshifthi3, packv2hi,
flag_mulhi, flag_mulhisi_parts, flag_machi, flag_machi_acconly,
flag_macinithi, flag_macinit1hi, flag_mulv2hi, flag_mulv2hi_parts,
flag_macv2hi_parts, flag_macv2hi_parts_acconly,
flag_macinitv2hi_parts, flag_macinit1v2hi_parts): New patterns.
From-SVN: r113245
2006-04-25 13:49:27 +02:00
|
|
|
|
|
|
|
|
|
(define_insn "ssneghi2"
|
|
|
|
|
[(set (match_operand:HI 0 "register_operand" "=d")
|
|
|
|
|
(ss_neg:HI (match_operand:HI 1 "register_operand" "d")))]
|
|
|
|
|
""
|
rtlanal.c (note_uses): Deal with SEQUENCEs.
* rtlanal.c (note_uses): Deal with SEQUENCEs.
* config/bfin/bfin.c: Include "timevar.h".
(bfin_flag_schedule_insns2, splitting_for_sched,
bfin_flag_var_tracking): New variables.
(print_operand): Handle '%!'.
(override_options): Disable normal sched2 pass, instead set
bfin_flag_schedule_insns2 for reorg to handle it.
(output_file_start): Likewise for var-tracking.
(bfin_optimize_loop): Take some care not to stumble over SEQUENCEs.
(gen_one_bundle, bfin_gen_bundles, type_for_anomaly, trapping_loads_p):
New functions.
(bfin_reorg): Do second scheduling pass here, and call
bfin_gen_bundles. Use type_for_anomaly and trapping_loads_p instead
of examining insns directly. If bfin_flag_var_tracking, call
var-tracking pass when done with everything else.
* config/bfin/bfin.h (PRINT_OPERAND_PUNCT_VALID_P): '!' is valid.
* config/bfin/bfin.md (UNSPEC_32BIT): New constant.
(movsi_insn32): New pattern, with two new splits to create it
before the final scheduling pass.
(neghi2): Not a dsp32 insn, rather alu0.
(movbi, pushsi_insn, popsi_insn, movsi_insn, movv2hi_insn, movhi_insn,
movqi_insn, movsf_insn, movsi_insv, extendhisi2, zero_extendhisi2,
extendqihi2, extendqisi2, zero_extendqihi2, zero_extendqisi2,
mulhisi3, umulhisi3, ssadsi3, sssubsi3, smaxsi3, sminsi3, abssi2,
ssnegsi2, signbitssi2, smaxhi3, sminhi3, abshi2, ssneghi2, signbitshi2,
movhi_low2high, movhi_high2high, movhi_low2low, movhi_high2low,
movhiv2hi_low, movhiv2hi_high, composev2hi, packv2hi, movv2hi_hi,
ssaddhi3, sssubhi3, addv2hi3, ssaddv2hi3, subv2hi3, sssubv2hi3,
addsubv2hi3, subaddv2hi3, ssaddsubv2hi3, sssubaddv2hi3, sublohiv2hi3,
subhilov2hi3, sssublohiv2hi3, sssubhilov2hi3, addlohiv2hi3,
addhilov2hi3, ssaddlohiv2hi3, ssaddhilov2hi3, sminv2hi3, smaxv2hi3,
flag_mulhi, flag_mulhisi, flag_mulhisi_parts, flag_machi,
flag_machi_acconly, flag_macinithi, flag_macinit1hi, mulv2hi3,
flag_mulv2hi, flag_mulv2hi_parts, flag_macv2hi_parts,
flag_macv2hi_parts_acconly, flag_macinitv2hi_parts,
flag_macinit1v2hi_parts, mulhisi_ll, mulhisi_lh, mulhisi_hl,
mulhisi_hh, ssnegv2hi2, absv2hi2, ssashiftv2hi3, ssashifthi3,
lshiftv2hi3, lshifthi3): Use '%!' to terminate all dsp32/load/store
variants instead of ';'.
(ror_one, rol_one): Likewise. Make them dsp32 insns.
(ashlsi3_insn, ashrsi3, lshrsi3): Add dsp32 variants.
(align8, align16, align24): Now named patterns; also using '%!'.
(mnop): New insn.
From-SVN: r119534
2006-12-05 09:49:56 +01:00
|
|
|
|
"%0 = -%1 (V)%!"
|
genmodes.c (make_vector_mode): Allow making VECTOR_MODE_INT of a MODE_PARTIAL_INT mode.
* genmodes.c (make_vector_mode): Allow making VECTOR_MODE_INT of a
MODE_PARTIAL_INT mode.
* config/bfin/bfin-modes.def: Add V2PDI and V2SI.
* config/bfin/bfin.c (print_operand): Add macflag and mac/msu modifiers
for CONST_INTs.
(hard_regno_mode_ok): V2PDImode is ok for accumulators.
* config/bfin/bfin.h (CLASS_MAX_NREGS, HARD_REGNO_NREGS): Handle
V2PDImode.
* config/bfin/predicates.md (const01_operand, vec_shift_operand):
New predicates.
* config/bfin/bfin.md (UNSPEC_MUL_WITH_FLAG, UNSPEC_MAC_WITH_FLAG):
New constants.
(MACFLAG_NONE, MACFLAG_T, MACFLAG_FU, MACFLAG_TFU, MACFLAG_IS,
MACFLAG_IU, MACFLAG_W32, MACFLAG_M, MACFLAG_S2RND, MACFLAG_ISS2,
MACFLAG_IH): Likewise.
(movstricthi_1): Renamed from "*movstricthi".
(load_accumulator, load_accumulator_pair, movsi_insv, insv,
ssaddsi3, sssubsi3, ssnegsi2, signbitssi2, smaxhi3, sminhi3,
abshi2, neghi2, ssneghi2, signbitshi2, movhi_low2high,
movhi_high2high, movhi_low2low, movhi_high2low, movhiv2hi_low,
movhiv2hi_high, composev2hi, movv2hi_hi, movv2hi_hi_low,
movv2hi_hi_high, ssaddhi3, sssubhi3, ssaddv2hi3, sssubv2hi3,
addsubv2hi3, subaddv2hi3, ssaddsubv2hi3, sssubaddv2hi3,
sublohiv2hi3, subhilov2hi3, sssublohiv2hi3, sssubhilov2hi3,
addlohiv2hi3, addhilov2hi3, ssaddlohiv2hi3, ssaddhilov2hi3,
mulhisi_ll, mulhisi_lh, mulhisi_hl, mulhisi_hh, ssnegv2hi2,
ssashiftv2hi3, ssashifthi3, lshiftv2hi3, lshifthi3, packv2hi,
flag_mulhi, flag_mulhisi_parts, flag_machi, flag_machi_acconly,
flag_macinithi, flag_macinit1hi, flag_mulv2hi, flag_mulv2hi_parts,
flag_macv2hi_parts, flag_macv2hi_parts_acconly,
flag_macinitv2hi_parts, flag_macinit1v2hi_parts): New patterns.
From-SVN: r113245
2006-04-25 13:49:27 +02:00
|
|
|
|
[(set_attr "type" "dsp32")])
|
|
|
|
|
|
Makefile.in (lib2funcs): Add _clrsbsi2 and _clrsbdi2.
libgcc/
* Makefile.in (lib2funcs): Add _clrsbsi2 and _clrsbdi2.
* libgcc-std.ver.in (GCC_4.7.0): New section.
gcc/
* doc/extend.texi (__builtin_clrsb, __builtin_clrsbl,
__builtin_clrsbll): Document.
* doc/rtl.texi (clrsb): New entry.
* optabs.c (widen_leading): Renamed from widen_clz. New argument
UNOPTAB. All callers changed. Use UNOPTAB instead of clz_optab.
(expand_unop): Handle clrsb_optab.
(init_optabs): Initialize it.
* optabs.h (enum optab_index): New entry OTI_clrsb.
(clrsb_optab): Define.
* genopinit.c (optabs): Add an entry for it.
* builtins.c (expand_builtin): Handle clrsb builtin functions.
* builtins.def (BUILT_IN_CLRSB, BUILT_IN_CLRSBIMAX, BUILT_IN_CLRSBL,
BUILT_IN_CLRSBLL): New.
* rtl.def (CLRSB): New code.
* dwarf2out.c (mem_loc_descriptor): Handle it.
* simplify-rtx.c (simplify_const_unary_operation): Likewise.
Use op_mode rather than mode when optimizing ffs, clz, ctz, parity
and popcount.
* libgcc2.c (__clrsbSI2, __clrsbDI2): New functions.
* libgcc2.h (__clrsbSI2, __clrsbDI2): Define and declare.
(__ctzDI2): Move declaration.
* config/bfin/bfin.md (clrsbsi2): New expander.
(signbitssi2): Use the CLRSB rtx.
(clrsbhi2): Renamed from signbitshi2. Use the CLRSB rtx.
* config/bfin/bfin.c (bdesc_1arg): Changed accordingly.
gcc/testsuite/
* gcc.c-torture/excute/builtin-bitops-1.c (MAKE_FUNS): Make
my_clrsb test functions.
(main): Test clrsb.
* gcc.dg/builtin-protos-1.c (test_s, test_u, test_sl, test_ul,
test_sll, test_ull): Add clrsb tests.
* gcc.dg/torture/builtin-attr-1.c: Add tests for clrsb, clrsbl,
clrsbll.
From-SVN: r175261
2011-06-21 16:16:39 +02:00
|
|
|
|
(define_insn "clrsbhi2"
|
genmodes.c (make_vector_mode): Allow making VECTOR_MODE_INT of a MODE_PARTIAL_INT mode.
* genmodes.c (make_vector_mode): Allow making VECTOR_MODE_INT of a
MODE_PARTIAL_INT mode.
* config/bfin/bfin-modes.def: Add V2PDI and V2SI.
* config/bfin/bfin.c (print_operand): Add macflag and mac/msu modifiers
for CONST_INTs.
(hard_regno_mode_ok): V2PDImode is ok for accumulators.
* config/bfin/bfin.h (CLASS_MAX_NREGS, HARD_REGNO_NREGS): Handle
V2PDImode.
* config/bfin/predicates.md (const01_operand, vec_shift_operand):
New predicates.
* config/bfin/bfin.md (UNSPEC_MUL_WITH_FLAG, UNSPEC_MAC_WITH_FLAG):
New constants.
(MACFLAG_NONE, MACFLAG_T, MACFLAG_FU, MACFLAG_TFU, MACFLAG_IS,
MACFLAG_IU, MACFLAG_W32, MACFLAG_M, MACFLAG_S2RND, MACFLAG_ISS2,
MACFLAG_IH): Likewise.
(movstricthi_1): Renamed from "*movstricthi".
(load_accumulator, load_accumulator_pair, movsi_insv, insv,
ssaddsi3, sssubsi3, ssnegsi2, signbitssi2, smaxhi3, sminhi3,
abshi2, neghi2, ssneghi2, signbitshi2, movhi_low2high,
movhi_high2high, movhi_low2low, movhi_high2low, movhiv2hi_low,
movhiv2hi_high, composev2hi, movv2hi_hi, movv2hi_hi_low,
movv2hi_hi_high, ssaddhi3, sssubhi3, ssaddv2hi3, sssubv2hi3,
addsubv2hi3, subaddv2hi3, ssaddsubv2hi3, sssubaddv2hi3,
sublohiv2hi3, subhilov2hi3, sssublohiv2hi3, sssubhilov2hi3,
addlohiv2hi3, addhilov2hi3, ssaddlohiv2hi3, ssaddhilov2hi3,
mulhisi_ll, mulhisi_lh, mulhisi_hl, mulhisi_hh, ssnegv2hi2,
ssashiftv2hi3, ssashifthi3, lshiftv2hi3, lshifthi3, packv2hi,
flag_mulhi, flag_mulhisi_parts, flag_machi, flag_machi_acconly,
flag_macinithi, flag_macinit1hi, flag_mulv2hi, flag_mulv2hi_parts,
flag_macv2hi_parts, flag_macv2hi_parts_acconly,
flag_macinitv2hi_parts, flag_macinit1v2hi_parts): New patterns.
From-SVN: r113245
2006-04-25 13:49:27 +02:00
|
|
|
|
[(set (match_operand:HI 0 "register_operand" "=d")
|
Makefile.in (lib2funcs): Add _clrsbsi2 and _clrsbdi2.
libgcc/
* Makefile.in (lib2funcs): Add _clrsbsi2 and _clrsbdi2.
* libgcc-std.ver.in (GCC_4.7.0): New section.
gcc/
* doc/extend.texi (__builtin_clrsb, __builtin_clrsbl,
__builtin_clrsbll): Document.
* doc/rtl.texi (clrsb): New entry.
* optabs.c (widen_leading): Renamed from widen_clz. New argument
UNOPTAB. All callers changed. Use UNOPTAB instead of clz_optab.
(expand_unop): Handle clrsb_optab.
(init_optabs): Initialize it.
* optabs.h (enum optab_index): New entry OTI_clrsb.
(clrsb_optab): Define.
* genopinit.c (optabs): Add an entry for it.
* builtins.c (expand_builtin): Handle clrsb builtin functions.
* builtins.def (BUILT_IN_CLRSB, BUILT_IN_CLRSBIMAX, BUILT_IN_CLRSBL,
BUILT_IN_CLRSBLL): New.
* rtl.def (CLRSB): New code.
* dwarf2out.c (mem_loc_descriptor): Handle it.
* simplify-rtx.c (simplify_const_unary_operation): Likewise.
Use op_mode rather than mode when optimizing ffs, clz, ctz, parity
and popcount.
* libgcc2.c (__clrsbSI2, __clrsbDI2): New functions.
* libgcc2.h (__clrsbSI2, __clrsbDI2): Define and declare.
(__ctzDI2): Move declaration.
* config/bfin/bfin.md (clrsbsi2): New expander.
(signbitssi2): Use the CLRSB rtx.
(clrsbhi2): Renamed from signbitshi2. Use the CLRSB rtx.
* config/bfin/bfin.c (bdesc_1arg): Changed accordingly.
gcc/testsuite/
* gcc.c-torture/excute/builtin-bitops-1.c (MAKE_FUNS): Make
my_clrsb test functions.
(main): Test clrsb.
* gcc.dg/builtin-protos-1.c (test_s, test_u, test_sl, test_ul,
test_sll, test_ull): Add clrsb tests.
* gcc.dg/torture/builtin-attr-1.c: Add tests for clrsb, clrsbl,
clrsbll.
From-SVN: r175261
2011-06-21 16:16:39 +02:00
|
|
|
|
(clrsb:HI (match_operand:HI 1 "register_operand" "d")))]
|
genmodes.c (make_vector_mode): Allow making VECTOR_MODE_INT of a MODE_PARTIAL_INT mode.
* genmodes.c (make_vector_mode): Allow making VECTOR_MODE_INT of a
MODE_PARTIAL_INT mode.
* config/bfin/bfin-modes.def: Add V2PDI and V2SI.
* config/bfin/bfin.c (print_operand): Add macflag and mac/msu modifiers
for CONST_INTs.
(hard_regno_mode_ok): V2PDImode is ok for accumulators.
* config/bfin/bfin.h (CLASS_MAX_NREGS, HARD_REGNO_NREGS): Handle
V2PDImode.
* config/bfin/predicates.md (const01_operand, vec_shift_operand):
New predicates.
* config/bfin/bfin.md (UNSPEC_MUL_WITH_FLAG, UNSPEC_MAC_WITH_FLAG):
New constants.
(MACFLAG_NONE, MACFLAG_T, MACFLAG_FU, MACFLAG_TFU, MACFLAG_IS,
MACFLAG_IU, MACFLAG_W32, MACFLAG_M, MACFLAG_S2RND, MACFLAG_ISS2,
MACFLAG_IH): Likewise.
(movstricthi_1): Renamed from "*movstricthi".
(load_accumulator, load_accumulator_pair, movsi_insv, insv,
ssaddsi3, sssubsi3, ssnegsi2, signbitssi2, smaxhi3, sminhi3,
abshi2, neghi2, ssneghi2, signbitshi2, movhi_low2high,
movhi_high2high, movhi_low2low, movhi_high2low, movhiv2hi_low,
movhiv2hi_high, composev2hi, movv2hi_hi, movv2hi_hi_low,
movv2hi_hi_high, ssaddhi3, sssubhi3, ssaddv2hi3, sssubv2hi3,
addsubv2hi3, subaddv2hi3, ssaddsubv2hi3, sssubaddv2hi3,
sublohiv2hi3, subhilov2hi3, sssublohiv2hi3, sssubhilov2hi3,
addlohiv2hi3, addhilov2hi3, ssaddlohiv2hi3, ssaddhilov2hi3,
mulhisi_ll, mulhisi_lh, mulhisi_hl, mulhisi_hh, ssnegv2hi2,
ssashiftv2hi3, ssashifthi3, lshiftv2hi3, lshifthi3, packv2hi,
flag_mulhi, flag_mulhisi_parts, flag_machi, flag_machi_acconly,
flag_macinithi, flag_macinit1hi, flag_mulv2hi, flag_mulv2hi_parts,
flag_macv2hi_parts, flag_macv2hi_parts_acconly,
flag_macinitv2hi_parts, flag_macinit1v2hi_parts): New patterns.
From-SVN: r113245
2006-04-25 13:49:27 +02:00
|
|
|
|
""
|
rtlanal.c (note_uses): Deal with SEQUENCEs.
* rtlanal.c (note_uses): Deal with SEQUENCEs.
* config/bfin/bfin.c: Include "timevar.h".
(bfin_flag_schedule_insns2, splitting_for_sched,
bfin_flag_var_tracking): New variables.
(print_operand): Handle '%!'.
(override_options): Disable normal sched2 pass, instead set
bfin_flag_schedule_insns2 for reorg to handle it.
(output_file_start): Likewise for var-tracking.
(bfin_optimize_loop): Take some care not to stumble over SEQUENCEs.
(gen_one_bundle, bfin_gen_bundles, type_for_anomaly, trapping_loads_p):
New functions.
(bfin_reorg): Do second scheduling pass here, and call
bfin_gen_bundles. Use type_for_anomaly and trapping_loads_p instead
of examining insns directly. If bfin_flag_var_tracking, call
var-tracking pass when done with everything else.
* config/bfin/bfin.h (PRINT_OPERAND_PUNCT_VALID_P): '!' is valid.
* config/bfin/bfin.md (UNSPEC_32BIT): New constant.
(movsi_insn32): New pattern, with two new splits to create it
before the final scheduling pass.
(neghi2): Not a dsp32 insn, rather alu0.
(movbi, pushsi_insn, popsi_insn, movsi_insn, movv2hi_insn, movhi_insn,
movqi_insn, movsf_insn, movsi_insv, extendhisi2, zero_extendhisi2,
extendqihi2, extendqisi2, zero_extendqihi2, zero_extendqisi2,
mulhisi3, umulhisi3, ssadsi3, sssubsi3, smaxsi3, sminsi3, abssi2,
ssnegsi2, signbitssi2, smaxhi3, sminhi3, abshi2, ssneghi2, signbitshi2,
movhi_low2high, movhi_high2high, movhi_low2low, movhi_high2low,
movhiv2hi_low, movhiv2hi_high, composev2hi, packv2hi, movv2hi_hi,
ssaddhi3, sssubhi3, addv2hi3, ssaddv2hi3, subv2hi3, sssubv2hi3,
addsubv2hi3, subaddv2hi3, ssaddsubv2hi3, sssubaddv2hi3, sublohiv2hi3,
subhilov2hi3, sssublohiv2hi3, sssubhilov2hi3, addlohiv2hi3,
addhilov2hi3, ssaddlohiv2hi3, ssaddhilov2hi3, sminv2hi3, smaxv2hi3,
flag_mulhi, flag_mulhisi, flag_mulhisi_parts, flag_machi,
flag_machi_acconly, flag_macinithi, flag_macinit1hi, mulv2hi3,
flag_mulv2hi, flag_mulv2hi_parts, flag_macv2hi_parts,
flag_macv2hi_parts_acconly, flag_macinitv2hi_parts,
flag_macinit1v2hi_parts, mulhisi_ll, mulhisi_lh, mulhisi_hl,
mulhisi_hh, ssnegv2hi2, absv2hi2, ssashiftv2hi3, ssashifthi3,
lshiftv2hi3, lshifthi3): Use '%!' to terminate all dsp32/load/store
variants instead of ';'.
(ror_one, rol_one): Likewise. Make them dsp32 insns.
(ashlsi3_insn, ashrsi3, lshrsi3): Add dsp32 variants.
(align8, align16, align24): Now named patterns; also using '%!'.
(mnop): New insn.
From-SVN: r119534
2006-12-05 09:49:56 +01:00
|
|
|
|
"%h0 = signbits %h1%!"
|
genmodes.c (make_vector_mode): Allow making VECTOR_MODE_INT of a MODE_PARTIAL_INT mode.
* genmodes.c (make_vector_mode): Allow making VECTOR_MODE_INT of a
MODE_PARTIAL_INT mode.
* config/bfin/bfin-modes.def: Add V2PDI and V2SI.
* config/bfin/bfin.c (print_operand): Add macflag and mac/msu modifiers
for CONST_INTs.
(hard_regno_mode_ok): V2PDImode is ok for accumulators.
* config/bfin/bfin.h (CLASS_MAX_NREGS, HARD_REGNO_NREGS): Handle
V2PDImode.
* config/bfin/predicates.md (const01_operand, vec_shift_operand):
New predicates.
* config/bfin/bfin.md (UNSPEC_MUL_WITH_FLAG, UNSPEC_MAC_WITH_FLAG):
New constants.
(MACFLAG_NONE, MACFLAG_T, MACFLAG_FU, MACFLAG_TFU, MACFLAG_IS,
MACFLAG_IU, MACFLAG_W32, MACFLAG_M, MACFLAG_S2RND, MACFLAG_ISS2,
MACFLAG_IH): Likewise.
(movstricthi_1): Renamed from "*movstricthi".
(load_accumulator, load_accumulator_pair, movsi_insv, insv,
ssaddsi3, sssubsi3, ssnegsi2, signbitssi2, smaxhi3, sminhi3,
abshi2, neghi2, ssneghi2, signbitshi2, movhi_low2high,
movhi_high2high, movhi_low2low, movhi_high2low, movhiv2hi_low,
movhiv2hi_high, composev2hi, movv2hi_hi, movv2hi_hi_low,
movv2hi_hi_high, ssaddhi3, sssubhi3, ssaddv2hi3, sssubv2hi3,
addsubv2hi3, subaddv2hi3, ssaddsubv2hi3, sssubaddv2hi3,
sublohiv2hi3, subhilov2hi3, sssublohiv2hi3, sssubhilov2hi3,
addlohiv2hi3, addhilov2hi3, ssaddlohiv2hi3, ssaddhilov2hi3,
mulhisi_ll, mulhisi_lh, mulhisi_hl, mulhisi_hh, ssnegv2hi2,
ssashiftv2hi3, ssashifthi3, lshiftv2hi3, lshifthi3, packv2hi,
flag_mulhi, flag_mulhisi_parts, flag_machi, flag_machi_acconly,
flag_macinithi, flag_macinit1hi, flag_mulv2hi, flag_mulv2hi_parts,
flag_macv2hi_parts, flag_macv2hi_parts_acconly,
flag_macinitv2hi_parts, flag_macinit1v2hi_parts): New patterns.
From-SVN: r113245
2006-04-25 13:49:27 +02:00
|
|
|
|
[(set_attr "type" "dsp32")])
|
|
|
|
|
|
2005-04-05 13:26:48 +02:00
|
|
|
|
(define_insn "mulsi3"
|
|
|
|
|
[(set (match_operand:SI 0 "register_operand" "=d")
|
|
|
|
|
(mult:SI (match_operand:SI 1 "register_operand" "%0")
|
|
|
|
|
(match_operand:SI 2 "register_operand" "d")))]
|
|
|
|
|
""
|
genmodes.c (make_vector_mode): Allow making VECTOR_MODE_INT of a MODE_PARTIAL_INT mode.
* genmodes.c (make_vector_mode): Allow making VECTOR_MODE_INT of a
MODE_PARTIAL_INT mode.
* config/bfin/bfin-modes.def: Add V2PDI and V2SI.
* config/bfin/bfin.c (print_operand): Add macflag and mac/msu modifiers
for CONST_INTs.
(hard_regno_mode_ok): V2PDImode is ok for accumulators.
* config/bfin/bfin.h (CLASS_MAX_NREGS, HARD_REGNO_NREGS): Handle
V2PDImode.
* config/bfin/predicates.md (const01_operand, vec_shift_operand):
New predicates.
* config/bfin/bfin.md (UNSPEC_MUL_WITH_FLAG, UNSPEC_MAC_WITH_FLAG):
New constants.
(MACFLAG_NONE, MACFLAG_T, MACFLAG_FU, MACFLAG_TFU, MACFLAG_IS,
MACFLAG_IU, MACFLAG_W32, MACFLAG_M, MACFLAG_S2RND, MACFLAG_ISS2,
MACFLAG_IH): Likewise.
(movstricthi_1): Renamed from "*movstricthi".
(load_accumulator, load_accumulator_pair, movsi_insv, insv,
ssaddsi3, sssubsi3, ssnegsi2, signbitssi2, smaxhi3, sminhi3,
abshi2, neghi2, ssneghi2, signbitshi2, movhi_low2high,
movhi_high2high, movhi_low2low, movhi_high2low, movhiv2hi_low,
movhiv2hi_high, composev2hi, movv2hi_hi, movv2hi_hi_low,
movv2hi_hi_high, ssaddhi3, sssubhi3, ssaddv2hi3, sssubv2hi3,
addsubv2hi3, subaddv2hi3, ssaddsubv2hi3, sssubaddv2hi3,
sublohiv2hi3, subhilov2hi3, sssublohiv2hi3, sssubhilov2hi3,
addlohiv2hi3, addhilov2hi3, ssaddlohiv2hi3, ssaddhilov2hi3,
mulhisi_ll, mulhisi_lh, mulhisi_hl, mulhisi_hh, ssnegv2hi2,
ssashiftv2hi3, ssashifthi3, lshiftv2hi3, lshifthi3, packv2hi,
flag_mulhi, flag_mulhisi_parts, flag_machi, flag_machi_acconly,
flag_macinithi, flag_macinit1hi, flag_mulv2hi, flag_mulv2hi_parts,
flag_macv2hi_parts, flag_macv2hi_parts_acconly,
flag_macinitv2hi_parts, flag_macinit1v2hi_parts): New patterns.
From-SVN: r113245
2006-04-25 13:49:27 +02:00
|
|
|
|
"%0 *= %2;"
|
2005-04-05 13:26:48 +02:00
|
|
|
|
[(set_attr "type" "mult")])
|
|
|
|
|
|
2007-02-27 17:29:10 +01:00
|
|
|
|
(define_expand "umulsi3_highpart"
|
2007-04-12 15:39:35 +02:00
|
|
|
|
[(parallel
|
|
|
|
|
[(set (match_operand:SI 0 "register_operand" "")
|
|
|
|
|
(truncate:SI
|
|
|
|
|
(lshiftrt:DI
|
|
|
|
|
(mult:DI (zero_extend:DI
|
|
|
|
|
(match_operand:SI 1 "nonimmediate_operand" ""))
|
|
|
|
|
(zero_extend:DI
|
|
|
|
|
(match_operand:SI 2 "register_operand" "")))
|
|
|
|
|
(const_int 32))))
|
|
|
|
|
(clobber (reg:PDI REG_A0))
|
|
|
|
|
(clobber (reg:PDI REG_A1))])]
|
2007-02-27 17:29:10 +01:00
|
|
|
|
""
|
|
|
|
|
{
|
2007-04-12 15:39:35 +02:00
|
|
|
|
if (!optimize_size)
|
|
|
|
|
{
|
|
|
|
|
rtx a1reg = gen_rtx_REG (PDImode, REG_A1);
|
|
|
|
|
rtx a0reg = gen_rtx_REG (PDImode, REG_A0);
|
|
|
|
|
emit_insn (gen_flag_macinit1hi (a1reg,
|
|
|
|
|
gen_lowpart (HImode, operands[1]),
|
|
|
|
|
gen_lowpart (HImode, operands[2]),
|
|
|
|
|
GEN_INT (MACFLAG_FU)));
|
|
|
|
|
emit_insn (gen_lshrpdi3 (a1reg, a1reg, GEN_INT (16)));
|
|
|
|
|
emit_insn (gen_flag_mul_macv2hi_parts_acconly (a0reg, a1reg,
|
|
|
|
|
gen_lowpart (V2HImode, operands[1]),
|
|
|
|
|
gen_lowpart (V2HImode, operands[2]),
|
|
|
|
|
const1_rtx, const1_rtx,
|
|
|
|
|
const1_rtx, const0_rtx, a1reg,
|
|
|
|
|
const0_rtx, GEN_INT (MACFLAG_FU),
|
|
|
|
|
GEN_INT (MACFLAG_FU)));
|
|
|
|
|
emit_insn (gen_flag_machi_parts_acconly (a1reg,
|
|
|
|
|
gen_lowpart (V2HImode, operands[2]),
|
|
|
|
|
gen_lowpart (V2HImode, operands[1]),
|
|
|
|
|
const1_rtx, const0_rtx,
|
|
|
|
|
a1reg, const0_rtx, GEN_INT (MACFLAG_FU)));
|
|
|
|
|
emit_insn (gen_lshrpdi3 (a1reg, a1reg, GEN_INT (16)));
|
2007-05-03 15:17:51 +02:00
|
|
|
|
emit_insn (gen_addpdi3 (a0reg, a0reg, a1reg));
|
|
|
|
|
emit_insn (gen_us_truncpdisi2 (operands[0], a0reg));
|
2007-04-12 15:39:35 +02:00
|
|
|
|
}
|
|
|
|
|
else
|
|
|
|
|
{
|
|
|
|
|
rtx umulsi3_highpart_libfunc
|
|
|
|
|
= init_one_libfunc ("__umulsi3_highpart");
|
2007-02-27 17:29:10 +01:00
|
|
|
|
|
2007-04-12 15:39:35 +02:00
|
|
|
|
emit_library_call_value (umulsi3_highpart_libfunc,
|
|
|
|
|
operands[0], LCT_NORMAL, SImode,
|
2017-09-04 09:30:53 +02:00
|
|
|
|
operands[1], SImode, operands[2], SImode);
|
2007-04-12 15:39:35 +02:00
|
|
|
|
}
|
2007-02-27 17:29:10 +01:00
|
|
|
|
DONE;
|
|
|
|
|
})
|
|
|
|
|
|
|
|
|
|
(define_expand "smulsi3_highpart"
|
2007-04-12 15:39:35 +02:00
|
|
|
|
[(parallel
|
|
|
|
|
[(set (match_operand:SI 0 "register_operand" "")
|
|
|
|
|
(truncate:SI
|
|
|
|
|
(lshiftrt:DI
|
|
|
|
|
(mult:DI (sign_extend:DI
|
|
|
|
|
(match_operand:SI 1 "nonimmediate_operand" ""))
|
|
|
|
|
(sign_extend:DI
|
|
|
|
|
(match_operand:SI 2 "register_operand" "")))
|
|
|
|
|
(const_int 32))))
|
|
|
|
|
(clobber (reg:PDI REG_A0))
|
|
|
|
|
(clobber (reg:PDI REG_A1))])]
|
2007-02-27 17:29:10 +01:00
|
|
|
|
""
|
|
|
|
|
{
|
2007-04-12 15:39:35 +02:00
|
|
|
|
if (!optimize_size)
|
|
|
|
|
{
|
|
|
|
|
rtx a1reg = gen_rtx_REG (PDImode, REG_A1);
|
|
|
|
|
rtx a0reg = gen_rtx_REG (PDImode, REG_A0);
|
|
|
|
|
emit_insn (gen_flag_macinit1hi (a1reg,
|
|
|
|
|
gen_lowpart (HImode, operands[1]),
|
|
|
|
|
gen_lowpart (HImode, operands[2]),
|
|
|
|
|
GEN_INT (MACFLAG_FU)));
|
|
|
|
|
emit_insn (gen_lshrpdi3 (a1reg, a1reg, GEN_INT (16)));
|
|
|
|
|
emit_insn (gen_flag_mul_macv2hi_parts_acconly (a0reg, a1reg,
|
|
|
|
|
gen_lowpart (V2HImode, operands[1]),
|
|
|
|
|
gen_lowpart (V2HImode, operands[2]),
|
|
|
|
|
const1_rtx, const1_rtx,
|
|
|
|
|
const1_rtx, const0_rtx, a1reg,
|
|
|
|
|
const0_rtx, GEN_INT (MACFLAG_IS),
|
|
|
|
|
GEN_INT (MACFLAG_IS_M)));
|
|
|
|
|
emit_insn (gen_flag_machi_parts_acconly (a1reg,
|
|
|
|
|
gen_lowpart (V2HImode, operands[2]),
|
|
|
|
|
gen_lowpart (V2HImode, operands[1]),
|
|
|
|
|
const1_rtx, const0_rtx,
|
|
|
|
|
a1reg, const0_rtx, GEN_INT (MACFLAG_IS_M)));
|
|
|
|
|
emit_insn (gen_ashrpdi3 (a1reg, a1reg, GEN_INT (16)));
|
|
|
|
|
emit_insn (gen_sum_of_accumulators (operands[0], a0reg, a0reg, a1reg));
|
|
|
|
|
}
|
|
|
|
|
else
|
|
|
|
|
{
|
|
|
|
|
rtx smulsi3_highpart_libfunc
|
|
|
|
|
= init_one_libfunc ("__smulsi3_highpart");
|
2007-02-27 17:29:10 +01:00
|
|
|
|
|
2007-04-12 15:39:35 +02:00
|
|
|
|
emit_library_call_value (smulsi3_highpart_libfunc,
|
|
|
|
|
operands[0], LCT_NORMAL, SImode,
|
2017-09-04 09:30:53 +02:00
|
|
|
|
operands[1], SImode, operands[2], SImode);
|
2007-04-12 15:39:35 +02:00
|
|
|
|
}
|
2007-02-27 17:29:10 +01:00
|
|
|
|
DONE;
|
|
|
|
|
})
|
|
|
|
|
|
2005-04-05 13:26:48 +02:00
|
|
|
|
(define_expand "ashlsi3"
|
|
|
|
|
[(set (match_operand:SI 0 "register_operand" "")
|
|
|
|
|
(ashift:SI (match_operand:SI 1 "register_operand" "")
|
|
|
|
|
(match_operand:SI 2 "nonmemory_operand" "")))]
|
|
|
|
|
""
|
|
|
|
|
{
|
|
|
|
|
if (GET_CODE (operands[2]) == CONST_INT
|
|
|
|
|
&& ((unsigned HOST_WIDE_INT) INTVAL (operands[2])) > 31)
|
|
|
|
|
{
|
|
|
|
|
emit_insn (gen_movsi (operands[0], const0_rtx));
|
|
|
|
|
DONE;
|
|
|
|
|
}
|
|
|
|
|
})
|
|
|
|
|
|
|
|
|
|
(define_insn_and_split "*ashlsi3_insn"
|
rtlanal.c (note_uses): Deal with SEQUENCEs.
* rtlanal.c (note_uses): Deal with SEQUENCEs.
* config/bfin/bfin.c: Include "timevar.h".
(bfin_flag_schedule_insns2, splitting_for_sched,
bfin_flag_var_tracking): New variables.
(print_operand): Handle '%!'.
(override_options): Disable normal sched2 pass, instead set
bfin_flag_schedule_insns2 for reorg to handle it.
(output_file_start): Likewise for var-tracking.
(bfin_optimize_loop): Take some care not to stumble over SEQUENCEs.
(gen_one_bundle, bfin_gen_bundles, type_for_anomaly, trapping_loads_p):
New functions.
(bfin_reorg): Do second scheduling pass here, and call
bfin_gen_bundles. Use type_for_anomaly and trapping_loads_p instead
of examining insns directly. If bfin_flag_var_tracking, call
var-tracking pass when done with everything else.
* config/bfin/bfin.h (PRINT_OPERAND_PUNCT_VALID_P): '!' is valid.
* config/bfin/bfin.md (UNSPEC_32BIT): New constant.
(movsi_insn32): New pattern, with two new splits to create it
before the final scheduling pass.
(neghi2): Not a dsp32 insn, rather alu0.
(movbi, pushsi_insn, popsi_insn, movsi_insn, movv2hi_insn, movhi_insn,
movqi_insn, movsf_insn, movsi_insv, extendhisi2, zero_extendhisi2,
extendqihi2, extendqisi2, zero_extendqihi2, zero_extendqisi2,
mulhisi3, umulhisi3, ssadsi3, sssubsi3, smaxsi3, sminsi3, abssi2,
ssnegsi2, signbitssi2, smaxhi3, sminhi3, abshi2, ssneghi2, signbitshi2,
movhi_low2high, movhi_high2high, movhi_low2low, movhi_high2low,
movhiv2hi_low, movhiv2hi_high, composev2hi, packv2hi, movv2hi_hi,
ssaddhi3, sssubhi3, addv2hi3, ssaddv2hi3, subv2hi3, sssubv2hi3,
addsubv2hi3, subaddv2hi3, ssaddsubv2hi3, sssubaddv2hi3, sublohiv2hi3,
subhilov2hi3, sssublohiv2hi3, sssubhilov2hi3, addlohiv2hi3,
addhilov2hi3, ssaddlohiv2hi3, ssaddhilov2hi3, sminv2hi3, smaxv2hi3,
flag_mulhi, flag_mulhisi, flag_mulhisi_parts, flag_machi,
flag_machi_acconly, flag_macinithi, flag_macinit1hi, mulv2hi3,
flag_mulv2hi, flag_mulv2hi_parts, flag_macv2hi_parts,
flag_macv2hi_parts_acconly, flag_macinitv2hi_parts,
flag_macinit1v2hi_parts, mulhisi_ll, mulhisi_lh, mulhisi_hl,
mulhisi_hh, ssnegv2hi2, absv2hi2, ssashiftv2hi3, ssashifthi3,
lshiftv2hi3, lshifthi3): Use '%!' to terminate all dsp32/load/store
variants instead of ';'.
(ror_one, rol_one): Likewise. Make them dsp32 insns.
(ashlsi3_insn, ashrsi3, lshrsi3): Add dsp32 variants.
(align8, align16, align24): Now named patterns; also using '%!'.
(mnop): New insn.
From-SVN: r119534
2006-12-05 09:49:56 +01:00
|
|
|
|
[(set (match_operand:SI 0 "register_operand" "=d,d,a,a,a")
|
|
|
|
|
(ashift:SI (match_operand:SI 1 "register_operand" "0,d,a,a,a")
|
|
|
|
|
(match_operand:SI 2 "nonmemory_operand" "dKu5,Ku5,P1,P2,?P3P4")))]
|
2005-04-05 13:26:48 +02:00
|
|
|
|
""
|
|
|
|
|
"@
|
|
|
|
|
%0 <<= %2;
|
rtlanal.c (note_uses): Deal with SEQUENCEs.
* rtlanal.c (note_uses): Deal with SEQUENCEs.
* config/bfin/bfin.c: Include "timevar.h".
(bfin_flag_schedule_insns2, splitting_for_sched,
bfin_flag_var_tracking): New variables.
(print_operand): Handle '%!'.
(override_options): Disable normal sched2 pass, instead set
bfin_flag_schedule_insns2 for reorg to handle it.
(output_file_start): Likewise for var-tracking.
(bfin_optimize_loop): Take some care not to stumble over SEQUENCEs.
(gen_one_bundle, bfin_gen_bundles, type_for_anomaly, trapping_loads_p):
New functions.
(bfin_reorg): Do second scheduling pass here, and call
bfin_gen_bundles. Use type_for_anomaly and trapping_loads_p instead
of examining insns directly. If bfin_flag_var_tracking, call
var-tracking pass when done with everything else.
* config/bfin/bfin.h (PRINT_OPERAND_PUNCT_VALID_P): '!' is valid.
* config/bfin/bfin.md (UNSPEC_32BIT): New constant.
(movsi_insn32): New pattern, with two new splits to create it
before the final scheduling pass.
(neghi2): Not a dsp32 insn, rather alu0.
(movbi, pushsi_insn, popsi_insn, movsi_insn, movv2hi_insn, movhi_insn,
movqi_insn, movsf_insn, movsi_insv, extendhisi2, zero_extendhisi2,
extendqihi2, extendqisi2, zero_extendqihi2, zero_extendqisi2,
mulhisi3, umulhisi3, ssadsi3, sssubsi3, smaxsi3, sminsi3, abssi2,
ssnegsi2, signbitssi2, smaxhi3, sminhi3, abshi2, ssneghi2, signbitshi2,
movhi_low2high, movhi_high2high, movhi_low2low, movhi_high2low,
movhiv2hi_low, movhiv2hi_high, composev2hi, packv2hi, movv2hi_hi,
ssaddhi3, sssubhi3, addv2hi3, ssaddv2hi3, subv2hi3, sssubv2hi3,
addsubv2hi3, subaddv2hi3, ssaddsubv2hi3, sssubaddv2hi3, sublohiv2hi3,
subhilov2hi3, sssublohiv2hi3, sssubhilov2hi3, addlohiv2hi3,
addhilov2hi3, ssaddlohiv2hi3, ssaddhilov2hi3, sminv2hi3, smaxv2hi3,
flag_mulhi, flag_mulhisi, flag_mulhisi_parts, flag_machi,
flag_machi_acconly, flag_macinithi, flag_macinit1hi, mulv2hi3,
flag_mulv2hi, flag_mulv2hi_parts, flag_macv2hi_parts,
flag_macv2hi_parts_acconly, flag_macinitv2hi_parts,
flag_macinit1v2hi_parts, mulhisi_ll, mulhisi_lh, mulhisi_hl,
mulhisi_hh, ssnegv2hi2, absv2hi2, ssashiftv2hi3, ssashifthi3,
lshiftv2hi3, lshifthi3): Use '%!' to terminate all dsp32/load/store
variants instead of ';'.
(ror_one, rol_one): Likewise. Make them dsp32 insns.
(ashlsi3_insn, ashrsi3, lshrsi3): Add dsp32 variants.
(align8, align16, align24): Now named patterns; also using '%!'.
(mnop): New insn.
From-SVN: r119534
2006-12-05 09:49:56 +01:00
|
|
|
|
%0 = %1 << %2%!
|
2005-04-05 13:26:48 +02:00
|
|
|
|
%0 = %1 + %1;
|
|
|
|
|
%0 = %1 << %2;
|
|
|
|
|
#"
|
|
|
|
|
"PREG_P (operands[0]) && INTVAL (operands[2]) > 2"
|
|
|
|
|
[(set (match_dup 0) (ashift:SI (match_dup 1) (const_int 2)))
|
|
|
|
|
(set (match_dup 0) (ashift:SI (match_dup 0) (match_dup 3)))]
|
|
|
|
|
"operands[3] = GEN_INT (INTVAL (operands[2]) - 2);"
|
From Jie Zhang <jie.zhang@analog.com>:
* config/bfin/predicates.md (p_register_operand): New
predicate.
(dp_register_operand): New predicate.
* config/bfin/bfin-protos.h (WA_05000074): Define.
(ENABLE_WA_05000074): Define.
* config/bfin/bfin.c (bfin_cpus[]): Add WA_05000074 for
all cpus.
(bfin_gen_bundles): Put dsp32shiftimm instruction in slot[0].
* config/bfin/bfin.md (define_attr type): Add dsp32shiftimm.
(define_attr addrtype): Allow load/store register to be
P register.
(define_attr storereg): New.
(define_cpu_unit anomaly_05000074): New.
(define_insn_reservation dsp32shiftimm): New.
(define_insn_reservation dsp32shiftimm_anomaly_05000074): New.
(define_insn_reservation loadp): Cannot use slot2.
(define_insn_reservation loadsp): Cannot use slot2.
(define_insn_reservation storep): Cannot use slot2. Does not
apply when working around 05000074.
(define_insn_reservation storep_anomaly_05000074): New.
(define_insn_reservation storei): Does not apply when working
around 05000074.
(define_insn_reservation storei_anomaly_05000074): New.
(define_attr length): Add dsp32shiftimm case.
(define_insn movsi_insn32, movsi_insv, ashlsi3_insn, ashrsi3,
ror_one, rol_one, lshrsi3, lshrpdi3, ashrpdi3, movhiv2hi_low,
movhiv2hi_high, composev2hi, packv2hi, movv2hi_hi,
ssashiftv2hi3, ssashifthi3, ssashiftsi3, lshiftv2hi3, lshifthi3):
Set type as dsp32shiftimm for dsp32shiftimm alternatives.
From-SVN: r151490
2009-09-07 23:40:23 +02:00
|
|
|
|
[(set_attr "type" "shft,dsp32shiftimm,shft,shft,*")])
|
2005-04-05 13:26:48 +02:00
|
|
|
|
|
|
|
|
|
(define_insn "ashrsi3"
|
rtlanal.c (note_uses): Deal with SEQUENCEs.
* rtlanal.c (note_uses): Deal with SEQUENCEs.
* config/bfin/bfin.c: Include "timevar.h".
(bfin_flag_schedule_insns2, splitting_for_sched,
bfin_flag_var_tracking): New variables.
(print_operand): Handle '%!'.
(override_options): Disable normal sched2 pass, instead set
bfin_flag_schedule_insns2 for reorg to handle it.
(output_file_start): Likewise for var-tracking.
(bfin_optimize_loop): Take some care not to stumble over SEQUENCEs.
(gen_one_bundle, bfin_gen_bundles, type_for_anomaly, trapping_loads_p):
New functions.
(bfin_reorg): Do second scheduling pass here, and call
bfin_gen_bundles. Use type_for_anomaly and trapping_loads_p instead
of examining insns directly. If bfin_flag_var_tracking, call
var-tracking pass when done with everything else.
* config/bfin/bfin.h (PRINT_OPERAND_PUNCT_VALID_P): '!' is valid.
* config/bfin/bfin.md (UNSPEC_32BIT): New constant.
(movsi_insn32): New pattern, with two new splits to create it
before the final scheduling pass.
(neghi2): Not a dsp32 insn, rather alu0.
(movbi, pushsi_insn, popsi_insn, movsi_insn, movv2hi_insn, movhi_insn,
movqi_insn, movsf_insn, movsi_insv, extendhisi2, zero_extendhisi2,
extendqihi2, extendqisi2, zero_extendqihi2, zero_extendqisi2,
mulhisi3, umulhisi3, ssadsi3, sssubsi3, smaxsi3, sminsi3, abssi2,
ssnegsi2, signbitssi2, smaxhi3, sminhi3, abshi2, ssneghi2, signbitshi2,
movhi_low2high, movhi_high2high, movhi_low2low, movhi_high2low,
movhiv2hi_low, movhiv2hi_high, composev2hi, packv2hi, movv2hi_hi,
ssaddhi3, sssubhi3, addv2hi3, ssaddv2hi3, subv2hi3, sssubv2hi3,
addsubv2hi3, subaddv2hi3, ssaddsubv2hi3, sssubaddv2hi3, sublohiv2hi3,
subhilov2hi3, sssublohiv2hi3, sssubhilov2hi3, addlohiv2hi3,
addhilov2hi3, ssaddlohiv2hi3, ssaddhilov2hi3, sminv2hi3, smaxv2hi3,
flag_mulhi, flag_mulhisi, flag_mulhisi_parts, flag_machi,
flag_machi_acconly, flag_macinithi, flag_macinit1hi, mulv2hi3,
flag_mulv2hi, flag_mulv2hi_parts, flag_macv2hi_parts,
flag_macv2hi_parts_acconly, flag_macinitv2hi_parts,
flag_macinit1v2hi_parts, mulhisi_ll, mulhisi_lh, mulhisi_hl,
mulhisi_hh, ssnegv2hi2, absv2hi2, ssashiftv2hi3, ssashifthi3,
lshiftv2hi3, lshifthi3): Use '%!' to terminate all dsp32/load/store
variants instead of ';'.
(ror_one, rol_one): Likewise. Make them dsp32 insns.
(ashlsi3_insn, ashrsi3, lshrsi3): Add dsp32 variants.
(align8, align16, align24): Now named patterns; also using '%!'.
(mnop): New insn.
From-SVN: r119534
2006-12-05 09:49:56 +01:00
|
|
|
|
[(set (match_operand:SI 0 "register_operand" "=d,d")
|
|
|
|
|
(ashiftrt:SI (match_operand:SI 1 "register_operand" "0,d")
|
|
|
|
|
(match_operand:SI 2 "nonmemory_operand" "dKu5,Ku5")))]
|
2005-04-05 13:26:48 +02:00
|
|
|
|
""
|
rtlanal.c (note_uses): Deal with SEQUENCEs.
* rtlanal.c (note_uses): Deal with SEQUENCEs.
* config/bfin/bfin.c: Include "timevar.h".
(bfin_flag_schedule_insns2, splitting_for_sched,
bfin_flag_var_tracking): New variables.
(print_operand): Handle '%!'.
(override_options): Disable normal sched2 pass, instead set
bfin_flag_schedule_insns2 for reorg to handle it.
(output_file_start): Likewise for var-tracking.
(bfin_optimize_loop): Take some care not to stumble over SEQUENCEs.
(gen_one_bundle, bfin_gen_bundles, type_for_anomaly, trapping_loads_p):
New functions.
(bfin_reorg): Do second scheduling pass here, and call
bfin_gen_bundles. Use type_for_anomaly and trapping_loads_p instead
of examining insns directly. If bfin_flag_var_tracking, call
var-tracking pass when done with everything else.
* config/bfin/bfin.h (PRINT_OPERAND_PUNCT_VALID_P): '!' is valid.
* config/bfin/bfin.md (UNSPEC_32BIT): New constant.
(movsi_insn32): New pattern, with two new splits to create it
before the final scheduling pass.
(neghi2): Not a dsp32 insn, rather alu0.
(movbi, pushsi_insn, popsi_insn, movsi_insn, movv2hi_insn, movhi_insn,
movqi_insn, movsf_insn, movsi_insv, extendhisi2, zero_extendhisi2,
extendqihi2, extendqisi2, zero_extendqihi2, zero_extendqisi2,
mulhisi3, umulhisi3, ssadsi3, sssubsi3, smaxsi3, sminsi3, abssi2,
ssnegsi2, signbitssi2, smaxhi3, sminhi3, abshi2, ssneghi2, signbitshi2,
movhi_low2high, movhi_high2high, movhi_low2low, movhi_high2low,
movhiv2hi_low, movhiv2hi_high, composev2hi, packv2hi, movv2hi_hi,
ssaddhi3, sssubhi3, addv2hi3, ssaddv2hi3, subv2hi3, sssubv2hi3,
addsubv2hi3, subaddv2hi3, ssaddsubv2hi3, sssubaddv2hi3, sublohiv2hi3,
subhilov2hi3, sssublohiv2hi3, sssubhilov2hi3, addlohiv2hi3,
addhilov2hi3, ssaddlohiv2hi3, ssaddhilov2hi3, sminv2hi3, smaxv2hi3,
flag_mulhi, flag_mulhisi, flag_mulhisi_parts, flag_machi,
flag_machi_acconly, flag_macinithi, flag_macinit1hi, mulv2hi3,
flag_mulv2hi, flag_mulv2hi_parts, flag_macv2hi_parts,
flag_macv2hi_parts_acconly, flag_macinitv2hi_parts,
flag_macinit1v2hi_parts, mulhisi_ll, mulhisi_lh, mulhisi_hl,
mulhisi_hh, ssnegv2hi2, absv2hi2, ssashiftv2hi3, ssashifthi3,
lshiftv2hi3, lshifthi3): Use '%!' to terminate all dsp32/load/store
variants instead of ';'.
(ror_one, rol_one): Likewise. Make them dsp32 insns.
(ashlsi3_insn, ashrsi3, lshrsi3): Add dsp32 variants.
(align8, align16, align24): Now named patterns; also using '%!'.
(mnop): New insn.
From-SVN: r119534
2006-12-05 09:49:56 +01:00
|
|
|
|
"@
|
|
|
|
|
%0 >>>= %2;
|
|
|
|
|
%0 = %1 >>> %2%!"
|
From Jie Zhang <jie.zhang@analog.com>:
* config/bfin/predicates.md (p_register_operand): New
predicate.
(dp_register_operand): New predicate.
* config/bfin/bfin-protos.h (WA_05000074): Define.
(ENABLE_WA_05000074): Define.
* config/bfin/bfin.c (bfin_cpus[]): Add WA_05000074 for
all cpus.
(bfin_gen_bundles): Put dsp32shiftimm instruction in slot[0].
* config/bfin/bfin.md (define_attr type): Add dsp32shiftimm.
(define_attr addrtype): Allow load/store register to be
P register.
(define_attr storereg): New.
(define_cpu_unit anomaly_05000074): New.
(define_insn_reservation dsp32shiftimm): New.
(define_insn_reservation dsp32shiftimm_anomaly_05000074): New.
(define_insn_reservation loadp): Cannot use slot2.
(define_insn_reservation loadsp): Cannot use slot2.
(define_insn_reservation storep): Cannot use slot2. Does not
apply when working around 05000074.
(define_insn_reservation storep_anomaly_05000074): New.
(define_insn_reservation storei): Does not apply when working
around 05000074.
(define_insn_reservation storei_anomaly_05000074): New.
(define_attr length): Add dsp32shiftimm case.
(define_insn movsi_insn32, movsi_insv, ashlsi3_insn, ashrsi3,
ror_one, rol_one, lshrsi3, lshrpdi3, ashrpdi3, movhiv2hi_low,
movhiv2hi_high, composev2hi, packv2hi, movv2hi_hi,
ssashiftv2hi3, ssashifthi3, ssashiftsi3, lshiftv2hi3, lshifthi3):
Set type as dsp32shiftimm for dsp32shiftimm alternatives.
From-SVN: r151490
2009-09-07 23:40:23 +02:00
|
|
|
|
[(set_attr "type" "shft,dsp32shiftimm")])
|
2005-04-05 13:26:48 +02:00
|
|
|
|
|
2007-02-27 16:26:19 +01:00
|
|
|
|
(define_insn "rotl16"
|
|
|
|
|
[(set (match_operand:SI 0 "register_operand" "=d")
|
|
|
|
|
(rotate:SI (match_operand:SI 1 "register_operand" "d")
|
|
|
|
|
(const_int 16)))]
|
|
|
|
|
""
|
|
|
|
|
"%0 = PACK (%h1, %d1)%!"
|
|
|
|
|
[(set_attr "type" "dsp32")])
|
|
|
|
|
|
|
|
|
|
(define_expand "rotlsi3"
|
|
|
|
|
[(set (match_operand:SI 0 "register_operand" "")
|
|
|
|
|
(rotate:SI (match_operand:SI 1 "register_operand" "")
|
2011-05-03 17:09:19 +02:00
|
|
|
|
(match_operand:SI 2 "const_int_operand" "")))]
|
2007-02-27 16:26:19 +01:00
|
|
|
|
""
|
|
|
|
|
{
|
2011-05-03 17:09:19 +02:00
|
|
|
|
if (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) != 16)
|
2007-02-27 16:26:19 +01:00
|
|
|
|
FAIL;
|
|
|
|
|
})
|
|
|
|
|
|
|
|
|
|
(define_expand "rotrsi3"
|
|
|
|
|
[(set (match_operand:SI 0 "register_operand" "")
|
|
|
|
|
(rotatert:SI (match_operand:SI 1 "register_operand" "")
|
2011-05-03 17:09:19 +02:00
|
|
|
|
(match_operand:SI 2 "const_int_operand" "")))]
|
2007-02-27 16:26:19 +01:00
|
|
|
|
""
|
|
|
|
|
{
|
2011-05-03 17:09:19 +02:00
|
|
|
|
if (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) != 16)
|
2007-02-27 16:26:19 +01:00
|
|
|
|
FAIL;
|
|
|
|
|
emit_insn (gen_rotl16 (operands[0], operands[1]));
|
|
|
|
|
DONE;
|
|
|
|
|
})
|
|
|
|
|
|
|
|
|
|
|
bfin.md (ror_one, [...]): New patterns.
* config/bfin/bfin.md (ror_one, rol_one, ashrdi3, ashldi3, lshrdi3):
New patterns.
(movbi): Add alternative to set CC to zero.
(compare_eq, compare_ne, compare_le, compare_lt, compare_leu,
compare_ltu): Now named patterns.
From-SVN: r101320
2005-06-25 13:52:32 +02:00
|
|
|
|
(define_insn "ror_one"
|
|
|
|
|
[(set (match_operand:SI 0 "register_operand" "=d")
|
|
|
|
|
(ior:SI (lshiftrt:SI (match_operand:SI 1 "register_operand" "d") (const_int 1))
|
|
|
|
|
(ashift:SI (zero_extend:SI (reg:BI REG_CC)) (const_int 31))))
|
|
|
|
|
(set (reg:BI REG_CC)
|
|
|
|
|
(zero_extract:BI (match_dup 1) (const_int 1) (const_int 0)))]
|
|
|
|
|
""
|
rtlanal.c (note_uses): Deal with SEQUENCEs.
* rtlanal.c (note_uses): Deal with SEQUENCEs.
* config/bfin/bfin.c: Include "timevar.h".
(bfin_flag_schedule_insns2, splitting_for_sched,
bfin_flag_var_tracking): New variables.
(print_operand): Handle '%!'.
(override_options): Disable normal sched2 pass, instead set
bfin_flag_schedule_insns2 for reorg to handle it.
(output_file_start): Likewise for var-tracking.
(bfin_optimize_loop): Take some care not to stumble over SEQUENCEs.
(gen_one_bundle, bfin_gen_bundles, type_for_anomaly, trapping_loads_p):
New functions.
(bfin_reorg): Do second scheduling pass here, and call
bfin_gen_bundles. Use type_for_anomaly and trapping_loads_p instead
of examining insns directly. If bfin_flag_var_tracking, call
var-tracking pass when done with everything else.
* config/bfin/bfin.h (PRINT_OPERAND_PUNCT_VALID_P): '!' is valid.
* config/bfin/bfin.md (UNSPEC_32BIT): New constant.
(movsi_insn32): New pattern, with two new splits to create it
before the final scheduling pass.
(neghi2): Not a dsp32 insn, rather alu0.
(movbi, pushsi_insn, popsi_insn, movsi_insn, movv2hi_insn, movhi_insn,
movqi_insn, movsf_insn, movsi_insv, extendhisi2, zero_extendhisi2,
extendqihi2, extendqisi2, zero_extendqihi2, zero_extendqisi2,
mulhisi3, umulhisi3, ssadsi3, sssubsi3, smaxsi3, sminsi3, abssi2,
ssnegsi2, signbitssi2, smaxhi3, sminhi3, abshi2, ssneghi2, signbitshi2,
movhi_low2high, movhi_high2high, movhi_low2low, movhi_high2low,
movhiv2hi_low, movhiv2hi_high, composev2hi, packv2hi, movv2hi_hi,
ssaddhi3, sssubhi3, addv2hi3, ssaddv2hi3, subv2hi3, sssubv2hi3,
addsubv2hi3, subaddv2hi3, ssaddsubv2hi3, sssubaddv2hi3, sublohiv2hi3,
subhilov2hi3, sssublohiv2hi3, sssubhilov2hi3, addlohiv2hi3,
addhilov2hi3, ssaddlohiv2hi3, ssaddhilov2hi3, sminv2hi3, smaxv2hi3,
flag_mulhi, flag_mulhisi, flag_mulhisi_parts, flag_machi,
flag_machi_acconly, flag_macinithi, flag_macinit1hi, mulv2hi3,
flag_mulv2hi, flag_mulv2hi_parts, flag_macv2hi_parts,
flag_macv2hi_parts_acconly, flag_macinitv2hi_parts,
flag_macinit1v2hi_parts, mulhisi_ll, mulhisi_lh, mulhisi_hl,
mulhisi_hh, ssnegv2hi2, absv2hi2, ssashiftv2hi3, ssashifthi3,
lshiftv2hi3, lshifthi3): Use '%!' to terminate all dsp32/load/store
variants instead of ';'.
(ror_one, rol_one): Likewise. Make them dsp32 insns.
(ashlsi3_insn, ashrsi3, lshrsi3): Add dsp32 variants.
(align8, align16, align24): Now named patterns; also using '%!'.
(mnop): New insn.
From-SVN: r119534
2006-12-05 09:49:56 +01:00
|
|
|
|
"%0 = ROT %1 BY -1%!"
|
From Jie Zhang <jie.zhang@analog.com>:
* config/bfin/predicates.md (p_register_operand): New
predicate.
(dp_register_operand): New predicate.
* config/bfin/bfin-protos.h (WA_05000074): Define.
(ENABLE_WA_05000074): Define.
* config/bfin/bfin.c (bfin_cpus[]): Add WA_05000074 for
all cpus.
(bfin_gen_bundles): Put dsp32shiftimm instruction in slot[0].
* config/bfin/bfin.md (define_attr type): Add dsp32shiftimm.
(define_attr addrtype): Allow load/store register to be
P register.
(define_attr storereg): New.
(define_cpu_unit anomaly_05000074): New.
(define_insn_reservation dsp32shiftimm): New.
(define_insn_reservation dsp32shiftimm_anomaly_05000074): New.
(define_insn_reservation loadp): Cannot use slot2.
(define_insn_reservation loadsp): Cannot use slot2.
(define_insn_reservation storep): Cannot use slot2. Does not
apply when working around 05000074.
(define_insn_reservation storep_anomaly_05000074): New.
(define_insn_reservation storei): Does not apply when working
around 05000074.
(define_insn_reservation storei_anomaly_05000074): New.
(define_attr length): Add dsp32shiftimm case.
(define_insn movsi_insn32, movsi_insv, ashlsi3_insn, ashrsi3,
ror_one, rol_one, lshrsi3, lshrpdi3, ashrpdi3, movhiv2hi_low,
movhiv2hi_high, composev2hi, packv2hi, movv2hi_hi,
ssashiftv2hi3, ssashifthi3, ssashiftsi3, lshiftv2hi3, lshifthi3):
Set type as dsp32shiftimm for dsp32shiftimm alternatives.
From-SVN: r151490
2009-09-07 23:40:23 +02:00
|
|
|
|
[(set_attr "type" "dsp32shiftimm")])
|
bfin.md (ror_one, [...]): New patterns.
* config/bfin/bfin.md (ror_one, rol_one, ashrdi3, ashldi3, lshrdi3):
New patterns.
(movbi): Add alternative to set CC to zero.
(compare_eq, compare_ne, compare_le, compare_lt, compare_leu,
compare_ltu): Now named patterns.
From-SVN: r101320
2005-06-25 13:52:32 +02:00
|
|
|
|
|
|
|
|
|
(define_insn "rol_one"
|
|
|
|
|
[(set (match_operand:SI 0 "register_operand" "+d")
|
|
|
|
|
(ior:SI (ashift:SI (match_operand:SI 1 "register_operand" "d") (const_int 1))
|
|
|
|
|
(zero_extend:SI (reg:BI REG_CC))))
|
|
|
|
|
(set (reg:BI REG_CC)
|
2022-04-11 05:02:48 +02:00
|
|
|
|
(zero_extract:BI (match_dup 1) (const_int 1) (const_int 31)))]
|
bfin.md (ror_one, [...]): New patterns.
* config/bfin/bfin.md (ror_one, rol_one, ashrdi3, ashldi3, lshrdi3):
New patterns.
(movbi): Add alternative to set CC to zero.
(compare_eq, compare_ne, compare_le, compare_lt, compare_leu,
compare_ltu): Now named patterns.
From-SVN: r101320
2005-06-25 13:52:32 +02:00
|
|
|
|
""
|
rtlanal.c (note_uses): Deal with SEQUENCEs.
* rtlanal.c (note_uses): Deal with SEQUENCEs.
* config/bfin/bfin.c: Include "timevar.h".
(bfin_flag_schedule_insns2, splitting_for_sched,
bfin_flag_var_tracking): New variables.
(print_operand): Handle '%!'.
(override_options): Disable normal sched2 pass, instead set
bfin_flag_schedule_insns2 for reorg to handle it.
(output_file_start): Likewise for var-tracking.
(bfin_optimize_loop): Take some care not to stumble over SEQUENCEs.
(gen_one_bundle, bfin_gen_bundles, type_for_anomaly, trapping_loads_p):
New functions.
(bfin_reorg): Do second scheduling pass here, and call
bfin_gen_bundles. Use type_for_anomaly and trapping_loads_p instead
of examining insns directly. If bfin_flag_var_tracking, call
var-tracking pass when done with everything else.
* config/bfin/bfin.h (PRINT_OPERAND_PUNCT_VALID_P): '!' is valid.
* config/bfin/bfin.md (UNSPEC_32BIT): New constant.
(movsi_insn32): New pattern, with two new splits to create it
before the final scheduling pass.
(neghi2): Not a dsp32 insn, rather alu0.
(movbi, pushsi_insn, popsi_insn, movsi_insn, movv2hi_insn, movhi_insn,
movqi_insn, movsf_insn, movsi_insv, extendhisi2, zero_extendhisi2,
extendqihi2, extendqisi2, zero_extendqihi2, zero_extendqisi2,
mulhisi3, umulhisi3, ssadsi3, sssubsi3, smaxsi3, sminsi3, abssi2,
ssnegsi2, signbitssi2, smaxhi3, sminhi3, abshi2, ssneghi2, signbitshi2,
movhi_low2high, movhi_high2high, movhi_low2low, movhi_high2low,
movhiv2hi_low, movhiv2hi_high, composev2hi, packv2hi, movv2hi_hi,
ssaddhi3, sssubhi3, addv2hi3, ssaddv2hi3, subv2hi3, sssubv2hi3,
addsubv2hi3, subaddv2hi3, ssaddsubv2hi3, sssubaddv2hi3, sublohiv2hi3,
subhilov2hi3, sssublohiv2hi3, sssubhilov2hi3, addlohiv2hi3,
addhilov2hi3, ssaddlohiv2hi3, ssaddhilov2hi3, sminv2hi3, smaxv2hi3,
flag_mulhi, flag_mulhisi, flag_mulhisi_parts, flag_machi,
flag_machi_acconly, flag_macinithi, flag_macinit1hi, mulv2hi3,
flag_mulv2hi, flag_mulv2hi_parts, flag_macv2hi_parts,
flag_macv2hi_parts_acconly, flag_macinitv2hi_parts,
flag_macinit1v2hi_parts, mulhisi_ll, mulhisi_lh, mulhisi_hl,
mulhisi_hh, ssnegv2hi2, absv2hi2, ssashiftv2hi3, ssashifthi3,
lshiftv2hi3, lshifthi3): Use '%!' to terminate all dsp32/load/store
variants instead of ';'.
(ror_one, rol_one): Likewise. Make them dsp32 insns.
(ashlsi3_insn, ashrsi3, lshrsi3): Add dsp32 variants.
(align8, align16, align24): Now named patterns; also using '%!'.
(mnop): New insn.
From-SVN: r119534
2006-12-05 09:49:56 +01:00
|
|
|
|
"%0 = ROT %1 BY 1%!"
|
From Jie Zhang <jie.zhang@analog.com>:
* config/bfin/predicates.md (p_register_operand): New
predicate.
(dp_register_operand): New predicate.
* config/bfin/bfin-protos.h (WA_05000074): Define.
(ENABLE_WA_05000074): Define.
* config/bfin/bfin.c (bfin_cpus[]): Add WA_05000074 for
all cpus.
(bfin_gen_bundles): Put dsp32shiftimm instruction in slot[0].
* config/bfin/bfin.md (define_attr type): Add dsp32shiftimm.
(define_attr addrtype): Allow load/store register to be
P register.
(define_attr storereg): New.
(define_cpu_unit anomaly_05000074): New.
(define_insn_reservation dsp32shiftimm): New.
(define_insn_reservation dsp32shiftimm_anomaly_05000074): New.
(define_insn_reservation loadp): Cannot use slot2.
(define_insn_reservation loadsp): Cannot use slot2.
(define_insn_reservation storep): Cannot use slot2. Does not
apply when working around 05000074.
(define_insn_reservation storep_anomaly_05000074): New.
(define_insn_reservation storei): Does not apply when working
around 05000074.
(define_insn_reservation storei_anomaly_05000074): New.
(define_attr length): Add dsp32shiftimm case.
(define_insn movsi_insn32, movsi_insv, ashlsi3_insn, ashrsi3,
ror_one, rol_one, lshrsi3, lshrpdi3, ashrpdi3, movhiv2hi_low,
movhiv2hi_high, composev2hi, packv2hi, movv2hi_hi,
ssashiftv2hi3, ssashifthi3, ssashiftsi3, lshiftv2hi3, lshifthi3):
Set type as dsp32shiftimm for dsp32shiftimm alternatives.
From-SVN: r151490
2009-09-07 23:40:23 +02:00
|
|
|
|
[(set_attr "type" "dsp32shiftimm")])
|
bfin.md (ror_one, [...]): New patterns.
* config/bfin/bfin.md (ror_one, rol_one, ashrdi3, ashldi3, lshrdi3):
New patterns.
(movbi): Add alternative to set CC to zero.
(compare_eq, compare_ne, compare_le, compare_lt, compare_leu,
compare_ltu): Now named patterns.
From-SVN: r101320
2005-06-25 13:52:32 +02:00
|
|
|
|
|
|
|
|
|
(define_expand "lshrdi3"
|
|
|
|
|
[(set (match_operand:DI 0 "register_operand" "")
|
|
|
|
|
(lshiftrt:DI (match_operand:DI 1 "register_operand" "")
|
|
|
|
|
(match_operand:DI 2 "general_operand" "")))]
|
|
|
|
|
""
|
|
|
|
|
{
|
|
|
|
|
rtx lo_half[2], hi_half[2];
|
|
|
|
|
|
|
|
|
|
if (operands[2] != const1_rtx)
|
|
|
|
|
FAIL;
|
|
|
|
|
if (! rtx_equal_p (operands[0], operands[1]))
|
|
|
|
|
emit_move_insn (operands[0], operands[1]);
|
|
|
|
|
|
|
|
|
|
split_di (operands, 2, lo_half, hi_half);
|
|
|
|
|
|
|
|
|
|
emit_move_insn (bfin_cc_rtx, const0_rtx);
|
|
|
|
|
emit_insn (gen_ror_one (hi_half[0], hi_half[0]));
|
|
|
|
|
emit_insn (gen_ror_one (lo_half[0], lo_half[0]));
|
|
|
|
|
DONE;
|
|
|
|
|
})
|
|
|
|
|
|
|
|
|
|
(define_expand "ashrdi3"
|
|
|
|
|
[(set (match_operand:DI 0 "register_operand" "")
|
|
|
|
|
(ashiftrt:DI (match_operand:DI 1 "register_operand" "")
|
|
|
|
|
(match_operand:DI 2 "general_operand" "")))]
|
|
|
|
|
""
|
|
|
|
|
{
|
|
|
|
|
rtx lo_half[2], hi_half[2];
|
|
|
|
|
|
|
|
|
|
if (operands[2] != const1_rtx)
|
|
|
|
|
FAIL;
|
|
|
|
|
if (! rtx_equal_p (operands[0], operands[1]))
|
|
|
|
|
emit_move_insn (operands[0], operands[1]);
|
|
|
|
|
|
|
|
|
|
split_di (operands, 2, lo_half, hi_half);
|
|
|
|
|
|
|
|
|
|
emit_insn (gen_compare_lt (gen_rtx_REG (BImode, REG_CC),
|
|
|
|
|
hi_half[1], const0_rtx));
|
|
|
|
|
emit_insn (gen_ror_one (hi_half[0], hi_half[0]));
|
|
|
|
|
emit_insn (gen_ror_one (lo_half[0], lo_half[0]));
|
|
|
|
|
DONE;
|
|
|
|
|
})
|
|
|
|
|
|
|
|
|
|
(define_expand "ashldi3"
|
|
|
|
|
[(set (match_operand:DI 0 "register_operand" "")
|
|
|
|
|
(ashift:DI (match_operand:DI 1 "register_operand" "")
|
|
|
|
|
(match_operand:DI 2 "general_operand" "")))]
|
|
|
|
|
""
|
|
|
|
|
{
|
|
|
|
|
rtx lo_half[2], hi_half[2];
|
|
|
|
|
|
|
|
|
|
if (operands[2] != const1_rtx)
|
|
|
|
|
FAIL;
|
|
|
|
|
if (! rtx_equal_p (operands[0], operands[1]))
|
|
|
|
|
emit_move_insn (operands[0], operands[1]);
|
|
|
|
|
|
|
|
|
|
split_di (operands, 2, lo_half, hi_half);
|
|
|
|
|
|
|
|
|
|
emit_move_insn (bfin_cc_rtx, const0_rtx);
|
|
|
|
|
emit_insn (gen_rol_one (lo_half[0], lo_half[0]));
|
|
|
|
|
emit_insn (gen_rol_one (hi_half[0], hi_half[0]));
|
|
|
|
|
DONE;
|
|
|
|
|
})
|
|
|
|
|
|
2005-04-05 13:26:48 +02:00
|
|
|
|
(define_insn "lshrsi3"
|
rtlanal.c (note_uses): Deal with SEQUENCEs.
* rtlanal.c (note_uses): Deal with SEQUENCEs.
* config/bfin/bfin.c: Include "timevar.h".
(bfin_flag_schedule_insns2, splitting_for_sched,
bfin_flag_var_tracking): New variables.
(print_operand): Handle '%!'.
(override_options): Disable normal sched2 pass, instead set
bfin_flag_schedule_insns2 for reorg to handle it.
(output_file_start): Likewise for var-tracking.
(bfin_optimize_loop): Take some care not to stumble over SEQUENCEs.
(gen_one_bundle, bfin_gen_bundles, type_for_anomaly, trapping_loads_p):
New functions.
(bfin_reorg): Do second scheduling pass here, and call
bfin_gen_bundles. Use type_for_anomaly and trapping_loads_p instead
of examining insns directly. If bfin_flag_var_tracking, call
var-tracking pass when done with everything else.
* config/bfin/bfin.h (PRINT_OPERAND_PUNCT_VALID_P): '!' is valid.
* config/bfin/bfin.md (UNSPEC_32BIT): New constant.
(movsi_insn32): New pattern, with two new splits to create it
before the final scheduling pass.
(neghi2): Not a dsp32 insn, rather alu0.
(movbi, pushsi_insn, popsi_insn, movsi_insn, movv2hi_insn, movhi_insn,
movqi_insn, movsf_insn, movsi_insv, extendhisi2, zero_extendhisi2,
extendqihi2, extendqisi2, zero_extendqihi2, zero_extendqisi2,
mulhisi3, umulhisi3, ssadsi3, sssubsi3, smaxsi3, sminsi3, abssi2,
ssnegsi2, signbitssi2, smaxhi3, sminhi3, abshi2, ssneghi2, signbitshi2,
movhi_low2high, movhi_high2high, movhi_low2low, movhi_high2low,
movhiv2hi_low, movhiv2hi_high, composev2hi, packv2hi, movv2hi_hi,
ssaddhi3, sssubhi3, addv2hi3, ssaddv2hi3, subv2hi3, sssubv2hi3,
addsubv2hi3, subaddv2hi3, ssaddsubv2hi3, sssubaddv2hi3, sublohiv2hi3,
subhilov2hi3, sssublohiv2hi3, sssubhilov2hi3, addlohiv2hi3,
addhilov2hi3, ssaddlohiv2hi3, ssaddhilov2hi3, sminv2hi3, smaxv2hi3,
flag_mulhi, flag_mulhisi, flag_mulhisi_parts, flag_machi,
flag_machi_acconly, flag_macinithi, flag_macinit1hi, mulv2hi3,
flag_mulv2hi, flag_mulv2hi_parts, flag_macv2hi_parts,
flag_macv2hi_parts_acconly, flag_macinitv2hi_parts,
flag_macinit1v2hi_parts, mulhisi_ll, mulhisi_lh, mulhisi_hl,
mulhisi_hh, ssnegv2hi2, absv2hi2, ssashiftv2hi3, ssashifthi3,
lshiftv2hi3, lshifthi3): Use '%!' to terminate all dsp32/load/store
variants instead of ';'.
(ror_one, rol_one): Likewise. Make them dsp32 insns.
(ashlsi3_insn, ashrsi3, lshrsi3): Add dsp32 variants.
(align8, align16, align24): Now named patterns; also using '%!'.
(mnop): New insn.
From-SVN: r119534
2006-12-05 09:49:56 +01:00
|
|
|
|
[(set (match_operand:SI 0 "register_operand" "=d,d,a")
|
|
|
|
|
(lshiftrt:SI (match_operand:SI 1 "register_operand" "0,d,a")
|
|
|
|
|
(match_operand:SI 2 "nonmemory_operand" "dKu5,Ku5,P1P2")))]
|
2005-04-05 13:26:48 +02:00
|
|
|
|
""
|
|
|
|
|
"@
|
|
|
|
|
%0 >>= %2;
|
rtlanal.c (note_uses): Deal with SEQUENCEs.
* rtlanal.c (note_uses): Deal with SEQUENCEs.
* config/bfin/bfin.c: Include "timevar.h".
(bfin_flag_schedule_insns2, splitting_for_sched,
bfin_flag_var_tracking): New variables.
(print_operand): Handle '%!'.
(override_options): Disable normal sched2 pass, instead set
bfin_flag_schedule_insns2 for reorg to handle it.
(output_file_start): Likewise for var-tracking.
(bfin_optimize_loop): Take some care not to stumble over SEQUENCEs.
(gen_one_bundle, bfin_gen_bundles, type_for_anomaly, trapping_loads_p):
New functions.
(bfin_reorg): Do second scheduling pass here, and call
bfin_gen_bundles. Use type_for_anomaly and trapping_loads_p instead
of examining insns directly. If bfin_flag_var_tracking, call
var-tracking pass when done with everything else.
* config/bfin/bfin.h (PRINT_OPERAND_PUNCT_VALID_P): '!' is valid.
* config/bfin/bfin.md (UNSPEC_32BIT): New constant.
(movsi_insn32): New pattern, with two new splits to create it
before the final scheduling pass.
(neghi2): Not a dsp32 insn, rather alu0.
(movbi, pushsi_insn, popsi_insn, movsi_insn, movv2hi_insn, movhi_insn,
movqi_insn, movsf_insn, movsi_insv, extendhisi2, zero_extendhisi2,
extendqihi2, extendqisi2, zero_extendqihi2, zero_extendqisi2,
mulhisi3, umulhisi3, ssadsi3, sssubsi3, smaxsi3, sminsi3, abssi2,
ssnegsi2, signbitssi2, smaxhi3, sminhi3, abshi2, ssneghi2, signbitshi2,
movhi_low2high, movhi_high2high, movhi_low2low, movhi_high2low,
movhiv2hi_low, movhiv2hi_high, composev2hi, packv2hi, movv2hi_hi,
ssaddhi3, sssubhi3, addv2hi3, ssaddv2hi3, subv2hi3, sssubv2hi3,
addsubv2hi3, subaddv2hi3, ssaddsubv2hi3, sssubaddv2hi3, sublohiv2hi3,
subhilov2hi3, sssublohiv2hi3, sssubhilov2hi3, addlohiv2hi3,
addhilov2hi3, ssaddlohiv2hi3, ssaddhilov2hi3, sminv2hi3, smaxv2hi3,
flag_mulhi, flag_mulhisi, flag_mulhisi_parts, flag_machi,
flag_machi_acconly, flag_macinithi, flag_macinit1hi, mulv2hi3,
flag_mulv2hi, flag_mulv2hi_parts, flag_macv2hi_parts,
flag_macv2hi_parts_acconly, flag_macinitv2hi_parts,
flag_macinit1v2hi_parts, mulhisi_ll, mulhisi_lh, mulhisi_hl,
mulhisi_hh, ssnegv2hi2, absv2hi2, ssashiftv2hi3, ssashifthi3,
lshiftv2hi3, lshifthi3): Use '%!' to terminate all dsp32/load/store
variants instead of ';'.
(ror_one, rol_one): Likewise. Make them dsp32 insns.
(ashlsi3_insn, ashrsi3, lshrsi3): Add dsp32 variants.
(align8, align16, align24): Now named patterns; also using '%!'.
(mnop): New insn.
From-SVN: r119534
2006-12-05 09:49:56 +01:00
|
|
|
|
%0 = %1 >> %2%!
|
2005-04-05 13:26:48 +02:00
|
|
|
|
%0 = %1 >> %2;"
|
From Jie Zhang <jie.zhang@analog.com>:
* config/bfin/predicates.md (p_register_operand): New
predicate.
(dp_register_operand): New predicate.
* config/bfin/bfin-protos.h (WA_05000074): Define.
(ENABLE_WA_05000074): Define.
* config/bfin/bfin.c (bfin_cpus[]): Add WA_05000074 for
all cpus.
(bfin_gen_bundles): Put dsp32shiftimm instruction in slot[0].
* config/bfin/bfin.md (define_attr type): Add dsp32shiftimm.
(define_attr addrtype): Allow load/store register to be
P register.
(define_attr storereg): New.
(define_cpu_unit anomaly_05000074): New.
(define_insn_reservation dsp32shiftimm): New.
(define_insn_reservation dsp32shiftimm_anomaly_05000074): New.
(define_insn_reservation loadp): Cannot use slot2.
(define_insn_reservation loadsp): Cannot use slot2.
(define_insn_reservation storep): Cannot use slot2. Does not
apply when working around 05000074.
(define_insn_reservation storep_anomaly_05000074): New.
(define_insn_reservation storei): Does not apply when working
around 05000074.
(define_insn_reservation storei_anomaly_05000074): New.
(define_attr length): Add dsp32shiftimm case.
(define_insn movsi_insn32, movsi_insv, ashlsi3_insn, ashrsi3,
ror_one, rol_one, lshrsi3, lshrpdi3, ashrpdi3, movhiv2hi_low,
movhiv2hi_high, composev2hi, packv2hi, movv2hi_hi,
ssashiftv2hi3, ssashifthi3, ssashiftsi3, lshiftv2hi3, lshifthi3):
Set type as dsp32shiftimm for dsp32shiftimm alternatives.
From-SVN: r151490
2009-09-07 23:40:23 +02:00
|
|
|
|
[(set_attr "type" "shft,dsp32shiftimm,shft")])
|
2005-04-05 13:26:48 +02:00
|
|
|
|
|
2007-04-12 15:03:17 +02:00
|
|
|
|
(define_insn "lshrpdi3"
|
|
|
|
|
[(set (match_operand:PDI 0 "register_operand" "=e")
|
|
|
|
|
(lshiftrt:PDI (match_operand:PDI 1 "register_operand" "0")
|
|
|
|
|
(match_operand:SI 2 "nonmemory_operand" "Ku5")))]
|
|
|
|
|
""
|
|
|
|
|
"%0 = %1 >> %2%!"
|
From Jie Zhang <jie.zhang@analog.com>:
* config/bfin/predicates.md (p_register_operand): New
predicate.
(dp_register_operand): New predicate.
* config/bfin/bfin-protos.h (WA_05000074): Define.
(ENABLE_WA_05000074): Define.
* config/bfin/bfin.c (bfin_cpus[]): Add WA_05000074 for
all cpus.
(bfin_gen_bundles): Put dsp32shiftimm instruction in slot[0].
* config/bfin/bfin.md (define_attr type): Add dsp32shiftimm.
(define_attr addrtype): Allow load/store register to be
P register.
(define_attr storereg): New.
(define_cpu_unit anomaly_05000074): New.
(define_insn_reservation dsp32shiftimm): New.
(define_insn_reservation dsp32shiftimm_anomaly_05000074): New.
(define_insn_reservation loadp): Cannot use slot2.
(define_insn_reservation loadsp): Cannot use slot2.
(define_insn_reservation storep): Cannot use slot2. Does not
apply when working around 05000074.
(define_insn_reservation storep_anomaly_05000074): New.
(define_insn_reservation storei): Does not apply when working
around 05000074.
(define_insn_reservation storei_anomaly_05000074): New.
(define_attr length): Add dsp32shiftimm case.
(define_insn movsi_insn32, movsi_insv, ashlsi3_insn, ashrsi3,
ror_one, rol_one, lshrsi3, lshrpdi3, ashrpdi3, movhiv2hi_low,
movhiv2hi_high, composev2hi, packv2hi, movv2hi_hi,
ssashiftv2hi3, ssashifthi3, ssashiftsi3, lshiftv2hi3, lshifthi3):
Set type as dsp32shiftimm for dsp32shiftimm alternatives.
From-SVN: r151490
2009-09-07 23:40:23 +02:00
|
|
|
|
[(set_attr "type" "dsp32shiftimm")])
|
2007-04-12 15:03:17 +02:00
|
|
|
|
|
|
|
|
|
(define_insn "ashrpdi3"
|
|
|
|
|
[(set (match_operand:PDI 0 "register_operand" "=e")
|
|
|
|
|
(ashiftrt:PDI (match_operand:PDI 1 "register_operand" "0")
|
|
|
|
|
(match_operand:SI 2 "nonmemory_operand" "Ku5")))]
|
|
|
|
|
""
|
|
|
|
|
"%0 = %1 >>> %2%!"
|
From Jie Zhang <jie.zhang@analog.com>:
* config/bfin/predicates.md (p_register_operand): New
predicate.
(dp_register_operand): New predicate.
* config/bfin/bfin-protos.h (WA_05000074): Define.
(ENABLE_WA_05000074): Define.
* config/bfin/bfin.c (bfin_cpus[]): Add WA_05000074 for
all cpus.
(bfin_gen_bundles): Put dsp32shiftimm instruction in slot[0].
* config/bfin/bfin.md (define_attr type): Add dsp32shiftimm.
(define_attr addrtype): Allow load/store register to be
P register.
(define_attr storereg): New.
(define_cpu_unit anomaly_05000074): New.
(define_insn_reservation dsp32shiftimm): New.
(define_insn_reservation dsp32shiftimm_anomaly_05000074): New.
(define_insn_reservation loadp): Cannot use slot2.
(define_insn_reservation loadsp): Cannot use slot2.
(define_insn_reservation storep): Cannot use slot2. Does not
apply when working around 05000074.
(define_insn_reservation storep_anomaly_05000074): New.
(define_insn_reservation storei): Does not apply when working
around 05000074.
(define_insn_reservation storei_anomaly_05000074): New.
(define_attr length): Add dsp32shiftimm case.
(define_insn movsi_insn32, movsi_insv, ashlsi3_insn, ashrsi3,
ror_one, rol_one, lshrsi3, lshrpdi3, ashrpdi3, movhiv2hi_low,
movhiv2hi_high, composev2hi, packv2hi, movv2hi_hi,
ssashiftv2hi3, ssashifthi3, ssashiftsi3, lshiftv2hi3, lshifthi3):
Set type as dsp32shiftimm for dsp32shiftimm alternatives.
From-SVN: r151490
2009-09-07 23:40:23 +02:00
|
|
|
|
[(set_attr "type" "dsp32shiftimm")])
|
2007-04-12 15:03:17 +02:00
|
|
|
|
|
2005-04-05 13:26:48 +02:00
|
|
|
|
;; A pattern to reload the equivalent of
|
|
|
|
|
;; (set (Dreg) (plus (FP) (large_constant)))
|
|
|
|
|
;; or
|
|
|
|
|
;; (set (dagreg) (plus (FP) (arbitrary_constant)))
|
|
|
|
|
;; using a scratch register
|
|
|
|
|
(define_expand "reload_insi"
|
|
|
|
|
[(parallel [(set (match_operand:SI 0 "register_operand" "=w")
|
|
|
|
|
(match_operand:SI 1 "fp_plus_const_operand" ""))
|
|
|
|
|
(clobber (match_operand:SI 2 "register_operand" "=&a"))])]
|
|
|
|
|
""
|
|
|
|
|
{
|
|
|
|
|
rtx fp_op = XEXP (operands[1], 0);
|
|
|
|
|
rtx const_op = XEXP (operands[1], 1);
|
|
|
|
|
rtx primary = operands[0];
|
|
|
|
|
rtx scratch = operands[2];
|
|
|
|
|
|
|
|
|
|
emit_move_insn (scratch, const_op);
|
|
|
|
|
emit_insn (gen_addsi3 (scratch, scratch, fp_op));
|
|
|
|
|
emit_move_insn (primary, scratch);
|
|
|
|
|
DONE;
|
|
|
|
|
})
|
|
|
|
|
|
2009-09-14 15:05:02 +02:00
|
|
|
|
(define_mode_iterator AREG [PDI V2PDI])
|
|
|
|
|
|
|
|
|
|
(define_insn "reload_in<mode>"
|
|
|
|
|
[(set (match_operand:AREG 0 "register_operand" "=e")
|
|
|
|
|
(match_operand:AREG 1 "memory_operand" "m"))
|
2007-09-13 19:16:29 +02:00
|
|
|
|
(clobber (match_operand:SI 2 "register_operand" "=d"))]
|
|
|
|
|
""
|
|
|
|
|
{
|
|
|
|
|
rtx xops[4];
|
|
|
|
|
xops[0] = operands[0];
|
|
|
|
|
xops[1] = operands[2];
|
|
|
|
|
split_di (operands + 1, 1, xops + 2, xops + 3);
|
|
|
|
|
output_asm_insn ("%1 = %2;", xops);
|
|
|
|
|
output_asm_insn ("%w0 = %1;", xops);
|
|
|
|
|
output_asm_insn ("%1 = %3;", xops);
|
|
|
|
|
output_asm_insn ("%x0 = %1;", xops);
|
|
|
|
|
return "";
|
|
|
|
|
}
|
|
|
|
|
[(set_attr "seq_insns" "multi")
|
|
|
|
|
(set_attr "type" "mcld")
|
|
|
|
|
(set_attr "length" "12")])
|
|
|
|
|
|
2009-09-14 15:05:02 +02:00
|
|
|
|
(define_insn "reload_out<mode>"
|
|
|
|
|
[(set (match_operand:AREG 0 "memory_operand" "=m")
|
|
|
|
|
(match_operand:AREG 1 "register_operand" "e"))
|
2007-09-13 19:16:29 +02:00
|
|
|
|
(clobber (match_operand:SI 2 "register_operand" "=d"))]
|
|
|
|
|
""
|
|
|
|
|
{
|
|
|
|
|
rtx xops[4];
|
|
|
|
|
xops[0] = operands[1];
|
|
|
|
|
xops[1] = operands[2];
|
|
|
|
|
split_di (operands, 1, xops + 2, xops + 3);
|
|
|
|
|
output_asm_insn ("%1 = %w0;", xops);
|
|
|
|
|
output_asm_insn ("%2 = %1;", xops);
|
|
|
|
|
output_asm_insn ("%1 = %x0;", xops);
|
|
|
|
|
output_asm_insn ("%3 = %1;", xops);
|
|
|
|
|
return "";
|
|
|
|
|
}
|
|
|
|
|
[(set_attr "seq_insns" "multi")
|
|
|
|
|
(set_attr "type" "mcld")
|
|
|
|
|
(set_attr "length" "12")])
|
|
|
|
|
|
2005-04-05 13:26:48 +02:00
|
|
|
|
;; Jump instructions
|
|
|
|
|
|
|
|
|
|
(define_insn "jump"
|
|
|
|
|
[(set (pc)
|
|
|
|
|
(label_ref (match_operand 0 "" "")))]
|
|
|
|
|
""
|
|
|
|
|
{
|
|
|
|
|
if (get_attr_length (insn) == 2)
|
|
|
|
|
return "jump.s %0;";
|
|
|
|
|
else
|
|
|
|
|
return "jump.l %0;";
|
|
|
|
|
}
|
|
|
|
|
[(set_attr "type" "br")])
|
|
|
|
|
|
|
|
|
|
(define_insn "indirect_jump"
|
|
|
|
|
[(set (pc)
|
|
|
|
|
(match_operand:SI 0 "register_operand" "a"))]
|
|
|
|
|
""
|
|
|
|
|
"jump (%0);"
|
|
|
|
|
[(set_attr "type" "misc")])
|
|
|
|
|
|
|
|
|
|
(define_expand "tablejump"
|
|
|
|
|
[(parallel [(set (pc) (match_operand:SI 0 "register_operand" "a"))
|
|
|
|
|
(use (label_ref (match_operand 1 "" "")))])]
|
|
|
|
|
""
|
|
|
|
|
{
|
|
|
|
|
/* In PIC mode, the table entries are stored PC relative.
|
|
|
|
|
Convert the relative address to an absolute address. */
|
|
|
|
|
if (flag_pic)
|
|
|
|
|
{
|
|
|
|
|
rtx op1 = gen_rtx_LABEL_REF (Pmode, operands[1]);
|
|
|
|
|
|
|
|
|
|
operands[0] = expand_simple_binop (Pmode, PLUS, operands[0],
|
|
|
|
|
op1, NULL_RTX, 0, OPTAB_DIRECT);
|
|
|
|
|
}
|
|
|
|
|
})
|
|
|
|
|
|
|
|
|
|
(define_insn "*tablejump_internal"
|
|
|
|
|
[(set (pc) (match_operand:SI 0 "register_operand" "a"))
|
|
|
|
|
(use (label_ref (match_operand 1 "" "")))]
|
|
|
|
|
""
|
|
|
|
|
"jump (%0);"
|
|
|
|
|
[(set_attr "type" "misc")])
|
|
|
|
|
|
bfin-protos.h (bfin_hardware_loop): Declare.
* config/bfin/bfin-protos.h (bfin_hardware_loop): Declare.
* config/bfin/bfin.c (basic-block.h): Include.
(struct machine_function): New.
(bfin_init_machine_status): New.
(override_options): Initialize init_machine_status.
(bfin_hardware_loop): New.
(MAX_LOOP_DEPTH, MAX_LOOP_LENGTH): Define.
(DEF_VEC_P (loop_info)): New.
(DEF_VEC_ALLOC_P (loop_info,heap)): New.
(struct loop_info): New.
(loop_info): New typedef.
(struct loop_work): New.
(loop_work): New typedef.
(DEF_VEC_O (loop_work)): New.
(DEF_VEC_ALLOC_O (loop_work,heap)): New.
(bfin_dump_loops): New.
(bfin_bb_in_loop): New.
(bfin_scan_loop): New.
(bfin_optimize_loop): New.
(bfin_reorg_loops): New.
(bfin_reorg): Use bfin_reorg_loops.
* config/bfin/bfin.h (FIRST_PSEUDO_REGISTER): Adjust for adding
loop registers.
(I_REGNO_P): Simplify.
(DP_REGNO_P, DPREG_P): New macros.
(REGISTER_NAMES, FIXED_REGISTERS, CALL_USED_REGISTERS,
REG_ALLOC_ORDER): Add LT0, LT1, LC0, LC1, LB0, LB1.
(enum reg_class, REG_CLASS_NAMES, REG_CLASS_CONTENTS):
Add LT_REGS, LC_REGS, LB_REGS.
(REG_CLASS_FROM_LETTER): Add 't' for LT_REGS, 'k' for LC_REGS,
'l' for LB_REGS.
(REGNO_REG_CLASS): Deal with loop registers.
* config/bfin/bfin.md: Add comment for 't', 'k', 'l' constraint
letters.
(REG_LT0, REG_LT1, REG_LC0, REG_LC1, REG_LB0, REG_LB1):
New constants for loop registers.
(UNSPEC_LSETUP_END): New.
(seq_insns): New define_attr. Set it for appropriate insns.
(movsi_insn): Add alternatives for move from/to
loop count registers.
(doloop_end): New define_expand.
(loop_end): New define_insn.
(define_split for bad doloop_end): New.
(lsetup_with_autoinit): New define_insn.
(lsetup_without_autoinit): New define_insn.
(rep_movsi, rep_movhi): Clobber LT1, LC1, LB1.
* config/bfin/predicates.md (lc_register_operand): New.
(lt_register_operand): New.
(lb_register_operand): New.
(nondp_register_operand): New.
(nondp_reg_or_memory_operand): New.
* doc/md.texi: Document Blackfin new 't', 'k', 'l' constraint letters.
From-SVN: r114274
2006-05-31 18:46:15 +02:00
|
|
|
|
;; Hardware loop
|
|
|
|
|
|
|
|
|
|
; operand 0 is the loop count pseudo register
|
2013-11-09 12:42:16 +01:00
|
|
|
|
; operand 1 is the label to jump to at the top of the loop
|
bfin-protos.h (bfin_hardware_loop): Declare.
* config/bfin/bfin-protos.h (bfin_hardware_loop): Declare.
* config/bfin/bfin.c (basic-block.h): Include.
(struct machine_function): New.
(bfin_init_machine_status): New.
(override_options): Initialize init_machine_status.
(bfin_hardware_loop): New.
(MAX_LOOP_DEPTH, MAX_LOOP_LENGTH): Define.
(DEF_VEC_P (loop_info)): New.
(DEF_VEC_ALLOC_P (loop_info,heap)): New.
(struct loop_info): New.
(loop_info): New typedef.
(struct loop_work): New.
(loop_work): New typedef.
(DEF_VEC_O (loop_work)): New.
(DEF_VEC_ALLOC_O (loop_work,heap)): New.
(bfin_dump_loops): New.
(bfin_bb_in_loop): New.
(bfin_scan_loop): New.
(bfin_optimize_loop): New.
(bfin_reorg_loops): New.
(bfin_reorg): Use bfin_reorg_loops.
* config/bfin/bfin.h (FIRST_PSEUDO_REGISTER): Adjust for adding
loop registers.
(I_REGNO_P): Simplify.
(DP_REGNO_P, DPREG_P): New macros.
(REGISTER_NAMES, FIXED_REGISTERS, CALL_USED_REGISTERS,
REG_ALLOC_ORDER): Add LT0, LT1, LC0, LC1, LB0, LB1.
(enum reg_class, REG_CLASS_NAMES, REG_CLASS_CONTENTS):
Add LT_REGS, LC_REGS, LB_REGS.
(REG_CLASS_FROM_LETTER): Add 't' for LT_REGS, 'k' for LC_REGS,
'l' for LB_REGS.
(REGNO_REG_CLASS): Deal with loop registers.
* config/bfin/bfin.md: Add comment for 't', 'k', 'l' constraint
letters.
(REG_LT0, REG_LT1, REG_LC0, REG_LC1, REG_LB0, REG_LB1):
New constants for loop registers.
(UNSPEC_LSETUP_END): New.
(seq_insns): New define_attr. Set it for appropriate insns.
(movsi_insn): Add alternatives for move from/to
loop count registers.
(doloop_end): New define_expand.
(loop_end): New define_insn.
(define_split for bad doloop_end): New.
(lsetup_with_autoinit): New define_insn.
(lsetup_without_autoinit): New define_insn.
(rep_movsi, rep_movhi): Clobber LT1, LC1, LB1.
* config/bfin/predicates.md (lc_register_operand): New.
(lt_register_operand): New.
(lb_register_operand): New.
(nondp_register_operand): New.
(nondp_reg_or_memory_operand): New.
* doc/md.texi: Document Blackfin new 't', 'k', 'l' constraint letters.
From-SVN: r114274
2006-05-31 18:46:15 +02:00
|
|
|
|
(define_expand "doloop_end"
|
|
|
|
|
[(parallel [(set (pc) (if_then_else
|
|
|
|
|
(ne (match_operand:SI 0 "" "")
|
|
|
|
|
(const_int 1))
|
2013-11-09 12:42:16 +01:00
|
|
|
|
(label_ref (match_operand 1 "" ""))
|
bfin-protos.h (bfin_hardware_loop): Declare.
* config/bfin/bfin-protos.h (bfin_hardware_loop): Declare.
* config/bfin/bfin.c (basic-block.h): Include.
(struct machine_function): New.
(bfin_init_machine_status): New.
(override_options): Initialize init_machine_status.
(bfin_hardware_loop): New.
(MAX_LOOP_DEPTH, MAX_LOOP_LENGTH): Define.
(DEF_VEC_P (loop_info)): New.
(DEF_VEC_ALLOC_P (loop_info,heap)): New.
(struct loop_info): New.
(loop_info): New typedef.
(struct loop_work): New.
(loop_work): New typedef.
(DEF_VEC_O (loop_work)): New.
(DEF_VEC_ALLOC_O (loop_work,heap)): New.
(bfin_dump_loops): New.
(bfin_bb_in_loop): New.
(bfin_scan_loop): New.
(bfin_optimize_loop): New.
(bfin_reorg_loops): New.
(bfin_reorg): Use bfin_reorg_loops.
* config/bfin/bfin.h (FIRST_PSEUDO_REGISTER): Adjust for adding
loop registers.
(I_REGNO_P): Simplify.
(DP_REGNO_P, DPREG_P): New macros.
(REGISTER_NAMES, FIXED_REGISTERS, CALL_USED_REGISTERS,
REG_ALLOC_ORDER): Add LT0, LT1, LC0, LC1, LB0, LB1.
(enum reg_class, REG_CLASS_NAMES, REG_CLASS_CONTENTS):
Add LT_REGS, LC_REGS, LB_REGS.
(REG_CLASS_FROM_LETTER): Add 't' for LT_REGS, 'k' for LC_REGS,
'l' for LB_REGS.
(REGNO_REG_CLASS): Deal with loop registers.
* config/bfin/bfin.md: Add comment for 't', 'k', 'l' constraint
letters.
(REG_LT0, REG_LT1, REG_LC0, REG_LC1, REG_LB0, REG_LB1):
New constants for loop registers.
(UNSPEC_LSETUP_END): New.
(seq_insns): New define_attr. Set it for appropriate insns.
(movsi_insn): Add alternatives for move from/to
loop count registers.
(doloop_end): New define_expand.
(loop_end): New define_insn.
(define_split for bad doloop_end): New.
(lsetup_with_autoinit): New define_insn.
(lsetup_without_autoinit): New define_insn.
(rep_movsi, rep_movhi): Clobber LT1, LC1, LB1.
* config/bfin/predicates.md (lc_register_operand): New.
(lt_register_operand): New.
(lb_register_operand): New.
(nondp_register_operand): New.
(nondp_reg_or_memory_operand): New.
* doc/md.texi: Document Blackfin new 't', 'k', 'l' constraint letters.
From-SVN: r114274
2006-05-31 18:46:15 +02:00
|
|
|
|
(pc)))
|
|
|
|
|
(set (match_dup 0)
|
|
|
|
|
(plus:SI (match_dup 0)
|
|
|
|
|
(const_int -1)))
|
|
|
|
|
(unspec [(const_int 0)] UNSPEC_LSETUP_END)
|
Clobber the condition code in the bfin doloop patterns
Per Aldy's excellent, but tough to follow analysis in PR 103226, this patch
fixes the bfin-elf regression.
In simplest terms the doloop patterns on this port may clobber the condition
code register, but they do not expose that until after register allocation.
That would be fine, except that other patterns have exposed CC earlier. As
a result the dataflow, particularly for CC, is incorrect.
This leads the register allocators to assume that a value in CC outside the
loop is still valid inside the loop when in fact, the value has been
clobbered. This is what caused pr80974 to start failing.
With this fix, not only do we fix the pr80974 regression, but we fix ~20
other execution failures in the port. It also reduces test time for the
port from ~90 minutes to ~60 minutes.
PR tree-optimization/103226
gcc/
* config/bfin/bfin.md (doloop pattern, splitter and expander): Clobber
CC.
2021-11-20 17:20:07 +01:00
|
|
|
|
(clobber (match_dup 2))
|
|
|
|
|
(clobber (reg:BI REG_CC))])] ; match_scratch
|
bfin-protos.h (bfin_hardware_loop): Declare.
* config/bfin/bfin-protos.h (bfin_hardware_loop): Declare.
* config/bfin/bfin.c (basic-block.h): Include.
(struct machine_function): New.
(bfin_init_machine_status): New.
(override_options): Initialize init_machine_status.
(bfin_hardware_loop): New.
(MAX_LOOP_DEPTH, MAX_LOOP_LENGTH): Define.
(DEF_VEC_P (loop_info)): New.
(DEF_VEC_ALLOC_P (loop_info,heap)): New.
(struct loop_info): New.
(loop_info): New typedef.
(struct loop_work): New.
(loop_work): New typedef.
(DEF_VEC_O (loop_work)): New.
(DEF_VEC_ALLOC_O (loop_work,heap)): New.
(bfin_dump_loops): New.
(bfin_bb_in_loop): New.
(bfin_scan_loop): New.
(bfin_optimize_loop): New.
(bfin_reorg_loops): New.
(bfin_reorg): Use bfin_reorg_loops.
* config/bfin/bfin.h (FIRST_PSEUDO_REGISTER): Adjust for adding
loop registers.
(I_REGNO_P): Simplify.
(DP_REGNO_P, DPREG_P): New macros.
(REGISTER_NAMES, FIXED_REGISTERS, CALL_USED_REGISTERS,
REG_ALLOC_ORDER): Add LT0, LT1, LC0, LC1, LB0, LB1.
(enum reg_class, REG_CLASS_NAMES, REG_CLASS_CONTENTS):
Add LT_REGS, LC_REGS, LB_REGS.
(REG_CLASS_FROM_LETTER): Add 't' for LT_REGS, 'k' for LC_REGS,
'l' for LB_REGS.
(REGNO_REG_CLASS): Deal with loop registers.
* config/bfin/bfin.md: Add comment for 't', 'k', 'l' constraint
letters.
(REG_LT0, REG_LT1, REG_LC0, REG_LC1, REG_LB0, REG_LB1):
New constants for loop registers.
(UNSPEC_LSETUP_END): New.
(seq_insns): New define_attr. Set it for appropriate insns.
(movsi_insn): Add alternatives for move from/to
loop count registers.
(doloop_end): New define_expand.
(loop_end): New define_insn.
(define_split for bad doloop_end): New.
(lsetup_with_autoinit): New define_insn.
(lsetup_without_autoinit): New define_insn.
(rep_movsi, rep_movhi): Clobber LT1, LC1, LB1.
* config/bfin/predicates.md (lc_register_operand): New.
(lt_register_operand): New.
(lb_register_operand): New.
(nondp_register_operand): New.
(nondp_reg_or_memory_operand): New.
* doc/md.texi: Document Blackfin new 't', 'k', 'l' constraint letters.
From-SVN: r114274
2006-05-31 18:46:15 +02:00
|
|
|
|
""
|
2007-02-23 16:52:27 +01:00
|
|
|
|
{
|
2007-02-27 14:13:26 +01:00
|
|
|
|
/* The loop optimizer doesn't check the predicates... */
|
|
|
|
|
if (GET_MODE (operands[0]) != SImode)
|
|
|
|
|
FAIL;
|
2007-02-23 16:52:27 +01:00
|
|
|
|
bfin_hardware_loop ();
|
2013-11-09 12:42:16 +01:00
|
|
|
|
operands[2] = gen_rtx_SCRATCH (SImode);
|
2007-02-23 16:52:27 +01:00
|
|
|
|
})
|
bfin-protos.h (bfin_hardware_loop): Declare.
* config/bfin/bfin-protos.h (bfin_hardware_loop): Declare.
* config/bfin/bfin.c (basic-block.h): Include.
(struct machine_function): New.
(bfin_init_machine_status): New.
(override_options): Initialize init_machine_status.
(bfin_hardware_loop): New.
(MAX_LOOP_DEPTH, MAX_LOOP_LENGTH): Define.
(DEF_VEC_P (loop_info)): New.
(DEF_VEC_ALLOC_P (loop_info,heap)): New.
(struct loop_info): New.
(loop_info): New typedef.
(struct loop_work): New.
(loop_work): New typedef.
(DEF_VEC_O (loop_work)): New.
(DEF_VEC_ALLOC_O (loop_work,heap)): New.
(bfin_dump_loops): New.
(bfin_bb_in_loop): New.
(bfin_scan_loop): New.
(bfin_optimize_loop): New.
(bfin_reorg_loops): New.
(bfin_reorg): Use bfin_reorg_loops.
* config/bfin/bfin.h (FIRST_PSEUDO_REGISTER): Adjust for adding
loop registers.
(I_REGNO_P): Simplify.
(DP_REGNO_P, DPREG_P): New macros.
(REGISTER_NAMES, FIXED_REGISTERS, CALL_USED_REGISTERS,
REG_ALLOC_ORDER): Add LT0, LT1, LC0, LC1, LB0, LB1.
(enum reg_class, REG_CLASS_NAMES, REG_CLASS_CONTENTS):
Add LT_REGS, LC_REGS, LB_REGS.
(REG_CLASS_FROM_LETTER): Add 't' for LT_REGS, 'k' for LC_REGS,
'l' for LB_REGS.
(REGNO_REG_CLASS): Deal with loop registers.
* config/bfin/bfin.md: Add comment for 't', 'k', 'l' constraint
letters.
(REG_LT0, REG_LT1, REG_LC0, REG_LC1, REG_LB0, REG_LB1):
New constants for loop registers.
(UNSPEC_LSETUP_END): New.
(seq_insns): New define_attr. Set it for appropriate insns.
(movsi_insn): Add alternatives for move from/to
loop count registers.
(doloop_end): New define_expand.
(loop_end): New define_insn.
(define_split for bad doloop_end): New.
(lsetup_with_autoinit): New define_insn.
(lsetup_without_autoinit): New define_insn.
(rep_movsi, rep_movhi): Clobber LT1, LC1, LB1.
* config/bfin/predicates.md (lc_register_operand): New.
(lt_register_operand): New.
(lb_register_operand): New.
(nondp_register_operand): New.
(nondp_reg_or_memory_operand): New.
* doc/md.texi: Document Blackfin new 't', 'k', 'l' constraint letters.
From-SVN: r114274
2006-05-31 18:46:15 +02:00
|
|
|
|
|
|
|
|
|
(define_insn "loop_end"
|
|
|
|
|
[(set (pc)
|
2011-05-02 19:01:01 +02:00
|
|
|
|
(if_then_else (ne (match_operand:SI 2 "nonimmediate_operand" "0,0,0")
|
bfin-protos.h (bfin_hardware_loop): Declare.
* config/bfin/bfin-protos.h (bfin_hardware_loop): Declare.
* config/bfin/bfin.c (basic-block.h): Include.
(struct machine_function): New.
(bfin_init_machine_status): New.
(override_options): Initialize init_machine_status.
(bfin_hardware_loop): New.
(MAX_LOOP_DEPTH, MAX_LOOP_LENGTH): Define.
(DEF_VEC_P (loop_info)): New.
(DEF_VEC_ALLOC_P (loop_info,heap)): New.
(struct loop_info): New.
(loop_info): New typedef.
(struct loop_work): New.
(loop_work): New typedef.
(DEF_VEC_O (loop_work)): New.
(DEF_VEC_ALLOC_O (loop_work,heap)): New.
(bfin_dump_loops): New.
(bfin_bb_in_loop): New.
(bfin_scan_loop): New.
(bfin_optimize_loop): New.
(bfin_reorg_loops): New.
(bfin_reorg): Use bfin_reorg_loops.
* config/bfin/bfin.h (FIRST_PSEUDO_REGISTER): Adjust for adding
loop registers.
(I_REGNO_P): Simplify.
(DP_REGNO_P, DPREG_P): New macros.
(REGISTER_NAMES, FIXED_REGISTERS, CALL_USED_REGISTERS,
REG_ALLOC_ORDER): Add LT0, LT1, LC0, LC1, LB0, LB1.
(enum reg_class, REG_CLASS_NAMES, REG_CLASS_CONTENTS):
Add LT_REGS, LC_REGS, LB_REGS.
(REG_CLASS_FROM_LETTER): Add 't' for LT_REGS, 'k' for LC_REGS,
'l' for LB_REGS.
(REGNO_REG_CLASS): Deal with loop registers.
* config/bfin/bfin.md: Add comment for 't', 'k', 'l' constraint
letters.
(REG_LT0, REG_LT1, REG_LC0, REG_LC1, REG_LB0, REG_LB1):
New constants for loop registers.
(UNSPEC_LSETUP_END): New.
(seq_insns): New define_attr. Set it for appropriate insns.
(movsi_insn): Add alternatives for move from/to
loop count registers.
(doloop_end): New define_expand.
(loop_end): New define_insn.
(define_split for bad doloop_end): New.
(lsetup_with_autoinit): New define_insn.
(lsetup_without_autoinit): New define_insn.
(rep_movsi, rep_movhi): Clobber LT1, LC1, LB1.
* config/bfin/predicates.md (lc_register_operand): New.
(lt_register_operand): New.
(lb_register_operand): New.
(nondp_register_operand): New.
(nondp_reg_or_memory_operand): New.
* doc/md.texi: Document Blackfin new 't', 'k', 'l' constraint letters.
From-SVN: r114274
2006-05-31 18:46:15 +02:00
|
|
|
|
(const_int 1))
|
|
|
|
|
(label_ref (match_operand 1 "" ""))
|
|
|
|
|
(pc)))
|
2011-05-02 19:01:01 +02:00
|
|
|
|
(set (match_operand:SI 0 "nonimmediate_operand" "=a*d,*b*v*f,m")
|
|
|
|
|
(plus (match_dup 2)
|
bfin-protos.h (bfin_hardware_loop): Declare.
* config/bfin/bfin-protos.h (bfin_hardware_loop): Declare.
* config/bfin/bfin.c (basic-block.h): Include.
(struct machine_function): New.
(bfin_init_machine_status): New.
(override_options): Initialize init_machine_status.
(bfin_hardware_loop): New.
(MAX_LOOP_DEPTH, MAX_LOOP_LENGTH): Define.
(DEF_VEC_P (loop_info)): New.
(DEF_VEC_ALLOC_P (loop_info,heap)): New.
(struct loop_info): New.
(loop_info): New typedef.
(struct loop_work): New.
(loop_work): New typedef.
(DEF_VEC_O (loop_work)): New.
(DEF_VEC_ALLOC_O (loop_work,heap)): New.
(bfin_dump_loops): New.
(bfin_bb_in_loop): New.
(bfin_scan_loop): New.
(bfin_optimize_loop): New.
(bfin_reorg_loops): New.
(bfin_reorg): Use bfin_reorg_loops.
* config/bfin/bfin.h (FIRST_PSEUDO_REGISTER): Adjust for adding
loop registers.
(I_REGNO_P): Simplify.
(DP_REGNO_P, DPREG_P): New macros.
(REGISTER_NAMES, FIXED_REGISTERS, CALL_USED_REGISTERS,
REG_ALLOC_ORDER): Add LT0, LT1, LC0, LC1, LB0, LB1.
(enum reg_class, REG_CLASS_NAMES, REG_CLASS_CONTENTS):
Add LT_REGS, LC_REGS, LB_REGS.
(REG_CLASS_FROM_LETTER): Add 't' for LT_REGS, 'k' for LC_REGS,
'l' for LB_REGS.
(REGNO_REG_CLASS): Deal with loop registers.
* config/bfin/bfin.md: Add comment for 't', 'k', 'l' constraint
letters.
(REG_LT0, REG_LT1, REG_LC0, REG_LC1, REG_LB0, REG_LB1):
New constants for loop registers.
(UNSPEC_LSETUP_END): New.
(seq_insns): New define_attr. Set it for appropriate insns.
(movsi_insn): Add alternatives for move from/to
loop count registers.
(doloop_end): New define_expand.
(loop_end): New define_insn.
(define_split for bad doloop_end): New.
(lsetup_with_autoinit): New define_insn.
(lsetup_without_autoinit): New define_insn.
(rep_movsi, rep_movhi): Clobber LT1, LC1, LB1.
* config/bfin/predicates.md (lc_register_operand): New.
(lt_register_operand): New.
(lb_register_operand): New.
(nondp_register_operand): New.
(nondp_reg_or_memory_operand): New.
* doc/md.texi: Document Blackfin new 't', 'k', 'l' constraint letters.
From-SVN: r114274
2006-05-31 18:46:15 +02:00
|
|
|
|
(const_int -1)))
|
|
|
|
|
(unspec [(const_int 0)] UNSPEC_LSETUP_END)
|
Clobber the condition code in the bfin doloop patterns
Per Aldy's excellent, but tough to follow analysis in PR 103226, this patch
fixes the bfin-elf regression.
In simplest terms the doloop patterns on this port may clobber the condition
code register, but they do not expose that until after register allocation.
That would be fine, except that other patterns have exposed CC earlier. As
a result the dataflow, particularly for CC, is incorrect.
This leads the register allocators to assume that a value in CC outside the
loop is still valid inside the loop when in fact, the value has been
clobbered. This is what caused pr80974 to start failing.
With this fix, not only do we fix the pr80974 regression, but we fix ~20
other execution failures in the port. It also reduces test time for the
port from ~90 minutes to ~60 minutes.
PR tree-optimization/103226
gcc/
* config/bfin/bfin.md (doloop pattern, splitter and expander): Clobber
CC.
2021-11-20 17:20:07 +01:00
|
|
|
|
(clobber (match_scratch:SI 3 "=X,&r,&r"))
|
|
|
|
|
(clobber (reg:BI REG_CC))]
|
bfin-protos.h (bfin_hardware_loop): Declare.
* config/bfin/bfin-protos.h (bfin_hardware_loop): Declare.
* config/bfin/bfin.c (basic-block.h): Include.
(struct machine_function): New.
(bfin_init_machine_status): New.
(override_options): Initialize init_machine_status.
(bfin_hardware_loop): New.
(MAX_LOOP_DEPTH, MAX_LOOP_LENGTH): Define.
(DEF_VEC_P (loop_info)): New.
(DEF_VEC_ALLOC_P (loop_info,heap)): New.
(struct loop_info): New.
(loop_info): New typedef.
(struct loop_work): New.
(loop_work): New typedef.
(DEF_VEC_O (loop_work)): New.
(DEF_VEC_ALLOC_O (loop_work,heap)): New.
(bfin_dump_loops): New.
(bfin_bb_in_loop): New.
(bfin_scan_loop): New.
(bfin_optimize_loop): New.
(bfin_reorg_loops): New.
(bfin_reorg): Use bfin_reorg_loops.
* config/bfin/bfin.h (FIRST_PSEUDO_REGISTER): Adjust for adding
loop registers.
(I_REGNO_P): Simplify.
(DP_REGNO_P, DPREG_P): New macros.
(REGISTER_NAMES, FIXED_REGISTERS, CALL_USED_REGISTERS,
REG_ALLOC_ORDER): Add LT0, LT1, LC0, LC1, LB0, LB1.
(enum reg_class, REG_CLASS_NAMES, REG_CLASS_CONTENTS):
Add LT_REGS, LC_REGS, LB_REGS.
(REG_CLASS_FROM_LETTER): Add 't' for LT_REGS, 'k' for LC_REGS,
'l' for LB_REGS.
(REGNO_REG_CLASS): Deal with loop registers.
* config/bfin/bfin.md: Add comment for 't', 'k', 'l' constraint
letters.
(REG_LT0, REG_LT1, REG_LC0, REG_LC1, REG_LB0, REG_LB1):
New constants for loop registers.
(UNSPEC_LSETUP_END): New.
(seq_insns): New define_attr. Set it for appropriate insns.
(movsi_insn): Add alternatives for move from/to
loop count registers.
(doloop_end): New define_expand.
(loop_end): New define_insn.
(define_split for bad doloop_end): New.
(lsetup_with_autoinit): New define_insn.
(lsetup_without_autoinit): New define_insn.
(rep_movsi, rep_movhi): Clobber LT1, LC1, LB1.
* config/bfin/predicates.md (lc_register_operand): New.
(lt_register_operand): New.
(lb_register_operand): New.
(nondp_register_operand): New.
(nondp_reg_or_memory_operand): New.
* doc/md.texi: Document Blackfin new 't', 'k', 'l' constraint letters.
From-SVN: r114274
2006-05-31 18:46:15 +02:00
|
|
|
|
""
|
|
|
|
|
"@
|
|
|
|
|
/* loop end %0 %l1 */
|
|
|
|
|
#
|
|
|
|
|
#"
|
|
|
|
|
[(set_attr "length" "6,10,14")])
|
|
|
|
|
|
|
|
|
|
(define_split
|
|
|
|
|
[(set (pc)
|
2014-09-22 12:23:42 +02:00
|
|
|
|
(if_then_else (ne (match_operand:SI 0 "nondp_reg_or_memory_operand")
|
bfin-protos.h (bfin_hardware_loop): Declare.
* config/bfin/bfin-protos.h (bfin_hardware_loop): Declare.
* config/bfin/bfin.c (basic-block.h): Include.
(struct machine_function): New.
(bfin_init_machine_status): New.
(override_options): Initialize init_machine_status.
(bfin_hardware_loop): New.
(MAX_LOOP_DEPTH, MAX_LOOP_LENGTH): Define.
(DEF_VEC_P (loop_info)): New.
(DEF_VEC_ALLOC_P (loop_info,heap)): New.
(struct loop_info): New.
(loop_info): New typedef.
(struct loop_work): New.
(loop_work): New typedef.
(DEF_VEC_O (loop_work)): New.
(DEF_VEC_ALLOC_O (loop_work,heap)): New.
(bfin_dump_loops): New.
(bfin_bb_in_loop): New.
(bfin_scan_loop): New.
(bfin_optimize_loop): New.
(bfin_reorg_loops): New.
(bfin_reorg): Use bfin_reorg_loops.
* config/bfin/bfin.h (FIRST_PSEUDO_REGISTER): Adjust for adding
loop registers.
(I_REGNO_P): Simplify.
(DP_REGNO_P, DPREG_P): New macros.
(REGISTER_NAMES, FIXED_REGISTERS, CALL_USED_REGISTERS,
REG_ALLOC_ORDER): Add LT0, LT1, LC0, LC1, LB0, LB1.
(enum reg_class, REG_CLASS_NAMES, REG_CLASS_CONTENTS):
Add LT_REGS, LC_REGS, LB_REGS.
(REG_CLASS_FROM_LETTER): Add 't' for LT_REGS, 'k' for LC_REGS,
'l' for LB_REGS.
(REGNO_REG_CLASS): Deal with loop registers.
* config/bfin/bfin.md: Add comment for 't', 'k', 'l' constraint
letters.
(REG_LT0, REG_LT1, REG_LC0, REG_LC1, REG_LB0, REG_LB1):
New constants for loop registers.
(UNSPEC_LSETUP_END): New.
(seq_insns): New define_attr. Set it for appropriate insns.
(movsi_insn): Add alternatives for move from/to
loop count registers.
(doloop_end): New define_expand.
(loop_end): New define_insn.
(define_split for bad doloop_end): New.
(lsetup_with_autoinit): New define_insn.
(lsetup_without_autoinit): New define_insn.
(rep_movsi, rep_movhi): Clobber LT1, LC1, LB1.
* config/bfin/predicates.md (lc_register_operand): New.
(lt_register_operand): New.
(lb_register_operand): New.
(nondp_register_operand): New.
(nondp_reg_or_memory_operand): New.
* doc/md.texi: Document Blackfin new 't', 'k', 'l' constraint letters.
From-SVN: r114274
2006-05-31 18:46:15 +02:00
|
|
|
|
(const_int 1))
|
2014-09-22 12:23:42 +02:00
|
|
|
|
(label_ref (match_operand 1 ""))
|
bfin-protos.h (bfin_hardware_loop): Declare.
* config/bfin/bfin-protos.h (bfin_hardware_loop): Declare.
* config/bfin/bfin.c (basic-block.h): Include.
(struct machine_function): New.
(bfin_init_machine_status): New.
(override_options): Initialize init_machine_status.
(bfin_hardware_loop): New.
(MAX_LOOP_DEPTH, MAX_LOOP_LENGTH): Define.
(DEF_VEC_P (loop_info)): New.
(DEF_VEC_ALLOC_P (loop_info,heap)): New.
(struct loop_info): New.
(loop_info): New typedef.
(struct loop_work): New.
(loop_work): New typedef.
(DEF_VEC_O (loop_work)): New.
(DEF_VEC_ALLOC_O (loop_work,heap)): New.
(bfin_dump_loops): New.
(bfin_bb_in_loop): New.
(bfin_scan_loop): New.
(bfin_optimize_loop): New.
(bfin_reorg_loops): New.
(bfin_reorg): Use bfin_reorg_loops.
* config/bfin/bfin.h (FIRST_PSEUDO_REGISTER): Adjust for adding
loop registers.
(I_REGNO_P): Simplify.
(DP_REGNO_P, DPREG_P): New macros.
(REGISTER_NAMES, FIXED_REGISTERS, CALL_USED_REGISTERS,
REG_ALLOC_ORDER): Add LT0, LT1, LC0, LC1, LB0, LB1.
(enum reg_class, REG_CLASS_NAMES, REG_CLASS_CONTENTS):
Add LT_REGS, LC_REGS, LB_REGS.
(REG_CLASS_FROM_LETTER): Add 't' for LT_REGS, 'k' for LC_REGS,
'l' for LB_REGS.
(REGNO_REG_CLASS): Deal with loop registers.
* config/bfin/bfin.md: Add comment for 't', 'k', 'l' constraint
letters.
(REG_LT0, REG_LT1, REG_LC0, REG_LC1, REG_LB0, REG_LB1):
New constants for loop registers.
(UNSPEC_LSETUP_END): New.
(seq_insns): New define_attr. Set it for appropriate insns.
(movsi_insn): Add alternatives for move from/to
loop count registers.
(doloop_end): New define_expand.
(loop_end): New define_insn.
(define_split for bad doloop_end): New.
(lsetup_with_autoinit): New define_insn.
(lsetup_without_autoinit): New define_insn.
(rep_movsi, rep_movhi): Clobber LT1, LC1, LB1.
* config/bfin/predicates.md (lc_register_operand): New.
(lt_register_operand): New.
(lb_register_operand): New.
(nondp_register_operand): New.
(nondp_reg_or_memory_operand): New.
* doc/md.texi: Document Blackfin new 't', 'k', 'l' constraint letters.
From-SVN: r114274
2006-05-31 18:46:15 +02:00
|
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|
(pc)))
|
|
|
|
|
(set (match_dup 0)
|
|
|
|
|
(plus (match_dup 0)
|
|
|
|
|
(const_int -1)))
|
|
|
|
|
(unspec [(const_int 0)] UNSPEC_LSETUP_END)
|
Clobber the condition code in the bfin doloop patterns
Per Aldy's excellent, but tough to follow analysis in PR 103226, this patch
fixes the bfin-elf regression.
In simplest terms the doloop patterns on this port may clobber the condition
code register, but they do not expose that until after register allocation.
That would be fine, except that other patterns have exposed CC earlier. As
a result the dataflow, particularly for CC, is incorrect.
This leads the register allocators to assume that a value in CC outside the
loop is still valid inside the loop when in fact, the value has been
clobbered. This is what caused pr80974 to start failing.
With this fix, not only do we fix the pr80974 regression, but we fix ~20
other execution failures in the port. It also reduces test time for the
port from ~90 minutes to ~60 minutes.
PR tree-optimization/103226
gcc/
* config/bfin/bfin.md (doloop pattern, splitter and expander): Clobber
CC.
2021-11-20 17:20:07 +01:00
|
|
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(clobber (match_scratch:SI 2))
|
|
|
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|
(clobber (reg:BI REG_CC))]
|
hw-doloop.c: New file.
* hw-doloop.c: New file.
* hw-doloop.h: New file.
* Makefile.in (OBJS): Add hw-doloop.o.
(hw-doloop.o): New rule.
($(obj_out_file)): Add hw-doloop.h dependency.
* config/bfin/bfin.c: Include "hw-doloop.h".
(loop_info, DEF_VEC_P for loop_info, loop_info_d): Remove.
(bfin_dump_loops, bfin_bb_in_loop, bfin_scan_loop): Remove.
(hwloop_optimize): Renamed from bfin_optimize_loop. Argument
type changed to hwloop_info. Return bool, true if the loop was
successfully optimized. Remove code that was moved to
hw-doloop.c, and adjust other parts.
(hwloop_fail): New static function, containing parts that used
to be in bfin_optimize_loop.
(bfin_discover_loop, bfin_discover_loops, free_loops,
bfin_reorder_loops): Remove.
(hwloop_pattern_reg): New static function.
(bfin_doloop_hooks): New variable.
(bfin_reorg_loops): Remove most code, call reorg_loops.
* config/bfin/bfin.md (doloop_end splitter): Also enable if
loop counter is a memory_operand.
From-SVN: r175985
2011-07-07 17:42:41 +02:00
|
|
|
|
"memory_operand (operands[0], SImode) || splitting_loops"
|
bfin-protos.h (bfin_hardware_loop): Declare.
* config/bfin/bfin-protos.h (bfin_hardware_loop): Declare.
* config/bfin/bfin.c (basic-block.h): Include.
(struct machine_function): New.
(bfin_init_machine_status): New.
(override_options): Initialize init_machine_status.
(bfin_hardware_loop): New.
(MAX_LOOP_DEPTH, MAX_LOOP_LENGTH): Define.
(DEF_VEC_P (loop_info)): New.
(DEF_VEC_ALLOC_P (loop_info,heap)): New.
(struct loop_info): New.
(loop_info): New typedef.
(struct loop_work): New.
(loop_work): New typedef.
(DEF_VEC_O (loop_work)): New.
(DEF_VEC_ALLOC_O (loop_work,heap)): New.
(bfin_dump_loops): New.
(bfin_bb_in_loop): New.
(bfin_scan_loop): New.
(bfin_optimize_loop): New.
(bfin_reorg_loops): New.
(bfin_reorg): Use bfin_reorg_loops.
* config/bfin/bfin.h (FIRST_PSEUDO_REGISTER): Adjust for adding
loop registers.
(I_REGNO_P): Simplify.
(DP_REGNO_P, DPREG_P): New macros.
(REGISTER_NAMES, FIXED_REGISTERS, CALL_USED_REGISTERS,
REG_ALLOC_ORDER): Add LT0, LT1, LC0, LC1, LB0, LB1.
(enum reg_class, REG_CLASS_NAMES, REG_CLASS_CONTENTS):
Add LT_REGS, LC_REGS, LB_REGS.
(REG_CLASS_FROM_LETTER): Add 't' for LT_REGS, 'k' for LC_REGS,
'l' for LB_REGS.
(REGNO_REG_CLASS): Deal with loop registers.
* config/bfin/bfin.md: Add comment for 't', 'k', 'l' constraint
letters.
(REG_LT0, REG_LT1, REG_LC0, REG_LC1, REG_LB0, REG_LB1):
New constants for loop registers.
(UNSPEC_LSETUP_END): New.
(seq_insns): New define_attr. Set it for appropriate insns.
(movsi_insn): Add alternatives for move from/to
loop count registers.
(doloop_end): New define_expand.
(loop_end): New define_insn.
(define_split for bad doloop_end): New.
(lsetup_with_autoinit): New define_insn.
(lsetup_without_autoinit): New define_insn.
(rep_movsi, rep_movhi): Clobber LT1, LC1, LB1.
* config/bfin/predicates.md (lc_register_operand): New.
(lt_register_operand): New.
(lb_register_operand): New.
(nondp_register_operand): New.
(nondp_reg_or_memory_operand): New.
* doc/md.texi: Document Blackfin new 't', 'k', 'l' constraint letters.
From-SVN: r114274
2006-05-31 18:46:15 +02:00
|
|
|
|
[(set (match_dup 2) (match_dup 0))
|
|
|
|
|
(set (match_dup 2) (plus:SI (match_dup 2) (const_int -1)))
|
|
|
|
|
(set (match_dup 0) (match_dup 2))
|
|
|
|
|
(set (reg:BI REG_CC) (eq:BI (match_dup 2) (const_int 0)))
|
|
|
|
|
(set (pc)
|
|
|
|
|
(if_then_else (eq (reg:BI REG_CC)
|
|
|
|
|
(const_int 0))
|
|
|
|
|
(label_ref (match_dup 1))
|
|
|
|
|
(pc)))]
|
|
|
|
|
"")
|
|
|
|
|
|
|
|
|
|
(define_insn "lsetup_with_autoinit"
|
|
|
|
|
[(set (match_operand:SI 0 "lt_register_operand" "=t")
|
|
|
|
|
(label_ref (match_operand 1 "" "")))
|
2006-06-18 12:30:23 +02:00
|
|
|
|
(set (match_operand:SI 2 "lb_register_operand" "=u")
|
bfin-protos.h (bfin_hardware_loop): Declare.
* config/bfin/bfin-protos.h (bfin_hardware_loop): Declare.
* config/bfin/bfin.c (basic-block.h): Include.
(struct machine_function): New.
(bfin_init_machine_status): New.
(override_options): Initialize init_machine_status.
(bfin_hardware_loop): New.
(MAX_LOOP_DEPTH, MAX_LOOP_LENGTH): Define.
(DEF_VEC_P (loop_info)): New.
(DEF_VEC_ALLOC_P (loop_info,heap)): New.
(struct loop_info): New.
(loop_info): New typedef.
(struct loop_work): New.
(loop_work): New typedef.
(DEF_VEC_O (loop_work)): New.
(DEF_VEC_ALLOC_O (loop_work,heap)): New.
(bfin_dump_loops): New.
(bfin_bb_in_loop): New.
(bfin_scan_loop): New.
(bfin_optimize_loop): New.
(bfin_reorg_loops): New.
(bfin_reorg): Use bfin_reorg_loops.
* config/bfin/bfin.h (FIRST_PSEUDO_REGISTER): Adjust for adding
loop registers.
(I_REGNO_P): Simplify.
(DP_REGNO_P, DPREG_P): New macros.
(REGISTER_NAMES, FIXED_REGISTERS, CALL_USED_REGISTERS,
REG_ALLOC_ORDER): Add LT0, LT1, LC0, LC1, LB0, LB1.
(enum reg_class, REG_CLASS_NAMES, REG_CLASS_CONTENTS):
Add LT_REGS, LC_REGS, LB_REGS.
(REG_CLASS_FROM_LETTER): Add 't' for LT_REGS, 'k' for LC_REGS,
'l' for LB_REGS.
(REGNO_REG_CLASS): Deal with loop registers.
* config/bfin/bfin.md: Add comment for 't', 'k', 'l' constraint
letters.
(REG_LT0, REG_LT1, REG_LC0, REG_LC1, REG_LB0, REG_LB1):
New constants for loop registers.
(UNSPEC_LSETUP_END): New.
(seq_insns): New define_attr. Set it for appropriate insns.
(movsi_insn): Add alternatives for move from/to
loop count registers.
(doloop_end): New define_expand.
(loop_end): New define_insn.
(define_split for bad doloop_end): New.
(lsetup_with_autoinit): New define_insn.
(lsetup_without_autoinit): New define_insn.
(rep_movsi, rep_movhi): Clobber LT1, LC1, LB1.
* config/bfin/predicates.md (lc_register_operand): New.
(lt_register_operand): New.
(lb_register_operand): New.
(nondp_register_operand): New.
(nondp_reg_or_memory_operand): New.
* doc/md.texi: Document Blackfin new 't', 'k', 'l' constraint letters.
From-SVN: r114274
2006-05-31 18:46:15 +02:00
|
|
|
|
(label_ref (match_operand 3 "" "")))
|
|
|
|
|
(set (match_operand:SI 4 "lc_register_operand" "=k")
|
|
|
|
|
(match_operand:SI 5 "register_operand" "a"))]
|
|
|
|
|
""
|
|
|
|
|
"LSETUP (%1, %3) %4 = %5;"
|
|
|
|
|
[(set_attr "length" "4")])
|
|
|
|
|
|
|
|
|
|
(define_insn "lsetup_without_autoinit"
|
|
|
|
|
[(set (match_operand:SI 0 "lt_register_operand" "=t")
|
|
|
|
|
(label_ref (match_operand 1 "" "")))
|
2006-06-18 12:30:23 +02:00
|
|
|
|
(set (match_operand:SI 2 "lb_register_operand" "=u")
|
bfin-protos.h (bfin_hardware_loop): Declare.
* config/bfin/bfin-protos.h (bfin_hardware_loop): Declare.
* config/bfin/bfin.c (basic-block.h): Include.
(struct machine_function): New.
(bfin_init_machine_status): New.
(override_options): Initialize init_machine_status.
(bfin_hardware_loop): New.
(MAX_LOOP_DEPTH, MAX_LOOP_LENGTH): Define.
(DEF_VEC_P (loop_info)): New.
(DEF_VEC_ALLOC_P (loop_info,heap)): New.
(struct loop_info): New.
(loop_info): New typedef.
(struct loop_work): New.
(loop_work): New typedef.
(DEF_VEC_O (loop_work)): New.
(DEF_VEC_ALLOC_O (loop_work,heap)): New.
(bfin_dump_loops): New.
(bfin_bb_in_loop): New.
(bfin_scan_loop): New.
(bfin_optimize_loop): New.
(bfin_reorg_loops): New.
(bfin_reorg): Use bfin_reorg_loops.
* config/bfin/bfin.h (FIRST_PSEUDO_REGISTER): Adjust for adding
loop registers.
(I_REGNO_P): Simplify.
(DP_REGNO_P, DPREG_P): New macros.
(REGISTER_NAMES, FIXED_REGISTERS, CALL_USED_REGISTERS,
REG_ALLOC_ORDER): Add LT0, LT1, LC0, LC1, LB0, LB1.
(enum reg_class, REG_CLASS_NAMES, REG_CLASS_CONTENTS):
Add LT_REGS, LC_REGS, LB_REGS.
(REG_CLASS_FROM_LETTER): Add 't' for LT_REGS, 'k' for LC_REGS,
'l' for LB_REGS.
(REGNO_REG_CLASS): Deal with loop registers.
* config/bfin/bfin.md: Add comment for 't', 'k', 'l' constraint
letters.
(REG_LT0, REG_LT1, REG_LC0, REG_LC1, REG_LB0, REG_LB1):
New constants for loop registers.
(UNSPEC_LSETUP_END): New.
(seq_insns): New define_attr. Set it for appropriate insns.
(movsi_insn): Add alternatives for move from/to
loop count registers.
(doloop_end): New define_expand.
(loop_end): New define_insn.
(define_split for bad doloop_end): New.
(lsetup_with_autoinit): New define_insn.
(lsetup_without_autoinit): New define_insn.
(rep_movsi, rep_movhi): Clobber LT1, LC1, LB1.
* config/bfin/predicates.md (lc_register_operand): New.
(lt_register_operand): New.
(lb_register_operand): New.
(nondp_register_operand): New.
(nondp_reg_or_memory_operand): New.
* doc/md.texi: Document Blackfin new 't', 'k', 'l' constraint letters.
From-SVN: r114274
2006-05-31 18:46:15 +02:00
|
|
|
|
(label_ref (match_operand 3 "" "")))
|
|
|
|
|
(use (match_operand:SI 4 "lc_register_operand" "k"))]
|
|
|
|
|
""
|
|
|
|
|
"LSETUP (%1, %3) %4;"
|
|
|
|
|
[(set_attr "length" "4")])
|
|
|
|
|
|
2005-04-05 13:26:48 +02:00
|
|
|
|
;; Call instructions..
|
|
|
|
|
|
bfin.opt (mfdpic): New option.
* config/bfin/bfin.opt (mfdpic): New option.
* config/bfin/t-bfin-elf (EXTRA_PARTS): Add crtbeginS.o and crtendS.o.
(EXTRA_MULTILIB_PARTS): Likewise.
(CRTSTUFF_T_CFLAGS, TARGET_LIBGCC2_CFLAGS): Use -fpic.
(MULTILIB_OPTIONS, MULTILIB_EXCEPTIONS): Build one extra -mfdpic
multilib.
* config/bfin/elf.h (STARTFILE_SPEC): Don't link in crt0.o if -shared.
(CRT_CALL_STATIC_FUNCTION): New.
* config/bfin/uclinux.h (STARTFILE_SPEC): Don't link in crt0.o if
-shared.
(CRT_CALL_STATIC_FUNCTION): New.
* config/bfin/bfin.c (legitimize_pic_address): Now static. Handle
FD-PIC moves.
(n_pregs_to_save): PIC register doesn't need to be saved with FD-PIC.
(print_operand): Handle UNSPEC_MOVE_FDPIC and UNSPEC_FUNCDESC_GOT17M4.
(initialize_trampoline): Changed to handle FD-PIC code generation.
(expand_move): If TARGET_FDPIC, use emit_pic_move as needed.
(bfin_expand_call): Generate FD-PIC calls if TARGET_FDPIC.
(override_options): Disallow -mid-shared-library -mfdpic combination.
Can't do unaligned ops if FD-PIC.
Turn off flag_pic if trying to generate non-id-shared-library
non-fdpic code, since it's not supported.
(bfin_assemble_integer): New function.
(TARGET_ASM_INTEGER): Define.
* config/bfin/crti.s (__init, __fini): Save P3 on the stack if
__BFIN_FDPIC__.
* config/bfin/crtn.s: Restore them.
* config/bfin/bfin.h (TARGET_CPU_CPP_BUILTINS): Define __BFIN_FDPIC__
if TARGET_FDPIC.
(DRIVER_SELF_SPECS, SUBTARGET_DRIVER_SELF_SPECS,
LINK_GCC_C_SEQUENCE_SPEC, ASM_SPEC, LINK_SPEC): New macros.
(FDPIC_FPTR_REGNO, FDPIC_REGNO, OUR_FDPIC_REG): New macros.
(TRAMPOLINE_SIZE, TRAMPOLINE_TEMPLATE): Adjust for FD-PIC.
(CONDITIONAL_REGISTER_USAGE): If TARGET_FDPIC, FDPIC_REGNO is
call-used.
(enum reg_class, REG_CLASS_CONTENTS, REG_CLASS_NAMES): Add
FDPIC_REGS and FDPIC_FPTR_REGS.
(REG_CLASS_FROM_LETTER): Use 'Z' and 'Y' for them.
* config/bfin/bfin.md (UNSPEC_MOVE_FDPIC, UNSPEC_FUNCDESC_GOT17M4,
UNSPEC_VOLATILE_LOAD_FUNCDESC): New constants.
(load_funcdescsi): New pattern.
(call_symbol_fdpic, sibcall_symbol_fdpic, call_value_symbol_fdpic,
sibcall_value_symbol_fdpic, call_insn_fdpic, sibcall_insn_fdpic,
call_value_insn_fdpic, sibcall_value_insn_fdpic): New patterns.
From-SVN: r114199
2006-05-29 16:11:07 +02:00
|
|
|
|
;; The explicit MEM inside the UNSPEC prevents the compiler from moving
|
|
|
|
|
;; the load before a branch after a NULL test, or before a store that
|
|
|
|
|
;; initializes a function descriptor.
|
|
|
|
|
|
|
|
|
|
(define_insn_and_split "load_funcdescsi"
|
|
|
|
|
[(set (match_operand:SI 0 "register_operand" "=a")
|
|
|
|
|
(unspec_volatile:SI [(mem:SI (match_operand:SI 1 "address_operand" "p"))]
|
|
|
|
|
UNSPEC_VOLATILE_LOAD_FUNCDESC))]
|
|
|
|
|
""
|
|
|
|
|
"#"
|
|
|
|
|
"reload_completed"
|
|
|
|
|
[(set (match_dup 0) (mem:SI (match_dup 1)))])
|
|
|
|
|
|
2005-04-05 13:26:48 +02:00
|
|
|
|
(define_expand "call"
|
bfin-protos.h (bfin_longcall_p): Declare.
* config/bfin/bfin-protos.h (bfin_longcall_p): Declare.
* config/bfin/predicates.md (symbol_ref_operand): New.
(call_insn_operand): Delete. All callers changed to use
register_no_elim_operand.
* config/bfin/bfin.c (init_cumulative_args): Initialize the new
call_cookie field.
(function_arg): Use it to generate the call's operand 2.
(bfin_longcall_p): New function.
(bfin_expand_call): Extra arg "cookie". All callers and declaration
changed. Emit extra USE in the pattern. Use bfin_longcall_p to
determine if the address needs to be in a REG.
(bfin_handle_longcall_attribute): New function.
(bfin_attribute_table): Add "longcall" and "shortcall".
* config/bfin/bfin.h (CALL_NORMAL, CALL_LONG, CALL_SHORT): New macros.
(CUMULATIVE_ARGS): New member call_cookie.
(PREDICATE_CODES): Add symbol_ref_operand.
* config/bfin/bfin.md (call, call_value, sibcall, sibcall_value): Add
extra USE to the pattern.
(call_symbol, sibcall_symbol, call_value_symbol, sibcall_value_symbol):
New patterns, split off call_insn, sibcall_insn, call_value_insn and
sibcall_value_insn; now the new patterns handle direct calls and the
old ones indirect calls.
* doc/extend.texi: Mention Blackfin in longcall/shortcall docs.
From-SVN: r102191
2005-07-20 11:48:03 +02:00
|
|
|
|
[(parallel [(call (match_operand:SI 0 "" "")
|
|
|
|
|
(match_operand 1 "" ""))
|
|
|
|
|
(use (match_operand 2 "" ""))])]
|
2005-04-05 13:26:48 +02:00
|
|
|
|
""
|
bfin-protos.h (bfin_longcall_p): Declare.
* config/bfin/bfin-protos.h (bfin_longcall_p): Declare.
* config/bfin/predicates.md (symbol_ref_operand): New.
(call_insn_operand): Delete. All callers changed to use
register_no_elim_operand.
* config/bfin/bfin.c (init_cumulative_args): Initialize the new
call_cookie field.
(function_arg): Use it to generate the call's operand 2.
(bfin_longcall_p): New function.
(bfin_expand_call): Extra arg "cookie". All callers and declaration
changed. Emit extra USE in the pattern. Use bfin_longcall_p to
determine if the address needs to be in a REG.
(bfin_handle_longcall_attribute): New function.
(bfin_attribute_table): Add "longcall" and "shortcall".
* config/bfin/bfin.h (CALL_NORMAL, CALL_LONG, CALL_SHORT): New macros.
(CUMULATIVE_ARGS): New member call_cookie.
(PREDICATE_CODES): Add symbol_ref_operand.
* config/bfin/bfin.md (call, call_value, sibcall, sibcall_value): Add
extra USE to the pattern.
(call_symbol, sibcall_symbol, call_value_symbol, sibcall_value_symbol):
New patterns, split off call_insn, sibcall_insn, call_value_insn and
sibcall_value_insn; now the new patterns handle direct calls and the
old ones indirect calls.
* doc/extend.texi: Mention Blackfin in longcall/shortcall docs.
From-SVN: r102191
2005-07-20 11:48:03 +02:00
|
|
|
|
{
|
|
|
|
|
bfin_expand_call (NULL_RTX, operands[0], operands[1], operands[2], 0);
|
|
|
|
|
DONE;
|
|
|
|
|
})
|
2005-04-05 13:26:48 +02:00
|
|
|
|
|
|
|
|
|
(define_expand "sibcall"
|
|
|
|
|
[(parallel [(call (match_operand:SI 0 "" "")
|
|
|
|
|
(match_operand 1 "" ""))
|
bfin-protos.h (bfin_longcall_p): Declare.
* config/bfin/bfin-protos.h (bfin_longcall_p): Declare.
* config/bfin/predicates.md (symbol_ref_operand): New.
(call_insn_operand): Delete. All callers changed to use
register_no_elim_operand.
* config/bfin/bfin.c (init_cumulative_args): Initialize the new
call_cookie field.
(function_arg): Use it to generate the call's operand 2.
(bfin_longcall_p): New function.
(bfin_expand_call): Extra arg "cookie". All callers and declaration
changed. Emit extra USE in the pattern. Use bfin_longcall_p to
determine if the address needs to be in a REG.
(bfin_handle_longcall_attribute): New function.
(bfin_attribute_table): Add "longcall" and "shortcall".
* config/bfin/bfin.h (CALL_NORMAL, CALL_LONG, CALL_SHORT): New macros.
(CUMULATIVE_ARGS): New member call_cookie.
(PREDICATE_CODES): Add symbol_ref_operand.
* config/bfin/bfin.md (call, call_value, sibcall, sibcall_value): Add
extra USE to the pattern.
(call_symbol, sibcall_symbol, call_value_symbol, sibcall_value_symbol):
New patterns, split off call_insn, sibcall_insn, call_value_insn and
sibcall_value_insn; now the new patterns handle direct calls and the
old ones indirect calls.
* doc/extend.texi: Mention Blackfin in longcall/shortcall docs.
From-SVN: r102191
2005-07-20 11:48:03 +02:00
|
|
|
|
(use (match_operand 2 "" ""))
|
2005-04-05 13:26:48 +02:00
|
|
|
|
(return)])]
|
|
|
|
|
""
|
bfin-protos.h (bfin_longcall_p): Declare.
* config/bfin/bfin-protos.h (bfin_longcall_p): Declare.
* config/bfin/predicates.md (symbol_ref_operand): New.
(call_insn_operand): Delete. All callers changed to use
register_no_elim_operand.
* config/bfin/bfin.c (init_cumulative_args): Initialize the new
call_cookie field.
(function_arg): Use it to generate the call's operand 2.
(bfin_longcall_p): New function.
(bfin_expand_call): Extra arg "cookie". All callers and declaration
changed. Emit extra USE in the pattern. Use bfin_longcall_p to
determine if the address needs to be in a REG.
(bfin_handle_longcall_attribute): New function.
(bfin_attribute_table): Add "longcall" and "shortcall".
* config/bfin/bfin.h (CALL_NORMAL, CALL_LONG, CALL_SHORT): New macros.
(CUMULATIVE_ARGS): New member call_cookie.
(PREDICATE_CODES): Add symbol_ref_operand.
* config/bfin/bfin.md (call, call_value, sibcall, sibcall_value): Add
extra USE to the pattern.
(call_symbol, sibcall_symbol, call_value_symbol, sibcall_value_symbol):
New patterns, split off call_insn, sibcall_insn, call_value_insn and
sibcall_value_insn; now the new patterns handle direct calls and the
old ones indirect calls.
* doc/extend.texi: Mention Blackfin in longcall/shortcall docs.
From-SVN: r102191
2005-07-20 11:48:03 +02:00
|
|
|
|
{
|
|
|
|
|
bfin_expand_call (NULL_RTX, operands[0], operands[1], operands[2], 1);
|
|
|
|
|
DONE;
|
|
|
|
|
})
|
2005-04-05 13:26:48 +02:00
|
|
|
|
|
|
|
|
|
(define_expand "call_value"
|
bfin-protos.h (bfin_longcall_p): Declare.
* config/bfin/bfin-protos.h (bfin_longcall_p): Declare.
* config/bfin/predicates.md (symbol_ref_operand): New.
(call_insn_operand): Delete. All callers changed to use
register_no_elim_operand.
* config/bfin/bfin.c (init_cumulative_args): Initialize the new
call_cookie field.
(function_arg): Use it to generate the call's operand 2.
(bfin_longcall_p): New function.
(bfin_expand_call): Extra arg "cookie". All callers and declaration
changed. Emit extra USE in the pattern. Use bfin_longcall_p to
determine if the address needs to be in a REG.
(bfin_handle_longcall_attribute): New function.
(bfin_attribute_table): Add "longcall" and "shortcall".
* config/bfin/bfin.h (CALL_NORMAL, CALL_LONG, CALL_SHORT): New macros.
(CUMULATIVE_ARGS): New member call_cookie.
(PREDICATE_CODES): Add symbol_ref_operand.
* config/bfin/bfin.md (call, call_value, sibcall, sibcall_value): Add
extra USE to the pattern.
(call_symbol, sibcall_symbol, call_value_symbol, sibcall_value_symbol):
New patterns, split off call_insn, sibcall_insn, call_value_insn and
sibcall_value_insn; now the new patterns handle direct calls and the
old ones indirect calls.
* doc/extend.texi: Mention Blackfin in longcall/shortcall docs.
From-SVN: r102191
2005-07-20 11:48:03 +02:00
|
|
|
|
[(parallel [(set (match_operand 0 "register_operand" "")
|
|
|
|
|
(call (match_operand:SI 1 "" "")
|
|
|
|
|
(match_operand 2 "" "")))
|
|
|
|
|
(use (match_operand 3 "" ""))])]
|
2005-04-05 13:26:48 +02:00
|
|
|
|
""
|
bfin-protos.h (bfin_longcall_p): Declare.
* config/bfin/bfin-protos.h (bfin_longcall_p): Declare.
* config/bfin/predicates.md (symbol_ref_operand): New.
(call_insn_operand): Delete. All callers changed to use
register_no_elim_operand.
* config/bfin/bfin.c (init_cumulative_args): Initialize the new
call_cookie field.
(function_arg): Use it to generate the call's operand 2.
(bfin_longcall_p): New function.
(bfin_expand_call): Extra arg "cookie". All callers and declaration
changed. Emit extra USE in the pattern. Use bfin_longcall_p to
determine if the address needs to be in a REG.
(bfin_handle_longcall_attribute): New function.
(bfin_attribute_table): Add "longcall" and "shortcall".
* config/bfin/bfin.h (CALL_NORMAL, CALL_LONG, CALL_SHORT): New macros.
(CUMULATIVE_ARGS): New member call_cookie.
(PREDICATE_CODES): Add symbol_ref_operand.
* config/bfin/bfin.md (call, call_value, sibcall, sibcall_value): Add
extra USE to the pattern.
(call_symbol, sibcall_symbol, call_value_symbol, sibcall_value_symbol):
New patterns, split off call_insn, sibcall_insn, call_value_insn and
sibcall_value_insn; now the new patterns handle direct calls and the
old ones indirect calls.
* doc/extend.texi: Mention Blackfin in longcall/shortcall docs.
From-SVN: r102191
2005-07-20 11:48:03 +02:00
|
|
|
|
{
|
|
|
|
|
bfin_expand_call (operands[0], operands[1], operands[2], operands[3], 0);
|
|
|
|
|
DONE;
|
|
|
|
|
})
|
2005-04-05 13:26:48 +02:00
|
|
|
|
|
|
|
|
|
(define_expand "sibcall_value"
|
|
|
|
|
[(parallel [(set (match_operand 0 "register_operand" "")
|
|
|
|
|
(call (match_operand:SI 1 "" "")
|
|
|
|
|
(match_operand 2 "" "")))
|
bfin-protos.h (bfin_longcall_p): Declare.
* config/bfin/bfin-protos.h (bfin_longcall_p): Declare.
* config/bfin/predicates.md (symbol_ref_operand): New.
(call_insn_operand): Delete. All callers changed to use
register_no_elim_operand.
* config/bfin/bfin.c (init_cumulative_args): Initialize the new
call_cookie field.
(function_arg): Use it to generate the call's operand 2.
(bfin_longcall_p): New function.
(bfin_expand_call): Extra arg "cookie". All callers and declaration
changed. Emit extra USE in the pattern. Use bfin_longcall_p to
determine if the address needs to be in a REG.
(bfin_handle_longcall_attribute): New function.
(bfin_attribute_table): Add "longcall" and "shortcall".
* config/bfin/bfin.h (CALL_NORMAL, CALL_LONG, CALL_SHORT): New macros.
(CUMULATIVE_ARGS): New member call_cookie.
(PREDICATE_CODES): Add symbol_ref_operand.
* config/bfin/bfin.md (call, call_value, sibcall, sibcall_value): Add
extra USE to the pattern.
(call_symbol, sibcall_symbol, call_value_symbol, sibcall_value_symbol):
New patterns, split off call_insn, sibcall_insn, call_value_insn and
sibcall_value_insn; now the new patterns handle direct calls and the
old ones indirect calls.
* doc/extend.texi: Mention Blackfin in longcall/shortcall docs.
From-SVN: r102191
2005-07-20 11:48:03 +02:00
|
|
|
|
(use (match_operand 3 "" ""))
|
2005-04-05 13:26:48 +02:00
|
|
|
|
(return)])]
|
|
|
|
|
""
|
bfin-protos.h (bfin_longcall_p): Declare.
* config/bfin/bfin-protos.h (bfin_longcall_p): Declare.
* config/bfin/predicates.md (symbol_ref_operand): New.
(call_insn_operand): Delete. All callers changed to use
register_no_elim_operand.
* config/bfin/bfin.c (init_cumulative_args): Initialize the new
call_cookie field.
(function_arg): Use it to generate the call's operand 2.
(bfin_longcall_p): New function.
(bfin_expand_call): Extra arg "cookie". All callers and declaration
changed. Emit extra USE in the pattern. Use bfin_longcall_p to
determine if the address needs to be in a REG.
(bfin_handle_longcall_attribute): New function.
(bfin_attribute_table): Add "longcall" and "shortcall".
* config/bfin/bfin.h (CALL_NORMAL, CALL_LONG, CALL_SHORT): New macros.
(CUMULATIVE_ARGS): New member call_cookie.
(PREDICATE_CODES): Add symbol_ref_operand.
* config/bfin/bfin.md (call, call_value, sibcall, sibcall_value): Add
extra USE to the pattern.
(call_symbol, sibcall_symbol, call_value_symbol, sibcall_value_symbol):
New patterns, split off call_insn, sibcall_insn, call_value_insn and
sibcall_value_insn; now the new patterns handle direct calls and the
old ones indirect calls.
* doc/extend.texi: Mention Blackfin in longcall/shortcall docs.
From-SVN: r102191
2005-07-20 11:48:03 +02:00
|
|
|
|
{
|
|
|
|
|
bfin_expand_call (operands[0], operands[1], operands[2], operands[3], 1);
|
|
|
|
|
DONE;
|
|
|
|
|
})
|
2005-04-05 13:26:48 +02:00
|
|
|
|
|
bfin.opt (mfdpic): New option.
* config/bfin/bfin.opt (mfdpic): New option.
* config/bfin/t-bfin-elf (EXTRA_PARTS): Add crtbeginS.o and crtendS.o.
(EXTRA_MULTILIB_PARTS): Likewise.
(CRTSTUFF_T_CFLAGS, TARGET_LIBGCC2_CFLAGS): Use -fpic.
(MULTILIB_OPTIONS, MULTILIB_EXCEPTIONS): Build one extra -mfdpic
multilib.
* config/bfin/elf.h (STARTFILE_SPEC): Don't link in crt0.o if -shared.
(CRT_CALL_STATIC_FUNCTION): New.
* config/bfin/uclinux.h (STARTFILE_SPEC): Don't link in crt0.o if
-shared.
(CRT_CALL_STATIC_FUNCTION): New.
* config/bfin/bfin.c (legitimize_pic_address): Now static. Handle
FD-PIC moves.
(n_pregs_to_save): PIC register doesn't need to be saved with FD-PIC.
(print_operand): Handle UNSPEC_MOVE_FDPIC and UNSPEC_FUNCDESC_GOT17M4.
(initialize_trampoline): Changed to handle FD-PIC code generation.
(expand_move): If TARGET_FDPIC, use emit_pic_move as needed.
(bfin_expand_call): Generate FD-PIC calls if TARGET_FDPIC.
(override_options): Disallow -mid-shared-library -mfdpic combination.
Can't do unaligned ops if FD-PIC.
Turn off flag_pic if trying to generate non-id-shared-library
non-fdpic code, since it's not supported.
(bfin_assemble_integer): New function.
(TARGET_ASM_INTEGER): Define.
* config/bfin/crti.s (__init, __fini): Save P3 on the stack if
__BFIN_FDPIC__.
* config/bfin/crtn.s: Restore them.
* config/bfin/bfin.h (TARGET_CPU_CPP_BUILTINS): Define __BFIN_FDPIC__
if TARGET_FDPIC.
(DRIVER_SELF_SPECS, SUBTARGET_DRIVER_SELF_SPECS,
LINK_GCC_C_SEQUENCE_SPEC, ASM_SPEC, LINK_SPEC): New macros.
(FDPIC_FPTR_REGNO, FDPIC_REGNO, OUR_FDPIC_REG): New macros.
(TRAMPOLINE_SIZE, TRAMPOLINE_TEMPLATE): Adjust for FD-PIC.
(CONDITIONAL_REGISTER_USAGE): If TARGET_FDPIC, FDPIC_REGNO is
call-used.
(enum reg_class, REG_CLASS_CONTENTS, REG_CLASS_NAMES): Add
FDPIC_REGS and FDPIC_FPTR_REGS.
(REG_CLASS_FROM_LETTER): Use 'Z' and 'Y' for them.
* config/bfin/bfin.md (UNSPEC_MOVE_FDPIC, UNSPEC_FUNCDESC_GOT17M4,
UNSPEC_VOLATILE_LOAD_FUNCDESC): New constants.
(load_funcdescsi): New pattern.
(call_symbol_fdpic, sibcall_symbol_fdpic, call_value_symbol_fdpic,
sibcall_value_symbol_fdpic, call_insn_fdpic, sibcall_insn_fdpic,
call_value_insn_fdpic, sibcall_value_insn_fdpic): New patterns.
From-SVN: r114199
2006-05-29 16:11:07 +02:00
|
|
|
|
(define_insn "*call_symbol_fdpic"
|
|
|
|
|
[(call (mem:SI (match_operand:SI 0 "symbol_ref_operand" "Q"))
|
|
|
|
|
(match_operand 1 "general_operand" "g"))
|
|
|
|
|
(use (match_operand:SI 2 "register_operand" "Z"))
|
2009-09-03 17:37:28 +02:00
|
|
|
|
(use (match_operand 3 "" ""))
|
|
|
|
|
(clobber (reg:SI REG_RETS))]
|
bfin.opt (mfdpic): New option.
* config/bfin/bfin.opt (mfdpic): New option.
* config/bfin/t-bfin-elf (EXTRA_PARTS): Add crtbeginS.o and crtendS.o.
(EXTRA_MULTILIB_PARTS): Likewise.
(CRTSTUFF_T_CFLAGS, TARGET_LIBGCC2_CFLAGS): Use -fpic.
(MULTILIB_OPTIONS, MULTILIB_EXCEPTIONS): Build one extra -mfdpic
multilib.
* config/bfin/elf.h (STARTFILE_SPEC): Don't link in crt0.o if -shared.
(CRT_CALL_STATIC_FUNCTION): New.
* config/bfin/uclinux.h (STARTFILE_SPEC): Don't link in crt0.o if
-shared.
(CRT_CALL_STATIC_FUNCTION): New.
* config/bfin/bfin.c (legitimize_pic_address): Now static. Handle
FD-PIC moves.
(n_pregs_to_save): PIC register doesn't need to be saved with FD-PIC.
(print_operand): Handle UNSPEC_MOVE_FDPIC and UNSPEC_FUNCDESC_GOT17M4.
(initialize_trampoline): Changed to handle FD-PIC code generation.
(expand_move): If TARGET_FDPIC, use emit_pic_move as needed.
(bfin_expand_call): Generate FD-PIC calls if TARGET_FDPIC.
(override_options): Disallow -mid-shared-library -mfdpic combination.
Can't do unaligned ops if FD-PIC.
Turn off flag_pic if trying to generate non-id-shared-library
non-fdpic code, since it's not supported.
(bfin_assemble_integer): New function.
(TARGET_ASM_INTEGER): Define.
* config/bfin/crti.s (__init, __fini): Save P3 on the stack if
__BFIN_FDPIC__.
* config/bfin/crtn.s: Restore them.
* config/bfin/bfin.h (TARGET_CPU_CPP_BUILTINS): Define __BFIN_FDPIC__
if TARGET_FDPIC.
(DRIVER_SELF_SPECS, SUBTARGET_DRIVER_SELF_SPECS,
LINK_GCC_C_SEQUENCE_SPEC, ASM_SPEC, LINK_SPEC): New macros.
(FDPIC_FPTR_REGNO, FDPIC_REGNO, OUR_FDPIC_REG): New macros.
(TRAMPOLINE_SIZE, TRAMPOLINE_TEMPLATE): Adjust for FD-PIC.
(CONDITIONAL_REGISTER_USAGE): If TARGET_FDPIC, FDPIC_REGNO is
call-used.
(enum reg_class, REG_CLASS_CONTENTS, REG_CLASS_NAMES): Add
FDPIC_REGS and FDPIC_FPTR_REGS.
(REG_CLASS_FROM_LETTER): Use 'Z' and 'Y' for them.
* config/bfin/bfin.md (UNSPEC_MOVE_FDPIC, UNSPEC_FUNCDESC_GOT17M4,
UNSPEC_VOLATILE_LOAD_FUNCDESC): New constants.
(load_funcdescsi): New pattern.
(call_symbol_fdpic, sibcall_symbol_fdpic, call_value_symbol_fdpic,
sibcall_value_symbol_fdpic, call_insn_fdpic, sibcall_insn_fdpic,
call_value_insn_fdpic, sibcall_value_insn_fdpic): New patterns.
From-SVN: r114199
2006-05-29 16:11:07 +02:00
|
|
|
|
"! SIBLING_CALL_P (insn)
|
|
|
|
|
&& GET_CODE (operands[0]) == SYMBOL_REF
|
|
|
|
|
&& !bfin_longcall_p (operands[0], INTVAL (operands[3]))"
|
|
|
|
|
"call %0;"
|
|
|
|
|
[(set_attr "type" "call")
|
|
|
|
|
(set_attr "length" "4")])
|
|
|
|
|
|
|
|
|
|
(define_insn "*sibcall_symbol_fdpic"
|
|
|
|
|
[(call (mem:SI (match_operand:SI 0 "symbol_ref_operand" "Q"))
|
|
|
|
|
(match_operand 1 "general_operand" "g"))
|
|
|
|
|
(use (match_operand:SI 2 "register_operand" "Z"))
|
|
|
|
|
(use (match_operand 3 "" ""))
|
|
|
|
|
(return)]
|
|
|
|
|
"SIBLING_CALL_P (insn)
|
|
|
|
|
&& GET_CODE (operands[0]) == SYMBOL_REF
|
|
|
|
|
&& !bfin_longcall_p (operands[0], INTVAL (operands[3]))"
|
|
|
|
|
"jump.l %0;"
|
|
|
|
|
[(set_attr "type" "br")
|
|
|
|
|
(set_attr "length" "4")])
|
|
|
|
|
|
|
|
|
|
(define_insn "*call_value_symbol_fdpic"
|
|
|
|
|
[(set (match_operand 0 "register_operand" "=d")
|
|
|
|
|
(call (mem:SI (match_operand:SI 1 "symbol_ref_operand" "Q"))
|
|
|
|
|
(match_operand 2 "general_operand" "g")))
|
|
|
|
|
(use (match_operand:SI 3 "register_operand" "Z"))
|
2009-09-03 17:37:28 +02:00
|
|
|
|
(use (match_operand 4 "" ""))
|
|
|
|
|
(clobber (reg:SI REG_RETS))]
|
bfin.opt (mfdpic): New option.
* config/bfin/bfin.opt (mfdpic): New option.
* config/bfin/t-bfin-elf (EXTRA_PARTS): Add crtbeginS.o and crtendS.o.
(EXTRA_MULTILIB_PARTS): Likewise.
(CRTSTUFF_T_CFLAGS, TARGET_LIBGCC2_CFLAGS): Use -fpic.
(MULTILIB_OPTIONS, MULTILIB_EXCEPTIONS): Build one extra -mfdpic
multilib.
* config/bfin/elf.h (STARTFILE_SPEC): Don't link in crt0.o if -shared.
(CRT_CALL_STATIC_FUNCTION): New.
* config/bfin/uclinux.h (STARTFILE_SPEC): Don't link in crt0.o if
-shared.
(CRT_CALL_STATIC_FUNCTION): New.
* config/bfin/bfin.c (legitimize_pic_address): Now static. Handle
FD-PIC moves.
(n_pregs_to_save): PIC register doesn't need to be saved with FD-PIC.
(print_operand): Handle UNSPEC_MOVE_FDPIC and UNSPEC_FUNCDESC_GOT17M4.
(initialize_trampoline): Changed to handle FD-PIC code generation.
(expand_move): If TARGET_FDPIC, use emit_pic_move as needed.
(bfin_expand_call): Generate FD-PIC calls if TARGET_FDPIC.
(override_options): Disallow -mid-shared-library -mfdpic combination.
Can't do unaligned ops if FD-PIC.
Turn off flag_pic if trying to generate non-id-shared-library
non-fdpic code, since it's not supported.
(bfin_assemble_integer): New function.
(TARGET_ASM_INTEGER): Define.
* config/bfin/crti.s (__init, __fini): Save P3 on the stack if
__BFIN_FDPIC__.
* config/bfin/crtn.s: Restore them.
* config/bfin/bfin.h (TARGET_CPU_CPP_BUILTINS): Define __BFIN_FDPIC__
if TARGET_FDPIC.
(DRIVER_SELF_SPECS, SUBTARGET_DRIVER_SELF_SPECS,
LINK_GCC_C_SEQUENCE_SPEC, ASM_SPEC, LINK_SPEC): New macros.
(FDPIC_FPTR_REGNO, FDPIC_REGNO, OUR_FDPIC_REG): New macros.
(TRAMPOLINE_SIZE, TRAMPOLINE_TEMPLATE): Adjust for FD-PIC.
(CONDITIONAL_REGISTER_USAGE): If TARGET_FDPIC, FDPIC_REGNO is
call-used.
(enum reg_class, REG_CLASS_CONTENTS, REG_CLASS_NAMES): Add
FDPIC_REGS and FDPIC_FPTR_REGS.
(REG_CLASS_FROM_LETTER): Use 'Z' and 'Y' for them.
* config/bfin/bfin.md (UNSPEC_MOVE_FDPIC, UNSPEC_FUNCDESC_GOT17M4,
UNSPEC_VOLATILE_LOAD_FUNCDESC): New constants.
(load_funcdescsi): New pattern.
(call_symbol_fdpic, sibcall_symbol_fdpic, call_value_symbol_fdpic,
sibcall_value_symbol_fdpic, call_insn_fdpic, sibcall_insn_fdpic,
call_value_insn_fdpic, sibcall_value_insn_fdpic): New patterns.
From-SVN: r114199
2006-05-29 16:11:07 +02:00
|
|
|
|
"! SIBLING_CALL_P (insn)
|
|
|
|
|
&& GET_CODE (operands[1]) == SYMBOL_REF
|
|
|
|
|
&& !bfin_longcall_p (operands[1], INTVAL (operands[4]))"
|
|
|
|
|
"call %1;"
|
|
|
|
|
[(set_attr "type" "call")
|
|
|
|
|
(set_attr "length" "4")])
|
|
|
|
|
|
|
|
|
|
(define_insn "*sibcall_value_symbol_fdpic"
|
|
|
|
|
[(set (match_operand 0 "register_operand" "=d")
|
|
|
|
|
(call (mem:SI (match_operand:SI 1 "symbol_ref_operand" "Q"))
|
|
|
|
|
(match_operand 2 "general_operand" "g")))
|
|
|
|
|
(use (match_operand:SI 3 "register_operand" "Z"))
|
|
|
|
|
(use (match_operand 4 "" ""))
|
|
|
|
|
(return)]
|
|
|
|
|
"SIBLING_CALL_P (insn)
|
|
|
|
|
&& GET_CODE (operands[1]) == SYMBOL_REF
|
|
|
|
|
&& !bfin_longcall_p (operands[1], INTVAL (operands[4]))"
|
|
|
|
|
"jump.l %1;"
|
|
|
|
|
[(set_attr "type" "br")
|
|
|
|
|
(set_attr "length" "4")])
|
|
|
|
|
|
|
|
|
|
(define_insn "*call_insn_fdpic"
|
|
|
|
|
[(call (mem:SI (match_operand:SI 0 "register_no_elim_operand" "Y"))
|
|
|
|
|
(match_operand 1 "general_operand" "g"))
|
|
|
|
|
(use (match_operand:SI 2 "register_operand" "Z"))
|
2009-09-03 17:37:28 +02:00
|
|
|
|
(use (match_operand 3 "" ""))
|
|
|
|
|
(clobber (reg:SI REG_RETS))]
|
bfin.opt (mfdpic): New option.
* config/bfin/bfin.opt (mfdpic): New option.
* config/bfin/t-bfin-elf (EXTRA_PARTS): Add crtbeginS.o and crtendS.o.
(EXTRA_MULTILIB_PARTS): Likewise.
(CRTSTUFF_T_CFLAGS, TARGET_LIBGCC2_CFLAGS): Use -fpic.
(MULTILIB_OPTIONS, MULTILIB_EXCEPTIONS): Build one extra -mfdpic
multilib.
* config/bfin/elf.h (STARTFILE_SPEC): Don't link in crt0.o if -shared.
(CRT_CALL_STATIC_FUNCTION): New.
* config/bfin/uclinux.h (STARTFILE_SPEC): Don't link in crt0.o if
-shared.
(CRT_CALL_STATIC_FUNCTION): New.
* config/bfin/bfin.c (legitimize_pic_address): Now static. Handle
FD-PIC moves.
(n_pregs_to_save): PIC register doesn't need to be saved with FD-PIC.
(print_operand): Handle UNSPEC_MOVE_FDPIC and UNSPEC_FUNCDESC_GOT17M4.
(initialize_trampoline): Changed to handle FD-PIC code generation.
(expand_move): If TARGET_FDPIC, use emit_pic_move as needed.
(bfin_expand_call): Generate FD-PIC calls if TARGET_FDPIC.
(override_options): Disallow -mid-shared-library -mfdpic combination.
Can't do unaligned ops if FD-PIC.
Turn off flag_pic if trying to generate non-id-shared-library
non-fdpic code, since it's not supported.
(bfin_assemble_integer): New function.
(TARGET_ASM_INTEGER): Define.
* config/bfin/crti.s (__init, __fini): Save P3 on the stack if
__BFIN_FDPIC__.
* config/bfin/crtn.s: Restore them.
* config/bfin/bfin.h (TARGET_CPU_CPP_BUILTINS): Define __BFIN_FDPIC__
if TARGET_FDPIC.
(DRIVER_SELF_SPECS, SUBTARGET_DRIVER_SELF_SPECS,
LINK_GCC_C_SEQUENCE_SPEC, ASM_SPEC, LINK_SPEC): New macros.
(FDPIC_FPTR_REGNO, FDPIC_REGNO, OUR_FDPIC_REG): New macros.
(TRAMPOLINE_SIZE, TRAMPOLINE_TEMPLATE): Adjust for FD-PIC.
(CONDITIONAL_REGISTER_USAGE): If TARGET_FDPIC, FDPIC_REGNO is
call-used.
(enum reg_class, REG_CLASS_CONTENTS, REG_CLASS_NAMES): Add
FDPIC_REGS and FDPIC_FPTR_REGS.
(REG_CLASS_FROM_LETTER): Use 'Z' and 'Y' for them.
* config/bfin/bfin.md (UNSPEC_MOVE_FDPIC, UNSPEC_FUNCDESC_GOT17M4,
UNSPEC_VOLATILE_LOAD_FUNCDESC): New constants.
(load_funcdescsi): New pattern.
(call_symbol_fdpic, sibcall_symbol_fdpic, call_value_symbol_fdpic,
sibcall_value_symbol_fdpic, call_insn_fdpic, sibcall_insn_fdpic,
call_value_insn_fdpic, sibcall_value_insn_fdpic): New patterns.
From-SVN: r114199
2006-05-29 16:11:07 +02:00
|
|
|
|
"! SIBLING_CALL_P (insn)"
|
|
|
|
|
"call (%0);"
|
|
|
|
|
[(set_attr "type" "call")
|
|
|
|
|
(set_attr "length" "2")])
|
|
|
|
|
|
|
|
|
|
(define_insn "*sibcall_insn_fdpic"
|
|
|
|
|
[(call (mem:SI (match_operand:SI 0 "register_no_elim_operand" "Y"))
|
|
|
|
|
(match_operand 1 "general_operand" "g"))
|
|
|
|
|
(use (match_operand:SI 2 "register_operand" "Z"))
|
|
|
|
|
(use (match_operand 3 "" ""))
|
|
|
|
|
(return)]
|
|
|
|
|
"SIBLING_CALL_P (insn)"
|
|
|
|
|
"jump (%0);"
|
|
|
|
|
[(set_attr "type" "br")
|
|
|
|
|
(set_attr "length" "2")])
|
|
|
|
|
|
|
|
|
|
(define_insn "*call_value_insn_fdpic"
|
|
|
|
|
[(set (match_operand 0 "register_operand" "=d")
|
|
|
|
|
(call (mem:SI (match_operand:SI 1 "register_no_elim_operand" "Y"))
|
|
|
|
|
(match_operand 2 "general_operand" "g")))
|
|
|
|
|
(use (match_operand:SI 3 "register_operand" "Z"))
|
2009-09-03 17:37:28 +02:00
|
|
|
|
(use (match_operand 4 "" ""))
|
|
|
|
|
(clobber (reg:SI REG_RETS))]
|
bfin.opt (mfdpic): New option.
* config/bfin/bfin.opt (mfdpic): New option.
* config/bfin/t-bfin-elf (EXTRA_PARTS): Add crtbeginS.o and crtendS.o.
(EXTRA_MULTILIB_PARTS): Likewise.
(CRTSTUFF_T_CFLAGS, TARGET_LIBGCC2_CFLAGS): Use -fpic.
(MULTILIB_OPTIONS, MULTILIB_EXCEPTIONS): Build one extra -mfdpic
multilib.
* config/bfin/elf.h (STARTFILE_SPEC): Don't link in crt0.o if -shared.
(CRT_CALL_STATIC_FUNCTION): New.
* config/bfin/uclinux.h (STARTFILE_SPEC): Don't link in crt0.o if
-shared.
(CRT_CALL_STATIC_FUNCTION): New.
* config/bfin/bfin.c (legitimize_pic_address): Now static. Handle
FD-PIC moves.
(n_pregs_to_save): PIC register doesn't need to be saved with FD-PIC.
(print_operand): Handle UNSPEC_MOVE_FDPIC and UNSPEC_FUNCDESC_GOT17M4.
(initialize_trampoline): Changed to handle FD-PIC code generation.
(expand_move): If TARGET_FDPIC, use emit_pic_move as needed.
(bfin_expand_call): Generate FD-PIC calls if TARGET_FDPIC.
(override_options): Disallow -mid-shared-library -mfdpic combination.
Can't do unaligned ops if FD-PIC.
Turn off flag_pic if trying to generate non-id-shared-library
non-fdpic code, since it's not supported.
(bfin_assemble_integer): New function.
(TARGET_ASM_INTEGER): Define.
* config/bfin/crti.s (__init, __fini): Save P3 on the stack if
__BFIN_FDPIC__.
* config/bfin/crtn.s: Restore them.
* config/bfin/bfin.h (TARGET_CPU_CPP_BUILTINS): Define __BFIN_FDPIC__
if TARGET_FDPIC.
(DRIVER_SELF_SPECS, SUBTARGET_DRIVER_SELF_SPECS,
LINK_GCC_C_SEQUENCE_SPEC, ASM_SPEC, LINK_SPEC): New macros.
(FDPIC_FPTR_REGNO, FDPIC_REGNO, OUR_FDPIC_REG): New macros.
(TRAMPOLINE_SIZE, TRAMPOLINE_TEMPLATE): Adjust for FD-PIC.
(CONDITIONAL_REGISTER_USAGE): If TARGET_FDPIC, FDPIC_REGNO is
call-used.
(enum reg_class, REG_CLASS_CONTENTS, REG_CLASS_NAMES): Add
FDPIC_REGS and FDPIC_FPTR_REGS.
(REG_CLASS_FROM_LETTER): Use 'Z' and 'Y' for them.
* config/bfin/bfin.md (UNSPEC_MOVE_FDPIC, UNSPEC_FUNCDESC_GOT17M4,
UNSPEC_VOLATILE_LOAD_FUNCDESC): New constants.
(load_funcdescsi): New pattern.
(call_symbol_fdpic, sibcall_symbol_fdpic, call_value_symbol_fdpic,
sibcall_value_symbol_fdpic, call_insn_fdpic, sibcall_insn_fdpic,
call_value_insn_fdpic, sibcall_value_insn_fdpic): New patterns.
From-SVN: r114199
2006-05-29 16:11:07 +02:00
|
|
|
|
"! SIBLING_CALL_P (insn)"
|
|
|
|
|
"call (%1);"
|
|
|
|
|
[(set_attr "type" "call")
|
|
|
|
|
(set_attr "length" "2")])
|
|
|
|
|
|
|
|
|
|
(define_insn "*sibcall_value_insn_fdpic"
|
|
|
|
|
[(set (match_operand 0 "register_operand" "=d")
|
|
|
|
|
(call (mem:SI (match_operand:SI 1 "register_no_elim_operand" "Y"))
|
|
|
|
|
(match_operand 2 "general_operand" "g")))
|
|
|
|
|
(use (match_operand:SI 3 "register_operand" "Z"))
|
|
|
|
|
(use (match_operand 4 "" ""))
|
|
|
|
|
(return)]
|
|
|
|
|
"SIBLING_CALL_P (insn)"
|
|
|
|
|
"jump (%1);"
|
|
|
|
|
[(set_attr "type" "br")
|
|
|
|
|
(set_attr "length" "2")])
|
|
|
|
|
|
bfin-protos.h (bfin_longcall_p): Declare.
* config/bfin/bfin-protos.h (bfin_longcall_p): Declare.
* config/bfin/predicates.md (symbol_ref_operand): New.
(call_insn_operand): Delete. All callers changed to use
register_no_elim_operand.
* config/bfin/bfin.c (init_cumulative_args): Initialize the new
call_cookie field.
(function_arg): Use it to generate the call's operand 2.
(bfin_longcall_p): New function.
(bfin_expand_call): Extra arg "cookie". All callers and declaration
changed. Emit extra USE in the pattern. Use bfin_longcall_p to
determine if the address needs to be in a REG.
(bfin_handle_longcall_attribute): New function.
(bfin_attribute_table): Add "longcall" and "shortcall".
* config/bfin/bfin.h (CALL_NORMAL, CALL_LONG, CALL_SHORT): New macros.
(CUMULATIVE_ARGS): New member call_cookie.
(PREDICATE_CODES): Add symbol_ref_operand.
* config/bfin/bfin.md (call, call_value, sibcall, sibcall_value): Add
extra USE to the pattern.
(call_symbol, sibcall_symbol, call_value_symbol, sibcall_value_symbol):
New patterns, split off call_insn, sibcall_insn, call_value_insn and
sibcall_value_insn; now the new patterns handle direct calls and the
old ones indirect calls.
* doc/extend.texi: Mention Blackfin in longcall/shortcall docs.
From-SVN: r102191
2005-07-20 11:48:03 +02:00
|
|
|
|
(define_insn "*call_symbol"
|
|
|
|
|
[(call (mem:SI (match_operand:SI 0 "symbol_ref_operand" "Q"))
|
|
|
|
|
(match_operand 1 "general_operand" "g"))
|
2009-09-03 17:37:28 +02:00
|
|
|
|
(use (match_operand 2 "" ""))
|
|
|
|
|
(clobber (reg:SI REG_RETS))]
|
2005-04-05 13:26:48 +02:00
|
|
|
|
"! SIBLING_CALL_P (insn)
|
2006-11-20 13:35:47 +01:00
|
|
|
|
&& (!TARGET_ID_SHARED_LIBRARY || TARGET_LEAF_ID_SHARED_LIBRARY)
|
bfin-protos.h (bfin_longcall_p): Declare.
* config/bfin/bfin-protos.h (bfin_longcall_p): Declare.
* config/bfin/predicates.md (symbol_ref_operand): New.
(call_insn_operand): Delete. All callers changed to use
register_no_elim_operand.
* config/bfin/bfin.c (init_cumulative_args): Initialize the new
call_cookie field.
(function_arg): Use it to generate the call's operand 2.
(bfin_longcall_p): New function.
(bfin_expand_call): Extra arg "cookie". All callers and declaration
changed. Emit extra USE in the pattern. Use bfin_longcall_p to
determine if the address needs to be in a REG.
(bfin_handle_longcall_attribute): New function.
(bfin_attribute_table): Add "longcall" and "shortcall".
* config/bfin/bfin.h (CALL_NORMAL, CALL_LONG, CALL_SHORT): New macros.
(CUMULATIVE_ARGS): New member call_cookie.
(PREDICATE_CODES): Add symbol_ref_operand.
* config/bfin/bfin.md (call, call_value, sibcall, sibcall_value): Add
extra USE to the pattern.
(call_symbol, sibcall_symbol, call_value_symbol, sibcall_value_symbol):
New patterns, split off call_insn, sibcall_insn, call_value_insn and
sibcall_value_insn; now the new patterns handle direct calls and the
old ones indirect calls.
* doc/extend.texi: Mention Blackfin in longcall/shortcall docs.
From-SVN: r102191
2005-07-20 11:48:03 +02:00
|
|
|
|
&& GET_CODE (operands[0]) == SYMBOL_REF
|
|
|
|
|
&& !bfin_longcall_p (operands[0], INTVAL (operands[2]))"
|
2006-03-13 17:30:40 +01:00
|
|
|
|
"call %0;"
|
2005-04-05 13:26:48 +02:00
|
|
|
|
[(set_attr "type" "call")
|
bfin-protos.h (bfin_longcall_p): Declare.
* config/bfin/bfin-protos.h (bfin_longcall_p): Declare.
* config/bfin/predicates.md (symbol_ref_operand): New.
(call_insn_operand): Delete. All callers changed to use
register_no_elim_operand.
* config/bfin/bfin.c (init_cumulative_args): Initialize the new
call_cookie field.
(function_arg): Use it to generate the call's operand 2.
(bfin_longcall_p): New function.
(bfin_expand_call): Extra arg "cookie". All callers and declaration
changed. Emit extra USE in the pattern. Use bfin_longcall_p to
determine if the address needs to be in a REG.
(bfin_handle_longcall_attribute): New function.
(bfin_attribute_table): Add "longcall" and "shortcall".
* config/bfin/bfin.h (CALL_NORMAL, CALL_LONG, CALL_SHORT): New macros.
(CUMULATIVE_ARGS): New member call_cookie.
(PREDICATE_CODES): Add symbol_ref_operand.
* config/bfin/bfin.md (call, call_value, sibcall, sibcall_value): Add
extra USE to the pattern.
(call_symbol, sibcall_symbol, call_value_symbol, sibcall_value_symbol):
New patterns, split off call_insn, sibcall_insn, call_value_insn and
sibcall_value_insn; now the new patterns handle direct calls and the
old ones indirect calls.
* doc/extend.texi: Mention Blackfin in longcall/shortcall docs.
From-SVN: r102191
2005-07-20 11:48:03 +02:00
|
|
|
|
(set_attr "length" "4")])
|
2005-04-05 13:26:48 +02:00
|
|
|
|
|
bfin-protos.h (bfin_longcall_p): Declare.
* config/bfin/bfin-protos.h (bfin_longcall_p): Declare.
* config/bfin/predicates.md (symbol_ref_operand): New.
(call_insn_operand): Delete. All callers changed to use
register_no_elim_operand.
* config/bfin/bfin.c (init_cumulative_args): Initialize the new
call_cookie field.
(function_arg): Use it to generate the call's operand 2.
(bfin_longcall_p): New function.
(bfin_expand_call): Extra arg "cookie". All callers and declaration
changed. Emit extra USE in the pattern. Use bfin_longcall_p to
determine if the address needs to be in a REG.
(bfin_handle_longcall_attribute): New function.
(bfin_attribute_table): Add "longcall" and "shortcall".
* config/bfin/bfin.h (CALL_NORMAL, CALL_LONG, CALL_SHORT): New macros.
(CUMULATIVE_ARGS): New member call_cookie.
(PREDICATE_CODES): Add symbol_ref_operand.
* config/bfin/bfin.md (call, call_value, sibcall, sibcall_value): Add
extra USE to the pattern.
(call_symbol, sibcall_symbol, call_value_symbol, sibcall_value_symbol):
New patterns, split off call_insn, sibcall_insn, call_value_insn and
sibcall_value_insn; now the new patterns handle direct calls and the
old ones indirect calls.
* doc/extend.texi: Mention Blackfin in longcall/shortcall docs.
From-SVN: r102191
2005-07-20 11:48:03 +02:00
|
|
|
|
(define_insn "*sibcall_symbol"
|
|
|
|
|
[(call (mem:SI (match_operand:SI 0 "symbol_ref_operand" "Q"))
|
|
|
|
|
(match_operand 1 "general_operand" "g"))
|
|
|
|
|
(use (match_operand 2 "" ""))
|
2005-04-05 13:26:48 +02:00
|
|
|
|
(return)]
|
|
|
|
|
"SIBLING_CALL_P (insn)
|
2006-11-20 13:35:47 +01:00
|
|
|
|
&& (!TARGET_ID_SHARED_LIBRARY || TARGET_LEAF_ID_SHARED_LIBRARY)
|
bfin-protos.h (bfin_longcall_p): Declare.
* config/bfin/bfin-protos.h (bfin_longcall_p): Declare.
* config/bfin/predicates.md (symbol_ref_operand): New.
(call_insn_operand): Delete. All callers changed to use
register_no_elim_operand.
* config/bfin/bfin.c (init_cumulative_args): Initialize the new
call_cookie field.
(function_arg): Use it to generate the call's operand 2.
(bfin_longcall_p): New function.
(bfin_expand_call): Extra arg "cookie". All callers and declaration
changed. Emit extra USE in the pattern. Use bfin_longcall_p to
determine if the address needs to be in a REG.
(bfin_handle_longcall_attribute): New function.
(bfin_attribute_table): Add "longcall" and "shortcall".
* config/bfin/bfin.h (CALL_NORMAL, CALL_LONG, CALL_SHORT): New macros.
(CUMULATIVE_ARGS): New member call_cookie.
(PREDICATE_CODES): Add symbol_ref_operand.
* config/bfin/bfin.md (call, call_value, sibcall, sibcall_value): Add
extra USE to the pattern.
(call_symbol, sibcall_symbol, call_value_symbol, sibcall_value_symbol):
New patterns, split off call_insn, sibcall_insn, call_value_insn and
sibcall_value_insn; now the new patterns handle direct calls and the
old ones indirect calls.
* doc/extend.texi: Mention Blackfin in longcall/shortcall docs.
From-SVN: r102191
2005-07-20 11:48:03 +02:00
|
|
|
|
&& GET_CODE (operands[0]) == SYMBOL_REF
|
|
|
|
|
&& !bfin_longcall_p (operands[0], INTVAL (operands[2]))"
|
2006-03-13 17:30:40 +01:00
|
|
|
|
"jump.l %0;"
|
2005-04-05 13:26:48 +02:00
|
|
|
|
[(set_attr "type" "br")
|
bfin-protos.h (bfin_longcall_p): Declare.
* config/bfin/bfin-protos.h (bfin_longcall_p): Declare.
* config/bfin/predicates.md (symbol_ref_operand): New.
(call_insn_operand): Delete. All callers changed to use
register_no_elim_operand.
* config/bfin/bfin.c (init_cumulative_args): Initialize the new
call_cookie field.
(function_arg): Use it to generate the call's operand 2.
(bfin_longcall_p): New function.
(bfin_expand_call): Extra arg "cookie". All callers and declaration
changed. Emit extra USE in the pattern. Use bfin_longcall_p to
determine if the address needs to be in a REG.
(bfin_handle_longcall_attribute): New function.
(bfin_attribute_table): Add "longcall" and "shortcall".
* config/bfin/bfin.h (CALL_NORMAL, CALL_LONG, CALL_SHORT): New macros.
(CUMULATIVE_ARGS): New member call_cookie.
(PREDICATE_CODES): Add symbol_ref_operand.
* config/bfin/bfin.md (call, call_value, sibcall, sibcall_value): Add
extra USE to the pattern.
(call_symbol, sibcall_symbol, call_value_symbol, sibcall_value_symbol):
New patterns, split off call_insn, sibcall_insn, call_value_insn and
sibcall_value_insn; now the new patterns handle direct calls and the
old ones indirect calls.
* doc/extend.texi: Mention Blackfin in longcall/shortcall docs.
From-SVN: r102191
2005-07-20 11:48:03 +02:00
|
|
|
|
(set_attr "length" "4")])
|
2005-04-05 13:26:48 +02:00
|
|
|
|
|
bfin-protos.h (bfin_longcall_p): Declare.
* config/bfin/bfin-protos.h (bfin_longcall_p): Declare.
* config/bfin/predicates.md (symbol_ref_operand): New.
(call_insn_operand): Delete. All callers changed to use
register_no_elim_operand.
* config/bfin/bfin.c (init_cumulative_args): Initialize the new
call_cookie field.
(function_arg): Use it to generate the call's operand 2.
(bfin_longcall_p): New function.
(bfin_expand_call): Extra arg "cookie". All callers and declaration
changed. Emit extra USE in the pattern. Use bfin_longcall_p to
determine if the address needs to be in a REG.
(bfin_handle_longcall_attribute): New function.
(bfin_attribute_table): Add "longcall" and "shortcall".
* config/bfin/bfin.h (CALL_NORMAL, CALL_LONG, CALL_SHORT): New macros.
(CUMULATIVE_ARGS): New member call_cookie.
(PREDICATE_CODES): Add symbol_ref_operand.
* config/bfin/bfin.md (call, call_value, sibcall, sibcall_value): Add
extra USE to the pattern.
(call_symbol, sibcall_symbol, call_value_symbol, sibcall_value_symbol):
New patterns, split off call_insn, sibcall_insn, call_value_insn and
sibcall_value_insn; now the new patterns handle direct calls and the
old ones indirect calls.
* doc/extend.texi: Mention Blackfin in longcall/shortcall docs.
From-SVN: r102191
2005-07-20 11:48:03 +02:00
|
|
|
|
(define_insn "*call_value_symbol"
|
|
|
|
|
[(set (match_operand 0 "register_operand" "=d")
|
|
|
|
|
(call (mem:SI (match_operand:SI 1 "symbol_ref_operand" "Q"))
|
|
|
|
|
(match_operand 2 "general_operand" "g")))
|
2009-09-03 17:37:28 +02:00
|
|
|
|
(use (match_operand 3 "" ""))
|
|
|
|
|
(clobber (reg:SI REG_RETS))]
|
2005-04-05 13:26:48 +02:00
|
|
|
|
"! SIBLING_CALL_P (insn)
|
2006-11-20 13:35:47 +01:00
|
|
|
|
&& (!TARGET_ID_SHARED_LIBRARY || TARGET_LEAF_ID_SHARED_LIBRARY)
|
bfin-protos.h (bfin_longcall_p): Declare.
* config/bfin/bfin-protos.h (bfin_longcall_p): Declare.
* config/bfin/predicates.md (symbol_ref_operand): New.
(call_insn_operand): Delete. All callers changed to use
register_no_elim_operand.
* config/bfin/bfin.c (init_cumulative_args): Initialize the new
call_cookie field.
(function_arg): Use it to generate the call's operand 2.
(bfin_longcall_p): New function.
(bfin_expand_call): Extra arg "cookie". All callers and declaration
changed. Emit extra USE in the pattern. Use bfin_longcall_p to
determine if the address needs to be in a REG.
(bfin_handle_longcall_attribute): New function.
(bfin_attribute_table): Add "longcall" and "shortcall".
* config/bfin/bfin.h (CALL_NORMAL, CALL_LONG, CALL_SHORT): New macros.
(CUMULATIVE_ARGS): New member call_cookie.
(PREDICATE_CODES): Add symbol_ref_operand.
* config/bfin/bfin.md (call, call_value, sibcall, sibcall_value): Add
extra USE to the pattern.
(call_symbol, sibcall_symbol, call_value_symbol, sibcall_value_symbol):
New patterns, split off call_insn, sibcall_insn, call_value_insn and
sibcall_value_insn; now the new patterns handle direct calls and the
old ones indirect calls.
* doc/extend.texi: Mention Blackfin in longcall/shortcall docs.
From-SVN: r102191
2005-07-20 11:48:03 +02:00
|
|
|
|
&& GET_CODE (operands[1]) == SYMBOL_REF
|
|
|
|
|
&& !bfin_longcall_p (operands[1], INTVAL (operands[3]))"
|
2006-03-13 17:30:40 +01:00
|
|
|
|
"call %1;"
|
2005-04-05 13:26:48 +02:00
|
|
|
|
[(set_attr "type" "call")
|
bfin-protos.h (bfin_longcall_p): Declare.
* config/bfin/bfin-protos.h (bfin_longcall_p): Declare.
* config/bfin/predicates.md (symbol_ref_operand): New.
(call_insn_operand): Delete. All callers changed to use
register_no_elim_operand.
* config/bfin/bfin.c (init_cumulative_args): Initialize the new
call_cookie field.
(function_arg): Use it to generate the call's operand 2.
(bfin_longcall_p): New function.
(bfin_expand_call): Extra arg "cookie". All callers and declaration
changed. Emit extra USE in the pattern. Use bfin_longcall_p to
determine if the address needs to be in a REG.
(bfin_handle_longcall_attribute): New function.
(bfin_attribute_table): Add "longcall" and "shortcall".
* config/bfin/bfin.h (CALL_NORMAL, CALL_LONG, CALL_SHORT): New macros.
(CUMULATIVE_ARGS): New member call_cookie.
(PREDICATE_CODES): Add symbol_ref_operand.
* config/bfin/bfin.md (call, call_value, sibcall, sibcall_value): Add
extra USE to the pattern.
(call_symbol, sibcall_symbol, call_value_symbol, sibcall_value_symbol):
New patterns, split off call_insn, sibcall_insn, call_value_insn and
sibcall_value_insn; now the new patterns handle direct calls and the
old ones indirect calls.
* doc/extend.texi: Mention Blackfin in longcall/shortcall docs.
From-SVN: r102191
2005-07-20 11:48:03 +02:00
|
|
|
|
(set_attr "length" "4")])
|
2005-04-05 13:26:48 +02:00
|
|
|
|
|
bfin-protos.h (bfin_longcall_p): Declare.
* config/bfin/bfin-protos.h (bfin_longcall_p): Declare.
* config/bfin/predicates.md (symbol_ref_operand): New.
(call_insn_operand): Delete. All callers changed to use
register_no_elim_operand.
* config/bfin/bfin.c (init_cumulative_args): Initialize the new
call_cookie field.
(function_arg): Use it to generate the call's operand 2.
(bfin_longcall_p): New function.
(bfin_expand_call): Extra arg "cookie". All callers and declaration
changed. Emit extra USE in the pattern. Use bfin_longcall_p to
determine if the address needs to be in a REG.
(bfin_handle_longcall_attribute): New function.
(bfin_attribute_table): Add "longcall" and "shortcall".
* config/bfin/bfin.h (CALL_NORMAL, CALL_LONG, CALL_SHORT): New macros.
(CUMULATIVE_ARGS): New member call_cookie.
(PREDICATE_CODES): Add symbol_ref_operand.
* config/bfin/bfin.md (call, call_value, sibcall, sibcall_value): Add
extra USE to the pattern.
(call_symbol, sibcall_symbol, call_value_symbol, sibcall_value_symbol):
New patterns, split off call_insn, sibcall_insn, call_value_insn and
sibcall_value_insn; now the new patterns handle direct calls and the
old ones indirect calls.
* doc/extend.texi: Mention Blackfin in longcall/shortcall docs.
From-SVN: r102191
2005-07-20 11:48:03 +02:00
|
|
|
|
(define_insn "*sibcall_value_symbol"
|
|
|
|
|
[(set (match_operand 0 "register_operand" "=d")
|
|
|
|
|
(call (mem:SI (match_operand:SI 1 "symbol_ref_operand" "Q"))
|
|
|
|
|
(match_operand 2 "general_operand" "g")))
|
|
|
|
|
(use (match_operand 3 "" ""))
|
2005-04-05 13:26:48 +02:00
|
|
|
|
(return)]
|
|
|
|
|
"SIBLING_CALL_P (insn)
|
2006-11-20 13:35:47 +01:00
|
|
|
|
&& (!TARGET_ID_SHARED_LIBRARY || TARGET_LEAF_ID_SHARED_LIBRARY)
|
bfin-protos.h (bfin_longcall_p): Declare.
* config/bfin/bfin-protos.h (bfin_longcall_p): Declare.
* config/bfin/predicates.md (symbol_ref_operand): New.
(call_insn_operand): Delete. All callers changed to use
register_no_elim_operand.
* config/bfin/bfin.c (init_cumulative_args): Initialize the new
call_cookie field.
(function_arg): Use it to generate the call's operand 2.
(bfin_longcall_p): New function.
(bfin_expand_call): Extra arg "cookie". All callers and declaration
changed. Emit extra USE in the pattern. Use bfin_longcall_p to
determine if the address needs to be in a REG.
(bfin_handle_longcall_attribute): New function.
(bfin_attribute_table): Add "longcall" and "shortcall".
* config/bfin/bfin.h (CALL_NORMAL, CALL_LONG, CALL_SHORT): New macros.
(CUMULATIVE_ARGS): New member call_cookie.
(PREDICATE_CODES): Add symbol_ref_operand.
* config/bfin/bfin.md (call, call_value, sibcall, sibcall_value): Add
extra USE to the pattern.
(call_symbol, sibcall_symbol, call_value_symbol, sibcall_value_symbol):
New patterns, split off call_insn, sibcall_insn, call_value_insn and
sibcall_value_insn; now the new patterns handle direct calls and the
old ones indirect calls.
* doc/extend.texi: Mention Blackfin in longcall/shortcall docs.
From-SVN: r102191
2005-07-20 11:48:03 +02:00
|
|
|
|
&& GET_CODE (operands[1]) == SYMBOL_REF
|
|
|
|
|
&& !bfin_longcall_p (operands[1], INTVAL (operands[3]))"
|
2006-03-13 17:30:40 +01:00
|
|
|
|
"jump.l %1;"
|
bfin-protos.h (bfin_longcall_p): Declare.
* config/bfin/bfin-protos.h (bfin_longcall_p): Declare.
* config/bfin/predicates.md (symbol_ref_operand): New.
(call_insn_operand): Delete. All callers changed to use
register_no_elim_operand.
* config/bfin/bfin.c (init_cumulative_args): Initialize the new
call_cookie field.
(function_arg): Use it to generate the call's operand 2.
(bfin_longcall_p): New function.
(bfin_expand_call): Extra arg "cookie". All callers and declaration
changed. Emit extra USE in the pattern. Use bfin_longcall_p to
determine if the address needs to be in a REG.
(bfin_handle_longcall_attribute): New function.
(bfin_attribute_table): Add "longcall" and "shortcall".
* config/bfin/bfin.h (CALL_NORMAL, CALL_LONG, CALL_SHORT): New macros.
(CUMULATIVE_ARGS): New member call_cookie.
(PREDICATE_CODES): Add symbol_ref_operand.
* config/bfin/bfin.md (call, call_value, sibcall, sibcall_value): Add
extra USE to the pattern.
(call_symbol, sibcall_symbol, call_value_symbol, sibcall_value_symbol):
New patterns, split off call_insn, sibcall_insn, call_value_insn and
sibcall_value_insn; now the new patterns handle direct calls and the
old ones indirect calls.
* doc/extend.texi: Mention Blackfin in longcall/shortcall docs.
From-SVN: r102191
2005-07-20 11:48:03 +02:00
|
|
|
|
[(set_attr "type" "br")
|
|
|
|
|
(set_attr "length" "4")])
|
|
|
|
|
|
|
|
|
|
(define_insn "*call_insn"
|
|
|
|
|
[(call (mem:SI (match_operand:SI 0 "register_no_elim_operand" "a"))
|
|
|
|
|
(match_operand 1 "general_operand" "g"))
|
2009-09-03 17:37:28 +02:00
|
|
|
|
(use (match_operand 2 "" ""))
|
|
|
|
|
(clobber (reg:SI REG_RETS))]
|
bfin-protos.h (bfin_longcall_p): Declare.
* config/bfin/bfin-protos.h (bfin_longcall_p): Declare.
* config/bfin/predicates.md (symbol_ref_operand): New.
(call_insn_operand): Delete. All callers changed to use
register_no_elim_operand.
* config/bfin/bfin.c (init_cumulative_args): Initialize the new
call_cookie field.
(function_arg): Use it to generate the call's operand 2.
(bfin_longcall_p): New function.
(bfin_expand_call): Extra arg "cookie". All callers and declaration
changed. Emit extra USE in the pattern. Use bfin_longcall_p to
determine if the address needs to be in a REG.
(bfin_handle_longcall_attribute): New function.
(bfin_attribute_table): Add "longcall" and "shortcall".
* config/bfin/bfin.h (CALL_NORMAL, CALL_LONG, CALL_SHORT): New macros.
(CUMULATIVE_ARGS): New member call_cookie.
(PREDICATE_CODES): Add symbol_ref_operand.
* config/bfin/bfin.md (call, call_value, sibcall, sibcall_value): Add
extra USE to the pattern.
(call_symbol, sibcall_symbol, call_value_symbol, sibcall_value_symbol):
New patterns, split off call_insn, sibcall_insn, call_value_insn and
sibcall_value_insn; now the new patterns handle direct calls and the
old ones indirect calls.
* doc/extend.texi: Mention Blackfin in longcall/shortcall docs.
From-SVN: r102191
2005-07-20 11:48:03 +02:00
|
|
|
|
"! SIBLING_CALL_P (insn)"
|
|
|
|
|
"call (%0);"
|
|
|
|
|
[(set_attr "type" "call")
|
|
|
|
|
(set_attr "length" "2")])
|
|
|
|
|
|
|
|
|
|
(define_insn "*sibcall_insn"
|
|
|
|
|
[(call (mem:SI (match_operand:SI 0 "register_no_elim_operand" "z"))
|
|
|
|
|
(match_operand 1 "general_operand" "g"))
|
|
|
|
|
(use (match_operand 2 "" ""))
|
|
|
|
|
(return)]
|
|
|
|
|
"SIBLING_CALL_P (insn)"
|
|
|
|
|
"jump (%0);"
|
|
|
|
|
[(set_attr "type" "br")
|
|
|
|
|
(set_attr "length" "2")])
|
|
|
|
|
|
|
|
|
|
(define_insn "*call_value_insn"
|
|
|
|
|
[(set (match_operand 0 "register_operand" "=d")
|
|
|
|
|
(call (mem:SI (match_operand:SI 1 "register_no_elim_operand" "a"))
|
|
|
|
|
(match_operand 2 "general_operand" "g")))
|
2009-09-03 17:37:28 +02:00
|
|
|
|
(use (match_operand 3 "" ""))
|
|
|
|
|
(clobber (reg:SI REG_RETS))]
|
bfin-protos.h (bfin_longcall_p): Declare.
* config/bfin/bfin-protos.h (bfin_longcall_p): Declare.
* config/bfin/predicates.md (symbol_ref_operand): New.
(call_insn_operand): Delete. All callers changed to use
register_no_elim_operand.
* config/bfin/bfin.c (init_cumulative_args): Initialize the new
call_cookie field.
(function_arg): Use it to generate the call's operand 2.
(bfin_longcall_p): New function.
(bfin_expand_call): Extra arg "cookie". All callers and declaration
changed. Emit extra USE in the pattern. Use bfin_longcall_p to
determine if the address needs to be in a REG.
(bfin_handle_longcall_attribute): New function.
(bfin_attribute_table): Add "longcall" and "shortcall".
* config/bfin/bfin.h (CALL_NORMAL, CALL_LONG, CALL_SHORT): New macros.
(CUMULATIVE_ARGS): New member call_cookie.
(PREDICATE_CODES): Add symbol_ref_operand.
* config/bfin/bfin.md (call, call_value, sibcall, sibcall_value): Add
extra USE to the pattern.
(call_symbol, sibcall_symbol, call_value_symbol, sibcall_value_symbol):
New patterns, split off call_insn, sibcall_insn, call_value_insn and
sibcall_value_insn; now the new patterns handle direct calls and the
old ones indirect calls.
* doc/extend.texi: Mention Blackfin in longcall/shortcall docs.
From-SVN: r102191
2005-07-20 11:48:03 +02:00
|
|
|
|
"! SIBLING_CALL_P (insn)"
|
|
|
|
|
"call (%1);"
|
|
|
|
|
[(set_attr "type" "call")
|
|
|
|
|
(set_attr "length" "2")])
|
|
|
|
|
|
|
|
|
|
(define_insn "*sibcall_value_insn"
|
|
|
|
|
[(set (match_operand 0 "register_operand" "=d")
|
|
|
|
|
(call (mem:SI (match_operand:SI 1 "register_no_elim_operand" "z"))
|
|
|
|
|
(match_operand 2 "general_operand" "g")))
|
|
|
|
|
(use (match_operand 3 "" ""))
|
|
|
|
|
(return)]
|
|
|
|
|
"SIBLING_CALL_P (insn)"
|
|
|
|
|
"jump (%1);"
|
2005-04-05 13:26:48 +02:00
|
|
|
|
[(set_attr "type" "br")
|
bfin-protos.h (bfin_longcall_p): Declare.
* config/bfin/bfin-protos.h (bfin_longcall_p): Declare.
* config/bfin/predicates.md (symbol_ref_operand): New.
(call_insn_operand): Delete. All callers changed to use
register_no_elim_operand.
* config/bfin/bfin.c (init_cumulative_args): Initialize the new
call_cookie field.
(function_arg): Use it to generate the call's operand 2.
(bfin_longcall_p): New function.
(bfin_expand_call): Extra arg "cookie". All callers and declaration
changed. Emit extra USE in the pattern. Use bfin_longcall_p to
determine if the address needs to be in a REG.
(bfin_handle_longcall_attribute): New function.
(bfin_attribute_table): Add "longcall" and "shortcall".
* config/bfin/bfin.h (CALL_NORMAL, CALL_LONG, CALL_SHORT): New macros.
(CUMULATIVE_ARGS): New member call_cookie.
(PREDICATE_CODES): Add symbol_ref_operand.
* config/bfin/bfin.md (call, call_value, sibcall, sibcall_value): Add
extra USE to the pattern.
(call_symbol, sibcall_symbol, call_value_symbol, sibcall_value_symbol):
New patterns, split off call_insn, sibcall_insn, call_value_insn and
sibcall_value_insn; now the new patterns handle direct calls and the
old ones indirect calls.
* doc/extend.texi: Mention Blackfin in longcall/shortcall docs.
From-SVN: r102191
2005-07-20 11:48:03 +02:00
|
|
|
|
(set_attr "length" "2")])
|
2005-04-05 13:26:48 +02:00
|
|
|
|
|
|
|
|
|
;; Block move patterns
|
|
|
|
|
|
|
|
|
|
;; We cheat. This copies one more word than operand 2 indicates.
|
|
|
|
|
|
|
|
|
|
(define_insn "rep_movsi"
|
|
|
|
|
[(set (match_operand:SI 0 "register_operand" "=&a")
|
|
|
|
|
(plus:SI (plus:SI (match_operand:SI 3 "register_operand" "0")
|
|
|
|
|
(ashift:SI (match_operand:SI 2 "register_operand" "a")
|
|
|
|
|
(const_int 2)))
|
|
|
|
|
(const_int 4)))
|
|
|
|
|
(set (match_operand:SI 1 "register_operand" "=&b")
|
|
|
|
|
(plus:SI (plus:SI (match_operand:SI 4 "register_operand" "1")
|
|
|
|
|
(ashift:SI (match_dup 2) (const_int 2)))
|
|
|
|
|
(const_int 4)))
|
|
|
|
|
(set (mem:BLK (match_dup 3))
|
|
|
|
|
(mem:BLK (match_dup 4)))
|
|
|
|
|
(use (match_dup 2))
|
bfin-protos.h (bfin_hardware_loop): Declare.
* config/bfin/bfin-protos.h (bfin_hardware_loop): Declare.
* config/bfin/bfin.c (basic-block.h): Include.
(struct machine_function): New.
(bfin_init_machine_status): New.
(override_options): Initialize init_machine_status.
(bfin_hardware_loop): New.
(MAX_LOOP_DEPTH, MAX_LOOP_LENGTH): Define.
(DEF_VEC_P (loop_info)): New.
(DEF_VEC_ALLOC_P (loop_info,heap)): New.
(struct loop_info): New.
(loop_info): New typedef.
(struct loop_work): New.
(loop_work): New typedef.
(DEF_VEC_O (loop_work)): New.
(DEF_VEC_ALLOC_O (loop_work,heap)): New.
(bfin_dump_loops): New.
(bfin_bb_in_loop): New.
(bfin_scan_loop): New.
(bfin_optimize_loop): New.
(bfin_reorg_loops): New.
(bfin_reorg): Use bfin_reorg_loops.
* config/bfin/bfin.h (FIRST_PSEUDO_REGISTER): Adjust for adding
loop registers.
(I_REGNO_P): Simplify.
(DP_REGNO_P, DPREG_P): New macros.
(REGISTER_NAMES, FIXED_REGISTERS, CALL_USED_REGISTERS,
REG_ALLOC_ORDER): Add LT0, LT1, LC0, LC1, LB0, LB1.
(enum reg_class, REG_CLASS_NAMES, REG_CLASS_CONTENTS):
Add LT_REGS, LC_REGS, LB_REGS.
(REG_CLASS_FROM_LETTER): Add 't' for LT_REGS, 'k' for LC_REGS,
'l' for LB_REGS.
(REGNO_REG_CLASS): Deal with loop registers.
* config/bfin/bfin.md: Add comment for 't', 'k', 'l' constraint
letters.
(REG_LT0, REG_LT1, REG_LC0, REG_LC1, REG_LB0, REG_LB1):
New constants for loop registers.
(UNSPEC_LSETUP_END): New.
(seq_insns): New define_attr. Set it for appropriate insns.
(movsi_insn): Add alternatives for move from/to
loop count registers.
(doloop_end): New define_expand.
(loop_end): New define_insn.
(define_split for bad doloop_end): New.
(lsetup_with_autoinit): New define_insn.
(lsetup_without_autoinit): New define_insn.
(rep_movsi, rep_movhi): Clobber LT1, LC1, LB1.
* config/bfin/predicates.md (lc_register_operand): New.
(lt_register_operand): New.
(lb_register_operand): New.
(nondp_register_operand): New.
(nondp_reg_or_memory_operand): New.
* doc/md.texi: Document Blackfin new 't', 'k', 'l' constraint letters.
From-SVN: r114274
2006-05-31 18:46:15 +02:00
|
|
|
|
(clobber (match_scratch:HI 5 "=&d"))
|
|
|
|
|
(clobber (reg:SI REG_LT1))
|
|
|
|
|
(clobber (reg:SI REG_LC1))
|
|
|
|
|
(clobber (reg:SI REG_LB1))]
|
2005-04-05 13:26:48 +02:00
|
|
|
|
""
|
2005-11-11 18:58:31 +01:00
|
|
|
|
"%5 = [%4++]; lsetup (1f, 1f) LC1 = %2; 1: MNOP || [%3++] = %5 || %5 = [%4++]; [%3++] = %5;"
|
2005-04-05 13:26:48 +02:00
|
|
|
|
[(set_attr "type" "misc")
|
bfin-protos.h (bfin_hardware_loop): Declare.
* config/bfin/bfin-protos.h (bfin_hardware_loop): Declare.
* config/bfin/bfin.c (basic-block.h): Include.
(struct machine_function): New.
(bfin_init_machine_status): New.
(override_options): Initialize init_machine_status.
(bfin_hardware_loop): New.
(MAX_LOOP_DEPTH, MAX_LOOP_LENGTH): Define.
(DEF_VEC_P (loop_info)): New.
(DEF_VEC_ALLOC_P (loop_info,heap)): New.
(struct loop_info): New.
(loop_info): New typedef.
(struct loop_work): New.
(loop_work): New typedef.
(DEF_VEC_O (loop_work)): New.
(DEF_VEC_ALLOC_O (loop_work,heap)): New.
(bfin_dump_loops): New.
(bfin_bb_in_loop): New.
(bfin_scan_loop): New.
(bfin_optimize_loop): New.
(bfin_reorg_loops): New.
(bfin_reorg): Use bfin_reorg_loops.
* config/bfin/bfin.h (FIRST_PSEUDO_REGISTER): Adjust for adding
loop registers.
(I_REGNO_P): Simplify.
(DP_REGNO_P, DPREG_P): New macros.
(REGISTER_NAMES, FIXED_REGISTERS, CALL_USED_REGISTERS,
REG_ALLOC_ORDER): Add LT0, LT1, LC0, LC1, LB0, LB1.
(enum reg_class, REG_CLASS_NAMES, REG_CLASS_CONTENTS):
Add LT_REGS, LC_REGS, LB_REGS.
(REG_CLASS_FROM_LETTER): Add 't' for LT_REGS, 'k' for LC_REGS,
'l' for LB_REGS.
(REGNO_REG_CLASS): Deal with loop registers.
* config/bfin/bfin.md: Add comment for 't', 'k', 'l' constraint
letters.
(REG_LT0, REG_LT1, REG_LC0, REG_LC1, REG_LB0, REG_LB1):
New constants for loop registers.
(UNSPEC_LSETUP_END): New.
(seq_insns): New define_attr. Set it for appropriate insns.
(movsi_insn): Add alternatives for move from/to
loop count registers.
(doloop_end): New define_expand.
(loop_end): New define_insn.
(define_split for bad doloop_end): New.
(lsetup_with_autoinit): New define_insn.
(lsetup_without_autoinit): New define_insn.
(rep_movsi, rep_movhi): Clobber LT1, LC1, LB1.
* config/bfin/predicates.md (lc_register_operand): New.
(lt_register_operand): New.
(lb_register_operand): New.
(nondp_register_operand): New.
(nondp_reg_or_memory_operand): New.
* doc/md.texi: Document Blackfin new 't', 'k', 'l' constraint letters.
From-SVN: r114274
2006-05-31 18:46:15 +02:00
|
|
|
|
(set_attr "length" "16")
|
|
|
|
|
(set_attr "seq_insns" "multi")])
|
2005-04-05 13:26:48 +02:00
|
|
|
|
|
|
|
|
|
(define_insn "rep_movhi"
|
|
|
|
|
[(set (match_operand:SI 0 "register_operand" "=&a")
|
|
|
|
|
(plus:SI (plus:SI (match_operand:SI 3 "register_operand" "0")
|
|
|
|
|
(ashift:SI (match_operand:SI 2 "register_operand" "a")
|
|
|
|
|
(const_int 1)))
|
|
|
|
|
(const_int 2)))
|
|
|
|
|
(set (match_operand:SI 1 "register_operand" "=&b")
|
|
|
|
|
(plus:SI (plus:SI (match_operand:SI 4 "register_operand" "1")
|
|
|
|
|
(ashift:SI (match_dup 2) (const_int 1)))
|
|
|
|
|
(const_int 2)))
|
|
|
|
|
(set (mem:BLK (match_dup 3))
|
|
|
|
|
(mem:BLK (match_dup 4)))
|
|
|
|
|
(use (match_dup 2))
|
bfin-protos.h (bfin_hardware_loop): Declare.
* config/bfin/bfin-protos.h (bfin_hardware_loop): Declare.
* config/bfin/bfin.c (basic-block.h): Include.
(struct machine_function): New.
(bfin_init_machine_status): New.
(override_options): Initialize init_machine_status.
(bfin_hardware_loop): New.
(MAX_LOOP_DEPTH, MAX_LOOP_LENGTH): Define.
(DEF_VEC_P (loop_info)): New.
(DEF_VEC_ALLOC_P (loop_info,heap)): New.
(struct loop_info): New.
(loop_info): New typedef.
(struct loop_work): New.
(loop_work): New typedef.
(DEF_VEC_O (loop_work)): New.
(DEF_VEC_ALLOC_O (loop_work,heap)): New.
(bfin_dump_loops): New.
(bfin_bb_in_loop): New.
(bfin_scan_loop): New.
(bfin_optimize_loop): New.
(bfin_reorg_loops): New.
(bfin_reorg): Use bfin_reorg_loops.
* config/bfin/bfin.h (FIRST_PSEUDO_REGISTER): Adjust for adding
loop registers.
(I_REGNO_P): Simplify.
(DP_REGNO_P, DPREG_P): New macros.
(REGISTER_NAMES, FIXED_REGISTERS, CALL_USED_REGISTERS,
REG_ALLOC_ORDER): Add LT0, LT1, LC0, LC1, LB0, LB1.
(enum reg_class, REG_CLASS_NAMES, REG_CLASS_CONTENTS):
Add LT_REGS, LC_REGS, LB_REGS.
(REG_CLASS_FROM_LETTER): Add 't' for LT_REGS, 'k' for LC_REGS,
'l' for LB_REGS.
(REGNO_REG_CLASS): Deal with loop registers.
* config/bfin/bfin.md: Add comment for 't', 'k', 'l' constraint
letters.
(REG_LT0, REG_LT1, REG_LC0, REG_LC1, REG_LB0, REG_LB1):
New constants for loop registers.
(UNSPEC_LSETUP_END): New.
(seq_insns): New define_attr. Set it for appropriate insns.
(movsi_insn): Add alternatives for move from/to
loop count registers.
(doloop_end): New define_expand.
(loop_end): New define_insn.
(define_split for bad doloop_end): New.
(lsetup_with_autoinit): New define_insn.
(lsetup_without_autoinit): New define_insn.
(rep_movsi, rep_movhi): Clobber LT1, LC1, LB1.
* config/bfin/predicates.md (lc_register_operand): New.
(lt_register_operand): New.
(lb_register_operand): New.
(nondp_register_operand): New.
(nondp_reg_or_memory_operand): New.
* doc/md.texi: Document Blackfin new 't', 'k', 'l' constraint letters.
From-SVN: r114274
2006-05-31 18:46:15 +02:00
|
|
|
|
(clobber (match_scratch:HI 5 "=&d"))
|
|
|
|
|
(clobber (reg:SI REG_LT1))
|
|
|
|
|
(clobber (reg:SI REG_LC1))
|
|
|
|
|
(clobber (reg:SI REG_LB1))]
|
2005-04-05 13:26:48 +02:00
|
|
|
|
""
|
2005-11-11 18:58:31 +01:00
|
|
|
|
"%h5 = W[%4++]; lsetup (1f, 1f) LC1 = %2; 1: MNOP || W [%3++] = %5 || %h5 = W [%4++]; W [%3++] = %5;"
|
2005-04-05 13:26:48 +02:00
|
|
|
|
[(set_attr "type" "misc")
|
bfin-protos.h (bfin_hardware_loop): Declare.
* config/bfin/bfin-protos.h (bfin_hardware_loop): Declare.
* config/bfin/bfin.c (basic-block.h): Include.
(struct machine_function): New.
(bfin_init_machine_status): New.
(override_options): Initialize init_machine_status.
(bfin_hardware_loop): New.
(MAX_LOOP_DEPTH, MAX_LOOP_LENGTH): Define.
(DEF_VEC_P (loop_info)): New.
(DEF_VEC_ALLOC_P (loop_info,heap)): New.
(struct loop_info): New.
(loop_info): New typedef.
(struct loop_work): New.
(loop_work): New typedef.
(DEF_VEC_O (loop_work)): New.
(DEF_VEC_ALLOC_O (loop_work,heap)): New.
(bfin_dump_loops): New.
(bfin_bb_in_loop): New.
(bfin_scan_loop): New.
(bfin_optimize_loop): New.
(bfin_reorg_loops): New.
(bfin_reorg): Use bfin_reorg_loops.
* config/bfin/bfin.h (FIRST_PSEUDO_REGISTER): Adjust for adding
loop registers.
(I_REGNO_P): Simplify.
(DP_REGNO_P, DPREG_P): New macros.
(REGISTER_NAMES, FIXED_REGISTERS, CALL_USED_REGISTERS,
REG_ALLOC_ORDER): Add LT0, LT1, LC0, LC1, LB0, LB1.
(enum reg_class, REG_CLASS_NAMES, REG_CLASS_CONTENTS):
Add LT_REGS, LC_REGS, LB_REGS.
(REG_CLASS_FROM_LETTER): Add 't' for LT_REGS, 'k' for LC_REGS,
'l' for LB_REGS.
(REGNO_REG_CLASS): Deal with loop registers.
* config/bfin/bfin.md: Add comment for 't', 'k', 'l' constraint
letters.
(REG_LT0, REG_LT1, REG_LC0, REG_LC1, REG_LB0, REG_LB1):
New constants for loop registers.
(UNSPEC_LSETUP_END): New.
(seq_insns): New define_attr. Set it for appropriate insns.
(movsi_insn): Add alternatives for move from/to
loop count registers.
(doloop_end): New define_expand.
(loop_end): New define_insn.
(define_split for bad doloop_end): New.
(lsetup_with_autoinit): New define_insn.
(lsetup_without_autoinit): New define_insn.
(rep_movsi, rep_movhi): Clobber LT1, LC1, LB1.
* config/bfin/predicates.md (lc_register_operand): New.
(lt_register_operand): New.
(lb_register_operand): New.
(nondp_register_operand): New.
(nondp_reg_or_memory_operand): New.
* doc/md.texi: Document Blackfin new 't', 'k', 'l' constraint letters.
From-SVN: r114274
2006-05-31 18:46:15 +02:00
|
|
|
|
(set_attr "length" "16")
|
|
|
|
|
(set_attr "seq_insns" "multi")])
|
2005-04-05 13:26:48 +02:00
|
|
|
|
|
builtins.c (get_memory_rtx): Fix comment.
2019-06-27 Aaron Sawdey <acsawdey@linux.ibm.com>
* builtins.c (get_memory_rtx): Fix comment.
* optabs.def (movmem_optab): Change to cpymem_optab.
* expr.c (emit_block_move_via_cpymem): Change movmem to cpymem.
(emit_block_move_hints): Change movmem to cpymem.
* defaults.h: Change movmem to cpymem.
* targhooks.c (get_move_ratio): Change movmem to cpymem.
(default_use_by_pieces_infrastructure_p): Ditto.
* config/aarch64/aarch64-protos.h: Change movmem to cpymem.
* config/aarch64/aarch64.c (aarch64_expand_movmem): Change movmem
to cpymem.
* config/aarch64/aarch64.h: Change movmem to cpymem.
* config/aarch64/aarch64.md (movmemdi): Change name to cpymemdi.
* config/alpha/alpha.h: Change movmem to cpymem in comment.
* config/alpha/alpha.md (movmemqi, movmemdi, *movmemdi_1): Change
movmem to cpymem.
* config/arc/arc-protos.h: Change movmem to cpymem.
* config/arc/arc.c (arc_expand_movmem): Change movmem to cpymem.
* config/arc/arc.h: Change movmem to cpymem in comment.
* config/arc/arc.md (movmemsi): Change movmem to cpymem.
* config/arm/arm-protos.h: Change movmem to cpymem in names.
* config/arm/arm.c (arm_movmemqi_unaligned, arm_gen_movmemqi,
gen_movmem_ldrd_strd, thumb_expand_movmemqi) Change movmem to cpymem.
* config/arm/arm.md (movmemqi): Change movmem to cpymem.
* config/arm/thumb1.md (movmem12b, movmem8b): Change movmem to cpymem.
* config/avr/avr-protos.h: Change movmem to cpymem.
* config/avr/avr.c (avr_adjust_insn_length, avr_emit_movmemhi,
avr_out_movmem): Change movmem to cpymem.
* config/avr/avr.md (movmemhi, movmem_<mode>, movmemx_<mode>):
Change movmem to cpymem.
* config/bfin/bfin-protos.h: Change movmem to cpymem.
* config/bfin/bfin.c (single_move_for_movmem, bfin_expand_movmem):
Change movmem to cpymem.
* config/bfin/bfin.h: Change movmem to cpymem in comment.
* config/bfin/bfin.md (movmemsi): Change name to cpymemsi.
* config/c6x/c6x-protos.h: Change movmem to cpymem.
* config/c6x/c6x.c (c6x_expand_movmem): Change movmem to cpymem.
* config/c6x/c6x.md (movmemsi): Change name to cpymemsi.
* config/frv/frv.md (movmemsi): Change name to cpymemsi.
* config/ft32/ft32.md (movmemsi): Change name to cpymemsi.
* config/h8300/h8300.md (movmemsi): Change name to cpymemsi.
* config/i386/i386-expand.c (expand_set_or_movmem_via_loop,
expand_set_or_movmem_via_rep, expand_movmem_epilogue,
expand_setmem_epilogue_via_loop, expand_set_or_cpymem_prologue,
expand_small_cpymem_or_setmem,
expand_set_or_cpymem_prologue_epilogue_by_misaligned_moves,
expand_set_or_cpymem_constant_prologue,
ix86_expand_set_or_cpymem): Change movmem to cpymem.
* config/i386/i386-protos.h: Change movmem to cpymem.
* config/i386/i386.h: Change movmem to cpymem in comment.
* config/i386/i386.md (movmem<mode>): Change name to cpymem.
(setmem<mode>): Change expansion function name.
* config/lm32/lm32.md (movmemsi): Change name to cpymemsi.
* config/m32c/blkmov.md (movmemhi, movmemhi_bhi_op, movmemhi_bpsi_op,
movmemhi_whi_op, movmemhi_wpsi_op): Change movmem to cpymem.
* config/m32c/m32c-protos.h: Change movmem to cpymem.
* config/m32c/m32c.c (m32c_expand_movmemhi): Change movmem to cpymem.
* config/m32r/m32r.c (m32r_expand_block_move): Change movmem to cpymem.
* config/m32r/m32r.md (movmemsi, movmemsi_internal): Change movmem
to cpymem.
* config/mcore/mcore.md (movmemsi): Change name to cpymemsi.
* config/microblaze/microblaze.c: Change movmem to cpymem in comment.
* config/microblaze/microblaze.md (movmemsi): Change name to cpymemsi.
* config/mips/mips.c (mips_use_by_pieces_infrastructure_p):
Change movmem to cpymem.
* config/mips/mips.h: Change movmem to cpymem.
* config/mips/mips.md (movmemsi): Change name to cpymemsi.
* config/nds32/nds32-memory-manipulation.c
(nds32_expand_movmemsi_loop_unknown_size,
nds32_expand_movmemsi_loop_known_size, nds32_expand_movmemsi_loop,
nds32_expand_movmemsi_unroll,
nds32_expand_movmemsi): Change movmem to cpymem.
* config/nds32/nds32-multiple.md (movmemsi): Change name to cpymemsi.
* config/nds32/nds32-protos.h: Change movmem to cpymem.
* config/pa/pa.c (compute_movmem_length): Change movmem to cpymem.
(pa_adjust_insn_length): Change call to compute_movmem_length.
* config/pa/pa.md (movmemsi, movmemsi_prereload, movmemsi_postreload,
movmemdi, movmemdi_prereload,
movmemdi_postreload): Change movmem to cpymem.
* config/pdp11/pdp11.md (movmemhi, movmemhi1,
movmemhi_nocc, UNSPEC_MOVMEM): Change movmem to cpymem.
* config/riscv/riscv.c: Change movmem to cpymem in comment.
* config/riscv/riscv.h: Change movmem to cpymem.
* config/riscv/riscv.md: (movmemsi) Change name to cpymemsi.
* config/rs6000/rs6000.md: (movmemsi) Change name to cpymemsi.
* config/rx/rx.md: (UNSPEC_MOVMEM, movmemsi, rx_movmem): Change
movmem to cpymem.
* config/s390/s390-protos.h: Change movmem to cpymem.
* config/s390/s390.c (s390_expand_movmem, s390_expand_setmem,
s390_expand_insv): Change movmem to cpymem.
* config/s390/s390.md (movmem<mode>, movmem_short, *movmem_short,
movmem_long, *movmem_long, *movmem_long_31z): Change movmem to cpymem.
* config/sh/sh.md (movmemsi): Change name to cpymemsi.
* config/sparc/sparc.h: Change movmem to cpymem in comment.
* config/vax/vax-protos.h (vax_output_movmemsi): Remove prototype
for nonexistent function.
* config/vax/vax.h: Change movmem to cpymem in comment.
* config/vax/vax.md (movmemhi, movmemhi1): Change movmem to cpymem.
* config/visium/visium.h: Change movmem to cpymem in comment.
* config/visium/visium.md (movmemsi): Change name to cpymemsi.
* config/xtensa/xtensa.md (movmemsi): Change name to cpymemsi.
* doc/md.texi: Change movmem to cpymem and update description to match.
* doc/rtl.texi: Change movmem to cpymem.
* target.def (use_by_pieces_infrastructure_p): Change movmem to cpymem.
* doc/tm.texi: Regenerate.
From-SVN: r272755
2019-06-27 16:45:36 +02:00
|
|
|
|
(define_expand "cpymemsi"
|
2005-04-05 13:26:48 +02:00
|
|
|
|
[(match_operand:BLK 0 "general_operand" "")
|
|
|
|
|
(match_operand:BLK 1 "general_operand" "")
|
|
|
|
|
(match_operand:SI 2 "const_int_operand" "")
|
|
|
|
|
(match_operand:SI 3 "const_int_operand" "")]
|
|
|
|
|
""
|
|
|
|
|
{
|
builtins.c (get_memory_rtx): Fix comment.
2019-06-27 Aaron Sawdey <acsawdey@linux.ibm.com>
* builtins.c (get_memory_rtx): Fix comment.
* optabs.def (movmem_optab): Change to cpymem_optab.
* expr.c (emit_block_move_via_cpymem): Change movmem to cpymem.
(emit_block_move_hints): Change movmem to cpymem.
* defaults.h: Change movmem to cpymem.
* targhooks.c (get_move_ratio): Change movmem to cpymem.
(default_use_by_pieces_infrastructure_p): Ditto.
* config/aarch64/aarch64-protos.h: Change movmem to cpymem.
* config/aarch64/aarch64.c (aarch64_expand_movmem): Change movmem
to cpymem.
* config/aarch64/aarch64.h: Change movmem to cpymem.
* config/aarch64/aarch64.md (movmemdi): Change name to cpymemdi.
* config/alpha/alpha.h: Change movmem to cpymem in comment.
* config/alpha/alpha.md (movmemqi, movmemdi, *movmemdi_1): Change
movmem to cpymem.
* config/arc/arc-protos.h: Change movmem to cpymem.
* config/arc/arc.c (arc_expand_movmem): Change movmem to cpymem.
* config/arc/arc.h: Change movmem to cpymem in comment.
* config/arc/arc.md (movmemsi): Change movmem to cpymem.
* config/arm/arm-protos.h: Change movmem to cpymem in names.
* config/arm/arm.c (arm_movmemqi_unaligned, arm_gen_movmemqi,
gen_movmem_ldrd_strd, thumb_expand_movmemqi) Change movmem to cpymem.
* config/arm/arm.md (movmemqi): Change movmem to cpymem.
* config/arm/thumb1.md (movmem12b, movmem8b): Change movmem to cpymem.
* config/avr/avr-protos.h: Change movmem to cpymem.
* config/avr/avr.c (avr_adjust_insn_length, avr_emit_movmemhi,
avr_out_movmem): Change movmem to cpymem.
* config/avr/avr.md (movmemhi, movmem_<mode>, movmemx_<mode>):
Change movmem to cpymem.
* config/bfin/bfin-protos.h: Change movmem to cpymem.
* config/bfin/bfin.c (single_move_for_movmem, bfin_expand_movmem):
Change movmem to cpymem.
* config/bfin/bfin.h: Change movmem to cpymem in comment.
* config/bfin/bfin.md (movmemsi): Change name to cpymemsi.
* config/c6x/c6x-protos.h: Change movmem to cpymem.
* config/c6x/c6x.c (c6x_expand_movmem): Change movmem to cpymem.
* config/c6x/c6x.md (movmemsi): Change name to cpymemsi.
* config/frv/frv.md (movmemsi): Change name to cpymemsi.
* config/ft32/ft32.md (movmemsi): Change name to cpymemsi.
* config/h8300/h8300.md (movmemsi): Change name to cpymemsi.
* config/i386/i386-expand.c (expand_set_or_movmem_via_loop,
expand_set_or_movmem_via_rep, expand_movmem_epilogue,
expand_setmem_epilogue_via_loop, expand_set_or_cpymem_prologue,
expand_small_cpymem_or_setmem,
expand_set_or_cpymem_prologue_epilogue_by_misaligned_moves,
expand_set_or_cpymem_constant_prologue,
ix86_expand_set_or_cpymem): Change movmem to cpymem.
* config/i386/i386-protos.h: Change movmem to cpymem.
* config/i386/i386.h: Change movmem to cpymem in comment.
* config/i386/i386.md (movmem<mode>): Change name to cpymem.
(setmem<mode>): Change expansion function name.
* config/lm32/lm32.md (movmemsi): Change name to cpymemsi.
* config/m32c/blkmov.md (movmemhi, movmemhi_bhi_op, movmemhi_bpsi_op,
movmemhi_whi_op, movmemhi_wpsi_op): Change movmem to cpymem.
* config/m32c/m32c-protos.h: Change movmem to cpymem.
* config/m32c/m32c.c (m32c_expand_movmemhi): Change movmem to cpymem.
* config/m32r/m32r.c (m32r_expand_block_move): Change movmem to cpymem.
* config/m32r/m32r.md (movmemsi, movmemsi_internal): Change movmem
to cpymem.
* config/mcore/mcore.md (movmemsi): Change name to cpymemsi.
* config/microblaze/microblaze.c: Change movmem to cpymem in comment.
* config/microblaze/microblaze.md (movmemsi): Change name to cpymemsi.
* config/mips/mips.c (mips_use_by_pieces_infrastructure_p):
Change movmem to cpymem.
* config/mips/mips.h: Change movmem to cpymem.
* config/mips/mips.md (movmemsi): Change name to cpymemsi.
* config/nds32/nds32-memory-manipulation.c
(nds32_expand_movmemsi_loop_unknown_size,
nds32_expand_movmemsi_loop_known_size, nds32_expand_movmemsi_loop,
nds32_expand_movmemsi_unroll,
nds32_expand_movmemsi): Change movmem to cpymem.
* config/nds32/nds32-multiple.md (movmemsi): Change name to cpymemsi.
* config/nds32/nds32-protos.h: Change movmem to cpymem.
* config/pa/pa.c (compute_movmem_length): Change movmem to cpymem.
(pa_adjust_insn_length): Change call to compute_movmem_length.
* config/pa/pa.md (movmemsi, movmemsi_prereload, movmemsi_postreload,
movmemdi, movmemdi_prereload,
movmemdi_postreload): Change movmem to cpymem.
* config/pdp11/pdp11.md (movmemhi, movmemhi1,
movmemhi_nocc, UNSPEC_MOVMEM): Change movmem to cpymem.
* config/riscv/riscv.c: Change movmem to cpymem in comment.
* config/riscv/riscv.h: Change movmem to cpymem.
* config/riscv/riscv.md: (movmemsi) Change name to cpymemsi.
* config/rs6000/rs6000.md: (movmemsi) Change name to cpymemsi.
* config/rx/rx.md: (UNSPEC_MOVMEM, movmemsi, rx_movmem): Change
movmem to cpymem.
* config/s390/s390-protos.h: Change movmem to cpymem.
* config/s390/s390.c (s390_expand_movmem, s390_expand_setmem,
s390_expand_insv): Change movmem to cpymem.
* config/s390/s390.md (movmem<mode>, movmem_short, *movmem_short,
movmem_long, *movmem_long, *movmem_long_31z): Change movmem to cpymem.
* config/sh/sh.md (movmemsi): Change name to cpymemsi.
* config/sparc/sparc.h: Change movmem to cpymem in comment.
* config/vax/vax-protos.h (vax_output_movmemsi): Remove prototype
for nonexistent function.
* config/vax/vax.h: Change movmem to cpymem in comment.
* config/vax/vax.md (movmemhi, movmemhi1): Change movmem to cpymem.
* config/visium/visium.h: Change movmem to cpymem in comment.
* config/visium/visium.md (movmemsi): Change name to cpymemsi.
* config/xtensa/xtensa.md (movmemsi): Change name to cpymemsi.
* doc/md.texi: Change movmem to cpymem and update description to match.
* doc/rtl.texi: Change movmem to cpymem.
* target.def (use_by_pieces_infrastructure_p): Change movmem to cpymem.
* doc/tm.texi: Regenerate.
From-SVN: r272755
2019-06-27 16:45:36 +02:00
|
|
|
|
if (bfin_expand_cpymem (operands[0], operands[1], operands[2], operands[3]))
|
2005-04-05 13:26:48 +02:00
|
|
|
|
DONE;
|
|
|
|
|
FAIL;
|
|
|
|
|
})
|
|
|
|
|
|
|
|
|
|
;; Conditional branch patterns
|
|
|
|
|
;; The Blackfin has only few condition codes: eq, lt, lte, ltu, leu
|
|
|
|
|
|
bfin.md (ror_one, [...]): New patterns.
* config/bfin/bfin.md (ror_one, rol_one, ashrdi3, ashldi3, lshrdi3):
New patterns.
(movbi): Add alternative to set CC to zero.
(compare_eq, compare_ne, compare_le, compare_lt, compare_leu,
compare_ltu): Now named patterns.
From-SVN: r101320
2005-06-25 13:52:32 +02:00
|
|
|
|
(define_insn "compare_eq"
|
2006-02-21 16:32:21 +01:00
|
|
|
|
[(set (match_operand:BI 0 "register_operand" "=C,C")
|
2005-04-05 13:26:48 +02:00
|
|
|
|
(eq:BI (match_operand:SI 1 "register_operand" "d,a")
|
2005-07-11 18:15:45 +02:00
|
|
|
|
(match_operand:SI 2 "reg_or_const_int_operand" "dKs3,aKs3")))]
|
2005-04-05 13:26:48 +02:00
|
|
|
|
""
|
|
|
|
|
"cc =%1==%2;"
|
|
|
|
|
[(set_attr "type" "compare")])
|
|
|
|
|
|
bfin.md (ror_one, [...]): New patterns.
* config/bfin/bfin.md (ror_one, rol_one, ashrdi3, ashldi3, lshrdi3):
New patterns.
(movbi): Add alternative to set CC to zero.
(compare_eq, compare_ne, compare_le, compare_lt, compare_leu,
compare_ltu): Now named patterns.
From-SVN: r101320
2005-06-25 13:52:32 +02:00
|
|
|
|
(define_insn "compare_ne"
|
2006-02-21 16:32:21 +01:00
|
|
|
|
[(set (match_operand:BI 0 "register_operand" "=C,C")
|
2005-04-05 13:26:48 +02:00
|
|
|
|
(ne:BI (match_operand:SI 1 "register_operand" "d,a")
|
2005-07-11 18:15:45 +02:00
|
|
|
|
(match_operand:SI 2 "reg_or_const_int_operand" "dKs3,aKs3")))]
|
2005-04-05 13:26:48 +02:00
|
|
|
|
"0"
|
|
|
|
|
"cc =%1!=%2;"
|
|
|
|
|
[(set_attr "type" "compare")])
|
|
|
|
|
|
bfin.md (ror_one, [...]): New patterns.
* config/bfin/bfin.md (ror_one, rol_one, ashrdi3, ashldi3, lshrdi3):
New patterns.
(movbi): Add alternative to set CC to zero.
(compare_eq, compare_ne, compare_le, compare_lt, compare_leu,
compare_ltu): Now named patterns.
From-SVN: r101320
2005-06-25 13:52:32 +02:00
|
|
|
|
(define_insn "compare_lt"
|
2006-02-21 16:32:21 +01:00
|
|
|
|
[(set (match_operand:BI 0 "register_operand" "=C,C")
|
2005-04-05 13:26:48 +02:00
|
|
|
|
(lt:BI (match_operand:SI 1 "register_operand" "d,a")
|
2005-07-11 18:15:45 +02:00
|
|
|
|
(match_operand:SI 2 "reg_or_const_int_operand" "dKs3,aKs3")))]
|
2005-04-05 13:26:48 +02:00
|
|
|
|
""
|
|
|
|
|
"cc =%1<%2;"
|
|
|
|
|
[(set_attr "type" "compare")])
|
|
|
|
|
|
bfin.md (ror_one, [...]): New patterns.
* config/bfin/bfin.md (ror_one, rol_one, ashrdi3, ashldi3, lshrdi3):
New patterns.
(movbi): Add alternative to set CC to zero.
(compare_eq, compare_ne, compare_le, compare_lt, compare_leu,
compare_ltu): Now named patterns.
From-SVN: r101320
2005-06-25 13:52:32 +02:00
|
|
|
|
(define_insn "compare_le"
|
2006-02-21 16:32:21 +01:00
|
|
|
|
[(set (match_operand:BI 0 "register_operand" "=C,C")
|
2005-04-05 13:26:48 +02:00
|
|
|
|
(le:BI (match_operand:SI 1 "register_operand" "d,a")
|
2005-07-11 18:15:45 +02:00
|
|
|
|
(match_operand:SI 2 "reg_or_const_int_operand" "dKs3,aKs3")))]
|
2005-04-05 13:26:48 +02:00
|
|
|
|
""
|
|
|
|
|
"cc =%1<=%2;"
|
|
|
|
|
[(set_attr "type" "compare")])
|
|
|
|
|
|
bfin.md (ror_one, [...]): New patterns.
* config/bfin/bfin.md (ror_one, rol_one, ashrdi3, ashldi3, lshrdi3):
New patterns.
(movbi): Add alternative to set CC to zero.
(compare_eq, compare_ne, compare_le, compare_lt, compare_leu,
compare_ltu): Now named patterns.
From-SVN: r101320
2005-06-25 13:52:32 +02:00
|
|
|
|
(define_insn "compare_leu"
|
2006-02-21 16:32:21 +01:00
|
|
|
|
[(set (match_operand:BI 0 "register_operand" "=C,C")
|
2005-04-05 13:26:48 +02:00
|
|
|
|
(leu:BI (match_operand:SI 1 "register_operand" "d,a")
|
2005-07-11 18:15:45 +02:00
|
|
|
|
(match_operand:SI 2 "reg_or_const_int_operand" "dKu3,aKu3")))]
|
2005-04-05 13:26:48 +02:00
|
|
|
|
""
|
|
|
|
|
"cc =%1<=%2 (iu);"
|
|
|
|
|
[(set_attr "type" "compare")])
|
|
|
|
|
|
bfin.md (ror_one, [...]): New patterns.
* config/bfin/bfin.md (ror_one, rol_one, ashrdi3, ashldi3, lshrdi3):
New patterns.
(movbi): Add alternative to set CC to zero.
(compare_eq, compare_ne, compare_le, compare_lt, compare_leu,
compare_ltu): Now named patterns.
From-SVN: r101320
2005-06-25 13:52:32 +02:00
|
|
|
|
(define_insn "compare_ltu"
|
2006-02-21 16:32:21 +01:00
|
|
|
|
[(set (match_operand:BI 0 "register_operand" "=C,C")
|
2005-04-05 13:26:48 +02:00
|
|
|
|
(ltu:BI (match_operand:SI 1 "register_operand" "d,a")
|
2005-07-11 18:15:45 +02:00
|
|
|
|
(match_operand:SI 2 "reg_or_const_int_operand" "dKu3,aKu3")))]
|
2005-04-05 13:26:48 +02:00
|
|
|
|
""
|
|
|
|
|
"cc =%1<%2 (iu);"
|
|
|
|
|
[(set_attr "type" "compare")])
|
|
|
|
|
|
rtl.def (SS_ABS): New code.
* rtl.def (SS_ABS): New code.
* config/bfin/bfin.c (print_operand): New modifier 'v'.
(enum bfin_builtins): Add BFIN_BUILTIN_SUM_2X16, BFIN_BUILTIN_ABS_1x32,
BFIN_BUILTIN_ROUND_1x32, BFIN_BUILTIN_MULT_1x32x32,
BFIN_BUILTIN_MULT_1x32x32NS, BFIN_BUILTIN_SSASHIFT_1x32.
(bfin_init_builtins): Define them.
(bdesc_1arg, bdesc_2arg): Add some of them here, ...
(bfin_expand_builtin): ... and handle the others here.
* config/bfin/bfin.md (ssabssi2, ssroundsi2, ssashiftsi3,
flag_mul_macv2hi_parts_acconly_andcc0): New patterns.
(ss_absv2hi2): Renamed from absv2hi; use ss_abs code.
(ssashiftv2hi3, ssashifthi3, lshiftv2hi3, lshifthi3): Shift count
operand is only HImode.
From-SVN: r124280
2007-04-29 15:22:04 +02:00
|
|
|
|
;; Same as above, but and CC with the overflow bit generated by the first
|
|
|
|
|
;; multiplication.
|
|
|
|
|
(define_insn "flag_mul_macv2hi_parts_acconly_andcc0"
|
|
|
|
|
[(set (match_operand:PDI 0 "register_operand" "=B,e,e")
|
|
|
|
|
(unspec:PDI [(vec_select:HI
|
|
|
|
|
(match_operand:V2HI 2 "register_operand" "d,d,d")
|
|
|
|
|
(parallel [(match_operand 4 "const01_operand" "P0P1,P0P1,P0P1")]))
|
|
|
|
|
(vec_select:HI
|
|
|
|
|
(match_operand:V2HI 3 "register_operand" "d,d,d")
|
|
|
|
|
(parallel [(match_operand 6 "const01_operand" "P0P1,P0P1,P0P1")]))
|
|
|
|
|
(match_operand 10 "const_int_operand" "PB,PA,PA")]
|
|
|
|
|
UNSPEC_MUL_WITH_FLAG))
|
|
|
|
|
(set (match_operand:PDI 1 "register_operand" "=B,e,e")
|
|
|
|
|
(unspec:PDI [(vec_select:HI
|
|
|
|
|
(match_dup 2)
|
|
|
|
|
(parallel [(match_operand 5 "const01_operand" "P0P1,P0P1,P0P1")]))
|
|
|
|
|
(vec_select:HI
|
|
|
|
|
(match_dup 3)
|
|
|
|
|
(parallel [(match_operand 7 "const01_operand" "P0P1,P0P1,P0P1")]))
|
|
|
|
|
(match_operand:PDI 8 "register_operand" "1,1,1")
|
|
|
|
|
(match_operand 9 "const01_operand" "P0P1,P0P1,P0P1")
|
|
|
|
|
(match_operand 11 "const_int_operand" "PA,PB,PA")]
|
|
|
|
|
UNSPEC_MAC_WITH_FLAG))
|
|
|
|
|
(set (reg:BI REG_CC)
|
|
|
|
|
(and:BI (reg:BI REG_CC)
|
|
|
|
|
(unspec:BI [(vec_select:HI (match_dup 2) (parallel [(match_dup 4)]))
|
|
|
|
|
(vec_select:HI (match_dup 3) (parallel [(match_dup 6)]))
|
|
|
|
|
(match_dup 10)]
|
|
|
|
|
UNSPEC_MUL_WITH_FLAG)))]
|
|
|
|
|
"MACFLAGS_MATCH_P (INTVAL (operands[10]), INTVAL (operands[11]))"
|
|
|
|
|
{
|
|
|
|
|
rtx xops[6];
|
|
|
|
|
const char *templates[] = {
|
|
|
|
|
"%0 = %h2 * %h3, %1 %b4 %h2 * %h3 %M5;\n\tCC &= %v0;",
|
|
|
|
|
"%0 = %d2 * %h3, %1 %b4 %h2 * %h3 %M5;\n\tCC &= %v0;",
|
|
|
|
|
"%0 = %h2 * %h3, %1 %b4 %d2 * %h3 %M5;\n\tCC &= %v0;",
|
|
|
|
|
"%0 = %d2 * %h3, %1 %b4 %d2 * %h3 %M5;\n\tCC &= %v0;",
|
|
|
|
|
"%0 = %h2 * %d3, %1 %b4 %h2 * %h3 %M5;\n\tCC &= %v0;",
|
|
|
|
|
"%0 = %d2 * %d3, %1 %b4 %h2 * %h3 %M5;\n\tCC &= %v0;",
|
|
|
|
|
"%0 = %h2 * %d3, %1 %b4 %d2 * %h3 %M5;\n\tCC &= %v0;",
|
|
|
|
|
"%0 = %d2 * %d3, %1 %b4 %d2 * %h3 %M5;\n\tCC &= %v0;",
|
|
|
|
|
"%0 = %h2 * %h3, %1 %b4 %h2 * %d3 %M5;\n\tCC &= %v0;",
|
|
|
|
|
"%0 = %d2 * %h3, %1 %b4 %h2 * %d3 %M5;\n\tCC &= %v0;",
|
|
|
|
|
"%0 = %h2 * %h3, %1 %b4 %d2 * %d3 %M5;\n\tCC &= %v0;",
|
|
|
|
|
"%0 = %d2 * %h3, %1 %b4 %d2 * %d3 %M5;\n\tCC &= %v0;",
|
|
|
|
|
"%0 = %h2 * %d3, %1 %b4 %h2 * %d3 %M5;\n\tCC &= %v0;",
|
|
|
|
|
"%0 = %d2 * %d3, %1 %b4 %h2 * %d3 %M5;\n\tCC &= %v0;",
|
|
|
|
|
"%0 = %h2 * %d3, %1 %b4 %d2 * %d3 %M5;\n\tCC &= %v0;",
|
|
|
|
|
"%0 = %d2 * %d3, %1 %b4 %d2 * %d3 %M5;\n\tCC &= %v0;" };
|
|
|
|
|
int alt = (INTVAL (operands[4]) + (INTVAL (operands[5]) << 1)
|
|
|
|
|
+ (INTVAL (operands[6]) << 2) + (INTVAL (operands[7]) << 3));
|
|
|
|
|
xops[0] = operands[0];
|
|
|
|
|
xops[1] = operands[1];
|
|
|
|
|
xops[2] = operands[2];
|
|
|
|
|
xops[3] = operands[3];
|
|
|
|
|
xops[4] = operands[9];
|
|
|
|
|
xops[5] = which_alternative == 0 ? operands[10] : operands[11];
|
|
|
|
|
output_asm_insn (templates[alt], xops);
|
|
|
|
|
return "";
|
|
|
|
|
}
|
|
|
|
|
[(set_attr "type" "misc")
|
|
|
|
|
(set_attr "length" "6")
|
|
|
|
|
(set_attr "seq_insns" "multi")])
|
2005-04-05 13:26:48 +02:00
|
|
|
|
|
2009-05-12 11:43:48 +02:00
|
|
|
|
(define_expand "cbranchsi4"
|
|
|
|
|
[(set (pc)
|
|
|
|
|
(if_then_else (match_operator 0 "ordered_comparison_operator"
|
|
|
|
|
[(match_operand:SI 1 "register_operand" "")
|
|
|
|
|
(match_operand:SI 2 "reg_or_const_int_operand" "")])
|
|
|
|
|
(label_ref (match_operand 3 "" ""))
|
|
|
|
|
(pc)))]
|
2005-04-05 13:26:48 +02:00
|
|
|
|
""
|
|
|
|
|
{
|
2009-05-12 11:43:48 +02:00
|
|
|
|
rtx bi_compare = bfin_gen_compare (operands[0], SImode);
|
|
|
|
|
emit_jump_insn (gen_cbranchbi4 (bi_compare, bfin_cc_rtx, CONST0_RTX (BImode),
|
|
|
|
|
operands[3]));
|
|
|
|
|
DONE;
|
2005-04-05 13:26:48 +02:00
|
|
|
|
})
|
|
|
|
|
|
|
|
|
|
(define_insn "cbranchbi4"
|
|
|
|
|
[(set (pc)
|
|
|
|
|
(if_then_else
|
2009-05-12 11:43:48 +02:00
|
|
|
|
(match_operator 0 "bfin_bimode_comparison_operator"
|
2006-02-21 16:32:21 +01:00
|
|
|
|
[(match_operand:BI 1 "register_operand" "C")
|
2005-04-05 13:26:48 +02:00
|
|
|
|
(match_operand:BI 2 "immediate_operand" "P0")])
|
|
|
|
|
(label_ref (match_operand 3 "" ""))
|
|
|
|
|
(pc)))]
|
|
|
|
|
""
|
|
|
|
|
{
|
|
|
|
|
asm_conditional_branch (insn, operands, 0, 0);
|
|
|
|
|
return "";
|
|
|
|
|
}
|
|
|
|
|
[(set_attr "type" "brcc")])
|
|
|
|
|
|
|
|
|
|
;; Special cbranch patterns to deal with the speculative load problem - see
|
|
|
|
|
;; bfin_reorg for details.
|
|
|
|
|
|
|
|
|
|
(define_insn "cbranch_predicted_taken"
|
|
|
|
|
[(set (pc)
|
|
|
|
|
(if_then_else
|
2009-05-12 11:43:48 +02:00
|
|
|
|
(match_operator 0 "bfin_bimode_comparison_operator"
|
2006-02-21 16:32:21 +01:00
|
|
|
|
[(match_operand:BI 1 "register_operand" "C")
|
2005-04-05 13:26:48 +02:00
|
|
|
|
(match_operand:BI 2 "immediate_operand" "P0")])
|
|
|
|
|
(label_ref (match_operand 3 "" ""))
|
|
|
|
|
(pc)))
|
|
|
|
|
(unspec [(const_int 0)] UNSPEC_CBRANCH_TAKEN)]
|
|
|
|
|
""
|
|
|
|
|
{
|
|
|
|
|
asm_conditional_branch (insn, operands, 0, 1);
|
|
|
|
|
return "";
|
|
|
|
|
}
|
|
|
|
|
[(set_attr "type" "brcc")])
|
|
|
|
|
|
|
|
|
|
(define_insn "cbranch_with_nops"
|
|
|
|
|
[(set (pc)
|
|
|
|
|
(if_then_else
|
2009-05-12 11:43:48 +02:00
|
|
|
|
(match_operator 0 "bfin_bimode_comparison_operator"
|
2006-02-21 16:32:21 +01:00
|
|
|
|
[(match_operand:BI 1 "register_operand" "C")
|
2005-04-05 13:26:48 +02:00
|
|
|
|
(match_operand:BI 2 "immediate_operand" "P0")])
|
|
|
|
|
(label_ref (match_operand 3 "" ""))
|
|
|
|
|
(pc)))
|
|
|
|
|
(unspec [(match_operand 4 "immediate_operand" "")] UNSPEC_CBRANCH_NOPS)]
|
|
|
|
|
"reload_completed"
|
|
|
|
|
{
|
|
|
|
|
asm_conditional_branch (insn, operands, INTVAL (operands[4]), 0);
|
|
|
|
|
return "";
|
|
|
|
|
}
|
|
|
|
|
[(set_attr "type" "brcc")
|
2008-09-10 15:28:34 +02:00
|
|
|
|
(set_attr "length" "8")])
|
2005-04-05 13:26:48 +02:00
|
|
|
|
|
2009-05-12 11:43:48 +02:00
|
|
|
|
;; setcc insns.
|
2005-04-05 13:26:48 +02:00
|
|
|
|
|
2009-05-12 11:43:48 +02:00
|
|
|
|
(define_expand "cstorebi4"
|
|
|
|
|
[(set (match_dup 4)
|
|
|
|
|
(match_operator:BI 1 "bfin_bimode_comparison_operator"
|
|
|
|
|
[(match_operand:BI 2 "register_operand" "")
|
|
|
|
|
(match_operand:BI 3 "reg_or_const_int_operand" "")]))
|
2005-04-05 13:26:48 +02:00
|
|
|
|
(set (match_operand:SI 0 "register_operand" "")
|
2009-05-12 11:43:48 +02:00
|
|
|
|
(ne:SI (match_dup 4) (const_int 0)))]
|
2005-04-05 13:26:48 +02:00
|
|
|
|
""
|
|
|
|
|
{
|
2009-05-12 11:43:48 +02:00
|
|
|
|
/* It could be expanded as a movbisi instruction, but the portable
|
|
|
|
|
alternative produces better code. */
|
|
|
|
|
if (GET_CODE (operands[1]) == NE)
|
|
|
|
|
FAIL;
|
2005-04-05 13:26:48 +02:00
|
|
|
|
|
2009-05-12 11:43:48 +02:00
|
|
|
|
operands[4] = bfin_cc_rtx;
|
2005-04-05 13:26:48 +02:00
|
|
|
|
})
|
|
|
|
|
|
2009-05-12 11:43:48 +02:00
|
|
|
|
(define_expand "cstoresi4"
|
|
|
|
|
[(set (match_operand:SI 0 "register_operand")
|
|
|
|
|
(match_operator:SI 1 "ordered_comparison_operator"
|
|
|
|
|
[(match_operand:SI 2 "register_operand" "")
|
|
|
|
|
(match_operand:SI 3 "reg_or_const_int_operand" "")]))]
|
2005-04-05 13:26:48 +02:00
|
|
|
|
""
|
|
|
|
|
{
|
2009-05-12 11:43:48 +02:00
|
|
|
|
rtx bi_compare, test;
|
2005-04-05 13:26:48 +02:00
|
|
|
|
|
2009-05-12 11:43:48 +02:00
|
|
|
|
if (!bfin_direct_comparison_operator (operands[1], SImode))
|
|
|
|
|
{
|
|
|
|
|
if (!register_operand (operands[3], SImode)
|
|
|
|
|
|| GET_CODE (operands[1]) == NE)
|
|
|
|
|
FAIL;
|
|
|
|
|
test = gen_rtx_fmt_ee (swap_condition (GET_CODE (operands[1])),
|
|
|
|
|
SImode, operands[3], operands[2]);
|
|
|
|
|
}
|
|
|
|
|
else
|
|
|
|
|
test = operands[1];
|
|
|
|
|
|
|
|
|
|
bi_compare = bfin_gen_compare (test, SImode);
|
|
|
|
|
gcc_assert (GET_CODE (bi_compare) == NE);
|
|
|
|
|
emit_insn (gen_movbisi (operands[0], bfin_cc_rtx));
|
|
|
|
|
DONE;
|
2005-04-05 13:26:48 +02:00
|
|
|
|
})
|
|
|
|
|
|
|
|
|
|
(define_insn "nop"
|
|
|
|
|
[(const_int 0)]
|
|
|
|
|
""
|
|
|
|
|
"nop;")
|
|
|
|
|
|
2007-06-12 16:35:13 +02:00
|
|
|
|
;; A nop which stays there when emitted.
|
|
|
|
|
(define_insn "forced_nop"
|
|
|
|
|
[(unspec [(const_int 0)] UNSPEC_NOP)]
|
|
|
|
|
""
|
|
|
|
|
"nop;")
|
|
|
|
|
|
rtlanal.c (note_uses): Deal with SEQUENCEs.
* rtlanal.c (note_uses): Deal with SEQUENCEs.
* config/bfin/bfin.c: Include "timevar.h".
(bfin_flag_schedule_insns2, splitting_for_sched,
bfin_flag_var_tracking): New variables.
(print_operand): Handle '%!'.
(override_options): Disable normal sched2 pass, instead set
bfin_flag_schedule_insns2 for reorg to handle it.
(output_file_start): Likewise for var-tracking.
(bfin_optimize_loop): Take some care not to stumble over SEQUENCEs.
(gen_one_bundle, bfin_gen_bundles, type_for_anomaly, trapping_loads_p):
New functions.
(bfin_reorg): Do second scheduling pass here, and call
bfin_gen_bundles. Use type_for_anomaly and trapping_loads_p instead
of examining insns directly. If bfin_flag_var_tracking, call
var-tracking pass when done with everything else.
* config/bfin/bfin.h (PRINT_OPERAND_PUNCT_VALID_P): '!' is valid.
* config/bfin/bfin.md (UNSPEC_32BIT): New constant.
(movsi_insn32): New pattern, with two new splits to create it
before the final scheduling pass.
(neghi2): Not a dsp32 insn, rather alu0.
(movbi, pushsi_insn, popsi_insn, movsi_insn, movv2hi_insn, movhi_insn,
movqi_insn, movsf_insn, movsi_insv, extendhisi2, zero_extendhisi2,
extendqihi2, extendqisi2, zero_extendqihi2, zero_extendqisi2,
mulhisi3, umulhisi3, ssadsi3, sssubsi3, smaxsi3, sminsi3, abssi2,
ssnegsi2, signbitssi2, smaxhi3, sminhi3, abshi2, ssneghi2, signbitshi2,
movhi_low2high, movhi_high2high, movhi_low2low, movhi_high2low,
movhiv2hi_low, movhiv2hi_high, composev2hi, packv2hi, movv2hi_hi,
ssaddhi3, sssubhi3, addv2hi3, ssaddv2hi3, subv2hi3, sssubv2hi3,
addsubv2hi3, subaddv2hi3, ssaddsubv2hi3, sssubaddv2hi3, sublohiv2hi3,
subhilov2hi3, sssublohiv2hi3, sssubhilov2hi3, addlohiv2hi3,
addhilov2hi3, ssaddlohiv2hi3, ssaddhilov2hi3, sminv2hi3, smaxv2hi3,
flag_mulhi, flag_mulhisi, flag_mulhisi_parts, flag_machi,
flag_machi_acconly, flag_macinithi, flag_macinit1hi, mulv2hi3,
flag_mulv2hi, flag_mulv2hi_parts, flag_macv2hi_parts,
flag_macv2hi_parts_acconly, flag_macinitv2hi_parts,
flag_macinit1v2hi_parts, mulhisi_ll, mulhisi_lh, mulhisi_hl,
mulhisi_hh, ssnegv2hi2, absv2hi2, ssashiftv2hi3, ssashifthi3,
lshiftv2hi3, lshifthi3): Use '%!' to terminate all dsp32/load/store
variants instead of ';'.
(ror_one, rol_one): Likewise. Make them dsp32 insns.
(ashlsi3_insn, ashrsi3, lshrsi3): Add dsp32 variants.
(align8, align16, align24): Now named patterns; also using '%!'.
(mnop): New insn.
From-SVN: r119534
2006-12-05 09:49:56 +01:00
|
|
|
|
(define_insn "mnop"
|
|
|
|
|
[(unspec [(const_int 0)] UNSPEC_32BIT)]
|
|
|
|
|
""
|
|
|
|
|
"mnop%!"
|
|
|
|
|
[(set_attr "type" "dsp32")])
|
|
|
|
|
|
2005-04-05 13:26:48 +02:00
|
|
|
|
;;;;;;;;;;;;;;;;;;;; CC2dreg ;;;;;;;;;;;;;;;;;;;;;;;;;
|
|
|
|
|
(define_insn "movsibi"
|
2006-02-21 16:32:21 +01:00
|
|
|
|
[(set (match_operand:BI 0 "register_operand" "=C")
|
2005-04-05 13:26:48 +02:00
|
|
|
|
(ne:BI (match_operand:SI 1 "register_operand" "d")
|
|
|
|
|
(const_int 0)))]
|
|
|
|
|
""
|
|
|
|
|
"CC = %1;"
|
|
|
|
|
[(set_attr "length" "2")])
|
|
|
|
|
|
2009-05-12 11:43:48 +02:00
|
|
|
|
(define_insn_and_split "movbisi"
|
2005-04-05 13:26:48 +02:00
|
|
|
|
[(set (match_operand:SI 0 "register_operand" "=d")
|
2006-02-21 16:32:21 +01:00
|
|
|
|
(ne:SI (match_operand:BI 1 "register_operand" "C")
|
2005-04-05 13:26:48 +02:00
|
|
|
|
(const_int 0)))]
|
|
|
|
|
""
|
2009-05-12 11:43:48 +02:00
|
|
|
|
"#"
|
|
|
|
|
""
|
|
|
|
|
[(set (match_operand:SI 0 "register_operand" "")
|
|
|
|
|
(zero_extend:SI (match_operand:BI 1 "register_operand" "")))]
|
|
|
|
|
"")
|
2005-04-05 13:26:48 +02:00
|
|
|
|
|
bfin.md (<optab>di3): Now a define_expand which expands logical operations piecewise.
* config/bfin/bfin.md (<optab>di3): Now a define_expand which expands
logical operations piecewise.
(<optab>di_zesidi_di, <optab>di_sesidi_di, negdi2, one_cmpldi2,
zero_extendsidi2, subdi_di_zesidi, subdi_zesidi_di, subdi_di_sesidi,
subdi_sesidi_di): Delete.
(add_with_carry): Produce carry in CC instead of a DREG to shorten
the generated sequence. Allow three-reg add in constraints. Rewrite
the rtl expression for carry to avoid zero_extend of a constant.
(sub_with_carry): New pattern.
(adddi3, subdi3): Change into define_expand. For subtract, generate a
different sequence not involving jumps.
(notbi): Now a named pattern.
From-SVN: r124414
2007-05-04 13:00:00 +02:00
|
|
|
|
(define_insn "notbi"
|
2006-02-21 16:32:21 +01:00
|
|
|
|
[(set (match_operand:BI 0 "register_operand" "=C")
|
|
|
|
|
(eq:BI (match_operand:BI 1 "register_operand" " 0")
|
2005-04-05 13:26:48 +02:00
|
|
|
|
(const_int 0)))]
|
|
|
|
|
""
|
|
|
|
|
"%0 = ! %0;" /* NOT CC;" */
|
|
|
|
|
[(set_attr "type" "compare")])
|
|
|
|
|
|
|
|
|
|
;; Vector and DSP insns
|
|
|
|
|
|
|
|
|
|
(define_insn ""
|
|
|
|
|
[(set (match_operand:SI 0 "register_operand" "=d")
|
|
|
|
|
(ior:SI (ashift:SI (match_operand:SI 1 "register_operand" "d")
|
|
|
|
|
(const_int 24))
|
|
|
|
|
(lshiftrt:SI (match_operand:SI 2 "register_operand" "d")
|
|
|
|
|
(const_int 8))))]
|
|
|
|
|
""
|
rtlanal.c (note_uses): Deal with SEQUENCEs.
* rtlanal.c (note_uses): Deal with SEQUENCEs.
* config/bfin/bfin.c: Include "timevar.h".
(bfin_flag_schedule_insns2, splitting_for_sched,
bfin_flag_var_tracking): New variables.
(print_operand): Handle '%!'.
(override_options): Disable normal sched2 pass, instead set
bfin_flag_schedule_insns2 for reorg to handle it.
(output_file_start): Likewise for var-tracking.
(bfin_optimize_loop): Take some care not to stumble over SEQUENCEs.
(gen_one_bundle, bfin_gen_bundles, type_for_anomaly, trapping_loads_p):
New functions.
(bfin_reorg): Do second scheduling pass here, and call
bfin_gen_bundles. Use type_for_anomaly and trapping_loads_p instead
of examining insns directly. If bfin_flag_var_tracking, call
var-tracking pass when done with everything else.
* config/bfin/bfin.h (PRINT_OPERAND_PUNCT_VALID_P): '!' is valid.
* config/bfin/bfin.md (UNSPEC_32BIT): New constant.
(movsi_insn32): New pattern, with two new splits to create it
before the final scheduling pass.
(neghi2): Not a dsp32 insn, rather alu0.
(movbi, pushsi_insn, popsi_insn, movsi_insn, movv2hi_insn, movhi_insn,
movqi_insn, movsf_insn, movsi_insv, extendhisi2, zero_extendhisi2,
extendqihi2, extendqisi2, zero_extendqihi2, zero_extendqisi2,
mulhisi3, umulhisi3, ssadsi3, sssubsi3, smaxsi3, sminsi3, abssi2,
ssnegsi2, signbitssi2, smaxhi3, sminhi3, abshi2, ssneghi2, signbitshi2,
movhi_low2high, movhi_high2high, movhi_low2low, movhi_high2low,
movhiv2hi_low, movhiv2hi_high, composev2hi, packv2hi, movv2hi_hi,
ssaddhi3, sssubhi3, addv2hi3, ssaddv2hi3, subv2hi3, sssubv2hi3,
addsubv2hi3, subaddv2hi3, ssaddsubv2hi3, sssubaddv2hi3, sublohiv2hi3,
subhilov2hi3, sssublohiv2hi3, sssubhilov2hi3, addlohiv2hi3,
addhilov2hi3, ssaddlohiv2hi3, ssaddhilov2hi3, sminv2hi3, smaxv2hi3,
flag_mulhi, flag_mulhisi, flag_mulhisi_parts, flag_machi,
flag_machi_acconly, flag_macinithi, flag_macinit1hi, mulv2hi3,
flag_mulv2hi, flag_mulv2hi_parts, flag_macv2hi_parts,
flag_macv2hi_parts_acconly, flag_macinitv2hi_parts,
flag_macinit1v2hi_parts, mulhisi_ll, mulhisi_lh, mulhisi_hl,
mulhisi_hh, ssnegv2hi2, absv2hi2, ssashiftv2hi3, ssashifthi3,
lshiftv2hi3, lshifthi3): Use '%!' to terminate all dsp32/load/store
variants instead of ';'.
(ror_one, rol_one): Likewise. Make them dsp32 insns.
(ashlsi3_insn, ashrsi3, lshrsi3): Add dsp32 variants.
(align8, align16, align24): Now named patterns; also using '%!'.
(mnop): New insn.
From-SVN: r119534
2006-12-05 09:49:56 +01:00
|
|
|
|
"%0 = ALIGN8(%1, %2)%!"
|
2005-04-05 13:26:48 +02:00
|
|
|
|
[(set_attr "type" "dsp32")])
|
|
|
|
|
|
|
|
|
|
(define_insn ""
|
|
|
|
|
[(set (match_operand:SI 0 "register_operand" "=d")
|
|
|
|
|
(ior:SI (ashift:SI (match_operand:SI 1 "register_operand" "d")
|
|
|
|
|
(const_int 16))
|
|
|
|
|
(lshiftrt:SI (match_operand:SI 2 "register_operand" "d")
|
|
|
|
|
(const_int 16))))]
|
|
|
|
|
""
|
rtlanal.c (note_uses): Deal with SEQUENCEs.
* rtlanal.c (note_uses): Deal with SEQUENCEs.
* config/bfin/bfin.c: Include "timevar.h".
(bfin_flag_schedule_insns2, splitting_for_sched,
bfin_flag_var_tracking): New variables.
(print_operand): Handle '%!'.
(override_options): Disable normal sched2 pass, instead set
bfin_flag_schedule_insns2 for reorg to handle it.
(output_file_start): Likewise for var-tracking.
(bfin_optimize_loop): Take some care not to stumble over SEQUENCEs.
(gen_one_bundle, bfin_gen_bundles, type_for_anomaly, trapping_loads_p):
New functions.
(bfin_reorg): Do second scheduling pass here, and call
bfin_gen_bundles. Use type_for_anomaly and trapping_loads_p instead
of examining insns directly. If bfin_flag_var_tracking, call
var-tracking pass when done with everything else.
* config/bfin/bfin.h (PRINT_OPERAND_PUNCT_VALID_P): '!' is valid.
* config/bfin/bfin.md (UNSPEC_32BIT): New constant.
(movsi_insn32): New pattern, with two new splits to create it
before the final scheduling pass.
(neghi2): Not a dsp32 insn, rather alu0.
(movbi, pushsi_insn, popsi_insn, movsi_insn, movv2hi_insn, movhi_insn,
movqi_insn, movsf_insn, movsi_insv, extendhisi2, zero_extendhisi2,
extendqihi2, extendqisi2, zero_extendqihi2, zero_extendqisi2,
mulhisi3, umulhisi3, ssadsi3, sssubsi3, smaxsi3, sminsi3, abssi2,
ssnegsi2, signbitssi2, smaxhi3, sminhi3, abshi2, ssneghi2, signbitshi2,
movhi_low2high, movhi_high2high, movhi_low2low, movhi_high2low,
movhiv2hi_low, movhiv2hi_high, composev2hi, packv2hi, movv2hi_hi,
ssaddhi3, sssubhi3, addv2hi3, ssaddv2hi3, subv2hi3, sssubv2hi3,
addsubv2hi3, subaddv2hi3, ssaddsubv2hi3, sssubaddv2hi3, sublohiv2hi3,
subhilov2hi3, sssublohiv2hi3, sssubhilov2hi3, addlohiv2hi3,
addhilov2hi3, ssaddlohiv2hi3, ssaddhilov2hi3, sminv2hi3, smaxv2hi3,
flag_mulhi, flag_mulhisi, flag_mulhisi_parts, flag_machi,
flag_machi_acconly, flag_macinithi, flag_macinit1hi, mulv2hi3,
flag_mulv2hi, flag_mulv2hi_parts, flag_macv2hi_parts,
flag_macv2hi_parts_acconly, flag_macinitv2hi_parts,
flag_macinit1v2hi_parts, mulhisi_ll, mulhisi_lh, mulhisi_hl,
mulhisi_hh, ssnegv2hi2, absv2hi2, ssashiftv2hi3, ssashifthi3,
lshiftv2hi3, lshifthi3): Use '%!' to terminate all dsp32/load/store
variants instead of ';'.
(ror_one, rol_one): Likewise. Make them dsp32 insns.
(ashlsi3_insn, ashrsi3, lshrsi3): Add dsp32 variants.
(align8, align16, align24): Now named patterns; also using '%!'.
(mnop): New insn.
From-SVN: r119534
2006-12-05 09:49:56 +01:00
|
|
|
|
"%0 = ALIGN16(%1, %2)%!"
|
2005-04-05 13:26:48 +02:00
|
|
|
|
[(set_attr "type" "dsp32")])
|
|
|
|
|
|
|
|
|
|
(define_insn ""
|
|
|
|
|
[(set (match_operand:SI 0 "register_operand" "=d")
|
|
|
|
|
(ior:SI (ashift:SI (match_operand:SI 1 "register_operand" "d")
|
|
|
|
|
(const_int 8))
|
|
|
|
|
(lshiftrt:SI (match_operand:SI 2 "register_operand" "d")
|
|
|
|
|
(const_int 24))))]
|
|
|
|
|
""
|
rtlanal.c (note_uses): Deal with SEQUENCEs.
* rtlanal.c (note_uses): Deal with SEQUENCEs.
* config/bfin/bfin.c: Include "timevar.h".
(bfin_flag_schedule_insns2, splitting_for_sched,
bfin_flag_var_tracking): New variables.
(print_operand): Handle '%!'.
(override_options): Disable normal sched2 pass, instead set
bfin_flag_schedule_insns2 for reorg to handle it.
(output_file_start): Likewise for var-tracking.
(bfin_optimize_loop): Take some care not to stumble over SEQUENCEs.
(gen_one_bundle, bfin_gen_bundles, type_for_anomaly, trapping_loads_p):
New functions.
(bfin_reorg): Do second scheduling pass here, and call
bfin_gen_bundles. Use type_for_anomaly and trapping_loads_p instead
of examining insns directly. If bfin_flag_var_tracking, call
var-tracking pass when done with everything else.
* config/bfin/bfin.h (PRINT_OPERAND_PUNCT_VALID_P): '!' is valid.
* config/bfin/bfin.md (UNSPEC_32BIT): New constant.
(movsi_insn32): New pattern, with two new splits to create it
before the final scheduling pass.
(neghi2): Not a dsp32 insn, rather alu0.
(movbi, pushsi_insn, popsi_insn, movsi_insn, movv2hi_insn, movhi_insn,
movqi_insn, movsf_insn, movsi_insv, extendhisi2, zero_extendhisi2,
extendqihi2, extendqisi2, zero_extendqihi2, zero_extendqisi2,
mulhisi3, umulhisi3, ssadsi3, sssubsi3, smaxsi3, sminsi3, abssi2,
ssnegsi2, signbitssi2, smaxhi3, sminhi3, abshi2, ssneghi2, signbitshi2,
movhi_low2high, movhi_high2high, movhi_low2low, movhi_high2low,
movhiv2hi_low, movhiv2hi_high, composev2hi, packv2hi, movv2hi_hi,
ssaddhi3, sssubhi3, addv2hi3, ssaddv2hi3, subv2hi3, sssubv2hi3,
addsubv2hi3, subaddv2hi3, ssaddsubv2hi3, sssubaddv2hi3, sublohiv2hi3,
subhilov2hi3, sssublohiv2hi3, sssubhilov2hi3, addlohiv2hi3,
addhilov2hi3, ssaddlohiv2hi3, ssaddhilov2hi3, sminv2hi3, smaxv2hi3,
flag_mulhi, flag_mulhisi, flag_mulhisi_parts, flag_machi,
flag_machi_acconly, flag_macinithi, flag_macinit1hi, mulv2hi3,
flag_mulv2hi, flag_mulv2hi_parts, flag_macv2hi_parts,
flag_macv2hi_parts_acconly, flag_macinitv2hi_parts,
flag_macinit1v2hi_parts, mulhisi_ll, mulhisi_lh, mulhisi_hl,
mulhisi_hh, ssnegv2hi2, absv2hi2, ssashiftv2hi3, ssashifthi3,
lshiftv2hi3, lshifthi3): Use '%!' to terminate all dsp32/load/store
variants instead of ';'.
(ror_one, rol_one): Likewise. Make them dsp32 insns.
(ashlsi3_insn, ashrsi3, lshrsi3): Add dsp32 variants.
(align8, align16, align24): Now named patterns; also using '%!'.
(mnop): New insn.
From-SVN: r119534
2006-12-05 09:49:56 +01:00
|
|
|
|
"%0 = ALIGN24(%1, %2)%!"
|
2005-04-05 13:26:48 +02:00
|
|
|
|
[(set_attr "type" "dsp32")])
|
|
|
|
|
|
|
|
|
|
;; Prologue and epilogue.
|
|
|
|
|
|
|
|
|
|
(define_expand "prologue"
|
|
|
|
|
[(const_int 1)]
|
|
|
|
|
""
|
|
|
|
|
"bfin_expand_prologue (); DONE;")
|
|
|
|
|
|
|
|
|
|
(define_expand "epilogue"
|
|
|
|
|
[(const_int 1)]
|
|
|
|
|
""
|
2007-05-08 13:59:08 +02:00
|
|
|
|
"bfin_expand_epilogue (1, 0, 0); DONE;")
|
2005-04-05 13:26:48 +02:00
|
|
|
|
|
|
|
|
|
(define_expand "sibcall_epilogue"
|
|
|
|
|
[(const_int 1)]
|
|
|
|
|
""
|
2007-05-08 13:59:08 +02:00
|
|
|
|
"bfin_expand_epilogue (0, 0, 1); DONE;")
|
2005-04-05 13:26:48 +02:00
|
|
|
|
|
|
|
|
|
(define_expand "eh_return"
|
cfgcleanup.c (try_crossjump_to_edge): Only skip past NOTE_INSN_BASIC_BLOCK.
* cfgcleanup.c (try_crossjump_to_edge): Only skip past
NOTE_INSN_BASIC_BLOCK.
* cfglayout.c (duplicate_insn_chain): Copy epilogue insn marks.
Duplicate NOTE_INSN_EPILOGUE_BEG notes.
* cfgrtl.c (can_delete_note_p): Allow NOTE_INSN_EPILOGUE_BEG
to be deleted.
* dwarf2out.c (struct cfa_loc): Change indirect field to bitfield,
add in_use field.
(add_cfi): Disable check redefining cfa away from drap.
(lookup_cfa_1): Add remember argument; handle remember/restore.
(lookup_cfa): Pass remember argument.
(cfa_remember): New.
(compute_barrier_args_size_1): Remove sibcall check.
(dwarf2out_frame_debug_def_cfa): New.
(dwarf2out_frame_debug_adjust_cfa): New.
(dwarf2out_frame_debug_cfa_offset): New.
(dwarf2out_frame_debug_cfa_register): New.
(dwarf2out_frame_debug_cfa_restore): New.
(dwarf2out_frame_debug): Handle REG_CFA_* notes.
(dwarf2out_begin_epilogue): New.
(dwarf2out_frame_debug_restore_state): New.
(dw_cfi_oprnd1_desc): Handle DW_CFA_remember_state,
DW_CFA_restore_state.
(output_cfi_directive): Likewise.
(convert_cfa_to_fb_loc_list): Likewise.
(dw_cfi_oprnd1_desc): Handle DW_CFA_restore.
* dwarf2out.h: Update.
* emit-rtl.c (try_split): Don't split RTX_FRAME_RELATED_P.
(copy_insn_1): Early out for null.
* final.c (final_scan_insn): Call dwarf2out_begin_epilogue
and dwarf2out_frame_debug_restore_state.
* function.c (prologue, epilogue, sibcall_epilogue): Remove.
(prologue_insn_hash, epilogue_insn_hash): New.
(free_after_compilation): Adjust freeing accordingly.
(record_insns): Create hash table if needed; push insns into
hash instead of array.
(maybe_copy_epilogue_insn): New.
(contains): Search hash table instead of array.
(sibcall_epilogue_contains): Remove.
(thread_prologue_and_epilogue_insns): Split eh_return insns
and mark them as epilogues.
(reposition_prologue_and_epilogue_notes): Rewrite epilogue
scanning in terms of basic blocks.
* insn-notes.def (CFA_RESTORE_STATE): New.
* jump.c (returnjump_p_1): Accept EH_RETURN.
(eh_returnjump_p_1, eh_returnjump_p): New.
* reg-notes.def (CFA_DEF_CFA, CFA_ADJUST_CFA, CFA_OFFSET,
CFA_REGISTER, CFA_RESTORE): New.
* rtl.def (EH_RETURN): New.
* rtl.h (eh_returnjump_p, maybe_copy_epilogue_insn): Declare.
* config/bfin/bfin.md (UNSPEC_VOLATILE_EH_RETURN): Remove.
(eh_return_internal): Use eh_return rtx; split w/ epilogue.
* config/i386/i386.c (gen_push): Update cfa state.
(pro_epilogue_adjust_stack): Add set_cfa argument. When true,
add a CFA_ADJUST_CFA note.
(ix86_dwarf_handle_frame_unspec): Remove.
(ix86_expand_prologue): Update cfa state.
(ix86_emit_restore_reg_using_pop): New.
(ix86_emit_restore_regs_using_pop): New.
(ix86_emit_leave): New.
(ix86_emit_restore_regs_using_mov): Add CFA_RESTORE notes.
(ix86_expand_epilogue): Add notes for unwinding the epilogue.
* config/i386/i386.h (struct machine_cfa_state): New.
(ix86_cfa_state): New.
* config/i386/i386.md (UNSPEC_EH_RETURN): Remove.
(eh_return_internal): Merge from eh_return_<mode>,
use eh_return rtx, split w/ epilogue.
From-SVN: r147995
2009-05-30 02:33:46 +02:00
|
|
|
|
[(use (match_operand:SI 0 "register_operand" ""))]
|
2005-04-05 13:26:48 +02:00
|
|
|
|
""
|
|
|
|
|
{
|
2007-06-13 19:41:07 +02:00
|
|
|
|
emit_insn (gen_eh_store_handler (EH_RETURN_HANDLER_RTX, operands[0]));
|
2006-10-12 10:52:58 +02:00
|
|
|
|
emit_jump_insn (gen_eh_return_internal ());
|
2005-04-05 13:26:48 +02:00
|
|
|
|
emit_barrier ();
|
2005-05-17 15:10:26 +02:00
|
|
|
|
DONE;
|
2005-04-05 13:26:48 +02:00
|
|
|
|
})
|
|
|
|
|
|
2007-06-13 19:41:07 +02:00
|
|
|
|
(define_insn "eh_store_handler"
|
|
|
|
|
[(unspec_volatile [(match_operand:SI 1 "register_operand" "da")]
|
|
|
|
|
UNSPEC_VOLATILE_STORE_EH_HANDLER)
|
|
|
|
|
(clobber (match_operand:SI 0 "memory_operand" "=m"))]
|
|
|
|
|
""
|
|
|
|
|
"%0 = %1%!"
|
|
|
|
|
[(set_attr "type" "mcst")])
|
|
|
|
|
|
2005-04-05 13:26:48 +02:00
|
|
|
|
(define_insn_and_split "eh_return_internal"
|
cfgcleanup.c (try_crossjump_to_edge): Only skip past NOTE_INSN_BASIC_BLOCK.
* cfgcleanup.c (try_crossjump_to_edge): Only skip past
NOTE_INSN_BASIC_BLOCK.
* cfglayout.c (duplicate_insn_chain): Copy epilogue insn marks.
Duplicate NOTE_INSN_EPILOGUE_BEG notes.
* cfgrtl.c (can_delete_note_p): Allow NOTE_INSN_EPILOGUE_BEG
to be deleted.
* dwarf2out.c (struct cfa_loc): Change indirect field to bitfield,
add in_use field.
(add_cfi): Disable check redefining cfa away from drap.
(lookup_cfa_1): Add remember argument; handle remember/restore.
(lookup_cfa): Pass remember argument.
(cfa_remember): New.
(compute_barrier_args_size_1): Remove sibcall check.
(dwarf2out_frame_debug_def_cfa): New.
(dwarf2out_frame_debug_adjust_cfa): New.
(dwarf2out_frame_debug_cfa_offset): New.
(dwarf2out_frame_debug_cfa_register): New.
(dwarf2out_frame_debug_cfa_restore): New.
(dwarf2out_frame_debug): Handle REG_CFA_* notes.
(dwarf2out_begin_epilogue): New.
(dwarf2out_frame_debug_restore_state): New.
(dw_cfi_oprnd1_desc): Handle DW_CFA_remember_state,
DW_CFA_restore_state.
(output_cfi_directive): Likewise.
(convert_cfa_to_fb_loc_list): Likewise.
(dw_cfi_oprnd1_desc): Handle DW_CFA_restore.
* dwarf2out.h: Update.
* emit-rtl.c (try_split): Don't split RTX_FRAME_RELATED_P.
(copy_insn_1): Early out for null.
* final.c (final_scan_insn): Call dwarf2out_begin_epilogue
and dwarf2out_frame_debug_restore_state.
* function.c (prologue, epilogue, sibcall_epilogue): Remove.
(prologue_insn_hash, epilogue_insn_hash): New.
(free_after_compilation): Adjust freeing accordingly.
(record_insns): Create hash table if needed; push insns into
hash instead of array.
(maybe_copy_epilogue_insn): New.
(contains): Search hash table instead of array.
(sibcall_epilogue_contains): Remove.
(thread_prologue_and_epilogue_insns): Split eh_return insns
and mark them as epilogues.
(reposition_prologue_and_epilogue_notes): Rewrite epilogue
scanning in terms of basic blocks.
* insn-notes.def (CFA_RESTORE_STATE): New.
* jump.c (returnjump_p_1): Accept EH_RETURN.
(eh_returnjump_p_1, eh_returnjump_p): New.
* reg-notes.def (CFA_DEF_CFA, CFA_ADJUST_CFA, CFA_OFFSET,
CFA_REGISTER, CFA_RESTORE): New.
* rtl.def (EH_RETURN): New.
* rtl.h (eh_returnjump_p, maybe_copy_epilogue_insn): Declare.
* config/bfin/bfin.md (UNSPEC_VOLATILE_EH_RETURN): Remove.
(eh_return_internal): Use eh_return rtx; split w/ epilogue.
* config/i386/i386.c (gen_push): Update cfa state.
(pro_epilogue_adjust_stack): Add set_cfa argument. When true,
add a CFA_ADJUST_CFA note.
(ix86_dwarf_handle_frame_unspec): Remove.
(ix86_expand_prologue): Update cfa state.
(ix86_emit_restore_reg_using_pop): New.
(ix86_emit_restore_regs_using_pop): New.
(ix86_emit_leave): New.
(ix86_emit_restore_regs_using_mov): Add CFA_RESTORE notes.
(ix86_expand_epilogue): Add notes for unwinding the epilogue.
* config/i386/i386.h (struct machine_cfa_state): New.
(ix86_cfa_state): New.
* config/i386/i386.md (UNSPEC_EH_RETURN): Remove.
(eh_return_internal): Merge from eh_return_<mode>,
use eh_return rtx, split w/ epilogue.
From-SVN: r147995
2009-05-30 02:33:46 +02:00
|
|
|
|
[(eh_return)]
|
2005-04-05 13:26:48 +02:00
|
|
|
|
""
|
|
|
|
|
"#"
|
cfgcleanup.c (try_crossjump_to_edge): Only skip past NOTE_INSN_BASIC_BLOCK.
* cfgcleanup.c (try_crossjump_to_edge): Only skip past
NOTE_INSN_BASIC_BLOCK.
* cfglayout.c (duplicate_insn_chain): Copy epilogue insn marks.
Duplicate NOTE_INSN_EPILOGUE_BEG notes.
* cfgrtl.c (can_delete_note_p): Allow NOTE_INSN_EPILOGUE_BEG
to be deleted.
* dwarf2out.c (struct cfa_loc): Change indirect field to bitfield,
add in_use field.
(add_cfi): Disable check redefining cfa away from drap.
(lookup_cfa_1): Add remember argument; handle remember/restore.
(lookup_cfa): Pass remember argument.
(cfa_remember): New.
(compute_barrier_args_size_1): Remove sibcall check.
(dwarf2out_frame_debug_def_cfa): New.
(dwarf2out_frame_debug_adjust_cfa): New.
(dwarf2out_frame_debug_cfa_offset): New.
(dwarf2out_frame_debug_cfa_register): New.
(dwarf2out_frame_debug_cfa_restore): New.
(dwarf2out_frame_debug): Handle REG_CFA_* notes.
(dwarf2out_begin_epilogue): New.
(dwarf2out_frame_debug_restore_state): New.
(dw_cfi_oprnd1_desc): Handle DW_CFA_remember_state,
DW_CFA_restore_state.
(output_cfi_directive): Likewise.
(convert_cfa_to_fb_loc_list): Likewise.
(dw_cfi_oprnd1_desc): Handle DW_CFA_restore.
* dwarf2out.h: Update.
* emit-rtl.c (try_split): Don't split RTX_FRAME_RELATED_P.
(copy_insn_1): Early out for null.
* final.c (final_scan_insn): Call dwarf2out_begin_epilogue
and dwarf2out_frame_debug_restore_state.
* function.c (prologue, epilogue, sibcall_epilogue): Remove.
(prologue_insn_hash, epilogue_insn_hash): New.
(free_after_compilation): Adjust freeing accordingly.
(record_insns): Create hash table if needed; push insns into
hash instead of array.
(maybe_copy_epilogue_insn): New.
(contains): Search hash table instead of array.
(sibcall_epilogue_contains): Remove.
(thread_prologue_and_epilogue_insns): Split eh_return insns
and mark them as epilogues.
(reposition_prologue_and_epilogue_notes): Rewrite epilogue
scanning in terms of basic blocks.
* insn-notes.def (CFA_RESTORE_STATE): New.
* jump.c (returnjump_p_1): Accept EH_RETURN.
(eh_returnjump_p_1, eh_returnjump_p): New.
* reg-notes.def (CFA_DEF_CFA, CFA_ADJUST_CFA, CFA_OFFSET,
CFA_REGISTER, CFA_RESTORE): New.
* rtl.def (EH_RETURN): New.
* rtl.h (eh_returnjump_p, maybe_copy_epilogue_insn): Declare.
* config/bfin/bfin.md (UNSPEC_VOLATILE_EH_RETURN): Remove.
(eh_return_internal): Use eh_return rtx; split w/ epilogue.
* config/i386/i386.c (gen_push): Update cfa state.
(pro_epilogue_adjust_stack): Add set_cfa argument. When true,
add a CFA_ADJUST_CFA note.
(ix86_dwarf_handle_frame_unspec): Remove.
(ix86_expand_prologue): Update cfa state.
(ix86_emit_restore_reg_using_pop): New.
(ix86_emit_restore_regs_using_pop): New.
(ix86_emit_leave): New.
(ix86_emit_restore_regs_using_mov): Add CFA_RESTORE notes.
(ix86_expand_epilogue): Add notes for unwinding the epilogue.
* config/i386/i386.h (struct machine_cfa_state): New.
(ix86_cfa_state): New.
* config/i386/i386.md (UNSPEC_EH_RETURN): Remove.
(eh_return_internal): Merge from eh_return_<mode>,
use eh_return rtx, split w/ epilogue.
From-SVN: r147995
2009-05-30 02:33:46 +02:00
|
|
|
|
"epilogue_completed"
|
2005-04-05 13:26:48 +02:00
|
|
|
|
[(const_int 1)]
|
2007-05-08 13:59:08 +02:00
|
|
|
|
"bfin_expand_epilogue (1, 1, 0); DONE;")
|
2005-04-05 13:26:48 +02:00
|
|
|
|
|
|
|
|
|
(define_insn "link"
|
|
|
|
|
[(set (mem:SI (plus:SI (reg:SI REG_SP) (const_int -4))) (reg:SI REG_RETS))
|
|
|
|
|
(set (mem:SI (plus:SI (reg:SI REG_SP) (const_int -8))) (reg:SI REG_FP))
|
|
|
|
|
(set (reg:SI REG_FP)
|
|
|
|
|
(plus:SI (reg:SI REG_SP) (const_int -8)))
|
|
|
|
|
(set (reg:SI REG_SP)
|
|
|
|
|
(plus:SI (reg:SI REG_SP) (match_operand:SI 0 "immediate_operand" "i")))]
|
|
|
|
|
""
|
|
|
|
|
"LINK %Z0;"
|
|
|
|
|
[(set_attr "length" "4")])
|
|
|
|
|
|
|
|
|
|
(define_insn "unlink"
|
|
|
|
|
[(set (reg:SI REG_FP) (mem:SI (reg:SI REG_FP)))
|
|
|
|
|
(set (reg:SI REG_RETS) (mem:SI (plus:SI (reg:SI REG_FP) (const_int 4))))
|
|
|
|
|
(set (reg:SI REG_SP) (plus:SI (reg:SI REG_FP) (const_int 8)))]
|
|
|
|
|
""
|
|
|
|
|
"UNLINK;"
|
|
|
|
|
[(set_attr "length" "4")])
|
|
|
|
|
|
|
|
|
|
;; This pattern is slightly clumsy. The stack adjust must be the final SET in
|
|
|
|
|
;; the pattern, otherwise dwarf2out becomes very confused about which reg goes
|
|
|
|
|
;; where on the stack, since it goes through all elements of the parallel in
|
|
|
|
|
;; sequence.
|
|
|
|
|
(define_insn "push_multiple"
|
|
|
|
|
[(match_parallel 0 "push_multiple_operation"
|
|
|
|
|
[(unspec [(match_operand:SI 1 "immediate_operand" "i")] UNSPEC_PUSH_MULTIPLE)])]
|
|
|
|
|
""
|
|
|
|
|
{
|
|
|
|
|
output_push_multiple (insn, operands);
|
|
|
|
|
return "";
|
|
|
|
|
})
|
|
|
|
|
|
|
|
|
|
(define_insn "pop_multiple"
|
|
|
|
|
[(match_parallel 0 "pop_multiple_operation"
|
|
|
|
|
[(set (reg:SI REG_SP)
|
|
|
|
|
(plus:SI (reg:SI REG_SP) (match_operand:SI 1 "immediate_operand" "i")))])]
|
|
|
|
|
""
|
|
|
|
|
{
|
|
|
|
|
output_pop_multiple (insn, operands);
|
|
|
|
|
return "";
|
|
|
|
|
})
|
|
|
|
|
|
|
|
|
|
(define_insn "return_internal"
|
|
|
|
|
[(return)
|
2009-09-03 17:37:28 +02:00
|
|
|
|
(use (match_operand 0 "register_operand" ""))]
|
2005-04-05 13:26:48 +02:00
|
|
|
|
"reload_completed"
|
|
|
|
|
{
|
2009-09-03 17:37:28 +02:00
|
|
|
|
switch (REGNO (operands[0]))
|
2005-04-05 13:26:48 +02:00
|
|
|
|
{
|
2009-09-03 17:37:28 +02:00
|
|
|
|
case REG_RETX:
|
2005-04-05 13:26:48 +02:00
|
|
|
|
return "rtx;";
|
2009-09-03 17:37:28 +02:00
|
|
|
|
case REG_RETN:
|
2005-04-05 13:26:48 +02:00
|
|
|
|
return "rtn;";
|
2009-09-03 17:37:28 +02:00
|
|
|
|
case REG_RETI:
|
2005-04-05 13:26:48 +02:00
|
|
|
|
return "rti;";
|
2009-09-03 17:37:28 +02:00
|
|
|
|
case REG_RETS:
|
2005-04-05 13:26:48 +02:00
|
|
|
|
return "rts;";
|
|
|
|
|
}
|
|
|
|
|
gcc_unreachable ();
|
|
|
|
|
})
|
|
|
|
|
|
2009-09-07 20:06:51 +02:00
|
|
|
|
;; When used at a location where CC contains 1, causes a speculative load
|
|
|
|
|
;; that is later cancelled. This is used for certain workarounds in
|
|
|
|
|
;; interrupt handler prologues.
|
2008-10-29 17:37:22 +01:00
|
|
|
|
(define_insn "dummy_load"
|
|
|
|
|
[(unspec_volatile [(match_operand 0 "register_operand" "a")
|
|
|
|
|
(match_operand 1 "register_operand" "C")]
|
|
|
|
|
UNSPEC_VOLATILE_DUMMY)]
|
|
|
|
|
""
|
|
|
|
|
"if cc jump 4;\n\tr7 = [%0];"
|
|
|
|
|
[(set_attr "type" "misc")
|
|
|
|
|
(set_attr "length" "4")
|
|
|
|
|
(set_attr "seq_insns" "multi")])
|
|
|
|
|
|
2009-09-07 20:06:51 +02:00
|
|
|
|
;; A placeholder insn inserted before the final scheduling pass. It is used
|
|
|
|
|
;; to improve scheduling of loads when workarounds for speculative loads are
|
|
|
|
|
;; needed, by not placing them in the first few cycles after a conditional
|
|
|
|
|
;; branch.
|
|
|
|
|
(define_insn "stall"
|
|
|
|
|
[(unspec_volatile [(match_operand 0 "const_int_operand" "P1P3")]
|
|
|
|
|
UNSPEC_VOLATILE_STALL)]
|
|
|
|
|
""
|
|
|
|
|
""
|
|
|
|
|
[(set_attr "type" "stall")])
|
|
|
|
|
|
2005-06-08 11:25:11 +02:00
|
|
|
|
(define_insn "csync"
|
|
|
|
|
[(unspec_volatile [(const_int 0)] UNSPEC_VOLATILE_CSYNC)]
|
|
|
|
|
""
|
|
|
|
|
"csync;"
|
2005-07-11 18:11:28 +02:00
|
|
|
|
[(set_attr "type" "sync")])
|
2005-06-08 11:25:11 +02:00
|
|
|
|
|
|
|
|
|
(define_insn "ssync"
|
|
|
|
|
[(unspec_volatile [(const_int 0)] UNSPEC_VOLATILE_SSYNC)]
|
|
|
|
|
""
|
|
|
|
|
"ssync;"
|
2005-07-11 18:11:28 +02:00
|
|
|
|
[(set_attr "type" "sync")])
|
2005-06-08 11:25:11 +02:00
|
|
|
|
|
2005-11-18 15:15:11 +01:00
|
|
|
|
(define_insn "trap"
|
|
|
|
|
[(trap_if (const_int 1) (const_int 3))]
|
|
|
|
|
""
|
|
|
|
|
"excpt 3;"
|
|
|
|
|
[(set_attr "type" "misc")
|
|
|
|
|
(set_attr "length" "2")])
|
|
|
|
|
|
2005-07-20 13:12:26 +02:00
|
|
|
|
(define_insn "trapifcc"
|
|
|
|
|
[(trap_if (reg:BI REG_CC) (const_int 3))]
|
|
|
|
|
""
|
|
|
|
|
"if !cc jump 4 (bp); excpt 3;"
|
|
|
|
|
[(set_attr "type" "misc")
|
bfin-protos.h (bfin_hardware_loop): Declare.
* config/bfin/bfin-protos.h (bfin_hardware_loop): Declare.
* config/bfin/bfin.c (basic-block.h): Include.
(struct machine_function): New.
(bfin_init_machine_status): New.
(override_options): Initialize init_machine_status.
(bfin_hardware_loop): New.
(MAX_LOOP_DEPTH, MAX_LOOP_LENGTH): Define.
(DEF_VEC_P (loop_info)): New.
(DEF_VEC_ALLOC_P (loop_info,heap)): New.
(struct loop_info): New.
(loop_info): New typedef.
(struct loop_work): New.
(loop_work): New typedef.
(DEF_VEC_O (loop_work)): New.
(DEF_VEC_ALLOC_O (loop_work,heap)): New.
(bfin_dump_loops): New.
(bfin_bb_in_loop): New.
(bfin_scan_loop): New.
(bfin_optimize_loop): New.
(bfin_reorg_loops): New.
(bfin_reorg): Use bfin_reorg_loops.
* config/bfin/bfin.h (FIRST_PSEUDO_REGISTER): Adjust for adding
loop registers.
(I_REGNO_P): Simplify.
(DP_REGNO_P, DPREG_P): New macros.
(REGISTER_NAMES, FIXED_REGISTERS, CALL_USED_REGISTERS,
REG_ALLOC_ORDER): Add LT0, LT1, LC0, LC1, LB0, LB1.
(enum reg_class, REG_CLASS_NAMES, REG_CLASS_CONTENTS):
Add LT_REGS, LC_REGS, LB_REGS.
(REG_CLASS_FROM_LETTER): Add 't' for LT_REGS, 'k' for LC_REGS,
'l' for LB_REGS.
(REGNO_REG_CLASS): Deal with loop registers.
* config/bfin/bfin.md: Add comment for 't', 'k', 'l' constraint
letters.
(REG_LT0, REG_LT1, REG_LC0, REG_LC1, REG_LB0, REG_LB1):
New constants for loop registers.
(UNSPEC_LSETUP_END): New.
(seq_insns): New define_attr. Set it for appropriate insns.
(movsi_insn): Add alternatives for move from/to
loop count registers.
(doloop_end): New define_expand.
(loop_end): New define_insn.
(define_split for bad doloop_end): New.
(lsetup_with_autoinit): New define_insn.
(lsetup_without_autoinit): New define_insn.
(rep_movsi, rep_movhi): Clobber LT1, LC1, LB1.
* config/bfin/predicates.md (lc_register_operand): New.
(lt_register_operand): New.
(lb_register_operand): New.
(nondp_register_operand): New.
(nondp_reg_or_memory_operand): New.
* doc/md.texi: Document Blackfin new 't', 'k', 'l' constraint letters.
From-SVN: r114274
2006-05-31 18:46:15 +02:00
|
|
|
|
(set_attr "length" "4")
|
|
|
|
|
(set_attr "seq_insns" "multi")])
|
2005-07-20 13:12:26 +02:00
|
|
|
|
|
2005-04-05 13:26:48 +02:00
|
|
|
|
;;; Vector instructions
|
|
|
|
|
|
genmodes.c (make_vector_mode): Allow making VECTOR_MODE_INT of a MODE_PARTIAL_INT mode.
* genmodes.c (make_vector_mode): Allow making VECTOR_MODE_INT of a
MODE_PARTIAL_INT mode.
* config/bfin/bfin-modes.def: Add V2PDI and V2SI.
* config/bfin/bfin.c (print_operand): Add macflag and mac/msu modifiers
for CONST_INTs.
(hard_regno_mode_ok): V2PDImode is ok for accumulators.
* config/bfin/bfin.h (CLASS_MAX_NREGS, HARD_REGNO_NREGS): Handle
V2PDImode.
* config/bfin/predicates.md (const01_operand, vec_shift_operand):
New predicates.
* config/bfin/bfin.md (UNSPEC_MUL_WITH_FLAG, UNSPEC_MAC_WITH_FLAG):
New constants.
(MACFLAG_NONE, MACFLAG_T, MACFLAG_FU, MACFLAG_TFU, MACFLAG_IS,
MACFLAG_IU, MACFLAG_W32, MACFLAG_M, MACFLAG_S2RND, MACFLAG_ISS2,
MACFLAG_IH): Likewise.
(movstricthi_1): Renamed from "*movstricthi".
(load_accumulator, load_accumulator_pair, movsi_insv, insv,
ssaddsi3, sssubsi3, ssnegsi2, signbitssi2, smaxhi3, sminhi3,
abshi2, neghi2, ssneghi2, signbitshi2, movhi_low2high,
movhi_high2high, movhi_low2low, movhi_high2low, movhiv2hi_low,
movhiv2hi_high, composev2hi, movv2hi_hi, movv2hi_hi_low,
movv2hi_hi_high, ssaddhi3, sssubhi3, ssaddv2hi3, sssubv2hi3,
addsubv2hi3, subaddv2hi3, ssaddsubv2hi3, sssubaddv2hi3,
sublohiv2hi3, subhilov2hi3, sssublohiv2hi3, sssubhilov2hi3,
addlohiv2hi3, addhilov2hi3, ssaddlohiv2hi3, ssaddhilov2hi3,
mulhisi_ll, mulhisi_lh, mulhisi_hl, mulhisi_hh, ssnegv2hi2,
ssashiftv2hi3, ssashifthi3, lshiftv2hi3, lshifthi3, packv2hi,
flag_mulhi, flag_mulhisi_parts, flag_machi, flag_machi_acconly,
flag_macinithi, flag_macinit1hi, flag_mulv2hi, flag_mulv2hi_parts,
flag_macv2hi_parts, flag_macv2hi_parts_acconly,
flag_macinitv2hi_parts, flag_macinit1v2hi_parts): New patterns.
From-SVN: r113245
2006-04-25 13:49:27 +02:00
|
|
|
|
;; First, all sorts of move variants
|
|
|
|
|
|
|
|
|
|
(define_insn "movhiv2hi_low"
|
|
|
|
|
[(set (match_operand:V2HI 0 "register_operand" "=d")
|
|
|
|
|
(vec_concat:V2HI
|
|
|
|
|
(match_operand:HI 2 "register_operand" "d")
|
|
|
|
|
(vec_select:HI (match_operand:V2HI 1 "register_operand" "0")
|
|
|
|
|
(parallel [(const_int 1)]))))]
|
|
|
|
|
""
|
rtlanal.c (note_uses): Deal with SEQUENCEs.
* rtlanal.c (note_uses): Deal with SEQUENCEs.
* config/bfin/bfin.c: Include "timevar.h".
(bfin_flag_schedule_insns2, splitting_for_sched,
bfin_flag_var_tracking): New variables.
(print_operand): Handle '%!'.
(override_options): Disable normal sched2 pass, instead set
bfin_flag_schedule_insns2 for reorg to handle it.
(output_file_start): Likewise for var-tracking.
(bfin_optimize_loop): Take some care not to stumble over SEQUENCEs.
(gen_one_bundle, bfin_gen_bundles, type_for_anomaly, trapping_loads_p):
New functions.
(bfin_reorg): Do second scheduling pass here, and call
bfin_gen_bundles. Use type_for_anomaly and trapping_loads_p instead
of examining insns directly. If bfin_flag_var_tracking, call
var-tracking pass when done with everything else.
* config/bfin/bfin.h (PRINT_OPERAND_PUNCT_VALID_P): '!' is valid.
* config/bfin/bfin.md (UNSPEC_32BIT): New constant.
(movsi_insn32): New pattern, with two new splits to create it
before the final scheduling pass.
(neghi2): Not a dsp32 insn, rather alu0.
(movbi, pushsi_insn, popsi_insn, movsi_insn, movv2hi_insn, movhi_insn,
movqi_insn, movsf_insn, movsi_insv, extendhisi2, zero_extendhisi2,
extendqihi2, extendqisi2, zero_extendqihi2, zero_extendqisi2,
mulhisi3, umulhisi3, ssadsi3, sssubsi3, smaxsi3, sminsi3, abssi2,
ssnegsi2, signbitssi2, smaxhi3, sminhi3, abshi2, ssneghi2, signbitshi2,
movhi_low2high, movhi_high2high, movhi_low2low, movhi_high2low,
movhiv2hi_low, movhiv2hi_high, composev2hi, packv2hi, movv2hi_hi,
ssaddhi3, sssubhi3, addv2hi3, ssaddv2hi3, subv2hi3, sssubv2hi3,
addsubv2hi3, subaddv2hi3, ssaddsubv2hi3, sssubaddv2hi3, sublohiv2hi3,
subhilov2hi3, sssublohiv2hi3, sssubhilov2hi3, addlohiv2hi3,
addhilov2hi3, ssaddlohiv2hi3, ssaddhilov2hi3, sminv2hi3, smaxv2hi3,
flag_mulhi, flag_mulhisi, flag_mulhisi_parts, flag_machi,
flag_machi_acconly, flag_macinithi, flag_macinit1hi, mulv2hi3,
flag_mulv2hi, flag_mulv2hi_parts, flag_macv2hi_parts,
flag_macv2hi_parts_acconly, flag_macinitv2hi_parts,
flag_macinit1v2hi_parts, mulhisi_ll, mulhisi_lh, mulhisi_hl,
mulhisi_hh, ssnegv2hi2, absv2hi2, ssashiftv2hi3, ssashifthi3,
lshiftv2hi3, lshifthi3): Use '%!' to terminate all dsp32/load/store
variants instead of ';'.
(ror_one, rol_one): Likewise. Make them dsp32 insns.
(ashlsi3_insn, ashrsi3, lshrsi3): Add dsp32 variants.
(align8, align16, align24): Now named patterns; also using '%!'.
(mnop): New insn.
From-SVN: r119534
2006-12-05 09:49:56 +01:00
|
|
|
|
"%h0 = %h2 << 0%!"
|
From Jie Zhang <jie.zhang@analog.com>:
* config/bfin/predicates.md (p_register_operand): New
predicate.
(dp_register_operand): New predicate.
* config/bfin/bfin-protos.h (WA_05000074): Define.
(ENABLE_WA_05000074): Define.
* config/bfin/bfin.c (bfin_cpus[]): Add WA_05000074 for
all cpus.
(bfin_gen_bundles): Put dsp32shiftimm instruction in slot[0].
* config/bfin/bfin.md (define_attr type): Add dsp32shiftimm.
(define_attr addrtype): Allow load/store register to be
P register.
(define_attr storereg): New.
(define_cpu_unit anomaly_05000074): New.
(define_insn_reservation dsp32shiftimm): New.
(define_insn_reservation dsp32shiftimm_anomaly_05000074): New.
(define_insn_reservation loadp): Cannot use slot2.
(define_insn_reservation loadsp): Cannot use slot2.
(define_insn_reservation storep): Cannot use slot2. Does not
apply when working around 05000074.
(define_insn_reservation storep_anomaly_05000074): New.
(define_insn_reservation storei): Does not apply when working
around 05000074.
(define_insn_reservation storei_anomaly_05000074): New.
(define_attr length): Add dsp32shiftimm case.
(define_insn movsi_insn32, movsi_insv, ashlsi3_insn, ashrsi3,
ror_one, rol_one, lshrsi3, lshrpdi3, ashrpdi3, movhiv2hi_low,
movhiv2hi_high, composev2hi, packv2hi, movv2hi_hi,
ssashiftv2hi3, ssashifthi3, ssashiftsi3, lshiftv2hi3, lshifthi3):
Set type as dsp32shiftimm for dsp32shiftimm alternatives.
From-SVN: r151490
2009-09-07 23:40:23 +02:00
|
|
|
|
[(set_attr "type" "dsp32shiftimm")])
|
genmodes.c (make_vector_mode): Allow making VECTOR_MODE_INT of a MODE_PARTIAL_INT mode.
* genmodes.c (make_vector_mode): Allow making VECTOR_MODE_INT of a
MODE_PARTIAL_INT mode.
* config/bfin/bfin-modes.def: Add V2PDI and V2SI.
* config/bfin/bfin.c (print_operand): Add macflag and mac/msu modifiers
for CONST_INTs.
(hard_regno_mode_ok): V2PDImode is ok for accumulators.
* config/bfin/bfin.h (CLASS_MAX_NREGS, HARD_REGNO_NREGS): Handle
V2PDImode.
* config/bfin/predicates.md (const01_operand, vec_shift_operand):
New predicates.
* config/bfin/bfin.md (UNSPEC_MUL_WITH_FLAG, UNSPEC_MAC_WITH_FLAG):
New constants.
(MACFLAG_NONE, MACFLAG_T, MACFLAG_FU, MACFLAG_TFU, MACFLAG_IS,
MACFLAG_IU, MACFLAG_W32, MACFLAG_M, MACFLAG_S2RND, MACFLAG_ISS2,
MACFLAG_IH): Likewise.
(movstricthi_1): Renamed from "*movstricthi".
(load_accumulator, load_accumulator_pair, movsi_insv, insv,
ssaddsi3, sssubsi3, ssnegsi2, signbitssi2, smaxhi3, sminhi3,
abshi2, neghi2, ssneghi2, signbitshi2, movhi_low2high,
movhi_high2high, movhi_low2low, movhi_high2low, movhiv2hi_low,
movhiv2hi_high, composev2hi, movv2hi_hi, movv2hi_hi_low,
movv2hi_hi_high, ssaddhi3, sssubhi3, ssaddv2hi3, sssubv2hi3,
addsubv2hi3, subaddv2hi3, ssaddsubv2hi3, sssubaddv2hi3,
sublohiv2hi3, subhilov2hi3, sssublohiv2hi3, sssubhilov2hi3,
addlohiv2hi3, addhilov2hi3, ssaddlohiv2hi3, ssaddhilov2hi3,
mulhisi_ll, mulhisi_lh, mulhisi_hl, mulhisi_hh, ssnegv2hi2,
ssashiftv2hi3, ssashifthi3, lshiftv2hi3, lshifthi3, packv2hi,
flag_mulhi, flag_mulhisi_parts, flag_machi, flag_machi_acconly,
flag_macinithi, flag_macinit1hi, flag_mulv2hi, flag_mulv2hi_parts,
flag_macv2hi_parts, flag_macv2hi_parts_acconly,
flag_macinitv2hi_parts, flag_macinit1v2hi_parts): New patterns.
From-SVN: r113245
2006-04-25 13:49:27 +02:00
|
|
|
|
|
|
|
|
|
(define_insn "movhiv2hi_high"
|
|
|
|
|
[(set (match_operand:V2HI 0 "register_operand" "=d")
|
|
|
|
|
(vec_concat:V2HI
|
|
|
|
|
(vec_select:HI (match_operand:V2HI 1 "register_operand" "0")
|
|
|
|
|
(parallel [(const_int 0)]))
|
|
|
|
|
(match_operand:HI 2 "register_operand" "d")))]
|
|
|
|
|
""
|
rtlanal.c (note_uses): Deal with SEQUENCEs.
* rtlanal.c (note_uses): Deal with SEQUENCEs.
* config/bfin/bfin.c: Include "timevar.h".
(bfin_flag_schedule_insns2, splitting_for_sched,
bfin_flag_var_tracking): New variables.
(print_operand): Handle '%!'.
(override_options): Disable normal sched2 pass, instead set
bfin_flag_schedule_insns2 for reorg to handle it.
(output_file_start): Likewise for var-tracking.
(bfin_optimize_loop): Take some care not to stumble over SEQUENCEs.
(gen_one_bundle, bfin_gen_bundles, type_for_anomaly, trapping_loads_p):
New functions.
(bfin_reorg): Do second scheduling pass here, and call
bfin_gen_bundles. Use type_for_anomaly and trapping_loads_p instead
of examining insns directly. If bfin_flag_var_tracking, call
var-tracking pass when done with everything else.
* config/bfin/bfin.h (PRINT_OPERAND_PUNCT_VALID_P): '!' is valid.
* config/bfin/bfin.md (UNSPEC_32BIT): New constant.
(movsi_insn32): New pattern, with two new splits to create it
before the final scheduling pass.
(neghi2): Not a dsp32 insn, rather alu0.
(movbi, pushsi_insn, popsi_insn, movsi_insn, movv2hi_insn, movhi_insn,
movqi_insn, movsf_insn, movsi_insv, extendhisi2, zero_extendhisi2,
extendqihi2, extendqisi2, zero_extendqihi2, zero_extendqisi2,
mulhisi3, umulhisi3, ssadsi3, sssubsi3, smaxsi3, sminsi3, abssi2,
ssnegsi2, signbitssi2, smaxhi3, sminhi3, abshi2, ssneghi2, signbitshi2,
movhi_low2high, movhi_high2high, movhi_low2low, movhi_high2low,
movhiv2hi_low, movhiv2hi_high, composev2hi, packv2hi, movv2hi_hi,
ssaddhi3, sssubhi3, addv2hi3, ssaddv2hi3, subv2hi3, sssubv2hi3,
addsubv2hi3, subaddv2hi3, ssaddsubv2hi3, sssubaddv2hi3, sublohiv2hi3,
subhilov2hi3, sssublohiv2hi3, sssubhilov2hi3, addlohiv2hi3,
addhilov2hi3, ssaddlohiv2hi3, ssaddhilov2hi3, sminv2hi3, smaxv2hi3,
flag_mulhi, flag_mulhisi, flag_mulhisi_parts, flag_machi,
flag_machi_acconly, flag_macinithi, flag_macinit1hi, mulv2hi3,
flag_mulv2hi, flag_mulv2hi_parts, flag_macv2hi_parts,
flag_macv2hi_parts_acconly, flag_macinitv2hi_parts,
flag_macinit1v2hi_parts, mulhisi_ll, mulhisi_lh, mulhisi_hl,
mulhisi_hh, ssnegv2hi2, absv2hi2, ssashiftv2hi3, ssashifthi3,
lshiftv2hi3, lshifthi3): Use '%!' to terminate all dsp32/load/store
variants instead of ';'.
(ror_one, rol_one): Likewise. Make them dsp32 insns.
(ashlsi3_insn, ashrsi3, lshrsi3): Add dsp32 variants.
(align8, align16, align24): Now named patterns; also using '%!'.
(mnop): New insn.
From-SVN: r119534
2006-12-05 09:49:56 +01:00
|
|
|
|
"%d0 = %h2 << 0%!"
|
From Jie Zhang <jie.zhang@analog.com>:
* config/bfin/predicates.md (p_register_operand): New
predicate.
(dp_register_operand): New predicate.
* config/bfin/bfin-protos.h (WA_05000074): Define.
(ENABLE_WA_05000074): Define.
* config/bfin/bfin.c (bfin_cpus[]): Add WA_05000074 for
all cpus.
(bfin_gen_bundles): Put dsp32shiftimm instruction in slot[0].
* config/bfin/bfin.md (define_attr type): Add dsp32shiftimm.
(define_attr addrtype): Allow load/store register to be
P register.
(define_attr storereg): New.
(define_cpu_unit anomaly_05000074): New.
(define_insn_reservation dsp32shiftimm): New.
(define_insn_reservation dsp32shiftimm_anomaly_05000074): New.
(define_insn_reservation loadp): Cannot use slot2.
(define_insn_reservation loadsp): Cannot use slot2.
(define_insn_reservation storep): Cannot use slot2. Does not
apply when working around 05000074.
(define_insn_reservation storep_anomaly_05000074): New.
(define_insn_reservation storei): Does not apply when working
around 05000074.
(define_insn_reservation storei_anomaly_05000074): New.
(define_attr length): Add dsp32shiftimm case.
(define_insn movsi_insn32, movsi_insv, ashlsi3_insn, ashrsi3,
ror_one, rol_one, lshrsi3, lshrpdi3, ashrpdi3, movhiv2hi_low,
movhiv2hi_high, composev2hi, packv2hi, movv2hi_hi,
ssashiftv2hi3, ssashifthi3, ssashiftsi3, lshiftv2hi3, lshifthi3):
Set type as dsp32shiftimm for dsp32shiftimm alternatives.
From-SVN: r151490
2009-09-07 23:40:23 +02:00
|
|
|
|
[(set_attr "type" "dsp32shiftimm")])
|
genmodes.c (make_vector_mode): Allow making VECTOR_MODE_INT of a MODE_PARTIAL_INT mode.
* genmodes.c (make_vector_mode): Allow making VECTOR_MODE_INT of a
MODE_PARTIAL_INT mode.
* config/bfin/bfin-modes.def: Add V2PDI and V2SI.
* config/bfin/bfin.c (print_operand): Add macflag and mac/msu modifiers
for CONST_INTs.
(hard_regno_mode_ok): V2PDImode is ok for accumulators.
* config/bfin/bfin.h (CLASS_MAX_NREGS, HARD_REGNO_NREGS): Handle
V2PDImode.
* config/bfin/predicates.md (const01_operand, vec_shift_operand):
New predicates.
* config/bfin/bfin.md (UNSPEC_MUL_WITH_FLAG, UNSPEC_MAC_WITH_FLAG):
New constants.
(MACFLAG_NONE, MACFLAG_T, MACFLAG_FU, MACFLAG_TFU, MACFLAG_IS,
MACFLAG_IU, MACFLAG_W32, MACFLAG_M, MACFLAG_S2RND, MACFLAG_ISS2,
MACFLAG_IH): Likewise.
(movstricthi_1): Renamed from "*movstricthi".
(load_accumulator, load_accumulator_pair, movsi_insv, insv,
ssaddsi3, sssubsi3, ssnegsi2, signbitssi2, smaxhi3, sminhi3,
abshi2, neghi2, ssneghi2, signbitshi2, movhi_low2high,
movhi_high2high, movhi_low2low, movhi_high2low, movhiv2hi_low,
movhiv2hi_high, composev2hi, movv2hi_hi, movv2hi_hi_low,
movv2hi_hi_high, ssaddhi3, sssubhi3, ssaddv2hi3, sssubv2hi3,
addsubv2hi3, subaddv2hi3, ssaddsubv2hi3, sssubaddv2hi3,
sublohiv2hi3, subhilov2hi3, sssublohiv2hi3, sssubhilov2hi3,
addlohiv2hi3, addhilov2hi3, ssaddlohiv2hi3, ssaddhilov2hi3,
mulhisi_ll, mulhisi_lh, mulhisi_hl, mulhisi_hh, ssnegv2hi2,
ssashiftv2hi3, ssashifthi3, lshiftv2hi3, lshifthi3, packv2hi,
flag_mulhi, flag_mulhisi_parts, flag_machi, flag_machi_acconly,
flag_macinithi, flag_macinit1hi, flag_mulv2hi, flag_mulv2hi_parts,
flag_macv2hi_parts, flag_macv2hi_parts_acconly,
flag_macinitv2hi_parts, flag_macinit1v2hi_parts): New patterns.
From-SVN: r113245
2006-04-25 13:49:27 +02:00
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|
;; No earlyclobber on alternative two since our sequence ought to be safe.
|
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;; The order of operands is intentional to match the VDSP builtin (high word
|
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;; is passed first).
|
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|
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(define_insn_and_split "composev2hi"
|
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[(set (match_operand:V2HI 0 "register_operand" "=d,d")
|
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(vec_concat:V2HI (match_operand:HI 2 "register_operand" "0,d")
|
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(match_operand:HI 1 "register_operand" "d,d")))]
|
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""
|
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"@
|
2008-10-23 00:42:02 +02:00
|
|
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|
%d0 = %h1 << 0%!
|
genmodes.c (make_vector_mode): Allow making VECTOR_MODE_INT of a MODE_PARTIAL_INT mode.
* genmodes.c (make_vector_mode): Allow making VECTOR_MODE_INT of a
MODE_PARTIAL_INT mode.
* config/bfin/bfin-modes.def: Add V2PDI and V2SI.
* config/bfin/bfin.c (print_operand): Add macflag and mac/msu modifiers
for CONST_INTs.
(hard_regno_mode_ok): V2PDImode is ok for accumulators.
* config/bfin/bfin.h (CLASS_MAX_NREGS, HARD_REGNO_NREGS): Handle
V2PDImode.
* config/bfin/predicates.md (const01_operand, vec_shift_operand):
New predicates.
* config/bfin/bfin.md (UNSPEC_MUL_WITH_FLAG, UNSPEC_MAC_WITH_FLAG):
New constants.
(MACFLAG_NONE, MACFLAG_T, MACFLAG_FU, MACFLAG_TFU, MACFLAG_IS,
MACFLAG_IU, MACFLAG_W32, MACFLAG_M, MACFLAG_S2RND, MACFLAG_ISS2,
MACFLAG_IH): Likewise.
(movstricthi_1): Renamed from "*movstricthi".
(load_accumulator, load_accumulator_pair, movsi_insv, insv,
ssaddsi3, sssubsi3, ssnegsi2, signbitssi2, smaxhi3, sminhi3,
abshi2, neghi2, ssneghi2, signbitshi2, movhi_low2high,
movhi_high2high, movhi_low2low, movhi_high2low, movhiv2hi_low,
movhiv2hi_high, composev2hi, movv2hi_hi, movv2hi_hi_low,
movv2hi_hi_high, ssaddhi3, sssubhi3, ssaddv2hi3, sssubv2hi3,
addsubv2hi3, subaddv2hi3, ssaddsubv2hi3, sssubaddv2hi3,
sublohiv2hi3, subhilov2hi3, sssublohiv2hi3, sssubhilov2hi3,
addlohiv2hi3, addhilov2hi3, ssaddlohiv2hi3, ssaddhilov2hi3,
mulhisi_ll, mulhisi_lh, mulhisi_hl, mulhisi_hh, ssnegv2hi2,
ssashiftv2hi3, ssashifthi3, lshiftv2hi3, lshifthi3, packv2hi,
flag_mulhi, flag_mulhisi_parts, flag_machi, flag_machi_acconly,
flag_macinithi, flag_macinit1hi, flag_mulv2hi, flag_mulv2hi_parts,
flag_macv2hi_parts, flag_macv2hi_parts_acconly,
flag_macinitv2hi_parts, flag_macinit1v2hi_parts): New patterns.
From-SVN: r113245
2006-04-25 13:49:27 +02:00
|
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#"
|
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"reload_completed"
|
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[(set (match_dup 0)
|
|
|
|
|
(vec_concat:V2HI
|
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|
(vec_select:HI (match_dup 0) (parallel [(const_int 0)]))
|
2008-10-23 00:42:02 +02:00
|
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|
(match_dup 1)))
|
genmodes.c (make_vector_mode): Allow making VECTOR_MODE_INT of a MODE_PARTIAL_INT mode.
* genmodes.c (make_vector_mode): Allow making VECTOR_MODE_INT of a
MODE_PARTIAL_INT mode.
* config/bfin/bfin-modes.def: Add V2PDI and V2SI.
* config/bfin/bfin.c (print_operand): Add macflag and mac/msu modifiers
for CONST_INTs.
(hard_regno_mode_ok): V2PDImode is ok for accumulators.
* config/bfin/bfin.h (CLASS_MAX_NREGS, HARD_REGNO_NREGS): Handle
V2PDImode.
* config/bfin/predicates.md (const01_operand, vec_shift_operand):
New predicates.
* config/bfin/bfin.md (UNSPEC_MUL_WITH_FLAG, UNSPEC_MAC_WITH_FLAG):
New constants.
(MACFLAG_NONE, MACFLAG_T, MACFLAG_FU, MACFLAG_TFU, MACFLAG_IS,
MACFLAG_IU, MACFLAG_W32, MACFLAG_M, MACFLAG_S2RND, MACFLAG_ISS2,
MACFLAG_IH): Likewise.
(movstricthi_1): Renamed from "*movstricthi".
(load_accumulator, load_accumulator_pair, movsi_insv, insv,
ssaddsi3, sssubsi3, ssnegsi2, signbitssi2, smaxhi3, sminhi3,
abshi2, neghi2, ssneghi2, signbitshi2, movhi_low2high,
movhi_high2high, movhi_low2low, movhi_high2low, movhiv2hi_low,
movhiv2hi_high, composev2hi, movv2hi_hi, movv2hi_hi_low,
movv2hi_hi_high, ssaddhi3, sssubhi3, ssaddv2hi3, sssubv2hi3,
addsubv2hi3, subaddv2hi3, ssaddsubv2hi3, sssubaddv2hi3,
sublohiv2hi3, subhilov2hi3, sssublohiv2hi3, sssubhilov2hi3,
addlohiv2hi3, addhilov2hi3, ssaddlohiv2hi3, ssaddhilov2hi3,
mulhisi_ll, mulhisi_lh, mulhisi_hl, mulhisi_hh, ssnegv2hi2,
ssashiftv2hi3, ssashifthi3, lshiftv2hi3, lshifthi3, packv2hi,
flag_mulhi, flag_mulhisi_parts, flag_machi, flag_machi_acconly,
flag_macinithi, flag_macinit1hi, flag_mulv2hi, flag_mulv2hi_parts,
flag_macv2hi_parts, flag_macv2hi_parts_acconly,
flag_macinitv2hi_parts, flag_macinit1v2hi_parts): New patterns.
From-SVN: r113245
2006-04-25 13:49:27 +02:00
|
|
|
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(set (match_dup 0)
|
|
|
|
|
(vec_concat:V2HI
|
2008-10-23 00:42:02 +02:00
|
|
|
|
(match_dup 2)
|
genmodes.c (make_vector_mode): Allow making VECTOR_MODE_INT of a MODE_PARTIAL_INT mode.
* genmodes.c (make_vector_mode): Allow making VECTOR_MODE_INT of a
MODE_PARTIAL_INT mode.
* config/bfin/bfin-modes.def: Add V2PDI and V2SI.
* config/bfin/bfin.c (print_operand): Add macflag and mac/msu modifiers
for CONST_INTs.
(hard_regno_mode_ok): V2PDImode is ok for accumulators.
* config/bfin/bfin.h (CLASS_MAX_NREGS, HARD_REGNO_NREGS): Handle
V2PDImode.
* config/bfin/predicates.md (const01_operand, vec_shift_operand):
New predicates.
* config/bfin/bfin.md (UNSPEC_MUL_WITH_FLAG, UNSPEC_MAC_WITH_FLAG):
New constants.
(MACFLAG_NONE, MACFLAG_T, MACFLAG_FU, MACFLAG_TFU, MACFLAG_IS,
MACFLAG_IU, MACFLAG_W32, MACFLAG_M, MACFLAG_S2RND, MACFLAG_ISS2,
MACFLAG_IH): Likewise.
(movstricthi_1): Renamed from "*movstricthi".
(load_accumulator, load_accumulator_pair, movsi_insv, insv,
ssaddsi3, sssubsi3, ssnegsi2, signbitssi2, smaxhi3, sminhi3,
abshi2, neghi2, ssneghi2, signbitshi2, movhi_low2high,
movhi_high2high, movhi_low2low, movhi_high2low, movhiv2hi_low,
movhiv2hi_high, composev2hi, movv2hi_hi, movv2hi_hi_low,
movv2hi_hi_high, ssaddhi3, sssubhi3, ssaddv2hi3, sssubv2hi3,
addsubv2hi3, subaddv2hi3, ssaddsubv2hi3, sssubaddv2hi3,
sublohiv2hi3, subhilov2hi3, sssublohiv2hi3, sssubhilov2hi3,
addlohiv2hi3, addhilov2hi3, ssaddlohiv2hi3, ssaddhilov2hi3,
mulhisi_ll, mulhisi_lh, mulhisi_hl, mulhisi_hh, ssnegv2hi2,
ssashiftv2hi3, ssashifthi3, lshiftv2hi3, lshifthi3, packv2hi,
flag_mulhi, flag_mulhisi_parts, flag_machi, flag_machi_acconly,
flag_macinithi, flag_macinit1hi, flag_mulv2hi, flag_mulv2hi_parts,
flag_macv2hi_parts, flag_macv2hi_parts_acconly,
flag_macinitv2hi_parts, flag_macinit1v2hi_parts): New patterns.
From-SVN: r113245
2006-04-25 13:49:27 +02:00
|
|
|
|
(vec_select:HI (match_dup 0) (parallel [(const_int 1)]))))]
|
|
|
|
|
""
|
From Jie Zhang <jie.zhang@analog.com>:
* config/bfin/predicates.md (p_register_operand): New
predicate.
(dp_register_operand): New predicate.
* config/bfin/bfin-protos.h (WA_05000074): Define.
(ENABLE_WA_05000074): Define.
* config/bfin/bfin.c (bfin_cpus[]): Add WA_05000074 for
all cpus.
(bfin_gen_bundles): Put dsp32shiftimm instruction in slot[0].
* config/bfin/bfin.md (define_attr type): Add dsp32shiftimm.
(define_attr addrtype): Allow load/store register to be
P register.
(define_attr storereg): New.
(define_cpu_unit anomaly_05000074): New.
(define_insn_reservation dsp32shiftimm): New.
(define_insn_reservation dsp32shiftimm_anomaly_05000074): New.
(define_insn_reservation loadp): Cannot use slot2.
(define_insn_reservation loadsp): Cannot use slot2.
(define_insn_reservation storep): Cannot use slot2. Does not
apply when working around 05000074.
(define_insn_reservation storep_anomaly_05000074): New.
(define_insn_reservation storei): Does not apply when working
around 05000074.
(define_insn_reservation storei_anomaly_05000074): New.
(define_attr length): Add dsp32shiftimm case.
(define_insn movsi_insn32, movsi_insv, ashlsi3_insn, ashrsi3,
ror_one, rol_one, lshrsi3, lshrpdi3, ashrpdi3, movhiv2hi_low,
movhiv2hi_high, composev2hi, packv2hi, movv2hi_hi,
ssashiftv2hi3, ssashifthi3, ssashiftsi3, lshiftv2hi3, lshifthi3):
Set type as dsp32shiftimm for dsp32shiftimm alternatives.
From-SVN: r151490
2009-09-07 23:40:23 +02:00
|
|
|
|
[(set_attr "type" "dsp32shiftimm")])
|
genmodes.c (make_vector_mode): Allow making VECTOR_MODE_INT of a MODE_PARTIAL_INT mode.
* genmodes.c (make_vector_mode): Allow making VECTOR_MODE_INT of a
MODE_PARTIAL_INT mode.
* config/bfin/bfin-modes.def: Add V2PDI and V2SI.
* config/bfin/bfin.c (print_operand): Add macflag and mac/msu modifiers
for CONST_INTs.
(hard_regno_mode_ok): V2PDImode is ok for accumulators.
* config/bfin/bfin.h (CLASS_MAX_NREGS, HARD_REGNO_NREGS): Handle
V2PDImode.
* config/bfin/predicates.md (const01_operand, vec_shift_operand):
New predicates.
* config/bfin/bfin.md (UNSPEC_MUL_WITH_FLAG, UNSPEC_MAC_WITH_FLAG):
New constants.
(MACFLAG_NONE, MACFLAG_T, MACFLAG_FU, MACFLAG_TFU, MACFLAG_IS,
MACFLAG_IU, MACFLAG_W32, MACFLAG_M, MACFLAG_S2RND, MACFLAG_ISS2,
MACFLAG_IH): Likewise.
(movstricthi_1): Renamed from "*movstricthi".
(load_accumulator, load_accumulator_pair, movsi_insv, insv,
ssaddsi3, sssubsi3, ssnegsi2, signbitssi2, smaxhi3, sminhi3,
abshi2, neghi2, ssneghi2, signbitshi2, movhi_low2high,
movhi_high2high, movhi_low2low, movhi_high2low, movhiv2hi_low,
movhiv2hi_high, composev2hi, movv2hi_hi, movv2hi_hi_low,
movv2hi_hi_high, ssaddhi3, sssubhi3, ssaddv2hi3, sssubv2hi3,
addsubv2hi3, subaddv2hi3, ssaddsubv2hi3, sssubaddv2hi3,
sublohiv2hi3, subhilov2hi3, sssublohiv2hi3, sssubhilov2hi3,
addlohiv2hi3, addhilov2hi3, ssaddlohiv2hi3, ssaddhilov2hi3,
mulhisi_ll, mulhisi_lh, mulhisi_hl, mulhisi_hh, ssnegv2hi2,
ssashiftv2hi3, ssashifthi3, lshiftv2hi3, lshifthi3, packv2hi,
flag_mulhi, flag_mulhisi_parts, flag_machi, flag_machi_acconly,
flag_macinithi, flag_macinit1hi, flag_mulv2hi, flag_mulv2hi_parts,
flag_macv2hi_parts, flag_macv2hi_parts_acconly,
flag_macinitv2hi_parts, flag_macinit1v2hi_parts): New patterns.
From-SVN: r113245
2006-04-25 13:49:27 +02:00
|
|
|
|
|
|
|
|
|
; Like composev2hi, but operating on elements of V2HI vectors.
|
|
|
|
|
; Useful on its own, and as a combiner bridge for the multiply and
|
|
|
|
|
; mac patterns.
|
|
|
|
|
(define_insn "packv2hi"
|
2007-04-12 17:22:06 +02:00
|
|
|
|
[(set (match_operand:V2HI 0 "register_operand" "=d,d,d,d,d,d,d,d")
|
genmodes.c (make_vector_mode): Allow making VECTOR_MODE_INT of a MODE_PARTIAL_INT mode.
* genmodes.c (make_vector_mode): Allow making VECTOR_MODE_INT of a
MODE_PARTIAL_INT mode.
* config/bfin/bfin-modes.def: Add V2PDI and V2SI.
* config/bfin/bfin.c (print_operand): Add macflag and mac/msu modifiers
for CONST_INTs.
(hard_regno_mode_ok): V2PDImode is ok for accumulators.
* config/bfin/bfin.h (CLASS_MAX_NREGS, HARD_REGNO_NREGS): Handle
V2PDImode.
* config/bfin/predicates.md (const01_operand, vec_shift_operand):
New predicates.
* config/bfin/bfin.md (UNSPEC_MUL_WITH_FLAG, UNSPEC_MAC_WITH_FLAG):
New constants.
(MACFLAG_NONE, MACFLAG_T, MACFLAG_FU, MACFLAG_TFU, MACFLAG_IS,
MACFLAG_IU, MACFLAG_W32, MACFLAG_M, MACFLAG_S2RND, MACFLAG_ISS2,
MACFLAG_IH): Likewise.
(movstricthi_1): Renamed from "*movstricthi".
(load_accumulator, load_accumulator_pair, movsi_insv, insv,
ssaddsi3, sssubsi3, ssnegsi2, signbitssi2, smaxhi3, sminhi3,
abshi2, neghi2, ssneghi2, signbitshi2, movhi_low2high,
movhi_high2high, movhi_low2low, movhi_high2low, movhiv2hi_low,
movhiv2hi_high, composev2hi, movv2hi_hi, movv2hi_hi_low,
movv2hi_hi_high, ssaddhi3, sssubhi3, ssaddv2hi3, sssubv2hi3,
addsubv2hi3, subaddv2hi3, ssaddsubv2hi3, sssubaddv2hi3,
sublohiv2hi3, subhilov2hi3, sssublohiv2hi3, sssubhilov2hi3,
addlohiv2hi3, addhilov2hi3, ssaddlohiv2hi3, ssaddhilov2hi3,
mulhisi_ll, mulhisi_lh, mulhisi_hl, mulhisi_hh, ssnegv2hi2,
ssashiftv2hi3, ssashifthi3, lshiftv2hi3, lshifthi3, packv2hi,
flag_mulhi, flag_mulhisi_parts, flag_machi, flag_machi_acconly,
flag_macinithi, flag_macinit1hi, flag_mulv2hi, flag_mulv2hi_parts,
flag_macv2hi_parts, flag_macv2hi_parts_acconly,
flag_macinitv2hi_parts, flag_macinit1v2hi_parts): New patterns.
From-SVN: r113245
2006-04-25 13:49:27 +02:00
|
|
|
|
(vec_concat:V2HI (vec_select:HI
|
2007-04-12 17:22:06 +02:00
|
|
|
|
(match_operand:V2HI 1 "register_operand" "0,0,d,d,d,d,d,d")
|
|
|
|
|
(parallel [(match_operand 3 "const01_operand" "P0,P0,P0,P1,P0,P1,P0,P1")]))
|
genmodes.c (make_vector_mode): Allow making VECTOR_MODE_INT of a MODE_PARTIAL_INT mode.
* genmodes.c (make_vector_mode): Allow making VECTOR_MODE_INT of a
MODE_PARTIAL_INT mode.
* config/bfin/bfin-modes.def: Add V2PDI and V2SI.
* config/bfin/bfin.c (print_operand): Add macflag and mac/msu modifiers
for CONST_INTs.
(hard_regno_mode_ok): V2PDImode is ok for accumulators.
* config/bfin/bfin.h (CLASS_MAX_NREGS, HARD_REGNO_NREGS): Handle
V2PDImode.
* config/bfin/predicates.md (const01_operand, vec_shift_operand):
New predicates.
* config/bfin/bfin.md (UNSPEC_MUL_WITH_FLAG, UNSPEC_MAC_WITH_FLAG):
New constants.
(MACFLAG_NONE, MACFLAG_T, MACFLAG_FU, MACFLAG_TFU, MACFLAG_IS,
MACFLAG_IU, MACFLAG_W32, MACFLAG_M, MACFLAG_S2RND, MACFLAG_ISS2,
MACFLAG_IH): Likewise.
(movstricthi_1): Renamed from "*movstricthi".
(load_accumulator, load_accumulator_pair, movsi_insv, insv,
ssaddsi3, sssubsi3, ssnegsi2, signbitssi2, smaxhi3, sminhi3,
abshi2, neghi2, ssneghi2, signbitshi2, movhi_low2high,
movhi_high2high, movhi_low2low, movhi_high2low, movhiv2hi_low,
movhiv2hi_high, composev2hi, movv2hi_hi, movv2hi_hi_low,
movv2hi_hi_high, ssaddhi3, sssubhi3, ssaddv2hi3, sssubv2hi3,
addsubv2hi3, subaddv2hi3, ssaddsubv2hi3, sssubaddv2hi3,
sublohiv2hi3, subhilov2hi3, sssublohiv2hi3, sssubhilov2hi3,
addlohiv2hi3, addhilov2hi3, ssaddlohiv2hi3, ssaddhilov2hi3,
mulhisi_ll, mulhisi_lh, mulhisi_hl, mulhisi_hh, ssnegv2hi2,
ssashiftv2hi3, ssashifthi3, lshiftv2hi3, lshifthi3, packv2hi,
flag_mulhi, flag_mulhisi_parts, flag_machi, flag_machi_acconly,
flag_macinithi, flag_macinit1hi, flag_mulv2hi, flag_mulv2hi_parts,
flag_macv2hi_parts, flag_macv2hi_parts_acconly,
flag_macinitv2hi_parts, flag_macinit1v2hi_parts): New patterns.
From-SVN: r113245
2006-04-25 13:49:27 +02:00
|
|
|
|
(vec_select:HI
|
2007-04-12 17:22:06 +02:00
|
|
|
|
(match_operand:V2HI 2 "register_operand" "d,d,0,0,d,d,d,d")
|
|
|
|
|
(parallel [(match_operand 4 "const01_operand" "P0,P1,P1,P1,P0,P0,P1,P1")]))))]
|
genmodes.c (make_vector_mode): Allow making VECTOR_MODE_INT of a MODE_PARTIAL_INT mode.
* genmodes.c (make_vector_mode): Allow making VECTOR_MODE_INT of a
MODE_PARTIAL_INT mode.
* config/bfin/bfin-modes.def: Add V2PDI and V2SI.
* config/bfin/bfin.c (print_operand): Add macflag and mac/msu modifiers
for CONST_INTs.
(hard_regno_mode_ok): V2PDImode is ok for accumulators.
* config/bfin/bfin.h (CLASS_MAX_NREGS, HARD_REGNO_NREGS): Handle
V2PDImode.
* config/bfin/predicates.md (const01_operand, vec_shift_operand):
New predicates.
* config/bfin/bfin.md (UNSPEC_MUL_WITH_FLAG, UNSPEC_MAC_WITH_FLAG):
New constants.
(MACFLAG_NONE, MACFLAG_T, MACFLAG_FU, MACFLAG_TFU, MACFLAG_IS,
MACFLAG_IU, MACFLAG_W32, MACFLAG_M, MACFLAG_S2RND, MACFLAG_ISS2,
MACFLAG_IH): Likewise.
(movstricthi_1): Renamed from "*movstricthi".
(load_accumulator, load_accumulator_pair, movsi_insv, insv,
ssaddsi3, sssubsi3, ssnegsi2, signbitssi2, smaxhi3, sminhi3,
abshi2, neghi2, ssneghi2, signbitshi2, movhi_low2high,
movhi_high2high, movhi_low2low, movhi_high2low, movhiv2hi_low,
movhiv2hi_high, composev2hi, movv2hi_hi, movv2hi_hi_low,
movv2hi_hi_high, ssaddhi3, sssubhi3, ssaddv2hi3, sssubv2hi3,
addsubv2hi3, subaddv2hi3, ssaddsubv2hi3, sssubaddv2hi3,
sublohiv2hi3, subhilov2hi3, sssublohiv2hi3, sssubhilov2hi3,
addlohiv2hi3, addhilov2hi3, ssaddlohiv2hi3, ssaddhilov2hi3,
mulhisi_ll, mulhisi_lh, mulhisi_hl, mulhisi_hh, ssnegv2hi2,
ssashiftv2hi3, ssashifthi3, lshiftv2hi3, lshifthi3, packv2hi,
flag_mulhi, flag_mulhisi_parts, flag_machi, flag_machi_acconly,
flag_macinithi, flag_macinit1hi, flag_mulv2hi, flag_mulv2hi_parts,
flag_macv2hi_parts, flag_macv2hi_parts_acconly,
flag_macinitv2hi_parts, flag_macinit1v2hi_parts): New patterns.
From-SVN: r113245
2006-04-25 13:49:27 +02:00
|
|
|
|
""
|
|
|
|
|
"@
|
2007-04-12 17:22:06 +02:00
|
|
|
|
%d0 = %h2 << 0%!
|
|
|
|
|
%d0 = %d2 << 0%!
|
|
|
|
|
%h0 = %h1 << 0%!
|
|
|
|
|
%h0 = %d1 << 0%!
|
rtlanal.c (note_uses): Deal with SEQUENCEs.
* rtlanal.c (note_uses): Deal with SEQUENCEs.
* config/bfin/bfin.c: Include "timevar.h".
(bfin_flag_schedule_insns2, splitting_for_sched,
bfin_flag_var_tracking): New variables.
(print_operand): Handle '%!'.
(override_options): Disable normal sched2 pass, instead set
bfin_flag_schedule_insns2 for reorg to handle it.
(output_file_start): Likewise for var-tracking.
(bfin_optimize_loop): Take some care not to stumble over SEQUENCEs.
(gen_one_bundle, bfin_gen_bundles, type_for_anomaly, trapping_loads_p):
New functions.
(bfin_reorg): Do second scheduling pass here, and call
bfin_gen_bundles. Use type_for_anomaly and trapping_loads_p instead
of examining insns directly. If bfin_flag_var_tracking, call
var-tracking pass when done with everything else.
* config/bfin/bfin.h (PRINT_OPERAND_PUNCT_VALID_P): '!' is valid.
* config/bfin/bfin.md (UNSPEC_32BIT): New constant.
(movsi_insn32): New pattern, with two new splits to create it
before the final scheduling pass.
(neghi2): Not a dsp32 insn, rather alu0.
(movbi, pushsi_insn, popsi_insn, movsi_insn, movv2hi_insn, movhi_insn,
movqi_insn, movsf_insn, movsi_insv, extendhisi2, zero_extendhisi2,
extendqihi2, extendqisi2, zero_extendqihi2, zero_extendqisi2,
mulhisi3, umulhisi3, ssadsi3, sssubsi3, smaxsi3, sminsi3, abssi2,
ssnegsi2, signbitssi2, smaxhi3, sminhi3, abshi2, ssneghi2, signbitshi2,
movhi_low2high, movhi_high2high, movhi_low2low, movhi_high2low,
movhiv2hi_low, movhiv2hi_high, composev2hi, packv2hi, movv2hi_hi,
ssaddhi3, sssubhi3, addv2hi3, ssaddv2hi3, subv2hi3, sssubv2hi3,
addsubv2hi3, subaddv2hi3, ssaddsubv2hi3, sssubaddv2hi3, sublohiv2hi3,
subhilov2hi3, sssublohiv2hi3, sssubhilov2hi3, addlohiv2hi3,
addhilov2hi3, ssaddlohiv2hi3, ssaddhilov2hi3, sminv2hi3, smaxv2hi3,
flag_mulhi, flag_mulhisi, flag_mulhisi_parts, flag_machi,
flag_machi_acconly, flag_macinithi, flag_macinit1hi, mulv2hi3,
flag_mulv2hi, flag_mulv2hi_parts, flag_macv2hi_parts,
flag_macv2hi_parts_acconly, flag_macinitv2hi_parts,
flag_macinit1v2hi_parts, mulhisi_ll, mulhisi_lh, mulhisi_hl,
mulhisi_hh, ssnegv2hi2, absv2hi2, ssashiftv2hi3, ssashifthi3,
lshiftv2hi3, lshifthi3): Use '%!' to terminate all dsp32/load/store
variants instead of ';'.
(ror_one, rol_one): Likewise. Make them dsp32 insns.
(ashlsi3_insn, ashrsi3, lshrsi3): Add dsp32 variants.
(align8, align16, align24): Now named patterns; also using '%!'.
(mnop): New insn.
From-SVN: r119534
2006-12-05 09:49:56 +01:00
|
|
|
|
%0 = PACK (%h2,%h1)%!
|
|
|
|
|
%0 = PACK (%h2,%d1)%!
|
|
|
|
|
%0 = PACK (%d2,%h1)%!
|
|
|
|
|
%0 = PACK (%d2,%d1)%!"
|
From Jie Zhang <jie.zhang@analog.com>:
* config/bfin/predicates.md (p_register_operand): New
predicate.
(dp_register_operand): New predicate.
* config/bfin/bfin-protos.h (WA_05000074): Define.
(ENABLE_WA_05000074): Define.
* config/bfin/bfin.c (bfin_cpus[]): Add WA_05000074 for
all cpus.
(bfin_gen_bundles): Put dsp32shiftimm instruction in slot[0].
* config/bfin/bfin.md (define_attr type): Add dsp32shiftimm.
(define_attr addrtype): Allow load/store register to be
P register.
(define_attr storereg): New.
(define_cpu_unit anomaly_05000074): New.
(define_insn_reservation dsp32shiftimm): New.
(define_insn_reservation dsp32shiftimm_anomaly_05000074): New.
(define_insn_reservation loadp): Cannot use slot2.
(define_insn_reservation loadsp): Cannot use slot2.
(define_insn_reservation storep): Cannot use slot2. Does not
apply when working around 05000074.
(define_insn_reservation storep_anomaly_05000074): New.
(define_insn_reservation storei): Does not apply when working
around 05000074.
(define_insn_reservation storei_anomaly_05000074): New.
(define_attr length): Add dsp32shiftimm case.
(define_insn movsi_insn32, movsi_insv, ashlsi3_insn, ashrsi3,
ror_one, rol_one, lshrsi3, lshrpdi3, ashrpdi3, movhiv2hi_low,
movhiv2hi_high, composev2hi, packv2hi, movv2hi_hi,
ssashiftv2hi3, ssashifthi3, ssashiftsi3, lshiftv2hi3, lshifthi3):
Set type as dsp32shiftimm for dsp32shiftimm alternatives.
From-SVN: r151490
2009-09-07 23:40:23 +02:00
|
|
|
|
[(set_attr "type" "dsp32shiftimm,dsp32shiftimm,dsp32shiftimm,dsp32shiftimm,dsp32,dsp32,dsp32,dsp32")])
|
genmodes.c (make_vector_mode): Allow making VECTOR_MODE_INT of a MODE_PARTIAL_INT mode.
* genmodes.c (make_vector_mode): Allow making VECTOR_MODE_INT of a
MODE_PARTIAL_INT mode.
* config/bfin/bfin-modes.def: Add V2PDI and V2SI.
* config/bfin/bfin.c (print_operand): Add macflag and mac/msu modifiers
for CONST_INTs.
(hard_regno_mode_ok): V2PDImode is ok for accumulators.
* config/bfin/bfin.h (CLASS_MAX_NREGS, HARD_REGNO_NREGS): Handle
V2PDImode.
* config/bfin/predicates.md (const01_operand, vec_shift_operand):
New predicates.
* config/bfin/bfin.md (UNSPEC_MUL_WITH_FLAG, UNSPEC_MAC_WITH_FLAG):
New constants.
(MACFLAG_NONE, MACFLAG_T, MACFLAG_FU, MACFLAG_TFU, MACFLAG_IS,
MACFLAG_IU, MACFLAG_W32, MACFLAG_M, MACFLAG_S2RND, MACFLAG_ISS2,
MACFLAG_IH): Likewise.
(movstricthi_1): Renamed from "*movstricthi".
(load_accumulator, load_accumulator_pair, movsi_insv, insv,
ssaddsi3, sssubsi3, ssnegsi2, signbitssi2, smaxhi3, sminhi3,
abshi2, neghi2, ssneghi2, signbitshi2, movhi_low2high,
movhi_high2high, movhi_low2low, movhi_high2low, movhiv2hi_low,
movhiv2hi_high, composev2hi, movv2hi_hi, movv2hi_hi_low,
movv2hi_hi_high, ssaddhi3, sssubhi3, ssaddv2hi3, sssubv2hi3,
addsubv2hi3, subaddv2hi3, ssaddsubv2hi3, sssubaddv2hi3,
sublohiv2hi3, subhilov2hi3, sssublohiv2hi3, sssubhilov2hi3,
addlohiv2hi3, addhilov2hi3, ssaddlohiv2hi3, ssaddhilov2hi3,
mulhisi_ll, mulhisi_lh, mulhisi_hl, mulhisi_hh, ssnegv2hi2,
ssashiftv2hi3, ssashifthi3, lshiftv2hi3, lshifthi3, packv2hi,
flag_mulhi, flag_mulhisi_parts, flag_machi, flag_machi_acconly,
flag_macinithi, flag_macinit1hi, flag_mulv2hi, flag_mulv2hi_parts,
flag_macv2hi_parts, flag_macv2hi_parts_acconly,
flag_macinitv2hi_parts, flag_macinit1v2hi_parts): New patterns.
From-SVN: r113245
2006-04-25 13:49:27 +02:00
|
|
|
|
|
|
|
|
|
(define_insn "movv2hi_hi"
|
|
|
|
|
[(set (match_operand:HI 0 "register_operand" "=d,d,d")
|
|
|
|
|
(vec_select:HI (match_operand:V2HI 1 "register_operand" "0,d,d")
|
2006-05-04 13:03:41 +02:00
|
|
|
|
(parallel [(match_operand 2 "const01_operand" "P0,P0,P1")])))]
|
genmodes.c (make_vector_mode): Allow making VECTOR_MODE_INT of a MODE_PARTIAL_INT mode.
* genmodes.c (make_vector_mode): Allow making VECTOR_MODE_INT of a
MODE_PARTIAL_INT mode.
* config/bfin/bfin-modes.def: Add V2PDI and V2SI.
* config/bfin/bfin.c (print_operand): Add macflag and mac/msu modifiers
for CONST_INTs.
(hard_regno_mode_ok): V2PDImode is ok for accumulators.
* config/bfin/bfin.h (CLASS_MAX_NREGS, HARD_REGNO_NREGS): Handle
V2PDImode.
* config/bfin/predicates.md (const01_operand, vec_shift_operand):
New predicates.
* config/bfin/bfin.md (UNSPEC_MUL_WITH_FLAG, UNSPEC_MAC_WITH_FLAG):
New constants.
(MACFLAG_NONE, MACFLAG_T, MACFLAG_FU, MACFLAG_TFU, MACFLAG_IS,
MACFLAG_IU, MACFLAG_W32, MACFLAG_M, MACFLAG_S2RND, MACFLAG_ISS2,
MACFLAG_IH): Likewise.
(movstricthi_1): Renamed from "*movstricthi".
(load_accumulator, load_accumulator_pair, movsi_insv, insv,
ssaddsi3, sssubsi3, ssnegsi2, signbitssi2, smaxhi3, sminhi3,
abshi2, neghi2, ssneghi2, signbitshi2, movhi_low2high,
movhi_high2high, movhi_low2low, movhi_high2low, movhiv2hi_low,
movhiv2hi_high, composev2hi, movv2hi_hi, movv2hi_hi_low,
movv2hi_hi_high, ssaddhi3, sssubhi3, ssaddv2hi3, sssubv2hi3,
addsubv2hi3, subaddv2hi3, ssaddsubv2hi3, sssubaddv2hi3,
sublohiv2hi3, subhilov2hi3, sssublohiv2hi3, sssubhilov2hi3,
addlohiv2hi3, addhilov2hi3, ssaddlohiv2hi3, ssaddhilov2hi3,
mulhisi_ll, mulhisi_lh, mulhisi_hl, mulhisi_hh, ssnegv2hi2,
ssashiftv2hi3, ssashifthi3, lshiftv2hi3, lshifthi3, packv2hi,
flag_mulhi, flag_mulhisi_parts, flag_machi, flag_machi_acconly,
flag_macinithi, flag_macinit1hi, flag_mulv2hi, flag_mulv2hi_parts,
flag_macv2hi_parts, flag_macv2hi_parts_acconly,
flag_macinitv2hi_parts, flag_macinit1v2hi_parts): New patterns.
From-SVN: r113245
2006-04-25 13:49:27 +02:00
|
|
|
|
""
|
|
|
|
|
"@
|
|
|
|
|
/* optimized out */
|
rtlanal.c (note_uses): Deal with SEQUENCEs.
* rtlanal.c (note_uses): Deal with SEQUENCEs.
* config/bfin/bfin.c: Include "timevar.h".
(bfin_flag_schedule_insns2, splitting_for_sched,
bfin_flag_var_tracking): New variables.
(print_operand): Handle '%!'.
(override_options): Disable normal sched2 pass, instead set
bfin_flag_schedule_insns2 for reorg to handle it.
(output_file_start): Likewise for var-tracking.
(bfin_optimize_loop): Take some care not to stumble over SEQUENCEs.
(gen_one_bundle, bfin_gen_bundles, type_for_anomaly, trapping_loads_p):
New functions.
(bfin_reorg): Do second scheduling pass here, and call
bfin_gen_bundles. Use type_for_anomaly and trapping_loads_p instead
of examining insns directly. If bfin_flag_var_tracking, call
var-tracking pass when done with everything else.
* config/bfin/bfin.h (PRINT_OPERAND_PUNCT_VALID_P): '!' is valid.
* config/bfin/bfin.md (UNSPEC_32BIT): New constant.
(movsi_insn32): New pattern, with two new splits to create it
before the final scheduling pass.
(neghi2): Not a dsp32 insn, rather alu0.
(movbi, pushsi_insn, popsi_insn, movsi_insn, movv2hi_insn, movhi_insn,
movqi_insn, movsf_insn, movsi_insv, extendhisi2, zero_extendhisi2,
extendqihi2, extendqisi2, zero_extendqihi2, zero_extendqisi2,
mulhisi3, umulhisi3, ssadsi3, sssubsi3, smaxsi3, sminsi3, abssi2,
ssnegsi2, signbitssi2, smaxhi3, sminhi3, abshi2, ssneghi2, signbitshi2,
movhi_low2high, movhi_high2high, movhi_low2low, movhi_high2low,
movhiv2hi_low, movhiv2hi_high, composev2hi, packv2hi, movv2hi_hi,
ssaddhi3, sssubhi3, addv2hi3, ssaddv2hi3, subv2hi3, sssubv2hi3,
addsubv2hi3, subaddv2hi3, ssaddsubv2hi3, sssubaddv2hi3, sublohiv2hi3,
subhilov2hi3, sssublohiv2hi3, sssubhilov2hi3, addlohiv2hi3,
addhilov2hi3, ssaddlohiv2hi3, ssaddhilov2hi3, sminv2hi3, smaxv2hi3,
flag_mulhi, flag_mulhisi, flag_mulhisi_parts, flag_machi,
flag_machi_acconly, flag_macinithi, flag_macinit1hi, mulv2hi3,
flag_mulv2hi, flag_mulv2hi_parts, flag_macv2hi_parts,
flag_macv2hi_parts_acconly, flag_macinitv2hi_parts,
flag_macinit1v2hi_parts, mulhisi_ll, mulhisi_lh, mulhisi_hl,
mulhisi_hh, ssnegv2hi2, absv2hi2, ssashiftv2hi3, ssashifthi3,
lshiftv2hi3, lshifthi3): Use '%!' to terminate all dsp32/load/store
variants instead of ';'.
(ror_one, rol_one): Likewise. Make them dsp32 insns.
(ashlsi3_insn, ashrsi3, lshrsi3): Add dsp32 variants.
(align8, align16, align24): Now named patterns; also using '%!'.
(mnop): New insn.
From-SVN: r119534
2006-12-05 09:49:56 +01:00
|
|
|
|
%h0 = %h1 << 0%!
|
|
|
|
|
%h0 = %d1 << 0%!"
|
From Jie Zhang <jie.zhang@analog.com>:
* config/bfin/predicates.md (p_register_operand): New
predicate.
(dp_register_operand): New predicate.
* config/bfin/bfin-protos.h (WA_05000074): Define.
(ENABLE_WA_05000074): Define.
* config/bfin/bfin.c (bfin_cpus[]): Add WA_05000074 for
all cpus.
(bfin_gen_bundles): Put dsp32shiftimm instruction in slot[0].
* config/bfin/bfin.md (define_attr type): Add dsp32shiftimm.
(define_attr addrtype): Allow load/store register to be
P register.
(define_attr storereg): New.
(define_cpu_unit anomaly_05000074): New.
(define_insn_reservation dsp32shiftimm): New.
(define_insn_reservation dsp32shiftimm_anomaly_05000074): New.
(define_insn_reservation loadp): Cannot use slot2.
(define_insn_reservation loadsp): Cannot use slot2.
(define_insn_reservation storep): Cannot use slot2. Does not
apply when working around 05000074.
(define_insn_reservation storep_anomaly_05000074): New.
(define_insn_reservation storei): Does not apply when working
around 05000074.
(define_insn_reservation storei_anomaly_05000074): New.
(define_attr length): Add dsp32shiftimm case.
(define_insn movsi_insn32, movsi_insv, ashlsi3_insn, ashrsi3,
ror_one, rol_one, lshrsi3, lshrpdi3, ashrpdi3, movhiv2hi_low,
movhiv2hi_high, composev2hi, packv2hi, movv2hi_hi,
ssashiftv2hi3, ssashifthi3, ssashiftsi3, lshiftv2hi3, lshifthi3):
Set type as dsp32shiftimm for dsp32shiftimm alternatives.
From-SVN: r151490
2009-09-07 23:40:23 +02:00
|
|
|
|
[(set_attr "type" "dsp32shiftimm")])
|
genmodes.c (make_vector_mode): Allow making VECTOR_MODE_INT of a MODE_PARTIAL_INT mode.
* genmodes.c (make_vector_mode): Allow making VECTOR_MODE_INT of a
MODE_PARTIAL_INT mode.
* config/bfin/bfin-modes.def: Add V2PDI and V2SI.
* config/bfin/bfin.c (print_operand): Add macflag and mac/msu modifiers
for CONST_INTs.
(hard_regno_mode_ok): V2PDImode is ok for accumulators.
* config/bfin/bfin.h (CLASS_MAX_NREGS, HARD_REGNO_NREGS): Handle
V2PDImode.
* config/bfin/predicates.md (const01_operand, vec_shift_operand):
New predicates.
* config/bfin/bfin.md (UNSPEC_MUL_WITH_FLAG, UNSPEC_MAC_WITH_FLAG):
New constants.
(MACFLAG_NONE, MACFLAG_T, MACFLAG_FU, MACFLAG_TFU, MACFLAG_IS,
MACFLAG_IU, MACFLAG_W32, MACFLAG_M, MACFLAG_S2RND, MACFLAG_ISS2,
MACFLAG_IH): Likewise.
(movstricthi_1): Renamed from "*movstricthi".
(load_accumulator, load_accumulator_pair, movsi_insv, insv,
ssaddsi3, sssubsi3, ssnegsi2, signbitssi2, smaxhi3, sminhi3,
abshi2, neghi2, ssneghi2, signbitshi2, movhi_low2high,
movhi_high2high, movhi_low2low, movhi_high2low, movhiv2hi_low,
movhiv2hi_high, composev2hi, movv2hi_hi, movv2hi_hi_low,
movv2hi_hi_high, ssaddhi3, sssubhi3, ssaddv2hi3, sssubv2hi3,
addsubv2hi3, subaddv2hi3, ssaddsubv2hi3, sssubaddv2hi3,
sublohiv2hi3, subhilov2hi3, sssublohiv2hi3, sssubhilov2hi3,
addlohiv2hi3, addhilov2hi3, ssaddlohiv2hi3, ssaddhilov2hi3,
mulhisi_ll, mulhisi_lh, mulhisi_hl, mulhisi_hh, ssnegv2hi2,
ssashiftv2hi3, ssashifthi3, lshiftv2hi3, lshifthi3, packv2hi,
flag_mulhi, flag_mulhisi_parts, flag_machi, flag_machi_acconly,
flag_macinithi, flag_macinit1hi, flag_mulv2hi, flag_mulv2hi_parts,
flag_macv2hi_parts, flag_macv2hi_parts_acconly,
flag_macinitv2hi_parts, flag_macinit1v2hi_parts): New patterns.
From-SVN: r113245
2006-04-25 13:49:27 +02:00
|
|
|
|
|
|
|
|
|
(define_expand "movv2hi_hi_low"
|
|
|
|
|
[(set (match_operand:HI 0 "register_operand" "")
|
|
|
|
|
(vec_select:HI (match_operand:V2HI 1 "register_operand" "")
|
|
|
|
|
(parallel [(const_int 0)])))]
|
|
|
|
|
""
|
|
|
|
|
"")
|
|
|
|
|
|
|
|
|
|
(define_expand "movv2hi_hi_high"
|
|
|
|
|
[(set (match_operand:HI 0 "register_operand" "")
|
|
|
|
|
(vec_select:HI (match_operand:V2HI 1 "register_operand" "")
|
|
|
|
|
(parallel [(const_int 1)])))]
|
|
|
|
|
""
|
|
|
|
|
"")
|
|
|
|
|
|
2007-02-04 17:40:30 +01:00
|
|
|
|
;; Unusual arithmetic operations on 16-bit registers.
|
genmodes.c (make_vector_mode): Allow making VECTOR_MODE_INT of a MODE_PARTIAL_INT mode.
* genmodes.c (make_vector_mode): Allow making VECTOR_MODE_INT of a
MODE_PARTIAL_INT mode.
* config/bfin/bfin-modes.def: Add V2PDI and V2SI.
* config/bfin/bfin.c (print_operand): Add macflag and mac/msu modifiers
for CONST_INTs.
(hard_regno_mode_ok): V2PDImode is ok for accumulators.
* config/bfin/bfin.h (CLASS_MAX_NREGS, HARD_REGNO_NREGS): Handle
V2PDImode.
* config/bfin/predicates.md (const01_operand, vec_shift_operand):
New predicates.
* config/bfin/bfin.md (UNSPEC_MUL_WITH_FLAG, UNSPEC_MAC_WITH_FLAG):
New constants.
(MACFLAG_NONE, MACFLAG_T, MACFLAG_FU, MACFLAG_TFU, MACFLAG_IS,
MACFLAG_IU, MACFLAG_W32, MACFLAG_M, MACFLAG_S2RND, MACFLAG_ISS2,
MACFLAG_IH): Likewise.
(movstricthi_1): Renamed from "*movstricthi".
(load_accumulator, load_accumulator_pair, movsi_insv, insv,
ssaddsi3, sssubsi3, ssnegsi2, signbitssi2, smaxhi3, sminhi3,
abshi2, neghi2, ssneghi2, signbitshi2, movhi_low2high,
movhi_high2high, movhi_low2low, movhi_high2low, movhiv2hi_low,
movhiv2hi_high, composev2hi, movv2hi_hi, movv2hi_hi_low,
movv2hi_hi_high, ssaddhi3, sssubhi3, ssaddv2hi3, sssubv2hi3,
addsubv2hi3, subaddv2hi3, ssaddsubv2hi3, sssubaddv2hi3,
sublohiv2hi3, subhilov2hi3, sssublohiv2hi3, sssubhilov2hi3,
addlohiv2hi3, addhilov2hi3, ssaddlohiv2hi3, ssaddhilov2hi3,
mulhisi_ll, mulhisi_lh, mulhisi_hl, mulhisi_hh, ssnegv2hi2,
ssashiftv2hi3, ssashifthi3, lshiftv2hi3, lshifthi3, packv2hi,
flag_mulhi, flag_mulhisi_parts, flag_machi, flag_machi_acconly,
flag_macinithi, flag_macinit1hi, flag_mulv2hi, flag_mulv2hi_parts,
flag_macv2hi_parts, flag_macv2hi_parts_acconly,
flag_macinitv2hi_parts, flag_macinit1v2hi_parts): New patterns.
From-SVN: r113245
2006-04-25 13:49:27 +02:00
|
|
|
|
|
bfin.md (sp_or_sm, [...]): New macro.
gcc/
* config/bfin/bfin.md (sp_or_sm, spm_string, spm_name): New macro.
(ss<spm_name>hi3, ss<spm_name>hi3_parts, ss<spm_name>hi3_low_parts,
ss<spm_name_hi3_high_parts): New patterns, replacing ssaddhi3, ssubhi3,
ssaddhi3_parts and sssubhi3_parts.
(flag_mulhi3_parts): Produce a HImode output rather than trying to set
a VEC_SELECT.
* config/bfin/bfin.c (bfin_expand_builtin, case BFIN_BUILTIN_CPLX_SQU):
Adjust accordingly.
gcc/testsuite/
* gcc.target/bfin/20090411-1.c: New test.
From-SVN: r146929
2009-04-29 10:41:32 +02:00
|
|
|
|
(define_code_iterator sp_or_sm [ss_plus ss_minus])
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(define_code_attr spm_string [(ss_plus "+") (ss_minus "-")])
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(define_code_attr spm_name [(ss_plus "add") (ss_minus "sub")])
|
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(define_insn "ss<spm_name>hi3"
|
genmodes.c (make_vector_mode): Allow making VECTOR_MODE_INT of a MODE_PARTIAL_INT mode.
* genmodes.c (make_vector_mode): Allow making VECTOR_MODE_INT of a
MODE_PARTIAL_INT mode.
* config/bfin/bfin-modes.def: Add V2PDI and V2SI.
* config/bfin/bfin.c (print_operand): Add macflag and mac/msu modifiers
for CONST_INTs.
(hard_regno_mode_ok): V2PDImode is ok for accumulators.
* config/bfin/bfin.h (CLASS_MAX_NREGS, HARD_REGNO_NREGS): Handle
V2PDImode.
* config/bfin/predicates.md (const01_operand, vec_shift_operand):
New predicates.
* config/bfin/bfin.md (UNSPEC_MUL_WITH_FLAG, UNSPEC_MAC_WITH_FLAG):
New constants.
(MACFLAG_NONE, MACFLAG_T, MACFLAG_FU, MACFLAG_TFU, MACFLAG_IS,
MACFLAG_IU, MACFLAG_W32, MACFLAG_M, MACFLAG_S2RND, MACFLAG_ISS2,
MACFLAG_IH): Likewise.
(movstricthi_1): Renamed from "*movstricthi".
(load_accumulator, load_accumulator_pair, movsi_insv, insv,
ssaddsi3, sssubsi3, ssnegsi2, signbitssi2, smaxhi3, sminhi3,
abshi2, neghi2, ssneghi2, signbitshi2, movhi_low2high,
movhi_high2high, movhi_low2low, movhi_high2low, movhiv2hi_low,
movhiv2hi_high, composev2hi, movv2hi_hi, movv2hi_hi_low,
movv2hi_hi_high, ssaddhi3, sssubhi3, ssaddv2hi3, sssubv2hi3,
addsubv2hi3, subaddv2hi3, ssaddsubv2hi3, sssubaddv2hi3,
sublohiv2hi3, subhilov2hi3, sssublohiv2hi3, sssubhilov2hi3,
addlohiv2hi3, addhilov2hi3, ssaddlohiv2hi3, ssaddhilov2hi3,
mulhisi_ll, mulhisi_lh, mulhisi_hl, mulhisi_hh, ssnegv2hi2,
ssashiftv2hi3, ssashifthi3, lshiftv2hi3, lshifthi3, packv2hi,
flag_mulhi, flag_mulhisi_parts, flag_machi, flag_machi_acconly,
flag_macinithi, flag_macinit1hi, flag_mulv2hi, flag_mulv2hi_parts,
flag_macv2hi_parts, flag_macv2hi_parts_acconly,
flag_macinitv2hi_parts, flag_macinit1v2hi_parts): New patterns.
From-SVN: r113245
2006-04-25 13:49:27 +02:00
|
|
|
|
[(set (match_operand:HI 0 "register_operand" "=d")
|
bfin.md (sp_or_sm, [...]): New macro.
gcc/
* config/bfin/bfin.md (sp_or_sm, spm_string, spm_name): New macro.
(ss<spm_name>hi3, ss<spm_name>hi3_parts, ss<spm_name>hi3_low_parts,
ss<spm_name_hi3_high_parts): New patterns, replacing ssaddhi3, ssubhi3,
ssaddhi3_parts and sssubhi3_parts.
(flag_mulhi3_parts): Produce a HImode output rather than trying to set
a VEC_SELECT.
* config/bfin/bfin.c (bfin_expand_builtin, case BFIN_BUILTIN_CPLX_SQU):
Adjust accordingly.
gcc/testsuite/
* gcc.target/bfin/20090411-1.c: New test.
From-SVN: r146929
2009-04-29 10:41:32 +02:00
|
|
|
|
(sp_or_sm:HI (match_operand:HI 1 "register_operand" "d")
|
genmodes.c (make_vector_mode): Allow making VECTOR_MODE_INT of a MODE_PARTIAL_INT mode.
* genmodes.c (make_vector_mode): Allow making VECTOR_MODE_INT of a
MODE_PARTIAL_INT mode.
* config/bfin/bfin-modes.def: Add V2PDI and V2SI.
* config/bfin/bfin.c (print_operand): Add macflag and mac/msu modifiers
for CONST_INTs.
(hard_regno_mode_ok): V2PDImode is ok for accumulators.
* config/bfin/bfin.h (CLASS_MAX_NREGS, HARD_REGNO_NREGS): Handle
V2PDImode.
* config/bfin/predicates.md (const01_operand, vec_shift_operand):
New predicates.
* config/bfin/bfin.md (UNSPEC_MUL_WITH_FLAG, UNSPEC_MAC_WITH_FLAG):
New constants.
(MACFLAG_NONE, MACFLAG_T, MACFLAG_FU, MACFLAG_TFU, MACFLAG_IS,
MACFLAG_IU, MACFLAG_W32, MACFLAG_M, MACFLAG_S2RND, MACFLAG_ISS2,
MACFLAG_IH): Likewise.
(movstricthi_1): Renamed from "*movstricthi".
(load_accumulator, load_accumulator_pair, movsi_insv, insv,
ssaddsi3, sssubsi3, ssnegsi2, signbitssi2, smaxhi3, sminhi3,
abshi2, neghi2, ssneghi2, signbitshi2, movhi_low2high,
movhi_high2high, movhi_low2low, movhi_high2low, movhiv2hi_low,
movhiv2hi_high, composev2hi, movv2hi_hi, movv2hi_hi_low,
movv2hi_hi_high, ssaddhi3, sssubhi3, ssaddv2hi3, sssubv2hi3,
addsubv2hi3, subaddv2hi3, ssaddsubv2hi3, sssubaddv2hi3,
sublohiv2hi3, subhilov2hi3, sssublohiv2hi3, sssubhilov2hi3,
addlohiv2hi3, addhilov2hi3, ssaddlohiv2hi3, ssaddhilov2hi3,
mulhisi_ll, mulhisi_lh, mulhisi_hl, mulhisi_hh, ssnegv2hi2,
ssashiftv2hi3, ssashifthi3, lshiftv2hi3, lshifthi3, packv2hi,
flag_mulhi, flag_mulhisi_parts, flag_machi, flag_machi_acconly,
flag_macinithi, flag_macinit1hi, flag_mulv2hi, flag_mulv2hi_parts,
flag_macv2hi_parts, flag_macv2hi_parts_acconly,
flag_macinitv2hi_parts, flag_macinit1v2hi_parts): New patterns.
From-SVN: r113245
2006-04-25 13:49:27 +02:00
|
|
|
|
(match_operand:HI 2 "register_operand" "d")))]
|
|
|
|
|
""
|
bfin.md (sp_or_sm, [...]): New macro.
gcc/
* config/bfin/bfin.md (sp_or_sm, spm_string, spm_name): New macro.
(ss<spm_name>hi3, ss<spm_name>hi3_parts, ss<spm_name>hi3_low_parts,
ss<spm_name_hi3_high_parts): New patterns, replacing ssaddhi3, ssubhi3,
ssaddhi3_parts and sssubhi3_parts.
(flag_mulhi3_parts): Produce a HImode output rather than trying to set
a VEC_SELECT.
* config/bfin/bfin.c (bfin_expand_builtin, case BFIN_BUILTIN_CPLX_SQU):
Adjust accordingly.
gcc/testsuite/
* gcc.target/bfin/20090411-1.c: New test.
From-SVN: r146929
2009-04-29 10:41:32 +02:00
|
|
|
|
"%h0 = %h1 <spm_string> %h2 (S)%!"
|
genmodes.c (make_vector_mode): Allow making VECTOR_MODE_INT of a MODE_PARTIAL_INT mode.
* genmodes.c (make_vector_mode): Allow making VECTOR_MODE_INT of a
MODE_PARTIAL_INT mode.
* config/bfin/bfin-modes.def: Add V2PDI and V2SI.
* config/bfin/bfin.c (print_operand): Add macflag and mac/msu modifiers
for CONST_INTs.
(hard_regno_mode_ok): V2PDImode is ok for accumulators.
* config/bfin/bfin.h (CLASS_MAX_NREGS, HARD_REGNO_NREGS): Handle
V2PDImode.
* config/bfin/predicates.md (const01_operand, vec_shift_operand):
New predicates.
* config/bfin/bfin.md (UNSPEC_MUL_WITH_FLAG, UNSPEC_MAC_WITH_FLAG):
New constants.
(MACFLAG_NONE, MACFLAG_T, MACFLAG_FU, MACFLAG_TFU, MACFLAG_IS,
MACFLAG_IU, MACFLAG_W32, MACFLAG_M, MACFLAG_S2RND, MACFLAG_ISS2,
MACFLAG_IH): Likewise.
(movstricthi_1): Renamed from "*movstricthi".
(load_accumulator, load_accumulator_pair, movsi_insv, insv,
ssaddsi3, sssubsi3, ssnegsi2, signbitssi2, smaxhi3, sminhi3,
abshi2, neghi2, ssneghi2, signbitshi2, movhi_low2high,
movhi_high2high, movhi_low2low, movhi_high2low, movhiv2hi_low,
movhiv2hi_high, composev2hi, movv2hi_hi, movv2hi_hi_low,
movv2hi_hi_high, ssaddhi3, sssubhi3, ssaddv2hi3, sssubv2hi3,
addsubv2hi3, subaddv2hi3, ssaddsubv2hi3, sssubaddv2hi3,
sublohiv2hi3, subhilov2hi3, sssublohiv2hi3, sssubhilov2hi3,
addlohiv2hi3, addhilov2hi3, ssaddlohiv2hi3, ssaddhilov2hi3,
mulhisi_ll, mulhisi_lh, mulhisi_hl, mulhisi_hh, ssnegv2hi2,
ssashiftv2hi3, ssashifthi3, lshiftv2hi3, lshifthi3, packv2hi,
flag_mulhi, flag_mulhisi_parts, flag_machi, flag_machi_acconly,
flag_macinithi, flag_macinit1hi, flag_mulv2hi, flag_mulv2hi_parts,
flag_macv2hi_parts, flag_macv2hi_parts_acconly,
flag_macinitv2hi_parts, flag_macinit1v2hi_parts): New patterns.
From-SVN: r113245
2006-04-25 13:49:27 +02:00
|
|
|
|
[(set_attr "type" "dsp32")])
|
|
|
|
|
|
bfin.md (sp_or_sm, [...]): New macro.
gcc/
* config/bfin/bfin.md (sp_or_sm, spm_string, spm_name): New macro.
(ss<spm_name>hi3, ss<spm_name>hi3_parts, ss<spm_name>hi3_low_parts,
ss<spm_name_hi3_high_parts): New patterns, replacing ssaddhi3, ssubhi3,
ssaddhi3_parts and sssubhi3_parts.
(flag_mulhi3_parts): Produce a HImode output rather than trying to set
a VEC_SELECT.
* config/bfin/bfin.c (bfin_expand_builtin, case BFIN_BUILTIN_CPLX_SQU):
Adjust accordingly.
gcc/testsuite/
* gcc.target/bfin/20090411-1.c: New test.
From-SVN: r146929
2009-04-29 10:41:32 +02:00
|
|
|
|
(define_insn "ss<spm_name>hi3_parts"
|
|
|
|
|
[(set (match_operand:HI 0 "register_operand" "=d")
|
|
|
|
|
(sp_or_sm:HI (vec_select:HI
|
|
|
|
|
(match_operand:V2HI 1 "register_operand" "d")
|
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|
(parallel [(match_operand 3 "const01_operand" "P0P1")]))
|
|
|
|
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(vec_select:HI
|
|
|
|
|
(match_operand:V2HI 2 "register_operand" "d")
|
|
|
|
|
(parallel [(match_operand 4 "const01_operand" "P0P1")]))))]
|
|
|
|
|
""
|
From Jie Zhang:
* config/bfin/bfin.c (enum bfin_builtins): Add BFIN_BUILTIN_ONES,
BFIN_BUILTIN_CPLX_MUL_16_S40, BFIN_BUILTIN_CPLX_MAC_16_S40,
BFIN_BUILTIN_CPLX_MSU_16_S40, and BFIN_BUILTIN_CPLX_SQU.
(bfin_init_builtins): Initialize __builtin_bfin_ones,
__builtin_bfin_min_fr1x16, __builtin_bfin_max_fr1x16,
__builtin_bfin_min_fr1x32, __builtin_bfin_max_fr1x32,
__builtin_bfin_cmplx_add, __builtin_bfin_cmplx_sub,
__builtin_bfin_cmplx_mul_s40, __builtin_bfin_cmplx_mac_s40,
__builtin_bfin_cmplx_msu_s40 and __builtin_bfin_csqu_fr16.
(bdesc_1arg): Add __builtin_bfin_ones.
(bfin_expand_builtin): Expand __builtin_bfin_cmplx_mul_s40,
__builtin_bfin_cmplx_mac_s40, __builtin_bfin_cmplx_msu_s40,
and __builtin_bfin_csqu_fr16.
* config/bfin/bfin.md (UNSPEC_ONES): New constant.
(ones): New define_insn.
(ssaddhi3_parts): New define_insn.
(sssubhi3_parts): New define_insn.
(flag_mulhi_parts): New define_insn.
From-SVN: r128475
2007-09-13 20:27:28 +02:00
|
|
|
|
{
|
|
|
|
|
const char *templates[] = {
|
bfin.md (sp_or_sm, [...]): New macro.
gcc/
* config/bfin/bfin.md (sp_or_sm, spm_string, spm_name): New macro.
(ss<spm_name>hi3, ss<spm_name>hi3_parts, ss<spm_name>hi3_low_parts,
ss<spm_name_hi3_high_parts): New patterns, replacing ssaddhi3, ssubhi3,
ssaddhi3_parts and sssubhi3_parts.
(flag_mulhi3_parts): Produce a HImode output rather than trying to set
a VEC_SELECT.
* config/bfin/bfin.c (bfin_expand_builtin, case BFIN_BUILTIN_CPLX_SQU):
Adjust accordingly.
gcc/testsuite/
* gcc.target/bfin/20090411-1.c: New test.
From-SVN: r146929
2009-04-29 10:41:32 +02:00
|
|
|
|
"%h0 = %h1 <spm_string> %h2 (S)%!",
|
|
|
|
|
"%h0 = %d1 <spm_string> %h2 (S)%!",
|
|
|
|
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"%h0 = %h1 <spm_string> %d2 (S)%!",
|
|
|
|
|
"%h0 = %d1 <spm_string> %d2 (S)%!" };
|
|
|
|
|
int alt = INTVAL (operands[3]) + (INTVAL (operands[4]) << 1);
|
From Jie Zhang:
* config/bfin/bfin.c (enum bfin_builtins): Add BFIN_BUILTIN_ONES,
BFIN_BUILTIN_CPLX_MUL_16_S40, BFIN_BUILTIN_CPLX_MAC_16_S40,
BFIN_BUILTIN_CPLX_MSU_16_S40, and BFIN_BUILTIN_CPLX_SQU.
(bfin_init_builtins): Initialize __builtin_bfin_ones,
__builtin_bfin_min_fr1x16, __builtin_bfin_max_fr1x16,
__builtin_bfin_min_fr1x32, __builtin_bfin_max_fr1x32,
__builtin_bfin_cmplx_add, __builtin_bfin_cmplx_sub,
__builtin_bfin_cmplx_mul_s40, __builtin_bfin_cmplx_mac_s40,
__builtin_bfin_cmplx_msu_s40 and __builtin_bfin_csqu_fr16.
(bdesc_1arg): Add __builtin_bfin_ones.
(bfin_expand_builtin): Expand __builtin_bfin_cmplx_mul_s40,
__builtin_bfin_cmplx_mac_s40, __builtin_bfin_cmplx_msu_s40,
and __builtin_bfin_csqu_fr16.
* config/bfin/bfin.md (UNSPEC_ONES): New constant.
(ones): New define_insn.
(ssaddhi3_parts): New define_insn.
(sssubhi3_parts): New define_insn.
(flag_mulhi_parts): New define_insn.
From-SVN: r128475
2007-09-13 20:27:28 +02:00
|
|
|
|
return templates[alt];
|
|
|
|
|
}
|
|
|
|
|
[(set_attr "type" "dsp32")])
|
|
|
|
|
|
bfin.md (sp_or_sm, [...]): New macro.
gcc/
* config/bfin/bfin.md (sp_or_sm, spm_string, spm_name): New macro.
(ss<spm_name>hi3, ss<spm_name>hi3_parts, ss<spm_name>hi3_low_parts,
ss<spm_name_hi3_high_parts): New patterns, replacing ssaddhi3, ssubhi3,
ssaddhi3_parts and sssubhi3_parts.
(flag_mulhi3_parts): Produce a HImode output rather than trying to set
a VEC_SELECT.
* config/bfin/bfin.c (bfin_expand_builtin, case BFIN_BUILTIN_CPLX_SQU):
Adjust accordingly.
gcc/testsuite/
* gcc.target/bfin/20090411-1.c: New test.
From-SVN: r146929
2009-04-29 10:41:32 +02:00
|
|
|
|
(define_insn "ss<spm_name>hi3_low_parts"
|
|
|
|
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[(set (match_operand:V2HI 0 "register_operand" "=d")
|
|
|
|
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(vec_concat:V2HI
|
|
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|
|
(vec_select:HI (match_operand:V2HI 1 "register_operand" "0")
|
|
|
|
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(parallel [(const_int 0)]))
|
|
|
|
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(sp_or_sm:HI (vec_select:HI
|
|
|
|
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(match_operand:V2HI 2 "register_operand" "d")
|
|
|
|
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(parallel [(match_operand 4 "const01_operand" "P0P1")]))
|
|
|
|
|
(vec_select:HI
|
|
|
|
|
(match_operand:V2HI 3 "register_operand" "d")
|
|
|
|
|
(parallel [(match_operand 5 "const01_operand" "P0P1")])))))]
|
|
|
|
|
""
|
From Jie Zhang:
* config/bfin/bfin.c (enum bfin_builtins): Add BFIN_BUILTIN_ONES,
BFIN_BUILTIN_CPLX_MUL_16_S40, BFIN_BUILTIN_CPLX_MAC_16_S40,
BFIN_BUILTIN_CPLX_MSU_16_S40, and BFIN_BUILTIN_CPLX_SQU.
(bfin_init_builtins): Initialize __builtin_bfin_ones,
__builtin_bfin_min_fr1x16, __builtin_bfin_max_fr1x16,
__builtin_bfin_min_fr1x32, __builtin_bfin_max_fr1x32,
__builtin_bfin_cmplx_add, __builtin_bfin_cmplx_sub,
__builtin_bfin_cmplx_mul_s40, __builtin_bfin_cmplx_mac_s40,
__builtin_bfin_cmplx_msu_s40 and __builtin_bfin_csqu_fr16.
(bdesc_1arg): Add __builtin_bfin_ones.
(bfin_expand_builtin): Expand __builtin_bfin_cmplx_mul_s40,
__builtin_bfin_cmplx_mac_s40, __builtin_bfin_cmplx_msu_s40,
and __builtin_bfin_csqu_fr16.
* config/bfin/bfin.md (UNSPEC_ONES): New constant.
(ones): New define_insn.
(ssaddhi3_parts): New define_insn.
(sssubhi3_parts): New define_insn.
(flag_mulhi_parts): New define_insn.
From-SVN: r128475
2007-09-13 20:27:28 +02:00
|
|
|
|
{
|
|
|
|
|
const char *templates[] = {
|
bfin.md (sp_or_sm, [...]): New macro.
gcc/
* config/bfin/bfin.md (sp_or_sm, spm_string, spm_name): New macro.
(ss<spm_name>hi3, ss<spm_name>hi3_parts, ss<spm_name>hi3_low_parts,
ss<spm_name_hi3_high_parts): New patterns, replacing ssaddhi3, ssubhi3,
ssaddhi3_parts and sssubhi3_parts.
(flag_mulhi3_parts): Produce a HImode output rather than trying to set
a VEC_SELECT.
* config/bfin/bfin.c (bfin_expand_builtin, case BFIN_BUILTIN_CPLX_SQU):
Adjust accordingly.
gcc/testsuite/
* gcc.target/bfin/20090411-1.c: New test.
From-SVN: r146929
2009-04-29 10:41:32 +02:00
|
|
|
|
"%h0 = %h2 <spm_string> %h3 (S)%!",
|
|
|
|
|
"%h0 = %d2 <spm_string> %h3 (S)%!",
|
|
|
|
|
"%h0 = %h2 <spm_string> %d3 (S)%!",
|
|
|
|
|
"%h0 = %d2 <spm_string> %d3 (S)%!" };
|
|
|
|
|
int alt = INTVAL (operands[4]) + (INTVAL (operands[5]) << 1);
|
From Jie Zhang:
* config/bfin/bfin.c (enum bfin_builtins): Add BFIN_BUILTIN_ONES,
BFIN_BUILTIN_CPLX_MUL_16_S40, BFIN_BUILTIN_CPLX_MAC_16_S40,
BFIN_BUILTIN_CPLX_MSU_16_S40, and BFIN_BUILTIN_CPLX_SQU.
(bfin_init_builtins): Initialize __builtin_bfin_ones,
__builtin_bfin_min_fr1x16, __builtin_bfin_max_fr1x16,
__builtin_bfin_min_fr1x32, __builtin_bfin_max_fr1x32,
__builtin_bfin_cmplx_add, __builtin_bfin_cmplx_sub,
__builtin_bfin_cmplx_mul_s40, __builtin_bfin_cmplx_mac_s40,
__builtin_bfin_cmplx_msu_s40 and __builtin_bfin_csqu_fr16.
(bdesc_1arg): Add __builtin_bfin_ones.
(bfin_expand_builtin): Expand __builtin_bfin_cmplx_mul_s40,
__builtin_bfin_cmplx_mac_s40, __builtin_bfin_cmplx_msu_s40,
and __builtin_bfin_csqu_fr16.
* config/bfin/bfin.md (UNSPEC_ONES): New constant.
(ones): New define_insn.
(ssaddhi3_parts): New define_insn.
(sssubhi3_parts): New define_insn.
(flag_mulhi_parts): New define_insn.
From-SVN: r128475
2007-09-13 20:27:28 +02:00
|
|
|
|
return templates[alt];
|
|
|
|
|
}
|
|
|
|
|
[(set_attr "type" "dsp32")])
|
|
|
|
|
|
bfin.md (sp_or_sm, [...]): New macro.
gcc/
* config/bfin/bfin.md (sp_or_sm, spm_string, spm_name): New macro.
(ss<spm_name>hi3, ss<spm_name>hi3_parts, ss<spm_name>hi3_low_parts,
ss<spm_name_hi3_high_parts): New patterns, replacing ssaddhi3, ssubhi3,
ssaddhi3_parts and sssubhi3_parts.
(flag_mulhi3_parts): Produce a HImode output rather than trying to set
a VEC_SELECT.
* config/bfin/bfin.c (bfin_expand_builtin, case BFIN_BUILTIN_CPLX_SQU):
Adjust accordingly.
gcc/testsuite/
* gcc.target/bfin/20090411-1.c: New test.
From-SVN: r146929
2009-04-29 10:41:32 +02:00
|
|
|
|
(define_insn "ss<spm_name>hi3_high_parts"
|
|
|
|
|
[(set (match_operand:V2HI 0 "register_operand" "=d")
|
|
|
|
|
(vec_concat:V2HI
|
|
|
|
|
(sp_or_sm:HI (vec_select:HI
|
|
|
|
|
(match_operand:V2HI 2 "register_operand" "d")
|
|
|
|
|
(parallel [(match_operand 4 "const01_operand" "P0P1")]))
|
|
|
|
|
(vec_select:HI
|
|
|
|
|
(match_operand:V2HI 3 "register_operand" "d")
|
|
|
|
|
(parallel [(match_operand 5 "const01_operand" "P0P1")])))
|
|
|
|
|
(vec_select:HI (match_operand:V2HI 1 "register_operand" "0")
|
|
|
|
|
(parallel [(const_int 1)]))))]
|
|
|
|
|
""
|
|
|
|
|
{
|
|
|
|
|
const char *templates[] = {
|
|
|
|
|
"%d0 = %h2 <spm_string> %h3 (S)%!",
|
|
|
|
|
"%d0 = %d2 <spm_string> %h3 (S)%!",
|
|
|
|
|
"%d0 = %h2 <spm_string> %d3 (S)%!",
|
|
|
|
|
"%d0 = %d2 <spm_string> %d3 (S)%!" };
|
|
|
|
|
int alt = INTVAL (operands[4]) + (INTVAL (operands[5]) << 1);
|
|
|
|
|
return templates[alt];
|
|
|
|
|
}
|
genmodes.c (make_vector_mode): Allow making VECTOR_MODE_INT of a MODE_PARTIAL_INT mode.
* genmodes.c (make_vector_mode): Allow making VECTOR_MODE_INT of a
MODE_PARTIAL_INT mode.
* config/bfin/bfin-modes.def: Add V2PDI and V2SI.
* config/bfin/bfin.c (print_operand): Add macflag and mac/msu modifiers
for CONST_INTs.
(hard_regno_mode_ok): V2PDImode is ok for accumulators.
* config/bfin/bfin.h (CLASS_MAX_NREGS, HARD_REGNO_NREGS): Handle
V2PDImode.
* config/bfin/predicates.md (const01_operand, vec_shift_operand):
New predicates.
* config/bfin/bfin.md (UNSPEC_MUL_WITH_FLAG, UNSPEC_MAC_WITH_FLAG):
New constants.
(MACFLAG_NONE, MACFLAG_T, MACFLAG_FU, MACFLAG_TFU, MACFLAG_IS,
MACFLAG_IU, MACFLAG_W32, MACFLAG_M, MACFLAG_S2RND, MACFLAG_ISS2,
MACFLAG_IH): Likewise.
(movstricthi_1): Renamed from "*movstricthi".
(load_accumulator, load_accumulator_pair, movsi_insv, insv,
ssaddsi3, sssubsi3, ssnegsi2, signbitssi2, smaxhi3, sminhi3,
abshi2, neghi2, ssneghi2, signbitshi2, movhi_low2high,
movhi_high2high, movhi_low2low, movhi_high2low, movhiv2hi_low,
movhiv2hi_high, composev2hi, movv2hi_hi, movv2hi_hi_low,
movv2hi_hi_high, ssaddhi3, sssubhi3, ssaddv2hi3, sssubv2hi3,
addsubv2hi3, subaddv2hi3, ssaddsubv2hi3, sssubaddv2hi3,
sublohiv2hi3, subhilov2hi3, sssublohiv2hi3, sssubhilov2hi3,
addlohiv2hi3, addhilov2hi3, ssaddlohiv2hi3, ssaddhilov2hi3,
mulhisi_ll, mulhisi_lh, mulhisi_hl, mulhisi_hh, ssnegv2hi2,
ssashiftv2hi3, ssashifthi3, lshiftv2hi3, lshifthi3, packv2hi,
flag_mulhi, flag_mulhisi_parts, flag_machi, flag_machi_acconly,
flag_macinithi, flag_macinit1hi, flag_mulv2hi, flag_mulv2hi_parts,
flag_macv2hi_parts, flag_macv2hi_parts_acconly,
flag_macinitv2hi_parts, flag_macinit1v2hi_parts): New patterns.
From-SVN: r113245
2006-04-25 13:49:27 +02:00
|
|
|
|
[(set_attr "type" "dsp32")])
|
|
|
|
|
|
|
|
|
|
;; V2HI vector insns
|
|
|
|
|
|
2005-06-30 09:57:05 +02:00
|
|
|
|
(define_insn "addv2hi3"
|
2005-04-05 13:26:48 +02:00
|
|
|
|
[(set (match_operand:V2HI 0 "register_operand" "=d")
|
|
|
|
|
(plus:V2HI (match_operand:V2HI 1 "register_operand" "d")
|
|
|
|
|
(match_operand:V2HI 2 "register_operand" "d")))]
|
|
|
|
|
""
|
rtlanal.c (note_uses): Deal with SEQUENCEs.
* rtlanal.c (note_uses): Deal with SEQUENCEs.
* config/bfin/bfin.c: Include "timevar.h".
(bfin_flag_schedule_insns2, splitting_for_sched,
bfin_flag_var_tracking): New variables.
(print_operand): Handle '%!'.
(override_options): Disable normal sched2 pass, instead set
bfin_flag_schedule_insns2 for reorg to handle it.
(output_file_start): Likewise for var-tracking.
(bfin_optimize_loop): Take some care not to stumble over SEQUENCEs.
(gen_one_bundle, bfin_gen_bundles, type_for_anomaly, trapping_loads_p):
New functions.
(bfin_reorg): Do second scheduling pass here, and call
bfin_gen_bundles. Use type_for_anomaly and trapping_loads_p instead
of examining insns directly. If bfin_flag_var_tracking, call
var-tracking pass when done with everything else.
* config/bfin/bfin.h (PRINT_OPERAND_PUNCT_VALID_P): '!' is valid.
* config/bfin/bfin.md (UNSPEC_32BIT): New constant.
(movsi_insn32): New pattern, with two new splits to create it
before the final scheduling pass.
(neghi2): Not a dsp32 insn, rather alu0.
(movbi, pushsi_insn, popsi_insn, movsi_insn, movv2hi_insn, movhi_insn,
movqi_insn, movsf_insn, movsi_insv, extendhisi2, zero_extendhisi2,
extendqihi2, extendqisi2, zero_extendqihi2, zero_extendqisi2,
mulhisi3, umulhisi3, ssadsi3, sssubsi3, smaxsi3, sminsi3, abssi2,
ssnegsi2, signbitssi2, smaxhi3, sminhi3, abshi2, ssneghi2, signbitshi2,
movhi_low2high, movhi_high2high, movhi_low2low, movhi_high2low,
movhiv2hi_low, movhiv2hi_high, composev2hi, packv2hi, movv2hi_hi,
ssaddhi3, sssubhi3, addv2hi3, ssaddv2hi3, subv2hi3, sssubv2hi3,
addsubv2hi3, subaddv2hi3, ssaddsubv2hi3, sssubaddv2hi3, sublohiv2hi3,
subhilov2hi3, sssublohiv2hi3, sssubhilov2hi3, addlohiv2hi3,
addhilov2hi3, ssaddlohiv2hi3, ssaddhilov2hi3, sminv2hi3, smaxv2hi3,
flag_mulhi, flag_mulhisi, flag_mulhisi_parts, flag_machi,
flag_machi_acconly, flag_macinithi, flag_macinit1hi, mulv2hi3,
flag_mulv2hi, flag_mulv2hi_parts, flag_macv2hi_parts,
flag_macv2hi_parts_acconly, flag_macinitv2hi_parts,
flag_macinit1v2hi_parts, mulhisi_ll, mulhisi_lh, mulhisi_hl,
mulhisi_hh, ssnegv2hi2, absv2hi2, ssashiftv2hi3, ssashifthi3,
lshiftv2hi3, lshifthi3): Use '%!' to terminate all dsp32/load/store
variants instead of ';'.
(ror_one, rol_one): Likewise. Make them dsp32 insns.
(ashlsi3_insn, ashrsi3, lshrsi3): Add dsp32 variants.
(align8, align16, align24): Now named patterns; also using '%!'.
(mnop): New insn.
From-SVN: r119534
2006-12-05 09:49:56 +01:00
|
|
|
|
"%0 = %1 +|+ %2%!"
|
2005-04-05 13:26:48 +02:00
|
|
|
|
[(set_attr "type" "dsp32")])
|
|
|
|
|
|
genmodes.c (make_vector_mode): Allow making VECTOR_MODE_INT of a MODE_PARTIAL_INT mode.
* genmodes.c (make_vector_mode): Allow making VECTOR_MODE_INT of a
MODE_PARTIAL_INT mode.
* config/bfin/bfin-modes.def: Add V2PDI and V2SI.
* config/bfin/bfin.c (print_operand): Add macflag and mac/msu modifiers
for CONST_INTs.
(hard_regno_mode_ok): V2PDImode is ok for accumulators.
* config/bfin/bfin.h (CLASS_MAX_NREGS, HARD_REGNO_NREGS): Handle
V2PDImode.
* config/bfin/predicates.md (const01_operand, vec_shift_operand):
New predicates.
* config/bfin/bfin.md (UNSPEC_MUL_WITH_FLAG, UNSPEC_MAC_WITH_FLAG):
New constants.
(MACFLAG_NONE, MACFLAG_T, MACFLAG_FU, MACFLAG_TFU, MACFLAG_IS,
MACFLAG_IU, MACFLAG_W32, MACFLAG_M, MACFLAG_S2RND, MACFLAG_ISS2,
MACFLAG_IH): Likewise.
(movstricthi_1): Renamed from "*movstricthi".
(load_accumulator, load_accumulator_pair, movsi_insv, insv,
ssaddsi3, sssubsi3, ssnegsi2, signbitssi2, smaxhi3, sminhi3,
abshi2, neghi2, ssneghi2, signbitshi2, movhi_low2high,
movhi_high2high, movhi_low2low, movhi_high2low, movhiv2hi_low,
movhiv2hi_high, composev2hi, movv2hi_hi, movv2hi_hi_low,
movv2hi_hi_high, ssaddhi3, sssubhi3, ssaddv2hi3, sssubv2hi3,
addsubv2hi3, subaddv2hi3, ssaddsubv2hi3, sssubaddv2hi3,
sublohiv2hi3, subhilov2hi3, sssublohiv2hi3, sssubhilov2hi3,
addlohiv2hi3, addhilov2hi3, ssaddlohiv2hi3, ssaddhilov2hi3,
mulhisi_ll, mulhisi_lh, mulhisi_hl, mulhisi_hh, ssnegv2hi2,
ssashiftv2hi3, ssashifthi3, lshiftv2hi3, lshifthi3, packv2hi,
flag_mulhi, flag_mulhisi_parts, flag_machi, flag_machi_acconly,
flag_macinithi, flag_macinit1hi, flag_mulv2hi, flag_mulv2hi_parts,
flag_macv2hi_parts, flag_macv2hi_parts_acconly,
flag_macinitv2hi_parts, flag_macinit1v2hi_parts): New patterns.
From-SVN: r113245
2006-04-25 13:49:27 +02:00
|
|
|
|
(define_insn "ssaddv2hi3"
|
|
|
|
|
[(set (match_operand:V2HI 0 "register_operand" "=d")
|
|
|
|
|
(ss_plus:V2HI (match_operand:V2HI 1 "register_operand" "d")
|
|
|
|
|
(match_operand:V2HI 2 "register_operand" "d")))]
|
|
|
|
|
""
|
rtlanal.c (note_uses): Deal with SEQUENCEs.
* rtlanal.c (note_uses): Deal with SEQUENCEs.
* config/bfin/bfin.c: Include "timevar.h".
(bfin_flag_schedule_insns2, splitting_for_sched,
bfin_flag_var_tracking): New variables.
(print_operand): Handle '%!'.
(override_options): Disable normal sched2 pass, instead set
bfin_flag_schedule_insns2 for reorg to handle it.
(output_file_start): Likewise for var-tracking.
(bfin_optimize_loop): Take some care not to stumble over SEQUENCEs.
(gen_one_bundle, bfin_gen_bundles, type_for_anomaly, trapping_loads_p):
New functions.
(bfin_reorg): Do second scheduling pass here, and call
bfin_gen_bundles. Use type_for_anomaly and trapping_loads_p instead
of examining insns directly. If bfin_flag_var_tracking, call
var-tracking pass when done with everything else.
* config/bfin/bfin.h (PRINT_OPERAND_PUNCT_VALID_P): '!' is valid.
* config/bfin/bfin.md (UNSPEC_32BIT): New constant.
(movsi_insn32): New pattern, with two new splits to create it
before the final scheduling pass.
(neghi2): Not a dsp32 insn, rather alu0.
(movbi, pushsi_insn, popsi_insn, movsi_insn, movv2hi_insn, movhi_insn,
movqi_insn, movsf_insn, movsi_insv, extendhisi2, zero_extendhisi2,
extendqihi2, extendqisi2, zero_extendqihi2, zero_extendqisi2,
mulhisi3, umulhisi3, ssadsi3, sssubsi3, smaxsi3, sminsi3, abssi2,
ssnegsi2, signbitssi2, smaxhi3, sminhi3, abshi2, ssneghi2, signbitshi2,
movhi_low2high, movhi_high2high, movhi_low2low, movhi_high2low,
movhiv2hi_low, movhiv2hi_high, composev2hi, packv2hi, movv2hi_hi,
ssaddhi3, sssubhi3, addv2hi3, ssaddv2hi3, subv2hi3, sssubv2hi3,
addsubv2hi3, subaddv2hi3, ssaddsubv2hi3, sssubaddv2hi3, sublohiv2hi3,
subhilov2hi3, sssublohiv2hi3, sssubhilov2hi3, addlohiv2hi3,
addhilov2hi3, ssaddlohiv2hi3, ssaddhilov2hi3, sminv2hi3, smaxv2hi3,
flag_mulhi, flag_mulhisi, flag_mulhisi_parts, flag_machi,
flag_machi_acconly, flag_macinithi, flag_macinit1hi, mulv2hi3,
flag_mulv2hi, flag_mulv2hi_parts, flag_macv2hi_parts,
flag_macv2hi_parts_acconly, flag_macinitv2hi_parts,
flag_macinit1v2hi_parts, mulhisi_ll, mulhisi_lh, mulhisi_hl,
mulhisi_hh, ssnegv2hi2, absv2hi2, ssashiftv2hi3, ssashifthi3,
lshiftv2hi3, lshifthi3): Use '%!' to terminate all dsp32/load/store
variants instead of ';'.
(ror_one, rol_one): Likewise. Make them dsp32 insns.
(ashlsi3_insn, ashrsi3, lshrsi3): Add dsp32 variants.
(align8, align16, align24): Now named patterns; also using '%!'.
(mnop): New insn.
From-SVN: r119534
2006-12-05 09:49:56 +01:00
|
|
|
|
"%0 = %1 +|+ %2 (S)%!"
|
genmodes.c (make_vector_mode): Allow making VECTOR_MODE_INT of a MODE_PARTIAL_INT mode.
* genmodes.c (make_vector_mode): Allow making VECTOR_MODE_INT of a
MODE_PARTIAL_INT mode.
* config/bfin/bfin-modes.def: Add V2PDI and V2SI.
* config/bfin/bfin.c (print_operand): Add macflag and mac/msu modifiers
for CONST_INTs.
(hard_regno_mode_ok): V2PDImode is ok for accumulators.
* config/bfin/bfin.h (CLASS_MAX_NREGS, HARD_REGNO_NREGS): Handle
V2PDImode.
* config/bfin/predicates.md (const01_operand, vec_shift_operand):
New predicates.
* config/bfin/bfin.md (UNSPEC_MUL_WITH_FLAG, UNSPEC_MAC_WITH_FLAG):
New constants.
(MACFLAG_NONE, MACFLAG_T, MACFLAG_FU, MACFLAG_TFU, MACFLAG_IS,
MACFLAG_IU, MACFLAG_W32, MACFLAG_M, MACFLAG_S2RND, MACFLAG_ISS2,
MACFLAG_IH): Likewise.
(movstricthi_1): Renamed from "*movstricthi".
(load_accumulator, load_accumulator_pair, movsi_insv, insv,
ssaddsi3, sssubsi3, ssnegsi2, signbitssi2, smaxhi3, sminhi3,
abshi2, neghi2, ssneghi2, signbitshi2, movhi_low2high,
movhi_high2high, movhi_low2low, movhi_high2low, movhiv2hi_low,
movhiv2hi_high, composev2hi, movv2hi_hi, movv2hi_hi_low,
movv2hi_hi_high, ssaddhi3, sssubhi3, ssaddv2hi3, sssubv2hi3,
addsubv2hi3, subaddv2hi3, ssaddsubv2hi3, sssubaddv2hi3,
sublohiv2hi3, subhilov2hi3, sssublohiv2hi3, sssubhilov2hi3,
addlohiv2hi3, addhilov2hi3, ssaddlohiv2hi3, ssaddhilov2hi3,
mulhisi_ll, mulhisi_lh, mulhisi_hl, mulhisi_hh, ssnegv2hi2,
ssashiftv2hi3, ssashifthi3, lshiftv2hi3, lshifthi3, packv2hi,
flag_mulhi, flag_mulhisi_parts, flag_machi, flag_machi_acconly,
flag_macinithi, flag_macinit1hi, flag_mulv2hi, flag_mulv2hi_parts,
flag_macv2hi_parts, flag_macv2hi_parts_acconly,
flag_macinitv2hi_parts, flag_macinit1v2hi_parts): New patterns.
From-SVN: r113245
2006-04-25 13:49:27 +02:00
|
|
|
|
[(set_attr "type" "dsp32")])
|
|
|
|
|
|
2005-06-30 09:57:05 +02:00
|
|
|
|
(define_insn "subv2hi3"
|
2005-04-05 13:26:48 +02:00
|
|
|
|
[(set (match_operand:V2HI 0 "register_operand" "=d")
|
|
|
|
|
(minus:V2HI (match_operand:V2HI 1 "register_operand" "d")
|
|
|
|
|
(match_operand:V2HI 2 "register_operand" "d")))]
|
|
|
|
|
""
|
rtlanal.c (note_uses): Deal with SEQUENCEs.
* rtlanal.c (note_uses): Deal with SEQUENCEs.
* config/bfin/bfin.c: Include "timevar.h".
(bfin_flag_schedule_insns2, splitting_for_sched,
bfin_flag_var_tracking): New variables.
(print_operand): Handle '%!'.
(override_options): Disable normal sched2 pass, instead set
bfin_flag_schedule_insns2 for reorg to handle it.
(output_file_start): Likewise for var-tracking.
(bfin_optimize_loop): Take some care not to stumble over SEQUENCEs.
(gen_one_bundle, bfin_gen_bundles, type_for_anomaly, trapping_loads_p):
New functions.
(bfin_reorg): Do second scheduling pass here, and call
bfin_gen_bundles. Use type_for_anomaly and trapping_loads_p instead
of examining insns directly. If bfin_flag_var_tracking, call
var-tracking pass when done with everything else.
* config/bfin/bfin.h (PRINT_OPERAND_PUNCT_VALID_P): '!' is valid.
* config/bfin/bfin.md (UNSPEC_32BIT): New constant.
(movsi_insn32): New pattern, with two new splits to create it
before the final scheduling pass.
(neghi2): Not a dsp32 insn, rather alu0.
(movbi, pushsi_insn, popsi_insn, movsi_insn, movv2hi_insn, movhi_insn,
movqi_insn, movsf_insn, movsi_insv, extendhisi2, zero_extendhisi2,
extendqihi2, extendqisi2, zero_extendqihi2, zero_extendqisi2,
mulhisi3, umulhisi3, ssadsi3, sssubsi3, smaxsi3, sminsi3, abssi2,
ssnegsi2, signbitssi2, smaxhi3, sminhi3, abshi2, ssneghi2, signbitshi2,
movhi_low2high, movhi_high2high, movhi_low2low, movhi_high2low,
movhiv2hi_low, movhiv2hi_high, composev2hi, packv2hi, movv2hi_hi,
ssaddhi3, sssubhi3, addv2hi3, ssaddv2hi3, subv2hi3, sssubv2hi3,
addsubv2hi3, subaddv2hi3, ssaddsubv2hi3, sssubaddv2hi3, sublohiv2hi3,
subhilov2hi3, sssublohiv2hi3, sssubhilov2hi3, addlohiv2hi3,
addhilov2hi3, ssaddlohiv2hi3, ssaddhilov2hi3, sminv2hi3, smaxv2hi3,
flag_mulhi, flag_mulhisi, flag_mulhisi_parts, flag_machi,
flag_machi_acconly, flag_macinithi, flag_macinit1hi, mulv2hi3,
flag_mulv2hi, flag_mulv2hi_parts, flag_macv2hi_parts,
flag_macv2hi_parts_acconly, flag_macinitv2hi_parts,
flag_macinit1v2hi_parts, mulhisi_ll, mulhisi_lh, mulhisi_hl,
mulhisi_hh, ssnegv2hi2, absv2hi2, ssashiftv2hi3, ssashifthi3,
lshiftv2hi3, lshifthi3): Use '%!' to terminate all dsp32/load/store
variants instead of ';'.
(ror_one, rol_one): Likewise. Make them dsp32 insns.
(ashlsi3_insn, ashrsi3, lshrsi3): Add dsp32 variants.
(align8, align16, align24): Now named patterns; also using '%!'.
(mnop): New insn.
From-SVN: r119534
2006-12-05 09:49:56 +01:00
|
|
|
|
"%0 = %1 -|- %2%!"
|
2005-04-05 13:26:48 +02:00
|
|
|
|
[(set_attr "type" "dsp32")])
|
|
|
|
|
|
genmodes.c (make_vector_mode): Allow making VECTOR_MODE_INT of a MODE_PARTIAL_INT mode.
* genmodes.c (make_vector_mode): Allow making VECTOR_MODE_INT of a
MODE_PARTIAL_INT mode.
* config/bfin/bfin-modes.def: Add V2PDI and V2SI.
* config/bfin/bfin.c (print_operand): Add macflag and mac/msu modifiers
for CONST_INTs.
(hard_regno_mode_ok): V2PDImode is ok for accumulators.
* config/bfin/bfin.h (CLASS_MAX_NREGS, HARD_REGNO_NREGS): Handle
V2PDImode.
* config/bfin/predicates.md (const01_operand, vec_shift_operand):
New predicates.
* config/bfin/bfin.md (UNSPEC_MUL_WITH_FLAG, UNSPEC_MAC_WITH_FLAG):
New constants.
(MACFLAG_NONE, MACFLAG_T, MACFLAG_FU, MACFLAG_TFU, MACFLAG_IS,
MACFLAG_IU, MACFLAG_W32, MACFLAG_M, MACFLAG_S2RND, MACFLAG_ISS2,
MACFLAG_IH): Likewise.
(movstricthi_1): Renamed from "*movstricthi".
(load_accumulator, load_accumulator_pair, movsi_insv, insv,
ssaddsi3, sssubsi3, ssnegsi2, signbitssi2, smaxhi3, sminhi3,
abshi2, neghi2, ssneghi2, signbitshi2, movhi_low2high,
movhi_high2high, movhi_low2low, movhi_high2low, movhiv2hi_low,
movhiv2hi_high, composev2hi, movv2hi_hi, movv2hi_hi_low,
movv2hi_hi_high, ssaddhi3, sssubhi3, ssaddv2hi3, sssubv2hi3,
addsubv2hi3, subaddv2hi3, ssaddsubv2hi3, sssubaddv2hi3,
sublohiv2hi3, subhilov2hi3, sssublohiv2hi3, sssubhilov2hi3,
addlohiv2hi3, addhilov2hi3, ssaddlohiv2hi3, ssaddhilov2hi3,
mulhisi_ll, mulhisi_lh, mulhisi_hl, mulhisi_hh, ssnegv2hi2,
ssashiftv2hi3, ssashifthi3, lshiftv2hi3, lshifthi3, packv2hi,
flag_mulhi, flag_mulhisi_parts, flag_machi, flag_machi_acconly,
flag_macinithi, flag_macinit1hi, flag_mulv2hi, flag_mulv2hi_parts,
flag_macv2hi_parts, flag_macv2hi_parts_acconly,
flag_macinitv2hi_parts, flag_macinit1v2hi_parts): New patterns.
From-SVN: r113245
2006-04-25 13:49:27 +02:00
|
|
|
|
(define_insn "sssubv2hi3"
|
|
|
|
|
[(set (match_operand:V2HI 0 "register_operand" "=d")
|
|
|
|
|
(ss_minus:V2HI (match_operand:V2HI 1 "register_operand" "d")
|
|
|
|
|
(match_operand:V2HI 2 "register_operand" "d")))]
|
|
|
|
|
""
|
rtlanal.c (note_uses): Deal with SEQUENCEs.
* rtlanal.c (note_uses): Deal with SEQUENCEs.
* config/bfin/bfin.c: Include "timevar.h".
(bfin_flag_schedule_insns2, splitting_for_sched,
bfin_flag_var_tracking): New variables.
(print_operand): Handle '%!'.
(override_options): Disable normal sched2 pass, instead set
bfin_flag_schedule_insns2 for reorg to handle it.
(output_file_start): Likewise for var-tracking.
(bfin_optimize_loop): Take some care not to stumble over SEQUENCEs.
(gen_one_bundle, bfin_gen_bundles, type_for_anomaly, trapping_loads_p):
New functions.
(bfin_reorg): Do second scheduling pass here, and call
bfin_gen_bundles. Use type_for_anomaly and trapping_loads_p instead
of examining insns directly. If bfin_flag_var_tracking, call
var-tracking pass when done with everything else.
* config/bfin/bfin.h (PRINT_OPERAND_PUNCT_VALID_P): '!' is valid.
* config/bfin/bfin.md (UNSPEC_32BIT): New constant.
(movsi_insn32): New pattern, with two new splits to create it
before the final scheduling pass.
(neghi2): Not a dsp32 insn, rather alu0.
(movbi, pushsi_insn, popsi_insn, movsi_insn, movv2hi_insn, movhi_insn,
movqi_insn, movsf_insn, movsi_insv, extendhisi2, zero_extendhisi2,
extendqihi2, extendqisi2, zero_extendqihi2, zero_extendqisi2,
mulhisi3, umulhisi3, ssadsi3, sssubsi3, smaxsi3, sminsi3, abssi2,
ssnegsi2, signbitssi2, smaxhi3, sminhi3, abshi2, ssneghi2, signbitshi2,
movhi_low2high, movhi_high2high, movhi_low2low, movhi_high2low,
movhiv2hi_low, movhiv2hi_high, composev2hi, packv2hi, movv2hi_hi,
ssaddhi3, sssubhi3, addv2hi3, ssaddv2hi3, subv2hi3, sssubv2hi3,
addsubv2hi3, subaddv2hi3, ssaddsubv2hi3, sssubaddv2hi3, sublohiv2hi3,
subhilov2hi3, sssublohiv2hi3, sssubhilov2hi3, addlohiv2hi3,
addhilov2hi3, ssaddlohiv2hi3, ssaddhilov2hi3, sminv2hi3, smaxv2hi3,
flag_mulhi, flag_mulhisi, flag_mulhisi_parts, flag_machi,
flag_machi_acconly, flag_macinithi, flag_macinit1hi, mulv2hi3,
flag_mulv2hi, flag_mulv2hi_parts, flag_macv2hi_parts,
flag_macv2hi_parts_acconly, flag_macinitv2hi_parts,
flag_macinit1v2hi_parts, mulhisi_ll, mulhisi_lh, mulhisi_hl,
mulhisi_hh, ssnegv2hi2, absv2hi2, ssashiftv2hi3, ssashifthi3,
lshiftv2hi3, lshifthi3): Use '%!' to terminate all dsp32/load/store
variants instead of ';'.
(ror_one, rol_one): Likewise. Make them dsp32 insns.
(ashlsi3_insn, ashrsi3, lshrsi3): Add dsp32 variants.
(align8, align16, align24): Now named patterns; also using '%!'.
(mnop): New insn.
From-SVN: r119534
2006-12-05 09:49:56 +01:00
|
|
|
|
"%0 = %1 -|- %2 (S)%!"
|
genmodes.c (make_vector_mode): Allow making VECTOR_MODE_INT of a MODE_PARTIAL_INT mode.
* genmodes.c (make_vector_mode): Allow making VECTOR_MODE_INT of a
MODE_PARTIAL_INT mode.
* config/bfin/bfin-modes.def: Add V2PDI and V2SI.
* config/bfin/bfin.c (print_operand): Add macflag and mac/msu modifiers
for CONST_INTs.
(hard_regno_mode_ok): V2PDImode is ok for accumulators.
* config/bfin/bfin.h (CLASS_MAX_NREGS, HARD_REGNO_NREGS): Handle
V2PDImode.
* config/bfin/predicates.md (const01_operand, vec_shift_operand):
New predicates.
* config/bfin/bfin.md (UNSPEC_MUL_WITH_FLAG, UNSPEC_MAC_WITH_FLAG):
New constants.
(MACFLAG_NONE, MACFLAG_T, MACFLAG_FU, MACFLAG_TFU, MACFLAG_IS,
MACFLAG_IU, MACFLAG_W32, MACFLAG_M, MACFLAG_S2RND, MACFLAG_ISS2,
MACFLAG_IH): Likewise.
(movstricthi_1): Renamed from "*movstricthi".
(load_accumulator, load_accumulator_pair, movsi_insv, insv,
ssaddsi3, sssubsi3, ssnegsi2, signbitssi2, smaxhi3, sminhi3,
abshi2, neghi2, ssneghi2, signbitshi2, movhi_low2high,
movhi_high2high, movhi_low2low, movhi_high2low, movhiv2hi_low,
movhiv2hi_high, composev2hi, movv2hi_hi, movv2hi_hi_low,
movv2hi_hi_high, ssaddhi3, sssubhi3, ssaddv2hi3, sssubv2hi3,
addsubv2hi3, subaddv2hi3, ssaddsubv2hi3, sssubaddv2hi3,
sublohiv2hi3, subhilov2hi3, sssublohiv2hi3, sssubhilov2hi3,
addlohiv2hi3, addhilov2hi3, ssaddlohiv2hi3, ssaddhilov2hi3,
mulhisi_ll, mulhisi_lh, mulhisi_hl, mulhisi_hh, ssnegv2hi2,
ssashiftv2hi3, ssashifthi3, lshiftv2hi3, lshifthi3, packv2hi,
flag_mulhi, flag_mulhisi_parts, flag_machi, flag_machi_acconly,
flag_macinithi, flag_macinit1hi, flag_mulv2hi, flag_mulv2hi_parts,
flag_macv2hi_parts, flag_macv2hi_parts_acconly,
flag_macinitv2hi_parts, flag_macinit1v2hi_parts): New patterns.
From-SVN: r113245
2006-04-25 13:49:27 +02:00
|
|
|
|
[(set_attr "type" "dsp32")])
|
|
|
|
|
|
|
|
|
|
(define_insn "addsubv2hi3"
|
|
|
|
|
[(set (match_operand:V2HI 0 "register_operand" "=d")
|
|
|
|
|
(vec_concat:V2HI
|
|
|
|
|
(minus:HI (vec_select:HI (match_operand:V2HI 1 "register_operand" "d")
|
|
|
|
|
(parallel [(const_int 0)]))
|
|
|
|
|
(vec_select:HI (match_operand:V2HI 2 "register_operand" "d")
|
|
|
|
|
(parallel [(const_int 0)])))
|
|
|
|
|
(plus:HI (vec_select:HI (match_dup 1) (parallel [(const_int 1)]))
|
|
|
|
|
(vec_select:HI (match_dup 2) (parallel [(const_int 1)])))))]
|
|
|
|
|
""
|
2021-10-19 12:00:10 +02:00
|
|
|
|
"%0 = %1 +|- %2%!"
|
genmodes.c (make_vector_mode): Allow making VECTOR_MODE_INT of a MODE_PARTIAL_INT mode.
* genmodes.c (make_vector_mode): Allow making VECTOR_MODE_INT of a
MODE_PARTIAL_INT mode.
* config/bfin/bfin-modes.def: Add V2PDI and V2SI.
* config/bfin/bfin.c (print_operand): Add macflag and mac/msu modifiers
for CONST_INTs.
(hard_regno_mode_ok): V2PDImode is ok for accumulators.
* config/bfin/bfin.h (CLASS_MAX_NREGS, HARD_REGNO_NREGS): Handle
V2PDImode.
* config/bfin/predicates.md (const01_operand, vec_shift_operand):
New predicates.
* config/bfin/bfin.md (UNSPEC_MUL_WITH_FLAG, UNSPEC_MAC_WITH_FLAG):
New constants.
(MACFLAG_NONE, MACFLAG_T, MACFLAG_FU, MACFLAG_TFU, MACFLAG_IS,
MACFLAG_IU, MACFLAG_W32, MACFLAG_M, MACFLAG_S2RND, MACFLAG_ISS2,
MACFLAG_IH): Likewise.
(movstricthi_1): Renamed from "*movstricthi".
(load_accumulator, load_accumulator_pair, movsi_insv, insv,
ssaddsi3, sssubsi3, ssnegsi2, signbitssi2, smaxhi3, sminhi3,
abshi2, neghi2, ssneghi2, signbitshi2, movhi_low2high,
movhi_high2high, movhi_low2low, movhi_high2low, movhiv2hi_low,
movhiv2hi_high, composev2hi, movv2hi_hi, movv2hi_hi_low,
movv2hi_hi_high, ssaddhi3, sssubhi3, ssaddv2hi3, sssubv2hi3,
addsubv2hi3, subaddv2hi3, ssaddsubv2hi3, sssubaddv2hi3,
sublohiv2hi3, subhilov2hi3, sssublohiv2hi3, sssubhilov2hi3,
addlohiv2hi3, addhilov2hi3, ssaddlohiv2hi3, ssaddhilov2hi3,
mulhisi_ll, mulhisi_lh, mulhisi_hl, mulhisi_hh, ssnegv2hi2,
ssashiftv2hi3, ssashifthi3, lshiftv2hi3, lshifthi3, packv2hi,
flag_mulhi, flag_mulhisi_parts, flag_machi, flag_machi_acconly,
flag_macinithi, flag_macinit1hi, flag_mulv2hi, flag_mulv2hi_parts,
flag_macv2hi_parts, flag_macv2hi_parts_acconly,
flag_macinitv2hi_parts, flag_macinit1v2hi_parts): New patterns.
From-SVN: r113245
2006-04-25 13:49:27 +02:00
|
|
|
|
[(set_attr "type" "dsp32")])
|
|
|
|
|
|
2021-10-19 12:00:10 +02:00
|
|
|
|
(define_insn "subaddv2hi3"
|
genmodes.c (make_vector_mode): Allow making VECTOR_MODE_INT of a MODE_PARTIAL_INT mode.
* genmodes.c (make_vector_mode): Allow making VECTOR_MODE_INT of a
MODE_PARTIAL_INT mode.
* config/bfin/bfin-modes.def: Add V2PDI and V2SI.
* config/bfin/bfin.c (print_operand): Add macflag and mac/msu modifiers
for CONST_INTs.
(hard_regno_mode_ok): V2PDImode is ok for accumulators.
* config/bfin/bfin.h (CLASS_MAX_NREGS, HARD_REGNO_NREGS): Handle
V2PDImode.
* config/bfin/predicates.md (const01_operand, vec_shift_operand):
New predicates.
* config/bfin/bfin.md (UNSPEC_MUL_WITH_FLAG, UNSPEC_MAC_WITH_FLAG):
New constants.
(MACFLAG_NONE, MACFLAG_T, MACFLAG_FU, MACFLAG_TFU, MACFLAG_IS,
MACFLAG_IU, MACFLAG_W32, MACFLAG_M, MACFLAG_S2RND, MACFLAG_ISS2,
MACFLAG_IH): Likewise.
(movstricthi_1): Renamed from "*movstricthi".
(load_accumulator, load_accumulator_pair, movsi_insv, insv,
ssaddsi3, sssubsi3, ssnegsi2, signbitssi2, smaxhi3, sminhi3,
abshi2, neghi2, ssneghi2, signbitshi2, movhi_low2high,
movhi_high2high, movhi_low2low, movhi_high2low, movhiv2hi_low,
movhiv2hi_high, composev2hi, movv2hi_hi, movv2hi_hi_low,
movv2hi_hi_high, ssaddhi3, sssubhi3, ssaddv2hi3, sssubv2hi3,
addsubv2hi3, subaddv2hi3, ssaddsubv2hi3, sssubaddv2hi3,
sublohiv2hi3, subhilov2hi3, sssublohiv2hi3, sssubhilov2hi3,
addlohiv2hi3, addhilov2hi3, ssaddlohiv2hi3, ssaddhilov2hi3,
mulhisi_ll, mulhisi_lh, mulhisi_hl, mulhisi_hh, ssnegv2hi2,
ssashiftv2hi3, ssashifthi3, lshiftv2hi3, lshifthi3, packv2hi,
flag_mulhi, flag_mulhisi_parts, flag_machi, flag_machi_acconly,
flag_macinithi, flag_macinit1hi, flag_mulv2hi, flag_mulv2hi_parts,
flag_macv2hi_parts, flag_macv2hi_parts_acconly,
flag_macinitv2hi_parts, flag_macinit1v2hi_parts): New patterns.
From-SVN: r113245
2006-04-25 13:49:27 +02:00
|
|
|
|
[(set (match_operand:V2HI 0 "register_operand" "=d")
|
|
|
|
|
(vec_concat:V2HI
|
2021-10-19 12:00:10 +02:00
|
|
|
|
(plus:HI (vec_select:HI (match_operand:V2HI 1 "register_operand" "d")
|
|
|
|
|
(parallel [(const_int 0)]))
|
|
|
|
|
(vec_select:HI (match_operand:V2HI 2 "register_operand" "d")
|
|
|
|
|
(parallel [(const_int 0)])))
|
|
|
|
|
(minus:HI (vec_select:HI (match_dup 1) (parallel [(const_int 1)]))
|
|
|
|
|
(vec_select:HI (match_dup 2) (parallel [(const_int 1)])))))]
|
genmodes.c (make_vector_mode): Allow making VECTOR_MODE_INT of a MODE_PARTIAL_INT mode.
* genmodes.c (make_vector_mode): Allow making VECTOR_MODE_INT of a
MODE_PARTIAL_INT mode.
* config/bfin/bfin-modes.def: Add V2PDI and V2SI.
* config/bfin/bfin.c (print_operand): Add macflag and mac/msu modifiers
for CONST_INTs.
(hard_regno_mode_ok): V2PDImode is ok for accumulators.
* config/bfin/bfin.h (CLASS_MAX_NREGS, HARD_REGNO_NREGS): Handle
V2PDImode.
* config/bfin/predicates.md (const01_operand, vec_shift_operand):
New predicates.
* config/bfin/bfin.md (UNSPEC_MUL_WITH_FLAG, UNSPEC_MAC_WITH_FLAG):
New constants.
(MACFLAG_NONE, MACFLAG_T, MACFLAG_FU, MACFLAG_TFU, MACFLAG_IS,
MACFLAG_IU, MACFLAG_W32, MACFLAG_M, MACFLAG_S2RND, MACFLAG_ISS2,
MACFLAG_IH): Likewise.
(movstricthi_1): Renamed from "*movstricthi".
(load_accumulator, load_accumulator_pair, movsi_insv, insv,
ssaddsi3, sssubsi3, ssnegsi2, signbitssi2, smaxhi3, sminhi3,
abshi2, neghi2, ssneghi2, signbitshi2, movhi_low2high,
movhi_high2high, movhi_low2low, movhi_high2low, movhiv2hi_low,
movhiv2hi_high, composev2hi, movv2hi_hi, movv2hi_hi_low,
movv2hi_hi_high, ssaddhi3, sssubhi3, ssaddv2hi3, sssubv2hi3,
addsubv2hi3, subaddv2hi3, ssaddsubv2hi3, sssubaddv2hi3,
sublohiv2hi3, subhilov2hi3, sssublohiv2hi3, sssubhilov2hi3,
addlohiv2hi3, addhilov2hi3, ssaddlohiv2hi3, ssaddhilov2hi3,
mulhisi_ll, mulhisi_lh, mulhisi_hl, mulhisi_hh, ssnegv2hi2,
ssashiftv2hi3, ssashifthi3, lshiftv2hi3, lshifthi3, packv2hi,
flag_mulhi, flag_mulhisi_parts, flag_machi, flag_machi_acconly,
flag_macinithi, flag_macinit1hi, flag_mulv2hi, flag_mulv2hi_parts,
flag_macv2hi_parts, flag_macv2hi_parts_acconly,
flag_macinitv2hi_parts, flag_macinit1v2hi_parts): New patterns.
From-SVN: r113245
2006-04-25 13:49:27 +02:00
|
|
|
|
""
|
2021-10-19 12:00:10 +02:00
|
|
|
|
"%0 = %1 -|+ %2%!"
|
genmodes.c (make_vector_mode): Allow making VECTOR_MODE_INT of a MODE_PARTIAL_INT mode.
* genmodes.c (make_vector_mode): Allow making VECTOR_MODE_INT of a
MODE_PARTIAL_INT mode.
* config/bfin/bfin-modes.def: Add V2PDI and V2SI.
* config/bfin/bfin.c (print_operand): Add macflag and mac/msu modifiers
for CONST_INTs.
(hard_regno_mode_ok): V2PDImode is ok for accumulators.
* config/bfin/bfin.h (CLASS_MAX_NREGS, HARD_REGNO_NREGS): Handle
V2PDImode.
* config/bfin/predicates.md (const01_operand, vec_shift_operand):
New predicates.
* config/bfin/bfin.md (UNSPEC_MUL_WITH_FLAG, UNSPEC_MAC_WITH_FLAG):
New constants.
(MACFLAG_NONE, MACFLAG_T, MACFLAG_FU, MACFLAG_TFU, MACFLAG_IS,
MACFLAG_IU, MACFLAG_W32, MACFLAG_M, MACFLAG_S2RND, MACFLAG_ISS2,
MACFLAG_IH): Likewise.
(movstricthi_1): Renamed from "*movstricthi".
(load_accumulator, load_accumulator_pair, movsi_insv, insv,
ssaddsi3, sssubsi3, ssnegsi2, signbitssi2, smaxhi3, sminhi3,
abshi2, neghi2, ssneghi2, signbitshi2, movhi_low2high,
movhi_high2high, movhi_low2low, movhi_high2low, movhiv2hi_low,
movhiv2hi_high, composev2hi, movv2hi_hi, movv2hi_hi_low,
movv2hi_hi_high, ssaddhi3, sssubhi3, ssaddv2hi3, sssubv2hi3,
addsubv2hi3, subaddv2hi3, ssaddsubv2hi3, sssubaddv2hi3,
sublohiv2hi3, subhilov2hi3, sssublohiv2hi3, sssubhilov2hi3,
addlohiv2hi3, addhilov2hi3, ssaddlohiv2hi3, ssaddhilov2hi3,
mulhisi_ll, mulhisi_lh, mulhisi_hl, mulhisi_hh, ssnegv2hi2,
ssashiftv2hi3, ssashifthi3, lshiftv2hi3, lshifthi3, packv2hi,
flag_mulhi, flag_mulhisi_parts, flag_machi, flag_machi_acconly,
flag_macinithi, flag_macinit1hi, flag_mulv2hi, flag_mulv2hi_parts,
flag_macv2hi_parts, flag_macv2hi_parts_acconly,
flag_macinitv2hi_parts, flag_macinit1v2hi_parts): New patterns.
From-SVN: r113245
2006-04-25 13:49:27 +02:00
|
|
|
|
[(set_attr "type" "dsp32")])
|
|
|
|
|
|
2021-10-19 12:00:10 +02:00
|
|
|
|
(define_insn "ssaddsubv2hi3"
|
genmodes.c (make_vector_mode): Allow making VECTOR_MODE_INT of a MODE_PARTIAL_INT mode.
* genmodes.c (make_vector_mode): Allow making VECTOR_MODE_INT of a
MODE_PARTIAL_INT mode.
* config/bfin/bfin-modes.def: Add V2PDI and V2SI.
* config/bfin/bfin.c (print_operand): Add macflag and mac/msu modifiers
for CONST_INTs.
(hard_regno_mode_ok): V2PDImode is ok for accumulators.
* config/bfin/bfin.h (CLASS_MAX_NREGS, HARD_REGNO_NREGS): Handle
V2PDImode.
* config/bfin/predicates.md (const01_operand, vec_shift_operand):
New predicates.
* config/bfin/bfin.md (UNSPEC_MUL_WITH_FLAG, UNSPEC_MAC_WITH_FLAG):
New constants.
(MACFLAG_NONE, MACFLAG_T, MACFLAG_FU, MACFLAG_TFU, MACFLAG_IS,
MACFLAG_IU, MACFLAG_W32, MACFLAG_M, MACFLAG_S2RND, MACFLAG_ISS2,
MACFLAG_IH): Likewise.
(movstricthi_1): Renamed from "*movstricthi".
(load_accumulator, load_accumulator_pair, movsi_insv, insv,
ssaddsi3, sssubsi3, ssnegsi2, signbitssi2, smaxhi3, sminhi3,
abshi2, neghi2, ssneghi2, signbitshi2, movhi_low2high,
movhi_high2high, movhi_low2low, movhi_high2low, movhiv2hi_low,
movhiv2hi_high, composev2hi, movv2hi_hi, movv2hi_hi_low,
movv2hi_hi_high, ssaddhi3, sssubhi3, ssaddv2hi3, sssubv2hi3,
addsubv2hi3, subaddv2hi3, ssaddsubv2hi3, sssubaddv2hi3,
sublohiv2hi3, subhilov2hi3, sssublohiv2hi3, sssubhilov2hi3,
addlohiv2hi3, addhilov2hi3, ssaddlohiv2hi3, ssaddhilov2hi3,
mulhisi_ll, mulhisi_lh, mulhisi_hl, mulhisi_hh, ssnegv2hi2,
ssashiftv2hi3, ssashifthi3, lshiftv2hi3, lshifthi3, packv2hi,
flag_mulhi, flag_mulhisi_parts, flag_machi, flag_machi_acconly,
flag_macinithi, flag_macinit1hi, flag_mulv2hi, flag_mulv2hi_parts,
flag_macv2hi_parts, flag_macv2hi_parts_acconly,
flag_macinitv2hi_parts, flag_macinit1v2hi_parts): New patterns.
From-SVN: r113245
2006-04-25 13:49:27 +02:00
|
|
|
|
[(set (match_operand:V2HI 0 "register_operand" "=d")
|
|
|
|
|
(vec_concat:V2HI
|
|
|
|
|
(ss_minus:HI (vec_select:HI (match_operand:V2HI 1 "register_operand" "d")
|
|
|
|
|
(parallel [(const_int 0)]))
|
|
|
|
|
(vec_select:HI (match_operand:V2HI 2 "register_operand" "d")
|
|
|
|
|
(parallel [(const_int 0)])))
|
|
|
|
|
(ss_plus:HI (vec_select:HI (match_dup 1) (parallel [(const_int 1)]))
|
|
|
|
|
(vec_select:HI (match_dup 2) (parallel [(const_int 1)])))))]
|
|
|
|
|
""
|
2021-10-19 12:00:10 +02:00
|
|
|
|
"%0 = %1 +|- %2 (S)%!"
|
|
|
|
|
[(set_attr "type" "dsp32")])
|
|
|
|
|
|
|
|
|
|
(define_insn "sssubaddv2hi3"
|
|
|
|
|
[(set (match_operand:V2HI 0 "register_operand" "=d")
|
|
|
|
|
(vec_concat:V2HI
|
|
|
|
|
(ss_plus:HI (vec_select:HI (match_operand:V2HI 1 "register_operand" "d")
|
|
|
|
|
(parallel [(const_int 0)]))
|
|
|
|
|
(vec_select:HI (match_operand:V2HI 2 "register_operand" "d")
|
|
|
|
|
(parallel [(const_int 0)])))
|
|
|
|
|
(ss_minus:HI (vec_select:HI (match_dup 1) (parallel [(const_int 1)]))
|
|
|
|
|
(vec_select:HI (match_dup 2) (parallel [(const_int 1)])))))]
|
|
|
|
|
""
|
rtlanal.c (note_uses): Deal with SEQUENCEs.
* rtlanal.c (note_uses): Deal with SEQUENCEs.
* config/bfin/bfin.c: Include "timevar.h".
(bfin_flag_schedule_insns2, splitting_for_sched,
bfin_flag_var_tracking): New variables.
(print_operand): Handle '%!'.
(override_options): Disable normal sched2 pass, instead set
bfin_flag_schedule_insns2 for reorg to handle it.
(output_file_start): Likewise for var-tracking.
(bfin_optimize_loop): Take some care not to stumble over SEQUENCEs.
(gen_one_bundle, bfin_gen_bundles, type_for_anomaly, trapping_loads_p):
New functions.
(bfin_reorg): Do second scheduling pass here, and call
bfin_gen_bundles. Use type_for_anomaly and trapping_loads_p instead
of examining insns directly. If bfin_flag_var_tracking, call
var-tracking pass when done with everything else.
* config/bfin/bfin.h (PRINT_OPERAND_PUNCT_VALID_P): '!' is valid.
* config/bfin/bfin.md (UNSPEC_32BIT): New constant.
(movsi_insn32): New pattern, with two new splits to create it
before the final scheduling pass.
(neghi2): Not a dsp32 insn, rather alu0.
(movbi, pushsi_insn, popsi_insn, movsi_insn, movv2hi_insn, movhi_insn,
movqi_insn, movsf_insn, movsi_insv, extendhisi2, zero_extendhisi2,
extendqihi2, extendqisi2, zero_extendqihi2, zero_extendqisi2,
mulhisi3, umulhisi3, ssadsi3, sssubsi3, smaxsi3, sminsi3, abssi2,
ssnegsi2, signbitssi2, smaxhi3, sminhi3, abshi2, ssneghi2, signbitshi2,
movhi_low2high, movhi_high2high, movhi_low2low, movhi_high2low,
movhiv2hi_low, movhiv2hi_high, composev2hi, packv2hi, movv2hi_hi,
ssaddhi3, sssubhi3, addv2hi3, ssaddv2hi3, subv2hi3, sssubv2hi3,
addsubv2hi3, subaddv2hi3, ssaddsubv2hi3, sssubaddv2hi3, sublohiv2hi3,
subhilov2hi3, sssublohiv2hi3, sssubhilov2hi3, addlohiv2hi3,
addhilov2hi3, ssaddlohiv2hi3, ssaddhilov2hi3, sminv2hi3, smaxv2hi3,
flag_mulhi, flag_mulhisi, flag_mulhisi_parts, flag_machi,
flag_machi_acconly, flag_macinithi, flag_macinit1hi, mulv2hi3,
flag_mulv2hi, flag_mulv2hi_parts, flag_macv2hi_parts,
flag_macv2hi_parts_acconly, flag_macinitv2hi_parts,
flag_macinit1v2hi_parts, mulhisi_ll, mulhisi_lh, mulhisi_hl,
mulhisi_hh, ssnegv2hi2, absv2hi2, ssashiftv2hi3, ssashifthi3,
lshiftv2hi3, lshifthi3): Use '%!' to terminate all dsp32/load/store
variants instead of ';'.
(ror_one, rol_one): Likewise. Make them dsp32 insns.
(ashlsi3_insn, ashrsi3, lshrsi3): Add dsp32 variants.
(align8, align16, align24): Now named patterns; also using '%!'.
(mnop): New insn.
From-SVN: r119534
2006-12-05 09:49:56 +01:00
|
|
|
|
"%0 = %1 -|+ %2 (S)%!"
|
genmodes.c (make_vector_mode): Allow making VECTOR_MODE_INT of a MODE_PARTIAL_INT mode.
* genmodes.c (make_vector_mode): Allow making VECTOR_MODE_INT of a
MODE_PARTIAL_INT mode.
* config/bfin/bfin-modes.def: Add V2PDI and V2SI.
* config/bfin/bfin.c (print_operand): Add macflag and mac/msu modifiers
for CONST_INTs.
(hard_regno_mode_ok): V2PDImode is ok for accumulators.
* config/bfin/bfin.h (CLASS_MAX_NREGS, HARD_REGNO_NREGS): Handle
V2PDImode.
* config/bfin/predicates.md (const01_operand, vec_shift_operand):
New predicates.
* config/bfin/bfin.md (UNSPEC_MUL_WITH_FLAG, UNSPEC_MAC_WITH_FLAG):
New constants.
(MACFLAG_NONE, MACFLAG_T, MACFLAG_FU, MACFLAG_TFU, MACFLAG_IS,
MACFLAG_IU, MACFLAG_W32, MACFLAG_M, MACFLAG_S2RND, MACFLAG_ISS2,
MACFLAG_IH): Likewise.
(movstricthi_1): Renamed from "*movstricthi".
(load_accumulator, load_accumulator_pair, movsi_insv, insv,
ssaddsi3, sssubsi3, ssnegsi2, signbitssi2, smaxhi3, sminhi3,
abshi2, neghi2, ssneghi2, signbitshi2, movhi_low2high,
movhi_high2high, movhi_low2low, movhi_high2low, movhiv2hi_low,
movhiv2hi_high, composev2hi, movv2hi_hi, movv2hi_hi_low,
movv2hi_hi_high, ssaddhi3, sssubhi3, ssaddv2hi3, sssubv2hi3,
addsubv2hi3, subaddv2hi3, ssaddsubv2hi3, sssubaddv2hi3,
sublohiv2hi3, subhilov2hi3, sssublohiv2hi3, sssubhilov2hi3,
addlohiv2hi3, addhilov2hi3, ssaddlohiv2hi3, ssaddhilov2hi3,
mulhisi_ll, mulhisi_lh, mulhisi_hl, mulhisi_hh, ssnegv2hi2,
ssashiftv2hi3, ssashifthi3, lshiftv2hi3, lshifthi3, packv2hi,
flag_mulhi, flag_mulhisi_parts, flag_machi, flag_machi_acconly,
flag_macinithi, flag_macinit1hi, flag_mulv2hi, flag_mulv2hi_parts,
flag_macv2hi_parts, flag_macv2hi_parts_acconly,
flag_macinitv2hi_parts, flag_macinit1v2hi_parts): New patterns.
From-SVN: r113245
2006-04-25 13:49:27 +02:00
|
|
|
|
[(set_attr "type" "dsp32")])
|
|
|
|
|
|
|
|
|
|
(define_insn "sublohiv2hi3"
|
|
|
|
|
[(set (match_operand:HI 0 "register_operand" "=d")
|
|
|
|
|
(minus:HI (vec_select:HI (match_operand:V2HI 1 "register_operand" "d")
|
|
|
|
|
(parallel [(const_int 1)]))
|
|
|
|
|
(vec_select:HI (match_operand:V2HI 2 "register_operand" "d")
|
|
|
|
|
(parallel [(const_int 0)]))))]
|
|
|
|
|
""
|
rtlanal.c (note_uses): Deal with SEQUENCEs.
* rtlanal.c (note_uses): Deal with SEQUENCEs.
* config/bfin/bfin.c: Include "timevar.h".
(bfin_flag_schedule_insns2, splitting_for_sched,
bfin_flag_var_tracking): New variables.
(print_operand): Handle '%!'.
(override_options): Disable normal sched2 pass, instead set
bfin_flag_schedule_insns2 for reorg to handle it.
(output_file_start): Likewise for var-tracking.
(bfin_optimize_loop): Take some care not to stumble over SEQUENCEs.
(gen_one_bundle, bfin_gen_bundles, type_for_anomaly, trapping_loads_p):
New functions.
(bfin_reorg): Do second scheduling pass here, and call
bfin_gen_bundles. Use type_for_anomaly and trapping_loads_p instead
of examining insns directly. If bfin_flag_var_tracking, call
var-tracking pass when done with everything else.
* config/bfin/bfin.h (PRINT_OPERAND_PUNCT_VALID_P): '!' is valid.
* config/bfin/bfin.md (UNSPEC_32BIT): New constant.
(movsi_insn32): New pattern, with two new splits to create it
before the final scheduling pass.
(neghi2): Not a dsp32 insn, rather alu0.
(movbi, pushsi_insn, popsi_insn, movsi_insn, movv2hi_insn, movhi_insn,
movqi_insn, movsf_insn, movsi_insv, extendhisi2, zero_extendhisi2,
extendqihi2, extendqisi2, zero_extendqihi2, zero_extendqisi2,
mulhisi3, umulhisi3, ssadsi3, sssubsi3, smaxsi3, sminsi3, abssi2,
ssnegsi2, signbitssi2, smaxhi3, sminhi3, abshi2, ssneghi2, signbitshi2,
movhi_low2high, movhi_high2high, movhi_low2low, movhi_high2low,
movhiv2hi_low, movhiv2hi_high, composev2hi, packv2hi, movv2hi_hi,
ssaddhi3, sssubhi3, addv2hi3, ssaddv2hi3, subv2hi3, sssubv2hi3,
addsubv2hi3, subaddv2hi3, ssaddsubv2hi3, sssubaddv2hi3, sublohiv2hi3,
subhilov2hi3, sssublohiv2hi3, sssubhilov2hi3, addlohiv2hi3,
addhilov2hi3, ssaddlohiv2hi3, ssaddhilov2hi3, sminv2hi3, smaxv2hi3,
flag_mulhi, flag_mulhisi, flag_mulhisi_parts, flag_machi,
flag_machi_acconly, flag_macinithi, flag_macinit1hi, mulv2hi3,
flag_mulv2hi, flag_mulv2hi_parts, flag_macv2hi_parts,
flag_macv2hi_parts_acconly, flag_macinitv2hi_parts,
flag_macinit1v2hi_parts, mulhisi_ll, mulhisi_lh, mulhisi_hl,
mulhisi_hh, ssnegv2hi2, absv2hi2, ssashiftv2hi3, ssashifthi3,
lshiftv2hi3, lshifthi3): Use '%!' to terminate all dsp32/load/store
variants instead of ';'.
(ror_one, rol_one): Likewise. Make them dsp32 insns.
(ashlsi3_insn, ashrsi3, lshrsi3): Add dsp32 variants.
(align8, align16, align24): Now named patterns; also using '%!'.
(mnop): New insn.
From-SVN: r119534
2006-12-05 09:49:56 +01:00
|
|
|
|
"%h0 = %d1 - %h2%!"
|
genmodes.c (make_vector_mode): Allow making VECTOR_MODE_INT of a MODE_PARTIAL_INT mode.
* genmodes.c (make_vector_mode): Allow making VECTOR_MODE_INT of a
MODE_PARTIAL_INT mode.
* config/bfin/bfin-modes.def: Add V2PDI and V2SI.
* config/bfin/bfin.c (print_operand): Add macflag and mac/msu modifiers
for CONST_INTs.
(hard_regno_mode_ok): V2PDImode is ok for accumulators.
* config/bfin/bfin.h (CLASS_MAX_NREGS, HARD_REGNO_NREGS): Handle
V2PDImode.
* config/bfin/predicates.md (const01_operand, vec_shift_operand):
New predicates.
* config/bfin/bfin.md (UNSPEC_MUL_WITH_FLAG, UNSPEC_MAC_WITH_FLAG):
New constants.
(MACFLAG_NONE, MACFLAG_T, MACFLAG_FU, MACFLAG_TFU, MACFLAG_IS,
MACFLAG_IU, MACFLAG_W32, MACFLAG_M, MACFLAG_S2RND, MACFLAG_ISS2,
MACFLAG_IH): Likewise.
(movstricthi_1): Renamed from "*movstricthi".
(load_accumulator, load_accumulator_pair, movsi_insv, insv,
ssaddsi3, sssubsi3, ssnegsi2, signbitssi2, smaxhi3, sminhi3,
abshi2, neghi2, ssneghi2, signbitshi2, movhi_low2high,
movhi_high2high, movhi_low2low, movhi_high2low, movhiv2hi_low,
movhiv2hi_high, composev2hi, movv2hi_hi, movv2hi_hi_low,
movv2hi_hi_high, ssaddhi3, sssubhi3, ssaddv2hi3, sssubv2hi3,
addsubv2hi3, subaddv2hi3, ssaddsubv2hi3, sssubaddv2hi3,
sublohiv2hi3, subhilov2hi3, sssublohiv2hi3, sssubhilov2hi3,
addlohiv2hi3, addhilov2hi3, ssaddlohiv2hi3, ssaddhilov2hi3,
mulhisi_ll, mulhisi_lh, mulhisi_hl, mulhisi_hh, ssnegv2hi2,
ssashiftv2hi3, ssashifthi3, lshiftv2hi3, lshifthi3, packv2hi,
flag_mulhi, flag_mulhisi_parts, flag_machi, flag_machi_acconly,
flag_macinithi, flag_macinit1hi, flag_mulv2hi, flag_mulv2hi_parts,
flag_macv2hi_parts, flag_macv2hi_parts_acconly,
flag_macinitv2hi_parts, flag_macinit1v2hi_parts): New patterns.
From-SVN: r113245
2006-04-25 13:49:27 +02:00
|
|
|
|
[(set_attr "type" "dsp32")])
|
|
|
|
|
|
|
|
|
|
(define_insn "subhilov2hi3"
|
|
|
|
|
[(set (match_operand:HI 0 "register_operand" "=d")
|
|
|
|
|
(minus:HI (vec_select:HI (match_operand:V2HI 1 "register_operand" "d")
|
|
|
|
|
(parallel [(const_int 0)]))
|
|
|
|
|
(vec_select:HI (match_operand:V2HI 2 "register_operand" "d")
|
|
|
|
|
(parallel [(const_int 1)]))))]
|
|
|
|
|
""
|
rtlanal.c (note_uses): Deal with SEQUENCEs.
* rtlanal.c (note_uses): Deal with SEQUENCEs.
* config/bfin/bfin.c: Include "timevar.h".
(bfin_flag_schedule_insns2, splitting_for_sched,
bfin_flag_var_tracking): New variables.
(print_operand): Handle '%!'.
(override_options): Disable normal sched2 pass, instead set
bfin_flag_schedule_insns2 for reorg to handle it.
(output_file_start): Likewise for var-tracking.
(bfin_optimize_loop): Take some care not to stumble over SEQUENCEs.
(gen_one_bundle, bfin_gen_bundles, type_for_anomaly, trapping_loads_p):
New functions.
(bfin_reorg): Do second scheduling pass here, and call
bfin_gen_bundles. Use type_for_anomaly and trapping_loads_p instead
of examining insns directly. If bfin_flag_var_tracking, call
var-tracking pass when done with everything else.
* config/bfin/bfin.h (PRINT_OPERAND_PUNCT_VALID_P): '!' is valid.
* config/bfin/bfin.md (UNSPEC_32BIT): New constant.
(movsi_insn32): New pattern, with two new splits to create it
before the final scheduling pass.
(neghi2): Not a dsp32 insn, rather alu0.
(movbi, pushsi_insn, popsi_insn, movsi_insn, movv2hi_insn, movhi_insn,
movqi_insn, movsf_insn, movsi_insv, extendhisi2, zero_extendhisi2,
extendqihi2, extendqisi2, zero_extendqihi2, zero_extendqisi2,
mulhisi3, umulhisi3, ssadsi3, sssubsi3, smaxsi3, sminsi3, abssi2,
ssnegsi2, signbitssi2, smaxhi3, sminhi3, abshi2, ssneghi2, signbitshi2,
movhi_low2high, movhi_high2high, movhi_low2low, movhi_high2low,
movhiv2hi_low, movhiv2hi_high, composev2hi, packv2hi, movv2hi_hi,
ssaddhi3, sssubhi3, addv2hi3, ssaddv2hi3, subv2hi3, sssubv2hi3,
addsubv2hi3, subaddv2hi3, ssaddsubv2hi3, sssubaddv2hi3, sublohiv2hi3,
subhilov2hi3, sssublohiv2hi3, sssubhilov2hi3, addlohiv2hi3,
addhilov2hi3, ssaddlohiv2hi3, ssaddhilov2hi3, sminv2hi3, smaxv2hi3,
flag_mulhi, flag_mulhisi, flag_mulhisi_parts, flag_machi,
flag_machi_acconly, flag_macinithi, flag_macinit1hi, mulv2hi3,
flag_mulv2hi, flag_mulv2hi_parts, flag_macv2hi_parts,
flag_macv2hi_parts_acconly, flag_macinitv2hi_parts,
flag_macinit1v2hi_parts, mulhisi_ll, mulhisi_lh, mulhisi_hl,
mulhisi_hh, ssnegv2hi2, absv2hi2, ssashiftv2hi3, ssashifthi3,
lshiftv2hi3, lshifthi3): Use '%!' to terminate all dsp32/load/store
variants instead of ';'.
(ror_one, rol_one): Likewise. Make them dsp32 insns.
(ashlsi3_insn, ashrsi3, lshrsi3): Add dsp32 variants.
(align8, align16, align24): Now named patterns; also using '%!'.
(mnop): New insn.
From-SVN: r119534
2006-12-05 09:49:56 +01:00
|
|
|
|
"%h0 = %h1 - %d2%!"
|
genmodes.c (make_vector_mode): Allow making VECTOR_MODE_INT of a MODE_PARTIAL_INT mode.
* genmodes.c (make_vector_mode): Allow making VECTOR_MODE_INT of a
MODE_PARTIAL_INT mode.
* config/bfin/bfin-modes.def: Add V2PDI and V2SI.
* config/bfin/bfin.c (print_operand): Add macflag and mac/msu modifiers
for CONST_INTs.
(hard_regno_mode_ok): V2PDImode is ok for accumulators.
* config/bfin/bfin.h (CLASS_MAX_NREGS, HARD_REGNO_NREGS): Handle
V2PDImode.
* config/bfin/predicates.md (const01_operand, vec_shift_operand):
New predicates.
* config/bfin/bfin.md (UNSPEC_MUL_WITH_FLAG, UNSPEC_MAC_WITH_FLAG):
New constants.
(MACFLAG_NONE, MACFLAG_T, MACFLAG_FU, MACFLAG_TFU, MACFLAG_IS,
MACFLAG_IU, MACFLAG_W32, MACFLAG_M, MACFLAG_S2RND, MACFLAG_ISS2,
MACFLAG_IH): Likewise.
(movstricthi_1): Renamed from "*movstricthi".
(load_accumulator, load_accumulator_pair, movsi_insv, insv,
ssaddsi3, sssubsi3, ssnegsi2, signbitssi2, smaxhi3, sminhi3,
abshi2, neghi2, ssneghi2, signbitshi2, movhi_low2high,
movhi_high2high, movhi_low2low, movhi_high2low, movhiv2hi_low,
movhiv2hi_high, composev2hi, movv2hi_hi, movv2hi_hi_low,
movv2hi_hi_high, ssaddhi3, sssubhi3, ssaddv2hi3, sssubv2hi3,
addsubv2hi3, subaddv2hi3, ssaddsubv2hi3, sssubaddv2hi3,
sublohiv2hi3, subhilov2hi3, sssublohiv2hi3, sssubhilov2hi3,
addlohiv2hi3, addhilov2hi3, ssaddlohiv2hi3, ssaddhilov2hi3,
mulhisi_ll, mulhisi_lh, mulhisi_hl, mulhisi_hh, ssnegv2hi2,
ssashiftv2hi3, ssashifthi3, lshiftv2hi3, lshifthi3, packv2hi,
flag_mulhi, flag_mulhisi_parts, flag_machi, flag_machi_acconly,
flag_macinithi, flag_macinit1hi, flag_mulv2hi, flag_mulv2hi_parts,
flag_macv2hi_parts, flag_macv2hi_parts_acconly,
flag_macinitv2hi_parts, flag_macinit1v2hi_parts): New patterns.
From-SVN: r113245
2006-04-25 13:49:27 +02:00
|
|
|
|
[(set_attr "type" "dsp32")])
|
|
|
|
|
|
|
|
|
|
(define_insn "sssublohiv2hi3"
|
|
|
|
|
[(set (match_operand:HI 0 "register_operand" "=d")
|
|
|
|
|
(ss_minus:HI (vec_select:HI (match_operand:V2HI 1 "register_operand" "d")
|
|
|
|
|
(parallel [(const_int 1)]))
|
|
|
|
|
(vec_select:HI (match_operand:V2HI 2 "register_operand" "d")
|
|
|
|
|
(parallel [(const_int 0)]))))]
|
|
|
|
|
""
|
rtlanal.c (note_uses): Deal with SEQUENCEs.
* rtlanal.c (note_uses): Deal with SEQUENCEs.
* config/bfin/bfin.c: Include "timevar.h".
(bfin_flag_schedule_insns2, splitting_for_sched,
bfin_flag_var_tracking): New variables.
(print_operand): Handle '%!'.
(override_options): Disable normal sched2 pass, instead set
bfin_flag_schedule_insns2 for reorg to handle it.
(output_file_start): Likewise for var-tracking.
(bfin_optimize_loop): Take some care not to stumble over SEQUENCEs.
(gen_one_bundle, bfin_gen_bundles, type_for_anomaly, trapping_loads_p):
New functions.
(bfin_reorg): Do second scheduling pass here, and call
bfin_gen_bundles. Use type_for_anomaly and trapping_loads_p instead
of examining insns directly. If bfin_flag_var_tracking, call
var-tracking pass when done with everything else.
* config/bfin/bfin.h (PRINT_OPERAND_PUNCT_VALID_P): '!' is valid.
* config/bfin/bfin.md (UNSPEC_32BIT): New constant.
(movsi_insn32): New pattern, with two new splits to create it
before the final scheduling pass.
(neghi2): Not a dsp32 insn, rather alu0.
(movbi, pushsi_insn, popsi_insn, movsi_insn, movv2hi_insn, movhi_insn,
movqi_insn, movsf_insn, movsi_insv, extendhisi2, zero_extendhisi2,
extendqihi2, extendqisi2, zero_extendqihi2, zero_extendqisi2,
mulhisi3, umulhisi3, ssadsi3, sssubsi3, smaxsi3, sminsi3, abssi2,
ssnegsi2, signbitssi2, smaxhi3, sminhi3, abshi2, ssneghi2, signbitshi2,
movhi_low2high, movhi_high2high, movhi_low2low, movhi_high2low,
movhiv2hi_low, movhiv2hi_high, composev2hi, packv2hi, movv2hi_hi,
ssaddhi3, sssubhi3, addv2hi3, ssaddv2hi3, subv2hi3, sssubv2hi3,
addsubv2hi3, subaddv2hi3, ssaddsubv2hi3, sssubaddv2hi3, sublohiv2hi3,
subhilov2hi3, sssublohiv2hi3, sssubhilov2hi3, addlohiv2hi3,
addhilov2hi3, ssaddlohiv2hi3, ssaddhilov2hi3, sminv2hi3, smaxv2hi3,
flag_mulhi, flag_mulhisi, flag_mulhisi_parts, flag_machi,
flag_machi_acconly, flag_macinithi, flag_macinit1hi, mulv2hi3,
flag_mulv2hi, flag_mulv2hi_parts, flag_macv2hi_parts,
flag_macv2hi_parts_acconly, flag_macinitv2hi_parts,
flag_macinit1v2hi_parts, mulhisi_ll, mulhisi_lh, mulhisi_hl,
mulhisi_hh, ssnegv2hi2, absv2hi2, ssashiftv2hi3, ssashifthi3,
lshiftv2hi3, lshifthi3): Use '%!' to terminate all dsp32/load/store
variants instead of ';'.
(ror_one, rol_one): Likewise. Make them dsp32 insns.
(ashlsi3_insn, ashrsi3, lshrsi3): Add dsp32 variants.
(align8, align16, align24): Now named patterns; also using '%!'.
(mnop): New insn.
From-SVN: r119534
2006-12-05 09:49:56 +01:00
|
|
|
|
"%h0 = %d1 - %h2 (S)%!"
|
genmodes.c (make_vector_mode): Allow making VECTOR_MODE_INT of a MODE_PARTIAL_INT mode.
* genmodes.c (make_vector_mode): Allow making VECTOR_MODE_INT of a
MODE_PARTIAL_INT mode.
* config/bfin/bfin-modes.def: Add V2PDI and V2SI.
* config/bfin/bfin.c (print_operand): Add macflag and mac/msu modifiers
for CONST_INTs.
(hard_regno_mode_ok): V2PDImode is ok for accumulators.
* config/bfin/bfin.h (CLASS_MAX_NREGS, HARD_REGNO_NREGS): Handle
V2PDImode.
* config/bfin/predicates.md (const01_operand, vec_shift_operand):
New predicates.
* config/bfin/bfin.md (UNSPEC_MUL_WITH_FLAG, UNSPEC_MAC_WITH_FLAG):
New constants.
(MACFLAG_NONE, MACFLAG_T, MACFLAG_FU, MACFLAG_TFU, MACFLAG_IS,
MACFLAG_IU, MACFLAG_W32, MACFLAG_M, MACFLAG_S2RND, MACFLAG_ISS2,
MACFLAG_IH): Likewise.
(movstricthi_1): Renamed from "*movstricthi".
(load_accumulator, load_accumulator_pair, movsi_insv, insv,
ssaddsi3, sssubsi3, ssnegsi2, signbitssi2, smaxhi3, sminhi3,
abshi2, neghi2, ssneghi2, signbitshi2, movhi_low2high,
movhi_high2high, movhi_low2low, movhi_high2low, movhiv2hi_low,
movhiv2hi_high, composev2hi, movv2hi_hi, movv2hi_hi_low,
movv2hi_hi_high, ssaddhi3, sssubhi3, ssaddv2hi3, sssubv2hi3,
addsubv2hi3, subaddv2hi3, ssaddsubv2hi3, sssubaddv2hi3,
sublohiv2hi3, subhilov2hi3, sssublohiv2hi3, sssubhilov2hi3,
addlohiv2hi3, addhilov2hi3, ssaddlohiv2hi3, ssaddhilov2hi3,
mulhisi_ll, mulhisi_lh, mulhisi_hl, mulhisi_hh, ssnegv2hi2,
ssashiftv2hi3, ssashifthi3, lshiftv2hi3, lshifthi3, packv2hi,
flag_mulhi, flag_mulhisi_parts, flag_machi, flag_machi_acconly,
flag_macinithi, flag_macinit1hi, flag_mulv2hi, flag_mulv2hi_parts,
flag_macv2hi_parts, flag_macv2hi_parts_acconly,
flag_macinitv2hi_parts, flag_macinit1v2hi_parts): New patterns.
From-SVN: r113245
2006-04-25 13:49:27 +02:00
|
|
|
|
[(set_attr "type" "dsp32")])
|
|
|
|
|
|
|
|
|
|
(define_insn "sssubhilov2hi3"
|
|
|
|
|
[(set (match_operand:HI 0 "register_operand" "=d")
|
|
|
|
|
(ss_minus:HI (vec_select:HI (match_operand:V2HI 1 "register_operand" "d")
|
|
|
|
|
(parallel [(const_int 0)]))
|
|
|
|
|
(vec_select:HI (match_operand:V2HI 2 "register_operand" "d")
|
|
|
|
|
(parallel [(const_int 1)]))))]
|
|
|
|
|
""
|
rtlanal.c (note_uses): Deal with SEQUENCEs.
* rtlanal.c (note_uses): Deal with SEQUENCEs.
* config/bfin/bfin.c: Include "timevar.h".
(bfin_flag_schedule_insns2, splitting_for_sched,
bfin_flag_var_tracking): New variables.
(print_operand): Handle '%!'.
(override_options): Disable normal sched2 pass, instead set
bfin_flag_schedule_insns2 for reorg to handle it.
(output_file_start): Likewise for var-tracking.
(bfin_optimize_loop): Take some care not to stumble over SEQUENCEs.
(gen_one_bundle, bfin_gen_bundles, type_for_anomaly, trapping_loads_p):
New functions.
(bfin_reorg): Do second scheduling pass here, and call
bfin_gen_bundles. Use type_for_anomaly and trapping_loads_p instead
of examining insns directly. If bfin_flag_var_tracking, call
var-tracking pass when done with everything else.
* config/bfin/bfin.h (PRINT_OPERAND_PUNCT_VALID_P): '!' is valid.
* config/bfin/bfin.md (UNSPEC_32BIT): New constant.
(movsi_insn32): New pattern, with two new splits to create it
before the final scheduling pass.
(neghi2): Not a dsp32 insn, rather alu0.
(movbi, pushsi_insn, popsi_insn, movsi_insn, movv2hi_insn, movhi_insn,
movqi_insn, movsf_insn, movsi_insv, extendhisi2, zero_extendhisi2,
extendqihi2, extendqisi2, zero_extendqihi2, zero_extendqisi2,
mulhisi3, umulhisi3, ssadsi3, sssubsi3, smaxsi3, sminsi3, abssi2,
ssnegsi2, signbitssi2, smaxhi3, sminhi3, abshi2, ssneghi2, signbitshi2,
movhi_low2high, movhi_high2high, movhi_low2low, movhi_high2low,
movhiv2hi_low, movhiv2hi_high, composev2hi, packv2hi, movv2hi_hi,
ssaddhi3, sssubhi3, addv2hi3, ssaddv2hi3, subv2hi3, sssubv2hi3,
addsubv2hi3, subaddv2hi3, ssaddsubv2hi3, sssubaddv2hi3, sublohiv2hi3,
subhilov2hi3, sssublohiv2hi3, sssubhilov2hi3, addlohiv2hi3,
addhilov2hi3, ssaddlohiv2hi3, ssaddhilov2hi3, sminv2hi3, smaxv2hi3,
flag_mulhi, flag_mulhisi, flag_mulhisi_parts, flag_machi,
flag_machi_acconly, flag_macinithi, flag_macinit1hi, mulv2hi3,
flag_mulv2hi, flag_mulv2hi_parts, flag_macv2hi_parts,
flag_macv2hi_parts_acconly, flag_macinitv2hi_parts,
flag_macinit1v2hi_parts, mulhisi_ll, mulhisi_lh, mulhisi_hl,
mulhisi_hh, ssnegv2hi2, absv2hi2, ssashiftv2hi3, ssashifthi3,
lshiftv2hi3, lshifthi3): Use '%!' to terminate all dsp32/load/store
variants instead of ';'.
(ror_one, rol_one): Likewise. Make them dsp32 insns.
(ashlsi3_insn, ashrsi3, lshrsi3): Add dsp32 variants.
(align8, align16, align24): Now named patterns; also using '%!'.
(mnop): New insn.
From-SVN: r119534
2006-12-05 09:49:56 +01:00
|
|
|
|
"%h0 = %h1 - %d2 (S)%!"
|
genmodes.c (make_vector_mode): Allow making VECTOR_MODE_INT of a MODE_PARTIAL_INT mode.
* genmodes.c (make_vector_mode): Allow making VECTOR_MODE_INT of a
MODE_PARTIAL_INT mode.
* config/bfin/bfin-modes.def: Add V2PDI and V2SI.
* config/bfin/bfin.c (print_operand): Add macflag and mac/msu modifiers
for CONST_INTs.
(hard_regno_mode_ok): V2PDImode is ok for accumulators.
* config/bfin/bfin.h (CLASS_MAX_NREGS, HARD_REGNO_NREGS): Handle
V2PDImode.
* config/bfin/predicates.md (const01_operand, vec_shift_operand):
New predicates.
* config/bfin/bfin.md (UNSPEC_MUL_WITH_FLAG, UNSPEC_MAC_WITH_FLAG):
New constants.
(MACFLAG_NONE, MACFLAG_T, MACFLAG_FU, MACFLAG_TFU, MACFLAG_IS,
MACFLAG_IU, MACFLAG_W32, MACFLAG_M, MACFLAG_S2RND, MACFLAG_ISS2,
MACFLAG_IH): Likewise.
(movstricthi_1): Renamed from "*movstricthi".
(load_accumulator, load_accumulator_pair, movsi_insv, insv,
ssaddsi3, sssubsi3, ssnegsi2, signbitssi2, smaxhi3, sminhi3,
abshi2, neghi2, ssneghi2, signbitshi2, movhi_low2high,
movhi_high2high, movhi_low2low, movhi_high2low, movhiv2hi_low,
movhiv2hi_high, composev2hi, movv2hi_hi, movv2hi_hi_low,
movv2hi_hi_high, ssaddhi3, sssubhi3, ssaddv2hi3, sssubv2hi3,
addsubv2hi3, subaddv2hi3, ssaddsubv2hi3, sssubaddv2hi3,
sublohiv2hi3, subhilov2hi3, sssublohiv2hi3, sssubhilov2hi3,
addlohiv2hi3, addhilov2hi3, ssaddlohiv2hi3, ssaddhilov2hi3,
mulhisi_ll, mulhisi_lh, mulhisi_hl, mulhisi_hh, ssnegv2hi2,
ssashiftv2hi3, ssashifthi3, lshiftv2hi3, lshifthi3, packv2hi,
flag_mulhi, flag_mulhisi_parts, flag_machi, flag_machi_acconly,
flag_macinithi, flag_macinit1hi, flag_mulv2hi, flag_mulv2hi_parts,
flag_macv2hi_parts, flag_macv2hi_parts_acconly,
flag_macinitv2hi_parts, flag_macinit1v2hi_parts): New patterns.
From-SVN: r113245
2006-04-25 13:49:27 +02:00
|
|
|
|
[(set_attr "type" "dsp32")])
|
|
|
|
|
|
|
|
|
|
(define_insn "addlohiv2hi3"
|
|
|
|
|
[(set (match_operand:HI 0 "register_operand" "=d")
|
|
|
|
|
(plus:HI (vec_select:HI (match_operand:V2HI 1 "register_operand" "d")
|
|
|
|
|
(parallel [(const_int 1)]))
|
|
|
|
|
(vec_select:HI (match_operand:V2HI 2 "register_operand" "d")
|
|
|
|
|
(parallel [(const_int 0)]))))]
|
|
|
|
|
""
|
rtlanal.c (note_uses): Deal with SEQUENCEs.
* rtlanal.c (note_uses): Deal with SEQUENCEs.
* config/bfin/bfin.c: Include "timevar.h".
(bfin_flag_schedule_insns2, splitting_for_sched,
bfin_flag_var_tracking): New variables.
(print_operand): Handle '%!'.
(override_options): Disable normal sched2 pass, instead set
bfin_flag_schedule_insns2 for reorg to handle it.
(output_file_start): Likewise for var-tracking.
(bfin_optimize_loop): Take some care not to stumble over SEQUENCEs.
(gen_one_bundle, bfin_gen_bundles, type_for_anomaly, trapping_loads_p):
New functions.
(bfin_reorg): Do second scheduling pass here, and call
bfin_gen_bundles. Use type_for_anomaly and trapping_loads_p instead
of examining insns directly. If bfin_flag_var_tracking, call
var-tracking pass when done with everything else.
* config/bfin/bfin.h (PRINT_OPERAND_PUNCT_VALID_P): '!' is valid.
* config/bfin/bfin.md (UNSPEC_32BIT): New constant.
(movsi_insn32): New pattern, with two new splits to create it
before the final scheduling pass.
(neghi2): Not a dsp32 insn, rather alu0.
(movbi, pushsi_insn, popsi_insn, movsi_insn, movv2hi_insn, movhi_insn,
movqi_insn, movsf_insn, movsi_insv, extendhisi2, zero_extendhisi2,
extendqihi2, extendqisi2, zero_extendqihi2, zero_extendqisi2,
mulhisi3, umulhisi3, ssadsi3, sssubsi3, smaxsi3, sminsi3, abssi2,
ssnegsi2, signbitssi2, smaxhi3, sminhi3, abshi2, ssneghi2, signbitshi2,
movhi_low2high, movhi_high2high, movhi_low2low, movhi_high2low,
movhiv2hi_low, movhiv2hi_high, composev2hi, packv2hi, movv2hi_hi,
ssaddhi3, sssubhi3, addv2hi3, ssaddv2hi3, subv2hi3, sssubv2hi3,
addsubv2hi3, subaddv2hi3, ssaddsubv2hi3, sssubaddv2hi3, sublohiv2hi3,
subhilov2hi3, sssublohiv2hi3, sssubhilov2hi3, addlohiv2hi3,
addhilov2hi3, ssaddlohiv2hi3, ssaddhilov2hi3, sminv2hi3, smaxv2hi3,
flag_mulhi, flag_mulhisi, flag_mulhisi_parts, flag_machi,
flag_machi_acconly, flag_macinithi, flag_macinit1hi, mulv2hi3,
flag_mulv2hi, flag_mulv2hi_parts, flag_macv2hi_parts,
flag_macv2hi_parts_acconly, flag_macinitv2hi_parts,
flag_macinit1v2hi_parts, mulhisi_ll, mulhisi_lh, mulhisi_hl,
mulhisi_hh, ssnegv2hi2, absv2hi2, ssashiftv2hi3, ssashifthi3,
lshiftv2hi3, lshifthi3): Use '%!' to terminate all dsp32/load/store
variants instead of ';'.
(ror_one, rol_one): Likewise. Make them dsp32 insns.
(ashlsi3_insn, ashrsi3, lshrsi3): Add dsp32 variants.
(align8, align16, align24): Now named patterns; also using '%!'.
(mnop): New insn.
From-SVN: r119534
2006-12-05 09:49:56 +01:00
|
|
|
|
"%h0 = %d1 + %h2%!"
|
genmodes.c (make_vector_mode): Allow making VECTOR_MODE_INT of a MODE_PARTIAL_INT mode.
* genmodes.c (make_vector_mode): Allow making VECTOR_MODE_INT of a
MODE_PARTIAL_INT mode.
* config/bfin/bfin-modes.def: Add V2PDI and V2SI.
* config/bfin/bfin.c (print_operand): Add macflag and mac/msu modifiers
for CONST_INTs.
(hard_regno_mode_ok): V2PDImode is ok for accumulators.
* config/bfin/bfin.h (CLASS_MAX_NREGS, HARD_REGNO_NREGS): Handle
V2PDImode.
* config/bfin/predicates.md (const01_operand, vec_shift_operand):
New predicates.
* config/bfin/bfin.md (UNSPEC_MUL_WITH_FLAG, UNSPEC_MAC_WITH_FLAG):
New constants.
(MACFLAG_NONE, MACFLAG_T, MACFLAG_FU, MACFLAG_TFU, MACFLAG_IS,
MACFLAG_IU, MACFLAG_W32, MACFLAG_M, MACFLAG_S2RND, MACFLAG_ISS2,
MACFLAG_IH): Likewise.
(movstricthi_1): Renamed from "*movstricthi".
(load_accumulator, load_accumulator_pair, movsi_insv, insv,
ssaddsi3, sssubsi3, ssnegsi2, signbitssi2, smaxhi3, sminhi3,
abshi2, neghi2, ssneghi2, signbitshi2, movhi_low2high,
movhi_high2high, movhi_low2low, movhi_high2low, movhiv2hi_low,
movhiv2hi_high, composev2hi, movv2hi_hi, movv2hi_hi_low,
movv2hi_hi_high, ssaddhi3, sssubhi3, ssaddv2hi3, sssubv2hi3,
addsubv2hi3, subaddv2hi3, ssaddsubv2hi3, sssubaddv2hi3,
sublohiv2hi3, subhilov2hi3, sssublohiv2hi3, sssubhilov2hi3,
addlohiv2hi3, addhilov2hi3, ssaddlohiv2hi3, ssaddhilov2hi3,
mulhisi_ll, mulhisi_lh, mulhisi_hl, mulhisi_hh, ssnegv2hi2,
ssashiftv2hi3, ssashifthi3, lshiftv2hi3, lshifthi3, packv2hi,
flag_mulhi, flag_mulhisi_parts, flag_machi, flag_machi_acconly,
flag_macinithi, flag_macinit1hi, flag_mulv2hi, flag_mulv2hi_parts,
flag_macv2hi_parts, flag_macv2hi_parts_acconly,
flag_macinitv2hi_parts, flag_macinit1v2hi_parts): New patterns.
From-SVN: r113245
2006-04-25 13:49:27 +02:00
|
|
|
|
[(set_attr "type" "dsp32")])
|
|
|
|
|
|
|
|
|
|
(define_insn "addhilov2hi3"
|
|
|
|
|
[(set (match_operand:HI 0 "register_operand" "=d")
|
|
|
|
|
(plus:HI (vec_select:HI (match_operand:V2HI 1 "register_operand" "d")
|
|
|
|
|
(parallel [(const_int 0)]))
|
|
|
|
|
(vec_select:HI (match_operand:V2HI 2 "register_operand" "d")
|
|
|
|
|
(parallel [(const_int 1)]))))]
|
|
|
|
|
""
|
rtlanal.c (note_uses): Deal with SEQUENCEs.
* rtlanal.c (note_uses): Deal with SEQUENCEs.
* config/bfin/bfin.c: Include "timevar.h".
(bfin_flag_schedule_insns2, splitting_for_sched,
bfin_flag_var_tracking): New variables.
(print_operand): Handle '%!'.
(override_options): Disable normal sched2 pass, instead set
bfin_flag_schedule_insns2 for reorg to handle it.
(output_file_start): Likewise for var-tracking.
(bfin_optimize_loop): Take some care not to stumble over SEQUENCEs.
(gen_one_bundle, bfin_gen_bundles, type_for_anomaly, trapping_loads_p):
New functions.
(bfin_reorg): Do second scheduling pass here, and call
bfin_gen_bundles. Use type_for_anomaly and trapping_loads_p instead
of examining insns directly. If bfin_flag_var_tracking, call
var-tracking pass when done with everything else.
* config/bfin/bfin.h (PRINT_OPERAND_PUNCT_VALID_P): '!' is valid.
* config/bfin/bfin.md (UNSPEC_32BIT): New constant.
(movsi_insn32): New pattern, with two new splits to create it
before the final scheduling pass.
(neghi2): Not a dsp32 insn, rather alu0.
(movbi, pushsi_insn, popsi_insn, movsi_insn, movv2hi_insn, movhi_insn,
movqi_insn, movsf_insn, movsi_insv, extendhisi2, zero_extendhisi2,
extendqihi2, extendqisi2, zero_extendqihi2, zero_extendqisi2,
mulhisi3, umulhisi3, ssadsi3, sssubsi3, smaxsi3, sminsi3, abssi2,
ssnegsi2, signbitssi2, smaxhi3, sminhi3, abshi2, ssneghi2, signbitshi2,
movhi_low2high, movhi_high2high, movhi_low2low, movhi_high2low,
movhiv2hi_low, movhiv2hi_high, composev2hi, packv2hi, movv2hi_hi,
ssaddhi3, sssubhi3, addv2hi3, ssaddv2hi3, subv2hi3, sssubv2hi3,
addsubv2hi3, subaddv2hi3, ssaddsubv2hi3, sssubaddv2hi3, sublohiv2hi3,
subhilov2hi3, sssublohiv2hi3, sssubhilov2hi3, addlohiv2hi3,
addhilov2hi3, ssaddlohiv2hi3, ssaddhilov2hi3, sminv2hi3, smaxv2hi3,
flag_mulhi, flag_mulhisi, flag_mulhisi_parts, flag_machi,
flag_machi_acconly, flag_macinithi, flag_macinit1hi, mulv2hi3,
flag_mulv2hi, flag_mulv2hi_parts, flag_macv2hi_parts,
flag_macv2hi_parts_acconly, flag_macinitv2hi_parts,
flag_macinit1v2hi_parts, mulhisi_ll, mulhisi_lh, mulhisi_hl,
mulhisi_hh, ssnegv2hi2, absv2hi2, ssashiftv2hi3, ssashifthi3,
lshiftv2hi3, lshifthi3): Use '%!' to terminate all dsp32/load/store
variants instead of ';'.
(ror_one, rol_one): Likewise. Make them dsp32 insns.
(ashlsi3_insn, ashrsi3, lshrsi3): Add dsp32 variants.
(align8, align16, align24): Now named patterns; also using '%!'.
(mnop): New insn.
From-SVN: r119534
2006-12-05 09:49:56 +01:00
|
|
|
|
"%h0 = %h1 + %d2%!"
|
genmodes.c (make_vector_mode): Allow making VECTOR_MODE_INT of a MODE_PARTIAL_INT mode.
* genmodes.c (make_vector_mode): Allow making VECTOR_MODE_INT of a
MODE_PARTIAL_INT mode.
* config/bfin/bfin-modes.def: Add V2PDI and V2SI.
* config/bfin/bfin.c (print_operand): Add macflag and mac/msu modifiers
for CONST_INTs.
(hard_regno_mode_ok): V2PDImode is ok for accumulators.
* config/bfin/bfin.h (CLASS_MAX_NREGS, HARD_REGNO_NREGS): Handle
V2PDImode.
* config/bfin/predicates.md (const01_operand, vec_shift_operand):
New predicates.
* config/bfin/bfin.md (UNSPEC_MUL_WITH_FLAG, UNSPEC_MAC_WITH_FLAG):
New constants.
(MACFLAG_NONE, MACFLAG_T, MACFLAG_FU, MACFLAG_TFU, MACFLAG_IS,
MACFLAG_IU, MACFLAG_W32, MACFLAG_M, MACFLAG_S2RND, MACFLAG_ISS2,
MACFLAG_IH): Likewise.
(movstricthi_1): Renamed from "*movstricthi".
(load_accumulator, load_accumulator_pair, movsi_insv, insv,
ssaddsi3, sssubsi3, ssnegsi2, signbitssi2, smaxhi3, sminhi3,
abshi2, neghi2, ssneghi2, signbitshi2, movhi_low2high,
movhi_high2high, movhi_low2low, movhi_high2low, movhiv2hi_low,
movhiv2hi_high, composev2hi, movv2hi_hi, movv2hi_hi_low,
movv2hi_hi_high, ssaddhi3, sssubhi3, ssaddv2hi3, sssubv2hi3,
addsubv2hi3, subaddv2hi3, ssaddsubv2hi3, sssubaddv2hi3,
sublohiv2hi3, subhilov2hi3, sssublohiv2hi3, sssubhilov2hi3,
addlohiv2hi3, addhilov2hi3, ssaddlohiv2hi3, ssaddhilov2hi3,
mulhisi_ll, mulhisi_lh, mulhisi_hl, mulhisi_hh, ssnegv2hi2,
ssashiftv2hi3, ssashifthi3, lshiftv2hi3, lshifthi3, packv2hi,
flag_mulhi, flag_mulhisi_parts, flag_machi, flag_machi_acconly,
flag_macinithi, flag_macinit1hi, flag_mulv2hi, flag_mulv2hi_parts,
flag_macv2hi_parts, flag_macv2hi_parts_acconly,
flag_macinitv2hi_parts, flag_macinit1v2hi_parts): New patterns.
From-SVN: r113245
2006-04-25 13:49:27 +02:00
|
|
|
|
[(set_attr "type" "dsp32")])
|
|
|
|
|
|
|
|
|
|
(define_insn "ssaddlohiv2hi3"
|
|
|
|
|
[(set (match_operand:HI 0 "register_operand" "=d")
|
|
|
|
|
(ss_plus:HI (vec_select:HI (match_operand:V2HI 1 "register_operand" "d")
|
|
|
|
|
(parallel [(const_int 1)]))
|
|
|
|
|
(vec_select:HI (match_operand:V2HI 2 "register_operand" "d")
|
|
|
|
|
(parallel [(const_int 0)]))))]
|
|
|
|
|
""
|
rtlanal.c (note_uses): Deal with SEQUENCEs.
* rtlanal.c (note_uses): Deal with SEQUENCEs.
* config/bfin/bfin.c: Include "timevar.h".
(bfin_flag_schedule_insns2, splitting_for_sched,
bfin_flag_var_tracking): New variables.
(print_operand): Handle '%!'.
(override_options): Disable normal sched2 pass, instead set
bfin_flag_schedule_insns2 for reorg to handle it.
(output_file_start): Likewise for var-tracking.
(bfin_optimize_loop): Take some care not to stumble over SEQUENCEs.
(gen_one_bundle, bfin_gen_bundles, type_for_anomaly, trapping_loads_p):
New functions.
(bfin_reorg): Do second scheduling pass here, and call
bfin_gen_bundles. Use type_for_anomaly and trapping_loads_p instead
of examining insns directly. If bfin_flag_var_tracking, call
var-tracking pass when done with everything else.
* config/bfin/bfin.h (PRINT_OPERAND_PUNCT_VALID_P): '!' is valid.
* config/bfin/bfin.md (UNSPEC_32BIT): New constant.
(movsi_insn32): New pattern, with two new splits to create it
before the final scheduling pass.
(neghi2): Not a dsp32 insn, rather alu0.
(movbi, pushsi_insn, popsi_insn, movsi_insn, movv2hi_insn, movhi_insn,
movqi_insn, movsf_insn, movsi_insv, extendhisi2, zero_extendhisi2,
extendqihi2, extendqisi2, zero_extendqihi2, zero_extendqisi2,
mulhisi3, umulhisi3, ssadsi3, sssubsi3, smaxsi3, sminsi3, abssi2,
ssnegsi2, signbitssi2, smaxhi3, sminhi3, abshi2, ssneghi2, signbitshi2,
movhi_low2high, movhi_high2high, movhi_low2low, movhi_high2low,
movhiv2hi_low, movhiv2hi_high, composev2hi, packv2hi, movv2hi_hi,
ssaddhi3, sssubhi3, addv2hi3, ssaddv2hi3, subv2hi3, sssubv2hi3,
addsubv2hi3, subaddv2hi3, ssaddsubv2hi3, sssubaddv2hi3, sublohiv2hi3,
subhilov2hi3, sssublohiv2hi3, sssubhilov2hi3, addlohiv2hi3,
addhilov2hi3, ssaddlohiv2hi3, ssaddhilov2hi3, sminv2hi3, smaxv2hi3,
flag_mulhi, flag_mulhisi, flag_mulhisi_parts, flag_machi,
flag_machi_acconly, flag_macinithi, flag_macinit1hi, mulv2hi3,
flag_mulv2hi, flag_mulv2hi_parts, flag_macv2hi_parts,
flag_macv2hi_parts_acconly, flag_macinitv2hi_parts,
flag_macinit1v2hi_parts, mulhisi_ll, mulhisi_lh, mulhisi_hl,
mulhisi_hh, ssnegv2hi2, absv2hi2, ssashiftv2hi3, ssashifthi3,
lshiftv2hi3, lshifthi3): Use '%!' to terminate all dsp32/load/store
variants instead of ';'.
(ror_one, rol_one): Likewise. Make them dsp32 insns.
(ashlsi3_insn, ashrsi3, lshrsi3): Add dsp32 variants.
(align8, align16, align24): Now named patterns; also using '%!'.
(mnop): New insn.
From-SVN: r119534
2006-12-05 09:49:56 +01:00
|
|
|
|
"%h0 = %d1 + %h2 (S)%!"
|
genmodes.c (make_vector_mode): Allow making VECTOR_MODE_INT of a MODE_PARTIAL_INT mode.
* genmodes.c (make_vector_mode): Allow making VECTOR_MODE_INT of a
MODE_PARTIAL_INT mode.
* config/bfin/bfin-modes.def: Add V2PDI and V2SI.
* config/bfin/bfin.c (print_operand): Add macflag and mac/msu modifiers
for CONST_INTs.
(hard_regno_mode_ok): V2PDImode is ok for accumulators.
* config/bfin/bfin.h (CLASS_MAX_NREGS, HARD_REGNO_NREGS): Handle
V2PDImode.
* config/bfin/predicates.md (const01_operand, vec_shift_operand):
New predicates.
* config/bfin/bfin.md (UNSPEC_MUL_WITH_FLAG, UNSPEC_MAC_WITH_FLAG):
New constants.
(MACFLAG_NONE, MACFLAG_T, MACFLAG_FU, MACFLAG_TFU, MACFLAG_IS,
MACFLAG_IU, MACFLAG_W32, MACFLAG_M, MACFLAG_S2RND, MACFLAG_ISS2,
MACFLAG_IH): Likewise.
(movstricthi_1): Renamed from "*movstricthi".
(load_accumulator, load_accumulator_pair, movsi_insv, insv,
ssaddsi3, sssubsi3, ssnegsi2, signbitssi2, smaxhi3, sminhi3,
abshi2, neghi2, ssneghi2, signbitshi2, movhi_low2high,
movhi_high2high, movhi_low2low, movhi_high2low, movhiv2hi_low,
movhiv2hi_high, composev2hi, movv2hi_hi, movv2hi_hi_low,
movv2hi_hi_high, ssaddhi3, sssubhi3, ssaddv2hi3, sssubv2hi3,
addsubv2hi3, subaddv2hi3, ssaddsubv2hi3, sssubaddv2hi3,
sublohiv2hi3, subhilov2hi3, sssublohiv2hi3, sssubhilov2hi3,
addlohiv2hi3, addhilov2hi3, ssaddlohiv2hi3, ssaddhilov2hi3,
mulhisi_ll, mulhisi_lh, mulhisi_hl, mulhisi_hh, ssnegv2hi2,
ssashiftv2hi3, ssashifthi3, lshiftv2hi3, lshifthi3, packv2hi,
flag_mulhi, flag_mulhisi_parts, flag_machi, flag_machi_acconly,
flag_macinithi, flag_macinit1hi, flag_mulv2hi, flag_mulv2hi_parts,
flag_macv2hi_parts, flag_macv2hi_parts_acconly,
flag_macinitv2hi_parts, flag_macinit1v2hi_parts): New patterns.
From-SVN: r113245
2006-04-25 13:49:27 +02:00
|
|
|
|
[(set_attr "type" "dsp32")])
|
|
|
|
|
|
|
|
|
|
(define_insn "ssaddhilov2hi3"
|
|
|
|
|
[(set (match_operand:HI 0 "register_operand" "=d")
|
|
|
|
|
(ss_plus:HI (vec_select:HI (match_operand:V2HI 1 "register_operand" "d")
|
|
|
|
|
(parallel [(const_int 0)]))
|
|
|
|
|
(vec_select:HI (match_operand:V2HI 2 "register_operand" "d")
|
|
|
|
|
(parallel [(const_int 1)]))))]
|
|
|
|
|
""
|
rtlanal.c (note_uses): Deal with SEQUENCEs.
* rtlanal.c (note_uses): Deal with SEQUENCEs.
* config/bfin/bfin.c: Include "timevar.h".
(bfin_flag_schedule_insns2, splitting_for_sched,
bfin_flag_var_tracking): New variables.
(print_operand): Handle '%!'.
(override_options): Disable normal sched2 pass, instead set
bfin_flag_schedule_insns2 for reorg to handle it.
(output_file_start): Likewise for var-tracking.
(bfin_optimize_loop): Take some care not to stumble over SEQUENCEs.
(gen_one_bundle, bfin_gen_bundles, type_for_anomaly, trapping_loads_p):
New functions.
(bfin_reorg): Do second scheduling pass here, and call
bfin_gen_bundles. Use type_for_anomaly and trapping_loads_p instead
of examining insns directly. If bfin_flag_var_tracking, call
var-tracking pass when done with everything else.
* config/bfin/bfin.h (PRINT_OPERAND_PUNCT_VALID_P): '!' is valid.
* config/bfin/bfin.md (UNSPEC_32BIT): New constant.
(movsi_insn32): New pattern, with two new splits to create it
before the final scheduling pass.
(neghi2): Not a dsp32 insn, rather alu0.
(movbi, pushsi_insn, popsi_insn, movsi_insn, movv2hi_insn, movhi_insn,
movqi_insn, movsf_insn, movsi_insv, extendhisi2, zero_extendhisi2,
extendqihi2, extendqisi2, zero_extendqihi2, zero_extendqisi2,
mulhisi3, umulhisi3, ssadsi3, sssubsi3, smaxsi3, sminsi3, abssi2,
ssnegsi2, signbitssi2, smaxhi3, sminhi3, abshi2, ssneghi2, signbitshi2,
movhi_low2high, movhi_high2high, movhi_low2low, movhi_high2low,
movhiv2hi_low, movhiv2hi_high, composev2hi, packv2hi, movv2hi_hi,
ssaddhi3, sssubhi3, addv2hi3, ssaddv2hi3, subv2hi3, sssubv2hi3,
addsubv2hi3, subaddv2hi3, ssaddsubv2hi3, sssubaddv2hi3, sublohiv2hi3,
subhilov2hi3, sssublohiv2hi3, sssubhilov2hi3, addlohiv2hi3,
addhilov2hi3, ssaddlohiv2hi3, ssaddhilov2hi3, sminv2hi3, smaxv2hi3,
flag_mulhi, flag_mulhisi, flag_mulhisi_parts, flag_machi,
flag_machi_acconly, flag_macinithi, flag_macinit1hi, mulv2hi3,
flag_mulv2hi, flag_mulv2hi_parts, flag_macv2hi_parts,
flag_macv2hi_parts_acconly, flag_macinitv2hi_parts,
flag_macinit1v2hi_parts, mulhisi_ll, mulhisi_lh, mulhisi_hl,
mulhisi_hh, ssnegv2hi2, absv2hi2, ssashiftv2hi3, ssashifthi3,
lshiftv2hi3, lshifthi3): Use '%!' to terminate all dsp32/load/store
variants instead of ';'.
(ror_one, rol_one): Likewise. Make them dsp32 insns.
(ashlsi3_insn, ashrsi3, lshrsi3): Add dsp32 variants.
(align8, align16, align24): Now named patterns; also using '%!'.
(mnop): New insn.
From-SVN: r119534
2006-12-05 09:49:56 +01:00
|
|
|
|
"%h0 = %h1 + %d2 (S)%!"
|
genmodes.c (make_vector_mode): Allow making VECTOR_MODE_INT of a MODE_PARTIAL_INT mode.
* genmodes.c (make_vector_mode): Allow making VECTOR_MODE_INT of a
MODE_PARTIAL_INT mode.
* config/bfin/bfin-modes.def: Add V2PDI and V2SI.
* config/bfin/bfin.c (print_operand): Add macflag and mac/msu modifiers
for CONST_INTs.
(hard_regno_mode_ok): V2PDImode is ok for accumulators.
* config/bfin/bfin.h (CLASS_MAX_NREGS, HARD_REGNO_NREGS): Handle
V2PDImode.
* config/bfin/predicates.md (const01_operand, vec_shift_operand):
New predicates.
* config/bfin/bfin.md (UNSPEC_MUL_WITH_FLAG, UNSPEC_MAC_WITH_FLAG):
New constants.
(MACFLAG_NONE, MACFLAG_T, MACFLAG_FU, MACFLAG_TFU, MACFLAG_IS,
MACFLAG_IU, MACFLAG_W32, MACFLAG_M, MACFLAG_S2RND, MACFLAG_ISS2,
MACFLAG_IH): Likewise.
(movstricthi_1): Renamed from "*movstricthi".
(load_accumulator, load_accumulator_pair, movsi_insv, insv,
ssaddsi3, sssubsi3, ssnegsi2, signbitssi2, smaxhi3, sminhi3,
abshi2, neghi2, ssneghi2, signbitshi2, movhi_low2high,
movhi_high2high, movhi_low2low, movhi_high2low, movhiv2hi_low,
movhiv2hi_high, composev2hi, movv2hi_hi, movv2hi_hi_low,
movv2hi_hi_high, ssaddhi3, sssubhi3, ssaddv2hi3, sssubv2hi3,
addsubv2hi3, subaddv2hi3, ssaddsubv2hi3, sssubaddv2hi3,
sublohiv2hi3, subhilov2hi3, sssublohiv2hi3, sssubhilov2hi3,
addlohiv2hi3, addhilov2hi3, ssaddlohiv2hi3, ssaddhilov2hi3,
mulhisi_ll, mulhisi_lh, mulhisi_hl, mulhisi_hh, ssnegv2hi2,
ssashiftv2hi3, ssashifthi3, lshiftv2hi3, lshifthi3, packv2hi,
flag_mulhi, flag_mulhisi_parts, flag_machi, flag_machi_acconly,
flag_macinithi, flag_macinit1hi, flag_mulv2hi, flag_mulv2hi_parts,
flag_macv2hi_parts, flag_macv2hi_parts_acconly,
flag_macinitv2hi_parts, flag_macinit1v2hi_parts): New patterns.
From-SVN: r113245
2006-04-25 13:49:27 +02:00
|
|
|
|
[(set_attr "type" "dsp32")])
|
|
|
|
|
|
2005-06-30 09:57:05 +02:00
|
|
|
|
(define_insn "sminv2hi3"
|
2005-04-05 13:26:48 +02:00
|
|
|
|
[(set (match_operand:V2HI 0 "register_operand" "=d")
|
|
|
|
|
(smin:V2HI (match_operand:V2HI 1 "register_operand" "d")
|
|
|
|
|
(match_operand:V2HI 2 "register_operand" "d")))]
|
|
|
|
|
""
|
rtlanal.c (note_uses): Deal with SEQUENCEs.
* rtlanal.c (note_uses): Deal with SEQUENCEs.
* config/bfin/bfin.c: Include "timevar.h".
(bfin_flag_schedule_insns2, splitting_for_sched,
bfin_flag_var_tracking): New variables.
(print_operand): Handle '%!'.
(override_options): Disable normal sched2 pass, instead set
bfin_flag_schedule_insns2 for reorg to handle it.
(output_file_start): Likewise for var-tracking.
(bfin_optimize_loop): Take some care not to stumble over SEQUENCEs.
(gen_one_bundle, bfin_gen_bundles, type_for_anomaly, trapping_loads_p):
New functions.
(bfin_reorg): Do second scheduling pass here, and call
bfin_gen_bundles. Use type_for_anomaly and trapping_loads_p instead
of examining insns directly. If bfin_flag_var_tracking, call
var-tracking pass when done with everything else.
* config/bfin/bfin.h (PRINT_OPERAND_PUNCT_VALID_P): '!' is valid.
* config/bfin/bfin.md (UNSPEC_32BIT): New constant.
(movsi_insn32): New pattern, with two new splits to create it
before the final scheduling pass.
(neghi2): Not a dsp32 insn, rather alu0.
(movbi, pushsi_insn, popsi_insn, movsi_insn, movv2hi_insn, movhi_insn,
movqi_insn, movsf_insn, movsi_insv, extendhisi2, zero_extendhisi2,
extendqihi2, extendqisi2, zero_extendqihi2, zero_extendqisi2,
mulhisi3, umulhisi3, ssadsi3, sssubsi3, smaxsi3, sminsi3, abssi2,
ssnegsi2, signbitssi2, smaxhi3, sminhi3, abshi2, ssneghi2, signbitshi2,
movhi_low2high, movhi_high2high, movhi_low2low, movhi_high2low,
movhiv2hi_low, movhiv2hi_high, composev2hi, packv2hi, movv2hi_hi,
ssaddhi3, sssubhi3, addv2hi3, ssaddv2hi3, subv2hi3, sssubv2hi3,
addsubv2hi3, subaddv2hi3, ssaddsubv2hi3, sssubaddv2hi3, sublohiv2hi3,
subhilov2hi3, sssublohiv2hi3, sssubhilov2hi3, addlohiv2hi3,
addhilov2hi3, ssaddlohiv2hi3, ssaddhilov2hi3, sminv2hi3, smaxv2hi3,
flag_mulhi, flag_mulhisi, flag_mulhisi_parts, flag_machi,
flag_machi_acconly, flag_macinithi, flag_macinit1hi, mulv2hi3,
flag_mulv2hi, flag_mulv2hi_parts, flag_macv2hi_parts,
flag_macv2hi_parts_acconly, flag_macinitv2hi_parts,
flag_macinit1v2hi_parts, mulhisi_ll, mulhisi_lh, mulhisi_hl,
mulhisi_hh, ssnegv2hi2, absv2hi2, ssashiftv2hi3, ssashifthi3,
lshiftv2hi3, lshifthi3): Use '%!' to terminate all dsp32/load/store
variants instead of ';'.
(ror_one, rol_one): Likewise. Make them dsp32 insns.
(ashlsi3_insn, ashrsi3, lshrsi3): Add dsp32 variants.
(align8, align16, align24): Now named patterns; also using '%!'.
(mnop): New insn.
From-SVN: r119534
2006-12-05 09:49:56 +01:00
|
|
|
|
"%0 = MIN (%1, %2) (V)%!"
|
2005-04-05 13:26:48 +02:00
|
|
|
|
[(set_attr "type" "dsp32")])
|
|
|
|
|
|
2005-06-30 09:57:05 +02:00
|
|
|
|
(define_insn "smaxv2hi3"
|
2005-04-05 13:26:48 +02:00
|
|
|
|
[(set (match_operand:V2HI 0 "register_operand" "=d")
|
|
|
|
|
(smax:V2HI (match_operand:V2HI 1 "register_operand" "d")
|
|
|
|
|
(match_operand:V2HI 2 "register_operand" "d")))]
|
|
|
|
|
""
|
rtlanal.c (note_uses): Deal with SEQUENCEs.
* rtlanal.c (note_uses): Deal with SEQUENCEs.
* config/bfin/bfin.c: Include "timevar.h".
(bfin_flag_schedule_insns2, splitting_for_sched,
bfin_flag_var_tracking): New variables.
(print_operand): Handle '%!'.
(override_options): Disable normal sched2 pass, instead set
bfin_flag_schedule_insns2 for reorg to handle it.
(output_file_start): Likewise for var-tracking.
(bfin_optimize_loop): Take some care not to stumble over SEQUENCEs.
(gen_one_bundle, bfin_gen_bundles, type_for_anomaly, trapping_loads_p):
New functions.
(bfin_reorg): Do second scheduling pass here, and call
bfin_gen_bundles. Use type_for_anomaly and trapping_loads_p instead
of examining insns directly. If bfin_flag_var_tracking, call
var-tracking pass when done with everything else.
* config/bfin/bfin.h (PRINT_OPERAND_PUNCT_VALID_P): '!' is valid.
* config/bfin/bfin.md (UNSPEC_32BIT): New constant.
(movsi_insn32): New pattern, with two new splits to create it
before the final scheduling pass.
(neghi2): Not a dsp32 insn, rather alu0.
(movbi, pushsi_insn, popsi_insn, movsi_insn, movv2hi_insn, movhi_insn,
movqi_insn, movsf_insn, movsi_insv, extendhisi2, zero_extendhisi2,
extendqihi2, extendqisi2, zero_extendqihi2, zero_extendqisi2,
mulhisi3, umulhisi3, ssadsi3, sssubsi3, smaxsi3, sminsi3, abssi2,
ssnegsi2, signbitssi2, smaxhi3, sminhi3, abshi2, ssneghi2, signbitshi2,
movhi_low2high, movhi_high2high, movhi_low2low, movhi_high2low,
movhiv2hi_low, movhiv2hi_high, composev2hi, packv2hi, movv2hi_hi,
ssaddhi3, sssubhi3, addv2hi3, ssaddv2hi3, subv2hi3, sssubv2hi3,
addsubv2hi3, subaddv2hi3, ssaddsubv2hi3, sssubaddv2hi3, sublohiv2hi3,
subhilov2hi3, sssublohiv2hi3, sssubhilov2hi3, addlohiv2hi3,
addhilov2hi3, ssaddlohiv2hi3, ssaddhilov2hi3, sminv2hi3, smaxv2hi3,
flag_mulhi, flag_mulhisi, flag_mulhisi_parts, flag_machi,
flag_machi_acconly, flag_macinithi, flag_macinit1hi, mulv2hi3,
flag_mulv2hi, flag_mulv2hi_parts, flag_macv2hi_parts,
flag_macv2hi_parts_acconly, flag_macinitv2hi_parts,
flag_macinit1v2hi_parts, mulhisi_ll, mulhisi_lh, mulhisi_hl,
mulhisi_hh, ssnegv2hi2, absv2hi2, ssashiftv2hi3, ssashifthi3,
lshiftv2hi3, lshifthi3): Use '%!' to terminate all dsp32/load/store
variants instead of ';'.
(ror_one, rol_one): Likewise. Make them dsp32 insns.
(ashlsi3_insn, ashrsi3, lshrsi3): Add dsp32 variants.
(align8, align16, align24): Now named patterns; also using '%!'.
(mnop): New insn.
From-SVN: r119534
2006-12-05 09:49:56 +01:00
|
|
|
|
"%0 = MAX (%1, %2) (V)%!"
|
2005-04-05 13:26:48 +02:00
|
|
|
|
[(set_attr "type" "dsp32")])
|
|
|
|
|
|
genmodes.c (make_vector_mode): Allow making VECTOR_MODE_INT of a MODE_PARTIAL_INT mode.
* genmodes.c (make_vector_mode): Allow making VECTOR_MODE_INT of a
MODE_PARTIAL_INT mode.
* config/bfin/bfin-modes.def: Add V2PDI and V2SI.
* config/bfin/bfin.c (print_operand): Add macflag and mac/msu modifiers
for CONST_INTs.
(hard_regno_mode_ok): V2PDImode is ok for accumulators.
* config/bfin/bfin.h (CLASS_MAX_NREGS, HARD_REGNO_NREGS): Handle
V2PDImode.
* config/bfin/predicates.md (const01_operand, vec_shift_operand):
New predicates.
* config/bfin/bfin.md (UNSPEC_MUL_WITH_FLAG, UNSPEC_MAC_WITH_FLAG):
New constants.
(MACFLAG_NONE, MACFLAG_T, MACFLAG_FU, MACFLAG_TFU, MACFLAG_IS,
MACFLAG_IU, MACFLAG_W32, MACFLAG_M, MACFLAG_S2RND, MACFLAG_ISS2,
MACFLAG_IH): Likewise.
(movstricthi_1): Renamed from "*movstricthi".
(load_accumulator, load_accumulator_pair, movsi_insv, insv,
ssaddsi3, sssubsi3, ssnegsi2, signbitssi2, smaxhi3, sminhi3,
abshi2, neghi2, ssneghi2, signbitshi2, movhi_low2high,
movhi_high2high, movhi_low2low, movhi_high2low, movhiv2hi_low,
movhiv2hi_high, composev2hi, movv2hi_hi, movv2hi_hi_low,
movv2hi_hi_high, ssaddhi3, sssubhi3, ssaddv2hi3, sssubv2hi3,
addsubv2hi3, subaddv2hi3, ssaddsubv2hi3, sssubaddv2hi3,
sublohiv2hi3, subhilov2hi3, sssublohiv2hi3, sssubhilov2hi3,
addlohiv2hi3, addhilov2hi3, ssaddlohiv2hi3, ssaddhilov2hi3,
mulhisi_ll, mulhisi_lh, mulhisi_hl, mulhisi_hh, ssnegv2hi2,
ssashiftv2hi3, ssashifthi3, lshiftv2hi3, lshifthi3, packv2hi,
flag_mulhi, flag_mulhisi_parts, flag_machi, flag_machi_acconly,
flag_macinithi, flag_macinit1hi, flag_mulv2hi, flag_mulv2hi_parts,
flag_macv2hi_parts, flag_macv2hi_parts_acconly,
flag_macinitv2hi_parts, flag_macinit1v2hi_parts): New patterns.
From-SVN: r113245
2006-04-25 13:49:27 +02:00
|
|
|
|
;; Multiplications.
|
|
|
|
|
|
|
|
|
|
;; The Blackfin allows a lot of different options, and we need many patterns to
|
|
|
|
|
;; cover most of the hardware's abilities.
|
|
|
|
|
;; There are a few simple patterns using MULT rtx codes, but most of them use
|
|
|
|
|
;; an unspec with a const_int operand that determines which flag to use in the
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;; instruction.
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;; There are variants for single and parallel multiplications.
|
2007-02-04 17:40:30 +01:00
|
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|
|
;; There are variants which just use 16-bit lowparts as inputs, and variants
|
genmodes.c (make_vector_mode): Allow making VECTOR_MODE_INT of a MODE_PARTIAL_INT mode.
* genmodes.c (make_vector_mode): Allow making VECTOR_MODE_INT of a
MODE_PARTIAL_INT mode.
* config/bfin/bfin-modes.def: Add V2PDI and V2SI.
* config/bfin/bfin.c (print_operand): Add macflag and mac/msu modifiers
for CONST_INTs.
(hard_regno_mode_ok): V2PDImode is ok for accumulators.
* config/bfin/bfin.h (CLASS_MAX_NREGS, HARD_REGNO_NREGS): Handle
V2PDImode.
* config/bfin/predicates.md (const01_operand, vec_shift_operand):
New predicates.
* config/bfin/bfin.md (UNSPEC_MUL_WITH_FLAG, UNSPEC_MAC_WITH_FLAG):
New constants.
(MACFLAG_NONE, MACFLAG_T, MACFLAG_FU, MACFLAG_TFU, MACFLAG_IS,
MACFLAG_IU, MACFLAG_W32, MACFLAG_M, MACFLAG_S2RND, MACFLAG_ISS2,
MACFLAG_IH): Likewise.
(movstricthi_1): Renamed from "*movstricthi".
(load_accumulator, load_accumulator_pair, movsi_insv, insv,
ssaddsi3, sssubsi3, ssnegsi2, signbitssi2, smaxhi3, sminhi3,
abshi2, neghi2, ssneghi2, signbitshi2, movhi_low2high,
movhi_high2high, movhi_low2low, movhi_high2low, movhiv2hi_low,
movhiv2hi_high, composev2hi, movv2hi_hi, movv2hi_hi_low,
movv2hi_hi_high, ssaddhi3, sssubhi3, ssaddv2hi3, sssubv2hi3,
addsubv2hi3, subaddv2hi3, ssaddsubv2hi3, sssubaddv2hi3,
sublohiv2hi3, subhilov2hi3, sssublohiv2hi3, sssubhilov2hi3,
addlohiv2hi3, addhilov2hi3, ssaddlohiv2hi3, ssaddhilov2hi3,
mulhisi_ll, mulhisi_lh, mulhisi_hl, mulhisi_hh, ssnegv2hi2,
ssashiftv2hi3, ssashifthi3, lshiftv2hi3, lshifthi3, packv2hi,
flag_mulhi, flag_mulhisi_parts, flag_machi, flag_machi_acconly,
flag_macinithi, flag_macinit1hi, flag_mulv2hi, flag_mulv2hi_parts,
flag_macv2hi_parts, flag_macv2hi_parts_acconly,
flag_macinitv2hi_parts, flag_macinit1v2hi_parts): New patterns.
From-SVN: r113245
2006-04-25 13:49:27 +02:00
|
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;; which allow the user to choose just which halves to use as input values.
|
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;; There are variants which set D registers, variants which set accumulators,
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|
;; variants which set both, some of them optionally using the accumulators as
|
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;; inputs for multiply-accumulate operations.
|
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(define_insn "flag_mulhi"
|
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[(set (match_operand:HI 0 "register_operand" "=d")
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(unspec:HI [(match_operand:HI 1 "register_operand" "d")
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(match_operand:HI 2 "register_operand" "d")
|
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(match_operand 3 "const_int_operand" "n")]
|
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|
UNSPEC_MUL_WITH_FLAG))]
|
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|
""
|
rtlanal.c (note_uses): Deal with SEQUENCEs.
* rtlanal.c (note_uses): Deal with SEQUENCEs.
* config/bfin/bfin.c: Include "timevar.h".
(bfin_flag_schedule_insns2, splitting_for_sched,
bfin_flag_var_tracking): New variables.
(print_operand): Handle '%!'.
(override_options): Disable normal sched2 pass, instead set
bfin_flag_schedule_insns2 for reorg to handle it.
(output_file_start): Likewise for var-tracking.
(bfin_optimize_loop): Take some care not to stumble over SEQUENCEs.
(gen_one_bundle, bfin_gen_bundles, type_for_anomaly, trapping_loads_p):
New functions.
(bfin_reorg): Do second scheduling pass here, and call
bfin_gen_bundles. Use type_for_anomaly and trapping_loads_p instead
of examining insns directly. If bfin_flag_var_tracking, call
var-tracking pass when done with everything else.
* config/bfin/bfin.h (PRINT_OPERAND_PUNCT_VALID_P): '!' is valid.
* config/bfin/bfin.md (UNSPEC_32BIT): New constant.
(movsi_insn32): New pattern, with two new splits to create it
before the final scheduling pass.
(neghi2): Not a dsp32 insn, rather alu0.
(movbi, pushsi_insn, popsi_insn, movsi_insn, movv2hi_insn, movhi_insn,
movqi_insn, movsf_insn, movsi_insv, extendhisi2, zero_extendhisi2,
extendqihi2, extendqisi2, zero_extendqihi2, zero_extendqisi2,
mulhisi3, umulhisi3, ssadsi3, sssubsi3, smaxsi3, sminsi3, abssi2,
ssnegsi2, signbitssi2, smaxhi3, sminhi3, abshi2, ssneghi2, signbitshi2,
movhi_low2high, movhi_high2high, movhi_low2low, movhi_high2low,
movhiv2hi_low, movhiv2hi_high, composev2hi, packv2hi, movv2hi_hi,
ssaddhi3, sssubhi3, addv2hi3, ssaddv2hi3, subv2hi3, sssubv2hi3,
addsubv2hi3, subaddv2hi3, ssaddsubv2hi3, sssubaddv2hi3, sublohiv2hi3,
subhilov2hi3, sssublohiv2hi3, sssubhilov2hi3, addlohiv2hi3,
addhilov2hi3, ssaddlohiv2hi3, ssaddhilov2hi3, sminv2hi3, smaxv2hi3,
flag_mulhi, flag_mulhisi, flag_mulhisi_parts, flag_machi,
flag_machi_acconly, flag_macinithi, flag_macinit1hi, mulv2hi3,
flag_mulv2hi, flag_mulv2hi_parts, flag_macv2hi_parts,
flag_macv2hi_parts_acconly, flag_macinitv2hi_parts,
flag_macinit1v2hi_parts, mulhisi_ll, mulhisi_lh, mulhisi_hl,
mulhisi_hh, ssnegv2hi2, absv2hi2, ssashiftv2hi3, ssashifthi3,
lshiftv2hi3, lshifthi3): Use '%!' to terminate all dsp32/load/store
variants instead of ';'.
(ror_one, rol_one): Likewise. Make them dsp32 insns.
(ashlsi3_insn, ashrsi3, lshrsi3): Add dsp32 variants.
(align8, align16, align24): Now named patterns; also using '%!'.
(mnop): New insn.
From-SVN: r119534
2006-12-05 09:49:56 +01:00
|
|
|
|
"%h0 = %h1 * %h2 %M3%!"
|
genmodes.c (make_vector_mode): Allow making VECTOR_MODE_INT of a MODE_PARTIAL_INT mode.
* genmodes.c (make_vector_mode): Allow making VECTOR_MODE_INT of a
MODE_PARTIAL_INT mode.
* config/bfin/bfin-modes.def: Add V2PDI and V2SI.
* config/bfin/bfin.c (print_operand): Add macflag and mac/msu modifiers
for CONST_INTs.
(hard_regno_mode_ok): V2PDImode is ok for accumulators.
* config/bfin/bfin.h (CLASS_MAX_NREGS, HARD_REGNO_NREGS): Handle
V2PDImode.
* config/bfin/predicates.md (const01_operand, vec_shift_operand):
New predicates.
* config/bfin/bfin.md (UNSPEC_MUL_WITH_FLAG, UNSPEC_MAC_WITH_FLAG):
New constants.
(MACFLAG_NONE, MACFLAG_T, MACFLAG_FU, MACFLAG_TFU, MACFLAG_IS,
MACFLAG_IU, MACFLAG_W32, MACFLAG_M, MACFLAG_S2RND, MACFLAG_ISS2,
MACFLAG_IH): Likewise.
(movstricthi_1): Renamed from "*movstricthi".
(load_accumulator, load_accumulator_pair, movsi_insv, insv,
ssaddsi3, sssubsi3, ssnegsi2, signbitssi2, smaxhi3, sminhi3,
abshi2, neghi2, ssneghi2, signbitshi2, movhi_low2high,
movhi_high2high, movhi_low2low, movhi_high2low, movhiv2hi_low,
movhiv2hi_high, composev2hi, movv2hi_hi, movv2hi_hi_low,
movv2hi_hi_high, ssaddhi3, sssubhi3, ssaddv2hi3, sssubv2hi3,
addsubv2hi3, subaddv2hi3, ssaddsubv2hi3, sssubaddv2hi3,
sublohiv2hi3, subhilov2hi3, sssublohiv2hi3, sssubhilov2hi3,
addlohiv2hi3, addhilov2hi3, ssaddlohiv2hi3, ssaddhilov2hi3,
mulhisi_ll, mulhisi_lh, mulhisi_hl, mulhisi_hh, ssnegv2hi2,
ssashiftv2hi3, ssashifthi3, lshiftv2hi3, lshifthi3, packv2hi,
flag_mulhi, flag_mulhisi_parts, flag_machi, flag_machi_acconly,
flag_macinithi, flag_macinit1hi, flag_mulv2hi, flag_mulv2hi_parts,
flag_macv2hi_parts, flag_macv2hi_parts_acconly,
flag_macinitv2hi_parts, flag_macinit1v2hi_parts): New patterns.
From-SVN: r113245
2006-04-25 13:49:27 +02:00
|
|
|
|
[(set_attr "type" "dsp32")])
|
|
|
|
|
|
From Jie Zhang:
* config/bfin/bfin.c (enum bfin_builtins): Add BFIN_BUILTIN_ONES,
BFIN_BUILTIN_CPLX_MUL_16_S40, BFIN_BUILTIN_CPLX_MAC_16_S40,
BFIN_BUILTIN_CPLX_MSU_16_S40, and BFIN_BUILTIN_CPLX_SQU.
(bfin_init_builtins): Initialize __builtin_bfin_ones,
__builtin_bfin_min_fr1x16, __builtin_bfin_max_fr1x16,
__builtin_bfin_min_fr1x32, __builtin_bfin_max_fr1x32,
__builtin_bfin_cmplx_add, __builtin_bfin_cmplx_sub,
__builtin_bfin_cmplx_mul_s40, __builtin_bfin_cmplx_mac_s40,
__builtin_bfin_cmplx_msu_s40 and __builtin_bfin_csqu_fr16.
(bdesc_1arg): Add __builtin_bfin_ones.
(bfin_expand_builtin): Expand __builtin_bfin_cmplx_mul_s40,
__builtin_bfin_cmplx_mac_s40, __builtin_bfin_cmplx_msu_s40,
and __builtin_bfin_csqu_fr16.
* config/bfin/bfin.md (UNSPEC_ONES): New constant.
(ones): New define_insn.
(ssaddhi3_parts): New define_insn.
(sssubhi3_parts): New define_insn.
(flag_mulhi_parts): New define_insn.
From-SVN: r128475
2007-09-13 20:27:28 +02:00
|
|
|
|
(define_insn "flag_mulhi_parts"
|
bfin.md (sp_or_sm, [...]): New macro.
gcc/
* config/bfin/bfin.md (sp_or_sm, spm_string, spm_name): New macro.
(ss<spm_name>hi3, ss<spm_name>hi3_parts, ss<spm_name>hi3_low_parts,
ss<spm_name_hi3_high_parts): New patterns, replacing ssaddhi3, ssubhi3,
ssaddhi3_parts and sssubhi3_parts.
(flag_mulhi3_parts): Produce a HImode output rather than trying to set
a VEC_SELECT.
* config/bfin/bfin.c (bfin_expand_builtin, case BFIN_BUILTIN_CPLX_SQU):
Adjust accordingly.
gcc/testsuite/
* gcc.target/bfin/20090411-1.c: New test.
From-SVN: r146929
2009-04-29 10:41:32 +02:00
|
|
|
|
[(set (match_operand:HI 0 "register_operand" "=d")
|
From Jie Zhang:
* config/bfin/bfin.c (enum bfin_builtins): Add BFIN_BUILTIN_ONES,
BFIN_BUILTIN_CPLX_MUL_16_S40, BFIN_BUILTIN_CPLX_MAC_16_S40,
BFIN_BUILTIN_CPLX_MSU_16_S40, and BFIN_BUILTIN_CPLX_SQU.
(bfin_init_builtins): Initialize __builtin_bfin_ones,
__builtin_bfin_min_fr1x16, __builtin_bfin_max_fr1x16,
__builtin_bfin_min_fr1x32, __builtin_bfin_max_fr1x32,
__builtin_bfin_cmplx_add, __builtin_bfin_cmplx_sub,
__builtin_bfin_cmplx_mul_s40, __builtin_bfin_cmplx_mac_s40,
__builtin_bfin_cmplx_msu_s40 and __builtin_bfin_csqu_fr16.
(bdesc_1arg): Add __builtin_bfin_ones.
(bfin_expand_builtin): Expand __builtin_bfin_cmplx_mul_s40,
__builtin_bfin_cmplx_mac_s40, __builtin_bfin_cmplx_msu_s40,
and __builtin_bfin_csqu_fr16.
* config/bfin/bfin.md (UNSPEC_ONES): New constant.
(ones): New define_insn.
(ssaddhi3_parts): New define_insn.
(sssubhi3_parts): New define_insn.
(flag_mulhi_parts): New define_insn.
From-SVN: r128475
2007-09-13 20:27:28 +02:00
|
|
|
|
(unspec:HI [(vec_select:HI
|
|
|
|
|
(match_operand:V2HI 1 "register_operand" "d")
|
bfin.md (sp_or_sm, [...]): New macro.
gcc/
* config/bfin/bfin.md (sp_or_sm, spm_string, spm_name): New macro.
(ss<spm_name>hi3, ss<spm_name>hi3_parts, ss<spm_name>hi3_low_parts,
ss<spm_name_hi3_high_parts): New patterns, replacing ssaddhi3, ssubhi3,
ssaddhi3_parts and sssubhi3_parts.
(flag_mulhi3_parts): Produce a HImode output rather than trying to set
a VEC_SELECT.
* config/bfin/bfin.c (bfin_expand_builtin, case BFIN_BUILTIN_CPLX_SQU):
Adjust accordingly.
gcc/testsuite/
* gcc.target/bfin/20090411-1.c: New test.
From-SVN: r146929
2009-04-29 10:41:32 +02:00
|
|
|
|
(parallel [(match_operand 3 "const01_operand" "P0P1")]))
|
From Jie Zhang:
* config/bfin/bfin.c (enum bfin_builtins): Add BFIN_BUILTIN_ONES,
BFIN_BUILTIN_CPLX_MUL_16_S40, BFIN_BUILTIN_CPLX_MAC_16_S40,
BFIN_BUILTIN_CPLX_MSU_16_S40, and BFIN_BUILTIN_CPLX_SQU.
(bfin_init_builtins): Initialize __builtin_bfin_ones,
__builtin_bfin_min_fr1x16, __builtin_bfin_max_fr1x16,
__builtin_bfin_min_fr1x32, __builtin_bfin_max_fr1x32,
__builtin_bfin_cmplx_add, __builtin_bfin_cmplx_sub,
__builtin_bfin_cmplx_mul_s40, __builtin_bfin_cmplx_mac_s40,
__builtin_bfin_cmplx_msu_s40 and __builtin_bfin_csqu_fr16.
(bdesc_1arg): Add __builtin_bfin_ones.
(bfin_expand_builtin): Expand __builtin_bfin_cmplx_mul_s40,
__builtin_bfin_cmplx_mac_s40, __builtin_bfin_cmplx_msu_s40,
and __builtin_bfin_csqu_fr16.
* config/bfin/bfin.md (UNSPEC_ONES): New constant.
(ones): New define_insn.
(ssaddhi3_parts): New define_insn.
(sssubhi3_parts): New define_insn.
(flag_mulhi_parts): New define_insn.
From-SVN: r128475
2007-09-13 20:27:28 +02:00
|
|
|
|
(vec_select:HI
|
|
|
|
|
(match_operand:V2HI 2 "register_operand" "d")
|
bfin.md (sp_or_sm, [...]): New macro.
gcc/
* config/bfin/bfin.md (sp_or_sm, spm_string, spm_name): New macro.
(ss<spm_name>hi3, ss<spm_name>hi3_parts, ss<spm_name>hi3_low_parts,
ss<spm_name_hi3_high_parts): New patterns, replacing ssaddhi3, ssubhi3,
ssaddhi3_parts and sssubhi3_parts.
(flag_mulhi3_parts): Produce a HImode output rather than trying to set
a VEC_SELECT.
* config/bfin/bfin.c (bfin_expand_builtin, case BFIN_BUILTIN_CPLX_SQU):
Adjust accordingly.
gcc/testsuite/
* gcc.target/bfin/20090411-1.c: New test.
From-SVN: r146929
2009-04-29 10:41:32 +02:00
|
|
|
|
(parallel [(match_operand 4 "const01_operand" "P0P1")]))
|
|
|
|
|
(match_operand 5 "const_int_operand" "n")]
|
From Jie Zhang:
* config/bfin/bfin.c (enum bfin_builtins): Add BFIN_BUILTIN_ONES,
BFIN_BUILTIN_CPLX_MUL_16_S40, BFIN_BUILTIN_CPLX_MAC_16_S40,
BFIN_BUILTIN_CPLX_MSU_16_S40, and BFIN_BUILTIN_CPLX_SQU.
(bfin_init_builtins): Initialize __builtin_bfin_ones,
__builtin_bfin_min_fr1x16, __builtin_bfin_max_fr1x16,
__builtin_bfin_min_fr1x32, __builtin_bfin_max_fr1x32,
__builtin_bfin_cmplx_add, __builtin_bfin_cmplx_sub,
__builtin_bfin_cmplx_mul_s40, __builtin_bfin_cmplx_mac_s40,
__builtin_bfin_cmplx_msu_s40 and __builtin_bfin_csqu_fr16.
(bdesc_1arg): Add __builtin_bfin_ones.
(bfin_expand_builtin): Expand __builtin_bfin_cmplx_mul_s40,
__builtin_bfin_cmplx_mac_s40, __builtin_bfin_cmplx_msu_s40,
and __builtin_bfin_csqu_fr16.
* config/bfin/bfin.md (UNSPEC_ONES): New constant.
(ones): New define_insn.
(ssaddhi3_parts): New define_insn.
(sssubhi3_parts): New define_insn.
(flag_mulhi_parts): New define_insn.
From-SVN: r128475
2007-09-13 20:27:28 +02:00
|
|
|
|
UNSPEC_MUL_WITH_FLAG))]
|
|
|
|
|
""
|
|
|
|
|
{
|
|
|
|
|
const char *templates[] = {
|
bfin.md (sp_or_sm, [...]): New macro.
gcc/
* config/bfin/bfin.md (sp_or_sm, spm_string, spm_name): New macro.
(ss<spm_name>hi3, ss<spm_name>hi3_parts, ss<spm_name>hi3_low_parts,
ss<spm_name_hi3_high_parts): New patterns, replacing ssaddhi3, ssubhi3,
ssaddhi3_parts and sssubhi3_parts.
(flag_mulhi3_parts): Produce a HImode output rather than trying to set
a VEC_SELECT.
* config/bfin/bfin.c (bfin_expand_builtin, case BFIN_BUILTIN_CPLX_SQU):
Adjust accordingly.
gcc/testsuite/
* gcc.target/bfin/20090411-1.c: New test.
From-SVN: r146929
2009-04-29 10:41:32 +02:00
|
|
|
|
"%h0 = %h1 * %h2 %M5%!",
|
|
|
|
|
"%h0 = %d1 * %h2 %M5%!",
|
|
|
|
|
"%h0 = %h1 * %d2 %M5%!",
|
|
|
|
|
"%h0 = %d1 * %d2 %M5%!" };
|
|
|
|
|
int alt = INTVAL (operands[3]) + (INTVAL (operands[4]) << 1);
|
From Jie Zhang:
* config/bfin/bfin.c (enum bfin_builtins): Add BFIN_BUILTIN_ONES,
BFIN_BUILTIN_CPLX_MUL_16_S40, BFIN_BUILTIN_CPLX_MAC_16_S40,
BFIN_BUILTIN_CPLX_MSU_16_S40, and BFIN_BUILTIN_CPLX_SQU.
(bfin_init_builtins): Initialize __builtin_bfin_ones,
__builtin_bfin_min_fr1x16, __builtin_bfin_max_fr1x16,
__builtin_bfin_min_fr1x32, __builtin_bfin_max_fr1x32,
__builtin_bfin_cmplx_add, __builtin_bfin_cmplx_sub,
__builtin_bfin_cmplx_mul_s40, __builtin_bfin_cmplx_mac_s40,
__builtin_bfin_cmplx_msu_s40 and __builtin_bfin_csqu_fr16.
(bdesc_1arg): Add __builtin_bfin_ones.
(bfin_expand_builtin): Expand __builtin_bfin_cmplx_mul_s40,
__builtin_bfin_cmplx_mac_s40, __builtin_bfin_cmplx_msu_s40,
and __builtin_bfin_csqu_fr16.
* config/bfin/bfin.md (UNSPEC_ONES): New constant.
(ones): New define_insn.
(ssaddhi3_parts): New define_insn.
(sssubhi3_parts): New define_insn.
(flag_mulhi_parts): New define_insn.
From-SVN: r128475
2007-09-13 20:27:28 +02:00
|
|
|
|
return templates[alt];
|
|
|
|
|
}
|
|
|
|
|
[(set_attr "type" "dsp32")])
|
|
|
|
|
|
genmodes.c (make_vector_mode): Allow making VECTOR_MODE_INT of a MODE_PARTIAL_INT mode.
* genmodes.c (make_vector_mode): Allow making VECTOR_MODE_INT of a
MODE_PARTIAL_INT mode.
* config/bfin/bfin-modes.def: Add V2PDI and V2SI.
* config/bfin/bfin.c (print_operand): Add macflag and mac/msu modifiers
for CONST_INTs.
(hard_regno_mode_ok): V2PDImode is ok for accumulators.
* config/bfin/bfin.h (CLASS_MAX_NREGS, HARD_REGNO_NREGS): Handle
V2PDImode.
* config/bfin/predicates.md (const01_operand, vec_shift_operand):
New predicates.
* config/bfin/bfin.md (UNSPEC_MUL_WITH_FLAG, UNSPEC_MAC_WITH_FLAG):
New constants.
(MACFLAG_NONE, MACFLAG_T, MACFLAG_FU, MACFLAG_TFU, MACFLAG_IS,
MACFLAG_IU, MACFLAG_W32, MACFLAG_M, MACFLAG_S2RND, MACFLAG_ISS2,
MACFLAG_IH): Likewise.
(movstricthi_1): Renamed from "*movstricthi".
(load_accumulator, load_accumulator_pair, movsi_insv, insv,
ssaddsi3, sssubsi3, ssnegsi2, signbitssi2, smaxhi3, sminhi3,
abshi2, neghi2, ssneghi2, signbitshi2, movhi_low2high,
movhi_high2high, movhi_low2low, movhi_high2low, movhiv2hi_low,
movhiv2hi_high, composev2hi, movv2hi_hi, movv2hi_hi_low,
movv2hi_hi_high, ssaddhi3, sssubhi3, ssaddv2hi3, sssubv2hi3,
addsubv2hi3, subaddv2hi3, ssaddsubv2hi3, sssubaddv2hi3,
sublohiv2hi3, subhilov2hi3, sssublohiv2hi3, sssubhilov2hi3,
addlohiv2hi3, addhilov2hi3, ssaddlohiv2hi3, ssaddhilov2hi3,
mulhisi_ll, mulhisi_lh, mulhisi_hl, mulhisi_hh, ssnegv2hi2,
ssashiftv2hi3, ssashifthi3, lshiftv2hi3, lshifthi3, packv2hi,
flag_mulhi, flag_mulhisi_parts, flag_machi, flag_machi_acconly,
flag_macinithi, flag_macinit1hi, flag_mulv2hi, flag_mulv2hi_parts,
flag_macv2hi_parts, flag_macv2hi_parts_acconly,
flag_macinitv2hi_parts, flag_macinit1v2hi_parts): New patterns.
From-SVN: r113245
2006-04-25 13:49:27 +02:00
|
|
|
|
(define_insn "flag_mulhisi"
|
|
|
|
|
[(set (match_operand:SI 0 "register_operand" "=d")
|
|
|
|
|
(unspec:SI [(match_operand:HI 1 "register_operand" "d")
|
|
|
|
|
(match_operand:HI 2 "register_operand" "d")
|
|
|
|
|
(match_operand 3 "const_int_operand" "n")]
|
|
|
|
|
UNSPEC_MUL_WITH_FLAG))]
|
|
|
|
|
""
|
rtlanal.c (note_uses): Deal with SEQUENCEs.
* rtlanal.c (note_uses): Deal with SEQUENCEs.
* config/bfin/bfin.c: Include "timevar.h".
(bfin_flag_schedule_insns2, splitting_for_sched,
bfin_flag_var_tracking): New variables.
(print_operand): Handle '%!'.
(override_options): Disable normal sched2 pass, instead set
bfin_flag_schedule_insns2 for reorg to handle it.
(output_file_start): Likewise for var-tracking.
(bfin_optimize_loop): Take some care not to stumble over SEQUENCEs.
(gen_one_bundle, bfin_gen_bundles, type_for_anomaly, trapping_loads_p):
New functions.
(bfin_reorg): Do second scheduling pass here, and call
bfin_gen_bundles. Use type_for_anomaly and trapping_loads_p instead
of examining insns directly. If bfin_flag_var_tracking, call
var-tracking pass when done with everything else.
* config/bfin/bfin.h (PRINT_OPERAND_PUNCT_VALID_P): '!' is valid.
* config/bfin/bfin.md (UNSPEC_32BIT): New constant.
(movsi_insn32): New pattern, with two new splits to create it
before the final scheduling pass.
(neghi2): Not a dsp32 insn, rather alu0.
(movbi, pushsi_insn, popsi_insn, movsi_insn, movv2hi_insn, movhi_insn,
movqi_insn, movsf_insn, movsi_insv, extendhisi2, zero_extendhisi2,
extendqihi2, extendqisi2, zero_extendqihi2, zero_extendqisi2,
mulhisi3, umulhisi3, ssadsi3, sssubsi3, smaxsi3, sminsi3, abssi2,
ssnegsi2, signbitssi2, smaxhi3, sminhi3, abshi2, ssneghi2, signbitshi2,
movhi_low2high, movhi_high2high, movhi_low2low, movhi_high2low,
movhiv2hi_low, movhiv2hi_high, composev2hi, packv2hi, movv2hi_hi,
ssaddhi3, sssubhi3, addv2hi3, ssaddv2hi3, subv2hi3, sssubv2hi3,
addsubv2hi3, subaddv2hi3, ssaddsubv2hi3, sssubaddv2hi3, sublohiv2hi3,
subhilov2hi3, sssublohiv2hi3, sssubhilov2hi3, addlohiv2hi3,
addhilov2hi3, ssaddlohiv2hi3, ssaddhilov2hi3, sminv2hi3, smaxv2hi3,
flag_mulhi, flag_mulhisi, flag_mulhisi_parts, flag_machi,
flag_machi_acconly, flag_macinithi, flag_macinit1hi, mulv2hi3,
flag_mulv2hi, flag_mulv2hi_parts, flag_macv2hi_parts,
flag_macv2hi_parts_acconly, flag_macinitv2hi_parts,
flag_macinit1v2hi_parts, mulhisi_ll, mulhisi_lh, mulhisi_hl,
mulhisi_hh, ssnegv2hi2, absv2hi2, ssashiftv2hi3, ssashifthi3,
lshiftv2hi3, lshifthi3): Use '%!' to terminate all dsp32/load/store
variants instead of ';'.
(ror_one, rol_one): Likewise. Make them dsp32 insns.
(ashlsi3_insn, ashrsi3, lshrsi3): Add dsp32 variants.
(align8, align16, align24): Now named patterns; also using '%!'.
(mnop): New insn.
From-SVN: r119534
2006-12-05 09:49:56 +01:00
|
|
|
|
"%0 = %h1 * %h2 %M3%!"
|
genmodes.c (make_vector_mode): Allow making VECTOR_MODE_INT of a MODE_PARTIAL_INT mode.
* genmodes.c (make_vector_mode): Allow making VECTOR_MODE_INT of a
MODE_PARTIAL_INT mode.
* config/bfin/bfin-modes.def: Add V2PDI and V2SI.
* config/bfin/bfin.c (print_operand): Add macflag and mac/msu modifiers
for CONST_INTs.
(hard_regno_mode_ok): V2PDImode is ok for accumulators.
* config/bfin/bfin.h (CLASS_MAX_NREGS, HARD_REGNO_NREGS): Handle
V2PDImode.
* config/bfin/predicates.md (const01_operand, vec_shift_operand):
New predicates.
* config/bfin/bfin.md (UNSPEC_MUL_WITH_FLAG, UNSPEC_MAC_WITH_FLAG):
New constants.
(MACFLAG_NONE, MACFLAG_T, MACFLAG_FU, MACFLAG_TFU, MACFLAG_IS,
MACFLAG_IU, MACFLAG_W32, MACFLAG_M, MACFLAG_S2RND, MACFLAG_ISS2,
MACFLAG_IH): Likewise.
(movstricthi_1): Renamed from "*movstricthi".
(load_accumulator, load_accumulator_pair, movsi_insv, insv,
ssaddsi3, sssubsi3, ssnegsi2, signbitssi2, smaxhi3, sminhi3,
abshi2, neghi2, ssneghi2, signbitshi2, movhi_low2high,
movhi_high2high, movhi_low2low, movhi_high2low, movhiv2hi_low,
movhiv2hi_high, composev2hi, movv2hi_hi, movv2hi_hi_low,
movv2hi_hi_high, ssaddhi3, sssubhi3, ssaddv2hi3, sssubv2hi3,
addsubv2hi3, subaddv2hi3, ssaddsubv2hi3, sssubaddv2hi3,
sublohiv2hi3, subhilov2hi3, sssublohiv2hi3, sssubhilov2hi3,
addlohiv2hi3, addhilov2hi3, ssaddlohiv2hi3, ssaddhilov2hi3,
mulhisi_ll, mulhisi_lh, mulhisi_hl, mulhisi_hh, ssnegv2hi2,
ssashiftv2hi3, ssashifthi3, lshiftv2hi3, lshifthi3, packv2hi,
flag_mulhi, flag_mulhisi_parts, flag_machi, flag_machi_acconly,
flag_macinithi, flag_macinit1hi, flag_mulv2hi, flag_mulv2hi_parts,
flag_macv2hi_parts, flag_macv2hi_parts_acconly,
flag_macinitv2hi_parts, flag_macinit1v2hi_parts): New patterns.
From-SVN: r113245
2006-04-25 13:49:27 +02:00
|
|
|
|
[(set_attr "type" "dsp32")])
|
|
|
|
|
|
|
|
|
|
(define_insn "flag_mulhisi_parts"
|
|
|
|
|
[(set (match_operand:SI 0 "register_operand" "=d")
|
|
|
|
|
(unspec:SI [(vec_select:HI
|
|
|
|
|
(match_operand:V2HI 1 "register_operand" "d")
|
2006-05-04 13:03:41 +02:00
|
|
|
|
(parallel [(match_operand 3 "const01_operand" "P0P1")]))
|
genmodes.c (make_vector_mode): Allow making VECTOR_MODE_INT of a MODE_PARTIAL_INT mode.
* genmodes.c (make_vector_mode): Allow making VECTOR_MODE_INT of a
MODE_PARTIAL_INT mode.
* config/bfin/bfin-modes.def: Add V2PDI and V2SI.
* config/bfin/bfin.c (print_operand): Add macflag and mac/msu modifiers
for CONST_INTs.
(hard_regno_mode_ok): V2PDImode is ok for accumulators.
* config/bfin/bfin.h (CLASS_MAX_NREGS, HARD_REGNO_NREGS): Handle
V2PDImode.
* config/bfin/predicates.md (const01_operand, vec_shift_operand):
New predicates.
* config/bfin/bfin.md (UNSPEC_MUL_WITH_FLAG, UNSPEC_MAC_WITH_FLAG):
New constants.
(MACFLAG_NONE, MACFLAG_T, MACFLAG_FU, MACFLAG_TFU, MACFLAG_IS,
MACFLAG_IU, MACFLAG_W32, MACFLAG_M, MACFLAG_S2RND, MACFLAG_ISS2,
MACFLAG_IH): Likewise.
(movstricthi_1): Renamed from "*movstricthi".
(load_accumulator, load_accumulator_pair, movsi_insv, insv,
ssaddsi3, sssubsi3, ssnegsi2, signbitssi2, smaxhi3, sminhi3,
abshi2, neghi2, ssneghi2, signbitshi2, movhi_low2high,
movhi_high2high, movhi_low2low, movhi_high2low, movhiv2hi_low,
movhiv2hi_high, composev2hi, movv2hi_hi, movv2hi_hi_low,
movv2hi_hi_high, ssaddhi3, sssubhi3, ssaddv2hi3, sssubv2hi3,
addsubv2hi3, subaddv2hi3, ssaddsubv2hi3, sssubaddv2hi3,
sublohiv2hi3, subhilov2hi3, sssublohiv2hi3, sssubhilov2hi3,
addlohiv2hi3, addhilov2hi3, ssaddlohiv2hi3, ssaddhilov2hi3,
mulhisi_ll, mulhisi_lh, mulhisi_hl, mulhisi_hh, ssnegv2hi2,
ssashiftv2hi3, ssashifthi3, lshiftv2hi3, lshifthi3, packv2hi,
flag_mulhi, flag_mulhisi_parts, flag_machi, flag_machi_acconly,
flag_macinithi, flag_macinit1hi, flag_mulv2hi, flag_mulv2hi_parts,
flag_macv2hi_parts, flag_macv2hi_parts_acconly,
flag_macinitv2hi_parts, flag_macinit1v2hi_parts): New patterns.
From-SVN: r113245
2006-04-25 13:49:27 +02:00
|
|
|
|
(vec_select:HI
|
|
|
|
|
(match_operand:V2HI 2 "register_operand" "d")
|
2006-05-04 13:03:41 +02:00
|
|
|
|
(parallel [(match_operand 4 "const01_operand" "P0P1")]))
|
genmodes.c (make_vector_mode): Allow making VECTOR_MODE_INT of a MODE_PARTIAL_INT mode.
* genmodes.c (make_vector_mode): Allow making VECTOR_MODE_INT of a
MODE_PARTIAL_INT mode.
* config/bfin/bfin-modes.def: Add V2PDI and V2SI.
* config/bfin/bfin.c (print_operand): Add macflag and mac/msu modifiers
for CONST_INTs.
(hard_regno_mode_ok): V2PDImode is ok for accumulators.
* config/bfin/bfin.h (CLASS_MAX_NREGS, HARD_REGNO_NREGS): Handle
V2PDImode.
* config/bfin/predicates.md (const01_operand, vec_shift_operand):
New predicates.
* config/bfin/bfin.md (UNSPEC_MUL_WITH_FLAG, UNSPEC_MAC_WITH_FLAG):
New constants.
(MACFLAG_NONE, MACFLAG_T, MACFLAG_FU, MACFLAG_TFU, MACFLAG_IS,
MACFLAG_IU, MACFLAG_W32, MACFLAG_M, MACFLAG_S2RND, MACFLAG_ISS2,
MACFLAG_IH): Likewise.
(movstricthi_1): Renamed from "*movstricthi".
(load_accumulator, load_accumulator_pair, movsi_insv, insv,
ssaddsi3, sssubsi3, ssnegsi2, signbitssi2, smaxhi3, sminhi3,
abshi2, neghi2, ssneghi2, signbitshi2, movhi_low2high,
movhi_high2high, movhi_low2low, movhi_high2low, movhiv2hi_low,
movhiv2hi_high, composev2hi, movv2hi_hi, movv2hi_hi_low,
movv2hi_hi_high, ssaddhi3, sssubhi3, ssaddv2hi3, sssubv2hi3,
addsubv2hi3, subaddv2hi3, ssaddsubv2hi3, sssubaddv2hi3,
sublohiv2hi3, subhilov2hi3, sssublohiv2hi3, sssubhilov2hi3,
addlohiv2hi3, addhilov2hi3, ssaddlohiv2hi3, ssaddhilov2hi3,
mulhisi_ll, mulhisi_lh, mulhisi_hl, mulhisi_hh, ssnegv2hi2,
ssashiftv2hi3, ssashifthi3, lshiftv2hi3, lshifthi3, packv2hi,
flag_mulhi, flag_mulhisi_parts, flag_machi, flag_machi_acconly,
flag_macinithi, flag_macinit1hi, flag_mulv2hi, flag_mulv2hi_parts,
flag_macv2hi_parts, flag_macv2hi_parts_acconly,
flag_macinitv2hi_parts, flag_macinit1v2hi_parts): New patterns.
From-SVN: r113245
2006-04-25 13:49:27 +02:00
|
|
|
|
(match_operand 5 "const_int_operand" "n")]
|
|
|
|
|
UNSPEC_MUL_WITH_FLAG))]
|
|
|
|
|
""
|
|
|
|
|
{
|
|
|
|
|
const char *templates[] = {
|
rtlanal.c (note_uses): Deal with SEQUENCEs.
* rtlanal.c (note_uses): Deal with SEQUENCEs.
* config/bfin/bfin.c: Include "timevar.h".
(bfin_flag_schedule_insns2, splitting_for_sched,
bfin_flag_var_tracking): New variables.
(print_operand): Handle '%!'.
(override_options): Disable normal sched2 pass, instead set
bfin_flag_schedule_insns2 for reorg to handle it.
(output_file_start): Likewise for var-tracking.
(bfin_optimize_loop): Take some care not to stumble over SEQUENCEs.
(gen_one_bundle, bfin_gen_bundles, type_for_anomaly, trapping_loads_p):
New functions.
(bfin_reorg): Do second scheduling pass here, and call
bfin_gen_bundles. Use type_for_anomaly and trapping_loads_p instead
of examining insns directly. If bfin_flag_var_tracking, call
var-tracking pass when done with everything else.
* config/bfin/bfin.h (PRINT_OPERAND_PUNCT_VALID_P): '!' is valid.
* config/bfin/bfin.md (UNSPEC_32BIT): New constant.
(movsi_insn32): New pattern, with two new splits to create it
before the final scheduling pass.
(neghi2): Not a dsp32 insn, rather alu0.
(movbi, pushsi_insn, popsi_insn, movsi_insn, movv2hi_insn, movhi_insn,
movqi_insn, movsf_insn, movsi_insv, extendhisi2, zero_extendhisi2,
extendqihi2, extendqisi2, zero_extendqihi2, zero_extendqisi2,
mulhisi3, umulhisi3, ssadsi3, sssubsi3, smaxsi3, sminsi3, abssi2,
ssnegsi2, signbitssi2, smaxhi3, sminhi3, abshi2, ssneghi2, signbitshi2,
movhi_low2high, movhi_high2high, movhi_low2low, movhi_high2low,
movhiv2hi_low, movhiv2hi_high, composev2hi, packv2hi, movv2hi_hi,
ssaddhi3, sssubhi3, addv2hi3, ssaddv2hi3, subv2hi3, sssubv2hi3,
addsubv2hi3, subaddv2hi3, ssaddsubv2hi3, sssubaddv2hi3, sublohiv2hi3,
subhilov2hi3, sssublohiv2hi3, sssubhilov2hi3, addlohiv2hi3,
addhilov2hi3, ssaddlohiv2hi3, ssaddhilov2hi3, sminv2hi3, smaxv2hi3,
flag_mulhi, flag_mulhisi, flag_mulhisi_parts, flag_machi,
flag_machi_acconly, flag_macinithi, flag_macinit1hi, mulv2hi3,
flag_mulv2hi, flag_mulv2hi_parts, flag_macv2hi_parts,
flag_macv2hi_parts_acconly, flag_macinitv2hi_parts,
flag_macinit1v2hi_parts, mulhisi_ll, mulhisi_lh, mulhisi_hl,
mulhisi_hh, ssnegv2hi2, absv2hi2, ssashiftv2hi3, ssashifthi3,
lshiftv2hi3, lshifthi3): Use '%!' to terminate all dsp32/load/store
variants instead of ';'.
(ror_one, rol_one): Likewise. Make them dsp32 insns.
(ashlsi3_insn, ashrsi3, lshrsi3): Add dsp32 variants.
(align8, align16, align24): Now named patterns; also using '%!'.
(mnop): New insn.
From-SVN: r119534
2006-12-05 09:49:56 +01:00
|
|
|
|
"%0 = %h1 * %h2 %M5%!",
|
|
|
|
|
"%0 = %d1 * %h2 %M5%!",
|
|
|
|
|
"%0 = %h1 * %d2 %M5%!",
|
|
|
|
|
"%0 = %d1 * %d2 %M5%!" };
|
genmodes.c (make_vector_mode): Allow making VECTOR_MODE_INT of a MODE_PARTIAL_INT mode.
* genmodes.c (make_vector_mode): Allow making VECTOR_MODE_INT of a
MODE_PARTIAL_INT mode.
* config/bfin/bfin-modes.def: Add V2PDI and V2SI.
* config/bfin/bfin.c (print_operand): Add macflag and mac/msu modifiers
for CONST_INTs.
(hard_regno_mode_ok): V2PDImode is ok for accumulators.
* config/bfin/bfin.h (CLASS_MAX_NREGS, HARD_REGNO_NREGS): Handle
V2PDImode.
* config/bfin/predicates.md (const01_operand, vec_shift_operand):
New predicates.
* config/bfin/bfin.md (UNSPEC_MUL_WITH_FLAG, UNSPEC_MAC_WITH_FLAG):
New constants.
(MACFLAG_NONE, MACFLAG_T, MACFLAG_FU, MACFLAG_TFU, MACFLAG_IS,
MACFLAG_IU, MACFLAG_W32, MACFLAG_M, MACFLAG_S2RND, MACFLAG_ISS2,
MACFLAG_IH): Likewise.
(movstricthi_1): Renamed from "*movstricthi".
(load_accumulator, load_accumulator_pair, movsi_insv, insv,
ssaddsi3, sssubsi3, ssnegsi2, signbitssi2, smaxhi3, sminhi3,
abshi2, neghi2, ssneghi2, signbitshi2, movhi_low2high,
movhi_high2high, movhi_low2low, movhi_high2low, movhiv2hi_low,
movhiv2hi_high, composev2hi, movv2hi_hi, movv2hi_hi_low,
movv2hi_hi_high, ssaddhi3, sssubhi3, ssaddv2hi3, sssubv2hi3,
addsubv2hi3, subaddv2hi3, ssaddsubv2hi3, sssubaddv2hi3,
sublohiv2hi3, subhilov2hi3, sssublohiv2hi3, sssubhilov2hi3,
addlohiv2hi3, addhilov2hi3, ssaddlohiv2hi3, ssaddhilov2hi3,
mulhisi_ll, mulhisi_lh, mulhisi_hl, mulhisi_hh, ssnegv2hi2,
ssashiftv2hi3, ssashifthi3, lshiftv2hi3, lshifthi3, packv2hi,
flag_mulhi, flag_mulhisi_parts, flag_machi, flag_machi_acconly,
flag_macinithi, flag_macinit1hi, flag_mulv2hi, flag_mulv2hi_parts,
flag_macv2hi_parts, flag_macv2hi_parts_acconly,
flag_macinitv2hi_parts, flag_macinit1v2hi_parts): New patterns.
From-SVN: r113245
2006-04-25 13:49:27 +02:00
|
|
|
|
int alt = INTVAL (operands[3]) + (INTVAL (operands[4]) << 1);
|
|
|
|
|
return templates[alt];
|
|
|
|
|
}
|
|
|
|
|
[(set_attr "type" "dsp32")])
|
|
|
|
|
|
2007-04-12 15:03:17 +02:00
|
|
|
|
;; Three alternatives here to cover all possible allocations:
|
|
|
|
|
;; 0. mac flag is usable only for accumulator 1 - use A1 and odd DREG
|
|
|
|
|
;; 1. mac flag is usable for accumulator 0 - use A0 and even DREG
|
|
|
|
|
;; 2. mac flag is usable in any accumulator - use A1 and odd DREG
|
|
|
|
|
;; Other patterns which don't have a DREG destination can collapse cases
|
|
|
|
|
;; 1 and 2 into one.
|
genmodes.c (make_vector_mode): Allow making VECTOR_MODE_INT of a MODE_PARTIAL_INT mode.
* genmodes.c (make_vector_mode): Allow making VECTOR_MODE_INT of a
MODE_PARTIAL_INT mode.
* config/bfin/bfin-modes.def: Add V2PDI and V2SI.
* config/bfin/bfin.c (print_operand): Add macflag and mac/msu modifiers
for CONST_INTs.
(hard_regno_mode_ok): V2PDImode is ok for accumulators.
* config/bfin/bfin.h (CLASS_MAX_NREGS, HARD_REGNO_NREGS): Handle
V2PDImode.
* config/bfin/predicates.md (const01_operand, vec_shift_operand):
New predicates.
* config/bfin/bfin.md (UNSPEC_MUL_WITH_FLAG, UNSPEC_MAC_WITH_FLAG):
New constants.
(MACFLAG_NONE, MACFLAG_T, MACFLAG_FU, MACFLAG_TFU, MACFLAG_IS,
MACFLAG_IU, MACFLAG_W32, MACFLAG_M, MACFLAG_S2RND, MACFLAG_ISS2,
MACFLAG_IH): Likewise.
(movstricthi_1): Renamed from "*movstricthi".
(load_accumulator, load_accumulator_pair, movsi_insv, insv,
ssaddsi3, sssubsi3, ssnegsi2, signbitssi2, smaxhi3, sminhi3,
abshi2, neghi2, ssneghi2, signbitshi2, movhi_low2high,
movhi_high2high, movhi_low2low, movhi_high2low, movhiv2hi_low,
movhiv2hi_high, composev2hi, movv2hi_hi, movv2hi_hi_low,
movv2hi_hi_high, ssaddhi3, sssubhi3, ssaddv2hi3, sssubv2hi3,
addsubv2hi3, subaddv2hi3, ssaddsubv2hi3, sssubaddv2hi3,
sublohiv2hi3, subhilov2hi3, sssublohiv2hi3, sssubhilov2hi3,
addlohiv2hi3, addhilov2hi3, ssaddlohiv2hi3, ssaddhilov2hi3,
mulhisi_ll, mulhisi_lh, mulhisi_hl, mulhisi_hh, ssnegv2hi2,
ssashiftv2hi3, ssashifthi3, lshiftv2hi3, lshifthi3, packv2hi,
flag_mulhi, flag_mulhisi_parts, flag_machi, flag_machi_acconly,
flag_macinithi, flag_macinit1hi, flag_mulv2hi, flag_mulv2hi_parts,
flag_macv2hi_parts, flag_macv2hi_parts_acconly,
flag_macinitv2hi_parts, flag_macinit1v2hi_parts): New patterns.
From-SVN: r113245
2006-04-25 13:49:27 +02:00
|
|
|
|
(define_insn "flag_machi"
|
2007-04-12 15:03:17 +02:00
|
|
|
|
[(set (match_operand:HI 0 "register_operand" "=W,D,W")
|
|
|
|
|
(unspec:HI [(match_operand:HI 2 "register_operand" "d,d,d")
|
|
|
|
|
(match_operand:HI 3 "register_operand" "d,d,d")
|
|
|
|
|
(match_operand 4 "register_operand" "1,1,1")
|
|
|
|
|
(match_operand 5 "const01_operand" "P0P1,P0P1,P0P1")
|
|
|
|
|
(match_operand 6 "const_int_operand" "PB,PA,PA")]
|
genmodes.c (make_vector_mode): Allow making VECTOR_MODE_INT of a MODE_PARTIAL_INT mode.
* genmodes.c (make_vector_mode): Allow making VECTOR_MODE_INT of a
MODE_PARTIAL_INT mode.
* config/bfin/bfin-modes.def: Add V2PDI and V2SI.
* config/bfin/bfin.c (print_operand): Add macflag and mac/msu modifiers
for CONST_INTs.
(hard_regno_mode_ok): V2PDImode is ok for accumulators.
* config/bfin/bfin.h (CLASS_MAX_NREGS, HARD_REGNO_NREGS): Handle
V2PDImode.
* config/bfin/predicates.md (const01_operand, vec_shift_operand):
New predicates.
* config/bfin/bfin.md (UNSPEC_MUL_WITH_FLAG, UNSPEC_MAC_WITH_FLAG):
New constants.
(MACFLAG_NONE, MACFLAG_T, MACFLAG_FU, MACFLAG_TFU, MACFLAG_IS,
MACFLAG_IU, MACFLAG_W32, MACFLAG_M, MACFLAG_S2RND, MACFLAG_ISS2,
MACFLAG_IH): Likewise.
(movstricthi_1): Renamed from "*movstricthi".
(load_accumulator, load_accumulator_pair, movsi_insv, insv,
ssaddsi3, sssubsi3, ssnegsi2, signbitssi2, smaxhi3, sminhi3,
abshi2, neghi2, ssneghi2, signbitshi2, movhi_low2high,
movhi_high2high, movhi_low2low, movhi_high2low, movhiv2hi_low,
movhiv2hi_high, composev2hi, movv2hi_hi, movv2hi_hi_low,
movv2hi_hi_high, ssaddhi3, sssubhi3, ssaddv2hi3, sssubv2hi3,
addsubv2hi3, subaddv2hi3, ssaddsubv2hi3, sssubaddv2hi3,
sublohiv2hi3, subhilov2hi3, sssublohiv2hi3, sssubhilov2hi3,
addlohiv2hi3, addhilov2hi3, ssaddlohiv2hi3, ssaddhilov2hi3,
mulhisi_ll, mulhisi_lh, mulhisi_hl, mulhisi_hh, ssnegv2hi2,
ssashiftv2hi3, ssashifthi3, lshiftv2hi3, lshifthi3, packv2hi,
flag_mulhi, flag_mulhisi_parts, flag_machi, flag_machi_acconly,
flag_macinithi, flag_macinit1hi, flag_mulv2hi, flag_mulv2hi_parts,
flag_macv2hi_parts, flag_macv2hi_parts_acconly,
flag_macinitv2hi_parts, flag_macinit1v2hi_parts): New patterns.
From-SVN: r113245
2006-04-25 13:49:27 +02:00
|
|
|
|
UNSPEC_MAC_WITH_FLAG))
|
2007-04-12 15:03:17 +02:00
|
|
|
|
(set (match_operand:PDI 1 "register_operand" "=B,A,B")
|
genmodes.c (make_vector_mode): Allow making VECTOR_MODE_INT of a MODE_PARTIAL_INT mode.
* genmodes.c (make_vector_mode): Allow making VECTOR_MODE_INT of a
MODE_PARTIAL_INT mode.
* config/bfin/bfin-modes.def: Add V2PDI and V2SI.
* config/bfin/bfin.c (print_operand): Add macflag and mac/msu modifiers
for CONST_INTs.
(hard_regno_mode_ok): V2PDImode is ok for accumulators.
* config/bfin/bfin.h (CLASS_MAX_NREGS, HARD_REGNO_NREGS): Handle
V2PDImode.
* config/bfin/predicates.md (const01_operand, vec_shift_operand):
New predicates.
* config/bfin/bfin.md (UNSPEC_MUL_WITH_FLAG, UNSPEC_MAC_WITH_FLAG):
New constants.
(MACFLAG_NONE, MACFLAG_T, MACFLAG_FU, MACFLAG_TFU, MACFLAG_IS,
MACFLAG_IU, MACFLAG_W32, MACFLAG_M, MACFLAG_S2RND, MACFLAG_ISS2,
MACFLAG_IH): Likewise.
(movstricthi_1): Renamed from "*movstricthi".
(load_accumulator, load_accumulator_pair, movsi_insv, insv,
ssaddsi3, sssubsi3, ssnegsi2, signbitssi2, smaxhi3, sminhi3,
abshi2, neghi2, ssneghi2, signbitshi2, movhi_low2high,
movhi_high2high, movhi_low2low, movhi_high2low, movhiv2hi_low,
movhiv2hi_high, composev2hi, movv2hi_hi, movv2hi_hi_low,
movv2hi_hi_high, ssaddhi3, sssubhi3, ssaddv2hi3, sssubv2hi3,
addsubv2hi3, subaddv2hi3, ssaddsubv2hi3, sssubaddv2hi3,
sublohiv2hi3, subhilov2hi3, sssublohiv2hi3, sssubhilov2hi3,
addlohiv2hi3, addhilov2hi3, ssaddlohiv2hi3, ssaddhilov2hi3,
mulhisi_ll, mulhisi_lh, mulhisi_hl, mulhisi_hh, ssnegv2hi2,
ssashiftv2hi3, ssashifthi3, lshiftv2hi3, lshifthi3, packv2hi,
flag_mulhi, flag_mulhisi_parts, flag_machi, flag_machi_acconly,
flag_macinithi, flag_macinit1hi, flag_mulv2hi, flag_mulv2hi_parts,
flag_macv2hi_parts, flag_macv2hi_parts_acconly,
flag_macinitv2hi_parts, flag_macinit1v2hi_parts): New patterns.
From-SVN: r113245
2006-04-25 13:49:27 +02:00
|
|
|
|
(unspec:PDI [(match_dup 1) (match_dup 2) (match_dup 3)
|
|
|
|
|
(match_dup 4) (match_dup 5)]
|
|
|
|
|
UNSPEC_MAC_WITH_FLAG))]
|
|
|
|
|
""
|
2007-04-12 15:03:17 +02:00
|
|
|
|
"%h0 = (%1 %b5 %h2 * %h3) %M6%!"
|
genmodes.c (make_vector_mode): Allow making VECTOR_MODE_INT of a MODE_PARTIAL_INT mode.
* genmodes.c (make_vector_mode): Allow making VECTOR_MODE_INT of a
MODE_PARTIAL_INT mode.
* config/bfin/bfin-modes.def: Add V2PDI and V2SI.
* config/bfin/bfin.c (print_operand): Add macflag and mac/msu modifiers
for CONST_INTs.
(hard_regno_mode_ok): V2PDImode is ok for accumulators.
* config/bfin/bfin.h (CLASS_MAX_NREGS, HARD_REGNO_NREGS): Handle
V2PDImode.
* config/bfin/predicates.md (const01_operand, vec_shift_operand):
New predicates.
* config/bfin/bfin.md (UNSPEC_MUL_WITH_FLAG, UNSPEC_MAC_WITH_FLAG):
New constants.
(MACFLAG_NONE, MACFLAG_T, MACFLAG_FU, MACFLAG_TFU, MACFLAG_IS,
MACFLAG_IU, MACFLAG_W32, MACFLAG_M, MACFLAG_S2RND, MACFLAG_ISS2,
MACFLAG_IH): Likewise.
(movstricthi_1): Renamed from "*movstricthi".
(load_accumulator, load_accumulator_pair, movsi_insv, insv,
ssaddsi3, sssubsi3, ssnegsi2, signbitssi2, smaxhi3, sminhi3,
abshi2, neghi2, ssneghi2, signbitshi2, movhi_low2high,
movhi_high2high, movhi_low2low, movhi_high2low, movhiv2hi_low,
movhiv2hi_high, composev2hi, movv2hi_hi, movv2hi_hi_low,
movv2hi_hi_high, ssaddhi3, sssubhi3, ssaddv2hi3, sssubv2hi3,
addsubv2hi3, subaddv2hi3, ssaddsubv2hi3, sssubaddv2hi3,
sublohiv2hi3, subhilov2hi3, sssublohiv2hi3, sssubhilov2hi3,
addlohiv2hi3, addhilov2hi3, ssaddlohiv2hi3, ssaddhilov2hi3,
mulhisi_ll, mulhisi_lh, mulhisi_hl, mulhisi_hh, ssnegv2hi2,
ssashiftv2hi3, ssashifthi3, lshiftv2hi3, lshifthi3, packv2hi,
flag_mulhi, flag_mulhisi_parts, flag_machi, flag_machi_acconly,
flag_macinithi, flag_macinit1hi, flag_mulv2hi, flag_mulv2hi_parts,
flag_macv2hi_parts, flag_macv2hi_parts_acconly,
flag_macinitv2hi_parts, flag_macinit1v2hi_parts): New patterns.
From-SVN: r113245
2006-04-25 13:49:27 +02:00
|
|
|
|
[(set_attr "type" "dsp32")])
|
|
|
|
|
|
|
|
|
|
(define_insn "flag_machi_acconly"
|
2007-04-12 15:03:17 +02:00
|
|
|
|
[(set (match_operand:PDI 0 "register_operand" "=B,e")
|
|
|
|
|
(unspec:PDI [(match_operand:HI 1 "register_operand" "d,d")
|
|
|
|
|
(match_operand:HI 2 "register_operand" "d,d")
|
|
|
|
|
(match_operand 3 "register_operand" "0,0")
|
|
|
|
|
(match_operand 4 "const01_operand" "P0P1,P0P1")
|
|
|
|
|
(match_operand 5 "const_int_operand" "PB,PA")]
|
genmodes.c (make_vector_mode): Allow making VECTOR_MODE_INT of a MODE_PARTIAL_INT mode.
* genmodes.c (make_vector_mode): Allow making VECTOR_MODE_INT of a
MODE_PARTIAL_INT mode.
* config/bfin/bfin-modes.def: Add V2PDI and V2SI.
* config/bfin/bfin.c (print_operand): Add macflag and mac/msu modifiers
for CONST_INTs.
(hard_regno_mode_ok): V2PDImode is ok for accumulators.
* config/bfin/bfin.h (CLASS_MAX_NREGS, HARD_REGNO_NREGS): Handle
V2PDImode.
* config/bfin/predicates.md (const01_operand, vec_shift_operand):
New predicates.
* config/bfin/bfin.md (UNSPEC_MUL_WITH_FLAG, UNSPEC_MAC_WITH_FLAG):
New constants.
(MACFLAG_NONE, MACFLAG_T, MACFLAG_FU, MACFLAG_TFU, MACFLAG_IS,
MACFLAG_IU, MACFLAG_W32, MACFLAG_M, MACFLAG_S2RND, MACFLAG_ISS2,
MACFLAG_IH): Likewise.
(movstricthi_1): Renamed from "*movstricthi".
(load_accumulator, load_accumulator_pair, movsi_insv, insv,
ssaddsi3, sssubsi3, ssnegsi2, signbitssi2, smaxhi3, sminhi3,
abshi2, neghi2, ssneghi2, signbitshi2, movhi_low2high,
movhi_high2high, movhi_low2low, movhi_high2low, movhiv2hi_low,
movhiv2hi_high, composev2hi, movv2hi_hi, movv2hi_hi_low,
movv2hi_hi_high, ssaddhi3, sssubhi3, ssaddv2hi3, sssubv2hi3,
addsubv2hi3, subaddv2hi3, ssaddsubv2hi3, sssubaddv2hi3,
sublohiv2hi3, subhilov2hi3, sssublohiv2hi3, sssubhilov2hi3,
addlohiv2hi3, addhilov2hi3, ssaddlohiv2hi3, ssaddhilov2hi3,
mulhisi_ll, mulhisi_lh, mulhisi_hl, mulhisi_hh, ssnegv2hi2,
ssashiftv2hi3, ssashifthi3, lshiftv2hi3, lshifthi3, packv2hi,
flag_mulhi, flag_mulhisi_parts, flag_machi, flag_machi_acconly,
flag_macinithi, flag_macinit1hi, flag_mulv2hi, flag_mulv2hi_parts,
flag_macv2hi_parts, flag_macv2hi_parts_acconly,
flag_macinitv2hi_parts, flag_macinit1v2hi_parts): New patterns.
From-SVN: r113245
2006-04-25 13:49:27 +02:00
|
|
|
|
UNSPEC_MAC_WITH_FLAG))]
|
|
|
|
|
""
|
2007-04-12 15:03:17 +02:00
|
|
|
|
"%0 %b4 %h1 * %h2 %M5%!"
|
|
|
|
|
[(set_attr "type" "dsp32")])
|
|
|
|
|
|
|
|
|
|
(define_insn "flag_machi_parts_acconly"
|
|
|
|
|
[(set (match_operand:PDI 0 "register_operand" "=B,e")
|
|
|
|
|
(unspec:PDI [(vec_select:HI
|
|
|
|
|
(match_operand:V2HI 1 "register_operand" "d,d")
|
|
|
|
|
(parallel [(match_operand 3 "const01_operand" "P0P1,P0P1")]))
|
|
|
|
|
(vec_select:HI
|
|
|
|
|
(match_operand:V2HI 2 "register_operand" "d,d")
|
|
|
|
|
(parallel [(match_operand 4 "const01_operand" "P0P1,P0P1")]))
|
|
|
|
|
(match_operand:PDI 5 "register_operand" "0,0")
|
|
|
|
|
(match_operand 6 "const01_operand" "P0P1,P0P1")
|
|
|
|
|
(match_operand 7 "const_int_operand" "PB,PA")]
|
|
|
|
|
UNSPEC_MAC_WITH_FLAG))]
|
|
|
|
|
""
|
|
|
|
|
{
|
|
|
|
|
const char *templates[] = {
|
|
|
|
|
"%0 %b6 %h1 * %h2 %M7%!",
|
|
|
|
|
"%0 %b6 %d1 * %h2 %M7%!",
|
|
|
|
|
"%0 %b6 %h1 * %d2 %M7%!",
|
|
|
|
|
"%0 %b6 %d1 * %d2 %M7%!"
|
|
|
|
|
};
|
|
|
|
|
int alt = INTVAL (operands[3]) + (INTVAL (operands[4]) << 1);
|
|
|
|
|
return templates[alt];
|
|
|
|
|
}
|
genmodes.c (make_vector_mode): Allow making VECTOR_MODE_INT of a MODE_PARTIAL_INT mode.
* genmodes.c (make_vector_mode): Allow making VECTOR_MODE_INT of a
MODE_PARTIAL_INT mode.
* config/bfin/bfin-modes.def: Add V2PDI and V2SI.
* config/bfin/bfin.c (print_operand): Add macflag and mac/msu modifiers
for CONST_INTs.
(hard_regno_mode_ok): V2PDImode is ok for accumulators.
* config/bfin/bfin.h (CLASS_MAX_NREGS, HARD_REGNO_NREGS): Handle
V2PDImode.
* config/bfin/predicates.md (const01_operand, vec_shift_operand):
New predicates.
* config/bfin/bfin.md (UNSPEC_MUL_WITH_FLAG, UNSPEC_MAC_WITH_FLAG):
New constants.
(MACFLAG_NONE, MACFLAG_T, MACFLAG_FU, MACFLAG_TFU, MACFLAG_IS,
MACFLAG_IU, MACFLAG_W32, MACFLAG_M, MACFLAG_S2RND, MACFLAG_ISS2,
MACFLAG_IH): Likewise.
(movstricthi_1): Renamed from "*movstricthi".
(load_accumulator, load_accumulator_pair, movsi_insv, insv,
ssaddsi3, sssubsi3, ssnegsi2, signbitssi2, smaxhi3, sminhi3,
abshi2, neghi2, ssneghi2, signbitshi2, movhi_low2high,
movhi_high2high, movhi_low2low, movhi_high2low, movhiv2hi_low,
movhiv2hi_high, composev2hi, movv2hi_hi, movv2hi_hi_low,
movv2hi_hi_high, ssaddhi3, sssubhi3, ssaddv2hi3, sssubv2hi3,
addsubv2hi3, subaddv2hi3, ssaddsubv2hi3, sssubaddv2hi3,
sublohiv2hi3, subhilov2hi3, sssublohiv2hi3, sssubhilov2hi3,
addlohiv2hi3, addhilov2hi3, ssaddlohiv2hi3, ssaddhilov2hi3,
mulhisi_ll, mulhisi_lh, mulhisi_hl, mulhisi_hh, ssnegv2hi2,
ssashiftv2hi3, ssashifthi3, lshiftv2hi3, lshifthi3, packv2hi,
flag_mulhi, flag_mulhisi_parts, flag_machi, flag_machi_acconly,
flag_macinithi, flag_macinit1hi, flag_mulv2hi, flag_mulv2hi_parts,
flag_macv2hi_parts, flag_macv2hi_parts_acconly,
flag_macinitv2hi_parts, flag_macinit1v2hi_parts): New patterns.
From-SVN: r113245
2006-04-25 13:49:27 +02:00
|
|
|
|
[(set_attr "type" "dsp32")])
|
|
|
|
|
|
|
|
|
|
(define_insn "flag_macinithi"
|
2007-04-12 15:03:17 +02:00
|
|
|
|
[(set (match_operand:HI 0 "register_operand" "=W,D,W")
|
|
|
|
|
(unspec:HI [(match_operand:HI 1 "register_operand" "d,d,d")
|
|
|
|
|
(match_operand:HI 2 "register_operand" "d,d,d")
|
|
|
|
|
(match_operand 3 "const_int_operand" "PB,PA,PA")]
|
genmodes.c (make_vector_mode): Allow making VECTOR_MODE_INT of a MODE_PARTIAL_INT mode.
* genmodes.c (make_vector_mode): Allow making VECTOR_MODE_INT of a
MODE_PARTIAL_INT mode.
* config/bfin/bfin-modes.def: Add V2PDI and V2SI.
* config/bfin/bfin.c (print_operand): Add macflag and mac/msu modifiers
for CONST_INTs.
(hard_regno_mode_ok): V2PDImode is ok for accumulators.
* config/bfin/bfin.h (CLASS_MAX_NREGS, HARD_REGNO_NREGS): Handle
V2PDImode.
* config/bfin/predicates.md (const01_operand, vec_shift_operand):
New predicates.
* config/bfin/bfin.md (UNSPEC_MUL_WITH_FLAG, UNSPEC_MAC_WITH_FLAG):
New constants.
(MACFLAG_NONE, MACFLAG_T, MACFLAG_FU, MACFLAG_TFU, MACFLAG_IS,
MACFLAG_IU, MACFLAG_W32, MACFLAG_M, MACFLAG_S2RND, MACFLAG_ISS2,
MACFLAG_IH): Likewise.
(movstricthi_1): Renamed from "*movstricthi".
(load_accumulator, load_accumulator_pair, movsi_insv, insv,
ssaddsi3, sssubsi3, ssnegsi2, signbitssi2, smaxhi3, sminhi3,
abshi2, neghi2, ssneghi2, signbitshi2, movhi_low2high,
movhi_high2high, movhi_low2low, movhi_high2low, movhiv2hi_low,
movhiv2hi_high, composev2hi, movv2hi_hi, movv2hi_hi_low,
movv2hi_hi_high, ssaddhi3, sssubhi3, ssaddv2hi3, sssubv2hi3,
addsubv2hi3, subaddv2hi3, ssaddsubv2hi3, sssubaddv2hi3,
sublohiv2hi3, subhilov2hi3, sssublohiv2hi3, sssubhilov2hi3,
addlohiv2hi3, addhilov2hi3, ssaddlohiv2hi3, ssaddhilov2hi3,
mulhisi_ll, mulhisi_lh, mulhisi_hl, mulhisi_hh, ssnegv2hi2,
ssashiftv2hi3, ssashifthi3, lshiftv2hi3, lshifthi3, packv2hi,
flag_mulhi, flag_mulhisi_parts, flag_machi, flag_machi_acconly,
flag_macinithi, flag_macinit1hi, flag_mulv2hi, flag_mulv2hi_parts,
flag_macv2hi_parts, flag_macv2hi_parts_acconly,
flag_macinitv2hi_parts, flag_macinit1v2hi_parts): New patterns.
From-SVN: r113245
2006-04-25 13:49:27 +02:00
|
|
|
|
UNSPEC_MAC_WITH_FLAG))
|
2007-04-12 15:03:17 +02:00
|
|
|
|
(set (match_operand:PDI 4 "register_operand" "=B,A,B")
|
genmodes.c (make_vector_mode): Allow making VECTOR_MODE_INT of a MODE_PARTIAL_INT mode.
* genmodes.c (make_vector_mode): Allow making VECTOR_MODE_INT of a
MODE_PARTIAL_INT mode.
* config/bfin/bfin-modes.def: Add V2PDI and V2SI.
* config/bfin/bfin.c (print_operand): Add macflag and mac/msu modifiers
for CONST_INTs.
(hard_regno_mode_ok): V2PDImode is ok for accumulators.
* config/bfin/bfin.h (CLASS_MAX_NREGS, HARD_REGNO_NREGS): Handle
V2PDImode.
* config/bfin/predicates.md (const01_operand, vec_shift_operand):
New predicates.
* config/bfin/bfin.md (UNSPEC_MUL_WITH_FLAG, UNSPEC_MAC_WITH_FLAG):
New constants.
(MACFLAG_NONE, MACFLAG_T, MACFLAG_FU, MACFLAG_TFU, MACFLAG_IS,
MACFLAG_IU, MACFLAG_W32, MACFLAG_M, MACFLAG_S2RND, MACFLAG_ISS2,
MACFLAG_IH): Likewise.
(movstricthi_1): Renamed from "*movstricthi".
(load_accumulator, load_accumulator_pair, movsi_insv, insv,
ssaddsi3, sssubsi3, ssnegsi2, signbitssi2, smaxhi3, sminhi3,
abshi2, neghi2, ssneghi2, signbitshi2, movhi_low2high,
movhi_high2high, movhi_low2low, movhi_high2low, movhiv2hi_low,
movhiv2hi_high, composev2hi, movv2hi_hi, movv2hi_hi_low,
movv2hi_hi_high, ssaddhi3, sssubhi3, ssaddv2hi3, sssubv2hi3,
addsubv2hi3, subaddv2hi3, ssaddsubv2hi3, sssubaddv2hi3,
sublohiv2hi3, subhilov2hi3, sssublohiv2hi3, sssubhilov2hi3,
addlohiv2hi3, addhilov2hi3, ssaddlohiv2hi3, ssaddhilov2hi3,
mulhisi_ll, mulhisi_lh, mulhisi_hl, mulhisi_hh, ssnegv2hi2,
ssashiftv2hi3, ssashifthi3, lshiftv2hi3, lshifthi3, packv2hi,
flag_mulhi, flag_mulhisi_parts, flag_machi, flag_machi_acconly,
flag_macinithi, flag_macinit1hi, flag_mulv2hi, flag_mulv2hi_parts,
flag_macv2hi_parts, flag_macv2hi_parts_acconly,
flag_macinitv2hi_parts, flag_macinit1v2hi_parts): New patterns.
From-SVN: r113245
2006-04-25 13:49:27 +02:00
|
|
|
|
(unspec:PDI [(match_dup 1) (match_dup 2) (match_dup 3)]
|
|
|
|
|
UNSPEC_MAC_WITH_FLAG))]
|
|
|
|
|
""
|
2007-04-12 15:03:17 +02:00
|
|
|
|
"%h0 = (%4 = %h1 * %h2) %M3%!"
|
genmodes.c (make_vector_mode): Allow making VECTOR_MODE_INT of a MODE_PARTIAL_INT mode.
* genmodes.c (make_vector_mode): Allow making VECTOR_MODE_INT of a
MODE_PARTIAL_INT mode.
* config/bfin/bfin-modes.def: Add V2PDI and V2SI.
* config/bfin/bfin.c (print_operand): Add macflag and mac/msu modifiers
for CONST_INTs.
(hard_regno_mode_ok): V2PDImode is ok for accumulators.
* config/bfin/bfin.h (CLASS_MAX_NREGS, HARD_REGNO_NREGS): Handle
V2PDImode.
* config/bfin/predicates.md (const01_operand, vec_shift_operand):
New predicates.
* config/bfin/bfin.md (UNSPEC_MUL_WITH_FLAG, UNSPEC_MAC_WITH_FLAG):
New constants.
(MACFLAG_NONE, MACFLAG_T, MACFLAG_FU, MACFLAG_TFU, MACFLAG_IS,
MACFLAG_IU, MACFLAG_W32, MACFLAG_M, MACFLAG_S2RND, MACFLAG_ISS2,
MACFLAG_IH): Likewise.
(movstricthi_1): Renamed from "*movstricthi".
(load_accumulator, load_accumulator_pair, movsi_insv, insv,
ssaddsi3, sssubsi3, ssnegsi2, signbitssi2, smaxhi3, sminhi3,
abshi2, neghi2, ssneghi2, signbitshi2, movhi_low2high,
movhi_high2high, movhi_low2low, movhi_high2low, movhiv2hi_low,
movhiv2hi_high, composev2hi, movv2hi_hi, movv2hi_hi_low,
movv2hi_hi_high, ssaddhi3, sssubhi3, ssaddv2hi3, sssubv2hi3,
addsubv2hi3, subaddv2hi3, ssaddsubv2hi3, sssubaddv2hi3,
sublohiv2hi3, subhilov2hi3, sssublohiv2hi3, sssubhilov2hi3,
addlohiv2hi3, addhilov2hi3, ssaddlohiv2hi3, ssaddhilov2hi3,
mulhisi_ll, mulhisi_lh, mulhisi_hl, mulhisi_hh, ssnegv2hi2,
ssashiftv2hi3, ssashifthi3, lshiftv2hi3, lshifthi3, packv2hi,
flag_mulhi, flag_mulhisi_parts, flag_machi, flag_machi_acconly,
flag_macinithi, flag_macinit1hi, flag_mulv2hi, flag_mulv2hi_parts,
flag_macv2hi_parts, flag_macv2hi_parts_acconly,
flag_macinitv2hi_parts, flag_macinit1v2hi_parts): New patterns.
From-SVN: r113245
2006-04-25 13:49:27 +02:00
|
|
|
|
[(set_attr "type" "dsp32")])
|
|
|
|
|
|
|
|
|
|
(define_insn "flag_macinit1hi"
|
2007-04-12 15:03:17 +02:00
|
|
|
|
[(set (match_operand:PDI 0 "register_operand" "=B,e")
|
|
|
|
|
(unspec:PDI [(match_operand:HI 1 "register_operand" "d,d")
|
|
|
|
|
(match_operand:HI 2 "register_operand" "d,d")
|
|
|
|
|
(match_operand 3 "const_int_operand" "PB,PA")]
|
genmodes.c (make_vector_mode): Allow making VECTOR_MODE_INT of a MODE_PARTIAL_INT mode.
* genmodes.c (make_vector_mode): Allow making VECTOR_MODE_INT of a
MODE_PARTIAL_INT mode.
* config/bfin/bfin-modes.def: Add V2PDI and V2SI.
* config/bfin/bfin.c (print_operand): Add macflag and mac/msu modifiers
for CONST_INTs.
(hard_regno_mode_ok): V2PDImode is ok for accumulators.
* config/bfin/bfin.h (CLASS_MAX_NREGS, HARD_REGNO_NREGS): Handle
V2PDImode.
* config/bfin/predicates.md (const01_operand, vec_shift_operand):
New predicates.
* config/bfin/bfin.md (UNSPEC_MUL_WITH_FLAG, UNSPEC_MAC_WITH_FLAG):
New constants.
(MACFLAG_NONE, MACFLAG_T, MACFLAG_FU, MACFLAG_TFU, MACFLAG_IS,
MACFLAG_IU, MACFLAG_W32, MACFLAG_M, MACFLAG_S2RND, MACFLAG_ISS2,
MACFLAG_IH): Likewise.
(movstricthi_1): Renamed from "*movstricthi".
(load_accumulator, load_accumulator_pair, movsi_insv, insv,
ssaddsi3, sssubsi3, ssnegsi2, signbitssi2, smaxhi3, sminhi3,
abshi2, neghi2, ssneghi2, signbitshi2, movhi_low2high,
movhi_high2high, movhi_low2low, movhi_high2low, movhiv2hi_low,
movhiv2hi_high, composev2hi, movv2hi_hi, movv2hi_hi_low,
movv2hi_hi_high, ssaddhi3, sssubhi3, ssaddv2hi3, sssubv2hi3,
addsubv2hi3, subaddv2hi3, ssaddsubv2hi3, sssubaddv2hi3,
sublohiv2hi3, subhilov2hi3, sssublohiv2hi3, sssubhilov2hi3,
addlohiv2hi3, addhilov2hi3, ssaddlohiv2hi3, ssaddhilov2hi3,
mulhisi_ll, mulhisi_lh, mulhisi_hl, mulhisi_hh, ssnegv2hi2,
ssashiftv2hi3, ssashifthi3, lshiftv2hi3, lshifthi3, packv2hi,
flag_mulhi, flag_mulhisi_parts, flag_machi, flag_machi_acconly,
flag_macinithi, flag_macinit1hi, flag_mulv2hi, flag_mulv2hi_parts,
flag_macv2hi_parts, flag_macv2hi_parts_acconly,
flag_macinitv2hi_parts, flag_macinit1v2hi_parts): New patterns.
From-SVN: r113245
2006-04-25 13:49:27 +02:00
|
|
|
|
UNSPEC_MAC_WITH_FLAG))]
|
|
|
|
|
""
|
rtlanal.c (note_uses): Deal with SEQUENCEs.
* rtlanal.c (note_uses): Deal with SEQUENCEs.
* config/bfin/bfin.c: Include "timevar.h".
(bfin_flag_schedule_insns2, splitting_for_sched,
bfin_flag_var_tracking): New variables.
(print_operand): Handle '%!'.
(override_options): Disable normal sched2 pass, instead set
bfin_flag_schedule_insns2 for reorg to handle it.
(output_file_start): Likewise for var-tracking.
(bfin_optimize_loop): Take some care not to stumble over SEQUENCEs.
(gen_one_bundle, bfin_gen_bundles, type_for_anomaly, trapping_loads_p):
New functions.
(bfin_reorg): Do second scheduling pass here, and call
bfin_gen_bundles. Use type_for_anomaly and trapping_loads_p instead
of examining insns directly. If bfin_flag_var_tracking, call
var-tracking pass when done with everything else.
* config/bfin/bfin.h (PRINT_OPERAND_PUNCT_VALID_P): '!' is valid.
* config/bfin/bfin.md (UNSPEC_32BIT): New constant.
(movsi_insn32): New pattern, with two new splits to create it
before the final scheduling pass.
(neghi2): Not a dsp32 insn, rather alu0.
(movbi, pushsi_insn, popsi_insn, movsi_insn, movv2hi_insn, movhi_insn,
movqi_insn, movsf_insn, movsi_insv, extendhisi2, zero_extendhisi2,
extendqihi2, extendqisi2, zero_extendqihi2, zero_extendqisi2,
mulhisi3, umulhisi3, ssadsi3, sssubsi3, smaxsi3, sminsi3, abssi2,
ssnegsi2, signbitssi2, smaxhi3, sminhi3, abshi2, ssneghi2, signbitshi2,
movhi_low2high, movhi_high2high, movhi_low2low, movhi_high2low,
movhiv2hi_low, movhiv2hi_high, composev2hi, packv2hi, movv2hi_hi,
ssaddhi3, sssubhi3, addv2hi3, ssaddv2hi3, subv2hi3, sssubv2hi3,
addsubv2hi3, subaddv2hi3, ssaddsubv2hi3, sssubaddv2hi3, sublohiv2hi3,
subhilov2hi3, sssublohiv2hi3, sssubhilov2hi3, addlohiv2hi3,
addhilov2hi3, ssaddlohiv2hi3, ssaddhilov2hi3, sminv2hi3, smaxv2hi3,
flag_mulhi, flag_mulhisi, flag_mulhisi_parts, flag_machi,
flag_machi_acconly, flag_macinithi, flag_macinit1hi, mulv2hi3,
flag_mulv2hi, flag_mulv2hi_parts, flag_macv2hi_parts,
flag_macv2hi_parts_acconly, flag_macinitv2hi_parts,
flag_macinit1v2hi_parts, mulhisi_ll, mulhisi_lh, mulhisi_hl,
mulhisi_hh, ssnegv2hi2, absv2hi2, ssashiftv2hi3, ssashifthi3,
lshiftv2hi3, lshifthi3): Use '%!' to terminate all dsp32/load/store
variants instead of ';'.
(ror_one, rol_one): Likewise. Make them dsp32 insns.
(ashlsi3_insn, ashrsi3, lshrsi3): Add dsp32 variants.
(align8, align16, align24): Now named patterns; also using '%!'.
(mnop): New insn.
From-SVN: r119534
2006-12-05 09:49:56 +01:00
|
|
|
|
"%0 = %h1 * %h2 %M3%!"
|
genmodes.c (make_vector_mode): Allow making VECTOR_MODE_INT of a MODE_PARTIAL_INT mode.
* genmodes.c (make_vector_mode): Allow making VECTOR_MODE_INT of a
MODE_PARTIAL_INT mode.
* config/bfin/bfin-modes.def: Add V2PDI and V2SI.
* config/bfin/bfin.c (print_operand): Add macflag and mac/msu modifiers
for CONST_INTs.
(hard_regno_mode_ok): V2PDImode is ok for accumulators.
* config/bfin/bfin.h (CLASS_MAX_NREGS, HARD_REGNO_NREGS): Handle
V2PDImode.
* config/bfin/predicates.md (const01_operand, vec_shift_operand):
New predicates.
* config/bfin/bfin.md (UNSPEC_MUL_WITH_FLAG, UNSPEC_MAC_WITH_FLAG):
New constants.
(MACFLAG_NONE, MACFLAG_T, MACFLAG_FU, MACFLAG_TFU, MACFLAG_IS,
MACFLAG_IU, MACFLAG_W32, MACFLAG_M, MACFLAG_S2RND, MACFLAG_ISS2,
MACFLAG_IH): Likewise.
(movstricthi_1): Renamed from "*movstricthi".
(load_accumulator, load_accumulator_pair, movsi_insv, insv,
ssaddsi3, sssubsi3, ssnegsi2, signbitssi2, smaxhi3, sminhi3,
abshi2, neghi2, ssneghi2, signbitshi2, movhi_low2high,
movhi_high2high, movhi_low2low, movhi_high2low, movhiv2hi_low,
movhiv2hi_high, composev2hi, movv2hi_hi, movv2hi_hi_low,
movv2hi_hi_high, ssaddhi3, sssubhi3, ssaddv2hi3, sssubv2hi3,
addsubv2hi3, subaddv2hi3, ssaddsubv2hi3, sssubaddv2hi3,
sublohiv2hi3, subhilov2hi3, sssublohiv2hi3, sssubhilov2hi3,
addlohiv2hi3, addhilov2hi3, ssaddlohiv2hi3, ssaddhilov2hi3,
mulhisi_ll, mulhisi_lh, mulhisi_hl, mulhisi_hh, ssnegv2hi2,
ssashiftv2hi3, ssashifthi3, lshiftv2hi3, lshifthi3, packv2hi,
flag_mulhi, flag_mulhisi_parts, flag_machi, flag_machi_acconly,
flag_macinithi, flag_macinit1hi, flag_mulv2hi, flag_mulv2hi_parts,
flag_macv2hi_parts, flag_macv2hi_parts_acconly,
flag_macinitv2hi_parts, flag_macinit1v2hi_parts): New patterns.
From-SVN: r113245
2006-04-25 13:49:27 +02:00
|
|
|
|
[(set_attr "type" "dsp32")])
|
|
|
|
|
|
2005-06-30 09:57:05 +02:00
|
|
|
|
(define_insn "mulv2hi3"
|
2005-04-05 13:26:48 +02:00
|
|
|
|
[(set (match_operand:V2HI 0 "register_operand" "=d")
|
|
|
|
|
(mult:V2HI (match_operand:V2HI 1 "register_operand" "d")
|
|
|
|
|
(match_operand:V2HI 2 "register_operand" "d")))]
|
|
|
|
|
""
|
rtlanal.c (note_uses): Deal with SEQUENCEs.
* rtlanal.c (note_uses): Deal with SEQUENCEs.
* config/bfin/bfin.c: Include "timevar.h".
(bfin_flag_schedule_insns2, splitting_for_sched,
bfin_flag_var_tracking): New variables.
(print_operand): Handle '%!'.
(override_options): Disable normal sched2 pass, instead set
bfin_flag_schedule_insns2 for reorg to handle it.
(output_file_start): Likewise for var-tracking.
(bfin_optimize_loop): Take some care not to stumble over SEQUENCEs.
(gen_one_bundle, bfin_gen_bundles, type_for_anomaly, trapping_loads_p):
New functions.
(bfin_reorg): Do second scheduling pass here, and call
bfin_gen_bundles. Use type_for_anomaly and trapping_loads_p instead
of examining insns directly. If bfin_flag_var_tracking, call
var-tracking pass when done with everything else.
* config/bfin/bfin.h (PRINT_OPERAND_PUNCT_VALID_P): '!' is valid.
* config/bfin/bfin.md (UNSPEC_32BIT): New constant.
(movsi_insn32): New pattern, with two new splits to create it
before the final scheduling pass.
(neghi2): Not a dsp32 insn, rather alu0.
(movbi, pushsi_insn, popsi_insn, movsi_insn, movv2hi_insn, movhi_insn,
movqi_insn, movsf_insn, movsi_insv, extendhisi2, zero_extendhisi2,
extendqihi2, extendqisi2, zero_extendqihi2, zero_extendqisi2,
mulhisi3, umulhisi3, ssadsi3, sssubsi3, smaxsi3, sminsi3, abssi2,
ssnegsi2, signbitssi2, smaxhi3, sminhi3, abshi2, ssneghi2, signbitshi2,
movhi_low2high, movhi_high2high, movhi_low2low, movhi_high2low,
movhiv2hi_low, movhiv2hi_high, composev2hi, packv2hi, movv2hi_hi,
ssaddhi3, sssubhi3, addv2hi3, ssaddv2hi3, subv2hi3, sssubv2hi3,
addsubv2hi3, subaddv2hi3, ssaddsubv2hi3, sssubaddv2hi3, sublohiv2hi3,
subhilov2hi3, sssublohiv2hi3, sssubhilov2hi3, addlohiv2hi3,
addhilov2hi3, ssaddlohiv2hi3, ssaddhilov2hi3, sminv2hi3, smaxv2hi3,
flag_mulhi, flag_mulhisi, flag_mulhisi_parts, flag_machi,
flag_machi_acconly, flag_macinithi, flag_macinit1hi, mulv2hi3,
flag_mulv2hi, flag_mulv2hi_parts, flag_macv2hi_parts,
flag_macv2hi_parts_acconly, flag_macinitv2hi_parts,
flag_macinit1v2hi_parts, mulhisi_ll, mulhisi_lh, mulhisi_hl,
mulhisi_hh, ssnegv2hi2, absv2hi2, ssashiftv2hi3, ssashifthi3,
lshiftv2hi3, lshifthi3): Use '%!' to terminate all dsp32/load/store
variants instead of ';'.
(ror_one, rol_one): Likewise. Make them dsp32 insns.
(ashlsi3_insn, ashrsi3, lshrsi3): Add dsp32 variants.
(align8, align16, align24): Now named patterns; also using '%!'.
(mnop): New insn.
From-SVN: r119534
2006-12-05 09:49:56 +01:00
|
|
|
|
"%h0 = %h1 * %h2, %d0 = %d1 * %d2 (IS)%!"
|
2005-04-05 13:26:48 +02:00
|
|
|
|
[(set_attr "type" "dsp32")])
|
|
|
|
|
|
genmodes.c (make_vector_mode): Allow making VECTOR_MODE_INT of a MODE_PARTIAL_INT mode.
* genmodes.c (make_vector_mode): Allow making VECTOR_MODE_INT of a
MODE_PARTIAL_INT mode.
* config/bfin/bfin-modes.def: Add V2PDI and V2SI.
* config/bfin/bfin.c (print_operand): Add macflag and mac/msu modifiers
for CONST_INTs.
(hard_regno_mode_ok): V2PDImode is ok for accumulators.
* config/bfin/bfin.h (CLASS_MAX_NREGS, HARD_REGNO_NREGS): Handle
V2PDImode.
* config/bfin/predicates.md (const01_operand, vec_shift_operand):
New predicates.
* config/bfin/bfin.md (UNSPEC_MUL_WITH_FLAG, UNSPEC_MAC_WITH_FLAG):
New constants.
(MACFLAG_NONE, MACFLAG_T, MACFLAG_FU, MACFLAG_TFU, MACFLAG_IS,
MACFLAG_IU, MACFLAG_W32, MACFLAG_M, MACFLAG_S2RND, MACFLAG_ISS2,
MACFLAG_IH): Likewise.
(movstricthi_1): Renamed from "*movstricthi".
(load_accumulator, load_accumulator_pair, movsi_insv, insv,
ssaddsi3, sssubsi3, ssnegsi2, signbitssi2, smaxhi3, sminhi3,
abshi2, neghi2, ssneghi2, signbitshi2, movhi_low2high,
movhi_high2high, movhi_low2low, movhi_high2low, movhiv2hi_low,
movhiv2hi_high, composev2hi, movv2hi_hi, movv2hi_hi_low,
movv2hi_hi_high, ssaddhi3, sssubhi3, ssaddv2hi3, sssubv2hi3,
addsubv2hi3, subaddv2hi3, ssaddsubv2hi3, sssubaddv2hi3,
sublohiv2hi3, subhilov2hi3, sssublohiv2hi3, sssubhilov2hi3,
addlohiv2hi3, addhilov2hi3, ssaddlohiv2hi3, ssaddhilov2hi3,
mulhisi_ll, mulhisi_lh, mulhisi_hl, mulhisi_hh, ssnegv2hi2,
ssashiftv2hi3, ssashifthi3, lshiftv2hi3, lshifthi3, packv2hi,
flag_mulhi, flag_mulhisi_parts, flag_machi, flag_machi_acconly,
flag_macinithi, flag_macinit1hi, flag_mulv2hi, flag_mulv2hi_parts,
flag_macv2hi_parts, flag_macv2hi_parts_acconly,
flag_macinitv2hi_parts, flag_macinit1v2hi_parts): New patterns.
From-SVN: r113245
2006-04-25 13:49:27 +02:00
|
|
|
|
(define_insn "flag_mulv2hi"
|
|
|
|
|
[(set (match_operand:V2HI 0 "register_operand" "=d")
|
|
|
|
|
(unspec:V2HI [(match_operand:V2HI 1 "register_operand" "d")
|
|
|
|
|
(match_operand:V2HI 2 "register_operand" "d")
|
|
|
|
|
(match_operand 3 "const_int_operand" "n")]
|
|
|
|
|
UNSPEC_MUL_WITH_FLAG))]
|
|
|
|
|
""
|
rtlanal.c (note_uses): Deal with SEQUENCEs.
* rtlanal.c (note_uses): Deal with SEQUENCEs.
* config/bfin/bfin.c: Include "timevar.h".
(bfin_flag_schedule_insns2, splitting_for_sched,
bfin_flag_var_tracking): New variables.
(print_operand): Handle '%!'.
(override_options): Disable normal sched2 pass, instead set
bfin_flag_schedule_insns2 for reorg to handle it.
(output_file_start): Likewise for var-tracking.
(bfin_optimize_loop): Take some care not to stumble over SEQUENCEs.
(gen_one_bundle, bfin_gen_bundles, type_for_anomaly, trapping_loads_p):
New functions.
(bfin_reorg): Do second scheduling pass here, and call
bfin_gen_bundles. Use type_for_anomaly and trapping_loads_p instead
of examining insns directly. If bfin_flag_var_tracking, call
var-tracking pass when done with everything else.
* config/bfin/bfin.h (PRINT_OPERAND_PUNCT_VALID_P): '!' is valid.
* config/bfin/bfin.md (UNSPEC_32BIT): New constant.
(movsi_insn32): New pattern, with two new splits to create it
before the final scheduling pass.
(neghi2): Not a dsp32 insn, rather alu0.
(movbi, pushsi_insn, popsi_insn, movsi_insn, movv2hi_insn, movhi_insn,
movqi_insn, movsf_insn, movsi_insv, extendhisi2, zero_extendhisi2,
extendqihi2, extendqisi2, zero_extendqihi2, zero_extendqisi2,
mulhisi3, umulhisi3, ssadsi3, sssubsi3, smaxsi3, sminsi3, abssi2,
ssnegsi2, signbitssi2, smaxhi3, sminhi3, abshi2, ssneghi2, signbitshi2,
movhi_low2high, movhi_high2high, movhi_low2low, movhi_high2low,
movhiv2hi_low, movhiv2hi_high, composev2hi, packv2hi, movv2hi_hi,
ssaddhi3, sssubhi3, addv2hi3, ssaddv2hi3, subv2hi3, sssubv2hi3,
addsubv2hi3, subaddv2hi3, ssaddsubv2hi3, sssubaddv2hi3, sublohiv2hi3,
subhilov2hi3, sssublohiv2hi3, sssubhilov2hi3, addlohiv2hi3,
addhilov2hi3, ssaddlohiv2hi3, ssaddhilov2hi3, sminv2hi3, smaxv2hi3,
flag_mulhi, flag_mulhisi, flag_mulhisi_parts, flag_machi,
flag_machi_acconly, flag_macinithi, flag_macinit1hi, mulv2hi3,
flag_mulv2hi, flag_mulv2hi_parts, flag_macv2hi_parts,
flag_macv2hi_parts_acconly, flag_macinitv2hi_parts,
flag_macinit1v2hi_parts, mulhisi_ll, mulhisi_lh, mulhisi_hl,
mulhisi_hh, ssnegv2hi2, absv2hi2, ssashiftv2hi3, ssashifthi3,
lshiftv2hi3, lshifthi3): Use '%!' to terminate all dsp32/load/store
variants instead of ';'.
(ror_one, rol_one): Likewise. Make them dsp32 insns.
(ashlsi3_insn, ashrsi3, lshrsi3): Add dsp32 variants.
(align8, align16, align24): Now named patterns; also using '%!'.
(mnop): New insn.
From-SVN: r119534
2006-12-05 09:49:56 +01:00
|
|
|
|
"%h0 = %h1 * %h2, %d0 = %d1 * %d2 %M3%!"
|
genmodes.c (make_vector_mode): Allow making VECTOR_MODE_INT of a MODE_PARTIAL_INT mode.
* genmodes.c (make_vector_mode): Allow making VECTOR_MODE_INT of a
MODE_PARTIAL_INT mode.
* config/bfin/bfin-modes.def: Add V2PDI and V2SI.
* config/bfin/bfin.c (print_operand): Add macflag and mac/msu modifiers
for CONST_INTs.
(hard_regno_mode_ok): V2PDImode is ok for accumulators.
* config/bfin/bfin.h (CLASS_MAX_NREGS, HARD_REGNO_NREGS): Handle
V2PDImode.
* config/bfin/predicates.md (const01_operand, vec_shift_operand):
New predicates.
* config/bfin/bfin.md (UNSPEC_MUL_WITH_FLAG, UNSPEC_MAC_WITH_FLAG):
New constants.
(MACFLAG_NONE, MACFLAG_T, MACFLAG_FU, MACFLAG_TFU, MACFLAG_IS,
MACFLAG_IU, MACFLAG_W32, MACFLAG_M, MACFLAG_S2RND, MACFLAG_ISS2,
MACFLAG_IH): Likewise.
(movstricthi_1): Renamed from "*movstricthi".
(load_accumulator, load_accumulator_pair, movsi_insv, insv,
ssaddsi3, sssubsi3, ssnegsi2, signbitssi2, smaxhi3, sminhi3,
abshi2, neghi2, ssneghi2, signbitshi2, movhi_low2high,
movhi_high2high, movhi_low2low, movhi_high2low, movhiv2hi_low,
movhiv2hi_high, composev2hi, movv2hi_hi, movv2hi_hi_low,
movv2hi_hi_high, ssaddhi3, sssubhi3, ssaddv2hi3, sssubv2hi3,
addsubv2hi3, subaddv2hi3, ssaddsubv2hi3, sssubaddv2hi3,
sublohiv2hi3, subhilov2hi3, sssublohiv2hi3, sssubhilov2hi3,
addlohiv2hi3, addhilov2hi3, ssaddlohiv2hi3, ssaddhilov2hi3,
mulhisi_ll, mulhisi_lh, mulhisi_hl, mulhisi_hh, ssnegv2hi2,
ssashiftv2hi3, ssashifthi3, lshiftv2hi3, lshifthi3, packv2hi,
flag_mulhi, flag_mulhisi_parts, flag_machi, flag_machi_acconly,
flag_macinithi, flag_macinit1hi, flag_mulv2hi, flag_mulv2hi_parts,
flag_macv2hi_parts, flag_macv2hi_parts_acconly,
flag_macinitv2hi_parts, flag_macinit1v2hi_parts): New patterns.
From-SVN: r113245
2006-04-25 13:49:27 +02:00
|
|
|
|
[(set_attr "type" "dsp32")])
|
|
|
|
|
|
|
|
|
|
(define_insn "flag_mulv2hi_parts"
|
|
|
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[(set (match_operand:V2HI 0 "register_operand" "=d")
|
|
|
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(unspec:V2HI [(vec_concat:V2HI
|
|
|
|
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(vec_select:HI
|
|
|
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(match_operand:V2HI 1 "register_operand" "d")
|
2006-05-04 13:03:41 +02:00
|
|
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(parallel [(match_operand 3 "const01_operand" "P0P1")]))
|
genmodes.c (make_vector_mode): Allow making VECTOR_MODE_INT of a MODE_PARTIAL_INT mode.
* genmodes.c (make_vector_mode): Allow making VECTOR_MODE_INT of a
MODE_PARTIAL_INT mode.
* config/bfin/bfin-modes.def: Add V2PDI and V2SI.
* config/bfin/bfin.c (print_operand): Add macflag and mac/msu modifiers
for CONST_INTs.
(hard_regno_mode_ok): V2PDImode is ok for accumulators.
* config/bfin/bfin.h (CLASS_MAX_NREGS, HARD_REGNO_NREGS): Handle
V2PDImode.
* config/bfin/predicates.md (const01_operand, vec_shift_operand):
New predicates.
* config/bfin/bfin.md (UNSPEC_MUL_WITH_FLAG, UNSPEC_MAC_WITH_FLAG):
New constants.
(MACFLAG_NONE, MACFLAG_T, MACFLAG_FU, MACFLAG_TFU, MACFLAG_IS,
MACFLAG_IU, MACFLAG_W32, MACFLAG_M, MACFLAG_S2RND, MACFLAG_ISS2,
MACFLAG_IH): Likewise.
(movstricthi_1): Renamed from "*movstricthi".
(load_accumulator, load_accumulator_pair, movsi_insv, insv,
ssaddsi3, sssubsi3, ssnegsi2, signbitssi2, smaxhi3, sminhi3,
abshi2, neghi2, ssneghi2, signbitshi2, movhi_low2high,
movhi_high2high, movhi_low2low, movhi_high2low, movhiv2hi_low,
movhiv2hi_high, composev2hi, movv2hi_hi, movv2hi_hi_low,
movv2hi_hi_high, ssaddhi3, sssubhi3, ssaddv2hi3, sssubv2hi3,
addsubv2hi3, subaddv2hi3, ssaddsubv2hi3, sssubaddv2hi3,
sublohiv2hi3, subhilov2hi3, sssublohiv2hi3, sssubhilov2hi3,
addlohiv2hi3, addhilov2hi3, ssaddlohiv2hi3, ssaddhilov2hi3,
mulhisi_ll, mulhisi_lh, mulhisi_hl, mulhisi_hh, ssnegv2hi2,
ssashiftv2hi3, ssashifthi3, lshiftv2hi3, lshifthi3, packv2hi,
flag_mulhi, flag_mulhisi_parts, flag_machi, flag_machi_acconly,
flag_macinithi, flag_macinit1hi, flag_mulv2hi, flag_mulv2hi_parts,
flag_macv2hi_parts, flag_macv2hi_parts_acconly,
flag_macinitv2hi_parts, flag_macinit1v2hi_parts): New patterns.
From-SVN: r113245
2006-04-25 13:49:27 +02:00
|
|
|
|
(vec_select:HI
|
|
|
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|
(match_dup 1)
|
2006-05-04 13:03:41 +02:00
|
|
|
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(parallel [(match_operand 4 "const01_operand" "P0P1")])))
|
genmodes.c (make_vector_mode): Allow making VECTOR_MODE_INT of a MODE_PARTIAL_INT mode.
* genmodes.c (make_vector_mode): Allow making VECTOR_MODE_INT of a
MODE_PARTIAL_INT mode.
* config/bfin/bfin-modes.def: Add V2PDI and V2SI.
* config/bfin/bfin.c (print_operand): Add macflag and mac/msu modifiers
for CONST_INTs.
(hard_regno_mode_ok): V2PDImode is ok for accumulators.
* config/bfin/bfin.h (CLASS_MAX_NREGS, HARD_REGNO_NREGS): Handle
V2PDImode.
* config/bfin/predicates.md (const01_operand, vec_shift_operand):
New predicates.
* config/bfin/bfin.md (UNSPEC_MUL_WITH_FLAG, UNSPEC_MAC_WITH_FLAG):
New constants.
(MACFLAG_NONE, MACFLAG_T, MACFLAG_FU, MACFLAG_TFU, MACFLAG_IS,
MACFLAG_IU, MACFLAG_W32, MACFLAG_M, MACFLAG_S2RND, MACFLAG_ISS2,
MACFLAG_IH): Likewise.
(movstricthi_1): Renamed from "*movstricthi".
(load_accumulator, load_accumulator_pair, movsi_insv, insv,
ssaddsi3, sssubsi3, ssnegsi2, signbitssi2, smaxhi3, sminhi3,
abshi2, neghi2, ssneghi2, signbitshi2, movhi_low2high,
movhi_high2high, movhi_low2low, movhi_high2low, movhiv2hi_low,
movhiv2hi_high, composev2hi, movv2hi_hi, movv2hi_hi_low,
movv2hi_hi_high, ssaddhi3, sssubhi3, ssaddv2hi3, sssubv2hi3,
addsubv2hi3, subaddv2hi3, ssaddsubv2hi3, sssubaddv2hi3,
sublohiv2hi3, subhilov2hi3, sssublohiv2hi3, sssubhilov2hi3,
addlohiv2hi3, addhilov2hi3, ssaddlohiv2hi3, ssaddhilov2hi3,
mulhisi_ll, mulhisi_lh, mulhisi_hl, mulhisi_hh, ssnegv2hi2,
ssashiftv2hi3, ssashifthi3, lshiftv2hi3, lshifthi3, packv2hi,
flag_mulhi, flag_mulhisi_parts, flag_machi, flag_machi_acconly,
flag_macinithi, flag_macinit1hi, flag_mulv2hi, flag_mulv2hi_parts,
flag_macv2hi_parts, flag_macv2hi_parts_acconly,
flag_macinitv2hi_parts, flag_macinit1v2hi_parts): New patterns.
From-SVN: r113245
2006-04-25 13:49:27 +02:00
|
|
|
|
(vec_concat:V2HI
|
|
|
|
|
(vec_select:HI (match_operand:V2HI 2 "register_operand" "d")
|
2006-05-04 13:03:41 +02:00
|
|
|
|
(parallel [(match_operand 5 "const01_operand" "P0P1")]))
|
genmodes.c (make_vector_mode): Allow making VECTOR_MODE_INT of a MODE_PARTIAL_INT mode.
* genmodes.c (make_vector_mode): Allow making VECTOR_MODE_INT of a
MODE_PARTIAL_INT mode.
* config/bfin/bfin-modes.def: Add V2PDI and V2SI.
* config/bfin/bfin.c (print_operand): Add macflag and mac/msu modifiers
for CONST_INTs.
(hard_regno_mode_ok): V2PDImode is ok for accumulators.
* config/bfin/bfin.h (CLASS_MAX_NREGS, HARD_REGNO_NREGS): Handle
V2PDImode.
* config/bfin/predicates.md (const01_operand, vec_shift_operand):
New predicates.
* config/bfin/bfin.md (UNSPEC_MUL_WITH_FLAG, UNSPEC_MAC_WITH_FLAG):
New constants.
(MACFLAG_NONE, MACFLAG_T, MACFLAG_FU, MACFLAG_TFU, MACFLAG_IS,
MACFLAG_IU, MACFLAG_W32, MACFLAG_M, MACFLAG_S2RND, MACFLAG_ISS2,
MACFLAG_IH): Likewise.
(movstricthi_1): Renamed from "*movstricthi".
(load_accumulator, load_accumulator_pair, movsi_insv, insv,
ssaddsi3, sssubsi3, ssnegsi2, signbitssi2, smaxhi3, sminhi3,
abshi2, neghi2, ssneghi2, signbitshi2, movhi_low2high,
movhi_high2high, movhi_low2low, movhi_high2low, movhiv2hi_low,
movhiv2hi_high, composev2hi, movv2hi_hi, movv2hi_hi_low,
movv2hi_hi_high, ssaddhi3, sssubhi3, ssaddv2hi3, sssubv2hi3,
addsubv2hi3, subaddv2hi3, ssaddsubv2hi3, sssubaddv2hi3,
sublohiv2hi3, subhilov2hi3, sssublohiv2hi3, sssubhilov2hi3,
addlohiv2hi3, addhilov2hi3, ssaddlohiv2hi3, ssaddhilov2hi3,
mulhisi_ll, mulhisi_lh, mulhisi_hl, mulhisi_hh, ssnegv2hi2,
ssashiftv2hi3, ssashifthi3, lshiftv2hi3, lshifthi3, packv2hi,
flag_mulhi, flag_mulhisi_parts, flag_machi, flag_machi_acconly,
flag_macinithi, flag_macinit1hi, flag_mulv2hi, flag_mulv2hi_parts,
flag_macv2hi_parts, flag_macv2hi_parts_acconly,
flag_macinitv2hi_parts, flag_macinit1v2hi_parts): New patterns.
From-SVN: r113245
2006-04-25 13:49:27 +02:00
|
|
|
|
(vec_select:HI (match_dup 2)
|
2006-05-04 13:03:41 +02:00
|
|
|
|
(parallel [(match_operand 6 "const01_operand" "P0P1")])))
|
genmodes.c (make_vector_mode): Allow making VECTOR_MODE_INT of a MODE_PARTIAL_INT mode.
* genmodes.c (make_vector_mode): Allow making VECTOR_MODE_INT of a
MODE_PARTIAL_INT mode.
* config/bfin/bfin-modes.def: Add V2PDI and V2SI.
* config/bfin/bfin.c (print_operand): Add macflag and mac/msu modifiers
for CONST_INTs.
(hard_regno_mode_ok): V2PDImode is ok for accumulators.
* config/bfin/bfin.h (CLASS_MAX_NREGS, HARD_REGNO_NREGS): Handle
V2PDImode.
* config/bfin/predicates.md (const01_operand, vec_shift_operand):
New predicates.
* config/bfin/bfin.md (UNSPEC_MUL_WITH_FLAG, UNSPEC_MAC_WITH_FLAG):
New constants.
(MACFLAG_NONE, MACFLAG_T, MACFLAG_FU, MACFLAG_TFU, MACFLAG_IS,
MACFLAG_IU, MACFLAG_W32, MACFLAG_M, MACFLAG_S2RND, MACFLAG_ISS2,
MACFLAG_IH): Likewise.
(movstricthi_1): Renamed from "*movstricthi".
(load_accumulator, load_accumulator_pair, movsi_insv, insv,
ssaddsi3, sssubsi3, ssnegsi2, signbitssi2, smaxhi3, sminhi3,
abshi2, neghi2, ssneghi2, signbitshi2, movhi_low2high,
movhi_high2high, movhi_low2low, movhi_high2low, movhiv2hi_low,
movhiv2hi_high, composev2hi, movv2hi_hi, movv2hi_hi_low,
movv2hi_hi_high, ssaddhi3, sssubhi3, ssaddv2hi3, sssubv2hi3,
addsubv2hi3, subaddv2hi3, ssaddsubv2hi3, sssubaddv2hi3,
sublohiv2hi3, subhilov2hi3, sssublohiv2hi3, sssubhilov2hi3,
addlohiv2hi3, addhilov2hi3, ssaddlohiv2hi3, ssaddhilov2hi3,
mulhisi_ll, mulhisi_lh, mulhisi_hl, mulhisi_hh, ssnegv2hi2,
ssashiftv2hi3, ssashifthi3, lshiftv2hi3, lshifthi3, packv2hi,
flag_mulhi, flag_mulhisi_parts, flag_machi, flag_machi_acconly,
flag_macinithi, flag_macinit1hi, flag_mulv2hi, flag_mulv2hi_parts,
flag_macv2hi_parts, flag_macv2hi_parts_acconly,
flag_macinitv2hi_parts, flag_macinit1v2hi_parts): New patterns.
From-SVN: r113245
2006-04-25 13:49:27 +02:00
|
|
|
|
(match_operand 7 "const_int_operand" "n")]
|
|
|
|
|
UNSPEC_MUL_WITH_FLAG))]
|
|
|
|
|
""
|
|
|
|
|
{
|
|
|
|
|
const char *templates[] = {
|
rtlanal.c (note_uses): Deal with SEQUENCEs.
* rtlanal.c (note_uses): Deal with SEQUENCEs.
* config/bfin/bfin.c: Include "timevar.h".
(bfin_flag_schedule_insns2, splitting_for_sched,
bfin_flag_var_tracking): New variables.
(print_operand): Handle '%!'.
(override_options): Disable normal sched2 pass, instead set
bfin_flag_schedule_insns2 for reorg to handle it.
(output_file_start): Likewise for var-tracking.
(bfin_optimize_loop): Take some care not to stumble over SEQUENCEs.
(gen_one_bundle, bfin_gen_bundles, type_for_anomaly, trapping_loads_p):
New functions.
(bfin_reorg): Do second scheduling pass here, and call
bfin_gen_bundles. Use type_for_anomaly and trapping_loads_p instead
of examining insns directly. If bfin_flag_var_tracking, call
var-tracking pass when done with everything else.
* config/bfin/bfin.h (PRINT_OPERAND_PUNCT_VALID_P): '!' is valid.
* config/bfin/bfin.md (UNSPEC_32BIT): New constant.
(movsi_insn32): New pattern, with two new splits to create it
before the final scheduling pass.
(neghi2): Not a dsp32 insn, rather alu0.
(movbi, pushsi_insn, popsi_insn, movsi_insn, movv2hi_insn, movhi_insn,
movqi_insn, movsf_insn, movsi_insv, extendhisi2, zero_extendhisi2,
extendqihi2, extendqisi2, zero_extendqihi2, zero_extendqisi2,
mulhisi3, umulhisi3, ssadsi3, sssubsi3, smaxsi3, sminsi3, abssi2,
ssnegsi2, signbitssi2, smaxhi3, sminhi3, abshi2, ssneghi2, signbitshi2,
movhi_low2high, movhi_high2high, movhi_low2low, movhi_high2low,
movhiv2hi_low, movhiv2hi_high, composev2hi, packv2hi, movv2hi_hi,
ssaddhi3, sssubhi3, addv2hi3, ssaddv2hi3, subv2hi3, sssubv2hi3,
addsubv2hi3, subaddv2hi3, ssaddsubv2hi3, sssubaddv2hi3, sublohiv2hi3,
subhilov2hi3, sssublohiv2hi3, sssubhilov2hi3, addlohiv2hi3,
addhilov2hi3, ssaddlohiv2hi3, ssaddhilov2hi3, sminv2hi3, smaxv2hi3,
flag_mulhi, flag_mulhisi, flag_mulhisi_parts, flag_machi,
flag_machi_acconly, flag_macinithi, flag_macinit1hi, mulv2hi3,
flag_mulv2hi, flag_mulv2hi_parts, flag_macv2hi_parts,
flag_macv2hi_parts_acconly, flag_macinitv2hi_parts,
flag_macinit1v2hi_parts, mulhisi_ll, mulhisi_lh, mulhisi_hl,
mulhisi_hh, ssnegv2hi2, absv2hi2, ssashiftv2hi3, ssashifthi3,
lshiftv2hi3, lshifthi3): Use '%!' to terminate all dsp32/load/store
variants instead of ';'.
(ror_one, rol_one): Likewise. Make them dsp32 insns.
(ashlsi3_insn, ashrsi3, lshrsi3): Add dsp32 variants.
(align8, align16, align24): Now named patterns; also using '%!'.
(mnop): New insn.
From-SVN: r119534
2006-12-05 09:49:56 +01:00
|
|
|
|
"%h0 = %h1 * %h2, %d0 = %h1 * %h2 %M7%!",
|
|
|
|
|
"%h0 = %d1 * %h2, %d0 = %h1 * %h2 %M7%!",
|
|
|
|
|
"%h0 = %h1 * %h2, %d0 = %d1 * %h2 %M7%!",
|
|
|
|
|
"%h0 = %d1 * %h2, %d0 = %d1 * %h2 %M7%!",
|
|
|
|
|
"%h0 = %h1 * %d2, %d0 = %h1 * %h2 %M7%!",
|
|
|
|
|
"%h0 = %d1 * %d2, %d0 = %h1 * %h2 %M7%!",
|
|
|
|
|
"%h0 = %h1 * %d2, %d0 = %d1 * %h2 %M7%!",
|
|
|
|
|
"%h0 = %d1 * %d2, %d0 = %d1 * %h2 %M7%!",
|
|
|
|
|
"%h0 = %h1 * %h2, %d0 = %h1 * %d2 %M7%!",
|
|
|
|
|
"%h0 = %d1 * %h2, %d0 = %h1 * %d2 %M7%!",
|
|
|
|
|
"%h0 = %h1 * %h2, %d0 = %d1 * %d2 %M7%!",
|
|
|
|
|
"%h0 = %d1 * %h2, %d0 = %d1 * %d2 %M7%!",
|
|
|
|
|
"%h0 = %h1 * %d2, %d0 = %h1 * %d2 %M7%!",
|
|
|
|
|
"%h0 = %d1 * %d2, %d0 = %h1 * %d2 %M7%!",
|
|
|
|
|
"%h0 = %h1 * %d2, %d0 = %d1 * %d2 %M7%!",
|
|
|
|
|
"%h0 = %d1 * %d2, %d0 = %d1 * %d2 %M7%!" };
|
genmodes.c (make_vector_mode): Allow making VECTOR_MODE_INT of a MODE_PARTIAL_INT mode.
* genmodes.c (make_vector_mode): Allow making VECTOR_MODE_INT of a
MODE_PARTIAL_INT mode.
* config/bfin/bfin-modes.def: Add V2PDI and V2SI.
* config/bfin/bfin.c (print_operand): Add macflag and mac/msu modifiers
for CONST_INTs.
(hard_regno_mode_ok): V2PDImode is ok for accumulators.
* config/bfin/bfin.h (CLASS_MAX_NREGS, HARD_REGNO_NREGS): Handle
V2PDImode.
* config/bfin/predicates.md (const01_operand, vec_shift_operand):
New predicates.
* config/bfin/bfin.md (UNSPEC_MUL_WITH_FLAG, UNSPEC_MAC_WITH_FLAG):
New constants.
(MACFLAG_NONE, MACFLAG_T, MACFLAG_FU, MACFLAG_TFU, MACFLAG_IS,
MACFLAG_IU, MACFLAG_W32, MACFLAG_M, MACFLAG_S2RND, MACFLAG_ISS2,
MACFLAG_IH): Likewise.
(movstricthi_1): Renamed from "*movstricthi".
(load_accumulator, load_accumulator_pair, movsi_insv, insv,
ssaddsi3, sssubsi3, ssnegsi2, signbitssi2, smaxhi3, sminhi3,
abshi2, neghi2, ssneghi2, signbitshi2, movhi_low2high,
movhi_high2high, movhi_low2low, movhi_high2low, movhiv2hi_low,
movhiv2hi_high, composev2hi, movv2hi_hi, movv2hi_hi_low,
movv2hi_hi_high, ssaddhi3, sssubhi3, ssaddv2hi3, sssubv2hi3,
addsubv2hi3, subaddv2hi3, ssaddsubv2hi3, sssubaddv2hi3,
sublohiv2hi3, subhilov2hi3, sssublohiv2hi3, sssubhilov2hi3,
addlohiv2hi3, addhilov2hi3, ssaddlohiv2hi3, ssaddhilov2hi3,
mulhisi_ll, mulhisi_lh, mulhisi_hl, mulhisi_hh, ssnegv2hi2,
ssashiftv2hi3, ssashifthi3, lshiftv2hi3, lshifthi3, packv2hi,
flag_mulhi, flag_mulhisi_parts, flag_machi, flag_machi_acconly,
flag_macinithi, flag_macinit1hi, flag_mulv2hi, flag_mulv2hi_parts,
flag_macv2hi_parts, flag_macv2hi_parts_acconly,
flag_macinitv2hi_parts, flag_macinit1v2hi_parts): New patterns.
From-SVN: r113245
2006-04-25 13:49:27 +02:00
|
|
|
|
int alt = (INTVAL (operands[3]) + (INTVAL (operands[4]) << 1)
|
|
|
|
|
+ (INTVAL (operands[5]) << 2) + (INTVAL (operands[6]) << 3));
|
|
|
|
|
return templates[alt];
|
|
|
|
|
}
|
|
|
|
|
[(set_attr "type" "dsp32")])
|
|
|
|
|
|
|
|
|
|
;; A slightly complicated pattern.
|
|
|
|
|
;; Operand 0 is the halfword output; operand 11 is the accumulator output
|
|
|
|
|
;; Halfword inputs are operands 1 and 2; operands 3, 4, 5 and 6 specify which
|
|
|
|
|
;; parts of these 2x16 bit registers to use.
|
|
|
|
|
;; Operand 7 is the accumulator input.
|
|
|
|
|
;; Operands 8/9 specify whether low/high parts are mac (0) or msu (1)
|
|
|
|
|
;; Operand 10 is the macflag to be used.
|
|
|
|
|
(define_insn "flag_macv2hi_parts"
|
|
|
|
|
[(set (match_operand:V2HI 0 "register_operand" "=d")
|
|
|
|
|
(unspec:V2HI [(vec_concat:V2HI
|
|
|
|
|
(vec_select:HI
|
|
|
|
|
(match_operand:V2HI 1 "register_operand" "d")
|
2006-05-04 13:03:41 +02:00
|
|
|
|
(parallel [(match_operand 3 "const01_operand" "P0P1")]))
|
genmodes.c (make_vector_mode): Allow making VECTOR_MODE_INT of a MODE_PARTIAL_INT mode.
* genmodes.c (make_vector_mode): Allow making VECTOR_MODE_INT of a
MODE_PARTIAL_INT mode.
* config/bfin/bfin-modes.def: Add V2PDI and V2SI.
* config/bfin/bfin.c (print_operand): Add macflag and mac/msu modifiers
for CONST_INTs.
(hard_regno_mode_ok): V2PDImode is ok for accumulators.
* config/bfin/bfin.h (CLASS_MAX_NREGS, HARD_REGNO_NREGS): Handle
V2PDImode.
* config/bfin/predicates.md (const01_operand, vec_shift_operand):
New predicates.
* config/bfin/bfin.md (UNSPEC_MUL_WITH_FLAG, UNSPEC_MAC_WITH_FLAG):
New constants.
(MACFLAG_NONE, MACFLAG_T, MACFLAG_FU, MACFLAG_TFU, MACFLAG_IS,
MACFLAG_IU, MACFLAG_W32, MACFLAG_M, MACFLAG_S2RND, MACFLAG_ISS2,
MACFLAG_IH): Likewise.
(movstricthi_1): Renamed from "*movstricthi".
(load_accumulator, load_accumulator_pair, movsi_insv, insv,
ssaddsi3, sssubsi3, ssnegsi2, signbitssi2, smaxhi3, sminhi3,
abshi2, neghi2, ssneghi2, signbitshi2, movhi_low2high,
movhi_high2high, movhi_low2low, movhi_high2low, movhiv2hi_low,
movhiv2hi_high, composev2hi, movv2hi_hi, movv2hi_hi_low,
movv2hi_hi_high, ssaddhi3, sssubhi3, ssaddv2hi3, sssubv2hi3,
addsubv2hi3, subaddv2hi3, ssaddsubv2hi3, sssubaddv2hi3,
sublohiv2hi3, subhilov2hi3, sssublohiv2hi3, sssubhilov2hi3,
addlohiv2hi3, addhilov2hi3, ssaddlohiv2hi3, ssaddhilov2hi3,
mulhisi_ll, mulhisi_lh, mulhisi_hl, mulhisi_hh, ssnegv2hi2,
ssashiftv2hi3, ssashifthi3, lshiftv2hi3, lshifthi3, packv2hi,
flag_mulhi, flag_mulhisi_parts, flag_machi, flag_machi_acconly,
flag_macinithi, flag_macinit1hi, flag_mulv2hi, flag_mulv2hi_parts,
flag_macv2hi_parts, flag_macv2hi_parts_acconly,
flag_macinitv2hi_parts, flag_macinit1v2hi_parts): New patterns.
From-SVN: r113245
2006-04-25 13:49:27 +02:00
|
|
|
|
(vec_select:HI
|
|
|
|
|
(match_dup 1)
|
2006-05-04 13:03:41 +02:00
|
|
|
|
(parallel [(match_operand 4 "const01_operand" "P0P1")])))
|
genmodes.c (make_vector_mode): Allow making VECTOR_MODE_INT of a MODE_PARTIAL_INT mode.
* genmodes.c (make_vector_mode): Allow making VECTOR_MODE_INT of a
MODE_PARTIAL_INT mode.
* config/bfin/bfin-modes.def: Add V2PDI and V2SI.
* config/bfin/bfin.c (print_operand): Add macflag and mac/msu modifiers
for CONST_INTs.
(hard_regno_mode_ok): V2PDImode is ok for accumulators.
* config/bfin/bfin.h (CLASS_MAX_NREGS, HARD_REGNO_NREGS): Handle
V2PDImode.
* config/bfin/predicates.md (const01_operand, vec_shift_operand):
New predicates.
* config/bfin/bfin.md (UNSPEC_MUL_WITH_FLAG, UNSPEC_MAC_WITH_FLAG):
New constants.
(MACFLAG_NONE, MACFLAG_T, MACFLAG_FU, MACFLAG_TFU, MACFLAG_IS,
MACFLAG_IU, MACFLAG_W32, MACFLAG_M, MACFLAG_S2RND, MACFLAG_ISS2,
MACFLAG_IH): Likewise.
(movstricthi_1): Renamed from "*movstricthi".
(load_accumulator, load_accumulator_pair, movsi_insv, insv,
ssaddsi3, sssubsi3, ssnegsi2, signbitssi2, smaxhi3, sminhi3,
abshi2, neghi2, ssneghi2, signbitshi2, movhi_low2high,
movhi_high2high, movhi_low2low, movhi_high2low, movhiv2hi_low,
movhiv2hi_high, composev2hi, movv2hi_hi, movv2hi_hi_low,
movv2hi_hi_high, ssaddhi3, sssubhi3, ssaddv2hi3, sssubv2hi3,
addsubv2hi3, subaddv2hi3, ssaddsubv2hi3, sssubaddv2hi3,
sublohiv2hi3, subhilov2hi3, sssublohiv2hi3, sssubhilov2hi3,
addlohiv2hi3, addhilov2hi3, ssaddlohiv2hi3, ssaddhilov2hi3,
mulhisi_ll, mulhisi_lh, mulhisi_hl, mulhisi_hh, ssnegv2hi2,
ssashiftv2hi3, ssashifthi3, lshiftv2hi3, lshifthi3, packv2hi,
flag_mulhi, flag_mulhisi_parts, flag_machi, flag_machi_acconly,
flag_macinithi, flag_macinit1hi, flag_mulv2hi, flag_mulv2hi_parts,
flag_macv2hi_parts, flag_macv2hi_parts_acconly,
flag_macinitv2hi_parts, flag_macinit1v2hi_parts): New patterns.
From-SVN: r113245
2006-04-25 13:49:27 +02:00
|
|
|
|
(vec_concat:V2HI
|
|
|
|
|
(vec_select:HI (match_operand:V2HI 2 "register_operand" "d")
|
2006-05-04 13:03:41 +02:00
|
|
|
|
(parallel [(match_operand 5 "const01_operand" "P0P1")]))
|
genmodes.c (make_vector_mode): Allow making VECTOR_MODE_INT of a MODE_PARTIAL_INT mode.
* genmodes.c (make_vector_mode): Allow making VECTOR_MODE_INT of a
MODE_PARTIAL_INT mode.
* config/bfin/bfin-modes.def: Add V2PDI and V2SI.
* config/bfin/bfin.c (print_operand): Add macflag and mac/msu modifiers
for CONST_INTs.
(hard_regno_mode_ok): V2PDImode is ok for accumulators.
* config/bfin/bfin.h (CLASS_MAX_NREGS, HARD_REGNO_NREGS): Handle
V2PDImode.
* config/bfin/predicates.md (const01_operand, vec_shift_operand):
New predicates.
* config/bfin/bfin.md (UNSPEC_MUL_WITH_FLAG, UNSPEC_MAC_WITH_FLAG):
New constants.
(MACFLAG_NONE, MACFLAG_T, MACFLAG_FU, MACFLAG_TFU, MACFLAG_IS,
MACFLAG_IU, MACFLAG_W32, MACFLAG_M, MACFLAG_S2RND, MACFLAG_ISS2,
MACFLAG_IH): Likewise.
(movstricthi_1): Renamed from "*movstricthi".
(load_accumulator, load_accumulator_pair, movsi_insv, insv,
ssaddsi3, sssubsi3, ssnegsi2, signbitssi2, smaxhi3, sminhi3,
abshi2, neghi2, ssneghi2, signbitshi2, movhi_low2high,
movhi_high2high, movhi_low2low, movhi_high2low, movhiv2hi_low,
movhiv2hi_high, composev2hi, movv2hi_hi, movv2hi_hi_low,
movv2hi_hi_high, ssaddhi3, sssubhi3, ssaddv2hi3, sssubv2hi3,
addsubv2hi3, subaddv2hi3, ssaddsubv2hi3, sssubaddv2hi3,
sublohiv2hi3, subhilov2hi3, sssublohiv2hi3, sssubhilov2hi3,
addlohiv2hi3, addhilov2hi3, ssaddlohiv2hi3, ssaddhilov2hi3,
mulhisi_ll, mulhisi_lh, mulhisi_hl, mulhisi_hh, ssnegv2hi2,
ssashiftv2hi3, ssashifthi3, lshiftv2hi3, lshifthi3, packv2hi,
flag_mulhi, flag_mulhisi_parts, flag_machi, flag_machi_acconly,
flag_macinithi, flag_macinit1hi, flag_mulv2hi, flag_mulv2hi_parts,
flag_macv2hi_parts, flag_macv2hi_parts_acconly,
flag_macinitv2hi_parts, flag_macinit1v2hi_parts): New patterns.
From-SVN: r113245
2006-04-25 13:49:27 +02:00
|
|
|
|
(vec_select:HI (match_dup 2)
|
2006-05-04 13:03:41 +02:00
|
|
|
|
(parallel [(match_operand 6 "const01_operand" "P0P1")])))
|
genmodes.c (make_vector_mode): Allow making VECTOR_MODE_INT of a MODE_PARTIAL_INT mode.
* genmodes.c (make_vector_mode): Allow making VECTOR_MODE_INT of a
MODE_PARTIAL_INT mode.
* config/bfin/bfin-modes.def: Add V2PDI and V2SI.
* config/bfin/bfin.c (print_operand): Add macflag and mac/msu modifiers
for CONST_INTs.
(hard_regno_mode_ok): V2PDImode is ok for accumulators.
* config/bfin/bfin.h (CLASS_MAX_NREGS, HARD_REGNO_NREGS): Handle
V2PDImode.
* config/bfin/predicates.md (const01_operand, vec_shift_operand):
New predicates.
* config/bfin/bfin.md (UNSPEC_MUL_WITH_FLAG, UNSPEC_MAC_WITH_FLAG):
New constants.
(MACFLAG_NONE, MACFLAG_T, MACFLAG_FU, MACFLAG_TFU, MACFLAG_IS,
MACFLAG_IU, MACFLAG_W32, MACFLAG_M, MACFLAG_S2RND, MACFLAG_ISS2,
MACFLAG_IH): Likewise.
(movstricthi_1): Renamed from "*movstricthi".
(load_accumulator, load_accumulator_pair, movsi_insv, insv,
ssaddsi3, sssubsi3, ssnegsi2, signbitssi2, smaxhi3, sminhi3,
abshi2, neghi2, ssneghi2, signbitshi2, movhi_low2high,
movhi_high2high, movhi_low2low, movhi_high2low, movhiv2hi_low,
movhiv2hi_high, composev2hi, movv2hi_hi, movv2hi_hi_low,
movv2hi_hi_high, ssaddhi3, sssubhi3, ssaddv2hi3, sssubv2hi3,
addsubv2hi3, subaddv2hi3, ssaddsubv2hi3, sssubaddv2hi3,
sublohiv2hi3, subhilov2hi3, sssublohiv2hi3, sssubhilov2hi3,
addlohiv2hi3, addhilov2hi3, ssaddlohiv2hi3, ssaddhilov2hi3,
mulhisi_ll, mulhisi_lh, mulhisi_hl, mulhisi_hh, ssnegv2hi2,
ssashiftv2hi3, ssashifthi3, lshiftv2hi3, lshifthi3, packv2hi,
flag_mulhi, flag_mulhisi_parts, flag_machi, flag_machi_acconly,
flag_macinithi, flag_macinit1hi, flag_mulv2hi, flag_mulv2hi_parts,
flag_macv2hi_parts, flag_macv2hi_parts_acconly,
flag_macinitv2hi_parts, flag_macinit1v2hi_parts): New patterns.
From-SVN: r113245
2006-04-25 13:49:27 +02:00
|
|
|
|
(match_operand:V2PDI 7 "register_operand" "e")
|
|
|
|
|
(match_operand 8 "const01_operand" "P0P1")
|
|
|
|
|
(match_operand 9 "const01_operand" "P0P1")
|
|
|
|
|
(match_operand 10 "const_int_operand" "n")]
|
|
|
|
|
UNSPEC_MAC_WITH_FLAG))
|
|
|
|
|
(set (match_operand:V2PDI 11 "register_operand" "=e")
|
|
|
|
|
(unspec:V2PDI [(vec_concat:V2HI
|
|
|
|
|
(vec_select:HI (match_dup 1) (parallel [(match_dup 3)]))
|
|
|
|
|
(vec_select:HI (match_dup 1) (parallel [(match_dup 4)])))
|
|
|
|
|
(vec_concat:V2HI
|
|
|
|
|
(vec_select:HI (match_dup 2) (parallel [(match_dup 5)]))
|
|
|
|
|
(vec_select:HI (match_dup 2) (parallel [(match_dup 5)])))
|
|
|
|
|
(match_dup 7) (match_dup 8) (match_dup 9) (match_dup 10)]
|
|
|
|
|
UNSPEC_MAC_WITH_FLAG))]
|
|
|
|
|
""
|
|
|
|
|
{
|
|
|
|
|
const char *templates[] = {
|
rtlanal.c (note_uses): Deal with SEQUENCEs.
* rtlanal.c (note_uses): Deal with SEQUENCEs.
* config/bfin/bfin.c: Include "timevar.h".
(bfin_flag_schedule_insns2, splitting_for_sched,
bfin_flag_var_tracking): New variables.
(print_operand): Handle '%!'.
(override_options): Disable normal sched2 pass, instead set
bfin_flag_schedule_insns2 for reorg to handle it.
(output_file_start): Likewise for var-tracking.
(bfin_optimize_loop): Take some care not to stumble over SEQUENCEs.
(gen_one_bundle, bfin_gen_bundles, type_for_anomaly, trapping_loads_p):
New functions.
(bfin_reorg): Do second scheduling pass here, and call
bfin_gen_bundles. Use type_for_anomaly and trapping_loads_p instead
of examining insns directly. If bfin_flag_var_tracking, call
var-tracking pass when done with everything else.
* config/bfin/bfin.h (PRINT_OPERAND_PUNCT_VALID_P): '!' is valid.
* config/bfin/bfin.md (UNSPEC_32BIT): New constant.
(movsi_insn32): New pattern, with two new splits to create it
before the final scheduling pass.
(neghi2): Not a dsp32 insn, rather alu0.
(movbi, pushsi_insn, popsi_insn, movsi_insn, movv2hi_insn, movhi_insn,
movqi_insn, movsf_insn, movsi_insv, extendhisi2, zero_extendhisi2,
extendqihi2, extendqisi2, zero_extendqihi2, zero_extendqisi2,
mulhisi3, umulhisi3, ssadsi3, sssubsi3, smaxsi3, sminsi3, abssi2,
ssnegsi2, signbitssi2, smaxhi3, sminhi3, abshi2, ssneghi2, signbitshi2,
movhi_low2high, movhi_high2high, movhi_low2low, movhi_high2low,
movhiv2hi_low, movhiv2hi_high, composev2hi, packv2hi, movv2hi_hi,
ssaddhi3, sssubhi3, addv2hi3, ssaddv2hi3, subv2hi3, sssubv2hi3,
addsubv2hi3, subaddv2hi3, ssaddsubv2hi3, sssubaddv2hi3, sublohiv2hi3,
subhilov2hi3, sssublohiv2hi3, sssubhilov2hi3, addlohiv2hi3,
addhilov2hi3, ssaddlohiv2hi3, ssaddhilov2hi3, sminv2hi3, smaxv2hi3,
flag_mulhi, flag_mulhisi, flag_mulhisi_parts, flag_machi,
flag_machi_acconly, flag_macinithi, flag_macinit1hi, mulv2hi3,
flag_mulv2hi, flag_mulv2hi_parts, flag_macv2hi_parts,
flag_macv2hi_parts_acconly, flag_macinitv2hi_parts,
flag_macinit1v2hi_parts, mulhisi_ll, mulhisi_lh, mulhisi_hl,
mulhisi_hh, ssnegv2hi2, absv2hi2, ssashiftv2hi3, ssashifthi3,
lshiftv2hi3, lshifthi3): Use '%!' to terminate all dsp32/load/store
variants instead of ';'.
(ror_one, rol_one): Likewise. Make them dsp32 insns.
(ashlsi3_insn, ashrsi3, lshrsi3): Add dsp32 variants.
(align8, align16, align24): Now named patterns; also using '%!'.
(mnop): New insn.
From-SVN: r119534
2006-12-05 09:49:56 +01:00
|
|
|
|
"%h0 = (A0 %b8 %h1 * %h2), %d0 = (A1 %b9 %h1 * %h2) %M10%!",
|
|
|
|
|
"%h0 = (A0 %b8 %d1 * %h2), %d0 = (A1 %b9 %h1 * %h2) %M10%!",
|
|
|
|
|
"%h0 = (A0 %b8 %h1 * %h2), %d0 = (A1 %b9 %d1 * %h2) %M10%!",
|
|
|
|
|
"%h0 = (A0 %b8 %d1 * %h2), %d0 = (A1 %b9 %d1 * %h2) %M10%!",
|
|
|
|
|
"%h0 = (A0 %b8 %h1 * %d2), %d0 = (A1 %b9 %h1 * %h2) %M10%!",
|
|
|
|
|
"%h0 = (A0 %b8 %d1 * %d2), %d0 = (A1 %b9 %h1 * %h2) %M10%!",
|
|
|
|
|
"%h0 = (A0 %b8 %h1 * %d2), %d0 = (A1 %b9 %d1 * %h2) %M10%!",
|
|
|
|
|
"%h0 = (A0 %b8 %d1 * %d2), %d0 = (A1 %b9 %d1 * %h2) %M10%!",
|
|
|
|
|
"%h0 = (A0 %b8 %h1 * %h2), %d0 = (A1 %b9 %h1 * %d2) %M10%!",
|
|
|
|
|
"%h0 = (A0 %b8 %d1 * %h2), %d0 = (A1 %b9 %h1 * %d2) %M10%!",
|
|
|
|
|
"%h0 = (A0 %b8 %h1 * %h2), %d0 = (A1 %b9 %d1 * %d2) %M10%!",
|
|
|
|
|
"%h0 = (A0 %b8 %d1 * %h2), %d0 = (A1 %b9 %d1 * %d2) %M10%!",
|
|
|
|
|
"%h0 = (A0 %b8 %h1 * %d2), %d0 = (A1 %b9 %h1 * %d2) %M10%!",
|
|
|
|
|
"%h0 = (A0 %b8 %d1 * %d2), %d0 = (A1 %b9 %h1 * %d2) %M10%!",
|
|
|
|
|
"%h0 = (A0 %b8 %h1 * %d2), %d0 = (A1 %b9 %d1 * %d2) %M10%!",
|
|
|
|
|
"%h0 = (A0 %b8 %d1 * %d2), %d0 = (A1 %b9 %d1 * %d2) %M10%!" };
|
genmodes.c (make_vector_mode): Allow making VECTOR_MODE_INT of a MODE_PARTIAL_INT mode.
* genmodes.c (make_vector_mode): Allow making VECTOR_MODE_INT of a
MODE_PARTIAL_INT mode.
* config/bfin/bfin-modes.def: Add V2PDI and V2SI.
* config/bfin/bfin.c (print_operand): Add macflag and mac/msu modifiers
for CONST_INTs.
(hard_regno_mode_ok): V2PDImode is ok for accumulators.
* config/bfin/bfin.h (CLASS_MAX_NREGS, HARD_REGNO_NREGS): Handle
V2PDImode.
* config/bfin/predicates.md (const01_operand, vec_shift_operand):
New predicates.
* config/bfin/bfin.md (UNSPEC_MUL_WITH_FLAG, UNSPEC_MAC_WITH_FLAG):
New constants.
(MACFLAG_NONE, MACFLAG_T, MACFLAG_FU, MACFLAG_TFU, MACFLAG_IS,
MACFLAG_IU, MACFLAG_W32, MACFLAG_M, MACFLAG_S2RND, MACFLAG_ISS2,
MACFLAG_IH): Likewise.
(movstricthi_1): Renamed from "*movstricthi".
(load_accumulator, load_accumulator_pair, movsi_insv, insv,
ssaddsi3, sssubsi3, ssnegsi2, signbitssi2, smaxhi3, sminhi3,
abshi2, neghi2, ssneghi2, signbitshi2, movhi_low2high,
movhi_high2high, movhi_low2low, movhi_high2low, movhiv2hi_low,
movhiv2hi_high, composev2hi, movv2hi_hi, movv2hi_hi_low,
movv2hi_hi_high, ssaddhi3, sssubhi3, ssaddv2hi3, sssubv2hi3,
addsubv2hi3, subaddv2hi3, ssaddsubv2hi3, sssubaddv2hi3,
sublohiv2hi3, subhilov2hi3, sssublohiv2hi3, sssubhilov2hi3,
addlohiv2hi3, addhilov2hi3, ssaddlohiv2hi3, ssaddhilov2hi3,
mulhisi_ll, mulhisi_lh, mulhisi_hl, mulhisi_hh, ssnegv2hi2,
ssashiftv2hi3, ssashifthi3, lshiftv2hi3, lshifthi3, packv2hi,
flag_mulhi, flag_mulhisi_parts, flag_machi, flag_machi_acconly,
flag_macinithi, flag_macinit1hi, flag_mulv2hi, flag_mulv2hi_parts,
flag_macv2hi_parts, flag_macv2hi_parts_acconly,
flag_macinitv2hi_parts, flag_macinit1v2hi_parts): New patterns.
From-SVN: r113245
2006-04-25 13:49:27 +02:00
|
|
|
|
int alt = (INTVAL (operands[3]) + (INTVAL (operands[4]) << 1)
|
|
|
|
|
+ (INTVAL (operands[5]) << 2) + (INTVAL (operands[6]) << 3));
|
|
|
|
|
return templates[alt];
|
|
|
|
|
}
|
|
|
|
|
[(set_attr "type" "dsp32")])
|
|
|
|
|
|
|
|
|
|
(define_insn "flag_macv2hi_parts_acconly"
|
|
|
|
|
[(set (match_operand:V2PDI 0 "register_operand" "=e")
|
|
|
|
|
(unspec:V2PDI [(vec_concat:V2HI
|
|
|
|
|
(vec_select:HI
|
|
|
|
|
(match_operand:V2HI 1 "register_operand" "d")
|
2006-05-04 13:03:41 +02:00
|
|
|
|
(parallel [(match_operand 3 "const01_operand" "P0P1")]))
|
genmodes.c (make_vector_mode): Allow making VECTOR_MODE_INT of a MODE_PARTIAL_INT mode.
* genmodes.c (make_vector_mode): Allow making VECTOR_MODE_INT of a
MODE_PARTIAL_INT mode.
* config/bfin/bfin-modes.def: Add V2PDI and V2SI.
* config/bfin/bfin.c (print_operand): Add macflag and mac/msu modifiers
for CONST_INTs.
(hard_regno_mode_ok): V2PDImode is ok for accumulators.
* config/bfin/bfin.h (CLASS_MAX_NREGS, HARD_REGNO_NREGS): Handle
V2PDImode.
* config/bfin/predicates.md (const01_operand, vec_shift_operand):
New predicates.
* config/bfin/bfin.md (UNSPEC_MUL_WITH_FLAG, UNSPEC_MAC_WITH_FLAG):
New constants.
(MACFLAG_NONE, MACFLAG_T, MACFLAG_FU, MACFLAG_TFU, MACFLAG_IS,
MACFLAG_IU, MACFLAG_W32, MACFLAG_M, MACFLAG_S2RND, MACFLAG_ISS2,
MACFLAG_IH): Likewise.
(movstricthi_1): Renamed from "*movstricthi".
(load_accumulator, load_accumulator_pair, movsi_insv, insv,
ssaddsi3, sssubsi3, ssnegsi2, signbitssi2, smaxhi3, sminhi3,
abshi2, neghi2, ssneghi2, signbitshi2, movhi_low2high,
movhi_high2high, movhi_low2low, movhi_high2low, movhiv2hi_low,
movhiv2hi_high, composev2hi, movv2hi_hi, movv2hi_hi_low,
movv2hi_hi_high, ssaddhi3, sssubhi3, ssaddv2hi3, sssubv2hi3,
addsubv2hi3, subaddv2hi3, ssaddsubv2hi3, sssubaddv2hi3,
sublohiv2hi3, subhilov2hi3, sssublohiv2hi3, sssubhilov2hi3,
addlohiv2hi3, addhilov2hi3, ssaddlohiv2hi3, ssaddhilov2hi3,
mulhisi_ll, mulhisi_lh, mulhisi_hl, mulhisi_hh, ssnegv2hi2,
ssashiftv2hi3, ssashifthi3, lshiftv2hi3, lshifthi3, packv2hi,
flag_mulhi, flag_mulhisi_parts, flag_machi, flag_machi_acconly,
flag_macinithi, flag_macinit1hi, flag_mulv2hi, flag_mulv2hi_parts,
flag_macv2hi_parts, flag_macv2hi_parts_acconly,
flag_macinitv2hi_parts, flag_macinit1v2hi_parts): New patterns.
From-SVN: r113245
2006-04-25 13:49:27 +02:00
|
|
|
|
(vec_select:HI
|
|
|
|
|
(match_dup 1)
|
2006-05-04 13:03:41 +02:00
|
|
|
|
(parallel [(match_operand 4 "const01_operand" "P0P1")])))
|
genmodes.c (make_vector_mode): Allow making VECTOR_MODE_INT of a MODE_PARTIAL_INT mode.
* genmodes.c (make_vector_mode): Allow making VECTOR_MODE_INT of a
MODE_PARTIAL_INT mode.
* config/bfin/bfin-modes.def: Add V2PDI and V2SI.
* config/bfin/bfin.c (print_operand): Add macflag and mac/msu modifiers
for CONST_INTs.
(hard_regno_mode_ok): V2PDImode is ok for accumulators.
* config/bfin/bfin.h (CLASS_MAX_NREGS, HARD_REGNO_NREGS): Handle
V2PDImode.
* config/bfin/predicates.md (const01_operand, vec_shift_operand):
New predicates.
* config/bfin/bfin.md (UNSPEC_MUL_WITH_FLAG, UNSPEC_MAC_WITH_FLAG):
New constants.
(MACFLAG_NONE, MACFLAG_T, MACFLAG_FU, MACFLAG_TFU, MACFLAG_IS,
MACFLAG_IU, MACFLAG_W32, MACFLAG_M, MACFLAG_S2RND, MACFLAG_ISS2,
MACFLAG_IH): Likewise.
(movstricthi_1): Renamed from "*movstricthi".
(load_accumulator, load_accumulator_pair, movsi_insv, insv,
ssaddsi3, sssubsi3, ssnegsi2, signbitssi2, smaxhi3, sminhi3,
abshi2, neghi2, ssneghi2, signbitshi2, movhi_low2high,
movhi_high2high, movhi_low2low, movhi_high2low, movhiv2hi_low,
movhiv2hi_high, composev2hi, movv2hi_hi, movv2hi_hi_low,
movv2hi_hi_high, ssaddhi3, sssubhi3, ssaddv2hi3, sssubv2hi3,
addsubv2hi3, subaddv2hi3, ssaddsubv2hi3, sssubaddv2hi3,
sublohiv2hi3, subhilov2hi3, sssublohiv2hi3, sssubhilov2hi3,
addlohiv2hi3, addhilov2hi3, ssaddlohiv2hi3, ssaddhilov2hi3,
mulhisi_ll, mulhisi_lh, mulhisi_hl, mulhisi_hh, ssnegv2hi2,
ssashiftv2hi3, ssashifthi3, lshiftv2hi3, lshifthi3, packv2hi,
flag_mulhi, flag_mulhisi_parts, flag_machi, flag_machi_acconly,
flag_macinithi, flag_macinit1hi, flag_mulv2hi, flag_mulv2hi_parts,
flag_macv2hi_parts, flag_macv2hi_parts_acconly,
flag_macinitv2hi_parts, flag_macinit1v2hi_parts): New patterns.
From-SVN: r113245
2006-04-25 13:49:27 +02:00
|
|
|
|
(vec_concat:V2HI
|
|
|
|
|
(vec_select:HI (match_operand:V2HI 2 "register_operand" "d")
|
2006-05-04 13:03:41 +02:00
|
|
|
|
(parallel [(match_operand 5 "const01_operand" "P0P1")]))
|
genmodes.c (make_vector_mode): Allow making VECTOR_MODE_INT of a MODE_PARTIAL_INT mode.
* genmodes.c (make_vector_mode): Allow making VECTOR_MODE_INT of a
MODE_PARTIAL_INT mode.
* config/bfin/bfin-modes.def: Add V2PDI and V2SI.
* config/bfin/bfin.c (print_operand): Add macflag and mac/msu modifiers
for CONST_INTs.
(hard_regno_mode_ok): V2PDImode is ok for accumulators.
* config/bfin/bfin.h (CLASS_MAX_NREGS, HARD_REGNO_NREGS): Handle
V2PDImode.
* config/bfin/predicates.md (const01_operand, vec_shift_operand):
New predicates.
* config/bfin/bfin.md (UNSPEC_MUL_WITH_FLAG, UNSPEC_MAC_WITH_FLAG):
New constants.
(MACFLAG_NONE, MACFLAG_T, MACFLAG_FU, MACFLAG_TFU, MACFLAG_IS,
MACFLAG_IU, MACFLAG_W32, MACFLAG_M, MACFLAG_S2RND, MACFLAG_ISS2,
MACFLAG_IH): Likewise.
(movstricthi_1): Renamed from "*movstricthi".
(load_accumulator, load_accumulator_pair, movsi_insv, insv,
ssaddsi3, sssubsi3, ssnegsi2, signbitssi2, smaxhi3, sminhi3,
abshi2, neghi2, ssneghi2, signbitshi2, movhi_low2high,
movhi_high2high, movhi_low2low, movhi_high2low, movhiv2hi_low,
movhiv2hi_high, composev2hi, movv2hi_hi, movv2hi_hi_low,
movv2hi_hi_high, ssaddhi3, sssubhi3, ssaddv2hi3, sssubv2hi3,
addsubv2hi3, subaddv2hi3, ssaddsubv2hi3, sssubaddv2hi3,
sublohiv2hi3, subhilov2hi3, sssublohiv2hi3, sssubhilov2hi3,
addlohiv2hi3, addhilov2hi3, ssaddlohiv2hi3, ssaddhilov2hi3,
mulhisi_ll, mulhisi_lh, mulhisi_hl, mulhisi_hh, ssnegv2hi2,
ssashiftv2hi3, ssashifthi3, lshiftv2hi3, lshifthi3, packv2hi,
flag_mulhi, flag_mulhisi_parts, flag_machi, flag_machi_acconly,
flag_macinithi, flag_macinit1hi, flag_mulv2hi, flag_mulv2hi_parts,
flag_macv2hi_parts, flag_macv2hi_parts_acconly,
flag_macinitv2hi_parts, flag_macinit1v2hi_parts): New patterns.
From-SVN: r113245
2006-04-25 13:49:27 +02:00
|
|
|
|
(vec_select:HI (match_dup 2)
|
2006-05-04 13:03:41 +02:00
|
|
|
|
(parallel [(match_operand 6 "const01_operand" "P0P1")])))
|
genmodes.c (make_vector_mode): Allow making VECTOR_MODE_INT of a MODE_PARTIAL_INT mode.
* genmodes.c (make_vector_mode): Allow making VECTOR_MODE_INT of a
MODE_PARTIAL_INT mode.
* config/bfin/bfin-modes.def: Add V2PDI and V2SI.
* config/bfin/bfin.c (print_operand): Add macflag and mac/msu modifiers
for CONST_INTs.
(hard_regno_mode_ok): V2PDImode is ok for accumulators.
* config/bfin/bfin.h (CLASS_MAX_NREGS, HARD_REGNO_NREGS): Handle
V2PDImode.
* config/bfin/predicates.md (const01_operand, vec_shift_operand):
New predicates.
* config/bfin/bfin.md (UNSPEC_MUL_WITH_FLAG, UNSPEC_MAC_WITH_FLAG):
New constants.
(MACFLAG_NONE, MACFLAG_T, MACFLAG_FU, MACFLAG_TFU, MACFLAG_IS,
MACFLAG_IU, MACFLAG_W32, MACFLAG_M, MACFLAG_S2RND, MACFLAG_ISS2,
MACFLAG_IH): Likewise.
(movstricthi_1): Renamed from "*movstricthi".
(load_accumulator, load_accumulator_pair, movsi_insv, insv,
ssaddsi3, sssubsi3, ssnegsi2, signbitssi2, smaxhi3, sminhi3,
abshi2, neghi2, ssneghi2, signbitshi2, movhi_low2high,
movhi_high2high, movhi_low2low, movhi_high2low, movhiv2hi_low,
movhiv2hi_high, composev2hi, movv2hi_hi, movv2hi_hi_low,
movv2hi_hi_high, ssaddhi3, sssubhi3, ssaddv2hi3, sssubv2hi3,
addsubv2hi3, subaddv2hi3, ssaddsubv2hi3, sssubaddv2hi3,
sublohiv2hi3, subhilov2hi3, sssublohiv2hi3, sssubhilov2hi3,
addlohiv2hi3, addhilov2hi3, ssaddlohiv2hi3, ssaddhilov2hi3,
mulhisi_ll, mulhisi_lh, mulhisi_hl, mulhisi_hh, ssnegv2hi2,
ssashiftv2hi3, ssashifthi3, lshiftv2hi3, lshifthi3, packv2hi,
flag_mulhi, flag_mulhisi_parts, flag_machi, flag_machi_acconly,
flag_macinithi, flag_macinit1hi, flag_mulv2hi, flag_mulv2hi_parts,
flag_macv2hi_parts, flag_macv2hi_parts_acconly,
flag_macinitv2hi_parts, flag_macinit1v2hi_parts): New patterns.
From-SVN: r113245
2006-04-25 13:49:27 +02:00
|
|
|
|
(match_operand:V2PDI 7 "register_operand" "e")
|
|
|
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|
(match_operand 8 "const01_operand" "P0P1")
|
|
|
|
|
(match_operand 9 "const01_operand" "P0P1")
|
|
|
|
|
(match_operand 10 "const_int_operand" "n")]
|
|
|
|
|
UNSPEC_MAC_WITH_FLAG))]
|
|
|
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|
""
|
|
|
|
|
{
|
|
|
|
|
const char *templates[] = {
|
rtlanal.c (note_uses): Deal with SEQUENCEs.
* rtlanal.c (note_uses): Deal with SEQUENCEs.
* config/bfin/bfin.c: Include "timevar.h".
(bfin_flag_schedule_insns2, splitting_for_sched,
bfin_flag_var_tracking): New variables.
(print_operand): Handle '%!'.
(override_options): Disable normal sched2 pass, instead set
bfin_flag_schedule_insns2 for reorg to handle it.
(output_file_start): Likewise for var-tracking.
(bfin_optimize_loop): Take some care not to stumble over SEQUENCEs.
(gen_one_bundle, bfin_gen_bundles, type_for_anomaly, trapping_loads_p):
New functions.
(bfin_reorg): Do second scheduling pass here, and call
bfin_gen_bundles. Use type_for_anomaly and trapping_loads_p instead
of examining insns directly. If bfin_flag_var_tracking, call
var-tracking pass when done with everything else.
* config/bfin/bfin.h (PRINT_OPERAND_PUNCT_VALID_P): '!' is valid.
* config/bfin/bfin.md (UNSPEC_32BIT): New constant.
(movsi_insn32): New pattern, with two new splits to create it
before the final scheduling pass.
(neghi2): Not a dsp32 insn, rather alu0.
(movbi, pushsi_insn, popsi_insn, movsi_insn, movv2hi_insn, movhi_insn,
movqi_insn, movsf_insn, movsi_insv, extendhisi2, zero_extendhisi2,
extendqihi2, extendqisi2, zero_extendqihi2, zero_extendqisi2,
mulhisi3, umulhisi3, ssadsi3, sssubsi3, smaxsi3, sminsi3, abssi2,
ssnegsi2, signbitssi2, smaxhi3, sminhi3, abshi2, ssneghi2, signbitshi2,
movhi_low2high, movhi_high2high, movhi_low2low, movhi_high2low,
movhiv2hi_low, movhiv2hi_high, composev2hi, packv2hi, movv2hi_hi,
ssaddhi3, sssubhi3, addv2hi3, ssaddv2hi3, subv2hi3, sssubv2hi3,
addsubv2hi3, subaddv2hi3, ssaddsubv2hi3, sssubaddv2hi3, sublohiv2hi3,
subhilov2hi3, sssublohiv2hi3, sssubhilov2hi3, addlohiv2hi3,
addhilov2hi3, ssaddlohiv2hi3, ssaddhilov2hi3, sminv2hi3, smaxv2hi3,
flag_mulhi, flag_mulhisi, flag_mulhisi_parts, flag_machi,
flag_machi_acconly, flag_macinithi, flag_macinit1hi, mulv2hi3,
flag_mulv2hi, flag_mulv2hi_parts, flag_macv2hi_parts,
flag_macv2hi_parts_acconly, flag_macinitv2hi_parts,
flag_macinit1v2hi_parts, mulhisi_ll, mulhisi_lh, mulhisi_hl,
mulhisi_hh, ssnegv2hi2, absv2hi2, ssashiftv2hi3, ssashifthi3,
lshiftv2hi3, lshifthi3): Use '%!' to terminate all dsp32/load/store
variants instead of ';'.
(ror_one, rol_one): Likewise. Make them dsp32 insns.
(ashlsi3_insn, ashrsi3, lshrsi3): Add dsp32 variants.
(align8, align16, align24): Now named patterns; also using '%!'.
(mnop): New insn.
From-SVN: r119534
2006-12-05 09:49:56 +01:00
|
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|
"A0 %b8 %h1 * %h2, A1 %b9 %h1 * %h2 %M10%!",
|
|
|
|
|
"A0 %b8 %d1 * %h2, A1 %b9 %h1 * %h2 %M10%!",
|
|
|
|
|
"A0 %b8 %h1 * %h2, A1 %b9 %d1 * %h2 %M10%!",
|
|
|
|
|
"A0 %b8 %d1 * %h2, A1 %b9 %d1 * %h2 %M10%!",
|
|
|
|
|
"A0 %b8 %h1 * %d2, A1 %b9 %h1 * %h2 %M10%!",
|
|
|
|
|
"A0 %b8 %d1 * %d2, A1 %b9 %h1 * %h2 %M10%!",
|
|
|
|
|
"A0 %b8 %h1 * %d2, A1 %b9 %d1 * %h2 %M10%!",
|
|
|
|
|
"A0 %b8 %d1 * %d2, A1 %b9 %d1 * %h2 %M10%!",
|
|
|
|
|
"A0 %b8 %h1 * %h2, A1 %b9 %h1 * %d2 %M10%!",
|
|
|
|
|
"A0 %b8 %d1 * %h2, A1 %b9 %h1 * %d2 %M10%!",
|
|
|
|
|
"A0 %b8 %h1 * %h2, A1 %b9 %d1 * %d2 %M10%!",
|
|
|
|
|
"A0 %b8 %d1 * %h2, A1 %b9 %d1 * %d2 %M10%!",
|
|
|
|
|
"A0 %b8 %h1 * %d2, A1 %b9 %h1 * %d2 %M10%!",
|
|
|
|
|
"A0 %b8 %d1 * %d2, A1 %b9 %h1 * %d2 %M10%!",
|
|
|
|
|
"A0 %b8 %h1 * %d2, A1 %b9 %d1 * %d2 %M10%!",
|
|
|
|
|
"A0 %b8 %d1 * %d2, A1 %b9 %d1 * %d2 %M10%!" };
|
genmodes.c (make_vector_mode): Allow making VECTOR_MODE_INT of a MODE_PARTIAL_INT mode.
* genmodes.c (make_vector_mode): Allow making VECTOR_MODE_INT of a
MODE_PARTIAL_INT mode.
* config/bfin/bfin-modes.def: Add V2PDI and V2SI.
* config/bfin/bfin.c (print_operand): Add macflag and mac/msu modifiers
for CONST_INTs.
(hard_regno_mode_ok): V2PDImode is ok for accumulators.
* config/bfin/bfin.h (CLASS_MAX_NREGS, HARD_REGNO_NREGS): Handle
V2PDImode.
* config/bfin/predicates.md (const01_operand, vec_shift_operand):
New predicates.
* config/bfin/bfin.md (UNSPEC_MUL_WITH_FLAG, UNSPEC_MAC_WITH_FLAG):
New constants.
(MACFLAG_NONE, MACFLAG_T, MACFLAG_FU, MACFLAG_TFU, MACFLAG_IS,
MACFLAG_IU, MACFLAG_W32, MACFLAG_M, MACFLAG_S2RND, MACFLAG_ISS2,
MACFLAG_IH): Likewise.
(movstricthi_1): Renamed from "*movstricthi".
(load_accumulator, load_accumulator_pair, movsi_insv, insv,
ssaddsi3, sssubsi3, ssnegsi2, signbitssi2, smaxhi3, sminhi3,
abshi2, neghi2, ssneghi2, signbitshi2, movhi_low2high,
movhi_high2high, movhi_low2low, movhi_high2low, movhiv2hi_low,
movhiv2hi_high, composev2hi, movv2hi_hi, movv2hi_hi_low,
movv2hi_hi_high, ssaddhi3, sssubhi3, ssaddv2hi3, sssubv2hi3,
addsubv2hi3, subaddv2hi3, ssaddsubv2hi3, sssubaddv2hi3,
sublohiv2hi3, subhilov2hi3, sssublohiv2hi3, sssubhilov2hi3,
addlohiv2hi3, addhilov2hi3, ssaddlohiv2hi3, ssaddhilov2hi3,
mulhisi_ll, mulhisi_lh, mulhisi_hl, mulhisi_hh, ssnegv2hi2,
ssashiftv2hi3, ssashifthi3, lshiftv2hi3, lshifthi3, packv2hi,
flag_mulhi, flag_mulhisi_parts, flag_machi, flag_machi_acconly,
flag_macinithi, flag_macinit1hi, flag_mulv2hi, flag_mulv2hi_parts,
flag_macv2hi_parts, flag_macv2hi_parts_acconly,
flag_macinitv2hi_parts, flag_macinit1v2hi_parts): New patterns.
From-SVN: r113245
2006-04-25 13:49:27 +02:00
|
|
|
|
int alt = (INTVAL (operands[3]) + (INTVAL (operands[4]) << 1)
|
|
|
|
|
+ (INTVAL (operands[5]) << 2) + (INTVAL (operands[6]) << 3));
|
|
|
|
|
return templates[alt];
|
|
|
|
|
}
|
|
|
|
|
[(set_attr "type" "dsp32")])
|
|
|
|
|
|
|
|
|
|
;; Same as above, but initializing the accumulators and therefore a couple fewer
|
|
|
|
|
;; necessary operands.
|
|
|
|
|
(define_insn "flag_macinitv2hi_parts"
|
2005-04-05 13:26:48 +02:00
|
|
|
|
[(set (match_operand:V2HI 0 "register_operand" "=d")
|
genmodes.c (make_vector_mode): Allow making VECTOR_MODE_INT of a MODE_PARTIAL_INT mode.
* genmodes.c (make_vector_mode): Allow making VECTOR_MODE_INT of a
MODE_PARTIAL_INT mode.
* config/bfin/bfin-modes.def: Add V2PDI and V2SI.
* config/bfin/bfin.c (print_operand): Add macflag and mac/msu modifiers
for CONST_INTs.
(hard_regno_mode_ok): V2PDImode is ok for accumulators.
* config/bfin/bfin.h (CLASS_MAX_NREGS, HARD_REGNO_NREGS): Handle
V2PDImode.
* config/bfin/predicates.md (const01_operand, vec_shift_operand):
New predicates.
* config/bfin/bfin.md (UNSPEC_MUL_WITH_FLAG, UNSPEC_MAC_WITH_FLAG):
New constants.
(MACFLAG_NONE, MACFLAG_T, MACFLAG_FU, MACFLAG_TFU, MACFLAG_IS,
MACFLAG_IU, MACFLAG_W32, MACFLAG_M, MACFLAG_S2RND, MACFLAG_ISS2,
MACFLAG_IH): Likewise.
(movstricthi_1): Renamed from "*movstricthi".
(load_accumulator, load_accumulator_pair, movsi_insv, insv,
ssaddsi3, sssubsi3, ssnegsi2, signbitssi2, smaxhi3, sminhi3,
abshi2, neghi2, ssneghi2, signbitshi2, movhi_low2high,
movhi_high2high, movhi_low2low, movhi_high2low, movhiv2hi_low,
movhiv2hi_high, composev2hi, movv2hi_hi, movv2hi_hi_low,
movv2hi_hi_high, ssaddhi3, sssubhi3, ssaddv2hi3, sssubv2hi3,
addsubv2hi3, subaddv2hi3, ssaddsubv2hi3, sssubaddv2hi3,
sublohiv2hi3, subhilov2hi3, sssublohiv2hi3, sssubhilov2hi3,
addlohiv2hi3, addhilov2hi3, ssaddlohiv2hi3, ssaddhilov2hi3,
mulhisi_ll, mulhisi_lh, mulhisi_hl, mulhisi_hh, ssnegv2hi2,
ssashiftv2hi3, ssashifthi3, lshiftv2hi3, lshifthi3, packv2hi,
flag_mulhi, flag_mulhisi_parts, flag_machi, flag_machi_acconly,
flag_macinithi, flag_macinit1hi, flag_mulv2hi, flag_mulv2hi_parts,
flag_macv2hi_parts, flag_macv2hi_parts_acconly,
flag_macinitv2hi_parts, flag_macinit1v2hi_parts): New patterns.
From-SVN: r113245
2006-04-25 13:49:27 +02:00
|
|
|
|
(unspec:V2HI [(vec_concat:V2HI
|
|
|
|
|
(vec_select:HI
|
|
|
|
|
(match_operand:V2HI 1 "register_operand" "d")
|
2006-05-04 13:03:41 +02:00
|
|
|
|
(parallel [(match_operand 3 "const01_operand" "P0P1")]))
|
genmodes.c (make_vector_mode): Allow making VECTOR_MODE_INT of a MODE_PARTIAL_INT mode.
* genmodes.c (make_vector_mode): Allow making VECTOR_MODE_INT of a
MODE_PARTIAL_INT mode.
* config/bfin/bfin-modes.def: Add V2PDI and V2SI.
* config/bfin/bfin.c (print_operand): Add macflag and mac/msu modifiers
for CONST_INTs.
(hard_regno_mode_ok): V2PDImode is ok for accumulators.
* config/bfin/bfin.h (CLASS_MAX_NREGS, HARD_REGNO_NREGS): Handle
V2PDImode.
* config/bfin/predicates.md (const01_operand, vec_shift_operand):
New predicates.
* config/bfin/bfin.md (UNSPEC_MUL_WITH_FLAG, UNSPEC_MAC_WITH_FLAG):
New constants.
(MACFLAG_NONE, MACFLAG_T, MACFLAG_FU, MACFLAG_TFU, MACFLAG_IS,
MACFLAG_IU, MACFLAG_W32, MACFLAG_M, MACFLAG_S2RND, MACFLAG_ISS2,
MACFLAG_IH): Likewise.
(movstricthi_1): Renamed from "*movstricthi".
(load_accumulator, load_accumulator_pair, movsi_insv, insv,
ssaddsi3, sssubsi3, ssnegsi2, signbitssi2, smaxhi3, sminhi3,
abshi2, neghi2, ssneghi2, signbitshi2, movhi_low2high,
movhi_high2high, movhi_low2low, movhi_high2low, movhiv2hi_low,
movhiv2hi_high, composev2hi, movv2hi_hi, movv2hi_hi_low,
movv2hi_hi_high, ssaddhi3, sssubhi3, ssaddv2hi3, sssubv2hi3,
addsubv2hi3, subaddv2hi3, ssaddsubv2hi3, sssubaddv2hi3,
sublohiv2hi3, subhilov2hi3, sssublohiv2hi3, sssubhilov2hi3,
addlohiv2hi3, addhilov2hi3, ssaddlohiv2hi3, ssaddhilov2hi3,
mulhisi_ll, mulhisi_lh, mulhisi_hl, mulhisi_hh, ssnegv2hi2,
ssashiftv2hi3, ssashifthi3, lshiftv2hi3, lshifthi3, packv2hi,
flag_mulhi, flag_mulhisi_parts, flag_machi, flag_machi_acconly,
flag_macinithi, flag_macinit1hi, flag_mulv2hi, flag_mulv2hi_parts,
flag_macv2hi_parts, flag_macv2hi_parts_acconly,
flag_macinitv2hi_parts, flag_macinit1v2hi_parts): New patterns.
From-SVN: r113245
2006-04-25 13:49:27 +02:00
|
|
|
|
(vec_select:HI
|
|
|
|
|
(match_dup 1)
|
2006-05-04 13:03:41 +02:00
|
|
|
|
(parallel [(match_operand 4 "const01_operand" "P0P1")])))
|
genmodes.c (make_vector_mode): Allow making VECTOR_MODE_INT of a MODE_PARTIAL_INT mode.
* genmodes.c (make_vector_mode): Allow making VECTOR_MODE_INT of a
MODE_PARTIAL_INT mode.
* config/bfin/bfin-modes.def: Add V2PDI and V2SI.
* config/bfin/bfin.c (print_operand): Add macflag and mac/msu modifiers
for CONST_INTs.
(hard_regno_mode_ok): V2PDImode is ok for accumulators.
* config/bfin/bfin.h (CLASS_MAX_NREGS, HARD_REGNO_NREGS): Handle
V2PDImode.
* config/bfin/predicates.md (const01_operand, vec_shift_operand):
New predicates.
* config/bfin/bfin.md (UNSPEC_MUL_WITH_FLAG, UNSPEC_MAC_WITH_FLAG):
New constants.
(MACFLAG_NONE, MACFLAG_T, MACFLAG_FU, MACFLAG_TFU, MACFLAG_IS,
MACFLAG_IU, MACFLAG_W32, MACFLAG_M, MACFLAG_S2RND, MACFLAG_ISS2,
MACFLAG_IH): Likewise.
(movstricthi_1): Renamed from "*movstricthi".
(load_accumulator, load_accumulator_pair, movsi_insv, insv,
ssaddsi3, sssubsi3, ssnegsi2, signbitssi2, smaxhi3, sminhi3,
abshi2, neghi2, ssneghi2, signbitshi2, movhi_low2high,
movhi_high2high, movhi_low2low, movhi_high2low, movhiv2hi_low,
movhiv2hi_high, composev2hi, movv2hi_hi, movv2hi_hi_low,
movv2hi_hi_high, ssaddhi3, sssubhi3, ssaddv2hi3, sssubv2hi3,
addsubv2hi3, subaddv2hi3, ssaddsubv2hi3, sssubaddv2hi3,
sublohiv2hi3, subhilov2hi3, sssublohiv2hi3, sssubhilov2hi3,
addlohiv2hi3, addhilov2hi3, ssaddlohiv2hi3, ssaddhilov2hi3,
mulhisi_ll, mulhisi_lh, mulhisi_hl, mulhisi_hh, ssnegv2hi2,
ssashiftv2hi3, ssashifthi3, lshiftv2hi3, lshifthi3, packv2hi,
flag_mulhi, flag_mulhisi_parts, flag_machi, flag_machi_acconly,
flag_macinithi, flag_macinit1hi, flag_mulv2hi, flag_mulv2hi_parts,
flag_macv2hi_parts, flag_macv2hi_parts_acconly,
flag_macinitv2hi_parts, flag_macinit1v2hi_parts): New patterns.
From-SVN: r113245
2006-04-25 13:49:27 +02:00
|
|
|
|
(vec_concat:V2HI
|
|
|
|
|
(vec_select:HI (match_operand:V2HI 2 "register_operand" "d")
|
2006-05-04 13:03:41 +02:00
|
|
|
|
(parallel [(match_operand 5 "const01_operand" "P0P1")]))
|
genmodes.c (make_vector_mode): Allow making VECTOR_MODE_INT of a MODE_PARTIAL_INT mode.
* genmodes.c (make_vector_mode): Allow making VECTOR_MODE_INT of a
MODE_PARTIAL_INT mode.
* config/bfin/bfin-modes.def: Add V2PDI and V2SI.
* config/bfin/bfin.c (print_operand): Add macflag and mac/msu modifiers
for CONST_INTs.
(hard_regno_mode_ok): V2PDImode is ok for accumulators.
* config/bfin/bfin.h (CLASS_MAX_NREGS, HARD_REGNO_NREGS): Handle
V2PDImode.
* config/bfin/predicates.md (const01_operand, vec_shift_operand):
New predicates.
* config/bfin/bfin.md (UNSPEC_MUL_WITH_FLAG, UNSPEC_MAC_WITH_FLAG):
New constants.
(MACFLAG_NONE, MACFLAG_T, MACFLAG_FU, MACFLAG_TFU, MACFLAG_IS,
MACFLAG_IU, MACFLAG_W32, MACFLAG_M, MACFLAG_S2RND, MACFLAG_ISS2,
MACFLAG_IH): Likewise.
(movstricthi_1): Renamed from "*movstricthi".
(load_accumulator, load_accumulator_pair, movsi_insv, insv,
ssaddsi3, sssubsi3, ssnegsi2, signbitssi2, smaxhi3, sminhi3,
abshi2, neghi2, ssneghi2, signbitshi2, movhi_low2high,
movhi_high2high, movhi_low2low, movhi_high2low, movhiv2hi_low,
movhiv2hi_high, composev2hi, movv2hi_hi, movv2hi_hi_low,
movv2hi_hi_high, ssaddhi3, sssubhi3, ssaddv2hi3, sssubv2hi3,
addsubv2hi3, subaddv2hi3, ssaddsubv2hi3, sssubaddv2hi3,
sublohiv2hi3, subhilov2hi3, sssublohiv2hi3, sssubhilov2hi3,
addlohiv2hi3, addhilov2hi3, ssaddlohiv2hi3, ssaddhilov2hi3,
mulhisi_ll, mulhisi_lh, mulhisi_hl, mulhisi_hh, ssnegv2hi2,
ssashiftv2hi3, ssashifthi3, lshiftv2hi3, lshifthi3, packv2hi,
flag_mulhi, flag_mulhisi_parts, flag_machi, flag_machi_acconly,
flag_macinithi, flag_macinit1hi, flag_mulv2hi, flag_mulv2hi_parts,
flag_macv2hi_parts, flag_macv2hi_parts_acconly,
flag_macinitv2hi_parts, flag_macinit1v2hi_parts): New patterns.
From-SVN: r113245
2006-04-25 13:49:27 +02:00
|
|
|
|
(vec_select:HI (match_dup 2)
|
2006-05-04 13:03:41 +02:00
|
|
|
|
(parallel [(match_operand 6 "const01_operand" "P0P1")])))
|
genmodes.c (make_vector_mode): Allow making VECTOR_MODE_INT of a MODE_PARTIAL_INT mode.
* genmodes.c (make_vector_mode): Allow making VECTOR_MODE_INT of a
MODE_PARTIAL_INT mode.
* config/bfin/bfin-modes.def: Add V2PDI and V2SI.
* config/bfin/bfin.c (print_operand): Add macflag and mac/msu modifiers
for CONST_INTs.
(hard_regno_mode_ok): V2PDImode is ok for accumulators.
* config/bfin/bfin.h (CLASS_MAX_NREGS, HARD_REGNO_NREGS): Handle
V2PDImode.
* config/bfin/predicates.md (const01_operand, vec_shift_operand):
New predicates.
* config/bfin/bfin.md (UNSPEC_MUL_WITH_FLAG, UNSPEC_MAC_WITH_FLAG):
New constants.
(MACFLAG_NONE, MACFLAG_T, MACFLAG_FU, MACFLAG_TFU, MACFLAG_IS,
MACFLAG_IU, MACFLAG_W32, MACFLAG_M, MACFLAG_S2RND, MACFLAG_ISS2,
MACFLAG_IH): Likewise.
(movstricthi_1): Renamed from "*movstricthi".
(load_accumulator, load_accumulator_pair, movsi_insv, insv,
ssaddsi3, sssubsi3, ssnegsi2, signbitssi2, smaxhi3, sminhi3,
abshi2, neghi2, ssneghi2, signbitshi2, movhi_low2high,
movhi_high2high, movhi_low2low, movhi_high2low, movhiv2hi_low,
movhiv2hi_high, composev2hi, movv2hi_hi, movv2hi_hi_low,
movv2hi_hi_high, ssaddhi3, sssubhi3, ssaddv2hi3, sssubv2hi3,
addsubv2hi3, subaddv2hi3, ssaddsubv2hi3, sssubaddv2hi3,
sublohiv2hi3, subhilov2hi3, sssublohiv2hi3, sssubhilov2hi3,
addlohiv2hi3, addhilov2hi3, ssaddlohiv2hi3, ssaddhilov2hi3,
mulhisi_ll, mulhisi_lh, mulhisi_hl, mulhisi_hh, ssnegv2hi2,
ssashiftv2hi3, ssashifthi3, lshiftv2hi3, lshifthi3, packv2hi,
flag_mulhi, flag_mulhisi_parts, flag_machi, flag_machi_acconly,
flag_macinithi, flag_macinit1hi, flag_mulv2hi, flag_mulv2hi_parts,
flag_macv2hi_parts, flag_macv2hi_parts_acconly,
flag_macinitv2hi_parts, flag_macinit1v2hi_parts): New patterns.
From-SVN: r113245
2006-04-25 13:49:27 +02:00
|
|
|
|
(match_operand 7 "const_int_operand" "n")]
|
|
|
|
|
UNSPEC_MAC_WITH_FLAG))
|
|
|
|
|
(set (match_operand:V2PDI 8 "register_operand" "=e")
|
|
|
|
|
(unspec:V2PDI [(vec_concat:V2HI
|
|
|
|
|
(vec_select:HI (match_dup 1) (parallel [(match_dup 3)]))
|
|
|
|
|
(vec_select:HI (match_dup 1) (parallel [(match_dup 4)])))
|
|
|
|
|
(vec_concat:V2HI
|
|
|
|
|
(vec_select:HI (match_dup 2) (parallel [(match_dup 5)]))
|
|
|
|
|
(vec_select:HI (match_dup 2) (parallel [(match_dup 5)])))
|
|
|
|
|
(match_dup 7)]
|
|
|
|
|
UNSPEC_MAC_WITH_FLAG))]
|
|
|
|
|
""
|
|
|
|
|
{
|
|
|
|
|
const char *templates[] = {
|
rtlanal.c (note_uses): Deal with SEQUENCEs.
* rtlanal.c (note_uses): Deal with SEQUENCEs.
* config/bfin/bfin.c: Include "timevar.h".
(bfin_flag_schedule_insns2, splitting_for_sched,
bfin_flag_var_tracking): New variables.
(print_operand): Handle '%!'.
(override_options): Disable normal sched2 pass, instead set
bfin_flag_schedule_insns2 for reorg to handle it.
(output_file_start): Likewise for var-tracking.
(bfin_optimize_loop): Take some care not to stumble over SEQUENCEs.
(gen_one_bundle, bfin_gen_bundles, type_for_anomaly, trapping_loads_p):
New functions.
(bfin_reorg): Do second scheduling pass here, and call
bfin_gen_bundles. Use type_for_anomaly and trapping_loads_p instead
of examining insns directly. If bfin_flag_var_tracking, call
var-tracking pass when done with everything else.
* config/bfin/bfin.h (PRINT_OPERAND_PUNCT_VALID_P): '!' is valid.
* config/bfin/bfin.md (UNSPEC_32BIT): New constant.
(movsi_insn32): New pattern, with two new splits to create it
before the final scheduling pass.
(neghi2): Not a dsp32 insn, rather alu0.
(movbi, pushsi_insn, popsi_insn, movsi_insn, movv2hi_insn, movhi_insn,
movqi_insn, movsf_insn, movsi_insv, extendhisi2, zero_extendhisi2,
extendqihi2, extendqisi2, zero_extendqihi2, zero_extendqisi2,
mulhisi3, umulhisi3, ssadsi3, sssubsi3, smaxsi3, sminsi3, abssi2,
ssnegsi2, signbitssi2, smaxhi3, sminhi3, abshi2, ssneghi2, signbitshi2,
movhi_low2high, movhi_high2high, movhi_low2low, movhi_high2low,
movhiv2hi_low, movhiv2hi_high, composev2hi, packv2hi, movv2hi_hi,
ssaddhi3, sssubhi3, addv2hi3, ssaddv2hi3, subv2hi3, sssubv2hi3,
addsubv2hi3, subaddv2hi3, ssaddsubv2hi3, sssubaddv2hi3, sublohiv2hi3,
subhilov2hi3, sssublohiv2hi3, sssubhilov2hi3, addlohiv2hi3,
addhilov2hi3, ssaddlohiv2hi3, ssaddhilov2hi3, sminv2hi3, smaxv2hi3,
flag_mulhi, flag_mulhisi, flag_mulhisi_parts, flag_machi,
flag_machi_acconly, flag_macinithi, flag_macinit1hi, mulv2hi3,
flag_mulv2hi, flag_mulv2hi_parts, flag_macv2hi_parts,
flag_macv2hi_parts_acconly, flag_macinitv2hi_parts,
flag_macinit1v2hi_parts, mulhisi_ll, mulhisi_lh, mulhisi_hl,
mulhisi_hh, ssnegv2hi2, absv2hi2, ssashiftv2hi3, ssashifthi3,
lshiftv2hi3, lshifthi3): Use '%!' to terminate all dsp32/load/store
variants instead of ';'.
(ror_one, rol_one): Likewise. Make them dsp32 insns.
(ashlsi3_insn, ashrsi3, lshrsi3): Add dsp32 variants.
(align8, align16, align24): Now named patterns; also using '%!'.
(mnop): New insn.
From-SVN: r119534
2006-12-05 09:49:56 +01:00
|
|
|
|
"%h0 = (A0 = %h1 * %h2), %d0 = (A1 = %h1 * %h2) %M7%!",
|
|
|
|
|
"%h0 = (A0 = %d1 * %h2), %d0 = (A1 = %h1 * %h2) %M7%!",
|
|
|
|
|
"%h0 = (A0 = %h1 * %h2), %d0 = (A1 = %d1 * %h2) %M7%!",
|
|
|
|
|
"%h0 = (A0 = %d1 * %h2), %d0 = (A1 = %d1 * %h2) %M7%!",
|
|
|
|
|
"%h0 = (A0 = %h1 * %d2), %d0 = (A1 = %h1 * %h2) %M7%!",
|
|
|
|
|
"%h0 = (A0 = %d1 * %d2), %d0 = (A1 = %h1 * %h2) %M7%!",
|
|
|
|
|
"%h0 = (A0 = %h1 * %d2), %d0 = (A1 = %d1 * %h2) %M7%!",
|
|
|
|
|
"%h0 = (A0 = %d1 * %d2), %d0 = (A1 = %d1 * %h2) %M7%!",
|
|
|
|
|
"%h0 = (A0 = %h1 * %h2), %d0 = (A1 = %h1 * %d2) %M7%!",
|
|
|
|
|
"%h0 = (A0 = %d1 * %h2), %d0 = (A1 = %h1 * %d2) %M7%!",
|
|
|
|
|
"%h0 = (A0 = %h1 * %h2), %d0 = (A1 = %d1 * %d2) %M7%!",
|
|
|
|
|
"%h0 = (A0 = %d1 * %h2), %d0 = (A1 = %d1 * %d2) %M7%!",
|
|
|
|
|
"%h0 = (A0 = %h1 * %d2), %d0 = (A1 = %h1 * %d2) %M7%!",
|
|
|
|
|
"%h0 = (A0 = %d1 * %d2), %d0 = (A1 = %h1 * %d2) %M7%!",
|
|
|
|
|
"%h0 = (A0 = %h1 * %d2), %d0 = (A1 = %d1 * %d2) %M7%!",
|
|
|
|
|
"%h0 = (A0 = %d1 * %d2), %d0 = (A1 = %d1 * %d2) %M7%!" };
|
genmodes.c (make_vector_mode): Allow making VECTOR_MODE_INT of a MODE_PARTIAL_INT mode.
* genmodes.c (make_vector_mode): Allow making VECTOR_MODE_INT of a
MODE_PARTIAL_INT mode.
* config/bfin/bfin-modes.def: Add V2PDI and V2SI.
* config/bfin/bfin.c (print_operand): Add macflag and mac/msu modifiers
for CONST_INTs.
(hard_regno_mode_ok): V2PDImode is ok for accumulators.
* config/bfin/bfin.h (CLASS_MAX_NREGS, HARD_REGNO_NREGS): Handle
V2PDImode.
* config/bfin/predicates.md (const01_operand, vec_shift_operand):
New predicates.
* config/bfin/bfin.md (UNSPEC_MUL_WITH_FLAG, UNSPEC_MAC_WITH_FLAG):
New constants.
(MACFLAG_NONE, MACFLAG_T, MACFLAG_FU, MACFLAG_TFU, MACFLAG_IS,
MACFLAG_IU, MACFLAG_W32, MACFLAG_M, MACFLAG_S2RND, MACFLAG_ISS2,
MACFLAG_IH): Likewise.
(movstricthi_1): Renamed from "*movstricthi".
(load_accumulator, load_accumulator_pair, movsi_insv, insv,
ssaddsi3, sssubsi3, ssnegsi2, signbitssi2, smaxhi3, sminhi3,
abshi2, neghi2, ssneghi2, signbitshi2, movhi_low2high,
movhi_high2high, movhi_low2low, movhi_high2low, movhiv2hi_low,
movhiv2hi_high, composev2hi, movv2hi_hi, movv2hi_hi_low,
movv2hi_hi_high, ssaddhi3, sssubhi3, ssaddv2hi3, sssubv2hi3,
addsubv2hi3, subaddv2hi3, ssaddsubv2hi3, sssubaddv2hi3,
sublohiv2hi3, subhilov2hi3, sssublohiv2hi3, sssubhilov2hi3,
addlohiv2hi3, addhilov2hi3, ssaddlohiv2hi3, ssaddhilov2hi3,
mulhisi_ll, mulhisi_lh, mulhisi_hl, mulhisi_hh, ssnegv2hi2,
ssashiftv2hi3, ssashifthi3, lshiftv2hi3, lshifthi3, packv2hi,
flag_mulhi, flag_mulhisi_parts, flag_machi, flag_machi_acconly,
flag_macinithi, flag_macinit1hi, flag_mulv2hi, flag_mulv2hi_parts,
flag_macv2hi_parts, flag_macv2hi_parts_acconly,
flag_macinitv2hi_parts, flag_macinit1v2hi_parts): New patterns.
From-SVN: r113245
2006-04-25 13:49:27 +02:00
|
|
|
|
int alt = (INTVAL (operands[3]) + (INTVAL (operands[4]) << 1)
|
|
|
|
|
+ (INTVAL (operands[5]) << 2) + (INTVAL (operands[6]) << 3));
|
|
|
|
|
return templates[alt];
|
|
|
|
|
}
|
|
|
|
|
[(set_attr "type" "dsp32")])
|
|
|
|
|
|
|
|
|
|
(define_insn "flag_macinit1v2hi_parts"
|
|
|
|
|
[(set (match_operand:V2PDI 0 "register_operand" "=e")
|
|
|
|
|
(unspec:V2PDI [(vec_concat:V2HI
|
|
|
|
|
(vec_select:HI
|
|
|
|
|
(match_operand:V2HI 1 "register_operand" "d")
|
2006-05-04 13:03:41 +02:00
|
|
|
|
(parallel [(match_operand 3 "const01_operand" "P0P1")]))
|
genmodes.c (make_vector_mode): Allow making VECTOR_MODE_INT of a MODE_PARTIAL_INT mode.
* genmodes.c (make_vector_mode): Allow making VECTOR_MODE_INT of a
MODE_PARTIAL_INT mode.
* config/bfin/bfin-modes.def: Add V2PDI and V2SI.
* config/bfin/bfin.c (print_operand): Add macflag and mac/msu modifiers
for CONST_INTs.
(hard_regno_mode_ok): V2PDImode is ok for accumulators.
* config/bfin/bfin.h (CLASS_MAX_NREGS, HARD_REGNO_NREGS): Handle
V2PDImode.
* config/bfin/predicates.md (const01_operand, vec_shift_operand):
New predicates.
* config/bfin/bfin.md (UNSPEC_MUL_WITH_FLAG, UNSPEC_MAC_WITH_FLAG):
New constants.
(MACFLAG_NONE, MACFLAG_T, MACFLAG_FU, MACFLAG_TFU, MACFLAG_IS,
MACFLAG_IU, MACFLAG_W32, MACFLAG_M, MACFLAG_S2RND, MACFLAG_ISS2,
MACFLAG_IH): Likewise.
(movstricthi_1): Renamed from "*movstricthi".
(load_accumulator, load_accumulator_pair, movsi_insv, insv,
ssaddsi3, sssubsi3, ssnegsi2, signbitssi2, smaxhi3, sminhi3,
abshi2, neghi2, ssneghi2, signbitshi2, movhi_low2high,
movhi_high2high, movhi_low2low, movhi_high2low, movhiv2hi_low,
movhiv2hi_high, composev2hi, movv2hi_hi, movv2hi_hi_low,
movv2hi_hi_high, ssaddhi3, sssubhi3, ssaddv2hi3, sssubv2hi3,
addsubv2hi3, subaddv2hi3, ssaddsubv2hi3, sssubaddv2hi3,
sublohiv2hi3, subhilov2hi3, sssublohiv2hi3, sssubhilov2hi3,
addlohiv2hi3, addhilov2hi3, ssaddlohiv2hi3, ssaddhilov2hi3,
mulhisi_ll, mulhisi_lh, mulhisi_hl, mulhisi_hh, ssnegv2hi2,
ssashiftv2hi3, ssashifthi3, lshiftv2hi3, lshifthi3, packv2hi,
flag_mulhi, flag_mulhisi_parts, flag_machi, flag_machi_acconly,
flag_macinithi, flag_macinit1hi, flag_mulv2hi, flag_mulv2hi_parts,
flag_macv2hi_parts, flag_macv2hi_parts_acconly,
flag_macinitv2hi_parts, flag_macinit1v2hi_parts): New patterns.
From-SVN: r113245
2006-04-25 13:49:27 +02:00
|
|
|
|
(vec_select:HI
|
|
|
|
|
(match_dup 1)
|
2006-05-04 13:03:41 +02:00
|
|
|
|
(parallel [(match_operand 4 "const01_operand" "P0P1")])))
|
genmodes.c (make_vector_mode): Allow making VECTOR_MODE_INT of a MODE_PARTIAL_INT mode.
* genmodes.c (make_vector_mode): Allow making VECTOR_MODE_INT of a
MODE_PARTIAL_INT mode.
* config/bfin/bfin-modes.def: Add V2PDI and V2SI.
* config/bfin/bfin.c (print_operand): Add macflag and mac/msu modifiers
for CONST_INTs.
(hard_regno_mode_ok): V2PDImode is ok for accumulators.
* config/bfin/bfin.h (CLASS_MAX_NREGS, HARD_REGNO_NREGS): Handle
V2PDImode.
* config/bfin/predicates.md (const01_operand, vec_shift_operand):
New predicates.
* config/bfin/bfin.md (UNSPEC_MUL_WITH_FLAG, UNSPEC_MAC_WITH_FLAG):
New constants.
(MACFLAG_NONE, MACFLAG_T, MACFLAG_FU, MACFLAG_TFU, MACFLAG_IS,
MACFLAG_IU, MACFLAG_W32, MACFLAG_M, MACFLAG_S2RND, MACFLAG_ISS2,
MACFLAG_IH): Likewise.
(movstricthi_1): Renamed from "*movstricthi".
(load_accumulator, load_accumulator_pair, movsi_insv, insv,
ssaddsi3, sssubsi3, ssnegsi2, signbitssi2, smaxhi3, sminhi3,
abshi2, neghi2, ssneghi2, signbitshi2, movhi_low2high,
movhi_high2high, movhi_low2low, movhi_high2low, movhiv2hi_low,
movhiv2hi_high, composev2hi, movv2hi_hi, movv2hi_hi_low,
movv2hi_hi_high, ssaddhi3, sssubhi3, ssaddv2hi3, sssubv2hi3,
addsubv2hi3, subaddv2hi3, ssaddsubv2hi3, sssubaddv2hi3,
sublohiv2hi3, subhilov2hi3, sssublohiv2hi3, sssubhilov2hi3,
addlohiv2hi3, addhilov2hi3, ssaddlohiv2hi3, ssaddhilov2hi3,
mulhisi_ll, mulhisi_lh, mulhisi_hl, mulhisi_hh, ssnegv2hi2,
ssashiftv2hi3, ssashifthi3, lshiftv2hi3, lshifthi3, packv2hi,
flag_mulhi, flag_mulhisi_parts, flag_machi, flag_machi_acconly,
flag_macinithi, flag_macinit1hi, flag_mulv2hi, flag_mulv2hi_parts,
flag_macv2hi_parts, flag_macv2hi_parts_acconly,
flag_macinitv2hi_parts, flag_macinit1v2hi_parts): New patterns.
From-SVN: r113245
2006-04-25 13:49:27 +02:00
|
|
|
|
(vec_concat:V2HI
|
|
|
|
|
(vec_select:HI (match_operand:V2HI 2 "register_operand" "d")
|
2006-05-04 13:03:41 +02:00
|
|
|
|
(parallel [(match_operand 5 "const01_operand" "P0P1")]))
|
genmodes.c (make_vector_mode): Allow making VECTOR_MODE_INT of a MODE_PARTIAL_INT mode.
* genmodes.c (make_vector_mode): Allow making VECTOR_MODE_INT of a
MODE_PARTIAL_INT mode.
* config/bfin/bfin-modes.def: Add V2PDI and V2SI.
* config/bfin/bfin.c (print_operand): Add macflag and mac/msu modifiers
for CONST_INTs.
(hard_regno_mode_ok): V2PDImode is ok for accumulators.
* config/bfin/bfin.h (CLASS_MAX_NREGS, HARD_REGNO_NREGS): Handle
V2PDImode.
* config/bfin/predicates.md (const01_operand, vec_shift_operand):
New predicates.
* config/bfin/bfin.md (UNSPEC_MUL_WITH_FLAG, UNSPEC_MAC_WITH_FLAG):
New constants.
(MACFLAG_NONE, MACFLAG_T, MACFLAG_FU, MACFLAG_TFU, MACFLAG_IS,
MACFLAG_IU, MACFLAG_W32, MACFLAG_M, MACFLAG_S2RND, MACFLAG_ISS2,
MACFLAG_IH): Likewise.
(movstricthi_1): Renamed from "*movstricthi".
(load_accumulator, load_accumulator_pair, movsi_insv, insv,
ssaddsi3, sssubsi3, ssnegsi2, signbitssi2, smaxhi3, sminhi3,
abshi2, neghi2, ssneghi2, signbitshi2, movhi_low2high,
movhi_high2high, movhi_low2low, movhi_high2low, movhiv2hi_low,
movhiv2hi_high, composev2hi, movv2hi_hi, movv2hi_hi_low,
movv2hi_hi_high, ssaddhi3, sssubhi3, ssaddv2hi3, sssubv2hi3,
addsubv2hi3, subaddv2hi3, ssaddsubv2hi3, sssubaddv2hi3,
sublohiv2hi3, subhilov2hi3, sssublohiv2hi3, sssubhilov2hi3,
addlohiv2hi3, addhilov2hi3, ssaddlohiv2hi3, ssaddhilov2hi3,
mulhisi_ll, mulhisi_lh, mulhisi_hl, mulhisi_hh, ssnegv2hi2,
ssashiftv2hi3, ssashifthi3, lshiftv2hi3, lshifthi3, packv2hi,
flag_mulhi, flag_mulhisi_parts, flag_machi, flag_machi_acconly,
flag_macinithi, flag_macinit1hi, flag_mulv2hi, flag_mulv2hi_parts,
flag_macv2hi_parts, flag_macv2hi_parts_acconly,
flag_macinitv2hi_parts, flag_macinit1v2hi_parts): New patterns.
From-SVN: r113245
2006-04-25 13:49:27 +02:00
|
|
|
|
(vec_select:HI (match_dup 2)
|
2006-05-04 13:03:41 +02:00
|
|
|
|
(parallel [(match_operand 6 "const01_operand" "P0P1")])))
|
genmodes.c (make_vector_mode): Allow making VECTOR_MODE_INT of a MODE_PARTIAL_INT mode.
* genmodes.c (make_vector_mode): Allow making VECTOR_MODE_INT of a
MODE_PARTIAL_INT mode.
* config/bfin/bfin-modes.def: Add V2PDI and V2SI.
* config/bfin/bfin.c (print_operand): Add macflag and mac/msu modifiers
for CONST_INTs.
(hard_regno_mode_ok): V2PDImode is ok for accumulators.
* config/bfin/bfin.h (CLASS_MAX_NREGS, HARD_REGNO_NREGS): Handle
V2PDImode.
* config/bfin/predicates.md (const01_operand, vec_shift_operand):
New predicates.
* config/bfin/bfin.md (UNSPEC_MUL_WITH_FLAG, UNSPEC_MAC_WITH_FLAG):
New constants.
(MACFLAG_NONE, MACFLAG_T, MACFLAG_FU, MACFLAG_TFU, MACFLAG_IS,
MACFLAG_IU, MACFLAG_W32, MACFLAG_M, MACFLAG_S2RND, MACFLAG_ISS2,
MACFLAG_IH): Likewise.
(movstricthi_1): Renamed from "*movstricthi".
(load_accumulator, load_accumulator_pair, movsi_insv, insv,
ssaddsi3, sssubsi3, ssnegsi2, signbitssi2, smaxhi3, sminhi3,
abshi2, neghi2, ssneghi2, signbitshi2, movhi_low2high,
movhi_high2high, movhi_low2low, movhi_high2low, movhiv2hi_low,
movhiv2hi_high, composev2hi, movv2hi_hi, movv2hi_hi_low,
movv2hi_hi_high, ssaddhi3, sssubhi3, ssaddv2hi3, sssubv2hi3,
addsubv2hi3, subaddv2hi3, ssaddsubv2hi3, sssubaddv2hi3,
sublohiv2hi3, subhilov2hi3, sssublohiv2hi3, sssubhilov2hi3,
addlohiv2hi3, addhilov2hi3, ssaddlohiv2hi3, ssaddhilov2hi3,
mulhisi_ll, mulhisi_lh, mulhisi_hl, mulhisi_hh, ssnegv2hi2,
ssashiftv2hi3, ssashifthi3, lshiftv2hi3, lshifthi3, packv2hi,
flag_mulhi, flag_mulhisi_parts, flag_machi, flag_machi_acconly,
flag_macinithi, flag_macinit1hi, flag_mulv2hi, flag_mulv2hi_parts,
flag_macv2hi_parts, flag_macv2hi_parts_acconly,
flag_macinitv2hi_parts, flag_macinit1v2hi_parts): New patterns.
From-SVN: r113245
2006-04-25 13:49:27 +02:00
|
|
|
|
(match_operand 7 "const_int_operand" "n")]
|
|
|
|
|
UNSPEC_MAC_WITH_FLAG))]
|
|
|
|
|
""
|
|
|
|
|
{
|
|
|
|
|
const char *templates[] = {
|
rtlanal.c (note_uses): Deal with SEQUENCEs.
* rtlanal.c (note_uses): Deal with SEQUENCEs.
* config/bfin/bfin.c: Include "timevar.h".
(bfin_flag_schedule_insns2, splitting_for_sched,
bfin_flag_var_tracking): New variables.
(print_operand): Handle '%!'.
(override_options): Disable normal sched2 pass, instead set
bfin_flag_schedule_insns2 for reorg to handle it.
(output_file_start): Likewise for var-tracking.
(bfin_optimize_loop): Take some care not to stumble over SEQUENCEs.
(gen_one_bundle, bfin_gen_bundles, type_for_anomaly, trapping_loads_p):
New functions.
(bfin_reorg): Do second scheduling pass here, and call
bfin_gen_bundles. Use type_for_anomaly and trapping_loads_p instead
of examining insns directly. If bfin_flag_var_tracking, call
var-tracking pass when done with everything else.
* config/bfin/bfin.h (PRINT_OPERAND_PUNCT_VALID_P): '!' is valid.
* config/bfin/bfin.md (UNSPEC_32BIT): New constant.
(movsi_insn32): New pattern, with two new splits to create it
before the final scheduling pass.
(neghi2): Not a dsp32 insn, rather alu0.
(movbi, pushsi_insn, popsi_insn, movsi_insn, movv2hi_insn, movhi_insn,
movqi_insn, movsf_insn, movsi_insv, extendhisi2, zero_extendhisi2,
extendqihi2, extendqisi2, zero_extendqihi2, zero_extendqisi2,
mulhisi3, umulhisi3, ssadsi3, sssubsi3, smaxsi3, sminsi3, abssi2,
ssnegsi2, signbitssi2, smaxhi3, sminhi3, abshi2, ssneghi2, signbitshi2,
movhi_low2high, movhi_high2high, movhi_low2low, movhi_high2low,
movhiv2hi_low, movhiv2hi_high, composev2hi, packv2hi, movv2hi_hi,
ssaddhi3, sssubhi3, addv2hi3, ssaddv2hi3, subv2hi3, sssubv2hi3,
addsubv2hi3, subaddv2hi3, ssaddsubv2hi3, sssubaddv2hi3, sublohiv2hi3,
subhilov2hi3, sssublohiv2hi3, sssubhilov2hi3, addlohiv2hi3,
addhilov2hi3, ssaddlohiv2hi3, ssaddhilov2hi3, sminv2hi3, smaxv2hi3,
flag_mulhi, flag_mulhisi, flag_mulhisi_parts, flag_machi,
flag_machi_acconly, flag_macinithi, flag_macinit1hi, mulv2hi3,
flag_mulv2hi, flag_mulv2hi_parts, flag_macv2hi_parts,
flag_macv2hi_parts_acconly, flag_macinitv2hi_parts,
flag_macinit1v2hi_parts, mulhisi_ll, mulhisi_lh, mulhisi_hl,
mulhisi_hh, ssnegv2hi2, absv2hi2, ssashiftv2hi3, ssashifthi3,
lshiftv2hi3, lshifthi3): Use '%!' to terminate all dsp32/load/store
variants instead of ';'.
(ror_one, rol_one): Likewise. Make them dsp32 insns.
(ashlsi3_insn, ashrsi3, lshrsi3): Add dsp32 variants.
(align8, align16, align24): Now named patterns; also using '%!'.
(mnop): New insn.
From-SVN: r119534
2006-12-05 09:49:56 +01:00
|
|
|
|
"A0 = %h1 * %h2, A1 = %h1 * %h2 %M7%!",
|
|
|
|
|
"A0 = %d1 * %h2, A1 = %h1 * %h2 %M7%!",
|
|
|
|
|
"A0 = %h1 * %h2, A1 = %d1 * %h2 %M7%!",
|
|
|
|
|
"A0 = %d1 * %h2, A1 = %d1 * %h2 %M7%!",
|
|
|
|
|
"A0 = %h1 * %d2, A1 = %h1 * %h2 %M7%!",
|
|
|
|
|
"A0 = %d1 * %d2, A1 = %h1 * %h2 %M7%!",
|
|
|
|
|
"A0 = %h1 * %d2, A1 = %d1 * %h2 %M7%!",
|
|
|
|
|
"A0 = %d1 * %d2, A1 = %d1 * %h2 %M7%!",
|
|
|
|
|
"A0 = %h1 * %h2, A1 = %h1 * %d2 %M7%!",
|
|
|
|
|
"A0 = %d1 * %h2, A1 = %h1 * %d2 %M7%!",
|
|
|
|
|
"A0 = %h1 * %h2, A1 = %d1 * %d2 %M7%!",
|
|
|
|
|
"A0 = %d1 * %h2, A1 = %d1 * %d2 %M7%!",
|
|
|
|
|
"A0 = %h1 * %d2, A1 = %h1 * %d2 %M7%!",
|
|
|
|
|
"A0 = %d1 * %d2, A1 = %h1 * %d2 %M7%!",
|
|
|
|
|
"A0 = %h1 * %d2, A1 = %d1 * %d2 %M7%!",
|
|
|
|
|
"A0 = %d1 * %d2, A1 = %d1 * %d2 %M7%!" };
|
genmodes.c (make_vector_mode): Allow making VECTOR_MODE_INT of a MODE_PARTIAL_INT mode.
* genmodes.c (make_vector_mode): Allow making VECTOR_MODE_INT of a
MODE_PARTIAL_INT mode.
* config/bfin/bfin-modes.def: Add V2PDI and V2SI.
* config/bfin/bfin.c (print_operand): Add macflag and mac/msu modifiers
for CONST_INTs.
(hard_regno_mode_ok): V2PDImode is ok for accumulators.
* config/bfin/bfin.h (CLASS_MAX_NREGS, HARD_REGNO_NREGS): Handle
V2PDImode.
* config/bfin/predicates.md (const01_operand, vec_shift_operand):
New predicates.
* config/bfin/bfin.md (UNSPEC_MUL_WITH_FLAG, UNSPEC_MAC_WITH_FLAG):
New constants.
(MACFLAG_NONE, MACFLAG_T, MACFLAG_FU, MACFLAG_TFU, MACFLAG_IS,
MACFLAG_IU, MACFLAG_W32, MACFLAG_M, MACFLAG_S2RND, MACFLAG_ISS2,
MACFLAG_IH): Likewise.
(movstricthi_1): Renamed from "*movstricthi".
(load_accumulator, load_accumulator_pair, movsi_insv, insv,
ssaddsi3, sssubsi3, ssnegsi2, signbitssi2, smaxhi3, sminhi3,
abshi2, neghi2, ssneghi2, signbitshi2, movhi_low2high,
movhi_high2high, movhi_low2low, movhi_high2low, movhiv2hi_low,
movhiv2hi_high, composev2hi, movv2hi_hi, movv2hi_hi_low,
movv2hi_hi_high, ssaddhi3, sssubhi3, ssaddv2hi3, sssubv2hi3,
addsubv2hi3, subaddv2hi3, ssaddsubv2hi3, sssubaddv2hi3,
sublohiv2hi3, subhilov2hi3, sssublohiv2hi3, sssubhilov2hi3,
addlohiv2hi3, addhilov2hi3, ssaddlohiv2hi3, ssaddhilov2hi3,
mulhisi_ll, mulhisi_lh, mulhisi_hl, mulhisi_hh, ssnegv2hi2,
ssashiftv2hi3, ssashifthi3, lshiftv2hi3, lshifthi3, packv2hi,
flag_mulhi, flag_mulhisi_parts, flag_machi, flag_machi_acconly,
flag_macinithi, flag_macinit1hi, flag_mulv2hi, flag_mulv2hi_parts,
flag_macv2hi_parts, flag_macv2hi_parts_acconly,
flag_macinitv2hi_parts, flag_macinit1v2hi_parts): New patterns.
From-SVN: r113245
2006-04-25 13:49:27 +02:00
|
|
|
|
int alt = (INTVAL (operands[3]) + (INTVAL (operands[4]) << 1)
|
|
|
|
|
+ (INTVAL (operands[5]) << 2) + (INTVAL (operands[6]) << 3));
|
|
|
|
|
return templates[alt];
|
|
|
|
|
}
|
|
|
|
|
[(set_attr "type" "dsp32")])
|
|
|
|
|
|
2007-04-12 15:03:17 +02:00
|
|
|
|
;; A mixture of multiply and multiply-accumulate for when we only want to
|
|
|
|
|
;; initialize one part.
|
|
|
|
|
(define_insn "flag_mul_macv2hi_parts_acconly"
|
|
|
|
|
[(set (match_operand:PDI 0 "register_operand" "=B,e,e")
|
|
|
|
|
(unspec:PDI [(vec_select:HI
|
|
|
|
|
(match_operand:V2HI 2 "register_operand" "d,d,d")
|
|
|
|
|
(parallel [(match_operand 4 "const01_operand" "P0P1,P0P1,P0P1")]))
|
|
|
|
|
(vec_select:HI
|
|
|
|
|
(match_operand:V2HI 3 "register_operand" "d,d,d")
|
|
|
|
|
(parallel [(match_operand 6 "const01_operand" "P0P1,P0P1,P0P1")]))
|
|
|
|
|
(match_operand 10 "const_int_operand" "PB,PA,PA")]
|
|
|
|
|
UNSPEC_MUL_WITH_FLAG))
|
|
|
|
|
(set (match_operand:PDI 1 "register_operand" "=B,e,e")
|
|
|
|
|
(unspec:PDI [(vec_select:HI
|
|
|
|
|
(match_dup 2)
|
|
|
|
|
(parallel [(match_operand 5 "const01_operand" "P0P1,P0P1,P0P1")]))
|
|
|
|
|
(vec_select:HI
|
|
|
|
|
(match_dup 3)
|
|
|
|
|
(parallel [(match_operand 7 "const01_operand" "P0P1,P0P1,P0P1")]))
|
|
|
|
|
(match_operand:PDI 8 "register_operand" "1,1,1")
|
|
|
|
|
(match_operand 9 "const01_operand" "P0P1,P0P1,P0P1")
|
|
|
|
|
(match_operand 11 "const_int_operand" "PA,PB,PA")]
|
|
|
|
|
UNSPEC_MAC_WITH_FLAG))]
|
|
|
|
|
"MACFLAGS_MATCH_P (INTVAL (operands[10]), INTVAL (operands[11]))"
|
|
|
|
|
{
|
|
|
|
|
rtx xops[6];
|
|
|
|
|
const char *templates[] = {
|
|
|
|
|
"%0 = %h2 * %h3, %1 %b4 %h2 * %h3 %M5%!",
|
|
|
|
|
"%0 = %d2 * %h3, %1 %b4 %h2 * %h3 %M5%!",
|
|
|
|
|
"%0 = %h2 * %h3, %1 %b4 %d2 * %h3 %M5%!",
|
|
|
|
|
"%0 = %d2 * %h3, %1 %b4 %d2 * %h3 %M5%!",
|
|
|
|
|
"%0 = %h2 * %d3, %1 %b4 %h2 * %h3 %M5%!",
|
|
|
|
|
"%0 = %d2 * %d3, %1 %b4 %h2 * %h3 %M5%!",
|
|
|
|
|
"%0 = %h2 * %d3, %1 %b4 %d2 * %h3 %M5%!",
|
|
|
|
|
"%0 = %d2 * %d3, %1 %b4 %d2 * %h3 %M5%!",
|
|
|
|
|
"%0 = %h2 * %h3, %1 %b4 %h2 * %d3 %M5%!",
|
|
|
|
|
"%0 = %d2 * %h3, %1 %b4 %h2 * %d3 %M5%!",
|
|
|
|
|
"%0 = %h2 * %h3, %1 %b4 %d2 * %d3 %M5%!",
|
|
|
|
|
"%0 = %d2 * %h3, %1 %b4 %d2 * %d3 %M5%!",
|
|
|
|
|
"%0 = %h2 * %d3, %1 %b4 %h2 * %d3 %M5%!",
|
|
|
|
|
"%0 = %d2 * %d3, %1 %b4 %h2 * %d3 %M5%!",
|
|
|
|
|
"%0 = %h2 * %d3, %1 %b4 %d2 * %d3 %M5%!",
|
|
|
|
|
"%0 = %d2 * %d3, %1 %b4 %d2 * %d3 %M5%!" };
|
|
|
|
|
int alt = (INTVAL (operands[4]) + (INTVAL (operands[5]) << 1)
|
|
|
|
|
+ (INTVAL (operands[6]) << 2) + (INTVAL (operands[7]) << 3));
|
|
|
|
|
xops[0] = operands[0];
|
|
|
|
|
xops[1] = operands[1];
|
|
|
|
|
xops[2] = operands[2];
|
|
|
|
|
xops[3] = operands[3];
|
|
|
|
|
xops[4] = operands[9];
|
|
|
|
|
xops[5] = which_alternative == 0 ? operands[10] : operands[11];
|
|
|
|
|
output_asm_insn (templates[alt], xops);
|
|
|
|
|
return "";
|
|
|
|
|
}
|
|
|
|
|
[(set_attr "type" "dsp32")])
|
|
|
|
|
|
|
|
|
|
|
md.texi (Iterators): Renamed from Macros.
* doc/md.texi (Iterators): Renamed from Macros. All contents
changed to reflect rename of respectively define_code_macro and
define_mode_macro to define_code_iterator and define_mode_iterator.
(Mode Iterators, Code Iterators): Similar.
* read-rtl.c (struct iterator_group, struct iterator_traverse_data)
(uses_mode_iterator_p, apply_mode_iterator, uses_code_iterator_p)
(apply_iterator_to_string, uses_iterator_p, apply_iterator_traverse)
(initialize_iterators, find_iterator, check_code_iterator)
(map_attr_string, apply_mode_maps, apply_iterator_to_rtx, add_mapping)
(read_mapping, read_rtx_1): Similar.
* config/alpha/sync.md, config/alpha/alpha.md, config/frv/frv.md,
config/s390/s390.md, config/m32c/blkmov.md, config/m32c/m32c.md,
config/spu/spu.md, config/sparc/sparc.md, config/sparc/sync.md,
config/i386/i386.md, config/i386/mmx.md, config/i386/sse.md,
config/i386/sync.md, config/crx/crx.md, config/xtensa/xtensa.md,
config/cris/cris.c, config/cris/cris.md, config/ia64/sync.md,
config/ia64/div.md, config/ia64/vect.md, config/ia64/ia64.md,
config/m68k/m68k.md, config/rs6000/spe.md, config/rs6000/altivec.md,
config/rs6000/sync.md, config/rs6000/rs6000.md,
config/arm/vec-common.md, config/arm/neon.md, config/arm/iwmmxt.md,
config/arm/arm.md, config/mips/mips-dsp.md, config/mips/mips.md,
config/vax/vax.md, config/bfin/bfin.md: Similar.
From-SVN: r127715
2007-08-22 22:32:18 +02:00
|
|
|
|
(define_code_iterator s_or_u [sign_extend zero_extend])
|
bfin.h (enum reg_class, [...]): Add D0REGS through D7REGS.
* config/bfin/bfin.h (enum reg_class, REG_CLASS_NAMES,
REG_CLASS_CONTENTS): Add D0REGS through D7REGS.
(CONSTRAINT_LEN): Add entry for 'q'.
(REG_CLASS_FROM_CONSTRAINT): Renamed from REG_CLASS_FROM_LETTER.
Add 'q' constraints.
(REGNO_REG_CLASS): For R0 through R7, return corresponding regclass.
(CLASS_LIKELY_SPILLED_P): True for R0, R1 and R2.
* config/bfin/bfin.md (add_with_carry): New pattern.
(s_or_u, su_optab, su_modifier): New code macros/attrs.
(<su_optab>hisi_ll, <su_optab>hisi_lh, <su_optab>hisi_hl,
<su_optab>hisi_hh): Renamed from mulhisi_xx patterns; macroized to
support unsigned multiplies too. Removed incorrect commutativity from
operand 1 constraint where appropriate.
(usmulhisi_ull, usmulhisi_ulh, usmulhisi_uhl, usmulhisi_uhh): New
patterns.
(<su_optab>hisi_ll_lh, <su_optab>hisi_ll_hl, <su_optab>hisi_ll_hh,
<su_optab>hisi_lh_hl, <su_optab>hisi_lh_hh, <su_optab>hisi_hl_hh):
New patterns.
(usmulhisi_ll_lul, usmulhisi_ll_luh, usmulhisi_ll_hul,
usmulhisi_ll_huh, usmulhisi_lh_lul, usmulhisi_lh_luh, usmulhisi_lh_hul,
usmulhisi_lh_huh, usmulhisi_hl_lul, usmulhisi_hl_luh, usmulhisi_hl_hul,
usmulhisi_hl_huh, usmulhisi_hh_lul, usmulhisi_hh_luh, usmulhisi_hh_hul,
usmulhisi_hh_huh): New patterns.
From-SVN: r122373
2007-02-27 14:44:10 +01:00
|
|
|
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(define_code_attr su_optab [(sign_extend "mul")
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(zero_extend "umul")])
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(define_code_attr su_modifier [(sign_extend "IS")
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(zero_extend "FU")])
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(define_insn "<su_optab>hisi_ll"
|
genmodes.c (make_vector_mode): Allow making VECTOR_MODE_INT of a MODE_PARTIAL_INT mode.
* genmodes.c (make_vector_mode): Allow making VECTOR_MODE_INT of a
MODE_PARTIAL_INT mode.
* config/bfin/bfin-modes.def: Add V2PDI and V2SI.
* config/bfin/bfin.c (print_operand): Add macflag and mac/msu modifiers
for CONST_INTs.
(hard_regno_mode_ok): V2PDImode is ok for accumulators.
* config/bfin/bfin.h (CLASS_MAX_NREGS, HARD_REGNO_NREGS): Handle
V2PDImode.
* config/bfin/predicates.md (const01_operand, vec_shift_operand):
New predicates.
* config/bfin/bfin.md (UNSPEC_MUL_WITH_FLAG, UNSPEC_MAC_WITH_FLAG):
New constants.
(MACFLAG_NONE, MACFLAG_T, MACFLAG_FU, MACFLAG_TFU, MACFLAG_IS,
MACFLAG_IU, MACFLAG_W32, MACFLAG_M, MACFLAG_S2RND, MACFLAG_ISS2,
MACFLAG_IH): Likewise.
(movstricthi_1): Renamed from "*movstricthi".
(load_accumulator, load_accumulator_pair, movsi_insv, insv,
ssaddsi3, sssubsi3, ssnegsi2, signbitssi2, smaxhi3, sminhi3,
abshi2, neghi2, ssneghi2, signbitshi2, movhi_low2high,
movhi_high2high, movhi_low2low, movhi_high2low, movhiv2hi_low,
movhiv2hi_high, composev2hi, movv2hi_hi, movv2hi_hi_low,
movv2hi_hi_high, ssaddhi3, sssubhi3, ssaddv2hi3, sssubv2hi3,
addsubv2hi3, subaddv2hi3, ssaddsubv2hi3, sssubaddv2hi3,
sublohiv2hi3, subhilov2hi3, sssublohiv2hi3, sssubhilov2hi3,
addlohiv2hi3, addhilov2hi3, ssaddlohiv2hi3, ssaddhilov2hi3,
mulhisi_ll, mulhisi_lh, mulhisi_hl, mulhisi_hh, ssnegv2hi2,
ssashiftv2hi3, ssashifthi3, lshiftv2hi3, lshifthi3, packv2hi,
flag_mulhi, flag_mulhisi_parts, flag_machi, flag_machi_acconly,
flag_macinithi, flag_macinit1hi, flag_mulv2hi, flag_mulv2hi_parts,
flag_macv2hi_parts, flag_macv2hi_parts_acconly,
flag_macinitv2hi_parts, flag_macinit1v2hi_parts): New patterns.
From-SVN: r113245
2006-04-25 13:49:27 +02:00
|
|
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[(set (match_operand:SI 0 "register_operand" "=d")
|
bfin.h (enum reg_class, [...]): Add D0REGS through D7REGS.
* config/bfin/bfin.h (enum reg_class, REG_CLASS_NAMES,
REG_CLASS_CONTENTS): Add D0REGS through D7REGS.
(CONSTRAINT_LEN): Add entry for 'q'.
(REG_CLASS_FROM_CONSTRAINT): Renamed from REG_CLASS_FROM_LETTER.
Add 'q' constraints.
(REGNO_REG_CLASS): For R0 through R7, return corresponding regclass.
(CLASS_LIKELY_SPILLED_P): True for R0, R1 and R2.
* config/bfin/bfin.md (add_with_carry): New pattern.
(s_or_u, su_optab, su_modifier): New code macros/attrs.
(<su_optab>hisi_ll, <su_optab>hisi_lh, <su_optab>hisi_hl,
<su_optab>hisi_hh): Renamed from mulhisi_xx patterns; macroized to
support unsigned multiplies too. Removed incorrect commutativity from
operand 1 constraint where appropriate.
(usmulhisi_ull, usmulhisi_ulh, usmulhisi_uhl, usmulhisi_uhh): New
patterns.
(<su_optab>hisi_ll_lh, <su_optab>hisi_ll_hl, <su_optab>hisi_ll_hh,
<su_optab>hisi_lh_hl, <su_optab>hisi_lh_hh, <su_optab>hisi_hl_hh):
New patterns.
(usmulhisi_ll_lul, usmulhisi_ll_luh, usmulhisi_ll_hul,
usmulhisi_ll_huh, usmulhisi_lh_lul, usmulhisi_lh_luh, usmulhisi_lh_hul,
usmulhisi_lh_huh, usmulhisi_hl_lul, usmulhisi_hl_luh, usmulhisi_hl_hul,
usmulhisi_hl_huh, usmulhisi_hh_lul, usmulhisi_hh_luh, usmulhisi_hh_hul,
usmulhisi_hh_huh): New patterns.
From-SVN: r122373
2007-02-27 14:44:10 +01:00
|
|
|
|
(mult:SI (s_or_u:SI
|
genmodes.c (make_vector_mode): Allow making VECTOR_MODE_INT of a MODE_PARTIAL_INT mode.
* genmodes.c (make_vector_mode): Allow making VECTOR_MODE_INT of a
MODE_PARTIAL_INT mode.
* config/bfin/bfin-modes.def: Add V2PDI and V2SI.
* config/bfin/bfin.c (print_operand): Add macflag and mac/msu modifiers
for CONST_INTs.
(hard_regno_mode_ok): V2PDImode is ok for accumulators.
* config/bfin/bfin.h (CLASS_MAX_NREGS, HARD_REGNO_NREGS): Handle
V2PDImode.
* config/bfin/predicates.md (const01_operand, vec_shift_operand):
New predicates.
* config/bfin/bfin.md (UNSPEC_MUL_WITH_FLAG, UNSPEC_MAC_WITH_FLAG):
New constants.
(MACFLAG_NONE, MACFLAG_T, MACFLAG_FU, MACFLAG_TFU, MACFLAG_IS,
MACFLAG_IU, MACFLAG_W32, MACFLAG_M, MACFLAG_S2RND, MACFLAG_ISS2,
MACFLAG_IH): Likewise.
(movstricthi_1): Renamed from "*movstricthi".
(load_accumulator, load_accumulator_pair, movsi_insv, insv,
ssaddsi3, sssubsi3, ssnegsi2, signbitssi2, smaxhi3, sminhi3,
abshi2, neghi2, ssneghi2, signbitshi2, movhi_low2high,
movhi_high2high, movhi_low2low, movhi_high2low, movhiv2hi_low,
movhiv2hi_high, composev2hi, movv2hi_hi, movv2hi_hi_low,
movv2hi_hi_high, ssaddhi3, sssubhi3, ssaddv2hi3, sssubv2hi3,
addsubv2hi3, subaddv2hi3, ssaddsubv2hi3, sssubaddv2hi3,
sublohiv2hi3, subhilov2hi3, sssublohiv2hi3, sssubhilov2hi3,
addlohiv2hi3, addhilov2hi3, ssaddlohiv2hi3, ssaddhilov2hi3,
mulhisi_ll, mulhisi_lh, mulhisi_hl, mulhisi_hh, ssnegv2hi2,
ssashiftv2hi3, ssashifthi3, lshiftv2hi3, lshifthi3, packv2hi,
flag_mulhi, flag_mulhisi_parts, flag_machi, flag_machi_acconly,
flag_macinithi, flag_macinit1hi, flag_mulv2hi, flag_mulv2hi_parts,
flag_macv2hi_parts, flag_macv2hi_parts_acconly,
flag_macinitv2hi_parts, flag_macinit1v2hi_parts): New patterns.
From-SVN: r113245
2006-04-25 13:49:27 +02:00
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(vec_select:HI (match_operand:V2HI 1 "register_operand" "%d")
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(parallel [(const_int 0)])))
|
bfin.h (enum reg_class, [...]): Add D0REGS through D7REGS.
* config/bfin/bfin.h (enum reg_class, REG_CLASS_NAMES,
REG_CLASS_CONTENTS): Add D0REGS through D7REGS.
(CONSTRAINT_LEN): Add entry for 'q'.
(REG_CLASS_FROM_CONSTRAINT): Renamed from REG_CLASS_FROM_LETTER.
Add 'q' constraints.
(REGNO_REG_CLASS): For R0 through R7, return corresponding regclass.
(CLASS_LIKELY_SPILLED_P): True for R0, R1 and R2.
* config/bfin/bfin.md (add_with_carry): New pattern.
(s_or_u, su_optab, su_modifier): New code macros/attrs.
(<su_optab>hisi_ll, <su_optab>hisi_lh, <su_optab>hisi_hl,
<su_optab>hisi_hh): Renamed from mulhisi_xx patterns; macroized to
support unsigned multiplies too. Removed incorrect commutativity from
operand 1 constraint where appropriate.
(usmulhisi_ull, usmulhisi_ulh, usmulhisi_uhl, usmulhisi_uhh): New
patterns.
(<su_optab>hisi_ll_lh, <su_optab>hisi_ll_hl, <su_optab>hisi_ll_hh,
<su_optab>hisi_lh_hl, <su_optab>hisi_lh_hh, <su_optab>hisi_hl_hh):
New patterns.
(usmulhisi_ll_lul, usmulhisi_ll_luh, usmulhisi_ll_hul,
usmulhisi_ll_huh, usmulhisi_lh_lul, usmulhisi_lh_luh, usmulhisi_lh_hul,
usmulhisi_lh_huh, usmulhisi_hl_lul, usmulhisi_hl_luh, usmulhisi_hl_hul,
usmulhisi_hl_huh, usmulhisi_hh_lul, usmulhisi_hh_luh, usmulhisi_hh_hul,
usmulhisi_hh_huh): New patterns.
From-SVN: r122373
2007-02-27 14:44:10 +01:00
|
|
|
|
(s_or_u:SI
|
genmodes.c (make_vector_mode): Allow making VECTOR_MODE_INT of a MODE_PARTIAL_INT mode.
* genmodes.c (make_vector_mode): Allow making VECTOR_MODE_INT of a
MODE_PARTIAL_INT mode.
* config/bfin/bfin-modes.def: Add V2PDI and V2SI.
* config/bfin/bfin.c (print_operand): Add macflag and mac/msu modifiers
for CONST_INTs.
(hard_regno_mode_ok): V2PDImode is ok for accumulators.
* config/bfin/bfin.h (CLASS_MAX_NREGS, HARD_REGNO_NREGS): Handle
V2PDImode.
* config/bfin/predicates.md (const01_operand, vec_shift_operand):
New predicates.
* config/bfin/bfin.md (UNSPEC_MUL_WITH_FLAG, UNSPEC_MAC_WITH_FLAG):
New constants.
(MACFLAG_NONE, MACFLAG_T, MACFLAG_FU, MACFLAG_TFU, MACFLAG_IS,
MACFLAG_IU, MACFLAG_W32, MACFLAG_M, MACFLAG_S2RND, MACFLAG_ISS2,
MACFLAG_IH): Likewise.
(movstricthi_1): Renamed from "*movstricthi".
(load_accumulator, load_accumulator_pair, movsi_insv, insv,
ssaddsi3, sssubsi3, ssnegsi2, signbitssi2, smaxhi3, sminhi3,
abshi2, neghi2, ssneghi2, signbitshi2, movhi_low2high,
movhi_high2high, movhi_low2low, movhi_high2low, movhiv2hi_low,
movhiv2hi_high, composev2hi, movv2hi_hi, movv2hi_hi_low,
movv2hi_hi_high, ssaddhi3, sssubhi3, ssaddv2hi3, sssubv2hi3,
addsubv2hi3, subaddv2hi3, ssaddsubv2hi3, sssubaddv2hi3,
sublohiv2hi3, subhilov2hi3, sssublohiv2hi3, sssubhilov2hi3,
addlohiv2hi3, addhilov2hi3, ssaddlohiv2hi3, ssaddhilov2hi3,
mulhisi_ll, mulhisi_lh, mulhisi_hl, mulhisi_hh, ssnegv2hi2,
ssashiftv2hi3, ssashifthi3, lshiftv2hi3, lshifthi3, packv2hi,
flag_mulhi, flag_mulhisi_parts, flag_machi, flag_machi_acconly,
flag_macinithi, flag_macinit1hi, flag_mulv2hi, flag_mulv2hi_parts,
flag_macv2hi_parts, flag_macv2hi_parts_acconly,
flag_macinitv2hi_parts, flag_macinit1v2hi_parts): New patterns.
From-SVN: r113245
2006-04-25 13:49:27 +02:00
|
|
|
|
(vec_select:HI (match_operand:V2HI 2 "register_operand" "d")
|
|
|
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(parallel [(const_int 0)])))))]
|
|
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""
|
bfin.h (enum reg_class, [...]): Add D0REGS through D7REGS.
* config/bfin/bfin.h (enum reg_class, REG_CLASS_NAMES,
REG_CLASS_CONTENTS): Add D0REGS through D7REGS.
(CONSTRAINT_LEN): Add entry for 'q'.
(REG_CLASS_FROM_CONSTRAINT): Renamed from REG_CLASS_FROM_LETTER.
Add 'q' constraints.
(REGNO_REG_CLASS): For R0 through R7, return corresponding regclass.
(CLASS_LIKELY_SPILLED_P): True for R0, R1 and R2.
* config/bfin/bfin.md (add_with_carry): New pattern.
(s_or_u, su_optab, su_modifier): New code macros/attrs.
(<su_optab>hisi_ll, <su_optab>hisi_lh, <su_optab>hisi_hl,
<su_optab>hisi_hh): Renamed from mulhisi_xx patterns; macroized to
support unsigned multiplies too. Removed incorrect commutativity from
operand 1 constraint where appropriate.
(usmulhisi_ull, usmulhisi_ulh, usmulhisi_uhl, usmulhisi_uhh): New
patterns.
(<su_optab>hisi_ll_lh, <su_optab>hisi_ll_hl, <su_optab>hisi_ll_hh,
<su_optab>hisi_lh_hl, <su_optab>hisi_lh_hh, <su_optab>hisi_hl_hh):
New patterns.
(usmulhisi_ll_lul, usmulhisi_ll_luh, usmulhisi_ll_hul,
usmulhisi_ll_huh, usmulhisi_lh_lul, usmulhisi_lh_luh, usmulhisi_lh_hul,
usmulhisi_lh_huh, usmulhisi_hl_lul, usmulhisi_hl_luh, usmulhisi_hl_hul,
usmulhisi_hl_huh, usmulhisi_hh_lul, usmulhisi_hh_luh, usmulhisi_hh_hul,
usmulhisi_hh_huh): New patterns.
From-SVN: r122373
2007-02-27 14:44:10 +01:00
|
|
|
|
"%0 = %h1 * %h2 (<su_modifier>)%!"
|
genmodes.c (make_vector_mode): Allow making VECTOR_MODE_INT of a MODE_PARTIAL_INT mode.
* genmodes.c (make_vector_mode): Allow making VECTOR_MODE_INT of a
MODE_PARTIAL_INT mode.
* config/bfin/bfin-modes.def: Add V2PDI and V2SI.
* config/bfin/bfin.c (print_operand): Add macflag and mac/msu modifiers
for CONST_INTs.
(hard_regno_mode_ok): V2PDImode is ok for accumulators.
* config/bfin/bfin.h (CLASS_MAX_NREGS, HARD_REGNO_NREGS): Handle
V2PDImode.
* config/bfin/predicates.md (const01_operand, vec_shift_operand):
New predicates.
* config/bfin/bfin.md (UNSPEC_MUL_WITH_FLAG, UNSPEC_MAC_WITH_FLAG):
New constants.
(MACFLAG_NONE, MACFLAG_T, MACFLAG_FU, MACFLAG_TFU, MACFLAG_IS,
MACFLAG_IU, MACFLAG_W32, MACFLAG_M, MACFLAG_S2RND, MACFLAG_ISS2,
MACFLAG_IH): Likewise.
(movstricthi_1): Renamed from "*movstricthi".
(load_accumulator, load_accumulator_pair, movsi_insv, insv,
ssaddsi3, sssubsi3, ssnegsi2, signbitssi2, smaxhi3, sminhi3,
abshi2, neghi2, ssneghi2, signbitshi2, movhi_low2high,
movhi_high2high, movhi_low2low, movhi_high2low, movhiv2hi_low,
movhiv2hi_high, composev2hi, movv2hi_hi, movv2hi_hi_low,
movv2hi_hi_high, ssaddhi3, sssubhi3, ssaddv2hi3, sssubv2hi3,
addsubv2hi3, subaddv2hi3, ssaddsubv2hi3, sssubaddv2hi3,
sublohiv2hi3, subhilov2hi3, sssublohiv2hi3, sssubhilov2hi3,
addlohiv2hi3, addhilov2hi3, ssaddlohiv2hi3, ssaddhilov2hi3,
mulhisi_ll, mulhisi_lh, mulhisi_hl, mulhisi_hh, ssnegv2hi2,
ssashiftv2hi3, ssashifthi3, lshiftv2hi3, lshifthi3, packv2hi,
flag_mulhi, flag_mulhisi_parts, flag_machi, flag_machi_acconly,
flag_macinithi, flag_macinit1hi, flag_mulv2hi, flag_mulv2hi_parts,
flag_macv2hi_parts, flag_macv2hi_parts_acconly,
flag_macinitv2hi_parts, flag_macinit1v2hi_parts): New patterns.
From-SVN: r113245
2006-04-25 13:49:27 +02:00
|
|
|
|
[(set_attr "type" "dsp32")])
|
|
|
|
|
|
bfin.h (enum reg_class, [...]): Add D0REGS through D7REGS.
* config/bfin/bfin.h (enum reg_class, REG_CLASS_NAMES,
REG_CLASS_CONTENTS): Add D0REGS through D7REGS.
(CONSTRAINT_LEN): Add entry for 'q'.
(REG_CLASS_FROM_CONSTRAINT): Renamed from REG_CLASS_FROM_LETTER.
Add 'q' constraints.
(REGNO_REG_CLASS): For R0 through R7, return corresponding regclass.
(CLASS_LIKELY_SPILLED_P): True for R0, R1 and R2.
* config/bfin/bfin.md (add_with_carry): New pattern.
(s_or_u, su_optab, su_modifier): New code macros/attrs.
(<su_optab>hisi_ll, <su_optab>hisi_lh, <su_optab>hisi_hl,
<su_optab>hisi_hh): Renamed from mulhisi_xx patterns; macroized to
support unsigned multiplies too. Removed incorrect commutativity from
operand 1 constraint where appropriate.
(usmulhisi_ull, usmulhisi_ulh, usmulhisi_uhl, usmulhisi_uhh): New
patterns.
(<su_optab>hisi_ll_lh, <su_optab>hisi_ll_hl, <su_optab>hisi_ll_hh,
<su_optab>hisi_lh_hl, <su_optab>hisi_lh_hh, <su_optab>hisi_hl_hh):
New patterns.
(usmulhisi_ll_lul, usmulhisi_ll_luh, usmulhisi_ll_hul,
usmulhisi_ll_huh, usmulhisi_lh_lul, usmulhisi_lh_luh, usmulhisi_lh_hul,
usmulhisi_lh_huh, usmulhisi_hl_lul, usmulhisi_hl_luh, usmulhisi_hl_hul,
usmulhisi_hl_huh, usmulhisi_hh_lul, usmulhisi_hh_luh, usmulhisi_hh_hul,
usmulhisi_hh_huh): New patterns.
From-SVN: r122373
2007-02-27 14:44:10 +01:00
|
|
|
|
(define_insn "<su_optab>hisi_lh"
|
genmodes.c (make_vector_mode): Allow making VECTOR_MODE_INT of a MODE_PARTIAL_INT mode.
* genmodes.c (make_vector_mode): Allow making VECTOR_MODE_INT of a
MODE_PARTIAL_INT mode.
* config/bfin/bfin-modes.def: Add V2PDI and V2SI.
* config/bfin/bfin.c (print_operand): Add macflag and mac/msu modifiers
for CONST_INTs.
(hard_regno_mode_ok): V2PDImode is ok for accumulators.
* config/bfin/bfin.h (CLASS_MAX_NREGS, HARD_REGNO_NREGS): Handle
V2PDImode.
* config/bfin/predicates.md (const01_operand, vec_shift_operand):
New predicates.
* config/bfin/bfin.md (UNSPEC_MUL_WITH_FLAG, UNSPEC_MAC_WITH_FLAG):
New constants.
(MACFLAG_NONE, MACFLAG_T, MACFLAG_FU, MACFLAG_TFU, MACFLAG_IS,
MACFLAG_IU, MACFLAG_W32, MACFLAG_M, MACFLAG_S2RND, MACFLAG_ISS2,
MACFLAG_IH): Likewise.
(movstricthi_1): Renamed from "*movstricthi".
(load_accumulator, load_accumulator_pair, movsi_insv, insv,
ssaddsi3, sssubsi3, ssnegsi2, signbitssi2, smaxhi3, sminhi3,
abshi2, neghi2, ssneghi2, signbitshi2, movhi_low2high,
movhi_high2high, movhi_low2low, movhi_high2low, movhiv2hi_low,
movhiv2hi_high, composev2hi, movv2hi_hi, movv2hi_hi_low,
movv2hi_hi_high, ssaddhi3, sssubhi3, ssaddv2hi3, sssubv2hi3,
addsubv2hi3, subaddv2hi3, ssaddsubv2hi3, sssubaddv2hi3,
sublohiv2hi3, subhilov2hi3, sssublohiv2hi3, sssubhilov2hi3,
addlohiv2hi3, addhilov2hi3, ssaddlohiv2hi3, ssaddhilov2hi3,
mulhisi_ll, mulhisi_lh, mulhisi_hl, mulhisi_hh, ssnegv2hi2,
ssashiftv2hi3, ssashifthi3, lshiftv2hi3, lshifthi3, packv2hi,
flag_mulhi, flag_mulhisi_parts, flag_machi, flag_machi_acconly,
flag_macinithi, flag_macinit1hi, flag_mulv2hi, flag_mulv2hi_parts,
flag_macv2hi_parts, flag_macv2hi_parts_acconly,
flag_macinitv2hi_parts, flag_macinit1v2hi_parts): New patterns.
From-SVN: r113245
2006-04-25 13:49:27 +02:00
|
|
|
|
[(set (match_operand:SI 0 "register_operand" "=d")
|
bfin.h (enum reg_class, [...]): Add D0REGS through D7REGS.
* config/bfin/bfin.h (enum reg_class, REG_CLASS_NAMES,
REG_CLASS_CONTENTS): Add D0REGS through D7REGS.
(CONSTRAINT_LEN): Add entry for 'q'.
(REG_CLASS_FROM_CONSTRAINT): Renamed from REG_CLASS_FROM_LETTER.
Add 'q' constraints.
(REGNO_REG_CLASS): For R0 through R7, return corresponding regclass.
(CLASS_LIKELY_SPILLED_P): True for R0, R1 and R2.
* config/bfin/bfin.md (add_with_carry): New pattern.
(s_or_u, su_optab, su_modifier): New code macros/attrs.
(<su_optab>hisi_ll, <su_optab>hisi_lh, <su_optab>hisi_hl,
<su_optab>hisi_hh): Renamed from mulhisi_xx patterns; macroized to
support unsigned multiplies too. Removed incorrect commutativity from
operand 1 constraint where appropriate.
(usmulhisi_ull, usmulhisi_ulh, usmulhisi_uhl, usmulhisi_uhh): New
patterns.
(<su_optab>hisi_ll_lh, <su_optab>hisi_ll_hl, <su_optab>hisi_ll_hh,
<su_optab>hisi_lh_hl, <su_optab>hisi_lh_hh, <su_optab>hisi_hl_hh):
New patterns.
(usmulhisi_ll_lul, usmulhisi_ll_luh, usmulhisi_ll_hul,
usmulhisi_ll_huh, usmulhisi_lh_lul, usmulhisi_lh_luh, usmulhisi_lh_hul,
usmulhisi_lh_huh, usmulhisi_hl_lul, usmulhisi_hl_luh, usmulhisi_hl_hul,
usmulhisi_hl_huh, usmulhisi_hh_lul, usmulhisi_hh_luh, usmulhisi_hh_hul,
usmulhisi_hh_huh): New patterns.
From-SVN: r122373
2007-02-27 14:44:10 +01:00
|
|
|
|
(mult:SI (s_or_u:SI
|
|
|
|
|
(vec_select:HI (match_operand:V2HI 1 "register_operand" "d")
|
genmodes.c (make_vector_mode): Allow making VECTOR_MODE_INT of a MODE_PARTIAL_INT mode.
* genmodes.c (make_vector_mode): Allow making VECTOR_MODE_INT of a
MODE_PARTIAL_INT mode.
* config/bfin/bfin-modes.def: Add V2PDI and V2SI.
* config/bfin/bfin.c (print_operand): Add macflag and mac/msu modifiers
for CONST_INTs.
(hard_regno_mode_ok): V2PDImode is ok for accumulators.
* config/bfin/bfin.h (CLASS_MAX_NREGS, HARD_REGNO_NREGS): Handle
V2PDImode.
* config/bfin/predicates.md (const01_operand, vec_shift_operand):
New predicates.
* config/bfin/bfin.md (UNSPEC_MUL_WITH_FLAG, UNSPEC_MAC_WITH_FLAG):
New constants.
(MACFLAG_NONE, MACFLAG_T, MACFLAG_FU, MACFLAG_TFU, MACFLAG_IS,
MACFLAG_IU, MACFLAG_W32, MACFLAG_M, MACFLAG_S2RND, MACFLAG_ISS2,
MACFLAG_IH): Likewise.
(movstricthi_1): Renamed from "*movstricthi".
(load_accumulator, load_accumulator_pair, movsi_insv, insv,
ssaddsi3, sssubsi3, ssnegsi2, signbitssi2, smaxhi3, sminhi3,
abshi2, neghi2, ssneghi2, signbitshi2, movhi_low2high,
movhi_high2high, movhi_low2low, movhi_high2low, movhiv2hi_low,
movhiv2hi_high, composev2hi, movv2hi_hi, movv2hi_hi_low,
movv2hi_hi_high, ssaddhi3, sssubhi3, ssaddv2hi3, sssubv2hi3,
addsubv2hi3, subaddv2hi3, ssaddsubv2hi3, sssubaddv2hi3,
sublohiv2hi3, subhilov2hi3, sssublohiv2hi3, sssubhilov2hi3,
addlohiv2hi3, addhilov2hi3, ssaddlohiv2hi3, ssaddhilov2hi3,
mulhisi_ll, mulhisi_lh, mulhisi_hl, mulhisi_hh, ssnegv2hi2,
ssashiftv2hi3, ssashifthi3, lshiftv2hi3, lshifthi3, packv2hi,
flag_mulhi, flag_mulhisi_parts, flag_machi, flag_machi_acconly,
flag_macinithi, flag_macinit1hi, flag_mulv2hi, flag_mulv2hi_parts,
flag_macv2hi_parts, flag_macv2hi_parts_acconly,
flag_macinitv2hi_parts, flag_macinit1v2hi_parts): New patterns.
From-SVN: r113245
2006-04-25 13:49:27 +02:00
|
|
|
|
(parallel [(const_int 0)])))
|
bfin.h (enum reg_class, [...]): Add D0REGS through D7REGS.
* config/bfin/bfin.h (enum reg_class, REG_CLASS_NAMES,
REG_CLASS_CONTENTS): Add D0REGS through D7REGS.
(CONSTRAINT_LEN): Add entry for 'q'.
(REG_CLASS_FROM_CONSTRAINT): Renamed from REG_CLASS_FROM_LETTER.
Add 'q' constraints.
(REGNO_REG_CLASS): For R0 through R7, return corresponding regclass.
(CLASS_LIKELY_SPILLED_P): True for R0, R1 and R2.
* config/bfin/bfin.md (add_with_carry): New pattern.
(s_or_u, su_optab, su_modifier): New code macros/attrs.
(<su_optab>hisi_ll, <su_optab>hisi_lh, <su_optab>hisi_hl,
<su_optab>hisi_hh): Renamed from mulhisi_xx patterns; macroized to
support unsigned multiplies too. Removed incorrect commutativity from
operand 1 constraint where appropriate.
(usmulhisi_ull, usmulhisi_ulh, usmulhisi_uhl, usmulhisi_uhh): New
patterns.
(<su_optab>hisi_ll_lh, <su_optab>hisi_ll_hl, <su_optab>hisi_ll_hh,
<su_optab>hisi_lh_hl, <su_optab>hisi_lh_hh, <su_optab>hisi_hl_hh):
New patterns.
(usmulhisi_ll_lul, usmulhisi_ll_luh, usmulhisi_ll_hul,
usmulhisi_ll_huh, usmulhisi_lh_lul, usmulhisi_lh_luh, usmulhisi_lh_hul,
usmulhisi_lh_huh, usmulhisi_hl_lul, usmulhisi_hl_luh, usmulhisi_hl_hul,
usmulhisi_hl_huh, usmulhisi_hh_lul, usmulhisi_hh_luh, usmulhisi_hh_hul,
usmulhisi_hh_huh): New patterns.
From-SVN: r122373
2007-02-27 14:44:10 +01:00
|
|
|
|
(s_or_u:SI
|
genmodes.c (make_vector_mode): Allow making VECTOR_MODE_INT of a MODE_PARTIAL_INT mode.
* genmodes.c (make_vector_mode): Allow making VECTOR_MODE_INT of a
MODE_PARTIAL_INT mode.
* config/bfin/bfin-modes.def: Add V2PDI and V2SI.
* config/bfin/bfin.c (print_operand): Add macflag and mac/msu modifiers
for CONST_INTs.
(hard_regno_mode_ok): V2PDImode is ok for accumulators.
* config/bfin/bfin.h (CLASS_MAX_NREGS, HARD_REGNO_NREGS): Handle
V2PDImode.
* config/bfin/predicates.md (const01_operand, vec_shift_operand):
New predicates.
* config/bfin/bfin.md (UNSPEC_MUL_WITH_FLAG, UNSPEC_MAC_WITH_FLAG):
New constants.
(MACFLAG_NONE, MACFLAG_T, MACFLAG_FU, MACFLAG_TFU, MACFLAG_IS,
MACFLAG_IU, MACFLAG_W32, MACFLAG_M, MACFLAG_S2RND, MACFLAG_ISS2,
MACFLAG_IH): Likewise.
(movstricthi_1): Renamed from "*movstricthi".
(load_accumulator, load_accumulator_pair, movsi_insv, insv,
ssaddsi3, sssubsi3, ssnegsi2, signbitssi2, smaxhi3, sminhi3,
abshi2, neghi2, ssneghi2, signbitshi2, movhi_low2high,
movhi_high2high, movhi_low2low, movhi_high2low, movhiv2hi_low,
movhiv2hi_high, composev2hi, movv2hi_hi, movv2hi_hi_low,
movv2hi_hi_high, ssaddhi3, sssubhi3, ssaddv2hi3, sssubv2hi3,
addsubv2hi3, subaddv2hi3, ssaddsubv2hi3, sssubaddv2hi3,
sublohiv2hi3, subhilov2hi3, sssublohiv2hi3, sssubhilov2hi3,
addlohiv2hi3, addhilov2hi3, ssaddlohiv2hi3, ssaddhilov2hi3,
mulhisi_ll, mulhisi_lh, mulhisi_hl, mulhisi_hh, ssnegv2hi2,
ssashiftv2hi3, ssashifthi3, lshiftv2hi3, lshifthi3, packv2hi,
flag_mulhi, flag_mulhisi_parts, flag_machi, flag_machi_acconly,
flag_macinithi, flag_macinit1hi, flag_mulv2hi, flag_mulv2hi_parts,
flag_macv2hi_parts, flag_macv2hi_parts_acconly,
flag_macinitv2hi_parts, flag_macinit1v2hi_parts): New patterns.
From-SVN: r113245
2006-04-25 13:49:27 +02:00
|
|
|
|
(vec_select:HI (match_operand:V2HI 2 "register_operand" "d")
|
|
|
|
|
(parallel [(const_int 1)])))))]
|
|
|
|
|
""
|
bfin.h (enum reg_class, [...]): Add D0REGS through D7REGS.
* config/bfin/bfin.h (enum reg_class, REG_CLASS_NAMES,
REG_CLASS_CONTENTS): Add D0REGS through D7REGS.
(CONSTRAINT_LEN): Add entry for 'q'.
(REG_CLASS_FROM_CONSTRAINT): Renamed from REG_CLASS_FROM_LETTER.
Add 'q' constraints.
(REGNO_REG_CLASS): For R0 through R7, return corresponding regclass.
(CLASS_LIKELY_SPILLED_P): True for R0, R1 and R2.
* config/bfin/bfin.md (add_with_carry): New pattern.
(s_or_u, su_optab, su_modifier): New code macros/attrs.
(<su_optab>hisi_ll, <su_optab>hisi_lh, <su_optab>hisi_hl,
<su_optab>hisi_hh): Renamed from mulhisi_xx patterns; macroized to
support unsigned multiplies too. Removed incorrect commutativity from
operand 1 constraint where appropriate.
(usmulhisi_ull, usmulhisi_ulh, usmulhisi_uhl, usmulhisi_uhh): New
patterns.
(<su_optab>hisi_ll_lh, <su_optab>hisi_ll_hl, <su_optab>hisi_ll_hh,
<su_optab>hisi_lh_hl, <su_optab>hisi_lh_hh, <su_optab>hisi_hl_hh):
New patterns.
(usmulhisi_ll_lul, usmulhisi_ll_luh, usmulhisi_ll_hul,
usmulhisi_ll_huh, usmulhisi_lh_lul, usmulhisi_lh_luh, usmulhisi_lh_hul,
usmulhisi_lh_huh, usmulhisi_hl_lul, usmulhisi_hl_luh, usmulhisi_hl_hul,
usmulhisi_hl_huh, usmulhisi_hh_lul, usmulhisi_hh_luh, usmulhisi_hh_hul,
usmulhisi_hh_huh): New patterns.
From-SVN: r122373
2007-02-27 14:44:10 +01:00
|
|
|
|
"%0 = %h1 * %d2 (<su_modifier>)%!"
|
genmodes.c (make_vector_mode): Allow making VECTOR_MODE_INT of a MODE_PARTIAL_INT mode.
* genmodes.c (make_vector_mode): Allow making VECTOR_MODE_INT of a
MODE_PARTIAL_INT mode.
* config/bfin/bfin-modes.def: Add V2PDI and V2SI.
* config/bfin/bfin.c (print_operand): Add macflag and mac/msu modifiers
for CONST_INTs.
(hard_regno_mode_ok): V2PDImode is ok for accumulators.
* config/bfin/bfin.h (CLASS_MAX_NREGS, HARD_REGNO_NREGS): Handle
V2PDImode.
* config/bfin/predicates.md (const01_operand, vec_shift_operand):
New predicates.
* config/bfin/bfin.md (UNSPEC_MUL_WITH_FLAG, UNSPEC_MAC_WITH_FLAG):
New constants.
(MACFLAG_NONE, MACFLAG_T, MACFLAG_FU, MACFLAG_TFU, MACFLAG_IS,
MACFLAG_IU, MACFLAG_W32, MACFLAG_M, MACFLAG_S2RND, MACFLAG_ISS2,
MACFLAG_IH): Likewise.
(movstricthi_1): Renamed from "*movstricthi".
(load_accumulator, load_accumulator_pair, movsi_insv, insv,
ssaddsi3, sssubsi3, ssnegsi2, signbitssi2, smaxhi3, sminhi3,
abshi2, neghi2, ssneghi2, signbitshi2, movhi_low2high,
movhi_high2high, movhi_low2low, movhi_high2low, movhiv2hi_low,
movhiv2hi_high, composev2hi, movv2hi_hi, movv2hi_hi_low,
movv2hi_hi_high, ssaddhi3, sssubhi3, ssaddv2hi3, sssubv2hi3,
addsubv2hi3, subaddv2hi3, ssaddsubv2hi3, sssubaddv2hi3,
sublohiv2hi3, subhilov2hi3, sssublohiv2hi3, sssubhilov2hi3,
addlohiv2hi3, addhilov2hi3, ssaddlohiv2hi3, ssaddhilov2hi3,
mulhisi_ll, mulhisi_lh, mulhisi_hl, mulhisi_hh, ssnegv2hi2,
ssashiftv2hi3, ssashifthi3, lshiftv2hi3, lshifthi3, packv2hi,
flag_mulhi, flag_mulhisi_parts, flag_machi, flag_machi_acconly,
flag_macinithi, flag_macinit1hi, flag_mulv2hi, flag_mulv2hi_parts,
flag_macv2hi_parts, flag_macv2hi_parts_acconly,
flag_macinitv2hi_parts, flag_macinit1v2hi_parts): New patterns.
From-SVN: r113245
2006-04-25 13:49:27 +02:00
|
|
|
|
[(set_attr "type" "dsp32")])
|
|
|
|
|
|
bfin.h (enum reg_class, [...]): Add D0REGS through D7REGS.
* config/bfin/bfin.h (enum reg_class, REG_CLASS_NAMES,
REG_CLASS_CONTENTS): Add D0REGS through D7REGS.
(CONSTRAINT_LEN): Add entry for 'q'.
(REG_CLASS_FROM_CONSTRAINT): Renamed from REG_CLASS_FROM_LETTER.
Add 'q' constraints.
(REGNO_REG_CLASS): For R0 through R7, return corresponding regclass.
(CLASS_LIKELY_SPILLED_P): True for R0, R1 and R2.
* config/bfin/bfin.md (add_with_carry): New pattern.
(s_or_u, su_optab, su_modifier): New code macros/attrs.
(<su_optab>hisi_ll, <su_optab>hisi_lh, <su_optab>hisi_hl,
<su_optab>hisi_hh): Renamed from mulhisi_xx patterns; macroized to
support unsigned multiplies too. Removed incorrect commutativity from
operand 1 constraint where appropriate.
(usmulhisi_ull, usmulhisi_ulh, usmulhisi_uhl, usmulhisi_uhh): New
patterns.
(<su_optab>hisi_ll_lh, <su_optab>hisi_ll_hl, <su_optab>hisi_ll_hh,
<su_optab>hisi_lh_hl, <su_optab>hisi_lh_hh, <su_optab>hisi_hl_hh):
New patterns.
(usmulhisi_ll_lul, usmulhisi_ll_luh, usmulhisi_ll_hul,
usmulhisi_ll_huh, usmulhisi_lh_lul, usmulhisi_lh_luh, usmulhisi_lh_hul,
usmulhisi_lh_huh, usmulhisi_hl_lul, usmulhisi_hl_luh, usmulhisi_hl_hul,
usmulhisi_hl_huh, usmulhisi_hh_lul, usmulhisi_hh_luh, usmulhisi_hh_hul,
usmulhisi_hh_huh): New patterns.
From-SVN: r122373
2007-02-27 14:44:10 +01:00
|
|
|
|
(define_insn "<su_optab>hisi_hl"
|
genmodes.c (make_vector_mode): Allow making VECTOR_MODE_INT of a MODE_PARTIAL_INT mode.
* genmodes.c (make_vector_mode): Allow making VECTOR_MODE_INT of a
MODE_PARTIAL_INT mode.
* config/bfin/bfin-modes.def: Add V2PDI and V2SI.
* config/bfin/bfin.c (print_operand): Add macflag and mac/msu modifiers
for CONST_INTs.
(hard_regno_mode_ok): V2PDImode is ok for accumulators.
* config/bfin/bfin.h (CLASS_MAX_NREGS, HARD_REGNO_NREGS): Handle
V2PDImode.
* config/bfin/predicates.md (const01_operand, vec_shift_operand):
New predicates.
* config/bfin/bfin.md (UNSPEC_MUL_WITH_FLAG, UNSPEC_MAC_WITH_FLAG):
New constants.
(MACFLAG_NONE, MACFLAG_T, MACFLAG_FU, MACFLAG_TFU, MACFLAG_IS,
MACFLAG_IU, MACFLAG_W32, MACFLAG_M, MACFLAG_S2RND, MACFLAG_ISS2,
MACFLAG_IH): Likewise.
(movstricthi_1): Renamed from "*movstricthi".
(load_accumulator, load_accumulator_pair, movsi_insv, insv,
ssaddsi3, sssubsi3, ssnegsi2, signbitssi2, smaxhi3, sminhi3,
abshi2, neghi2, ssneghi2, signbitshi2, movhi_low2high,
movhi_high2high, movhi_low2low, movhi_high2low, movhiv2hi_low,
movhiv2hi_high, composev2hi, movv2hi_hi, movv2hi_hi_low,
movv2hi_hi_high, ssaddhi3, sssubhi3, ssaddv2hi3, sssubv2hi3,
addsubv2hi3, subaddv2hi3, ssaddsubv2hi3, sssubaddv2hi3,
sublohiv2hi3, subhilov2hi3, sssublohiv2hi3, sssubhilov2hi3,
addlohiv2hi3, addhilov2hi3, ssaddlohiv2hi3, ssaddhilov2hi3,
mulhisi_ll, mulhisi_lh, mulhisi_hl, mulhisi_hh, ssnegv2hi2,
ssashiftv2hi3, ssashifthi3, lshiftv2hi3, lshifthi3, packv2hi,
flag_mulhi, flag_mulhisi_parts, flag_machi, flag_machi_acconly,
flag_macinithi, flag_macinit1hi, flag_mulv2hi, flag_mulv2hi_parts,
flag_macv2hi_parts, flag_macv2hi_parts_acconly,
flag_macinitv2hi_parts, flag_macinit1v2hi_parts): New patterns.
From-SVN: r113245
2006-04-25 13:49:27 +02:00
|
|
|
|
[(set (match_operand:SI 0 "register_operand" "=d")
|
bfin.h (enum reg_class, [...]): Add D0REGS through D7REGS.
* config/bfin/bfin.h (enum reg_class, REG_CLASS_NAMES,
REG_CLASS_CONTENTS): Add D0REGS through D7REGS.
(CONSTRAINT_LEN): Add entry for 'q'.
(REG_CLASS_FROM_CONSTRAINT): Renamed from REG_CLASS_FROM_LETTER.
Add 'q' constraints.
(REGNO_REG_CLASS): For R0 through R7, return corresponding regclass.
(CLASS_LIKELY_SPILLED_P): True for R0, R1 and R2.
* config/bfin/bfin.md (add_with_carry): New pattern.
(s_or_u, su_optab, su_modifier): New code macros/attrs.
(<su_optab>hisi_ll, <su_optab>hisi_lh, <su_optab>hisi_hl,
<su_optab>hisi_hh): Renamed from mulhisi_xx patterns; macroized to
support unsigned multiplies too. Removed incorrect commutativity from
operand 1 constraint where appropriate.
(usmulhisi_ull, usmulhisi_ulh, usmulhisi_uhl, usmulhisi_uhh): New
patterns.
(<su_optab>hisi_ll_lh, <su_optab>hisi_ll_hl, <su_optab>hisi_ll_hh,
<su_optab>hisi_lh_hl, <su_optab>hisi_lh_hh, <su_optab>hisi_hl_hh):
New patterns.
(usmulhisi_ll_lul, usmulhisi_ll_luh, usmulhisi_ll_hul,
usmulhisi_ll_huh, usmulhisi_lh_lul, usmulhisi_lh_luh, usmulhisi_lh_hul,
usmulhisi_lh_huh, usmulhisi_hl_lul, usmulhisi_hl_luh, usmulhisi_hl_hul,
usmulhisi_hl_huh, usmulhisi_hh_lul, usmulhisi_hh_luh, usmulhisi_hh_hul,
usmulhisi_hh_huh): New patterns.
From-SVN: r122373
2007-02-27 14:44:10 +01:00
|
|
|
|
(mult:SI (s_or_u:SI
|
|
|
|
|
(vec_select:HI (match_operand:V2HI 1 "register_operand" "d")
|
|
|
|
|
(parallel [(const_int 1)])))
|
|
|
|
|
(s_or_u:SI
|
|
|
|
|
(vec_select:HI (match_operand:V2HI 2 "register_operand" "d")
|
|
|
|
|
(parallel [(const_int 0)])))))]
|
|
|
|
|
""
|
|
|
|
|
"%0 = %d1 * %h2 (<su_modifier>)%!"
|
|
|
|
|
[(set_attr "type" "dsp32")])
|
|
|
|
|
|
|
|
|
|
(define_insn "<su_optab>hisi_hh"
|
|
|
|
|
[(set (match_operand:SI 0 "register_operand" "=d")
|
|
|
|
|
(mult:SI (s_or_u:SI
|
genmodes.c (make_vector_mode): Allow making VECTOR_MODE_INT of a MODE_PARTIAL_INT mode.
* genmodes.c (make_vector_mode): Allow making VECTOR_MODE_INT of a
MODE_PARTIAL_INT mode.
* config/bfin/bfin-modes.def: Add V2PDI and V2SI.
* config/bfin/bfin.c (print_operand): Add macflag and mac/msu modifiers
for CONST_INTs.
(hard_regno_mode_ok): V2PDImode is ok for accumulators.
* config/bfin/bfin.h (CLASS_MAX_NREGS, HARD_REGNO_NREGS): Handle
V2PDImode.
* config/bfin/predicates.md (const01_operand, vec_shift_operand):
New predicates.
* config/bfin/bfin.md (UNSPEC_MUL_WITH_FLAG, UNSPEC_MAC_WITH_FLAG):
New constants.
(MACFLAG_NONE, MACFLAG_T, MACFLAG_FU, MACFLAG_TFU, MACFLAG_IS,
MACFLAG_IU, MACFLAG_W32, MACFLAG_M, MACFLAG_S2RND, MACFLAG_ISS2,
MACFLAG_IH): Likewise.
(movstricthi_1): Renamed from "*movstricthi".
(load_accumulator, load_accumulator_pair, movsi_insv, insv,
ssaddsi3, sssubsi3, ssnegsi2, signbitssi2, smaxhi3, sminhi3,
abshi2, neghi2, ssneghi2, signbitshi2, movhi_low2high,
movhi_high2high, movhi_low2low, movhi_high2low, movhiv2hi_low,
movhiv2hi_high, composev2hi, movv2hi_hi, movv2hi_hi_low,
movv2hi_hi_high, ssaddhi3, sssubhi3, ssaddv2hi3, sssubv2hi3,
addsubv2hi3, subaddv2hi3, ssaddsubv2hi3, sssubaddv2hi3,
sublohiv2hi3, subhilov2hi3, sssublohiv2hi3, sssubhilov2hi3,
addlohiv2hi3, addhilov2hi3, ssaddlohiv2hi3, ssaddhilov2hi3,
mulhisi_ll, mulhisi_lh, mulhisi_hl, mulhisi_hh, ssnegv2hi2,
ssashiftv2hi3, ssashifthi3, lshiftv2hi3, lshifthi3, packv2hi,
flag_mulhi, flag_mulhisi_parts, flag_machi, flag_machi_acconly,
flag_macinithi, flag_macinit1hi, flag_mulv2hi, flag_mulv2hi_parts,
flag_macv2hi_parts, flag_macv2hi_parts_acconly,
flag_macinitv2hi_parts, flag_macinit1v2hi_parts): New patterns.
From-SVN: r113245
2006-04-25 13:49:27 +02:00
|
|
|
|
(vec_select:HI (match_operand:V2HI 1 "register_operand" "%d")
|
|
|
|
|
(parallel [(const_int 1)])))
|
bfin.h (enum reg_class, [...]): Add D0REGS through D7REGS.
* config/bfin/bfin.h (enum reg_class, REG_CLASS_NAMES,
REG_CLASS_CONTENTS): Add D0REGS through D7REGS.
(CONSTRAINT_LEN): Add entry for 'q'.
(REG_CLASS_FROM_CONSTRAINT): Renamed from REG_CLASS_FROM_LETTER.
Add 'q' constraints.
(REGNO_REG_CLASS): For R0 through R7, return corresponding regclass.
(CLASS_LIKELY_SPILLED_P): True for R0, R1 and R2.
* config/bfin/bfin.md (add_with_carry): New pattern.
(s_or_u, su_optab, su_modifier): New code macros/attrs.
(<su_optab>hisi_ll, <su_optab>hisi_lh, <su_optab>hisi_hl,
<su_optab>hisi_hh): Renamed from mulhisi_xx patterns; macroized to
support unsigned multiplies too. Removed incorrect commutativity from
operand 1 constraint where appropriate.
(usmulhisi_ull, usmulhisi_ulh, usmulhisi_uhl, usmulhisi_uhh): New
patterns.
(<su_optab>hisi_ll_lh, <su_optab>hisi_ll_hl, <su_optab>hisi_ll_hh,
<su_optab>hisi_lh_hl, <su_optab>hisi_lh_hh, <su_optab>hisi_hl_hh):
New patterns.
(usmulhisi_ll_lul, usmulhisi_ll_luh, usmulhisi_ll_hul,
usmulhisi_ll_huh, usmulhisi_lh_lul, usmulhisi_lh_luh, usmulhisi_lh_hul,
usmulhisi_lh_huh, usmulhisi_hl_lul, usmulhisi_hl_luh, usmulhisi_hl_hul,
usmulhisi_hl_huh, usmulhisi_hh_lul, usmulhisi_hh_luh, usmulhisi_hh_hul,
usmulhisi_hh_huh): New patterns.
From-SVN: r122373
2007-02-27 14:44:10 +01:00
|
|
|
|
(s_or_u:SI
|
|
|
|
|
(vec_select:HI (match_operand:V2HI 2 "register_operand" "d")
|
|
|
|
|
(parallel [(const_int 1)])))))]
|
|
|
|
|
""
|
|
|
|
|
"%0 = %d1 * %d2 (<su_modifier>)%!"
|
|
|
|
|
[(set_attr "type" "dsp32")])
|
|
|
|
|
|
|
|
|
|
;; Additional variants for signed * unsigned multiply.
|
|
|
|
|
|
|
|
|
|
(define_insn "usmulhisi_ull"
|
|
|
|
|
[(set (match_operand:SI 0 "register_operand" "=W")
|
|
|
|
|
(mult:SI (zero_extend:SI
|
|
|
|
|
(vec_select:HI (match_operand:V2HI 1 "register_operand" "%d")
|
|
|
|
|
(parallel [(const_int 0)])))
|
genmodes.c (make_vector_mode): Allow making VECTOR_MODE_INT of a MODE_PARTIAL_INT mode.
* genmodes.c (make_vector_mode): Allow making VECTOR_MODE_INT of a
MODE_PARTIAL_INT mode.
* config/bfin/bfin-modes.def: Add V2PDI and V2SI.
* config/bfin/bfin.c (print_operand): Add macflag and mac/msu modifiers
for CONST_INTs.
(hard_regno_mode_ok): V2PDImode is ok for accumulators.
* config/bfin/bfin.h (CLASS_MAX_NREGS, HARD_REGNO_NREGS): Handle
V2PDImode.
* config/bfin/predicates.md (const01_operand, vec_shift_operand):
New predicates.
* config/bfin/bfin.md (UNSPEC_MUL_WITH_FLAG, UNSPEC_MAC_WITH_FLAG):
New constants.
(MACFLAG_NONE, MACFLAG_T, MACFLAG_FU, MACFLAG_TFU, MACFLAG_IS,
MACFLAG_IU, MACFLAG_W32, MACFLAG_M, MACFLAG_S2RND, MACFLAG_ISS2,
MACFLAG_IH): Likewise.
(movstricthi_1): Renamed from "*movstricthi".
(load_accumulator, load_accumulator_pair, movsi_insv, insv,
ssaddsi3, sssubsi3, ssnegsi2, signbitssi2, smaxhi3, sminhi3,
abshi2, neghi2, ssneghi2, signbitshi2, movhi_low2high,
movhi_high2high, movhi_low2low, movhi_high2low, movhiv2hi_low,
movhiv2hi_high, composev2hi, movv2hi_hi, movv2hi_hi_low,
movv2hi_hi_high, ssaddhi3, sssubhi3, ssaddv2hi3, sssubv2hi3,
addsubv2hi3, subaddv2hi3, ssaddsubv2hi3, sssubaddv2hi3,
sublohiv2hi3, subhilov2hi3, sssublohiv2hi3, sssubhilov2hi3,
addlohiv2hi3, addhilov2hi3, ssaddlohiv2hi3, ssaddhilov2hi3,
mulhisi_ll, mulhisi_lh, mulhisi_hl, mulhisi_hh, ssnegv2hi2,
ssashiftv2hi3, ssashifthi3, lshiftv2hi3, lshifthi3, packv2hi,
flag_mulhi, flag_mulhisi_parts, flag_machi, flag_machi_acconly,
flag_macinithi, flag_macinit1hi, flag_mulv2hi, flag_mulv2hi_parts,
flag_macv2hi_parts, flag_macv2hi_parts_acconly,
flag_macinitv2hi_parts, flag_macinit1v2hi_parts): New patterns.
From-SVN: r113245
2006-04-25 13:49:27 +02:00
|
|
|
|
(sign_extend:SI
|
|
|
|
|
(vec_select:HI (match_operand:V2HI 2 "register_operand" "d")
|
|
|
|
|
(parallel [(const_int 0)])))))]
|
|
|
|
|
""
|
bfin.h (enum reg_class, [...]): Add D0REGS through D7REGS.
* config/bfin/bfin.h (enum reg_class, REG_CLASS_NAMES,
REG_CLASS_CONTENTS): Add D0REGS through D7REGS.
(CONSTRAINT_LEN): Add entry for 'q'.
(REG_CLASS_FROM_CONSTRAINT): Renamed from REG_CLASS_FROM_LETTER.
Add 'q' constraints.
(REGNO_REG_CLASS): For R0 through R7, return corresponding regclass.
(CLASS_LIKELY_SPILLED_P): True for R0, R1 and R2.
* config/bfin/bfin.md (add_with_carry): New pattern.
(s_or_u, su_optab, su_modifier): New code macros/attrs.
(<su_optab>hisi_ll, <su_optab>hisi_lh, <su_optab>hisi_hl,
<su_optab>hisi_hh): Renamed from mulhisi_xx patterns; macroized to
support unsigned multiplies too. Removed incorrect commutativity from
operand 1 constraint where appropriate.
(usmulhisi_ull, usmulhisi_ulh, usmulhisi_uhl, usmulhisi_uhh): New
patterns.
(<su_optab>hisi_ll_lh, <su_optab>hisi_ll_hl, <su_optab>hisi_ll_hh,
<su_optab>hisi_lh_hl, <su_optab>hisi_lh_hh, <su_optab>hisi_hl_hh):
New patterns.
(usmulhisi_ll_lul, usmulhisi_ll_luh, usmulhisi_ll_hul,
usmulhisi_ll_huh, usmulhisi_lh_lul, usmulhisi_lh_luh, usmulhisi_lh_hul,
usmulhisi_lh_huh, usmulhisi_hl_lul, usmulhisi_hl_luh, usmulhisi_hl_hul,
usmulhisi_hl_huh, usmulhisi_hh_lul, usmulhisi_hh_luh, usmulhisi_hh_hul,
usmulhisi_hh_huh): New patterns.
From-SVN: r122373
2007-02-27 14:44:10 +01:00
|
|
|
|
"%0 = %h2 * %h1 (IS,M)%!"
|
genmodes.c (make_vector_mode): Allow making VECTOR_MODE_INT of a MODE_PARTIAL_INT mode.
* genmodes.c (make_vector_mode): Allow making VECTOR_MODE_INT of a
MODE_PARTIAL_INT mode.
* config/bfin/bfin-modes.def: Add V2PDI and V2SI.
* config/bfin/bfin.c (print_operand): Add macflag and mac/msu modifiers
for CONST_INTs.
(hard_regno_mode_ok): V2PDImode is ok for accumulators.
* config/bfin/bfin.h (CLASS_MAX_NREGS, HARD_REGNO_NREGS): Handle
V2PDImode.
* config/bfin/predicates.md (const01_operand, vec_shift_operand):
New predicates.
* config/bfin/bfin.md (UNSPEC_MUL_WITH_FLAG, UNSPEC_MAC_WITH_FLAG):
New constants.
(MACFLAG_NONE, MACFLAG_T, MACFLAG_FU, MACFLAG_TFU, MACFLAG_IS,
MACFLAG_IU, MACFLAG_W32, MACFLAG_M, MACFLAG_S2RND, MACFLAG_ISS2,
MACFLAG_IH): Likewise.
(movstricthi_1): Renamed from "*movstricthi".
(load_accumulator, load_accumulator_pair, movsi_insv, insv,
ssaddsi3, sssubsi3, ssnegsi2, signbitssi2, smaxhi3, sminhi3,
abshi2, neghi2, ssneghi2, signbitshi2, movhi_low2high,
movhi_high2high, movhi_low2low, movhi_high2low, movhiv2hi_low,
movhiv2hi_high, composev2hi, movv2hi_hi, movv2hi_hi_low,
movv2hi_hi_high, ssaddhi3, sssubhi3, ssaddv2hi3, sssubv2hi3,
addsubv2hi3, subaddv2hi3, ssaddsubv2hi3, sssubaddv2hi3,
sublohiv2hi3, subhilov2hi3, sssublohiv2hi3, sssubhilov2hi3,
addlohiv2hi3, addhilov2hi3, ssaddlohiv2hi3, ssaddhilov2hi3,
mulhisi_ll, mulhisi_lh, mulhisi_hl, mulhisi_hh, ssnegv2hi2,
ssashiftv2hi3, ssashifthi3, lshiftv2hi3, lshifthi3, packv2hi,
flag_mulhi, flag_mulhisi_parts, flag_machi, flag_machi_acconly,
flag_macinithi, flag_macinit1hi, flag_mulv2hi, flag_mulv2hi_parts,
flag_macv2hi_parts, flag_macv2hi_parts_acconly,
flag_macinitv2hi_parts, flag_macinit1v2hi_parts): New patterns.
From-SVN: r113245
2006-04-25 13:49:27 +02:00
|
|
|
|
[(set_attr "type" "dsp32")])
|
|
|
|
|
|
bfin.h (enum reg_class, [...]): Add D0REGS through D7REGS.
* config/bfin/bfin.h (enum reg_class, REG_CLASS_NAMES,
REG_CLASS_CONTENTS): Add D0REGS through D7REGS.
(CONSTRAINT_LEN): Add entry for 'q'.
(REG_CLASS_FROM_CONSTRAINT): Renamed from REG_CLASS_FROM_LETTER.
Add 'q' constraints.
(REGNO_REG_CLASS): For R0 through R7, return corresponding regclass.
(CLASS_LIKELY_SPILLED_P): True for R0, R1 and R2.
* config/bfin/bfin.md (add_with_carry): New pattern.
(s_or_u, su_optab, su_modifier): New code macros/attrs.
(<su_optab>hisi_ll, <su_optab>hisi_lh, <su_optab>hisi_hl,
<su_optab>hisi_hh): Renamed from mulhisi_xx patterns; macroized to
support unsigned multiplies too. Removed incorrect commutativity from
operand 1 constraint where appropriate.
(usmulhisi_ull, usmulhisi_ulh, usmulhisi_uhl, usmulhisi_uhh): New
patterns.
(<su_optab>hisi_ll_lh, <su_optab>hisi_ll_hl, <su_optab>hisi_ll_hh,
<su_optab>hisi_lh_hl, <su_optab>hisi_lh_hh, <su_optab>hisi_hl_hh):
New patterns.
(usmulhisi_ll_lul, usmulhisi_ll_luh, usmulhisi_ll_hul,
usmulhisi_ll_huh, usmulhisi_lh_lul, usmulhisi_lh_luh, usmulhisi_lh_hul,
usmulhisi_lh_huh, usmulhisi_hl_lul, usmulhisi_hl_luh, usmulhisi_hl_hul,
usmulhisi_hl_huh, usmulhisi_hh_lul, usmulhisi_hh_luh, usmulhisi_hh_hul,
usmulhisi_hh_huh): New patterns.
From-SVN: r122373
2007-02-27 14:44:10 +01:00
|
|
|
|
(define_insn "usmulhisi_ulh"
|
|
|
|
|
[(set (match_operand:SI 0 "register_operand" "=W")
|
|
|
|
|
(mult:SI (zero_extend:SI
|
|
|
|
|
(vec_select:HI (match_operand:V2HI 1 "register_operand" "d")
|
|
|
|
|
(parallel [(const_int 0)])))
|
|
|
|
|
(sign_extend:SI
|
|
|
|
|
(vec_select:HI (match_operand:V2HI 2 "register_operand" "d")
|
|
|
|
|
(parallel [(const_int 1)])))))]
|
|
|
|
|
""
|
|
|
|
|
"%0 = %d2 * %h1 (IS,M)%!"
|
|
|
|
|
[(set_attr "type" "dsp32")])
|
|
|
|
|
|
|
|
|
|
(define_insn "usmulhisi_uhl"
|
|
|
|
|
[(set (match_operand:SI 0 "register_operand" "=W")
|
|
|
|
|
(mult:SI (zero_extend:SI
|
|
|
|
|
(vec_select:HI (match_operand:V2HI 1 "register_operand" "d")
|
|
|
|
|
(parallel [(const_int 1)])))
|
|
|
|
|
(sign_extend:SI
|
|
|
|
|
(vec_select:HI (match_operand:V2HI 2 "register_operand" "d")
|
|
|
|
|
(parallel [(const_int 0)])))))]
|
|
|
|
|
""
|
|
|
|
|
"%0 = %h2 * %d1 (IS,M)%!"
|
|
|
|
|
[(set_attr "type" "dsp32")])
|
|
|
|
|
|
|
|
|
|
(define_insn "usmulhisi_uhh"
|
|
|
|
|
[(set (match_operand:SI 0 "register_operand" "=W")
|
|
|
|
|
(mult:SI (zero_extend:SI
|
genmodes.c (make_vector_mode): Allow making VECTOR_MODE_INT of a MODE_PARTIAL_INT mode.
* genmodes.c (make_vector_mode): Allow making VECTOR_MODE_INT of a
MODE_PARTIAL_INT mode.
* config/bfin/bfin-modes.def: Add V2PDI and V2SI.
* config/bfin/bfin.c (print_operand): Add macflag and mac/msu modifiers
for CONST_INTs.
(hard_regno_mode_ok): V2PDImode is ok for accumulators.
* config/bfin/bfin.h (CLASS_MAX_NREGS, HARD_REGNO_NREGS): Handle
V2PDImode.
* config/bfin/predicates.md (const01_operand, vec_shift_operand):
New predicates.
* config/bfin/bfin.md (UNSPEC_MUL_WITH_FLAG, UNSPEC_MAC_WITH_FLAG):
New constants.
(MACFLAG_NONE, MACFLAG_T, MACFLAG_FU, MACFLAG_TFU, MACFLAG_IS,
MACFLAG_IU, MACFLAG_W32, MACFLAG_M, MACFLAG_S2RND, MACFLAG_ISS2,
MACFLAG_IH): Likewise.
(movstricthi_1): Renamed from "*movstricthi".
(load_accumulator, load_accumulator_pair, movsi_insv, insv,
ssaddsi3, sssubsi3, ssnegsi2, signbitssi2, smaxhi3, sminhi3,
abshi2, neghi2, ssneghi2, signbitshi2, movhi_low2high,
movhi_high2high, movhi_low2low, movhi_high2low, movhiv2hi_low,
movhiv2hi_high, composev2hi, movv2hi_hi, movv2hi_hi_low,
movv2hi_hi_high, ssaddhi3, sssubhi3, ssaddv2hi3, sssubv2hi3,
addsubv2hi3, subaddv2hi3, ssaddsubv2hi3, sssubaddv2hi3,
sublohiv2hi3, subhilov2hi3, sssublohiv2hi3, sssubhilov2hi3,
addlohiv2hi3, addhilov2hi3, ssaddlohiv2hi3, ssaddhilov2hi3,
mulhisi_ll, mulhisi_lh, mulhisi_hl, mulhisi_hh, ssnegv2hi2,
ssashiftv2hi3, ssashifthi3, lshiftv2hi3, lshifthi3, packv2hi,
flag_mulhi, flag_mulhisi_parts, flag_machi, flag_machi_acconly,
flag_macinithi, flag_macinit1hi, flag_mulv2hi, flag_mulv2hi_parts,
flag_macv2hi_parts, flag_macv2hi_parts_acconly,
flag_macinitv2hi_parts, flag_macinit1v2hi_parts): New patterns.
From-SVN: r113245
2006-04-25 13:49:27 +02:00
|
|
|
|
(vec_select:HI (match_operand:V2HI 1 "register_operand" "%d")
|
|
|
|
|
(parallel [(const_int 1)])))
|
|
|
|
|
(sign_extend:SI
|
|
|
|
|
(vec_select:HI (match_operand:V2HI 2 "register_operand" "d")
|
|
|
|
|
(parallel [(const_int 1)])))))]
|
|
|
|
|
""
|
bfin.h (enum reg_class, [...]): Add D0REGS through D7REGS.
* config/bfin/bfin.h (enum reg_class, REG_CLASS_NAMES,
REG_CLASS_CONTENTS): Add D0REGS through D7REGS.
(CONSTRAINT_LEN): Add entry for 'q'.
(REG_CLASS_FROM_CONSTRAINT): Renamed from REG_CLASS_FROM_LETTER.
Add 'q' constraints.
(REGNO_REG_CLASS): For R0 through R7, return corresponding regclass.
(CLASS_LIKELY_SPILLED_P): True for R0, R1 and R2.
* config/bfin/bfin.md (add_with_carry): New pattern.
(s_or_u, su_optab, su_modifier): New code macros/attrs.
(<su_optab>hisi_ll, <su_optab>hisi_lh, <su_optab>hisi_hl,
<su_optab>hisi_hh): Renamed from mulhisi_xx patterns; macroized to
support unsigned multiplies too. Removed incorrect commutativity from
operand 1 constraint where appropriate.
(usmulhisi_ull, usmulhisi_ulh, usmulhisi_uhl, usmulhisi_uhh): New
patterns.
(<su_optab>hisi_ll_lh, <su_optab>hisi_ll_hl, <su_optab>hisi_ll_hh,
<su_optab>hisi_lh_hl, <su_optab>hisi_lh_hh, <su_optab>hisi_hl_hh):
New patterns.
(usmulhisi_ll_lul, usmulhisi_ll_luh, usmulhisi_ll_hul,
usmulhisi_ll_huh, usmulhisi_lh_lul, usmulhisi_lh_luh, usmulhisi_lh_hul,
usmulhisi_lh_huh, usmulhisi_hl_lul, usmulhisi_hl_luh, usmulhisi_hl_hul,
usmulhisi_hl_huh, usmulhisi_hh_lul, usmulhisi_hh_luh, usmulhisi_hh_hul,
usmulhisi_hh_huh): New patterns.
From-SVN: r122373
2007-02-27 14:44:10 +01:00
|
|
|
|
"%0 = %d2 * %d1 (IS,M)%!"
|
|
|
|
|
[(set_attr "type" "dsp32")])
|
|
|
|
|
|
|
|
|
|
;; Parallel versions of these operations. First, normal signed or unsigned
|
|
|
|
|
;; multiplies.
|
|
|
|
|
|
|
|
|
|
(define_insn "<su_optab>hisi_ll_lh"
|
|
|
|
|
[(set (match_operand:SI 0 "register_operand" "=q0,q2,q4,q6")
|
|
|
|
|
(mult:SI (s_or_u:SI
|
|
|
|
|
(vec_select:HI (match_operand:V2HI 1 "register_operand" "d,d,d,d")
|
|
|
|
|
(parallel [(const_int 0)])))
|
|
|
|
|
(s_or_u:SI
|
|
|
|
|
(vec_select:HI (match_operand:V2HI 2 "register_operand" "d,d,d,d")
|
|
|
|
|
(parallel [(const_int 0)])))))
|
|
|
|
|
(set (match_operand:SI 3 "register_operand" "=q1,q3,q5,q7")
|
|
|
|
|
(mult:SI (s_or_u:SI
|
|
|
|
|
(vec_select:HI (match_dup 1) (parallel [(const_int 0)])))
|
|
|
|
|
(s_or_u:SI
|
|
|
|
|
(vec_select:HI (match_dup 2) (parallel [(const_int 1)])))))]
|
|
|
|
|
""
|
|
|
|
|
"%0 = %h1 * %h2, %3 = %h1 * %d2 (<su_modifier>)%!"
|
|
|
|
|
[(set_attr "type" "dsp32")])
|
|
|
|
|
|
|
|
|
|
(define_insn "<su_optab>hisi_ll_hl"
|
|
|
|
|
[(set (match_operand:SI 0 "register_operand" "=q0,q2,q4,q6")
|
|
|
|
|
(mult:SI (s_or_u:SI
|
|
|
|
|
(vec_select:HI (match_operand:V2HI 1 "register_operand" "d,d,d,d")
|
|
|
|
|
(parallel [(const_int 0)])))
|
|
|
|
|
(s_or_u:SI
|
|
|
|
|
(vec_select:HI (match_operand:V2HI 2 "register_operand" "d,d,d,d")
|
|
|
|
|
(parallel [(const_int 0)])))))
|
|
|
|
|
(set (match_operand:SI 3 "register_operand" "=q1,q3,q5,q7")
|
|
|
|
|
(mult:SI (s_or_u:SI
|
|
|
|
|
(vec_select:HI (match_dup 1) (parallel [(const_int 1)])))
|
|
|
|
|
(s_or_u:SI
|
|
|
|
|
(vec_select:HI (match_dup 2) (parallel [(const_int 0)])))))]
|
|
|
|
|
""
|
|
|
|
|
"%0 = %h1 * %h2, %3 = %d1 * %h2 (<su_modifier>)%!"
|
|
|
|
|
[(set_attr "type" "dsp32")])
|
|
|
|
|
|
|
|
|
|
(define_insn "<su_optab>hisi_ll_hh"
|
|
|
|
|
[(set (match_operand:SI 0 "register_operand" "=q0,q2,q4,q6")
|
|
|
|
|
(mult:SI (s_or_u:SI
|
|
|
|
|
(vec_select:HI (match_operand:V2HI 1 "register_operand" "d,d,d,d")
|
|
|
|
|
(parallel [(const_int 0)])))
|
|
|
|
|
(s_or_u:SI
|
|
|
|
|
(vec_select:HI (match_operand:V2HI 2 "register_operand" "d,d,d,d")
|
|
|
|
|
(parallel [(const_int 0)])))))
|
|
|
|
|
(set (match_operand:SI 3 "register_operand" "=q1,q3,q5,q7")
|
|
|
|
|
(mult:SI (s_or_u:SI
|
|
|
|
|
(vec_select:HI (match_dup 1) (parallel [(const_int 1)])))
|
|
|
|
|
(s_or_u:SI
|
|
|
|
|
(vec_select:HI (match_dup 2) (parallel [(const_int 1)])))))]
|
|
|
|
|
""
|
|
|
|
|
"%0 = %h1 * %h2, %3 = %d1 * %d2 (<su_modifier>)%!"
|
|
|
|
|
[(set_attr "type" "dsp32")])
|
|
|
|
|
|
|
|
|
|
(define_insn "<su_optab>hisi_lh_hl"
|
|
|
|
|
[(set (match_operand:SI 0 "register_operand" "=q0,q2,q4,q6")
|
|
|
|
|
(mult:SI (s_or_u:SI
|
|
|
|
|
(vec_select:HI (match_operand:V2HI 1 "register_operand" "d,d,d,d")
|
|
|
|
|
(parallel [(const_int 0)])))
|
|
|
|
|
(s_or_u:SI
|
|
|
|
|
(vec_select:HI (match_operand:V2HI 2 "register_operand" "d,d,d,d")
|
|
|
|
|
(parallel [(const_int 1)])))))
|
|
|
|
|
(set (match_operand:SI 3 "register_operand" "=q1,q3,q5,q7")
|
|
|
|
|
(mult:SI (s_or_u:SI
|
|
|
|
|
(vec_select:HI (match_dup 1) (parallel [(const_int 1)])))
|
|
|
|
|
(s_or_u:SI
|
|
|
|
|
(vec_select:HI (match_dup 2) (parallel [(const_int 0)])))))]
|
|
|
|
|
""
|
|
|
|
|
"%0 = %h1 * %d2, %3 = %d1 * %h2 (<su_modifier>)%!"
|
|
|
|
|
[(set_attr "type" "dsp32")])
|
|
|
|
|
|
|
|
|
|
(define_insn "<su_optab>hisi_lh_hh"
|
|
|
|
|
[(set (match_operand:SI 0 "register_operand" "=q0,q2,q4,q6")
|
|
|
|
|
(mult:SI (s_or_u:SI
|
|
|
|
|
(vec_select:HI (match_operand:V2HI 1 "register_operand" "d,d,d,d")
|
|
|
|
|
(parallel [(const_int 0)])))
|
|
|
|
|
(s_or_u:SI
|
|
|
|
|
(vec_select:HI (match_operand:V2HI 2 "register_operand" "d,d,d,d")
|
|
|
|
|
(parallel [(const_int 1)])))))
|
|
|
|
|
(set (match_operand:SI 3 "register_operand" "=q1,q3,q5,q7")
|
|
|
|
|
(mult:SI (s_or_u:SI
|
|
|
|
|
(vec_select:HI (match_dup 1) (parallel [(const_int 1)])))
|
|
|
|
|
(s_or_u:SI
|
|
|
|
|
(vec_select:HI (match_dup 2) (parallel [(const_int 1)])))))]
|
|
|
|
|
""
|
|
|
|
|
"%0 = %h1 * %d2, %3 = %d1 * %d2 (<su_modifier>)%!"
|
|
|
|
|
[(set_attr "type" "dsp32")])
|
|
|
|
|
|
|
|
|
|
(define_insn "<su_optab>hisi_hl_hh"
|
|
|
|
|
[(set (match_operand:SI 0 "register_operand" "=q0,q2,q4,q6")
|
|
|
|
|
(mult:SI (s_or_u:SI
|
|
|
|
|
(vec_select:HI (match_operand:V2HI 1 "register_operand" "d,d,d,d")
|
|
|
|
|
(parallel [(const_int 1)])))
|
|
|
|
|
(s_or_u:SI
|
|
|
|
|
(vec_select:HI (match_operand:V2HI 2 "register_operand" "d,d,d,d")
|
|
|
|
|
(parallel [(const_int 0)])))))
|
|
|
|
|
(set (match_operand:SI 3 "register_operand" "=q1,q3,q5,q7")
|
|
|
|
|
(mult:SI (s_or_u:SI
|
|
|
|
|
(vec_select:HI (match_dup 1) (parallel [(const_int 1)])))
|
|
|
|
|
(s_or_u:SI
|
|
|
|
|
(vec_select:HI (match_dup 2) (parallel [(const_int 1)])))))]
|
|
|
|
|
""
|
|
|
|
|
"%0 = %d1 * %h2, %3 = %d1 * %d2 (<su_modifier>)%!"
|
|
|
|
|
[(set_attr "type" "dsp32")])
|
|
|
|
|
|
|
|
|
|
;; Special signed * unsigned variants.
|
|
|
|
|
|
|
|
|
|
(define_insn "usmulhisi_ll_lul"
|
|
|
|
|
[(set (match_operand:SI 0 "register_operand" "=q0,q2,q4,q6")
|
|
|
|
|
(mult:SI (sign_extend:SI
|
|
|
|
|
(vec_select:HI (match_operand:V2HI 1 "register_operand" "d,d,d,d")
|
|
|
|
|
(parallel [(const_int 0)])))
|
|
|
|
|
(sign_extend:SI
|
|
|
|
|
(vec_select:HI (match_operand:V2HI 2 "register_operand" "d,d,d,d")
|
|
|
|
|
(parallel [(const_int 0)])))))
|
|
|
|
|
(set (match_operand:SI 3 "register_operand" "=q1,q3,q5,q7")
|
|
|
|
|
(mult:SI (sign_extend:SI
|
|
|
|
|
(vec_select:HI (match_dup 1) (parallel [(const_int 0)])))
|
|
|
|
|
(zero_extend:SI
|
|
|
|
|
(vec_select:HI (match_dup 2) (parallel [(const_int 0)])))))]
|
|
|
|
|
""
|
|
|
|
|
"%0 = %h1 * %h2, %3 = %h1 * %h2 (IS,M)%!"
|
|
|
|
|
[(set_attr "type" "dsp32")])
|
|
|
|
|
|
|
|
|
|
(define_insn "usmulhisi_ll_luh"
|
|
|
|
|
[(set (match_operand:SI 0 "register_operand" "=q0,q2,q4,q6")
|
|
|
|
|
(mult:SI (sign_extend:SI
|
|
|
|
|
(vec_select:HI (match_operand:V2HI 1 "register_operand" "d,d,d,d")
|
|
|
|
|
(parallel [(const_int 0)])))
|
|
|
|
|
(sign_extend:SI
|
|
|
|
|
(vec_select:HI (match_operand:V2HI 2 "register_operand" "d,d,d,d")
|
|
|
|
|
(parallel [(const_int 0)])))))
|
|
|
|
|
(set (match_operand:SI 3 "register_operand" "=q1,q3,q5,q7")
|
|
|
|
|
(mult:SI (sign_extend:SI
|
|
|
|
|
(vec_select:HI (match_dup 1) (parallel [(const_int 0)])))
|
|
|
|
|
(zero_extend:SI
|
|
|
|
|
(vec_select:HI (match_dup 2) (parallel [(const_int 1)])))))]
|
|
|
|
|
""
|
|
|
|
|
"%0 = %h1 * %h2, %3 = %h1 * %d2 (IS,M)%!"
|
|
|
|
|
[(set_attr "type" "dsp32")])
|
|
|
|
|
|
|
|
|
|
(define_insn "usmulhisi_ll_hul"
|
|
|
|
|
[(set (match_operand:SI 0 "register_operand" "=q0,q2,q4,q6")
|
|
|
|
|
(mult:SI (sign_extend:SI
|
|
|
|
|
(vec_select:HI (match_operand:V2HI 1 "register_operand" "d,d,d,d")
|
|
|
|
|
(parallel [(const_int 0)])))
|
|
|
|
|
(sign_extend:SI
|
|
|
|
|
(vec_select:HI (match_operand:V2HI 2 "register_operand" "d,d,d,d")
|
|
|
|
|
(parallel [(const_int 0)])))))
|
|
|
|
|
(set (match_operand:SI 3 "register_operand" "=q1,q3,q5,q7")
|
|
|
|
|
(mult:SI (sign_extend:SI
|
|
|
|
|
(vec_select:HI (match_dup 1) (parallel [(const_int 1)])))
|
|
|
|
|
(zero_extend:SI
|
|
|
|
|
(vec_select:HI (match_dup 2) (parallel [(const_int 0)])))))]
|
|
|
|
|
""
|
|
|
|
|
"%0 = %h1 * %h2, %3 = %d1 * %h2 (IS,M)%!"
|
|
|
|
|
[(set_attr "type" "dsp32")])
|
|
|
|
|
|
|
|
|
|
(define_insn "usmulhisi_ll_huh"
|
|
|
|
|
[(set (match_operand:SI 0 "register_operand" "=q0,q2,q4,q6")
|
|
|
|
|
(mult:SI (sign_extend:SI
|
|
|
|
|
(vec_select:HI (match_operand:V2HI 1 "register_operand" "d,d,d,d")
|
|
|
|
|
(parallel [(const_int 0)])))
|
|
|
|
|
(sign_extend:SI
|
|
|
|
|
(vec_select:HI (match_operand:V2HI 2 "register_operand" "d,d,d,d")
|
|
|
|
|
(parallel [(const_int 0)])))))
|
|
|
|
|
(set (match_operand:SI 3 "register_operand" "=q1,q3,q5,q7")
|
|
|
|
|
(mult:SI (sign_extend:SI
|
|
|
|
|
(vec_select:HI (match_dup 1) (parallel [(const_int 1)])))
|
|
|
|
|
(zero_extend:SI
|
|
|
|
|
(vec_select:HI (match_dup 2) (parallel [(const_int 1)])))))]
|
|
|
|
|
""
|
|
|
|
|
"%0 = %h1 * %h2, %3 = %d1 * %d2 (IS,M)%!"
|
|
|
|
|
[(set_attr "type" "dsp32")])
|
|
|
|
|
|
|
|
|
|
(define_insn "usmulhisi_lh_lul"
|
|
|
|
|
[(set (match_operand:SI 0 "register_operand" "=q0,q2,q4,q6")
|
|
|
|
|
(mult:SI (sign_extend:SI
|
|
|
|
|
(vec_select:HI (match_operand:V2HI 1 "register_operand" "d,d,d,d")
|
|
|
|
|
(parallel [(const_int 0)])))
|
|
|
|
|
(sign_extend:SI
|
|
|
|
|
(vec_select:HI (match_operand:V2HI 2 "register_operand" "d,d,d,d")
|
|
|
|
|
(parallel [(const_int 1)])))))
|
|
|
|
|
(set (match_operand:SI 3 "register_operand" "=q1,q3,q5,q7")
|
|
|
|
|
(mult:SI (sign_extend:SI
|
|
|
|
|
(vec_select:HI (match_dup 1) (parallel [(const_int 0)])))
|
|
|
|
|
(zero_extend:SI
|
|
|
|
|
(vec_select:HI (match_dup 2) (parallel [(const_int 0)])))))]
|
|
|
|
|
""
|
|
|
|
|
"%0 = %h1 * %d2, %3 = %h1 * %h2 (IS,M)%!"
|
|
|
|
|
[(set_attr "type" "dsp32")])
|
|
|
|
|
|
|
|
|
|
(define_insn "usmulhisi_lh_luh"
|
|
|
|
|
[(set (match_operand:SI 0 "register_operand" "=q0,q2,q4,q6")
|
|
|
|
|
(mult:SI (sign_extend:SI
|
|
|
|
|
(vec_select:HI (match_operand:V2HI 1 "register_operand" "d,d,d,d")
|
|
|
|
|
(parallel [(const_int 0)])))
|
|
|
|
|
(sign_extend:SI
|
|
|
|
|
(vec_select:HI (match_operand:V2HI 2 "register_operand" "d,d,d,d")
|
|
|
|
|
(parallel [(const_int 1)])))))
|
|
|
|
|
(set (match_operand:SI 3 "register_operand" "=q1,q3,q5,q7")
|
|
|
|
|
(mult:SI (sign_extend:SI
|
|
|
|
|
(vec_select:HI (match_dup 1) (parallel [(const_int 0)])))
|
|
|
|
|
(zero_extend:SI
|
|
|
|
|
(vec_select:HI (match_dup 2) (parallel [(const_int 1)])))))]
|
|
|
|
|
""
|
|
|
|
|
"%0 = %h1 * %d2, %3 = %h1 * %d2 (IS,M)%!"
|
|
|
|
|
[(set_attr "type" "dsp32")])
|
|
|
|
|
|
|
|
|
|
(define_insn "usmulhisi_lh_hul"
|
|
|
|
|
[(set (match_operand:SI 0 "register_operand" "=q0,q2,q4,q6")
|
|
|
|
|
(mult:SI (sign_extend:SI
|
|
|
|
|
(vec_select:HI (match_operand:V2HI 1 "register_operand" "d,d,d,d")
|
|
|
|
|
(parallel [(const_int 0)])))
|
|
|
|
|
(sign_extend:SI
|
|
|
|
|
(vec_select:HI (match_operand:V2HI 2 "register_operand" "d,d,d,d")
|
|
|
|
|
(parallel [(const_int 1)])))))
|
|
|
|
|
(set (match_operand:SI 3 "register_operand" "=q1,q3,q5,q7")
|
|
|
|
|
(mult:SI (sign_extend:SI
|
|
|
|
|
(vec_select:HI (match_dup 1) (parallel [(const_int 1)])))
|
|
|
|
|
(zero_extend:SI
|
|
|
|
|
(vec_select:HI (match_dup 2) (parallel [(const_int 0)])))))]
|
|
|
|
|
""
|
|
|
|
|
"%0 = %h1 * %d2, %3 = %d1 * %h2 (IS,M)%!"
|
|
|
|
|
[(set_attr "type" "dsp32")])
|
|
|
|
|
|
|
|
|
|
(define_insn "usmulhisi_lh_huh"
|
|
|
|
|
[(set (match_operand:SI 0 "register_operand" "=q0,q2,q4,q6")
|
|
|
|
|
(mult:SI (sign_extend:SI
|
|
|
|
|
(vec_select:HI (match_operand:V2HI 1 "register_operand" "d,d,d,d")
|
|
|
|
|
(parallel [(const_int 0)])))
|
|
|
|
|
(sign_extend:SI
|
|
|
|
|
(vec_select:HI (match_operand:V2HI 2 "register_operand" "d,d,d,d")
|
|
|
|
|
(parallel [(const_int 1)])))))
|
|
|
|
|
(set (match_operand:SI 3 "register_operand" "=q1,q3,q5,q7")
|
|
|
|
|
(mult:SI (sign_extend:SI
|
|
|
|
|
(vec_select:HI (match_dup 1) (parallel [(const_int 1)])))
|
|
|
|
|
(zero_extend:SI
|
|
|
|
|
(vec_select:HI (match_dup 2) (parallel [(const_int 1)])))))]
|
|
|
|
|
""
|
|
|
|
|
"%0 = %h1 * %d2, %3 = %d1 * %d2 (IS,M)%!"
|
|
|
|
|
[(set_attr "type" "dsp32")])
|
|
|
|
|
|
|
|
|
|
(define_insn "usmulhisi_hl_lul"
|
|
|
|
|
[(set (match_operand:SI 0 "register_operand" "=q0,q2,q4,q6")
|
|
|
|
|
(mult:SI (sign_extend:SI
|
|
|
|
|
(vec_select:HI (match_operand:V2HI 1 "register_operand" "d,d,d,d")
|
|
|
|
|
(parallel [(const_int 1)])))
|
|
|
|
|
(sign_extend:SI
|
|
|
|
|
(vec_select:HI (match_operand:V2HI 2 "register_operand" "d,d,d,d")
|
|
|
|
|
(parallel [(const_int 0)])))))
|
|
|
|
|
(set (match_operand:SI 3 "register_operand" "=q1,q3,q5,q7")
|
|
|
|
|
(mult:SI (sign_extend:SI
|
|
|
|
|
(vec_select:HI (match_dup 1) (parallel [(const_int 0)])))
|
|
|
|
|
(zero_extend:SI
|
|
|
|
|
(vec_select:HI (match_dup 2) (parallel [(const_int 0)])))))]
|
|
|
|
|
""
|
|
|
|
|
"%0 = %d1 * %h2, %3 = %h1 * %h2 (IS,M)%!"
|
|
|
|
|
[(set_attr "type" "dsp32")])
|
|
|
|
|
|
|
|
|
|
(define_insn "usmulhisi_hl_luh"
|
|
|
|
|
[(set (match_operand:SI 0 "register_operand" "=q0,q2,q4,q6")
|
|
|
|
|
(mult:SI (sign_extend:SI
|
|
|
|
|
(vec_select:HI (match_operand:V2HI 1 "register_operand" "d,d,d,d")
|
|
|
|
|
(parallel [(const_int 1)])))
|
|
|
|
|
(sign_extend:SI
|
|
|
|
|
(vec_select:HI (match_operand:V2HI 2 "register_operand" "d,d,d,d")
|
|
|
|
|
(parallel [(const_int 0)])))))
|
|
|
|
|
(set (match_operand:SI 3 "register_operand" "=q1,q3,q5,q7")
|
|
|
|
|
(mult:SI (sign_extend:SI
|
|
|
|
|
(vec_select:HI (match_dup 1) (parallel [(const_int 0)])))
|
|
|
|
|
(zero_extend:SI
|
|
|
|
|
(vec_select:HI (match_dup 2) (parallel [(const_int 1)])))))]
|
|
|
|
|
""
|
|
|
|
|
"%0 = %d1 * %h2, %3 = %h1 * %d2 (IS,M)%!"
|
|
|
|
|
[(set_attr "type" "dsp32")])
|
|
|
|
|
|
|
|
|
|
(define_insn "usmulhisi_hl_hul"
|
|
|
|
|
[(set (match_operand:SI 0 "register_operand" "=q0,q2,q4,q6")
|
|
|
|
|
(mult:SI (sign_extend:SI
|
|
|
|
|
(vec_select:HI (match_operand:V2HI 1 "register_operand" "d,d,d,d")
|
|
|
|
|
(parallel [(const_int 1)])))
|
|
|
|
|
(sign_extend:SI
|
|
|
|
|
(vec_select:HI (match_operand:V2HI 2 "register_operand" "d,d,d,d")
|
|
|
|
|
(parallel [(const_int 0)])))))
|
|
|
|
|
(set (match_operand:SI 3 "register_operand" "=q1,q3,q5,q7")
|
|
|
|
|
(mult:SI (sign_extend:SI
|
|
|
|
|
(vec_select:HI (match_dup 1) (parallel [(const_int 1)])))
|
|
|
|
|
(zero_extend:SI
|
|
|
|
|
(vec_select:HI (match_dup 2) (parallel [(const_int 0)])))))]
|
|
|
|
|
""
|
|
|
|
|
"%0 = %d1 * %h2, %3 = %d1 * %h2 (IS,M)%!"
|
|
|
|
|
[(set_attr "type" "dsp32")])
|
|
|
|
|
|
|
|
|
|
(define_insn "usmulhisi_hl_huh"
|
|
|
|
|
[(set (match_operand:SI 0 "register_operand" "=q0,q2,q4,q6")
|
|
|
|
|
(mult:SI (sign_extend:SI
|
|
|
|
|
(vec_select:HI (match_operand:V2HI 1 "register_operand" "d,d,d,d")
|
|
|
|
|
(parallel [(const_int 1)])))
|
|
|
|
|
(sign_extend:SI
|
|
|
|
|
(vec_select:HI (match_operand:V2HI 2 "register_operand" "d,d,d,d")
|
|
|
|
|
(parallel [(const_int 0)])))))
|
|
|
|
|
(set (match_operand:SI 3 "register_operand" "=q1,q3,q5,q7")
|
|
|
|
|
(mult:SI (sign_extend:SI
|
|
|
|
|
(vec_select:HI (match_dup 1) (parallel [(const_int 1)])))
|
|
|
|
|
(zero_extend:SI
|
|
|
|
|
(vec_select:HI (match_dup 2) (parallel [(const_int 1)])))))]
|
|
|
|
|
""
|
|
|
|
|
"%0 = %d1 * %h2, %3 = %d1 * %d2 (IS,M)%!"
|
|
|
|
|
[(set_attr "type" "dsp32")])
|
|
|
|
|
|
|
|
|
|
(define_insn "usmulhisi_hh_lul"
|
|
|
|
|
[(set (match_operand:SI 0 "register_operand" "=q0,q2,q4,q6")
|
|
|
|
|
(mult:SI (sign_extend:SI
|
|
|
|
|
(vec_select:HI (match_operand:V2HI 1 "register_operand" "d,d,d,d")
|
|
|
|
|
(parallel [(const_int 1)])))
|
|
|
|
|
(sign_extend:SI
|
|
|
|
|
(vec_select:HI (match_operand:V2HI 2 "register_operand" "d,d,d,d")
|
|
|
|
|
(parallel [(const_int 1)])))))
|
|
|
|
|
(set (match_operand:SI 3 "register_operand" "=q1,q3,q5,q7")
|
|
|
|
|
(mult:SI (sign_extend:SI
|
|
|
|
|
(vec_select:HI (match_dup 1) (parallel [(const_int 0)])))
|
|
|
|
|
(zero_extend:SI
|
|
|
|
|
(vec_select:HI (match_dup 2) (parallel [(const_int 0)])))))]
|
|
|
|
|
""
|
|
|
|
|
"%0 = %d1 * %d2, %3 = %h1 * %h2 (IS,M)%!"
|
genmodes.c (make_vector_mode): Allow making VECTOR_MODE_INT of a MODE_PARTIAL_INT mode.
* genmodes.c (make_vector_mode): Allow making VECTOR_MODE_INT of a
MODE_PARTIAL_INT mode.
* config/bfin/bfin-modes.def: Add V2PDI and V2SI.
* config/bfin/bfin.c (print_operand): Add macflag and mac/msu modifiers
for CONST_INTs.
(hard_regno_mode_ok): V2PDImode is ok for accumulators.
* config/bfin/bfin.h (CLASS_MAX_NREGS, HARD_REGNO_NREGS): Handle
V2PDImode.
* config/bfin/predicates.md (const01_operand, vec_shift_operand):
New predicates.
* config/bfin/bfin.md (UNSPEC_MUL_WITH_FLAG, UNSPEC_MAC_WITH_FLAG):
New constants.
(MACFLAG_NONE, MACFLAG_T, MACFLAG_FU, MACFLAG_TFU, MACFLAG_IS,
MACFLAG_IU, MACFLAG_W32, MACFLAG_M, MACFLAG_S2RND, MACFLAG_ISS2,
MACFLAG_IH): Likewise.
(movstricthi_1): Renamed from "*movstricthi".
(load_accumulator, load_accumulator_pair, movsi_insv, insv,
ssaddsi3, sssubsi3, ssnegsi2, signbitssi2, smaxhi3, sminhi3,
abshi2, neghi2, ssneghi2, signbitshi2, movhi_low2high,
movhi_high2high, movhi_low2low, movhi_high2low, movhiv2hi_low,
movhiv2hi_high, composev2hi, movv2hi_hi, movv2hi_hi_low,
movv2hi_hi_high, ssaddhi3, sssubhi3, ssaddv2hi3, sssubv2hi3,
addsubv2hi3, subaddv2hi3, ssaddsubv2hi3, sssubaddv2hi3,
sublohiv2hi3, subhilov2hi3, sssublohiv2hi3, sssubhilov2hi3,
addlohiv2hi3, addhilov2hi3, ssaddlohiv2hi3, ssaddhilov2hi3,
mulhisi_ll, mulhisi_lh, mulhisi_hl, mulhisi_hh, ssnegv2hi2,
ssashiftv2hi3, ssashifthi3, lshiftv2hi3, lshifthi3, packv2hi,
flag_mulhi, flag_mulhisi_parts, flag_machi, flag_machi_acconly,
flag_macinithi, flag_macinit1hi, flag_mulv2hi, flag_mulv2hi_parts,
flag_macv2hi_parts, flag_macv2hi_parts_acconly,
flag_macinitv2hi_parts, flag_macinit1v2hi_parts): New patterns.
From-SVN: r113245
2006-04-25 13:49:27 +02:00
|
|
|
|
[(set_attr "type" "dsp32")])
|
|
|
|
|
|
bfin.h (enum reg_class, [...]): Add D0REGS through D7REGS.
* config/bfin/bfin.h (enum reg_class, REG_CLASS_NAMES,
REG_CLASS_CONTENTS): Add D0REGS through D7REGS.
(CONSTRAINT_LEN): Add entry for 'q'.
(REG_CLASS_FROM_CONSTRAINT): Renamed from REG_CLASS_FROM_LETTER.
Add 'q' constraints.
(REGNO_REG_CLASS): For R0 through R7, return corresponding regclass.
(CLASS_LIKELY_SPILLED_P): True for R0, R1 and R2.
* config/bfin/bfin.md (add_with_carry): New pattern.
(s_or_u, su_optab, su_modifier): New code macros/attrs.
(<su_optab>hisi_ll, <su_optab>hisi_lh, <su_optab>hisi_hl,
<su_optab>hisi_hh): Renamed from mulhisi_xx patterns; macroized to
support unsigned multiplies too. Removed incorrect commutativity from
operand 1 constraint where appropriate.
(usmulhisi_ull, usmulhisi_ulh, usmulhisi_uhl, usmulhisi_uhh): New
patterns.
(<su_optab>hisi_ll_lh, <su_optab>hisi_ll_hl, <su_optab>hisi_ll_hh,
<su_optab>hisi_lh_hl, <su_optab>hisi_lh_hh, <su_optab>hisi_hl_hh):
New patterns.
(usmulhisi_ll_lul, usmulhisi_ll_luh, usmulhisi_ll_hul,
usmulhisi_ll_huh, usmulhisi_lh_lul, usmulhisi_lh_luh, usmulhisi_lh_hul,
usmulhisi_lh_huh, usmulhisi_hl_lul, usmulhisi_hl_luh, usmulhisi_hl_hul,
usmulhisi_hl_huh, usmulhisi_hh_lul, usmulhisi_hh_luh, usmulhisi_hh_hul,
usmulhisi_hh_huh): New patterns.
From-SVN: r122373
2007-02-27 14:44:10 +01:00
|
|
|
|
(define_insn "usmulhisi_hh_luh"
|
|
|
|
|
[(set (match_operand:SI 0 "register_operand" "=q0,q2,q4,q6")
|
|
|
|
|
(mult:SI (sign_extend:SI
|
|
|
|
|
(vec_select:HI (match_operand:V2HI 1 "register_operand" "d,d,d,d")
|
|
|
|
|
(parallel [(const_int 1)])))
|
|
|
|
|
(sign_extend:SI
|
|
|
|
|
(vec_select:HI (match_operand:V2HI 2 "register_operand" "d,d,d,d")
|
|
|
|
|
(parallel [(const_int 1)])))))
|
|
|
|
|
(set (match_operand:SI 3 "register_operand" "=q1,q3,q5,q7")
|
|
|
|
|
(mult:SI (sign_extend:SI
|
|
|
|
|
(vec_select:HI (match_dup 1) (parallel [(const_int 0)])))
|
|
|
|
|
(zero_extend:SI
|
|
|
|
|
(vec_select:HI (match_dup 2) (parallel [(const_int 1)])))))]
|
|
|
|
|
""
|
|
|
|
|
"%0 = %d1 * %d2, %3 = %h1 * %d2 (IS,M)%!"
|
|
|
|
|
[(set_attr "type" "dsp32")])
|
|
|
|
|
|
|
|
|
|
(define_insn "usmulhisi_hh_hul"
|
|
|
|
|
[(set (match_operand:SI 0 "register_operand" "=q0,q2,q4,q6")
|
|
|
|
|
(mult:SI (sign_extend:SI
|
|
|
|
|
(vec_select:HI (match_operand:V2HI 1 "register_operand" "d,d,d,d")
|
|
|
|
|
(parallel [(const_int 1)])))
|
|
|
|
|
(sign_extend:SI
|
|
|
|
|
(vec_select:HI (match_operand:V2HI 2 "register_operand" "d,d,d,d")
|
|
|
|
|
(parallel [(const_int 1)])))))
|
|
|
|
|
(set (match_operand:SI 3 "register_operand" "=q1,q3,q5,q7")
|
|
|
|
|
(mult:SI (sign_extend:SI
|
|
|
|
|
(vec_select:HI (match_dup 1) (parallel [(const_int 1)])))
|
|
|
|
|
(zero_extend:SI
|
|
|
|
|
(vec_select:HI (match_dup 2) (parallel [(const_int 0)])))))]
|
|
|
|
|
""
|
|
|
|
|
"%0 = %d1 * %d2, %3 = %d1 * %h2 (IS,M)%!"
|
|
|
|
|
[(set_attr "type" "dsp32")])
|
|
|
|
|
|
|
|
|
|
(define_insn "usmulhisi_hh_huh"
|
|
|
|
|
[(set (match_operand:SI 0 "register_operand" "=q0,q2,q4,q6")
|
|
|
|
|
(mult:SI (sign_extend:SI
|
|
|
|
|
(vec_select:HI (match_operand:V2HI 1 "register_operand" "d,d,d,d")
|
|
|
|
|
(parallel [(const_int 1)])))
|
|
|
|
|
(sign_extend:SI
|
|
|
|
|
(vec_select:HI (match_operand:V2HI 2 "register_operand" "d,d,d,d")
|
|
|
|
|
(parallel [(const_int 1)])))))
|
|
|
|
|
(set (match_operand:SI 3 "register_operand" "=q1,q3,q5,q7")
|
|
|
|
|
(mult:SI (sign_extend:SI
|
|
|
|
|
(vec_select:HI (match_dup 1) (parallel [(const_int 1)])))
|
|
|
|
|
(zero_extend:SI
|
|
|
|
|
(vec_select:HI (match_dup 2) (parallel [(const_int 1)])))))]
|
|
|
|
|
""
|
|
|
|
|
"%0 = %d1 * %d2, %3 = %d1 * %d2 (IS,M)%!"
|
|
|
|
|
[(set_attr "type" "dsp32")])
|
|
|
|
|
|
|
|
|
|
;; Vector neg/abs.
|
|
|
|
|
|
genmodes.c (make_vector_mode): Allow making VECTOR_MODE_INT of a MODE_PARTIAL_INT mode.
* genmodes.c (make_vector_mode): Allow making VECTOR_MODE_INT of a
MODE_PARTIAL_INT mode.
* config/bfin/bfin-modes.def: Add V2PDI and V2SI.
* config/bfin/bfin.c (print_operand): Add macflag and mac/msu modifiers
for CONST_INTs.
(hard_regno_mode_ok): V2PDImode is ok for accumulators.
* config/bfin/bfin.h (CLASS_MAX_NREGS, HARD_REGNO_NREGS): Handle
V2PDImode.
* config/bfin/predicates.md (const01_operand, vec_shift_operand):
New predicates.
* config/bfin/bfin.md (UNSPEC_MUL_WITH_FLAG, UNSPEC_MAC_WITH_FLAG):
New constants.
(MACFLAG_NONE, MACFLAG_T, MACFLAG_FU, MACFLAG_TFU, MACFLAG_IS,
MACFLAG_IU, MACFLAG_W32, MACFLAG_M, MACFLAG_S2RND, MACFLAG_ISS2,
MACFLAG_IH): Likewise.
(movstricthi_1): Renamed from "*movstricthi".
(load_accumulator, load_accumulator_pair, movsi_insv, insv,
ssaddsi3, sssubsi3, ssnegsi2, signbitssi2, smaxhi3, sminhi3,
abshi2, neghi2, ssneghi2, signbitshi2, movhi_low2high,
movhi_high2high, movhi_low2low, movhi_high2low, movhiv2hi_low,
movhiv2hi_high, composev2hi, movv2hi_hi, movv2hi_hi_low,
movv2hi_hi_high, ssaddhi3, sssubhi3, ssaddv2hi3, sssubv2hi3,
addsubv2hi3, subaddv2hi3, ssaddsubv2hi3, sssubaddv2hi3,
sublohiv2hi3, subhilov2hi3, sssublohiv2hi3, sssubhilov2hi3,
addlohiv2hi3, addhilov2hi3, ssaddlohiv2hi3, ssaddhilov2hi3,
mulhisi_ll, mulhisi_lh, mulhisi_hl, mulhisi_hh, ssnegv2hi2,
ssashiftv2hi3, ssashifthi3, lshiftv2hi3, lshifthi3, packv2hi,
flag_mulhi, flag_mulhisi_parts, flag_machi, flag_machi_acconly,
flag_macinithi, flag_macinit1hi, flag_mulv2hi, flag_mulv2hi_parts,
flag_macv2hi_parts, flag_macv2hi_parts_acconly,
flag_macinitv2hi_parts, flag_macinit1v2hi_parts): New patterns.
From-SVN: r113245
2006-04-25 13:49:27 +02:00
|
|
|
|
(define_insn "ssnegv2hi2"
|
|
|
|
|
[(set (match_operand:V2HI 0 "register_operand" "=d")
|
|
|
|
|
(ss_neg:V2HI (match_operand:V2HI 1 "register_operand" "d")))]
|
2005-04-05 13:26:48 +02:00
|
|
|
|
""
|
rtlanal.c (note_uses): Deal with SEQUENCEs.
* rtlanal.c (note_uses): Deal with SEQUENCEs.
* config/bfin/bfin.c: Include "timevar.h".
(bfin_flag_schedule_insns2, splitting_for_sched,
bfin_flag_var_tracking): New variables.
(print_operand): Handle '%!'.
(override_options): Disable normal sched2 pass, instead set
bfin_flag_schedule_insns2 for reorg to handle it.
(output_file_start): Likewise for var-tracking.
(bfin_optimize_loop): Take some care not to stumble over SEQUENCEs.
(gen_one_bundle, bfin_gen_bundles, type_for_anomaly, trapping_loads_p):
New functions.
(bfin_reorg): Do second scheduling pass here, and call
bfin_gen_bundles. Use type_for_anomaly and trapping_loads_p instead
of examining insns directly. If bfin_flag_var_tracking, call
var-tracking pass when done with everything else.
* config/bfin/bfin.h (PRINT_OPERAND_PUNCT_VALID_P): '!' is valid.
* config/bfin/bfin.md (UNSPEC_32BIT): New constant.
(movsi_insn32): New pattern, with two new splits to create it
before the final scheduling pass.
(neghi2): Not a dsp32 insn, rather alu0.
(movbi, pushsi_insn, popsi_insn, movsi_insn, movv2hi_insn, movhi_insn,
movqi_insn, movsf_insn, movsi_insv, extendhisi2, zero_extendhisi2,
extendqihi2, extendqisi2, zero_extendqihi2, zero_extendqisi2,
mulhisi3, umulhisi3, ssadsi3, sssubsi3, smaxsi3, sminsi3, abssi2,
ssnegsi2, signbitssi2, smaxhi3, sminhi3, abshi2, ssneghi2, signbitshi2,
movhi_low2high, movhi_high2high, movhi_low2low, movhi_high2low,
movhiv2hi_low, movhiv2hi_high, composev2hi, packv2hi, movv2hi_hi,
ssaddhi3, sssubhi3, addv2hi3, ssaddv2hi3, subv2hi3, sssubv2hi3,
addsubv2hi3, subaddv2hi3, ssaddsubv2hi3, sssubaddv2hi3, sublohiv2hi3,
subhilov2hi3, sssublohiv2hi3, sssubhilov2hi3, addlohiv2hi3,
addhilov2hi3, ssaddlohiv2hi3, ssaddhilov2hi3, sminv2hi3, smaxv2hi3,
flag_mulhi, flag_mulhisi, flag_mulhisi_parts, flag_machi,
flag_machi_acconly, flag_macinithi, flag_macinit1hi, mulv2hi3,
flag_mulv2hi, flag_mulv2hi_parts, flag_macv2hi_parts,
flag_macv2hi_parts_acconly, flag_macinitv2hi_parts,
flag_macinit1v2hi_parts, mulhisi_ll, mulhisi_lh, mulhisi_hl,
mulhisi_hh, ssnegv2hi2, absv2hi2, ssashiftv2hi3, ssashifthi3,
lshiftv2hi3, lshifthi3): Use '%!' to terminate all dsp32/load/store
variants instead of ';'.
(ror_one, rol_one): Likewise. Make them dsp32 insns.
(ashlsi3_insn, ashrsi3, lshrsi3): Add dsp32 variants.
(align8, align16, align24): Now named patterns; also using '%!'.
(mnop): New insn.
From-SVN: r119534
2006-12-05 09:49:56 +01:00
|
|
|
|
"%0 = - %1 (V)%!"
|
2005-04-05 13:26:48 +02:00
|
|
|
|
[(set_attr "type" "dsp32")])
|
|
|
|
|
|
rtl.def (SS_ABS): New code.
* rtl.def (SS_ABS): New code.
* config/bfin/bfin.c (print_operand): New modifier 'v'.
(enum bfin_builtins): Add BFIN_BUILTIN_SUM_2X16, BFIN_BUILTIN_ABS_1x32,
BFIN_BUILTIN_ROUND_1x32, BFIN_BUILTIN_MULT_1x32x32,
BFIN_BUILTIN_MULT_1x32x32NS, BFIN_BUILTIN_SSASHIFT_1x32.
(bfin_init_builtins): Define them.
(bdesc_1arg, bdesc_2arg): Add some of them here, ...
(bfin_expand_builtin): ... and handle the others here.
* config/bfin/bfin.md (ssabssi2, ssroundsi2, ssashiftsi3,
flag_mul_macv2hi_parts_acconly_andcc0): New patterns.
(ss_absv2hi2): Renamed from absv2hi; use ss_abs code.
(ssashiftv2hi3, ssashifthi3, lshiftv2hi3, lshifthi3): Shift count
operand is only HImode.
From-SVN: r124280
2007-04-29 15:22:04 +02:00
|
|
|
|
(define_insn "ssabsv2hi2"
|
2005-04-05 13:26:48 +02:00
|
|
|
|
[(set (match_operand:V2HI 0 "register_operand" "=d")
|
rtl.def (SS_ABS): New code.
* rtl.def (SS_ABS): New code.
* config/bfin/bfin.c (print_operand): New modifier 'v'.
(enum bfin_builtins): Add BFIN_BUILTIN_SUM_2X16, BFIN_BUILTIN_ABS_1x32,
BFIN_BUILTIN_ROUND_1x32, BFIN_BUILTIN_MULT_1x32x32,
BFIN_BUILTIN_MULT_1x32x32NS, BFIN_BUILTIN_SSASHIFT_1x32.
(bfin_init_builtins): Define them.
(bdesc_1arg, bdesc_2arg): Add some of them here, ...
(bfin_expand_builtin): ... and handle the others here.
* config/bfin/bfin.md (ssabssi2, ssroundsi2, ssashiftsi3,
flag_mul_macv2hi_parts_acconly_andcc0): New patterns.
(ss_absv2hi2): Renamed from absv2hi; use ss_abs code.
(ssashiftv2hi3, ssashifthi3, lshiftv2hi3, lshifthi3): Shift count
operand is only HImode.
From-SVN: r124280
2007-04-29 15:22:04 +02:00
|
|
|
|
(ss_abs:V2HI (match_operand:V2HI 1 "register_operand" "d")))]
|
2005-04-05 13:26:48 +02:00
|
|
|
|
""
|
rtlanal.c (note_uses): Deal with SEQUENCEs.
* rtlanal.c (note_uses): Deal with SEQUENCEs.
* config/bfin/bfin.c: Include "timevar.h".
(bfin_flag_schedule_insns2, splitting_for_sched,
bfin_flag_var_tracking): New variables.
(print_operand): Handle '%!'.
(override_options): Disable normal sched2 pass, instead set
bfin_flag_schedule_insns2 for reorg to handle it.
(output_file_start): Likewise for var-tracking.
(bfin_optimize_loop): Take some care not to stumble over SEQUENCEs.
(gen_one_bundle, bfin_gen_bundles, type_for_anomaly, trapping_loads_p):
New functions.
(bfin_reorg): Do second scheduling pass here, and call
bfin_gen_bundles. Use type_for_anomaly and trapping_loads_p instead
of examining insns directly. If bfin_flag_var_tracking, call
var-tracking pass when done with everything else.
* config/bfin/bfin.h (PRINT_OPERAND_PUNCT_VALID_P): '!' is valid.
* config/bfin/bfin.md (UNSPEC_32BIT): New constant.
(movsi_insn32): New pattern, with two new splits to create it
before the final scheduling pass.
(neghi2): Not a dsp32 insn, rather alu0.
(movbi, pushsi_insn, popsi_insn, movsi_insn, movv2hi_insn, movhi_insn,
movqi_insn, movsf_insn, movsi_insv, extendhisi2, zero_extendhisi2,
extendqihi2, extendqisi2, zero_extendqihi2, zero_extendqisi2,
mulhisi3, umulhisi3, ssadsi3, sssubsi3, smaxsi3, sminsi3, abssi2,
ssnegsi2, signbitssi2, smaxhi3, sminhi3, abshi2, ssneghi2, signbitshi2,
movhi_low2high, movhi_high2high, movhi_low2low, movhi_high2low,
movhiv2hi_low, movhiv2hi_high, composev2hi, packv2hi, movv2hi_hi,
ssaddhi3, sssubhi3, addv2hi3, ssaddv2hi3, subv2hi3, sssubv2hi3,
addsubv2hi3, subaddv2hi3, ssaddsubv2hi3, sssubaddv2hi3, sublohiv2hi3,
subhilov2hi3, sssublohiv2hi3, sssubhilov2hi3, addlohiv2hi3,
addhilov2hi3, ssaddlohiv2hi3, ssaddhilov2hi3, sminv2hi3, smaxv2hi3,
flag_mulhi, flag_mulhisi, flag_mulhisi_parts, flag_machi,
flag_machi_acconly, flag_macinithi, flag_macinit1hi, mulv2hi3,
flag_mulv2hi, flag_mulv2hi_parts, flag_macv2hi_parts,
flag_macv2hi_parts_acconly, flag_macinitv2hi_parts,
flag_macinit1v2hi_parts, mulhisi_ll, mulhisi_lh, mulhisi_hl,
mulhisi_hh, ssnegv2hi2, absv2hi2, ssashiftv2hi3, ssashifthi3,
lshiftv2hi3, lshifthi3): Use '%!' to terminate all dsp32/load/store
variants instead of ';'.
(ror_one, rol_one): Likewise. Make them dsp32 insns.
(ashlsi3_insn, ashrsi3, lshrsi3): Add dsp32 variants.
(align8, align16, align24): Now named patterns; also using '%!'.
(mnop): New insn.
From-SVN: r119534
2006-12-05 09:49:56 +01:00
|
|
|
|
"%0 = ABS %1 (V)%!"
|
2005-04-05 13:26:48 +02:00
|
|
|
|
[(set_attr "type" "dsp32")])
|
|
|
|
|
|
genmodes.c (make_vector_mode): Allow making VECTOR_MODE_INT of a MODE_PARTIAL_INT mode.
* genmodes.c (make_vector_mode): Allow making VECTOR_MODE_INT of a
MODE_PARTIAL_INT mode.
* config/bfin/bfin-modes.def: Add V2PDI and V2SI.
* config/bfin/bfin.c (print_operand): Add macflag and mac/msu modifiers
for CONST_INTs.
(hard_regno_mode_ok): V2PDImode is ok for accumulators.
* config/bfin/bfin.h (CLASS_MAX_NREGS, HARD_REGNO_NREGS): Handle
V2PDImode.
* config/bfin/predicates.md (const01_operand, vec_shift_operand):
New predicates.
* config/bfin/bfin.md (UNSPEC_MUL_WITH_FLAG, UNSPEC_MAC_WITH_FLAG):
New constants.
(MACFLAG_NONE, MACFLAG_T, MACFLAG_FU, MACFLAG_TFU, MACFLAG_IS,
MACFLAG_IU, MACFLAG_W32, MACFLAG_M, MACFLAG_S2RND, MACFLAG_ISS2,
MACFLAG_IH): Likewise.
(movstricthi_1): Renamed from "*movstricthi".
(load_accumulator, load_accumulator_pair, movsi_insv, insv,
ssaddsi3, sssubsi3, ssnegsi2, signbitssi2, smaxhi3, sminhi3,
abshi2, neghi2, ssneghi2, signbitshi2, movhi_low2high,
movhi_high2high, movhi_low2low, movhi_high2low, movhiv2hi_low,
movhiv2hi_high, composev2hi, movv2hi_hi, movv2hi_hi_low,
movv2hi_hi_high, ssaddhi3, sssubhi3, ssaddv2hi3, sssubv2hi3,
addsubv2hi3, subaddv2hi3, ssaddsubv2hi3, sssubaddv2hi3,
sublohiv2hi3, subhilov2hi3, sssublohiv2hi3, sssubhilov2hi3,
addlohiv2hi3, addhilov2hi3, ssaddlohiv2hi3, ssaddhilov2hi3,
mulhisi_ll, mulhisi_lh, mulhisi_hl, mulhisi_hh, ssnegv2hi2,
ssashiftv2hi3, ssashifthi3, lshiftv2hi3, lshifthi3, packv2hi,
flag_mulhi, flag_mulhisi_parts, flag_machi, flag_machi_acconly,
flag_macinithi, flag_macinit1hi, flag_mulv2hi, flag_mulv2hi_parts,
flag_macv2hi_parts, flag_macv2hi_parts_acconly,
flag_macinitv2hi_parts, flag_macinit1v2hi_parts): New patterns.
From-SVN: r113245
2006-04-25 13:49:27 +02:00
|
|
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|
;; Shifts.
|
|
|
|
|
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|
(define_insn "ssashiftv2hi3"
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|
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|
[(set (match_operand:V2HI 0 "register_operand" "=d,d,d")
|
|
|
|
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(if_then_else:V2HI
|
rtl.def (SS_ABS): New code.
* rtl.def (SS_ABS): New code.
* config/bfin/bfin.c (print_operand): New modifier 'v'.
(enum bfin_builtins): Add BFIN_BUILTIN_SUM_2X16, BFIN_BUILTIN_ABS_1x32,
BFIN_BUILTIN_ROUND_1x32, BFIN_BUILTIN_MULT_1x32x32,
BFIN_BUILTIN_MULT_1x32x32NS, BFIN_BUILTIN_SSASHIFT_1x32.
(bfin_init_builtins): Define them.
(bdesc_1arg, bdesc_2arg): Add some of them here, ...
(bfin_expand_builtin): ... and handle the others here.
* config/bfin/bfin.md (ssabssi2, ssroundsi2, ssashiftsi3,
flag_mul_macv2hi_parts_acconly_andcc0): New patterns.
(ss_absv2hi2): Renamed from absv2hi; use ss_abs code.
(ssashiftv2hi3, ssashifthi3, lshiftv2hi3, lshifthi3): Shift count
operand is only HImode.
From-SVN: r124280
2007-04-29 15:22:04 +02:00
|
|
|
|
(lt (match_operand:HI 2 "vec_shift_operand" "d,Ku4,Ks4") (const_int 0))
|
genmodes.c (make_vector_mode): Allow making VECTOR_MODE_INT of a MODE_PARTIAL_INT mode.
* genmodes.c (make_vector_mode): Allow making VECTOR_MODE_INT of a
MODE_PARTIAL_INT mode.
* config/bfin/bfin-modes.def: Add V2PDI and V2SI.
* config/bfin/bfin.c (print_operand): Add macflag and mac/msu modifiers
for CONST_INTs.
(hard_regno_mode_ok): V2PDImode is ok for accumulators.
* config/bfin/bfin.h (CLASS_MAX_NREGS, HARD_REGNO_NREGS): Handle
V2PDImode.
* config/bfin/predicates.md (const01_operand, vec_shift_operand):
New predicates.
* config/bfin/bfin.md (UNSPEC_MUL_WITH_FLAG, UNSPEC_MAC_WITH_FLAG):
New constants.
(MACFLAG_NONE, MACFLAG_T, MACFLAG_FU, MACFLAG_TFU, MACFLAG_IS,
MACFLAG_IU, MACFLAG_W32, MACFLAG_M, MACFLAG_S2RND, MACFLAG_ISS2,
MACFLAG_IH): Likewise.
(movstricthi_1): Renamed from "*movstricthi".
(load_accumulator, load_accumulator_pair, movsi_insv, insv,
ssaddsi3, sssubsi3, ssnegsi2, signbitssi2, smaxhi3, sminhi3,
abshi2, neghi2, ssneghi2, signbitshi2, movhi_low2high,
movhi_high2high, movhi_low2low, movhi_high2low, movhiv2hi_low,
movhiv2hi_high, composev2hi, movv2hi_hi, movv2hi_hi_low,
movv2hi_hi_high, ssaddhi3, sssubhi3, ssaddv2hi3, sssubv2hi3,
addsubv2hi3, subaddv2hi3, ssaddsubv2hi3, sssubaddv2hi3,
sublohiv2hi3, subhilov2hi3, sssublohiv2hi3, sssubhilov2hi3,
addlohiv2hi3, addhilov2hi3, ssaddlohiv2hi3, ssaddhilov2hi3,
mulhisi_ll, mulhisi_lh, mulhisi_hl, mulhisi_hh, ssnegv2hi2,
ssashiftv2hi3, ssashifthi3, lshiftv2hi3, lshifthi3, packv2hi,
flag_mulhi, flag_mulhisi_parts, flag_machi, flag_machi_acconly,
flag_macinithi, flag_macinit1hi, flag_mulv2hi, flag_mulv2hi_parts,
flag_macv2hi_parts, flag_macv2hi_parts_acconly,
flag_macinitv2hi_parts, flag_macinit1v2hi_parts): New patterns.
From-SVN: r113245
2006-04-25 13:49:27 +02:00
|
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(ashiftrt:V2HI (match_operand:V2HI 1 "register_operand" "d,d,d")
|
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(match_dup 2))
|
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(ss_ashift:V2HI (match_dup 1) (match_dup 2))))]
|
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|
""
|
|
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"@
|
2007-02-27 14:55:56 +01:00
|
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|
%0 = ASHIFT %1 BY %h2 (V, S)%!
|
2006-12-07 12:06:08 +01:00
|
|
|
|
%0 = %1 << %2 (V,S)%!
|
|
|
|
|
%0 = %1 >>> %N2 (V,S)%!"
|
From Jie Zhang <jie.zhang@analog.com>:
* config/bfin/predicates.md (p_register_operand): New
predicate.
(dp_register_operand): New predicate.
* config/bfin/bfin-protos.h (WA_05000074): Define.
(ENABLE_WA_05000074): Define.
* config/bfin/bfin.c (bfin_cpus[]): Add WA_05000074 for
all cpus.
(bfin_gen_bundles): Put dsp32shiftimm instruction in slot[0].
* config/bfin/bfin.md (define_attr type): Add dsp32shiftimm.
(define_attr addrtype): Allow load/store register to be
P register.
(define_attr storereg): New.
(define_cpu_unit anomaly_05000074): New.
(define_insn_reservation dsp32shiftimm): New.
(define_insn_reservation dsp32shiftimm_anomaly_05000074): New.
(define_insn_reservation loadp): Cannot use slot2.
(define_insn_reservation loadsp): Cannot use slot2.
(define_insn_reservation storep): Cannot use slot2. Does not
apply when working around 05000074.
(define_insn_reservation storep_anomaly_05000074): New.
(define_insn_reservation storei): Does not apply when working
around 05000074.
(define_insn_reservation storei_anomaly_05000074): New.
(define_attr length): Add dsp32shiftimm case.
(define_insn movsi_insn32, movsi_insv, ashlsi3_insn, ashrsi3,
ror_one, rol_one, lshrsi3, lshrpdi3, ashrpdi3, movhiv2hi_low,
movhiv2hi_high, composev2hi, packv2hi, movv2hi_hi,
ssashiftv2hi3, ssashifthi3, ssashiftsi3, lshiftv2hi3, lshifthi3):
Set type as dsp32shiftimm for dsp32shiftimm alternatives.
From-SVN: r151490
2009-09-07 23:40:23 +02:00
|
|
|
|
[(set_attr "type" "dsp32,dsp32shiftimm,dsp32shiftimm")])
|
genmodes.c (make_vector_mode): Allow making VECTOR_MODE_INT of a MODE_PARTIAL_INT mode.
* genmodes.c (make_vector_mode): Allow making VECTOR_MODE_INT of a
MODE_PARTIAL_INT mode.
* config/bfin/bfin-modes.def: Add V2PDI and V2SI.
* config/bfin/bfin.c (print_operand): Add macflag and mac/msu modifiers
for CONST_INTs.
(hard_regno_mode_ok): V2PDImode is ok for accumulators.
* config/bfin/bfin.h (CLASS_MAX_NREGS, HARD_REGNO_NREGS): Handle
V2PDImode.
* config/bfin/predicates.md (const01_operand, vec_shift_operand):
New predicates.
* config/bfin/bfin.md (UNSPEC_MUL_WITH_FLAG, UNSPEC_MAC_WITH_FLAG):
New constants.
(MACFLAG_NONE, MACFLAG_T, MACFLAG_FU, MACFLAG_TFU, MACFLAG_IS,
MACFLAG_IU, MACFLAG_W32, MACFLAG_M, MACFLAG_S2RND, MACFLAG_ISS2,
MACFLAG_IH): Likewise.
(movstricthi_1): Renamed from "*movstricthi".
(load_accumulator, load_accumulator_pair, movsi_insv, insv,
ssaddsi3, sssubsi3, ssnegsi2, signbitssi2, smaxhi3, sminhi3,
abshi2, neghi2, ssneghi2, signbitshi2, movhi_low2high,
movhi_high2high, movhi_low2low, movhi_high2low, movhiv2hi_low,
movhiv2hi_high, composev2hi, movv2hi_hi, movv2hi_hi_low,
movv2hi_hi_high, ssaddhi3, sssubhi3, ssaddv2hi3, sssubv2hi3,
addsubv2hi3, subaddv2hi3, ssaddsubv2hi3, sssubaddv2hi3,
sublohiv2hi3, subhilov2hi3, sssublohiv2hi3, sssubhilov2hi3,
addlohiv2hi3, addhilov2hi3, ssaddlohiv2hi3, ssaddhilov2hi3,
mulhisi_ll, mulhisi_lh, mulhisi_hl, mulhisi_hh, ssnegv2hi2,
ssashiftv2hi3, ssashifthi3, lshiftv2hi3, lshifthi3, packv2hi,
flag_mulhi, flag_mulhisi_parts, flag_machi, flag_machi_acconly,
flag_macinithi, flag_macinit1hi, flag_mulv2hi, flag_mulv2hi_parts,
flag_macv2hi_parts, flag_macv2hi_parts_acconly,
flag_macinitv2hi_parts, flag_macinit1v2hi_parts): New patterns.
From-SVN: r113245
2006-04-25 13:49:27 +02:00
|
|
|
|
|
|
|
|
|
(define_insn "ssashifthi3"
|
|
|
|
|
[(set (match_operand:HI 0 "register_operand" "=d,d,d")
|
|
|
|
|
(if_then_else:HI
|
rtl.def (SS_ABS): New code.
* rtl.def (SS_ABS): New code.
* config/bfin/bfin.c (print_operand): New modifier 'v'.
(enum bfin_builtins): Add BFIN_BUILTIN_SUM_2X16, BFIN_BUILTIN_ABS_1x32,
BFIN_BUILTIN_ROUND_1x32, BFIN_BUILTIN_MULT_1x32x32,
BFIN_BUILTIN_MULT_1x32x32NS, BFIN_BUILTIN_SSASHIFT_1x32.
(bfin_init_builtins): Define them.
(bdesc_1arg, bdesc_2arg): Add some of them here, ...
(bfin_expand_builtin): ... and handle the others here.
* config/bfin/bfin.md (ssabssi2, ssroundsi2, ssashiftsi3,
flag_mul_macv2hi_parts_acconly_andcc0): New patterns.
(ss_absv2hi2): Renamed from absv2hi; use ss_abs code.
(ssashiftv2hi3, ssashifthi3, lshiftv2hi3, lshifthi3): Shift count
operand is only HImode.
From-SVN: r124280
2007-04-29 15:22:04 +02:00
|
|
|
|
(lt (match_operand:HI 2 "vec_shift_operand" "d,Ku4,Ks4") (const_int 0))
|
genmodes.c (make_vector_mode): Allow making VECTOR_MODE_INT of a MODE_PARTIAL_INT mode.
* genmodes.c (make_vector_mode): Allow making VECTOR_MODE_INT of a
MODE_PARTIAL_INT mode.
* config/bfin/bfin-modes.def: Add V2PDI and V2SI.
* config/bfin/bfin.c (print_operand): Add macflag and mac/msu modifiers
for CONST_INTs.
(hard_regno_mode_ok): V2PDImode is ok for accumulators.
* config/bfin/bfin.h (CLASS_MAX_NREGS, HARD_REGNO_NREGS): Handle
V2PDImode.
* config/bfin/predicates.md (const01_operand, vec_shift_operand):
New predicates.
* config/bfin/bfin.md (UNSPEC_MUL_WITH_FLAG, UNSPEC_MAC_WITH_FLAG):
New constants.
(MACFLAG_NONE, MACFLAG_T, MACFLAG_FU, MACFLAG_TFU, MACFLAG_IS,
MACFLAG_IU, MACFLAG_W32, MACFLAG_M, MACFLAG_S2RND, MACFLAG_ISS2,
MACFLAG_IH): Likewise.
(movstricthi_1): Renamed from "*movstricthi".
(load_accumulator, load_accumulator_pair, movsi_insv, insv,
ssaddsi3, sssubsi3, ssnegsi2, signbitssi2, smaxhi3, sminhi3,
abshi2, neghi2, ssneghi2, signbitshi2, movhi_low2high,
movhi_high2high, movhi_low2low, movhi_high2low, movhiv2hi_low,
movhiv2hi_high, composev2hi, movv2hi_hi, movv2hi_hi_low,
movv2hi_hi_high, ssaddhi3, sssubhi3, ssaddv2hi3, sssubv2hi3,
addsubv2hi3, subaddv2hi3, ssaddsubv2hi3, sssubaddv2hi3,
sublohiv2hi3, subhilov2hi3, sssublohiv2hi3, sssubhilov2hi3,
addlohiv2hi3, addhilov2hi3, ssaddlohiv2hi3, ssaddhilov2hi3,
mulhisi_ll, mulhisi_lh, mulhisi_hl, mulhisi_hh, ssnegv2hi2,
ssashiftv2hi3, ssashifthi3, lshiftv2hi3, lshifthi3, packv2hi,
flag_mulhi, flag_mulhisi_parts, flag_machi, flag_machi_acconly,
flag_macinithi, flag_macinit1hi, flag_mulv2hi, flag_mulv2hi_parts,
flag_macv2hi_parts, flag_macv2hi_parts_acconly,
flag_macinitv2hi_parts, flag_macinit1v2hi_parts): New patterns.
From-SVN: r113245
2006-04-25 13:49:27 +02:00
|
|
|
|
(ashiftrt:HI (match_operand:HI 1 "register_operand" "d,d,d")
|
|
|
|
|
(match_dup 2))
|
|
|
|
|
(ss_ashift:HI (match_dup 1) (match_dup 2))))]
|
|
|
|
|
""
|
|
|
|
|
"@
|
2007-02-27 14:55:56 +01:00
|
|
|
|
%0 = ASHIFT %1 BY %h2 (V, S)%!
|
2006-12-07 12:06:08 +01:00
|
|
|
|
%0 = %1 << %2 (V,S)%!
|
|
|
|
|
%0 = %1 >>> %N2 (V,S)%!"
|
From Jie Zhang <jie.zhang@analog.com>:
* config/bfin/predicates.md (p_register_operand): New
predicate.
(dp_register_operand): New predicate.
* config/bfin/bfin-protos.h (WA_05000074): Define.
(ENABLE_WA_05000074): Define.
* config/bfin/bfin.c (bfin_cpus[]): Add WA_05000074 for
all cpus.
(bfin_gen_bundles): Put dsp32shiftimm instruction in slot[0].
* config/bfin/bfin.md (define_attr type): Add dsp32shiftimm.
(define_attr addrtype): Allow load/store register to be
P register.
(define_attr storereg): New.
(define_cpu_unit anomaly_05000074): New.
(define_insn_reservation dsp32shiftimm): New.
(define_insn_reservation dsp32shiftimm_anomaly_05000074): New.
(define_insn_reservation loadp): Cannot use slot2.
(define_insn_reservation loadsp): Cannot use slot2.
(define_insn_reservation storep): Cannot use slot2. Does not
apply when working around 05000074.
(define_insn_reservation storep_anomaly_05000074): New.
(define_insn_reservation storei): Does not apply when working
around 05000074.
(define_insn_reservation storei_anomaly_05000074): New.
(define_attr length): Add dsp32shiftimm case.
(define_insn movsi_insn32, movsi_insv, ashlsi3_insn, ashrsi3,
ror_one, rol_one, lshrsi3, lshrpdi3, ashrpdi3, movhiv2hi_low,
movhiv2hi_high, composev2hi, packv2hi, movv2hi_hi,
ssashiftv2hi3, ssashifthi3, ssashiftsi3, lshiftv2hi3, lshifthi3):
Set type as dsp32shiftimm for dsp32shiftimm alternatives.
From-SVN: r151490
2009-09-07 23:40:23 +02:00
|
|
|
|
[(set_attr "type" "dsp32,dsp32shiftimm,dsp32shiftimm")])
|
genmodes.c (make_vector_mode): Allow making VECTOR_MODE_INT of a MODE_PARTIAL_INT mode.
* genmodes.c (make_vector_mode): Allow making VECTOR_MODE_INT of a
MODE_PARTIAL_INT mode.
* config/bfin/bfin-modes.def: Add V2PDI and V2SI.
* config/bfin/bfin.c (print_operand): Add macflag and mac/msu modifiers
for CONST_INTs.
(hard_regno_mode_ok): V2PDImode is ok for accumulators.
* config/bfin/bfin.h (CLASS_MAX_NREGS, HARD_REGNO_NREGS): Handle
V2PDImode.
* config/bfin/predicates.md (const01_operand, vec_shift_operand):
New predicates.
* config/bfin/bfin.md (UNSPEC_MUL_WITH_FLAG, UNSPEC_MAC_WITH_FLAG):
New constants.
(MACFLAG_NONE, MACFLAG_T, MACFLAG_FU, MACFLAG_TFU, MACFLAG_IS,
MACFLAG_IU, MACFLAG_W32, MACFLAG_M, MACFLAG_S2RND, MACFLAG_ISS2,
MACFLAG_IH): Likewise.
(movstricthi_1): Renamed from "*movstricthi".
(load_accumulator, load_accumulator_pair, movsi_insv, insv,
ssaddsi3, sssubsi3, ssnegsi2, signbitssi2, smaxhi3, sminhi3,
abshi2, neghi2, ssneghi2, signbitshi2, movhi_low2high,
movhi_high2high, movhi_low2low, movhi_high2low, movhiv2hi_low,
movhiv2hi_high, composev2hi, movv2hi_hi, movv2hi_hi_low,
movv2hi_hi_high, ssaddhi3, sssubhi3, ssaddv2hi3, sssubv2hi3,
addsubv2hi3, subaddv2hi3, ssaddsubv2hi3, sssubaddv2hi3,
sublohiv2hi3, subhilov2hi3, sssublohiv2hi3, sssubhilov2hi3,
addlohiv2hi3, addhilov2hi3, ssaddlohiv2hi3, ssaddhilov2hi3,
mulhisi_ll, mulhisi_lh, mulhisi_hl, mulhisi_hh, ssnegv2hi2,
ssashiftv2hi3, ssashifthi3, lshiftv2hi3, lshifthi3, packv2hi,
flag_mulhi, flag_mulhisi_parts, flag_machi, flag_machi_acconly,
flag_macinithi, flag_macinit1hi, flag_mulv2hi, flag_mulv2hi_parts,
flag_macv2hi_parts, flag_macv2hi_parts_acconly,
flag_macinitv2hi_parts, flag_macinit1v2hi_parts): New patterns.
From-SVN: r113245
2006-04-25 13:49:27 +02:00
|
|
|
|
|
rtl.def (SS_ABS): New code.
* rtl.def (SS_ABS): New code.
* config/bfin/bfin.c (print_operand): New modifier 'v'.
(enum bfin_builtins): Add BFIN_BUILTIN_SUM_2X16, BFIN_BUILTIN_ABS_1x32,
BFIN_BUILTIN_ROUND_1x32, BFIN_BUILTIN_MULT_1x32x32,
BFIN_BUILTIN_MULT_1x32x32NS, BFIN_BUILTIN_SSASHIFT_1x32.
(bfin_init_builtins): Define them.
(bdesc_1arg, bdesc_2arg): Add some of them here, ...
(bfin_expand_builtin): ... and handle the others here.
* config/bfin/bfin.md (ssabssi2, ssroundsi2, ssashiftsi3,
flag_mul_macv2hi_parts_acconly_andcc0): New patterns.
(ss_absv2hi2): Renamed from absv2hi; use ss_abs code.
(ssashiftv2hi3, ssashifthi3, lshiftv2hi3, lshifthi3): Shift count
operand is only HImode.
From-SVN: r124280
2007-04-29 15:22:04 +02:00
|
|
|
|
(define_insn "ssashiftsi3"
|
|
|
|
|
[(set (match_operand:SI 0 "register_operand" "=d,d,d")
|
|
|
|
|
(if_then_else:SI
|
|
|
|
|
(lt (match_operand:HI 2 "reg_or_const_int_operand" "d,Ku5,Ks5") (const_int 0))
|
|
|
|
|
(ashiftrt:SI (match_operand:HI 1 "register_operand" "d,d,d")
|
|
|
|
|
(match_dup 2))
|
|
|
|
|
(ss_ashift:SI (match_dup 1) (match_dup 2))))]
|
|
|
|
|
""
|
|
|
|
|
"@
|
|
|
|
|
%0 = ASHIFT %1 BY %h2 (S)%!
|
|
|
|
|
%0 = %1 << %2 (S)%!
|
|
|
|
|
%0 = %1 >>> %N2 (S)%!"
|
From Jie Zhang <jie.zhang@analog.com>:
* config/bfin/predicates.md (p_register_operand): New
predicate.
(dp_register_operand): New predicate.
* config/bfin/bfin-protos.h (WA_05000074): Define.
(ENABLE_WA_05000074): Define.
* config/bfin/bfin.c (bfin_cpus[]): Add WA_05000074 for
all cpus.
(bfin_gen_bundles): Put dsp32shiftimm instruction in slot[0].
* config/bfin/bfin.md (define_attr type): Add dsp32shiftimm.
(define_attr addrtype): Allow load/store register to be
P register.
(define_attr storereg): New.
(define_cpu_unit anomaly_05000074): New.
(define_insn_reservation dsp32shiftimm): New.
(define_insn_reservation dsp32shiftimm_anomaly_05000074): New.
(define_insn_reservation loadp): Cannot use slot2.
(define_insn_reservation loadsp): Cannot use slot2.
(define_insn_reservation storep): Cannot use slot2. Does not
apply when working around 05000074.
(define_insn_reservation storep_anomaly_05000074): New.
(define_insn_reservation storei): Does not apply when working
around 05000074.
(define_insn_reservation storei_anomaly_05000074): New.
(define_attr length): Add dsp32shiftimm case.
(define_insn movsi_insn32, movsi_insv, ashlsi3_insn, ashrsi3,
ror_one, rol_one, lshrsi3, lshrpdi3, ashrpdi3, movhiv2hi_low,
movhiv2hi_high, composev2hi, packv2hi, movv2hi_hi,
ssashiftv2hi3, ssashifthi3, ssashiftsi3, lshiftv2hi3, lshifthi3):
Set type as dsp32shiftimm for dsp32shiftimm alternatives.
From-SVN: r151490
2009-09-07 23:40:23 +02:00
|
|
|
|
[(set_attr "type" "dsp32,dsp32shiftimm,dsp32shiftimm")])
|
rtl.def (SS_ABS): New code.
* rtl.def (SS_ABS): New code.
* config/bfin/bfin.c (print_operand): New modifier 'v'.
(enum bfin_builtins): Add BFIN_BUILTIN_SUM_2X16, BFIN_BUILTIN_ABS_1x32,
BFIN_BUILTIN_ROUND_1x32, BFIN_BUILTIN_MULT_1x32x32,
BFIN_BUILTIN_MULT_1x32x32NS, BFIN_BUILTIN_SSASHIFT_1x32.
(bfin_init_builtins): Define them.
(bdesc_1arg, bdesc_2arg): Add some of them here, ...
(bfin_expand_builtin): ... and handle the others here.
* config/bfin/bfin.md (ssabssi2, ssroundsi2, ssashiftsi3,
flag_mul_macv2hi_parts_acconly_andcc0): New patterns.
(ss_absv2hi2): Renamed from absv2hi; use ss_abs code.
(ssashiftv2hi3, ssashifthi3, lshiftv2hi3, lshifthi3): Shift count
operand is only HImode.
From-SVN: r124280
2007-04-29 15:22:04 +02:00
|
|
|
|
|
genmodes.c (make_vector_mode): Allow making VECTOR_MODE_INT of a MODE_PARTIAL_INT mode.
* genmodes.c (make_vector_mode): Allow making VECTOR_MODE_INT of a
MODE_PARTIAL_INT mode.
* config/bfin/bfin-modes.def: Add V2PDI and V2SI.
* config/bfin/bfin.c (print_operand): Add macflag and mac/msu modifiers
for CONST_INTs.
(hard_regno_mode_ok): V2PDImode is ok for accumulators.
* config/bfin/bfin.h (CLASS_MAX_NREGS, HARD_REGNO_NREGS): Handle
V2PDImode.
* config/bfin/predicates.md (const01_operand, vec_shift_operand):
New predicates.
* config/bfin/bfin.md (UNSPEC_MUL_WITH_FLAG, UNSPEC_MAC_WITH_FLAG):
New constants.
(MACFLAG_NONE, MACFLAG_T, MACFLAG_FU, MACFLAG_TFU, MACFLAG_IS,
MACFLAG_IU, MACFLAG_W32, MACFLAG_M, MACFLAG_S2RND, MACFLAG_ISS2,
MACFLAG_IH): Likewise.
(movstricthi_1): Renamed from "*movstricthi".
(load_accumulator, load_accumulator_pair, movsi_insv, insv,
ssaddsi3, sssubsi3, ssnegsi2, signbitssi2, smaxhi3, sminhi3,
abshi2, neghi2, ssneghi2, signbitshi2, movhi_low2high,
movhi_high2high, movhi_low2low, movhi_high2low, movhiv2hi_low,
movhiv2hi_high, composev2hi, movv2hi_hi, movv2hi_hi_low,
movv2hi_hi_high, ssaddhi3, sssubhi3, ssaddv2hi3, sssubv2hi3,
addsubv2hi3, subaddv2hi3, ssaddsubv2hi3, sssubaddv2hi3,
sublohiv2hi3, subhilov2hi3, sssublohiv2hi3, sssubhilov2hi3,
addlohiv2hi3, addhilov2hi3, ssaddlohiv2hi3, ssaddhilov2hi3,
mulhisi_ll, mulhisi_lh, mulhisi_hl, mulhisi_hh, ssnegv2hi2,
ssashiftv2hi3, ssashifthi3, lshiftv2hi3, lshifthi3, packv2hi,
flag_mulhi, flag_mulhisi_parts, flag_machi, flag_machi_acconly,
flag_macinithi, flag_macinit1hi, flag_mulv2hi, flag_mulv2hi_parts,
flag_macv2hi_parts, flag_macv2hi_parts_acconly,
flag_macinitv2hi_parts, flag_macinit1v2hi_parts): New patterns.
From-SVN: r113245
2006-04-25 13:49:27 +02:00
|
|
|
|
(define_insn "lshiftv2hi3"
|
|
|
|
|
[(set (match_operand:V2HI 0 "register_operand" "=d,d,d")
|
|
|
|
|
(if_then_else:V2HI
|
rtl.def (SS_ABS): New code.
* rtl.def (SS_ABS): New code.
* config/bfin/bfin.c (print_operand): New modifier 'v'.
(enum bfin_builtins): Add BFIN_BUILTIN_SUM_2X16, BFIN_BUILTIN_ABS_1x32,
BFIN_BUILTIN_ROUND_1x32, BFIN_BUILTIN_MULT_1x32x32,
BFIN_BUILTIN_MULT_1x32x32NS, BFIN_BUILTIN_SSASHIFT_1x32.
(bfin_init_builtins): Define them.
(bdesc_1arg, bdesc_2arg): Add some of them here, ...
(bfin_expand_builtin): ... and handle the others here.
* config/bfin/bfin.md (ssabssi2, ssroundsi2, ssashiftsi3,
flag_mul_macv2hi_parts_acconly_andcc0): New patterns.
(ss_absv2hi2): Renamed from absv2hi; use ss_abs code.
(ssashiftv2hi3, ssashifthi3, lshiftv2hi3, lshifthi3): Shift count
operand is only HImode.
From-SVN: r124280
2007-04-29 15:22:04 +02:00
|
|
|
|
(lt (match_operand:HI 2 "vec_shift_operand" "d,Ku4,Ks4") (const_int 0))
|
genmodes.c (make_vector_mode): Allow making VECTOR_MODE_INT of a MODE_PARTIAL_INT mode.
* genmodes.c (make_vector_mode): Allow making VECTOR_MODE_INT of a
MODE_PARTIAL_INT mode.
* config/bfin/bfin-modes.def: Add V2PDI and V2SI.
* config/bfin/bfin.c (print_operand): Add macflag and mac/msu modifiers
for CONST_INTs.
(hard_regno_mode_ok): V2PDImode is ok for accumulators.
* config/bfin/bfin.h (CLASS_MAX_NREGS, HARD_REGNO_NREGS): Handle
V2PDImode.
* config/bfin/predicates.md (const01_operand, vec_shift_operand):
New predicates.
* config/bfin/bfin.md (UNSPEC_MUL_WITH_FLAG, UNSPEC_MAC_WITH_FLAG):
New constants.
(MACFLAG_NONE, MACFLAG_T, MACFLAG_FU, MACFLAG_TFU, MACFLAG_IS,
MACFLAG_IU, MACFLAG_W32, MACFLAG_M, MACFLAG_S2RND, MACFLAG_ISS2,
MACFLAG_IH): Likewise.
(movstricthi_1): Renamed from "*movstricthi".
(load_accumulator, load_accumulator_pair, movsi_insv, insv,
ssaddsi3, sssubsi3, ssnegsi2, signbitssi2, smaxhi3, sminhi3,
abshi2, neghi2, ssneghi2, signbitshi2, movhi_low2high,
movhi_high2high, movhi_low2low, movhi_high2low, movhiv2hi_low,
movhiv2hi_high, composev2hi, movv2hi_hi, movv2hi_hi_low,
movv2hi_hi_high, ssaddhi3, sssubhi3, ssaddv2hi3, sssubv2hi3,
addsubv2hi3, subaddv2hi3, ssaddsubv2hi3, sssubaddv2hi3,
sublohiv2hi3, subhilov2hi3, sssublohiv2hi3, sssubhilov2hi3,
addlohiv2hi3, addhilov2hi3, ssaddlohiv2hi3, ssaddhilov2hi3,
mulhisi_ll, mulhisi_lh, mulhisi_hl, mulhisi_hh, ssnegv2hi2,
ssashiftv2hi3, ssashifthi3, lshiftv2hi3, lshifthi3, packv2hi,
flag_mulhi, flag_mulhisi_parts, flag_machi, flag_machi_acconly,
flag_macinithi, flag_macinit1hi, flag_mulv2hi, flag_mulv2hi_parts,
flag_macv2hi_parts, flag_macv2hi_parts_acconly,
flag_macinitv2hi_parts, flag_macinit1v2hi_parts): New patterns.
From-SVN: r113245
2006-04-25 13:49:27 +02:00
|
|
|
|
(lshiftrt:V2HI (match_operand:V2HI 1 "register_operand" "d,d,d")
|
|
|
|
|
(match_dup 2))
|
|
|
|
|
(ashift:V2HI (match_dup 1) (match_dup 2))))]
|
|
|
|
|
""
|
|
|
|
|
"@
|
2007-02-27 14:55:56 +01:00
|
|
|
|
%0 = LSHIFT %1 BY %h2 (V)%!
|
2006-12-07 12:06:08 +01:00
|
|
|
|
%0 = %1 << %2 (V)%!
|
|
|
|
|
%0 = %1 >> %N2 (V)%!"
|
From Jie Zhang <jie.zhang@analog.com>:
* config/bfin/predicates.md (p_register_operand): New
predicate.
(dp_register_operand): New predicate.
* config/bfin/bfin-protos.h (WA_05000074): Define.
(ENABLE_WA_05000074): Define.
* config/bfin/bfin.c (bfin_cpus[]): Add WA_05000074 for
all cpus.
(bfin_gen_bundles): Put dsp32shiftimm instruction in slot[0].
* config/bfin/bfin.md (define_attr type): Add dsp32shiftimm.
(define_attr addrtype): Allow load/store register to be
P register.
(define_attr storereg): New.
(define_cpu_unit anomaly_05000074): New.
(define_insn_reservation dsp32shiftimm): New.
(define_insn_reservation dsp32shiftimm_anomaly_05000074): New.
(define_insn_reservation loadp): Cannot use slot2.
(define_insn_reservation loadsp): Cannot use slot2.
(define_insn_reservation storep): Cannot use slot2. Does not
apply when working around 05000074.
(define_insn_reservation storep_anomaly_05000074): New.
(define_insn_reservation storei): Does not apply when working
around 05000074.
(define_insn_reservation storei_anomaly_05000074): New.
(define_attr length): Add dsp32shiftimm case.
(define_insn movsi_insn32, movsi_insv, ashlsi3_insn, ashrsi3,
ror_one, rol_one, lshrsi3, lshrpdi3, ashrpdi3, movhiv2hi_low,
movhiv2hi_high, composev2hi, packv2hi, movv2hi_hi,
ssashiftv2hi3, ssashifthi3, ssashiftsi3, lshiftv2hi3, lshifthi3):
Set type as dsp32shiftimm for dsp32shiftimm alternatives.
From-SVN: r151490
2009-09-07 23:40:23 +02:00
|
|
|
|
[(set_attr "type" "dsp32,dsp32shiftimm,dsp32shiftimm")])
|
genmodes.c (make_vector_mode): Allow making VECTOR_MODE_INT of a MODE_PARTIAL_INT mode.
* genmodes.c (make_vector_mode): Allow making VECTOR_MODE_INT of a
MODE_PARTIAL_INT mode.
* config/bfin/bfin-modes.def: Add V2PDI and V2SI.
* config/bfin/bfin.c (print_operand): Add macflag and mac/msu modifiers
for CONST_INTs.
(hard_regno_mode_ok): V2PDImode is ok for accumulators.
* config/bfin/bfin.h (CLASS_MAX_NREGS, HARD_REGNO_NREGS): Handle
V2PDImode.
* config/bfin/predicates.md (const01_operand, vec_shift_operand):
New predicates.
* config/bfin/bfin.md (UNSPEC_MUL_WITH_FLAG, UNSPEC_MAC_WITH_FLAG):
New constants.
(MACFLAG_NONE, MACFLAG_T, MACFLAG_FU, MACFLAG_TFU, MACFLAG_IS,
MACFLAG_IU, MACFLAG_W32, MACFLAG_M, MACFLAG_S2RND, MACFLAG_ISS2,
MACFLAG_IH): Likewise.
(movstricthi_1): Renamed from "*movstricthi".
(load_accumulator, load_accumulator_pair, movsi_insv, insv,
ssaddsi3, sssubsi3, ssnegsi2, signbitssi2, smaxhi3, sminhi3,
abshi2, neghi2, ssneghi2, signbitshi2, movhi_low2high,
movhi_high2high, movhi_low2low, movhi_high2low, movhiv2hi_low,
movhiv2hi_high, composev2hi, movv2hi_hi, movv2hi_hi_low,
movv2hi_hi_high, ssaddhi3, sssubhi3, ssaddv2hi3, sssubv2hi3,
addsubv2hi3, subaddv2hi3, ssaddsubv2hi3, sssubaddv2hi3,
sublohiv2hi3, subhilov2hi3, sssublohiv2hi3, sssubhilov2hi3,
addlohiv2hi3, addhilov2hi3, ssaddlohiv2hi3, ssaddhilov2hi3,
mulhisi_ll, mulhisi_lh, mulhisi_hl, mulhisi_hh, ssnegv2hi2,
ssashiftv2hi3, ssashifthi3, lshiftv2hi3, lshifthi3, packv2hi,
flag_mulhi, flag_mulhisi_parts, flag_machi, flag_machi_acconly,
flag_macinithi, flag_macinit1hi, flag_mulv2hi, flag_mulv2hi_parts,
flag_macv2hi_parts, flag_macv2hi_parts_acconly,
flag_macinitv2hi_parts, flag_macinit1v2hi_parts): New patterns.
From-SVN: r113245
2006-04-25 13:49:27 +02:00
|
|
|
|
|
|
|
|
|
(define_insn "lshifthi3"
|
|
|
|
|
[(set (match_operand:HI 0 "register_operand" "=d,d,d")
|
|
|
|
|
(if_then_else:HI
|
rtl.def (SS_ABS): New code.
* rtl.def (SS_ABS): New code.
* config/bfin/bfin.c (print_operand): New modifier 'v'.
(enum bfin_builtins): Add BFIN_BUILTIN_SUM_2X16, BFIN_BUILTIN_ABS_1x32,
BFIN_BUILTIN_ROUND_1x32, BFIN_BUILTIN_MULT_1x32x32,
BFIN_BUILTIN_MULT_1x32x32NS, BFIN_BUILTIN_SSASHIFT_1x32.
(bfin_init_builtins): Define them.
(bdesc_1arg, bdesc_2arg): Add some of them here, ...
(bfin_expand_builtin): ... and handle the others here.
* config/bfin/bfin.md (ssabssi2, ssroundsi2, ssashiftsi3,
flag_mul_macv2hi_parts_acconly_andcc0): New patterns.
(ss_absv2hi2): Renamed from absv2hi; use ss_abs code.
(ssashiftv2hi3, ssashifthi3, lshiftv2hi3, lshifthi3): Shift count
operand is only HImode.
From-SVN: r124280
2007-04-29 15:22:04 +02:00
|
|
|
|
(lt (match_operand:HI 2 "vec_shift_operand" "d,Ku4,Ks4") (const_int 0))
|
genmodes.c (make_vector_mode): Allow making VECTOR_MODE_INT of a MODE_PARTIAL_INT mode.
* genmodes.c (make_vector_mode): Allow making VECTOR_MODE_INT of a
MODE_PARTIAL_INT mode.
* config/bfin/bfin-modes.def: Add V2PDI and V2SI.
* config/bfin/bfin.c (print_operand): Add macflag and mac/msu modifiers
for CONST_INTs.
(hard_regno_mode_ok): V2PDImode is ok for accumulators.
* config/bfin/bfin.h (CLASS_MAX_NREGS, HARD_REGNO_NREGS): Handle
V2PDImode.
* config/bfin/predicates.md (const01_operand, vec_shift_operand):
New predicates.
* config/bfin/bfin.md (UNSPEC_MUL_WITH_FLAG, UNSPEC_MAC_WITH_FLAG):
New constants.
(MACFLAG_NONE, MACFLAG_T, MACFLAG_FU, MACFLAG_TFU, MACFLAG_IS,
MACFLAG_IU, MACFLAG_W32, MACFLAG_M, MACFLAG_S2RND, MACFLAG_ISS2,
MACFLAG_IH): Likewise.
(movstricthi_1): Renamed from "*movstricthi".
(load_accumulator, load_accumulator_pair, movsi_insv, insv,
ssaddsi3, sssubsi3, ssnegsi2, signbitssi2, smaxhi3, sminhi3,
abshi2, neghi2, ssneghi2, signbitshi2, movhi_low2high,
movhi_high2high, movhi_low2low, movhi_high2low, movhiv2hi_low,
movhiv2hi_high, composev2hi, movv2hi_hi, movv2hi_hi_low,
movv2hi_hi_high, ssaddhi3, sssubhi3, ssaddv2hi3, sssubv2hi3,
addsubv2hi3, subaddv2hi3, ssaddsubv2hi3, sssubaddv2hi3,
sublohiv2hi3, subhilov2hi3, sssublohiv2hi3, sssubhilov2hi3,
addlohiv2hi3, addhilov2hi3, ssaddlohiv2hi3, ssaddhilov2hi3,
mulhisi_ll, mulhisi_lh, mulhisi_hl, mulhisi_hh, ssnegv2hi2,
ssashiftv2hi3, ssashifthi3, lshiftv2hi3, lshifthi3, packv2hi,
flag_mulhi, flag_mulhisi_parts, flag_machi, flag_machi_acconly,
flag_macinithi, flag_macinit1hi, flag_mulv2hi, flag_mulv2hi_parts,
flag_macv2hi_parts, flag_macv2hi_parts_acconly,
flag_macinitv2hi_parts, flag_macinit1v2hi_parts): New patterns.
From-SVN: r113245
2006-04-25 13:49:27 +02:00
|
|
|
|
(lshiftrt:HI (match_operand:HI 1 "register_operand" "d,d,d")
|
|
|
|
|
(match_dup 2))
|
|
|
|
|
(ashift:HI (match_dup 1) (match_dup 2))))]
|
|
|
|
|
""
|
|
|
|
|
"@
|
2007-02-27 14:55:56 +01:00
|
|
|
|
%0 = LSHIFT %1 BY %h2 (V)%!
|
2006-12-07 12:06:08 +01:00
|
|
|
|
%0 = %1 << %2 (V)%!
|
|
|
|
|
%0 = %1 >> %N2 (V)%!"
|
From Jie Zhang <jie.zhang@analog.com>:
* config/bfin/predicates.md (p_register_operand): New
predicate.
(dp_register_operand): New predicate.
* config/bfin/bfin-protos.h (WA_05000074): Define.
(ENABLE_WA_05000074): Define.
* config/bfin/bfin.c (bfin_cpus[]): Add WA_05000074 for
all cpus.
(bfin_gen_bundles): Put dsp32shiftimm instruction in slot[0].
* config/bfin/bfin.md (define_attr type): Add dsp32shiftimm.
(define_attr addrtype): Allow load/store register to be
P register.
(define_attr storereg): New.
(define_cpu_unit anomaly_05000074): New.
(define_insn_reservation dsp32shiftimm): New.
(define_insn_reservation dsp32shiftimm_anomaly_05000074): New.
(define_insn_reservation loadp): Cannot use slot2.
(define_insn_reservation loadsp): Cannot use slot2.
(define_insn_reservation storep): Cannot use slot2. Does not
apply when working around 05000074.
(define_insn_reservation storep_anomaly_05000074): New.
(define_insn_reservation storei): Does not apply when working
around 05000074.
(define_insn_reservation storei_anomaly_05000074): New.
(define_attr length): Add dsp32shiftimm case.
(define_insn movsi_insn32, movsi_insv, ashlsi3_insn, ashrsi3,
ror_one, rol_one, lshrsi3, lshrpdi3, ashrpdi3, movhiv2hi_low,
movhiv2hi_high, composev2hi, packv2hi, movv2hi_hi,
ssashiftv2hi3, ssashifthi3, ssashiftsi3, lshiftv2hi3, lshifthi3):
Set type as dsp32shiftimm for dsp32shiftimm alternatives.
From-SVN: r151490
2009-09-07 23:40:23 +02:00
|
|
|
|
[(set_attr "type" "dsp32,dsp32shiftimm,dsp32shiftimm")])
|
genmodes.c (make_vector_mode): Allow making VECTOR_MODE_INT of a MODE_PARTIAL_INT mode.
* genmodes.c (make_vector_mode): Allow making VECTOR_MODE_INT of a
MODE_PARTIAL_INT mode.
* config/bfin/bfin-modes.def: Add V2PDI and V2SI.
* config/bfin/bfin.c (print_operand): Add macflag and mac/msu modifiers
for CONST_INTs.
(hard_regno_mode_ok): V2PDImode is ok for accumulators.
* config/bfin/bfin.h (CLASS_MAX_NREGS, HARD_REGNO_NREGS): Handle
V2PDImode.
* config/bfin/predicates.md (const01_operand, vec_shift_operand):
New predicates.
* config/bfin/bfin.md (UNSPEC_MUL_WITH_FLAG, UNSPEC_MAC_WITH_FLAG):
New constants.
(MACFLAG_NONE, MACFLAG_T, MACFLAG_FU, MACFLAG_TFU, MACFLAG_IS,
MACFLAG_IU, MACFLAG_W32, MACFLAG_M, MACFLAG_S2RND, MACFLAG_ISS2,
MACFLAG_IH): Likewise.
(movstricthi_1): Renamed from "*movstricthi".
(load_accumulator, load_accumulator_pair, movsi_insv, insv,
ssaddsi3, sssubsi3, ssnegsi2, signbitssi2, smaxhi3, sminhi3,
abshi2, neghi2, ssneghi2, signbitshi2, movhi_low2high,
movhi_high2high, movhi_low2low, movhi_high2low, movhiv2hi_low,
movhiv2hi_high, composev2hi, movv2hi_hi, movv2hi_hi_low,
movv2hi_hi_high, ssaddhi3, sssubhi3, ssaddv2hi3, sssubv2hi3,
addsubv2hi3, subaddv2hi3, ssaddsubv2hi3, sssubaddv2hi3,
sublohiv2hi3, subhilov2hi3, sssublohiv2hi3, sssubhilov2hi3,
addlohiv2hi3, addhilov2hi3, ssaddlohiv2hi3, ssaddhilov2hi3,
mulhisi_ll, mulhisi_lh, mulhisi_hl, mulhisi_hh, ssnegv2hi2,
ssashiftv2hi3, ssashifthi3, lshiftv2hi3, lshifthi3, packv2hi,
flag_mulhi, flag_mulhisi_parts, flag_machi, flag_machi_acconly,
flag_macinithi, flag_macinit1hi, flag_mulv2hi, flag_mulv2hi_parts,
flag_macv2hi_parts, flag_macv2hi_parts_acconly,
flag_macinitv2hi_parts, flag_macinit1v2hi_parts): New patterns.
From-SVN: r113245
2006-04-25 13:49:27 +02:00
|
|
|
|
|
2008-05-15 15:25:26 +02:00
|
|
|
|
;; Load without alignment exception (masking off low bits)
|
|
|
|
|
|
|
|
|
|
(define_insn "loadbytes"
|
|
|
|
|
[(set (match_operand:SI 0 "register_operand" "=d")
|
|
|
|
|
(mem:SI (and:SI (match_operand:SI 1 "register_operand" "b")
|
|
|
|
|
(const_int -4))))]
|
|
|
|
|
""
|
|
|
|
|
"DISALGNEXCPT || %0 = [%1];"
|
|
|
|
|
[(set_attr "type" "mcld")
|
|
|
|
|
(set_attr "length" "8")])
|
2009-09-03 17:37:28 +02:00
|
|
|
|
|
|
|
|
|
(include "sync.md")
|