iterators.md: New file.
2010-08-09 Sofiane Naci <sofiane.naci@arm.com>
* config/arm/iterators.md: New file.
* config/arm/arm.md: Include iterators.md.
(QHSI): Move to new file.
(LTUGEU, cnb, optab, ior_xor): Likewise.
* config/arm/iwmmxt.md (VMMX): Move to new file.
(VSHFT, MMX_char): Likewise.
* config/arm/neon.md (VD): Move to new file.
(VDX, VDI, VQ, VQX, VQI, VQXMOV, VSTRUCT, VTAB, V_TAB_n, VW): Likewise.
(VN, VDQ, VDQW, VDQIW, VCVTF, VCVTI, VMD, VMQ, VMDQ, VMDI): Likewise.
(VMDQI, VX, VE, V64, V32, V_CVTTO, V_elem, V_ext, V_two_elem): Likewise.
(V_three_elem, V_four_elem, V_req, V_widen, V_narrow, V_HALF): Likewise.
(V_half,V_DOUBLE, V_double, V_double_width, V_cmp_result): Likewise.
(V_if_elem, V_s_elem, V_u_elem, V_uf_sclr, V_sz_elem, VD_dup): Likewise.
(V_PAIR, vqh_ops, vqhs_ops, VQH_mnem, VQH_sign, V_suf64): Likewise.
(scalar_mul_constraint,Is_float_mode, Scalar_mul_8_16): Likewise.
(Is_d_reg, V_mode_nunits): Likewise.
* config/arm/vec-common.md (VALL): Move to new file.
(VALLW, VINT, VINTW): Likewise.
From-SVN: r163058
2010-08-10 15:37:25 +02:00
|
|
|
;; Code and mode itertator and attribute definitions for the ARM backend
|
2017-01-01 13:07:43 +01:00
|
|
|
;; Copyright (C) 2010-2017 Free Software Foundation, Inc.
|
iterators.md: New file.
2010-08-09 Sofiane Naci <sofiane.naci@arm.com>
* config/arm/iterators.md: New file.
* config/arm/arm.md: Include iterators.md.
(QHSI): Move to new file.
(LTUGEU, cnb, optab, ior_xor): Likewise.
* config/arm/iwmmxt.md (VMMX): Move to new file.
(VSHFT, MMX_char): Likewise.
* config/arm/neon.md (VD): Move to new file.
(VDX, VDI, VQ, VQX, VQI, VQXMOV, VSTRUCT, VTAB, V_TAB_n, VW): Likewise.
(VN, VDQ, VDQW, VDQIW, VCVTF, VCVTI, VMD, VMQ, VMDQ, VMDI): Likewise.
(VMDQI, VX, VE, V64, V32, V_CVTTO, V_elem, V_ext, V_two_elem): Likewise.
(V_three_elem, V_four_elem, V_req, V_widen, V_narrow, V_HALF): Likewise.
(V_half,V_DOUBLE, V_double, V_double_width, V_cmp_result): Likewise.
(V_if_elem, V_s_elem, V_u_elem, V_uf_sclr, V_sz_elem, VD_dup): Likewise.
(V_PAIR, vqh_ops, vqhs_ops, VQH_mnem, VQH_sign, V_suf64): Likewise.
(scalar_mul_constraint,Is_float_mode, Scalar_mul_8_16): Likewise.
(Is_d_reg, V_mode_nunits): Likewise.
* config/arm/vec-common.md (VALL): Move to new file.
(VALLW, VINT, VINTW): Likewise.
From-SVN: r163058
2010-08-10 15:37:25 +02:00
|
|
|
;; Contributed by ARM Ltd.
|
|
|
|
;;
|
|
|
|
;; This file is part of GCC.
|
|
|
|
;;
|
|
|
|
;; GCC is free software; you can redistribute it and/or modify it
|
|
|
|
;; under the terms of the GNU General Public License as published
|
|
|
|
;; by the Free Software Foundation; either version 3, or (at your
|
|
|
|
;; option) any later version.
|
|
|
|
|
|
|
|
;; GCC is distributed in the hope that it will be useful, but WITHOUT
|
|
|
|
;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
|
|
|
|
;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
|
|
|
|
;; License for more details.
|
|
|
|
|
|
|
|
;; You should have received a copy of the GNU General Public License
|
|
|
|
;; along with GCC; see the file COPYING3. If not see
|
|
|
|
;; <http://www.gnu.org/licenses/>.
|
|
|
|
|
|
|
|
|
|
|
|
;;----------------------------------------------------------------------------
|
|
|
|
;; Mode iterators
|
|
|
|
;;----------------------------------------------------------------------------
|
|
|
|
|
|
|
|
;; A list of modes that are exactly 64 bits in size. This is used to expand
|
|
|
|
;; some splits that are the same for all modes when operating on ARM
|
|
|
|
;; registers.
|
|
|
|
(define_mode_iterator ANY64 [DI DF V8QI V4HI V2SI V2SF])
|
|
|
|
|
2010-09-15 13:18:07 +02:00
|
|
|
(define_mode_iterator ANY128 [V2DI V2DF V16QI V8HI V4SI V4SF])
|
|
|
|
|
iterators.md: New file.
2010-08-09 Sofiane Naci <sofiane.naci@arm.com>
* config/arm/iterators.md: New file.
* config/arm/arm.md: Include iterators.md.
(QHSI): Move to new file.
(LTUGEU, cnb, optab, ior_xor): Likewise.
* config/arm/iwmmxt.md (VMMX): Move to new file.
(VSHFT, MMX_char): Likewise.
* config/arm/neon.md (VD): Move to new file.
(VDX, VDI, VQ, VQX, VQI, VQXMOV, VSTRUCT, VTAB, V_TAB_n, VW): Likewise.
(VN, VDQ, VDQW, VDQIW, VCVTF, VCVTI, VMD, VMQ, VMDQ, VMDI): Likewise.
(VMDQI, VX, VE, V64, V32, V_CVTTO, V_elem, V_ext, V_two_elem): Likewise.
(V_three_elem, V_four_elem, V_req, V_widen, V_narrow, V_HALF): Likewise.
(V_half,V_DOUBLE, V_double, V_double_width, V_cmp_result): Likewise.
(V_if_elem, V_s_elem, V_u_elem, V_uf_sclr, V_sz_elem, VD_dup): Likewise.
(V_PAIR, vqh_ops, vqhs_ops, VQH_mnem, VQH_sign, V_suf64): Likewise.
(scalar_mul_constraint,Is_float_mode, Scalar_mul_8_16): Likewise.
(Is_d_reg, V_mode_nunits): Likewise.
* config/arm/vec-common.md (VALL): Move to new file.
(VALLW, VINT, VINTW): Likewise.
From-SVN: r163058
2010-08-10 15:37:25 +02:00
|
|
|
;; A list of integer modes that are up to one word long
|
|
|
|
(define_mode_iterator QHSI [QI HI SI])
|
|
|
|
|
2015-10-09 12:53:31 +02:00
|
|
|
;; A list of integer modes that are half and one word long
|
|
|
|
(define_mode_iterator HSI [HI SI])
|
|
|
|
|
2011-10-14 16:38:58 +02:00
|
|
|
;; A list of integer modes that are less than a word
|
|
|
|
(define_mode_iterator NARROW [QI HI])
|
|
|
|
|
2012-05-29 16:14:06 +02:00
|
|
|
;; A list of all the integer modes up to 64bit
|
2011-10-14 16:38:58 +02:00
|
|
|
(define_mode_iterator QHSD [QI HI SI DI])
|
|
|
|
|
|
|
|
;; A list of the 32bit and 64bit integer modes
|
|
|
|
(define_mode_iterator SIDI [SI DI])
|
|
|
|
|
2012-07-05 11:07:00 +02:00
|
|
|
;; A list of modes which the VFP unit can handle
|
[ARM] Remove redundant TARGET_VFP
* arm.h (TARGET_VFP): Delete.
(TARGET_VFPD32): Remove references to TARGET_VFP.
(TARGET_VFP3, TARGET_VFP5): Likewise.
(TARGET_VFP_SINGLE, TARGET_VFP_DOUBLE): Likewise.
(TARGET_NEON_FP16): Likewise.
(TARGET_FMA): Likewise.
(TARGET_CRYPTO): Likewise.
(TARGET_NEON): Likewise.
(SECONDARY_OUTPUT_RELOAD_CLASS): Likewise.
(FUNCTION_ARG_REGNO_P): Likewise.
* arm.c (arm_option_check_internal): Likewise.
(arm_option_override): Likewise.
(use_return_insn): Likewise.
(arm_function_value_regno_p): Likewise.
(arm_apply_result_size): Likewise.
(use_vfp_abi): Likewise.
(arm_legitimate_address_outer_p): Likewise.
(thumb2_legitimate_address_p): Likewise.
(arm_legitimate_index_p): Likewise.
(thumb2_legitimate_index_p): Likewise.
(arm_legitimate_address): Likewise.
(arm_get_vfp_saved_size): Likewise.
(arm_emit_vfp_multi_reg_pop): Likewise.
(arm_get_frame_offsets): Likewise.
(arm_save_coproc_regs): Likewise.
(arm_hard_regno_mode_ok): Likewise.
(arm_expand_epilogue_apcs_frame): Likewise.
(arm_expand_epilogue): Likewise.
(arm_file_start): Likewise.
(arm_conditional_register_usage): Likewise.
(arm_validize_comparison): Use vfp_compare_operand directly.
* arm-builtins.c (arm_init_builtins): Remove references to TARGET_VFP.
(arm_expand_vfp_builtin): Use TARGET_HARD_FLOAT for detecting
unsupported usage.
(arm_atomic_assign_expand_fenv): Likewise.
* arm.md (divsf3): Likewise.
(arm_negsi2): Likewise.
(absdf2): Likewise.
(arm_movdi): Likewise.
(arm_movt): Likewise.
(cbranchsf4): Change predicate to vfp_compare_operand.
(cbranchdf4): Change predicate to vfp_compare_operand.
(cstorehf4): Change predicate to vfp_compare_operand.
(cstoresf4): Change predicate to vfp_compare_operand.
(cstoredf4): Change predicate to vfp_compare_operand.
(vfp_pop_multiple_with_writeback): Remove references to TARGET_VFP.
(movhi_insn_arch4, movhi_bytes): Likewise.
* constraints.md (Dt): Likewise.
(Dp): Likewise.
* iterators.md (SDF): Likewise.
* predicates.md (arm_float_compare_operand): Delete.
(const_double_vcvt_power_of_two_reciprocal): Remove references to
TARGET_VFP.
(const_double_vcvt_power_of_two): Likewise.
* thumb2.md thumb2_movsi_insn): Likewise.
* vfp.md (arm_movhi_vfp, thumb2_movhi_vfp): Likewise.
(movhf_vfp): Likewise.
(arm_movsi_vfp, thumb2_movsi_vfp): Likewise.
(movdi_vfp, movdi_vfp_cortexa8): Likewise.
(movsf_vfp, thumb2_movsf_vfp): Likewise.
(movdf_vfp, thumb2_movdf_vfp): Likewise.
(movsfcc_vfp, abssf2_vfp, negsf2_vfp, addsf3_vfp): Likewise.
(subsf3_vfp, divsf3_vfp): Likewise.
(mulsf3_vfp, mulsf3negsf_vfp, negmulsf3_vfp): Likewise.
(mulsf3addsf_vfp, (mulsf3subsf_vfp, mulsf3negsfaddsf_vfp): Likewise.
(mulsf3negsfsubsf_vfp): Likewise.
(truncsisf2_vfp, fixuns_truncsfsi2, floatsisf2_vfp): Likewise.
(floatunssisf2, sqrtsf2_vfp): Likewise.
(movcc_vfp): Likewise.
(cmpsf_split_vfp, cmpsf_trap_split_vfp): Likewise.
(cmpsf_vfp, cmpsf_trap_vfp): Likewise.
(push_multi_vfp): Likewise.
(set_fpscr, get_fpscr): Likewise.
* arm-c.c (arm_cpu_builtins): Unconditionally define __VFP_FP__.
From-SVN: r241118
2016-10-13 15:04:51 +02:00
|
|
|
(define_mode_iterator SDF [(SF "") (DF "TARGET_VFP_DOUBLE")])
|
2012-07-05 11:07:00 +02:00
|
|
|
|
iterators.md: New file.
2010-08-09 Sofiane Naci <sofiane.naci@arm.com>
* config/arm/iterators.md: New file.
* config/arm/arm.md: Include iterators.md.
(QHSI): Move to new file.
(LTUGEU, cnb, optab, ior_xor): Likewise.
* config/arm/iwmmxt.md (VMMX): Move to new file.
(VSHFT, MMX_char): Likewise.
* config/arm/neon.md (VD): Move to new file.
(VDX, VDI, VQ, VQX, VQI, VQXMOV, VSTRUCT, VTAB, V_TAB_n, VW): Likewise.
(VN, VDQ, VDQW, VDQIW, VCVTF, VCVTI, VMD, VMQ, VMDQ, VMDI): Likewise.
(VMDQI, VX, VE, V64, V32, V_CVTTO, V_elem, V_ext, V_two_elem): Likewise.
(V_three_elem, V_four_elem, V_req, V_widen, V_narrow, V_HALF): Likewise.
(V_half,V_DOUBLE, V_double, V_double_width, V_cmp_result): Likewise.
(V_if_elem, V_s_elem, V_u_elem, V_uf_sclr, V_sz_elem, VD_dup): Likewise.
(V_PAIR, vqh_ops, vqhs_ops, VQH_mnem, VQH_sign, V_suf64): Likewise.
(scalar_mul_constraint,Is_float_mode, Scalar_mul_8_16): Likewise.
(Is_d_reg, V_mode_nunits): Likewise.
* config/arm/vec-common.md (VALL): Move to new file.
(VALLW, VINT, VINTW): Likewise.
From-SVN: r163058
2010-08-10 15:37:25 +02:00
|
|
|
;; Integer element sizes implemented by IWMMXT.
|
|
|
|
(define_mode_iterator VMMX [V2SI V4HI V8QI])
|
|
|
|
|
arm.c (FL_IWMMXT2): New define.
* config/arm/arm.c (FL_IWMMXT2): New define.
(arm_arch_iwmmxt2): New variable.
(arm_option_override): Enable use of iWMMXt with VFP.
Disable use of iWMMXt with NEON. Disable use of iWMMXt under
Thumb mode. Set arm_arch_iwmmxt2.
(arm_expand_binop_builtin): Accept VOIDmode op.
(enum arm_builtins): Revise built-in fcode.
(IWMMXT2_BUILTIN): New define.
(IWMMXT2_BUILTIN2): Likewise.
(iwmmx2_mbuiltin): Likewise.
(builtin_description bdesc_2arg): Revise built in declaration.
(builtin_description bdesc_1arg): Likewise.
(arm_init_iwmmxt_builtins): Revise built in initialization.
(arm_expand_builtin): Revise built in expansion.
(arm_output_iwmmxt_shift_immediate): New function.
(arm_output_iwmmxt_tinsr): Likewise.
* config/arm/arm-protos.h (arm_output_iwmmxt_shift_immediate): Declare.
(arm_output_iwmmxt_tinsr): Likewise.
* config/arm/iwmmxt.md (WCGR0, WCGR1, WCGR2, WCGR3): New constant.
(iwmmxt_psadbw, iwmmxt_walign, iwmmxt_tmrc, iwmmxt_tmcr): Delete.
(rorv4hi3, rorv2si3, rordi3): Likewise.
(rorv4hi3_di, rorv2si3_di, rordi3_di): Likewise.
(ashrv4hi3_di, ashrv2si3_di, ashrdi3_di): Likewise.
(lshrv4hi3_di, lshrv2si3_di, lshrdi3_di): Likewise.
(ashlv4hi3_di, ashlv2si3_di, ashldi3_di): Likewise.
(iwmmxt_tbcstqi, iwmmxt_tbcsthi, iwmmxt_tbcstsi): Likewise
(*iwmmxt_clrv8qi, *iwmmxt_clrv4hi, *iwmmxt_clrv2si): Likewise.
(tbcstv8qi, tbcstv4hi, tbsctv2si): New pattern.
(iwmmxt_clrv8qi, iwmmxt_clrv4hi, iwmmxt_clrv2si): Likewise.
(*and<mode>3_iwmmxt, *ior<mode>3_iwmmxt, *xor<mode>3_iwmmxt): Likewise.
(ror<mode>3, ror<mode>3_di): Likewise.
(ashr<mode>3_di, lshr<mode>3_di, ashl<mode>3_di): Likewise.
(ashli<mode>3_iwmmxt, iwmmxt_waligni, iwmmxt_walignr): Likewise.
(iwmmxt_walignr0, iwmmxt_walignr1): Likewise.
(iwmmxt_walignr2, iwmmxt_walignr3): Likewise.
(iwmmxt_setwcgr0, iwmmxt_setwcgr1): Likewise.
(iwmmxt_setwcgr2, iwmmxt_setwcgr3): Likewise.
(iwmmxt_getwcgr0, iwmmxt_getwcgr1): Likewise.
(iwmmxt_getwcgr2, iwmmxt_getwcgr3): Likewise.
(All instruction patterns): Add wtype attribute.
(*iwmmxt_arm_movdi, *iwmmxt_movsi_insn): iWMMXt coexist with vfp.
(iwmmxt_uavgrndv8qi3, iwmmxt_uavgrndv4hi3): Revise the pattern.
(iwmmxt_uavgv8qi3, iwmmxt_uavgv4hi3): Likewise.
(ashr<mode>3_iwmmxt, ashl<mode>3_iwmmxt, lshr<mode>3_iwmmxt): Likewise.
(iwmmxt_tinsrb, iwmmxt_tinsrh, iwmmxt_tinsrw):Likewise.
(eqv8qi3, eqv4hi3, eqv2si3, gtuv8qi3): Likewise.
(gtuv4hi3, gtuv2si3, gtv8qi3, gtv4hi3, gtv2si3): Likewise.
(iwmmxt_wunpckihh, iwmmxt_wunpckihw, iwmmxt_wunpckilh): Likewise.
(iwmmxt_wunpckilw, iwmmxt_wunpckehub, iwmmxt_wunpckehuh): Likewise.
(iwmmxt_wunpckehuw, iwmmxt_wunpckehsb, iwmmxt_wunpckehsh): Likewise.
(iwmmxt_wunpckehsw, iwmmxt_wunpckelub, iwmmxt_wunpckeluh): Likewise.
(iwmmxt_wunpckeluw, iwmmxt_wunpckelsb, iwmmxt_wunpckelsh): Likewise.
(iwmmxt_wunpckelsw, iwmmxt_wmadds, iwmmxt_wmaddu): Likewise.
(iwmmxt_wsadb, iwmmxt_wsadh, iwmmxt_wsadbz, iwmmxt_wsadhz): Likewise.
(iwmmxt2.md): Include.
* config/arm/arm.h (TARGET_CPU_CPP_BUILTINS): Define __IWMMXT2__.
(TARGET_IWMMXT2): New define.
(TARGET_REALLY_IWMMXT2): Likewise.
(arm_arch_iwmmxt2): Declare.
* config/arm/mmintrin.h: Use __IWMMXT__ to enable iWMMXt intrinsics.
Use __IWMMXT2__ to enable iWMMXt2 intrinsics.
Use C name-mangling for intrinsics.
(__v8qi): Redefine.
(_mm_cvtsi32_si64, _mm_andnot_si64, _mm_sad_pu8): Revise.
(_mm_sad_pu16, _mm_align_si64, _mm_setwcx, _mm_getwcx): Likewise.
(_m_from_int): Likewise.
(_mm_sada_pu8, _mm_sada_pu16): New intrinsic.
(_mm_alignr0_si64, _mm_alignr1_si64, _mm_alignr2_si64): Likewise.
(_mm_alignr3_si64, _mm_tandcb, _mm_tandch, _mm_tandcw): Likewise.
(_mm_textrcb, _mm_textrch, _mm_textrcw, _mm_torcb): Likewise.
(_mm_torch, _mm_torcw, _mm_tbcst_pi8, _mm_tbcst_pi16): Likewise.
(_mm_tbcst_pi32): Likewise.
(_mm_abs_pi8, _mm_abs_pi16, _mm_abs_pi32): New iWMMXt2 intrinsic.
(_mm_addsubhx_pi16, _mm_absdiff_pu8, _mm_absdiff_pu16): Likewise.
(_mm_absdiff_pu32, _mm_addc_pu16, _mm_addc_pu32): Likewise.
(_mm_avg4_pu8, _mm_avg4r_pu8, _mm_maddx_pi16, _mm_maddx_pu16): Likewise.
(_mm_msub_pi16, _mm_msub_pu16, _mm_mulhi_pi32): Likewise.
(_mm_mulhi_pu32, _mm_mulhir_pi16, _mm_mulhir_pi32): Likewise.
(_mm_mulhir_pu16, _mm_mulhir_pu32, _mm_mullo_pi32): Likewise.
(_mm_qmulm_pi16, _mm_qmulm_pi32, _mm_qmulmr_pi16): Likewise.
(_mm_qmulmr_pi32, _mm_subaddhx_pi16, _mm_addbhusl_pu8): Likewise.
(_mm_addbhusm_pu8, _mm_qmiabb_pi32, _mm_qmiabbn_pi32): Likewise.
(_mm_qmiabt_pi32, _mm_qmiabtn_pi32, _mm_qmiatb_pi32): Likewise.
(_mm_qmiatbn_pi32, _mm_qmiatt_pi32, _mm_qmiattn_pi32): Likewise.
(_mm_wmiabb_si64, _mm_wmiabbn_si64, _mm_wmiabt_si64): Likewise.
(_mm_wmiabtn_si64, _mm_wmiatb_si64, _mm_wmiatbn_si64): Likewise.
(_mm_wmiatt_si64, _mm_wmiattn_si64, _mm_wmiawbb_si64): Likewise.
(_mm_wmiawbbn_si64, _mm_wmiawbt_si64, _mm_wmiawbtn_si64): Likewise.
(_mm_wmiawtb_si64, _mm_wmiawtbn_si64, _mm_wmiawtt_si64): Likewise.
(_mm_wmiawttn_si64, _mm_merge_si64): Likewise.
(_mm_torvscb, _mm_torvsch, _mm_torvscw): Likewise.
(_m_to_int): New define.
* config/arm/arm-cores.def (iwmmxt2): Add FL_IWMMXT2.
* config/arm/arm-arches.def (iwmmxt2): Likewise.
* config/arm/t-arm (MD_INCLUDES): Add marvell-f-iwmmxt.md and
iwmmxt2.md.
* config/arm/arm.md (marvell-f-iwmmxt.md): Include.
(arch): Add "iwmmxt2".
(arch_enabled): Handle "iwmmxt2".
(wtype): New attribute.
(UNSPEC_WMADDS, UNSPEC_WMADDU): Delete.
(UNSPEC_WALIGNI): New unspec.
* config/arm/predicates.md (imm_or_reg_operand): New predicate.
* config/arm/iterators.md (VMMX2): New mode_iterator.
* config/arm/marvell-f-iwmmxt.md: New file.
* config/arm/iwmmxt2.md: New file.
From-SVN: r188497
2012-06-13 09:28:51 +02:00
|
|
|
(define_mode_iterator VMMX2 [V4HI V2SI])
|
|
|
|
|
iterators.md: New file.
2010-08-09 Sofiane Naci <sofiane.naci@arm.com>
* config/arm/iterators.md: New file.
* config/arm/arm.md: Include iterators.md.
(QHSI): Move to new file.
(LTUGEU, cnb, optab, ior_xor): Likewise.
* config/arm/iwmmxt.md (VMMX): Move to new file.
(VSHFT, MMX_char): Likewise.
* config/arm/neon.md (VD): Move to new file.
(VDX, VDI, VQ, VQX, VQI, VQXMOV, VSTRUCT, VTAB, V_TAB_n, VW): Likewise.
(VN, VDQ, VDQW, VDQIW, VCVTF, VCVTI, VMD, VMQ, VMDQ, VMDI): Likewise.
(VMDQI, VX, VE, V64, V32, V_CVTTO, V_elem, V_ext, V_two_elem): Likewise.
(V_three_elem, V_four_elem, V_req, V_widen, V_narrow, V_HALF): Likewise.
(V_half,V_DOUBLE, V_double, V_double_width, V_cmp_result): Likewise.
(V_if_elem, V_s_elem, V_u_elem, V_uf_sclr, V_sz_elem, VD_dup): Likewise.
(V_PAIR, vqh_ops, vqhs_ops, VQH_mnem, VQH_sign, V_suf64): Likewise.
(scalar_mul_constraint,Is_float_mode, Scalar_mul_8_16): Likewise.
(Is_d_reg, V_mode_nunits): Likewise.
* config/arm/vec-common.md (VALL): Move to new file.
(VALLW, VINT, VINTW): Likewise.
From-SVN: r163058
2010-08-10 15:37:25 +02:00
|
|
|
;; Integer element sizes for shifts.
|
|
|
|
(define_mode_iterator VSHFT [V4HI V2SI DI])
|
|
|
|
|
|
|
|
;; Integer and float modes supported by Neon and IWMMXT.
|
|
|
|
(define_mode_iterator VALL [V2DI V2SI V4HI V8QI V2SF V4SI V8HI V16QI V4SF])
|
|
|
|
|
|
|
|
;; Integer and float modes supported by Neon and IWMMXT, except V2DI.
|
|
|
|
(define_mode_iterator VALLW [V2SI V4HI V8QI V2SF V4SI V8HI V16QI V4SF])
|
|
|
|
|
|
|
|
;; Integer modes supported by Neon and IWMMXT
|
|
|
|
(define_mode_iterator VINT [V2DI V2SI V4HI V8QI V4SI V8HI V16QI])
|
|
|
|
|
|
|
|
;; Integer modes supported by Neon and IWMMXT, except V2DI
|
|
|
|
(define_mode_iterator VINTW [V2SI V4HI V8QI V4SI V8HI V16QI])
|
|
|
|
|
[ARM] Remaining intrinsics
* config/arm/arm-builtins.c (VAR11, VAR12): New.
* config/arm/arm_neon_builtins.def (vcombine, vld2_dup, vld3_dup,
vld4_dup): Add v4hf variant.
(vget_high, vget_low): Add v8hf variant.
(vld1, vst1, vst1_lane, vld2, vld2_lane, vst2, vst2_lane, vld3,
vld3_lane, vst3, vst3_lane, vld4, vld4_lane, vst4, vst4_lane): Add
v4hf and v8hf variants.
* config/arm/iterators.md (VD_LANE, VD_RE, VQ2, VQ_HS): New.
(VDX): Add V4HF.
(V_DOUBLE): Add case for V4HF.
(VQX): Add V8HF.
(V_HALF): Add case for V8HF.
(VDQX): Add V4HF, V8HF.
(V_elem, V_two_elem, V_three_elem, V_four_elem, V_cmp_result,
V_uf_sclr, V_sz_elem, V_mode_nunits, q): Add cases for V4HF & V8HF.
* config/arm/neon.md (vec_set<mode>internal, vec_extract<mode>,
neon_vget_lane<mode>_sext_internal, neon_vget_lane<mode>_zext_internal,
vec_load_lanesoi<mode>, neon_vld2<mode>, vec_store_lanesoi<mode>,
neon_vst2<mode>, vec_load_lanesci<mode>, neon_vld3<mode>,
neon_vld3qa<mode>, neon_vld3qb<mode>, vec_store_lanesci<mode>,
neon_vst3<mode>, neon_vst3qa<mode>, neon_vst3qb<mode>,
vec_load_lanesxi<mode>, neon_vld4<mode>, neon_vld4qa<mode>,
neon_vld4qb<mode>, vec_store_lanesxi<mode>, neon_vst4<mode>,
neon_vst4qa<mode>, neon_vst4qb<mode>): Change VQ iterator to VQ2.
(neon_vcreate, neon_vreinterpretv8qi<mode>,
neon_vreinterpretv4hi<mode>, neon_vreinterpretv2si<mode>,
neon_vreinterpretv2sf<mode>, neon_vreinterpretdi<mode>):
Change VDX to VD_RE.
(neon_vld2_lane<mode>, neon_vst2_lane<mode>, neon_vld3_lane<mode>,
neon_vst3_lane<mode>, neon_vld4_lane<mode>, neon_vst4_lane<mode>):
Change VD iterator to VD_LANE, and VMQ iterator to VQ_HS.
* config/arm/arm_neon.h (float16x4x2_t, float16x8x2_t, float16x4x3_t,
float16x8x3_t, float16x4x4_t, float16x8x4_t, vcombine_f16,
vget_high_f16, vget_low_f16, vld1_f16, vld1q_f16, vst1_f16, vst1q_f16,
vst1_lane_f16, vst1q_lane_f16, vld2_f16, vld2q_f16, vld2_lane_f16,
vld2q_lane_f16, vld2_dup_f16, vst2_f16, vst2q_f16, vst2_lane_f16,
vst2q_lane_f16, vld3_f16, vld3q_f16, vld3_lane_f16, vld3q_lane_f16,
vld3_dup_f16, vst3_f16, vst3q_f16, vst3_lane_f16, vst3q_lane_f16,
vld4_f16, vld4q_f16, vld4_lane_f16, vld4q_lane_f16, vld4_dup_f16,
vst4_f16, vst4q_f16, vst4_lane_f16, vst4q_lane_f16): New.
From-SVN: r227541
2015-09-08 20:48:47 +02:00
|
|
|
;; Double-width vector modes, on which we support arithmetic (no HF!)
|
iterators.md: New file.
2010-08-09 Sofiane Naci <sofiane.naci@arm.com>
* config/arm/iterators.md: New file.
* config/arm/arm.md: Include iterators.md.
(QHSI): Move to new file.
(LTUGEU, cnb, optab, ior_xor): Likewise.
* config/arm/iwmmxt.md (VMMX): Move to new file.
(VSHFT, MMX_char): Likewise.
* config/arm/neon.md (VD): Move to new file.
(VDX, VDI, VQ, VQX, VQI, VQXMOV, VSTRUCT, VTAB, V_TAB_n, VW): Likewise.
(VN, VDQ, VDQW, VDQIW, VCVTF, VCVTI, VMD, VMQ, VMDQ, VMDI): Likewise.
(VMDQI, VX, VE, V64, V32, V_CVTTO, V_elem, V_ext, V_two_elem): Likewise.
(V_three_elem, V_four_elem, V_req, V_widen, V_narrow, V_HALF): Likewise.
(V_half,V_DOUBLE, V_double, V_double_width, V_cmp_result): Likewise.
(V_if_elem, V_s_elem, V_u_elem, V_uf_sclr, V_sz_elem, VD_dup): Likewise.
(V_PAIR, vqh_ops, vqhs_ops, VQH_mnem, VQH_sign, V_suf64): Likewise.
(scalar_mul_constraint,Is_float_mode, Scalar_mul_8_16): Likewise.
(Is_d_reg, V_mode_nunits): Likewise.
* config/arm/vec-common.md (VALL): Move to new file.
(VALLW, VINT, VINTW): Likewise.
From-SVN: r163058
2010-08-10 15:37:25 +02:00
|
|
|
(define_mode_iterator VD [V8QI V4HI V2SI V2SF])
|
|
|
|
|
[ARM] Remaining intrinsics
* config/arm/arm-builtins.c (VAR11, VAR12): New.
* config/arm/arm_neon_builtins.def (vcombine, vld2_dup, vld3_dup,
vld4_dup): Add v4hf variant.
(vget_high, vget_low): Add v8hf variant.
(vld1, vst1, vst1_lane, vld2, vld2_lane, vst2, vst2_lane, vld3,
vld3_lane, vst3, vst3_lane, vld4, vld4_lane, vst4, vst4_lane): Add
v4hf and v8hf variants.
* config/arm/iterators.md (VD_LANE, VD_RE, VQ2, VQ_HS): New.
(VDX): Add V4HF.
(V_DOUBLE): Add case for V4HF.
(VQX): Add V8HF.
(V_HALF): Add case for V8HF.
(VDQX): Add V4HF, V8HF.
(V_elem, V_two_elem, V_three_elem, V_four_elem, V_cmp_result,
V_uf_sclr, V_sz_elem, V_mode_nunits, q): Add cases for V4HF & V8HF.
* config/arm/neon.md (vec_set<mode>internal, vec_extract<mode>,
neon_vget_lane<mode>_sext_internal, neon_vget_lane<mode>_zext_internal,
vec_load_lanesoi<mode>, neon_vld2<mode>, vec_store_lanesoi<mode>,
neon_vst2<mode>, vec_load_lanesci<mode>, neon_vld3<mode>,
neon_vld3qa<mode>, neon_vld3qb<mode>, vec_store_lanesci<mode>,
neon_vst3<mode>, neon_vst3qa<mode>, neon_vst3qb<mode>,
vec_load_lanesxi<mode>, neon_vld4<mode>, neon_vld4qa<mode>,
neon_vld4qb<mode>, vec_store_lanesxi<mode>, neon_vst4<mode>,
neon_vst4qa<mode>, neon_vst4qb<mode>): Change VQ iterator to VQ2.
(neon_vcreate, neon_vreinterpretv8qi<mode>,
neon_vreinterpretv4hi<mode>, neon_vreinterpretv2si<mode>,
neon_vreinterpretv2sf<mode>, neon_vreinterpretdi<mode>):
Change VDX to VD_RE.
(neon_vld2_lane<mode>, neon_vst2_lane<mode>, neon_vld3_lane<mode>,
neon_vst3_lane<mode>, neon_vld4_lane<mode>, neon_vst4_lane<mode>):
Change VD iterator to VD_LANE, and VMQ iterator to VQ_HS.
* config/arm/arm_neon.h (float16x4x2_t, float16x8x2_t, float16x4x3_t,
float16x8x3_t, float16x4x4_t, float16x8x4_t, vcombine_f16,
vget_high_f16, vget_low_f16, vld1_f16, vld1q_f16, vst1_f16, vst1q_f16,
vst1_lane_f16, vst1q_lane_f16, vld2_f16, vld2q_f16, vld2_lane_f16,
vld2q_lane_f16, vld2_dup_f16, vst2_f16, vst2q_f16, vst2_lane_f16,
vst2q_lane_f16, vld3_f16, vld3q_f16, vld3_lane_f16, vld3q_lane_f16,
vld3_dup_f16, vst3_f16, vst3q_f16, vst3_lane_f16, vst3q_lane_f16,
vld4_f16, vld4q_f16, vld4_lane_f16, vld4q_lane_f16, vld4_dup_f16,
vst4_f16, vst4q_f16, vst4_lane_f16, vst4q_lane_f16): New.
From-SVN: r227541
2015-09-08 20:48:47 +02:00
|
|
|
;; Double-width vector modes plus 64-bit elements for vreinterpret + vcreate.
|
|
|
|
(define_mode_iterator VD_RE [V8QI V4HI V2SI V2SF DI])
|
|
|
|
|
iterators.md: New file.
2010-08-09 Sofiane Naci <sofiane.naci@arm.com>
* config/arm/iterators.md: New file.
* config/arm/arm.md: Include iterators.md.
(QHSI): Move to new file.
(LTUGEU, cnb, optab, ior_xor): Likewise.
* config/arm/iwmmxt.md (VMMX): Move to new file.
(VSHFT, MMX_char): Likewise.
* config/arm/neon.md (VD): Move to new file.
(VDX, VDI, VQ, VQX, VQI, VQXMOV, VSTRUCT, VTAB, V_TAB_n, VW): Likewise.
(VN, VDQ, VDQW, VDQIW, VCVTF, VCVTI, VMD, VMQ, VMDQ, VMDI): Likewise.
(VMDQI, VX, VE, V64, V32, V_CVTTO, V_elem, V_ext, V_two_elem): Likewise.
(V_three_elem, V_four_elem, V_req, V_widen, V_narrow, V_HALF): Likewise.
(V_half,V_DOUBLE, V_double, V_double_width, V_cmp_result): Likewise.
(V_if_elem, V_s_elem, V_u_elem, V_uf_sclr, V_sz_elem, VD_dup): Likewise.
(V_PAIR, vqh_ops, vqhs_ops, VQH_mnem, VQH_sign, V_suf64): Likewise.
(scalar_mul_constraint,Is_float_mode, Scalar_mul_8_16): Likewise.
(Is_d_reg, V_mode_nunits): Likewise.
* config/arm/vec-common.md (VALL): Move to new file.
(VALLW, VINT, VINTW): Likewise.
From-SVN: r163058
2010-08-10 15:37:25 +02:00
|
|
|
;; Double-width vector modes plus 64-bit elements.
|
[ARM] Remaining intrinsics
* config/arm/arm-builtins.c (VAR11, VAR12): New.
* config/arm/arm_neon_builtins.def (vcombine, vld2_dup, vld3_dup,
vld4_dup): Add v4hf variant.
(vget_high, vget_low): Add v8hf variant.
(vld1, vst1, vst1_lane, vld2, vld2_lane, vst2, vst2_lane, vld3,
vld3_lane, vst3, vst3_lane, vld4, vld4_lane, vst4, vst4_lane): Add
v4hf and v8hf variants.
* config/arm/iterators.md (VD_LANE, VD_RE, VQ2, VQ_HS): New.
(VDX): Add V4HF.
(V_DOUBLE): Add case for V4HF.
(VQX): Add V8HF.
(V_HALF): Add case for V8HF.
(VDQX): Add V4HF, V8HF.
(V_elem, V_two_elem, V_three_elem, V_four_elem, V_cmp_result,
V_uf_sclr, V_sz_elem, V_mode_nunits, q): Add cases for V4HF & V8HF.
* config/arm/neon.md (vec_set<mode>internal, vec_extract<mode>,
neon_vget_lane<mode>_sext_internal, neon_vget_lane<mode>_zext_internal,
vec_load_lanesoi<mode>, neon_vld2<mode>, vec_store_lanesoi<mode>,
neon_vst2<mode>, vec_load_lanesci<mode>, neon_vld3<mode>,
neon_vld3qa<mode>, neon_vld3qb<mode>, vec_store_lanesci<mode>,
neon_vst3<mode>, neon_vst3qa<mode>, neon_vst3qb<mode>,
vec_load_lanesxi<mode>, neon_vld4<mode>, neon_vld4qa<mode>,
neon_vld4qb<mode>, vec_store_lanesxi<mode>, neon_vst4<mode>,
neon_vst4qa<mode>, neon_vst4qb<mode>): Change VQ iterator to VQ2.
(neon_vcreate, neon_vreinterpretv8qi<mode>,
neon_vreinterpretv4hi<mode>, neon_vreinterpretv2si<mode>,
neon_vreinterpretv2sf<mode>, neon_vreinterpretdi<mode>):
Change VDX to VD_RE.
(neon_vld2_lane<mode>, neon_vst2_lane<mode>, neon_vld3_lane<mode>,
neon_vst3_lane<mode>, neon_vld4_lane<mode>, neon_vst4_lane<mode>):
Change VD iterator to VD_LANE, and VMQ iterator to VQ_HS.
* config/arm/arm_neon.h (float16x4x2_t, float16x8x2_t, float16x4x3_t,
float16x8x3_t, float16x4x4_t, float16x8x4_t, vcombine_f16,
vget_high_f16, vget_low_f16, vld1_f16, vld1q_f16, vst1_f16, vst1q_f16,
vst1_lane_f16, vst1q_lane_f16, vld2_f16, vld2q_f16, vld2_lane_f16,
vld2q_lane_f16, vld2_dup_f16, vst2_f16, vst2q_f16, vst2_lane_f16,
vst2q_lane_f16, vld3_f16, vld3q_f16, vld3_lane_f16, vld3q_lane_f16,
vld3_dup_f16, vst3_f16, vst3q_f16, vst3_lane_f16, vst3q_lane_f16,
vld4_f16, vld4q_f16, vld4_lane_f16, vld4q_lane_f16, vld4_dup_f16,
vst4_f16, vst4q_f16, vst4_lane_f16, vst4q_lane_f16): New.
From-SVN: r227541
2015-09-08 20:48:47 +02:00
|
|
|
(define_mode_iterator VDX [V8QI V4HI V4HF V2SI V2SF DI])
|
|
|
|
|
|
|
|
;; Double-width vector modes, with V4HF - for vldN_lane and vstN_lane.
|
|
|
|
(define_mode_iterator VD_LANE [V8QI V4HI V4HF V2SI V2SF])
|
iterators.md: New file.
2010-08-09 Sofiane Naci <sofiane.naci@arm.com>
* config/arm/iterators.md: New file.
* config/arm/arm.md: Include iterators.md.
(QHSI): Move to new file.
(LTUGEU, cnb, optab, ior_xor): Likewise.
* config/arm/iwmmxt.md (VMMX): Move to new file.
(VSHFT, MMX_char): Likewise.
* config/arm/neon.md (VD): Move to new file.
(VDX, VDI, VQ, VQX, VQI, VQXMOV, VSTRUCT, VTAB, V_TAB_n, VW): Likewise.
(VN, VDQ, VDQW, VDQIW, VCVTF, VCVTI, VMD, VMQ, VMDQ, VMDI): Likewise.
(VMDQI, VX, VE, V64, V32, V_CVTTO, V_elem, V_ext, V_two_elem): Likewise.
(V_three_elem, V_four_elem, V_req, V_widen, V_narrow, V_HALF): Likewise.
(V_half,V_DOUBLE, V_double, V_double_width, V_cmp_result): Likewise.
(V_if_elem, V_s_elem, V_u_elem, V_uf_sclr, V_sz_elem, VD_dup): Likewise.
(V_PAIR, vqh_ops, vqhs_ops, VQH_mnem, VQH_sign, V_suf64): Likewise.
(scalar_mul_constraint,Is_float_mode, Scalar_mul_8_16): Likewise.
(Is_d_reg, V_mode_nunits): Likewise.
* config/arm/vec-common.md (VALL): Move to new file.
(VALLW, VINT, VINTW): Likewise.
From-SVN: r163058
2010-08-10 15:37:25 +02:00
|
|
|
|
|
|
|
;; Double-width vector modes without floating-point elements.
|
|
|
|
(define_mode_iterator VDI [V8QI V4HI V2SI])
|
|
|
|
|
[ARM] Remaining intrinsics
* config/arm/arm-builtins.c (VAR11, VAR12): New.
* config/arm/arm_neon_builtins.def (vcombine, vld2_dup, vld3_dup,
vld4_dup): Add v4hf variant.
(vget_high, vget_low): Add v8hf variant.
(vld1, vst1, vst1_lane, vld2, vld2_lane, vst2, vst2_lane, vld3,
vld3_lane, vst3, vst3_lane, vld4, vld4_lane, vst4, vst4_lane): Add
v4hf and v8hf variants.
* config/arm/iterators.md (VD_LANE, VD_RE, VQ2, VQ_HS): New.
(VDX): Add V4HF.
(V_DOUBLE): Add case for V4HF.
(VQX): Add V8HF.
(V_HALF): Add case for V8HF.
(VDQX): Add V4HF, V8HF.
(V_elem, V_two_elem, V_three_elem, V_four_elem, V_cmp_result,
V_uf_sclr, V_sz_elem, V_mode_nunits, q): Add cases for V4HF & V8HF.
* config/arm/neon.md (vec_set<mode>internal, vec_extract<mode>,
neon_vget_lane<mode>_sext_internal, neon_vget_lane<mode>_zext_internal,
vec_load_lanesoi<mode>, neon_vld2<mode>, vec_store_lanesoi<mode>,
neon_vst2<mode>, vec_load_lanesci<mode>, neon_vld3<mode>,
neon_vld3qa<mode>, neon_vld3qb<mode>, vec_store_lanesci<mode>,
neon_vst3<mode>, neon_vst3qa<mode>, neon_vst3qb<mode>,
vec_load_lanesxi<mode>, neon_vld4<mode>, neon_vld4qa<mode>,
neon_vld4qb<mode>, vec_store_lanesxi<mode>, neon_vst4<mode>,
neon_vst4qa<mode>, neon_vst4qb<mode>): Change VQ iterator to VQ2.
(neon_vcreate, neon_vreinterpretv8qi<mode>,
neon_vreinterpretv4hi<mode>, neon_vreinterpretv2si<mode>,
neon_vreinterpretv2sf<mode>, neon_vreinterpretdi<mode>):
Change VDX to VD_RE.
(neon_vld2_lane<mode>, neon_vst2_lane<mode>, neon_vld3_lane<mode>,
neon_vst3_lane<mode>, neon_vld4_lane<mode>, neon_vst4_lane<mode>):
Change VD iterator to VD_LANE, and VMQ iterator to VQ_HS.
* config/arm/arm_neon.h (float16x4x2_t, float16x8x2_t, float16x4x3_t,
float16x8x3_t, float16x4x4_t, float16x8x4_t, vcombine_f16,
vget_high_f16, vget_low_f16, vld1_f16, vld1q_f16, vst1_f16, vst1q_f16,
vst1_lane_f16, vst1q_lane_f16, vld2_f16, vld2q_f16, vld2_lane_f16,
vld2q_lane_f16, vld2_dup_f16, vst2_f16, vst2q_f16, vst2_lane_f16,
vst2q_lane_f16, vld3_f16, vld3q_f16, vld3_lane_f16, vld3q_lane_f16,
vld3_dup_f16, vst3_f16, vst3q_f16, vst3_lane_f16, vst3q_lane_f16,
vld4_f16, vld4q_f16, vld4_lane_f16, vld4q_lane_f16, vld4_dup_f16,
vst4_f16, vst4q_f16, vst4_lane_f16, vst4q_lane_f16): New.
From-SVN: r227541
2015-09-08 20:48:47 +02:00
|
|
|
;; Quad-width vector modes supporting arithmetic (no HF!).
|
iterators.md: New file.
2010-08-09 Sofiane Naci <sofiane.naci@arm.com>
* config/arm/iterators.md: New file.
* config/arm/arm.md: Include iterators.md.
(QHSI): Move to new file.
(LTUGEU, cnb, optab, ior_xor): Likewise.
* config/arm/iwmmxt.md (VMMX): Move to new file.
(VSHFT, MMX_char): Likewise.
* config/arm/neon.md (VD): Move to new file.
(VDX, VDI, VQ, VQX, VQI, VQXMOV, VSTRUCT, VTAB, V_TAB_n, VW): Likewise.
(VN, VDQ, VDQW, VDQIW, VCVTF, VCVTI, VMD, VMQ, VMDQ, VMDI): Likewise.
(VMDQI, VX, VE, V64, V32, V_CVTTO, V_elem, V_ext, V_two_elem): Likewise.
(V_three_elem, V_four_elem, V_req, V_widen, V_narrow, V_HALF): Likewise.
(V_half,V_DOUBLE, V_double, V_double_width, V_cmp_result): Likewise.
(V_if_elem, V_s_elem, V_u_elem, V_uf_sclr, V_sz_elem, VD_dup): Likewise.
(V_PAIR, vqh_ops, vqhs_ops, VQH_mnem, VQH_sign, V_suf64): Likewise.
(scalar_mul_constraint,Is_float_mode, Scalar_mul_8_16): Likewise.
(Is_d_reg, V_mode_nunits): Likewise.
* config/arm/vec-common.md (VALL): Move to new file.
(VALLW, VINT, VINTW): Likewise.
From-SVN: r163058
2010-08-10 15:37:25 +02:00
|
|
|
(define_mode_iterator VQ [V16QI V8HI V4SI V4SF])
|
|
|
|
|
[ARM] Remaining intrinsics
* config/arm/arm-builtins.c (VAR11, VAR12): New.
* config/arm/arm_neon_builtins.def (vcombine, vld2_dup, vld3_dup,
vld4_dup): Add v4hf variant.
(vget_high, vget_low): Add v8hf variant.
(vld1, vst1, vst1_lane, vld2, vld2_lane, vst2, vst2_lane, vld3,
vld3_lane, vst3, vst3_lane, vld4, vld4_lane, vst4, vst4_lane): Add
v4hf and v8hf variants.
* config/arm/iterators.md (VD_LANE, VD_RE, VQ2, VQ_HS): New.
(VDX): Add V4HF.
(V_DOUBLE): Add case for V4HF.
(VQX): Add V8HF.
(V_HALF): Add case for V8HF.
(VDQX): Add V4HF, V8HF.
(V_elem, V_two_elem, V_three_elem, V_four_elem, V_cmp_result,
V_uf_sclr, V_sz_elem, V_mode_nunits, q): Add cases for V4HF & V8HF.
* config/arm/neon.md (vec_set<mode>internal, vec_extract<mode>,
neon_vget_lane<mode>_sext_internal, neon_vget_lane<mode>_zext_internal,
vec_load_lanesoi<mode>, neon_vld2<mode>, vec_store_lanesoi<mode>,
neon_vst2<mode>, vec_load_lanesci<mode>, neon_vld3<mode>,
neon_vld3qa<mode>, neon_vld3qb<mode>, vec_store_lanesci<mode>,
neon_vst3<mode>, neon_vst3qa<mode>, neon_vst3qb<mode>,
vec_load_lanesxi<mode>, neon_vld4<mode>, neon_vld4qa<mode>,
neon_vld4qb<mode>, vec_store_lanesxi<mode>, neon_vst4<mode>,
neon_vst4qa<mode>, neon_vst4qb<mode>): Change VQ iterator to VQ2.
(neon_vcreate, neon_vreinterpretv8qi<mode>,
neon_vreinterpretv4hi<mode>, neon_vreinterpretv2si<mode>,
neon_vreinterpretv2sf<mode>, neon_vreinterpretdi<mode>):
Change VDX to VD_RE.
(neon_vld2_lane<mode>, neon_vst2_lane<mode>, neon_vld3_lane<mode>,
neon_vst3_lane<mode>, neon_vld4_lane<mode>, neon_vst4_lane<mode>):
Change VD iterator to VD_LANE, and VMQ iterator to VQ_HS.
* config/arm/arm_neon.h (float16x4x2_t, float16x8x2_t, float16x4x3_t,
float16x8x3_t, float16x4x4_t, float16x8x4_t, vcombine_f16,
vget_high_f16, vget_low_f16, vld1_f16, vld1q_f16, vst1_f16, vst1q_f16,
vst1_lane_f16, vst1q_lane_f16, vld2_f16, vld2q_f16, vld2_lane_f16,
vld2q_lane_f16, vld2_dup_f16, vst2_f16, vst2q_f16, vst2_lane_f16,
vst2q_lane_f16, vld3_f16, vld3q_f16, vld3_lane_f16, vld3q_lane_f16,
vld3_dup_f16, vst3_f16, vst3q_f16, vst3_lane_f16, vst3q_lane_f16,
vld4_f16, vld4q_f16, vld4_lane_f16, vld4q_lane_f16, vld4_dup_f16,
vst4_f16, vst4q_f16, vst4_lane_f16, vst4q_lane_f16): New.
From-SVN: r227541
2015-09-08 20:48:47 +02:00
|
|
|
;; Quad-width vector modes, including V8HF.
|
|
|
|
(define_mode_iterator VQ2 [V16QI V8HI V8HF V4SI V4SF])
|
|
|
|
|
|
|
|
;; Quad-width vector modes with 16- or 32-bit elements
|
|
|
|
(define_mode_iterator VQ_HS [V8HI V8HF V4SI V4SF])
|
|
|
|
|
iterators.md: New file.
2010-08-09 Sofiane Naci <sofiane.naci@arm.com>
* config/arm/iterators.md: New file.
* config/arm/arm.md: Include iterators.md.
(QHSI): Move to new file.
(LTUGEU, cnb, optab, ior_xor): Likewise.
* config/arm/iwmmxt.md (VMMX): Move to new file.
(VSHFT, MMX_char): Likewise.
* config/arm/neon.md (VD): Move to new file.
(VDX, VDI, VQ, VQX, VQI, VQXMOV, VSTRUCT, VTAB, V_TAB_n, VW): Likewise.
(VN, VDQ, VDQW, VDQIW, VCVTF, VCVTI, VMD, VMQ, VMDQ, VMDI): Likewise.
(VMDQI, VX, VE, V64, V32, V_CVTTO, V_elem, V_ext, V_two_elem): Likewise.
(V_three_elem, V_four_elem, V_req, V_widen, V_narrow, V_HALF): Likewise.
(V_half,V_DOUBLE, V_double, V_double_width, V_cmp_result): Likewise.
(V_if_elem, V_s_elem, V_u_elem, V_uf_sclr, V_sz_elem, VD_dup): Likewise.
(V_PAIR, vqh_ops, vqhs_ops, VQH_mnem, VQH_sign, V_suf64): Likewise.
(scalar_mul_constraint,Is_float_mode, Scalar_mul_8_16): Likewise.
(Is_d_reg, V_mode_nunits): Likewise.
* config/arm/vec-common.md (VALL): Move to new file.
(VALLW, VINT, VINTW): Likewise.
From-SVN: r163058
2010-08-10 15:37:25 +02:00
|
|
|
;; Quad-width vector modes plus 64-bit elements.
|
[ARM] Remaining intrinsics
* config/arm/arm-builtins.c (VAR11, VAR12): New.
* config/arm/arm_neon_builtins.def (vcombine, vld2_dup, vld3_dup,
vld4_dup): Add v4hf variant.
(vget_high, vget_low): Add v8hf variant.
(vld1, vst1, vst1_lane, vld2, vld2_lane, vst2, vst2_lane, vld3,
vld3_lane, vst3, vst3_lane, vld4, vld4_lane, vst4, vst4_lane): Add
v4hf and v8hf variants.
* config/arm/iterators.md (VD_LANE, VD_RE, VQ2, VQ_HS): New.
(VDX): Add V4HF.
(V_DOUBLE): Add case for V4HF.
(VQX): Add V8HF.
(V_HALF): Add case for V8HF.
(VDQX): Add V4HF, V8HF.
(V_elem, V_two_elem, V_three_elem, V_four_elem, V_cmp_result,
V_uf_sclr, V_sz_elem, V_mode_nunits, q): Add cases for V4HF & V8HF.
* config/arm/neon.md (vec_set<mode>internal, vec_extract<mode>,
neon_vget_lane<mode>_sext_internal, neon_vget_lane<mode>_zext_internal,
vec_load_lanesoi<mode>, neon_vld2<mode>, vec_store_lanesoi<mode>,
neon_vst2<mode>, vec_load_lanesci<mode>, neon_vld3<mode>,
neon_vld3qa<mode>, neon_vld3qb<mode>, vec_store_lanesci<mode>,
neon_vst3<mode>, neon_vst3qa<mode>, neon_vst3qb<mode>,
vec_load_lanesxi<mode>, neon_vld4<mode>, neon_vld4qa<mode>,
neon_vld4qb<mode>, vec_store_lanesxi<mode>, neon_vst4<mode>,
neon_vst4qa<mode>, neon_vst4qb<mode>): Change VQ iterator to VQ2.
(neon_vcreate, neon_vreinterpretv8qi<mode>,
neon_vreinterpretv4hi<mode>, neon_vreinterpretv2si<mode>,
neon_vreinterpretv2sf<mode>, neon_vreinterpretdi<mode>):
Change VDX to VD_RE.
(neon_vld2_lane<mode>, neon_vst2_lane<mode>, neon_vld3_lane<mode>,
neon_vst3_lane<mode>, neon_vld4_lane<mode>, neon_vst4_lane<mode>):
Change VD iterator to VD_LANE, and VMQ iterator to VQ_HS.
* config/arm/arm_neon.h (float16x4x2_t, float16x8x2_t, float16x4x3_t,
float16x8x3_t, float16x4x4_t, float16x8x4_t, vcombine_f16,
vget_high_f16, vget_low_f16, vld1_f16, vld1q_f16, vst1_f16, vst1q_f16,
vst1_lane_f16, vst1q_lane_f16, vld2_f16, vld2q_f16, vld2_lane_f16,
vld2q_lane_f16, vld2_dup_f16, vst2_f16, vst2q_f16, vst2_lane_f16,
vst2q_lane_f16, vld3_f16, vld3q_f16, vld3_lane_f16, vld3q_lane_f16,
vld3_dup_f16, vst3_f16, vst3q_f16, vst3_lane_f16, vst3q_lane_f16,
vld4_f16, vld4q_f16, vld4_lane_f16, vld4q_lane_f16, vld4_dup_f16,
vst4_f16, vst4q_f16, vst4_lane_f16, vst4q_lane_f16): New.
From-SVN: r227541
2015-09-08 20:48:47 +02:00
|
|
|
(define_mode_iterator VQX [V16QI V8HI V8HF V4SI V4SF V2DI])
|
iterators.md: New file.
2010-08-09 Sofiane Naci <sofiane.naci@arm.com>
* config/arm/iterators.md: New file.
* config/arm/arm.md: Include iterators.md.
(QHSI): Move to new file.
(LTUGEU, cnb, optab, ior_xor): Likewise.
* config/arm/iwmmxt.md (VMMX): Move to new file.
(VSHFT, MMX_char): Likewise.
* config/arm/neon.md (VD): Move to new file.
(VDX, VDI, VQ, VQX, VQI, VQXMOV, VSTRUCT, VTAB, V_TAB_n, VW): Likewise.
(VN, VDQ, VDQW, VDQIW, VCVTF, VCVTI, VMD, VMQ, VMDQ, VMDI): Likewise.
(VMDQI, VX, VE, V64, V32, V_CVTTO, V_elem, V_ext, V_two_elem): Likewise.
(V_three_elem, V_four_elem, V_req, V_widen, V_narrow, V_HALF): Likewise.
(V_half,V_DOUBLE, V_double, V_double_width, V_cmp_result): Likewise.
(V_if_elem, V_s_elem, V_u_elem, V_uf_sclr, V_sz_elem, VD_dup): Likewise.
(V_PAIR, vqh_ops, vqhs_ops, VQH_mnem, VQH_sign, V_suf64): Likewise.
(scalar_mul_constraint,Is_float_mode, Scalar_mul_8_16): Likewise.
(Is_d_reg, V_mode_nunits): Likewise.
* config/arm/vec-common.md (VALL): Move to new file.
(VALLW, VINT, VINTW): Likewise.
From-SVN: r163058
2010-08-10 15:37:25 +02:00
|
|
|
|
|
|
|
;; Quad-width vector modes without floating-point elements.
|
|
|
|
(define_mode_iterator VQI [V16QI V8HI V4SI])
|
|
|
|
|
|
|
|
;; Quad-width vector modes, with TImode added, for moves.
|
2016-01-26 16:17:00 +01:00
|
|
|
(define_mode_iterator VQXMOV [V16QI V8HI V8HF V4SI V4SF V2DI TI])
|
iterators.md: New file.
2010-08-09 Sofiane Naci <sofiane.naci@arm.com>
* config/arm/iterators.md: New file.
* config/arm/arm.md: Include iterators.md.
(QHSI): Move to new file.
(LTUGEU, cnb, optab, ior_xor): Likewise.
* config/arm/iwmmxt.md (VMMX): Move to new file.
(VSHFT, MMX_char): Likewise.
* config/arm/neon.md (VD): Move to new file.
(VDX, VDI, VQ, VQX, VQI, VQXMOV, VSTRUCT, VTAB, V_TAB_n, VW): Likewise.
(VN, VDQ, VDQW, VDQIW, VCVTF, VCVTI, VMD, VMQ, VMDQ, VMDI): Likewise.
(VMDQI, VX, VE, V64, V32, V_CVTTO, V_elem, V_ext, V_two_elem): Likewise.
(V_three_elem, V_four_elem, V_req, V_widen, V_narrow, V_HALF): Likewise.
(V_half,V_DOUBLE, V_double, V_double_width, V_cmp_result): Likewise.
(V_if_elem, V_s_elem, V_u_elem, V_uf_sclr, V_sz_elem, VD_dup): Likewise.
(V_PAIR, vqh_ops, vqhs_ops, VQH_mnem, VQH_sign, V_suf64): Likewise.
(scalar_mul_constraint,Is_float_mode, Scalar_mul_8_16): Likewise.
(Is_d_reg, V_mode_nunits): Likewise.
* config/arm/vec-common.md (VALL): Move to new file.
(VALLW, VINT, VINTW): Likewise.
From-SVN: r163058
2010-08-10 15:37:25 +02:00
|
|
|
|
|
|
|
;; Opaque structure types wider than TImode.
|
|
|
|
(define_mode_iterator VSTRUCT [EI OI CI XI])
|
|
|
|
|
|
|
|
;; Opaque structure types used in table lookups (except vtbl1/vtbx1).
|
|
|
|
(define_mode_iterator VTAB [TI EI OI])
|
|
|
|
|
|
|
|
;; Widenable modes.
|
|
|
|
(define_mode_iterator VW [V8QI V4HI V2SI])
|
|
|
|
|
|
|
|
;; Narrowable modes.
|
|
|
|
(define_mode_iterator VN [V8HI V4SI V2DI])
|
|
|
|
|
|
|
|
;; All supported vector modes (except singleton DImode).
|
2016-01-26 16:17:00 +01:00
|
|
|
(define_mode_iterator VDQ [V8QI V16QI V4HI V8HI V2SI V4SI V4HF V8HF V2SF V4SF V2DI])
|
iterators.md: New file.
2010-08-09 Sofiane Naci <sofiane.naci@arm.com>
* config/arm/iterators.md: New file.
* config/arm/arm.md: Include iterators.md.
(QHSI): Move to new file.
(LTUGEU, cnb, optab, ior_xor): Likewise.
* config/arm/iwmmxt.md (VMMX): Move to new file.
(VSHFT, MMX_char): Likewise.
* config/arm/neon.md (VD): Move to new file.
(VDX, VDI, VQ, VQX, VQI, VQXMOV, VSTRUCT, VTAB, V_TAB_n, VW): Likewise.
(VN, VDQ, VDQW, VDQIW, VCVTF, VCVTI, VMD, VMQ, VMDQ, VMDI): Likewise.
(VMDQI, VX, VE, V64, V32, V_CVTTO, V_elem, V_ext, V_two_elem): Likewise.
(V_three_elem, V_four_elem, V_req, V_widen, V_narrow, V_HALF): Likewise.
(V_half,V_DOUBLE, V_double, V_double_width, V_cmp_result): Likewise.
(V_if_elem, V_s_elem, V_u_elem, V_uf_sclr, V_sz_elem, VD_dup): Likewise.
(V_PAIR, vqh_ops, vqhs_ops, VQH_mnem, VQH_sign, V_suf64): Likewise.
(scalar_mul_constraint,Is_float_mode, Scalar_mul_8_16): Likewise.
(Is_d_reg, V_mode_nunits): Likewise.
* config/arm/vec-common.md (VALL): Move to new file.
(VALLW, VINT, VINTW): Likewise.
From-SVN: r163058
2010-08-10 15:37:25 +02:00
|
|
|
|
2018-01-17 12:51:03 +01:00
|
|
|
;; All supported floating-point vector modes (except V2DF).
|
|
|
|
(define_mode_iterator VF [(V4HF "TARGET_NEON_FP16INST")
|
|
|
|
(V8HF "TARGET_NEON_FP16INST") V2SF V4SF])
|
|
|
|
|
iterators.md: New file.
2010-08-09 Sofiane Naci <sofiane.naci@arm.com>
* config/arm/iterators.md: New file.
* config/arm/arm.md: Include iterators.md.
(QHSI): Move to new file.
(LTUGEU, cnb, optab, ior_xor): Likewise.
* config/arm/iwmmxt.md (VMMX): Move to new file.
(VSHFT, MMX_char): Likewise.
* config/arm/neon.md (VD): Move to new file.
(VDX, VDI, VQ, VQX, VQI, VQXMOV, VSTRUCT, VTAB, V_TAB_n, VW): Likewise.
(VN, VDQ, VDQW, VDQIW, VCVTF, VCVTI, VMD, VMQ, VMDQ, VMDI): Likewise.
(VMDQI, VX, VE, V64, V32, V_CVTTO, V_elem, V_ext, V_two_elem): Likewise.
(V_three_elem, V_four_elem, V_req, V_widen, V_narrow, V_HALF): Likewise.
(V_half,V_DOUBLE, V_double, V_double_width, V_cmp_result): Likewise.
(V_if_elem, V_s_elem, V_u_elem, V_uf_sclr, V_sz_elem, VD_dup): Likewise.
(V_PAIR, vqh_ops, vqhs_ops, VQH_mnem, VQH_sign, V_suf64): Likewise.
(scalar_mul_constraint,Is_float_mode, Scalar_mul_8_16): Likewise.
(Is_d_reg, V_mode_nunits): Likewise.
* config/arm/vec-common.md (VALL): Move to new file.
(VALLW, VINT, VINTW): Likewise.
From-SVN: r163058
2010-08-10 15:37:25 +02:00
|
|
|
;; All supported vector modes (except those with 64-bit integer elements).
|
|
|
|
(define_mode_iterator VDQW [V8QI V16QI V4HI V8HI V2SI V4SI V2SF V4SF])
|
|
|
|
|
2016-09-23 11:23:01 +02:00
|
|
|
;; All supported vector modes including 16-bit float modes.
|
|
|
|
(define_mode_iterator VDQWH [V8QI V16QI V4HI V8HI V2SI V4SI V2SF V4SF
|
|
|
|
V8HF V4HF])
|
|
|
|
|
iterators.md: New file.
2010-08-09 Sofiane Naci <sofiane.naci@arm.com>
* config/arm/iterators.md: New file.
* config/arm/arm.md: Include iterators.md.
(QHSI): Move to new file.
(LTUGEU, cnb, optab, ior_xor): Likewise.
* config/arm/iwmmxt.md (VMMX): Move to new file.
(VSHFT, MMX_char): Likewise.
* config/arm/neon.md (VD): Move to new file.
(VDX, VDI, VQ, VQX, VQI, VQXMOV, VSTRUCT, VTAB, V_TAB_n, VW): Likewise.
(VN, VDQ, VDQW, VDQIW, VCVTF, VCVTI, VMD, VMQ, VMDQ, VMDI): Likewise.
(VMDQI, VX, VE, V64, V32, V_CVTTO, V_elem, V_ext, V_two_elem): Likewise.
(V_three_elem, V_four_elem, V_req, V_widen, V_narrow, V_HALF): Likewise.
(V_half,V_DOUBLE, V_double, V_double_width, V_cmp_result): Likewise.
(V_if_elem, V_s_elem, V_u_elem, V_uf_sclr, V_sz_elem, VD_dup): Likewise.
(V_PAIR, vqh_ops, vqhs_ops, VQH_mnem, VQH_sign, V_suf64): Likewise.
(scalar_mul_constraint,Is_float_mode, Scalar_mul_8_16): Likewise.
(Is_d_reg, V_mode_nunits): Likewise.
* config/arm/vec-common.md (VALL): Move to new file.
(VALLW, VINT, VINTW): Likewise.
From-SVN: r163058
2010-08-10 15:37:25 +02:00
|
|
|
;; Supported integer vector modes (not 64 bit elements).
|
|
|
|
(define_mode_iterator VDQIW [V8QI V16QI V4HI V8HI V2SI V4SI])
|
|
|
|
|
|
|
|
;; Supported integer vector modes (not singleton DI)
|
|
|
|
(define_mode_iterator VDQI [V8QI V16QI V4HI V8HI V2SI V4SI V2DI])
|
|
|
|
|
|
|
|
;; Vector modes, including 64-bit integer elements.
|
[ARM] Remaining intrinsics
* config/arm/arm-builtins.c (VAR11, VAR12): New.
* config/arm/arm_neon_builtins.def (vcombine, vld2_dup, vld3_dup,
vld4_dup): Add v4hf variant.
(vget_high, vget_low): Add v8hf variant.
(vld1, vst1, vst1_lane, vld2, vld2_lane, vst2, vst2_lane, vld3,
vld3_lane, vst3, vst3_lane, vld4, vld4_lane, vst4, vst4_lane): Add
v4hf and v8hf variants.
* config/arm/iterators.md (VD_LANE, VD_RE, VQ2, VQ_HS): New.
(VDX): Add V4HF.
(V_DOUBLE): Add case for V4HF.
(VQX): Add V8HF.
(V_HALF): Add case for V8HF.
(VDQX): Add V4HF, V8HF.
(V_elem, V_two_elem, V_three_elem, V_four_elem, V_cmp_result,
V_uf_sclr, V_sz_elem, V_mode_nunits, q): Add cases for V4HF & V8HF.
* config/arm/neon.md (vec_set<mode>internal, vec_extract<mode>,
neon_vget_lane<mode>_sext_internal, neon_vget_lane<mode>_zext_internal,
vec_load_lanesoi<mode>, neon_vld2<mode>, vec_store_lanesoi<mode>,
neon_vst2<mode>, vec_load_lanesci<mode>, neon_vld3<mode>,
neon_vld3qa<mode>, neon_vld3qb<mode>, vec_store_lanesci<mode>,
neon_vst3<mode>, neon_vst3qa<mode>, neon_vst3qb<mode>,
vec_load_lanesxi<mode>, neon_vld4<mode>, neon_vld4qa<mode>,
neon_vld4qb<mode>, vec_store_lanesxi<mode>, neon_vst4<mode>,
neon_vst4qa<mode>, neon_vst4qb<mode>): Change VQ iterator to VQ2.
(neon_vcreate, neon_vreinterpretv8qi<mode>,
neon_vreinterpretv4hi<mode>, neon_vreinterpretv2si<mode>,
neon_vreinterpretv2sf<mode>, neon_vreinterpretdi<mode>):
Change VDX to VD_RE.
(neon_vld2_lane<mode>, neon_vst2_lane<mode>, neon_vld3_lane<mode>,
neon_vst3_lane<mode>, neon_vld4_lane<mode>, neon_vst4_lane<mode>):
Change VD iterator to VD_LANE, and VMQ iterator to VQ_HS.
* config/arm/arm_neon.h (float16x4x2_t, float16x8x2_t, float16x4x3_t,
float16x8x3_t, float16x4x4_t, float16x8x4_t, vcombine_f16,
vget_high_f16, vget_low_f16, vld1_f16, vld1q_f16, vst1_f16, vst1q_f16,
vst1_lane_f16, vst1q_lane_f16, vld2_f16, vld2q_f16, vld2_lane_f16,
vld2q_lane_f16, vld2_dup_f16, vst2_f16, vst2q_f16, vst2_lane_f16,
vst2q_lane_f16, vld3_f16, vld3q_f16, vld3_lane_f16, vld3q_lane_f16,
vld3_dup_f16, vst3_f16, vst3q_f16, vst3_lane_f16, vst3q_lane_f16,
vld4_f16, vld4q_f16, vld4_lane_f16, vld4q_lane_f16, vld4_dup_f16,
vst4_f16, vst4q_f16, vst4_lane_f16, vst4q_lane_f16): New.
From-SVN: r227541
2015-09-08 20:48:47 +02:00
|
|
|
(define_mode_iterator VDQX [V8QI V16QI V4HI V8HI V2SI V4SI
|
|
|
|
V4HF V8HF V2SF V4SF DI V2DI])
|
iterators.md: New file.
2010-08-09 Sofiane Naci <sofiane.naci@arm.com>
* config/arm/iterators.md: New file.
* config/arm/arm.md: Include iterators.md.
(QHSI): Move to new file.
(LTUGEU, cnb, optab, ior_xor): Likewise.
* config/arm/iwmmxt.md (VMMX): Move to new file.
(VSHFT, MMX_char): Likewise.
* config/arm/neon.md (VD): Move to new file.
(VDX, VDI, VQ, VQX, VQI, VQXMOV, VSTRUCT, VTAB, V_TAB_n, VW): Likewise.
(VN, VDQ, VDQW, VDQIW, VCVTF, VCVTI, VMD, VMQ, VMDQ, VMDI): Likewise.
(VMDQI, VX, VE, V64, V32, V_CVTTO, V_elem, V_ext, V_two_elem): Likewise.
(V_three_elem, V_four_elem, V_req, V_widen, V_narrow, V_HALF): Likewise.
(V_half,V_DOUBLE, V_double, V_double_width, V_cmp_result): Likewise.
(V_if_elem, V_s_elem, V_u_elem, V_uf_sclr, V_sz_elem, VD_dup): Likewise.
(V_PAIR, vqh_ops, vqhs_ops, VQH_mnem, VQH_sign, V_suf64): Likewise.
(scalar_mul_constraint,Is_float_mode, Scalar_mul_8_16): Likewise.
(Is_d_reg, V_mode_nunits): Likewise.
* config/arm/vec-common.md (VALL): Move to new file.
(VALLW, VINT, VINTW): Likewise.
From-SVN: r163058
2010-08-10 15:37:25 +02:00
|
|
|
|
|
|
|
;; Vector modes including 64-bit integer elements, but no floats.
|
|
|
|
(define_mode_iterator VDQIX [V8QI V16QI V4HI V8HI V2SI V4SI DI V2DI])
|
|
|
|
|
2014-05-27 12:56:25 +02:00
|
|
|
;; Vector modes for H, S and D types.
|
|
|
|
(define_mode_iterator VDQHSD [V4HI V8HI V2SI V4SI V2DI])
|
|
|
|
|
iterators.md: New file.
2010-08-09 Sofiane Naci <sofiane.naci@arm.com>
* config/arm/iterators.md: New file.
* config/arm/arm.md: Include iterators.md.
(QHSI): Move to new file.
(LTUGEU, cnb, optab, ior_xor): Likewise.
* config/arm/iwmmxt.md (VMMX): Move to new file.
(VSHFT, MMX_char): Likewise.
* config/arm/neon.md (VD): Move to new file.
(VDX, VDI, VQ, VQX, VQI, VQXMOV, VSTRUCT, VTAB, V_TAB_n, VW): Likewise.
(VN, VDQ, VDQW, VDQIW, VCVTF, VCVTI, VMD, VMQ, VMDQ, VMDI): Likewise.
(VMDQI, VX, VE, V64, V32, V_CVTTO, V_elem, V_ext, V_two_elem): Likewise.
(V_three_elem, V_four_elem, V_req, V_widen, V_narrow, V_HALF): Likewise.
(V_half,V_DOUBLE, V_double, V_double_width, V_cmp_result): Likewise.
(V_if_elem, V_s_elem, V_u_elem, V_uf_sclr, V_sz_elem, VD_dup): Likewise.
(V_PAIR, vqh_ops, vqhs_ops, VQH_mnem, VQH_sign, V_suf64): Likewise.
(scalar_mul_constraint,Is_float_mode, Scalar_mul_8_16): Likewise.
(Is_d_reg, V_mode_nunits): Likewise.
* config/arm/vec-common.md (VALL): Move to new file.
(VALLW, VINT, VINTW): Likewise.
From-SVN: r163058
2010-08-10 15:37:25 +02:00
|
|
|
;; Vector modes for float->int conversions.
|
|
|
|
(define_mode_iterator VCVTF [V2SF V4SF])
|
|
|
|
|
|
|
|
;; Vector modes form int->float conversions.
|
|
|
|
(define_mode_iterator VCVTI [V2SI V4SI])
|
|
|
|
|
2016-09-23 11:54:44 +02:00
|
|
|
;; Vector modes for int->half conversions.
|
|
|
|
(define_mode_iterator VCVTHI [V4HI V8HI])
|
|
|
|
|
iterators.md: New file.
2010-08-09 Sofiane Naci <sofiane.naci@arm.com>
* config/arm/iterators.md: New file.
* config/arm/arm.md: Include iterators.md.
(QHSI): Move to new file.
(LTUGEU, cnb, optab, ior_xor): Likewise.
* config/arm/iwmmxt.md (VMMX): Move to new file.
(VSHFT, MMX_char): Likewise.
* config/arm/neon.md (VD): Move to new file.
(VDX, VDI, VQ, VQX, VQI, VQXMOV, VSTRUCT, VTAB, V_TAB_n, VW): Likewise.
(VN, VDQ, VDQW, VDQIW, VCVTF, VCVTI, VMD, VMQ, VMDQ, VMDI): Likewise.
(VMDQI, VX, VE, V64, V32, V_CVTTO, V_elem, V_ext, V_two_elem): Likewise.
(V_three_elem, V_four_elem, V_req, V_widen, V_narrow, V_HALF): Likewise.
(V_half,V_DOUBLE, V_double, V_double_width, V_cmp_result): Likewise.
(V_if_elem, V_s_elem, V_u_elem, V_uf_sclr, V_sz_elem, VD_dup): Likewise.
(V_PAIR, vqh_ops, vqhs_ops, VQH_mnem, VQH_sign, V_suf64): Likewise.
(scalar_mul_constraint,Is_float_mode, Scalar_mul_8_16): Likewise.
(Is_d_reg, V_mode_nunits): Likewise.
* config/arm/vec-common.md (VALL): Move to new file.
(VALLW, VINT, VINTW): Likewise.
From-SVN: r163058
2010-08-10 15:37:25 +02:00
|
|
|
;; Vector modes for doubleword multiply-accumulate, etc. insns.
|
|
|
|
(define_mode_iterator VMD [V4HI V2SI V2SF])
|
|
|
|
|
|
|
|
;; Vector modes for quadword multiply-accumulate, etc. insns.
|
|
|
|
(define_mode_iterator VMQ [V8HI V4SI V4SF])
|
|
|
|
|
|
|
|
;; Above modes combined.
|
|
|
|
(define_mode_iterator VMDQ [V4HI V2SI V2SF V8HI V4SI V4SF])
|
|
|
|
|
|
|
|
;; As VMD, but integer modes only.
|
|
|
|
(define_mode_iterator VMDI [V4HI V2SI])
|
|
|
|
|
|
|
|
;; As VMQ, but integer modes only.
|
|
|
|
(define_mode_iterator VMQI [V8HI V4SI])
|
|
|
|
|
|
|
|
;; Above modes combined.
|
|
|
|
(define_mode_iterator VMDQI [V4HI V2SI V8HI V4SI])
|
|
|
|
|
|
|
|
;; Modes with 8-bit and 16-bit elements.
|
|
|
|
(define_mode_iterator VX [V8QI V4HI V16QI V8HI])
|
|
|
|
|
|
|
|
;; Modes with 8-bit elements.
|
|
|
|
(define_mode_iterator VE [V8QI V16QI])
|
|
|
|
|
|
|
|
;; Modes with 64-bit elements only.
|
|
|
|
(define_mode_iterator V64 [DI V2DI])
|
|
|
|
|
|
|
|
;; Modes with 32-bit elements only.
|
|
|
|
(define_mode_iterator V32 [V2SI V2SF V4SI V4SF])
|
|
|
|
|
2010-08-25 09:23:26 +02:00
|
|
|
;; Modes with 8-bit, 16-bit and 32-bit elements.
|
|
|
|
(define_mode_iterator VU [V16QI V8HI V4SI])
|
configure.ac (fixed-point): Add ARM support.
gcc/
* configure.ac (fixed-point): Add ARM support.
* configure: Regenerate.
* config/arm/arm.c (arm_fixed_mode_set): New struct.
(arm_set_fixed_optab_libfunc): New.
(arm_set_fixed_conv_libfunc): New.
(arm_init_libfuncs): Initialise fixed-point helper libfuncs with
ARM-specific names.
(aapcs_libcall_value): Return sub-word-size fixed-point libcall
return values in SImode.
(arm_return_in_msb): Return fixed-point types in the msb.
(arm_pad_reg_upwards, arm_pad_arg_upwards): Pad fixed-point types
upwards.
(arm_scalar_mode_supported_p): Support fixed-point modes.
(arm_vector_mode_supported_p): Support vector fixed-point modes.
* config/arm/arm.h (SHORT_FRACT_TYPE_SIZE, FRACT_TYPE_SIZE)
(LONG_FRACT_TYPE_SIZE, LONG_LONG_FRACT_TYPE_SIZE)
(SHORT_ACCUM_TYPE_SIZE, ACCUM_TYPE_SIZE, LONG_ACCUM_TYPE_SIZE)
(LONG_LONG_ACCUM_TYPE_SIZE, MAX_FIXED_MODE_SIZE): Define.
* config/arm/iterators.md (FIXED, ADDSUB, UQADDSUB, QADDSUB, QMUL):
New mode iterators.
(qaddsub_suf): New mode attribute.
* config/arm/arm-modes.def (FRACT, UFRACT, ACCUM, UACCUM): Declare
vector modes.
* config/arm/predicates.md (sat_shift_operator): New predicate.
* config/arm/arm-fixed.md: New.
* config/arm/arm.md: Include arm-fixed.md.
* config/arm/t-arm (MD_INCLUDES): Add arm-fixed.md.
libgcc/
* config.host (arm*-*-linux*, arm*-*-uclinux*, arm*-*-eabi*)
(arm*-*-symbianelf*): Add t-fixedpoint-gnu-prefix makefile fragment.
* config/arm/bpabi-lib.h (LIBGCC2_FIXEDBIT_GNU_PREFIX): Define.
gcc/testsuite/
* gcc.target/arm/fixed-point-exec.c: New test.
From-SVN: r177025
2011-08-01 14:41:30 +02:00
|
|
|
|
2016-09-23 11:23:01 +02:00
|
|
|
;; Vector modes for 16-bit floating-point support.
|
|
|
|
(define_mode_iterator VH [V8HF V4HF])
|
|
|
|
|
configure.ac (fixed-point): Add ARM support.
gcc/
* configure.ac (fixed-point): Add ARM support.
* configure: Regenerate.
* config/arm/arm.c (arm_fixed_mode_set): New struct.
(arm_set_fixed_optab_libfunc): New.
(arm_set_fixed_conv_libfunc): New.
(arm_init_libfuncs): Initialise fixed-point helper libfuncs with
ARM-specific names.
(aapcs_libcall_value): Return sub-word-size fixed-point libcall
return values in SImode.
(arm_return_in_msb): Return fixed-point types in the msb.
(arm_pad_reg_upwards, arm_pad_arg_upwards): Pad fixed-point types
upwards.
(arm_scalar_mode_supported_p): Support fixed-point modes.
(arm_vector_mode_supported_p): Support vector fixed-point modes.
* config/arm/arm.h (SHORT_FRACT_TYPE_SIZE, FRACT_TYPE_SIZE)
(LONG_FRACT_TYPE_SIZE, LONG_LONG_FRACT_TYPE_SIZE)
(SHORT_ACCUM_TYPE_SIZE, ACCUM_TYPE_SIZE, LONG_ACCUM_TYPE_SIZE)
(LONG_LONG_ACCUM_TYPE_SIZE, MAX_FIXED_MODE_SIZE): Define.
* config/arm/iterators.md (FIXED, ADDSUB, UQADDSUB, QADDSUB, QMUL):
New mode iterators.
(qaddsub_suf): New mode attribute.
* config/arm/arm-modes.def (FRACT, UFRACT, ACCUM, UACCUM): Declare
vector modes.
* config/arm/predicates.md (sat_shift_operator): New predicate.
* config/arm/arm-fixed.md: New.
* config/arm/arm.md: Include arm-fixed.md.
* config/arm/t-arm (MD_INCLUDES): Add arm-fixed.md.
libgcc/
* config.host (arm*-*-linux*, arm*-*-uclinux*, arm*-*-eabi*)
(arm*-*-symbianelf*): Add t-fixedpoint-gnu-prefix makefile fragment.
* config/arm/bpabi-lib.h (LIBGCC2_FIXEDBIT_GNU_PREFIX): Define.
gcc/testsuite/
* gcc.target/arm/fixed-point-exec.c: New test.
From-SVN: r177025
2011-08-01 14:41:30 +02:00
|
|
|
;; Iterators used for fixed-point support.
|
|
|
|
(define_mode_iterator FIXED [QQ HQ SQ UQQ UHQ USQ HA SA UHA USA])
|
|
|
|
|
|
|
|
(define_mode_iterator ADDSUB [V4QQ V2HQ V2HA])
|
|
|
|
|
|
|
|
(define_mode_iterator UQADDSUB [V4UQQ V2UHQ UQQ UHQ V2UHA UHA])
|
|
|
|
|
|
|
|
(define_mode_iterator QADDSUB [V4QQ V2HQ QQ HQ V2HA HA SQ SA])
|
|
|
|
|
|
|
|
(define_mode_iterator QMUL [HQ HA])
|
|
|
|
|
2014-11-18 10:48:14 +01:00
|
|
|
;; Modes for polynomial or float values.
|
|
|
|
(define_mode_iterator VPF [V8QI V16QI V2SF V4SF])
|
|
|
|
|
iterators.md: New file.
2010-08-09 Sofiane Naci <sofiane.naci@arm.com>
* config/arm/iterators.md: New file.
* config/arm/arm.md: Include iterators.md.
(QHSI): Move to new file.
(LTUGEU, cnb, optab, ior_xor): Likewise.
* config/arm/iwmmxt.md (VMMX): Move to new file.
(VSHFT, MMX_char): Likewise.
* config/arm/neon.md (VD): Move to new file.
(VDX, VDI, VQ, VQX, VQI, VQXMOV, VSTRUCT, VTAB, V_TAB_n, VW): Likewise.
(VN, VDQ, VDQW, VDQIW, VCVTF, VCVTI, VMD, VMQ, VMDQ, VMDI): Likewise.
(VMDQI, VX, VE, V64, V32, V_CVTTO, V_elem, V_ext, V_two_elem): Likewise.
(V_three_elem, V_four_elem, V_req, V_widen, V_narrow, V_HALF): Likewise.
(V_half,V_DOUBLE, V_double, V_double_width, V_cmp_result): Likewise.
(V_if_elem, V_s_elem, V_u_elem, V_uf_sclr, V_sz_elem, VD_dup): Likewise.
(V_PAIR, vqh_ops, vqhs_ops, VQH_mnem, VQH_sign, V_suf64): Likewise.
(scalar_mul_constraint,Is_float_mode, Scalar_mul_8_16): Likewise.
(Is_d_reg, V_mode_nunits): Likewise.
* config/arm/vec-common.md (VALL): Move to new file.
(VALLW, VINT, VINTW): Likewise.
From-SVN: r163058
2010-08-10 15:37:25 +02:00
|
|
|
;;----------------------------------------------------------------------------
|
|
|
|
;; Code iterators
|
|
|
|
;;----------------------------------------------------------------------------
|
|
|
|
|
[PATCH 8/17][ARM] Add VFP FP16 arithmetic instructions.
gcc/
2016-09-23 Matthew Wahab <matthew.wahab@arm.com>
* config/arm/iterators.md (Code iterators): Fix some white-space
in the comments.
(GLTE): New.
(ABSNEG): New
(FCVT): Moved from vfp.md.
(VCVT_HF_US_N): New.
(VCVT_SI_US_N): New.
(VCVT_HF_US): New.
(VCVTH_US): New.
(FP16_RND): New.
(absneg_str): New.
(FCVTI32typename): Moved from vfp.md.
(sup): Add UNSPEC_VCVTA_S, UNSPEC_VCVTA_U, UNSPEC_VCVTM_S,
UNSPEC_VCVTM_U, UNSPEC_VCVTN_S, UNSPEC_VCVTN_U, UNSPEC_VCVTP_S,
UNSPEC_VCVTP_U, UNSPEC_VCVT_HF_S_N, UNSPEC_VCVT_HF_U_N,
UNSPEC_VCVT_SI_S_N, UNSPEC_VCVT_SI_U_N, UNSPEC_VCVTH_S_N,
UNSPEC_VCVTH_U_N, UNSPEC_VCVTH_S and UNSPEC_VCVTH_U.
(vcvth_op): New.
(fp16_rnd_str): New.
(fp16_rnd_insn): New.
* config/arm/unspecs.md (UNSPEC_VCVT_HF_S_N): New.
(UNSPEC_VCVT_HF_U_N): New.
(UNSPEC_VCVT_SI_S_N): New.
(UNSPEC_VCVT_SI_U_N): New.
(UNSPEC_VCVTH_S): New.
(UNSPEC_VCVTH_U): New.
(UNSPEC_VCVTA_S): New.
(UNSPEC_VCVTA_U): New.
(UNSPEC_VCVTM_S): New.
(UNSPEC_VCVTM_U): New.
(UNSPEC_VCVTN_S): New.
(UNSPEC_VCVTN_U): New.
(UNSPEC_VCVTP_S): New.
(UNSPEC_VCVTP_U): New.
(UNSPEC_VCVTP_S): New.
(UNSPEC_VCVTP_U): New.
(UNSPEC_VRND): New.
(UNSPEC_VRNDA): New.
(UNSPEC_VRNDI): New.
(UNSPEC_VRNDM): New.
(UNSPEC_VRNDN): New.
(UNSPEC_VRNDP): New.
(UNSPEC_VRNDX): New.
* config/arm/vfp.md (<absneg_str>hf2): New.
(neon_vabshf): New.
(neon_v<fp16_rnd_str>hf): New.
(neon_vrndihf): New.
(addhf3): New.
(subhf3): New.
(divhf3): New.
(mulhf3): New.
(*mulsf3neghf_vfp): New.
(*negmulhf3_vfp): New.
(*mulsf3addhf_vfp): New.
(*mulhf3subhf_vfp): New.
(*mulhf3neghfaddhf_vfp): New.
(*mulhf3neghfsubhf_vfp): New.
(fmahf4): New.
(neon_vfmahf): New.
(fmsubhf4_fp16): New.
(neon_vfmshf): New.
(*fnmsubhf4): New.
(*fnmaddhf4): New.
(neon_vsqrthf): New.
(neon_vrsqrtshf): New.
(FCVT): Move to iterators.md.
(FCVTI32typename): Likewise.
(neon_vcvth<sup>hf): New.
(neon_vcvth<sup>si): New.
(neon_vcvth<sup>_nhf_unspec): New.
(neon_vcvth<sup>_nhf): New.
(neon_vcvth<sup>_nsi_unspec): New.
(neon_vcvth<sup>_nsi): New.
(neon_vcvt<vcvth_op>h<sup>si): New.
(neon_<fmaxmin_op>hf): New.
testsuite/
2016-09-23 Matthew Wahab <matthew.wahab@arm.com>
* gcc.target/arm/armv8_2-fp16-arith-1.c: New.
* gcc.target/arm/armv8_2-fp16-conv-1.c: New.
From-SVN: r240411
2016-09-23 11:46:26 +02:00
|
|
|
;; A list of condition codes used in compare instructions where
|
|
|
|
;; the carry flag from the addition is used instead of doing the
|
iterators.md: New file.
2010-08-09 Sofiane Naci <sofiane.naci@arm.com>
* config/arm/iterators.md: New file.
* config/arm/arm.md: Include iterators.md.
(QHSI): Move to new file.
(LTUGEU, cnb, optab, ior_xor): Likewise.
* config/arm/iwmmxt.md (VMMX): Move to new file.
(VSHFT, MMX_char): Likewise.
* config/arm/neon.md (VD): Move to new file.
(VDX, VDI, VQ, VQX, VQI, VQXMOV, VSTRUCT, VTAB, V_TAB_n, VW): Likewise.
(VN, VDQ, VDQW, VDQIW, VCVTF, VCVTI, VMD, VMQ, VMDQ, VMDI): Likewise.
(VMDQI, VX, VE, V64, V32, V_CVTTO, V_elem, V_ext, V_two_elem): Likewise.
(V_three_elem, V_four_elem, V_req, V_widen, V_narrow, V_HALF): Likewise.
(V_half,V_DOUBLE, V_double, V_double_width, V_cmp_result): Likewise.
(V_if_elem, V_s_elem, V_u_elem, V_uf_sclr, V_sz_elem, VD_dup): Likewise.
(V_PAIR, vqh_ops, vqhs_ops, VQH_mnem, VQH_sign, V_suf64): Likewise.
(scalar_mul_constraint,Is_float_mode, Scalar_mul_8_16): Likewise.
(Is_d_reg, V_mode_nunits): Likewise.
* config/arm/vec-common.md (VALL): Move to new file.
(VALLW, VINT, VINTW): Likewise.
From-SVN: r163058
2010-08-10 15:37:25 +02:00
|
|
|
;; compare a second time.
|
|
|
|
(define_code_iterator LTUGEU [ltu geu])
|
|
|
|
|
2015-04-23 18:19:26 +02:00
|
|
|
;; The signed gt, ge comparisons
|
|
|
|
(define_code_iterator GTGE [gt ge])
|
|
|
|
|
[PATCH 8/17][ARM] Add VFP FP16 arithmetic instructions.
gcc/
2016-09-23 Matthew Wahab <matthew.wahab@arm.com>
* config/arm/iterators.md (Code iterators): Fix some white-space
in the comments.
(GLTE): New.
(ABSNEG): New
(FCVT): Moved from vfp.md.
(VCVT_HF_US_N): New.
(VCVT_SI_US_N): New.
(VCVT_HF_US): New.
(VCVTH_US): New.
(FP16_RND): New.
(absneg_str): New.
(FCVTI32typename): Moved from vfp.md.
(sup): Add UNSPEC_VCVTA_S, UNSPEC_VCVTA_U, UNSPEC_VCVTM_S,
UNSPEC_VCVTM_U, UNSPEC_VCVTN_S, UNSPEC_VCVTN_U, UNSPEC_VCVTP_S,
UNSPEC_VCVTP_U, UNSPEC_VCVT_HF_S_N, UNSPEC_VCVT_HF_U_N,
UNSPEC_VCVT_SI_S_N, UNSPEC_VCVT_SI_U_N, UNSPEC_VCVTH_S_N,
UNSPEC_VCVTH_U_N, UNSPEC_VCVTH_S and UNSPEC_VCVTH_U.
(vcvth_op): New.
(fp16_rnd_str): New.
(fp16_rnd_insn): New.
* config/arm/unspecs.md (UNSPEC_VCVT_HF_S_N): New.
(UNSPEC_VCVT_HF_U_N): New.
(UNSPEC_VCVT_SI_S_N): New.
(UNSPEC_VCVT_SI_U_N): New.
(UNSPEC_VCVTH_S): New.
(UNSPEC_VCVTH_U): New.
(UNSPEC_VCVTA_S): New.
(UNSPEC_VCVTA_U): New.
(UNSPEC_VCVTM_S): New.
(UNSPEC_VCVTM_U): New.
(UNSPEC_VCVTN_S): New.
(UNSPEC_VCVTN_U): New.
(UNSPEC_VCVTP_S): New.
(UNSPEC_VCVTP_U): New.
(UNSPEC_VCVTP_S): New.
(UNSPEC_VCVTP_U): New.
(UNSPEC_VRND): New.
(UNSPEC_VRNDA): New.
(UNSPEC_VRNDI): New.
(UNSPEC_VRNDM): New.
(UNSPEC_VRNDN): New.
(UNSPEC_VRNDP): New.
(UNSPEC_VRNDX): New.
* config/arm/vfp.md (<absneg_str>hf2): New.
(neon_vabshf): New.
(neon_v<fp16_rnd_str>hf): New.
(neon_vrndihf): New.
(addhf3): New.
(subhf3): New.
(divhf3): New.
(mulhf3): New.
(*mulsf3neghf_vfp): New.
(*negmulhf3_vfp): New.
(*mulsf3addhf_vfp): New.
(*mulhf3subhf_vfp): New.
(*mulhf3neghfaddhf_vfp): New.
(*mulhf3neghfsubhf_vfp): New.
(fmahf4): New.
(neon_vfmahf): New.
(fmsubhf4_fp16): New.
(neon_vfmshf): New.
(*fnmsubhf4): New.
(*fnmaddhf4): New.
(neon_vsqrthf): New.
(neon_vrsqrtshf): New.
(FCVT): Move to iterators.md.
(FCVTI32typename): Likewise.
(neon_vcvth<sup>hf): New.
(neon_vcvth<sup>si): New.
(neon_vcvth<sup>_nhf_unspec): New.
(neon_vcvth<sup>_nhf): New.
(neon_vcvth<sup>_nsi_unspec): New.
(neon_vcvth<sup>_nsi): New.
(neon_vcvt<vcvth_op>h<sup>si): New.
(neon_<fmaxmin_op>hf): New.
testsuite/
2016-09-23 Matthew Wahab <matthew.wahab@arm.com>
* gcc.target/arm/armv8_2-fp16-arith-1.c: New.
* gcc.target/arm/armv8_2-fp16-conv-1.c: New.
From-SVN: r240411
2016-09-23 11:46:26 +02:00
|
|
|
;; The signed gt, ge, lt, le comparisons
|
|
|
|
(define_code_iterator GLTE [gt ge lt le])
|
|
|
|
|
2015-04-23 18:19:26 +02:00
|
|
|
;; The unsigned gt, ge comparisons
|
|
|
|
(define_code_iterator GTUGEU [gtu geu])
|
|
|
|
|
|
|
|
;; Comparisons for vc<cmp>
|
|
|
|
(define_code_iterator COMPARISONS [eq gt ge le lt])
|
|
|
|
|
iterators.md: New file.
2010-08-09 Sofiane Naci <sofiane.naci@arm.com>
* config/arm/iterators.md: New file.
* config/arm/arm.md: Include iterators.md.
(QHSI): Move to new file.
(LTUGEU, cnb, optab, ior_xor): Likewise.
* config/arm/iwmmxt.md (VMMX): Move to new file.
(VSHFT, MMX_char): Likewise.
* config/arm/neon.md (VD): Move to new file.
(VDX, VDI, VQ, VQX, VQI, VQXMOV, VSTRUCT, VTAB, V_TAB_n, VW): Likewise.
(VN, VDQ, VDQW, VDQIW, VCVTF, VCVTI, VMD, VMQ, VMDQ, VMDI): Likewise.
(VMDQI, VX, VE, V64, V32, V_CVTTO, V_elem, V_ext, V_two_elem): Likewise.
(V_three_elem, V_four_elem, V_req, V_widen, V_narrow, V_HALF): Likewise.
(V_half,V_DOUBLE, V_double, V_double_width, V_cmp_result): Likewise.
(V_if_elem, V_s_elem, V_u_elem, V_uf_sclr, V_sz_elem, VD_dup): Likewise.
(V_PAIR, vqh_ops, vqhs_ops, VQH_mnem, VQH_sign, V_suf64): Likewise.
(scalar_mul_constraint,Is_float_mode, Scalar_mul_8_16): Likewise.
(Is_d_reg, V_mode_nunits): Likewise.
* config/arm/vec-common.md (VALL): Move to new file.
(VALLW, VINT, VINTW): Likewise.
From-SVN: r163058
2010-08-10 15:37:25 +02:00
|
|
|
;; A list of ...
|
2015-04-24 17:01:32 +02:00
|
|
|
(define_code_iterator IOR_XOR [ior xor])
|
iterators.md: New file.
2010-08-09 Sofiane Naci <sofiane.naci@arm.com>
* config/arm/iterators.md: New file.
* config/arm/arm.md: Include iterators.md.
(QHSI): Move to new file.
(LTUGEU, cnb, optab, ior_xor): Likewise.
* config/arm/iwmmxt.md (VMMX): Move to new file.
(VSHFT, MMX_char): Likewise.
* config/arm/neon.md (VD): Move to new file.
(VDX, VDI, VQ, VQX, VQI, VQXMOV, VSTRUCT, VTAB, V_TAB_n, VW): Likewise.
(VN, VDQ, VDQW, VDQIW, VCVTF, VCVTI, VMD, VMQ, VMDQ, VMDI): Likewise.
(VMDQI, VX, VE, V64, V32, V_CVTTO, V_elem, V_ext, V_two_elem): Likewise.
(V_three_elem, V_four_elem, V_req, V_widen, V_narrow, V_HALF): Likewise.
(V_half,V_DOUBLE, V_double, V_double_width, V_cmp_result): Likewise.
(V_if_elem, V_s_elem, V_u_elem, V_uf_sclr, V_sz_elem, VD_dup): Likewise.
(V_PAIR, vqh_ops, vqhs_ops, VQH_mnem, VQH_sign, V_suf64): Likewise.
(scalar_mul_constraint,Is_float_mode, Scalar_mul_8_16): Likewise.
(Is_d_reg, V_mode_nunits): Likewise.
* config/arm/vec-common.md (VALL): Move to new file.
(VALLW, VINT, VINTW): Likewise.
From-SVN: r163058
2010-08-10 15:37:25 +02:00
|
|
|
|
|
|
|
;; Operations on two halves of a quadword vector.
|
2015-04-24 17:01:32 +02:00
|
|
|
(define_code_iterator VQH_OPS [plus smin smax umin umax])
|
iterators.md: New file.
2010-08-09 Sofiane Naci <sofiane.naci@arm.com>
* config/arm/iterators.md: New file.
* config/arm/arm.md: Include iterators.md.
(QHSI): Move to new file.
(LTUGEU, cnb, optab, ior_xor): Likewise.
* config/arm/iwmmxt.md (VMMX): Move to new file.
(VSHFT, MMX_char): Likewise.
* config/arm/neon.md (VD): Move to new file.
(VDX, VDI, VQ, VQX, VQI, VQXMOV, VSTRUCT, VTAB, V_TAB_n, VW): Likewise.
(VN, VDQ, VDQW, VDQIW, VCVTF, VCVTI, VMD, VMQ, VMDQ, VMDI): Likewise.
(VMDQI, VX, VE, V64, V32, V_CVTTO, V_elem, V_ext, V_two_elem): Likewise.
(V_three_elem, V_four_elem, V_req, V_widen, V_narrow, V_HALF): Likewise.
(V_half,V_DOUBLE, V_double, V_double_width, V_cmp_result): Likewise.
(V_if_elem, V_s_elem, V_u_elem, V_uf_sclr, V_sz_elem, VD_dup): Likewise.
(V_PAIR, vqh_ops, vqhs_ops, VQH_mnem, VQH_sign, V_suf64): Likewise.
(scalar_mul_constraint,Is_float_mode, Scalar_mul_8_16): Likewise.
(Is_d_reg, V_mode_nunits): Likewise.
* config/arm/vec-common.md (VALL): Move to new file.
(VALLW, VINT, VINTW): Likewise.
From-SVN: r163058
2010-08-10 15:37:25 +02:00
|
|
|
|
|
|
|
;; Operations on two halves of a quadword vector,
|
|
|
|
;; without unsigned variants (for use with *SFmode pattern).
|
2015-04-24 17:01:32 +02:00
|
|
|
(define_code_iterator VQHS_OPS [plus smin smax])
|
iterators.md: New file.
2010-08-09 Sofiane Naci <sofiane.naci@arm.com>
* config/arm/iterators.md: New file.
* config/arm/arm.md: Include iterators.md.
(QHSI): Move to new file.
(LTUGEU, cnb, optab, ior_xor): Likewise.
* config/arm/iwmmxt.md (VMMX): Move to new file.
(VSHFT, MMX_char): Likewise.
* config/arm/neon.md (VD): Move to new file.
(VDX, VDI, VQ, VQX, VQI, VQXMOV, VSTRUCT, VTAB, V_TAB_n, VW): Likewise.
(VN, VDQ, VDQW, VDQIW, VCVTF, VCVTI, VMD, VMQ, VMDQ, VMDI): Likewise.
(VMDQI, VX, VE, V64, V32, V_CVTTO, V_elem, V_ext, V_two_elem): Likewise.
(V_three_elem, V_four_elem, V_req, V_widen, V_narrow, V_HALF): Likewise.
(V_half,V_DOUBLE, V_double, V_double_width, V_cmp_result): Likewise.
(V_if_elem, V_s_elem, V_u_elem, V_uf_sclr, V_sz_elem, VD_dup): Likewise.
(V_PAIR, vqh_ops, vqhs_ops, VQH_mnem, VQH_sign, V_suf64): Likewise.
(scalar_mul_constraint,Is_float_mode, Scalar_mul_8_16): Likewise.
(Is_d_reg, V_mode_nunits): Likewise.
* config/arm/vec-common.md (VALL): Move to new file.
(VALLW, VINT, VINTW): Likewise.
From-SVN: r163058
2010-08-10 15:37:25 +02:00
|
|
|
|
2010-08-25 09:23:26 +02:00
|
|
|
;; A list of widening operators
|
|
|
|
(define_code_iterator SE [sign_extend zero_extend])
|
iterators.md: New file.
2010-08-09 Sofiane Naci <sofiane.naci@arm.com>
* config/arm/iterators.md: New file.
* config/arm/arm.md: Include iterators.md.
(QHSI): Move to new file.
(LTUGEU, cnb, optab, ior_xor): Likewise.
* config/arm/iwmmxt.md (VMMX): Move to new file.
(VSHFT, MMX_char): Likewise.
* config/arm/neon.md (VD): Move to new file.
(VDX, VDI, VQ, VQX, VQI, VQXMOV, VSTRUCT, VTAB, V_TAB_n, VW): Likewise.
(VN, VDQ, VDQW, VDQIW, VCVTF, VCVTI, VMD, VMQ, VMDQ, VMDI): Likewise.
(VMDQI, VX, VE, V64, V32, V_CVTTO, V_elem, V_ext, V_two_elem): Likewise.
(V_three_elem, V_four_elem, V_req, V_widen, V_narrow, V_HALF): Likewise.
(V_half,V_DOUBLE, V_double, V_double_width, V_cmp_result): Likewise.
(V_if_elem, V_s_elem, V_u_elem, V_uf_sclr, V_sz_elem, VD_dup): Likewise.
(V_PAIR, vqh_ops, vqhs_ops, VQH_mnem, VQH_sign, V_suf64): Likewise.
(scalar_mul_constraint,Is_float_mode, Scalar_mul_8_16): Likewise.
(Is_d_reg, V_mode_nunits): Likewise.
* config/arm/vec-common.md (VALL): Move to new file.
(VALLW, VINT, VINTW): Likewise.
From-SVN: r163058
2010-08-10 15:37:25 +02:00
|
|
|
|
arm.c (arm_emit_coreregs_64bit_shift): Fix comment.
2012-11-13 Andrew Stubbs <ams@codesourcery.com>
Ulrich Weigand <ulrich.weigand@linaro.org>
* config/arm/arm.c (arm_emit_coreregs_64bit_shift): Fix comment.
* config/arm/arm.md (opt, opt_enabled): New attributes.
(enabled): Use opt_enabled.
(ashldi3, ashrdi3, lshrdi3): Add TARGET_NEON case.
(ashldi3): Allow general operands for TARGET_NEON case.
* config/arm/iterators.md (rshifts): New code iterator.
(shift, shifttype): New code attributes.
* config/arm/neon.md (UNSPEC_LOAD_COUNT): New unspec type.
(neon_load_count, ashldi3_neon_noclobber, ashldi3_neon,
signed_shift_di3_neon, unsigned_shift_di3_neon,
ashrdi3_neon_imm_noclobber, lshrdi3_neon_imm_noclobber,
<shift>di3_neon): New patterns.
Co-Authored-By: Ulrich Weigand <ulrich.weigand@linaro.org>
From-SVN: r193476
2012-11-13 14:31:50 +01:00
|
|
|
;; Right shifts
|
2015-04-24 17:01:32 +02:00
|
|
|
(define_code_iterator RSHIFTS [ashiftrt lshiftrt])
|
arm.c (arm_emit_coreregs_64bit_shift): Fix comment.
2012-11-13 Andrew Stubbs <ams@codesourcery.com>
Ulrich Weigand <ulrich.weigand@linaro.org>
* config/arm/arm.c (arm_emit_coreregs_64bit_shift): Fix comment.
* config/arm/arm.md (opt, opt_enabled): New attributes.
(enabled): Use opt_enabled.
(ashldi3, ashrdi3, lshrdi3): Add TARGET_NEON case.
(ashldi3): Allow general operands for TARGET_NEON case.
* config/arm/iterators.md (rshifts): New code iterator.
(shift, shifttype): New code attributes.
* config/arm/neon.md (UNSPEC_LOAD_COUNT): New unspec type.
(neon_load_count, ashldi3_neon_noclobber, ashldi3_neon,
signed_shift_di3_neon, unsigned_shift_di3_neon,
ashrdi3_neon_imm_noclobber, lshrdi3_neon_imm_noclobber,
<shift>di3_neon): New patterns.
Co-Authored-By: Ulrich Weigand <ulrich.weigand@linaro.org>
From-SVN: r193476
2012-11-13 14:31:50 +01:00
|
|
|
|
2014-09-02 17:57:56 +02:00
|
|
|
;; Iterator for integer conversions
|
|
|
|
(define_code_iterator FIXUORS [fix unsigned_fix])
|
|
|
|
|
2014-05-29 11:39:07 +02:00
|
|
|
;; Binary operators whose second operand can be shifted.
|
2015-04-24 17:01:32 +02:00
|
|
|
(define_code_iterator SHIFTABLE_OPS [plus minus ior xor and])
|
2014-05-29 11:39:07 +02:00
|
|
|
|
[PATCH 8/17][ARM] Add VFP FP16 arithmetic instructions.
gcc/
2016-09-23 Matthew Wahab <matthew.wahab@arm.com>
* config/arm/iterators.md (Code iterators): Fix some white-space
in the comments.
(GLTE): New.
(ABSNEG): New
(FCVT): Moved from vfp.md.
(VCVT_HF_US_N): New.
(VCVT_SI_US_N): New.
(VCVT_HF_US): New.
(VCVTH_US): New.
(FP16_RND): New.
(absneg_str): New.
(FCVTI32typename): Moved from vfp.md.
(sup): Add UNSPEC_VCVTA_S, UNSPEC_VCVTA_U, UNSPEC_VCVTM_S,
UNSPEC_VCVTM_U, UNSPEC_VCVTN_S, UNSPEC_VCVTN_U, UNSPEC_VCVTP_S,
UNSPEC_VCVTP_U, UNSPEC_VCVT_HF_S_N, UNSPEC_VCVT_HF_U_N,
UNSPEC_VCVT_SI_S_N, UNSPEC_VCVT_SI_U_N, UNSPEC_VCVTH_S_N,
UNSPEC_VCVTH_U_N, UNSPEC_VCVTH_S and UNSPEC_VCVTH_U.
(vcvth_op): New.
(fp16_rnd_str): New.
(fp16_rnd_insn): New.
* config/arm/unspecs.md (UNSPEC_VCVT_HF_S_N): New.
(UNSPEC_VCVT_HF_U_N): New.
(UNSPEC_VCVT_SI_S_N): New.
(UNSPEC_VCVT_SI_U_N): New.
(UNSPEC_VCVTH_S): New.
(UNSPEC_VCVTH_U): New.
(UNSPEC_VCVTA_S): New.
(UNSPEC_VCVTA_U): New.
(UNSPEC_VCVTM_S): New.
(UNSPEC_VCVTM_U): New.
(UNSPEC_VCVTN_S): New.
(UNSPEC_VCVTN_U): New.
(UNSPEC_VCVTP_S): New.
(UNSPEC_VCVTP_U): New.
(UNSPEC_VCVTP_S): New.
(UNSPEC_VCVTP_U): New.
(UNSPEC_VRND): New.
(UNSPEC_VRNDA): New.
(UNSPEC_VRNDI): New.
(UNSPEC_VRNDM): New.
(UNSPEC_VRNDN): New.
(UNSPEC_VRNDP): New.
(UNSPEC_VRNDX): New.
* config/arm/vfp.md (<absneg_str>hf2): New.
(neon_vabshf): New.
(neon_v<fp16_rnd_str>hf): New.
(neon_vrndihf): New.
(addhf3): New.
(subhf3): New.
(divhf3): New.
(mulhf3): New.
(*mulsf3neghf_vfp): New.
(*negmulhf3_vfp): New.
(*mulsf3addhf_vfp): New.
(*mulhf3subhf_vfp): New.
(*mulhf3neghfaddhf_vfp): New.
(*mulhf3neghfsubhf_vfp): New.
(fmahf4): New.
(neon_vfmahf): New.
(fmsubhf4_fp16): New.
(neon_vfmshf): New.
(*fnmsubhf4): New.
(*fnmaddhf4): New.
(neon_vsqrthf): New.
(neon_vrsqrtshf): New.
(FCVT): Move to iterators.md.
(FCVTI32typename): Likewise.
(neon_vcvth<sup>hf): New.
(neon_vcvth<sup>si): New.
(neon_vcvth<sup>_nhf_unspec): New.
(neon_vcvth<sup>_nhf): New.
(neon_vcvth<sup>_nsi_unspec): New.
(neon_vcvth<sup>_nsi): New.
(neon_vcvt<vcvth_op>h<sup>si): New.
(neon_<fmaxmin_op>hf): New.
testsuite/
2016-09-23 Matthew Wahab <matthew.wahab@arm.com>
* gcc.target/arm/armv8_2-fp16-arith-1.c: New.
* gcc.target/arm/armv8_2-fp16-conv-1.c: New.
From-SVN: r240411
2016-09-23 11:46:26 +02:00
|
|
|
;; Operations on the sign of a number.
|
|
|
|
(define_code_iterator ABSNEG [abs neg])
|
|
|
|
|
|
|
|
;; Conversions.
|
|
|
|
(define_code_iterator FCVT [unsigned_float float])
|
|
|
|
|
2015-04-24 17:01:32 +02:00
|
|
|
;; plus and minus are the only SHIFTABLE_OPS for which Thumb2 allows
|
2014-05-29 11:39:07 +02:00
|
|
|
;; a stack pointer opoerand. The minus operation is a candidate for an rsub
|
|
|
|
;; and hence only plus is supported.
|
|
|
|
(define_code_attr t2_binop0
|
|
|
|
[(plus "rk") (minus "r") (ior "r") (xor "r") (and "r")])
|
|
|
|
|
2015-04-24 17:01:32 +02:00
|
|
|
;; The instruction to use when a SHIFTABLE_OPS has a shift operation as
|
2014-05-29 11:39:07 +02:00
|
|
|
;; its first operand.
|
|
|
|
(define_code_attr arith_shift_insn
|
|
|
|
[(plus "add") (minus "rsb") (ior "orr") (xor "eor") (and "and")])
|
|
|
|
|
2015-04-23 18:19:26 +02:00
|
|
|
(define_code_attr cmp_op [(eq "eq") (gt "gt") (ge "ge") (lt "lt") (le "le")
|
|
|
|
(gtu "gt") (geu "ge")])
|
|
|
|
|
|
|
|
(define_code_attr cmp_type [(eq "i") (gt "s") (ge "s") (lt "s") (le "s")])
|
|
|
|
|
2012-11-26 13:33:02 +01:00
|
|
|
;;----------------------------------------------------------------------------
|
|
|
|
;; Int iterators
|
|
|
|
;;----------------------------------------------------------------------------
|
|
|
|
|
|
|
|
(define_int_iterator VRINT [UNSPEC_VRINTZ UNSPEC_VRINTP UNSPEC_VRINTM
|
|
|
|
UNSPEC_VRINTR UNSPEC_VRINTX UNSPEC_VRINTA])
|
|
|
|
|
2016-09-23 11:54:44 +02:00
|
|
|
(define_int_iterator NEON_VCMP [UNSPEC_VCEQ UNSPEC_VCGT UNSPEC_VCGE
|
|
|
|
UNSPEC_VCLT UNSPEC_VCLE])
|
2015-04-23 18:19:26 +02:00
|
|
|
|
|
|
|
(define_int_iterator NEON_VACMP [UNSPEC_VCAGE UNSPEC_VCAGT])
|
|
|
|
|
2016-09-23 11:54:44 +02:00
|
|
|
(define_int_iterator NEON_VAGLTE [UNSPEC_VCAGE UNSPEC_VCAGT
|
|
|
|
UNSPEC_VCALE UNSPEC_VCALT])
|
|
|
|
|
2014-09-02 17:57:56 +02:00
|
|
|
(define_int_iterator VCVT [UNSPEC_VRINTP UNSPEC_VRINTM UNSPEC_VRINTA])
|
|
|
|
|
2012-12-06 10:55:45 +01:00
|
|
|
(define_int_iterator NEON_VRINT [UNSPEC_NVRINTP UNSPEC_NVRINTZ UNSPEC_NVRINTM
|
|
|
|
UNSPEC_NVRINTX UNSPEC_NVRINTA UNSPEC_NVRINTN])
|
|
|
|
|
[2/2] Vectorise lroundf, lfloorf, lceilf using the new ARMv8-A vcvt* instructions.
PR target/62275
* config/arm/neon.md
(neon_vcvt<NEON_VCVT:nvrint_variant><su_optab><VCVTF:mode>
<v_cmp_result>): New pattern.
* config/arm/iterators.md (NEON_VCVT): New int iterator.
* config/arm/arm_neon_builtins.def (vcvtav2sf, vcvtav4sf, vcvtauv2sf,
vcvtauv4sf, vcvtpv2sf, vcvtpv4sf, vcvtpuv2sf, vcvtpuv4sf, vcvtmv2sf,
vcvtmv4sf, vcvtmuv2sf, vcvtmuv4sf): New builtin definitions.
* config/arm/arm.c (arm_builtin_vectorized_function): Handle
BUILT_IN_LROUNDF, BUILT_IN_LFLOORF, BUILT_IN_LCEILF.
PR target/62275
* gcc.target/arm/vect-lceilf_1.c: New test.
* gcc.target/arm/vect-lfloorf_1.c: Likewise.
* gcc.target/arm/vect-lroundf_1.c: Likewise.
From-SVN: r214826
2014-09-02 18:00:01 +02:00
|
|
|
(define_int_iterator NEON_VCVT [UNSPEC_NVRINTP UNSPEC_NVRINTM UNSPEC_NVRINTA])
|
|
|
|
|
2014-11-18 10:48:14 +01:00
|
|
|
(define_int_iterator VADDL [UNSPEC_VADDL_S UNSPEC_VADDL_U])
|
|
|
|
|
|
|
|
(define_int_iterator VADDW [UNSPEC_VADDW_S UNSPEC_VADDW_U])
|
|
|
|
|
|
|
|
(define_int_iterator VHADD [UNSPEC_VRHADD_S UNSPEC_VRHADD_U
|
|
|
|
UNSPEC_VHADD_S UNSPEC_VHADD_U])
|
|
|
|
|
|
|
|
(define_int_iterator VQADD [UNSPEC_VQADD_S UNSPEC_VQADD_U])
|
|
|
|
|
|
|
|
(define_int_iterator VADDHN [UNSPEC_VADDHN UNSPEC_VRADDHN])
|
|
|
|
|
|
|
|
(define_int_iterator VMLAL [UNSPEC_VMLAL_S UNSPEC_VMLAL_U])
|
|
|
|
|
|
|
|
(define_int_iterator VMLAL_LANE [UNSPEC_VMLAL_S_LANE UNSPEC_VMLAL_U_LANE])
|
|
|
|
|
|
|
|
(define_int_iterator VMLSL [UNSPEC_VMLSL_S UNSPEC_VMLSL_U])
|
|
|
|
|
|
|
|
(define_int_iterator VMLSL_LANE [UNSPEC_VMLSL_S_LANE UNSPEC_VMLSL_U_LANE])
|
|
|
|
|
|
|
|
(define_int_iterator VQDMULH [UNSPEC_VQDMULH UNSPEC_VQRDMULH])
|
|
|
|
|
|
|
|
(define_int_iterator VQDMULH_LANE [UNSPEC_VQDMULH_LANE UNSPEC_VQRDMULH_LANE])
|
|
|
|
|
|
|
|
(define_int_iterator VMULL [UNSPEC_VMULL_S UNSPEC_VMULL_U UNSPEC_VMULL_P])
|
|
|
|
|
|
|
|
(define_int_iterator VMULL_LANE [UNSPEC_VMULL_S_LANE UNSPEC_VMULL_U_LANE])
|
|
|
|
|
|
|
|
(define_int_iterator VSUBL [UNSPEC_VSUBL_S UNSPEC_VSUBL_U])
|
|
|
|
|
|
|
|
(define_int_iterator VSUBW [UNSPEC_VSUBW_S UNSPEC_VSUBW_U])
|
|
|
|
|
|
|
|
(define_int_iterator VHSUB [UNSPEC_VHSUB_S UNSPEC_VHSUB_U])
|
|
|
|
|
|
|
|
(define_int_iterator VQSUB [UNSPEC_VQSUB_S UNSPEC_VQSUB_U])
|
|
|
|
|
|
|
|
(define_int_iterator VSUBHN [UNSPEC_VSUBHN UNSPEC_VRSUBHN])
|
|
|
|
|
|
|
|
(define_int_iterator VABD [UNSPEC_VABD_S UNSPEC_VABD_U])
|
|
|
|
|
|
|
|
(define_int_iterator VABDL [UNSPEC_VABDL_S UNSPEC_VABDL_U])
|
|
|
|
|
|
|
|
(define_int_iterator VMAXMIN [UNSPEC_VMAX UNSPEC_VMAX_U
|
|
|
|
UNSPEC_VMIN UNSPEC_VMIN_U])
|
|
|
|
|
|
|
|
(define_int_iterator VMAXMINF [UNSPEC_VMAX UNSPEC_VMIN])
|
|
|
|
|
2015-12-23 11:28:18 +01:00
|
|
|
(define_int_iterator VMAXMINFNM [UNSPEC_VMAXNM UNSPEC_VMINNM])
|
|
|
|
|
2014-11-18 10:48:14 +01:00
|
|
|
(define_int_iterator VPADDL [UNSPEC_VPADDL_S UNSPEC_VPADDL_U])
|
|
|
|
|
|
|
|
(define_int_iterator VPADAL [UNSPEC_VPADAL_S UNSPEC_VPADAL_U])
|
|
|
|
|
|
|
|
(define_int_iterator VPMAXMIN [UNSPEC_VPMAX UNSPEC_VPMAX_U
|
|
|
|
UNSPEC_VPMIN UNSPEC_VPMIN_U])
|
|
|
|
|
|
|
|
(define_int_iterator VPMAXMINF [UNSPEC_VPMAX UNSPEC_VPMIN])
|
|
|
|
|
|
|
|
(define_int_iterator VCVT_US [UNSPEC_VCVT_S UNSPEC_VCVT_U])
|
|
|
|
|
|
|
|
(define_int_iterator VCVT_US_N [UNSPEC_VCVT_S_N UNSPEC_VCVT_U_N])
|
|
|
|
|
[PATCH 8/17][ARM] Add VFP FP16 arithmetic instructions.
gcc/
2016-09-23 Matthew Wahab <matthew.wahab@arm.com>
* config/arm/iterators.md (Code iterators): Fix some white-space
in the comments.
(GLTE): New.
(ABSNEG): New
(FCVT): Moved from vfp.md.
(VCVT_HF_US_N): New.
(VCVT_SI_US_N): New.
(VCVT_HF_US): New.
(VCVTH_US): New.
(FP16_RND): New.
(absneg_str): New.
(FCVTI32typename): Moved from vfp.md.
(sup): Add UNSPEC_VCVTA_S, UNSPEC_VCVTA_U, UNSPEC_VCVTM_S,
UNSPEC_VCVTM_U, UNSPEC_VCVTN_S, UNSPEC_VCVTN_U, UNSPEC_VCVTP_S,
UNSPEC_VCVTP_U, UNSPEC_VCVT_HF_S_N, UNSPEC_VCVT_HF_U_N,
UNSPEC_VCVT_SI_S_N, UNSPEC_VCVT_SI_U_N, UNSPEC_VCVTH_S_N,
UNSPEC_VCVTH_U_N, UNSPEC_VCVTH_S and UNSPEC_VCVTH_U.
(vcvth_op): New.
(fp16_rnd_str): New.
(fp16_rnd_insn): New.
* config/arm/unspecs.md (UNSPEC_VCVT_HF_S_N): New.
(UNSPEC_VCVT_HF_U_N): New.
(UNSPEC_VCVT_SI_S_N): New.
(UNSPEC_VCVT_SI_U_N): New.
(UNSPEC_VCVTH_S): New.
(UNSPEC_VCVTH_U): New.
(UNSPEC_VCVTA_S): New.
(UNSPEC_VCVTA_U): New.
(UNSPEC_VCVTM_S): New.
(UNSPEC_VCVTM_U): New.
(UNSPEC_VCVTN_S): New.
(UNSPEC_VCVTN_U): New.
(UNSPEC_VCVTP_S): New.
(UNSPEC_VCVTP_U): New.
(UNSPEC_VCVTP_S): New.
(UNSPEC_VCVTP_U): New.
(UNSPEC_VRND): New.
(UNSPEC_VRNDA): New.
(UNSPEC_VRNDI): New.
(UNSPEC_VRNDM): New.
(UNSPEC_VRNDN): New.
(UNSPEC_VRNDP): New.
(UNSPEC_VRNDX): New.
* config/arm/vfp.md (<absneg_str>hf2): New.
(neon_vabshf): New.
(neon_v<fp16_rnd_str>hf): New.
(neon_vrndihf): New.
(addhf3): New.
(subhf3): New.
(divhf3): New.
(mulhf3): New.
(*mulsf3neghf_vfp): New.
(*negmulhf3_vfp): New.
(*mulsf3addhf_vfp): New.
(*mulhf3subhf_vfp): New.
(*mulhf3neghfaddhf_vfp): New.
(*mulhf3neghfsubhf_vfp): New.
(fmahf4): New.
(neon_vfmahf): New.
(fmsubhf4_fp16): New.
(neon_vfmshf): New.
(*fnmsubhf4): New.
(*fnmaddhf4): New.
(neon_vsqrthf): New.
(neon_vrsqrtshf): New.
(FCVT): Move to iterators.md.
(FCVTI32typename): Likewise.
(neon_vcvth<sup>hf): New.
(neon_vcvth<sup>si): New.
(neon_vcvth<sup>_nhf_unspec): New.
(neon_vcvth<sup>_nhf): New.
(neon_vcvth<sup>_nsi_unspec): New.
(neon_vcvth<sup>_nsi): New.
(neon_vcvt<vcvth_op>h<sup>si): New.
(neon_<fmaxmin_op>hf): New.
testsuite/
2016-09-23 Matthew Wahab <matthew.wahab@arm.com>
* gcc.target/arm/armv8_2-fp16-arith-1.c: New.
* gcc.target/arm/armv8_2-fp16-conv-1.c: New.
From-SVN: r240411
2016-09-23 11:46:26 +02:00
|
|
|
(define_int_iterator VCVT_HF_US_N [UNSPEC_VCVT_HF_S_N UNSPEC_VCVT_HF_U_N])
|
|
|
|
|
|
|
|
(define_int_iterator VCVT_SI_US_N [UNSPEC_VCVT_SI_S_N UNSPEC_VCVT_SI_U_N])
|
|
|
|
|
|
|
|
(define_int_iterator VCVT_HF_US [UNSPEC_VCVTA_S UNSPEC_VCVTA_U
|
|
|
|
UNSPEC_VCVTM_S UNSPEC_VCVTM_U
|
|
|
|
UNSPEC_VCVTN_S UNSPEC_VCVTN_U
|
|
|
|
UNSPEC_VCVTP_S UNSPEC_VCVTP_U])
|
|
|
|
|
|
|
|
(define_int_iterator VCVTH_US [UNSPEC_VCVTH_S UNSPEC_VCVTH_U])
|
|
|
|
|
|
|
|
;; Operators for FP16 instructions.
|
|
|
|
(define_int_iterator FP16_RND [UNSPEC_VRND UNSPEC_VRNDA
|
|
|
|
UNSPEC_VRNDM UNSPEC_VRNDN
|
|
|
|
UNSPEC_VRNDP UNSPEC_VRNDX])
|
|
|
|
|
2014-11-18 10:48:14 +01:00
|
|
|
(define_int_iterator VQMOVN [UNSPEC_VQMOVN_S UNSPEC_VQMOVN_U])
|
|
|
|
|
|
|
|
(define_int_iterator VMOVL [UNSPEC_VMOVL_S UNSPEC_VMOVL_U])
|
|
|
|
|
|
|
|
(define_int_iterator VSHL [UNSPEC_VSHL_S UNSPEC_VSHL_U
|
|
|
|
UNSPEC_VRSHL_S UNSPEC_VRSHL_U])
|
|
|
|
|
|
|
|
(define_int_iterator VQSHL [UNSPEC_VQSHL_S UNSPEC_VQSHL_U
|
|
|
|
UNSPEC_VQRSHL_S UNSPEC_VQRSHL_U])
|
|
|
|
|
|
|
|
(define_int_iterator VSHR_N [UNSPEC_VSHR_S_N UNSPEC_VSHR_U_N
|
|
|
|
UNSPEC_VRSHR_S_N UNSPEC_VRSHR_U_N])
|
|
|
|
|
|
|
|
(define_int_iterator VSHRN_N [UNSPEC_VSHRN_N UNSPEC_VRSHRN_N])
|
|
|
|
|
|
|
|
(define_int_iterator VQSHRN_N [UNSPEC_VQSHRN_S_N UNSPEC_VQSHRN_U_N
|
|
|
|
UNSPEC_VQRSHRN_S_N UNSPEC_VQRSHRN_U_N])
|
|
|
|
|
|
|
|
(define_int_iterator VQSHRUN_N [UNSPEC_VQSHRUN_N UNSPEC_VQRSHRUN_N])
|
|
|
|
|
|
|
|
(define_int_iterator VQSHL_N [UNSPEC_VQSHL_S_N UNSPEC_VQSHL_U_N])
|
|
|
|
|
|
|
|
(define_int_iterator VSHLL_N [UNSPEC_VSHLL_S_N UNSPEC_VSHLL_U_N])
|
|
|
|
|
|
|
|
(define_int_iterator VSRA_N [UNSPEC_VSRA_S_N UNSPEC_VSRA_U_N
|
|
|
|
UNSPEC_VRSRA_S_N UNSPEC_VRSRA_U_N])
|
|
|
|
|
2013-12-19 18:55:38 +01:00
|
|
|
(define_int_iterator CRC [UNSPEC_CRC32B UNSPEC_CRC32H UNSPEC_CRC32W
|
|
|
|
UNSPEC_CRC32CB UNSPEC_CRC32CH UNSPEC_CRC32CW])
|
|
|
|
|
arm.c (enum arm_builtins): Add crypto builtins.
2013-12-19 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
* config/arm/arm.c (enum arm_builtins): Add crypto builtins.
(arm_init_neon_builtins): Handle crypto builtins.
(bdesc_2arg): Likewise.
(bdesc_1arg): Likewise.
(bdesc_3arg): New table.
(arm_expand_ternop_builtin): New function.
(arm_expand_unop_builtin): Handle sha1h explicitly.
(arm_expand_builtin): Handle ternary builtins.
* config/arm/arm.h (TARGET_CPU_CPP_BUILTINS):
Define __ARM_FEATURE_CRYPTO.
* config/arm/arm.md: Include crypto.md.
(is_neon_type): Add crypto types.
* config/arm/arm_neon_builtins.def: Add TImode reinterprets.
* config/arm/crypto.def: New.
* config/arm/crypto.md: Likewise.
* config/arm/iterators.md (CRYPTO_UNARY): New int iterator.
(CRYPTO_BINARY): Likewise.
(CRYPTO_TERNARY): Likewise.
(CRYPTO_SELECTING): Likewise.
(crypto_pattern): New int attribute.
(crypto_size_sfx): Likewise.
(crypto_mode): Likewise.
(crypto_type): Likewise.
* config/arm/neon-gen.ml: Handle poly64_t and poly128_t types.
Handle crypto intrinsics.
* config/arm/neon.ml: Add support for poly64 and polt128 types
and intrinsics. Define crypto intrinsics.
* config/arm/neon.md (neon_vreinterpretti<mode>): New pattern.
(neon_vreinterpretv16qi<mode>): Use VQXMOV mode iterator.
(neon_vreinterpretv8hi<mode>): Likewise.
(neon_vreinterpretv4si<mode>): Likewise.
(neon_vreinterpretv4sf<mode>): Likewise.
(neon_vreinterpretv2di<mode>): Likewise.
* config/arm/unspecs.md (UNSPEC_AESD, UNSPEC_AESE, UNSPEC_AESIMC,
UNSPEC_AESMC, UNSPEC_SHA1C, UNSPEC_SHA1M, UNSPEC_SHA1P, UNSPEC_SHA1H,
UNSPEC_SHA1SU0, UNSPEC_SHA1SU1, UNSPEC_SHA256H, UNSPEC_SHA256H2,
UNSPEC_SHA256SU0, UNSPEC_SHA256SU1, VMULLP64): Define.
* config/arm/arm_neon.h: Regenerate.
From-SVN: r206130
2013-12-19 19:21:10 +01:00
|
|
|
(define_int_iterator CRYPTO_UNARY [UNSPEC_AESMC UNSPEC_AESIMC])
|
|
|
|
|
|
|
|
(define_int_iterator CRYPTO_BINARY [UNSPEC_AESD UNSPEC_AESE
|
|
|
|
UNSPEC_SHA1SU1 UNSPEC_SHA256SU0])
|
|
|
|
|
|
|
|
(define_int_iterator CRYPTO_TERNARY [UNSPEC_SHA1SU0 UNSPEC_SHA256H
|
|
|
|
UNSPEC_SHA256H2 UNSPEC_SHA256SU1])
|
|
|
|
|
|
|
|
(define_int_iterator CRYPTO_SELECTING [UNSPEC_SHA1C UNSPEC_SHA1M
|
|
|
|
UNSPEC_SHA1P])
|
|
|
|
|
2015-12-16 12:56:21 +01:00
|
|
|
(define_int_iterator VQRDMLH_AS [UNSPEC_VQRDMLAH UNSPEC_VQRDMLSH])
|
|
|
|
|
2016-09-23 11:54:44 +02:00
|
|
|
(define_int_iterator VFM_LANE_AS [UNSPEC_VFMA_LANE UNSPEC_VFMS_LANE])
|
|
|
|
|
iterators.md: New file.
2010-08-09 Sofiane Naci <sofiane.naci@arm.com>
* config/arm/iterators.md: New file.
* config/arm/arm.md: Include iterators.md.
(QHSI): Move to new file.
(LTUGEU, cnb, optab, ior_xor): Likewise.
* config/arm/iwmmxt.md (VMMX): Move to new file.
(VSHFT, MMX_char): Likewise.
* config/arm/neon.md (VD): Move to new file.
(VDX, VDI, VQ, VQX, VQI, VQXMOV, VSTRUCT, VTAB, V_TAB_n, VW): Likewise.
(VN, VDQ, VDQW, VDQIW, VCVTF, VCVTI, VMD, VMQ, VMDQ, VMDI): Likewise.
(VMDQI, VX, VE, V64, V32, V_CVTTO, V_elem, V_ext, V_two_elem): Likewise.
(V_three_elem, V_four_elem, V_req, V_widen, V_narrow, V_HALF): Likewise.
(V_half,V_DOUBLE, V_double, V_double_width, V_cmp_result): Likewise.
(V_if_elem, V_s_elem, V_u_elem, V_uf_sclr, V_sz_elem, VD_dup): Likewise.
(V_PAIR, vqh_ops, vqhs_ops, VQH_mnem, VQH_sign, V_suf64): Likewise.
(scalar_mul_constraint,Is_float_mode, Scalar_mul_8_16): Likewise.
(Is_d_reg, V_mode_nunits): Likewise.
* config/arm/vec-common.md (VALL): Move to new file.
(VALLW, VINT, VINTW): Likewise.
From-SVN: r163058
2010-08-10 15:37:25 +02:00
|
|
|
;;----------------------------------------------------------------------------
|
|
|
|
;; Mode attributes
|
|
|
|
;;----------------------------------------------------------------------------
|
|
|
|
|
|
|
|
;; Determine element size suffix from vector mode.
|
|
|
|
(define_mode_attr MMX_char [(V8QI "b") (V4HI "h") (V2SI "w") (DI "d")])
|
|
|
|
|
|
|
|
;; vtbl<n> suffix for NEON vector modes.
|
|
|
|
(define_mode_attr VTAB_n [(TI "2") (EI "3") (OI "4")])
|
|
|
|
|
|
|
|
;; (Opposite) mode to convert to/from for NEON mode conversions.
|
|
|
|
(define_mode_attr V_CVTTO [(V2SI "V2SF") (V2SF "V2SI")
|
|
|
|
(V4SI "V4SF") (V4SF "V4SI")])
|
|
|
|
|
2011-12-23 14:53:17 +01:00
|
|
|
;; As above but in lower case.
|
|
|
|
(define_mode_attr V_cvtto [(V2SI "v2sf") (V2SF "v2si")
|
|
|
|
(V4SI "v4sf") (V4SF "v4si")])
|
|
|
|
|
2016-09-23 11:54:44 +02:00
|
|
|
;; (Opposite) mode to convert to/from for vector-half mode conversions.
|
|
|
|
(define_mode_attr VH_CVTTO [(V4HI "V4HF") (V4HF "V4HI")
|
|
|
|
(V8HI "V8HF") (V8HF "V8HI")])
|
|
|
|
|
iterators.md: New file.
2010-08-09 Sofiane Naci <sofiane.naci@arm.com>
* config/arm/iterators.md: New file.
* config/arm/arm.md: Include iterators.md.
(QHSI): Move to new file.
(LTUGEU, cnb, optab, ior_xor): Likewise.
* config/arm/iwmmxt.md (VMMX): Move to new file.
(VSHFT, MMX_char): Likewise.
* config/arm/neon.md (VD): Move to new file.
(VDX, VDI, VQ, VQX, VQI, VQXMOV, VSTRUCT, VTAB, V_TAB_n, VW): Likewise.
(VN, VDQ, VDQW, VDQIW, VCVTF, VCVTI, VMD, VMQ, VMDQ, VMDI): Likewise.
(VMDQI, VX, VE, V64, V32, V_CVTTO, V_elem, V_ext, V_two_elem): Likewise.
(V_three_elem, V_four_elem, V_req, V_widen, V_narrow, V_HALF): Likewise.
(V_half,V_DOUBLE, V_double, V_double_width, V_cmp_result): Likewise.
(V_if_elem, V_s_elem, V_u_elem, V_uf_sclr, V_sz_elem, VD_dup): Likewise.
(V_PAIR, vqh_ops, vqhs_ops, VQH_mnem, VQH_sign, V_suf64): Likewise.
(scalar_mul_constraint,Is_float_mode, Scalar_mul_8_16): Likewise.
(Is_d_reg, V_mode_nunits): Likewise.
* config/arm/vec-common.md (VALL): Move to new file.
(VALLW, VINT, VINTW): Likewise.
From-SVN: r163058
2010-08-10 15:37:25 +02:00
|
|
|
;; Define element mode for each vector mode.
|
|
|
|
(define_mode_attr V_elem [(V8QI "QI") (V16QI "QI")
|
[ARM] Remaining intrinsics
* config/arm/arm-builtins.c (VAR11, VAR12): New.
* config/arm/arm_neon_builtins.def (vcombine, vld2_dup, vld3_dup,
vld4_dup): Add v4hf variant.
(vget_high, vget_low): Add v8hf variant.
(vld1, vst1, vst1_lane, vld2, vld2_lane, vst2, vst2_lane, vld3,
vld3_lane, vst3, vst3_lane, vld4, vld4_lane, vst4, vst4_lane): Add
v4hf and v8hf variants.
* config/arm/iterators.md (VD_LANE, VD_RE, VQ2, VQ_HS): New.
(VDX): Add V4HF.
(V_DOUBLE): Add case for V4HF.
(VQX): Add V8HF.
(V_HALF): Add case for V8HF.
(VDQX): Add V4HF, V8HF.
(V_elem, V_two_elem, V_three_elem, V_four_elem, V_cmp_result,
V_uf_sclr, V_sz_elem, V_mode_nunits, q): Add cases for V4HF & V8HF.
* config/arm/neon.md (vec_set<mode>internal, vec_extract<mode>,
neon_vget_lane<mode>_sext_internal, neon_vget_lane<mode>_zext_internal,
vec_load_lanesoi<mode>, neon_vld2<mode>, vec_store_lanesoi<mode>,
neon_vst2<mode>, vec_load_lanesci<mode>, neon_vld3<mode>,
neon_vld3qa<mode>, neon_vld3qb<mode>, vec_store_lanesci<mode>,
neon_vst3<mode>, neon_vst3qa<mode>, neon_vst3qb<mode>,
vec_load_lanesxi<mode>, neon_vld4<mode>, neon_vld4qa<mode>,
neon_vld4qb<mode>, vec_store_lanesxi<mode>, neon_vst4<mode>,
neon_vst4qa<mode>, neon_vst4qb<mode>): Change VQ iterator to VQ2.
(neon_vcreate, neon_vreinterpretv8qi<mode>,
neon_vreinterpretv4hi<mode>, neon_vreinterpretv2si<mode>,
neon_vreinterpretv2sf<mode>, neon_vreinterpretdi<mode>):
Change VDX to VD_RE.
(neon_vld2_lane<mode>, neon_vst2_lane<mode>, neon_vld3_lane<mode>,
neon_vst3_lane<mode>, neon_vld4_lane<mode>, neon_vst4_lane<mode>):
Change VD iterator to VD_LANE, and VMQ iterator to VQ_HS.
* config/arm/arm_neon.h (float16x4x2_t, float16x8x2_t, float16x4x3_t,
float16x8x3_t, float16x4x4_t, float16x8x4_t, vcombine_f16,
vget_high_f16, vget_low_f16, vld1_f16, vld1q_f16, vst1_f16, vst1q_f16,
vst1_lane_f16, vst1q_lane_f16, vld2_f16, vld2q_f16, vld2_lane_f16,
vld2q_lane_f16, vld2_dup_f16, vst2_f16, vst2q_f16, vst2_lane_f16,
vst2q_lane_f16, vld3_f16, vld3q_f16, vld3_lane_f16, vld3q_lane_f16,
vld3_dup_f16, vst3_f16, vst3q_f16, vst3_lane_f16, vst3q_lane_f16,
vld4_f16, vld4q_f16, vld4_lane_f16, vld4q_lane_f16, vld4_dup_f16,
vst4_f16, vst4q_f16, vst4_lane_f16, vst4q_lane_f16): New.
From-SVN: r227541
2015-09-08 20:48:47 +02:00
|
|
|
(V4HI "HI") (V8HI "HI")
|
|
|
|
(V4HF "HF") (V8HF "HF")
|
iterators.md: New file.
2010-08-09 Sofiane Naci <sofiane.naci@arm.com>
* config/arm/iterators.md: New file.
* config/arm/arm.md: Include iterators.md.
(QHSI): Move to new file.
(LTUGEU, cnb, optab, ior_xor): Likewise.
* config/arm/iwmmxt.md (VMMX): Move to new file.
(VSHFT, MMX_char): Likewise.
* config/arm/neon.md (VD): Move to new file.
(VDX, VDI, VQ, VQX, VQI, VQXMOV, VSTRUCT, VTAB, V_TAB_n, VW): Likewise.
(VN, VDQ, VDQW, VDQIW, VCVTF, VCVTI, VMD, VMQ, VMDQ, VMDI): Likewise.
(VMDQI, VX, VE, V64, V32, V_CVTTO, V_elem, V_ext, V_two_elem): Likewise.
(V_three_elem, V_four_elem, V_req, V_widen, V_narrow, V_HALF): Likewise.
(V_half,V_DOUBLE, V_double, V_double_width, V_cmp_result): Likewise.
(V_if_elem, V_s_elem, V_u_elem, V_uf_sclr, V_sz_elem, VD_dup): Likewise.
(V_PAIR, vqh_ops, vqhs_ops, VQH_mnem, VQH_sign, V_suf64): Likewise.
(scalar_mul_constraint,Is_float_mode, Scalar_mul_8_16): Likewise.
(Is_d_reg, V_mode_nunits): Likewise.
* config/arm/vec-common.md (VALL): Move to new file.
(VALLW, VINT, VINTW): Likewise.
From-SVN: r163058
2010-08-10 15:37:25 +02:00
|
|
|
(V2SI "SI") (V4SI "SI")
|
|
|
|
(V2SF "SF") (V4SF "SF")
|
|
|
|
(DI "DI") (V2DI "DI")])
|
|
|
|
|
|
|
|
;; Element modes for vector extraction, padded up to register size.
|
|
|
|
|
|
|
|
(define_mode_attr V_ext [(V8QI "SI") (V16QI "SI")
|
|
|
|
(V4HI "SI") (V8HI "SI")
|
|
|
|
(V2SI "SI") (V4SI "SI")
|
|
|
|
(V2SF "SF") (V4SF "SF")
|
|
|
|
(DI "DI") (V2DI "DI")])
|
|
|
|
|
|
|
|
;; Mode of pair of elements for each vector mode, to define transfer
|
|
|
|
;; size for structure lane/dup loads and stores.
|
arm.c (arm_print_operand): Use MEM_SIZE to get the size of a '%A' memory reference.
gcc/
* config/arm/arm.c (arm_print_operand): Use MEM_SIZE to get the
size of a '%A' memory reference.
(T_DREG, T_QREG): New neon_builtin_type_bits.
(arm_init_neon_builtins): Assert that the load and store operands
are neon_struct_operands.
(locate_neon_builtin_icode): Provide the neon_builtin_type_bits.
(NEON_ARG_MEMORY): New builtin_arg.
(neon_dereference_pointer): New function.
(arm_expand_neon_args): Add a neon_builtin_type_bits argument.
Handle NEON_ARG_MEMORY.
(arm_expand_neon_builtin): Update after above interface changes.
Use NEON_ARG_MEMORY for loads and stores.
* config/arm/predicates.md (neon_struct_operand): New predicate.
* config/arm/iterators.md (V_two_elem): Tweak formatting.
(V_three_elem): Use BLKmode for accesses that have no associated mode.
(V_four_elem): Tweak formatting.
* config/arm/neon.md (neon_vld1<mode>, neon_vld1_dup<mode>)
(neon_vst1_lane<mode>, neon_vst1<mode>, neon_vld2<mode>)
(neon_vld2_lane<mode>, neon_vld2_dup<mode>, neon_vst2<mode>)
(neon_vst2_lane<mode>, neon_vld3<mode>, neon_vld3_lane<mode>)
(neon_vld3_dup<mode>, neon_vst3<mode>, neon_vst3_lane<mode>)
(neon_vld4<mode>, neon_vld4_lane<mode>, neon_vld4_dup<mode>)
(neon_vst4<mode>): Replace pointer operand with a memory operand.
Use %A in the output template.
(neon_vld3qa<mode>, neon_vld3qb<mode>, neon_vst3qa<mode>)
(neon_vst3qb<mode>, neon_vld4qa<mode>, neon_vld4qb<mode>)
(neon_vst4qa<mode>, neon_vst4qb<mode>): Likewise, but halve
the width of the memory access. Remove post-increment.
* config/arm/neon-testgen.ml: Allow addresses to have an alignment.
gcc/testsuite/
* gcc.target/arm/neon-vld3-1.c: New test.
* gcc.target/arm/neon-vst3-1.c: New test.
* gcc.target/arm/neon/v*.c: Regenerate.
From-SVN: r172314
2011-04-12 14:19:38 +02:00
|
|
|
(define_mode_attr V_two_elem [(V8QI "HI") (V16QI "HI")
|
|
|
|
(V4HI "SI") (V8HI "SI")
|
[ARM] Remaining intrinsics
* config/arm/arm-builtins.c (VAR11, VAR12): New.
* config/arm/arm_neon_builtins.def (vcombine, vld2_dup, vld3_dup,
vld4_dup): Add v4hf variant.
(vget_high, vget_low): Add v8hf variant.
(vld1, vst1, vst1_lane, vld2, vld2_lane, vst2, vst2_lane, vld3,
vld3_lane, vst3, vst3_lane, vld4, vld4_lane, vst4, vst4_lane): Add
v4hf and v8hf variants.
* config/arm/iterators.md (VD_LANE, VD_RE, VQ2, VQ_HS): New.
(VDX): Add V4HF.
(V_DOUBLE): Add case for V4HF.
(VQX): Add V8HF.
(V_HALF): Add case for V8HF.
(VDQX): Add V4HF, V8HF.
(V_elem, V_two_elem, V_three_elem, V_four_elem, V_cmp_result,
V_uf_sclr, V_sz_elem, V_mode_nunits, q): Add cases for V4HF & V8HF.
* config/arm/neon.md (vec_set<mode>internal, vec_extract<mode>,
neon_vget_lane<mode>_sext_internal, neon_vget_lane<mode>_zext_internal,
vec_load_lanesoi<mode>, neon_vld2<mode>, vec_store_lanesoi<mode>,
neon_vst2<mode>, vec_load_lanesci<mode>, neon_vld3<mode>,
neon_vld3qa<mode>, neon_vld3qb<mode>, vec_store_lanesci<mode>,
neon_vst3<mode>, neon_vst3qa<mode>, neon_vst3qb<mode>,
vec_load_lanesxi<mode>, neon_vld4<mode>, neon_vld4qa<mode>,
neon_vld4qb<mode>, vec_store_lanesxi<mode>, neon_vst4<mode>,
neon_vst4qa<mode>, neon_vst4qb<mode>): Change VQ iterator to VQ2.
(neon_vcreate, neon_vreinterpretv8qi<mode>,
neon_vreinterpretv4hi<mode>, neon_vreinterpretv2si<mode>,
neon_vreinterpretv2sf<mode>, neon_vreinterpretdi<mode>):
Change VDX to VD_RE.
(neon_vld2_lane<mode>, neon_vst2_lane<mode>, neon_vld3_lane<mode>,
neon_vst3_lane<mode>, neon_vld4_lane<mode>, neon_vst4_lane<mode>):
Change VD iterator to VD_LANE, and VMQ iterator to VQ_HS.
* config/arm/arm_neon.h (float16x4x2_t, float16x8x2_t, float16x4x3_t,
float16x8x3_t, float16x4x4_t, float16x8x4_t, vcombine_f16,
vget_high_f16, vget_low_f16, vld1_f16, vld1q_f16, vst1_f16, vst1q_f16,
vst1_lane_f16, vst1q_lane_f16, vld2_f16, vld2q_f16, vld2_lane_f16,
vld2q_lane_f16, vld2_dup_f16, vst2_f16, vst2q_f16, vst2_lane_f16,
vst2q_lane_f16, vld3_f16, vld3q_f16, vld3_lane_f16, vld3q_lane_f16,
vld3_dup_f16, vst3_f16, vst3q_f16, vst3_lane_f16, vst3q_lane_f16,
vld4_f16, vld4q_f16, vld4_lane_f16, vld4q_lane_f16, vld4_dup_f16,
vst4_f16, vst4q_f16, vst4_lane_f16, vst4q_lane_f16): New.
From-SVN: r227541
2015-09-08 20:48:47 +02:00
|
|
|
(V4HF "SF") (V8HF "SF")
|
iterators.md: New file.
2010-08-09 Sofiane Naci <sofiane.naci@arm.com>
* config/arm/iterators.md: New file.
* config/arm/arm.md: Include iterators.md.
(QHSI): Move to new file.
(LTUGEU, cnb, optab, ior_xor): Likewise.
* config/arm/iwmmxt.md (VMMX): Move to new file.
(VSHFT, MMX_char): Likewise.
* config/arm/neon.md (VD): Move to new file.
(VDX, VDI, VQ, VQX, VQI, VQXMOV, VSTRUCT, VTAB, V_TAB_n, VW): Likewise.
(VN, VDQ, VDQW, VDQIW, VCVTF, VCVTI, VMD, VMQ, VMDQ, VMDI): Likewise.
(VMDQI, VX, VE, V64, V32, V_CVTTO, V_elem, V_ext, V_two_elem): Likewise.
(V_three_elem, V_four_elem, V_req, V_widen, V_narrow, V_HALF): Likewise.
(V_half,V_DOUBLE, V_double, V_double_width, V_cmp_result): Likewise.
(V_if_elem, V_s_elem, V_u_elem, V_uf_sclr, V_sz_elem, VD_dup): Likewise.
(V_PAIR, vqh_ops, vqhs_ops, VQH_mnem, VQH_sign, V_suf64): Likewise.
(scalar_mul_constraint,Is_float_mode, Scalar_mul_8_16): Likewise.
(Is_d_reg, V_mode_nunits): Likewise.
* config/arm/vec-common.md (VALL): Move to new file.
(VALLW, VINT, VINTW): Likewise.
From-SVN: r163058
2010-08-10 15:37:25 +02:00
|
|
|
(V2SI "V2SI") (V4SI "V2SI")
|
|
|
|
(V2SF "V2SF") (V4SF "V2SF")
|
|
|
|
(DI "V2DI") (V2DI "V2DI")])
|
|
|
|
|
|
|
|
;; Similar, for three elements.
|
arm.c (arm_print_operand): Use MEM_SIZE to get the size of a '%A' memory reference.
gcc/
* config/arm/arm.c (arm_print_operand): Use MEM_SIZE to get the
size of a '%A' memory reference.
(T_DREG, T_QREG): New neon_builtin_type_bits.
(arm_init_neon_builtins): Assert that the load and store operands
are neon_struct_operands.
(locate_neon_builtin_icode): Provide the neon_builtin_type_bits.
(NEON_ARG_MEMORY): New builtin_arg.
(neon_dereference_pointer): New function.
(arm_expand_neon_args): Add a neon_builtin_type_bits argument.
Handle NEON_ARG_MEMORY.
(arm_expand_neon_builtin): Update after above interface changes.
Use NEON_ARG_MEMORY for loads and stores.
* config/arm/predicates.md (neon_struct_operand): New predicate.
* config/arm/iterators.md (V_two_elem): Tweak formatting.
(V_three_elem): Use BLKmode for accesses that have no associated mode.
(V_four_elem): Tweak formatting.
* config/arm/neon.md (neon_vld1<mode>, neon_vld1_dup<mode>)
(neon_vst1_lane<mode>, neon_vst1<mode>, neon_vld2<mode>)
(neon_vld2_lane<mode>, neon_vld2_dup<mode>, neon_vst2<mode>)
(neon_vst2_lane<mode>, neon_vld3<mode>, neon_vld3_lane<mode>)
(neon_vld3_dup<mode>, neon_vst3<mode>, neon_vst3_lane<mode>)
(neon_vld4<mode>, neon_vld4_lane<mode>, neon_vld4_dup<mode>)
(neon_vst4<mode>): Replace pointer operand with a memory operand.
Use %A in the output template.
(neon_vld3qa<mode>, neon_vld3qb<mode>, neon_vst3qa<mode>)
(neon_vst3qb<mode>, neon_vld4qa<mode>, neon_vld4qb<mode>)
(neon_vst4qa<mode>, neon_vst4qb<mode>): Likewise, but halve
the width of the memory access. Remove post-increment.
* config/arm/neon-testgen.ml: Allow addresses to have an alignment.
gcc/testsuite/
* gcc.target/arm/neon-vld3-1.c: New test.
* gcc.target/arm/neon-vst3-1.c: New test.
* gcc.target/arm/neon/v*.c: Regenerate.
From-SVN: r172314
2011-04-12 14:19:38 +02:00
|
|
|
(define_mode_attr V_three_elem [(V8QI "BLK") (V16QI "BLK")
|
|
|
|
(V4HI "BLK") (V8HI "BLK")
|
[ARM] Remaining intrinsics
* config/arm/arm-builtins.c (VAR11, VAR12): New.
* config/arm/arm_neon_builtins.def (vcombine, vld2_dup, vld3_dup,
vld4_dup): Add v4hf variant.
(vget_high, vget_low): Add v8hf variant.
(vld1, vst1, vst1_lane, vld2, vld2_lane, vst2, vst2_lane, vld3,
vld3_lane, vst3, vst3_lane, vld4, vld4_lane, vst4, vst4_lane): Add
v4hf and v8hf variants.
* config/arm/iterators.md (VD_LANE, VD_RE, VQ2, VQ_HS): New.
(VDX): Add V4HF.
(V_DOUBLE): Add case for V4HF.
(VQX): Add V8HF.
(V_HALF): Add case for V8HF.
(VDQX): Add V4HF, V8HF.
(V_elem, V_two_elem, V_three_elem, V_four_elem, V_cmp_result,
V_uf_sclr, V_sz_elem, V_mode_nunits, q): Add cases for V4HF & V8HF.
* config/arm/neon.md (vec_set<mode>internal, vec_extract<mode>,
neon_vget_lane<mode>_sext_internal, neon_vget_lane<mode>_zext_internal,
vec_load_lanesoi<mode>, neon_vld2<mode>, vec_store_lanesoi<mode>,
neon_vst2<mode>, vec_load_lanesci<mode>, neon_vld3<mode>,
neon_vld3qa<mode>, neon_vld3qb<mode>, vec_store_lanesci<mode>,
neon_vst3<mode>, neon_vst3qa<mode>, neon_vst3qb<mode>,
vec_load_lanesxi<mode>, neon_vld4<mode>, neon_vld4qa<mode>,
neon_vld4qb<mode>, vec_store_lanesxi<mode>, neon_vst4<mode>,
neon_vst4qa<mode>, neon_vst4qb<mode>): Change VQ iterator to VQ2.
(neon_vcreate, neon_vreinterpretv8qi<mode>,
neon_vreinterpretv4hi<mode>, neon_vreinterpretv2si<mode>,
neon_vreinterpretv2sf<mode>, neon_vreinterpretdi<mode>):
Change VDX to VD_RE.
(neon_vld2_lane<mode>, neon_vst2_lane<mode>, neon_vld3_lane<mode>,
neon_vst3_lane<mode>, neon_vld4_lane<mode>, neon_vst4_lane<mode>):
Change VD iterator to VD_LANE, and VMQ iterator to VQ_HS.
* config/arm/arm_neon.h (float16x4x2_t, float16x8x2_t, float16x4x3_t,
float16x8x3_t, float16x4x4_t, float16x8x4_t, vcombine_f16,
vget_high_f16, vget_low_f16, vld1_f16, vld1q_f16, vst1_f16, vst1q_f16,
vst1_lane_f16, vst1q_lane_f16, vld2_f16, vld2q_f16, vld2_lane_f16,
vld2q_lane_f16, vld2_dup_f16, vst2_f16, vst2q_f16, vst2_lane_f16,
vst2q_lane_f16, vld3_f16, vld3q_f16, vld3_lane_f16, vld3q_lane_f16,
vld3_dup_f16, vst3_f16, vst3q_f16, vst3_lane_f16, vst3q_lane_f16,
vld4_f16, vld4q_f16, vld4_lane_f16, vld4q_lane_f16, vld4_dup_f16,
vst4_f16, vst4q_f16, vst4_lane_f16, vst4q_lane_f16): New.
From-SVN: r227541
2015-09-08 20:48:47 +02:00
|
|
|
(V4HF "BLK") (V8HF "BLK")
|
arm.c (arm_print_operand): Use MEM_SIZE to get the size of a '%A' memory reference.
gcc/
* config/arm/arm.c (arm_print_operand): Use MEM_SIZE to get the
size of a '%A' memory reference.
(T_DREG, T_QREG): New neon_builtin_type_bits.
(arm_init_neon_builtins): Assert that the load and store operands
are neon_struct_operands.
(locate_neon_builtin_icode): Provide the neon_builtin_type_bits.
(NEON_ARG_MEMORY): New builtin_arg.
(neon_dereference_pointer): New function.
(arm_expand_neon_args): Add a neon_builtin_type_bits argument.
Handle NEON_ARG_MEMORY.
(arm_expand_neon_builtin): Update after above interface changes.
Use NEON_ARG_MEMORY for loads and stores.
* config/arm/predicates.md (neon_struct_operand): New predicate.
* config/arm/iterators.md (V_two_elem): Tweak formatting.
(V_three_elem): Use BLKmode for accesses that have no associated mode.
(V_four_elem): Tweak formatting.
* config/arm/neon.md (neon_vld1<mode>, neon_vld1_dup<mode>)
(neon_vst1_lane<mode>, neon_vst1<mode>, neon_vld2<mode>)
(neon_vld2_lane<mode>, neon_vld2_dup<mode>, neon_vst2<mode>)
(neon_vst2_lane<mode>, neon_vld3<mode>, neon_vld3_lane<mode>)
(neon_vld3_dup<mode>, neon_vst3<mode>, neon_vst3_lane<mode>)
(neon_vld4<mode>, neon_vld4_lane<mode>, neon_vld4_dup<mode>)
(neon_vst4<mode>): Replace pointer operand with a memory operand.
Use %A in the output template.
(neon_vld3qa<mode>, neon_vld3qb<mode>, neon_vst3qa<mode>)
(neon_vst3qb<mode>, neon_vld4qa<mode>, neon_vld4qb<mode>)
(neon_vst4qa<mode>, neon_vst4qb<mode>): Likewise, but halve
the width of the memory access. Remove post-increment.
* config/arm/neon-testgen.ml: Allow addresses to have an alignment.
gcc/testsuite/
* gcc.target/arm/neon-vld3-1.c: New test.
* gcc.target/arm/neon-vst3-1.c: New test.
* gcc.target/arm/neon/v*.c: Regenerate.
From-SVN: r172314
2011-04-12 14:19:38 +02:00
|
|
|
(V2SI "BLK") (V4SI "BLK")
|
|
|
|
(V2SF "BLK") (V4SF "BLK")
|
|
|
|
(DI "EI") (V2DI "EI")])
|
iterators.md: New file.
2010-08-09 Sofiane Naci <sofiane.naci@arm.com>
* config/arm/iterators.md: New file.
* config/arm/arm.md: Include iterators.md.
(QHSI): Move to new file.
(LTUGEU, cnb, optab, ior_xor): Likewise.
* config/arm/iwmmxt.md (VMMX): Move to new file.
(VSHFT, MMX_char): Likewise.
* config/arm/neon.md (VD): Move to new file.
(VDX, VDI, VQ, VQX, VQI, VQXMOV, VSTRUCT, VTAB, V_TAB_n, VW): Likewise.
(VN, VDQ, VDQW, VDQIW, VCVTF, VCVTI, VMD, VMQ, VMDQ, VMDI): Likewise.
(VMDQI, VX, VE, V64, V32, V_CVTTO, V_elem, V_ext, V_two_elem): Likewise.
(V_three_elem, V_four_elem, V_req, V_widen, V_narrow, V_HALF): Likewise.
(V_half,V_DOUBLE, V_double, V_double_width, V_cmp_result): Likewise.
(V_if_elem, V_s_elem, V_u_elem, V_uf_sclr, V_sz_elem, VD_dup): Likewise.
(V_PAIR, vqh_ops, vqhs_ops, VQH_mnem, VQH_sign, V_suf64): Likewise.
(scalar_mul_constraint,Is_float_mode, Scalar_mul_8_16): Likewise.
(Is_d_reg, V_mode_nunits): Likewise.
* config/arm/vec-common.md (VALL): Move to new file.
(VALLW, VINT, VINTW): Likewise.
From-SVN: r163058
2010-08-10 15:37:25 +02:00
|
|
|
|
|
|
|
;; Similar, for four elements.
|
|
|
|
(define_mode_attr V_four_elem [(V8QI "SI") (V16QI "SI")
|
arm.c (arm_print_operand): Use MEM_SIZE to get the size of a '%A' memory reference.
gcc/
* config/arm/arm.c (arm_print_operand): Use MEM_SIZE to get the
size of a '%A' memory reference.
(T_DREG, T_QREG): New neon_builtin_type_bits.
(arm_init_neon_builtins): Assert that the load and store operands
are neon_struct_operands.
(locate_neon_builtin_icode): Provide the neon_builtin_type_bits.
(NEON_ARG_MEMORY): New builtin_arg.
(neon_dereference_pointer): New function.
(arm_expand_neon_args): Add a neon_builtin_type_bits argument.
Handle NEON_ARG_MEMORY.
(arm_expand_neon_builtin): Update after above interface changes.
Use NEON_ARG_MEMORY for loads and stores.
* config/arm/predicates.md (neon_struct_operand): New predicate.
* config/arm/iterators.md (V_two_elem): Tweak formatting.
(V_three_elem): Use BLKmode for accesses that have no associated mode.
(V_four_elem): Tweak formatting.
* config/arm/neon.md (neon_vld1<mode>, neon_vld1_dup<mode>)
(neon_vst1_lane<mode>, neon_vst1<mode>, neon_vld2<mode>)
(neon_vld2_lane<mode>, neon_vld2_dup<mode>, neon_vst2<mode>)
(neon_vst2_lane<mode>, neon_vld3<mode>, neon_vld3_lane<mode>)
(neon_vld3_dup<mode>, neon_vst3<mode>, neon_vst3_lane<mode>)
(neon_vld4<mode>, neon_vld4_lane<mode>, neon_vld4_dup<mode>)
(neon_vst4<mode>): Replace pointer operand with a memory operand.
Use %A in the output template.
(neon_vld3qa<mode>, neon_vld3qb<mode>, neon_vst3qa<mode>)
(neon_vst3qb<mode>, neon_vld4qa<mode>, neon_vld4qb<mode>)
(neon_vst4qa<mode>, neon_vst4qb<mode>): Likewise, but halve
the width of the memory access. Remove post-increment.
* config/arm/neon-testgen.ml: Allow addresses to have an alignment.
gcc/testsuite/
* gcc.target/arm/neon-vld3-1.c: New test.
* gcc.target/arm/neon-vst3-1.c: New test.
* gcc.target/arm/neon/v*.c: Regenerate.
From-SVN: r172314
2011-04-12 14:19:38 +02:00
|
|
|
(V4HI "V4HI") (V8HI "V4HI")
|
[ARM] Remaining intrinsics
* config/arm/arm-builtins.c (VAR11, VAR12): New.
* config/arm/arm_neon_builtins.def (vcombine, vld2_dup, vld3_dup,
vld4_dup): Add v4hf variant.
(vget_high, vget_low): Add v8hf variant.
(vld1, vst1, vst1_lane, vld2, vld2_lane, vst2, vst2_lane, vld3,
vld3_lane, vst3, vst3_lane, vld4, vld4_lane, vst4, vst4_lane): Add
v4hf and v8hf variants.
* config/arm/iterators.md (VD_LANE, VD_RE, VQ2, VQ_HS): New.
(VDX): Add V4HF.
(V_DOUBLE): Add case for V4HF.
(VQX): Add V8HF.
(V_HALF): Add case for V8HF.
(VDQX): Add V4HF, V8HF.
(V_elem, V_two_elem, V_three_elem, V_four_elem, V_cmp_result,
V_uf_sclr, V_sz_elem, V_mode_nunits, q): Add cases for V4HF & V8HF.
* config/arm/neon.md (vec_set<mode>internal, vec_extract<mode>,
neon_vget_lane<mode>_sext_internal, neon_vget_lane<mode>_zext_internal,
vec_load_lanesoi<mode>, neon_vld2<mode>, vec_store_lanesoi<mode>,
neon_vst2<mode>, vec_load_lanesci<mode>, neon_vld3<mode>,
neon_vld3qa<mode>, neon_vld3qb<mode>, vec_store_lanesci<mode>,
neon_vst3<mode>, neon_vst3qa<mode>, neon_vst3qb<mode>,
vec_load_lanesxi<mode>, neon_vld4<mode>, neon_vld4qa<mode>,
neon_vld4qb<mode>, vec_store_lanesxi<mode>, neon_vst4<mode>,
neon_vst4qa<mode>, neon_vst4qb<mode>): Change VQ iterator to VQ2.
(neon_vcreate, neon_vreinterpretv8qi<mode>,
neon_vreinterpretv4hi<mode>, neon_vreinterpretv2si<mode>,
neon_vreinterpretv2sf<mode>, neon_vreinterpretdi<mode>):
Change VDX to VD_RE.
(neon_vld2_lane<mode>, neon_vst2_lane<mode>, neon_vld3_lane<mode>,
neon_vst3_lane<mode>, neon_vld4_lane<mode>, neon_vst4_lane<mode>):
Change VD iterator to VD_LANE, and VMQ iterator to VQ_HS.
* config/arm/arm_neon.h (float16x4x2_t, float16x8x2_t, float16x4x3_t,
float16x8x3_t, float16x4x4_t, float16x8x4_t, vcombine_f16,
vget_high_f16, vget_low_f16, vld1_f16, vld1q_f16, vst1_f16, vst1q_f16,
vst1_lane_f16, vst1q_lane_f16, vld2_f16, vld2q_f16, vld2_lane_f16,
vld2q_lane_f16, vld2_dup_f16, vst2_f16, vst2q_f16, vst2_lane_f16,
vst2q_lane_f16, vld3_f16, vld3q_f16, vld3_lane_f16, vld3q_lane_f16,
vld3_dup_f16, vst3_f16, vst3q_f16, vst3_lane_f16, vst3q_lane_f16,
vld4_f16, vld4q_f16, vld4_lane_f16, vld4q_lane_f16, vld4_dup_f16,
vst4_f16, vst4q_f16, vst4_lane_f16, vst4q_lane_f16): New.
From-SVN: r227541
2015-09-08 20:48:47 +02:00
|
|
|
(V4HF "V4HF") (V8HF "V4HF")
|
iterators.md: New file.
2010-08-09 Sofiane Naci <sofiane.naci@arm.com>
* config/arm/iterators.md: New file.
* config/arm/arm.md: Include iterators.md.
(QHSI): Move to new file.
(LTUGEU, cnb, optab, ior_xor): Likewise.
* config/arm/iwmmxt.md (VMMX): Move to new file.
(VSHFT, MMX_char): Likewise.
* config/arm/neon.md (VD): Move to new file.
(VDX, VDI, VQ, VQX, VQI, VQXMOV, VSTRUCT, VTAB, V_TAB_n, VW): Likewise.
(VN, VDQ, VDQW, VDQIW, VCVTF, VCVTI, VMD, VMQ, VMDQ, VMDI): Likewise.
(VMDQI, VX, VE, V64, V32, V_CVTTO, V_elem, V_ext, V_two_elem): Likewise.
(V_three_elem, V_four_elem, V_req, V_widen, V_narrow, V_HALF): Likewise.
(V_half,V_DOUBLE, V_double, V_double_width, V_cmp_result): Likewise.
(V_if_elem, V_s_elem, V_u_elem, V_uf_sclr, V_sz_elem, VD_dup): Likewise.
(V_PAIR, vqh_ops, vqhs_ops, VQH_mnem, VQH_sign, V_suf64): Likewise.
(scalar_mul_constraint,Is_float_mode, Scalar_mul_8_16): Likewise.
(Is_d_reg, V_mode_nunits): Likewise.
* config/arm/vec-common.md (VALL): Move to new file.
(VALLW, VINT, VINTW): Likewise.
From-SVN: r163058
2010-08-10 15:37:25 +02:00
|
|
|
(V2SI "V4SI") (V4SI "V4SI")
|
|
|
|
(V2SF "V4SF") (V4SF "V4SF")
|
|
|
|
(DI "OI") (V2DI "OI")])
|
|
|
|
|
|
|
|
;; Register width from element mode
|
|
|
|
(define_mode_attr V_reg [(V8QI "P") (V16QI "q")
|
2016-09-23 11:54:44 +02:00
|
|
|
(V4HI "P") (V8HI "q")
|
|
|
|
(V4HF "P") (V8HF "q")
|
|
|
|
(V2SI "P") (V4SI "q")
|
|
|
|
(V2SF "P") (V4SF "q")
|
|
|
|
(DI "P") (V2DI "q")
|
|
|
|
(SF "") (DF "P")
|
|
|
|
(HF "")])
|
iterators.md: New file.
2010-08-09 Sofiane Naci <sofiane.naci@arm.com>
* config/arm/iterators.md: New file.
* config/arm/arm.md: Include iterators.md.
(QHSI): Move to new file.
(LTUGEU, cnb, optab, ior_xor): Likewise.
* config/arm/iwmmxt.md (VMMX): Move to new file.
(VSHFT, MMX_char): Likewise.
* config/arm/neon.md (VD): Move to new file.
(VDX, VDI, VQ, VQX, VQI, VQXMOV, VSTRUCT, VTAB, V_TAB_n, VW): Likewise.
(VN, VDQ, VDQW, VDQIW, VCVTF, VCVTI, VMD, VMQ, VMDQ, VMDI): Likewise.
(VMDQI, VX, VE, V64, V32, V_CVTTO, V_elem, V_ext, V_two_elem): Likewise.
(V_three_elem, V_four_elem, V_req, V_widen, V_narrow, V_HALF): Likewise.
(V_half,V_DOUBLE, V_double, V_double_width, V_cmp_result): Likewise.
(V_if_elem, V_s_elem, V_u_elem, V_uf_sclr, V_sz_elem, VD_dup): Likewise.
(V_PAIR, vqh_ops, vqhs_ops, VQH_mnem, VQH_sign, V_suf64): Likewise.
(scalar_mul_constraint,Is_float_mode, Scalar_mul_8_16): Likewise.
(Is_d_reg, V_mode_nunits): Likewise.
* config/arm/vec-common.md (VALL): Move to new file.
(VALLW, VINT, VINTW): Likewise.
From-SVN: r163058
2010-08-10 15:37:25 +02:00
|
|
|
|
|
|
|
;; Wider modes with the same number of elements.
|
|
|
|
(define_mode_attr V_widen [(V8QI "V8HI") (V4HI "V4SI") (V2SI "V2DI")])
|
|
|
|
|
|
|
|
;; Narrower modes with the same number of elements.
|
|
|
|
(define_mode_attr V_narrow [(V8HI "V8QI") (V4SI "V4HI") (V2DI "V2SI")])
|
|
|
|
|
2010-09-15 13:18:07 +02:00
|
|
|
;; Narrower modes with double the number of elements.
|
|
|
|
(define_mode_attr V_narrow_pack [(V4SI "V8HI") (V8HI "V16QI") (V2DI "V4SI")
|
|
|
|
(V4HI "V8QI") (V2SI "V4HI") (DI "V2SI")])
|
|
|
|
|
iterators.md: New file.
2010-08-09 Sofiane Naci <sofiane.naci@arm.com>
* config/arm/iterators.md: New file.
* config/arm/arm.md: Include iterators.md.
(QHSI): Move to new file.
(LTUGEU, cnb, optab, ior_xor): Likewise.
* config/arm/iwmmxt.md (VMMX): Move to new file.
(VSHFT, MMX_char): Likewise.
* config/arm/neon.md (VD): Move to new file.
(VDX, VDI, VQ, VQX, VQI, VQXMOV, VSTRUCT, VTAB, V_TAB_n, VW): Likewise.
(VN, VDQ, VDQW, VDQIW, VCVTF, VCVTI, VMD, VMQ, VMDQ, VMDI): Likewise.
(VMDQI, VX, VE, V64, V32, V_CVTTO, V_elem, V_ext, V_two_elem): Likewise.
(V_three_elem, V_four_elem, V_req, V_widen, V_narrow, V_HALF): Likewise.
(V_half,V_DOUBLE, V_double, V_double_width, V_cmp_result): Likewise.
(V_if_elem, V_s_elem, V_u_elem, V_uf_sclr, V_sz_elem, VD_dup): Likewise.
(V_PAIR, vqh_ops, vqhs_ops, VQH_mnem, VQH_sign, V_suf64): Likewise.
(scalar_mul_constraint,Is_float_mode, Scalar_mul_8_16): Likewise.
(Is_d_reg, V_mode_nunits): Likewise.
* config/arm/vec-common.md (VALL): Move to new file.
(VALLW, VINT, VINTW): Likewise.
From-SVN: r163058
2010-08-10 15:37:25 +02:00
|
|
|
;; Modes with half the number of equal-sized elements.
|
|
|
|
(define_mode_attr V_HALF [(V16QI "V8QI") (V8HI "V4HI")
|
[ARM] Remaining intrinsics
* config/arm/arm-builtins.c (VAR11, VAR12): New.
* config/arm/arm_neon_builtins.def (vcombine, vld2_dup, vld3_dup,
vld4_dup): Add v4hf variant.
(vget_high, vget_low): Add v8hf variant.
(vld1, vst1, vst1_lane, vld2, vld2_lane, vst2, vst2_lane, vld3,
vld3_lane, vst3, vst3_lane, vld4, vld4_lane, vst4, vst4_lane): Add
v4hf and v8hf variants.
* config/arm/iterators.md (VD_LANE, VD_RE, VQ2, VQ_HS): New.
(VDX): Add V4HF.
(V_DOUBLE): Add case for V4HF.
(VQX): Add V8HF.
(V_HALF): Add case for V8HF.
(VDQX): Add V4HF, V8HF.
(V_elem, V_two_elem, V_three_elem, V_four_elem, V_cmp_result,
V_uf_sclr, V_sz_elem, V_mode_nunits, q): Add cases for V4HF & V8HF.
* config/arm/neon.md (vec_set<mode>internal, vec_extract<mode>,
neon_vget_lane<mode>_sext_internal, neon_vget_lane<mode>_zext_internal,
vec_load_lanesoi<mode>, neon_vld2<mode>, vec_store_lanesoi<mode>,
neon_vst2<mode>, vec_load_lanesci<mode>, neon_vld3<mode>,
neon_vld3qa<mode>, neon_vld3qb<mode>, vec_store_lanesci<mode>,
neon_vst3<mode>, neon_vst3qa<mode>, neon_vst3qb<mode>,
vec_load_lanesxi<mode>, neon_vld4<mode>, neon_vld4qa<mode>,
neon_vld4qb<mode>, vec_store_lanesxi<mode>, neon_vst4<mode>,
neon_vst4qa<mode>, neon_vst4qb<mode>): Change VQ iterator to VQ2.
(neon_vcreate, neon_vreinterpretv8qi<mode>,
neon_vreinterpretv4hi<mode>, neon_vreinterpretv2si<mode>,
neon_vreinterpretv2sf<mode>, neon_vreinterpretdi<mode>):
Change VDX to VD_RE.
(neon_vld2_lane<mode>, neon_vst2_lane<mode>, neon_vld3_lane<mode>,
neon_vst3_lane<mode>, neon_vld4_lane<mode>, neon_vst4_lane<mode>):
Change VD iterator to VD_LANE, and VMQ iterator to VQ_HS.
* config/arm/arm_neon.h (float16x4x2_t, float16x8x2_t, float16x4x3_t,
float16x8x3_t, float16x4x4_t, float16x8x4_t, vcombine_f16,
vget_high_f16, vget_low_f16, vld1_f16, vld1q_f16, vst1_f16, vst1q_f16,
vst1_lane_f16, vst1q_lane_f16, vld2_f16, vld2q_f16, vld2_lane_f16,
vld2q_lane_f16, vld2_dup_f16, vst2_f16, vst2q_f16, vst2_lane_f16,
vst2q_lane_f16, vld3_f16, vld3q_f16, vld3_lane_f16, vld3q_lane_f16,
vld3_dup_f16, vst3_f16, vst3q_f16, vst3_lane_f16, vst3q_lane_f16,
vld4_f16, vld4q_f16, vld4_lane_f16, vld4q_lane_f16, vld4_dup_f16,
vst4_f16, vst4q_f16, vst4_lane_f16, vst4q_lane_f16): New.
From-SVN: r227541
2015-09-08 20:48:47 +02:00
|
|
|
(V8HF "V4HF") (V4SI "V2SI")
|
|
|
|
(V4SF "V2SF") (V2DF "DF")
|
2016-09-23 11:54:44 +02:00
|
|
|
(V2DI "DI") (V4HF "HF")])
|
iterators.md: New file.
2010-08-09 Sofiane Naci <sofiane.naci@arm.com>
* config/arm/iterators.md: New file.
* config/arm/arm.md: Include iterators.md.
(QHSI): Move to new file.
(LTUGEU, cnb, optab, ior_xor): Likewise.
* config/arm/iwmmxt.md (VMMX): Move to new file.
(VSHFT, MMX_char): Likewise.
* config/arm/neon.md (VD): Move to new file.
(VDX, VDI, VQ, VQX, VQI, VQXMOV, VSTRUCT, VTAB, V_TAB_n, VW): Likewise.
(VN, VDQ, VDQW, VDQIW, VCVTF, VCVTI, VMD, VMQ, VMDQ, VMDI): Likewise.
(VMDQI, VX, VE, V64, V32, V_CVTTO, V_elem, V_ext, V_two_elem): Likewise.
(V_three_elem, V_four_elem, V_req, V_widen, V_narrow, V_HALF): Likewise.
(V_half,V_DOUBLE, V_double, V_double_width, V_cmp_result): Likewise.
(V_if_elem, V_s_elem, V_u_elem, V_uf_sclr, V_sz_elem, VD_dup): Likewise.
(V_PAIR, vqh_ops, vqhs_ops, VQH_mnem, VQH_sign, V_suf64): Likewise.
(scalar_mul_constraint,Is_float_mode, Scalar_mul_8_16): Likewise.
(Is_d_reg, V_mode_nunits): Likewise.
* config/arm/vec-common.md (VALL): Move to new file.
(VALLW, VINT, VINTW): Likewise.
From-SVN: r163058
2010-08-10 15:37:25 +02:00
|
|
|
|
|
|
|
;; Same, but lower-case.
|
|
|
|
(define_mode_attr V_half [(V16QI "v8qi") (V8HI "v4hi")
|
|
|
|
(V4SI "v2si") (V4SF "v2sf")
|
|
|
|
(V2DI "di")])
|
|
|
|
|
|
|
|
;; Modes with twice the number of equal-sized elements.
|
|
|
|
(define_mode_attr V_DOUBLE [(V8QI "V16QI") (V4HI "V8HI")
|
[ARM] Remaining intrinsics
* config/arm/arm-builtins.c (VAR11, VAR12): New.
* config/arm/arm_neon_builtins.def (vcombine, vld2_dup, vld3_dup,
vld4_dup): Add v4hf variant.
(vget_high, vget_low): Add v8hf variant.
(vld1, vst1, vst1_lane, vld2, vld2_lane, vst2, vst2_lane, vld3,
vld3_lane, vst3, vst3_lane, vld4, vld4_lane, vst4, vst4_lane): Add
v4hf and v8hf variants.
* config/arm/iterators.md (VD_LANE, VD_RE, VQ2, VQ_HS): New.
(VDX): Add V4HF.
(V_DOUBLE): Add case for V4HF.
(VQX): Add V8HF.
(V_HALF): Add case for V8HF.
(VDQX): Add V4HF, V8HF.
(V_elem, V_two_elem, V_three_elem, V_four_elem, V_cmp_result,
V_uf_sclr, V_sz_elem, V_mode_nunits, q): Add cases for V4HF & V8HF.
* config/arm/neon.md (vec_set<mode>internal, vec_extract<mode>,
neon_vget_lane<mode>_sext_internal, neon_vget_lane<mode>_zext_internal,
vec_load_lanesoi<mode>, neon_vld2<mode>, vec_store_lanesoi<mode>,
neon_vst2<mode>, vec_load_lanesci<mode>, neon_vld3<mode>,
neon_vld3qa<mode>, neon_vld3qb<mode>, vec_store_lanesci<mode>,
neon_vst3<mode>, neon_vst3qa<mode>, neon_vst3qb<mode>,
vec_load_lanesxi<mode>, neon_vld4<mode>, neon_vld4qa<mode>,
neon_vld4qb<mode>, vec_store_lanesxi<mode>, neon_vst4<mode>,
neon_vst4qa<mode>, neon_vst4qb<mode>): Change VQ iterator to VQ2.
(neon_vcreate, neon_vreinterpretv8qi<mode>,
neon_vreinterpretv4hi<mode>, neon_vreinterpretv2si<mode>,
neon_vreinterpretv2sf<mode>, neon_vreinterpretdi<mode>):
Change VDX to VD_RE.
(neon_vld2_lane<mode>, neon_vst2_lane<mode>, neon_vld3_lane<mode>,
neon_vst3_lane<mode>, neon_vld4_lane<mode>, neon_vst4_lane<mode>):
Change VD iterator to VD_LANE, and VMQ iterator to VQ_HS.
* config/arm/arm_neon.h (float16x4x2_t, float16x8x2_t, float16x4x3_t,
float16x8x3_t, float16x4x4_t, float16x8x4_t, vcombine_f16,
vget_high_f16, vget_low_f16, vld1_f16, vld1q_f16, vst1_f16, vst1q_f16,
vst1_lane_f16, vst1q_lane_f16, vld2_f16, vld2q_f16, vld2_lane_f16,
vld2q_lane_f16, vld2_dup_f16, vst2_f16, vst2q_f16, vst2_lane_f16,
vst2q_lane_f16, vld3_f16, vld3q_f16, vld3_lane_f16, vld3q_lane_f16,
vld3_dup_f16, vst3_f16, vst3q_f16, vst3_lane_f16, vst3q_lane_f16,
vld4_f16, vld4q_f16, vld4_lane_f16, vld4q_lane_f16, vld4_dup_f16,
vst4_f16, vst4q_f16, vst4_lane_f16, vst4q_lane_f16): New.
From-SVN: r227541
2015-09-08 20:48:47 +02:00
|
|
|
(V2SI "V4SI") (V4HF "V8HF")
|
|
|
|
(V2SF "V4SF") (DF "V2DF")
|
|
|
|
(DI "V2DI")])
|
iterators.md: New file.
2010-08-09 Sofiane Naci <sofiane.naci@arm.com>
* config/arm/iterators.md: New file.
* config/arm/arm.md: Include iterators.md.
(QHSI): Move to new file.
(LTUGEU, cnb, optab, ior_xor): Likewise.
* config/arm/iwmmxt.md (VMMX): Move to new file.
(VSHFT, MMX_char): Likewise.
* config/arm/neon.md (VD): Move to new file.
(VDX, VDI, VQ, VQX, VQI, VQXMOV, VSTRUCT, VTAB, V_TAB_n, VW): Likewise.
(VN, VDQ, VDQW, VDQIW, VCVTF, VCVTI, VMD, VMQ, VMDQ, VMDI): Likewise.
(VMDQI, VX, VE, V64, V32, V_CVTTO, V_elem, V_ext, V_two_elem): Likewise.
(V_three_elem, V_four_elem, V_req, V_widen, V_narrow, V_HALF): Likewise.
(V_half,V_DOUBLE, V_double, V_double_width, V_cmp_result): Likewise.
(V_if_elem, V_s_elem, V_u_elem, V_uf_sclr, V_sz_elem, VD_dup): Likewise.
(V_PAIR, vqh_ops, vqhs_ops, VQH_mnem, VQH_sign, V_suf64): Likewise.
(scalar_mul_constraint,Is_float_mode, Scalar_mul_8_16): Likewise.
(Is_d_reg, V_mode_nunits): Likewise.
* config/arm/vec-common.md (VALL): Move to new file.
(VALLW, VINT, VINTW): Likewise.
From-SVN: r163058
2010-08-10 15:37:25 +02:00
|
|
|
|
|
|
|
;; Same, but lower-case.
|
|
|
|
(define_mode_attr V_double [(V8QI "v16qi") (V4HI "v8hi")
|
|
|
|
(V2SI "v4si") (V2SF "v4sf")
|
|
|
|
(DI "v2di")])
|
|
|
|
|
|
|
|
;; Modes with double-width elements.
|
|
|
|
(define_mode_attr V_double_width [(V8QI "V4HI") (V16QI "V8HI")
|
|
|
|
(V4HI "V2SI") (V8HI "V4SI")
|
|
|
|
(V2SI "DI") (V4SI "V2DI")])
|
|
|
|
|
|
|
|
;; Double-sized modes with the same element size.
|
|
|
|
;; Used for neon_vdup_lane, where the second operand is double-sized
|
|
|
|
;; even when the first one is quad.
|
|
|
|
(define_mode_attr V_double_vector_mode [(V16QI "V8QI") (V8HI "V4HI")
|
2016-09-23 11:23:01 +02:00
|
|
|
(V4SI "V2SI") (V4SF "V2SF")
|
|
|
|
(V8QI "V8QI") (V4HI "V4HI")
|
|
|
|
(V2SI "V2SI") (V2SF "V2SF")
|
|
|
|
(V8HF "V4HF") (V4HF "V4HF")])
|
iterators.md: New file.
2010-08-09 Sofiane Naci <sofiane.naci@arm.com>
* config/arm/iterators.md: New file.
* config/arm/arm.md: Include iterators.md.
(QHSI): Move to new file.
(LTUGEU, cnb, optab, ior_xor): Likewise.
* config/arm/iwmmxt.md (VMMX): Move to new file.
(VSHFT, MMX_char): Likewise.
* config/arm/neon.md (VD): Move to new file.
(VDX, VDI, VQ, VQX, VQI, VQXMOV, VSTRUCT, VTAB, V_TAB_n, VW): Likewise.
(VN, VDQ, VDQW, VDQIW, VCVTF, VCVTI, VMD, VMQ, VMDQ, VMDI): Likewise.
(VMDQI, VX, VE, V64, V32, V_CVTTO, V_elem, V_ext, V_two_elem): Likewise.
(V_three_elem, V_four_elem, V_req, V_widen, V_narrow, V_HALF): Likewise.
(V_half,V_DOUBLE, V_double, V_double_width, V_cmp_result): Likewise.
(V_if_elem, V_s_elem, V_u_elem, V_uf_sclr, V_sz_elem, VD_dup): Likewise.
(V_PAIR, vqh_ops, vqhs_ops, VQH_mnem, VQH_sign, V_suf64): Likewise.
(scalar_mul_constraint,Is_float_mode, Scalar_mul_8_16): Likewise.
(Is_d_reg, V_mode_nunits): Likewise.
* config/arm/vec-common.md (VALL): Move to new file.
(VALLW, VINT, VINTW): Likewise.
From-SVN: r163058
2010-08-10 15:37:25 +02:00
|
|
|
|
|
|
|
;; Mode of result of comparison operations (and bit-select operand 1).
|
|
|
|
(define_mode_attr V_cmp_result [(V8QI "V8QI") (V16QI "V16QI")
|
[ARM] Remaining intrinsics
* config/arm/arm-builtins.c (VAR11, VAR12): New.
* config/arm/arm_neon_builtins.def (vcombine, vld2_dup, vld3_dup,
vld4_dup): Add v4hf variant.
(vget_high, vget_low): Add v8hf variant.
(vld1, vst1, vst1_lane, vld2, vld2_lane, vst2, vst2_lane, vld3,
vld3_lane, vst3, vst3_lane, vld4, vld4_lane, vst4, vst4_lane): Add
v4hf and v8hf variants.
* config/arm/iterators.md (VD_LANE, VD_RE, VQ2, VQ_HS): New.
(VDX): Add V4HF.
(V_DOUBLE): Add case for V4HF.
(VQX): Add V8HF.
(V_HALF): Add case for V8HF.
(VDQX): Add V4HF, V8HF.
(V_elem, V_two_elem, V_three_elem, V_four_elem, V_cmp_result,
V_uf_sclr, V_sz_elem, V_mode_nunits, q): Add cases for V4HF & V8HF.
* config/arm/neon.md (vec_set<mode>internal, vec_extract<mode>,
neon_vget_lane<mode>_sext_internal, neon_vget_lane<mode>_zext_internal,
vec_load_lanesoi<mode>, neon_vld2<mode>, vec_store_lanesoi<mode>,
neon_vst2<mode>, vec_load_lanesci<mode>, neon_vld3<mode>,
neon_vld3qa<mode>, neon_vld3qb<mode>, vec_store_lanesci<mode>,
neon_vst3<mode>, neon_vst3qa<mode>, neon_vst3qb<mode>,
vec_load_lanesxi<mode>, neon_vld4<mode>, neon_vld4qa<mode>,
neon_vld4qb<mode>, vec_store_lanesxi<mode>, neon_vst4<mode>,
neon_vst4qa<mode>, neon_vst4qb<mode>): Change VQ iterator to VQ2.
(neon_vcreate, neon_vreinterpretv8qi<mode>,
neon_vreinterpretv4hi<mode>, neon_vreinterpretv2si<mode>,
neon_vreinterpretv2sf<mode>, neon_vreinterpretdi<mode>):
Change VDX to VD_RE.
(neon_vld2_lane<mode>, neon_vst2_lane<mode>, neon_vld3_lane<mode>,
neon_vst3_lane<mode>, neon_vld4_lane<mode>, neon_vst4_lane<mode>):
Change VD iterator to VD_LANE, and VMQ iterator to VQ_HS.
* config/arm/arm_neon.h (float16x4x2_t, float16x8x2_t, float16x4x3_t,
float16x8x3_t, float16x4x4_t, float16x8x4_t, vcombine_f16,
vget_high_f16, vget_low_f16, vld1_f16, vld1q_f16, vst1_f16, vst1q_f16,
vst1_lane_f16, vst1q_lane_f16, vld2_f16, vld2q_f16, vld2_lane_f16,
vld2q_lane_f16, vld2_dup_f16, vst2_f16, vst2q_f16, vst2_lane_f16,
vst2q_lane_f16, vld3_f16, vld3q_f16, vld3_lane_f16, vld3q_lane_f16,
vld3_dup_f16, vst3_f16, vst3q_f16, vst3_lane_f16, vst3q_lane_f16,
vld4_f16, vld4q_f16, vld4_lane_f16, vld4q_lane_f16, vld4_dup_f16,
vst4_f16, vst4q_f16, vst4_lane_f16, vst4q_lane_f16): New.
From-SVN: r227541
2015-09-08 20:48:47 +02:00
|
|
|
(V4HI "V4HI") (V8HI "V8HI")
|
iterators.md: New file.
2010-08-09 Sofiane Naci <sofiane.naci@arm.com>
* config/arm/iterators.md: New file.
* config/arm/arm.md: Include iterators.md.
(QHSI): Move to new file.
(LTUGEU, cnb, optab, ior_xor): Likewise.
* config/arm/iwmmxt.md (VMMX): Move to new file.
(VSHFT, MMX_char): Likewise.
* config/arm/neon.md (VD): Move to new file.
(VDX, VDI, VQ, VQX, VQI, VQXMOV, VSTRUCT, VTAB, V_TAB_n, VW): Likewise.
(VN, VDQ, VDQW, VDQIW, VCVTF, VCVTI, VMD, VMQ, VMDQ, VMDI): Likewise.
(VMDQI, VX, VE, V64, V32, V_CVTTO, V_elem, V_ext, V_two_elem): Likewise.
(V_three_elem, V_four_elem, V_req, V_widen, V_narrow, V_HALF): Likewise.
(V_half,V_DOUBLE, V_double, V_double_width, V_cmp_result): Likewise.
(V_if_elem, V_s_elem, V_u_elem, V_uf_sclr, V_sz_elem, VD_dup): Likewise.
(V_PAIR, vqh_ops, vqhs_ops, VQH_mnem, VQH_sign, V_suf64): Likewise.
(scalar_mul_constraint,Is_float_mode, Scalar_mul_8_16): Likewise.
(Is_d_reg, V_mode_nunits): Likewise.
* config/arm/vec-common.md (VALL): Move to new file.
(VALLW, VINT, VINTW): Likewise.
From-SVN: r163058
2010-08-10 15:37:25 +02:00
|
|
|
(V2SI "V2SI") (V4SI "V4SI")
|
[ARM] Remaining intrinsics
* config/arm/arm-builtins.c (VAR11, VAR12): New.
* config/arm/arm_neon_builtins.def (vcombine, vld2_dup, vld3_dup,
vld4_dup): Add v4hf variant.
(vget_high, vget_low): Add v8hf variant.
(vld1, vst1, vst1_lane, vld2, vld2_lane, vst2, vst2_lane, vld3,
vld3_lane, vst3, vst3_lane, vld4, vld4_lane, vst4, vst4_lane): Add
v4hf and v8hf variants.
* config/arm/iterators.md (VD_LANE, VD_RE, VQ2, VQ_HS): New.
(VDX): Add V4HF.
(V_DOUBLE): Add case for V4HF.
(VQX): Add V8HF.
(V_HALF): Add case for V8HF.
(VDQX): Add V4HF, V8HF.
(V_elem, V_two_elem, V_three_elem, V_four_elem, V_cmp_result,
V_uf_sclr, V_sz_elem, V_mode_nunits, q): Add cases for V4HF & V8HF.
* config/arm/neon.md (vec_set<mode>internal, vec_extract<mode>,
neon_vget_lane<mode>_sext_internal, neon_vget_lane<mode>_zext_internal,
vec_load_lanesoi<mode>, neon_vld2<mode>, vec_store_lanesoi<mode>,
neon_vst2<mode>, vec_load_lanesci<mode>, neon_vld3<mode>,
neon_vld3qa<mode>, neon_vld3qb<mode>, vec_store_lanesci<mode>,
neon_vst3<mode>, neon_vst3qa<mode>, neon_vst3qb<mode>,
vec_load_lanesxi<mode>, neon_vld4<mode>, neon_vld4qa<mode>,
neon_vld4qb<mode>, vec_store_lanesxi<mode>, neon_vst4<mode>,
neon_vst4qa<mode>, neon_vst4qb<mode>): Change VQ iterator to VQ2.
(neon_vcreate, neon_vreinterpretv8qi<mode>,
neon_vreinterpretv4hi<mode>, neon_vreinterpretv2si<mode>,
neon_vreinterpretv2sf<mode>, neon_vreinterpretdi<mode>):
Change VDX to VD_RE.
(neon_vld2_lane<mode>, neon_vst2_lane<mode>, neon_vld3_lane<mode>,
neon_vst3_lane<mode>, neon_vld4_lane<mode>, neon_vst4_lane<mode>):
Change VD iterator to VD_LANE, and VMQ iterator to VQ_HS.
* config/arm/arm_neon.h (float16x4x2_t, float16x8x2_t, float16x4x3_t,
float16x8x3_t, float16x4x4_t, float16x8x4_t, vcombine_f16,
vget_high_f16, vget_low_f16, vld1_f16, vld1q_f16, vst1_f16, vst1q_f16,
vst1_lane_f16, vst1q_lane_f16, vld2_f16, vld2q_f16, vld2_lane_f16,
vld2q_lane_f16, vld2_dup_f16, vst2_f16, vst2q_f16, vst2_lane_f16,
vst2q_lane_f16, vld3_f16, vld3q_f16, vld3_lane_f16, vld3q_lane_f16,
vld3_dup_f16, vst3_f16, vst3q_f16, vst3_lane_f16, vst3q_lane_f16,
vld4_f16, vld4q_f16, vld4_lane_f16, vld4q_lane_f16, vld4_dup_f16,
vst4_f16, vst4q_f16, vst4_lane_f16, vst4q_lane_f16): New.
From-SVN: r227541
2015-09-08 20:48:47 +02:00
|
|
|
(V4HF "V4HI") (V8HF "V8HI")
|
iterators.md: New file.
2010-08-09 Sofiane Naci <sofiane.naci@arm.com>
* config/arm/iterators.md: New file.
* config/arm/arm.md: Include iterators.md.
(QHSI): Move to new file.
(LTUGEU, cnb, optab, ior_xor): Likewise.
* config/arm/iwmmxt.md (VMMX): Move to new file.
(VSHFT, MMX_char): Likewise.
* config/arm/neon.md (VD): Move to new file.
(VDX, VDI, VQ, VQX, VQI, VQXMOV, VSTRUCT, VTAB, V_TAB_n, VW): Likewise.
(VN, VDQ, VDQW, VDQIW, VCVTF, VCVTI, VMD, VMQ, VMDQ, VMDI): Likewise.
(VMDQI, VX, VE, V64, V32, V_CVTTO, V_elem, V_ext, V_two_elem): Likewise.
(V_three_elem, V_four_elem, V_req, V_widen, V_narrow, V_HALF): Likewise.
(V_half,V_DOUBLE, V_double, V_double_width, V_cmp_result): Likewise.
(V_if_elem, V_s_elem, V_u_elem, V_uf_sclr, V_sz_elem, VD_dup): Likewise.
(V_PAIR, vqh_ops, vqhs_ops, VQH_mnem, VQH_sign, V_suf64): Likewise.
(scalar_mul_constraint,Is_float_mode, Scalar_mul_8_16): Likewise.
(Is_d_reg, V_mode_nunits): Likewise.
* config/arm/vec-common.md (VALL): Move to new file.
(VALLW, VINT, VINTW): Likewise.
From-SVN: r163058
2010-08-10 15:37:25 +02:00
|
|
|
(V2SF "V2SI") (V4SF "V4SI")
|
|
|
|
(DI "DI") (V2DI "V2DI")])
|
|
|
|
|
2013-03-25 14:48:06 +01:00
|
|
|
(define_mode_attr v_cmp_result [(V8QI "v8qi") (V16QI "v16qi")
|
|
|
|
(V4HI "v4hi") (V8HI "v8hi")
|
|
|
|
(V2SI "v2si") (V4SI "v4si")
|
|
|
|
(DI "di") (V2DI "v2di")
|
|
|
|
(V2SF "v2si") (V4SF "v4si")])
|
|
|
|
|
iterators.md: New file.
2010-08-09 Sofiane Naci <sofiane.naci@arm.com>
* config/arm/iterators.md: New file.
* config/arm/arm.md: Include iterators.md.
(QHSI): Move to new file.
(LTUGEU, cnb, optab, ior_xor): Likewise.
* config/arm/iwmmxt.md (VMMX): Move to new file.
(VSHFT, MMX_char): Likewise.
* config/arm/neon.md (VD): Move to new file.
(VDX, VDI, VQ, VQX, VQI, VQXMOV, VSTRUCT, VTAB, V_TAB_n, VW): Likewise.
(VN, VDQ, VDQW, VDQIW, VCVTF, VCVTI, VMD, VMQ, VMDQ, VMDI): Likewise.
(VMDQI, VX, VE, V64, V32, V_CVTTO, V_elem, V_ext, V_two_elem): Likewise.
(V_three_elem, V_four_elem, V_req, V_widen, V_narrow, V_HALF): Likewise.
(V_half,V_DOUBLE, V_double, V_double_width, V_cmp_result): Likewise.
(V_if_elem, V_s_elem, V_u_elem, V_uf_sclr, V_sz_elem, VD_dup): Likewise.
(V_PAIR, vqh_ops, vqhs_ops, VQH_mnem, VQH_sign, V_suf64): Likewise.
(scalar_mul_constraint,Is_float_mode, Scalar_mul_8_16): Likewise.
(Is_d_reg, V_mode_nunits): Likewise.
* config/arm/vec-common.md (VALL): Move to new file.
(VALLW, VINT, VINTW): Likewise.
From-SVN: r163058
2010-08-10 15:37:25 +02:00
|
|
|
;; Get element type from double-width mode, for operations where we
|
|
|
|
;; don't care about signedness.
|
|
|
|
(define_mode_attr V_if_elem [(V8QI "i8") (V16QI "i8")
|
2016-09-23 11:54:44 +02:00
|
|
|
(V4HI "i16") (V8HI "i16")
|
|
|
|
(V2SI "i32") (V4SI "i32")
|
|
|
|
(DI "i64") (V2DI "i64")
|
|
|
|
(V2SF "f32") (V4SF "f32")
|
|
|
|
(SF "f32") (DF "f64")
|
|
|
|
(HF "f16") (V4HF "f16")
|
|
|
|
(V8HF "f16")])
|
iterators.md: New file.
2010-08-09 Sofiane Naci <sofiane.naci@arm.com>
* config/arm/iterators.md: New file.
* config/arm/arm.md: Include iterators.md.
(QHSI): Move to new file.
(LTUGEU, cnb, optab, ior_xor): Likewise.
* config/arm/iwmmxt.md (VMMX): Move to new file.
(VSHFT, MMX_char): Likewise.
* config/arm/neon.md (VD): Move to new file.
(VDX, VDI, VQ, VQX, VQI, VQXMOV, VSTRUCT, VTAB, V_TAB_n, VW): Likewise.
(VN, VDQ, VDQW, VDQIW, VCVTF, VCVTI, VMD, VMQ, VMDQ, VMDI): Likewise.
(VMDQI, VX, VE, V64, V32, V_CVTTO, V_elem, V_ext, V_two_elem): Likewise.
(V_three_elem, V_four_elem, V_req, V_widen, V_narrow, V_HALF): Likewise.
(V_half,V_DOUBLE, V_double, V_double_width, V_cmp_result): Likewise.
(V_if_elem, V_s_elem, V_u_elem, V_uf_sclr, V_sz_elem, VD_dup): Likewise.
(V_PAIR, vqh_ops, vqhs_ops, VQH_mnem, VQH_sign, V_suf64): Likewise.
(scalar_mul_constraint,Is_float_mode, Scalar_mul_8_16): Likewise.
(Is_d_reg, V_mode_nunits): Likewise.
* config/arm/vec-common.md (VALL): Move to new file.
(VALLW, VINT, VINTW): Likewise.
From-SVN: r163058
2010-08-10 15:37:25 +02:00
|
|
|
|
|
|
|
;; Same, but for operations which work on signed values.
|
|
|
|
(define_mode_attr V_s_elem [(V8QI "s8") (V16QI "s8")
|
2016-09-23 11:54:44 +02:00
|
|
|
(V4HI "s16") (V8HI "s16")
|
|
|
|
(V2SI "s32") (V4SI "s32")
|
|
|
|
(DI "s64") (V2DI "s64")
|
|
|
|
(V2SF "f32") (V4SF "f32")
|
|
|
|
(HF "f16") (V4HF "f16")
|
|
|
|
(V8HF "f16")])
|
iterators.md: New file.
2010-08-09 Sofiane Naci <sofiane.naci@arm.com>
* config/arm/iterators.md: New file.
* config/arm/arm.md: Include iterators.md.
(QHSI): Move to new file.
(LTUGEU, cnb, optab, ior_xor): Likewise.
* config/arm/iwmmxt.md (VMMX): Move to new file.
(VSHFT, MMX_char): Likewise.
* config/arm/neon.md (VD): Move to new file.
(VDX, VDI, VQ, VQX, VQI, VQXMOV, VSTRUCT, VTAB, V_TAB_n, VW): Likewise.
(VN, VDQ, VDQW, VDQIW, VCVTF, VCVTI, VMD, VMQ, VMDQ, VMDI): Likewise.
(VMDQI, VX, VE, V64, V32, V_CVTTO, V_elem, V_ext, V_two_elem): Likewise.
(V_three_elem, V_four_elem, V_req, V_widen, V_narrow, V_HALF): Likewise.
(V_half,V_DOUBLE, V_double, V_double_width, V_cmp_result): Likewise.
(V_if_elem, V_s_elem, V_u_elem, V_uf_sclr, V_sz_elem, VD_dup): Likewise.
(V_PAIR, vqh_ops, vqhs_ops, VQH_mnem, VQH_sign, V_suf64): Likewise.
(scalar_mul_constraint,Is_float_mode, Scalar_mul_8_16): Likewise.
(Is_d_reg, V_mode_nunits): Likewise.
* config/arm/vec-common.md (VALL): Move to new file.
(VALLW, VINT, VINTW): Likewise.
From-SVN: r163058
2010-08-10 15:37:25 +02:00
|
|
|
|
|
|
|
;; Same, but for operations which work on unsigned values.
|
|
|
|
(define_mode_attr V_u_elem [(V8QI "u8") (V16QI "u8")
|
|
|
|
(V4HI "u16") (V8HI "u16")
|
|
|
|
(V2SI "u32") (V4SI "u32")
|
|
|
|
(DI "u64") (V2DI "u64")
|
|
|
|
(V2SF "f32") (V4SF "f32")])
|
|
|
|
|
|
|
|
;; Element types for extraction of unsigned scalars.
|
|
|
|
(define_mode_attr V_uf_sclr [(V8QI "u8") (V16QI "u8")
|
|
|
|
(V4HI "u16") (V8HI "u16")
|
|
|
|
(V2SI "32") (V4SI "32")
|
[ARM] Remaining intrinsics
* config/arm/arm-builtins.c (VAR11, VAR12): New.
* config/arm/arm_neon_builtins.def (vcombine, vld2_dup, vld3_dup,
vld4_dup): Add v4hf variant.
(vget_high, vget_low): Add v8hf variant.
(vld1, vst1, vst1_lane, vld2, vld2_lane, vst2, vst2_lane, vld3,
vld3_lane, vst3, vst3_lane, vld4, vld4_lane, vst4, vst4_lane): Add
v4hf and v8hf variants.
* config/arm/iterators.md (VD_LANE, VD_RE, VQ2, VQ_HS): New.
(VDX): Add V4HF.
(V_DOUBLE): Add case for V4HF.
(VQX): Add V8HF.
(V_HALF): Add case for V8HF.
(VDQX): Add V4HF, V8HF.
(V_elem, V_two_elem, V_three_elem, V_four_elem, V_cmp_result,
V_uf_sclr, V_sz_elem, V_mode_nunits, q): Add cases for V4HF & V8HF.
* config/arm/neon.md (vec_set<mode>internal, vec_extract<mode>,
neon_vget_lane<mode>_sext_internal, neon_vget_lane<mode>_zext_internal,
vec_load_lanesoi<mode>, neon_vld2<mode>, vec_store_lanesoi<mode>,
neon_vst2<mode>, vec_load_lanesci<mode>, neon_vld3<mode>,
neon_vld3qa<mode>, neon_vld3qb<mode>, vec_store_lanesci<mode>,
neon_vst3<mode>, neon_vst3qa<mode>, neon_vst3qb<mode>,
vec_load_lanesxi<mode>, neon_vld4<mode>, neon_vld4qa<mode>,
neon_vld4qb<mode>, vec_store_lanesxi<mode>, neon_vst4<mode>,
neon_vst4qa<mode>, neon_vst4qb<mode>): Change VQ iterator to VQ2.
(neon_vcreate, neon_vreinterpretv8qi<mode>,
neon_vreinterpretv4hi<mode>, neon_vreinterpretv2si<mode>,
neon_vreinterpretv2sf<mode>, neon_vreinterpretdi<mode>):
Change VDX to VD_RE.
(neon_vld2_lane<mode>, neon_vst2_lane<mode>, neon_vld3_lane<mode>,
neon_vst3_lane<mode>, neon_vld4_lane<mode>, neon_vst4_lane<mode>):
Change VD iterator to VD_LANE, and VMQ iterator to VQ_HS.
* config/arm/arm_neon.h (float16x4x2_t, float16x8x2_t, float16x4x3_t,
float16x8x3_t, float16x4x4_t, float16x8x4_t, vcombine_f16,
vget_high_f16, vget_low_f16, vld1_f16, vld1q_f16, vst1_f16, vst1q_f16,
vst1_lane_f16, vst1q_lane_f16, vld2_f16, vld2q_f16, vld2_lane_f16,
vld2q_lane_f16, vld2_dup_f16, vst2_f16, vst2q_f16, vst2_lane_f16,
vst2q_lane_f16, vld3_f16, vld3q_f16, vld3_lane_f16, vld3q_lane_f16,
vld3_dup_f16, vst3_f16, vst3q_f16, vst3_lane_f16, vst3q_lane_f16,
vld4_f16, vld4q_f16, vld4_lane_f16, vld4q_lane_f16, vld4_dup_f16,
vst4_f16, vst4q_f16, vst4_lane_f16, vst4q_lane_f16): New.
From-SVN: r227541
2015-09-08 20:48:47 +02:00
|
|
|
(V4HF "u16") (V8HF "u16")
|
iterators.md: New file.
2010-08-09 Sofiane Naci <sofiane.naci@arm.com>
* config/arm/iterators.md: New file.
* config/arm/arm.md: Include iterators.md.
(QHSI): Move to new file.
(LTUGEU, cnb, optab, ior_xor): Likewise.
* config/arm/iwmmxt.md (VMMX): Move to new file.
(VSHFT, MMX_char): Likewise.
* config/arm/neon.md (VD): Move to new file.
(VDX, VDI, VQ, VQX, VQI, VQXMOV, VSTRUCT, VTAB, V_TAB_n, VW): Likewise.
(VN, VDQ, VDQW, VDQIW, VCVTF, VCVTI, VMD, VMQ, VMDQ, VMDI): Likewise.
(VMDQI, VX, VE, V64, V32, V_CVTTO, V_elem, V_ext, V_two_elem): Likewise.
(V_three_elem, V_four_elem, V_req, V_widen, V_narrow, V_HALF): Likewise.
(V_half,V_DOUBLE, V_double, V_double_width, V_cmp_result): Likewise.
(V_if_elem, V_s_elem, V_u_elem, V_uf_sclr, V_sz_elem, VD_dup): Likewise.
(V_PAIR, vqh_ops, vqhs_ops, VQH_mnem, VQH_sign, V_suf64): Likewise.
(scalar_mul_constraint,Is_float_mode, Scalar_mul_8_16): Likewise.
(Is_d_reg, V_mode_nunits): Likewise.
* config/arm/vec-common.md (VALL): Move to new file.
(VALLW, VINT, VINTW): Likewise.
From-SVN: r163058
2010-08-10 15:37:25 +02:00
|
|
|
(V2SF "32") (V4SF "32")])
|
|
|
|
|
|
|
|
(define_mode_attr V_sz_elem [(V8QI "8") (V16QI "8")
|
2016-09-23 11:54:44 +02:00
|
|
|
(V4HI "16") (V8HI "16")
|
|
|
|
(V2SI "32") (V4SI "32")
|
|
|
|
(DI "64") (V2DI "64")
|
[ARM] Remaining intrinsics
* config/arm/arm-builtins.c (VAR11, VAR12): New.
* config/arm/arm_neon_builtins.def (vcombine, vld2_dup, vld3_dup,
vld4_dup): Add v4hf variant.
(vget_high, vget_low): Add v8hf variant.
(vld1, vst1, vst1_lane, vld2, vld2_lane, vst2, vst2_lane, vld3,
vld3_lane, vst3, vst3_lane, vld4, vld4_lane, vst4, vst4_lane): Add
v4hf and v8hf variants.
* config/arm/iterators.md (VD_LANE, VD_RE, VQ2, VQ_HS): New.
(VDX): Add V4HF.
(V_DOUBLE): Add case for V4HF.
(VQX): Add V8HF.
(V_HALF): Add case for V8HF.
(VDQX): Add V4HF, V8HF.
(V_elem, V_two_elem, V_three_elem, V_four_elem, V_cmp_result,
V_uf_sclr, V_sz_elem, V_mode_nunits, q): Add cases for V4HF & V8HF.
* config/arm/neon.md (vec_set<mode>internal, vec_extract<mode>,
neon_vget_lane<mode>_sext_internal, neon_vget_lane<mode>_zext_internal,
vec_load_lanesoi<mode>, neon_vld2<mode>, vec_store_lanesoi<mode>,
neon_vst2<mode>, vec_load_lanesci<mode>, neon_vld3<mode>,
neon_vld3qa<mode>, neon_vld3qb<mode>, vec_store_lanesci<mode>,
neon_vst3<mode>, neon_vst3qa<mode>, neon_vst3qb<mode>,
vec_load_lanesxi<mode>, neon_vld4<mode>, neon_vld4qa<mode>,
neon_vld4qb<mode>, vec_store_lanesxi<mode>, neon_vst4<mode>,
neon_vst4qa<mode>, neon_vst4qb<mode>): Change VQ iterator to VQ2.
(neon_vcreate, neon_vreinterpretv8qi<mode>,
neon_vreinterpretv4hi<mode>, neon_vreinterpretv2si<mode>,
neon_vreinterpretv2sf<mode>, neon_vreinterpretdi<mode>):
Change VDX to VD_RE.
(neon_vld2_lane<mode>, neon_vst2_lane<mode>, neon_vld3_lane<mode>,
neon_vst3_lane<mode>, neon_vld4_lane<mode>, neon_vst4_lane<mode>):
Change VD iterator to VD_LANE, and VMQ iterator to VQ_HS.
* config/arm/arm_neon.h (float16x4x2_t, float16x8x2_t, float16x4x3_t,
float16x8x3_t, float16x4x4_t, float16x8x4_t, vcombine_f16,
vget_high_f16, vget_low_f16, vld1_f16, vld1q_f16, vst1_f16, vst1q_f16,
vst1_lane_f16, vst1q_lane_f16, vld2_f16, vld2q_f16, vld2_lane_f16,
vld2q_lane_f16, vld2_dup_f16, vst2_f16, vst2q_f16, vst2_lane_f16,
vst2q_lane_f16, vld3_f16, vld3q_f16, vld3_lane_f16, vld3q_lane_f16,
vld3_dup_f16, vst3_f16, vst3q_f16, vst3_lane_f16, vst3q_lane_f16,
vld4_f16, vld4q_f16, vld4_lane_f16, vld4q_lane_f16, vld4_dup_f16,
vst4_f16, vst4q_f16, vst4_lane_f16, vst4q_lane_f16): New.
From-SVN: r227541
2015-09-08 20:48:47 +02:00
|
|
|
(V4HF "16") (V8HF "16")
|
2016-09-23 11:54:44 +02:00
|
|
|
(V2SF "32") (V4SF "32")])
|
iterators.md: New file.
2010-08-09 Sofiane Naci <sofiane.naci@arm.com>
* config/arm/iterators.md: New file.
* config/arm/arm.md: Include iterators.md.
(QHSI): Move to new file.
(LTUGEU, cnb, optab, ior_xor): Likewise.
* config/arm/iwmmxt.md (VMMX): Move to new file.
(VSHFT, MMX_char): Likewise.
* config/arm/neon.md (VD): Move to new file.
(VDX, VDI, VQ, VQX, VQI, VQXMOV, VSTRUCT, VTAB, V_TAB_n, VW): Likewise.
(VN, VDQ, VDQW, VDQIW, VCVTF, VCVTI, VMD, VMQ, VMDQ, VMDI): Likewise.
(VMDQI, VX, VE, V64, V32, V_CVTTO, V_elem, V_ext, V_two_elem): Likewise.
(V_three_elem, V_four_elem, V_req, V_widen, V_narrow, V_HALF): Likewise.
(V_half,V_DOUBLE, V_double, V_double_width, V_cmp_result): Likewise.
(V_if_elem, V_s_elem, V_u_elem, V_uf_sclr, V_sz_elem, VD_dup): Likewise.
(V_PAIR, vqh_ops, vqhs_ops, VQH_mnem, VQH_sign, V_suf64): Likewise.
(scalar_mul_constraint,Is_float_mode, Scalar_mul_8_16): Likewise.
(Is_d_reg, V_mode_nunits): Likewise.
* config/arm/vec-common.md (VALL): Move to new file.
(VALLW, VINT, VINTW): Likewise.
From-SVN: r163058
2010-08-10 15:37:25 +02:00
|
|
|
|
2013-10-15 17:28:04 +02:00
|
|
|
(define_mode_attr V_elem_ch [(V8QI "b") (V16QI "b")
|
2016-09-23 11:54:44 +02:00
|
|
|
(V4HI "h") (V8HI "h")
|
|
|
|
(V2SI "s") (V4SI "s")
|
|
|
|
(DI "d") (V2DI "d")
|
|
|
|
(V2SF "s") (V4SF "s")
|
|
|
|
(V2SF "s") (V4SF "s")])
|
|
|
|
|
|
|
|
(define_mode_attr VH_elem_ch [(V4HI "s") (V8HI "s")
|
|
|
|
(V4HF "s") (V8HF "s")
|
|
|
|
(HF "s")])
|
2013-10-15 17:28:04 +02:00
|
|
|
|
iterators.md: New file.
2010-08-09 Sofiane Naci <sofiane.naci@arm.com>
* config/arm/iterators.md: New file.
* config/arm/arm.md: Include iterators.md.
(QHSI): Move to new file.
(LTUGEU, cnb, optab, ior_xor): Likewise.
* config/arm/iwmmxt.md (VMMX): Move to new file.
(VSHFT, MMX_char): Likewise.
* config/arm/neon.md (VD): Move to new file.
(VDX, VDI, VQ, VQX, VQI, VQXMOV, VSTRUCT, VTAB, V_TAB_n, VW): Likewise.
(VN, VDQ, VDQW, VDQIW, VCVTF, VCVTI, VMD, VMQ, VMDQ, VMDI): Likewise.
(VMDQI, VX, VE, V64, V32, V_CVTTO, V_elem, V_ext, V_two_elem): Likewise.
(V_three_elem, V_four_elem, V_req, V_widen, V_narrow, V_HALF): Likewise.
(V_half,V_DOUBLE, V_double, V_double_width, V_cmp_result): Likewise.
(V_if_elem, V_s_elem, V_u_elem, V_uf_sclr, V_sz_elem, VD_dup): Likewise.
(V_PAIR, vqh_ops, vqhs_ops, VQH_mnem, VQH_sign, V_suf64): Likewise.
(scalar_mul_constraint,Is_float_mode, Scalar_mul_8_16): Likewise.
(Is_d_reg, V_mode_nunits): Likewise.
* config/arm/vec-common.md (VALL): Move to new file.
(VALLW, VINT, VINTW): Likewise.
From-SVN: r163058
2010-08-10 15:37:25 +02:00
|
|
|
;; Element sizes for duplicating ARM registers to all elements of a vector.
|
|
|
|
(define_mode_attr VD_dup [(V8QI "8") (V4HI "16") (V2SI "32") (V2SF "32")])
|
|
|
|
|
|
|
|
;; Opaque integer types for results of pair-forming intrinsics (vtrn, etc.)
|
|
|
|
(define_mode_attr V_PAIR [(V8QI "TI") (V16QI "OI")
|
|
|
|
(V4HI "TI") (V8HI "OI")
|
|
|
|
(V2SI "TI") (V4SI "OI")
|
|
|
|
(V2SF "TI") (V4SF "OI")
|
|
|
|
(DI "TI") (V2DI "OI")])
|
|
|
|
|
|
|
|
;; Same, but lower-case.
|
|
|
|
(define_mode_attr V_pair [(V8QI "ti") (V16QI "oi")
|
|
|
|
(V4HI "ti") (V8HI "oi")
|
|
|
|
(V2SI "ti") (V4SI "oi")
|
|
|
|
(V2SF "ti") (V4SF "oi")
|
|
|
|
(DI "ti") (V2DI "oi")])
|
|
|
|
|
|
|
|
;; Extra suffix on some 64-bit insn names (to avoid collision with standard
|
|
|
|
;; names which we don't want to define).
|
|
|
|
(define_mode_attr V_suf64 [(V8QI "") (V16QI "")
|
|
|
|
(V4HI "") (V8HI "")
|
|
|
|
(V2SI "") (V4SI "")
|
|
|
|
(V2SF "") (V4SF "")
|
|
|
|
(DI "_neon") (V2DI "")])
|
|
|
|
|
|
|
|
|
|
|
|
;; Scalars to be presented to scalar multiplication instructions
|
|
|
|
;; must satisfy the following constraints.
|
|
|
|
;; 1. If the mode specifies 16-bit elements, the scalar must be in D0-D7.
|
|
|
|
;; 2. If the mode specifies 32-bit elements, the scalar must be in D0-D15.
|
|
|
|
|
|
|
|
;; This mode attribute is used to obtain the correct register constraints.
|
|
|
|
|
|
|
|
(define_mode_attr scalar_mul_constraint [(V4HI "x") (V2SI "t") (V2SF "t")
|
2016-09-23 11:54:44 +02:00
|
|
|
(V8HI "x") (V4SI "t") (V4SF "t")
|
|
|
|
(V8HF "x") (V4HF "x")])
|
iterators.md: New file.
2010-08-09 Sofiane Naci <sofiane.naci@arm.com>
* config/arm/iterators.md: New file.
* config/arm/arm.md: Include iterators.md.
(QHSI): Move to new file.
(LTUGEU, cnb, optab, ior_xor): Likewise.
* config/arm/iwmmxt.md (VMMX): Move to new file.
(VSHFT, MMX_char): Likewise.
* config/arm/neon.md (VD): Move to new file.
(VDX, VDI, VQ, VQX, VQI, VQXMOV, VSTRUCT, VTAB, V_TAB_n, VW): Likewise.
(VN, VDQ, VDQW, VDQIW, VCVTF, VCVTI, VMD, VMQ, VMDQ, VMDI): Likewise.
(VMDQI, VX, VE, V64, V32, V_CVTTO, V_elem, V_ext, V_two_elem): Likewise.
(V_three_elem, V_four_elem, V_req, V_widen, V_narrow, V_HALF): Likewise.
(V_half,V_DOUBLE, V_double, V_double_width, V_cmp_result): Likewise.
(V_if_elem, V_s_elem, V_u_elem, V_uf_sclr, V_sz_elem, VD_dup): Likewise.
(V_PAIR, vqh_ops, vqhs_ops, VQH_mnem, VQH_sign, V_suf64): Likewise.
(scalar_mul_constraint,Is_float_mode, Scalar_mul_8_16): Likewise.
(Is_d_reg, V_mode_nunits): Likewise.
* config/arm/vec-common.md (VALL): Move to new file.
(VALLW, VINT, VINTW): Likewise.
From-SVN: r163058
2010-08-10 15:37:25 +02:00
|
|
|
|
2013-09-05 11:29:27 +02:00
|
|
|
;; Predicates used for setting type for neon instructions
|
iterators.md: New file.
2010-08-09 Sofiane Naci <sofiane.naci@arm.com>
* config/arm/iterators.md: New file.
* config/arm/arm.md: Include iterators.md.
(QHSI): Move to new file.
(LTUGEU, cnb, optab, ior_xor): Likewise.
* config/arm/iwmmxt.md (VMMX): Move to new file.
(VSHFT, MMX_char): Likewise.
* config/arm/neon.md (VD): Move to new file.
(VDX, VDI, VQ, VQX, VQI, VQXMOV, VSTRUCT, VTAB, V_TAB_n, VW): Likewise.
(VN, VDQ, VDQW, VDQIW, VCVTF, VCVTI, VMD, VMQ, VMDQ, VMDI): Likewise.
(VMDQI, VX, VE, V64, V32, V_CVTTO, V_elem, V_ext, V_two_elem): Likewise.
(V_three_elem, V_four_elem, V_req, V_widen, V_narrow, V_HALF): Likewise.
(V_half,V_DOUBLE, V_double, V_double_width, V_cmp_result): Likewise.
(V_if_elem, V_s_elem, V_u_elem, V_uf_sclr, V_sz_elem, VD_dup): Likewise.
(V_PAIR, vqh_ops, vqhs_ops, VQH_mnem, VQH_sign, V_suf64): Likewise.
(scalar_mul_constraint,Is_float_mode, Scalar_mul_8_16): Likewise.
(Is_d_reg, V_mode_nunits): Likewise.
* config/arm/vec-common.md (VALL): Move to new file.
(VALLW, VINT, VINTW): Likewise.
From-SVN: r163058
2010-08-10 15:37:25 +02:00
|
|
|
|
|
|
|
(define_mode_attr Is_float_mode [(V8QI "false") (V16QI "false")
|
2016-09-23 11:54:44 +02:00
|
|
|
(V4HI "false") (V8HI "false")
|
|
|
|
(V2SI "false") (V4SI "false")
|
|
|
|
(V4HF "true") (V8HF "true")
|
|
|
|
(V2SF "true") (V4SF "true")
|
|
|
|
(DI "false") (V2DI "false")])
|
iterators.md: New file.
2010-08-09 Sofiane Naci <sofiane.naci@arm.com>
* config/arm/iterators.md: New file.
* config/arm/arm.md: Include iterators.md.
(QHSI): Move to new file.
(LTUGEU, cnb, optab, ior_xor): Likewise.
* config/arm/iwmmxt.md (VMMX): Move to new file.
(VSHFT, MMX_char): Likewise.
* config/arm/neon.md (VD): Move to new file.
(VDX, VDI, VQ, VQX, VQI, VQXMOV, VSTRUCT, VTAB, V_TAB_n, VW): Likewise.
(VN, VDQ, VDQW, VDQIW, VCVTF, VCVTI, VMD, VMQ, VMDQ, VMDI): Likewise.
(VMDQI, VX, VE, V64, V32, V_CVTTO, V_elem, V_ext, V_two_elem): Likewise.
(V_three_elem, V_four_elem, V_req, V_widen, V_narrow, V_HALF): Likewise.
(V_half,V_DOUBLE, V_double, V_double_width, V_cmp_result): Likewise.
(V_if_elem, V_s_elem, V_u_elem, V_uf_sclr, V_sz_elem, VD_dup): Likewise.
(V_PAIR, vqh_ops, vqhs_ops, VQH_mnem, VQH_sign, V_suf64): Likewise.
(scalar_mul_constraint,Is_float_mode, Scalar_mul_8_16): Likewise.
(Is_d_reg, V_mode_nunits): Likewise.
* config/arm/vec-common.md (VALL): Move to new file.
(VALLW, VINT, VINTW): Likewise.
From-SVN: r163058
2010-08-10 15:37:25 +02:00
|
|
|
|
|
|
|
(define_mode_attr Scalar_mul_8_16 [(V8QI "true") (V16QI "true")
|
2016-09-23 11:23:01 +02:00
|
|
|
(V4HI "true") (V8HI "true")
|
|
|
|
(V2SI "false") (V4SI "false")
|
|
|
|
(V2SF "false") (V4SF "false")
|
|
|
|
(DI "false") (V2DI "false")])
|
iterators.md: New file.
2010-08-09 Sofiane Naci <sofiane.naci@arm.com>
* config/arm/iterators.md: New file.
* config/arm/arm.md: Include iterators.md.
(QHSI): Move to new file.
(LTUGEU, cnb, optab, ior_xor): Likewise.
* config/arm/iwmmxt.md (VMMX): Move to new file.
(VSHFT, MMX_char): Likewise.
* config/arm/neon.md (VD): Move to new file.
(VDX, VDI, VQ, VQX, VQI, VQXMOV, VSTRUCT, VTAB, V_TAB_n, VW): Likewise.
(VN, VDQ, VDQW, VDQIW, VCVTF, VCVTI, VMD, VMQ, VMDQ, VMDI): Likewise.
(VMDQI, VX, VE, V64, V32, V_CVTTO, V_elem, V_ext, V_two_elem): Likewise.
(V_three_elem, V_four_elem, V_req, V_widen, V_narrow, V_HALF): Likewise.
(V_half,V_DOUBLE, V_double, V_double_width, V_cmp_result): Likewise.
(V_if_elem, V_s_elem, V_u_elem, V_uf_sclr, V_sz_elem, VD_dup): Likewise.
(V_PAIR, vqh_ops, vqhs_ops, VQH_mnem, VQH_sign, V_suf64): Likewise.
(scalar_mul_constraint,Is_float_mode, Scalar_mul_8_16): Likewise.
(Is_d_reg, V_mode_nunits): Likewise.
* config/arm/vec-common.md (VALL): Move to new file.
(VALLW, VINT, VINTW): Likewise.
From-SVN: r163058
2010-08-10 15:37:25 +02:00
|
|
|
|
|
|
|
(define_mode_attr Is_d_reg [(V8QI "true") (V16QI "false")
|
2016-09-23 11:54:44 +02:00
|
|
|
(V4HI "true") (V8HI "false")
|
|
|
|
(V2SI "true") (V4SI "false")
|
|
|
|
(V2SF "true") (V4SF "false")
|
|
|
|
(DI "true") (V2DI "false")
|
2016-09-23 11:23:01 +02:00
|
|
|
(V4HF "true") (V8HF "false")])
|
iterators.md: New file.
2010-08-09 Sofiane Naci <sofiane.naci@arm.com>
* config/arm/iterators.md: New file.
* config/arm/arm.md: Include iterators.md.
(QHSI): Move to new file.
(LTUGEU, cnb, optab, ior_xor): Likewise.
* config/arm/iwmmxt.md (VMMX): Move to new file.
(VSHFT, MMX_char): Likewise.
* config/arm/neon.md (VD): Move to new file.
(VDX, VDI, VQ, VQX, VQI, VQXMOV, VSTRUCT, VTAB, V_TAB_n, VW): Likewise.
(VN, VDQ, VDQW, VDQIW, VCVTF, VCVTI, VMD, VMQ, VMDQ, VMDI): Likewise.
(VMDQI, VX, VE, V64, V32, V_CVTTO, V_elem, V_ext, V_two_elem): Likewise.
(V_three_elem, V_four_elem, V_req, V_widen, V_narrow, V_HALF): Likewise.
(V_half,V_DOUBLE, V_double, V_double_width, V_cmp_result): Likewise.
(V_if_elem, V_s_elem, V_u_elem, V_uf_sclr, V_sz_elem, VD_dup): Likewise.
(V_PAIR, vqh_ops, vqhs_ops, VQH_mnem, VQH_sign, V_suf64): Likewise.
(scalar_mul_constraint,Is_float_mode, Scalar_mul_8_16): Likewise.
(Is_d_reg, V_mode_nunits): Likewise.
* config/arm/vec-common.md (VALL): Move to new file.
(VALLW, VINT, VINTW): Likewise.
From-SVN: r163058
2010-08-10 15:37:25 +02:00
|
|
|
|
|
|
|
(define_mode_attr V_mode_nunits [(V8QI "8") (V16QI "16")
|
[ARM] Remaining intrinsics
* config/arm/arm-builtins.c (VAR11, VAR12): New.
* config/arm/arm_neon_builtins.def (vcombine, vld2_dup, vld3_dup,
vld4_dup): Add v4hf variant.
(vget_high, vget_low): Add v8hf variant.
(vld1, vst1, vst1_lane, vld2, vld2_lane, vst2, vst2_lane, vld3,
vld3_lane, vst3, vst3_lane, vld4, vld4_lane, vst4, vst4_lane): Add
v4hf and v8hf variants.
* config/arm/iterators.md (VD_LANE, VD_RE, VQ2, VQ_HS): New.
(VDX): Add V4HF.
(V_DOUBLE): Add case for V4HF.
(VQX): Add V8HF.
(V_HALF): Add case for V8HF.
(VDQX): Add V4HF, V8HF.
(V_elem, V_two_elem, V_three_elem, V_four_elem, V_cmp_result,
V_uf_sclr, V_sz_elem, V_mode_nunits, q): Add cases for V4HF & V8HF.
* config/arm/neon.md (vec_set<mode>internal, vec_extract<mode>,
neon_vget_lane<mode>_sext_internal, neon_vget_lane<mode>_zext_internal,
vec_load_lanesoi<mode>, neon_vld2<mode>, vec_store_lanesoi<mode>,
neon_vst2<mode>, vec_load_lanesci<mode>, neon_vld3<mode>,
neon_vld3qa<mode>, neon_vld3qb<mode>, vec_store_lanesci<mode>,
neon_vst3<mode>, neon_vst3qa<mode>, neon_vst3qb<mode>,
vec_load_lanesxi<mode>, neon_vld4<mode>, neon_vld4qa<mode>,
neon_vld4qb<mode>, vec_store_lanesxi<mode>, neon_vst4<mode>,
neon_vst4qa<mode>, neon_vst4qb<mode>): Change VQ iterator to VQ2.
(neon_vcreate, neon_vreinterpretv8qi<mode>,
neon_vreinterpretv4hi<mode>, neon_vreinterpretv2si<mode>,
neon_vreinterpretv2sf<mode>, neon_vreinterpretdi<mode>):
Change VDX to VD_RE.
(neon_vld2_lane<mode>, neon_vst2_lane<mode>, neon_vld3_lane<mode>,
neon_vst3_lane<mode>, neon_vld4_lane<mode>, neon_vst4_lane<mode>):
Change VD iterator to VD_LANE, and VMQ iterator to VQ_HS.
* config/arm/arm_neon.h (float16x4x2_t, float16x8x2_t, float16x4x3_t,
float16x8x3_t, float16x4x4_t, float16x8x4_t, vcombine_f16,
vget_high_f16, vget_low_f16, vld1_f16, vld1q_f16, vst1_f16, vst1q_f16,
vst1_lane_f16, vst1q_lane_f16, vld2_f16, vld2q_f16, vld2_lane_f16,
vld2q_lane_f16, vld2_dup_f16, vst2_f16, vst2q_f16, vst2_lane_f16,
vst2q_lane_f16, vld3_f16, vld3q_f16, vld3_lane_f16, vld3q_lane_f16,
vld3_dup_f16, vst3_f16, vst3q_f16, vst3_lane_f16, vst3q_lane_f16,
vld4_f16, vld4q_f16, vld4_lane_f16, vld4q_lane_f16, vld4_dup_f16,
vst4_f16, vst4q_f16, vst4_lane_f16, vst4q_lane_f16): New.
From-SVN: r227541
2015-09-08 20:48:47 +02:00
|
|
|
(V4HF "4") (V8HF "8")
|
iterators.md: New file.
2010-08-09 Sofiane Naci <sofiane.naci@arm.com>
* config/arm/iterators.md: New file.
* config/arm/arm.md: Include iterators.md.
(QHSI): Move to new file.
(LTUGEU, cnb, optab, ior_xor): Likewise.
* config/arm/iwmmxt.md (VMMX): Move to new file.
(VSHFT, MMX_char): Likewise.
* config/arm/neon.md (VD): Move to new file.
(VDX, VDI, VQ, VQX, VQI, VQXMOV, VSTRUCT, VTAB, V_TAB_n, VW): Likewise.
(VN, VDQ, VDQW, VDQIW, VCVTF, VCVTI, VMD, VMQ, VMDQ, VMDI): Likewise.
(VMDQI, VX, VE, V64, V32, V_CVTTO, V_elem, V_ext, V_two_elem): Likewise.
(V_three_elem, V_four_elem, V_req, V_widen, V_narrow, V_HALF): Likewise.
(V_half,V_DOUBLE, V_double, V_double_width, V_cmp_result): Likewise.
(V_if_elem, V_s_elem, V_u_elem, V_uf_sclr, V_sz_elem, VD_dup): Likewise.
(V_PAIR, vqh_ops, vqhs_ops, VQH_mnem, VQH_sign, V_suf64): Likewise.
(scalar_mul_constraint,Is_float_mode, Scalar_mul_8_16): Likewise.
(Is_d_reg, V_mode_nunits): Likewise.
* config/arm/vec-common.md (VALL): Move to new file.
(VALLW, VINT, VINTW): Likewise.
From-SVN: r163058
2010-08-10 15:37:25 +02:00
|
|
|
(V4HI "4") (V8HI "8")
|
|
|
|
(V2SI "2") (V4SI "4")
|
|
|
|
(V2SF "2") (V4SF "4")
|
2010-09-15 13:18:07 +02:00
|
|
|
(DI "1") (V2DI "2")
|
|
|
|
(DF "1") (V2DF "2")])
|
iterators.md: New file.
2010-08-09 Sofiane Naci <sofiane.naci@arm.com>
* config/arm/iterators.md: New file.
* config/arm/arm.md: Include iterators.md.
(QHSI): Move to new file.
(LTUGEU, cnb, optab, ior_xor): Likewise.
* config/arm/iwmmxt.md (VMMX): Move to new file.
(VSHFT, MMX_char): Likewise.
* config/arm/neon.md (VD): Move to new file.
(VDX, VDI, VQ, VQX, VQI, VQXMOV, VSTRUCT, VTAB, V_TAB_n, VW): Likewise.
(VN, VDQ, VDQW, VDQIW, VCVTF, VCVTI, VMD, VMQ, VMDQ, VMDI): Likewise.
(VMDQI, VX, VE, V64, V32, V_CVTTO, V_elem, V_ext, V_two_elem): Likewise.
(V_three_elem, V_four_elem, V_req, V_widen, V_narrow, V_HALF): Likewise.
(V_half,V_DOUBLE, V_double, V_double_width, V_cmp_result): Likewise.
(V_if_elem, V_s_elem, V_u_elem, V_uf_sclr, V_sz_elem, VD_dup): Likewise.
(V_PAIR, vqh_ops, vqhs_ops, VQH_mnem, VQH_sign, V_suf64): Likewise.
(scalar_mul_constraint,Is_float_mode, Scalar_mul_8_16): Likewise.
(Is_d_reg, V_mode_nunits): Likewise.
* config/arm/vec-common.md (VALL): Move to new file.
(VALLW, VINT, VINTW): Likewise.
From-SVN: r163058
2010-08-10 15:37:25 +02:00
|
|
|
|
2010-08-25 09:23:26 +02:00
|
|
|
;; Same as V_widen, but lower-case.
|
|
|
|
(define_mode_attr V_widen_l [(V8QI "v8hi") (V4HI "v4si") ( V2SI "v2di")])
|
|
|
|
|
|
|
|
;; Widen. Result is half the number of elements, but widened to double-width.
|
|
|
|
(define_mode_attr V_unpack [(V16QI "V8HI") (V8HI "V4SI") (V4SI "V2DI")])
|
iterators.md: New file.
2010-08-09 Sofiane Naci <sofiane.naci@arm.com>
* config/arm/iterators.md: New file.
* config/arm/arm.md: Include iterators.md.
(QHSI): Move to new file.
(LTUGEU, cnb, optab, ior_xor): Likewise.
* config/arm/iwmmxt.md (VMMX): Move to new file.
(VSHFT, MMX_char): Likewise.
* config/arm/neon.md (VD): Move to new file.
(VDX, VDI, VQ, VQX, VQI, VQXMOV, VSTRUCT, VTAB, V_TAB_n, VW): Likewise.
(VN, VDQ, VDQW, VDQIW, VCVTF, VCVTI, VMD, VMQ, VMDQ, VMDI): Likewise.
(VMDQI, VX, VE, V64, V32, V_CVTTO, V_elem, V_ext, V_two_elem): Likewise.
(V_three_elem, V_four_elem, V_req, V_widen, V_narrow, V_HALF): Likewise.
(V_half,V_DOUBLE, V_double, V_double_width, V_cmp_result): Likewise.
(V_if_elem, V_s_elem, V_u_elem, V_uf_sclr, V_sz_elem, VD_dup): Likewise.
(V_PAIR, vqh_ops, vqhs_ops, VQH_mnem, VQH_sign, V_suf64): Likewise.
(scalar_mul_constraint,Is_float_mode, Scalar_mul_8_16): Likewise.
(Is_d_reg, V_mode_nunits): Likewise.
* config/arm/vec-common.md (VALL): Move to new file.
(VALLW, VINT, VINTW): Likewise.
From-SVN: r163058
2010-08-10 15:37:25 +02:00
|
|
|
|
re PR target/43137 (redundant register move for sign extending)
PR target/43137
* config/arm/iterators.md (qhs_zextenddi_cond, qhs_sextenddi_cond):
New define_mode_attrs.
* config/arm/arm.md (zero_extendsidi2, arm_zero_extendsidi2,
arm_exxtendsidi2, arm_extendsidi2): Delete patterns.
(zero_extend<mode>di2, extend<mode>di2 and related splits): New.
(thumb1_zero_extendhisi2): Remove code to handle LABEL_REFs.
Remove pool_range attribute.
(arm_zero_extendhisi2, arm_zero_extendhisi2_v6, arm_zero_extendqisi2,
arm_zero_extendqisi2_v6, thumb1_zero_extendqisi2_v6): Remove
pool_range and neg_pool_range attributes.
* config/arm/thumb2.md (thumb2_zero_extendsidi2,
thumb2_zero_extendhidi2, thumb2_zero_extendqidi2, thumb2_extendsidi2,
thumb2_extendhidi2, thumb2_extendqidi2): Delete.
PR target/43137
* gcc.target/arm/pr43137.c: New test.
From-SVN: r163935
2010-09-07 00:32:26 +02:00
|
|
|
;; Conditions to be used in extend<mode>di patterns.
|
|
|
|
(define_mode_attr qhs_zextenddi_cond [(SI "") (HI "&& arm_arch6") (QI "")])
|
|
|
|
(define_mode_attr qhs_sextenddi_cond [(SI "") (HI "&& arm_arch6")
|
|
|
|
(QI "&& arm_arch6")])
|
2011-09-30 11:36:43 +02:00
|
|
|
(define_mode_attr qhs_zextenddi_op [(SI "s_register_operand")
|
2010-09-21 15:11:03 +02:00
|
|
|
(HI "nonimmediate_operand")
|
|
|
|
(QI "nonimmediate_operand")])
|
2011-09-30 11:36:43 +02:00
|
|
|
(define_mode_attr qhs_extenddi_op [(SI "s_register_operand")
|
|
|
|
(HI "nonimmediate_operand")
|
|
|
|
(QI "arm_reg_or_extendqisi_mem_op")])
|
2013-02-22 15:23:12 +01:00
|
|
|
(define_mode_attr qhs_extenddi_cstr [(SI "r,0,r,r,r") (HI "r,0,rm,rm,r") (QI "r,0,rUq,rm,r")])
|
|
|
|
(define_mode_attr qhs_zextenddi_cstr [(SI "r,0,r,r") (HI "r,0,rm,r") (QI "r,0,rm,r")])
|
re PR target/43137 (redundant register move for sign extending)
PR target/43137
* config/arm/iterators.md (qhs_zextenddi_cond, qhs_sextenddi_cond):
New define_mode_attrs.
* config/arm/arm.md (zero_extendsidi2, arm_zero_extendsidi2,
arm_exxtendsidi2, arm_extendsidi2): Delete patterns.
(zero_extend<mode>di2, extend<mode>di2 and related splits): New.
(thumb1_zero_extendhisi2): Remove code to handle LABEL_REFs.
Remove pool_range attribute.
(arm_zero_extendhisi2, arm_zero_extendhisi2_v6, arm_zero_extendqisi2,
arm_zero_extendqisi2_v6, thumb1_zero_extendqisi2_v6): Remove
pool_range and neg_pool_range attributes.
* config/arm/thumb2.md (thumb2_zero_extendsidi2,
thumb2_zero_extendhidi2, thumb2_zero_extendqidi2, thumb2_extendsidi2,
thumb2_extendhidi2, thumb2_extendqidi2): Delete.
PR target/43137
* gcc.target/arm/pr43137.c: New test.
From-SVN: r163935
2010-09-07 00:32:26 +02:00
|
|
|
|
configure.ac (fixed-point): Add ARM support.
gcc/
* configure.ac (fixed-point): Add ARM support.
* configure: Regenerate.
* config/arm/arm.c (arm_fixed_mode_set): New struct.
(arm_set_fixed_optab_libfunc): New.
(arm_set_fixed_conv_libfunc): New.
(arm_init_libfuncs): Initialise fixed-point helper libfuncs with
ARM-specific names.
(aapcs_libcall_value): Return sub-word-size fixed-point libcall
return values in SImode.
(arm_return_in_msb): Return fixed-point types in the msb.
(arm_pad_reg_upwards, arm_pad_arg_upwards): Pad fixed-point types
upwards.
(arm_scalar_mode_supported_p): Support fixed-point modes.
(arm_vector_mode_supported_p): Support vector fixed-point modes.
* config/arm/arm.h (SHORT_FRACT_TYPE_SIZE, FRACT_TYPE_SIZE)
(LONG_FRACT_TYPE_SIZE, LONG_LONG_FRACT_TYPE_SIZE)
(SHORT_ACCUM_TYPE_SIZE, ACCUM_TYPE_SIZE, LONG_ACCUM_TYPE_SIZE)
(LONG_LONG_ACCUM_TYPE_SIZE, MAX_FIXED_MODE_SIZE): Define.
* config/arm/iterators.md (FIXED, ADDSUB, UQADDSUB, QADDSUB, QMUL):
New mode iterators.
(qaddsub_suf): New mode attribute.
* config/arm/arm-modes.def (FRACT, UFRACT, ACCUM, UACCUM): Declare
vector modes.
* config/arm/predicates.md (sat_shift_operator): New predicate.
* config/arm/arm-fixed.md: New.
* config/arm/arm.md: Include arm-fixed.md.
* config/arm/t-arm (MD_INCLUDES): Add arm-fixed.md.
libgcc/
* config.host (arm*-*-linux*, arm*-*-uclinux*, arm*-*-eabi*)
(arm*-*-symbianelf*): Add t-fixedpoint-gnu-prefix makefile fragment.
* config/arm/bpabi-lib.h (LIBGCC2_FIXEDBIT_GNU_PREFIX): Define.
gcc/testsuite/
* gcc.target/arm/fixed-point-exec.c: New test.
From-SVN: r177025
2011-08-01 14:41:30 +02:00
|
|
|
;; Mode attributes used for fixed-point support.
|
|
|
|
(define_mode_attr qaddsub_suf [(V4UQQ "8") (V2UHQ "16") (UQQ "8") (UHQ "16")
|
|
|
|
(V2UHA "16") (UHA "16")
|
|
|
|
(V4QQ "8") (V2HQ "16") (QQ "8") (HQ "16")
|
|
|
|
(V2HA "16") (HA "16") (SQ "") (SA "")])
|
|
|
|
|
md.texi (vec_widen_ushiftl_hi, [...]): Document.
* doc/md.texi (vec_widen_ushiftl_hi, vec_widen_ushiftl_lo,
vec_widen_sshiftl_hi, vec_widen_sshiftl_lo): Document.
* tree-pretty-print.c (dump_generic_node): Handle WIDEN_LSHIFT_EXPR,
VEC_WIDEN_LSHIFT_HI_EXPR and VEC_WIDEN_LSHIFT_LO_EXPR.
(op_code_prio): Likewise.
(op_symbol_code): Handle WIDEN_LSHIFT_EXPR.
* optabs.c (optab_for_tree_code): Handle
VEC_WIDEN_LSHIFT_HI_EXPR and VEC_WIDEN_LSHIFT_LO_EXPR.
(init-optabs): Initialize optab codes for vec_widen_u/sshiftl_hi/lo.
* optabs.h (enum optab_index): Add OTI_vec_widen_u/sshiftl_hi/lo.
* genopinit.c (optabs): Initialize the new optabs.
* expr.c (expand_expr_real_2): Handle
VEC_WIDEN_LSHIFT_HI_EXPR and VEC_WIDEN_LSHIFT_LO_EXPR.
* gimple-pretty-print.c (dump_binary_rhs): Likewise.
* tree-vectorizer.h (NUM_PATTERNS): Increase to 8.
* tree.def (WIDEN_LSHIFT_EXPR, VEC_WIDEN_LSHIFT_HI_EXPR,
VEC_WIDEN_LSHIFT_LO_EXPR): New.
* cfgexpand.c (expand_debug_expr): Handle new tree codes.
* tree-vect-patterns.c (vect_vect_recog_func_ptrs): Add
vect_recog_widen_shift_pattern.
(vect_handle_widen_mult_by_const): Rename...
(vect_handle_widen_op_by_const): ...to this. Handle shifts.
Add a new argument, update documentation.
(vect_recog_widen_mult_pattern): Assume that only second
operand can be constant. Update call to
vect_handle_widen_op_by_const.
(vect_recog_over_widening_pattern): Fix typo.
(vect_recog_widen_shift_pattern): New.
* tree-vect-stmts.c (vectorizable_type_promotion): Handle
widening shifts.
(supportable_widening_operation): Likewise.
* tree-inline.c (estimate_operator_cost): Handle new tree codes.
* tree-vect-generic.c (expand_vector_operations_1): Likewise.
* tree-cfg.c (verify_gimple_assign_binary): Likewise.
* config/arm/neon.md (neon_vec_<US>shiftl_<mode>): New.
(vec_widen_<US>shiftl_lo_<mode>, neon_vec_<US>shiftl_hi_<mode>,
vec_widen_<US>shiftl_hi_<mode>, neon_vec_<US>shift_left_<mode>):
Likewise.
* config/arm/predicates.md (const_neon_scalar_shift_amount_operand):
New.
* config/arm/iterators.md (V_innermode): New.
* tree-vect-slp.c (vect_build_slp_tree): Require same shift operand
for widening shift.
From-SVN: r180128
2011-10-18 11:39:04 +02:00
|
|
|
;; Mode attribute for vshll.
|
|
|
|
(define_mode_attr V_innermode [(V8QI "QI") (V4HI "HI") (V2SI "SI")])
|
|
|
|
|
2012-11-26 13:33:02 +01:00
|
|
|
;; Mode attributes used for VFP support.
|
2012-07-05 11:07:00 +02:00
|
|
|
(define_mode_attr F_constraint [(SF "t") (DF "w")])
|
2012-11-26 13:33:02 +01:00
|
|
|
(define_mode_attr vfp_type [(SF "s") (DF "d")])
|
|
|
|
(define_mode_attr vfp_double_cond [(SF "") (DF "&& TARGET_VFP_DOUBLE")])
|
2012-07-05 11:07:00 +02:00
|
|
|
|
2013-10-15 17:28:04 +02:00
|
|
|
;; Mode attribute used to build the "type" attribute.
|
|
|
|
(define_mode_attr q [(V8QI "") (V16QI "_q")
|
2016-09-23 11:54:44 +02:00
|
|
|
(V4HI "") (V8HI "_q")
|
|
|
|
(V2SI "") (V4SI "_q")
|
[ARM] Remaining intrinsics
* config/arm/arm-builtins.c (VAR11, VAR12): New.
* config/arm/arm_neon_builtins.def (vcombine, vld2_dup, vld3_dup,
vld4_dup): Add v4hf variant.
(vget_high, vget_low): Add v8hf variant.
(vld1, vst1, vst1_lane, vld2, vld2_lane, vst2, vst2_lane, vld3,
vld3_lane, vst3, vst3_lane, vld4, vld4_lane, vst4, vst4_lane): Add
v4hf and v8hf variants.
* config/arm/iterators.md (VD_LANE, VD_RE, VQ2, VQ_HS): New.
(VDX): Add V4HF.
(V_DOUBLE): Add case for V4HF.
(VQX): Add V8HF.
(V_HALF): Add case for V8HF.
(VDQX): Add V4HF, V8HF.
(V_elem, V_two_elem, V_three_elem, V_four_elem, V_cmp_result,
V_uf_sclr, V_sz_elem, V_mode_nunits, q): Add cases for V4HF & V8HF.
* config/arm/neon.md (vec_set<mode>internal, vec_extract<mode>,
neon_vget_lane<mode>_sext_internal, neon_vget_lane<mode>_zext_internal,
vec_load_lanesoi<mode>, neon_vld2<mode>, vec_store_lanesoi<mode>,
neon_vst2<mode>, vec_load_lanesci<mode>, neon_vld3<mode>,
neon_vld3qa<mode>, neon_vld3qb<mode>, vec_store_lanesci<mode>,
neon_vst3<mode>, neon_vst3qa<mode>, neon_vst3qb<mode>,
vec_load_lanesxi<mode>, neon_vld4<mode>, neon_vld4qa<mode>,
neon_vld4qb<mode>, vec_store_lanesxi<mode>, neon_vst4<mode>,
neon_vst4qa<mode>, neon_vst4qb<mode>): Change VQ iterator to VQ2.
(neon_vcreate, neon_vreinterpretv8qi<mode>,
neon_vreinterpretv4hi<mode>, neon_vreinterpretv2si<mode>,
neon_vreinterpretv2sf<mode>, neon_vreinterpretdi<mode>):
Change VDX to VD_RE.
(neon_vld2_lane<mode>, neon_vst2_lane<mode>, neon_vld3_lane<mode>,
neon_vst3_lane<mode>, neon_vld4_lane<mode>, neon_vst4_lane<mode>):
Change VD iterator to VD_LANE, and VMQ iterator to VQ_HS.
* config/arm/arm_neon.h (float16x4x2_t, float16x8x2_t, float16x4x3_t,
float16x8x3_t, float16x4x4_t, float16x8x4_t, vcombine_f16,
vget_high_f16, vget_low_f16, vld1_f16, vld1q_f16, vst1_f16, vst1q_f16,
vst1_lane_f16, vst1q_lane_f16, vld2_f16, vld2q_f16, vld2_lane_f16,
vld2q_lane_f16, vld2_dup_f16, vst2_f16, vst2q_f16, vst2_lane_f16,
vst2q_lane_f16, vld3_f16, vld3q_f16, vld3_lane_f16, vld3q_lane_f16,
vld3_dup_f16, vst3_f16, vst3q_f16, vst3_lane_f16, vst3q_lane_f16,
vld4_f16, vld4q_f16, vld4_lane_f16, vld4q_lane_f16, vld4_dup_f16,
vst4_f16, vst4q_f16, vst4_lane_f16, vst4q_lane_f16): New.
From-SVN: r227541
2015-09-08 20:48:47 +02:00
|
|
|
(V4HF "") (V8HF "_q")
|
2016-09-23 11:54:44 +02:00
|
|
|
(V2SF "") (V4SF "_q")
|
|
|
|
(V4HF "") (V8HF "_q")
|
|
|
|
(DI "") (V2DI "_q")
|
|
|
|
(DF "") (V2DF "_q")
|
|
|
|
(HF "")])
|
2013-10-15 17:28:04 +02:00
|
|
|
|
2014-11-18 10:48:14 +01:00
|
|
|
(define_mode_attr pf [(V8QI "p") (V16QI "p") (V2SF "f") (V4SF "f")])
|
|
|
|
|
iterators.md: New file.
2010-08-09 Sofiane Naci <sofiane.naci@arm.com>
* config/arm/iterators.md: New file.
* config/arm/arm.md: Include iterators.md.
(QHSI): Move to new file.
(LTUGEU, cnb, optab, ior_xor): Likewise.
* config/arm/iwmmxt.md (VMMX): Move to new file.
(VSHFT, MMX_char): Likewise.
* config/arm/neon.md (VD): Move to new file.
(VDX, VDI, VQ, VQX, VQI, VQXMOV, VSTRUCT, VTAB, V_TAB_n, VW): Likewise.
(VN, VDQ, VDQW, VDQIW, VCVTF, VCVTI, VMD, VMQ, VMDQ, VMDI): Likewise.
(VMDQI, VX, VE, V64, V32, V_CVTTO, V_elem, V_ext, V_two_elem): Likewise.
(V_three_elem, V_four_elem, V_req, V_widen, V_narrow, V_HALF): Likewise.
(V_half,V_DOUBLE, V_double, V_double_width, V_cmp_result): Likewise.
(V_if_elem, V_s_elem, V_u_elem, V_uf_sclr, V_sz_elem, VD_dup): Likewise.
(V_PAIR, vqh_ops, vqhs_ops, VQH_mnem, VQH_sign, V_suf64): Likewise.
(scalar_mul_constraint,Is_float_mode, Scalar_mul_8_16): Likewise.
(Is_d_reg, V_mode_nunits): Likewise.
* config/arm/vec-common.md (VALL): Move to new file.
(VALLW, VINT, VINTW): Likewise.
From-SVN: r163058
2010-08-10 15:37:25 +02:00
|
|
|
;;----------------------------------------------------------------------------
|
|
|
|
;; Code attributes
|
|
|
|
;;----------------------------------------------------------------------------
|
|
|
|
|
|
|
|
;; Assembler mnemonics for vqh_ops and vqhs_ops iterators.
|
|
|
|
(define_code_attr VQH_mnem [(plus "vadd") (smin "vmin") (smax "vmax")
|
|
|
|
(umin "vmin") (umax "vmax")])
|
|
|
|
|
2013-10-15 17:28:04 +02:00
|
|
|
;; Type attributes for vqh_ops and vqhs_ops iterators.
|
|
|
|
(define_code_attr VQH_type [(plus "add") (smin "minmax") (smax "minmax")
|
|
|
|
(umin "minmax") (umax "minmax")])
|
|
|
|
|
iterators.md: New file.
2010-08-09 Sofiane Naci <sofiane.naci@arm.com>
* config/arm/iterators.md: New file.
* config/arm/arm.md: Include iterators.md.
(QHSI): Move to new file.
(LTUGEU, cnb, optab, ior_xor): Likewise.
* config/arm/iwmmxt.md (VMMX): Move to new file.
(VSHFT, MMX_char): Likewise.
* config/arm/neon.md (VD): Move to new file.
(VDX, VDI, VQ, VQX, VQI, VQXMOV, VSTRUCT, VTAB, V_TAB_n, VW): Likewise.
(VN, VDQ, VDQW, VDQIW, VCVTF, VCVTI, VMD, VMQ, VMDQ, VMDI): Likewise.
(VMDQI, VX, VE, V64, V32, V_CVTTO, V_elem, V_ext, V_two_elem): Likewise.
(V_three_elem, V_four_elem, V_req, V_widen, V_narrow, V_HALF): Likewise.
(V_half,V_DOUBLE, V_double, V_double_width, V_cmp_result): Likewise.
(V_if_elem, V_s_elem, V_u_elem, V_uf_sclr, V_sz_elem, VD_dup): Likewise.
(V_PAIR, vqh_ops, vqhs_ops, VQH_mnem, VQH_sign, V_suf64): Likewise.
(scalar_mul_constraint,Is_float_mode, Scalar_mul_8_16): Likewise.
(Is_d_reg, V_mode_nunits): Likewise.
* config/arm/vec-common.md (VALL): Move to new file.
(VALLW, VINT, VINTW): Likewise.
From-SVN: r163058
2010-08-10 15:37:25 +02:00
|
|
|
;; Signs of above, where relevant.
|
|
|
|
(define_code_attr VQH_sign [(plus "i") (smin "s") (smax "s") (umin "u")
|
|
|
|
(umax "u")])
|
|
|
|
|
|
|
|
(define_code_attr cnb [(ltu "CC_C") (geu "CC")])
|
|
|
|
(define_code_attr optab [(ltu "ltu") (geu "geu")])
|
2010-08-25 09:23:26 +02:00
|
|
|
|
|
|
|
;; Assembler mnemonics for signedness of widening operations.
|
|
|
|
(define_code_attr US [(sign_extend "s") (zero_extend "u")])
|
arm.c (arm_emit_coreregs_64bit_shift): Fix comment.
2012-11-13 Andrew Stubbs <ams@codesourcery.com>
Ulrich Weigand <ulrich.weigand@linaro.org>
* config/arm/arm.c (arm_emit_coreregs_64bit_shift): Fix comment.
* config/arm/arm.md (opt, opt_enabled): New attributes.
(enabled): Use opt_enabled.
(ashldi3, ashrdi3, lshrdi3): Add TARGET_NEON case.
(ashldi3): Allow general operands for TARGET_NEON case.
* config/arm/iterators.md (rshifts): New code iterator.
(shift, shifttype): New code attributes.
* config/arm/neon.md (UNSPEC_LOAD_COUNT): New unspec type.
(neon_load_count, ashldi3_neon_noclobber, ashldi3_neon,
signed_shift_di3_neon, unsigned_shift_di3_neon,
ashrdi3_neon_imm_noclobber, lshrdi3_neon_imm_noclobber,
<shift>di3_neon): New patterns.
Co-Authored-By: Ulrich Weigand <ulrich.weigand@linaro.org>
From-SVN: r193476
2012-11-13 14:31:50 +01:00
|
|
|
|
2014-09-02 17:57:56 +02:00
|
|
|
;; Signedness suffix for float->fixed conversions. Empty for signed
|
|
|
|
;; conversion.
|
|
|
|
(define_code_attr su_optab [(fix "") (unsigned_fix "u")])
|
|
|
|
|
|
|
|
;; Sign prefix to use in instruction type suffixes, i.e. s32, u32.
|
|
|
|
(define_code_attr su [(fix "s") (unsigned_fix "u")])
|
|
|
|
|
arm.c (arm_emit_coreregs_64bit_shift): Fix comment.
2012-11-13 Andrew Stubbs <ams@codesourcery.com>
Ulrich Weigand <ulrich.weigand@linaro.org>
* config/arm/arm.c (arm_emit_coreregs_64bit_shift): Fix comment.
* config/arm/arm.md (opt, opt_enabled): New attributes.
(enabled): Use opt_enabled.
(ashldi3, ashrdi3, lshrdi3): Add TARGET_NEON case.
(ashldi3): Allow general operands for TARGET_NEON case.
* config/arm/iterators.md (rshifts): New code iterator.
(shift, shifttype): New code attributes.
* config/arm/neon.md (UNSPEC_LOAD_COUNT): New unspec type.
(neon_load_count, ashldi3_neon_noclobber, ashldi3_neon,
signed_shift_di3_neon, unsigned_shift_di3_neon,
ashrdi3_neon_imm_noclobber, lshrdi3_neon_imm_noclobber,
<shift>di3_neon): New patterns.
Co-Authored-By: Ulrich Weigand <ulrich.weigand@linaro.org>
From-SVN: r193476
2012-11-13 14:31:50 +01:00
|
|
|
;; Right shifts
|
|
|
|
(define_code_attr shift [(ashiftrt "ashr") (lshiftrt "lshr")])
|
|
|
|
(define_code_attr shifttype [(ashiftrt "signed") (lshiftrt "unsigned")])
|
|
|
|
|
[PATCH 8/17][ARM] Add VFP FP16 arithmetic instructions.
gcc/
2016-09-23 Matthew Wahab <matthew.wahab@arm.com>
* config/arm/iterators.md (Code iterators): Fix some white-space
in the comments.
(GLTE): New.
(ABSNEG): New
(FCVT): Moved from vfp.md.
(VCVT_HF_US_N): New.
(VCVT_SI_US_N): New.
(VCVT_HF_US): New.
(VCVTH_US): New.
(FP16_RND): New.
(absneg_str): New.
(FCVTI32typename): Moved from vfp.md.
(sup): Add UNSPEC_VCVTA_S, UNSPEC_VCVTA_U, UNSPEC_VCVTM_S,
UNSPEC_VCVTM_U, UNSPEC_VCVTN_S, UNSPEC_VCVTN_U, UNSPEC_VCVTP_S,
UNSPEC_VCVTP_U, UNSPEC_VCVT_HF_S_N, UNSPEC_VCVT_HF_U_N,
UNSPEC_VCVT_SI_S_N, UNSPEC_VCVT_SI_U_N, UNSPEC_VCVTH_S_N,
UNSPEC_VCVTH_U_N, UNSPEC_VCVTH_S and UNSPEC_VCVTH_U.
(vcvth_op): New.
(fp16_rnd_str): New.
(fp16_rnd_insn): New.
* config/arm/unspecs.md (UNSPEC_VCVT_HF_S_N): New.
(UNSPEC_VCVT_HF_U_N): New.
(UNSPEC_VCVT_SI_S_N): New.
(UNSPEC_VCVT_SI_U_N): New.
(UNSPEC_VCVTH_S): New.
(UNSPEC_VCVTH_U): New.
(UNSPEC_VCVTA_S): New.
(UNSPEC_VCVTA_U): New.
(UNSPEC_VCVTM_S): New.
(UNSPEC_VCVTM_U): New.
(UNSPEC_VCVTN_S): New.
(UNSPEC_VCVTN_U): New.
(UNSPEC_VCVTP_S): New.
(UNSPEC_VCVTP_U): New.
(UNSPEC_VCVTP_S): New.
(UNSPEC_VCVTP_U): New.
(UNSPEC_VRND): New.
(UNSPEC_VRNDA): New.
(UNSPEC_VRNDI): New.
(UNSPEC_VRNDM): New.
(UNSPEC_VRNDN): New.
(UNSPEC_VRNDP): New.
(UNSPEC_VRNDX): New.
* config/arm/vfp.md (<absneg_str>hf2): New.
(neon_vabshf): New.
(neon_v<fp16_rnd_str>hf): New.
(neon_vrndihf): New.
(addhf3): New.
(subhf3): New.
(divhf3): New.
(mulhf3): New.
(*mulsf3neghf_vfp): New.
(*negmulhf3_vfp): New.
(*mulsf3addhf_vfp): New.
(*mulhf3subhf_vfp): New.
(*mulhf3neghfaddhf_vfp): New.
(*mulhf3neghfsubhf_vfp): New.
(fmahf4): New.
(neon_vfmahf): New.
(fmsubhf4_fp16): New.
(neon_vfmshf): New.
(*fnmsubhf4): New.
(*fnmaddhf4): New.
(neon_vsqrthf): New.
(neon_vrsqrtshf): New.
(FCVT): Move to iterators.md.
(FCVTI32typename): Likewise.
(neon_vcvth<sup>hf): New.
(neon_vcvth<sup>si): New.
(neon_vcvth<sup>_nhf_unspec): New.
(neon_vcvth<sup>_nhf): New.
(neon_vcvth<sup>_nsi_unspec): New.
(neon_vcvth<sup>_nsi): New.
(neon_vcvt<vcvth_op>h<sup>si): New.
(neon_<fmaxmin_op>hf): New.
testsuite/
2016-09-23 Matthew Wahab <matthew.wahab@arm.com>
* gcc.target/arm/armv8_2-fp16-arith-1.c: New.
* gcc.target/arm/armv8_2-fp16-conv-1.c: New.
From-SVN: r240411
2016-09-23 11:46:26 +02:00
|
|
|
;; String reprentations of operations on the sign of a number.
|
|
|
|
(define_code_attr absneg_str [(abs "abs") (neg "neg")])
|
|
|
|
|
|
|
|
;; Conversions.
|
|
|
|
(define_code_attr FCVTI32typename [(unsigned_float "u32") (float "s32")])
|
|
|
|
|
2016-09-23 11:54:44 +02:00
|
|
|
(define_code_attr float_sup [(unsigned_float "u") (float "s")])
|
|
|
|
|
|
|
|
(define_code_attr float_SUP [(unsigned_float "U") (float "S")])
|
|
|
|
|
2012-11-26 13:33:02 +01:00
|
|
|
;;----------------------------------------------------------------------------
|
|
|
|
;; Int attributes
|
|
|
|
;;----------------------------------------------------------------------------
|
|
|
|
|
2014-11-18 10:48:14 +01:00
|
|
|
;; Mapping between vector UNSPEC operations and the signed ('s'),
|
|
|
|
;; unsigned ('u'), poly ('p') or float ('f') nature of their data type.
|
|
|
|
(define_int_attr sup [
|
|
|
|
(UNSPEC_VADDL_S "s") (UNSPEC_VADDL_U "u")
|
|
|
|
(UNSPEC_VADDW_S "s") (UNSPEC_VADDW_U "u")
|
|
|
|
(UNSPEC_VRHADD_S "s") (UNSPEC_VRHADD_U "u")
|
|
|
|
(UNSPEC_VHADD_S "s") (UNSPEC_VHADD_U "u")
|
|
|
|
(UNSPEC_VQADD_S "s") (UNSPEC_VQADD_U "u")
|
|
|
|
(UNSPEC_VMLAL_S "s") (UNSPEC_VMLAL_U "u")
|
|
|
|
(UNSPEC_VMLAL_S_LANE "s") (UNSPEC_VMLAL_U_LANE "u")
|
|
|
|
(UNSPEC_VMLSL_S "s") (UNSPEC_VMLSL_U "u")
|
|
|
|
(UNSPEC_VMLSL_S_LANE "s") (UNSPEC_VMLSL_U_LANE "u")
|
|
|
|
(UNSPEC_VMULL_S "s") (UNSPEC_VMULL_U "u") (UNSPEC_VMULL_P "p")
|
|
|
|
(UNSPEC_VMULL_S_LANE "s") (UNSPEC_VMULL_U_LANE "u")
|
|
|
|
(UNSPEC_VSUBL_S "s") (UNSPEC_VSUBL_U "u")
|
|
|
|
(UNSPEC_VSUBW_S "s") (UNSPEC_VSUBW_U "u")
|
|
|
|
(UNSPEC_VHSUB_S "s") (UNSPEC_VHSUB_U "u")
|
|
|
|
(UNSPEC_VQSUB_S "s") (UNSPEC_VQSUB_U "u")
|
|
|
|
(UNSPEC_VABD_S "s") (UNSPEC_VABD_U "u")
|
|
|
|
(UNSPEC_VABDL_S "s") (UNSPEC_VABDL_U "u")
|
|
|
|
(UNSPEC_VMAX "s") (UNSPEC_VMAX_U "u")
|
|
|
|
(UNSPEC_VMIN "s") (UNSPEC_VMIN_U "u")
|
|
|
|
(UNSPEC_VPADDL_S "s") (UNSPEC_VPADDL_U "u")
|
|
|
|
(UNSPEC_VPADAL_S "s") (UNSPEC_VPADAL_U "u")
|
|
|
|
(UNSPEC_VPMAX "s") (UNSPEC_VPMAX_U "u")
|
|
|
|
(UNSPEC_VPMIN "s") (UNSPEC_VPMIN_U "u")
|
|
|
|
(UNSPEC_VCVT_S "s") (UNSPEC_VCVT_U "u")
|
[PATCH 8/17][ARM] Add VFP FP16 arithmetic instructions.
gcc/
2016-09-23 Matthew Wahab <matthew.wahab@arm.com>
* config/arm/iterators.md (Code iterators): Fix some white-space
in the comments.
(GLTE): New.
(ABSNEG): New
(FCVT): Moved from vfp.md.
(VCVT_HF_US_N): New.
(VCVT_SI_US_N): New.
(VCVT_HF_US): New.
(VCVTH_US): New.
(FP16_RND): New.
(absneg_str): New.
(FCVTI32typename): Moved from vfp.md.
(sup): Add UNSPEC_VCVTA_S, UNSPEC_VCVTA_U, UNSPEC_VCVTM_S,
UNSPEC_VCVTM_U, UNSPEC_VCVTN_S, UNSPEC_VCVTN_U, UNSPEC_VCVTP_S,
UNSPEC_VCVTP_U, UNSPEC_VCVT_HF_S_N, UNSPEC_VCVT_HF_U_N,
UNSPEC_VCVT_SI_S_N, UNSPEC_VCVT_SI_U_N, UNSPEC_VCVTH_S_N,
UNSPEC_VCVTH_U_N, UNSPEC_VCVTH_S and UNSPEC_VCVTH_U.
(vcvth_op): New.
(fp16_rnd_str): New.
(fp16_rnd_insn): New.
* config/arm/unspecs.md (UNSPEC_VCVT_HF_S_N): New.
(UNSPEC_VCVT_HF_U_N): New.
(UNSPEC_VCVT_SI_S_N): New.
(UNSPEC_VCVT_SI_U_N): New.
(UNSPEC_VCVTH_S): New.
(UNSPEC_VCVTH_U): New.
(UNSPEC_VCVTA_S): New.
(UNSPEC_VCVTA_U): New.
(UNSPEC_VCVTM_S): New.
(UNSPEC_VCVTM_U): New.
(UNSPEC_VCVTN_S): New.
(UNSPEC_VCVTN_U): New.
(UNSPEC_VCVTP_S): New.
(UNSPEC_VCVTP_U): New.
(UNSPEC_VCVTP_S): New.
(UNSPEC_VCVTP_U): New.
(UNSPEC_VRND): New.
(UNSPEC_VRNDA): New.
(UNSPEC_VRNDI): New.
(UNSPEC_VRNDM): New.
(UNSPEC_VRNDN): New.
(UNSPEC_VRNDP): New.
(UNSPEC_VRNDX): New.
* config/arm/vfp.md (<absneg_str>hf2): New.
(neon_vabshf): New.
(neon_v<fp16_rnd_str>hf): New.
(neon_vrndihf): New.
(addhf3): New.
(subhf3): New.
(divhf3): New.
(mulhf3): New.
(*mulsf3neghf_vfp): New.
(*negmulhf3_vfp): New.
(*mulsf3addhf_vfp): New.
(*mulhf3subhf_vfp): New.
(*mulhf3neghfaddhf_vfp): New.
(*mulhf3neghfsubhf_vfp): New.
(fmahf4): New.
(neon_vfmahf): New.
(fmsubhf4_fp16): New.
(neon_vfmshf): New.
(*fnmsubhf4): New.
(*fnmaddhf4): New.
(neon_vsqrthf): New.
(neon_vrsqrtshf): New.
(FCVT): Move to iterators.md.
(FCVTI32typename): Likewise.
(neon_vcvth<sup>hf): New.
(neon_vcvth<sup>si): New.
(neon_vcvth<sup>_nhf_unspec): New.
(neon_vcvth<sup>_nhf): New.
(neon_vcvth<sup>_nsi_unspec): New.
(neon_vcvth<sup>_nsi): New.
(neon_vcvt<vcvth_op>h<sup>si): New.
(neon_<fmaxmin_op>hf): New.
testsuite/
2016-09-23 Matthew Wahab <matthew.wahab@arm.com>
* gcc.target/arm/armv8_2-fp16-arith-1.c: New.
* gcc.target/arm/armv8_2-fp16-conv-1.c: New.
From-SVN: r240411
2016-09-23 11:46:26 +02:00
|
|
|
(UNSPEC_VCVTA_S "s") (UNSPEC_VCVTA_U "u")
|
|
|
|
(UNSPEC_VCVTM_S "s") (UNSPEC_VCVTM_U "u")
|
|
|
|
(UNSPEC_VCVTN_S "s") (UNSPEC_VCVTN_U "u")
|
|
|
|
(UNSPEC_VCVTP_S "s") (UNSPEC_VCVTP_U "u")
|
2014-11-18 10:48:14 +01:00
|
|
|
(UNSPEC_VCVT_S_N "s") (UNSPEC_VCVT_U_N "u")
|
[PATCH 8/17][ARM] Add VFP FP16 arithmetic instructions.
gcc/
2016-09-23 Matthew Wahab <matthew.wahab@arm.com>
* config/arm/iterators.md (Code iterators): Fix some white-space
in the comments.
(GLTE): New.
(ABSNEG): New
(FCVT): Moved from vfp.md.
(VCVT_HF_US_N): New.
(VCVT_SI_US_N): New.
(VCVT_HF_US): New.
(VCVTH_US): New.
(FP16_RND): New.
(absneg_str): New.
(FCVTI32typename): Moved from vfp.md.
(sup): Add UNSPEC_VCVTA_S, UNSPEC_VCVTA_U, UNSPEC_VCVTM_S,
UNSPEC_VCVTM_U, UNSPEC_VCVTN_S, UNSPEC_VCVTN_U, UNSPEC_VCVTP_S,
UNSPEC_VCVTP_U, UNSPEC_VCVT_HF_S_N, UNSPEC_VCVT_HF_U_N,
UNSPEC_VCVT_SI_S_N, UNSPEC_VCVT_SI_U_N, UNSPEC_VCVTH_S_N,
UNSPEC_VCVTH_U_N, UNSPEC_VCVTH_S and UNSPEC_VCVTH_U.
(vcvth_op): New.
(fp16_rnd_str): New.
(fp16_rnd_insn): New.
* config/arm/unspecs.md (UNSPEC_VCVT_HF_S_N): New.
(UNSPEC_VCVT_HF_U_N): New.
(UNSPEC_VCVT_SI_S_N): New.
(UNSPEC_VCVT_SI_U_N): New.
(UNSPEC_VCVTH_S): New.
(UNSPEC_VCVTH_U): New.
(UNSPEC_VCVTA_S): New.
(UNSPEC_VCVTA_U): New.
(UNSPEC_VCVTM_S): New.
(UNSPEC_VCVTM_U): New.
(UNSPEC_VCVTN_S): New.
(UNSPEC_VCVTN_U): New.
(UNSPEC_VCVTP_S): New.
(UNSPEC_VCVTP_U): New.
(UNSPEC_VCVTP_S): New.
(UNSPEC_VCVTP_U): New.
(UNSPEC_VRND): New.
(UNSPEC_VRNDA): New.
(UNSPEC_VRNDI): New.
(UNSPEC_VRNDM): New.
(UNSPEC_VRNDN): New.
(UNSPEC_VRNDP): New.
(UNSPEC_VRNDX): New.
* config/arm/vfp.md (<absneg_str>hf2): New.
(neon_vabshf): New.
(neon_v<fp16_rnd_str>hf): New.
(neon_vrndihf): New.
(addhf3): New.
(subhf3): New.
(divhf3): New.
(mulhf3): New.
(*mulsf3neghf_vfp): New.
(*negmulhf3_vfp): New.
(*mulsf3addhf_vfp): New.
(*mulhf3subhf_vfp): New.
(*mulhf3neghfaddhf_vfp): New.
(*mulhf3neghfsubhf_vfp): New.
(fmahf4): New.
(neon_vfmahf): New.
(fmsubhf4_fp16): New.
(neon_vfmshf): New.
(*fnmsubhf4): New.
(*fnmaddhf4): New.
(neon_vsqrthf): New.
(neon_vrsqrtshf): New.
(FCVT): Move to iterators.md.
(FCVTI32typename): Likewise.
(neon_vcvth<sup>hf): New.
(neon_vcvth<sup>si): New.
(neon_vcvth<sup>_nhf_unspec): New.
(neon_vcvth<sup>_nhf): New.
(neon_vcvth<sup>_nsi_unspec): New.
(neon_vcvth<sup>_nsi): New.
(neon_vcvt<vcvth_op>h<sup>si): New.
(neon_<fmaxmin_op>hf): New.
testsuite/
2016-09-23 Matthew Wahab <matthew.wahab@arm.com>
* gcc.target/arm/armv8_2-fp16-arith-1.c: New.
* gcc.target/arm/armv8_2-fp16-conv-1.c: New.
From-SVN: r240411
2016-09-23 11:46:26 +02:00
|
|
|
(UNSPEC_VCVT_HF_S_N "s") (UNSPEC_VCVT_HF_U_N "u")
|
|
|
|
(UNSPEC_VCVT_SI_S_N "s") (UNSPEC_VCVT_SI_U_N "u")
|
2014-11-18 10:48:14 +01:00
|
|
|
(UNSPEC_VQMOVN_S "s") (UNSPEC_VQMOVN_U "u")
|
|
|
|
(UNSPEC_VMOVL_S "s") (UNSPEC_VMOVL_U "u")
|
|
|
|
(UNSPEC_VSHL_S "s") (UNSPEC_VSHL_U "u")
|
|
|
|
(UNSPEC_VRSHL_S "s") (UNSPEC_VRSHL_U "u")
|
|
|
|
(UNSPEC_VQSHL_S "s") (UNSPEC_VQSHL_U "u")
|
|
|
|
(UNSPEC_VQRSHL_S "s") (UNSPEC_VQRSHL_U "u")
|
|
|
|
(UNSPEC_VSHR_S_N "s") (UNSPEC_VSHR_U_N "u")
|
|
|
|
(UNSPEC_VRSHR_S_N "s") (UNSPEC_VRSHR_U_N "u")
|
|
|
|
(UNSPEC_VQSHRN_S_N "s") (UNSPEC_VQSHRN_U_N "u")
|
|
|
|
(UNSPEC_VQRSHRN_S_N "s") (UNSPEC_VQRSHRN_U_N "u")
|
|
|
|
(UNSPEC_VQSHL_S_N "s") (UNSPEC_VQSHL_U_N "u")
|
|
|
|
(UNSPEC_VSHLL_S_N "s") (UNSPEC_VSHLL_U_N "u")
|
|
|
|
(UNSPEC_VSRA_S_N "s") (UNSPEC_VSRA_U_N "u")
|
|
|
|
(UNSPEC_VRSRA_S_N "s") (UNSPEC_VRSRA_U_N "u")
|
[PATCH 8/17][ARM] Add VFP FP16 arithmetic instructions.
gcc/
2016-09-23 Matthew Wahab <matthew.wahab@arm.com>
* config/arm/iterators.md (Code iterators): Fix some white-space
in the comments.
(GLTE): New.
(ABSNEG): New
(FCVT): Moved from vfp.md.
(VCVT_HF_US_N): New.
(VCVT_SI_US_N): New.
(VCVT_HF_US): New.
(VCVTH_US): New.
(FP16_RND): New.
(absneg_str): New.
(FCVTI32typename): Moved from vfp.md.
(sup): Add UNSPEC_VCVTA_S, UNSPEC_VCVTA_U, UNSPEC_VCVTM_S,
UNSPEC_VCVTM_U, UNSPEC_VCVTN_S, UNSPEC_VCVTN_U, UNSPEC_VCVTP_S,
UNSPEC_VCVTP_U, UNSPEC_VCVT_HF_S_N, UNSPEC_VCVT_HF_U_N,
UNSPEC_VCVT_SI_S_N, UNSPEC_VCVT_SI_U_N, UNSPEC_VCVTH_S_N,
UNSPEC_VCVTH_U_N, UNSPEC_VCVTH_S and UNSPEC_VCVTH_U.
(vcvth_op): New.
(fp16_rnd_str): New.
(fp16_rnd_insn): New.
* config/arm/unspecs.md (UNSPEC_VCVT_HF_S_N): New.
(UNSPEC_VCVT_HF_U_N): New.
(UNSPEC_VCVT_SI_S_N): New.
(UNSPEC_VCVT_SI_U_N): New.
(UNSPEC_VCVTH_S): New.
(UNSPEC_VCVTH_U): New.
(UNSPEC_VCVTA_S): New.
(UNSPEC_VCVTA_U): New.
(UNSPEC_VCVTM_S): New.
(UNSPEC_VCVTM_U): New.
(UNSPEC_VCVTN_S): New.
(UNSPEC_VCVTN_U): New.
(UNSPEC_VCVTP_S): New.
(UNSPEC_VCVTP_U): New.
(UNSPEC_VCVTP_S): New.
(UNSPEC_VCVTP_U): New.
(UNSPEC_VRND): New.
(UNSPEC_VRNDA): New.
(UNSPEC_VRNDI): New.
(UNSPEC_VRNDM): New.
(UNSPEC_VRNDN): New.
(UNSPEC_VRNDP): New.
(UNSPEC_VRNDX): New.
* config/arm/vfp.md (<absneg_str>hf2): New.
(neon_vabshf): New.
(neon_v<fp16_rnd_str>hf): New.
(neon_vrndihf): New.
(addhf3): New.
(subhf3): New.
(divhf3): New.
(mulhf3): New.
(*mulsf3neghf_vfp): New.
(*negmulhf3_vfp): New.
(*mulsf3addhf_vfp): New.
(*mulhf3subhf_vfp): New.
(*mulhf3neghfaddhf_vfp): New.
(*mulhf3neghfsubhf_vfp): New.
(fmahf4): New.
(neon_vfmahf): New.
(fmsubhf4_fp16): New.
(neon_vfmshf): New.
(*fnmsubhf4): New.
(*fnmaddhf4): New.
(neon_vsqrthf): New.
(neon_vrsqrtshf): New.
(FCVT): Move to iterators.md.
(FCVTI32typename): Likewise.
(neon_vcvth<sup>hf): New.
(neon_vcvth<sup>si): New.
(neon_vcvth<sup>_nhf_unspec): New.
(neon_vcvth<sup>_nhf): New.
(neon_vcvth<sup>_nsi_unspec): New.
(neon_vcvth<sup>_nsi): New.
(neon_vcvt<vcvth_op>h<sup>si): New.
(neon_<fmaxmin_op>hf): New.
testsuite/
2016-09-23 Matthew Wahab <matthew.wahab@arm.com>
* gcc.target/arm/armv8_2-fp16-arith-1.c: New.
* gcc.target/arm/armv8_2-fp16-conv-1.c: New.
From-SVN: r240411
2016-09-23 11:46:26 +02:00
|
|
|
(UNSPEC_VCVTH_S "s") (UNSPEC_VCVTH_U "u")
|
2014-11-18 10:48:14 +01:00
|
|
|
])
|
|
|
|
|
[PATCH 8/17][ARM] Add VFP FP16 arithmetic instructions.
gcc/
2016-09-23 Matthew Wahab <matthew.wahab@arm.com>
* config/arm/iterators.md (Code iterators): Fix some white-space
in the comments.
(GLTE): New.
(ABSNEG): New
(FCVT): Moved from vfp.md.
(VCVT_HF_US_N): New.
(VCVT_SI_US_N): New.
(VCVT_HF_US): New.
(VCVTH_US): New.
(FP16_RND): New.
(absneg_str): New.
(FCVTI32typename): Moved from vfp.md.
(sup): Add UNSPEC_VCVTA_S, UNSPEC_VCVTA_U, UNSPEC_VCVTM_S,
UNSPEC_VCVTM_U, UNSPEC_VCVTN_S, UNSPEC_VCVTN_U, UNSPEC_VCVTP_S,
UNSPEC_VCVTP_U, UNSPEC_VCVT_HF_S_N, UNSPEC_VCVT_HF_U_N,
UNSPEC_VCVT_SI_S_N, UNSPEC_VCVT_SI_U_N, UNSPEC_VCVTH_S_N,
UNSPEC_VCVTH_U_N, UNSPEC_VCVTH_S and UNSPEC_VCVTH_U.
(vcvth_op): New.
(fp16_rnd_str): New.
(fp16_rnd_insn): New.
* config/arm/unspecs.md (UNSPEC_VCVT_HF_S_N): New.
(UNSPEC_VCVT_HF_U_N): New.
(UNSPEC_VCVT_SI_S_N): New.
(UNSPEC_VCVT_SI_U_N): New.
(UNSPEC_VCVTH_S): New.
(UNSPEC_VCVTH_U): New.
(UNSPEC_VCVTA_S): New.
(UNSPEC_VCVTA_U): New.
(UNSPEC_VCVTM_S): New.
(UNSPEC_VCVTM_U): New.
(UNSPEC_VCVTN_S): New.
(UNSPEC_VCVTN_U): New.
(UNSPEC_VCVTP_S): New.
(UNSPEC_VCVTP_U): New.
(UNSPEC_VCVTP_S): New.
(UNSPEC_VCVTP_U): New.
(UNSPEC_VRND): New.
(UNSPEC_VRNDA): New.
(UNSPEC_VRNDI): New.
(UNSPEC_VRNDM): New.
(UNSPEC_VRNDN): New.
(UNSPEC_VRNDP): New.
(UNSPEC_VRNDX): New.
* config/arm/vfp.md (<absneg_str>hf2): New.
(neon_vabshf): New.
(neon_v<fp16_rnd_str>hf): New.
(neon_vrndihf): New.
(addhf3): New.
(subhf3): New.
(divhf3): New.
(mulhf3): New.
(*mulsf3neghf_vfp): New.
(*negmulhf3_vfp): New.
(*mulsf3addhf_vfp): New.
(*mulhf3subhf_vfp): New.
(*mulhf3neghfaddhf_vfp): New.
(*mulhf3neghfsubhf_vfp): New.
(fmahf4): New.
(neon_vfmahf): New.
(fmsubhf4_fp16): New.
(neon_vfmshf): New.
(*fnmsubhf4): New.
(*fnmaddhf4): New.
(neon_vsqrthf): New.
(neon_vrsqrtshf): New.
(FCVT): Move to iterators.md.
(FCVTI32typename): Likewise.
(neon_vcvth<sup>hf): New.
(neon_vcvth<sup>si): New.
(neon_vcvth<sup>_nhf_unspec): New.
(neon_vcvth<sup>_nhf): New.
(neon_vcvth<sup>_nsi_unspec): New.
(neon_vcvth<sup>_nsi): New.
(neon_vcvt<vcvth_op>h<sup>si): New.
(neon_<fmaxmin_op>hf): New.
testsuite/
2016-09-23 Matthew Wahab <matthew.wahab@arm.com>
* gcc.target/arm/armv8_2-fp16-arith-1.c: New.
* gcc.target/arm/armv8_2-fp16-conv-1.c: New.
From-SVN: r240411
2016-09-23 11:46:26 +02:00
|
|
|
(define_int_attr vcvth_op
|
|
|
|
[(UNSPEC_VCVTA_S "a") (UNSPEC_VCVTA_U "a")
|
|
|
|
(UNSPEC_VCVTM_S "m") (UNSPEC_VCVTM_U "m")
|
|
|
|
(UNSPEC_VCVTN_S "n") (UNSPEC_VCVTN_U "n")
|
|
|
|
(UNSPEC_VCVTP_S "p") (UNSPEC_VCVTP_U "p")])
|
|
|
|
|
|
|
|
(define_int_attr fp16_rnd_str
|
|
|
|
[(UNSPEC_VRND "rnd") (UNSPEC_VRNDA "rnda")
|
|
|
|
(UNSPEC_VRNDM "rndm") (UNSPEC_VRNDN "rndn")
|
|
|
|
(UNSPEC_VRNDP "rndp") (UNSPEC_VRNDX "rndx")])
|
|
|
|
|
|
|
|
(define_int_attr fp16_rnd_insn
|
|
|
|
[(UNSPEC_VRND "vrintz") (UNSPEC_VRNDA "vrinta")
|
|
|
|
(UNSPEC_VRNDM "vrintm") (UNSPEC_VRNDN "vrintn")
|
|
|
|
(UNSPEC_VRNDP "vrintp") (UNSPEC_VRNDX "vrintx")])
|
|
|
|
|
2015-04-23 18:19:26 +02:00
|
|
|
(define_int_attr cmp_op_unsp [(UNSPEC_VCEQ "eq") (UNSPEC_VCGT "gt")
|
2016-09-23 11:54:44 +02:00
|
|
|
(UNSPEC_VCGE "ge") (UNSPEC_VCLE "le")
|
|
|
|
(UNSPEC_VCLT "lt") (UNSPEC_VCAGE "ge")
|
|
|
|
(UNSPEC_VCAGT "gt") (UNSPEC_VCALE "le")
|
|
|
|
(UNSPEC_VCALT "lt")])
|
2015-04-23 18:19:26 +02:00
|
|
|
|
2014-11-18 10:48:14 +01:00
|
|
|
(define_int_attr r [
|
|
|
|
(UNSPEC_VRHADD_S "r") (UNSPEC_VRHADD_U "r")
|
|
|
|
(UNSPEC_VHADD_S "") (UNSPEC_VHADD_U "")
|
|
|
|
(UNSPEC_VADDHN "") (UNSPEC_VRADDHN "r")
|
|
|
|
(UNSPEC_VQDMULH "") (UNSPEC_VQRDMULH "r")
|
|
|
|
(UNSPEC_VQDMULH_LANE "") (UNSPEC_VQRDMULH_LANE "r")
|
|
|
|
(UNSPEC_VSUBHN "") (UNSPEC_VRSUBHN "r")
|
|
|
|
])
|
|
|
|
|
|
|
|
(define_int_attr maxmin [
|
|
|
|
(UNSPEC_VMAX "max") (UNSPEC_VMAX_U "max")
|
|
|
|
(UNSPEC_VMIN "min") (UNSPEC_VMIN_U "min")
|
|
|
|
(UNSPEC_VPMAX "max") (UNSPEC_VPMAX_U "max")
|
|
|
|
(UNSPEC_VPMIN "min") (UNSPEC_VPMIN_U "min")
|
|
|
|
])
|
|
|
|
|
2015-12-23 11:28:18 +01:00
|
|
|
(define_int_attr fmaxmin [
|
|
|
|
(UNSPEC_VMAXNM "fmax") (UNSPEC_VMINNM "fmin")])
|
|
|
|
|
|
|
|
(define_int_attr fmaxmin_op [
|
|
|
|
(UNSPEC_VMAXNM "vmaxnm") (UNSPEC_VMINNM "vminnm")
|
|
|
|
])
|
|
|
|
|
2014-11-18 10:48:14 +01:00
|
|
|
(define_int_attr shift_op [
|
|
|
|
(UNSPEC_VSHL_S "shl") (UNSPEC_VSHL_U "shl")
|
|
|
|
(UNSPEC_VRSHL_S "rshl") (UNSPEC_VRSHL_U "rshl")
|
|
|
|
(UNSPEC_VQSHL_S "qshl") (UNSPEC_VQSHL_U "qshl")
|
|
|
|
(UNSPEC_VQRSHL_S "qrshl") (UNSPEC_VQRSHL_U "qrshl")
|
|
|
|
(UNSPEC_VSHR_S_N "shr") (UNSPEC_VSHR_U_N "shr")
|
|
|
|
(UNSPEC_VRSHR_S_N "rshr") (UNSPEC_VRSHR_U_N "rshr")
|
|
|
|
(UNSPEC_VSHRN_N "shrn") (UNSPEC_VRSHRN_N "rshrn")
|
|
|
|
(UNSPEC_VQRSHRN_S_N "qrshrn") (UNSPEC_VQRSHRN_U_N "qrshrn")
|
|
|
|
(UNSPEC_VQSHRN_S_N "qshrn") (UNSPEC_VQSHRN_U_N "qshrn")
|
|
|
|
(UNSPEC_VQSHRUN_N "qshrun") (UNSPEC_VQRSHRUN_N "qrshrun")
|
|
|
|
(UNSPEC_VSRA_S_N "sra") (UNSPEC_VSRA_U_N "sra")
|
|
|
|
(UNSPEC_VRSRA_S_N "rsra") (UNSPEC_VRSRA_U_N "rsra")
|
|
|
|
])
|
|
|
|
|
2012-11-26 13:33:02 +01:00
|
|
|
;; Standard names for floating point to integral rounding instructions.
|
|
|
|
(define_int_attr vrint_pattern [(UNSPEC_VRINTZ "btrunc") (UNSPEC_VRINTP "ceil")
|
|
|
|
(UNSPEC_VRINTA "round") (UNSPEC_VRINTM "floor")
|
|
|
|
(UNSPEC_VRINTR "nearbyint") (UNSPEC_VRINTX "rint")])
|
|
|
|
|
|
|
|
;; Suffixes for vrint instructions specifying rounding modes.
|
|
|
|
(define_int_attr vrint_variant [(UNSPEC_VRINTZ "z") (UNSPEC_VRINTP "p")
|
|
|
|
(UNSPEC_VRINTA "a") (UNSPEC_VRINTM "m")
|
|
|
|
(UNSPEC_VRINTR "r") (UNSPEC_VRINTX "x")])
|
|
|
|
|
|
|
|
;; Some of the vrint instuctions are predicable.
|
|
|
|
(define_int_attr vrint_predicable [(UNSPEC_VRINTZ "yes") (UNSPEC_VRINTP "no")
|
|
|
|
(UNSPEC_VRINTA "no") (UNSPEC_VRINTM "no")
|
|
|
|
(UNSPEC_VRINTR "yes") (UNSPEC_VRINTX "yes")])
|
2012-12-06 10:55:45 +01:00
|
|
|
|
2013-11-28 17:36:07 +01:00
|
|
|
(define_int_attr vrint_conds [(UNSPEC_VRINTZ "nocond") (UNSPEC_VRINTP "unconditional")
|
|
|
|
(UNSPEC_VRINTA "unconditional") (UNSPEC_VRINTM "unconditional")
|
|
|
|
(UNSPEC_VRINTR "nocond") (UNSPEC_VRINTX "nocond")])
|
|
|
|
|
2012-12-06 10:55:45 +01:00
|
|
|
(define_int_attr nvrint_variant [(UNSPEC_NVRINTZ "z") (UNSPEC_NVRINTP "p")
|
|
|
|
(UNSPEC_NVRINTA "a") (UNSPEC_NVRINTM "m")
|
|
|
|
(UNSPEC_NVRINTX "x") (UNSPEC_NVRINTN "n")])
|
2013-12-19 18:55:38 +01:00
|
|
|
|
|
|
|
(define_int_attr crc_variant [(UNSPEC_CRC32B "crc32b") (UNSPEC_CRC32H "crc32h")
|
|
|
|
(UNSPEC_CRC32W "crc32w") (UNSPEC_CRC32CB "crc32cb")
|
|
|
|
(UNSPEC_CRC32CH "crc32ch") (UNSPEC_CRC32CW "crc32cw")])
|
|
|
|
|
|
|
|
(define_int_attr crc_mode [(UNSPEC_CRC32B "QI") (UNSPEC_CRC32H "HI")
|
|
|
|
(UNSPEC_CRC32W "SI") (UNSPEC_CRC32CB "QI")
|
|
|
|
(UNSPEC_CRC32CH "HI") (UNSPEC_CRC32CW "SI")])
|
|
|
|
|
arm.c (enum arm_builtins): Add crypto builtins.
2013-12-19 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
* config/arm/arm.c (enum arm_builtins): Add crypto builtins.
(arm_init_neon_builtins): Handle crypto builtins.
(bdesc_2arg): Likewise.
(bdesc_1arg): Likewise.
(bdesc_3arg): New table.
(arm_expand_ternop_builtin): New function.
(arm_expand_unop_builtin): Handle sha1h explicitly.
(arm_expand_builtin): Handle ternary builtins.
* config/arm/arm.h (TARGET_CPU_CPP_BUILTINS):
Define __ARM_FEATURE_CRYPTO.
* config/arm/arm.md: Include crypto.md.
(is_neon_type): Add crypto types.
* config/arm/arm_neon_builtins.def: Add TImode reinterprets.
* config/arm/crypto.def: New.
* config/arm/crypto.md: Likewise.
* config/arm/iterators.md (CRYPTO_UNARY): New int iterator.
(CRYPTO_BINARY): Likewise.
(CRYPTO_TERNARY): Likewise.
(CRYPTO_SELECTING): Likewise.
(crypto_pattern): New int attribute.
(crypto_size_sfx): Likewise.
(crypto_mode): Likewise.
(crypto_type): Likewise.
* config/arm/neon-gen.ml: Handle poly64_t and poly128_t types.
Handle crypto intrinsics.
* config/arm/neon.ml: Add support for poly64 and polt128 types
and intrinsics. Define crypto intrinsics.
* config/arm/neon.md (neon_vreinterpretti<mode>): New pattern.
(neon_vreinterpretv16qi<mode>): Use VQXMOV mode iterator.
(neon_vreinterpretv8hi<mode>): Likewise.
(neon_vreinterpretv4si<mode>): Likewise.
(neon_vreinterpretv4sf<mode>): Likewise.
(neon_vreinterpretv2di<mode>): Likewise.
* config/arm/unspecs.md (UNSPEC_AESD, UNSPEC_AESE, UNSPEC_AESIMC,
UNSPEC_AESMC, UNSPEC_SHA1C, UNSPEC_SHA1M, UNSPEC_SHA1P, UNSPEC_SHA1H,
UNSPEC_SHA1SU0, UNSPEC_SHA1SU1, UNSPEC_SHA256H, UNSPEC_SHA256H2,
UNSPEC_SHA256SU0, UNSPEC_SHA256SU1, VMULLP64): Define.
* config/arm/arm_neon.h: Regenerate.
From-SVN: r206130
2013-12-19 19:21:10 +01:00
|
|
|
(define_int_attr crypto_pattern [(UNSPEC_SHA1H "sha1h") (UNSPEC_AESMC "aesmc")
|
|
|
|
(UNSPEC_AESIMC "aesimc") (UNSPEC_AESD "aesd")
|
|
|
|
(UNSPEC_AESE "aese") (UNSPEC_SHA1SU1 "sha1su1")
|
|
|
|
(UNSPEC_SHA256SU0 "sha256su0") (UNSPEC_SHA1C "sha1c")
|
|
|
|
(UNSPEC_SHA1M "sha1m") (UNSPEC_SHA1P "sha1p")
|
|
|
|
(UNSPEC_SHA1SU0 "sha1su0") (UNSPEC_SHA256H "sha256h")
|
|
|
|
(UNSPEC_SHA256H2 "sha256h2")
|
|
|
|
(UNSPEC_SHA256SU1 "sha256su1")])
|
|
|
|
|
|
|
|
(define_int_attr crypto_type
|
2014-03-28 18:22:47 +01:00
|
|
|
[(UNSPEC_AESE "crypto_aese") (UNSPEC_AESD "crypto_aese")
|
|
|
|
(UNSPEC_AESMC "crypto_aesmc") (UNSPEC_AESIMC "crypto_aesmc")
|
arm.c (enum arm_builtins): Add crypto builtins.
2013-12-19 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
* config/arm/arm.c (enum arm_builtins): Add crypto builtins.
(arm_init_neon_builtins): Handle crypto builtins.
(bdesc_2arg): Likewise.
(bdesc_1arg): Likewise.
(bdesc_3arg): New table.
(arm_expand_ternop_builtin): New function.
(arm_expand_unop_builtin): Handle sha1h explicitly.
(arm_expand_builtin): Handle ternary builtins.
* config/arm/arm.h (TARGET_CPU_CPP_BUILTINS):
Define __ARM_FEATURE_CRYPTO.
* config/arm/arm.md: Include crypto.md.
(is_neon_type): Add crypto types.
* config/arm/arm_neon_builtins.def: Add TImode reinterprets.
* config/arm/crypto.def: New.
* config/arm/crypto.md: Likewise.
* config/arm/iterators.md (CRYPTO_UNARY): New int iterator.
(CRYPTO_BINARY): Likewise.
(CRYPTO_TERNARY): Likewise.
(CRYPTO_SELECTING): Likewise.
(crypto_pattern): New int attribute.
(crypto_size_sfx): Likewise.
(crypto_mode): Likewise.
(crypto_type): Likewise.
* config/arm/neon-gen.ml: Handle poly64_t and poly128_t types.
Handle crypto intrinsics.
* config/arm/neon.ml: Add support for poly64 and polt128 types
and intrinsics. Define crypto intrinsics.
* config/arm/neon.md (neon_vreinterpretti<mode>): New pattern.
(neon_vreinterpretv16qi<mode>): Use VQXMOV mode iterator.
(neon_vreinterpretv8hi<mode>): Likewise.
(neon_vreinterpretv4si<mode>): Likewise.
(neon_vreinterpretv4sf<mode>): Likewise.
(neon_vreinterpretv2di<mode>): Likewise.
* config/arm/unspecs.md (UNSPEC_AESD, UNSPEC_AESE, UNSPEC_AESIMC,
UNSPEC_AESMC, UNSPEC_SHA1C, UNSPEC_SHA1M, UNSPEC_SHA1P, UNSPEC_SHA1H,
UNSPEC_SHA1SU0, UNSPEC_SHA1SU1, UNSPEC_SHA256H, UNSPEC_SHA256H2,
UNSPEC_SHA256SU0, UNSPEC_SHA256SU1, VMULLP64): Define.
* config/arm/arm_neon.h: Regenerate.
From-SVN: r206130
2013-12-19 19:21:10 +01:00
|
|
|
(UNSPEC_SHA1C "crypto_sha1_slow") (UNSPEC_SHA1P "crypto_sha1_slow")
|
|
|
|
(UNSPEC_SHA1M "crypto_sha1_slow") (UNSPEC_SHA1SU1 "crypto_sha1_fast")
|
|
|
|
(UNSPEC_SHA1SU0 "crypto_sha1_xor") (UNSPEC_SHA256H "crypto_sha256_slow")
|
|
|
|
(UNSPEC_SHA256H2 "crypto_sha256_slow") (UNSPEC_SHA256SU0 "crypto_sha256_fast")
|
|
|
|
(UNSPEC_SHA256SU1 "crypto_sha256_slow")])
|
|
|
|
|
|
|
|
(define_int_attr crypto_size_sfx [(UNSPEC_SHA1H "32") (UNSPEC_AESMC "8")
|
|
|
|
(UNSPEC_AESIMC "8") (UNSPEC_AESD "8")
|
|
|
|
(UNSPEC_AESE "8") (UNSPEC_SHA1SU1 "32")
|
|
|
|
(UNSPEC_SHA256SU0 "32") (UNSPEC_SHA1C "32")
|
|
|
|
(UNSPEC_SHA1M "32") (UNSPEC_SHA1P "32")
|
|
|
|
(UNSPEC_SHA1SU0 "32") (UNSPEC_SHA256H "32")
|
|
|
|
(UNSPEC_SHA256H2 "32") (UNSPEC_SHA256SU1 "32")])
|
|
|
|
|
|
|
|
(define_int_attr crypto_mode [(UNSPEC_SHA1H "V4SI") (UNSPEC_AESMC "V16QI")
|
|
|
|
(UNSPEC_AESIMC "V16QI") (UNSPEC_AESD "V16QI")
|
|
|
|
(UNSPEC_AESE "V16QI") (UNSPEC_SHA1SU1 "V4SI")
|
|
|
|
(UNSPEC_SHA256SU0 "V4SI") (UNSPEC_SHA1C "V4SI")
|
|
|
|
(UNSPEC_SHA1M "V4SI") (UNSPEC_SHA1P "V4SI")
|
|
|
|
(UNSPEC_SHA1SU0 "V4SI") (UNSPEC_SHA256H "V4SI")
|
|
|
|
(UNSPEC_SHA256H2 "V4SI") (UNSPEC_SHA256SU1 "V4SI")])
|
|
|
|
|
2013-05-30 10:11:30 +02:00
|
|
|
;; Both kinds of return insn.
|
2015-04-24 17:01:32 +02:00
|
|
|
(define_code_iterator RETURNS [return simple_return])
|
2013-05-30 10:11:30 +02:00
|
|
|
(define_code_attr return_str [(return "") (simple_return "simple_")])
|
|
|
|
(define_code_attr return_simple_p [(return "false") (simple_return "true")])
|
|
|
|
(define_code_attr return_cond_false [(return " && USE_RETURN_INSN (FALSE)")
|
|
|
|
(simple_return " && use_simple_return_p ()")])
|
|
|
|
(define_code_attr return_cond_true [(return " && USE_RETURN_INSN (TRUE)")
|
|
|
|
(simple_return " && use_simple_return_p ()")])
|
2015-12-16 12:56:21 +01:00
|
|
|
|
|
|
|
;; Attributes for VQRDMLAH/VQRDMLSH
|
|
|
|
(define_int_attr neon_rdma_as [(UNSPEC_VQRDMLAH "a") (UNSPEC_VQRDMLSH "s")])
|
2016-09-23 11:54:44 +02:00
|
|
|
|
|
|
|
;; Attributes for VFMA_LANE/ VFMS_LANE
|
|
|
|
(define_int_attr neon_vfm_lane_as
|
|
|
|
[(UNSPEC_VFMA_LANE "a") (UNSPEC_VFMS_LANE "s")])
|
2017-01-06 18:35:23 +01:00
|
|
|
|
|
|
|
;; An iterator for the CDP coprocessor instructions
|
|
|
|
(define_int_iterator CDPI [VUNSPEC_CDP VUNSPEC_CDP2])
|
|
|
|
(define_int_attr cdp [(VUNSPEC_CDP "cdp") (VUNSPEC_CDP2 "cdp2")])
|
|
|
|
(define_int_attr CDP [(VUNSPEC_CDP "CDP") (VUNSPEC_CDP2 "CDP2")])
|
[ARM] Implement support for ACLE Coprocessor LDC and STC intrinsics
gcc/ChangeLog:
2017-01-06 Andre Vieira <andre.simoesdiasvieira@arm.com>
* config/arm/arm.md (*ldc): New.
(*stc): New.
(<ldc>): New.
(<stc>): New.
* config/arm/arm.c (arm_coproc_builtin_available): Add
support for ldc,ldcl,stc,stcl,ldc2,ldc2l,stc2 and stc2l.
(arm_coproc_ldc_stc_legitimate_address): New.
* config/arm/arm-builtins.c (arm_type_qualifiers): Add
'qualifier_const_pointer'.
(LDC_QUALIFIERS): Define to...
(arm_ldc_qualifiers): ... this. New.
(STC_QUALIFIERS): Define to...
(arm_stc_qualifiers): ... this. New.
* config/arm/arm-protos.h
(arm_coproc_ldc_stc_legitimate_address): New.
* config/arm/arm_acle.h (__arm_ldc, __arm_ldcl, __arm_stc,
__arm_stcl, __arm_ldc2, __arm_ldc2l, __arm_stc2, __arm_stc2l): New.
* config/arm/arm_acle_builtins.def (ldc, ldc2, ldcl, ldc2l, stc,
stc2, stcl, stc2l): New.
* config/arm/constraints.md (Uz): New.
* config/arm/iterators.md (LDCI, STCI, ldc, stc, LDC STC): New.
* config/arm/unspecs.md (VUNSPEC_LDC, VUNSPEC_LDC2, VUNSPEC_LDCL,
VUNSPEC_LDC2L, VUNSPEC_STC, VUNSPEC_STC2, VUNSPEC_STCL,
VUNSPEC_STC2L): New.
gcc/testsuite/ChangeLog:
2017-01-06 Andre Vieira <andre.simoesdiasvieira@arm.com>
* gcc.target/arm/acle/ldc: New.
* gcc.target/arm/acle/ldc2: New.
* gcc.target/arm/acle/ldcl: New.
* gcc.target/arm/acle/ldc2l: New.
* gcc.target/arm/acle/stc: New.
* gcc.target/arm/acle/stc2: New.
* gcc.target/arm/acle/stcl: New.
* gcc.target/arm/acle/stc2l: New.
From-SVN: r244173
2017-01-06 18:37:39 +01:00
|
|
|
|
|
|
|
;; An iterator for the LDC coprocessor instruction
|
|
|
|
(define_int_iterator LDCI [VUNSPEC_LDC VUNSPEC_LDC2
|
|
|
|
VUNSPEC_LDCL VUNSPEC_LDC2L])
|
|
|
|
(define_int_attr ldc [(VUNSPEC_LDC "ldc") (VUNSPEC_LDC2 "ldc2")
|
|
|
|
(VUNSPEC_LDCL "ldcl") (VUNSPEC_LDC2L "ldc2l")])
|
|
|
|
(define_int_attr LDC [(VUNSPEC_LDC "LDC") (VUNSPEC_LDC2 "LDC2")
|
|
|
|
(VUNSPEC_LDCL "LDCL") (VUNSPEC_LDC2L "LDC2L")])
|
|
|
|
|
|
|
|
;; An iterator for the STC coprocessor instructions
|
|
|
|
(define_int_iterator STCI [VUNSPEC_STC VUNSPEC_STC2
|
|
|
|
VUNSPEC_STCL VUNSPEC_STC2L])
|
|
|
|
(define_int_attr stc [(VUNSPEC_STC "stc") (VUNSPEC_STC2 "stc2")
|
|
|
|
(VUNSPEC_STCL "stcl") (VUNSPEC_STC2L "stc2l")])
|
|
|
|
(define_int_attr STC [(VUNSPEC_STC "STC") (VUNSPEC_STC2 "STC2")
|
|
|
|
(VUNSPEC_STCL "STCL") (VUNSPEC_STC2L "STC2L")])
|
[ARM] Implement support for ACLE Coprocessor MCR and MRC intrinsics
gcc/ChangeLog:
2017-01-06 Andre Vieira <andre.simoesdiasvieira@arm.com>
* config/arm/arm.md (<mcr>): New.
(<mrc>): New.
* config/arm/arm.c (arm_coproc_builtin_available): Add
support for mcr, mrc, mcr2 and mrc2.
* config/arm/arm-builtins.c (MCR_QUALIFIERS): Define to...
(arm_mcr_qualifiers): ... this. New.
(MRC_QUALIFIERS): Define to ...
(arm_mrc_qualifiers): ... this. New.
(MCR_QUALIFIERS): Define to ...
(arm_mcr_qualifiers): ... this. New.
* config/arm/arm_acle.h (__arm_mcr, __arm_mrc, __arm_mcr2,
__arm_mrc2): New.
* config/arm/arm_acle_builtins.def (mcr, mcr2, mrc, mrc2): New.
* config/arm/iterators.md (MCRI, mcr, MCR, MRCI, mrc, MRC): New.
* config/arm/unspecs.md (VUNSPEC_MCR, VUNSPEC_MCR2, VUNSPEC_MRC,
VUNSPEC_MRC2): New.
gcc/testsuite/ChangeLog:
2017-01-06 Andre Vieira <andre.simoesdiasvieira@arm.com>
* gcc.target/arm/acle/mcr.c: New.
* gcc.target/arm/acle/mrc.c: New.
* gcc.target/arm/acle/mcr2.c: New.
* gcc.target/arm/acle/mrc2.c: New.
From-SVN: r244174
2017-01-06 18:40:50 +01:00
|
|
|
|
|
|
|
;; An iterator for the MCR coprocessor instructions
|
|
|
|
(define_int_iterator MCRI [VUNSPEC_MCR VUNSPEC_MCR2])
|
|
|
|
|
|
|
|
(define_int_attr mcr [(VUNSPEC_MCR "mcr") (VUNSPEC_MCR2 "mcr2")])
|
|
|
|
(define_int_attr MCR [(VUNSPEC_MCR "MCR") (VUNSPEC_MCR2 "MCR2")])
|
|
|
|
|
|
|
|
;; An iterator for the MRC coprocessor instructions
|
|
|
|
(define_int_iterator MRCI [VUNSPEC_MRC VUNSPEC_MRC2])
|
|
|
|
|
|
|
|
(define_int_attr mrc [(VUNSPEC_MRC "mrc") (VUNSPEC_MRC2 "mrc2")])
|
|
|
|
(define_int_attr MRC [(VUNSPEC_MRC "MRC") (VUNSPEC_MRC2 "MRC2")])
|
[ARM] Implement support for ACLE Coprocessor MCRR and MRRC intrinsics
gcc/ChangeLog:
2017-01-06 Andre Vieira <andre.simoesdiasvieira@arm.com>
* config/arm/arm.md (<mcrr>): New.
(<mrrc>): New.
* config/arm/arm.c (arm_arch5te): New.
(arm_option_override): Set arm_arch5te.
(arm_coproc_builtin_available): Add support for mcrr, mcrr2, mrrc
and mrrc2.
* config/arm/arm-builtins.c (MCRR_QUALIFIERS): Define to...
(arm_mcrr_qualifiers): ... this. New.
(MRRC_QUALIFIERS): Define to...
(arm_mrrc_qualifiers): ... this. New.
* config/arm/arm_acle.h (__arm_mcrr, __arm_mcrr2, __arm_mrrc,
__arm_mrrc2): New.
* config/arm/arm_acle_builtins.def (mcrr, mcrr2, mrrc, mrrc2): New.
* config/arm/iterators.md (MCRRI, mcrr, MCRR): New.
(MRRCI, mrrc, MRRC): New.
* config/arm/unspecs.md (VUNSPEC_MCRR, VUNSPEC_MCRR2, VUNSPEC_MRRC,
VUNSPEC_MRRC2): New.
gcc/testsuite/ChangeLog:
2017-01-06 Andre Vieira <andre.simoesdiasvieira@arm.com>
* gcc.target/arm/acle/mcrr: New.
* gcc.target/arm/acle/mcrr2: New.
* gcc.target/arm/acle/mrrc: New.
* gcc.target/arm/acle/mrrc2: New.
From-SVN: r244175
2017-01-06 18:49:12 +01:00
|
|
|
|
|
|
|
;; An iterator for the MCRR coprocessor instructions
|
|
|
|
(define_int_iterator MCRRI [VUNSPEC_MCRR VUNSPEC_MCRR2])
|
|
|
|
|
|
|
|
(define_int_attr mcrr [(VUNSPEC_MCRR "mcrr") (VUNSPEC_MCRR2 "mcrr2")])
|
|
|
|
(define_int_attr MCRR [(VUNSPEC_MCRR "MCRR") (VUNSPEC_MCRR2 "MCRR2")])
|
|
|
|
|
|
|
|
;; An iterator for the MRRC coprocessor instructions
|
|
|
|
(define_int_iterator MRRCI [VUNSPEC_MRRC VUNSPEC_MRRC2])
|
|
|
|
|
|
|
|
(define_int_attr mrrc [(VUNSPEC_MRRC "mrrc") (VUNSPEC_MRRC2 "mrrc2")])
|
|
|
|
(define_int_attr MRRC [(VUNSPEC_MRRC "MRRC") (VUNSPEC_MRRC2 "MRRC2")])
|