binutils-gdb/include/ChangeLog

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2019-05-24 Szabolcs Nagy <szabolcs.nagy@arm.com>
* elf/aarch64.h (DT_AARCH64_VARIANT_PCS): Define.
(STO_AARCH64_VARIANT_PCS): Define.
PowerPC relocations for prefix insns include/ * elf/ppc64.h (R_PPC64_PLTSEQ_NOTOC, R_PPC64_PLTCALL_NOTOC), (R_PPC64_PCREL_OPT, R_PPC64_D34, R_PPC64_D34_LO, R_PPC64_D34_HI30), (R_PPC64_D34_HA30, R_PPC64_PCREL34, R_PPC64_GOT_PCREL34), (R_PPC64_PLT_PCREL34, R_PPC64_PLT_PCREL34_NOTOC), (R_PPC64_ADDR16_HIGHER34, R_PPC64_ADDR16_HIGHERA34), (R_PPC64_ADDR16_HIGHEST34, R_PPC64_ADDR16_HIGHESTA34), (R_PPC64_REL16_HIGHER34, R_PPC64_REL16_HIGHERA34), (R_PPC64_REL16_HIGHEST34, R_PPC64_REL16_HIGHESTA34), (R_PPC64_D28, R_PPC64_PCREL28): Define. bfd/ * reloc.c (BFD_RELOC_PPC64_D34, BFD_RELOC_PPC64_D34_LO), (BFD_RELOC_PPC64_D34_HI30, BFD_RELOC_PPC64_D34_HA30), (BFD_RELOC_PPC64_PCREL34, BFD_RELOC_PPC64_GOT_PCREL34), (BFD_RELOC_PPC64_PLT_PCREL34), (BFD_RELOC_PPC64_ADDR16_HIGHER34, BFD_RELOC_PPC64_ADDR16_HIGHERA34), (BFD_RELOC_PPC64_ADDR16_HIGHEST34, BFD_RELOC_PPC64_ADDR16_HIGHESTA34), (BFD_RELOC_PPC64_REL16_HIGHER34, BFD_RELOC_PPC64_REL16_HIGHERA34), (BFD_RELOC_PPC64_REL16_HIGHEST34, BFD_RELOC_PPC64_REL16_HIGHESTA34), (BFD_RELOC_PPC64_D28, BFD_RELOC_PPC64_PCREL28): New reloc enums. * elf64-ppc.c (PNOP): Define. (ppc64_elf_howto_raw): Add reloc howtos for new relocations. (ppc64_elf_reloc_type_lookup): Translate new bfd reloc numbers. (ppc64_elf_ha_reloc): Adjust addend for highera34 and highesta34 relocs. (ppc64_elf_prefix_reloc): New function. (struct ppc_link_hash_table): Add notoc_plt. (is_branch_reloc): Add R_PPC64_PLTCALL_NOTOC. (is_plt_seq_reloc): Add R_PPC64_PLT_PCREL34, R_PPC64_PLT_PCREL34_NOTOC, and R_PPC64_PLTSEQ_NOTOC. (ppc64_elf_check_relocs): Handle pcrel got and plt relocs. Set has_pltcall for section on seeing R_PPC64_PLTCALL_NOTOC. Handle possible need for dynamic relocs on non-pcrel powerxx relocs. (dec_dynrel_count): Handle non-pcrel powerxx relocs. (ppc64_elf_inline_plt): Handle R_PPC64_PLTCALL_NOTOC. (toc_adjusting_stub_needed): Likewise. (ppc64_elf_tls_optimize): Handle R_PPC64_PLTSEQ_NOTOC. (ppc64_elf_relocate_section): Handle new powerxx relocs. * bfd-in2.h: Regenerate. * libbfd.h: Regenerate. gas/ * config/tc-ppc.c (ppc_elf_suffix): Support @pcrel, @got@pcrel, @plt@pcrel, @higher34, @highera34, @highest34, and @highesta34. (fixup_size): Handle new powerxx relocs. (md_assemble): Warn for @pcrel on non-prefix insns. Accept @l, @h and @ha on prefix insns, and infer reloc without any @ suffix. Translate powerxx relocs to suit DQ and DS field instructions. Include operand tests as well as opcode test to translate BFD_RELOC_HI16_S to BFD_RELOC_PPC_16DX_HA. (ppc_fix_adjustable): Return false for pcrel GOT and PLT relocs. (md_apply_fix): Handle new powerxx relocs. * config/tc-ppc.h (TC_FORCE_RELOCATION_SUB_LOCAL): Accept BFD_RELOC_PPC64_ADDR16_HIGHER34, BFD_RELOC_PPC64_ADDR16_HIGHERA34, BFD_RELOC_PPC64_ADDR16_HIGHEST34, BFD_RELOC_PPC64_ADDR16_HIGHESTA34, BFD_RELOC_PPC64_D34, and BFD_RELOC_PPC64_D28. * testsuite/gas/ppc/prefix-reloc.d, * testsuite/gas/ppc/prefix-reloc.s: New test. * testsuite/gas/ppc/ppc.exp: Run it.
2018-08-29 06:52:34 +02:00
2019-05-24 Alan Modra <amodra@gmail.com>
* elf/ppc64.h (R_PPC64_PLTSEQ_NOTOC, R_PPC64_PLTCALL_NOTOC),
(R_PPC64_PCREL_OPT, R_PPC64_D34, R_PPC64_D34_LO, R_PPC64_D34_HI30),
(R_PPC64_D34_HA30, R_PPC64_PCREL34, R_PPC64_GOT_PCREL34),
(R_PPC64_PLT_PCREL34, R_PPC64_PLT_PCREL34_NOTOC),
(R_PPC64_ADDR16_HIGHER34, R_PPC64_ADDR16_HIGHERA34),
(R_PPC64_ADDR16_HIGHEST34, R_PPC64_ADDR16_HIGHESTA34),
(R_PPC64_REL16_HIGHER34, R_PPC64_REL16_HIGHERA34),
(R_PPC64_REL16_HIGHEST34, R_PPC64_REL16_HIGHESTA34),
(R_PPC64_D28, R_PPC64_PCREL28): Define.
PowerPC add initial -mfuture instruction support This patch adds initial 64-bit insn assembler/disassembler support. The only instruction added is "pnop" along with the automatic aligning of prefix instruction so they do not cross 64-byte boundaries. include/ * dis-asm.h (WIDE_OUTPUT): Define. * opcode/ppc.h (prefix_opcodes, prefix_num_opcodes): Declare. (PPC_OPCODE_POWERXX, PPC_GET_PREFIX, PPC_GET_SUFFIX), (PPC_PREFIX_P, PPC_PREFIX_SEG): Define. opcodes/ * ppc-dis.c (ppc_opts): Add "future" entry. (PREFIX_OPCD_SEGS): Define. (prefix_opcd_indices): New array. (disassemble_init_powerpc): Initialize prefix_opcd_indices. (lookup_prefix): New function. (print_insn_powerpc): Handle 64-bit prefix instructions. * ppc-opc.c (PREFIX_OP, PREFIX_FORM, SUFFIX_MASK, PREFIX_MASK), (PMRR, POWERXX): Define. (prefix_opcodes): New instruction table. (prefix_num_opcodes): New constant. binutils/ * objdump.c (disassemble_bytes): Set WIDE_OUTPUT in flags. gas/ * config/tc-ppc.c (ppc_setup_opcodes): Handle prefix_opcodes. (struct insn_label_list): New. (insn_labels, free_insn_labels): New variables. (ppc_record_label, ppc_clear_labels, ppc_start_line_hook): New funcs. (ppc_frob_label, ppc_new_dot_label): Move functions earlier in file and call ppc_record_label. (md_assemble): Handle 64-bit prefix instructions. Align labels that are on the same line as a prefix instruction. * config/tc-ppc.h (tc_frob_label, ppc_frob_label): Move to later in the file. (md_start_line_hook): Define. (ppc_start_line_hook): Declare. * testsuite/gas/ppc/prefix-align.d, * testsuite/gas/ppc/prefix-align.s: New test. * testsuite/gas/ppc/ppc.exp: Run new test.
2018-05-15 23:48:14 +02:00
2019-05-24 Peter Bergner <bergner@linux.ibm.com>
Alan Modra <amodra@gmail.com>
* dis-asm.h (WIDE_OUTPUT): Define.
* opcode/ppc.h (prefix_opcodes, prefix_num_opcodes): Declare.
(PPC_OPCODE_POWERXX, PPC_GET_PREFIX, PPC_GET_SUFFIX),
(PPC_PREFIX_P, PPC_PREFIX_SEG): Define.
2019-05-23 Jose E. Marchesi <jose.marchesi@oracle.com>
* elf/bpf.h: New file.
2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
* elf/arm.h (Tag_MVE_arch): Define new enum value.
* opcode/arm.h (FPU_MVE, FPU_MVE_FP): New MACROs for new features.
2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
* opcode/aarch64.h (enum aarch64_opnd): New SVE_SHLIMM_UNPRED_22
operand.
2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
* opcode/aarch64.h (enum aarch64_insn_class): Add sve_size_tsz_bhs
iclass.
2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
* opcode/aarch64.h (enum aarch64_opnd): New SVE_Zm4_11_INDEX operand.
2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
* opcode/aarch64.h (enum aarch64_insn_class): Add sve_shift_tsz_bhsd
iclass.
[binutils][aarch64] New SVE_SHRIMM_UNPRED_22 operand. Include a new iclass to extract the variant from the most significant 3 bits of this operand. Instructions such as rshrnb include a constant shift amount as an operand, where the most significant three bits of this operand determine what size elements the instruction is operating on. The new SVE_SHRIMM_UNPRED_22 operand denotes this constant encoded in bits 22:20-19:18-16 while the new sve_shift_tsz_hsd iclass denotes that the SVE qualifier is encoded in bits 22:20-19. gas/ChangeLog: 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com> * config/tc-aarch64.c (parse_operands): Handle new SVE_SHRIMM_UNPRED_22 operand. include/ChangeLog: 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com> * opcode/aarch64.h (enum aarch64_opnd): New SVE_SHRIMM_UNPRED_22 operand. (enum aarch64_insn_class): Add sve_shift_tsz_hsd iclass. opcodes/ChangeLog: 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com> * aarch64-asm-2.c: Regenerated. * aarch64-dis-2.c: Regenerated. * aarch64-opc-2.c: Regenerated. * aarch64-asm.c (aarch64_ins_sve_shrimm): (aarch64_encode_variant_using_iclass): Handle sve_shift_tsz_hsd iclass encode. * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle sve_shift_tsz_hsd iclass decode. * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking for SVE_SHRIMM_UNPRED_22. (aarch64_print_operand): Add printing for SVE_SHRIMM_UNPRED_22. * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_SHRIMM_UNPRED_22 operand.
2019-05-09 11:29:22 +02:00
2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
* opcode/aarch64.h (enum aarch64_opnd): New SVE_SHRIMM_UNPRED_22
operand.
(enum aarch64_insn_class): Add sve_shift_tsz_hsd iclass.
2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
* opcode/aarch64.h (enum aarch64_insn_class): Add sve_size_013 iclass.
2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
* opcode/aarch64.h (enum aarch64_insn_class): Add sve_size_bh iclass.
2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
* opcode/aarch64.h (enum aarch64_insn_class): Add sve_size_sd2 iclass.
2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
* opcode/aarch64.h (enum aarch64_opnd): New SVE_ADDR_ZX operand.
2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
* opcode/aarch64.h (enum aarch64_opnd): New SVE_Zm3_11_INDEX operand.
2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
* opcode/aarch64.h (enum aarch64_insn_class): Add sve_size_hsd2 iclass.
2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
* opcode/aarch64.h (enum aarch64_opnd): New SVE_IMM_ROT3 operand.
[binutils][aarch64] SVE2 feature extension flags. Include all feature flag macros. The "sve2" extension that enables the core sve2 instructions. This also enables the sve extension, since sve is a requirement of sve2. Extra optional sve2 features are the bitperm, sm4, aes, and sha3 extensions. These are all given extra feature flags, "bitperm", "sve2-sm4", "sve2-aes", and "sve2-sha3" respectively. The sm4, aes, and sha3 extensions are explicitly marked as sve2 extensions to distinguish them from the corresponding NEON extensions. Rather than continue extending the current feature flag numbers, I used some bits that have been skipped. gas/ChangeLog: 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com> * config/tc-aarch64.c: Add command line architecture feature flags "sve2", "sve2-sm4", "sve2-aes", "sve2-sha3", "bitperm". * doc/c-aarch64.texi: Document new architecture feature flags. include/ChangeLog: 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com> * opcode/aarch64.h (AARCH64_FEATURE_SVE2 AARCH64_FEATURE_SVE2_AES, AARCH64_FEATURE_SVE2_BITPERM, AARCH64_FEATURE_SVE2_SM4, AARCH64_FEATURE_SVE2_SHA3): New feature macros. opcodes/ChangeLog: 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com> * aarch64-tbl.h (aarch64_feature_sve2, aarch64_feature_sve2aes, aarch64_feature_sve2sha3, aarch64_feature_sve2sm4, aarch64_feature_sve2bitperm): New feature sets. (SVE2, SVE2_AES, SVE2_SHA3, SVE2_SM4, SVE2_BITPERM): New macros for feature set addresses. (SVE2_INSN, SVE2_INSNC, SVE2AES_INSN, SVE2SHA3_INSN, SVE2SM4_INSN, SVE2SM4_INSNC, SVE2BITPERM_INSN): New macros.
2019-05-09 11:29:12 +02:00
2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
* opcode/aarch64.h (AARCH64_FEATURE_SVE2
AARCH64_FEATURE_SVE2_AES, AARCH64_FEATURE_SVE2_BITPERM,
AARCH64_FEATURE_SVE2_SM4, AARCH64_FEATURE_SVE2_SHA3): New
feature macros.
2019-05-06 Andrew Bennett <andrew.bennett@imgtec.com>
Faraz Shahbazker <fshahbazker@wavecomp.com>
* opcode/mips.h (ASE_EVA_R6): New macro.
(M_LLWPE_AB, M_SCWPE_AB): New enum values.
[BINUTILS, AArch64] Enable Transactional Memory Extension This patch enables the new Transactional Memory Extension added recently as part of Arm's new architecture technologies. We introduce a new optional extension "tme" to enable this. The following instructions are part of the extension: * tstart <Xt> * ttest <Xt> * tcommit * tcancel #<imm> The ISA for the above can be found here: https://developer.arm.com/docs/ddi0602/latest/base-instructions-alphabetic-order *** gas/ChangeLog *** 2019-05-01 Sudakshina Das <sudi.das@arm.com> * config/tc-aarch64.c (parse_operands): Add case for AARCH64_OPND_TME_UIMM16. (aarch64_features): Add "tme". * doc/c-aarch64.texi: Document the same. * testsuite/gas/aarch64/tme-invalid.d: New test. * testsuite/gas/aarch64/tme-invalid.l: New test. * testsuite/gas/aarch64/tme-invalid.s: New test. * testsuite/gas/aarch64/tme.d: New test. * testsuite/gas/aarch64/tme.s: New test. *** include/ChangeLog *** 2019-05-01 Sudakshina Das <sudi.das@arm.com> * opcode/aarch64.h (AARCH64_FEATURE_TME): New. (enum aarch64_opnd): Add AARCH64_OPND_TME_UIMM16. *** opcodes/ChangeLog *** 2019-05-01 Sudakshina Das <sudi.das@arm.com> * aarch64-asm-2.c: Regenerated. * aarch64-dis-2.c: Regenerated. * aarch64-opc-2.c: Regenerated. * aarch64-opc.c (operand_general_constraint_met_p): Add case for AARCH64_OPND_TME_UIMM16. (aarch64_print_operand): Likewise. * aarch64-tbl.h (QL_IMM_NIL): New. (TME): New. (_TME_INSN): New. (struct aarch64_opcode): Add tstart, tcommit, ttest and tcancel.
2019-05-01 18:14:01 +02:00
2019-05-01 Sudakshina Das <sudi.das@arm.com>
* opcode/aarch64.h (AARCH64_FEATURE_TME): New.
(enum aarch64_opnd): Add AARCH64_OPND_TME_UIMM16.
[MIPS] Add load-link, store-conditional paired instructions Add several baseline MIPS32R6[1] and MIPS64R6[2] instructions that were omitted from the initial spec. These instructions are optional in implementations but not associated with any ASE or pseudo-ASE. Their presence is indicated by the XNP bit in the Config5 register. [1] "MIPS Architecture for Programmers Volume II-A: The MIPS32 Instruction Set Manual", Imagination Technologies Ltd., Document Number: MD00086, Revision 6.06, December 15, 2016, Section 3.2 "Alphabetical List of Instructions", pp. 228-229, pp. 354-357. [2] "MIPS Architecture for Programmers Volume II-A: The MIPS64 Instruction Set Manual", Imagination Technologies Ltd., Document Number: MD00087, Revision 6.06, December 15, 2016, Section 3.2 "Alphabetical List of Instructions", pp. 289-290 and pp. 458-460. gas/ * config/tc-mips.c (macro) <M_LLWP_AB, M_LLDP_AB, M_SCWP_AB, M_SCDP_AB>: New cases and expansions for paired instructions. * testsuite/gas/mips/llpscp-32.s: New test source. * testsuite/gas/mips/llpscp-64.s: Likewise. * testsuite/gas/mips/llpscp-32.d: New test. * testsuite/gas/mips/llpscp-64.d: Likewise. * testsuite/gas/mips/mips.exp: Run the new tests. * testsuite/gas/mips/r6.s: Add new instructions to test source. * testsuite/gas/mips/r6-64.s: Likewise. * testsuite/gas/mips/r6-64-n32.d: Check new instructions. * testsuite/gas/mips/r6-64-n64.d: Likewise. * testsuite/gas/mips/r6-n32.d: Likewise. * testsuite/gas/mips/r6-n64.d: Likwwise. * testsuite/gas/mips/r6.d: Likewise. include/ * opcode/mips.h (M_LLWP_AB, M_LLDP_AB): New enum values. (M_SCWP_AB, M_SCDP_AB): Likewise. opcodes/ * mips-opc.c (mips_builtin_opcodes): Add llwp, lldp, scwp, scdp.
2019-04-23 00:12:09 +02:00
2019-04-26 Andrew Bennett <andrew.bennett@imgtec.com>
Faraz Shahbazker <fshahbazker@wavecomp.com>
* opcode/mips.h (M_LLWP_AB, M_LLDP_AB): New enum values.
(M_SCWP_AB, M_SCDP_AB): Likewise.
2019-04-25 Maciej W. Rozycki <macro@linux-mips.org>
* opcode/mips.h: Update comment for MIPS32 CODE20 operand.
[binutils, ARM, 10/16] BFCSEL infrastructure with new global reloc R_ARM_THM_BF12 This patch is part of a series of patches to add support for Armv8.1-M Mainline instructions to binutils. This adds infrastructure for the BFCSEL instructions which is one of the first instructions in Arm that have more than one relocations in them. This adds a new relocation R_ARM_THM_BF12. The inconsistency between external R_ARM_THM_BF12 and internal BFD_RELOC_ARM_THUMB_BF13 is because internally we count the static bit-0 of the immediate and we don't externally. ChangeLog entries are as follows : ChangeLog entries are as follows : *** bfd/ChnageLog *** 2019-04-04 Sudakshina Das <sudi.das@arm.com> * reloc.c (BFD_RELOC_ARM_THUMB_BF13): New. * bfd-in2.h: Regenerated. * libbfd.h: Regenerated. * elf32-arm.c (elf32_arm_howto_table_1): New entry for R_ARM_THM_BF13. (elf32_arm_reloc_map elf32_arm_reloc_map): Map BFD_RELOC_ARM_THUMB_BF13 and R_ARM_THM_BF12 together. (elf32_arm_final_link_relocate): New switch case for R_ARM_THM_BF13. *** elfcpp/ChangeLog *** 2019-04-04 Sudakshina Das <sudi.das@arm.com> * arm.h (R_ARM_THM_BF12): New relocation code. *** gas/ChangeLog *** 2019-04-04 Sudakshina Das <sudi.das@arm.com> * config/tc-arm.c (md_pcrel_from_section): New switch case for BFD_RELOC_ARM_THUMB_BF13. (md_appdy_fix): Likewise. (tc_gen_reloc): Likewise. *** include/ChangeLog *** 2019-04-04 Sudakshina Das <sudi.das@arm.com> * elf/arm.h (START_RELOC_NUMBERS): New entry for R_ARM_THM_BF12. *** opcodes/ChangeLog *** 2019-04-04 Sudakshina Das <sudi.das@arm.com> * arm-dis.c (print_insn_thumb32): Updated to accept new %Z pattern.
2019-04-15 12:46:54 +02:00
2019-04-15 Sudakshina Das <sudi.das@arm.com>
* elf/arm.h (START_RELOC_NUMBERS): New entry for R_ARM_THM_BF12.
[binutils, ARM, 8/16] BFL infrastructure with new global reloc R_ARM_THM_BF18 This patch is part of a series of patches to add support for Armv8.1-M Mainline instructions to binutils. This adds infrastructure for the BFL instructions which is one of the first instructions in Arm that have more than one relocations in them. This adds a new relocation R_ARM_THM_BF18. The inconsistency between external R_ARM_THM_BF18 and internal BFD_RELOC_ARM_THUMB_BF19 is because internally we count the static bit-0 of the immediate and we don't externally. ChangeLog entries are as follows : *** bfd/ChangeLog *** 2019-04-15 Sudakshina Das <sudi.das@arm.com> * reloc.c (BFD_RELOC_ARM_THUMB_BF19): New * libbfd.h: Regenerated. * bfd-in2.h: Regenerated. * bfd-elf32-arm.c (elf32_arm_howto_table_1): New entry for R_ARM_THM_BF18. (elf32_arm_reloc_map elf32_arm_reloc_map): Map BFD_RELOC_ARM_THUMB_BF19 and R_ARM_THM_BF18 together. (elf32_arm_final_link_relocate): New switch case for R_ARM_THM_BF19. *** elfcpp/ChangeLog *** 2019-04-15 Sudakshina Das <sudi.das@arm.com> * arm.h (R_ARM_THM_BF18): New relocation code. *** gas/ChangeLog *** 2019-04-15 Sudakshina Das <sudi.das@arm.com> * config/tc-arm.c (md_pcrel_from_section): New switch case for BFD_RELOC_ARM_THUMB_BF19. (md_appdy_fix): Likewise. (tc_gen_reloc): Likewise. *** include/ChangeLog *** 2019-04-15 Sudakshina Das <sudi.das@arm.com> * elf/arm.h (START_RELOC_NUMBERS): New entry for R_ARM_THM_BF18. *** opcodes/ChangeLog *** 2019-04-15 Sudakshina Das <sudi.das@arm.com> * arm-dis.c (print_insn_thumb32): Updated to accept new %Y pattern.
2019-04-15 12:37:51 +02:00
2019-04-15 Sudakshina Das <sudi.das@arm.com>
* elf/arm.h (START_RELOC_NUMBERS): New entry for R_ARM_THM_BF18.
[binutils, ARM, 5/16] BF insns infrastructure with new global reloc R_ARM_THM_BF16 This patch is part of a series of patches to add support for Armv8.1-M Mainline instructions to binutils. This adds infrastructure for the BF instructions which is one of the first instructions in Arm that have more than one relocations in them. This is the third infrastructure patch that adds a new relocation R_ARM_THM_BF16. The inconsistency between external R_ARM_THM_BF16 and internal BFD_RELOC_ARM_THUMB_BF17 is because internally we count the static bit-0 of the immediate and we don't externally. ChangeLog entries are as follows : *** bfd/ChangeLog *** 2019-04-15 Sudakshina Das <sudi.das@arm.com> * reloc.c (BFD_RELOC_ARM_THUMB_BF17): New enum. * bfd-in2.h: Regenerated. * libbfd.h: Regenerated. * bfd-elf32-arm.c (elf32_arm_howto_table_1): New entry for R_ARM_THM_BF16. (elf32_arm_reloc_map elf32_arm_reloc_map): Map BFD_RELOC_ARM_THUMB_BF17 and R_ARM_THM_BF16 together. (get_value_helper): New reloc helper. (elf32_arm_final_link_relocate): New switch case for R_ARM_THM_BF16. *** elfcpp/ChangeLog *** 2019-04-15 Sudakshina Das <sudi.das@arm.com> * arm.h (R_ARM_THM_BF16): New relocation code. *** gas/ChangeLog *** 2019-04-15 Sudakshina Das <sudi.das@arm.com> * config/tc-arm.c (md_pcrel_from_section): New switch case for BFD_RELOC_ARM_THUMB_BF17. (md_appdy_fix): Likewise. (tc_gen_reloc): Likewise. *** include/ChangeLog *** 2019-04-15 Sudakshina Das <sudi.das@arm.com> * elf/arm.h (START_RELOC_NUMBERS): New entry for R_ARM_THM_BF16. *** opcodes/ChangeLog *** 2019-04-15 Sudakshina Das <sudi.das@arm.com> * arm-dis.c (print_insn_thumb32): Updated to accept new %W pattern.
2019-04-15 12:18:57 +02:00
2019-04-15 Sudakshina Das <sudi.das@arm.com>
* elf/arm.h (START_RELOC_NUMBERS): New entry for R_ARM_THM_BF16.
[binutils, ARM, 1/16] Add support for Armv8.1-M Mainline CLI The patch is straightforward, it does the following: - support the new Tag_CPU_arch build attribute value, ie.: + declare the new value + update all the asserts forcing logic to be reviewed for new architectures + create a corresponding bfd_mach_arm_8_1M_MAIN enumerator in bfd and add mapping from Tag_CPU_arch to it + teach readelf about new Tag_CPU_arch value - declare armv8.1-m.main as a supported architecture value - define Armv8.1-M Mainline in terms of feature bits available - tell objdump mapping from bfd_mach_arm_8_1M_MAIN enumerator to feature bits available - update architecture-specific logic in gas and bfd guarded by the asserts mentioned above. - tests for all the above ChangeLog entries are as follows: *** bfd/ChangeLog *** 2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com> * archures.c (bfd_mach_arm_8_1M_MAIN): Define. * bfd-in2.h: Regenerate. * cpu-arm.c (arch_info_struct): Add entry for Armv8.1-M Mainline. * elf32-arm.c (using_thumb_only): Return true for Armv8.1-M Mainline and update assert. (using_thumb2): Likewise. (using_thumb2_bl): Update assert. (arch_has_arm_nop): Likewise. (bfd_arm_get_mach_from_attributes): Add case for Armv8.1-M Mainline. (tag_cpu_arch_combine): Add logic for Armv8.1-M Mainline merging. *** binutils/ChangeLog *** 2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com> * readelf.c (arm_attr_tag_CPU_arch): Add entry for Armv8.1-M Mainline. *** gas/ChangeLog *** 2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com> * config/tc-arm.c (cpu_arch_ver): Add entry for Armv8.1-M Mainline Tag_CPU_arch build attribute value. Reindent. (get_aeabi_cpu_arch_from_fset): Update assert. (aeabi_set_public_attributes): Update assert for Tag_DIV_use logic. * testsuite/gas/arm/attr-march-armv8_1-m.main.d: New test. *** include/ChangeLog *** 2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com> * elf/arm.h (TAG_CPU_ARCH_V8_1M_MAIN): new macro. (MAX_TAG_CPU_ARCH): Set value to above macro. * opcode/arm.h (ARM_EXT2_V8_1M_MAIN): New macro. (ARM_AEXT_V8_1M_MAIN): Likewise. (ARM_AEXT2_V8_1M_MAIN): Likewise. (ARM_ARCH_V8_1M_MAIN): Likewise. *** ld/ChangeLog *** 2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com> * testsuite/ld-arm/attr-merge-13.attr: New test. * testsuite/ld-arm/attr-merge-13a.s: New test. * testsuite/ld-arm/attr-merge-13b.s: New test. *** opcodes/ChangeLog *** 2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com> * arm-dis.c (select_arm_features): Add logic for Armv8.1-M Mainline.
2019-04-15 11:54:42 +02:00
2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
* elf/arm.h (TAG_CPU_ARCH_V8_1M_MAIN): new macro.
(MAX_TAG_CPU_ARCH): Set value to above macro.
* opcode/arm.h (ARM_EXT2_V8_1M_MAIN): New macro.
(ARM_AEXT_V8_1M_MAIN): Likewise.
(ARM_AEXT2_V8_1M_MAIN): Likewise.
(ARM_ARCH_V8_1M_MAIN): Likewise.
[BINUTILS, AArch64, 2/2] Update Store Allocation Tag instructions This patch updates the Store allocation tags instructions in Armv8.5-A Memory Tagging Extension. This is part of the changes that have been introduced recently in the 00bet10 release All of these instructions have an updated register operand (Xt -> <Xt|SP>) - STG <Xt|SP>, [<Xn|SP>, #<simm>] - STG <Xt|SP>, [<Xn|SP>, #<simm>]! - STG <Xt|SP>, [<Xn|SP>], #<simm> - STZG <Xt|SP>, [<Xn|SP>, #<simm>] - STZG <Xt|SP>, [<Xn|SP>, #<simm>]! - STZG <Xt|SP>, [<Xn|SP>], #<simm> - ST2G <Xt|SP>, [<Xn|SP>, #<simm>] - ST2G <Xt|SP>, [<Xn|SP>, #<simm>]! - ST2G <Xt|SP>, [<Xn|SP>], #<simm> - STZ2G <Xt|SP>, [<Xn|SP>, #<simm>] - STZ2G <Xt|SP>, [<Xn|SP>, #<simm>]! - STZ2G <Xt|SP>, [<Xn|SP>], #<simm> In order to accept <Rt|SP> a new operand type Rt_SP is introduced which has the same field as FLD_Rt but follows other semantics of Rn_SP. *** gas/ChangeLog *** 2019-04-11 Sudakshina Das <sudi.das@arm.com> * config/tc-aarch64.c (process_omitted_operand): Add case for AARCH64_OPND_Rt_SP. (parse_operands): Likewise. * testsuite/gas/aarch64/armv8_5-a-memtag.d: Update tests. * testsuite/gas/aarch64/armv8_5-a-memtag.s: Likewise. * testsuite/gas/aarch64/illegal-memtag.l: Likewise. * testsuite/gas/aarch64/illegal-memtag.s: Likewise. *** include/ChangeLog *** 2019-04-11 Sudakshina Das <sudi.das@arm.com> * opcode/aarch64.h (enum aarch64_opnd): Add AARCH64_OPND_Rt_SP. *** opcodes/ChangeLog *** 2019-04-11 Sudakshina Das <sudi.das@arm.com> * aarch64-opc.c (aarch64_print_operand): Add case for AARCH64_OPND_Rt_SP. (verify_constraints): Likewise. * aarch64-tbl.h (QL_LDST_AT): Update to add SP qualifier. (struct aarch64_opcode): Update stg, stzg, st2g, stz2g instructions to accept Rt|SP as first operand. (AARCH64_OPERANDS): Add new Rt_SP. * aarch64-asm-2.c: Regenerated. * aarch64-dis-2.c: Regenerated. * aarch64-opc-2.c: Regenerated.
2019-04-11 11:19:37 +02:00
2019-04-11 Sudakshina Das <sudi.das@arm.com>
* opcode/aarch64.h (enum aarch64_opnd): Add AARCH64_OPND_Rt_SP.
2019-04-08 H.J. Lu <hongjiu.lu@intel.com>
* elf/common.h (GNU_PROPERTY_X86_ISA_1_AVX512_BF16): New.
2019-04-07 13:11:49 +02:00
2019-04-07 Alan Modra <amodra@gmail.com>
Merge from gcc.
2019-04-03 Vineet Gupta <vgupta@synopsys.com>
PR89877
* longlong.h [__arc__] (add_ssaaaa): Add cc clobber.
(sub_ddmmss): Likewise.
x86: Move x86-specific linker options to elf_linker_x86_params Remove x86-specific linker options from bfd_link_info and put them in elf_linker_x86_params. Add _bfd_elf_linker_x86_set_options to pass x86-specific linker options from ld to bfd. bfd/ * elf-linker-x86.h: New file. * elf32-i386.c (elf_i386_convert_load_reloc): Use htab->params to get x86-specific linker options. * elf64-x86-64.c (elf_x86_64_convert_load_reloc): Likewise. (elf_x86_64_check_relocs): Likewise. (elf_x86_64_relocate_section): Likewise. (elf_x86_64_link_setup_gnu_properties): Likewise. * elfxx-x86.c (_bfd_x86_elf_merge_gnu_properties): Likewise. (_bfd_x86_elf_link_setup_gnu_properties): Likewise. (_bfd_elf_linker_x86_set_options): New function. * elfxx-x86.h: Include "elf-linker-x86.h". (elf_x86_link_hash_table): Add params. include/ * bfdlink.h (bfd_link_info): Remove x86-specific linker options. ld/ * Makefile.am (ELF_X86_DEPS): Add $(srcdir)/emultempl/elf-x86.em. (eelf_i386_sol2.c): Also depend on $(srcdir)/emultempl/solaris2-x86.em. (eelf_x86_64_sol2.c): Likewise. * Makefile.in: Regenerated. * emulparams/call_nop.sh: Set x86-specific linker options via params. * emulparams/cet.sh: Likewise. * emulparams/reloc_overflow.sh: Likewise. * emulparams/elf32_x86_64.sh (EXTRA_EM_FILE): New. Set to "elf-x86". * emulparams/elf_i386.sh: Likewise. * emulparams/elf_i386_be.sh: Likewise. * emulparams/elf_i386_chaos.sh: Likewise. * emulparams/elf_i386_ldso.sh: Likewise. * emulparams/elf_i386_vxworks.sh: Likewise. * emulparams/elf_iamcu.sh: Likewise. * emulparams/elf_k1om.sh: Likewise. * emulparams/elf_l1om.sh: Likewise. * emulparams/elf_x86_64.sh: Likewise. * emulparams/elf_i386_sol2.sh (EXTRA_EM_FILE): Changed to "solaris2-x86". * emulparams/elf_x86_64_sol2.sh: Likewise. * emultempl/elf-x86.em: New file. * emultempl/solaris2-x86.em: Likewise. * emultempl/elf32.em (gld${EMULATION_NAME}_before_parse): Don't set link_info.call_nop_byte.
2019-04-06 16:25:10 +02:00
2019-04-06 H.J. Lu <hongjiu.lu@intel.com>
* bfdlink.h (bfd_link_info): Remove x86-specific linker options.
[GAS, Arm] CLI with architecture sensitive extensions This patch adds a new framework to add architecture sensitive extensions, like GCC does. This patch also implements all architecture extensions currently available in GCC. This framework works as follows. To enable architecture sensitive extensions for a particular architecture, that architecture must contain an ARM_ARCH_OPT2 entry in the 'arm_archs' table. All fields here are the same as previous, with the addition of a new extra field at the end to <name> it's extension table. This <name>, corresponds to a <name>_ext_table of type 'struct arm_ext_table'. This struct can be filled with three types of entries: ARM_ADD (string <ext>, arm_feature_set <enable_bits>), which means +<ext> will enable <enable_bits> ARM_REMOVE (string <ext>, arm_feature_set <disable_bits>), which means +no<ext> will disable <disable_bits> ARM_EXT (string <ext>, arm_feature_set <enable_bits>, arm_feature_set <disable_bits>), which means +<ext> will enable <enable_bits> and +no<ext> will disable <disable_bits> (this is to be used instead of adding an ARM_ADD and ARM_REMOVE for the same <ext>) This patch does not disable the use of the old extensions, even if some of them are duplicated in the new tables. This is a "in-between-step" as we may want to deprecate the old table of extensions in later patches. For now, GAS will first look for the +<ext> or +no<ext> in the new table and if no entry is found it will continue searching in the old table, following old behaviour. If only an ARM_ADD or an ARM_REMOVE is defined for <ext> and +no<ext> or +<ext> resp. is used then it also continues to search the old table for it. A couple of caveats: - This patch does not enable the use of these architecture extensions with the '.arch_extension' directive. This is future work that I will tend to later. - This patch does not enable the use of these architecture extensions with the -mcpu option. This is future work that I will tend to later. - This patch does not change the current behaviour when combining an architecture extension and using -mfpu on the command-line. The current behaviour of GAS is to stage the union of feature bits enabled by both -march and -mfpu. GCC behaves differently here, so this is something we may want to revisit on a later date.
2019-04-01 11:43:32 +02:00
2019-04-01 Andre Vieira <andre.simoesdiasvieira@arm.com>
* opcode/arm.h (FPU_NEON_ARMV8_1): New.
(FPU_ARCH_NEON_VFP_ARMV8_1): Use FPU_NEON_ARMV8_1.
(FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_1): Likewise.
(FPU_ARCH_DOTPROD_NEON_VFP_ARMV8): Likewise.
(FPU_ARCH_NEON_VFP_ARMV8_2_FP16): New.
(FPU_ARCH_NEON_VFP_ARMV8_2_FP16FML): New.
(FPU_ARCH_NEON_VFP_ARMV8_4_FP16FML): New.
(FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_4): New.
2019-03-28 Alan Modra <amodra@gmail.com>
PR 24390
* opcode/ppc.h (PPC_OPERAND_CR_REG): Comment.
2019-03-25 Tamar Christina <tamar.christina@arm.com>
* dis-asm.h (struct disassemble_info): Add stop_offset.
[BFD, LD, AArch64, 3/3] Add --pac-plt to enable PLTs protected with PAC. This is part of the patch series to add support for BTI and PAC in AArch64 linker. 1) This patch adds new definitions of PAC enabled PLTs and both BTI and PAC enabled PLTs. 2) It also defines the new dynamic tag DT_AARCH64_PAC_PLT for the PAC enabled PLTs. 3) This patch adds a new ld command line option: --pac-plt. In the presence of this option, the linker uses the PAC enabled PLTs and marks with DT_AARCH64_PAC_PLT. 4) In case both BTI and PAC are enabled the linker should pick PLTs enabled with both and also use dynamic tags for both. All these are made according to the new AArch64 ELF ABI https://developer.arm.com/docs/ihi0056/latest/elf-for-the-arm-64-bit-architecture-aarch64-abi-2018q4 *** bfd/ChangeLog *** 2019-03-13 Sudakshina Das <sudi.das@arm.com> * elfnn-aarch64.c (PLT_PAC_ENTRY_SIZE, PLT_PAC_SMALL_ENTRY_SIZE): New. (PLT_BTI_PAC_ENTRY_SIZE, PLT_BTI_PAC_SMALL_ENTRY_SIZE): New. (setup_plt_values): Account for PAC or PAC and BTI enabled PLTs. (elfNN_aarch64_size_dynamic_sections): Add checks for PLT_BTI_PAC and PLT_PAC_PLT. (elfNN_aarch64_finish_dynamic_sections): Account for PLT_BTI_PAC. (get_plt_type): Add case for DT_AARCH64_PAC_PLT. (elfNN_aarch64_plt_sym_val): Add cases for PLT_BTI_PAC and PLT_PAC. *** binutils/ChangeLog *** 2019-03-13 Sudakshina Das <sudi.das@arm.com> * readelf.c (get_aarch64_dynamic_type): Add case for DT_AARCH64_PAC_PLT. (dynamic_section_aarch64_val): Likewise. *** include/ChangeLog *** 2019-03-13 Sudakshina Das <sudi.das@arm.com> * elf/aarch64.h (DT_AARCH64_PAC_PLT): New. *** ld/ChangeLog *** 2019-03-13 Sudakshina Das <sudi.das@arm.com> * NEWS: Document --pac-plt. * emultempl/aarch64elf.em (OPTION_PAC_PLT): New. (PARSE_AND_LIST_LONGOPTS, PARSE_AND_LIST_OPTIONS): Add pac-plt. (PARSE_AND_LIST_ARGS_CASES): Handle OPTION_PAC_PLT. * testsuite/ld-aarch64/aarch64-elf.exp: Add the following tests. * testsuite/ld-aarch64/bti-pac-plt-1.d: New test. * testsuite/ld-aarch64/bti-pac-plt-2.d: New test. * testsuite/ld-aarch64/pac-plt-1.d: New test. * testsuite/ld-aarch64/pac-plt-2.d: New test. * testsuite/ld-aarch64/bti-plt-1.s: Add .ifndef directive.
2019-03-13 12:09:10 +01:00
2019-03-13 Sudakshina Das <sudi.das@arm.com>
* elf/aarch64.h (DT_AARCH64_PAC_PLT): New.
[BFD, LD, AArch64, 2/3] Add --force-bti to enable BTI and to select BTI enabled PLTs This is part of the patch series to add support for BTI and PAC in AArch64 linker. 1) This patch adds a new ld command line option: --force-bti. In the presence of this option, the linker enables BTI with the GNU_PROPERTY_AARCH64_FEATURE_1_BTI feature. This gives out warning in case of missing gnu notes for BTI in inputs. 2) It also defines a new set of BTI enabled PLTs. These are used either when all the inputs are marked with GNU_PROPERTY_AARCH64_FEATURE_1_BTI or when the new --force-bti option is used. This required adding new fields in elf_aarch64_link_hash_table so that we could make the PLT related information more generic. 3) It also defines a dynamic tag DT_AARCH64_BTI_PLT. The linker uses this whenever it picks BTI enabled PLTs. All these are made according to the new AArch64 ELF ABI https://developer.arm.com/docs/ihi0056/latest/elf-for-the-arm-64-bit-architecture-aarch64-abi-2018q4 *** bfd/ChangeLog *** 2019-03-13 Sudakshina Das <sudi.das@arm.com> Szabolcs Nagy <szabolcs.nagy@arm.com> * bfd-in.h (aarch64_plt_type, aarch64_enable_bti_type): New. (aarch64_bti_pac_info): New. (bfd_elf64_aarch64_set_options): Add aarch64_bti_pac_info argument. (bfd_elf32_aarch64_set_options): Likewise. * bfd-in2.h: Regenerate * elfnn-aarch64.c (PLT_BTI_ENTRY_SIZE): New. (PLT_BTI_SMALL_ENTRY_SIZE, PLT_BTI_TLSDESC_ENTRY_SIZE): New. (elfNN_aarch64_small_plt0_bti_entry): New. (elfNN_aarch64_small_plt_bti_entry): New. (elfNN_aarch64_tlsdesc_small_plt_bti_entry): New. (elf_aarch64_obj_tdata): Add no_bti_warn and plt_type fields. (elf_aarch64_link_hash_table): Add plt0_entry, plt_entry and tlsdesc_plt_entry_size fields. (elfNN_aarch64_link_hash_table_create): Initialise the new fields. (setup_plt_values): New helper function. (bfd_elfNN_aarch64_set_options): Use new bp_info to set plt sizes and bti enable type. (elfNN_aarch64_allocate_dynrelocs): Use new size members instead of fixed macros. (elfNN_aarch64_size_dynamic_sections): Likewise and add checks. (elfNN_aarch64_create_small_pltn_entry): Use new generic pointers to plt stubs instead of fixed ones and update filling them according to the need for bti. (elfNN_aarch64_init_small_plt0_entry): Likewise. (elfNN_aarch64_finish_dynamic_sections): Likewise. (get_plt_type, elfNN_aarch64_get_synthetic_symtab): New. (elfNN_aarch64_plt_sym_val): Update size accordingly. (elfNN_aarch64_link_setup_gnu_properties): Set up plts if BTI GNU NOTE is set. (bfd_elfNN_get_synthetic_symtab): Define. (elfNN_aarch64_merge_gnu_properties): Give out warning with --force-bti and mising BTI NOTE SECTION. *** binutils/ChangeLog *** 2019-03-13 Sudakshina Das <sudi.das@arm.com> Szabolcs Nagy <szabolcs.nagy@arm.com> * readelf.c (get_aarch64_dynamic_type): New. (get_dynamic_type): Use above for EM_AARCH64. (dynamic_section_aarch64_val): New. (process_dynamic_section): Use above for EM_AARCH64. *** include/ChangeLog *** 2019-03-13 Sudakshina Das <sudi.das@arm.com> Szabolcs Nagy <szabolcs.nagy@arm.com> * elf/aarch64.h (DT_AARCH64_BTI_PLT): New. *** ld/ChangeLog *** 2019-03-13 Sudakshina Das <sudi.das@arm.com> Szabolcs Nagy <szabolcs.nagy@arm.com> * NEWS: Document --force-bti. * emultempl/aarch64elf.em (plt_type, bti_type, OPTION_FORCE_BTI): New. (PARSE_AND_LIST_SHORTOPTS, PARSE_AND_LIST_OPTIONS): Add force-bti. (PARSE_AND_LIST_ARGS_CASES): Handle OPTION_FORCE_BTI. * testsuite/ld-aarch64/aarch64-elf.exp: Add all the tests below. * testsuite/ld-aarch64/bti-plt-1.d: New test. * testsuite/ld-aarch64/bti-plt-1.s: New test. * testsuite/ld-aarch64/bti-plt-2.s: New test. * testsuite/ld-aarch64/bti-plt-2.d: New test. * testsuite/ld-aarch64/bti-plt-3.d: New test. * testsuite/ld-aarch64/bti-plt-4.d: New test. * testsuite/ld-aarch64/bti-plt-5.d: New test. * testsuite/ld-aarch64/bti-plt-6.d: New test. * testsuite/ld-aarch64/bti-plt-7.d: New test. * testsuite/ld-aarch64/bti-plt-so.s: New test. * testsuite/ld-aarch64/bti-plt.ld: New test.
2019-03-13 11:54:30 +01:00
2019-03-13 Sudakshina Das <sudi.das@arm.com>
Szabolcs Nagy <szabolcs.nagy@arm.com>
* elf/aarch64.h (DT_AARCH64_BTI_PLT): New.
[BFD, LD, AArch64, 1/3] Add support for GNU PROPERTIES in AArch64 for BTI and PAC This is part of the patch series to add support for BTI and PAC in AArch64 linker. This patch implements the following: 1) This extends in the gnu property support in the linker for AArch64 by defining backend hooks for elf_backend_setup_gnu_properties, elf_backend_merge_gnu_properties and elf_backend_parse_gnu_properties. 2) It defines AArch64 specific GNU property GNU_PROPERTY_AARCH64_FEATURE_1_AND and 2 bit for BTI and PAC in it. 3) It also adds support in readelf.c to read and print these new GNU properties in AArch64. All these are made according to the new AArch64 ELF ABI https://developer.arm.com/docs/ihi0056/latest/elf-for-the-arm-64-bit-architecture-aarch64-abi-2018q4 *** bfd/ChangeLog *** 2019-03-13 Sudakshina Das <sudi.das@arm.com> * elf-properties.c (_bfd_elf_link_setup_gnu_properties): Exclude linker created inputs from merge. * elfnn-aarch64.c (struct elf_aarch64_obj_tdata): Add field for GNU_PROPERTY_AARCH64_FEATURE_1_AND properties. (elfNN_aarch64_link_setup_gnu_properties): New. (elfNN_aarch64_merge_gnu_properties): New. (elf_backend_setup_gnu_properties): Define for AArch64. (elf_backend_merge_gnu_properties): Likewise. * elfxx-aarch64.c (_bfd_aarch64_elf_link_setup_gnu_properties): Define. (_bfd_aarch64_elf_parse_gnu_properties): Define. (_bfd_aarch64_elf_merge_gnu_properties): Define. * elfxx-aarch64.h (_bfd_aarch64_elf_link_setup_gnu_properties): Declare. (_bfd_aarch64_elf_parse_gnu_properties): Declare. (_bfd_aarch64_elf_merge_gnu_properties): Declare. (elf_backend_parse_gnu_properties): Define for AArch64. *** binutils/ChangeLog *** 2019-03-13 Sudakshina Das <sudi.das@arm.com> * readelf.c (decode_aarch64_feature_1_and): New. (print_gnu_property_note): Add case for AArch64 gnu notes. *** include/ChangeLog *** 2019-03-13 Sudakshina Das <sudi.das@arm.com> * elf/common.h (GNU_PROPERTY_AARCH64_FEATURE_1_AND): New. (GNU_PROPERTY_AARCH64_FEATURE_1_BTI): New. (GNU_PROPERTY_AARCH64_FEATURE_1_PAC): New. *** ld/ChangeLog *** 2019-03-13 Sudakshina Das <sudi.das@arm.com> * NEWS: Document GNU_PROPERTY_AARCH64_FEATURE_1_BTI and GNU_PROPERTY_AARCH64_FEATURE_1_PAC. * testsuite/ld-aarch64/aarch64-elf.exp: Add run commands for new tests. * testsuite/ld-aarch64/property-bti-pac1.d: New test. * testsuite/ld-aarch64/property-bti-pac1.s: New test. * testsuite/ld-aarch64/property-bti-pac2.d: New test. * testsuite/ld-aarch64/property-bti-pac2.s: New test. * testsuite/ld-aarch64/property-bti-pac3.d: New test.
2019-03-13 11:42:27 +01:00
2019-03-13 Sudakshina Das <sudi.das@arm.com>
* elf/common.h (GNU_PROPERTY_AARCH64_FEATURE_1_AND): New.
(GNU_PROPERTY_AARCH64_FEATURE_1_BTI): New.
(GNU_PROPERTY_AARCH64_FEATURE_1_PAC): New.
2019-02-20 Alan Hayward <alan.hayward@arm.com>
* elf/common.h (NT_ARM_PAC_MASK): Add define.
2019-02-15 Saagar Jha <saagar@saagarjha.com>
* mach-o/loader.h: Use new OS names in comments.
2019-02-11 Philippe Waroquiers <philippe.waroquiers@skynet.be>
* splay-tree.h (splay_tree_delete_key_fn): Update comment.
(splay_tree_delete_value_fn): Likewise.
2019-01-31 Andreas Krebbel <krebbel@linux.ibm.com>
* opcode/s390.h (enum s390_opcode_cpu_val): Add
S390_OPCODE_ARCH13.
AArch64: Remove ldgv and stgv instructions from Armv8.5-A Memory Tagging Extension. This patch is part of a series of patches to introduce a few changes to the Armv8.5-A Memory Tagging Extension. This patch removes the LDGV and STGV instructions. These instructions needed special infrastructure to support [base]! style for addressing mode. That is also removed now. Committed on behalf of Sudakshina Das. *** gas/ChangeLog *** * config/tc-aarch64.c (parse_address_main): Remove support for [base]! address expression. (parse_operands): Remove support for AARCH64_OPND_ADDR_SIMPLE_2. (warn_unpredictable_ldst): Remove support for ldstgv_indexed. * testsuite/gas/aarch64/armv8_5-a-memtag.d: Remove tests for ldgv and stgv. * testsuite/gas/aarch64/armv8_5-a-memtag.s: Likewise. * testsuite/gas/aarch64/illegal-memtag.l: Likewise. * testsuite/gas/aarch64/illegal-memtag.s: Likewise. *** include/ChangeLog *** * opcode/aarch64.h (enum aarch64_opnd): Remove AARCH64_OPND_ADDR_SIMPLE_2. (enum aarch64_insn_class): Remove ldstgv_indexed. *** opcodes/ChangeLog *** * aarch64-asm.c (aarch64_ins_addr_simple_2): Remove. * aarch64-asm.h (ins_addr_simple_2): Likeiwse. * aarch64-dis.c (aarch64_ext_addr_simple_2): Likewise. * aarch64-dis.h (ext_addr_simple_2): Likewise. * aarch64-opc.c (operand_general_constraint_met_p): Remove case for ldstgv_indexed. (aarch64_print_operand): Remove case for AARCH64_OPND_ADDR_SIMPLE_2. * aarch64-tbl.h (struct aarch64_opcode): Remove ldgv and stgv. (AARCH64_OPERANDS): Remove ADDR_SIMPLE_2. * aarch64-asm-2.c: Regenerated. * aarch64-dis-2.c: Regenerated. * aarch64-opc-2.c: Regenerated.
2019-01-25 14:57:14 +01:00
2019-01-25 Sudakshina Das <sudi.das@arm.com>
Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
* opcode/aarch64.h (enum aarch64_opnd): Remove
AARCH64_OPND_ADDR_SIMPLE_2.
(enum aarch64_insn_class): Remove ldstgv_indexed.
2019-01-22 Tom Tromey <tom@tromey.com>
* coff/ecoff.h: Include coff/sym.h.
2018-06-24 Nick Clifton <nickc@redhat.com>
2.32 branch created.
RISC-V: Support ELF attribute for gas and readelf. 2019-01-16 Kito Cheng <kito@andestech.com> Nelson Chu <nelson@andestech.com> bfd/ * elfnn-riscv.c (riscv_elf_obj_attrs_arg_type): New. (elf_backend_obj_attrs_vendor): Define. (elf_backend_obj_attrs_section_type): Likewise. (elf_backend_obj_attrs_section): Likewise. (elf_backend_obj_attrs_arg_type): Define as riscv_elf_obj_attrs_arg_type. * elfxx-riscv.c (riscv_estimate_digit): New. (riscv_estimate_arch_strlen1): Likewise. (riscv_estimate_arch_strlen): Likewise. (riscv_arch_str1): Likewise. (riscv_arch_str): Likewise. * elfxx-riscv.h (riscv_arch_str): Declare. binutils/ * readelf.c (get_riscv_section_type_name): New function. (get_section_type_name): Add handler for RISC-V. (riscv_attr_tag_t): Declare. (riscv_attr_tag): New. (display_riscv_attribute): New function. (process_attributes): Add handler for RISC-V. * testsuite/binutils-all/strip-3.d: Remove .riscv.attribute section. gas/ * config/tc-riscv.c (DEFAULT_RISCV_ATTR): Define to 0 if not defined. (riscv_set_options): Add `arch_attr` field. (riscv_opts): Set default value for arch_attr. (riscv_write_out_arch_attr): New. (riscv_set_public_attributes): Likewise. (riscv_md_end): Likewise. (riscv_convert_symbolic_attribute): Likewise. (s_riscv_attribute): Likewise. (explicit_arch_attr): Likewise. (riscv_pseudo_table): Add .attribute to the table. (options): Add OPTION_ARCH_ATTR and OPTION_NO_ARCH_ATTR enumeration constants. (md_longopts): Add `march-attr' and `mno-arch-attr' options. (md_parse_option): Handle the new options. (md_show_usage): Document the `march-attr' option. * config/tc-riscv.h (md_end): Define as riscv_md_end (riscv_md_end): Declare. (CONVERT_SYMBOLIC_ATTRIBUTE): Define as riscv_convert_symbolic_attribute. (riscv_convert_symbolic_attribute): Declare. (start_assemble): Declare. * testsuite/gas/elf/elf.exp: Adjust test case for section2.e. * testsuite/gas/elf/section2.e-riscv: New. * testsuite/gas/riscv/attribute-01.d: New test * testsuite/gas/riscv/attribute-02.d: Likewise. * testsuite/gas/riscv/attribute-03.d: Likewise. * testsuite/gas/riscv/attribute-04.d: Likewise. * testsuite/gas/riscv/attribute-04.s: Likewise. * testsuite/gas/riscv/attribute-05.d: Likewise. * testsuite/gas/riscv/attribute-05.s: Likewise. * testsuite/gas/riscv/attribute-06.d: Likewise. * testsuite/gas/riscv/attribute-06.s: Likewise. * testsuite/gas/riscv/attribute-07.d: Likewise. * testsuite/gas/riscv/attribute-07.s: Likewise. * testsuite/gas/riscv/attribute-08.d: Likewise. * testsuite/gas/riscv/attribute-08.s: Likewise. * testsuite/gas/riscv/attribute-unknown.d: Likewise. * testsuite/gas/riscv/attribute-unknown.s: Likewise. * testsuite/gas/riscv/empty.l: Likewise. * doc/c-riscv.texi (.attribute): Add documentation. * configure.ac (--enable-default-riscv-attribute): New options. * configure: Re-generate. * config.in: Re-generate. include/ * elf/riscv.h (SHT_RISCV_ATTRIBUTES): Define. (Tag_RISCV_arch): Likewise. (Tag_RISCV_priv_spec): Likewise. (Tag_RISCV_priv_spec_minor): Likewise. (Tag_RISCV_priv_spec_revision): Likewise. (Tag_RISCV_unaligned_access): Likewise. (Tag_RISCV_stack_align): Likewise.
2019-01-16 22:14:59 +01:00
2019-01-16 Kito Cheng <kito@andestech.com>
* elf/riscv.h (SHT_RISCV_ATTRIBUTES): Define.
(Tag_RISCV_arch): Likewise.
(Tag_RISCV_priv_spec): Likewise.
(Tag_RISCV_priv_spec_minor): Likewise.
(Tag_RISCV_priv_spec_revision): Likewise.
(Tag_RISCV_unaligned_access): Likewise.
(Tag_RISCV_stack_align): Likewise.
2019-01-14 Pavel I. Kryukov <kryukov@frtk.ru>
* dis-asm.h: include <string.h>
2019-01-10 Nick Clifton <nickc@redhat.com>
* Merge from GCC:
2018-12-22 Jason Merrill <jason@redhat.com>
* demangle.h: Remove support for ancient GNU (pre-3.0), Lucid,
ARM, HP, and EDG demangling styles.
2019-01-09 Sandra Loosemore <sandra@codesourcery.com>
Merge from GCC:
PR other/16615
* libiberty.h: Mechanically replace "can not" with "cannot".
* plugin-api.h: Likewise.
2018-12-25 Yoshinori Sato <ysato@users.sourceforge.jp>
* elf/rx.h (EF_RX_CPU_MASK): Update new bits.
(E_FLAG_RX_V3): New RXv3 type.
* opcode/rx.h (RX_Size): Add double size.
(RX_Operand_Type): Add double FPU registers.
(RX_Opcode_ID): Add new instuctions.
2019-01-01 Alan Modra <amodra@gmail.com>
Update year range in copyright notice of all files.
2019-01-01 11:53:15 +01:00
For older changes see ChangeLog-2018
2019-01-01 11:53:15 +01:00
Copyright (C) 2019 Free Software Foundation, Inc.
Copying and distribution of this file, with or without modification,
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