561a72d4dd
Modify AArch64 Assembly and disassembly functions to be able to fail and report why.
...
This patch if the first patch in a series to add the ability to add constraints
to system registers that an instruction must adhere to in order for the register
to be usable with that instruction.
These constraints can also be used to disambiguate between registers with the
same encoding during disassembly.
This patch adds a new flags entry in the sysreg structures and ensures it is
filled in and read out during assembly/disassembly. It also adds the ability for
the assemble and disassemble functions to be able to gracefully fail and re-use
the existing error reporting infrastructure.
The return type of these functions are changed to a boolean to denote success or
failure and the error structure is passed around to them. This requires
aarch64-gen changes so a lot of the changes here are just mechanical.
gas/
PR binutils/21446
* config/tc-aarch64.c (parse_sys_reg): Return register flags.
(parse_operands): Fill in register flags.
gdb/
PR binutils/21446
* aarch64-tdep.c (aarch64_analyze_prologue,
aarch64_software_single_step, aarch64_displaced_step_copy_insn):
Indicate not interested in errors.
include/
PR binutils/21446
* opcode/aarch64.h (aarch64_opnd_info): Change sysreg to struct.
(aarch64_decode_insn): Accept error struct.
opcodes/
PR binutils/21446
* aarch64-asm.h (aarch64_insert_operand, aarch64_##x): Return boolean
and take error struct.
* aarch64-asm.c (aarch64_ext_regno, aarch64_ins_reglane,
aarch64_ins_reglist, aarch64_ins_ldst_reglist,
aarch64_ins_ldst_reglist_r, aarch64_ins_ldst_elemlist,
aarch64_ins_advsimd_imm_shift, aarch64_ins_imm, aarch64_ins_imm_half,
aarch64_ins_advsimd_imm_modified, aarch64_ins_fpimm,
aarch64_ins_imm_rotate1, aarch64_ins_imm_rotate2, aarch64_ins_fbits,
aarch64_ins_aimm, aarch64_ins_limm_1, aarch64_ins_limm,
aarch64_ins_inv_limm, aarch64_ins_ft, aarch64_ins_addr_simple,
aarch64_ins_addr_regoff, aarch64_ins_addr_offset, aarch64_ins_addr_simm,
aarch64_ins_addr_simm10, aarch64_ins_addr_uimm12,
aarch64_ins_simd_addr_post, aarch64_ins_cond, aarch64_ins_sysreg,
aarch64_ins_pstatefield, aarch64_ins_sysins_op, aarch64_ins_barrier,
aarch64_ins_prfop, aarch64_ins_hint, aarch64_ins_reg_extended,
aarch64_ins_reg_shifted, aarch64_ins_sve_addr_ri_s4xvl,
aarch64_ins_sve_addr_ri_s6xvl, aarch64_ins_sve_addr_ri_s9xvl,
aarch64_ins_sve_addr_ri_s4, aarch64_ins_sve_addr_ri_u6,
aarch64_ins_sve_addr_rr_lsl, aarch64_ins_sve_addr_rz_xtw,
aarch64_ins_sve_addr_zi_u5, aarch64_ext_sve_addr_zz,
aarch64_ins_sve_addr_zz_lsl, aarch64_ins_sve_addr_zz_sxtw,
aarch64_ins_sve_addr_zz_uxtw, aarch64_ins_sve_aimm,
aarch64_ins_sve_asimm, aarch64_ins_sve_index, aarch64_ins_sve_limm_mov,
aarch64_ins_sve_quad_index, aarch64_ins_sve_reglist,
aarch64_ins_sve_scale, aarch64_ins_sve_shlimm, aarch64_ins_sve_shrimm,
aarch64_ins_sve_float_half_one, aarch64_ins_sve_float_half_two,
aarch64_ins_sve_float_zero_one, aarch64_opcode_encode): Likewise.
* aarch64-dis.h (aarch64_extract_operand, aarch64_##x): Likewise.
* aarch64-dis.c (aarch64_ext_regno, aarch64_ext_reglane,
aarch64_ext_reglist, aarch64_ext_ldst_reglist,
aarch64_ext_ldst_reglist_r, aarch64_ext_ldst_elemlist,
aarch64_ext_advsimd_imm_shift, aarch64_ext_imm, aarch64_ext_imm_half,
aarch64_ext_advsimd_imm_modified, aarch64_ext_fpimm,
aarch64_ext_imm_rotate1, aarch64_ext_imm_rotate2, aarch64_ext_fbits,
aarch64_ext_aimm, aarch64_ext_limm_1, aarch64_ext_limm, decode_limm,
aarch64_ext_inv_limm, aarch64_ext_ft, aarch64_ext_addr_simple,
aarch64_ext_addr_regoff, aarch64_ext_addr_offset, aarch64_ext_addr_simm,
aarch64_ext_addr_simm10, aarch64_ext_addr_uimm12,
aarch64_ext_simd_addr_post, aarch64_ext_cond, aarch64_ext_sysreg,
aarch64_ext_pstatefield, aarch64_ext_sysins_op, aarch64_ext_barrier,
aarch64_ext_prfop, aarch64_ext_hint, aarch64_ext_reg_extended,
aarch64_ext_reg_shifted, aarch64_ext_sve_addr_ri_s4xvl,
aarch64_ext_sve_addr_ri_s6xvl, aarch64_ext_sve_addr_ri_s9xvl,
aarch64_ext_sve_addr_ri_s4, aarch64_ext_sve_addr_ri_u6,
aarch64_ext_sve_addr_rr_lsl, aarch64_ext_sve_addr_rz_xtw,
aarch64_ext_sve_addr_zi_u5, aarch64_ext_sve_addr_zz,
aarch64_ext_sve_addr_zz_lsl, aarch64_ext_sve_addr_zz_sxtw,
aarch64_ext_sve_addr_zz_uxtw, aarch64_ext_sve_aimm,
aarch64_ext_sve_asimm, aarch64_ext_sve_index, aarch64_ext_sve_limm_mov,
aarch64_ext_sve_quad_index, aarch64_ext_sve_reglist,
aarch64_ext_sve_scale, aarch64_ext_sve_shlimm, aarch64_ext_sve_shrimm,
aarch64_ext_sve_float_half_one, aarch64_ext_sve_float_half_two,
aarch64_ext_sve_float_zero_one, aarch64_opcode_decode): Likewise.
(determine_disassembling_preference, aarch64_decode_insn,
print_insn_aarch64_word, print_insn_data): Take errors struct.
(print_insn_aarch64): Use errors.
* aarch64-asm-2.c: Regenerate.
* aarch64-dis-2.c: Regenerate.
* aarch64-gen.c (print_operand_inserter): Use errors and change type to
boolean in aarch64_insert_operan.
(print_operand_extractor): Likewise.
* aarch64-opc.c (aarch64_print_operand): Use sysreg struct.
2018-05-15 17:17:36 +01:00
1678bd35a3
Fix error messages in the NFP sources when building for 32-bit targets.
...
bfd * targets.c: Wrap nfp_elf64_vec in BFD64 ifdef.
include * opcode/nfp.h: Use uint64_t instead of bfd_vma.
opcodes * nfp-dis.c: Use uint64_t for instruction variables, not bfd_vma.
2018-05-15 13:28:06 +01:00
06cfb1c895
x86: Remove Disp<N> from movidir{i,64b}
...
* i386-opc.tbl: Remove Disp<N> from movidir{i,64b}.
2018-05-09 11:17:26 -07:00
84f9f8c330
PR22069, Several instances of register accidentally spelled as regsiter
...
PR 22069
binutils/
* od-macho.c (dump_unwind_encoding_x86): Adjust for macro renaming.
cpu/ChangeLog
* or1kcommon.cpu (spr-reg-info): Typo fix.
include/ChangeLog
* mach-o/unwind.h (MACH_O_UNWIND_X86_64_RBP_FRAME_REGISTERS):
Rename from MACH_O_UNWIND_X86_64_RBP_FRAME_REGSITERS.
(MACH_O_UNWIND_X86_EBP_FRAME_REGISTERS): Rename from
MACH_O_UNWIND_X86_EBP_FRAME_REGSITERS.
opcodes/ChangeLog
* cr16-opc.c (cr16_instruction): Comment typo fix.
* hppa-dis.c (print_insn_hppa): Likewise.
sim/ppc/ChangeLog
* e500_registers.h: Comment typo fix.
* ppc-instructions (ppc_insn_mfcr): Likewise.
2018-05-09 15:55:28 +09:30
e6f372ba66
RISC-V: Add missing hint instructions from RV128I.
...
gas/
* testsuite/gas/riscv/c-zero-imm.d: Add more tests.
* testsuite/gas/riscv/c-zero-imm.s: Likewise.
* testsuite/gas/riscv/c-zero-reg.d: Fix typo in test. Add disabled
future test for RV128 support.
* testsuite/gas/riscv/c-zero-reg.s: Likewise.
include/
* opcode/riscv-opc.h (MATCH_C_SRLI64, MASK_C_SRLI64): New.
(MATCH_C_SRAI64, MASK_C_SRAI64): New.
(MATCH_C_SLLI64, MASK_C_SLLI64): New.
opcodes/
* riscv-opc.c (match_c_slli, match_slli_as_c_slli): New.
(match_c_slli64, match_srxi_as_c_srxi): New.
(riscv_opcodes) <slli, sll>: Use match_slli_as_c_slli.
<srli, srl, srai, sra>: Use match_srxi_as_c_srxi.
<c.slli, c.srli, c.srai>: Use match_s_slli.
<c.slli64, c.srli64, c.srai64>: New.
2018-05-08 15:46:19 -07:00
f413a91378
Correct powerpc spe opcode lookup
...
Defining SPE2_OPCD_SEGS as 13 discounts the possibility that we'd
ever look up spe2_opcd_indices[14..16], which I think is possible.
Extend that array to size 16+1, using the macros we use to index the
array. Similarly use the index macros for PPC_OPCD_SEGS and
VLE_OPCD_SEGS.
* ppc-dis.c (PPC_OPCD_SEGS): Define using PPC_OP.
(VLE_OPCD_SEGS, SPE2_OPCD_SEGS): Similarly, using macros used to
partition opcode space for index lookup.
2018-05-08 22:28:44 +09:30
a87a64780f
Simplify VLE handling in print_insn_powerpc().
...
opcodes/
* ppc-dis.c (print_insn_powerpc) <insn_is_short>: Replace this...
<insn_length>: ...with this. Update usage.
Remove duplicate call to *info->memory_error_func.
2018-05-07 20:47:54 -05:00
c0a30a9f0a
Enable Intel MOVDIRI, MOVDIR64B instructions
...
gas/
* config/tc-i386.c (cpu_arch): Add .movdir, .movdir64b.
(cpu_noarch): Likewise.
(process_suffix): Add check for register size.
* doc/c-i386.texi: Document movdiri, movdir64b.
* testsuite/gas/i386/i386.exp: Run MOVDIR{I,64B} tests.
* testsuite/gas/i386/movdir-intel.d: New file.
* testsuite/gas/i386/movdir.d: Likewise.
* testsuite/gas/i386/movdir.s: Likewise.
* testsuite/gas/i386/movdir64b-reg.s: Likewise.
* testsuite/gas/i386/movdir64b-reg.l: Likewise.
* testsuite/gas/i386/x86-64-movdir-intel.d: Likewise.
* testsuite/gas/i386/x86-64-movdir.d: Likewise.
* testsuite/gas/i386/x86-64-movdir.s: Likewise.
* testsuite/gas/i386/x86-64-movdir64b-reg.s: Likewise.
* testsuite/gas/i386/x86-64-movdir64b-reg.l: Likewise.
opcodes/
* i386-dis.c (Gva): New.
(enum): Add PREFIX_0F38F8, PREFIX_0F38F9,
MOD_0F38F8_PREFIX_2, MOD_0F38F9_PREFIX_0.
(prefix_table): New instructions (see prefix above).
(mod_table): New instructions (see prefix above).
(OP_G): Handle va_mode.
* i386-gen.c (cpu_flag_init): Add CPU_MOVDIRI_FLAGS,
CPU_MOVDIR64B_FLAGS.
(cpu_flags): Add CpuMOVDIRI and CpuMOVDIR64B.
* i386-opc.h (enum): Add CpuMOVDIRI, CpuMOVDIR64B.
(i386_cpu_flags): Add cpumovdiri and cpumovdir64b.
* i386-opc.tbl: Add movidir{i,64b}.
* i386-init.h: Regenerated.
* i386-tbl.h: Likewise.
2018-05-07 16:57:48 -07:00
75c0a43899
x86: Replace AddrPrefixOp0 with AddrPrefixOpReg
...
This patch replaces AddrPrefixOp0 with AddrPrefixOpReg to indicate that
the size of register operand is controlled by the address size prefix.
This will be used by Intel MOVDIRI and MOVDIR64B instructions later.
gas/
* config/tc-i386.c (process_suffix): Check addrprefixopreg
instead of addrprefixop0.
opcodes/
* i386-gen.c (opcode_modifiers): Replace AddrPrefixOp0 with
AddrPrefixOpReg.
* i386-opc.h (AddrPrefixOp0): Renamed to ...
(AddrPrefixOpReg): This.
(i386_opcode_modifier): Rename addrprefixop0 to addrprefixopreg.
* i386-opc.tbl: Replace AddrPrefixOp0 with AddrPrefixOpReg.
2018-05-07 09:57:06 -07:00
2ceb7719f7
Cleanup ppc code dealing with opcode dumps.
...
include/
* opcode/ppc.h (powerpc_num_opcodes): Change type to unsigned.
(vle_num_opcodes): Likewise.
(spe2_num_opcodes): Likewise.
opcodes/
* ppc-opc.c (powerpc_num_opcodes): Likewise.
(vle_num_opcodes): Likewise.
(spe2_num_opcodes): Likewise.
* ppc-dis.c (disassemble_init_powerpc) <powerpc_opcd_indices>: Rewrite
initialization loop.
(disassemble_init_powerpc) <vle_opcd_indices>: Likewise.
(disassemble_init_powerpc) <spe2_opcd_indices>: Likewise. Initialize
only once.
gas/
* config/tc-ppc.c (ppc_setup_opcodes) <powerpc_opcodes>: Rewrite code
to dump the entire opcode table.
(ppc_setup_opcodes) <spe2_opcodes>: Likewise.
(ppc_setup_opcodes) <vle_opcodes>: Likewise. Fix calculation of
opcode index.
2018-05-07 09:40:59 -05:00
b3ac5c6c28
Fix unintialized memory in aarch64 opcodes.
...
This patch fixes an issue where the memory for the opcode structure is not zero'd before
the first exit branch. So there is one failure mode for which uninitialized memory
is returned.
This causes weird failures when the return code is not checked before inst is used.
opcodes/
* aarch64-dis.c (aarch64_opcode_decode): Moved memory clear code.
2018-05-01 17:12:58 +01:00
fe944acf8f
This patch adds support to objdump for disassembly of NFP (Netronome Flow Processor) ELF files (.nffw) as well as some basic readelf support.
...
bfd * Makefile.am: Added NFP files to build.
* archures.c: Added bfd_arch_nfp
* config.bfd: Added NFP support.
* configure.ac: Added NFP support.
* cpu-nfp.c: New, for NFP support.
* elf-bfd.h: Added elf_section_info()
* elf64-nfp.c: New, for NFP support.
* po/SRC-POTFILES.in: Added NFP source files.
* targets.c: Added nfp_elf64_vec
* bfd-in2.h: Regenerate.
* Makefile.in: Regenerate.
* configure: Regenerate.
binutils* readelf.c: Very basic support for EM_NFP and its section types.
* testsuite/binutils-all/nfp: New directory.
* testsuite/binutils-all/nfp/objdump.exp: New file. Run new
tests.
* testsuite/binutils-all/nfp/test2_ctx8.d: New file.
* testsuite/binutils-all/nfp/test2_no-pc_ctx4.d: New file.
* testsuite/binutils-all/nfp/test1.d: New file.
* testsuite/binutils-all/nfp/nfp6000.nffw: New file.
* testsuite/binutils-all/nfp/test2_nfp6000.nffw: New file.
* NEWS: Mention the new support.
include * dis-asm.h: Added print_nfp_disassembler_options prototype.
* elf/common.h: Added EM_NFP, officially assigned. See Google Group
Generic System V Application Binary Interface.
* elf/nfp.h: New, for NFP support.
* opcode/nfp.h: New, for NFP support.
opcodes Makefile.am: Added nfp-dis.c.
configure.ac: Added bfd_nfp_arch.
disassemble.h: Added print_insn_nfp prototype.
disassemble.c: Added ARCH_nfp and call to print_insn_nfp
nfp-dis.c: New, for NFP support.
po/POTFILES.in: Added nfp-dis.c to the list.
Makefile.in: Regenerate.
configure: Regenerate.
2018-04-30 17:02:59 +01:00
aa17843739
Revert "Enable Intel MOVDIRI, MOVDIR64B instructions."
...
This reverts commit a914a7c958
2018-04-27 14:34:13 +02:00
a914a7c958
Enable Intel MOVDIRI, MOVDIR64B instructions.
...
gas/
* config/tc-i386.c (cpu_arch): Add .movdir, .movdir64b.
(cpu_noarch): Likewise.
(process_suffix): Add check for register size.
* doc/c-i386.texi: Document movdiri, movdir64b.
* testsuite/gas/i386/i386.exp: Run MOVDIR{I,64B} tests.
* testsuite/gas/i386/movdir-intel.d: New test.
* testsuite/gas/i386/movdir.d: Likewise.
* testsuite/gas/i386/movdir.s: Likewise.
* testsuite/gas/i386/movdir64b-reg.s: Likewise.
* testsuite/gas/i386/movdir64b-reg.l: Likewise.
* testsuite/gas/i386/x86-64-movdir-intel.d: Likewise.
* testsuite/gas/i386/x86-64-movdir.d: Likewise.
* testsuite/gas/i386/x86-64-movdir.s: Likewise.
* testsuite/gas/i386/x86-64-movdir64b-reg.s: Likewise.
* testsuite/gas/i386/x86-64-movdir64b-reg.l: Likewise.
opcodes/
* i386-dis.c (enum): Add PREFIX_0F38F8, PREFIX_0F38F9.
(prefix_table): New instructions (see prefix above).
Add Gva macro and handling in OP_G.
* i386-gen.c (cpu_flag_init): Add CPU_MOVDIRI_FLAGS,
CPU_MOVDIR64B_FLAGS.
(cpu_flags): Likewise.
(opcode_modifiers): Add AddrPrefixOpReg.
(i386_opcode_modifier): Likewise.
* i386-opc.h (enum): Add CpuMOVDIRI, CpuMOVDIR64B.
(i386_cpu_flags): Likewise.
* i386-opc.tbl: Add movidir{i,64b}.
* i386-init.h: Regenerate.
* i386-tbl.h: Likewise.
2018-04-26 23:34:04 +02:00
e2195274d4
x86: fold various non-memory operand AVX512VL templates
...
There's little point carrying up to three templates per insn flavor
when the sole difference is operand size and the dependency on AVX512VL
being enabled. Instead the need for AVX512VL can be derived from an
operand allowing for ZMMword as well as one or both or XMMword and
YMMword (irrespective of whether this is a register or memory operand).
Without further abstraction to deal with the different Disp8MemShift
values between the templates, only a limited set (mostly ones only
allowing for non-memory operands) can be folded, which is being done
here.
Also drop IgnoreSize wherever possible from anything that's being
touched anyway.
2018-04-26 08:55:02 +02:00
59ef5df41e
x86: CpuXSAVE is a prereq for various other features
...
All of AVX, LWP, MPX, and PKU require XSAVE, and hence it as well as
XRSTOR should be enabled when enabling these ISA extensions. Leverage
these implications to shorten some of the cpu_flag_init[] entries.
2018-04-26 08:48:56 +02:00
6e041cf4b0
x86: drop CpuRegMMX, CpuReg[XYZ]MM, and CpuRegMask
...
It's not clear to me why they had been introduced - the respective
comments in opcodes/i386-gen.c are certainly wrong: ymm<N> registers
are very well supported (and necessary) with just AVX512F.
2018-04-26 08:48:01 +02:00
0e0eea7820
x86: x87-related adjustments
...
Neither 287 wrt 8087 nor 387 wrt 287 are proper supersets - in each case
some insns get removed from the ISA (they become NOPs, but code intended
for newer co-processors should not use them).
Furthermore with .no87, ST should not be recognized as a register name.
2018-04-26 08:45:35 +02:00
2f1bada2dc
x86: drop VexImmExt
...
It's only used in assertions, and hence not really needed for correct
code generation.
2018-04-26 08:30:06 +02:00
bacd145775
x86: drop redundant AVX512VL shift templates
...
These were wrongly left in place by commit ed438a93f1
2018-04-25 16:26:10 +02:00
10bba94bd4
Fix the mask for the sqrdml(a|s)h instructions.
...
Rn is supposed to have a 5 bit range but instead was given 4 bits
causing these instructions to disassemble as unknown instructions.
opcodes/
* aarch64-tbl.h (sqrdmlah, sqrdmlsh): Fix masks.
gas/
* testsuite/gas/aarch64/rdma.s: Test for larger register numbers.
* testsuite/gas/aarch64/rdma.d: Update results.
* testsuite/gas/aarch64/rdma-directive.d: Likewise.
2018-04-25 13:38:35 +01:00
c48935d75f
Enable Intel CLDEMOTE instruction.
...
gas/
* config/tc-i386.c (cpu_arch): Add .cldemote.
* doc/c-i386.texi: Document cldemote/.cldemote.
* testsuite/gas/i386/cldemote-intel.d: New.
* testsuite/gas/i386/cldemote.d: Likewise.
* testsuite/gas/i386/cldemote.s: Likewise.
* testsuite/gas/i386/i386.exp: Run new tests.
* testsuite/gas/i386/x86-64-cldemote-intel.d: New.
* testsuite/gas/i386/x86-64-cldemote.d: Likewise.
* testsuite/gas/i386/x86-64-cldemote.s: Likewise.
* testsuite/gas/i386/ilp32/x86-64-nops.d: Remove 0x0f1c
NOP encoding that maps to cldemote.
* testsuite/gas/i386/nops.d: Likewise.
* testsuite/gas/i386/nops.s: Likewise.
* testsuite/gas/i386/x86-64-nops.d: Likewise.
* testsuite/gas/i386/x86-64-nops.s: Likewise.
opcode/
* i386-dis.c: Add REG_0F1C_MOD_0, MOD_0F1C_PREFIX_0,
PREFIX_0F1C.
* i386-gen.c (cpu_flag_init): Add CPU_CLDEMOTE_FLAGS,
(cpu_flags): Add CpuCLDEMOTE.
* i386-init.h: Regenerate.
* i386-opc.h (enum): Add CpuCLDEMOTE,
(i386_cpu_flags): Add cpucldemote.
* i386-opc.tbl: Add cldemote.
* i386-tbl.h: Regenerate.
2018-04-17 11:56:34 +02:00
211dc24b87
Remove sh5 and sh64 support
...
include/
* dis-asm.h: Remove sh5 and sh64 support.
bfd/
* Makefile.am: Remove sh5 and sh64 support.
* archures.c: Likewise.
* config.bfd: Likewise.
* configure.ac: Likewise.
* cpu-sh.c: Likewise.
* elf32-sh-relocs.h: Likewise.
* elf32-sh.c: Likewise.
* targets.c: Likewise.
* elf32-sh64-com.c: Delete.
* elf32-sh64.c: Delete.
* elf32-sh64.h: Delete.
* elf64-sh64.c: Delete.
* Makefile.in: Regenerate.
* bfd-in2.h: Regenerate.
* configure: Regenerate.
* po/SRC-POTFILES.in: Regenerate.
opcodes/
* Makefile.am: Remove sh5 and sh64 support.
* configure.ac: Likewise.
* disassemble.c: Likewise.
* disassemble.h: Likewise.
* sh-dis.c: Likewise.
* sh64-dis.c: Delete.
* sh64-opc.c: Delete.
* sh64-opc.h: Delete.
* Makefile.in: Regenerate.
* configure: Regenerate.
* po/POTFILES.in: Regenerate.
bintuils/
* testsuite/binutils-all/objcopy.exp: Remove sh5 and sh64 support.
gas/
* Makefile.am: Remove sh5 and sh64 support.
* config/tc-sh.c: Likewise.
* configure.tgt: Likewise.
* doc/Makefile.am: Likewise.
* doc/as.texinfo: Likewise.
* testsuite/gas/cfi/cfi.exp: Likewise.
* testsuite/gas/sh/basic.exp: Likewise.
* config/tc-sh64.c: Delete.
* config/tc-sh64.h: Delete.
* doc/c-sh64.texi: Delete.
* testsuite/gas/sh/sh64/abi-32.d: Delete.
* testsuite/gas/sh/sh64/abi-32.s: Delete.
* testsuite/gas/sh/sh64/abi-64.d: Delete.
* testsuite/gas/sh/sh64/abi-64.s: Delete.
* testsuite/gas/sh/sh64/basic-1.d: Delete.
* testsuite/gas/sh/sh64/basic-1.s: Delete.
* testsuite/gas/sh/sh64/case-1.d: Delete.
* testsuite/gas/sh/sh64/case-1.s: Delete.
* testsuite/gas/sh/sh64/case-noexp-1.d: Delete.
* testsuite/gas/sh/sh64/crange1-1.d: Delete.
* testsuite/gas/sh/sh64/crange1-2.d: Delete.
* testsuite/gas/sh/sh64/crange1.s: Delete.
* testsuite/gas/sh/sh64/crange2-1.d: Delete.
* testsuite/gas/sh/sh64/crange2-2.d: Delete.
* testsuite/gas/sh/sh64/crange2-noexp-1.d: Delete.
* testsuite/gas/sh/sh64/crange2.s: Delete.
* testsuite/gas/sh/sh64/crange3-1.d: Delete.
* testsuite/gas/sh/sh64/crange3.s: Delete.
* testsuite/gas/sh/sh64/crange4-1.d: Delete.
* testsuite/gas/sh/sh64/crange4.s: Delete.
* testsuite/gas/sh/sh64/crange5-1.d: Delete.
* testsuite/gas/sh/sh64/crange5.s: Delete.
* testsuite/gas/sh/sh64/creg-1.d: Delete.
* testsuite/gas/sh/sh64/creg-1.s: Delete.
* testsuite/gas/sh/sh64/creg-2.d: Delete.
* testsuite/gas/sh/sh64/creg-2.s: Delete.
* testsuite/gas/sh/sh64/datal-1.s: Delete.
* testsuite/gas/sh/sh64/datal-2.d: Delete.
* testsuite/gas/sh/sh64/datal-2.s: Delete.
* testsuite/gas/sh/sh64/datal-3.s: Delete.
* testsuite/gas/sh/sh64/datal32-1.d: Delete.
* testsuite/gas/sh/sh64/datal32-3.d: Delete.
* testsuite/gas/sh/sh64/datal64-1.d: Delete.
* testsuite/gas/sh/sh64/datal64-3.d: Delete.
* testsuite/gas/sh/sh64/eh-1.d: Delete.
* testsuite/gas/sh/sh64/eh-1.s: Delete.
* testsuite/gas/sh/sh64/endian-1.d: Delete.
* testsuite/gas/sh/sh64/endian-1.s: Delete.
* testsuite/gas/sh/sh64/endian-2.d: Delete.
* testsuite/gas/sh/sh64/endian-2.s: Delete.
* testsuite/gas/sh/sh64/err-1.s: Delete.
* testsuite/gas/sh/sh64/err-2.s: Delete.
* testsuite/gas/sh/sh64/err-3.s: Delete.
* testsuite/gas/sh/sh64/err-4.s: Delete.
* testsuite/gas/sh/sh64/err-abi-32.s: Delete.
* testsuite/gas/sh/sh64/err-abi-64.s: Delete.
* testsuite/gas/sh/sh64/err-dsp.s: Delete.
* testsuite/gas/sh/sh64/err-movi-noexp-1.s: Delete.
* testsuite/gas/sh/sh64/err-noexp-cmd1.s: Delete.
* testsuite/gas/sh/sh64/err-pt-1.s: Delete.
* testsuite/gas/sh/sh64/err-pt32-cmd1.s: Delete.
* testsuite/gas/sh/sh64/err-pt32-cmd2.s: Delete.
* testsuite/gas/sh/sh64/err-pt32-cmd3.s: Delete.
* testsuite/gas/sh/sh64/err-ptb-1.s: Delete.
* testsuite/gas/sh/sh64/err-ptb-2.s: Delete.
* testsuite/gas/sh/sh64/err.exp: Delete.
* testsuite/gas/sh/sh64/immexpr1.s: Delete.
* testsuite/gas/sh/sh64/immexpr2.s: Delete.
* testsuite/gas/sh/sh64/immexpr32-1.d: Delete.
* testsuite/gas/sh/sh64/immexpr32-2.d: Delete.
* testsuite/gas/sh/sh64/immexpr64-1.d: Delete.
* testsuite/gas/sh/sh64/immexpr64-2.d: Delete.
* testsuite/gas/sh/sh64/lineno.d: Delete.
* testsuite/gas/sh/sh64/lineno.s: Delete.
* testsuite/gas/sh/sh64/localcom-1.d: Delete.
* testsuite/gas/sh/sh64/localcom-1.s: Delete.
* testsuite/gas/sh/sh64/mix-1.d: Delete.
* testsuite/gas/sh/sh64/mix-1.s: Delete.
* testsuite/gas/sh/sh64/mix-noexp-1.d: Delete.
* testsuite/gas/sh/sh64/movi-1.s: Delete.
* testsuite/gas/sh/sh64/movi-2.s: Delete.
* testsuite/gas/sh/sh64/movi-3.d: Delete.
* testsuite/gas/sh/sh64/movi-3.s: Delete.
* testsuite/gas/sh/sh64/movi32-1.d: Delete.
* testsuite/gas/sh/sh64/movi32-2.d: Delete.
* testsuite/gas/sh/sh64/movi32-noexp-2.d: Delete.
* testsuite/gas/sh/sh64/movi64-1.d: Delete.
* testsuite/gas/sh/sh64/movi64-2.d: Delete.
* testsuite/gas/sh/sh64/movi64-2.s: Delete.
* testsuite/gas/sh/sh64/movi64-3.d: Delete.
* testsuite/gas/sh/sh64/movi64-noexp-2.d: Delete.
* testsuite/gas/sh/sh64/pt-1.d: Delete.
* testsuite/gas/sh/sh64/pt-1.s: Delete.
* testsuite/gas/sh/sh64/pt-2.s: Delete.
* testsuite/gas/sh/sh64/pt-noexp-1.d: Delete.
* testsuite/gas/sh/sh64/pt32-1.d: Delete.
* testsuite/gas/sh/sh64/pt32-noexp-2.d: Delete.
* testsuite/gas/sh/sh64/pt64-1.d: Delete.
* testsuite/gas/sh/sh64/pt64-32-1.d: Delete.
* testsuite/gas/sh/sh64/pt64-32-2.d: Delete.
* testsuite/gas/sh/sh64/pt64-noexp-2.d: Delete.
* testsuite/gas/sh/sh64/ptc-1.s: Delete.
* testsuite/gas/sh/sh64/ptc32-1.d: Delete.
* testsuite/gas/sh/sh64/ptc32-noexp-1.d: Delete.
* testsuite/gas/sh/sh64/ptc64-1.d: Delete.
* testsuite/gas/sh/sh64/ptc64-32-1.d: Delete.
* testsuite/gas/sh/sh64/ptc64-noexp-1.d: Delete.
* testsuite/gas/sh/sh64/ptext-1.s: Delete.
* testsuite/gas/sh/sh64/ptext32-1.d: Delete.
* testsuite/gas/sh/sh64/ptext32-noexp-1.d: Delete.
* testsuite/gas/sh/sh64/ptext64-1.d: Delete.
* testsuite/gas/sh/sh64/ptext64-32-1.d: Delete.
* testsuite/gas/sh/sh64/ptext64-noexp-1.d: Delete.
* testsuite/gas/sh/sh64/rel-1.s: Delete.
* testsuite/gas/sh/sh64/rel-2.s: Delete.
* testsuite/gas/sh/sh64/rel-3.s: Delete.
* testsuite/gas/sh/sh64/rel-4.s: Delete.
* testsuite/gas/sh/sh64/rel-5.s: Delete.
* testsuite/gas/sh/sh64/rel32-1.d: Delete.
* testsuite/gas/sh/sh64/rel32-2.d: Delete.
* testsuite/gas/sh/sh64/rel32-3.d: Delete.
* testsuite/gas/sh/sh64/rel32-4.d: Delete.
* testsuite/gas/sh/sh64/rel32-5.d: Delete.
* testsuite/gas/sh/sh64/rel64-1.d: Delete.
* testsuite/gas/sh/sh64/rel64-2.d: Delete.
* testsuite/gas/sh/sh64/rel64-3.d: Delete.
* testsuite/gas/sh/sh64/rel64-4.d: Delete.
* testsuite/gas/sh/sh64/rel64-5.d: Delete.
* testsuite/gas/sh/sh64/relax-1.d: Delete.
* testsuite/gas/sh/sh64/relax-1.s: Delete.
* testsuite/gas/sh/sh64/relax-2.d: Delete.
* testsuite/gas/sh/sh64/relax-2.s: Delete.
* testsuite/gas/sh/sh64/relax-3.d: Delete.
* testsuite/gas/sh/sh64/relax-3.s: Delete.
* testsuite/gas/sh/sh64/sh64.exp: Delete.
* testsuite/gas/sh/sh64/shift-1.s: Delete.
* testsuite/gas/sh/sh64/shift-2.s: Delete.
* testsuite/gas/sh/sh64/shift-3.s: Delete.
* testsuite/gas/sh/sh64/shift32-1.d: Delete.
* testsuite/gas/sh/sh64/shift32-3.d: Delete.
* testsuite/gas/sh/sh64/shift32-noexp-3.d: Delete.
* testsuite/gas/sh/sh64/shift64-1.d: Delete.
* testsuite/gas/sh/sh64/shift64-2.d: Delete.
* testsuite/gas/sh/sh64/shift64-3.d: Delete.
* testsuite/gas/sh/sh64/shift64-noexp-3.d: Delete.
* testsuite/gas/sh/sh64/syntax-1.d: Delete.
* testsuite/gas/sh/sh64/syntax-1.s: Delete.
* testsuite/gas/sh/sh64/syntax-2.d: Delete.
* testsuite/gas/sh/sh64/syntax-2.s: Delete.
* testsuite/gas/sh/sh64/ua-1.s: Delete.
* testsuite/gas/sh/sh64/ua32-1.d: Delete.
* testsuite/gas/sh/sh64/ua64-1.d: Delete.
* Makefile.in: Regenerate.
* doc/Makefile.in: Regenerate.
* po/POTFILES.in: Regenerate.
ld/
* Makefile.am: Remove sh5 and sh64 support.
* configure.tgt: Likewise.
* ldlang.c: Likewise.
* testsuite/ld-elfcomm/elfcomm.exp: Likewise.
* testsuite/ld-gc/gc.exp: Likewise.
* testsuite/ld-gc/pr13683.d: Likewise.
* testsuite/ld-scripts/crossref.exp: Likewise.
* testsuite/ld-selective/selective.exp: Likewise.
* testsuite/ld-sh/ld-r-1.d: Likewise.
* testsuite/ld-sh/rd-sh.exp: Likewise.
* testsuite/ld-sh/sh.exp: Likewise.
* testsuite/ld-srec/srec.exp: Likewise.
* testsuite/ld-undefined/undefined.exp: Likewise.
* emulparams/shelf32.sh: Delete.
* emulparams/shelf32_linux.sh: Delete.
* emulparams/shelf32_nbsd.sh: Delete.
* emulparams/shelf64.sh: Delete.
* emulparams/shelf64_nbsd.sh: Delete.
* emulparams/shlelf32.sh: Delete.
* emulparams/shlelf32_linux.sh: Delete.
* emulparams/shlelf32_nbsd.sh: Delete.
* emulparams/shlelf64.sh: Delete.
* emulparams/shlelf64_nbsd.sh: Delete.
* emultempl/sh64elf.em: Delete.
* testsuite/ld-sh/sh64/abi32.sd: Delete.
* testsuite/ld-sh/sh64/abi32.xd: Delete.
* testsuite/ld-sh/sh64/abi64.sd: Delete.
* testsuite/ld-sh/sh64/abi64.xd: Delete.
* testsuite/ld-sh/sh64/abixx-noexp.sd: Delete.
* testsuite/ld-sh/sh64/cmpct1.sd: Delete.
* testsuite/ld-sh/sh64/cmpct1.xd: Delete.
* testsuite/ld-sh/sh64/crange-1.s: Delete.
* testsuite/ld-sh/sh64/crange-2a.s: Delete.
* testsuite/ld-sh/sh64/crange-2b.s: Delete.
* testsuite/ld-sh/sh64/crange-2c.s: Delete.
* testsuite/ld-sh/sh64/crange-2d.s: Delete.
* testsuite/ld-sh/sh64/crange-2e.s: Delete.
* testsuite/ld-sh/sh64/crange-2f.s: Delete.
* testsuite/ld-sh/sh64/crange-2g.s: Delete.
* testsuite/ld-sh/sh64/crange-2h.s: Delete.
* testsuite/ld-sh/sh64/crange-2i.s: Delete.
* testsuite/ld-sh/sh64/crange1.rd: Delete.
* testsuite/ld-sh/sh64/crange2.rd: Delete.
* testsuite/ld-sh/sh64/crange3-cmpct.rd: Delete.
* testsuite/ld-sh/sh64/crange3-media.rd: Delete.
* testsuite/ld-sh/sh64/crange3.dd: Delete.
* testsuite/ld-sh/sh64/crange3.rd: Delete.
* testsuite/ld-sh/sh64/crangerel1.rd: Delete.
* testsuite/ld-sh/sh64/crangerel2.rd: Delete.
* testsuite/ld-sh/sh64/dlsection-1.s: Delete.
* testsuite/ld-sh/sh64/dlsection.sd: Delete.
* testsuite/ld-sh/sh64/endian.dbd: Delete.
* testsuite/ld-sh/sh64/endian.dld: Delete.
* testsuite/ld-sh/sh64/endian.ld: Delete.
* testsuite/ld-sh/sh64/endian.s: Delete.
* testsuite/ld-sh/sh64/endian.sbd: Delete.
* testsuite/ld-sh/sh64/endian.sld: Delete.
* testsuite/ld-sh/sh64/gotplt.d: Delete.
* testsuite/ld-sh/sh64/gotplt.map: Delete.
* testsuite/ld-sh/sh64/gotplt.s: Delete.
* testsuite/ld-sh/sh64/init-cmpct.d: Delete.
* testsuite/ld-sh/sh64/init-media.d: Delete.
* testsuite/ld-sh/sh64/init.s: Delete.
* testsuite/ld-sh/sh64/init64.d: Delete.
* testsuite/ld-sh/sh64/mix1-noexp.sd: Delete.
* testsuite/ld-sh/sh64/mix1.sd: Delete.
* testsuite/ld-sh/sh64/mix1.xd: Delete.
* testsuite/ld-sh/sh64/mix2-noexp.sd: Delete.
* testsuite/ld-sh/sh64/mix2.sd: Delete.
* testsuite/ld-sh/sh64/mix2.xd: Delete.
* testsuite/ld-sh/sh64/rd-sh64.exp: Delete.
* testsuite/ld-sh/sh64/rel-1.s: Delete.
* testsuite/ld-sh/sh64/rel-2.s: Delete.
* testsuite/ld-sh/sh64/rel32.xd: Delete.
* testsuite/ld-sh/sh64/rel64.xd: Delete.
* testsuite/ld-sh/sh64/relax.exp: Delete.
* testsuite/ld-sh/sh64/relax1.s: Delete.
* testsuite/ld-sh/sh64/relax2.s: Delete.
* testsuite/ld-sh/sh64/relax3.s: Delete.
* testsuite/ld-sh/sh64/relax4.s: Delete.
* testsuite/ld-sh/sh64/reldl-1.s: Delete.
* testsuite/ld-sh/sh64/reldl-2.s: Delete.
* testsuite/ld-sh/sh64/reldl32.rd: Delete.
* testsuite/ld-sh/sh64/reldl64.rd: Delete.
* testsuite/ld-sh/sh64/relfail.exp: Delete.
* testsuite/ld-sh/sh64/relfail.s: Delete.
* testsuite/ld-sh/sh64/sh64-1.s: Delete.
* testsuite/ld-sh/sh64/sh64-2.s: Delete.
* testsuite/ld-sh/sh64/sh64.exp: Delete.
* testsuite/ld-sh/sh64/shcmp-1.s: Delete.
* testsuite/ld-sh/sh64/shdl-1.s: Delete.
* testsuite/ld-sh/sh64/shdl-2.s: Delete.
* testsuite/ld-sh/sh64/shdl32.xd: Delete.
* testsuite/ld-sh/sh64/shdl64.sd: Delete.
* testsuite/ld-sh/sh64/shdl64.xd: Delete.
* testsuite/ld-sh/sh64/shmix-1.s: Delete.
* testsuite/ld-sh/sh64/shmix-2.s: Delete.
* testsuite/ld-sh/sh64/shmix-3.s: Delete.
* testsuite/ld-sh/sh64/stobin-0-dso.d: Delete.
* testsuite/ld-sh/sh64/stobin-1.d: Delete.
* testsuite/ld-sh/sh64/stobin.s: Delete.
* testsuite/ld-sh/sh64/stolib.s: Delete.
* Makefile.in: Regenerate.
* po/BLD-POTFILES.in: Regenerate.
2018-04-16 15:29:39 +09:30
a9a4b30244
Remove w65 support
...
include/
* coff/internal.h: Remove w65 support.
* coff/w65.h: Delete.
bfd/
* Makefile.am: Remove w65 support.
* archures.c: Likewise.
* coffcode.h: Likewise.
* config.bfd: Likewise.
* configure.ac: Likewise.
* targets.c: Likewise.
* coff-w65.c: Delete.
* cpu-w65.c: Delete.
* Makefile.in: Regenerate.
* bfd-in2.h: Regenerate.
* configure: Regenerate.
* po/SRC-POTFILES.in: Regenerate.
opcodes/
* Makefile.am: Remove w65 support.
* configure.ac: Likewise.
* disassemble.c: Likewise.
* disassemble.h: Likewise.
* w65-dis.c: Delete.
* w65-opc.h: Delete.
* Makefile.in: Regenerate.
* configure: Regenerate.
* po/POTFILES.in: Regenerate.
binutils/
* testsuite/binutils-all/objcopy.exp: Remove w65 support.
ld/
* Makefile.am: Remove w65 support.
* configure.tgt: Likewise.
* emulparams/w65.sh: Delete.
* scripttempl/w65.sc: Delete.
* Makefile.in: Regenerate.
* po/BLD-POTFILES.in: Regenerate.
2018-04-16 15:26:05 +09:30
04cb01fd5a
Remove we32k support
...
include/
* coff/we32k.h: Delete.
bfd/
* Makefile.am: Remove we32k support.
* archures.c: Likewise.
* coffcode.h: Likewise.
* config.bfd: Likewise.
* configure.ac: Likewise.
* targets.c: Likewise.
* coff-we32k.c: Delete.
* cpu-we32k.c: Delete.
* Makefile.in: Regenerate.
* bfd-in2.h: Regenerate.
* configure: Regenerate.
* po/SRC-POTFILES.in: Regenerate.
opcodes/
* configure.ac: Remove we32k support.
* configure: Regenerate.
bintuils/
* testsuite/binutils-all/objdump.exp: Remove we32k support.
2018-04-16 15:24:43 +09:30
c2bf1eecf9
Remove m88k support
...
include/
* coff/internal.h: Remove m88k support.
* coff/m88k.h: Delete.
* opcode/m88k.h: Delete.
bfd/
* Makefile.am: Remove m88k support.
* aoutx.h: Likewise.
* archures.c: Likewise.
* coffcode.h: Likewise.
* coffswap.h: Likewise.
* config.bfd: Likewise.
* configure.ac: Likewise.
* cpu-ns32k.c: Likewise.
* elf32-nds32.c: Likewise.
* mach-o.c: Likewise.
* netbsd-core.c: Likewise.
* reloc.c: Likewise.
* targets.c: Likewise.
* coff-m88k.c: Delete.
* cpu-m88k.c: Delete.
* elf32-m88k.c: Delete.
* hosts/m88kmach3.h: Delete.
* m88kmach3.c: Delete.
* m88kopenbsd.c: Delete.
* Makefile.in: Regenerate.
* bfd-in2.h: Regenerate.
* configure: Regenerate.
* po/SRC-POTFILES.in: Regenerate.
opcodes/
* Makefile.am: Remove m88k support.
* configure.ac: Likewise.
* disassemble.c: Likewise.
* disassemble.h: Likewise.
* m88k-dis.c: Delete.
* Makefile.in: Regenerate.
* configure: Regenerate.
* po/POTFILES.in: Regenerate.
binutils/
* MAINTAINERS (Mark Kettenis): Move to past maintainers.
* testsuite/binutils-all/objdump.exp: Remove m88k support.
gas/
* configure.ac: Remove m88k support.
* config.in: Regenerate.
* configure: Regenerate.
ld/
* Makefile.am: Remove m88k support.
* configure.host: Likewise.
* configure.tgt: Likewise.
* testsuite/ld-elf/sec-to-seg.exp: Likewise.
* emulparams/m88kbcs.sh: Delete.
* scripttempl/m88kbcs.sc: Delete.
* Makefile.in: Regenerate.
* po/BLD-POTFILES.in: Regenerate.
2018-04-16 15:23:38 +09:30
6793974daa
Remove i370 support
...
include/
* elf/i370.h: Delete.
* opcode/i370.h: Delete.
bfd/
* Makefile.am: Remove i370 support.
* archures.c: Likewise.
* config.bfd: Likewise.
* configure.ac: Likewise.
* targets.c: Likewise.
* cpu-i370.c: Delete.
* elf32-i370.c: Delete.
* Makefile.in: Regenerate.
* bfd-in2.h: Regenerate.
* configure: Regenerate.
* po/SRC-POTFILES.in: Regenerate.
opcodes/
* Makefile.am: Remove i370 support.
* configure.ac: Likewise.
* disassemble.c: Likewise.
* disassemble.h: Likewise.
* i370-dis.c: Delete.
* i370-opc.c: Delete.
* Makefile.in: Regenerate.
* configure: Regenerate.
* po/POTFILES.in: Regenerate.
binutils/
* readelf.c: Remove i370 support.
* testsuite/binutils-all/objdump.exp: Likewise.
gas/
* Makefile.am: Remove i370 support.
* app.c: Likewise.
* config/obj-elf.c: Likewise.
* configure.tgt: Likewise.
* doc/Makefile.am: Likewise.
* doc/as.texinfo: Likewise.
* testsuite/gas/all/gas.exp: Likewise.
* testsuite/gas/elf/warn-2.s: Likewise.
* testsuite/gas/lns/lns.exp: Likewise.
* config/tc-i370.c: Delete.
* config/tc-i370.h: Delete.
* doc/c-i370.texi: Delete.
* Makefile.in: Regenerate.
* doc/Makefile.in: Regenerate.
* po/POTFILES.in: Regenerate.
ld/
* Makefile.am: Remove i370 support.
* configure.tgt: Likewise.
* testsuite/ld-elf/compressed1d.d: Likewise.
* testsuite/ld-elf/group8a.d: Likewise.
* testsuite/ld-elf/group8b.d: Likewise.
* testsuite/ld-elf/group9a.d: Likewise.
* testsuite/ld-elf/group9b.d: Likewise.
* testsuite/ld-elf/merge.d: Likewise.
* testsuite/ld-elf/pr12851.d: Likewise.
* testsuite/ld-elf/pr12975.d: Likewise.
* testsuite/ld-elf/pr13177.d: Likewise.
* testsuite/ld-elf/pr13195.d: Likewise.
* testsuite/ld-elf/pr17615.d: Likewise.
* testsuite/ld-elf/pr21562a.d: Likewise.
* testsuite/ld-elf/pr21562b.d: Likewise.
* testsuite/ld-elf/pr21562c.d: Likewise.
* testsuite/ld-elf/pr21562d.d: Likewise.
* testsuite/ld-elf/pr21562i.d: Likewise.
* testsuite/ld-elf/pr21562j.d: Likewise.
* testsuite/ld-elf/pr21562k.d: Likewise.
* testsuite/ld-elf/pr21562l.d: Likewise.
* testsuite/ld-elf/pr21562m.d: Likewise.
* testsuite/ld-elf/pr21562n.d: Likewise.
* testsuite/ld-elf/pr22677.d: Likewise.
* testsuite/lib/ld-lib.exp: Likewise.
* emulparams/elf32i370.sh: Delete.
* scripttempl/elfi370.sc: Delete.
* Makefile.in: Regenerate.
* po/BLD-POTFILES.in: Regenerate.
2018-04-16 15:21:56 +09:30
e82aa7944d
Remove h8500 support
...
include/
* coff/h8500.h: Delete.
* coff/internal.h: Remove h8500 support.
bfd/
* Makefile.am: Remove h8500 support.
* archures.c: Likewise.
* coffcode.h: Likewise.
* config.bfd: Likewise.
* configure.ac: Likewise.
* targets.c: Likewise.
* coff-h8500.c: Delete.
* cpu-h8500.c: Delete.
* Makefile.in: Regenerate.
* bfd-in2.h: Regenerate.
* configure: Regenerate.
* po/SRC-POTFILES.in: Regenerate.
opcodes/
* Makefile.am: Remove h8500 support.
* configure.ac: Likewise.
* disassemble.c: Likewise.
* disassemble.h: Likewise.
* h8500-dis.c: Delete.
* h8500-opc.h: Delete.
* Makefile.in: Regenerate.
* configure: Regenerate.
* po/POTFILES.in: Regenerate.
binutils/
* testsuite/binutils-all/objcopy.exp: Remove h8500 support.
* testsuite/lib/binutils-common.exp: Likewise.
gas/
* config/obj-coff.h: Remove h8500 support.
ld/
* Makefile.am: Remove h8500 support.
* configure.tgt: Likewise.
* emulparams/h8500.sh: Delete.
* emulparams/h8500b.sh: Delete.
* emulparams/h8500c.sh: Delete.
* emulparams/h8500m.sh: Delete.
* emulparams/h8500s.sh: Delete.
* scripttempl/h8500.sc: Delete.
* scripttempl/h8500b.sc: Delete.
* scripttempl/h8500c.sc: Delete.
* scripttempl/h8500m.sc: Delete.
* scripttempl/h8500s.sc: Delete.
* Makefile.in: Regenerate.
* po/BLD-POTFILES.in: Regenerate.
2018-04-16 15:19:52 +09:30
fceadf0951
Remove tahoe support
...
include/
* opcode/tahoe.h: Delete.
bfd/
* archures.c: Remove tahoe support.
* config.bfd: Likewise.
* configure.ac: Likewise.
* hosts/tahoe.h: Delete.
* bfd-in2.h: Regenerate.
* configure: Regenerate.
opcodes/
* configure.ac: Remove tahoe support.
* configure: Regenerate.
binutils/
* testsuite/binutils-all/objdump.exp: Remove tahoe support.
gprof/
* Makefile.am: Remove tahoe support.
* corefile.c: Likewise.
* tahoe.c: Delete.
* Makefile.in: Regenerate.
* po/POTFILES.in: Regenerate.
2018-04-16 15:08:40 +09:30
ae1d384372
x86: Allow 32-bit registers for tpause and umwait
...
Since only the first 32 bits of input operand are used for tpause and
umwait, the REX.W bit is skipped. Both 32-bit registers and 64-bit
registers are allowed.
gas/
* testsuite/gas/i386/x86-64-waitpkg.s: Add 32-bit registers
tests for tpause and umwait.
* testsuite/gas/i386/x86-64-waitpkg-intel.d: Updated.
* testsuite/gas/i386/x86-64-waitpkg.d: Likewise.
opcodes/
* i386-dis.c (prefix_table): Replace Em with Edq on tpause and
umwait.
* i386-opc.tbl: Allow 32-bit registers for tpause and umwait in
64-bit mode.
* i386-tbl.h: Regenerated.
2018-04-15 08:38:36 -07:00
de89d0a34d
Enable Intel WAITPKG instructions.
...
Intel has disclosed a set of new instructions for Tremont processor.
The spec is
https://software.intel.com/en-us/intel-architecture-instruction-set-extensions-programming-reference
This patch enables Intel WAITPKG instructions.
gas/
* config/tc-i386.c (cpu_arch): Add WAITPKG.
(cpu_noarch): Likewise.
* doc/c-i386.texi: Document WAITPKG.
* i386/i386.exp: Run WAITPKG tests.
* testsuite/gas/i386/waitpkg-intel.d: New test.
* testsuite/gas/i386/waitpkg.d: Likewise.
* testsuite/gas/i386/waitpkg.s: Likewise.
* testsuite/gas/i386/x86-64-waitpkg-intel.d: Likewise.
* testsuite/gas/i386/x86-64-waitpkg.d: Likewise.
* testsuite/gas/i386/x86-64-waitpkg.s: Likewise.
opcodes/
* i386-dis.c (enum): Add PREFIX_MOD_0_0FAE_REG_6,
PREFIX_MOD_1_0FAE_REG_6.
(va_mode): New.
(OP_E_register): Use va_mode.
* i386-dis-evex.h (prefix_table):
New instructions (see prefixes above).
* i386-gen.c (cpu_flag_init): Add WAITPKG.
(cpu_flags): Likewise.
* i386-opc.h (enum): Likewise.
(i386_cpu_flags): Likewise.
* i386-opc.tbl: Add umonitor, umwait, tpause.
* i386-init.h: Regenerate.
* i386-tbl.h: Likewise.
2018-04-11 21:37:12 +02:00
a8eb42a8b7
Remove i860, i960, bout and aout-adobe targets
...
Plus remove a few leftovers from the 29k support.
include/
* aout/adobe.h: Delete.
* aout/reloc.h: Delete.
* coff/i860.h: Delete.
* coff/i960.h: Delete.
* elf/i860.h: Delete.
* elf/i960.h: Delete.
* opcode/i860.h: Delete.
* opcode/i960.h: Delete.
* aout/aout64.h (enum reloc_type): Trim off 29k and other unused values.
* aout/ar.h (ARMAGB): Remove.
* coff/internal.h (struct internal_aouthdr, struct internal_scnhdr,
union internal_auxent): Remove i960 support.
bfd/
* aout-adobe.c: Delete.
* bout.c: Delete.
* coff-i860.c: Delete.
* coff-i960.c: Delete.
* cpu-i860.c: Delete.
* cpu-i960.c: Delete.
* elf32-i860.c: Delete.
* elf32-i960.c: Delete.
* hosts/i860mach3.h: Delete.
* Makefile.am: Remove i860, i960, bout, and adobe support.
* archures.c: Remove i860 and i960 support.
* coffcode.h: Likewise.
* reloc.c: Likewise.
* aoutx.h: Comment updates.
* archive.c: Remove BOUT and i960 support.
* bfd.c: Remove BOUT support.
* coffswap.h: Remove i960 support.
* config.bfd: Remove i860, i960 and adobe targets.
* configure.ac: Remove adode, bout, i860, i960, icoff targets.
* targets.c: Likewise.
* ieee.c: Remove i960 support.
* mach-o.c: Remove i860 support.
* Makefile.in: Regenerate.
* bfd-in2.h: Regenerate.
* configure: Regenerate.
* libbfd.h: Regenerate.
* po/SRC-POTFILES.in: Regenerate.
opcodes/
* opcodes/i860-dis.c: Delete.
* opcodes/i960-dis.c: Delete.
* Makefile.am: Remove i860 and i960 support.
* configure.ac: Likewise.
* disassemble.c: Likewise.
* disassemble.h: Likewise.
* Makefile.in: Regenerate.
* configure: Regenerate.
* po/POTFILES.in: Regenerate.
binutils/
* ieee.c: Remove i960 support.
* od-macho.c: Remove i860 support.
* readelf.c: Remove i860 and i960 support.
* testsuite/binutils-all/objcopy.exp: Likewise.
* testsuite/binutils-all/objdump.exp: Likewise.
* testsuite/lib/binutils-common.exp: Likewise.
gas/
* config/aout_gnu.h: Delete.
* config/tc-i860.c: Delete.
* config/tc-i860.h: Delete.
* config/tc-i960.c: Delete.
* config/tc-i960.h: Delete.
* doc/c-i860.texi: Delete.
* doc/c-i960.texi: Delete.
* testsuite/gas/i860/README.i860: Delete.
* testsuite/gas/i860/bitwise.d: Delete.
* testsuite/gas/i860/bitwise.s: Delete.
* testsuite/gas/i860/branch.d: Delete.
* testsuite/gas/i860/branch.s: Delete.
* testsuite/gas/i860/bte.d: Delete.
* testsuite/gas/i860/bte.s: Delete.
* testsuite/gas/i860/dir-align01.d: Delete.
* testsuite/gas/i860/dir-align01.s: Delete.
* testsuite/gas/i860/dir-intel01.d: Delete.
* testsuite/gas/i860/dir-intel01.s: Delete.
* testsuite/gas/i860/dir-intel02.d: Delete.
* testsuite/gas/i860/dir-intel02.s: Delete.
* testsuite/gas/i860/dir-intel03-err.l: Delete.
* testsuite/gas/i860/dir-intel03-err.s: Delete.
* testsuite/gas/i860/dual01.d: Delete.
* testsuite/gas/i860/dual01.s: Delete.
* testsuite/gas/i860/dual02-err.l: Delete.
* testsuite/gas/i860/dual02-err.s: Delete.
* testsuite/gas/i860/dual03.d: Delete.
* testsuite/gas/i860/dual03.s: Delete.
* testsuite/gas/i860/fldst01.d: Delete.
* testsuite/gas/i860/fldst01.s: Delete.
* testsuite/gas/i860/fldst02.d: Delete.
* testsuite/gas/i860/fldst02.s: Delete.
* testsuite/gas/i860/fldst03.d: Delete.
* testsuite/gas/i860/fldst03.s: Delete.
* testsuite/gas/i860/fldst04.d: Delete.
* testsuite/gas/i860/fldst04.s: Delete.
* testsuite/gas/i860/fldst05.d: Delete.
* testsuite/gas/i860/fldst05.s: Delete.
* testsuite/gas/i860/fldst06.d: Delete.
* testsuite/gas/i860/fldst06.s: Delete.
* testsuite/gas/i860/fldst07.d: Delete.
* testsuite/gas/i860/fldst07.s: Delete.
* testsuite/gas/i860/fldst08.d: Delete.
* testsuite/gas/i860/fldst08.s: Delete.
* testsuite/gas/i860/float01.d: Delete.
* testsuite/gas/i860/float01.s: Delete.
* testsuite/gas/i860/float02.d: Delete.
* testsuite/gas/i860/float02.s: Delete.
* testsuite/gas/i860/float03.d: Delete.
* testsuite/gas/i860/float03.s: Delete.
* testsuite/gas/i860/float04.d: Delete.
* testsuite/gas/i860/float04.s: Delete.
* testsuite/gas/i860/form.d: Delete.
* testsuite/gas/i860/form.s: Delete.
* testsuite/gas/i860/i860.exp: Delete.
* testsuite/gas/i860/iarith.d: Delete.
* testsuite/gas/i860/iarith.s: Delete.
* testsuite/gas/i860/ldst01.d: Delete.
* testsuite/gas/i860/ldst01.s: Delete.
* testsuite/gas/i860/ldst02.d: Delete.
* testsuite/gas/i860/ldst02.s: Delete.
* testsuite/gas/i860/ldst03.d: Delete.
* testsuite/gas/i860/ldst03.s: Delete.
* testsuite/gas/i860/ldst04.d: Delete.
* testsuite/gas/i860/ldst04.s: Delete.
* testsuite/gas/i860/ldst05.d: Delete.
* testsuite/gas/i860/ldst05.s: Delete.
* testsuite/gas/i860/ldst06.d: Delete.
* testsuite/gas/i860/ldst06.s: Delete.
* testsuite/gas/i860/pfam.d: Delete.
* testsuite/gas/i860/pfam.s: Delete.
* testsuite/gas/i860/pfmam.d: Delete.
* testsuite/gas/i860/pfmam.s: Delete.
* testsuite/gas/i860/pfmsm.d: Delete.
* testsuite/gas/i860/pfmsm.s: Delete.
* testsuite/gas/i860/pfsm.d: Delete.
* testsuite/gas/i860/pfsm.s: Delete.
* testsuite/gas/i860/pseudo-ops01.d: Delete.
* testsuite/gas/i860/pseudo-ops01.s: Delete.
* testsuite/gas/i860/regress01.d: Delete.
* testsuite/gas/i860/regress01.s: Delete.
* testsuite/gas/i860/shift.d: Delete.
* testsuite/gas/i860/shift.s: Delete.
* testsuite/gas/i860/simd.d: Delete.
* testsuite/gas/i860/simd.s: Delete.
* testsuite/gas/i860/system.d: Delete.
* testsuite/gas/i860/system.s: Delete.
* testsuite/gas/i860/xp.d: Delete.
* testsuite/gas/i860/xp.s: Delete.
* Makefile.am: Remove i860 and i960 support.
* configure.tgt: Likewise.
* doc/Makefile.am: Likewise.
* doc/all.texi: Likewise.
* testsuite/gas/all/gas.exp
* config/obj-coff.h: Remove i960 support.
* doc/internals.texi: Likewise.
* expr.c: Likewise.
* read.c: Likewise.
* write.c: Likewise.
* write.h: Likewise.
* testsuite/gas/lns/lns.exp: Likewise.
* testsuite/gas/symver/symver.exp: Likewise.
* config/tc-m68k.c: Remove BOUT support.
* config/tc-score.c: Likewise.
* config/tc-score7.c: Likewise.
* config/tc-sparc.c: Likewise.
* symbols.c: Likewise.
* doc/h8.texi: Likewise.
* configure.ac: Remove BOUT and i860 support.
* doc/as.texinfo: Remove BOUT, i860 and i960 support
* Makefile.in: Regenerate.
* config.in: Regenerate.
* configure: Regenerate.
* doc/Makefile.in: Regenerate.
* po/POTFILES.in: Regenerate.
ld/
* emulparams/coff_i860.sh: Delete.
* emulparams/elf32_i860.sh: Delete.
* emulparams/elf32_i960.sh: Delete.
* emulparams/gld960.sh: Delete.
* emulparams/gld960coff.sh: Delete.
* emulparams/lnk960.sh: Delete.
* emultempl/gld960.em: Delete.
* emultempl/gld960c.em: Delete.
* emultempl/lnk960.em: Delete.
* scripttempl/i860coff.sc: Delete.
* scripttempl/i960.sc: Delete.
* ld.texinfo: Remove i960 support.
* Makefile.am: Remove i860 and i960 support.
* configure.tgt: Likewise.
* testsuite/ld-discard/extern.d: Likewise.
* testsuite/ld-discard/start.d: Likewise.
* testsuite/ld-discard/static.d: Likewise.
* testsuite/ld-elf/compressed1d.d: Likewise.
* testsuite/ld-elf/group1.d: Likewise.
* testsuite/ld-elf/group3b.d: Likewise.
* testsuite/ld-elf/group8a.d: Likewise.
* testsuite/ld-elf/group8b.d: Likewise.
* testsuite/ld-elf/group9a.d: Likewise.
* testsuite/ld-elf/group9b.d: Likewise.
* testsuite/ld-elf/linkonce2.d: Likewise.
* testsuite/ld-elf/merge.d: Likewise.
* testsuite/ld-elf/merge2.d: Likewise.
* testsuite/ld-elf/merge3.d: Likewise.
* testsuite/ld-elf/orphan-10.d: Likewise.
* testsuite/ld-elf/orphan-11.d: Likewise.
* testsuite/ld-elf/orphan-12.d: Likewise.
* testsuite/ld-elf/orphan-9.d: Likewise.
* testsuite/ld-elf/orphan-region.d: Likewise.
* testsuite/ld-elf/orphan.d: Likewise.
* testsuite/ld-elf/orphan3.d: Likewise.
* testsuite/ld-elf/pr12851.d: Likewise.
* testsuite/ld-elf/pr12975.d: Likewise.
* testsuite/ld-elf/pr13177.d: Likewise.
* testsuite/ld-elf/pr13195.d: Likewise.
* testsuite/ld-elf/pr17550a.d: Likewise.
* testsuite/ld-elf/pr17550b.d: Likewise.
* testsuite/ld-elf/pr17550c.d: Likewise.
* testsuite/ld-elf/pr17550d.d: Likewise.
* testsuite/ld-elf/pr17615.d: Likewise.
* testsuite/ld-elf/pr20528a.d: Likewise.
* testsuite/ld-elf/pr20528b.d: Likewise.
* testsuite/ld-elf/pr21562a.d: Likewise.
* testsuite/ld-elf/pr21562b.d: Likewise.
* testsuite/ld-elf/pr21562c.d: Likewise.
* testsuite/ld-elf/pr21562d.d: Likewise.
* testsuite/ld-elf/pr21562i.d: Likewise.
* testsuite/ld-elf/pr21562j.d: Likewise.
* testsuite/ld-elf/pr21562k.d: Likewise.
* testsuite/ld-elf/pr21562l.d: Likewise.
* testsuite/ld-elf/pr21562m.d: Likewise.
* testsuite/ld-elf/pr21562n.d: Likewise.
* testsuite/ld-elf/pr22677.d: Likewise.
* testsuite/ld-elf/pr22836-1a.d: Likewise.
* testsuite/ld-elf/pr22836-1b.d: Likewise.
* testsuite/ld-elf/pr349.d: Likewise.
* testsuite/ld-elf/sec-to-seg.exp: Likewise.
* testsuite/ld-elf/sec64k.exp: Likewise.
* testsuite/ld-elf/warn1.d: Likewise.
* testsuite/ld-elf/warn2.d: Likewise.
* testsuite/ld-elf/warn3.d: Likewise.
* testsuite/lib/ld-lib.exp: Likewise.
* Makefile.in: Regenerate.
* po/BLD-POTFILES.in: Regenerate.
2018-04-11 21:49:30 +09:30
caf0678c84
i386: Clear vex instead of vex.evex
...
"vex" has many fields to control how to decode an instruction. Clear
all fields in "vex" before decoding an instruction to avoid using values
left from the previous instruction.
gas/
PR binutils/23025
* testsuite/gas/i386/prefix.s: Add tests for vcvtpd2dq with
VEX and EVEX prefixes.
* testsuite/gas/i386/prefix.d: Updated.
opcodes/
PR binutils/23025
* i386-dis.c (get_valid_dis386): Don't set vex.prefix nor vex.w
to 0.
(print_insn): Clear vex instead of vex.evex.
2018-04-04 04:36:44 -07:00
4fb0d2b912
Update Spanish translations for ld/ opcodes/ and gold/ sub-directories
2018-04-04 09:00:18 +01:00
c39e5b2671
x86: drop VecESize
...
It again can be inferred from other information.
The vpopcntd templates all need to have Dword added to their memory
operands; the lack thereof was actually a bug preventing certain Intel
syntax code to assemble, so test cases get extended.
2018-03-28 14:25:07 +02:00
8e6e0792d1
x86: convert broadcast insn attribute to boolean
...
The (only) valid broadcast type for an insn can be inferred from other
information.
2018-03-28 14:24:05 +02:00
9f123b911e
x86: fold to-scalar-int conversion insns
2018-03-28 14:22:56 +02:00
9646c87b5a
x86: don't show suffixes for to-scalar-int conversion insns
...
In the course of folding their patterns (possible now that the pointless
and partly even bogus VecESize are no longer in the way) I've noticed
that vcvt*2usi, other than their vcvt*2si counterparts, don't allow for
any suffixes. As that is supposedly intentional, make the disassembler
consistently omit suffixes for all to-scalar-int conversion insns.
2018-03-28 14:22:00 +02:00
c8d59609b1
Enhance the AARCH64 assembler to support LDFF1xx instructions which use REG+REG addressing with an assumed offset register.
...
PR 22988
opcode * opcode/aarch64.h (enum aarch64_opnd): Add
AARCH64_OPND_SVE_ADDR_R.
opcodes * aarch64-tbl.h (aarch64_opcode_table): Add entries for LDFF1xx
instructions with only a base address register.
* aarch64-opc.c (operand_general_constraint_met_p): Add code to
handle AARHC64_OPND_SVE_ADDR_R.
(aarch64_print_operand): Likewise.
* aarch64-asm-2.c: Regenerate.
* aarch64_dis-2.c: Regenerate.
* aarch64-opc-2.c: Regenerate.
gas * config/tc-aarch64.c (parse_operands): Add code to handle
AARCH64_OPN_SVE_ADDR_R.
* testsuite/gas/aarch64/sve.s: Add tests for LDFF1xx instructions
with an assumed XZR offset address register.
* testsuite/gas/aarch64/sve.d: Update expected disassembly.
2018-03-28 09:44:45 +01:00
b8c169f359
x86: drop pointless VecESize
...
The attribute is meaningful only in templates allowing embedded
broadcast. Drop them everywhere else.
2018-03-22 08:46:25 +01:00
96bc132a73
x86: drop remaining redundant DispN
...
A few of them were missed in commit 7ac2002247
2018-03-22 08:34:24 +01:00
9f79e88693
x86: fix swapped operand handling for BNDMOV
...
The wrong placement of the Load attribute in the templates prevented
this from working. The disassembler also didn't handle this consistently
with other similar dual-encoding insns.
2018-03-22 08:32:50 +01:00
d6793fa1ac
x86/Intel: fix fallout from earlier template folding
...
While many templates allowing multiple suitably matching XMM/YMM/ZMM
operand sizes can be folded, a few need to be split in order to not
wrongly accept "xmmword ptr" operands when only XMM registers are
permitted (and memory operands are more narrow). Add a test case
validating this.
2018-03-22 08:31:43 +01:00
f776822506
x86: fold a few XOP templates
...
Also add a new test case verifying that mixed operands of SIMD insns
with a size-less memory operand in the middle are properly rejected.
2018-03-22 08:29:45 +01:00
0e35537d75
RISC-V: Add .insn support.
...
gas/ChangeLog
2018-03-07 Kito Cheng <kito.cheng@gmail.com>
* config/tc-riscv.c (opcode_name_list): New.
(opcode_names_hash): Likewise.
(init_opcode_names_hash): Likewise.
(opcode_name_lookup): Likewise.
(validate_riscv_insn): New argument length, and add new format
which used in .insn directive.
(md_begin): Refine hash table initialization logic into
init_opcode_hash.
(init_opcode_hash): New.
(my_getOpcodeExpression): Parse opcode name for .insn.
(riscv_ip): New argument hash, able to handle .insn directive.
(s_riscv_insn): Handler for .insn directive.
(riscv_pseudo_table): New entry for .insn.
* doc/c-riscv.texi: Add documentation for .insn directive.
* testsuite/gas/riscv/insn.d: Add testcase for .insn directive.
* testsuite/gas/riscv/insn.s: Likewise.
include/ChangeLog
2018-03-07 Kito Cheng <kito.cheng@gmail.com>
* opcode/riscv.h (OP_MASK_FUNCT3): New.
(OP_SH_FUNCT3): Likewise.
(OP_MASK_FUNCT7): Likewise.
(OP_SH_FUNCT7): Likewise.
(OP_MASK_OP2): Likewise.
(OP_SH_OP2): Likewise.
(OP_MASK_CFUNCT4): Likewise.
(OP_SH_CFUNCT4): Likewise.
(OP_MASK_CFUNCT3): Likewise.
(OP_SH_CFUNCT3): Likewise.
(riscv_insn_types): Likewise.
opcodes/ChangeLog
2018-03-07 Kito Cheng <kito.cheng@gmail.com>
* riscv-opc.c (riscv_insn_types): New.
2018-03-14 16:04:03 -07:00
b4a3689a68
Updated Russian and Brazilian Portuguese translations.
...
ld * po/pt_BR.po: Updated Brazilian Portuguese translation.
opcodes * po/pt_BR.po: Updated Brazilian Portuguese translation.
gas * po/ru.po: Updated Russian translation.
2018-03-13 16:57:29 +00:00
d3d50934a9
x86-64: Also optimize "clr reg64"
...
"clr reg" is an alias of "xor reg, reg". We can encode "clr reg64" as
"xor reg32, reg32".
gas/
* config/tc-i386.c (optimize_encoding): Also encode "clr reg64"
as "xor reg32, reg32".
* testsuite/gas/i386/x86-64-optimize-1.s: Add "clr reg64" tests.
* testsuite/gas/i386/x86-64-optimize-1.d: Updated.
opcodes/
* i386-opc.tbl: Add Optimize to clr.
* i386-tbl.h: Regenerated.
2018-03-08 06:41:34 -08:00
bd5dea8822
x86: Remove support for old (<= 2.8.1) versions of gcc
...
Old (<= 2.8.1) versions of gcc generate broken fsubp, fsubrp, fdivp and
fdivrp instructions. Assembler translates them to correct ones with a
warning:
[hjl@gnu-cfl-1 gas]$ cat x.s
fsubp %st(3),%st
[hjl@gnu-cfl-1 gas]$ gcc -c x.s
x.s: Assembler messages:
x.s:1: Warning: translating to `fsubp %st,%st(3)'
[hjl@gnu-cfl-1 gas]$
This patch removes support for old (<= 2.8.1) versions of gcc:
[hjl@gnu-cfl-1 gas]$ ./as-new -o x.o x.s
x.s: Assembler messages:
x.s:1: Error: operand type mismatch for `fsubp'
[hjl@gnu-cfl-1 gas]$
gas/
* NEWS: Mention -mold-gcc removal.
* config/tc-i386.c (i386_error): Remove old_gcc_only.
(old_gcc): Removed.
(match_template): Remove old gcc support.
(OPTION_MOLD_GCC): Removed.
(OPTION_MRELAX_RELOCATIONS): Updated.
(md_longopts): Remove OPTION_MOLD_GCC.
(md_parse_option): Likewise.
(md_show_usage): Remove -mold-gcc.
* testsuite/gas/i386/general.s: Convert fsub/fdiv tests for old
(<= 2.8.1) versions of gcc.
* testsuite/gas/i386/intel.s: Likewise.
* testsuite/gas/i386/general.l: Updated.
* testsuite/gas/i386/intel-intel.d: Likewise.
* testsuite/gas/i386/intel.d: Likewise.
* testsuite/gas/i386/intel.e: Likewise.
* testsuite/gas/i386/i386.exp: Don't pass -mold-gcc to general.
include/
* opcode/i386 (OLDGCC_COMPAT): Removed.
opcodes/
* i386-gen.c (opcode_modifiers): Remove OldGcc.
* i386-opc.h (OldGcc): Removed.
(i386_opcode_modifier): Remove oldgcc.
* i386-opc.tbl: Remove fsubp, fsubrp, fdivp and fdivrp
instructions for old (<= 2.8.1) versions of gcc.
* i386-tbl.h: Regenerated.
2018-03-08 06:31:52 -08:00
e771e7c9fb
x86: fold several AVX512VL templates
...
The differences between some of the register and memory forms of the
same insn often don't really require the templates to be separate. For
example, Disp8MemShift is simply irrelevant to register forms. Fold
these as far as possible, and also fold register-only forms. Further
folding is possible, but needs other prereq work done first.
A note regarding EVEXDYN: This is intended to be used only when no other
properties of the template would make is_evex_encoding() return true. In
all "normal" cases I think it is preferable to omit this indicator, to
keep the table half way readable.
2018-03-08 08:58:55 +01:00
ed438a93f1
x86: fold certain AVX512 rotate and shift templates
...
Their memory forms were bogusly using VexLWP instead of VexNDD. Adjust
VexNDD handling to cope with these, allowing their register and memory
forms to be folded.
2018-03-08 08:58:05 +01:00
Tamar Christina
Francois H. Theron
H.J. Lu
Alan Modra
Jim Wilson
Peter Bergner
Igor Tsimbalist
Jan Beulich
Nick Clifton