In most cases we don't want expression symbols, such as that created
for an expression like "symbol + (1f - .)", resolved down to a
constant. Instead we'd like to leave the expression as "symbol +
constant" once the "1f - ." part has been resolved, and let the
backend decide whether "symbol" can be reduced further.
However, that doesn't work when trying to resolve .loc view symbols
early. We get expression symbols left as an O_symbol expression
pointing at an absolute symbol, and marked as sy_flags.sy_resolved.
That wouldn't really be a problem, but when one of those expression
symbols is used in further .loc view expressions, its value is taken
as zero.
This patch fixes the symbol value mistake, and stops creation of
O_symbol expression symbols pointing to absolute symbols. Either of
these fixes would cure the .loc view usage.
PR 24444
* symbols.c (resolve_symbol_value): When handling symbols
marked as sy_flags.resolved, return correct value for the
case of expression symbols left as an O_symbol expression.
Merge O_symbol code handling undefined and common symbols with
code handling special cases of expression symbols. Use
seg_left to test for undefined and common symbols. Don't
leave an O_symbol expression when X_add_symbol resolves to
the absolute_section. Init final_val later.
* testsuite/gas/mmix/basep-7.d: Adjust expected output.
gas * config/tc-msp430.c (msp430_make_init_symbols): Define
__crt0_run_{preinit,init,fini}_array symbols if
.{preinit,init,fini}_array sections exist.
* testsuite/gas/msp430/fini-array.d: New test.
* testsuite/gas/msp430/init-array.d: New test.
* testsuite/gas/msp430/preinit-array.d: New test.
* testsuite/gas/msp430/fini-array.s: New test source.
* testsuite/gas/msp430/init-array.s: New test source.
* testsuite/gas/msp430/preinit-array.s: New test source.
* testsuite/gas/msp430/msp430.exp: Add new tests to driver.
gas * config/tc-msp430.c (options): New OPTION_UNKNOWN_INTR_NOPS,
OPTION_NO_UNKNOWN_INTR_NOPS and do_unknown_interrupt_nops.
(md_parse_option): Handle OPTION_UNKNOWN_INTR_NOPS and
OPTION_NO_UNKNOWN_INTR_NOPS by setting do_unknown_interrupt_nops
accordingly.
(md_show_usage): Likewise.
(md_shortopts): Add "mu" for OPTION_UNKNOWN_INTR_NOPS and
"mU" for OPTION_NO_UNKNOWN_INTR_NOPS.
(md_longopts): Likewise.
(warn_eint_nop): Update comment.
(warn_unsure_interrupt): Don't warn if prev_insn_is_nop or
prev_insn_is_dint or we are assembling for 430 ISA.
(msp430_operands): Only call warn_unsure_interrupt if
do_unknown_interrupt_nops == TRUE.
* testsuite/gas/msp430/nop-unknown-intr.s: New test source file.
* testsuite/gas/msp430/nop-unknown-intr-430.d: New test.
* testsuite/gas/msp430/nop-unknown-intr-430x.d: New test.
* testsuite/gas/msp430/nop-unknown-intr-430x-ignore.d: New test.
* testsuite/gas/msp430/nop-unknown-intr-430.l: Warning output for new
test.
* testsuite/gas/msp430/nop-unknown-intr-430x.l: Likewise.
* testsuite/gas/msp430/msp430.exp: Add new tests to driver.
Some of these tests were excluded for ns32k-netbsd, exclude for all
ns32k instead.
binutils/
* testsuite/binutils-all/copy-2.d: Don't run for ns32k-*-*.
* testsuite/binutils-all/copy-3.d: Likewise.
gas/
* testsuite/gas/all/gas.exp: Remove ns32k xfails.
* testsuite/gas/all/weakref1u.d: Don't run for ns32k-*-*.
ld/
* testsuite/ld-scripts/pr20302.d: Don't run for ns32k-*-*.
* testsuite/ld-scripts/section-match-1.d: Likewise.
* testsuite/ld-undefined/require-defined.exp: Likewise.
GNU as' Arm backend assumes each mnemonic has a single entry in the instruction table but VLDR (system register) and VSTR (system register) are different instructions than VLDR and VSTR. It is thus necessary to add some form of demultiplexing in the parser. It starts by creating a new operand type OP_VLDR which indicate that the operand is either the existing OP_RVSD operand or a system register. The function parse_operands () then tries these two cases in order, calling the new parse_sys_vldr_vstr for the second case.
Since the encoding function is specified in the instruction table entry, it also need to have some sort of demultiplexing. This is done in do_vldr_vstr which either calls the existing do_neon_ldr_str () or calls the new do_t_vldr_vstr_sysreg ().
A new internal relocation is needed as well since the offset has a shorter range than in other Thumb coprocessor instructions. Disassembly also requires special care since VSTR (system register) reuse the STC encoding with the coprocessor number 15. Armv8.1-M Mainline ARM manual states that coprocessor 8, 14 and 15 are reserved for floating-point and MVE instructions a feature bit check is added if the coprocessor number is one of this value and we are trying to match a coprocessor instruction (eg. STC) to forbid the match.
ChangeLog entries are as follows:
*** bfd/ChangeLog ***
2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
* reloc.c (BFD_RELOC_ARM_T32_VLDR_VSTR_OFF_IMM): New internal
relocation.
* bfd-in2.h: Regenerate.
* libbfd.h: Likewise.
*** gas/ChangeLog ***
2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
* config/tc-arm.c (parse_sys_vldr_vstr): New function.
(OP_VLDR): New enum operand_parse_code enumerator.
(parse_operands): Add logic for OP_VLDR.
(do_t_vldr_vstr_sysreg): New function.
(do_vldr_vstr): Likewise.
(insns): Guard VLDR and VSTR by arm_ext_v4t for Thumb mode.
(md_apply_fix): Add bound check for VLDR and VSTR co-processor offset.
Add masking logic for BFD_RELOC_ARM_T32_VLDR_VSTR_OFF_IMM relocation.
* testsuite/gas/arm/archv8m_1m-cmse-main-bad.s: Add examples of bad
uses of VLDR and VSTR.
* testsuite/gas/arm/archv8m_1m-cmse-main-bad.l: Add error messages for
above bad uses.
* testsuite/gas/arm/archv8m_1m-cmse-main.s: Add examples of VLDR and
VSTR valid uses.
* testsuite/gas/arm/archv8m_1m-cmse-main.d: Add disassembly for the
above examples.
*** opcodes/ChangeLog ***
2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
* arm-dis.c (coprocessor_opcodes): Document new %J and %K format
specifier. Add entries for VLDR and VSTR of system registers.
(print_insn_coprocessor): Forbid coprocessor numbers 8, 14 and 15 in
coprocessor instructions on Armv8.1-M Mainline targets. Add handling
of %J and %K format specifier.
Like for CLRM, this patch aims to share as much logic with the similar looking VLDM/VSTM. This is achieved by adding 2 new enumerator values in enum reg_list_els for the single-precision and double-precision variants of VSCCLRM and extending parse_vfp_reg_list () to deal with these types.
These behave like the existing REGLIST_VFP_S and REGLIST_VFP_D types with extra logic to expect VPR as the last element in the register list.
The function is algo augmented with a new partial_match parameter to indicate if any register other than VPR had already been parsed in the register list so as to not try parsing the second variant if that's the case and return the right error message.
The rest of the patch is the usual encoding function, new disassembler table entries and format specifier and parsing, encoding and disassembling tests.
It is worth mentioning that the new entry in the disassembler table was added in the coprocessor-related table despite VSCCLRM always being available even in FPU-less configurations. The main reason for this is that VSCCLRM also match VLDMIA entry and must thus be tried first but coprocessor entries are tried before T32 entries. It also makes sense because it is in the same encoding space as coprocessor and VFP instructions and is thus the natural place for someone to look for this instruction.
Note: Both variants of VSCCLRM support D16-D31 registers but Armv8.1-M Mainline overall does not. I have thus decided not to implement support for these registers in order to keep the code simpler. It can always be added later if needed.
ChangeLog entries are as follows:
*** gas/ChangeLog ***
2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
* config/tc-arm.c (arm_typed_reg_parse): Fix typo in comment.
(enum reg_list_els): New REGLIST_VFP_S_VPR and REGLIST_VFP_D_VPR
enumerators.
(parse_vfp_reg_list): Add new partial_match parameter. Set
*partial_match to TRUE if at least one element in the register list has
matched. Add support for REGLIST_VFP_S_VPR and REGLIST_VFP_D_VPR
register lists which expect VPR as last element in the list.
(s_arm_unwind_save_vfp_armv6): Adapt call to parse_vfp_reg_list to new
prototype.
(s_arm_unwind_save_vfp): Likewise.
(enum operand_parse_code): New OP_VRSDVLST enumerator.
(parse_operands): Adapt call to parse_vfp_reg_list to new prototype.
Handle new OP_VRSDVLST case.
(do_t_vscclrm): New function.
(insns): New entry for VSCCLRM instruction.
* testsuite/gas/arm/archv8m_1m-cmse-main-bad.s: Add invalid VSCCLRM
instructions.
* testsuite/gas/arm/archv8m_1m-cmse-main-bad.l: Add error expectations
for above instructions.
* testsuite/gas/arm/archv8m_1m-cmse-main.s: Add tests for VSCCLRM
instruction.
* testsuite/gas/arm/archv8m_1m-cmse-main.d: Add expected disassembly
for above instructions.
*** opcodes/ChangeLog ***
2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
* arm-dis.c (coprocessor_opcodes): Document new %C format control code.
Add new entries for VSCCLRM instruction.
(print_insn_coprocessor): Handle new %C format control code.
Given the similarity between LDM/STM and CLRM register lists, most of the changes in this patch aim at sharing code between those two sets of instruction. Sharing is achieved both in parsing and encoding of those instructions.
In terms of parsing, parse_reg_list () is extended to take a type that describe what type of instruction is being parsed. The reg_list_els used for parse_vfp_reg_list () is reused for the type and that function is added an assert for the new REGLIST_CLRM and REGLIST_RN enumerators.
parse_reg_list () is then taught to accept APSR and reject SP and PC when parsing for a CLRM instruction. At last, caller of parse_reg_list () is updated accordingly and logic is added for the new OP_CLRMLST operand.
Encoding-wise, encode_thumb2_ldmstm () is reused to encode the variable bits of CLRM and is thus renamed encode_thumb2_multi (). A new do_io parameter is added to distinguish between LDM/STM and CLRM which guard all the LDM/STM specific code of the function.
Finally objdump is told how to disassemble CLRM, again reusing the logic to print the LDM/STM register list (format specifier 'm'). Tests are also added in the form of negative tests to check parsing and encoding/disassembling tests.
ChangeLog entries are as follows:
*** gas/ChangeLog ***
2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
* config/tc-arm.c (enum reg_list_els): Define earlier and add
REGLIST_RN and REGLIST_CLRM enumerators.
(parse_reg_list): Add etype parameter to distinguish between regular
core register list and CLRM register list. Add logic to
recognize CLRM register list.
(parse_vfp_reg_list): Assert type is not for core register list.
(s_arm_unwind_save_core): Update call to parse_reg_list to new
prototype.
(enum operand_parse_code): Declare OP_CLRMLST enumerator.
(parse_operands): Update call to parse_reg_list to new prototype. Add
logic for OP_CLRMLST.
(encode_thumb2_ldmstm): Rename into ...
(encode_thumb2_multi): This. Add do_io parameter. Add logic to
encode CLRM and guard LDM/STM only code by do_io.
(do_t_ldmstm): Adapt to use encode_thumb2_multi.
(do_t_push_pop): Likewise.
(do_t_clrm): New function.
(insns): Define CLRM.
* testsuite/gas/arm/archv8m_1m-cmse-main-bad.d: New file.
* testsuite/gas/arm/archv8m_1m-cmse-main-bad.l: Likewise.
* testsuite/gas/arm/archv8m_1m-cmse-main-bad.s: Likewise.
* testsuite/gas/arm/archv8m_1m-cmse-main.d: Likewise.
* testsuite/gas/arm/archv8m_1m-cmse-main.s: Likewise.
*** opcodes/ChangeLog ***
2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
* arm-dis.c (thumb_opcodes): Document %n control code. Add entry for
CLRM.
(print_insn_thumb32): Add logic to print %n CLRM register list.
s patch is part of a series of patches to add support for Armv8.1-M Mainline instructions to binutils.
This patch adds support to the Scalar low overhead loop instructions:
LE
WLS
DLS
We also add a new assembler resolvable relocation bfd_reloc_code_real enum for the 12-bit branch offset used in these instructions.
ChangeLog entries are as follows:
*** bfd/ChnageLog ***
2019-04-12 Sudakshina Das <sudi.das@arm.com>
* reloc.c (BFD_RELOC_ARM_THUMB_LOOP12): New.
* bfd-in2.h: Regenerated.
* libbfd.h: Regenerated.
*** gas/ChangeLog ***
2019-04-12 Sudakshina Das <sudi.das@arm.com>
Andre Vieira <andre.simoesdiasvieira@arm.com>
* config/tc-arm.c (operand_parse_code): Add OP_LR and OP_oLR
for the LR operand and optional LR operand.
(parse_operands): Add switch cases for OP_LR and OP_oLR for
both type checking and value checking.
(encode_thumb32_addr_mode): New entries for DLS, WLS and LE.
(v8_1_loop_reloc): New helper function for handling labels
for the low overhead loop instructions.
(do_t_loloop): New function to encode DLS, WLS and LE.
(insns): New entries for WLS, DLS and LE.
(md_pcrel_from_section): New switch case
for BFD_RELOC_ARM_THUMB_LOOP12.
(md_appdy_fix): Likewise.
(tc_gen_reloc): Likewise.
* testsuite/gas/arm/armv8_1-m-tloop.s: New.
* testsuite/gas/arm/armv8_1-m-tloop.d: New.
* testsuite/gas/arm/armv8_1-m-tloop-bad.s: New.
* testsuite/gas/arm/armv8_1-m-tloop-bad.d: New.
* testsuite/gas/arm/armv8_1-m-tloop-bad.l: New.
*** opcodes/ChangeLog ***
2019-04-12 Sudakshina Das <sudi.das@arm.com>
* arm-dis.c (print_insn_thumb32): Updated to accept new %P
and %Q patterns.
s patch is part of a series of patches to add support for Armv8.1-M Mainline instructions to binutils.
This patch adds the BFCSEL instruction. It also adds a local relocation with a new bfd_reloc_code_real enum.
ChangeLog entries are as follows:
2019-04-15 Sudakshina Das <sudi.das@arm.com>
* reloc.c (BFD_RELOC_THUMB_PCREL_BFCSEL): New relocation.
* bfd-in2.h: Regenerated.
* libbfd.h: Likewise.
*** gas/ChangeLog ***
2019-04-15 Sudakshina Das <sudi.das@arm.com>
Andre Vieira <andre.simoesdiasvieira@arm.com>
* config/tc-arm.c (T16_32_TAB): New entriy for bfcsel.
(do_t_v8_1_branch): New switch case for bfcsel.
(toU): Define.
(insns): New instruction for bfcsel.
(md_pcrel_from_section): New switch case
for BFD_RELOC_THUMB_PCREL_BFCSEL.
(md_appdy_fix): Likewise
(tc_gen_reloc): Likewise.
* testsuite/gas/arm/armv8_1-m-bfcsel.d: New.
* testsuite/gas/arm/armv8_1-m-bfcsel.s: New.
*** ld/ChangeLog ***
2019-04-15 Sudakshina Das <sudi.das@arm.com>
* testsuite/ld-arm/bfcsel.s: New.
* testsuite/ld-arm/bfcsel.d: New.
* testsuite/ld-arm/arm-elf.exp: Add above test.
*** opcodes/ChangeLog ***
2019-04-15 Sudakshina Das <sudi.das@arm.com>
* arm-dis.c (thumb32_opcodes): New instruction bfcsel.
(print_insn_thumb32): Edit the switch case for %Z.
This patch is part of a series of patches to add support for Armv8.1-M Mainline
instructions to binutils.
This patch adds the BFL instruction.
*** gas/ChangeLog ***
2019-04-15 Sudakshina Das <sudi.das@arm.com>
Andre Vieira <andre.simoesdiasvieira@arm.com>
* config/tc-arm.c (T16_32_TAB): New entrie for bfl.
(do_t_v8_1_branch): New switch case for bfl.
(insns): New instruction for bfl.
* testsuite/gas/arm/armv8_1-m-bfl.d: New.
* testsuite/gas/arm/armv8_1-m-bfl.s: New.
* testsuite/gas/arm/armv8_1-m-bfl-bad.s: New.
* testsuite/gas/arm/armv8_1-m-bfl-bad.d: New.
* testsuite/gas/arm/armv8_1-m-bfl-bad.l: New.
* testsuite/gas/arm/armv8_1-m-bfl-rel.d: New.
* testsuite/gas/arm/armv8_1-m-bfl-rel.s: New.
*** ld/ChangeLog ***
2019-04-15 Sudakshina Das <sudi.das@arm.com>
* testsuite/ld-arm/bfl.s: New.
* testsuite/ld-arm/bfl.d: New.
* testsuite/ld-arm/arm-elf.exp: Add above test.
*** opcodes/ChangeLog ***
2019-04-15 Sudakshina Das <sudi.das@arm.com>
* arm-dis.c (thumb32_opcodes): New instruction bfl.
This patch is part of a series of patches to add support for Armv8.1-M Mainline instructions to binutils.
This patch adds the BFX and BFLX instructions.
ChangeLog entries are as follows :
*** gas/ChangeLog ***
2019-04-15 Sudakshina Das <sudi.das@arm.com>
* config/tc-arm.c (T16_32_TAB): New entries for bfx and bflx.
(do_t_v8_1_branch): New switch cases for bfx and bflx.
(insns): New instruction for bfx and bflx.
* testsuite/gas/arm/armv8_1-m-bf-exchange.d: New.
* testsuite/gas/arm/armv8_1-m-bf-exchange.s: New.
* testsuite/gas/arm/armv8_1-m-bf-exchange-bad.s: New
* testsuite/gas/arm/armv8_1-m-bf-exchange-bad.l: New
* testsuite/gas/arm/armv8_1-m-bf-exchange-bad.d: New
*** opcodes/ChangeLog ***
2019-04-15 Sudakshina Das <sudi.das@arm.com>
* arm-dis.c (print_insn_thumb32): Add '%<bitfield>S' to print an
Arm register with r13 and r15 unpredictable.
(thumb32_opcodes): New instructions for bfx and bflx.
This patch is part of a series of patches to add support for Armv8.1-M Mainline
instructions to binutils.
This patch adds the BF instruction.
ChangeLog entries are as follows:
*** gas/ChangeLog ***
2019-04-15 Sudakshina Das <sudi.das@arm.com>
Andre Vieira <andre.simoesdiasvieira@arm.com>
* config/tc-arm.c (T16_32_TAB): New entries for bf.
(do_t_branch_future): New.
(insns): New instruction for bf.
* testsuite/gas/arm/armv8_1-m-bf.d: New.
* testsuite/gas/arm/armv8_1-m-bf.s: New.
* testsuite/gas/arm/armv8_1-m-bf-bad.s: New.
* testsuite/gas/arm/armv8_1-m-bf-bad.l: New.
* testsuite/gas/arm/armv8_1-m-bf-bad.d: New.
* testsuite/gas/arm/armv8_1-m-bf-rel.d: New.
* testsuite/gas/arm/armv8_1-m-bf-rel.s: New.
*** ld/ChangeLog ***
2019-04-15 Sudakshina Das <sudi.das@arm.com>
* testsuite/ld-arm/bf.s: New.
* testsuite/ld-arm/bf.d: New.
* testsuite/ld-arm/arm-elf.exp: Add above test.
*** opcodes/ChangeLog ***
2019-04-15 Sudakshina Das <sudi.das@arm.com>
* arm-dis.c (thumb32_opcodes): New instructions for bf.
This patch implements the dsp, fp and fp.dp extensions for Armv8.1-M Mainline.
This patch also removes the fp-armv8 check from the half-precision move
instructions 'do_neon_movhf', as checking that the FP16 instructions extension
feature bit is enabled 'ARM_EXT2_FP16_INST' is enough.
gas/ChangeLog:
2019-04-15 Andre Vieira <andre.simoesdiasvieira@arm.com>
* config/tc-arm.c (do_neon_movhf): Remove fp-armv8 check.
(armv8_1m_main_ext_table): New extension table.
(arm_archs): Use the new extension table.
* doc/c-arm.texi: Add missing arch and document new extensions.
* testsuite/gas/arm/armv8.1-m.main-fp.d: New.
* testsuite/gas/arm/armv8.1-m.main-fp-dp.d: New.
* testsuite/gas/arm/armv8.1-m.main-hp.d: New.
The patch is straightforward, it does the following:
- support the new Tag_CPU_arch build attribute value, ie.:
+ declare the new value
+ update all the asserts forcing logic to be reviewed for new
architectures
+ create a corresponding bfd_mach_arm_8_1M_MAIN enumerator in bfd and
add mapping from Tag_CPU_arch to it
+ teach readelf about new Tag_CPU_arch value
- declare armv8.1-m.main as a supported architecture value
- define Armv8.1-M Mainline in terms of feature bits available
- tell objdump mapping from bfd_mach_arm_8_1M_MAIN enumerator to feature
bits available
- update architecture-specific logic in gas and bfd guarded by the
asserts mentioned above.
- tests for all the above
ChangeLog entries are as follows:
*** bfd/ChangeLog ***
2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
* archures.c (bfd_mach_arm_8_1M_MAIN): Define.
* bfd-in2.h: Regenerate.
* cpu-arm.c (arch_info_struct): Add entry for Armv8.1-M Mainline.
* elf32-arm.c (using_thumb_only): Return true for Armv8.1-M Mainline
and update assert.
(using_thumb2): Likewise.
(using_thumb2_bl): Update assert.
(arch_has_arm_nop): Likewise.
(bfd_arm_get_mach_from_attributes): Add case for Armv8.1-M Mainline.
(tag_cpu_arch_combine): Add logic for Armv8.1-M Mainline merging.
*** binutils/ChangeLog ***
2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
* readelf.c (arm_attr_tag_CPU_arch): Add entry for Armv8.1-M Mainline.
*** gas/ChangeLog ***
2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
* config/tc-arm.c (cpu_arch_ver): Add entry for Armv8.1-M Mainline
Tag_CPU_arch build attribute value. Reindent.
(get_aeabi_cpu_arch_from_fset): Update assert.
(aeabi_set_public_attributes): Update assert for Tag_DIV_use logic.
* testsuite/gas/arm/attr-march-armv8_1-m.main.d: New test.
*** include/ChangeLog ***
2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
* elf/arm.h (TAG_CPU_ARCH_V8_1M_MAIN): new macro.
(MAX_TAG_CPU_ARCH): Set value to above macro.
* opcode/arm.h (ARM_EXT2_V8_1M_MAIN): New macro.
(ARM_AEXT_V8_1M_MAIN): Likewise.
(ARM_AEXT2_V8_1M_MAIN): Likewise.
(ARM_ARCH_V8_1M_MAIN): Likewise.
*** ld/ChangeLog ***
2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
* testsuite/ld-arm/attr-merge-13.attr: New test.
* testsuite/ld-arm/attr-merge-13a.s: New test.
* testsuite/ld-arm/attr-merge-13b.s: New test.
*** opcodes/ChangeLog ***
2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
* arm-dis.c (select_arm_features): Add logic for Armv8.1-M Mainline.
gas/
* config/tc-mips.c (mips_cpu_info_table): Add i6500. Update
default ASEs for i6400.
* doc/c-mips.texi (-march): Document i6500.
* testsuite/gas/mips/elf_mach_i6400.d: New test.
* testsuite/gas/mips/elf_mach_i6500.d: New test.
* testsuite/gas/mips/mips.exp: Run the new tests.
GAS does not enable implicit ASEs for most MIPS processors.
The rework of option handling done as part of .module implementation
left the implicit ASE logic broken and default enabled ASEs for
most processors did not get applied. This patch ensures the ASE
information is carried forward to the point where it is required.
gas/
* config/tc-mips.c (mips_set_options) <init_ase>: New field.
(file_mips_opts, mips_opts) <init_ase>: Initialize new field.
(file_mips_check_options): Propagate initial ASE settings.
(mips_after_parse_args, parse_code_option): Track the initial
ASE settings for a CPU.
(s_mipsset): Restore the initial ASE settings when reverting
to the default arch.
* testsuite/gas/mips/elf_mach_p6600.d: New test.
* testsuite/gas/mips/mips.exp: Run the new test.
gas/
2019-04-11 Max Filippov <jcmvbkbc@gmail.com>
* testsuite/gas/xtensa/loop-relax-2.d: New test definition.
* testsuite/gas/xtensa/loop-relax.d: New test definition.
* testsuite/gas/xtensa/loop-relax.s: New test source.
* testsuite/gas/xtensa/text-section-literals-1a.d: New test
definition.
* testsuite/gas/xtensa/text-section-literals-2.d: New test
definition.
* testsuite/gas/xtensa/text-section-literals-2.s: New test
source.
* testsuite/gas/xtensa/text-section-literals-2a.d: New test
definition.
* testsuite/gas/xtensa/text-section-literals-3.d: New test
definition.
* testsuite/gas/xtensa/text-section-literals-3.s: New test
source.
* testsuite/gas/xtensa/text-section-literals-4.d: New test
definition.
* testsuite/gas/xtensa/text-section-literals-4.s: New test
source.
* testsuite/gas/xtensa/text-section-literals-4a.d: New test
definition.
gas/
2019-04-11 Max Filippov <jcmvbkbc@gmail.com>
* testsuite/gas/xtensa/all.exp: Remove all expect-based
tests and all explicit run_dump_test / run_list_test
invocations. Add run_dump_tests for all .d files in the
test subdirectory.
* testsuite/gas/xtensa/entry_align.d: New test definition.
* testsuite/gas/xtensa/entry_align.l: New test output.
* testsuite/gas/xtensa/entry_misalign.d: New test definition.
* testsuite/gas/xtensa/entry_misalign2.d: New test definition.
* testsuite/gas/xtensa/j_too_far.d: New test definition.
* testsuite/gas/xtensa/j_too_far.l: New test output.
* testsuite/gas/xtensa/loop_align.d: New test definition.
* testsuite/gas/xtensa/loop_misalign.d: New test definition.
* testsuite/gas/xtensa/trampoline-2.d: New test definition.
* testsuite/gas/xtensa/trampoline-2.l: Remove empty output.
* testsuite/gas/xtensa/xtensa-err.exp: Use positive logic.
Provide literal position at the beginning of each section for literal
space reserved by relaxations when text-section-literals or
auto-litpools options are used. Remove code that adds fill frag to the
literal section for every .literal_position directive to avoid creation
of empty literal sections.
Fix auto-litpools tests that got literal pool address changes.
gas/
2019-04-11 Max Filippov <jcmvbkbc@gmail.com>
* config/tc-xtensa.c (xtensa_is_init_fini): Add declaration.
(xtensa_mark_literal_pool_location): Don't add fill frag to literal
section that records literal pool location.
(md_begin): Call xtensa_mark_literal_pool_location when text
section literals or auto litpools are used.
(xtensa_elf_section_change_hook): Call
xtensa_mark_literal_pool_location when text section literals or
auto litpools are used, there's no literal pool location defined
for the current section and it's not .init or .fini.
* testsuite/gas/xtensa/auto-litpools-first1.d: Fix up addresses.
* testsuite/gas/xtensa/auto-litpools-first2.d: Likewise.
* testsuite/gas/xtensa/auto-litpools.d: Likewise.
This patch updates the Store allocation tags instructions in
Armv8.5-A Memory Tagging Extension. This is part of the changes
that have been introduced recently in the 00bet10 release
All of these instructions have an updated register operand (Xt -> <Xt|SP>)
- STG <Xt|SP>, [<Xn|SP>, #<simm>]
- STG <Xt|SP>, [<Xn|SP>, #<simm>]!
- STG <Xt|SP>, [<Xn|SP>], #<simm>
- STZG <Xt|SP>, [<Xn|SP>, #<simm>]
- STZG <Xt|SP>, [<Xn|SP>, #<simm>]!
- STZG <Xt|SP>, [<Xn|SP>], #<simm>
- ST2G <Xt|SP>, [<Xn|SP>, #<simm>]
- ST2G <Xt|SP>, [<Xn|SP>, #<simm>]!
- ST2G <Xt|SP>, [<Xn|SP>], #<simm>
- STZ2G <Xt|SP>, [<Xn|SP>, #<simm>]
- STZ2G <Xt|SP>, [<Xn|SP>, #<simm>]!
- STZ2G <Xt|SP>, [<Xn|SP>], #<simm>
In order to accept <Rt|SP> a new operand type Rt_SP is introduced which has
the same field as FLD_Rt but follows other semantics of Rn_SP.
*** gas/ChangeLog ***
2019-04-11 Sudakshina Das <sudi.das@arm.com>
* config/tc-aarch64.c (process_omitted_operand): Add case for
AARCH64_OPND_Rt_SP.
(parse_operands): Likewise.
* testsuite/gas/aarch64/armv8_5-a-memtag.d: Update tests.
* testsuite/gas/aarch64/armv8_5-a-memtag.s: Likewise.
* testsuite/gas/aarch64/illegal-memtag.l: Likewise.
* testsuite/gas/aarch64/illegal-memtag.s: Likewise.
*** include/ChangeLog ***
2019-04-11 Sudakshina Das <sudi.das@arm.com>
* opcode/aarch64.h (enum aarch64_opnd): Add AARCH64_OPND_Rt_SP.
*** opcodes/ChangeLog ***
2019-04-11 Sudakshina Das <sudi.das@arm.com>
* aarch64-opc.c (aarch64_print_operand): Add case for
AARCH64_OPND_Rt_SP.
(verify_constraints): Likewise.
* aarch64-tbl.h (QL_LDST_AT): Update to add SP qualifier.
(struct aarch64_opcode): Update stg, stzg, st2g, stz2g instructions
to accept Rt|SP as first operand.
(AARCH64_OPERANDS): Add new Rt_SP.
* aarch64-asm-2.c: Regenerated.
* aarch64-dis-2.c: Regenerated.
* aarch64-opc-2.c: Regenerated.
This patch adds the new LDGM/STGM instructions of the
Armv8.5-A Memory Tagging Extension. This is part of the changes
that have been introduced recently in the 00bet10 release
The instructions are as follows:
LDGM Xt, [<Xn|SP>]
STGM Xt, [<Xn|SP>]
*** gas/ChangeLog ***
2019-04-11 Sudakshina Das <sudi.das@arm.com>
* testsuite/gas/aarch64/armv8_5-a-memtag.d: New tests for ldgm and stgm.
* testsuite/gas/aarch64/armv8_5-a-memtag.s: Likewise.
* testsuite/gas/aarch64/illegal-memtag.l: Likewise.
* testsuite/gas/aarch64/illegal-memtag.s: Likewise.
*** opcodes/ChangeLog ***
2019-04-11 Sudakshina Das <sudi.das@arm.com>
* aarch64-asm-2.c: Regenerated.
* aarch64-dis-2.c: Likewise.
* aarch64-opc-2.c: Likewise.
* aarch64-tbl.h (aarch64_opcode): Add new ldgm and stgm.
The fix H.J. implemented for PR gas/22791 in the thread starting at
[PATCH] x86-64: Treat PC32 relocation with branch as PLT32
https://sourceware.org/ml/binutils/2018-02/msg00065.html
is causing problems on Solaris/x86. The native linker is strongly
preferred there, and there's no intention of implementing the linker
optimization he plans there. Besides, the kernel runtime linker,
otherwise has no need to deal with that reloc at all, and instead of
adding (possibly even more) workarounds with no benefit, it seems
appropriate to disable the R_X86_64_PLT32 generation as branch marker on
Solaris/x86 in the first place.
The patch itself is trivial, the only complication is adapting the
testsuite. Since I've found no way to have conditional sections in the
.d files, I've instead used the solution already found elsewhere of
having separate .d files for the affected tests in an i386/solaris
subdirectory and skipping the original ones.
Tested on amd64-pc-solaris2.11 and x86_64-pc-linux-gnu without
regressions.
* config/tc-i386.c (need_plt32_p) [TE_SOLARIS]: Return FALSE.
* testsuite/gas/i386/solaris/solaris.exp: New driver.
* testsuite/gas/i386/solaris/reloc64.d,
testsuite/gas/i386/solaris/x86-64-jump.d,
testsuite/gas/i386/solaris/x86-64-mpx-branch-1.d,
testsuite/gas/i386/solaris/x86-64-mpx-branch-2.d,
testsuite/gas/i386/solaris/x86-64-nop-3.d,
testsuite/gas/i386/solaris/x86-64-nop-4.d,
testsuite/gas/i386/solaris/x86-64-nop-5.d,
testsuite/gas/i386/solaris/x86-64-relax-2.d,
testsuite/gas/i386/solaris/x86-64-relax-3.d: New tests.
* testsuite/gas/i386/reloc64.d,
testsuite/gas/i386/x86-64-jump.d,
testsuite/gas/i386/x86-64-mpx-branch-1.d,
testsuite/gas/i386/x86-64-mpx-branch-2.d,
testsuite/gas/i386/x86-64-nop-3.d,
testsuite/gas/i386/x86-64-nop-4.d,
testsuite/gas/i386/x86-64-nop-5.d,
testsuite/gas/i386/x86-64-relax-2.d,
testsuite/gas/i386/x86-64-relax-3.d: Skip on *-*-solaris*.
In Release 6 of the MIPS architecture [1], instruction RDHWR supports
a 3rd operand to serve as the 3-bit select field for the hardware
register.
[1] "MIPS Architecture for Programmers Volume II-A: The MIPS32
Instruction Set Manual", Imagination Technologies Ltd., Document
Number: MD00086, Revision 6.06, December 15, 2016, Section 3.2
"Alphabetical List of Instructions", pp. 332-334
opcodes/
* mips-opc.c (mips_builtin_opcodes): Add RDHWR rt rd sel.
gas/
* testsuite/gas/mips/mips.exp: Run hwr-names test.
* testsuite/gas/mips/hwr-names.s: Add test cases for RDHWR with
the SEL field.
* testsuite/gas/mips/mipsr6@hwr-names.d: New file.
Adds a new test checking conditional branch BO values.
* testsuite/gas/ppc/bc.s,
* testsuite/gas/ppc/bcat.d,
* testsuite/gas/ppc/bcaterr.d,
* testsuite/gas/ppc/bcaterr.l,
* testsuite/gas/ppc/bcy.d,
* testsuite/gas/ppc/bcyerr.d,
* testsuite/gas/ppc/bcyerr.l: New tests.
* testsuite/gas/ppc/ppc.exp: Run them.
When an instruction has operands, the PowerPC disassembler prints
spaces after the opcode so as to line up operands. If the operands
are all optional and all default value, then no operands are printed,
leaving trailing spaces. This patch fixes that.
opcodes/
* ppc-dis.c (print_insn_powerpc): Delay printing spaces after
opcode until first operand is output.
gas/
* testsuite/gas/ppc/476.d: Remove trailing spaces.
* testsuite/gas/ppc/a2.d: Likewise.
* testsuite/gas/ppc/booke.d: Likewise.
* testsuite/gas/ppc/booke_xcoff.d: Likewise.
* testsuite/gas/ppc/e500.d: Likewise.
* testsuite/gas/ppc/e500mc.d: Likewise.
* testsuite/gas/ppc/e6500.d: Likewise.
* testsuite/gas/ppc/htm.d: Likewise.
* testsuite/gas/ppc/power6.d: Likewise.
* testsuite/gas/ppc/power8.d: Likewise.
* testsuite/gas/ppc/power9.d: Likewise.
* testsuite/gas/ppc/vle.d: Likewise.
ld/
* testsuite/ld-powerpc/tlsexe32.d: Remove trailing spaces.
* testsuite/ld-powerpc/tlsopt5.d: Likewise.
* testsuite/ld-powerpc/tlsopt5_32.d: Likewise.
This patch adds a new framework to add architecture sensitive extensions, like
GCC does. This patch also implements all architecture extensions currently
available in GCC.
This framework works as follows. To enable architecture sensitive extensions
for a particular architecture, that architecture must contain an ARM_ARCH_OPT2
entry in the 'arm_archs' table. All fields here are the same as previous, with
the addition of a new extra field at the end to <name> it's extension table.
This <name>, corresponds to a <name>_ext_table of type 'struct arm_ext_table'.
This struct can be filled with three types of entries:
ARM_ADD (string <ext>, arm_feature_set <enable_bits>), which means +<ext> will
enable <enable_bits>
ARM_REMOVE (string <ext>, arm_feature_set <disable_bits>), which means
+no<ext> will disable <disable_bits>
ARM_EXT (string <ext>, arm_feature_set <enable_bits>, arm_feature_set
<disable_bits>), which means +<ext> will enable <enable_bits> and +no<ext>
will disable <disable_bits> (this is to be used instead of adding an
ARM_ADD and ARM_REMOVE for the same <ext>)
This patch does not disable the use of the old extensions, even if some of them
are duplicated in the new tables. This is a "in-between-step" as we may want to
deprecate the old table of extensions in later patches. For now, GAS will first
look for the +<ext> or +no<ext> in the new table and if no entry is found it
will continue searching in the old table, following old behaviour. If only an
ARM_ADD or an ARM_REMOVE is defined for <ext> and +no<ext> or +<ext> resp. is
used then it also continues to search the old table for it.
A couple of caveats:
- This patch does not enable the use of these architecture extensions with the
'.arch_extension' directive. This is future work that I will tend to later.
- This patch does not enable the use of these architecture extensions with the
-mcpu option. This is future work that I will tend to later.
- This patch does not change the current behaviour when combining an
architecture extension and using -mfpu on the command-line. The current
behaviour of GAS is to stage the union of feature bits enabled by both -march
and -mfpu. GCC behaves differently here, so this is something we may want to
revisit on a later date.
"mtfsb0 4*cr7+lt" doesn't make all that much sense, but unfortunately
glibc uses just that instead of "mtfsb0 28" to clear the fpscr xe bit.
So for backwards compatibility accept cr field expressions when
assembling mtfsb operands, but disassemble to a plain number.
PR 24390
include/
* opcode/ppc.h (PPC_OPERAND_CR_REG): Comment.
opcodes/
* ppc-opc.c (BTF): Define.
(powerpc_opcodes): Use for mtfsb*.
* ppc-dis.c (print_insn_powerpc): Print fields with both
PPC_OPERAND_CR_REG and PPC_OPERAND_CR_BIT as a plain number.
gas/
* testsuite/gas/ppc/476.d: Update mtfsb*.
* testsuite/gas/ppc/a2.d: Likewise.
and tidy "forward" test. I've removed some checks in d30v
md_apply_fix that have no business being there. Any symbol problems
will be caught later in tc_gen_reloc, and overflow checking is done in
gas/write.c.
* config/tc-d10v.c (md_apply_fix): Apply BFD_RELOC_8.
* config/tc-pdp11.c (md_apply_fix): Likewise.
* config/tc-d30v.c (md_apply_fix): Don't emit errors for BFD_RELOC_8,
BFD_RELOC_16, and BFD_RELOC_64.
* testsuite/gas/all/gas.exp: Move target exclusions for forward
test, but not cr16, to..
* testsuite/gas/all/forward.d: ..here, with explanation. Remove
d10v, d30v, and pdp11 xfails.
Update EVEX vector load/store optimization:
1. There is no need to check AVX since AVX2 is required for AVX512F.
2. We need to check both operands for ZMM register since AT&T syntax
may not set zmmword on the first operand.
3. Update Opcode_SIMD_IntD check and set.
4. Since the VEX prefix has 2 or 3 bytes, the EVEX prefix has 4 bytes,
EVEX Disp8 has 1 byte and VEX Disp32 has 4 bytes, we choose EVEX Disp8
over VEX Disp32.
* config/tc-i386.c (optimize_encoding): Don't check AVX for
EVEX vector load/store optimization. Check both operands for
ZMM register. Update EVEX vector load/store opcode check.
Choose EVEX Disp8 over VEX Disp32.
* testsuite/gas/i386/optimize-1.d: Updated.
* testsuite/gas/i386/optimize-1a.d: Likewise.
* testsuite/gas/i386/optimize-2.d: Likewise.
* testsuite/gas/i386/optimize-4.d: Likewise.
* testsuite/gas/i386/optimize-5.d: Likewise.
* testsuite/gas/i386/x86-64-optimize-2.d: Likewise.
* testsuite/gas/i386/x86-64-optimize-2a.d: Likewise.
* testsuite/gas/i386/x86-64-optimize-2b.d: Likewise.
* testsuite/gas/i386/x86-64-optimize-3.d: Likewise.
* testsuite/gas/i386/x86-64-optimize-5.d: Likewise.
* testsuite/gas/i386/x86-64-optimize-6.d: Likewise.
* testsuite/gas/i386/optimize-1.s: Add ZMM register load
test.
* testsuite/gas/i386/x86-64-optimize-2.s: Likewise.
Since not all AVX512F processors support AVX512VL, we can optimize
512-bit EVEX to 128-bit EVEX encoding for upper 16 vector registers
only when AVX512VL is enabled explicitly at command-line or via
".arch .avx512vl" directive.
PR gas/24352
* config/tc-i386.c (optimize_encoding): Check only
cpu_arch_flags.bitfield.cpuavx512vl.
* testsuite/gas/i386/i386.exp: Run x86-64-optimize-2b.
* testsuite/gas/i386/x86-64-optimize-2.d: Revert the last
change.
* testsuite/gas/i386/x86-64-optimize-2b.d: New file.
* testsuite/gas/i386/x86-64-optimize-2b.s: Likewise.
Since all AVX512 processors support AVX, we can encode 256-bit/512-bit
VEX/EVEX vector register clearing instructions with 128-bit VEX vector
register clearing instructions at -O1.
* config/tc-i386.c (optimize_encoding): Encode 256-bit/512-bit
VEX/EVEX vector register clearing instructions with 128-bit VEX
vector register clearing instructions at -O1.
* doc/c-i386.texi: Update -O1 and -O2 documentation.
* testsuite/gas/i386/i386.exp: Run optimize-1a and
x86-64-optimize-2a.
* testsuite/gas/i386/optimize-1a.d: New file.
* testsuite/gas/i386/x86-64-optimize-2a.d: Likewise.
Set optimize to INT_MAX, instead of -1, for -Os so that -Os will include
-O2 optimization.
PR gas/24353
* config/tc-i386.c (md_parse_option): Set optimize to INT_MAX
for -Os.
* testsuite/gas/i386/optimize-2.s: Add a test.
* testsuite/gas/i386/x86-64-optimize-3.s: Likewise.
* testsuite/gas/i386/optimize-2.d: Updated.
* testsuite/gas/i386/x86-64-optimize-3.d: Likewise.
We can optimize 512-bit EVEX to 128-bit EVEX encoding for upper 16
vector registers only when AVX512VL is enabled. We can't optimize
EVEX to 128-bit VEX encoding when AVX isn't enabled.
PR gas/24352
* config/tc-i386.c (optimize_encoding): Encode 512-bit EVEX
with 128-bit VEX encoding only when AVX is enabled and with
128-bit EVEX encoding only when AVX512VL is enabled.
* testsuite/gas/i386/i386.exp: Run PR gas/24352 tests.
* testsuite/gas/i386/optimize-6.s: New file.
* testsuite/gas/i386/optimize-6a.d: Likewise.
* testsuite/gas/i386/optimize-6b.d: Likewise.
* testsuite/gas/i386/optimize-6c.d: Likewise.
* testsuite/gas/i386/x86-64-optimize-7.s: Likewise.
* testsuite/gas/i386/x86-64-optimize-7a.d: Likewise.
* testsuite/gas/i386/x86-64-optimize-7b.d: Likewise.
* testsuite/gas/i386/x86-64-optimize-7c.d: Likewise.
* testsuite/gas/i386/x86-64-optimize-2.d: Updated.
Committed on behalf of Matthew Malcomson.
This allows checking the command line parsing more easily than before by
allowing many command line invokations from the same .d file.
Each line is used as a set of flags, and the tests are ran against the output
of the assembler with each set.
Each line of assembler is treated as another set of tests (as if the test file
were copied to another with a different #as: line).
This patch includes some example uses where multiple testcases can be merged
into one file using this new functionality.
binutils/ChangeLog:
* testsuite/lib/binutils-common.exp: Allow multiple "as" lines.
gas/ChangeLog:
* testsuite/gas/aarch64/dotproduct.d: Use multiple "as" lines.
* testsuite/gas/aarch64/dotproduct_armv8_4.d: Remove.
* testsuite/gas/aarch64/dotproduct_armv8_4.s: Remove.
* testsuite/gas/aarch64/illegal-dotproduct.d: Use multiple "as"
lines.
* testsuite/gas/aarch64/ldst-rcpc-armv8_2.d: Remove.
* testsuite/gas/aarch64/ldst-rcpc.d: Use multiple "as" lines.
The software trap instruction HLT that was introduced in Armv8-a is used
as the semihosting trap instruction in AArch64. In order to allow systems
configured to run AArch64 code to also run AArch32 with semihosting it was
decided that AArch32 should also use HLT in the case of the "mixed mode"
environment. This requires that HLT also be backported to all earlier
architectures. The instruction is in the undefined encoding space earlier
architectures but must trigger a semihosting trap [3].
The Arm Architectural Reference Manual [1] doesn't explicitly mention this
however this is an explicit requirement in the Semihosting-v2 protocol [2].
[1] https://developer.arm.com/docs/ddi0487/latest/arm-architecture-reference-manual-armv8-for-armv8-a-architecture-profile
[2] https://developer.arm.com/docs/100863/latest/the-semihosting-interface
[3] 19a6e31c9d
gas/ChangeLog:
* config/tc-arm.c (insns): Redefine THUMB_VARIANT and ARM_VARIANT for
hlt to armv1.
* testsuite/gas/arm/armv8a-automatic-hlt.d: Update TAGs
* testsuite/gas/arm/hlt.d: New test.
* testsuite/gas/arm/hlt.s: New test.
opcodes/ChangeLog:
* arm-dis.c (arm_opcodes): Redefine hlt to armv1.
This patch just adds a few negative tests for the Armv8.3-a complex instructions.
These already do the right disassembly without needing a verifier, but adding
some tests to make sure that stays that way.
gas/ChangeLog:
* testsuite/gas/aarch64/undefined_advsimd_armv8_3.d: New test.
* testsuite/gas/aarch64/undefined_advsimd_armv8_3.s: New test.
The AArch64 instruction set has cut-outs inside instructions encodings for
when a given encoding that would normally fall within the encoding space of
an instruction is instead undefined.
This updates the first few instructions FMLA, FMLA, FMUL and FMULX in the case
where sz:L == 11.
gas/ChangeLog:
PR binutils/23212
* testsuite/gas/aarch64/undefined_by_elem_sz_l.s: New test.
* testsuite/gas/aarch64/undefined_by_elem_sz_l.d: New test.
opcodes/ChangeLog:
PR binutils/23212
* aarch64-opc.h (enum aarch64_field_kind): Add FLD_sz.
* aarch64-opc.c (verify_elem_sd): New.
(fields): Add FLD_sz entr.
* aarch64-tbl.h (_SIMD_INSN): New.
(aarch64_opcode_table): Add elem_sd verifier to fmla, fmls, fmul and
fmulx scalar and vector by element isns.
This is done in order to avoid a pipeline hazard on the GR6.
gas/
* config/tc-visium.c (md_assemble) <mode_cad>: Align instruction
on 64-bit boundaries for the GR6.
* testsuite/gas/visium/allinsn_gr6.s: Tweak.
* testsuite/gas/visium/allinsn_gr6.d: Likewise.
* testsuite/gas/visium/bra-1.d: New test.
* testsuite/gas/visium/bra-1.s: Likewise.
* testsuite/gas/visium/visium.exp: Run bra-1 test.
Alan Modra
John Darrington
Matthew Fortune
Jozef Lawrynowicz
Andre Vieira
Matthew Fortune
Max Filippov
Sudakshina Das
Rainer Orth
Robert Suchanek
H.J. Lu
Xuepeng Guo
Peter Bergner
Andreas Krebbel
Matthew Malcomson
Tamar Christina
Eric Botcazou