Commit Graph

3925 Commits

Author SHA1 Message Date
Alex Coplan
c39c821c1d gas: Fix checking for backwards .org with negative offset
This patch fixes internal errors in (at least) arm and aarch64 GAS
when assembling code that attempts a negative .org.  The bug appears
to be a regression introduced in binutils-2.29 by commit 9875b36538.

	* write.c (relax_segment): Fix handling of negative offset when
	relaxing an rs_org frag.
	* testsuite/gas/aarch64/org-neg.d: New test.
	* testsuite/gas/aarch64/org-neg.l: Error output for test.
	* testsuite/gas/aarch64/org-neg.s: Input for test.
	* testsuite/gas/arm/org-neg.d: New test.
	* testsuite/gas/arm/org-neg.l: Error output for test.
	* testsuite/gas/arm/org-neg.s: Input for test.
2020-06-02 00:10:40 +09:30
Stephen Casner
66e3eb08a5 Fix all unexpected failures in gas testsuite for pdp11-aout.
These failures were caused by the PDP11's mix of little-endian octets
in shorts but shorts in big endian order for long or quad so regexps
did not match.  Also tests used addresses as values in .long which
required BRD_RELOC_32 that was not implemented.

* gas/config/tc-pdp11.c (md_number_to_chars): Implement .quad
* gas/testsuite/gas/all/gas.exp: Select alternate test scripts for
pdp11, skip octa test completely.
* gas/testsuite/gas/all/eqv-dot-pdp11.s: Identical to eqv-dot.s
* gas/testsuite/gas/all/eqv-dot-pdp11.d: Match different octet order.
* gas/testsuite/gas/all/cond-pdp11.l: Match different octet order.

* bfd/pdp11.c: Implement BRD_RELOC_32 to relocate the low 16 bits of
addreses in .long (used in testsuites) and .stab values.
2020-05-28 10:11:59 -07:00
Stephen Casner
1c912705af Fix PR gas/26001 (pdp11-*-*)
PR gas/26001
* gas/config/tc-pdp11.c (parse_reg): Distinguish register names from
symbols that begin with a register name.
* gas/testsuite/gas/pdp11/pdp11.exp: Add test of such symbols.
* gas/testsuite/gas/pdp11/pr26001.s: Likewise.
* gas/testsuite/gas/pdp11/pr26001.d: Likewise.
2020-05-27 18:40:38 -07:00
H.J. Lu
3c73074034 gas: Adjust x86 tests for PECOFF
* testsuite/gas/i386/align-branch-9.d: Updated for PECOFF.
	* testsuite/gas/i386/inval-avx512f.s: Add .p2align for PECOFF.
	* testsuite/gas/i386/inval-avx512f.l: Updated.
2020-05-26 14:18:08 -07:00
Stefan Schulze Frielinghaus
f687f5f563 S/390: z13: Accept vector alignment hints
Accept vector alignment hints on z13 although they are ignored there.
The advantage is that any binary compiled for architecture level z13 may
run on z14 or later and benefit from vector alignment hints.

gas/ChangeLog:

2020-05-18  Stefan Schulze Frielinghaus  <stefansf@linux.ibm.com>

	* testsuite/gas/s390/zarch-z13.d: Add regexp checks for vector
	load/store instruction variants with alignment hints.
	* testsuite/gas/s390/zarch-z13.s: Emit new vector load/store
	instruction variants with alignment hints.

opcodes/ChangeLog:

2020-05-18  Stefan Schulze Frielinghaus  <stefansf@linux.ibm.com>

	* s390-opc.txt: Relocate vector load/store instructions with
	additional alignment parameter and change architecture level
	constraint from z14 to z13.
2020-05-26 18:15:41 +02:00
Alan Modra
9fbb53c7c8 Replace "if (x) free (x)" with "free (x)", gas
* atof-generic.c: Replace "if (x) free (x)" with "free (x)"
	throughout.
	* config/obj-elf.c: Likewise.
	* config/tc-aarch64.c: Likewise.
	* config/tc-arm.c: Likewise.
	* config/tc-m68k.c: Likewise.
	* config/tc-nios2.c: Likewise.
	* config/tc-tic30.c: Likewise.
	* ecoff.c: Likewise.
	* read.c: Likewise.
	* stabs.c: Likewise.
	* symbols.c: Likewise.
	* testsuite/gas/all/test-gen.c: Likewise.
2020-05-21 10:45:33 +09:30
Nelson Chu
8f595e9b4f [PATCH v2 0/9] RISC-V: Support version controling for ISA standard extensions and CSR
1. Remove the -mriscv-isa-version and --with-riscv-isa-version options.
We can still use -march to choose the version for each extensions, so there is
no need to add these.

2. Change the arguments of options from [1p9|1p9p1|...] to [1.9|1.9.1|...].
Unlike the architecture string has specified by spec, ther is no need to do
the same thing for options.

3. Spilt the patches to reduce the burdens of review.

[PATCH 3/7] RISC-V: Support new GAS options and configure options to set ISA versions
to
[PATCH v2 3/9] RISC-V: Support GAS option -misa-spec to set ISA versions
[PATCH v2 4/9] RISC-V: Support configure options to set ISA versions by default.

[PATCH 4/7] RISC-V: Support version checking for CSR according to privilege version.
to
[PATCH v2 5/9] RISC-V: Support version checking for CSR according to privilege spec version.
[PATCH v2 6/9] RISC-V: Support configure option to choose the privilege spec version.

4. Use enum class rather than string to compare the choosen ISA spec in opcodes/riscv-opc.c.
The behavior is same as comparing the choosen privilege spec.

include	* opcode/riscv.h: Include "bfd.h" to support bfd_boolean.
	(enum riscv_isa_spec_class): New enum class.  All supported ISA spec
	belong to one of the class
	(struct riscv_ext_version): New structure holds version information
	for the specific ISA.
	* opcode/riscv-opc.h (DECLARE_CSR): There are two version information,
	define_version and abort_version.  The define_version means which
	privilege spec is started to define the CSR, and the abort_version
	means which privilege spec is started to abort the CSR.  If the CSR is
	valid for the newest spec, then the abort_version should be
	PRIV_SPEC_CLASS_DRAFT.
	(DECLARE_CSR_ALIAS): Same as DECLARE_CSR, but only for the obselete CSR.
	* opcode/riscv.h (enum riscv_priv_spec_class): New enum class.  Define
	the current supported privilege spec versions.
	(struct riscv_csr_extra): Add new fields to store more information
	about the CSR.  We use these information to find the suitable CSR
	address when user choosing a specific privilege spec.

binutils * dwarf.c: Updated since DECLARE_CSR is changed.

opcodes	* riscv-opc.c (riscv_ext_version_table): The table used to store
	all information about the supported spec and the corresponding ISA
	versions.  Currently, only Zicsr is supported to verify the
	correctness of Z sub extension settings.  Others will be supported
	in the future patches.
	(struct isa_spec_t, isa_specs): List for all supported ISA spec
	classes and the corresponding strings.
	(riscv_get_isa_spec_class): New function.  Get the corresponding ISA
	spec class by giving a ISA spec string.
	* riscv-opc.c (struct priv_spec_t): New structure.
	(struct priv_spec_t priv_specs): List for all supported privilege spec
	classes and the corresponding strings.
	(riscv_get_priv_spec_class): New function.  Get the corresponding
	privilege spec class by giving a spec string.
	(riscv_get_priv_spec_name): New function.  Get the corresponding
	privilege spec string by giving a CSR version class.
	* riscv-dis.c: Updated since DECLARE_CSR is changed.
	* riscv-dis.c: Add new disassembler option -Mpriv-spec to dump the CSR
	according to the chosen version.  Build a hash table riscv_csr_hash to
	store the valid CSR for the chosen pirv verison.  Dump the direct
	CSR address rather than it's name if it is invalid.
	(parse_riscv_dis_option_without_args): New function.  Parse the options
	without arguments.
	(parse_riscv_dis_option): Call parse_riscv_dis_option_without_args to
	parse the options without arguments first, and then handle the options
	with arguments.  Add the new option -Mpriv-spec, which has argument.
	* riscv-dis.c (print_riscv_disassembler_options): Add description
	about the new OBJDUMP option.

ld	* testsuite/ld-riscv-elf/attr-merge-arch-01.d: Updated
        priv attributes according to the -mpriv-spec option.
	* testsuite/ld-riscv-elf/attr-merge-arch-02.d: Likewise.
	* testsuite/ld-riscv-elf/attr-merge-arch-03.d: Likewise.
	* testsuite/ld-riscv-elf/attr-merge-priv-spec-a.s: Likewise.
	* testsuite/ld-riscv-elf/attr-merge-priv-spec-b.s: Likewise.
	* testsuite/ld-riscv-elf/attr-merge-priv-spec.d: Likewise.
	* testsuite/ld-riscv-elf/attr-merge-stack-align.d: Likewise.
	* testsuite/ld-riscv-elf/attr-merge-strict-align-01.d: Likewise.
	* testsuite/ld-riscv-elf/attr-merge-strict-align-02.d: Likewise.
	* testsuite/ld-riscv-elf/attr-merge-strict-align-03.d: Likewise.
	* testsuite/ld-riscv-elf/attr-merge-strict-align-04.d: Likewise.
	* testsuite/ld-riscv-elf/attr-merge-strict-align-05.d: Likewise.

bfd 	* elfxx-riscv.h (riscv_parse_subset_t): Add new callback function
	get_default_version.  It is used to find the default version for
	the specific extension.
	* elfxx-riscv.c (riscv_parsing_subset_version): Remove the parameters
	default_major_version and default_minor_version.  Add new bfd_boolean
	parameter *use_default_version.  Set it to TRUE if we need to call
	the callback rps->get_default_version to find the default version.
	(riscv_parse_std_ext): Call rps->get_default_version if we fail to find
	the default version in riscv_parsing_subset_version, and then call
	riscv_add_subset to add the subset into subset list.
	(riscv_parse_prefixed_ext): Likewise.
	(riscv_std_z_ext_strtab): Support Zicsr extensions.
	* elfnn-riscv.c (riscv_merge_std_ext): Use strcasecmp to compare the
	strings rather than characters.
	riscv_merge_arch_attr_info): The callback function get_default_version
	is only needed for assembler, so set it to NULL int the linker.
	* elfxx-riscv.c (riscv_estimate_digit): Remove the static.
	* elfxx-riscv.h: Updated.

gas	* testsuite/gas/riscv/priv-reg-fail-read-only-01.s: Updated.
	* config/tc-riscv.c (default_arch_with_ext, default_isa_spec):
	Static variables which are used to set the ISA extensions. You can
	use -march (or ELF build attributes) and -misa-spec to set them,
	respectively.
	(ext_version_hash): The hash table used to handle the extensions
	with versions.
	(init_ext_version_hash): Initialize the ext_version_hash according
	to riscv_ext_version_table.
	(riscv_get_default_ext_version): The callback function of
	riscv_parse_subset_t.  According to the choosed ISA spec,
	get the default version for the specific extension.
	(riscv_set_arch): Set the callback function.
	(enum options, struct option md_longopts): Add new option -misa-spec.
	(md_parse_option): Do not call riscv_set_arch for -march.  We will
	call it later in riscv_after_parse_args.  Call riscv_get_isa_spec_class
	to set default_isa_spec class.
	(riscv_after_parse_args): Call init_ext_version_hash to initialize the
	ext_version_hash, and then call riscv_set_arch to set the architecture
	with versions according to default_arch_with_ext.
	* testsuite/gas/riscv/attribute-02.d: Set 0p0 as default version for
	x extensions.
	* testsuite/gas/riscv/attribute-03.d: Likewise.
	* testsuite/gas/riscv/attribute-09.d: New testcase.  For i-ext, we
	already set it's version to 2p1 by march, so no need to use the default
	2p2 version.  For m-ext, we do not set the version by -march and ELF arch
	attribute, so set the default 2p0 to it.  For zicsr, it is not defined in
	ISA spec 2p2, so set 0p0 to it.
	* testsuite/gas/riscv/attribute-10.d: New testcase.  The version of
	zicsr is 2p0 according to ISA spec 20191213.
	* config/tc-riscv.c (DEFAULT_RISCV_ARCH_WITH_EXT)
	(DEFAULT_RISCV_ISA_SPEC): Default configure option settings.
	You can set them by configure options --with-arch and
	--with-isa-spec, respectively.
	(riscv_set_default_isa_spec): New function used to set the
	default ISA spec.
	(md_parse_option): Call riscv_set_default_isa_spec rather than
	call riscv_get_isa_spec_class directly.
	(riscv_after_parse_args): If the -isa-spec is not set, then we
	set the default ISA spec according to DEFAULT_RISCV_ISA_SPEC by
	calling riscv_set_default_isa_spec.
	* testsuite/gas/riscv/attribute-01.d: Add -misa-spec=2.2, since
	the --with-isa-spec may be set to different ISA spec.
	* testsuite/gas/riscv/attribute-02.d: Likewise.
	* testsuite/gas/riscv/attribute-03.d: Likewise.
	* testsuite/gas/riscv/attribute-04.d: Likewise.
	* testsuite/gas/riscv/attribute-05.d: Likewise.
	* testsuite/gas/riscv/attribute-06.d: Likewise.
	* testsuite/gas/riscv/attribute-07.d: Likewise.
	* configure.ac: Add configure options, --with-arch and
	--with-isa-spec.
	* configure: Regenerated.
	* config.in: Regenerated.
	* config/tc-riscv.c (default_priv_spec): Static variable which is
	used to check if the CSR is valid for the chosen privilege spec. You
	can use -mpriv-spec to set it.
	(enum reg_class): We now get the CSR address from csr_extra_hash rather
	than reg_names_hash.  Therefore, move RCLASS_CSR behind RCLASS_MAX.
	(riscv_init_csr_hashes): Only need to initialize one hash table
	csr_extra_hash.
	(riscv_csr_class_check): Change the return type to void.  Don't check
	the ISA dependency if -mcsr-check isn't set.
	(riscv_csr_version_check): New function.  Check and find the CSR address
	from csr_extra_hash, according to default_priv_spec.  Report warning
	for the invalid CSR if -mcsr-check is set.
	(reg_csr_lookup_internal): Updated.
	(reg_lookup_internal): Likewise.
	(md_begin): Updated since DECLARE_CSR and DECLARE_CSR_ALIAS are changed.
	(enum options, struct option md_longopts): Add new GAS option -mpriv-spec.
	(md_parse_option): Call riscv_set_default_priv_version to set
	default_priv_spec.
	(riscv_after_parse_args): If -mpriv-spec isn't set, then set the default
	privilege spec to the newest one.
	(enum riscv_csr_class, struct riscv_csr_extra): Move them to
	include/opcode/riscv.h.
	* testsuite/gas/riscv/priv-reg-fail-fext.d: This test case just want
	to check the ISA dependency for CSR, so fix the spec version by adding
	-mpriv-spec=1.11.
	* testsuite/gas/riscv/priv-reg-fail-fext.l: Likewise.  There are some
	version warnings for the test case.
	* gas/testsuite/gas/riscv/priv-reg-fail-read-only-01.d: Likewise.
	* gas/testsuite/gas/riscv/priv-reg-fail-read-only-01.l: Likewise.
	* gas/testsuite/gas/riscv/priv-reg-fail-read-only-02.d: Likewise.
	* gas/testsuite/gas/riscv/priv-reg-fail-rv32-only.d: Likewise.
	* gas/testsuite/gas/riscv/priv-reg-fail-rv32-only.l: Likewise.
	* gas/testsuite/gas/riscv/priv-reg-fail-version-1p9.d: New test case.
	Check whether the CSR is valid when privilege version 1.9 is choosed.
	* gas/testsuite/gas/riscv/priv-reg-fail-version-1p9.l: Likewise.
	* gas/testsuite/gas/riscv/priv-reg-fail-version-1p9p1.d: New test case.
	Check whether the CSR is valid when privilege version 1.9.1 is choosed.
	* gas/testsuite/gas/riscv/priv-reg-fail-version-1p9p1.l: Likewise.
	* gas/testsuite/gas/riscv/priv-reg-fail-version-1p10.d: New test case.
	Check whether the CSR is valid when privilege version 1.10 is choosed.
	* gas/testsuite/gas/riscv/priv-reg-fail-version-1p10.l: Likewise.
	* gas/testsuite/gas/riscv/priv-reg-fail-version-1p11.d: New test case.
	Check whether the CSR is valid when privilege version 1.11 is choosed.
	* gas/testsuite/gas/riscv/priv-reg-fail-version-1p11.l: Likewise.
	* config/tc-riscv.c (DEFAULT_RISCV_ISA_SPEC): Default configure option
	setting.  You can set it by configure option --with-priv-spec.
	(riscv_set_default_priv_spec): New function used to set the default
	privilege spec.
	(md_parse_option): Call riscv_set_default_priv_spec rather than
	call riscv_get_priv_spec_class directly.
	(riscv_after_parse_args): If -mpriv-spec isn't set, then we set the
	default privilege spec according to DEFAULT_RISCV_PRIV_SPEC by
	calling riscv_set_default_priv_spec.
	* testsuite/gas/riscv/csr-dw-regnums.d: Add -mpriv-spec=1.11, since
	the --with-priv-spec may be set to different privilege spec.
	* testsuite/gas/riscv/priv-reg.d: Likewise.
	* configure.ac: Add configure option --with-priv-spec.
	* configure: Regenerated.
	* config.in: Regenerated.
	* config/tc-riscv.c (explicit_attr): Rename explicit_arch_attr to
	explicit_attr.  Set it to TRUE if any ELF attribute is found.
	(riscv_set_default_priv_spec): Try to set the default_priv_spec if
	the priv attributes are set.
	(md_assemble): Set the default_priv_spec according to the priv
	attributes when we start to assemble instruction.
	(riscv_write_out_attrs): Rename riscv_write_out_arch_attr to
	riscv_write_out_attrs.  Update the arch and priv attributes.  If we
	don't set the corresponding ELF attributes, then try to output the
	default ones.
	(riscv_set_public_attributes): If any ELF attribute or -march-attr
	options is set (explicit_attr is TRUE), then call riscv_write_out_attrs
	to update the arch and priv attributes.
	(s_riscv_attribute): Make sure all arch and priv attributes are set
	before any instruction.
	* testsuite/gas/riscv/attribute-01.d: Update the priv attributes if any
	ELF attribute or -march-attr is set.  If the priv attributes are not
	set, then try to update them by the default setting (-mpriv-spec or
	--with-priv-spec).
	* testsuite/gas/riscv/attribute-02.d: Likewise.
	* testsuite/gas/riscv/attribute-03.d: Likewise.
	* testsuite/gas/riscv/attribute-04.d: Likewise.
	* testsuite/gas/riscv/attribute-06.d: Likewise.
	* testsuite/gas/riscv/attribute-07.d: Likewise.
	* testsuite/gas/riscv/attribute-08.d: Likewise.
	* testsuite/gas/riscv/attribute-09.d: Likewise.
	* testsuite/gas/riscv/attribute-10.d: Likewise.
	* testsuite/gas/riscv/attribute-unknown.d: Likewise.
	* testsuite/gas/riscv/attribute-05.d: Likewise.  Also, the priv spec
	set by priv attributes must be supported.
	* testsuite/gas/riscv/attribute-05.s: Likewise.
	* testsuite/gas/riscv/priv-reg-fail-version-1p9.d: Likewise.  Updated
	priv attributes according to the -mpriv-spec option.
	* testsuite/gas/riscv/priv-reg-fail-version-1p9p1.d: Likewise.
	* testsuite/gas/riscv/priv-reg-fail-version-1p10.d: Likewise.
	* testsuite/gas/riscv/priv-reg-fail-version-1p11.d: Likewise.
	* testsuite/gas/riscv/priv-reg.d: Removed.
	* testsuite/gas/riscv/priv-reg-version-1p9.d: New test case.  Dump the
	CSR according to the priv spec 1.9.
	* testsuite/gas/riscv/priv-reg-version-1p9p1.d: New test case.  Dump the
	CSR according to the priv spec 1.9.1.
	* testsuite/gas/riscv/priv-reg-version-1p10.d: New test case.  Dump the
	CSR according to the priv spec 1.10.
	* testsuite/gas/riscv/priv-reg-version-1p11.d: New test case.  Dump the
	CSR according to the priv spec 1.11.
	* config/tc-riscv.c (md_show_usage): Add descriptions about
	the new GAS options.
	* doc/c-riscv.texi: Likewise.
2020-05-20 17:22:48 +01:00
Peter Bergner
3d205eb448 Power10 dcbf, sync, and wait extensions.
opcodes/
	* ppc-opc.c (insert_ls, extract_ls): Handle 3-bit L fields and new
	WC values on POWER10 sync, dcbf  and wait instructions.
	(insert_pl, extract_pl): New functions.
	(L2OPT, LS, WC): Use insert_ls and extract_ls.
	(LS3): New , 3-bit L for sync.
	(LS3, L3OPT): New, 3-bit L for sync and dcbf.
	(SC2, PL): New, 2-bit SC and PL for sync and wait.
	(XWCPL_MASK, XL3RT_MASK, XSYNCLS_MASK): New instruction masks.
	(XOPL3, XWCPL, XSYNCLS): New opcode macros.
	(powerpc_opcodes) <dcbflp, dcbfps, dcbstps pause_short, phwsync,
	plwsync, stcisync, stncisync, stsync, waitrsv>: New extended mnemonics.
	<wait>: Enable PL operand on POWER10.
	<dcbf>: Enable L3OPT operand on POWER10.
	<sync>: Enable SC2 operand on POWER10.

gas/
	* testsuite/gas/ppc/power9.s <dcbf, dcbfl, dcbflp>: Add tests.
	* testsuite/gas/ppc/power9.d: Likewise.
	* testsuite/gas/ppc/power10.s <dcbf, dcbfps, dcbstps, hwsync, lwsync,
	pause_short, phwsync, plwsync, ptesync, stcisync, stncisync, stsync,
	sync, wait, waitrsv>: Add tests.
	* testsuite/gas/ppc/power10.d: Likewise.
2020-05-19 18:09:51 -05:00
Alexander Fedotov
164446e04c Fix the ARM assembler to generate a Realtime profile for armv8-r.
PR 25992
gas	* config/tc-arm.c : Add arm_ext_v8r feature.
	(it_fsm_post_encode): Check arm_ext_v8r feature.
	(get_aeabi_cpu_arch_from_fset): Check arm_ext_v8r feature.

include	* opcode/arm.h (ARM_EXT2_V8R): Define. Modified ARM_AEXT2_V8R.
2020-05-19 12:45:42 +01:00
liuhongt
503648e41e Don't handle lret/iret when -mlfence-before-ret=[or|not|shl|yes] since they are invalid in SGX enclaves.
gas/ChangeLog
	* gas/config/tc-i386.c: Not handle lret/iret.
	* gas/testsuite/gas/i386/lfence-ret-a.d: Adjust testcase.
	* gas/testsuite/gas/i386/lfence-ret-b.d: Ditto.
	* gas/testsuite/gas/i386/lfence-ret-c.d: Ditto.
	* gas/testsuite/gas/i386/lfence-ret-d.d: Ditto.
	* gas/testsuite/gas/i386/lfence-ret.s: Ditto.
	* gas/testsuite/gas/i386/x86-64-lfence-ret-a.d: Ditto.
	* gas/testsuite/gas/i386/x86-64-lfence-ret-b.d: Ditto.
	* gas/testsuite/gas/i386/x86-64-lfence-ret-c.d: Ditto.
	* gas/testsuite/gas/i386/x86-64-lfence-ret-d.d: Ditto.
	* gas/testsuite/gas/i386/x86-64-lfence-ret-e.d: Ditto.
	* gas/testsuite/gas/i386/x86-64-lfence-ret.s: Ditto.
	* gas/testsuite/gas/i386/x86-64-lfence-ret.e: Deleted.
2020-05-18 10:23:59 +08:00
Alan Modra
2a50b40146 Fix tight loop on recursively-defined symbols
This patch fixes a bug in GAS where the assembler enters a tight loop
when attempting to resolve recursively-defined symbols, e.g. when
trying to assemble "a=a".

This is a regression introduced between binutils 2.32 and 2.33,
by commit 1903f1385b

	* symbols.c (struct local_symbol): Update comment.
	(resolve_symbol_value): For resolved symbols equated to other
	symbols, verify that the referenced symbol is not a local_symbol
	before accessing sy_value.  Don't leave symbol loops during
	finalize_syms resolution.
	* testsuite/gas/all/assign-bad-recursive.d: New test.
	* testsuite/gas/all/assign-bad-recursive.l: Error output for test.
	* testsuite/gas/all/assign-bad-recursive.s: Assembly for test.
	* testsuite/gas/all/gas.exp: Run it.
2020-05-15 18:21:07 +09:30
Alan Modra
3b646889b0 Power10 VSX scalar min-max-compare quad precision operations
opcodes/
	* ppc-opc (powerpc_opcodes): Add xscmpeqqp, xscmpgeqp, xscmpgtqp,
	xsmaxcqp, xsmincqp.
gas/
	* testsuite/gas/ppc/scalarquad.d,
	* testsuite/gas/ppc/scalarquad.s: New test.
	* testsuite/gas/ppc/ppc.exp: Run it.
2020-05-11 21:08:38 +09:30
Alan Modra
9cc4ce8831 Power10 VSX load/store rightmost element operations
opcodes/
	* ppc-opc.c (powerpc_opcodes): Add lxvrbx, lxvrhx, lxvrwx, lxvrdx,
	stxvrbx, stxvrhx, stxvrwx, stxvrdx.
gas/
	* testsuite/gas/ppc/rightmost.d,
	* testsuite/gas/ppc/rightmost.s: New test.
	* testsuite/gas/ppc/ppc.exp: Run it.
2020-05-11 21:08:37 +09:30
Alan Modra
5d57bc3ff9 Power10 test lsb by byte operation
opcodes/
	* ppc-opc.c (powerpc_opcodes): Add xvtlsbb.
gas/
	* testsuite/gas/ppc/xvtlsbb.d,
	* testsuite/gas/ppc/xvtlsbb.s: New test.
	* testsuite/gas/ppc/ppc.exp: Run it.
2020-05-11 21:08:37 +09:30
Alan Modra
66ef5847c3 Power10 string operations
opcodes/
	* ppc-opc.c (powerpc_opcodes): Add vstribl, vstribr, vstrihl, vstrihr,
	vclrlb, vclrrb, vstribl., vstribr., vstrihl., vstrihr..
gas/
	* testsuite/gas/ppc/stringop.d,
	* testsuite/gas/ppc/stringop.s: New test.
	* testsuite/gas/ppc/ppc.exp: Run it.
2020-05-11 21:08:37 +09:30
Peter Bergner
4f3e9537c4 Power10 Set boolean extension
opcodes/
	* ppc-opc.c (powerpc_opcodes) <setbc, setbcr, setnbc, setnbcr>: New
	mnemonics.
gas/
	* testsuite/gas/ppc/set_bool.d,
	* testsuite/gas/ppc/set_bool.s: New test.
	* testsuite/gas/ppc/ppc.exp: Run it.
2020-05-11 21:08:37 +09:30
Alan Modra
ec40e91c77 Power10 bit manipulation operations
opcodes/
	* ppc-opc.c (UIM8, P_U8XX4_MASK): Define.
	(powerpc_opcodes): Add vgnb, vcfuged, vpextd, vpdepd, vclzdm,
	vctzdm, cntlzdm, pdepd, pextd, cfuged, cnttzdm.
	(prefix_opcodes): Add xxeval.
gas/
	* testsuite/gas/ppc/bitmanip.d,
	* testsuite/gas/ppc/bitmanip.s: New test.
	* testsuite/gas/ppc/ppc.exp: Run it.
2020-05-11 21:08:37 +09:30
Alan Modra
d7e97a765e Power10 VSX PCV generate operations
opcodes/
	* ppc-opc.c (powerpc_opcodes): Add xxgenpcvbm, xxgenpcvhm,
	xxgenpcvwm, xxgenpcvdm.
gas/
	* testsuite/gas/ppc/genpcv.d,
	* testsuite/gas/ppc/genpcv.s: New test.
	* testsuite/gas/ppc/ppc.exp: Run it.
2020-05-11 21:08:37 +09:30
Alan Modra
fdefed7c26 Power10 VSX Mask Manipulation Operations
opcodes/
	* ppc-opc.c (MP, VXVAM_MASK): Define.
	(VXVAPS_MASK): Use VXVA_MASK.
	(powerpc_opcodes): Add mtvsrbmi, vexpandbm, vexpandhm, vexpandwm,
	vexpanddm, vexpandqm, vextractbm, vextracthm, vextractwm,
	vextractdm, vextractqm, mtvsrbm, mtvsrhm, mtvsrwm, mtvsrdm, mtvsrqm,
	vcntmbb, vcntmbh, vcntmbw, vcntmbd.
gas/
	* testsuite/gas/ppc/maskmanip.d,
	* testsuite/gas/ppc/maskmanip.s: New test.
	* testsuite/gas/ppc/ppc.exp: Run it.
2020-05-11 21:08:37 +09:30
Alan Modra
aa3c112fab Power10 Reduced precision outer product operations
include/
	* opcode/ppc.h (PPC_OPERAND_ACC): Define.  Renumber following
	PPC_OPERAND defines.
opcodes/
	* ppc-opc.c (insert_xa6a, extract_xa6a, insert_xb6a, extract_xb6a):
	New functions.
	(powerpc_operands): Define ACC, PMSK8, PMSK4, PMSK2, XMSK, YMSK,
	YMSK2, XA6a, XA6ap, XB6a entries.
	(PMMIRR, P_X_MASK, P_XX1_MASK, P_GER_MASK): Define
	(P_GER2_MASK, P_GER4_MASK, P_GER8_MASK, P_GER64_MASK): Define.
	(PPCVSX4): Define.
	(powerpc_opcodes): Add xxmfacc, xxmtacc, xxsetaccz,
	xvi8ger4pp, xvi8ger4, xvf16ger2pp, xvf16ger2, xvf32gerpp, xvf32ger,
	xvi4ger8pp, xvi4ger8, xvi16ger2spp, xvi16ger2s, xvbf16ger2pp,
	xvbf16ger2, xvf64gerpp, xvf64ger, xvi16ger2, xvf16ger2np,
	xvf32gernp, xvi8ger4spp, xvi16ger2pp, xvbf16ger2np, xvf64gernp,
	xvf16ger2pn, xvf32gerpn, xvbf16ger2pn, xvf64gerpn, xvf16ger2nn,
	xvf32gernn, xvbf16ger2nn, xvf64gernn, xvcvbf16sp, xvcvspbf16.
	(prefix_opcodes): Add pmxvi8ger4pp, pmxvi8ger4, pmxvf16ger2pp,
	pmxvf16ger2, pmxvf32gerpp, pmxvf32ger, pmxvi4ger8pp, pmxvi4ger8,
	pmxvi16ger2spp, pmxvi16ger2s, pmxvbf16ger2pp, pmxvbf16ger2,
	pmxvf64gerpp, pmxvf64ger, pmxvi16ger2, pmxvf16ger2np, pmxvf32gernp,
	pmxvi8ger4spp, pmxvi16ger2pp, pmxvbf16ger2np, pmxvf64gernp,
	pmxvf16ger2pn, pmxvf32gerpn, pmxvbf16ger2pn, pmxvf64gerpn,
	pmxvf16ger2nn, pmxvf32gernn, pmxvbf16ger2nn, pmxvf64gernn.
gas/
	* config/tc-ppc.c (pre_defined_registers): Add accumulators.
	(md_assemble): Check acc specified in correct operand.
	* testsuite/gas/ppc/outerprod.d,
	* testsuite/gas/ppc/outerprod.s,
	* testsuite/gas/ppc/vsx4.d,
	* testsuite/gas/ppc/vsx4.s: New tests.
	* testsuite/gas/ppc/ppc.exp: Run them.
2020-05-11 21:08:37 +09:30
Alan Modra
6edbfd3beb Power10 SIMD permute class operations
opcodes/
	* ppc-opc.c (insert_imm32, extract_imm32): New functions.
	(insert_xts, extract_xts): New functions.
	(IMM32, UIM3, IX, UIM5, SH3, XTS, P8RR): Define.
	(P_XX4_MASK, P_UXX4_MASK, VSOP, P_VS_MASK, P_VSI_MASK): Define.
	(VXRC_MASK, VXSH_MASK): Define.
	(powerpc_opcodes): Add vinsbvlx, vsldbi, vextdubvlx, vextdubvrx,
	vextduhvlx, vextduhvrx, vextduwvlx, vextduwvrx, vextddvlx,
	vextddvrx, vinshvlx, vinswvlx, vinsw, vinsbvrx, vinshvrx,
	vinswvrx, vinsd, vinsblx, vsrdbi, vinshlx, vinswlx, vinsdlx,
	vinsbrx, vinshrx, vinswrx, vinsdrx, lxvkq.
	(prefix_opcodes): Add xxsplti32dx, xxspltidp, xxspltiw, xxblendvb,
	xxblendvh, xxblendvw, xxblendvd, xxpermx.
gas/
	* testsuite/gas/ppc/simd_perm.d,
	* testsuite/gas/ppc/simd_perm.s: New test.
	* testsuite/gas/ppc/ppc.exp: Run it.
2020-05-11 21:08:37 +09:30
Alan Modra
c7d7aea2f5 Power10 128-bit binary integer operations
opcodes/
	* ppc-opc.c (powerpc_opcodes): Add vrlq, vdivuq, vmsumcud, vrlqmi,
	vmuloud, vcmpuq, vslq, vdivsq, vcmpsq, vrlqnm, vcmpequq, vmulosd,
	vsrq, vdiveuq, vcmpgtuq, vmuleud, vsraq, vdivesq, vcmpgtsq, vmulesd,
	vcmpequq., vextsd2q, vmoduq, vcmpgtuq., vmodsq, vcmpgtsq., xscvqpuqz,
	xscvuqqp, xscvqpsqz, xscvsqqp, dcffixqq, dctfixqq.
gas/
	* testsuite/gas/ppc/int128.d,
	* testsuite/gas/ppc/int128.s: New test.
	* testsuite/gas/ppc/ppc.exp: Run it.
2020-05-11 21:08:37 +09:30
Alan Modra
94ba9882d5 Power10 VSX 32-byte storage access
bfd/
	* elf64-ppc.c (xlate_pcrel_opt): Handle lxvp and stxvp.
opcodes/
	* ppc-opc.c (insert_xtp, extract_xtp): New functions.
	(XTP, DQXP, DQXP_MASK): Define.
	(powerpc_opcodes): Add lxvp, stxvp, lxvpx, stxvpx.
	(prefix_opcodes): Add plxvp and pstxvp.
gas/
	* testsuite/gas/ppc/vsx_32byte.d,
	* testsuite/gas/ppc/vsx_32byte.s: New test.
	* testsuite/gas/ppc/ppc.exp: Run it.
ld/
	* testsuite/ld-powerpc/pcrelopt.s: Add lxvp and stxvp.
	* testsuite/ld-powerpc/pcrelopt.d: Update.
2020-05-11 21:08:37 +09:30
Alan Modra
f4791f1afa Power10 vector integer multiply, divide, modulo insns
opcodes/
	* ppc-opc.c (powerpc_opcodes): Add vdivuw, vdivud, vdivsw, vmulld,
	vdivsd, vmulhuw, vdiveuw, vmulhud, vdiveud, vmulhsw, vdivesw,
	vmulhsd, vdivesd, vmoduw, vmodud, vmodsw, vmodsd.
gas/
	* testsuite/gas/ppc/vec_mul.s,
	* testsuite/gas/ppc/vec_mul.d: New test.
	* testsuite/gas/ppc/ppc.exp: Run it.
2020-05-11 21:08:37 +09:30
Peter Bergner
3ff0a5ba64 Power10 byte reverse instructions
opcodes/
	* ppc-opc.c (powerpc_opcodes) <brd, brh, brw>: New mnemonics.
gas/
	* testsuite/gas/ppc/byte_rev.d,
	* testsuite/gas/ppc/byte_rev.s: New test.
	* testsuite/gas/ppc/ppc.exp: Run it.
2020-05-11 21:08:36 +09:30
Peter Bergner
afef4fe975 Power10 Copy/Paste Extensions
opcodes/
	* opcodes/ppc-opc.c (insert_l1opt, extract_l1opt): New functions.
	(L1OPT): Define.
	(powerpc_opcodes) <paste.>: Add L operand for cpu POWER10.
gas/
	* testsuite/gas/ppc/power10.d: Add paste. tests.
	* testsuite/gas/ppc/power10.s: Likewise.
2020-05-11 21:08:36 +09:30
Peter Bergner
1224c05de4 Power10 Add new L operand to the slbiag instruction
opcodes/
	* ppc-opc.c (powerpc_opcodes) <slbiag>: Add variant with L operand.
gas/
	* testsuite/gas/ppc/power10.s: New test.
	* testsuite/gas/ppc/power10.d: Likewise.
	* testsuite/gas/ppc/ppc.exp: Run it.
2020-05-11 21:08:36 +09:30
Alan Modra
7c1f422735 PowerPC Rename powerxx to power10
Now that ISA3.1 is out we can finish with the powerxx silliness.

bfd/
	* elf64-ppc.c: Rename powerxx to power10 throughout.
gas/
	* config/tc-ppc.c (md_assemble): Update for PPC_OPCODE_POWER10
	renaming.
	* testsuite/gas/ppc/prefix-align.d: Use -mpower10/-Mpower10 in
	place of -mfuture/-Mfuture.
	* testsuite/gas/ppc/prefix-pcrel.d: Likewise.
	* testsuite/gas/ppc/prefix-reloc.d: Likewise.
gold/
	* powerpc.cc: Rename powerxx to power10 throughout.
include/
	* elf/ppc64.h: Update comment.
	* opcode/ppc.h (PPC_OPCODE_POWER10): Rename from PPC_OPCODE_POWERXX.
ld/
	* testsuite/ld-powerpc/callstub-1.d: Use -mpower10/-Mpower10 in
	place of -mfuture/-Mfuture.
	* testsuite/ld-powerpc/notoc2.d: Likewise.
	* testsuite/ld-powerpc/powerpc.exp: Likewise.
	* testsuite/ld-powerpc/tlsgd.d: Likewise.
	* testsuite/ld-powerpc/tlsie.d: Likewise.
	* testsuite/ld-powerpc/tlsld.d: Likewise.
opcodes/
	* ppc-dis.c (ppc_opts): Add "power10" entry.
	(print_insn_powerpc): Update for PPC_OPCODE_POWER10 renaming.
	* ppc-opc.c (POWER10): Rename from POWERXX.  Update all uses.
2020-05-11 21:08:36 +09:30
Nick Clifton
546cb2d85e Restore readelf's warnings that describe real problems with the file being examined. Fix bug displaying empty file name tables.
binutils* dwarf.c (do_checks): New global variable.
	(display_formatted_table): Warn about an unexpected number of
	columns in the table, if checks are enabled.  Do not complain
	about the lack of data following the number of entries in the
	table if the table is empty.
	(display_debug_lines_decoded): Only warn about an unexpected
	number of columns in a table if checks are enabled.
	* dwarf.h (do_checks): Add a prototype.
	* elfcomm.c (error): Remove weak attribute.
	(warn): Likewise.
	* readelf.c (do_checks): Delete.
	(warn): Delete.
	(process_section_headers): Only warn about empty sections if
	checks are enabled.

gas	* dwarf2dbg.c (out_dir_and_file_list): Add comments describing the
	construction of a DWARF-5 directory name table.
	* testsuite/gas/elf/pr25917.d: Update expected output.
2020-05-05 16:16:03 +01:00
Andre Simoes Dias Vieira
fe05f369f0 gas: PR 25863: Fix scalar vmul inside it block when assembling for MVE
This fixes PR 25863 by fixing the condition in the parsing of vmul in
do_mve_vmull.  It also simplifies the code in there fixing latent issues that
would lead to NEON code being accepted when it shouldn't.

gas/ChangeLog:
2020-05-04  Andre Vieira  <andre.simoesdiasvieira@arm.com>

	PR gas/25863
	* config/tc-arm.c (do_mve_vmull): Fix scalar and NEON parsing of vmul.
	* testsuite/gas/arm/mve-scalar-vmult-it.d: New test.
	* testsuite/gas/arm/mve-scalar-vmult-it.s: New test.
2020-05-04 13:07:45 +01:00
Nick Clifton
4706679dac Fix an illegal memory access in the assembler when generating a DWARF5 file/directory table with no entries.
PR 25917
	* dwarf2dbg.c (out_dir_and_file_list): Check for the directory
	table's existence before looking at its entries.
	* testsuite/gas/elf/pr25917.s: New test source file.
	* testsuite/gas/elf/pr25917.d: New test driver.
	* testsuite/gas/elf/elf.exp (run_elf_list_test): Run the new test.
2020-05-04 10:19:38 +01:00
Alex Coplan
09c1e68a16 AArch64: add GAS support for UDF instruction
binutils * testsuite/binutils-all/aarch64/in-order-all.d: Update to use new
          disassembly.
        * testsuite/binutils-all/aarch64/out-of-order-all.d: Likewise.

ld/     * testsuite/ld-aarch64/erratum843419_tls_ie.d: Use udf in disassembly.
        * testsuite/ld-aarch64/farcall-b-section.d: Likewise.
        * testsuite/ld-aarch64/farcall-back.d: Likewise.
        * testsuite/ld-aarch64/farcall-bl-section.d: Likewise.

gas/   * config/tc-aarch64.c (fix_insn): Implement for AARCH64_OPND_UNDEFINED.
          (parse_operands): Implement for AARCH64_OPND_UNDEFINED.
        * testsuite/gas/aarch64/udf.s: New.
        * testsuite/gas/aarch64/udf.d: New.
        * testsuite/gas/aarch64/udf-invalid.s: New.
        * testsuite/gas/aarch64/udf-invalid.l: New.
        * testsuite/gas/aarch64/udf-invalid.d: New.

include * opcode/aarch64.h (enum aarch64_opnd): Add AARCH64_OPND_UNDEFINED.

opcodes * aarch64-opc.h (enum aarch64_field_kind): Add FLD_imm16_2.
        * aarch64-opc.c (fields): Add entry for FLD_imm16_2.
          (operand_general_constraint_met_p): validate AARCH64_OPND_UNDEFINED.
        * aarch64-tbl.h (aarch64_opcode_table): Add udf instruction, entry for
          FLD_imm16_2.
        * aarch64-asm-2.c: Regenerated.
        * aarch64-dis-2.c: Regenerated.
        * aarch64-opc-2.c: Regenerated.
2020-04-30 15:47:30 +01:00
Nick Clifton
241e541d00 Update expected disassembly after recent update.
PR 22699
	* testsuite/gas/sh/sh4al-dsp.d: Update expected disassembly.
2020-04-29 17:18:56 +01:00
Nick Clifton
5c936ef50f Fix the disassmbly of SH instructions which have an unsigned 8-bit immediate operand.
PR 22699
opcodes	* sh-opc.h (IMM0_8): Replace with IMM0_8S and IMM0_8U.  Use
	IMM0_8S for arithmetic insns and IMM0_8U for logical insns.
	* sh-dis.c (print_insn_sh): Change IMM0_8 case to IMM0_8S and add
	IMM0_8U case.

gas	* config/tc-sh.c (build_Mytes): Change operand type IMM0_8 to
	IMM0_8S and add support for IMM0_8U.
	* testsuite/gas/sh/sh4a.s: Add test of a logical insn using an
	unsigned 8-bit immediate.
	* testsuite/gas/sh/sh4a.d: Extended expected disassembly.
2020-04-29 13:13:55 +01:00
Tamar Christina
251dae9107 x86: Add i386 PE big-object support
The 64-bit version of binutils got support for the PE COFF BIG OBJ format a
couple of years ago.   The BIG OBJ format is a slightly different COFF format
which extends the size of the number of section field in the header from a
uint16_t to a uint32_t and so greatly increases the number of sections allowed.

However the 32-bit version of bfd never got support for this.  The GHC Haskell
compiler generates a great deal of symbols due to it's use of
-ffunction-sections and -fdata-sections.

This meant that we could not build the 32-bit version of the GHC Compiler for
many releases now as binutils didn't have this support.

This patch adds the support to the 32-bit port of binutils as well and also does
come cleanup in the code.

bfd/ChangeLog:

	* coff-i386.c (COFF_WITH_PE_BIGOBJ): New.
	* coff-x86_64.c (COFF_WITH_PE_BIGOBJ): New.
	* config.bfd (targ_selvecs): Rename x86_64_pe_be_vec
	to x86_64_pe_big_vec as it not a big-endian format.
	(vec i386_pe_big_vec): New.
	* configure.ac: Likewise.
	* targets.c: Likewise.
	* configure: Regenerate.
	* pe-i386.c (TARGET_SYM_BIG, TARGET_NAME_BIG,
	COFF_WITH_PE_BIGOBJ): New.
	* pe-x86_64.c (TARGET_SYM_BIG, TARGET_NAME_BIG):
	New.
	(x86_64_pe_be_vec): Moved.

gas/ChangeLog:

	* NEWS: Add news entry for big-obj.
	* config/tc-i386.c (i386_target_format): Support new format.
	* doc/c-i386.texi: Add i386 support.
	* testsuite/gas/pe/big-obj.d: Rename test to not be x64 specific.
	* testsuite/gas/pe/pe.exp (big-obj): Make test run on i386 as well.

ld/ChangeLog:

	* pe-dll.c (pe_detail_list):  Add pe-bigobj-i386.
2020-04-27 17:41:39 +01:00
liuhongt
a09f656b26 Improve -mlfence-after-load
1.Implict load for POP/POPF/POPA/XLATB, no load for Anysize insns
  2. Add -mlfence-before-ret=shl/yes, adjust operand size of
  or/not/shl according to ret's.
  3. Issue warning for REP CMPS/SCAS since they would affect control
  flow behavior.
  4. Adjust testcases and documents.

gas/Changelog:
	* config/tc-i386.c (lfence_before_ret_shl): New member.
	(load_insn_p): implict load for POP/POPA/POPF/XLATB, no load
	for Anysize insns.
	(insert_after_load): Issue warning for REP CMPS/SCAS.
	(insert_before_before): Handle iret, Handle
	-mlfence-before-ret=shl, Adjust operand size of or/not/shl to ret's,
	(md_parse_option): Change -mlfence-before-ret=[none|not|or] to
	-mlfence-before-ret=[none/not/or/shl/yes].
	Enable -mlfence-before-ret=shl when
	-mlfence-beofre-indirect-branch=all and no explict -mlfence-before-ret option.
	(md_show_usage): Ditto.
	* doc/c-i386.texi: Ditto.
	* testsuite/gas/i386/i386.exp: Add new testcases.
	* testsuite/gas/i386/lfence-load-b.d: New.
	* testsuite/gas/i386/lfence-load-b.e: New.
	* testsuite/gas/i386/lfence-load.d: Modified.
	* testsuite/gas/i386/lfence-load.e: New.
	* testsuite/gas/i386/lfence-load.s: Modified.
	* testsuite/gas/i386/lfence-ret-a.d: Modified.
	* testsuite/gas/i386/lfence-ret-b.d: Modified.
	* testsuite/gas/i386/lfence-ret-c.d: New.
	* testsuite/gas/i386/lfence-ret-d.d: New.
	* testsuite/gas/i386/lfence-ret.s: Modified.
	* testsuite/gas/i386/x86-64-lfence-load-b.d: New.
	* testsuite/gas/i386/x86-64-lfence-load.d: Modified.
	* testsuite/gas/i386/x86-64-lfence-load.s: Modified.
	* testsuite/gas/i386/x86-64-lfence-ret-a.d: Modified.
	* testsuite/gas/i386/x86-64-lfence-ret-b.d: Modified.
	* testsuite/gas/i386/x86-64-lfence-ret-c.d: New.
	* testsuite/gas/i386/x86-64-lfence-ret-d.d: New
	* testsuite/gas/i386/x86-64-lfence-ret-e.d: New.
	* testsuite/gas/i386/x86-64-lfence-ret.e: New.
	* testsuite/gas/i386/x86-64-lfence-ret.s: New.
2020-04-26 14:26:24 +08:00
Max Filippov
30ce8e47fa xtensa: fix PR ld/25861
Introduce new relaxations XTENSA_PDIFF{8,16,32} for positive differences
(subtracted symbol precedes diminished symbol) and XTENSA_NDIFF{8,16,32}
for negative differences (subtracted symbol follows diminished symbol).
Don't generate XTENSA_DIFF relocations in the assembler, generate
XTENSA_PDIFF or XTENSA_NDIFF based on relative symbol position.

Handle XTENSA_DIFF in BFD for compatibility with old object files.
Handle XTENSA_PDIFF and XTENSA_NDIFF in BFD, treating difference value
as unsigned.

2020-04-22  Max Filippov  <jcmvbkbc@gmail.com>
bfd/
	* bfd-in2.h: Regenerated.
	* elf32-xtensa.c (elf_howto_table): New entries for
	R_XTENSA_PDIFF{8,16,32} and R_XTENSA_NDIFF{8,16,32}.
	(elf_xtensa_reloc_type_lookup, elf_xtensa_do_reloc)
	(relax_section): Add cases for R_XTENSA_PDIFF{8,16,32} and
	R_XTENSA_NDIFF{8,16,32}.
	* libbfd.h (bfd_reloc_code_real_names): Add names for
	BFD_RELOC_XTENSA_PDIFF{8,16,32} and
	BFD_RELOC_XTENSA_NDIFF{8,16,32}.
	* reloc.c: Add documentation for BFD_RELOC_XTENSA_PDIFF{8,16,32}
	and BFD_RELOC_XTENSA_NDIFF{8,16,32}.

binutils/
	* readelf.c (is_none_reloc): Recognize
	BFD_RELOC_XTENSA_PDIFF{8,16,32} and
	BFD_RELOC_XTENSA_NDIFF{8,16,32}.

gas/
	* config/tc-xtensa.c (md_apply_fix): Replace
	BFD_RELOC_XTENSA_DIFF{8,16,32} generation with
	BFD_RELOC_XTENSA_PDIFF{8,16,32} and
	BFD_RELOC_XTENSA_NDIFF{8,16,32} generation.
	* testsuite/gas/xtensa/loc.d: Replace BFD_RELOC_XTENSA_DIFF16
	with BFD_RELOC_XTENSA_PDIFF16 in the expected output.

include/
	* elf/xtensa.h (elf_xtensa_reloc_type): New entries for
	R_XTENSA_PDIFF{8,16,32} and R_XTENSA_NDIFF{8,16,32}.

ld/
	* testsuite/ld-xtensa/relax-loc.d: New test definition.
	* testsuite/ld-xtensa/relax-loc.s: New test source.
	* testsuite/ld-xtensa/xtensa.exp (relax-loc): New test.
2020-04-22 18:46:45 -07:00
Alan Modra
31c89d6038 .symver fixes
* config/obj-elf.c (elf_frob_symbol): Unconditionally remove
	symbol for ".symver .. remove".
	* doc/as.texi (.symver): Update.
	* testsuite/gas/symver/symver11.s: Make foo weak.
	* testsuite/gas/symver/symver11.d: Expect an error.
	* testsuite/gas/symver/symver7.d: Allow other random symbols.
2020-04-22 22:24:03 +09:30
H.J. Lu
1d3eb55695 symver11.s: Add ".balign 8"
Add ".balign 8" to avoid

symver11.s:9: Error: misaligned data

for sh targets.

	* testsuite/gas/symver/symver11.s: Add ".balign 8".
2020-04-21 18:21:56 -07:00
Andreas Schwab
bb2a145347 Disallow PC relative for CMPI on MC68000/10
The MC68000/10 decodes the second operand of CMPI strictly as destination
operand, which disallows PC relative addressing, even though the insn
doesn't write to the operand.  This restriction has only been lifted for
the MC68020+ and CPU32.

opcodes:
	PR 25848
	* m68k-opc.c (m68k_opcodes): Allow pc-rel for second operand of
	cmpi only on m68020up and cpu32.

gas:
	PR 25848
	* testsuite/gas/m68k/operands.s: Add tests for cmpi.
	* testsuite/gas/m68k/operands.d: Update.
	* testsuite/gas/m68k/op68000.d: Update for new error messages.
2020-04-21 16:53:36 +02:00
Tamar Christina
c36876fe5b BFD: Exclude sections with no content from compress check.
The check in bfd_get_full_section_contents is trying to check that we don't
allocate more space for a section than the size of the section is on disk.

Previously we excluded linker created sections since they didn't have a size on
disk.  However we also need to exclude sections with no content as well such as
the BSS section.  Space for these would not have been allocated by the assembler
and so the check would incorrectly fail.

bfd/ChangeLog:

	PR binutils/24753
	* compress.c (bfd_get_full_section_contents): Exclude sections with no
	content.

gas/ChangeLog:

	PR binutils/24753
	* testsuite/gas/arm/pr24753.d: New test.
	* testsuite/gas/arm/pr24753.s: New test.
2020-04-21 15:17:18 +01:00
H.J. Lu
6914be53bd gas: Extend .symver directive
Extend .symver directive to update visibility of the original symbol and
assign one original symbol to different versioned symbols:

  .symver foo, foo@VERS_1, local    # Change foo to a local symbol.
  .symver foo, foo@VERS_2, hidden   # Change foo to a hidden symbol.
  .symver foo, foo@@VERS_3, remove  # Remove foo from symbol table.
  .symver foo, bar@V1               # Assign foo to bar@V1 and baz@V2.
  .symver foo, baz@V2

	PR gas/23840
	PR gas/25295
	* NEWS: Mention .symver extension.
	* config/obj-elf.c (obj_elf_find_and_add_versioned_name): New
	function.
	(obj_elf_symver): Call obj_elf_find_and_add_versioned_name to
	add a version name.  Add local, hidden and remove visibility
	support.
	(elf_frob_symbol): Handle the list of version names.  Update the
	original symbol to local, hidden or remove it from the symbol
	table.
	(elf_frob_file_before_adjust): Handle the list of version names.
	* config/obj-elf.h (elf_visibility): New.
	(elf_versioned_name_list): Likewise.
	(elf_obj_sy): Change local to bitfield. Add rename, bad_version
	and visibility.  Change versioned_name pointer to struct
	elf_versioned_name_list.
	* doc/as.texi: Update .symver directive.
	* testsuite/gas/symver/symver.exp: Run all *.d tests.  Add more
	error checking tests.
	* testsuite/gas/symver/symver6.d: New file.
	* testsuite/gas/symver/symver7.d: Likewise.
	* testsuite/gas/symver/symver7.s: Likewise.
	* testsuite/gas/symver/symver8.d: Likewise.
	* testsuite/gas/symver/symver8.s: Likewise.
	* testsuite/gas/symver/symver9.s: Likewise.
	* testsuite/gas/symver/symver9a.d: Likewise.
	* testsuite/gas/symver/symver9b.d: Likewise.
	* testsuite/gas/symver/symver10.s: Likewise.
	* testsuite/gas/symver/symver10a.d: Likewise.
	* testsuite/gas/symver/symver10b.d: Likewise.
	* testsuite/gas/symver/symver11.d: Likewise.
	* testsuite/gas/symver/symver11.s: Likewise.
	* testsuite/gas/symver/symver12.d: Likewise.
	* testsuite/gas/symver/symver12.s: Likewise.
	* testsuite/gas/symver/symver13.d: Likewise.
	* testsuite/gas/symver/symver13.s: Likewise.
	* testsuite/gas/symver/symver14.d: Likewise.
	* testsuite/gas/symver/symver14.l: Likewise.
	* testsuite/gas/symver/symver15.d: Likewise.
	* testsuite/gas/symver/symver15.l: Likewise.
	* testsuite/gas/symver/symver6.l: Removed.
	* testsuite/gas/symver/symver6.s: Updated.
2020-04-21 05:33:17 -07:00
Sudakshina Das
c2e5c986b3 [AArch64, Binutils] Add missing TSB instruction
This patch implements the TSB instructions:
https://developer.arm.com/docs/ddi0596/f/base-instructions-alphabetic-order/
tsb-csync-trace-synchronization-barrier
Since TSB and PSB both use the same (and only) argument "CSYNC", this patch
reuses it for TSB. However, the same argument would imply different value
for CRm:Op2 which are anyway fixed values, so I have diverted the
inserter/extracter function to dummy versions instead of the "hint" version.
The operand checker part still uses the existing infratructure for
AARCH64_OPND_BARRIER_PSB to make sure the operand is parsed correctly.

gas/ChangeLog:

2020-04-20  Sudakshina Das  <sudi.das@arm.com>

	* config/tc-aarch64.c (parse_barrier_psb): Update error messages
	to include TSB.
	* testsuite/gas/aarch64/system-2.d: Update -march and new tsb tests.
	* testsuite/gas/aarch64/system-2.s: Add new tsb tests.
	* testsuite/gas/aarch64/system.d: Update.

opcodes/ChangeLog:

2020-04-20  Sudakshina Das  <sudi.das@arm.com>

	* aarch64-asm.c (aarch64_ins_none): New.
	* aarch64-asm.h (ins_none): New declaration.
	* aarch64-dis.c (aarch64_ext_none): New.
	* aarch64-dis.h (ext_none): New declaration.
	* aarch64-opc.c (aarch64_print_operand): Update case for
	AARCH64_OPND_BARRIER_PSB.
	* aarch64-tbl.h (aarch64_opcode_table): Add tsb.
	(AARCH64_OPERANDS): Update inserter/extracter for
	AARCH64_OPND_BARRIER_PSB to use new dummy functions.
	* aarch64-asm-2.c: Regenerated.
	* aarch64-dis-2.c: Regenerated.
	* aarch64-opc-2.c: Regenerated.
2020-04-20 10:58:16 +01:00
Sudakshina Das
8a6e1d1d7f [AArch64, Binutils] Make hint space instructions valid for Armv8-a
There are a few instruction in AArch64 that are in the HINT space. Any of
these instructions should be accepted by the assembler/disassembler at any
architecture version. This patch fixes the existing instructions that are
not behaving accordingly.
I have used all of the instructions mentioned in the following to make the
changes:
https://developer.arm.com/docs/ddi0596/f/base-instructions-alphabetic-order/
hint-hint-instruction

gas/ChangeLog:

2020-04-20  Sudakshina Das  <sudi.das@arm.com>

	* testsuite/gas/aarch64/bti.d: Update -march option.
	* testsuite/gas/aarch64/illegal-bti.d: Remove.
	* testsuite/gas/aarch64/illegal-bti.l: Remove.
	* testsuite/gas/aarch64/illegal-ras-1.l: Remove esb.
	* testsuite/gas/aarch64/illegal-ras-1.s: Remove esb.

opcodes/ChangeLog:

2020-04-20  Sudakshina Das  <sudi.das@arm.com>

	* aarch64-tbl.h (aarch64_feature_bti, BTI, BTI_INSN): Remove.
	(aarch64_feature_ras, RAS): Likewise.
	(aarch64_feature_stat_profile, STAT_PROFILE): Likewise.
	(aarch64_opcode_table): Update bti, xpaclri, pacia1716, pacib1716,
	autia1716, autib1716, esb, psb, dgh, paciaz, paciasp, pacibz, pacibsp,
	autiaz, autiasp, autibz, autibsp to be CORE_INSN.
	* aarch64-asm-2.c: Regenerated.
	* aarch64-dis-2.c: Regenerated.
	* aarch64-opc-2.c: Regenerated.
2020-04-20 10:50:52 +01:00
Nick Clifton
8e4979ac1e Stop the MIPS assembler from accepting ifunc symbols.
PR 25803
gas	* config/obj-elf.c (obj_elf_type): Reject ifunc symbols on MIPS
	targets.
	* testsuite/gas/elf/elf.exp: Add MIPS targets to the list to skip
	for the type-2 test.
	* testsuite/gas/elf/type-noifunc.e: Update to allow for MIPS
	targets running this test.

bfd	* elfxx-mips.c (_bfd_mips_elf_adjust_dynamic_symbol): Replace an
	abort with a more helpful error message.
2020-04-16 18:02:10 +01:00
David Faust
c54a9b5669 cpu,gas,opcodes: support for eBPF JMP32 instruction class
Add support for the JMP32 class of eBPF instructions.

cpu/ChangeLog

	* bpf.cpu (define-cond-jump-insn): Renamed from djci.
	(dcji) New version with support for JMP32

gas/ChangeLog

	* testsuite/gas/bpf/bpf.exp: Run jump32 tests.
	* testsuite/gas/bpf/jump32.s: New file.
	* testsuite/gas/bpf/jump32.d: Likewise.

opcodes/ChangeLog

	* bpf-desc.c: Regenerate.
	* bpf-desc.h: Likewise.
	* bpf-opc.c: Regenerate.
	* bpf-opc.h: Likewise.
2020-04-16 09:52:57 +02:00
Cui,Lili
bb651e8b7f Add support for intel TSXLDTRK instructions$
gas/

	* config/tc-i386.c (cpu_arch): Add .TSXLDTRK.
	(cpu_noarch): Likewise.
	* doc/c-i386.texi: Document TSXLDTRK.
	* testsuite/gas/i386/i386.exp: Run TSXLDTRK tests.
	* testsuite/gas/i386/tsxldtrk.d: Likewise.
	* testsuite/gas/i386/tsxldtrk.s: Likewise.
	* testsuite/gas/i386/x86-64-tsxldtrk.d: Likewise.

opcodes/

	* i386-dis.c (enum): Add PREFIX_0F01_REG_5_MOD_3_RM_1,
	(prefix_table): New instructions (see prefixes above).
	(rm_table): Likewise.
	* i386-gen.c (cpu_flag_init): Add CPU_TSXLDTRK_FLAGS,
	CPU_ANY_TSXLDTRK_FLAGS.
	(cpu_flags): Add CpuTSXLDTRK.
	* i386-opc.h (enum): Add CpuTSXLDTRK.
	(i386_cpu_flags): Add cputsxldtrk.
	* i386-opc.tbl: Add XSUSPLDTRK insns.
	* i386-init.h: Regenerate.
	* i386-tbl.h: Likewise.
2020-04-07 13:59:50 +08:00
LiliCui
4b27d27c07 Add support for intel SERIALIZE instruction
gas/

	* config/tc-i386.c (cpu_arch): Add .serialize.
	(cpu_noarch): Likewise.
	* doc/c-i386.texi: Document serialize.
	* testsuite/gas/i386/i386.exp: Run serialize tests
	* testsuite/gas/i386/serialize.d: Likewise.
	* testsuite/gas/i386/x86-64-serialize.d: Likewise.
	* testsuite/gas/i386/serialize.s: Likewise.

opcodes/

	* i386-dis.c (prefix_table): New instructions serialize.
	* i386-gen.c (cpu_flag_init): Add CPU_SERIALIZE_FLAGS,
	CPU_ANY_SERIALIZE_FLAGS.
	(cpu_flags): Add CpuSERIALIZE.
	* i386-opc.h (enum): Add CpuSERIALIZE.
	(i386_cpu_flags): Add cpuserialize.
	* i386-opc.tbl: Add SERIALIZE insns.
	* i386-init.h: Regenerate.
	* i386-tbl.h: Likewise.
2020-04-02 05:48:36 -07:00
Rainer Orth
bb89747721 ld: Disable ifunc tests on Solaris
A couple of ld ifunc tests currently FAIL on 64-bit Solaris/x86:

FAIL: ld-ifunc/ifunc-10-x86-64
FAIL: ld-ifunc/ifunc-11-x86-64
FAIL: ld-ifunc/ifunc-12-x86-64
FAIL: ld-ifunc/ifunc-13-x86-64
FAIL: ld-ifunc/ifunc-14a-x86-64
FAIL: ld-ifunc/ifunc-14b-x86-64
FAIL: ld-ifunc/ifunc-14c-x86-64
FAIL: ld-ifunc/ifunc-14d-x86-64
FAIL: ld-ifunc/ifunc-14e-x86-64
FAIL: ld-ifunc/ifunc-14f-x86-64
FAIL: ld-ifunc/ifunc-15-x86-64
FAIL: ld-ifunc/ifunc-17a-x86-64
FAIL: ld-ifunc/ifunc-17b-x86-64
FAIL: ld-ifunc/ifunc-2-local-x86-64-now
FAIL: ld-ifunc/ifunc-2-local-x86-64
FAIL: ld-ifunc/ifunc-2-x86-64-now
FAIL: ld-ifunc/ifunc-2-x86-64
FAIL: ld-ifunc/ifunc-20-x86-64
FAIL: ld-ifunc/pr17154-x86-64-now
FAIL: ld-ifunc/pr17154-x86-64

For one, the actual error is weird:

./ld-new: target elf64-x86-64 not found
failed with: <./ld-new: target elf64-x86-64 not found>, no expected output
FAIL: ld-ifunc/ifunc-10-x86-64

although ld -V does report the elf_x86_64 emulation as supported:

$ ./ld/ld-new -V
GNU ld (GNU Binutils) 2.34.50.20200328
  Supported emulations:
   elf_x86_64_sol2
   elf_x86_64
[...]

When using ld -m elf_x86_64_sol2 instead, one of the testcases links
successfully.

However, there's no point in pursuing this: Solaris does not support
ifunc, as can be seen in <sys/elf.h>:

/*
 * GNU/Linux specific symbol type not used by Solaris
 */
#define STT_GNU_IFUNC   10

and never will, given that it has symbol capabilities as solution to
effectively the same problem:

http://www.linker-aliens.org/blogs/rie/entry/symbol_capabilitie/

Therefore this patch disables ifunc testing on Solaris completely by
removing Solaris from binutils/testsuite/lib/binutils-common.exp
(supports_gnu_osabi).  The ifunc part is justified above.  SHF_GNU_MBIND is
in the OS-specific range and conflicts with

#define SHF_SUNW_REALLOC        0x01000000      /* internal: krtld realloc */

While the comment suggests this might be relocatable without too much
problems, the description of mbind (no formal spec AFAICS, just the
comment in the binutils patch submission) strongly suggests that this
isn't relevant to Solaris at all.

Indirectly, clearing supports_gnu_osabi on Solaris disables
supports_gnu_unique.  Again, Solaris <sys/elf.h> has

/*
 * GNU/Linux specific binding not used by Solaris
 */
#define STB_GNU_UNIQUE  10

so this seems the right thing to do.

Afterwards, one can remove the explicit mentions of *-*-solaris2* in
quite a number of (but not all) the ld-ifunc dump file notarget lists.

There's one fallout, though: two gas tests now XPASS because they are
xfail'ed for !supports_gnu_osabi:

XPASS: mbind sections 12
XPASS: mbind section contents 16
XPASS: mbind sections 16
XPASS: mbind section contents 16

To fix that, I've changed

#xfail: ![supports_gnu_osabi]

to notarget.

Tested on x86_64-pc-solaris2.11, i386-pc-solaris2.11,
x86_64-pc-linux-gnu, and i686-pc-linux-gnu.

	ld:
	* testsuite/ld-ifunc/ifunc-10-i386.d: Remove *-*-solaris2* from
	notarget.
	* ifunc-11-i386.d: Likewise.
	* ifunc-12-i386.d: Likewise.
	* ifunc-13-i386.d: Likewise.
	* ifunc-14a-i386.d: Likewise.
	* ifunc-14b-i386.d: Likewise.
	* ifunc-14c-i386.d: Likewise.
	* ifunc-14d-i386.d: Likewise.
	* ifunc-14e-i386.d: Likewise.
	* ifunc-14f-i386.d: Likewise.
	* ifunc-15-i386.d: Likewise.
	* ifunc-16-i386-now.d: Likewise.
	* ifunc-16-i386.d: Likewise.
	* ifunc-17a-i386.d: Likewise.
	* ifunc-17b-i386.d: Likewise.
	* ifunc-18a-i386.d: Likewise.
	* ifunc-18b-i386.d: Likewise.
	* ifunc-19a-i386.d: Likewise.
	* ifunc-19b-i386.d: Likewise.
	* ifunc-2-i386-now.d: Likewise.
	* ifunc-2-i386.d: Likewise.
	* ifunc-2-local-i386-now.d: Likewise.
	* ifunc-2-local-i386.d: Likewise.
	* ifunc-20-i386.d: Likewise.
	* ifunc-21-i386.d: Likewise.
	* ifunc-22-i386.d: Likewise.
	* ifunc-5a-i386.d: Likewise.
	* ifunc-5a-local-i386.d: Likewise.
	* ifunc-5b-i386.d: Likewise.
	* ifunc-5b-local-i386.d: Likewise.
	* ifunc-5r-local-i386.d: Likewise.
	* ifunc-6a-i386.d: Likewise.
	* ifunc-6b-i386.d: Likewise.
	* ifunc-7a-i386.d: Likewise.
	* ifunc-7b-i386.d: Likewise.
	* ifunc-8-i386.d: Likewise.
	* ifunc-9-i386.d: Likewise.
	* pr17154-i386-now.d: Likewise.
	* pr17154-i386.d: Likewise.

	* ifunc-23a-x86.d: Remove notarget.
	* ifunc-24a-x86.d: Likewise.
	* ifunc-25a-x86.d: Likewise.

	gas:
	* testsuite/gas/elf/section12a.d: Use notarget instead of xfail.
	* testsuite/gas/elf/section12b.d: Likewise.
	* testsuite/gas/elf/section16a.d: Likewise.
	* testsuite/gas/elf/section16b.d: Likewise.

	binutils:
	* testsuite/lib/binutils-common.exp (supports_gnu_osabi): Don't
	enable on *-*-solaris*.
2020-04-02 10:52:57 +02:00
H.J. Lu
efc3a95039 x86: Force relocation against local absolute symbol
Define TC_FORCE_RELOCATION_ABS to force relocation against local
absolute symbol.

	PR gas/25756
	* config/tc-i386.h (TC_FORCE_RELOCATION_ABS): New.
	* testsuite/gas/i386/localpic.s: Add a test for relocation
	against local absolute symbol.
	* testsuite/gas/i386/x86-64-localpic.s: Likewise.
	* testsuite/gas/i386/localpic.d: Updated.
	* testsuite/gas/i386/x86-64-localpic.d: Likewise.
	* testsuite/gas/i386/ilp32/x86-64-localpic.d: Likewise.
2020-04-01 05:41:06 -07:00